X86ISelLowering.cpp revision 9142ed58eb9e613ca72e5ac67b827a5e421a5e93
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl) { 69 EVT VT = Vec.getValueType(); 70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 71 EVT ElVT = VT.getVectorElementType(); 72 int Factor = VT.getSizeInBits()/128; 73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 74 VT.getVectorNumElements()/Factor); 75 76 // Extract from UNDEF is UNDEF. 77 if (Vec.getOpcode() == ISD::UNDEF) 78 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 79 80 if (isa<ConstantSDNode>(Idx)) { 81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 82 83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 84 // we can match to VEXTRACTF128. 85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 86 87 // This is the index of the first element of the 128-bit chunk 88 // we want. 89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 90 * ElemsPerChunk); 91 92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 94 VecIdx); 95 96 return Result; 97 } 98 99 return SDValue(); 100} 101 102/// Generate a DAG to put 128-bits into a vector > 128 bits. This 103/// sets things up to match to an AVX VINSERTF128 instruction or a 104/// simple superregister reference. Idx is an index in the 128 bits 105/// we want. It need not be aligned to a 128-bit bounday. That makes 106/// lowering INSERT_VECTOR_ELT operations easier. 107static SDValue Insert128BitVector(SDValue Result, 108 SDValue Vec, 109 SDValue Idx, 110 SelectionDAG &DAG, 111 DebugLoc dl) { 112 if (isa<ConstantSDNode>(Idx)) { 113 EVT VT = Vec.getValueType(); 114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 115 116 EVT ElVT = VT.getVectorElementType(); 117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 118 EVT ResultVT = Result.getValueType(); 119 120 // Insert the relevant 128 bits. 121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 122 123 // This is the index of the first element of the 128-bit chunk 124 // we want. 125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 126 * ElemsPerChunk); 127 128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 130 VecIdx); 131 return Result; 132 } 133 134 return SDValue(); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X8664_MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetELF()) 148 return new TargetLoweringObjectFileELF(); 149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 150 return new TargetLoweringObjectFileCOFF(); 151 llvm_unreachable("unknown subtarget type"); 152} 153 154X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 155 : TargetLowering(TM, createTLOF(TM)) { 156 Subtarget = &TM.getSubtarget<X86Subtarget>(); 157 X86ScalarSSEf64 = Subtarget->hasSSE2(); 158 X86ScalarSSEf32 = Subtarget->hasSSE1(); 159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 160 161 RegInfo = TM.getRegisterInfo(); 162 TD = getTargetData(); 163 164 // Set up the TargetLowering object. 165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 166 167 // X86 is weird, it always uses i8 for shift amounts and setcc results. 168 setBooleanContents(ZeroOrOneBooleanContent); 169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 171 172 // For 64-bit since we have so many registers use the ILP scheduler, for 173 // 32-bit code use the register pressure specific scheduling. 174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 175 if (Subtarget->is64Bit()) 176 setSchedulingPreference(Sched::ILP); 177 else if (Subtarget->isAtom()) 178 setSchedulingPreference(Sched::Hybrid); 179 else 180 setSchedulingPreference(Sched::RegPressure); 181 setStackPointerRegisterToSaveRestore(X86StackPtr); 182 183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 184 // Setup Windows compiler runtime calls. 185 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 187 setLibcallName(RTLIB::SREM_I64, "_allrem"); 188 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 189 setLibcallName(RTLIB::MUL_I64, "_allmul"); 190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 195 196 // The _ftol2 runtime function has an unusual calling conv, which 197 // is modeled by a special pseudo-instruction. 198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 202 } 203 204 if (Subtarget->isTargetDarwin()) { 205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 206 setUseUnderscoreSetJmp(false); 207 setUseUnderscoreLongJmp(false); 208 } else if (Subtarget->isTargetMingw()) { 209 // MS runtime is weird: it exports _setjmp, but longjmp! 210 setUseUnderscoreSetJmp(true); 211 setUseUnderscoreLongJmp(false); 212 } else { 213 setUseUnderscoreSetJmp(true); 214 setUseUnderscoreLongJmp(true); 215 } 216 217 // Set up the register classes. 218 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 219 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 220 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 221 if (Subtarget->is64Bit()) 222 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 223 224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 225 226 // We don't accept any truncstore of integer registers. 227 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 228 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 230 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 232 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 233 234 // SETOEQ and SETUNE require checking two conditions. 235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 241 242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 243 // operation. 244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 247 248 if (Subtarget->is64Bit()) { 249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 } else if (!TM.Options.UseSoftFloat) { 252 // We have an algorithm for SSE2->double, and we turn this into a 253 // 64-bit FILD followed by conditional FADD for other targets. 254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 255 // We have an algorithm for SSE2, and we turn this into a 64-bit 256 // FILD for other targets. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 258 } 259 260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 261 // this operation. 262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 264 265 if (!TM.Options.UseSoftFloat) { 266 // SSE has no i16 to fp conversion, only i32 267 if (X86ScalarSSEf32) { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 269 // f32 and f64 cases are Legal, f80 case is not 270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 274 } 275 } else { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 278 } 279 280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 281 // are Legal, f80 is custom lowered. 282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 284 285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 286 // this operation. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 289 290 if (X86ScalarSSEf32) { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 292 // f32 and f64 cases are Legal, f80 case is not 293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 294 } else { 295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 297 } 298 299 // Handle FP_TO_UINT by promoting the destination to a larger signed 300 // conversion. 301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 304 305 if (Subtarget->is64Bit()) { 306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 308 } else if (!TM.Options.UseSoftFloat) { 309 // Since AVX is a superset of SSE3, only check for SSE here. 310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 311 // Expand FP_TO_UINT into a select. 312 // FIXME: We would like to use a Custom expander here eventually to do 313 // the optimal thing for SSE vs. the default expansion in the legalizer. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 315 else 316 // With SSE3 we can use fisttpll to convert to a signed i64; without 317 // SSE, we're stuck with a fistpll. 318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 319 } 320 321 if (isTargetFTOL()) { 322 // Use the _ftol2 runtime function, which has a pseudo-instruction 323 // to handle its weird calling convention. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 325 } 326 327 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 328 if (!X86ScalarSSEf64) { 329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 333 // Without SSE, i64->f64 goes through memory. 334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 335 } 336 } 337 338 // Scalar integer divide and remainder are lowered to use operations that 339 // produce two results, to match the available instructions. This exposes 340 // the two-result form to trivial CSE, which is able to combine x/y and x%y 341 // into a single instruction. 342 // 343 // Scalar integer multiply-high is also lowered to use two-result 344 // operations, to match the available instructions. However, plain multiply 345 // (low) operations are left as Legal, as there are single-result 346 // instructions for this in x86. Using the two-result multiply instructions 347 // when both high and low results are needed must be arranged by dagcombine. 348 for (unsigned i = 0, e = 4; i != e; ++i) { 349 MVT VT = IntVTs[i]; 350 setOperationAction(ISD::MULHS, VT, Expand); 351 setOperationAction(ISD::MULHU, VT, Expand); 352 setOperationAction(ISD::SDIV, VT, Expand); 353 setOperationAction(ISD::UDIV, VT, Expand); 354 setOperationAction(ISD::SREM, VT, Expand); 355 setOperationAction(ISD::UREM, VT, Expand); 356 357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 358 setOperationAction(ISD::ADDC, VT, Custom); 359 setOperationAction(ISD::ADDE, VT, Custom); 360 setOperationAction(ISD::SUBC, VT, Custom); 361 setOperationAction(ISD::SUBE, VT, Custom); 362 } 363 364 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 365 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 366 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 368 if (Subtarget->is64Bit()) 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f64 , Expand); 376 setOperationAction(ISD::FREM , MVT::f80 , Expand); 377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 378 379 // Promote the i8 variants and force them on up to i32 which has a shorter 380 // encoding. 381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 385 if (Subtarget->hasBMI()) { 386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 388 if (Subtarget->is64Bit()) 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 390 } else { 391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 393 if (Subtarget->is64Bit()) 394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 395 } 396 397 if (Subtarget->hasLZCNT()) { 398 // When promoting the i8 variants, force them to i32 for a shorter 399 // encoding. 400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 406 if (Subtarget->is64Bit()) 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 408 } else { 409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 418 } 419 } 420 421 if (Subtarget->hasPOPCNT()) { 422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 423 } else { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 427 if (Subtarget->is64Bit()) 428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 429 } 430 431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 433 434 // These should be promoted to a larger select which is supported. 435 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 436 // X86 wants to expand cmov itself. 437 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 438 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 439 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 440 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 443 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 446 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 449 if (Subtarget->is64Bit()) { 450 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 452 } 453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 454 455 // Darwin ABI issue. 456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 464 if (Subtarget->is64Bit()) { 465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 470 } 471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 475 if (Subtarget->is64Bit()) { 476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 479 } 480 481 if (Subtarget->hasSSE1()) 482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 483 484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 486 487 // On X86 and X86-64, atomic operations are lowered to locked instructions. 488 // Locked instructions, in turn, have implicit fence semantics (all memory 489 // operations are flushed before issuing the locked instruction, and they 490 // are not buffered), so we can fold away the common pattern of 491 // fence-atomic-fence. 492 setShouldFoldAtomicFences(true); 493 494 // Expand certain atomics 495 for (unsigned i = 0, e = 4; i != e; ++i) { 496 MVT VT = IntVTs[i]; 497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 500 } 501 502 if (!Subtarget->is64Bit()) { 503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 511 } 512 513 if (Subtarget->hasCmpxchg16b()) { 514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 515 } 516 517 // FIXME - use subtarget debug flags 518 if (!Subtarget->isTargetDarwin() && 519 !Subtarget->isTargetELF() && 520 !Subtarget->isTargetCygMing()) { 521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 522 } 523 524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 528 if (Subtarget->is64Bit()) { 529 setExceptionPointerRegister(X86::RAX); 530 setExceptionSelectorRegister(X86::RDX); 531 } else { 532 setExceptionPointerRegister(X86::EAX); 533 setExceptionSelectorRegister(X86::EDX); 534 } 535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 537 538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 540 541 setOperationAction(ISD::TRAP, MVT::Other, Legal); 542 543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 544 setOperationAction(ISD::VASTART , MVT::Other, Custom); 545 setOperationAction(ISD::VAEND , MVT::Other, Expand); 546 if (Subtarget->is64Bit()) { 547 setOperationAction(ISD::VAARG , MVT::Other, Custom); 548 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 549 } else { 550 setOperationAction(ISD::VAARG , MVT::Other, Expand); 551 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 552 } 553 554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 556 557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 559 MVT::i64 : MVT::i32, Custom); 560 else if (TM.Options.EnableSegmentedStacks) 561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 562 MVT::i64 : MVT::i32, Custom); 563 else 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Expand); 566 567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 568 // f32 and f64 use SSE. 569 // Set up the FP register classes. 570 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 571 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 572 573 // Use ANDPD to simulate FABS. 574 setOperationAction(ISD::FABS , MVT::f64, Custom); 575 setOperationAction(ISD::FABS , MVT::f32, Custom); 576 577 // Use XORP to simulate FNEG. 578 setOperationAction(ISD::FNEG , MVT::f64, Custom); 579 setOperationAction(ISD::FNEG , MVT::f32, Custom); 580 581 // Use ANDPD and ORPD to simulate FCOPYSIGN. 582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 584 585 // Lower this to FGETSIGNx86 plus an AND. 586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 588 589 // We don't support sin/cos/fmod 590 setOperationAction(ISD::FSIN , MVT::f64, Expand); 591 setOperationAction(ISD::FCOS , MVT::f64, Expand); 592 setOperationAction(ISD::FSIN , MVT::f32, Expand); 593 setOperationAction(ISD::FCOS , MVT::f32, Expand); 594 595 // Expand FP immediates into loads from the stack, except for the special 596 // cases we handle. 597 addLegalFPImmediate(APFloat(+0.0)); // xorpd 598 addLegalFPImmediate(APFloat(+0.0f)); // xorps 599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 600 // Use SSE for f32, x87 for f64. 601 // Set up the FP register classes. 602 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 604 605 // Use ANDPS to simulate FABS. 606 setOperationAction(ISD::FABS , MVT::f32, Custom); 607 608 // Use XORP to simulate FNEG. 609 setOperationAction(ISD::FNEG , MVT::f32, Custom); 610 611 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 612 613 // Use ANDPS and ORPS to simulate FCOPYSIGN. 614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 616 617 // We don't support sin/cos/fmod 618 setOperationAction(ISD::FSIN , MVT::f32, Expand); 619 setOperationAction(ISD::FCOS , MVT::f32, Expand); 620 621 // Special cases we handle for FP constants. 622 addLegalFPImmediate(APFloat(+0.0f)); // xorps 623 addLegalFPImmediate(APFloat(+0.0)); // FLD0 624 addLegalFPImmediate(APFloat(+1.0)); // FLD1 625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 627 628 if (!TM.Options.UnsafeFPMath) { 629 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 630 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 631 } 632 } else if (!TM.Options.UseSoftFloat) { 633 // f32 and f64 in x87. 634 // Set up the FP register classes. 635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 637 638 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 639 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 642 643 if (!TM.Options.UnsafeFPMath) { 644 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 645 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 646 } 647 addLegalFPImmediate(APFloat(+0.0)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 655 } 656 657 // We don't support FMA. 658 setOperationAction(ISD::FMA, MVT::f64, Expand); 659 setOperationAction(ISD::FMA, MVT::f32, Expand); 660 661 // Long double always uses X87. 662 if (!TM.Options.UseSoftFloat) { 663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 664 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 666 { 667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 668 addLegalFPImmediate(TmpFlt); // FLD0 669 TmpFlt.changeSign(); 670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 671 672 bool ignored; 673 APFloat TmpFlt2(+1.0); 674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 675 &ignored); 676 addLegalFPImmediate(TmpFlt2); // FLD1 677 TmpFlt2.changeSign(); 678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 679 } 680 681 if (!TM.Options.UnsafeFPMath) { 682 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 683 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 684 } 685 686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 687 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 689 setOperationAction(ISD::FRINT, MVT::f80, Expand); 690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 691 setOperationAction(ISD::FMA, MVT::f80, Expand); 692 } 693 694 // Always use a library call for pow. 695 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 696 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 697 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 698 699 setOperationAction(ISD::FLOG, MVT::f80, Expand); 700 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 701 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 702 setOperationAction(ISD::FEXP, MVT::f80, Expand); 703 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 704 705 // First set operation action for all vector types to either promote 706 // (for widening) or expand (for scalarization). Then we will selectively 707 // turn on ones that can be effectively codegen'd. 708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 769 setTruncStoreAction((MVT::SimpleValueType)VT, 770 (MVT::SimpleValueType)InnerVT, Expand); 771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 } 775 776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 777 // with -msoft-float, disable use of MMX as well. 778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 780 // No operations on x86mmx supported, everything uses intrinsics. 781 } 782 783 // MMX-sized vectors (other than x86mmx) are expected to be expanded 784 // into smaller operations. 785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 789 setOperationAction(ISD::AND, MVT::v8i8, Expand); 790 setOperationAction(ISD::AND, MVT::v4i16, Expand); 791 setOperationAction(ISD::AND, MVT::v2i32, Expand); 792 setOperationAction(ISD::AND, MVT::v1i64, Expand); 793 setOperationAction(ISD::OR, MVT::v8i8, Expand); 794 setOperationAction(ISD::OR, MVT::v4i16, Expand); 795 setOperationAction(ISD::OR, MVT::v2i32, Expand); 796 setOperationAction(ISD::OR, MVT::v1i64, Expand); 797 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 814 815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 817 818 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 830 } 831 832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 834 835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 836 // registers cannot be used even for integer operations. 837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 841 842 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 843 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 844 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 845 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 846 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 847 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 848 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 849 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 850 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 851 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 852 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 858 859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 863 864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 869 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 875 876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 878 EVT VT = (MVT::SimpleValueType)i; 879 // Do not attempt to custom lower non-power-of-2 vectors 880 if (!isPowerOf2_32(VT.getVectorNumElements())) 881 continue; 882 // Do not attempt to custom lower non-128-bit vectors 883 if (!VT.is128BitVector()) 884 continue; 885 setOperationAction(ISD::BUILD_VECTOR, 886 VT.getSimpleVT().SimpleTy, Custom); 887 setOperationAction(ISD::VECTOR_SHUFFLE, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 890 VT.getSimpleVT().SimpleTy, Custom); 891 } 892 893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 899 900 if (Subtarget->is64Bit()) { 901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 903 } 904 905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 908 EVT VT = SVT; 909 910 // Do not attempt to promote non-128-bit vectors 911 if (!VT.is128BitVector()) 912 continue; 913 914 setOperationAction(ISD::AND, SVT, Promote); 915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 916 setOperationAction(ISD::OR, SVT, Promote); 917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 918 setOperationAction(ISD::XOR, SVT, Promote); 919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 920 setOperationAction(ISD::LOAD, SVT, Promote); 921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 922 setOperationAction(ISD::SELECT, SVT, Promote); 923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 924 } 925 926 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 927 928 // Custom lower v2i64 and v2f64 selects. 929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 933 934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 936 } 937 938 if (Subtarget->hasSSE41()) { 939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 940 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 942 setOperationAction(ISD::FRINT, MVT::f32, Legal); 943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 945 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 947 setOperationAction(ISD::FRINT, MVT::f64, Legal); 948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 949 950 // FIXME: Do we need to handle scalar-to-vector here? 951 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 952 953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 958 959 // i8 and i16 vectors are custom , because the source register and source 960 // source memory operand types are not the same width. f32 vectors are 961 // custom since the immediate controlling the insert encodes additional 962 // information. 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 967 968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 972 973 // FIXME: these should be Legal but thats only for the case where 974 // the index is constant. For now custom expand to deal with that. 975 if (Subtarget->is64Bit()) { 976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 978 } 979 } 980 981 if (Subtarget->hasSSE2()) { 982 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 983 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 984 985 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 987 988 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 990 991 if (Subtarget->hasAVX2()) { 992 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 993 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 994 995 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 996 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 997 998 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 999 } else { 1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1002 1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1005 1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1007 } 1008 } 1009 1010 if (Subtarget->hasSSE42()) 1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1012 1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1020 1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1024 1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1031 1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1038 1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1042 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1049 1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1052 1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1055 1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1058 1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1063 1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1067 1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1072 1073 if (Subtarget->hasAVX2()) { 1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1078 1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1083 1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1087 // Don't lower v32i8 because there is no 128-bit byte mul 1088 1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1090 1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1093 1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1096 1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1098 } else { 1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1103 1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1108 1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1112 // Don't lower v32i8 because there is no 128-bit byte mul 1113 1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1116 1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1119 1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1121 } 1122 1123 // Custom lower several nodes for 256-bit types. 1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1127 EVT VT = SVT; 1128 1129 // Extract subvector is special because the value type 1130 // (result) is 128-bit but the source is 256-bit wide. 1131 if (VT.is128BitVector()) 1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1133 1134 // Do not attempt to custom lower other non-256-bit vectors 1135 if (!VT.is256BitVector()) 1136 continue; 1137 1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1144 } 1145 1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1149 EVT VT = SVT; 1150 1151 // Do not attempt to promote non-256-bit vectors 1152 if (!VT.is256BitVector()) 1153 continue; 1154 1155 setOperationAction(ISD::AND, SVT, Promote); 1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1157 setOperationAction(ISD::OR, SVT, Promote); 1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1159 setOperationAction(ISD::XOR, SVT, Promote); 1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::LOAD, SVT, Promote); 1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1163 setOperationAction(ISD::SELECT, SVT, Promote); 1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1165 } 1166 } 1167 1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1169 // of this type with custom code. 1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1173 Custom); 1174 } 1175 1176 // We want to custom lower some of our intrinsics. 1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1178 1179 1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1181 // handle type legalization for these operations here. 1182 // 1183 // FIXME: We really should do custom legalization for addition and 1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1185 // than generic legalization for 64-bit multiplication-with-overflow, though. 1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1187 // Add/Sub/Mul with overflow operations are custom lowered. 1188 MVT VT = IntVTs[i]; 1189 setOperationAction(ISD::SADDO, VT, Custom); 1190 setOperationAction(ISD::UADDO, VT, Custom); 1191 setOperationAction(ISD::SSUBO, VT, Custom); 1192 setOperationAction(ISD::USUBO, VT, Custom); 1193 setOperationAction(ISD::SMULO, VT, Custom); 1194 setOperationAction(ISD::UMULO, VT, Custom); 1195 } 1196 1197 // There are no 8-bit 3-address imul/mul instructions 1198 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1199 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1200 1201 if (!Subtarget->is64Bit()) { 1202 // These libcalls are not available in 32-bit. 1203 setLibcallName(RTLIB::SHL_I128, 0); 1204 setLibcallName(RTLIB::SRL_I128, 0); 1205 setLibcallName(RTLIB::SRA_I128, 0); 1206 } 1207 1208 // We have target-specific dag combine patterns for the following nodes: 1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1211 setTargetDAGCombine(ISD::VSELECT); 1212 setTargetDAGCombine(ISD::SELECT); 1213 setTargetDAGCombine(ISD::SHL); 1214 setTargetDAGCombine(ISD::SRA); 1215 setTargetDAGCombine(ISD::SRL); 1216 setTargetDAGCombine(ISD::OR); 1217 setTargetDAGCombine(ISD::AND); 1218 setTargetDAGCombine(ISD::ADD); 1219 setTargetDAGCombine(ISD::FADD); 1220 setTargetDAGCombine(ISD::FSUB); 1221 setTargetDAGCombine(ISD::SUB); 1222 setTargetDAGCombine(ISD::LOAD); 1223 setTargetDAGCombine(ISD::STORE); 1224 setTargetDAGCombine(ISD::ZERO_EXTEND); 1225 setTargetDAGCombine(ISD::SIGN_EXTEND); 1226 setTargetDAGCombine(ISD::TRUNCATE); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->getStackAlignment() >= 32) { 1331 if (Subtarget->hasAVX2()) 1332 return MVT::v8i32; 1333 if (Subtarget->hasAVX()) 1334 return MVT::v8f32; 1335 } 1336 if (Subtarget->hasSSE2()) 1337 return MVT::v4i32; 1338 if (Subtarget->hasSSE1()) 1339 return MVT::v4f32; 1340 } else if (!MemcpyStrSrc && Size >= 8 && 1341 !Subtarget->is64Bit() && 1342 Subtarget->getStackAlignment() >= 8 && 1343 Subtarget->hasSSE2()) { 1344 // Do not use f64 to lower memcpy if source is string constant. It's 1345 // better to use i32 to avoid the loads. 1346 return MVT::f64; 1347 } 1348 } 1349 if (Subtarget->is64Bit() && Size >= 8) 1350 return MVT::i64; 1351 return MVT::i32; 1352} 1353 1354/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1355/// current function. The returned value is a member of the 1356/// MachineJumpTableInfo::JTEntryKind enum. 1357unsigned X86TargetLowering::getJumpTableEncoding() const { 1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1359 // symbol. 1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1361 Subtarget->isPICStyleGOT()) 1362 return MachineJumpTableInfo::EK_Custom32; 1363 1364 // Otherwise, use the normal jump table encoding heuristics. 1365 return TargetLowering::getJumpTableEncoding(); 1366} 1367 1368const MCExpr * 1369X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1370 const MachineBasicBlock *MBB, 1371 unsigned uid,MCContext &Ctx) const{ 1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1373 Subtarget->isPICStyleGOT()); 1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1375 // entries. 1376 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1377 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1378} 1379 1380/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1381/// jumptable. 1382SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1383 SelectionDAG &DAG) const { 1384 if (!Subtarget->is64Bit()) 1385 // This doesn't have DebugLoc associated with it, but is not really the 1386 // same as a Register. 1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1388 return Table; 1389} 1390 1391/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1392/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1393/// MCExpr. 1394const MCExpr *X86TargetLowering:: 1395getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1396 MCContext &Ctx) const { 1397 // X86-64 uses RIP relative addressing based on the jump table label. 1398 if (Subtarget->isPICStyleRIPRel()) 1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1400 1401 // Otherwise, the reference is relative to the PIC base. 1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1403} 1404 1405// FIXME: Why this routine is here? Move to RegInfo! 1406std::pair<const TargetRegisterClass*, uint8_t> 1407X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1408 const TargetRegisterClass *RRC = 0; 1409 uint8_t Cost = 1; 1410 switch (VT.getSimpleVT().SimpleTy) { 1411 default: 1412 return TargetLowering::findRepresentativeClass(VT); 1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1414 RRC = (Subtarget->is64Bit() 1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1416 break; 1417 case MVT::x86mmx: 1418 RRC = X86::VR64RegisterClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = X86::VR128RegisterClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDValue TCChain = Chain; 1588 SDNode *Copy = *N->use_begin(); 1589 if (Copy->getOpcode() == ISD::CopyToReg) { 1590 // If the copy has a glue operand, we conservatively assume it isn't safe to 1591 // perform a tail call. 1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1593 return false; 1594 TCChain = Copy->getOperand(0); 1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1596 return false; 1597 1598 bool HasRet = false; 1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1600 UI != UE; ++UI) { 1601 if (UI->getOpcode() != X86ISD::RET_FLAG) 1602 return false; 1603 HasRet = true; 1604 } 1605 1606 if (!HasRet) 1607 return false; 1608 1609 Chain = TCChain; 1610 return true; 1611} 1612 1613EVT 1614X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1615 ISD::NodeType ExtendKind) const { 1616 MVT ReturnMVT; 1617 // TODO: Is this also valid on 32-bit? 1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1619 ReturnMVT = MVT::i8; 1620 else 1621 ReturnMVT = MVT::i32; 1622 1623 EVT MinVT = getRegisterType(Context, ReturnMVT); 1624 return VT.bitsLT(MinVT) ? MinVT : VT; 1625} 1626 1627/// LowerCallResult - Lower the result values of a call into the 1628/// appropriate copies out of appropriate physical registers. 1629/// 1630SDValue 1631X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1632 CallingConv::ID CallConv, bool isVarArg, 1633 const SmallVectorImpl<ISD::InputArg> &Ins, 1634 DebugLoc dl, SelectionDAG &DAG, 1635 SmallVectorImpl<SDValue> &InVals) const { 1636 1637 // Assign locations to each value returned by this call. 1638 SmallVector<CCValAssign, 16> RVLocs; 1639 bool Is64Bit = Subtarget->is64Bit(); 1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1641 getTargetMachine(), RVLocs, *DAG.getContext()); 1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1643 1644 // Copy all of the result registers out of their specified physreg. 1645 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1646 CCValAssign &VA = RVLocs[i]; 1647 EVT CopyVT = VA.getValVT(); 1648 1649 // If this is x86-64, and we disabled SSE, we can't return FP values 1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1652 report_fatal_error("SSE register return with SSE disabled"); 1653 } 1654 1655 SDValue Val; 1656 1657 // If this is a call to a function that returns an fp value on the floating 1658 // point stack, we must guarantee the the value is popped from the stack, so 1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1660 // if the return value is not used. We use the FpPOP_RETVAL instruction 1661 // instead. 1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1663 // If we prefer to use the value in xmm registers, copy it out as f80 and 1664 // use a truncate to move it from fp stack reg to xmm reg. 1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1666 SDValue Ops[] = { Chain, InFlag }; 1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1668 MVT::Other, MVT::Glue, Ops, 2), 1); 1669 Val = Chain.getValue(0); 1670 1671 // Round the f80 to the right size, which also moves it to the appropriate 1672 // xmm register. 1673 if (CopyVT != VA.getValVT()) 1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1675 // This truncation won't change the value. 1676 DAG.getIntPtrConstant(1)); 1677 } else { 1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1679 CopyVT, InFlag).getValue(1); 1680 Val = Chain.getValue(0); 1681 } 1682 InFlag = Chain.getValue(2); 1683 InVals.push_back(Val); 1684 } 1685 1686 return Chain; 1687} 1688 1689 1690//===----------------------------------------------------------------------===// 1691// C & StdCall & Fast Calling Convention implementation 1692//===----------------------------------------------------------------------===// 1693// StdCall calling convention seems to be standard for many Windows' API 1694// routines and around. It differs from C calling convention just a little: 1695// callee should clean up the stack, not caller. Symbols should be also 1696// decorated in some fancy way :) It doesn't support any vector arguments. 1697// For info on fast calling convention see Fast Calling Convention (tail call) 1698// implementation LowerX86_32FastCCCallTo. 1699 1700/// CallIsStructReturn - Determines whether a call uses struct return 1701/// semantics. 1702static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1703 if (Outs.empty()) 1704 return false; 1705 1706 return Outs[0].Flags.isSRet(); 1707} 1708 1709/// ArgsAreStructReturn - Determines whether a function uses struct 1710/// return semantics. 1711static bool 1712ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1713 if (Ins.empty()) 1714 return false; 1715 1716 return Ins[0].Flags.isSRet(); 1717} 1718 1719/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1720/// by "Src" to address "Dst" with size and alignment information specified by 1721/// the specific parameter attribute. The copy will be passed as a byval 1722/// function parameter. 1723static SDValue 1724CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1726 DebugLoc dl) { 1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1728 1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1730 /*isVolatile*/false, /*AlwaysInline=*/true, 1731 MachinePointerInfo(), MachinePointerInfo()); 1732} 1733 1734/// IsTailCallConvention - Return true if the calling convention is one that 1735/// supports tail call optimization. 1736static bool IsTailCallConvention(CallingConv::ID CC) { 1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1738} 1739 1740bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1742 return false; 1743 1744 CallSite CS(CI); 1745 CallingConv::ID CalleeCC = CS.getCallingConv(); 1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1747 return false; 1748 1749 return true; 1750} 1751 1752/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1753/// a tailcall target by changing its ABI. 1754static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1755 bool GuaranteedTailCallOpt) { 1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1757} 1758 1759SDValue 1760X86TargetLowering::LowerMemArgument(SDValue Chain, 1761 CallingConv::ID CallConv, 1762 const SmallVectorImpl<ISD::InputArg> &Ins, 1763 DebugLoc dl, SelectionDAG &DAG, 1764 const CCValAssign &VA, 1765 MachineFrameInfo *MFI, 1766 unsigned i) const { 1767 // Create the nodes corresponding to a load from this parameter slot. 1768 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1770 getTargetMachine().Options.GuaranteedTailCallOpt); 1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1772 EVT ValVT; 1773 1774 // If value is passed by pointer we have address passed instead of the value 1775 // itself. 1776 if (VA.getLocInfo() == CCValAssign::Indirect) 1777 ValVT = VA.getLocVT(); 1778 else 1779 ValVT = VA.getValVT(); 1780 1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1782 // changed with more analysis. 1783 // In case of tail call optimization mark all arguments mutable. Since they 1784 // could be overwritten by lowering of arguments in case of a tail call. 1785 if (Flags.isByVal()) { 1786 unsigned Bytes = Flags.getByValSize(); 1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1789 return DAG.getFrameIndex(FI, getPointerTy()); 1790 } else { 1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1792 VA.getLocMemOffset(), isImmutable); 1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1794 return DAG.getLoad(ValVT, dl, Chain, FIN, 1795 MachinePointerInfo::getFixedStack(FI), 1796 false, false, false, 0); 1797 } 1798} 1799 1800SDValue 1801X86TargetLowering::LowerFormalArguments(SDValue Chain, 1802 CallingConv::ID CallConv, 1803 bool isVarArg, 1804 const SmallVectorImpl<ISD::InputArg> &Ins, 1805 DebugLoc dl, 1806 SelectionDAG &DAG, 1807 SmallVectorImpl<SDValue> &InVals) 1808 const { 1809 MachineFunction &MF = DAG.getMachineFunction(); 1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1811 1812 const Function* Fn = MF.getFunction(); 1813 if (Fn->hasExternalLinkage() && 1814 Subtarget->isTargetCygMing() && 1815 Fn->getName() == "main") 1816 FuncInfo->setForceFramePointer(true); 1817 1818 MachineFrameInfo *MFI = MF.getFrameInfo(); 1819 bool Is64Bit = Subtarget->is64Bit(); 1820 bool IsWindows = Subtarget->isTargetWindows(); 1821 bool IsWin64 = Subtarget->isTargetWin64(); 1822 1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1824 "Var args not supported with calling convention fastcc or ghc"); 1825 1826 // Assign locations to all of the incoming arguments. 1827 SmallVector<CCValAssign, 16> ArgLocs; 1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1829 ArgLocs, *DAG.getContext()); 1830 1831 // Allocate shadow area for Win64 1832 if (IsWin64) { 1833 CCInfo.AllocateStack(32, 8); 1834 } 1835 1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1837 1838 unsigned LastVal = ~0U; 1839 SDValue ArgValue; 1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1841 CCValAssign &VA = ArgLocs[i]; 1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1843 // places. 1844 assert(VA.getValNo() != LastVal && 1845 "Don't support value assigned to multiple locs yet"); 1846 (void)LastVal; 1847 LastVal = VA.getValNo(); 1848 1849 if (VA.isRegLoc()) { 1850 EVT RegVT = VA.getLocVT(); 1851 const TargetRegisterClass *RC; 1852 if (RegVT == MVT::i32) 1853 RC = X86::GR32RegisterClass; 1854 else if (Is64Bit && RegVT == MVT::i64) 1855 RC = X86::GR64RegisterClass; 1856 else if (RegVT == MVT::f32) 1857 RC = X86::FR32RegisterClass; 1858 else if (RegVT == MVT::f64) 1859 RC = X86::FR64RegisterClass; 1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1861 RC = X86::VR256RegisterClass; 1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1863 RC = X86::VR128RegisterClass; 1864 else if (RegVT == MVT::x86mmx) 1865 RC = X86::VR64RegisterClass; 1866 else 1867 llvm_unreachable("Unknown argument type!"); 1868 1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1871 1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1874 // right size. 1875 if (VA.getLocInfo() == CCValAssign::SExt) 1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1877 DAG.getValueType(VA.getValVT())); 1878 else if (VA.getLocInfo() == CCValAssign::ZExt) 1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1880 DAG.getValueType(VA.getValVT())); 1881 else if (VA.getLocInfo() == CCValAssign::BCvt) 1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1883 1884 if (VA.isExtInLoc()) { 1885 // Handle MMX values passed in XMM regs. 1886 if (RegVT.isVector()) { 1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1888 ArgValue); 1889 } else 1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1891 } 1892 } else { 1893 assert(VA.isMemLoc()); 1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1895 } 1896 1897 // If value is passed via pointer - do a load. 1898 if (VA.getLocInfo() == CCValAssign::Indirect) 1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1900 MachinePointerInfo(), false, false, false, 0); 1901 1902 InVals.push_back(ArgValue); 1903 } 1904 1905 // The x86-64 ABI for returning structs by value requires that we copy 1906 // the sret argument into %rax for the return. Save the argument into 1907 // a virtual register so that we can access it from the return points. 1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1910 unsigned Reg = FuncInfo->getSRetReturnReg(); 1911 if (!Reg) { 1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1913 FuncInfo->setSRetReturnReg(Reg); 1914 } 1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1917 } 1918 1919 unsigned StackSize = CCInfo.getNextStackOffset(); 1920 // Align stack specially for tail calls. 1921 if (FuncIsMadeTailCallSafe(CallConv, 1922 MF.getTarget().Options.GuaranteedTailCallOpt)) 1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1924 1925 // If the function takes variable number of arguments, make a frame index for 1926 // the start of the first vararg value... for expansion of llvm.va_start. 1927 if (isVarArg) { 1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1929 CallConv != CallingConv::X86_ThisCall)) { 1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1931 } 1932 if (Is64Bit) { 1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1934 1935 // FIXME: We should really autogenerate these arrays 1936 static const uint16_t GPR64ArgRegsWin64[] = { 1937 X86::RCX, X86::RDX, X86::R8, X86::R9 1938 }; 1939 static const uint16_t GPR64ArgRegs64Bit[] = { 1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1941 }; 1942 static const uint16_t XMMArgRegs64Bit[] = { 1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1945 }; 1946 const uint16_t *GPR64ArgRegs; 1947 unsigned NumXMMRegs = 0; 1948 1949 if (IsWin64) { 1950 // The XMM registers which might contain var arg parameters are shadowed 1951 // in their paired GPR. So we only need to save the GPR to their home 1952 // slots. 1953 TotalNumIntRegs = 4; 1954 GPR64ArgRegs = GPR64ArgRegsWin64; 1955 } else { 1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1957 GPR64ArgRegs = GPR64ArgRegs64Bit; 1958 1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1960 TotalNumXMMRegs); 1961 } 1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1963 TotalNumIntRegs); 1964 1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1967 "SSE register cannot be used when SSE is disabled!"); 1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1969 NoImplicitFloatOps) && 1970 "SSE register cannot be used when SSE is disabled!"); 1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1972 !Subtarget->hasSSE1()) 1973 // Kernel mode asks for SSE to be disabled, so don't push them 1974 // on the stack. 1975 TotalNumXMMRegs = 0; 1976 1977 if (IsWin64) { 1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1979 // Get to the caller-allocated home save location. Add 8 to account 1980 // for the return address. 1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1984 // Fixup to set vararg frame on shadow area (4 x i64). 1985 if (NumIntRegs < 4) 1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1987 } else { 1988 // For X86-64, if there are vararg parameters that are passed via 1989 // registers, then we must store them to their spots on the stack so 1990 // they may be loaded by deferencing the result of va_next. 1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1993 FuncInfo->setRegSaveFrameIndex( 1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1995 false)); 1996 } 1997 1998 // Store the integer parameter registers. 1999 SmallVector<SDValue, 8> MemOps; 2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2001 getPointerTy()); 2002 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2005 DAG.getIntPtrConstant(Offset)); 2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2007 X86::GR64RegisterClass); 2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2009 SDValue Store = 2010 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2011 MachinePointerInfo::getFixedStack( 2012 FuncInfo->getRegSaveFrameIndex(), Offset), 2013 false, false, 0); 2014 MemOps.push_back(Store); 2015 Offset += 8; 2016 } 2017 2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2019 // Now store the XMM (fp + vector) parameter registers. 2020 SmallVector<SDValue, 11> SaveXMMOps; 2021 SaveXMMOps.push_back(Chain); 2022 2023 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2025 SaveXMMOps.push_back(ALVal); 2026 2027 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2028 FuncInfo->getRegSaveFrameIndex())); 2029 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2030 FuncInfo->getVarArgsFPOffset())); 2031 2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2034 X86::VR128RegisterClass); 2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2036 SaveXMMOps.push_back(Val); 2037 } 2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2039 MVT::Other, 2040 &SaveXMMOps[0], SaveXMMOps.size())); 2041 } 2042 2043 if (!MemOps.empty()) 2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2045 &MemOps[0], MemOps.size()); 2046 } 2047 } 2048 2049 // Some CCs need callee pop. 2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2051 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2053 } else { 2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2055 // If this is an sret function, the return should pop the hidden pointer. 2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2057 ArgsAreStructReturn(Ins)) 2058 FuncInfo->setBytesToPopOnReturn(4); 2059 } 2060 2061 if (!Is64Bit) { 2062 // RegSaveFrameIndex is X86-64 only. 2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2064 if (CallConv == CallingConv::X86_FastCall || 2065 CallConv == CallingConv::X86_ThisCall) 2066 // fastcc functions can't have varargs. 2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2068 } 2069 2070 FuncInfo->setArgumentStackSize(StackSize); 2071 2072 return Chain; 2073} 2074 2075SDValue 2076X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2077 SDValue StackPtr, SDValue Arg, 2078 DebugLoc dl, SelectionDAG &DAG, 2079 const CCValAssign &VA, 2080 ISD::ArgFlagsTy Flags) const { 2081 unsigned LocMemOffset = VA.getLocMemOffset(); 2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2084 if (Flags.isByVal()) 2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2086 2087 return DAG.getStore(Chain, dl, Arg, PtrOff, 2088 MachinePointerInfo::getStack(LocMemOffset), 2089 false, false, 0); 2090} 2091 2092/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2093/// optimization is performed and it is required. 2094SDValue 2095X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2096 SDValue &OutRetAddr, SDValue Chain, 2097 bool IsTailCall, bool Is64Bit, 2098 int FPDiff, DebugLoc dl) const { 2099 // Adjust the Return address stack slot. 2100 EVT VT = getPointerTy(); 2101 OutRetAddr = getReturnAddressFrameIndex(DAG); 2102 2103 // Load the "old" Return address. 2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2105 false, false, false, 0); 2106 return SDValue(OutRetAddr.getNode(), 1); 2107} 2108 2109/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2110/// optimization is performed and it is required (FPDiff!=0). 2111static SDValue 2112EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2113 SDValue Chain, SDValue RetAddrFrIdx, 2114 bool Is64Bit, int FPDiff, DebugLoc dl) { 2115 // Store the return address to the appropriate stack slot. 2116 if (!FPDiff) return Chain; 2117 // Calculate the new stack slot for the return address. 2118 int SlotSize = Is64Bit ? 8 : 4; 2119 int NewReturnAddrFI = 2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2125 false, false, 0); 2126 return Chain; 2127} 2128 2129SDValue 2130X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2131 CallingConv::ID CallConv, bool isVarArg, 2132 bool doesNotRet, bool &isTailCall, 2133 const SmallVectorImpl<ISD::OutputArg> &Outs, 2134 const SmallVectorImpl<SDValue> &OutVals, 2135 const SmallVectorImpl<ISD::InputArg> &Ins, 2136 DebugLoc dl, SelectionDAG &DAG, 2137 SmallVectorImpl<SDValue> &InVals) const { 2138 MachineFunction &MF = DAG.getMachineFunction(); 2139 bool Is64Bit = Subtarget->is64Bit(); 2140 bool IsWin64 = Subtarget->isTargetWin64(); 2141 bool IsWindows = Subtarget->isTargetWindows(); 2142 bool IsStructRet = CallIsStructReturn(Outs); 2143 bool IsSibcall = false; 2144 2145 if (MF.getTarget().Options.DisableTailCalls) 2146 isTailCall = false; 2147 2148 if (isTailCall) { 2149 // Check if it's really possible to do a tail call. 2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2152 Outs, OutVals, Ins, DAG); 2153 2154 // Sibcalls are automatically detected tailcalls which do not require 2155 // ABI changes. 2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2157 IsSibcall = true; 2158 2159 if (isTailCall) 2160 ++NumTailCalls; 2161 } 2162 2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2164 "Var args not supported with calling convention fastcc or ghc"); 2165 2166 // Analyze operands of the call, assigning locations to each operand. 2167 SmallVector<CCValAssign, 16> ArgLocs; 2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2169 ArgLocs, *DAG.getContext()); 2170 2171 // Allocate shadow area for Win64 2172 if (IsWin64) { 2173 CCInfo.AllocateStack(32, 8); 2174 } 2175 2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2177 2178 // Get a count of how many bytes are to be pushed on the stack. 2179 unsigned NumBytes = CCInfo.getNextStackOffset(); 2180 if (IsSibcall) 2181 // This is a sibcall. The memory operands are available in caller's 2182 // own caller's stack. 2183 NumBytes = 0; 2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2185 IsTailCallConvention(CallConv)) 2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2187 2188 int FPDiff = 0; 2189 if (isTailCall && !IsSibcall) { 2190 // Lower arguments at fp - stackoffset + fpdiff. 2191 unsigned NumBytesCallerPushed = 2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2193 FPDiff = NumBytesCallerPushed - NumBytes; 2194 2195 // Set the delta of movement of the returnaddr stackslot. 2196 // But only set if delta is greater than previous delta. 2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2199 } 2200 2201 if (!IsSibcall) 2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2203 2204 SDValue RetAddrFrIdx; 2205 // Load return address for tail calls. 2206 if (isTailCall && FPDiff) 2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2208 Is64Bit, FPDiff, dl); 2209 2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2211 SmallVector<SDValue, 8> MemOpChains; 2212 SDValue StackPtr; 2213 2214 // Walk the register/memloc assignments, inserting copies/loads. In the case 2215 // of tail call optimization arguments are handle later. 2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2217 CCValAssign &VA = ArgLocs[i]; 2218 EVT RegVT = VA.getLocVT(); 2219 SDValue Arg = OutVals[i]; 2220 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2221 bool isByVal = Flags.isByVal(); 2222 2223 // Promote the value if needed. 2224 switch (VA.getLocInfo()) { 2225 default: llvm_unreachable("Unknown loc info!"); 2226 case CCValAssign::Full: break; 2227 case CCValAssign::SExt: 2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2229 break; 2230 case CCValAssign::ZExt: 2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2232 break; 2233 case CCValAssign::AExt: 2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2235 // Special case: passing MMX values in XMM registers. 2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2239 } else 2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2241 break; 2242 case CCValAssign::BCvt: 2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2244 break; 2245 case CCValAssign::Indirect: { 2246 // Store the argument. 2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2250 MachinePointerInfo::getFixedStack(FI), 2251 false, false, 0); 2252 Arg = SpillSlot; 2253 break; 2254 } 2255 } 2256 2257 if (VA.isRegLoc()) { 2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2259 if (isVarArg && IsWin64) { 2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2261 // shadow reg if callee is a varargs function. 2262 unsigned ShadowReg = 0; 2263 switch (VA.getLocReg()) { 2264 case X86::XMM0: ShadowReg = X86::RCX; break; 2265 case X86::XMM1: ShadowReg = X86::RDX; break; 2266 case X86::XMM2: ShadowReg = X86::R8; break; 2267 case X86::XMM3: ShadowReg = X86::R9; break; 2268 } 2269 if (ShadowReg) 2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2271 } 2272 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2273 assert(VA.isMemLoc()); 2274 if (StackPtr.getNode() == 0) 2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2277 dl, DAG, VA, Flags)); 2278 } 2279 } 2280 2281 if (!MemOpChains.empty()) 2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2283 &MemOpChains[0], MemOpChains.size()); 2284 2285 // Build a sequence of copy-to-reg nodes chained together with token chain 2286 // and flag operands which copy the outgoing args into registers. 2287 SDValue InFlag; 2288 // Tail call byval lowering might overwrite argument registers so in case of 2289 // tail call optimization the copies to registers are lowered later. 2290 if (!isTailCall) 2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2293 RegsToPass[i].second, InFlag); 2294 InFlag = Chain.getValue(1); 2295 } 2296 2297 if (Subtarget->isPICStyleGOT()) { 2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2299 // GOT pointer. 2300 if (!isTailCall) { 2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2302 DAG.getNode(X86ISD::GlobalBaseReg, 2303 DebugLoc(), getPointerTy()), 2304 InFlag); 2305 InFlag = Chain.getValue(1); 2306 } else { 2307 // If we are tail calling and generating PIC/GOT style code load the 2308 // address of the callee into ECX. The value in ecx is used as target of 2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2310 // for tail calls on PIC/GOT architectures. Normally we would just put the 2311 // address of GOT into ebx and then call target@PLT. But for tail calls 2312 // ebx would be restored (since ebx is callee saved) before jumping to the 2313 // target@PLT. 2314 2315 // Note: The actual moving to ECX is done further down. 2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2317 if (G && !G->getGlobal()->hasHiddenVisibility() && 2318 !G->getGlobal()->hasProtectedVisibility()) 2319 Callee = LowerGlobalAddress(Callee, DAG); 2320 else if (isa<ExternalSymbolSDNode>(Callee)) 2321 Callee = LowerExternalSymbol(Callee, DAG); 2322 } 2323 } 2324 2325 if (Is64Bit && isVarArg && !IsWin64) { 2326 // From AMD64 ABI document: 2327 // For calls that may call functions that use varargs or stdargs 2328 // (prototype-less calls or calls to functions containing ellipsis (...) in 2329 // the declaration) %al is used as hidden argument to specify the number 2330 // of SSE registers used. The contents of %al do not need to match exactly 2331 // the number of registers, but must be an ubound on the number of SSE 2332 // registers used and is in the range 0 - 8 inclusive. 2333 2334 // Count the number of XMM registers allocated. 2335 static const uint16_t XMMArgRegs[] = { 2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2338 }; 2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2340 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2341 && "SSE registers cannot be used when SSE is disabled"); 2342 2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2345 InFlag = Chain.getValue(1); 2346 } 2347 2348 2349 // For tail calls lower the arguments to the 'real' stack slot. 2350 if (isTailCall) { 2351 // Force all the incoming stack arguments to be loaded from the stack 2352 // before any new outgoing arguments are stored to the stack, because the 2353 // outgoing stack slots may alias the incoming argument stack slots, and 2354 // the alias isn't otherwise explicit. This is slightly more conservative 2355 // than necessary, because it means that each store effectively depends 2356 // on every argument instead of just those arguments it would clobber. 2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2358 2359 SmallVector<SDValue, 8> MemOpChains2; 2360 SDValue FIN; 2361 int FI = 0; 2362 // Do not flag preceding copytoreg stuff together with the following stuff. 2363 InFlag = SDValue(); 2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2366 CCValAssign &VA = ArgLocs[i]; 2367 if (VA.isRegLoc()) 2368 continue; 2369 assert(VA.isMemLoc()); 2370 SDValue Arg = OutVals[i]; 2371 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2372 // Create frame index. 2373 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2376 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2377 2378 if (Flags.isByVal()) { 2379 // Copy relative to framepointer. 2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2381 if (StackPtr.getNode() == 0) 2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2383 getPointerTy()); 2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2385 2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2387 ArgChain, 2388 Flags, DAG, dl)); 2389 } else { 2390 // Store relative to framepointer. 2391 MemOpChains2.push_back( 2392 DAG.getStore(ArgChain, dl, Arg, FIN, 2393 MachinePointerInfo::getFixedStack(FI), 2394 false, false, 0)); 2395 } 2396 } 2397 } 2398 2399 if (!MemOpChains2.empty()) 2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2401 &MemOpChains2[0], MemOpChains2.size()); 2402 2403 // Copy arguments to their registers. 2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2406 RegsToPass[i].second, InFlag); 2407 InFlag = Chain.getValue(1); 2408 } 2409 InFlag =SDValue(); 2410 2411 // Store the return address to the appropriate stack slot. 2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2413 FPDiff, dl); 2414 } 2415 2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2418 // In the 64-bit large code model, we have to make all calls 2419 // through a register, since the call instruction's 32-bit 2420 // pc-relative offset may not be large enough to hold the whole 2421 // address. 2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2423 // If the callee is a GlobalAddress node (quite common, every direct call 2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2425 // it. 2426 2427 // We should use extra load for direct calls to dllimported functions in 2428 // non-JIT mode. 2429 const GlobalValue *GV = G->getGlobal(); 2430 if (!GV->hasDLLImportLinkage()) { 2431 unsigned char OpFlags = 0; 2432 bool ExtraLoad = false; 2433 unsigned WrapperKind = ISD::DELETED_NODE; 2434 2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2436 // external symbols most go through the PLT in PIC mode. If the symbol 2437 // has hidden or protected visibility, or if it is static or local, then 2438 // we don't need to use the PLT - we can directly call it. 2439 if (Subtarget->isTargetELF() && 2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2442 OpFlags = X86II::MO_PLT; 2443 } else if (Subtarget->isPICStyleStubAny() && 2444 (GV->isDeclaration() || GV->isWeakForLinker()) && 2445 (!Subtarget->getTargetTriple().isMacOSX() || 2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2447 // PC-relative references to external symbols should go through $stub, 2448 // unless we're building with the leopard linker or later, which 2449 // automatically synthesizes these stubs. 2450 OpFlags = X86II::MO_DARWIN_STUB; 2451 } else if (Subtarget->isPICStyleRIPRel() && 2452 isa<Function>(GV) && 2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2454 // If the function is marked as non-lazy, generate an indirect call 2455 // which loads from the GOT directly. This avoids runtime overhead 2456 // at the cost of eager binding (and one extra byte of encoding). 2457 OpFlags = X86II::MO_GOTPCREL; 2458 WrapperKind = X86ISD::WrapperRIP; 2459 ExtraLoad = true; 2460 } 2461 2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2463 G->getOffset(), OpFlags); 2464 2465 // Add a wrapper if needed. 2466 if (WrapperKind != ISD::DELETED_NODE) 2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2468 // Add extra indirection if needed. 2469 if (ExtraLoad) 2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2471 MachinePointerInfo::getGOT(), 2472 false, false, false, 0); 2473 } 2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2475 unsigned char OpFlags = 0; 2476 2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2478 // external symbols should go through the PLT. 2479 if (Subtarget->isTargetELF() && 2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2481 OpFlags = X86II::MO_PLT; 2482 } else if (Subtarget->isPICStyleStubAny() && 2483 (!Subtarget->getTargetTriple().isMacOSX() || 2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2485 // PC-relative references to external symbols should go through $stub, 2486 // unless we're building with the leopard linker or later, which 2487 // automatically synthesizes these stubs. 2488 OpFlags = X86II::MO_DARWIN_STUB; 2489 } 2490 2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2492 OpFlags); 2493 } 2494 2495 // Returns a chain & a flag for retval copy to use. 2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2497 SmallVector<SDValue, 8> Ops; 2498 2499 if (!IsSibcall && isTailCall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2501 DAG.getIntPtrConstant(0, true), InFlag); 2502 InFlag = Chain.getValue(1); 2503 } 2504 2505 Ops.push_back(Chain); 2506 Ops.push_back(Callee); 2507 2508 if (isTailCall) 2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2510 2511 // Add argument registers to the end of the list so that they are known live 2512 // into the call. 2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2515 RegsToPass[i].second.getValueType())); 2516 2517 // Add an implicit use GOT pointer in EBX. 2518 if (!isTailCall && Subtarget->isPICStyleGOT()) 2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2520 2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2522 if (Is64Bit && isVarArg && !IsWin64) 2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2524 2525 // Add a register mask operand representing the call-preserved registers. 2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2528 assert(Mask && "Missing call preserved mask for calling convention"); 2529 Ops.push_back(DAG.getRegisterMask(Mask)); 2530 2531 if (InFlag.getNode()) 2532 Ops.push_back(InFlag); 2533 2534 if (isTailCall) { 2535 // We used to do: 2536 //// If this is the first return lowered for this function, add the regs 2537 //// to the liveout set for the function. 2538 // This isn't right, although it's probably harmless on x86; liveouts 2539 // should be computed from returns not tail calls. Consider a void 2540 // function making a tail call to a function returning int. 2541 return DAG.getNode(X86ISD::TC_RETURN, dl, 2542 NodeTys, &Ops[0], Ops.size()); 2543 } 2544 2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2546 InFlag = Chain.getValue(1); 2547 2548 // Create the CALLSEQ_END node. 2549 unsigned NumBytesForCalleeToPush; 2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2551 getTargetMachine().Options.GuaranteedTailCallOpt)) 2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2554 IsStructRet) 2555 // If this is a call to a struct-return function, the callee 2556 // pops the hidden struct pointer, so we have to push it back. 2557 // This is common for Darwin/X86, Linux & Mingw32 targets. 2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2559 NumBytesForCalleeToPush = 4; 2560 else 2561 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2562 2563 // Returns a flag for retval copy to use. 2564 if (!IsSibcall) { 2565 Chain = DAG.getCALLSEQ_END(Chain, 2566 DAG.getIntPtrConstant(NumBytes, true), 2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2568 true), 2569 InFlag); 2570 InFlag = Chain.getValue(1); 2571 } 2572 2573 // Handle result values, copying them out of physregs into vregs that we 2574 // return. 2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2576 Ins, dl, DAG, InVals); 2577} 2578 2579 2580//===----------------------------------------------------------------------===// 2581// Fast Calling Convention (tail call) implementation 2582//===----------------------------------------------------------------------===// 2583 2584// Like std call, callee cleans arguments, convention except that ECX is 2585// reserved for storing the tail called function address. Only 2 registers are 2586// free for argument passing (inreg). Tail call optimization is performed 2587// provided: 2588// * tailcallopt is enabled 2589// * caller/callee are fastcc 2590// On X86_64 architecture with GOT-style position independent code only local 2591// (within module) calls are supported at the moment. 2592// To keep the stack aligned according to platform abi the function 2593// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2594// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2595// If a tail called function callee has more arguments than the caller the 2596// caller needs to make sure that there is room to move the RETADDR to. This is 2597// achieved by reserving an area the size of the argument delta right after the 2598// original REtADDR, but before the saved framepointer or the spilled registers 2599// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2600// stack layout: 2601// arg1 2602// arg2 2603// RETADDR 2604// [ new RETADDR 2605// move area ] 2606// (possible EBP) 2607// ESI 2608// EDI 2609// local1 .. 2610 2611/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2612/// for a 16 byte align requirement. 2613unsigned 2614X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2615 SelectionDAG& DAG) const { 2616 MachineFunction &MF = DAG.getMachineFunction(); 2617 const TargetMachine &TM = MF.getTarget(); 2618 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2619 unsigned StackAlignment = TFI.getStackAlignment(); 2620 uint64_t AlignMask = StackAlignment - 1; 2621 int64_t Offset = StackSize; 2622 uint64_t SlotSize = TD->getPointerSize(); 2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2624 // Number smaller than 12 so just add the difference. 2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2626 } else { 2627 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2628 Offset = ((~AlignMask) & Offset) + StackAlignment + 2629 (StackAlignment-SlotSize); 2630 } 2631 return Offset; 2632} 2633 2634/// MatchingStackOffset - Return true if the given stack call argument is 2635/// already available in the same position (relatively) of the caller's 2636/// incoming argument stack. 2637static 2638bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2640 const X86InstrInfo *TII) { 2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2642 int FI = INT_MAX; 2643 if (Arg.getOpcode() == ISD::CopyFromReg) { 2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2645 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2646 return false; 2647 MachineInstr *Def = MRI->getVRegDef(VR); 2648 if (!Def) 2649 return false; 2650 if (!Flags.isByVal()) { 2651 if (!TII->isLoadFromStackSlot(Def, FI)) 2652 return false; 2653 } else { 2654 unsigned Opcode = Def->getOpcode(); 2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2656 Def->getOperand(1).isFI()) { 2657 FI = Def->getOperand(1).getIndex(); 2658 Bytes = Flags.getByValSize(); 2659 } else 2660 return false; 2661 } 2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2663 if (Flags.isByVal()) 2664 // ByVal argument is passed in as a pointer but it's now being 2665 // dereferenced. e.g. 2666 // define @foo(%struct.X* %A) { 2667 // tail call @bar(%struct.X* byval %A) 2668 // } 2669 return false; 2670 SDValue Ptr = Ld->getBasePtr(); 2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2672 if (!FINode) 2673 return false; 2674 FI = FINode->getIndex(); 2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2677 FI = FINode->getIndex(); 2678 Bytes = Flags.getByValSize(); 2679 } else 2680 return false; 2681 2682 assert(FI != INT_MAX); 2683 if (!MFI->isFixedObjectIndex(FI)) 2684 return false; 2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2686} 2687 2688/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2689/// for tail call optimization. Targets which want to do tail call 2690/// optimization should implement this function. 2691bool 2692X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2693 CallingConv::ID CalleeCC, 2694 bool isVarArg, 2695 bool isCalleeStructRet, 2696 bool isCallerStructRet, 2697 const SmallVectorImpl<ISD::OutputArg> &Outs, 2698 const SmallVectorImpl<SDValue> &OutVals, 2699 const SmallVectorImpl<ISD::InputArg> &Ins, 2700 SelectionDAG& DAG) const { 2701 if (!IsTailCallConvention(CalleeCC) && 2702 CalleeCC != CallingConv::C) 2703 return false; 2704 2705 // If -tailcallopt is specified, make fastcc functions tail-callable. 2706 const MachineFunction &MF = DAG.getMachineFunction(); 2707 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2708 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2709 bool CCMatch = CallerCC == CalleeCC; 2710 2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2712 if (IsTailCallConvention(CalleeCC) && CCMatch) 2713 return true; 2714 return false; 2715 } 2716 2717 // Look for obvious safe cases to perform tail call optimization that do not 2718 // require ABI changes. This is what gcc calls sibcall. 2719 2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2721 // emit a special epilogue. 2722 if (RegInfo->needsStackRealignment(MF)) 2723 return false; 2724 2725 // Also avoid sibcall optimization if either caller or callee uses struct 2726 // return semantics. 2727 if (isCalleeStructRet || isCallerStructRet) 2728 return false; 2729 2730 // An stdcall caller is expected to clean up its arguments; the callee 2731 // isn't going to do that. 2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2733 return false; 2734 2735 // Do not sibcall optimize vararg calls unless all arguments are passed via 2736 // registers. 2737 if (isVarArg && !Outs.empty()) { 2738 2739 // Optimizing for varargs on Win64 is unlikely to be safe without 2740 // additional testing. 2741 if (Subtarget->isTargetWin64()) 2742 return false; 2743 2744 SmallVector<CCValAssign, 16> ArgLocs; 2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2746 getTargetMachine(), ArgLocs, *DAG.getContext()); 2747 2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2750 if (!ArgLocs[i].isRegLoc()) 2751 return false; 2752 } 2753 2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2755 // stack. Therefore, if it's not used by the call it is not safe to optimize 2756 // this into a sibcall. 2757 bool Unused = false; 2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2759 if (!Ins[i].Used) { 2760 Unused = true; 2761 break; 2762 } 2763 } 2764 if (Unused) { 2765 SmallVector<CCValAssign, 16> RVLocs; 2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2767 getTargetMachine(), RVLocs, *DAG.getContext()); 2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2770 CCValAssign &VA = RVLocs[i]; 2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2772 return false; 2773 } 2774 } 2775 2776 // If the calling conventions do not match, then we'd better make sure the 2777 // results are returned in the same way as what the caller expects. 2778 if (!CCMatch) { 2779 SmallVector<CCValAssign, 16> RVLocs1; 2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2781 getTargetMachine(), RVLocs1, *DAG.getContext()); 2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2783 2784 SmallVector<CCValAssign, 16> RVLocs2; 2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2786 getTargetMachine(), RVLocs2, *DAG.getContext()); 2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2788 2789 if (RVLocs1.size() != RVLocs2.size()) 2790 return false; 2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2793 return false; 2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2795 return false; 2796 if (RVLocs1[i].isRegLoc()) { 2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2798 return false; 2799 } else { 2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2801 return false; 2802 } 2803 } 2804 } 2805 2806 // If the callee takes no arguments then go on to check the results of the 2807 // call. 2808 if (!Outs.empty()) { 2809 // Check if stack adjustment is needed. For now, do not do this if any 2810 // argument is passed on the stack. 2811 SmallVector<CCValAssign, 16> ArgLocs; 2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2813 getTargetMachine(), ArgLocs, *DAG.getContext()); 2814 2815 // Allocate shadow area for Win64 2816 if (Subtarget->isTargetWin64()) { 2817 CCInfo.AllocateStack(32, 8); 2818 } 2819 2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2821 if (CCInfo.getNextStackOffset()) { 2822 MachineFunction &MF = DAG.getMachineFunction(); 2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2824 return false; 2825 2826 // Check if the arguments are already laid out in the right way as 2827 // the caller's fixed stack objects. 2828 MachineFrameInfo *MFI = MF.getFrameInfo(); 2829 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2830 const X86InstrInfo *TII = 2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2833 CCValAssign &VA = ArgLocs[i]; 2834 SDValue Arg = OutVals[i]; 2835 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2836 if (VA.getLocInfo() == CCValAssign::Indirect) 2837 return false; 2838 if (!VA.isRegLoc()) { 2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2840 MFI, MRI, TII)) 2841 return false; 2842 } 2843 } 2844 } 2845 2846 // If the tailcall address may be in a register, then make sure it's 2847 // possible to register allocate for it. In 32-bit, the call address can 2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2849 // callee-saved registers are restored. These happen to be the same 2850 // registers used to pass 'inreg' arguments so watch out for those. 2851 if (!Subtarget->is64Bit() && 2852 !isa<GlobalAddressSDNode>(Callee) && 2853 !isa<ExternalSymbolSDNode>(Callee)) { 2854 unsigned NumInRegs = 0; 2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2856 CCValAssign &VA = ArgLocs[i]; 2857 if (!VA.isRegLoc()) 2858 continue; 2859 unsigned Reg = VA.getLocReg(); 2860 switch (Reg) { 2861 default: break; 2862 case X86::EAX: case X86::EDX: case X86::ECX: 2863 if (++NumInRegs == 3) 2864 return false; 2865 break; 2866 } 2867 } 2868 } 2869 } 2870 2871 return true; 2872} 2873 2874FastISel * 2875X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2876 return X86::createFastISel(funcInfo); 2877} 2878 2879 2880//===----------------------------------------------------------------------===// 2881// Other Lowering Hooks 2882//===----------------------------------------------------------------------===// 2883 2884static bool MayFoldLoad(SDValue Op) { 2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2886} 2887 2888static bool MayFoldIntoStore(SDValue Op) { 2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2890} 2891 2892static bool isTargetShuffle(unsigned Opcode) { 2893 switch(Opcode) { 2894 default: return false; 2895 case X86ISD::PSHUFD: 2896 case X86ISD::PSHUFHW: 2897 case X86ISD::PSHUFLW: 2898 case X86ISD::SHUFP: 2899 case X86ISD::PALIGN: 2900 case X86ISD::MOVLHPS: 2901 case X86ISD::MOVLHPD: 2902 case X86ISD::MOVHLPS: 2903 case X86ISD::MOVLPS: 2904 case X86ISD::MOVLPD: 2905 case X86ISD::MOVSHDUP: 2906 case X86ISD::MOVSLDUP: 2907 case X86ISD::MOVDDUP: 2908 case X86ISD::MOVSS: 2909 case X86ISD::MOVSD: 2910 case X86ISD::UNPCKL: 2911 case X86ISD::UNPCKH: 2912 case X86ISD::VPERMILP: 2913 case X86ISD::VPERM2X128: 2914 return true; 2915 } 2916} 2917 2918static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2919 SDValue V1, SelectionDAG &DAG) { 2920 switch(Opc) { 2921 default: llvm_unreachable("Unknown x86 shuffle node"); 2922 case X86ISD::MOVSHDUP: 2923 case X86ISD::MOVSLDUP: 2924 case X86ISD::MOVDDUP: 2925 return DAG.getNode(Opc, dl, VT, V1); 2926 } 2927} 2928 2929static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2930 SDValue V1, unsigned TargetMask, 2931 SelectionDAG &DAG) { 2932 switch(Opc) { 2933 default: llvm_unreachable("Unknown x86 shuffle node"); 2934 case X86ISD::PSHUFD: 2935 case X86ISD::PSHUFHW: 2936 case X86ISD::PSHUFLW: 2937 case X86ISD::VPERMILP: 2938 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2939 } 2940} 2941 2942static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2943 SDValue V1, SDValue V2, unsigned TargetMask, 2944 SelectionDAG &DAG) { 2945 switch(Opc) { 2946 default: llvm_unreachable("Unknown x86 shuffle node"); 2947 case X86ISD::PALIGN: 2948 case X86ISD::SHUFP: 2949 case X86ISD::VPERM2X128: 2950 return DAG.getNode(Opc, dl, VT, V1, V2, 2951 DAG.getConstant(TargetMask, MVT::i8)); 2952 } 2953} 2954 2955static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2956 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2957 switch(Opc) { 2958 default: llvm_unreachable("Unknown x86 shuffle node"); 2959 case X86ISD::MOVLHPS: 2960 case X86ISD::MOVLHPD: 2961 case X86ISD::MOVHLPS: 2962 case X86ISD::MOVLPS: 2963 case X86ISD::MOVLPD: 2964 case X86ISD::MOVSS: 2965 case X86ISD::MOVSD: 2966 case X86ISD::UNPCKL: 2967 case X86ISD::UNPCKH: 2968 return DAG.getNode(Opc, dl, VT, V1, V2); 2969 } 2970} 2971 2972SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2973 MachineFunction &MF = DAG.getMachineFunction(); 2974 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2975 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2976 2977 if (ReturnAddrIndex == 0) { 2978 // Set up a frame object for the return address. 2979 uint64_t SlotSize = TD->getPointerSize(); 2980 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2981 false); 2982 FuncInfo->setRAIndex(ReturnAddrIndex); 2983 } 2984 2985 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2986} 2987 2988 2989bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2990 bool hasSymbolicDisplacement) { 2991 // Offset should fit into 32 bit immediate field. 2992 if (!isInt<32>(Offset)) 2993 return false; 2994 2995 // If we don't have a symbolic displacement - we don't have any extra 2996 // restrictions. 2997 if (!hasSymbolicDisplacement) 2998 return true; 2999 3000 // FIXME: Some tweaks might be needed for medium code model. 3001 if (M != CodeModel::Small && M != CodeModel::Kernel) 3002 return false; 3003 3004 // For small code model we assume that latest object is 16MB before end of 31 3005 // bits boundary. We may also accept pretty large negative constants knowing 3006 // that all objects are in the positive half of address space. 3007 if (M == CodeModel::Small && Offset < 16*1024*1024) 3008 return true; 3009 3010 // For kernel code model we know that all object resist in the negative half 3011 // of 32bits address space. We may not accept negative offsets, since they may 3012 // be just off and we may accept pretty large positive ones. 3013 if (M == CodeModel::Kernel && Offset > 0) 3014 return true; 3015 3016 return false; 3017} 3018 3019/// isCalleePop - Determines whether the callee is required to pop its 3020/// own arguments. Callee pop is necessary to support tail calls. 3021bool X86::isCalleePop(CallingConv::ID CallingConv, 3022 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3023 if (IsVarArg) 3024 return false; 3025 3026 switch (CallingConv) { 3027 default: 3028 return false; 3029 case CallingConv::X86_StdCall: 3030 return !is64Bit; 3031 case CallingConv::X86_FastCall: 3032 return !is64Bit; 3033 case CallingConv::X86_ThisCall: 3034 return !is64Bit; 3035 case CallingConv::Fast: 3036 return TailCallOpt; 3037 case CallingConv::GHC: 3038 return TailCallOpt; 3039 } 3040} 3041 3042/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3043/// specific condition code, returning the condition code and the LHS/RHS of the 3044/// comparison to make. 3045static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3046 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3047 if (!isFP) { 3048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3049 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3050 // X > -1 -> X == 0, jump !sign. 3051 RHS = DAG.getConstant(0, RHS.getValueType()); 3052 return X86::COND_NS; 3053 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3054 // X < 0 -> X == 0, jump on sign. 3055 return X86::COND_S; 3056 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3057 // X < 1 -> X <= 0 3058 RHS = DAG.getConstant(0, RHS.getValueType()); 3059 return X86::COND_LE; 3060 } 3061 } 3062 3063 switch (SetCCOpcode) { 3064 default: llvm_unreachable("Invalid integer condition!"); 3065 case ISD::SETEQ: return X86::COND_E; 3066 case ISD::SETGT: return X86::COND_G; 3067 case ISD::SETGE: return X86::COND_GE; 3068 case ISD::SETLT: return X86::COND_L; 3069 case ISD::SETLE: return X86::COND_LE; 3070 case ISD::SETNE: return X86::COND_NE; 3071 case ISD::SETULT: return X86::COND_B; 3072 case ISD::SETUGT: return X86::COND_A; 3073 case ISD::SETULE: return X86::COND_BE; 3074 case ISD::SETUGE: return X86::COND_AE; 3075 } 3076 } 3077 3078 // First determine if it is required or is profitable to flip the operands. 3079 3080 // If LHS is a foldable load, but RHS is not, flip the condition. 3081 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3082 !ISD::isNON_EXTLoad(RHS.getNode())) { 3083 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3084 std::swap(LHS, RHS); 3085 } 3086 3087 switch (SetCCOpcode) { 3088 default: break; 3089 case ISD::SETOLT: 3090 case ISD::SETOLE: 3091 case ISD::SETUGT: 3092 case ISD::SETUGE: 3093 std::swap(LHS, RHS); 3094 break; 3095 } 3096 3097 // On a floating point condition, the flags are set as follows: 3098 // ZF PF CF op 3099 // 0 | 0 | 0 | X > Y 3100 // 0 | 0 | 1 | X < Y 3101 // 1 | 0 | 0 | X == Y 3102 // 1 | 1 | 1 | unordered 3103 switch (SetCCOpcode) { 3104 default: llvm_unreachable("Condcode should be pre-legalized away"); 3105 case ISD::SETUEQ: 3106 case ISD::SETEQ: return X86::COND_E; 3107 case ISD::SETOLT: // flipped 3108 case ISD::SETOGT: 3109 case ISD::SETGT: return X86::COND_A; 3110 case ISD::SETOLE: // flipped 3111 case ISD::SETOGE: 3112 case ISD::SETGE: return X86::COND_AE; 3113 case ISD::SETUGT: // flipped 3114 case ISD::SETULT: 3115 case ISD::SETLT: return X86::COND_B; 3116 case ISD::SETUGE: // flipped 3117 case ISD::SETULE: 3118 case ISD::SETLE: return X86::COND_BE; 3119 case ISD::SETONE: 3120 case ISD::SETNE: return X86::COND_NE; 3121 case ISD::SETUO: return X86::COND_P; 3122 case ISD::SETO: return X86::COND_NP; 3123 case ISD::SETOEQ: 3124 case ISD::SETUNE: return X86::COND_INVALID; 3125 } 3126} 3127 3128/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3129/// code. Current x86 isa includes the following FP cmov instructions: 3130/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3131static bool hasFPCMov(unsigned X86CC) { 3132 switch (X86CC) { 3133 default: 3134 return false; 3135 case X86::COND_B: 3136 case X86::COND_BE: 3137 case X86::COND_E: 3138 case X86::COND_P: 3139 case X86::COND_A: 3140 case X86::COND_AE: 3141 case X86::COND_NE: 3142 case X86::COND_NP: 3143 return true; 3144 } 3145} 3146 3147/// isFPImmLegal - Returns true if the target can instruction select the 3148/// specified FP immediate natively. If false, the legalizer will 3149/// materialize the FP immediate as a load from a constant pool. 3150bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3151 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3152 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3153 return true; 3154 } 3155 return false; 3156} 3157 3158/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3159/// the specified range (L, H]. 3160static bool isUndefOrInRange(int Val, int Low, int Hi) { 3161 return (Val < 0) || (Val >= Low && Val < Hi); 3162} 3163 3164/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3165/// specified value. 3166static bool isUndefOrEqual(int Val, int CmpVal) { 3167 if (Val < 0 || Val == CmpVal) 3168 return true; 3169 return false; 3170} 3171 3172/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3173/// from position Pos and ending in Pos+Size, falls within the specified 3174/// sequential range (L, L+Pos]. or is undef. 3175static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3176 int Pos, int Size, int Low) { 3177 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3178 if (!isUndefOrEqual(Mask[i], Low)) 3179 return false; 3180 return true; 3181} 3182 3183/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3184/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3185/// the second operand. 3186static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3187 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3188 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3189 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3190 return (Mask[0] < 2 && Mask[1] < 2); 3191 return false; 3192} 3193 3194/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3195/// is suitable for input to PSHUFHW. 3196static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3197 if (VT != MVT::v8i16) 3198 return false; 3199 3200 // Lower quadword copied in order or undef. 3201 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3202 return false; 3203 3204 // Upper quadword shuffled. 3205 for (unsigned i = 4; i != 8; ++i) 3206 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3207 return false; 3208 3209 return true; 3210} 3211 3212/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3213/// is suitable for input to PSHUFLW. 3214static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3215 if (VT != MVT::v8i16) 3216 return false; 3217 3218 // Upper quadword copied in order. 3219 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3220 return false; 3221 3222 // Lower quadword shuffled. 3223 for (unsigned i = 0; i != 4; ++i) 3224 if (Mask[i] >= 4) 3225 return false; 3226 3227 return true; 3228} 3229 3230/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3231/// is suitable for input to PALIGNR. 3232static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3233 const X86Subtarget *Subtarget) { 3234 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3235 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3236 return false; 3237 3238 unsigned NumElts = VT.getVectorNumElements(); 3239 unsigned NumLanes = VT.getSizeInBits()/128; 3240 unsigned NumLaneElts = NumElts/NumLanes; 3241 3242 // Do not handle 64-bit element shuffles with palignr. 3243 if (NumLaneElts == 2) 3244 return false; 3245 3246 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3247 unsigned i; 3248 for (i = 0; i != NumLaneElts; ++i) { 3249 if (Mask[i+l] >= 0) 3250 break; 3251 } 3252 3253 // Lane is all undef, go to next lane 3254 if (i == NumLaneElts) 3255 continue; 3256 3257 int Start = Mask[i+l]; 3258 3259 // Make sure its in this lane in one of the sources 3260 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3261 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3262 return false; 3263 3264 // If not lane 0, then we must match lane 0 3265 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3266 return false; 3267 3268 // Correct second source to be contiguous with first source 3269 if (Start >= (int)NumElts) 3270 Start -= NumElts - NumLaneElts; 3271 3272 // Make sure we're shifting in the right direction. 3273 if (Start <= (int)(i+l)) 3274 return false; 3275 3276 Start -= i; 3277 3278 // Check the rest of the elements to see if they are consecutive. 3279 for (++i; i != NumLaneElts; ++i) { 3280 int Idx = Mask[i+l]; 3281 3282 // Make sure its in this lane 3283 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3284 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3285 return false; 3286 3287 // If not lane 0, then we must match lane 0 3288 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3289 return false; 3290 3291 if (Idx >= (int)NumElts) 3292 Idx -= NumElts - NumLaneElts; 3293 3294 if (!isUndefOrEqual(Idx, Start+i)) 3295 return false; 3296 3297 } 3298 } 3299 3300 return true; 3301} 3302 3303/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3304/// the two vector operands have swapped position. 3305static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3306 unsigned NumElems) { 3307 for (unsigned i = 0; i != NumElems; ++i) { 3308 int idx = Mask[i]; 3309 if (idx < 0) 3310 continue; 3311 else if (idx < (int)NumElems) 3312 Mask[i] = idx + NumElems; 3313 else 3314 Mask[i] = idx - NumElems; 3315 } 3316} 3317 3318/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3319/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3320/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3321/// reverse of what x86 shuffles want. 3322static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3323 bool Commuted = false) { 3324 if (!HasAVX && VT.getSizeInBits() == 256) 3325 return false; 3326 3327 unsigned NumElems = VT.getVectorNumElements(); 3328 unsigned NumLanes = VT.getSizeInBits()/128; 3329 unsigned NumLaneElems = NumElems/NumLanes; 3330 3331 if (NumLaneElems != 2 && NumLaneElems != 4) 3332 return false; 3333 3334 // VSHUFPSY divides the resulting vector into 4 chunks. 3335 // The sources are also splitted into 4 chunks, and each destination 3336 // chunk must come from a different source chunk. 3337 // 3338 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3339 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3340 // 3341 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3342 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3343 // 3344 // VSHUFPDY divides the resulting vector into 4 chunks. 3345 // The sources are also splitted into 4 chunks, and each destination 3346 // chunk must come from a different source chunk. 3347 // 3348 // SRC1 => X3 X2 X1 X0 3349 // SRC2 => Y3 Y2 Y1 Y0 3350 // 3351 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3352 // 3353 unsigned HalfLaneElems = NumLaneElems/2; 3354 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3355 for (unsigned i = 0; i != NumLaneElems; ++i) { 3356 int Idx = Mask[i+l]; 3357 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3358 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3359 return false; 3360 // For VSHUFPSY, the mask of the second half must be the same as the 3361 // first but with the appropriate offsets. This works in the same way as 3362 // VPERMILPS works with masks. 3363 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3364 continue; 3365 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3366 return false; 3367 } 3368 } 3369 3370 return true; 3371} 3372 3373/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3374/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3375static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3376 unsigned NumElems = VT.getVectorNumElements(); 3377 3378 if (VT.getSizeInBits() != 128) 3379 return false; 3380 3381 if (NumElems != 4) 3382 return false; 3383 3384 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3385 return isUndefOrEqual(Mask[0], 6) && 3386 isUndefOrEqual(Mask[1], 7) && 3387 isUndefOrEqual(Mask[2], 2) && 3388 isUndefOrEqual(Mask[3], 3); 3389} 3390 3391/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3392/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3393/// <2, 3, 2, 3> 3394static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3395 unsigned NumElems = VT.getVectorNumElements(); 3396 3397 if (VT.getSizeInBits() != 128) 3398 return false; 3399 3400 if (NumElems != 4) 3401 return false; 3402 3403 return isUndefOrEqual(Mask[0], 2) && 3404 isUndefOrEqual(Mask[1], 3) && 3405 isUndefOrEqual(Mask[2], 2) && 3406 isUndefOrEqual(Mask[3], 3); 3407} 3408 3409/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3410/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3411static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3412 if (VT.getSizeInBits() != 128) 3413 return false; 3414 3415 unsigned NumElems = VT.getVectorNumElements(); 3416 3417 if (NumElems != 2 && NumElems != 4) 3418 return false; 3419 3420 for (unsigned i = 0; i != NumElems/2; ++i) 3421 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3422 return false; 3423 3424 for (unsigned i = NumElems/2; i != NumElems; ++i) 3425 if (!isUndefOrEqual(Mask[i], i)) 3426 return false; 3427 3428 return true; 3429} 3430 3431/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3432/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3433static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3434 unsigned NumElems = VT.getVectorNumElements(); 3435 3436 if ((NumElems != 2 && NumElems != 4) 3437 || VT.getSizeInBits() > 128) 3438 return false; 3439 3440 for (unsigned i = 0; i != NumElems/2; ++i) 3441 if (!isUndefOrEqual(Mask[i], i)) 3442 return false; 3443 3444 for (unsigned i = 0; i != NumElems/2; ++i) 3445 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems)) 3446 return false; 3447 3448 return true; 3449} 3450 3451/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3452/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3453static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3454 bool HasAVX2, bool V2IsSplat = false) { 3455 unsigned NumElts = VT.getVectorNumElements(); 3456 3457 assert((VT.is128BitVector() || VT.is256BitVector()) && 3458 "Unsupported vector type for unpckh"); 3459 3460 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3461 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3462 return false; 3463 3464 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3465 // independently on 128-bit lanes. 3466 unsigned NumLanes = VT.getSizeInBits()/128; 3467 unsigned NumLaneElts = NumElts/NumLanes; 3468 3469 for (unsigned l = 0; l != NumLanes; ++l) { 3470 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3471 i != (l+1)*NumLaneElts; 3472 i += 2, ++j) { 3473 int BitI = Mask[i]; 3474 int BitI1 = Mask[i+1]; 3475 if (!isUndefOrEqual(BitI, j)) 3476 return false; 3477 if (V2IsSplat) { 3478 if (!isUndefOrEqual(BitI1, NumElts)) 3479 return false; 3480 } else { 3481 if (!isUndefOrEqual(BitI1, j + NumElts)) 3482 return false; 3483 } 3484 } 3485 } 3486 3487 return true; 3488} 3489 3490/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3491/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3492static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3493 bool HasAVX2, bool V2IsSplat = false) { 3494 unsigned NumElts = VT.getVectorNumElements(); 3495 3496 assert((VT.is128BitVector() || VT.is256BitVector()) && 3497 "Unsupported vector type for unpckh"); 3498 3499 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3500 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3501 return false; 3502 3503 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3504 // independently on 128-bit lanes. 3505 unsigned NumLanes = VT.getSizeInBits()/128; 3506 unsigned NumLaneElts = NumElts/NumLanes; 3507 3508 for (unsigned l = 0; l != NumLanes; ++l) { 3509 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3510 i != (l+1)*NumLaneElts; i += 2, ++j) { 3511 int BitI = Mask[i]; 3512 int BitI1 = Mask[i+1]; 3513 if (!isUndefOrEqual(BitI, j)) 3514 return false; 3515 if (V2IsSplat) { 3516 if (isUndefOrEqual(BitI1, NumElts)) 3517 return false; 3518 } else { 3519 if (!isUndefOrEqual(BitI1, j+NumElts)) 3520 return false; 3521 } 3522 } 3523 } 3524 return true; 3525} 3526 3527/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3528/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3529/// <0, 0, 1, 1> 3530static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3531 bool HasAVX2) { 3532 unsigned NumElts = VT.getVectorNumElements(); 3533 3534 assert((VT.is128BitVector() || VT.is256BitVector()) && 3535 "Unsupported vector type for unpckh"); 3536 3537 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3538 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3539 return false; 3540 3541 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3542 // FIXME: Need a better way to get rid of this, there's no latency difference 3543 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3544 // the former later. We should also remove the "_undef" special mask. 3545 if (NumElts == 4 && VT.getSizeInBits() == 256) 3546 return false; 3547 3548 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3549 // independently on 128-bit lanes. 3550 unsigned NumLanes = VT.getSizeInBits()/128; 3551 unsigned NumLaneElts = NumElts/NumLanes; 3552 3553 for (unsigned l = 0; l != NumLanes; ++l) { 3554 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3555 i != (l+1)*NumLaneElts; 3556 i += 2, ++j) { 3557 int BitI = Mask[i]; 3558 int BitI1 = Mask[i+1]; 3559 3560 if (!isUndefOrEqual(BitI, j)) 3561 return false; 3562 if (!isUndefOrEqual(BitI1, j)) 3563 return false; 3564 } 3565 } 3566 3567 return true; 3568} 3569 3570/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3571/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3572/// <2, 2, 3, 3> 3573static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3574 unsigned NumElts = VT.getVectorNumElements(); 3575 3576 assert((VT.is128BitVector() || VT.is256BitVector()) && 3577 "Unsupported vector type for unpckh"); 3578 3579 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3580 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3581 return false; 3582 3583 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3584 // independently on 128-bit lanes. 3585 unsigned NumLanes = VT.getSizeInBits()/128; 3586 unsigned NumLaneElts = NumElts/NumLanes; 3587 3588 for (unsigned l = 0; l != NumLanes; ++l) { 3589 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3590 i != (l+1)*NumLaneElts; i += 2, ++j) { 3591 int BitI = Mask[i]; 3592 int BitI1 = Mask[i+1]; 3593 if (!isUndefOrEqual(BitI, j)) 3594 return false; 3595 if (!isUndefOrEqual(BitI1, j)) 3596 return false; 3597 } 3598 } 3599 return true; 3600} 3601 3602/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3603/// specifies a shuffle of elements that is suitable for input to MOVSS, 3604/// MOVSD, and MOVD, i.e. setting the lowest element. 3605static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3606 if (VT.getVectorElementType().getSizeInBits() < 32) 3607 return false; 3608 if (VT.getSizeInBits() == 256) 3609 return false; 3610 3611 unsigned NumElts = VT.getVectorNumElements(); 3612 3613 if (!isUndefOrEqual(Mask[0], NumElts)) 3614 return false; 3615 3616 for (unsigned i = 1; i != NumElts; ++i) 3617 if (!isUndefOrEqual(Mask[i], i)) 3618 return false; 3619 3620 return true; 3621} 3622 3623/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3624/// as permutations between 128-bit chunks or halves. As an example: this 3625/// shuffle bellow: 3626/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3627/// The first half comes from the second half of V1 and the second half from the 3628/// the second half of V2. 3629static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3630 if (!HasAVX || VT.getSizeInBits() != 256) 3631 return false; 3632 3633 // The shuffle result is divided into half A and half B. In total the two 3634 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3635 // B must come from C, D, E or F. 3636 unsigned HalfSize = VT.getVectorNumElements()/2; 3637 bool MatchA = false, MatchB = false; 3638 3639 // Check if A comes from one of C, D, E, F. 3640 for (unsigned Half = 0; Half != 4; ++Half) { 3641 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3642 MatchA = true; 3643 break; 3644 } 3645 } 3646 3647 // Check if B comes from one of C, D, E, F. 3648 for (unsigned Half = 0; Half != 4; ++Half) { 3649 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3650 MatchB = true; 3651 break; 3652 } 3653 } 3654 3655 return MatchA && MatchB; 3656} 3657 3658/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3659/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3660static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3661 EVT VT = SVOp->getValueType(0); 3662 3663 unsigned HalfSize = VT.getVectorNumElements()/2; 3664 3665 unsigned FstHalf = 0, SndHalf = 0; 3666 for (unsigned i = 0; i < HalfSize; ++i) { 3667 if (SVOp->getMaskElt(i) > 0) { 3668 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3669 break; 3670 } 3671 } 3672 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3673 if (SVOp->getMaskElt(i) > 0) { 3674 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3675 break; 3676 } 3677 } 3678 3679 return (FstHalf | (SndHalf << 4)); 3680} 3681 3682/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3683/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3684/// Note that VPERMIL mask matching is different depending whether theunderlying 3685/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3686/// to the same elements of the low, but to the higher half of the source. 3687/// In VPERMILPD the two lanes could be shuffled independently of each other 3688/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3689static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3690 if (!HasAVX) 3691 return false; 3692 3693 unsigned NumElts = VT.getVectorNumElements(); 3694 // Only match 256-bit with 32/64-bit types 3695 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3696 return false; 3697 3698 unsigned NumLanes = VT.getSizeInBits()/128; 3699 unsigned LaneSize = NumElts/NumLanes; 3700 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3701 for (unsigned i = 0; i != LaneSize; ++i) { 3702 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3703 return false; 3704 if (NumElts != 8 || l == 0) 3705 continue; 3706 // VPERMILPS handling 3707 if (Mask[i] < 0) 3708 continue; 3709 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3710 return false; 3711 } 3712 } 3713 3714 return true; 3715} 3716 3717/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3718/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3719/// element of vector 2 and the other elements to come from vector 1 in order. 3720static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3721 bool V2IsSplat = false, bool V2IsUndef = false) { 3722 unsigned NumOps = VT.getVectorNumElements(); 3723 if (VT.getSizeInBits() == 256) 3724 return false; 3725 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3726 return false; 3727 3728 if (!isUndefOrEqual(Mask[0], 0)) 3729 return false; 3730 3731 for (unsigned i = 1; i != NumOps; ++i) 3732 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3733 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3734 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3735 return false; 3736 3737 return true; 3738} 3739 3740/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3741/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3742/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3743static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3744 const X86Subtarget *Subtarget) { 3745 if (!Subtarget->hasSSE3()) 3746 return false; 3747 3748 unsigned NumElems = VT.getVectorNumElements(); 3749 3750 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3751 (VT.getSizeInBits() == 256 && NumElems != 8)) 3752 return false; 3753 3754 // "i+1" is the value the indexed mask element must have 3755 for (unsigned i = 0; i != NumElems; i += 2) 3756 if (!isUndefOrEqual(Mask[i], i+1) || 3757 !isUndefOrEqual(Mask[i+1], i+1)) 3758 return false; 3759 3760 return true; 3761} 3762 3763/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3764/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3765/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3766static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3767 const X86Subtarget *Subtarget) { 3768 if (!Subtarget->hasSSE3()) 3769 return false; 3770 3771 unsigned NumElems = VT.getVectorNumElements(); 3772 3773 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3774 (VT.getSizeInBits() == 256 && NumElems != 8)) 3775 return false; 3776 3777 // "i" is the value the indexed mask element must have 3778 for (unsigned i = 0; i != NumElems; i += 2) 3779 if (!isUndefOrEqual(Mask[i], i) || 3780 !isUndefOrEqual(Mask[i+1], i)) 3781 return false; 3782 3783 return true; 3784} 3785 3786/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3787/// specifies a shuffle of elements that is suitable for input to 256-bit 3788/// version of MOVDDUP. 3789static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3790 unsigned NumElts = VT.getVectorNumElements(); 3791 3792 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3793 return false; 3794 3795 for (unsigned i = 0; i != NumElts/2; ++i) 3796 if (!isUndefOrEqual(Mask[i], 0)) 3797 return false; 3798 for (unsigned i = NumElts/2; i != NumElts; ++i) 3799 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3800 return false; 3801 return true; 3802} 3803 3804/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3805/// specifies a shuffle of elements that is suitable for input to 128-bit 3806/// version of MOVDDUP. 3807static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3808 if (VT.getSizeInBits() != 128) 3809 return false; 3810 3811 unsigned e = VT.getVectorNumElements() / 2; 3812 for (unsigned i = 0; i != e; ++i) 3813 if (!isUndefOrEqual(Mask[i], i)) 3814 return false; 3815 for (unsigned i = 0; i != e; ++i) 3816 if (!isUndefOrEqual(Mask[e+i], i)) 3817 return false; 3818 return true; 3819} 3820 3821/// isVEXTRACTF128Index - Return true if the specified 3822/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3823/// suitable for input to VEXTRACTF128. 3824bool X86::isVEXTRACTF128Index(SDNode *N) { 3825 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3826 return false; 3827 3828 // The index should be aligned on a 128-bit boundary. 3829 uint64_t Index = 3830 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3831 3832 unsigned VL = N->getValueType(0).getVectorNumElements(); 3833 unsigned VBits = N->getValueType(0).getSizeInBits(); 3834 unsigned ElSize = VBits / VL; 3835 bool Result = (Index * ElSize) % 128 == 0; 3836 3837 return Result; 3838} 3839 3840/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3841/// operand specifies a subvector insert that is suitable for input to 3842/// VINSERTF128. 3843bool X86::isVINSERTF128Index(SDNode *N) { 3844 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3845 return false; 3846 3847 // The index should be aligned on a 128-bit boundary. 3848 uint64_t Index = 3849 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3850 3851 unsigned VL = N->getValueType(0).getVectorNumElements(); 3852 unsigned VBits = N->getValueType(0).getSizeInBits(); 3853 unsigned ElSize = VBits / VL; 3854 bool Result = (Index * ElSize) % 128 == 0; 3855 3856 return Result; 3857} 3858 3859/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3860/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3861/// Handles 128-bit and 256-bit. 3862static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3863 EVT VT = N->getValueType(0); 3864 3865 assert((VT.is128BitVector() || VT.is256BitVector()) && 3866 "Unsupported vector type for PSHUF/SHUFP"); 3867 3868 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3869 // independently on 128-bit lanes. 3870 unsigned NumElts = VT.getVectorNumElements(); 3871 unsigned NumLanes = VT.getSizeInBits()/128; 3872 unsigned NumLaneElts = NumElts/NumLanes; 3873 3874 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3875 "Only supports 2 or 4 elements per lane"); 3876 3877 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3878 unsigned Mask = 0; 3879 for (unsigned i = 0; i != NumElts; ++i) { 3880 int Elt = N->getMaskElt(i); 3881 if (Elt < 0) continue; 3882 Elt %= NumLaneElts; 3883 unsigned ShAmt = i << Shift; 3884 if (ShAmt >= 8) ShAmt -= 8; 3885 Mask |= Elt << ShAmt; 3886 } 3887 3888 return Mask; 3889} 3890 3891/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3892/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3893static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3894 unsigned Mask = 0; 3895 // 8 nodes, but we only care about the last 4. 3896 for (unsigned i = 7; i >= 4; --i) { 3897 int Val = N->getMaskElt(i); 3898 if (Val >= 0) 3899 Mask |= (Val - 4); 3900 if (i != 4) 3901 Mask <<= 2; 3902 } 3903 return Mask; 3904} 3905 3906/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3907/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3908static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3909 unsigned Mask = 0; 3910 // 8 nodes, but we only care about the first 4. 3911 for (int i = 3; i >= 0; --i) { 3912 int Val = N->getMaskElt(i); 3913 if (Val >= 0) 3914 Mask |= Val; 3915 if (i != 0) 3916 Mask <<= 2; 3917 } 3918 return Mask; 3919} 3920 3921/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3922/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3923static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3924 EVT VT = SVOp->getValueType(0); 3925 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3926 3927 unsigned NumElts = VT.getVectorNumElements(); 3928 unsigned NumLanes = VT.getSizeInBits()/128; 3929 unsigned NumLaneElts = NumElts/NumLanes; 3930 3931 int Val = 0; 3932 unsigned i; 3933 for (i = 0; i != NumElts; ++i) { 3934 Val = SVOp->getMaskElt(i); 3935 if (Val >= 0) 3936 break; 3937 } 3938 if (Val >= (int)NumElts) 3939 Val -= NumElts - NumLaneElts; 3940 3941 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3942 return (Val - i) * EltSize; 3943} 3944 3945/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3946/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3947/// instructions. 3948unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3949 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3950 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3951 3952 uint64_t Index = 3953 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3954 3955 EVT VecVT = N->getOperand(0).getValueType(); 3956 EVT ElVT = VecVT.getVectorElementType(); 3957 3958 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3959 return Index / NumElemsPerChunk; 3960} 3961 3962/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3963/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3964/// instructions. 3965unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3966 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3967 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3968 3969 uint64_t Index = 3970 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3971 3972 EVT VecVT = N->getValueType(0); 3973 EVT ElVT = VecVT.getVectorElementType(); 3974 3975 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3976 return Index / NumElemsPerChunk; 3977} 3978 3979/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3980/// constant +0.0. 3981bool X86::isZeroNode(SDValue Elt) { 3982 return ((isa<ConstantSDNode>(Elt) && 3983 cast<ConstantSDNode>(Elt)->isNullValue()) || 3984 (isa<ConstantFPSDNode>(Elt) && 3985 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3986} 3987 3988/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3989/// their permute mask. 3990static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3991 SelectionDAG &DAG) { 3992 EVT VT = SVOp->getValueType(0); 3993 unsigned NumElems = VT.getVectorNumElements(); 3994 SmallVector<int, 8> MaskVec; 3995 3996 for (unsigned i = 0; i != NumElems; ++i) { 3997 int idx = SVOp->getMaskElt(i); 3998 if (idx < 0) 3999 MaskVec.push_back(idx); 4000 else if (idx < (int)NumElems) 4001 MaskVec.push_back(idx + NumElems); 4002 else 4003 MaskVec.push_back(idx - NumElems); 4004 } 4005 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4006 SVOp->getOperand(0), &MaskVec[0]); 4007} 4008 4009/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4010/// match movhlps. The lower half elements should come from upper half of 4011/// V1 (and in order), and the upper half elements should come from the upper 4012/// half of V2 (and in order). 4013static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4014 if (VT.getSizeInBits() != 128) 4015 return false; 4016 if (VT.getVectorNumElements() != 4) 4017 return false; 4018 for (unsigned i = 0, e = 2; i != e; ++i) 4019 if (!isUndefOrEqual(Mask[i], i+2)) 4020 return false; 4021 for (unsigned i = 2; i != 4; ++i) 4022 if (!isUndefOrEqual(Mask[i], i+4)) 4023 return false; 4024 return true; 4025} 4026 4027/// isScalarLoadToVector - Returns true if the node is a scalar load that 4028/// is promoted to a vector. It also returns the LoadSDNode by reference if 4029/// required. 4030static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4031 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4032 return false; 4033 N = N->getOperand(0).getNode(); 4034 if (!ISD::isNON_EXTLoad(N)) 4035 return false; 4036 if (LD) 4037 *LD = cast<LoadSDNode>(N); 4038 return true; 4039} 4040 4041// Test whether the given value is a vector value which will be legalized 4042// into a load. 4043static bool WillBeConstantPoolLoad(SDNode *N) { 4044 if (N->getOpcode() != ISD::BUILD_VECTOR) 4045 return false; 4046 4047 // Check for any non-constant elements. 4048 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4049 switch (N->getOperand(i).getNode()->getOpcode()) { 4050 case ISD::UNDEF: 4051 case ISD::ConstantFP: 4052 case ISD::Constant: 4053 break; 4054 default: 4055 return false; 4056 } 4057 4058 // Vectors of all-zeros and all-ones are materialized with special 4059 // instructions rather than being loaded. 4060 return !ISD::isBuildVectorAllZeros(N) && 4061 !ISD::isBuildVectorAllOnes(N); 4062} 4063 4064/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4065/// match movlp{s|d}. The lower half elements should come from lower half of 4066/// V1 (and in order), and the upper half elements should come from the upper 4067/// half of V2 (and in order). And since V1 will become the source of the 4068/// MOVLP, it must be either a vector load or a scalar load to vector. 4069static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4070 ArrayRef<int> Mask, EVT VT) { 4071 if (VT.getSizeInBits() != 128) 4072 return false; 4073 4074 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4075 return false; 4076 // Is V2 is a vector load, don't do this transformation. We will try to use 4077 // load folding shufps op. 4078 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4079 return false; 4080 4081 unsigned NumElems = VT.getVectorNumElements(); 4082 4083 if (NumElems != 2 && NumElems != 4) 4084 return false; 4085 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4086 if (!isUndefOrEqual(Mask[i], i)) 4087 return false; 4088 for (unsigned i = NumElems/2; i != NumElems; ++i) 4089 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4090 return false; 4091 return true; 4092} 4093 4094/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4095/// all the same. 4096static bool isSplatVector(SDNode *N) { 4097 if (N->getOpcode() != ISD::BUILD_VECTOR) 4098 return false; 4099 4100 SDValue SplatValue = N->getOperand(0); 4101 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4102 if (N->getOperand(i) != SplatValue) 4103 return false; 4104 return true; 4105} 4106 4107/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4108/// to an zero vector. 4109/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4110static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4111 SDValue V1 = N->getOperand(0); 4112 SDValue V2 = N->getOperand(1); 4113 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4114 for (unsigned i = 0; i != NumElems; ++i) { 4115 int Idx = N->getMaskElt(i); 4116 if (Idx >= (int)NumElems) { 4117 unsigned Opc = V2.getOpcode(); 4118 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4119 continue; 4120 if (Opc != ISD::BUILD_VECTOR || 4121 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4122 return false; 4123 } else if (Idx >= 0) { 4124 unsigned Opc = V1.getOpcode(); 4125 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4126 continue; 4127 if (Opc != ISD::BUILD_VECTOR || 4128 !X86::isZeroNode(V1.getOperand(Idx))) 4129 return false; 4130 } 4131 } 4132 return true; 4133} 4134 4135/// getZeroVector - Returns a vector of specified type with all zero elements. 4136/// 4137static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4138 SelectionDAG &DAG, DebugLoc dl) { 4139 assert(VT.isVector() && "Expected a vector type"); 4140 4141 // Always build SSE zero vectors as <4 x i32> bitcasted 4142 // to their dest type. This ensures they get CSE'd. 4143 SDValue Vec; 4144 if (VT.getSizeInBits() == 128) { // SSE 4145 if (Subtarget->hasSSE2()) { // SSE2 4146 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4148 } else { // SSE1 4149 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4151 } 4152 } else if (VT.getSizeInBits() == 256) { // AVX 4153 if (Subtarget->hasAVX2()) { // AVX2 4154 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4155 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4157 } else { 4158 // 256-bit logic and arithmetic instructions in AVX are all 4159 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4160 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4163 } 4164 } 4165 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4166} 4167 4168/// getOnesVector - Returns a vector of specified type with all bits set. 4169/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4170/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4171/// Then bitcast to their original type, ensuring they get CSE'd. 4172static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4173 DebugLoc dl) { 4174 assert(VT.isVector() && "Expected a vector type"); 4175 assert((VT.is128BitVector() || VT.is256BitVector()) 4176 && "Expected a 128-bit or 256-bit vector type"); 4177 4178 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4179 SDValue Vec; 4180 if (VT.getSizeInBits() == 256) { 4181 if (HasAVX2) { // AVX2 4182 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4183 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4184 } else { // AVX 4185 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4186 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4187 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4188 Vec = Insert128BitVector(InsV, Vec, 4189 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4190 } 4191 } else { 4192 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4193 } 4194 4195 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4196} 4197 4198/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4199/// that point to V2 points to its first element. 4200static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4201 for (unsigned i = 0; i != NumElems; ++i) { 4202 if (Mask[i] > (int)NumElems) { 4203 Mask[i] = NumElems; 4204 } 4205 } 4206} 4207 4208/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4209/// operation of specified width. 4210static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4211 SDValue V2) { 4212 unsigned NumElems = VT.getVectorNumElements(); 4213 SmallVector<int, 8> Mask; 4214 Mask.push_back(NumElems); 4215 for (unsigned i = 1; i != NumElems; ++i) 4216 Mask.push_back(i); 4217 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4218} 4219 4220/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4221static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4222 SDValue V2) { 4223 unsigned NumElems = VT.getVectorNumElements(); 4224 SmallVector<int, 8> Mask; 4225 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4226 Mask.push_back(i); 4227 Mask.push_back(i + NumElems); 4228 } 4229 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4230} 4231 4232/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4233static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4234 SDValue V2) { 4235 unsigned NumElems = VT.getVectorNumElements(); 4236 unsigned Half = NumElems/2; 4237 SmallVector<int, 8> Mask; 4238 for (unsigned i = 0; i != Half; ++i) { 4239 Mask.push_back(i + Half); 4240 Mask.push_back(i + NumElems + Half); 4241 } 4242 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4243} 4244 4245// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4246// a generic shuffle instruction because the target has no such instructions. 4247// Generate shuffles which repeat i16 and i8 several times until they can be 4248// represented by v4f32 and then be manipulated by target suported shuffles. 4249static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4250 EVT VT = V.getValueType(); 4251 int NumElems = VT.getVectorNumElements(); 4252 DebugLoc dl = V.getDebugLoc(); 4253 4254 while (NumElems > 4) { 4255 if (EltNo < NumElems/2) { 4256 V = getUnpackl(DAG, dl, VT, V, V); 4257 } else { 4258 V = getUnpackh(DAG, dl, VT, V, V); 4259 EltNo -= NumElems/2; 4260 } 4261 NumElems >>= 1; 4262 } 4263 return V; 4264} 4265 4266/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4267static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4268 EVT VT = V.getValueType(); 4269 DebugLoc dl = V.getDebugLoc(); 4270 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4271 && "Vector size not supported"); 4272 4273 if (VT.getSizeInBits() == 128) { 4274 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4275 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4276 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4277 &SplatMask[0]); 4278 } else { 4279 // To use VPERMILPS to splat scalars, the second half of indicies must 4280 // refer to the higher part, which is a duplication of the lower one, 4281 // because VPERMILPS can only handle in-lane permutations. 4282 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4283 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4284 4285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4286 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4287 &SplatMask[0]); 4288 } 4289 4290 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4291} 4292 4293/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4294static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4295 EVT SrcVT = SV->getValueType(0); 4296 SDValue V1 = SV->getOperand(0); 4297 DebugLoc dl = SV->getDebugLoc(); 4298 4299 int EltNo = SV->getSplatIndex(); 4300 int NumElems = SrcVT.getVectorNumElements(); 4301 unsigned Size = SrcVT.getSizeInBits(); 4302 4303 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4304 "Unknown how to promote splat for type"); 4305 4306 // Extract the 128-bit part containing the splat element and update 4307 // the splat element index when it refers to the higher register. 4308 if (Size == 256) { 4309 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4310 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4311 if (Idx > 0) 4312 EltNo -= NumElems/2; 4313 } 4314 4315 // All i16 and i8 vector types can't be used directly by a generic shuffle 4316 // instruction because the target has no such instruction. Generate shuffles 4317 // which repeat i16 and i8 several times until they fit in i32, and then can 4318 // be manipulated by target suported shuffles. 4319 EVT EltVT = SrcVT.getVectorElementType(); 4320 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4321 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4322 4323 // Recreate the 256-bit vector and place the same 128-bit vector 4324 // into the low and high part. This is necessary because we want 4325 // to use VPERM* to shuffle the vectors 4326 if (Size == 256) { 4327 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4328 DAG.getConstant(0, MVT::i32), DAG, dl); 4329 V1 = Insert128BitVector(InsV, V1, 4330 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4331 } 4332 4333 return getLegalSplat(DAG, V1, EltNo); 4334} 4335 4336/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4337/// vector of zero or undef vector. This produces a shuffle where the low 4338/// element of V2 is swizzled into the zero/undef vector, landing at element 4339/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4340static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4341 bool IsZero, 4342 const X86Subtarget *Subtarget, 4343 SelectionDAG &DAG) { 4344 EVT VT = V2.getValueType(); 4345 SDValue V1 = IsZero 4346 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4347 unsigned NumElems = VT.getVectorNumElements(); 4348 SmallVector<int, 16> MaskVec; 4349 for (unsigned i = 0; i != NumElems; ++i) 4350 // If this is the insertion idx, put the low elt of V2 here. 4351 MaskVec.push_back(i == Idx ? NumElems : i); 4352 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4353} 4354 4355/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4356/// target specific opcode. Returns true if the Mask could be calculated. 4357/// Sets IsUnary to true if only uses one source. 4358static bool getTargetShuffleMask(SDNode *N, EVT VT, 4359 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4360 unsigned NumElems = VT.getVectorNumElements(); 4361 SDValue ImmN; 4362 4363 IsUnary = false; 4364 switch(N->getOpcode()) { 4365 case X86ISD::SHUFP: 4366 ImmN = N->getOperand(N->getNumOperands()-1); 4367 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4368 break; 4369 case X86ISD::UNPCKH: 4370 DecodeUNPCKHMask(VT, Mask); 4371 break; 4372 case X86ISD::UNPCKL: 4373 DecodeUNPCKLMask(VT, Mask); 4374 break; 4375 case X86ISD::MOVHLPS: 4376 DecodeMOVHLPSMask(NumElems, Mask); 4377 break; 4378 case X86ISD::MOVLHPS: 4379 DecodeMOVLHPSMask(NumElems, Mask); 4380 break; 4381 case X86ISD::PSHUFD: 4382 case X86ISD::VPERMILP: 4383 ImmN = N->getOperand(N->getNumOperands()-1); 4384 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4385 IsUnary = true; 4386 break; 4387 case X86ISD::PSHUFHW: 4388 ImmN = N->getOperand(N->getNumOperands()-1); 4389 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4390 IsUnary = true; 4391 break; 4392 case X86ISD::PSHUFLW: 4393 ImmN = N->getOperand(N->getNumOperands()-1); 4394 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4395 IsUnary = true; 4396 break; 4397 case X86ISD::MOVSS: 4398 case X86ISD::MOVSD: { 4399 // The index 0 always comes from the first element of the second source, 4400 // this is why MOVSS and MOVSD are used in the first place. The other 4401 // elements come from the other positions of the first source vector 4402 Mask.push_back(NumElems); 4403 for (unsigned i = 1; i != NumElems; ++i) { 4404 Mask.push_back(i); 4405 } 4406 break; 4407 } 4408 case X86ISD::VPERM2X128: 4409 ImmN = N->getOperand(N->getNumOperands()-1); 4410 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4411 break; 4412 case X86ISD::MOVDDUP: 4413 case X86ISD::MOVLHPD: 4414 case X86ISD::MOVLPD: 4415 case X86ISD::MOVLPS: 4416 case X86ISD::MOVSHDUP: 4417 case X86ISD::MOVSLDUP: 4418 case X86ISD::PALIGN: 4419 // Not yet implemented 4420 return false; 4421 default: llvm_unreachable("unknown target shuffle node"); 4422 } 4423 4424 return true; 4425} 4426 4427/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4428/// element of the result of the vector shuffle. 4429static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4430 unsigned Depth) { 4431 if (Depth == 6) 4432 return SDValue(); // Limit search depth. 4433 4434 SDValue V = SDValue(N, 0); 4435 EVT VT = V.getValueType(); 4436 unsigned Opcode = V.getOpcode(); 4437 4438 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4439 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4440 int Elt = SV->getMaskElt(Index); 4441 4442 if (Elt < 0) 4443 return DAG.getUNDEF(VT.getVectorElementType()); 4444 4445 unsigned NumElems = VT.getVectorNumElements(); 4446 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4447 : SV->getOperand(1); 4448 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4449 } 4450 4451 // Recurse into target specific vector shuffles to find scalars. 4452 if (isTargetShuffle(Opcode)) { 4453 unsigned NumElems = VT.getVectorNumElements(); 4454 SmallVector<int, 16> ShuffleMask; 4455 SDValue ImmN; 4456 bool IsUnary; 4457 4458 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4459 return SDValue(); 4460 4461 int Elt = ShuffleMask[Index]; 4462 if (Elt < 0) 4463 return DAG.getUNDEF(VT.getVectorElementType()); 4464 4465 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4466 : N->getOperand(1); 4467 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4468 Depth+1); 4469 } 4470 4471 // Actual nodes that may contain scalar elements 4472 if (Opcode == ISD::BITCAST) { 4473 V = V.getOperand(0); 4474 EVT SrcVT = V.getValueType(); 4475 unsigned NumElems = VT.getVectorNumElements(); 4476 4477 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4478 return SDValue(); 4479 } 4480 4481 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4482 return (Index == 0) ? V.getOperand(0) 4483 : DAG.getUNDEF(VT.getVectorElementType()); 4484 4485 if (V.getOpcode() == ISD::BUILD_VECTOR) 4486 return V.getOperand(Index); 4487 4488 return SDValue(); 4489} 4490 4491/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4492/// shuffle operation which come from a consecutively from a zero. The 4493/// search can start in two different directions, from left or right. 4494static 4495unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4496 bool ZerosFromLeft, SelectionDAG &DAG) { 4497 unsigned i; 4498 for (i = 0; i != NumElems; ++i) { 4499 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4500 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4501 if (!(Elt.getNode() && 4502 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4503 break; 4504 } 4505 4506 return i; 4507} 4508 4509/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4510/// correspond consecutively to elements from one of the vector operands, 4511/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4512static 4513bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4514 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4515 unsigned NumElems, unsigned &OpNum) { 4516 bool SeenV1 = false; 4517 bool SeenV2 = false; 4518 4519 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4520 int Idx = SVOp->getMaskElt(i); 4521 // Ignore undef indicies 4522 if (Idx < 0) 4523 continue; 4524 4525 if (Idx < (int)NumElems) 4526 SeenV1 = true; 4527 else 4528 SeenV2 = true; 4529 4530 // Only accept consecutive elements from the same vector 4531 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4532 return false; 4533 } 4534 4535 OpNum = SeenV1 ? 0 : 1; 4536 return true; 4537} 4538 4539/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4540/// logical left shift of a vector. 4541static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4542 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4543 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4544 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4545 false /* check zeros from right */, DAG); 4546 unsigned OpSrc; 4547 4548 if (!NumZeros) 4549 return false; 4550 4551 // Considering the elements in the mask that are not consecutive zeros, 4552 // check if they consecutively come from only one of the source vectors. 4553 // 4554 // V1 = {X, A, B, C} 0 4555 // \ \ \ / 4556 // vector_shuffle V1, V2 <1, 2, 3, X> 4557 // 4558 if (!isShuffleMaskConsecutive(SVOp, 4559 0, // Mask Start Index 4560 NumElems-NumZeros, // Mask End Index(exclusive) 4561 NumZeros, // Where to start looking in the src vector 4562 NumElems, // Number of elements in vector 4563 OpSrc)) // Which source operand ? 4564 return false; 4565 4566 isLeft = false; 4567 ShAmt = NumZeros; 4568 ShVal = SVOp->getOperand(OpSrc); 4569 return true; 4570} 4571 4572/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4573/// logical left shift of a vector. 4574static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4575 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4576 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4577 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4578 true /* check zeros from left */, DAG); 4579 unsigned OpSrc; 4580 4581 if (!NumZeros) 4582 return false; 4583 4584 // Considering the elements in the mask that are not consecutive zeros, 4585 // check if they consecutively come from only one of the source vectors. 4586 // 4587 // 0 { A, B, X, X } = V2 4588 // / \ / / 4589 // vector_shuffle V1, V2 <X, X, 4, 5> 4590 // 4591 if (!isShuffleMaskConsecutive(SVOp, 4592 NumZeros, // Mask Start Index 4593 NumElems, // Mask End Index(exclusive) 4594 0, // Where to start looking in the src vector 4595 NumElems, // Number of elements in vector 4596 OpSrc)) // Which source operand ? 4597 return false; 4598 4599 isLeft = true; 4600 ShAmt = NumZeros; 4601 ShVal = SVOp->getOperand(OpSrc); 4602 return true; 4603} 4604 4605/// isVectorShift - Returns true if the shuffle can be implemented as a 4606/// logical left or right shift of a vector. 4607static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4609 // Although the logic below support any bitwidth size, there are no 4610 // shift instructions which handle more than 128-bit vectors. 4611 if (SVOp->getValueType(0).getSizeInBits() > 128) 4612 return false; 4613 4614 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4615 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4616 return true; 4617 4618 return false; 4619} 4620 4621/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4622/// 4623static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4624 unsigned NumNonZero, unsigned NumZero, 4625 SelectionDAG &DAG, 4626 const X86Subtarget* Subtarget, 4627 const TargetLowering &TLI) { 4628 if (NumNonZero > 8) 4629 return SDValue(); 4630 4631 DebugLoc dl = Op.getDebugLoc(); 4632 SDValue V(0, 0); 4633 bool First = true; 4634 for (unsigned i = 0; i < 16; ++i) { 4635 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4636 if (ThisIsNonZero && First) { 4637 if (NumZero) 4638 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4639 else 4640 V = DAG.getUNDEF(MVT::v8i16); 4641 First = false; 4642 } 4643 4644 if ((i & 1) != 0) { 4645 SDValue ThisElt(0, 0), LastElt(0, 0); 4646 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4647 if (LastIsNonZero) { 4648 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4649 MVT::i16, Op.getOperand(i-1)); 4650 } 4651 if (ThisIsNonZero) { 4652 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4653 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4654 ThisElt, DAG.getConstant(8, MVT::i8)); 4655 if (LastIsNonZero) 4656 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4657 } else 4658 ThisElt = LastElt; 4659 4660 if (ThisElt.getNode()) 4661 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4662 DAG.getIntPtrConstant(i/2)); 4663 } 4664 } 4665 4666 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4667} 4668 4669/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4670/// 4671static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4672 unsigned NumNonZero, unsigned NumZero, 4673 SelectionDAG &DAG, 4674 const X86Subtarget* Subtarget, 4675 const TargetLowering &TLI) { 4676 if (NumNonZero > 4) 4677 return SDValue(); 4678 4679 DebugLoc dl = Op.getDebugLoc(); 4680 SDValue V(0, 0); 4681 bool First = true; 4682 for (unsigned i = 0; i < 8; ++i) { 4683 bool isNonZero = (NonZeros & (1 << i)) != 0; 4684 if (isNonZero) { 4685 if (First) { 4686 if (NumZero) 4687 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4688 else 4689 V = DAG.getUNDEF(MVT::v8i16); 4690 First = false; 4691 } 4692 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4693 MVT::v8i16, V, Op.getOperand(i), 4694 DAG.getIntPtrConstant(i)); 4695 } 4696 } 4697 4698 return V; 4699} 4700 4701/// getVShift - Return a vector logical shift node. 4702/// 4703static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4704 unsigned NumBits, SelectionDAG &DAG, 4705 const TargetLowering &TLI, DebugLoc dl) { 4706 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4707 EVT ShVT = MVT::v2i64; 4708 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4709 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4710 return DAG.getNode(ISD::BITCAST, dl, VT, 4711 DAG.getNode(Opc, dl, ShVT, SrcOp, 4712 DAG.getConstant(NumBits, 4713 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4714} 4715 4716SDValue 4717X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4718 SelectionDAG &DAG) const { 4719 4720 // Check if the scalar load can be widened into a vector load. And if 4721 // the address is "base + cst" see if the cst can be "absorbed" into 4722 // the shuffle mask. 4723 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4724 SDValue Ptr = LD->getBasePtr(); 4725 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4726 return SDValue(); 4727 EVT PVT = LD->getValueType(0); 4728 if (PVT != MVT::i32 && PVT != MVT::f32) 4729 return SDValue(); 4730 4731 int FI = -1; 4732 int64_t Offset = 0; 4733 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4734 FI = FINode->getIndex(); 4735 Offset = 0; 4736 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4737 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4738 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4739 Offset = Ptr.getConstantOperandVal(1); 4740 Ptr = Ptr.getOperand(0); 4741 } else { 4742 return SDValue(); 4743 } 4744 4745 // FIXME: 256-bit vector instructions don't require a strict alignment, 4746 // improve this code to support it better. 4747 unsigned RequiredAlign = VT.getSizeInBits()/8; 4748 SDValue Chain = LD->getChain(); 4749 // Make sure the stack object alignment is at least 16 or 32. 4750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4751 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4752 if (MFI->isFixedObjectIndex(FI)) { 4753 // Can't change the alignment. FIXME: It's possible to compute 4754 // the exact stack offset and reference FI + adjust offset instead. 4755 // If someone *really* cares about this. That's the way to implement it. 4756 return SDValue(); 4757 } else { 4758 MFI->setObjectAlignment(FI, RequiredAlign); 4759 } 4760 } 4761 4762 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4763 // Ptr + (Offset & ~15). 4764 if (Offset < 0) 4765 return SDValue(); 4766 if ((Offset % RequiredAlign) & 3) 4767 return SDValue(); 4768 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4769 if (StartOffset) 4770 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4771 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4772 4773 int EltNo = (Offset - StartOffset) >> 2; 4774 int NumElems = VT.getVectorNumElements(); 4775 4776 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4777 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4778 LD->getPointerInfo().getWithOffset(StartOffset), 4779 false, false, false, 0); 4780 4781 SmallVector<int, 8> Mask; 4782 for (int i = 0; i < NumElems; ++i) 4783 Mask.push_back(EltNo); 4784 4785 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4786 } 4787 4788 return SDValue(); 4789} 4790 4791/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4792/// vector of type 'VT', see if the elements can be replaced by a single large 4793/// load which has the same value as a build_vector whose operands are 'elts'. 4794/// 4795/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4796/// 4797/// FIXME: we'd also like to handle the case where the last elements are zero 4798/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4799/// There's even a handy isZeroNode for that purpose. 4800static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4801 DebugLoc &DL, SelectionDAG &DAG) { 4802 EVT EltVT = VT.getVectorElementType(); 4803 unsigned NumElems = Elts.size(); 4804 4805 LoadSDNode *LDBase = NULL; 4806 unsigned LastLoadedElt = -1U; 4807 4808 // For each element in the initializer, see if we've found a load or an undef. 4809 // If we don't find an initial load element, or later load elements are 4810 // non-consecutive, bail out. 4811 for (unsigned i = 0; i < NumElems; ++i) { 4812 SDValue Elt = Elts[i]; 4813 4814 if (!Elt.getNode() || 4815 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4816 return SDValue(); 4817 if (!LDBase) { 4818 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4819 return SDValue(); 4820 LDBase = cast<LoadSDNode>(Elt.getNode()); 4821 LastLoadedElt = i; 4822 continue; 4823 } 4824 if (Elt.getOpcode() == ISD::UNDEF) 4825 continue; 4826 4827 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4828 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4829 return SDValue(); 4830 LastLoadedElt = i; 4831 } 4832 4833 // If we have found an entire vector of loads and undefs, then return a large 4834 // load of the entire vector width starting at the base pointer. If we found 4835 // consecutive loads for the low half, generate a vzext_load node. 4836 if (LastLoadedElt == NumElems - 1) { 4837 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4838 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4839 LDBase->getPointerInfo(), 4840 LDBase->isVolatile(), LDBase->isNonTemporal(), 4841 LDBase->isInvariant(), 0); 4842 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4843 LDBase->getPointerInfo(), 4844 LDBase->isVolatile(), LDBase->isNonTemporal(), 4845 LDBase->isInvariant(), LDBase->getAlignment()); 4846 } else if (NumElems == 4 && LastLoadedElt == 1 && 4847 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4848 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4849 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4850 SDValue ResNode = 4851 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4852 LDBase->getPointerInfo(), 4853 LDBase->getAlignment(), 4854 false/*isVolatile*/, true/*ReadMem*/, 4855 false/*WriteMem*/); 4856 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4857 } 4858 return SDValue(); 4859} 4860 4861/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4862/// to generate a splat value for the following cases: 4863/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4864/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4865/// a scalar load, or a constant. 4866/// The VBROADCAST node is returned when a pattern is found, 4867/// or SDValue() otherwise. 4868SDValue 4869X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4870 if (!Subtarget->hasAVX()) 4871 return SDValue(); 4872 4873 EVT VT = Op.getValueType(); 4874 DebugLoc dl = Op.getDebugLoc(); 4875 4876 SDValue Ld; 4877 bool ConstSplatVal; 4878 4879 switch (Op.getOpcode()) { 4880 default: 4881 // Unknown pattern found. 4882 return SDValue(); 4883 4884 case ISD::BUILD_VECTOR: { 4885 // The BUILD_VECTOR node must be a splat. 4886 if (!isSplatVector(Op.getNode())) 4887 return SDValue(); 4888 4889 Ld = Op.getOperand(0); 4890 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4891 Ld.getOpcode() == ISD::ConstantFP); 4892 4893 // The suspected load node has several users. Make sure that all 4894 // of its users are from the BUILD_VECTOR node. 4895 // Constants may have multiple users. 4896 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4897 return SDValue(); 4898 break; 4899 } 4900 4901 case ISD::VECTOR_SHUFFLE: { 4902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4903 4904 // Shuffles must have a splat mask where the first element is 4905 // broadcasted. 4906 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4907 return SDValue(); 4908 4909 SDValue Sc = Op.getOperand(0); 4910 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4911 return SDValue(); 4912 4913 Ld = Sc.getOperand(0); 4914 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4915 Ld.getOpcode() == ISD::ConstantFP); 4916 4917 // The scalar_to_vector node and the suspected 4918 // load node must have exactly one user. 4919 // Constants may have multiple users. 4920 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4921 return SDValue(); 4922 break; 4923 } 4924 } 4925 4926 bool Is256 = VT.getSizeInBits() == 256; 4927 bool Is128 = VT.getSizeInBits() == 128; 4928 4929 // Handle the broadcasting a single constant scalar from the constant pool 4930 // into a vector. On Sandybridge it is still better to load a constant vector 4931 // from the constant pool and not to broadcast it from a scalar. 4932 if (ConstSplatVal && Subtarget->hasAVX2()) { 4933 EVT CVT = Ld.getValueType(); 4934 assert(!CVT.isVector() && "Must not broadcast a vector type"); 4935 unsigned ScalarSize = CVT.getSizeInBits(); 4936 4937 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) || 4938 (Is128 && (ScalarSize == 32))) { 4939 4940 const Constant *C = 0; 4941 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 4942 C = CI->getConstantIntValue(); 4943 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 4944 C = CF->getConstantFPValue(); 4945 4946 assert(C && "Invalid constant type"); 4947 4948 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 4949 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 4950 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 4951 MachinePointerInfo::getConstantPool(), 4952 false, false, false, Alignment); 4953 4954 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4955 } 4956 } 4957 4958 // The scalar source must be a normal load. 4959 if (!ISD::isNormalLoad(Ld.getNode())) 4960 return SDValue(); 4961 4962 // Reject loads that have uses of the chain result 4963 if (Ld->hasAnyUseOfValue(1)) 4964 return SDValue(); 4965 4966 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4967 4968 // VBroadcast to YMM 4969 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4970 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4971 4972 // VBroadcast to XMM 4973 if (Is128 && (ScalarSize == 32)) 4974 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4975 4976 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4977 // double since there is vbroadcastsd xmm 4978 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 4979 // VBroadcast to YMM 4980 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 4981 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4982 4983 // VBroadcast to XMM 4984 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 4985 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4986 } 4987 4988 // Unsupported broadcast. 4989 return SDValue(); 4990} 4991 4992SDValue 4993X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4994 DebugLoc dl = Op.getDebugLoc(); 4995 4996 EVT VT = Op.getValueType(); 4997 EVT ExtVT = VT.getVectorElementType(); 4998 unsigned NumElems = Op.getNumOperands(); 4999 5000 // Vectors containing all zeros can be matched by pxor and xorps later 5001 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5002 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5003 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5004 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5005 return Op; 5006 5007 return getZeroVector(VT, Subtarget, DAG, dl); 5008 } 5009 5010 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5011 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5012 // vpcmpeqd on 256-bit vectors. 5013 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5014 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5015 return Op; 5016 5017 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5018 } 5019 5020 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5021 if (Broadcast.getNode()) 5022 return Broadcast; 5023 5024 unsigned EVTBits = ExtVT.getSizeInBits(); 5025 5026 unsigned NumZero = 0; 5027 unsigned NumNonZero = 0; 5028 unsigned NonZeros = 0; 5029 bool IsAllConstants = true; 5030 SmallSet<SDValue, 8> Values; 5031 for (unsigned i = 0; i < NumElems; ++i) { 5032 SDValue Elt = Op.getOperand(i); 5033 if (Elt.getOpcode() == ISD::UNDEF) 5034 continue; 5035 Values.insert(Elt); 5036 if (Elt.getOpcode() != ISD::Constant && 5037 Elt.getOpcode() != ISD::ConstantFP) 5038 IsAllConstants = false; 5039 if (X86::isZeroNode(Elt)) 5040 NumZero++; 5041 else { 5042 NonZeros |= (1 << i); 5043 NumNonZero++; 5044 } 5045 } 5046 5047 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5048 if (NumNonZero == 0) 5049 return DAG.getUNDEF(VT); 5050 5051 // Special case for single non-zero, non-undef, element. 5052 if (NumNonZero == 1) { 5053 unsigned Idx = CountTrailingZeros_32(NonZeros); 5054 SDValue Item = Op.getOperand(Idx); 5055 5056 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5057 // the value are obviously zero, truncate the value to i32 and do the 5058 // insertion that way. Only do this if the value is non-constant or if the 5059 // value is a constant being inserted into element 0. It is cheaper to do 5060 // a constant pool load than it is to do a movd + shuffle. 5061 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5062 (!IsAllConstants || Idx == 0)) { 5063 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5064 // Handle SSE only. 5065 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5066 EVT VecVT = MVT::v4i32; 5067 unsigned VecElts = 4; 5068 5069 // Truncate the value (which may itself be a constant) to i32, and 5070 // convert it to a vector with movd (S2V+shuffle to zero extend). 5071 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5072 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5073 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5074 5075 // Now we have our 32-bit value zero extended in the low element of 5076 // a vector. If Idx != 0, swizzle it into place. 5077 if (Idx != 0) { 5078 SmallVector<int, 4> Mask; 5079 Mask.push_back(Idx); 5080 for (unsigned i = 1; i != VecElts; ++i) 5081 Mask.push_back(i); 5082 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5083 DAG.getUNDEF(Item.getValueType()), 5084 &Mask[0]); 5085 } 5086 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5087 } 5088 } 5089 5090 // If we have a constant or non-constant insertion into the low element of 5091 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5092 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5093 // depending on what the source datatype is. 5094 if (Idx == 0) { 5095 if (NumZero == 0) 5096 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5097 5098 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5099 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5100 if (VT.getSizeInBits() == 256) { 5101 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5102 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5103 Item, DAG.getIntPtrConstant(0)); 5104 } 5105 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5106 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5107 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5108 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5109 } 5110 5111 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5112 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5113 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5114 if (VT.getSizeInBits() == 256) { 5115 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5116 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5117 DAG, dl); 5118 } else { 5119 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5120 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5121 } 5122 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5123 } 5124 } 5125 5126 // Is it a vector logical left shift? 5127 if (NumElems == 2 && Idx == 1 && 5128 X86::isZeroNode(Op.getOperand(0)) && 5129 !X86::isZeroNode(Op.getOperand(1))) { 5130 unsigned NumBits = VT.getSizeInBits(); 5131 return getVShift(true, VT, 5132 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5133 VT, Op.getOperand(1)), 5134 NumBits/2, DAG, *this, dl); 5135 } 5136 5137 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5138 return SDValue(); 5139 5140 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5141 // is a non-constant being inserted into an element other than the low one, 5142 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5143 // movd/movss) to move this into the low element, then shuffle it into 5144 // place. 5145 if (EVTBits == 32) { 5146 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5147 5148 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5149 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5150 SmallVector<int, 8> MaskVec; 5151 for (unsigned i = 0; i < NumElems; i++) 5152 MaskVec.push_back(i == Idx ? 0 : 1); 5153 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5154 } 5155 } 5156 5157 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5158 if (Values.size() == 1) { 5159 if (EVTBits == 32) { 5160 // Instead of a shuffle like this: 5161 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5162 // Check if it's possible to issue this instead. 5163 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5164 unsigned Idx = CountTrailingZeros_32(NonZeros); 5165 SDValue Item = Op.getOperand(Idx); 5166 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5167 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5168 } 5169 return SDValue(); 5170 } 5171 5172 // A vector full of immediates; various special cases are already 5173 // handled, so this is best done with a single constant-pool load. 5174 if (IsAllConstants) 5175 return SDValue(); 5176 5177 // For AVX-length vectors, build the individual 128-bit pieces and use 5178 // shuffles to put them in place. 5179 if (VT.getSizeInBits() == 256) { 5180 SmallVector<SDValue, 32> V; 5181 for (unsigned i = 0; i != NumElems; ++i) 5182 V.push_back(Op.getOperand(i)); 5183 5184 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5185 5186 // Build both the lower and upper subvector. 5187 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5188 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5189 NumElems/2); 5190 5191 // Recreate the wider vector with the lower and upper part. 5192 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5193 DAG.getConstant(0, MVT::i32), DAG, dl); 5194 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5195 DAG, dl); 5196 } 5197 5198 // Let legalizer expand 2-wide build_vectors. 5199 if (EVTBits == 64) { 5200 if (NumNonZero == 1) { 5201 // One half is zero or undef. 5202 unsigned Idx = CountTrailingZeros_32(NonZeros); 5203 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5204 Op.getOperand(Idx)); 5205 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5206 } 5207 return SDValue(); 5208 } 5209 5210 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5211 if (EVTBits == 8 && NumElems == 16) { 5212 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5213 Subtarget, *this); 5214 if (V.getNode()) return V; 5215 } 5216 5217 if (EVTBits == 16 && NumElems == 8) { 5218 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5219 Subtarget, *this); 5220 if (V.getNode()) return V; 5221 } 5222 5223 // If element VT is == 32 bits, turn it into a number of shuffles. 5224 SmallVector<SDValue, 8> V(NumElems); 5225 if (NumElems == 4 && NumZero > 0) { 5226 for (unsigned i = 0; i < 4; ++i) { 5227 bool isZero = !(NonZeros & (1 << i)); 5228 if (isZero) 5229 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5230 else 5231 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5232 } 5233 5234 for (unsigned i = 0; i < 2; ++i) { 5235 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5236 default: break; 5237 case 0: 5238 V[i] = V[i*2]; // Must be a zero vector. 5239 break; 5240 case 1: 5241 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5242 break; 5243 case 2: 5244 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5245 break; 5246 case 3: 5247 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5248 break; 5249 } 5250 } 5251 5252 bool Reverse1 = (NonZeros & 0x3) == 2; 5253 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5254 int MaskVec[] = { 5255 Reverse1 ? 1 : 0, 5256 Reverse1 ? 0 : 1, 5257 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5258 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5259 }; 5260 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5261 } 5262 5263 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5264 // Check for a build vector of consecutive loads. 5265 for (unsigned i = 0; i < NumElems; ++i) 5266 V[i] = Op.getOperand(i); 5267 5268 // Check for elements which are consecutive loads. 5269 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5270 if (LD.getNode()) 5271 return LD; 5272 5273 // For SSE 4.1, use insertps to put the high elements into the low element. 5274 if (getSubtarget()->hasSSE41()) { 5275 SDValue Result; 5276 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5277 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5278 else 5279 Result = DAG.getUNDEF(VT); 5280 5281 for (unsigned i = 1; i < NumElems; ++i) { 5282 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5283 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5284 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5285 } 5286 return Result; 5287 } 5288 5289 // Otherwise, expand into a number of unpckl*, start by extending each of 5290 // our (non-undef) elements to the full vector width with the element in the 5291 // bottom slot of the vector (which generates no code for SSE). 5292 for (unsigned i = 0; i < NumElems; ++i) { 5293 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5294 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5295 else 5296 V[i] = DAG.getUNDEF(VT); 5297 } 5298 5299 // Next, we iteratively mix elements, e.g. for v4f32: 5300 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5301 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5302 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5303 unsigned EltStride = NumElems >> 1; 5304 while (EltStride != 0) { 5305 for (unsigned i = 0; i < EltStride; ++i) { 5306 // If V[i+EltStride] is undef and this is the first round of mixing, 5307 // then it is safe to just drop this shuffle: V[i] is already in the 5308 // right place, the one element (since it's the first round) being 5309 // inserted as undef can be dropped. This isn't safe for successive 5310 // rounds because they will permute elements within both vectors. 5311 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5312 EltStride == NumElems/2) 5313 continue; 5314 5315 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5316 } 5317 EltStride >>= 1; 5318 } 5319 return V[0]; 5320 } 5321 return SDValue(); 5322} 5323 5324// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5325// them in a MMX register. This is better than doing a stack convert. 5326static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5327 DebugLoc dl = Op.getDebugLoc(); 5328 EVT ResVT = Op.getValueType(); 5329 5330 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5331 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5332 int Mask[2]; 5333 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5334 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5335 InVec = Op.getOperand(1); 5336 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5337 unsigned NumElts = ResVT.getVectorNumElements(); 5338 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5339 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5340 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5341 } else { 5342 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5343 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5344 Mask[0] = 0; Mask[1] = 2; 5345 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5346 } 5347 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5348} 5349 5350// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5351// to create 256-bit vectors from two other 128-bit ones. 5352static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5353 DebugLoc dl = Op.getDebugLoc(); 5354 EVT ResVT = Op.getValueType(); 5355 5356 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5357 5358 SDValue V1 = Op.getOperand(0); 5359 SDValue V2 = Op.getOperand(1); 5360 unsigned NumElems = ResVT.getVectorNumElements(); 5361 5362 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5363 DAG.getConstant(0, MVT::i32), DAG, dl); 5364 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5365 DAG, dl); 5366} 5367 5368SDValue 5369X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5370 EVT ResVT = Op.getValueType(); 5371 5372 assert(Op.getNumOperands() == 2); 5373 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5374 "Unsupported CONCAT_VECTORS for value type"); 5375 5376 // We support concatenate two MMX registers and place them in a MMX register. 5377 // This is better than doing a stack convert. 5378 if (ResVT.is128BitVector()) 5379 return LowerMMXCONCAT_VECTORS(Op, DAG); 5380 5381 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5382 // from two other 128-bit ones. 5383 return LowerAVXCONCAT_VECTORS(Op, DAG); 5384} 5385 5386// Try to lower a shuffle node into a simple blend instruction. 5387static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op, 5388 const X86Subtarget *Subtarget, 5389 SelectionDAG &DAG, EVT PtrTy) { 5390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5391 SDValue V1 = SVOp->getOperand(0); 5392 SDValue V2 = SVOp->getOperand(1); 5393 DebugLoc dl = SVOp->getDebugLoc(); 5394 LLVMContext *Context = DAG.getContext(); 5395 EVT VT = Op.getValueType(); 5396 EVT InVT = V1.getValueType(); 5397 EVT EltVT = VT.getVectorElementType(); 5398 unsigned EltSize = EltVT.getSizeInBits(); 5399 5400 int MaskSize = VT.getVectorNumElements(); 5401 int InSize = InVT.getVectorNumElements(); 5402 5403 // TODO: At the moment we only use AVX blends. We could also use SSE4 blends. 5404 if (!Subtarget->hasAVX()) 5405 return SDValue(); 5406 5407 if (MaskSize != InSize) 5408 return SDValue(); 5409 5410 SmallVector<Constant*,2> MaskVals; 5411 ConstantInt *Zero = ConstantInt::get(*Context, APInt(EltSize, 0)); 5412 ConstantInt *NegOne = ConstantInt::get(*Context, APInt(EltSize, -1)); 5413 5414 for (int i = 0; i < MaskSize; ++i) { 5415 int EltIdx = SVOp->getMaskElt(i); 5416 if (EltIdx == i || EltIdx == -1) 5417 MaskVals.push_back(NegOne); 5418 else if (EltIdx == (i + MaskSize)) 5419 MaskVals.push_back(Zero); 5420 else return SDValue(); 5421 } 5422 5423 Constant *MaskC = ConstantVector::get(MaskVals); 5424 EVT MaskTy = EVT::getEVT(MaskC->getType()); 5425 assert(MaskTy.getSizeInBits() == VT.getSizeInBits() && "Invalid mask size"); 5426 SDValue MaskIdx = DAG.getConstantPool(MaskC, PtrTy); 5427 unsigned Alignment = cast<ConstantPoolSDNode>(MaskIdx)->getAlignment(); 5428 SDValue Mask = DAG.getLoad(MaskTy, dl, DAG.getEntryNode(), MaskIdx, 5429 MachinePointerInfo::getConstantPool(), 5430 false, false, false, Alignment); 5431 5432 if (Subtarget->hasAVX2() && MaskTy == MVT::v32i8) 5433 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2); 5434 5435 if (Subtarget->hasAVX()) { 5436 switch (MaskTy.getSimpleVT().SimpleTy) { 5437 default: return SDValue(); 5438 case MVT::v16i8: 5439 case MVT::v4i32: 5440 case MVT::v2i64: 5441 case MVT::v8i32: 5442 case MVT::v4i64: 5443 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2); 5444 } 5445 } 5446 5447 return SDValue(); 5448} 5449 5450// v8i16 shuffles - Prefer shuffles in the following order: 5451// 1. [all] pshuflw, pshufhw, optional move 5452// 2. [ssse3] 1 x pshufb 5453// 3. [ssse3] 2 x pshufb + 1 x por 5454// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5455SDValue 5456X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5457 SelectionDAG &DAG) const { 5458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5459 SDValue V1 = SVOp->getOperand(0); 5460 SDValue V2 = SVOp->getOperand(1); 5461 DebugLoc dl = SVOp->getDebugLoc(); 5462 SmallVector<int, 8> MaskVals; 5463 5464 // Determine if more than 1 of the words in each of the low and high quadwords 5465 // of the result come from the same quadword of one of the two inputs. Undef 5466 // mask values count as coming from any quadword, for better codegen. 5467 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5468 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5469 std::bitset<4> InputQuads; 5470 for (unsigned i = 0; i < 8; ++i) { 5471 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5472 int EltIdx = SVOp->getMaskElt(i); 5473 MaskVals.push_back(EltIdx); 5474 if (EltIdx < 0) { 5475 ++Quad[0]; 5476 ++Quad[1]; 5477 ++Quad[2]; 5478 ++Quad[3]; 5479 continue; 5480 } 5481 ++Quad[EltIdx / 4]; 5482 InputQuads.set(EltIdx / 4); 5483 } 5484 5485 int BestLoQuad = -1; 5486 unsigned MaxQuad = 1; 5487 for (unsigned i = 0; i < 4; ++i) { 5488 if (LoQuad[i] > MaxQuad) { 5489 BestLoQuad = i; 5490 MaxQuad = LoQuad[i]; 5491 } 5492 } 5493 5494 int BestHiQuad = -1; 5495 MaxQuad = 1; 5496 for (unsigned i = 0; i < 4; ++i) { 5497 if (HiQuad[i] > MaxQuad) { 5498 BestHiQuad = i; 5499 MaxQuad = HiQuad[i]; 5500 } 5501 } 5502 5503 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5504 // of the two input vectors, shuffle them into one input vector so only a 5505 // single pshufb instruction is necessary. If There are more than 2 input 5506 // quads, disable the next transformation since it does not help SSSE3. 5507 bool V1Used = InputQuads[0] || InputQuads[1]; 5508 bool V2Used = InputQuads[2] || InputQuads[3]; 5509 if (Subtarget->hasSSSE3()) { 5510 if (InputQuads.count() == 2 && V1Used && V2Used) { 5511 BestLoQuad = InputQuads[0] ? 0 : 1; 5512 BestHiQuad = InputQuads[2] ? 2 : 3; 5513 } 5514 if (InputQuads.count() > 2) { 5515 BestLoQuad = -1; 5516 BestHiQuad = -1; 5517 } 5518 } 5519 5520 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5521 // the shuffle mask. If a quad is scored as -1, that means that it contains 5522 // words from all 4 input quadwords. 5523 SDValue NewV; 5524 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5525 int MaskV[] = { 5526 BestLoQuad < 0 ? 0 : BestLoQuad, 5527 BestHiQuad < 0 ? 1 : BestHiQuad 5528 }; 5529 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5530 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5531 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5532 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5533 5534 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5535 // source words for the shuffle, to aid later transformations. 5536 bool AllWordsInNewV = true; 5537 bool InOrder[2] = { true, true }; 5538 for (unsigned i = 0; i != 8; ++i) { 5539 int idx = MaskVals[i]; 5540 if (idx != (int)i) 5541 InOrder[i/4] = false; 5542 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5543 continue; 5544 AllWordsInNewV = false; 5545 break; 5546 } 5547 5548 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5549 if (AllWordsInNewV) { 5550 for (int i = 0; i != 8; ++i) { 5551 int idx = MaskVals[i]; 5552 if (idx < 0) 5553 continue; 5554 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5555 if ((idx != i) && idx < 4) 5556 pshufhw = false; 5557 if ((idx != i) && idx > 3) 5558 pshuflw = false; 5559 } 5560 V1 = NewV; 5561 V2Used = false; 5562 BestLoQuad = 0; 5563 BestHiQuad = 1; 5564 } 5565 5566 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5567 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5568 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5569 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5570 unsigned TargetMask = 0; 5571 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5572 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5574 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5575 getShufflePSHUFLWImmediate(SVOp); 5576 V1 = NewV.getOperand(0); 5577 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5578 } 5579 } 5580 5581 // If we have SSSE3, and all words of the result are from 1 input vector, 5582 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5583 // is present, fall back to case 4. 5584 if (Subtarget->hasSSSE3()) { 5585 SmallVector<SDValue,16> pshufbMask; 5586 5587 // If we have elements from both input vectors, set the high bit of the 5588 // shuffle mask element to zero out elements that come from V2 in the V1 5589 // mask, and elements that come from V1 in the V2 mask, so that the two 5590 // results can be OR'd together. 5591 bool TwoInputs = V1Used && V2Used; 5592 for (unsigned i = 0; i != 8; ++i) { 5593 int EltIdx = MaskVals[i] * 2; 5594 if (TwoInputs && (EltIdx >= 16)) { 5595 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5596 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5597 continue; 5598 } 5599 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5600 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5601 } 5602 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5603 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5604 DAG.getNode(ISD::BUILD_VECTOR, dl, 5605 MVT::v16i8, &pshufbMask[0], 16)); 5606 if (!TwoInputs) 5607 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5608 5609 // Calculate the shuffle mask for the second input, shuffle it, and 5610 // OR it with the first shuffled input. 5611 pshufbMask.clear(); 5612 for (unsigned i = 0; i != 8; ++i) { 5613 int EltIdx = MaskVals[i] * 2; 5614 if (EltIdx < 16) { 5615 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5617 continue; 5618 } 5619 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5620 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5621 } 5622 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5623 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5624 DAG.getNode(ISD::BUILD_VECTOR, dl, 5625 MVT::v16i8, &pshufbMask[0], 16)); 5626 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5627 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5628 } 5629 5630 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5631 // and update MaskVals with new element order. 5632 std::bitset<8> InOrder; 5633 if (BestLoQuad >= 0) { 5634 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5635 for (int i = 0; i != 4; ++i) { 5636 int idx = MaskVals[i]; 5637 if (idx < 0) { 5638 InOrder.set(i); 5639 } else if ((idx / 4) == BestLoQuad) { 5640 MaskV[i] = idx & 3; 5641 InOrder.set(i); 5642 } 5643 } 5644 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5645 &MaskV[0]); 5646 5647 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5649 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5650 NewV.getOperand(0), 5651 getShufflePSHUFLWImmediate(SVOp), DAG); 5652 } 5653 } 5654 5655 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5656 // and update MaskVals with the new element order. 5657 if (BestHiQuad >= 0) { 5658 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5659 for (unsigned i = 4; i != 8; ++i) { 5660 int idx = MaskVals[i]; 5661 if (idx < 0) { 5662 InOrder.set(i); 5663 } else if ((idx / 4) == BestHiQuad) { 5664 MaskV[i] = (idx & 3) + 4; 5665 InOrder.set(i); 5666 } 5667 } 5668 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5669 &MaskV[0]); 5670 5671 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5673 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5674 NewV.getOperand(0), 5675 getShufflePSHUFHWImmediate(SVOp), DAG); 5676 } 5677 } 5678 5679 // In case BestHi & BestLo were both -1, which means each quadword has a word 5680 // from each of the four input quadwords, calculate the InOrder bitvector now 5681 // before falling through to the insert/extract cleanup. 5682 if (BestLoQuad == -1 && BestHiQuad == -1) { 5683 NewV = V1; 5684 for (int i = 0; i != 8; ++i) 5685 if (MaskVals[i] < 0 || MaskVals[i] == i) 5686 InOrder.set(i); 5687 } 5688 5689 // The other elements are put in the right place using pextrw and pinsrw. 5690 for (unsigned i = 0; i != 8; ++i) { 5691 if (InOrder[i]) 5692 continue; 5693 int EltIdx = MaskVals[i]; 5694 if (EltIdx < 0) 5695 continue; 5696 SDValue ExtOp = (EltIdx < 8) 5697 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5698 DAG.getIntPtrConstant(EltIdx)) 5699 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5700 DAG.getIntPtrConstant(EltIdx - 8)); 5701 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5702 DAG.getIntPtrConstant(i)); 5703 } 5704 return NewV; 5705} 5706 5707// v16i8 shuffles - Prefer shuffles in the following order: 5708// 1. [ssse3] 1 x pshufb 5709// 2. [ssse3] 2 x pshufb + 1 x por 5710// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5711static 5712SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5713 SelectionDAG &DAG, 5714 const X86TargetLowering &TLI) { 5715 SDValue V1 = SVOp->getOperand(0); 5716 SDValue V2 = SVOp->getOperand(1); 5717 DebugLoc dl = SVOp->getDebugLoc(); 5718 ArrayRef<int> MaskVals = SVOp->getMask(); 5719 5720 // If we have SSSE3, case 1 is generated when all result bytes come from 5721 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5722 // present, fall back to case 3. 5723 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5724 bool V1Only = true; 5725 bool V2Only = true; 5726 for (unsigned i = 0; i < 16; ++i) { 5727 int EltIdx = MaskVals[i]; 5728 if (EltIdx < 0) 5729 continue; 5730 if (EltIdx < 16) 5731 V2Only = false; 5732 else 5733 V1Only = false; 5734 } 5735 5736 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5737 if (TLI.getSubtarget()->hasSSSE3()) { 5738 SmallVector<SDValue,16> pshufbMask; 5739 5740 // If all result elements are from one input vector, then only translate 5741 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5742 // 5743 // Otherwise, we have elements from both input vectors, and must zero out 5744 // elements that come from V2 in the first mask, and V1 in the second mask 5745 // so that we can OR them together. 5746 bool TwoInputs = !(V1Only || V2Only); 5747 for (unsigned i = 0; i != 16; ++i) { 5748 int EltIdx = MaskVals[i]; 5749 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5750 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5751 continue; 5752 } 5753 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5754 } 5755 // If all the elements are from V2, assign it to V1 and return after 5756 // building the first pshufb. 5757 if (V2Only) 5758 V1 = V2; 5759 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5760 DAG.getNode(ISD::BUILD_VECTOR, dl, 5761 MVT::v16i8, &pshufbMask[0], 16)); 5762 if (!TwoInputs) 5763 return V1; 5764 5765 // Calculate the shuffle mask for the second input, shuffle it, and 5766 // OR it with the first shuffled input. 5767 pshufbMask.clear(); 5768 for (unsigned i = 0; i != 16; ++i) { 5769 int EltIdx = MaskVals[i]; 5770 if (EltIdx < 16) { 5771 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5772 continue; 5773 } 5774 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5775 } 5776 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5777 DAG.getNode(ISD::BUILD_VECTOR, dl, 5778 MVT::v16i8, &pshufbMask[0], 16)); 5779 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5780 } 5781 5782 // No SSSE3 - Calculate in place words and then fix all out of place words 5783 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5784 // the 16 different words that comprise the two doublequadword input vectors. 5785 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5786 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5787 SDValue NewV = V2Only ? V2 : V1; 5788 for (int i = 0; i != 8; ++i) { 5789 int Elt0 = MaskVals[i*2]; 5790 int Elt1 = MaskVals[i*2+1]; 5791 5792 // This word of the result is all undef, skip it. 5793 if (Elt0 < 0 && Elt1 < 0) 5794 continue; 5795 5796 // This word of the result is already in the correct place, skip it. 5797 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5798 continue; 5799 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5800 continue; 5801 5802 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5803 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5804 SDValue InsElt; 5805 5806 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5807 // using a single extract together, load it and store it. 5808 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5809 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5810 DAG.getIntPtrConstant(Elt1 / 2)); 5811 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5812 DAG.getIntPtrConstant(i)); 5813 continue; 5814 } 5815 5816 // If Elt1 is defined, extract it from the appropriate source. If the 5817 // source byte is not also odd, shift the extracted word left 8 bits 5818 // otherwise clear the bottom 8 bits if we need to do an or. 5819 if (Elt1 >= 0) { 5820 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5821 DAG.getIntPtrConstant(Elt1 / 2)); 5822 if ((Elt1 & 1) == 0) 5823 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5824 DAG.getConstant(8, 5825 TLI.getShiftAmountTy(InsElt.getValueType()))); 5826 else if (Elt0 >= 0) 5827 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5828 DAG.getConstant(0xFF00, MVT::i16)); 5829 } 5830 // If Elt0 is defined, extract it from the appropriate source. If the 5831 // source byte is not also even, shift the extracted word right 8 bits. If 5832 // Elt1 was also defined, OR the extracted values together before 5833 // inserting them in the result. 5834 if (Elt0 >= 0) { 5835 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5836 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5837 if ((Elt0 & 1) != 0) 5838 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5839 DAG.getConstant(8, 5840 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5841 else if (Elt1 >= 0) 5842 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5843 DAG.getConstant(0x00FF, MVT::i16)); 5844 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5845 : InsElt0; 5846 } 5847 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5848 DAG.getIntPtrConstant(i)); 5849 } 5850 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5851} 5852 5853/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5854/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5855/// done when every pair / quad of shuffle mask elements point to elements in 5856/// the right sequence. e.g. 5857/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5858static 5859SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5860 SelectionDAG &DAG, DebugLoc dl) { 5861 EVT VT = SVOp->getValueType(0); 5862 SDValue V1 = SVOp->getOperand(0); 5863 SDValue V2 = SVOp->getOperand(1); 5864 unsigned NumElems = VT.getVectorNumElements(); 5865 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5866 EVT NewVT; 5867 switch (VT.getSimpleVT().SimpleTy) { 5868 default: llvm_unreachable("Unexpected!"); 5869 case MVT::v4f32: NewVT = MVT::v2f64; break; 5870 case MVT::v4i32: NewVT = MVT::v2i64; break; 5871 case MVT::v8i16: NewVT = MVT::v4i32; break; 5872 case MVT::v16i8: NewVT = MVT::v4i32; break; 5873 } 5874 5875 int Scale = NumElems / NewWidth; 5876 SmallVector<int, 8> MaskVec; 5877 for (unsigned i = 0; i < NumElems; i += Scale) { 5878 int StartIdx = -1; 5879 for (int j = 0; j < Scale; ++j) { 5880 int EltIdx = SVOp->getMaskElt(i+j); 5881 if (EltIdx < 0) 5882 continue; 5883 if (StartIdx == -1) 5884 StartIdx = EltIdx - (EltIdx % Scale); 5885 if (EltIdx != StartIdx + j) 5886 return SDValue(); 5887 } 5888 if (StartIdx == -1) 5889 MaskVec.push_back(-1); 5890 else 5891 MaskVec.push_back(StartIdx / Scale); 5892 } 5893 5894 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5895 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5896 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5897} 5898 5899/// getVZextMovL - Return a zero-extending vector move low node. 5900/// 5901static SDValue getVZextMovL(EVT VT, EVT OpVT, 5902 SDValue SrcOp, SelectionDAG &DAG, 5903 const X86Subtarget *Subtarget, DebugLoc dl) { 5904 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5905 LoadSDNode *LD = NULL; 5906 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5907 LD = dyn_cast<LoadSDNode>(SrcOp); 5908 if (!LD) { 5909 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5910 // instead. 5911 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5912 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5913 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5914 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5915 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5916 // PR2108 5917 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5918 return DAG.getNode(ISD::BITCAST, dl, VT, 5919 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5920 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5921 OpVT, 5922 SrcOp.getOperand(0) 5923 .getOperand(0)))); 5924 } 5925 } 5926 } 5927 5928 return DAG.getNode(ISD::BITCAST, dl, VT, 5929 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5930 DAG.getNode(ISD::BITCAST, dl, 5931 OpVT, SrcOp))); 5932} 5933 5934/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5935/// which could not be matched by any known target speficic shuffle 5936static SDValue 5937LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5938 EVT VT = SVOp->getValueType(0); 5939 5940 unsigned NumElems = VT.getVectorNumElements(); 5941 unsigned NumLaneElems = NumElems / 2; 5942 5943 DebugLoc dl = SVOp->getDebugLoc(); 5944 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5945 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5946 SDValue Shufs[2]; 5947 5948 SmallVector<int, 16> Mask; 5949 for (unsigned l = 0; l < 2; ++l) { 5950 // Build a shuffle mask for the output, discovering on the fly which 5951 // input vectors to use as shuffle operands (recorded in InputUsed). 5952 // If building a suitable shuffle vector proves too hard, then bail 5953 // out with useBuildVector set. 5954 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 5955 unsigned LaneStart = l * NumLaneElems; 5956 for (unsigned i = 0; i != NumLaneElems; ++i) { 5957 // The mask element. This indexes into the input. 5958 int Idx = SVOp->getMaskElt(i+LaneStart); 5959 if (Idx < 0) { 5960 // the mask element does not index into any input vector. 5961 Mask.push_back(-1); 5962 continue; 5963 } 5964 5965 // The input vector this mask element indexes into. 5966 int Input = Idx / NumLaneElems; 5967 5968 // Turn the index into an offset from the start of the input vector. 5969 Idx -= Input * NumLaneElems; 5970 5971 // Find or create a shuffle vector operand to hold this input. 5972 unsigned OpNo; 5973 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 5974 if (InputUsed[OpNo] == Input) 5975 // This input vector is already an operand. 5976 break; 5977 if (InputUsed[OpNo] < 0) { 5978 // Create a new operand for this input vector. 5979 InputUsed[OpNo] = Input; 5980 break; 5981 } 5982 } 5983 5984 if (OpNo >= array_lengthof(InputUsed)) { 5985 // More than two input vectors used! Give up. 5986 return SDValue(); 5987 } 5988 5989 // Add the mask index for the new shuffle vector. 5990 Mask.push_back(Idx + OpNo * NumLaneElems); 5991 } 5992 5993 if (InputUsed[0] < 0) { 5994 // No input vectors were used! The result is undefined. 5995 Shufs[l] = DAG.getUNDEF(NVT); 5996 } else { 5997 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 5998 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32), 5999 DAG, dl); 6000 // If only one input was used, use an undefined vector for the other. 6001 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6002 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6003 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32), 6004 DAG, dl); 6005 // At least one input vector was used. Create a new shuffle vector. 6006 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6007 } 6008 6009 Mask.clear(); 6010 } 6011 6012 // Concatenate the result back 6013 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0], 6014 DAG.getConstant(0, MVT::i32), DAG, dl); 6015 return Insert128BitVector(V, Shufs[1],DAG.getConstant(NumLaneElems, MVT::i32), 6016 DAG, dl); 6017} 6018 6019/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6020/// 4 elements, and match them with several different shuffle types. 6021static SDValue 6022LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6023 SDValue V1 = SVOp->getOperand(0); 6024 SDValue V2 = SVOp->getOperand(1); 6025 DebugLoc dl = SVOp->getDebugLoc(); 6026 EVT VT = SVOp->getValueType(0); 6027 6028 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6029 6030 std::pair<int, int> Locs[4]; 6031 int Mask1[] = { -1, -1, -1, -1 }; 6032 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6033 6034 unsigned NumHi = 0; 6035 unsigned NumLo = 0; 6036 for (unsigned i = 0; i != 4; ++i) { 6037 int Idx = PermMask[i]; 6038 if (Idx < 0) { 6039 Locs[i] = std::make_pair(-1, -1); 6040 } else { 6041 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6042 if (Idx < 4) { 6043 Locs[i] = std::make_pair(0, NumLo); 6044 Mask1[NumLo] = Idx; 6045 NumLo++; 6046 } else { 6047 Locs[i] = std::make_pair(1, NumHi); 6048 if (2+NumHi < 4) 6049 Mask1[2+NumHi] = Idx; 6050 NumHi++; 6051 } 6052 } 6053 } 6054 6055 if (NumLo <= 2 && NumHi <= 2) { 6056 // If no more than two elements come from either vector. This can be 6057 // implemented with two shuffles. First shuffle gather the elements. 6058 // The second shuffle, which takes the first shuffle as both of its 6059 // vector operands, put the elements into the right order. 6060 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6061 6062 int Mask2[] = { -1, -1, -1, -1 }; 6063 6064 for (unsigned i = 0; i != 4; ++i) 6065 if (Locs[i].first != -1) { 6066 unsigned Idx = (i < 2) ? 0 : 4; 6067 Idx += Locs[i].first * 2 + Locs[i].second; 6068 Mask2[i] = Idx; 6069 } 6070 6071 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6072 } else if (NumLo == 3 || NumHi == 3) { 6073 // Otherwise, we must have three elements from one vector, call it X, and 6074 // one element from the other, call it Y. First, use a shufps to build an 6075 // intermediate vector with the one element from Y and the element from X 6076 // that will be in the same half in the final destination (the indexes don't 6077 // matter). Then, use a shufps to build the final vector, taking the half 6078 // containing the element from Y from the intermediate, and the other half 6079 // from X. 6080 if (NumHi == 3) { 6081 // Normalize it so the 3 elements come from V1. 6082 CommuteVectorShuffleMask(PermMask, 4); 6083 std::swap(V1, V2); 6084 } 6085 6086 // Find the element from V2. 6087 unsigned HiIndex; 6088 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6089 int Val = PermMask[HiIndex]; 6090 if (Val < 0) 6091 continue; 6092 if (Val >= 4) 6093 break; 6094 } 6095 6096 Mask1[0] = PermMask[HiIndex]; 6097 Mask1[1] = -1; 6098 Mask1[2] = PermMask[HiIndex^1]; 6099 Mask1[3] = -1; 6100 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6101 6102 if (HiIndex >= 2) { 6103 Mask1[0] = PermMask[0]; 6104 Mask1[1] = PermMask[1]; 6105 Mask1[2] = HiIndex & 1 ? 6 : 4; 6106 Mask1[3] = HiIndex & 1 ? 4 : 6; 6107 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6108 } else { 6109 Mask1[0] = HiIndex & 1 ? 2 : 0; 6110 Mask1[1] = HiIndex & 1 ? 0 : 2; 6111 Mask1[2] = PermMask[2]; 6112 Mask1[3] = PermMask[3]; 6113 if (Mask1[2] >= 0) 6114 Mask1[2] += 4; 6115 if (Mask1[3] >= 0) 6116 Mask1[3] += 4; 6117 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6118 } 6119 } 6120 6121 // Break it into (shuffle shuffle_hi, shuffle_lo). 6122 int LoMask[] = { -1, -1, -1, -1 }; 6123 int HiMask[] = { -1, -1, -1, -1 }; 6124 6125 int *MaskPtr = LoMask; 6126 unsigned MaskIdx = 0; 6127 unsigned LoIdx = 0; 6128 unsigned HiIdx = 2; 6129 for (unsigned i = 0; i != 4; ++i) { 6130 if (i == 2) { 6131 MaskPtr = HiMask; 6132 MaskIdx = 1; 6133 LoIdx = 0; 6134 HiIdx = 2; 6135 } 6136 int Idx = PermMask[i]; 6137 if (Idx < 0) { 6138 Locs[i] = std::make_pair(-1, -1); 6139 } else if (Idx < 4) { 6140 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6141 MaskPtr[LoIdx] = Idx; 6142 LoIdx++; 6143 } else { 6144 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6145 MaskPtr[HiIdx] = Idx; 6146 HiIdx++; 6147 } 6148 } 6149 6150 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6151 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6152 int MaskOps[] = { -1, -1, -1, -1 }; 6153 for (unsigned i = 0; i != 4; ++i) 6154 if (Locs[i].first != -1) 6155 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6156 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6157} 6158 6159static bool MayFoldVectorLoad(SDValue V) { 6160 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6161 V = V.getOperand(0); 6162 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6163 V = V.getOperand(0); 6164 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6165 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6166 // BUILD_VECTOR (load), undef 6167 V = V.getOperand(0); 6168 if (MayFoldLoad(V)) 6169 return true; 6170 return false; 6171} 6172 6173// FIXME: the version above should always be used. Since there's 6174// a bug where several vector shuffles can't be folded because the 6175// DAG is not updated during lowering and a node claims to have two 6176// uses while it only has one, use this version, and let isel match 6177// another instruction if the load really happens to have more than 6178// one use. Remove this version after this bug get fixed. 6179// rdar://8434668, PR8156 6180static bool RelaxedMayFoldVectorLoad(SDValue V) { 6181 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6182 V = V.getOperand(0); 6183 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6184 V = V.getOperand(0); 6185 if (ISD::isNormalLoad(V.getNode())) 6186 return true; 6187 return false; 6188} 6189 6190static 6191SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6192 EVT VT = Op.getValueType(); 6193 6194 // Canonizalize to v2f64. 6195 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6196 return DAG.getNode(ISD::BITCAST, dl, VT, 6197 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6198 V1, DAG)); 6199} 6200 6201static 6202SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6203 bool HasSSE2) { 6204 SDValue V1 = Op.getOperand(0); 6205 SDValue V2 = Op.getOperand(1); 6206 EVT VT = Op.getValueType(); 6207 6208 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6209 6210 if (HasSSE2 && VT == MVT::v2f64) 6211 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6212 6213 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6214 return DAG.getNode(ISD::BITCAST, dl, VT, 6215 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6216 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6217 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6218} 6219 6220static 6221SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6222 SDValue V1 = Op.getOperand(0); 6223 SDValue V2 = Op.getOperand(1); 6224 EVT VT = Op.getValueType(); 6225 6226 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6227 "unsupported shuffle type"); 6228 6229 if (V2.getOpcode() == ISD::UNDEF) 6230 V2 = V1; 6231 6232 // v4i32 or v4f32 6233 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6234} 6235 6236static 6237SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6238 SDValue V1 = Op.getOperand(0); 6239 SDValue V2 = Op.getOperand(1); 6240 EVT VT = Op.getValueType(); 6241 unsigned NumElems = VT.getVectorNumElements(); 6242 6243 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6244 // operand of these instructions is only memory, so check if there's a 6245 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6246 // same masks. 6247 bool CanFoldLoad = false; 6248 6249 // Trivial case, when V2 comes from a load. 6250 if (MayFoldVectorLoad(V2)) 6251 CanFoldLoad = true; 6252 6253 // When V1 is a load, it can be folded later into a store in isel, example: 6254 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6255 // turns into: 6256 // (MOVLPSmr addr:$src1, VR128:$src2) 6257 // So, recognize this potential and also use MOVLPS or MOVLPD 6258 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6259 CanFoldLoad = true; 6260 6261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6262 if (CanFoldLoad) { 6263 if (HasSSE2 && NumElems == 2) 6264 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6265 6266 if (NumElems == 4) 6267 // If we don't care about the second element, procede to use movss. 6268 if (SVOp->getMaskElt(1) != -1) 6269 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6270 } 6271 6272 // movl and movlp will both match v2i64, but v2i64 is never matched by 6273 // movl earlier because we make it strict to avoid messing with the movlp load 6274 // folding logic (see the code above getMOVLP call). Match it here then, 6275 // this is horrible, but will stay like this until we move all shuffle 6276 // matching to x86 specific nodes. Note that for the 1st condition all 6277 // types are matched with movsd. 6278 if (HasSSE2) { 6279 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6280 // as to remove this logic from here, as much as possible 6281 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6282 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6283 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6284 } 6285 6286 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6287 6288 // Invert the operand order and use SHUFPS to match it. 6289 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6290 getShuffleSHUFImmediate(SVOp), DAG); 6291} 6292 6293SDValue 6294X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6296 EVT VT = Op.getValueType(); 6297 DebugLoc dl = Op.getDebugLoc(); 6298 SDValue V1 = Op.getOperand(0); 6299 SDValue V2 = Op.getOperand(1); 6300 6301 if (isZeroShuffle(SVOp)) 6302 return getZeroVector(VT, Subtarget, DAG, dl); 6303 6304 // Handle splat operations 6305 if (SVOp->isSplat()) { 6306 unsigned NumElem = VT.getVectorNumElements(); 6307 int Size = VT.getSizeInBits(); 6308 6309 // Use vbroadcast whenever the splat comes from a foldable load 6310 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6311 if (Broadcast.getNode()) 6312 return Broadcast; 6313 6314 // Handle splats by matching through known shuffle masks 6315 if ((Size == 128 && NumElem <= 4) || 6316 (Size == 256 && NumElem < 8)) 6317 return SDValue(); 6318 6319 // All remaning splats are promoted to target supported vector shuffles. 6320 return PromoteSplat(SVOp, DAG); 6321 } 6322 6323 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6324 // do it! 6325 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6326 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6327 if (NewOp.getNode()) 6328 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6329 } else if ((VT == MVT::v4i32 || 6330 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6331 // FIXME: Figure out a cleaner way to do this. 6332 // Try to make use of movq to zero out the top part. 6333 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6334 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6335 if (NewOp.getNode()) { 6336 EVT NewVT = NewOp.getValueType(); 6337 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6338 NewVT, true, false)) 6339 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6340 DAG, Subtarget, dl); 6341 } 6342 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6343 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6344 if (NewOp.getNode()) { 6345 EVT NewVT = NewOp.getValueType(); 6346 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6347 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6348 DAG, Subtarget, dl); 6349 } 6350 } 6351 } 6352 return SDValue(); 6353} 6354 6355SDValue 6356X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6357 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6358 SDValue V1 = Op.getOperand(0); 6359 SDValue V2 = Op.getOperand(1); 6360 EVT VT = Op.getValueType(); 6361 DebugLoc dl = Op.getDebugLoc(); 6362 unsigned NumElems = VT.getVectorNumElements(); 6363 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6364 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6365 bool V1IsSplat = false; 6366 bool V2IsSplat = false; 6367 bool HasSSE2 = Subtarget->hasSSE2(); 6368 bool HasAVX = Subtarget->hasAVX(); 6369 bool HasAVX2 = Subtarget->hasAVX2(); 6370 MachineFunction &MF = DAG.getMachineFunction(); 6371 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6372 6373 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6374 6375 if (V1IsUndef && V2IsUndef) 6376 return DAG.getUNDEF(VT); 6377 6378 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6379 6380 // Vector shuffle lowering takes 3 steps: 6381 // 6382 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6383 // narrowing and commutation of operands should be handled. 6384 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6385 // shuffle nodes. 6386 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6387 // so the shuffle can be broken into other shuffles and the legalizer can 6388 // try the lowering again. 6389 // 6390 // The general idea is that no vector_shuffle operation should be left to 6391 // be matched during isel, all of them must be converted to a target specific 6392 // node here. 6393 6394 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6395 // narrowing and commutation of operands should be handled. The actual code 6396 // doesn't include all of those, work in progress... 6397 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6398 if (NewOp.getNode()) 6399 return NewOp; 6400 6401 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6402 6403 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6404 // unpckh_undef). Only use pshufd if speed is more important than size. 6405 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6406 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6407 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6408 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6409 6410 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6411 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6412 return getMOVDDup(Op, dl, V1, DAG); 6413 6414 if (isMOVHLPS_v_undef_Mask(M, VT)) 6415 return getMOVHighToLow(Op, dl, DAG); 6416 6417 // Use to match splats 6418 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6419 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6420 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6421 6422 if (isPSHUFDMask(M, VT)) { 6423 // The actual implementation will match the mask in the if above and then 6424 // during isel it can match several different instructions, not only pshufd 6425 // as its name says, sad but true, emulate the behavior for now... 6426 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6427 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6428 6429 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6430 6431 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6432 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6433 6434 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6435 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6436 6437 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6438 TargetMask, DAG); 6439 } 6440 6441 // Check if this can be converted into a logical shift. 6442 bool isLeft = false; 6443 unsigned ShAmt = 0; 6444 SDValue ShVal; 6445 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6446 if (isShift && ShVal.hasOneUse()) { 6447 // If the shifted value has multiple uses, it may be cheaper to use 6448 // v_set0 + movlhps or movhlps, etc. 6449 EVT EltVT = VT.getVectorElementType(); 6450 ShAmt *= EltVT.getSizeInBits(); 6451 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6452 } 6453 6454 if (isMOVLMask(M, VT)) { 6455 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6456 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6457 if (!isMOVLPMask(M, VT)) { 6458 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6459 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6460 6461 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6462 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6463 } 6464 } 6465 6466 // FIXME: fold these into legal mask. 6467 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6468 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6469 6470 if (isMOVHLPSMask(M, VT)) 6471 return getMOVHighToLow(Op, dl, DAG); 6472 6473 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6474 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6475 6476 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6477 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6478 6479 if (isMOVLPMask(M, VT)) 6480 return getMOVLP(Op, dl, DAG, HasSSE2); 6481 6482 if (ShouldXformToMOVHLPS(M, VT) || 6483 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6484 return CommuteVectorShuffle(SVOp, DAG); 6485 6486 if (isShift) { 6487 // No better options. Use a vshldq / vsrldq. 6488 EVT EltVT = VT.getVectorElementType(); 6489 ShAmt *= EltVT.getSizeInBits(); 6490 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6491 } 6492 6493 bool Commuted = false; 6494 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6495 // 1,1,1,1 -> v8i16 though. 6496 V1IsSplat = isSplatVector(V1.getNode()); 6497 V2IsSplat = isSplatVector(V2.getNode()); 6498 6499 // Canonicalize the splat or undef, if present, to be on the RHS. 6500 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6501 CommuteVectorShuffleMask(M, NumElems); 6502 std::swap(V1, V2); 6503 std::swap(V1IsSplat, V2IsSplat); 6504 Commuted = true; 6505 } 6506 6507 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6508 // Shuffling low element of v1 into undef, just return v1. 6509 if (V2IsUndef) 6510 return V1; 6511 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6512 // the instruction selector will not match, so get a canonical MOVL with 6513 // swapped operands to undo the commute. 6514 return getMOVL(DAG, dl, VT, V2, V1); 6515 } 6516 6517 if (isUNPCKLMask(M, VT, HasAVX2)) 6518 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6519 6520 if (isUNPCKHMask(M, VT, HasAVX2)) 6521 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6522 6523 if (V2IsSplat) { 6524 // Normalize mask so all entries that point to V2 points to its first 6525 // element then try to match unpck{h|l} again. If match, return a 6526 // new vector_shuffle with the corrected mask.p 6527 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6528 NormalizeMask(NewMask, NumElems); 6529 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) { 6530 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6531 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) { 6532 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6533 } 6534 } 6535 6536 if (Commuted) { 6537 // Commute is back and try unpck* again. 6538 // FIXME: this seems wrong. 6539 CommuteVectorShuffleMask(M, NumElems); 6540 std::swap(V1, V2); 6541 std::swap(V1IsSplat, V2IsSplat); 6542 Commuted = false; 6543 6544 if (isUNPCKLMask(M, VT, HasAVX2)) 6545 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6546 6547 if (isUNPCKHMask(M, VT, HasAVX2)) 6548 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6549 } 6550 6551 // Normalize the node to match x86 shuffle ops if needed 6552 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6553 return CommuteVectorShuffle(SVOp, DAG); 6554 6555 // The checks below are all present in isShuffleMaskLegal, but they are 6556 // inlined here right now to enable us to directly emit target specific 6557 // nodes, and remove one by one until they don't return Op anymore. 6558 6559 if (isPALIGNRMask(M, VT, Subtarget)) 6560 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6561 getShufflePALIGNRImmediate(SVOp), 6562 DAG); 6563 6564 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6565 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6566 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6568 } 6569 6570 if (isPSHUFHWMask(M, VT)) 6571 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6572 getShufflePSHUFHWImmediate(SVOp), 6573 DAG); 6574 6575 if (isPSHUFLWMask(M, VT)) 6576 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6577 getShufflePSHUFLWImmediate(SVOp), 6578 DAG); 6579 6580 if (isSHUFPMask(M, VT, HasAVX)) 6581 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6582 getShuffleSHUFImmediate(SVOp), DAG); 6583 6584 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6585 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6586 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6587 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6588 6589 //===--------------------------------------------------------------------===// 6590 // Generate target specific nodes for 128 or 256-bit shuffles only 6591 // supported in the AVX instruction set. 6592 // 6593 6594 // Handle VMOVDDUPY permutations 6595 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6596 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6597 6598 // Handle VPERMILPS/D* permutations 6599 if (isVPERMILPMask(M, VT, HasAVX)) { 6600 if (HasAVX2 && VT == MVT::v8i32) 6601 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6602 getShuffleSHUFImmediate(SVOp), DAG); 6603 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6604 getShuffleSHUFImmediate(SVOp), DAG); 6605 } 6606 6607 // Handle VPERM2F128/VPERM2I128 permutations 6608 if (isVPERM2X128Mask(M, VT, HasAVX)) 6609 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6610 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6611 6612 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG, getPointerTy()); 6613 if (BlendOp.getNode()) 6614 return BlendOp; 6615 6616 //===--------------------------------------------------------------------===// 6617 // Since no target specific shuffle was selected for this generic one, 6618 // lower it into other known shuffles. FIXME: this isn't true yet, but 6619 // this is the plan. 6620 // 6621 6622 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6623 if (VT == MVT::v8i16) { 6624 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6625 if (NewOp.getNode()) 6626 return NewOp; 6627 } 6628 6629 if (VT == MVT::v16i8) { 6630 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6631 if (NewOp.getNode()) 6632 return NewOp; 6633 } 6634 6635 // Handle all 128-bit wide vectors with 4 elements, and match them with 6636 // several different shuffle types. 6637 if (NumElems == 4 && VT.getSizeInBits() == 128) 6638 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6639 6640 // Handle general 256-bit shuffles 6641 if (VT.is256BitVector()) 6642 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6643 6644 return SDValue(); 6645} 6646 6647SDValue 6648X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6649 SelectionDAG &DAG) const { 6650 EVT VT = Op.getValueType(); 6651 DebugLoc dl = Op.getDebugLoc(); 6652 6653 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6654 return SDValue(); 6655 6656 if (VT.getSizeInBits() == 8) { 6657 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6658 Op.getOperand(0), Op.getOperand(1)); 6659 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6660 DAG.getValueType(VT)); 6661 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6662 } else if (VT.getSizeInBits() == 16) { 6663 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6664 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6665 if (Idx == 0) 6666 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6667 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6668 DAG.getNode(ISD::BITCAST, dl, 6669 MVT::v4i32, 6670 Op.getOperand(0)), 6671 Op.getOperand(1))); 6672 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6673 Op.getOperand(0), Op.getOperand(1)); 6674 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6675 DAG.getValueType(VT)); 6676 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6677 } else if (VT == MVT::f32) { 6678 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6679 // the result back to FR32 register. It's only worth matching if the 6680 // result has a single use which is a store or a bitcast to i32. And in 6681 // the case of a store, it's not worth it if the index is a constant 0, 6682 // because a MOVSSmr can be used instead, which is smaller and faster. 6683 if (!Op.hasOneUse()) 6684 return SDValue(); 6685 SDNode *User = *Op.getNode()->use_begin(); 6686 if ((User->getOpcode() != ISD::STORE || 6687 (isa<ConstantSDNode>(Op.getOperand(1)) && 6688 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6689 (User->getOpcode() != ISD::BITCAST || 6690 User->getValueType(0) != MVT::i32)) 6691 return SDValue(); 6692 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6693 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6694 Op.getOperand(0)), 6695 Op.getOperand(1)); 6696 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6697 } else if (VT == MVT::i32 || VT == MVT::i64) { 6698 // ExtractPS/pextrq works with constant index. 6699 if (isa<ConstantSDNode>(Op.getOperand(1))) 6700 return Op; 6701 } 6702 return SDValue(); 6703} 6704 6705 6706SDValue 6707X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6708 SelectionDAG &DAG) const { 6709 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6710 return SDValue(); 6711 6712 SDValue Vec = Op.getOperand(0); 6713 EVT VecVT = Vec.getValueType(); 6714 6715 // If this is a 256-bit vector result, first extract the 128-bit vector and 6716 // then extract the element from the 128-bit vector. 6717 if (VecVT.getSizeInBits() == 256) { 6718 DebugLoc dl = Op.getNode()->getDebugLoc(); 6719 unsigned NumElems = VecVT.getVectorNumElements(); 6720 SDValue Idx = Op.getOperand(1); 6721 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6722 6723 // Get the 128-bit vector. 6724 bool Upper = IdxVal >= NumElems/2; 6725 Vec = Extract128BitVector(Vec, 6726 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6727 6728 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6729 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6730 } 6731 6732 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6733 6734 if (Subtarget->hasSSE41()) { 6735 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6736 if (Res.getNode()) 6737 return Res; 6738 } 6739 6740 EVT VT = Op.getValueType(); 6741 DebugLoc dl = Op.getDebugLoc(); 6742 // TODO: handle v16i8. 6743 if (VT.getSizeInBits() == 16) { 6744 SDValue Vec = Op.getOperand(0); 6745 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6746 if (Idx == 0) 6747 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6748 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6749 DAG.getNode(ISD::BITCAST, dl, 6750 MVT::v4i32, Vec), 6751 Op.getOperand(1))); 6752 // Transform it so it match pextrw which produces a 32-bit result. 6753 EVT EltVT = MVT::i32; 6754 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6755 Op.getOperand(0), Op.getOperand(1)); 6756 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6757 DAG.getValueType(VT)); 6758 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6759 } else if (VT.getSizeInBits() == 32) { 6760 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6761 if (Idx == 0) 6762 return Op; 6763 6764 // SHUFPS the element to the lowest double word, then movss. 6765 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6766 EVT VVT = Op.getOperand(0).getValueType(); 6767 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6768 DAG.getUNDEF(VVT), Mask); 6769 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6770 DAG.getIntPtrConstant(0)); 6771 } else if (VT.getSizeInBits() == 64) { 6772 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6773 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6774 // to match extract_elt for f64. 6775 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6776 if (Idx == 0) 6777 return Op; 6778 6779 // UNPCKHPD the element to the lowest double word, then movsd. 6780 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6781 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6782 int Mask[2] = { 1, -1 }; 6783 EVT VVT = Op.getOperand(0).getValueType(); 6784 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6785 DAG.getUNDEF(VVT), Mask); 6786 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6787 DAG.getIntPtrConstant(0)); 6788 } 6789 6790 return SDValue(); 6791} 6792 6793SDValue 6794X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6795 SelectionDAG &DAG) const { 6796 EVT VT = Op.getValueType(); 6797 EVT EltVT = VT.getVectorElementType(); 6798 DebugLoc dl = Op.getDebugLoc(); 6799 6800 SDValue N0 = Op.getOperand(0); 6801 SDValue N1 = Op.getOperand(1); 6802 SDValue N2 = Op.getOperand(2); 6803 6804 if (VT.getSizeInBits() == 256) 6805 return SDValue(); 6806 6807 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6808 isa<ConstantSDNode>(N2)) { 6809 unsigned Opc; 6810 if (VT == MVT::v8i16) 6811 Opc = X86ISD::PINSRW; 6812 else if (VT == MVT::v16i8) 6813 Opc = X86ISD::PINSRB; 6814 else 6815 Opc = X86ISD::PINSRB; 6816 6817 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6818 // argument. 6819 if (N1.getValueType() != MVT::i32) 6820 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6821 if (N2.getValueType() != MVT::i32) 6822 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6823 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6824 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6825 // Bits [7:6] of the constant are the source select. This will always be 6826 // zero here. The DAG Combiner may combine an extract_elt index into these 6827 // bits. For example (insert (extract, 3), 2) could be matched by putting 6828 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6829 // Bits [5:4] of the constant are the destination select. This is the 6830 // value of the incoming immediate. 6831 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6832 // combine either bitwise AND or insert of float 0.0 to set these bits. 6833 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6834 // Create this as a scalar to vector.. 6835 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6836 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6837 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6838 isa<ConstantSDNode>(N2)) { 6839 // PINSR* works with constant index. 6840 return Op; 6841 } 6842 return SDValue(); 6843} 6844 6845SDValue 6846X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6847 EVT VT = Op.getValueType(); 6848 EVT EltVT = VT.getVectorElementType(); 6849 6850 DebugLoc dl = Op.getDebugLoc(); 6851 SDValue N0 = Op.getOperand(0); 6852 SDValue N1 = Op.getOperand(1); 6853 SDValue N2 = Op.getOperand(2); 6854 6855 // If this is a 256-bit vector result, first extract the 128-bit vector, 6856 // insert the element into the extracted half and then place it back. 6857 if (VT.getSizeInBits() == 256) { 6858 if (!isa<ConstantSDNode>(N2)) 6859 return SDValue(); 6860 6861 // Get the desired 128-bit vector half. 6862 unsigned NumElems = VT.getVectorNumElements(); 6863 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6864 bool Upper = IdxVal >= NumElems/2; 6865 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6866 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6867 6868 // Insert the element into the desired half. 6869 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6870 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6871 6872 // Insert the changed part back to the 256-bit vector 6873 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6874 } 6875 6876 if (Subtarget->hasSSE41()) 6877 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6878 6879 if (EltVT == MVT::i8) 6880 return SDValue(); 6881 6882 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6883 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6884 // as its second argument. 6885 if (N1.getValueType() != MVT::i32) 6886 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6887 if (N2.getValueType() != MVT::i32) 6888 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6889 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6890 } 6891 return SDValue(); 6892} 6893 6894SDValue 6895X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6896 LLVMContext *Context = DAG.getContext(); 6897 DebugLoc dl = Op.getDebugLoc(); 6898 EVT OpVT = Op.getValueType(); 6899 6900 // If this is a 256-bit vector result, first insert into a 128-bit 6901 // vector and then insert into the 256-bit vector. 6902 if (OpVT.getSizeInBits() > 128) { 6903 // Insert into a 128-bit vector. 6904 EVT VT128 = EVT::getVectorVT(*Context, 6905 OpVT.getVectorElementType(), 6906 OpVT.getVectorNumElements() / 2); 6907 6908 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6909 6910 // Insert the 128-bit vector. 6911 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6912 DAG.getConstant(0, MVT::i32), 6913 DAG, dl); 6914 } 6915 6916 if (Op.getValueType() == MVT::v1i64 && 6917 Op.getOperand(0).getValueType() == MVT::i64) 6918 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6919 6920 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6921 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6922 "Expected an SSE type!"); 6923 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6924 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6925} 6926 6927// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6928// a simple subregister reference or explicit instructions to grab 6929// upper bits of a vector. 6930SDValue 6931X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6932 if (Subtarget->hasAVX()) { 6933 DebugLoc dl = Op.getNode()->getDebugLoc(); 6934 SDValue Vec = Op.getNode()->getOperand(0); 6935 SDValue Idx = Op.getNode()->getOperand(1); 6936 6937 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6938 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6939 return Extract128BitVector(Vec, Idx, DAG, dl); 6940 } 6941 } 6942 return SDValue(); 6943} 6944 6945// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6946// simple superregister reference or explicit instructions to insert 6947// the upper bits of a vector. 6948SDValue 6949X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6950 if (Subtarget->hasAVX()) { 6951 DebugLoc dl = Op.getNode()->getDebugLoc(); 6952 SDValue Vec = Op.getNode()->getOperand(0); 6953 SDValue SubVec = Op.getNode()->getOperand(1); 6954 SDValue Idx = Op.getNode()->getOperand(2); 6955 6956 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6957 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6958 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6959 } 6960 } 6961 return SDValue(); 6962} 6963 6964// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6965// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6966// one of the above mentioned nodes. It has to be wrapped because otherwise 6967// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6968// be used to form addressing mode. These wrapped nodes will be selected 6969// into MOV32ri. 6970SDValue 6971X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6972 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6973 6974 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6975 // global base reg. 6976 unsigned char OpFlag = 0; 6977 unsigned WrapperKind = X86ISD::Wrapper; 6978 CodeModel::Model M = getTargetMachine().getCodeModel(); 6979 6980 if (Subtarget->isPICStyleRIPRel() && 6981 (M == CodeModel::Small || M == CodeModel::Kernel)) 6982 WrapperKind = X86ISD::WrapperRIP; 6983 else if (Subtarget->isPICStyleGOT()) 6984 OpFlag = X86II::MO_GOTOFF; 6985 else if (Subtarget->isPICStyleStubPIC()) 6986 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6987 6988 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6989 CP->getAlignment(), 6990 CP->getOffset(), OpFlag); 6991 DebugLoc DL = CP->getDebugLoc(); 6992 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6993 // With PIC, the address is actually $g + Offset. 6994 if (OpFlag) { 6995 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6996 DAG.getNode(X86ISD::GlobalBaseReg, 6997 DebugLoc(), getPointerTy()), 6998 Result); 6999 } 7000 7001 return Result; 7002} 7003 7004SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7005 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7006 7007 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7008 // global base reg. 7009 unsigned char OpFlag = 0; 7010 unsigned WrapperKind = X86ISD::Wrapper; 7011 CodeModel::Model M = getTargetMachine().getCodeModel(); 7012 7013 if (Subtarget->isPICStyleRIPRel() && 7014 (M == CodeModel::Small || M == CodeModel::Kernel)) 7015 WrapperKind = X86ISD::WrapperRIP; 7016 else if (Subtarget->isPICStyleGOT()) 7017 OpFlag = X86II::MO_GOTOFF; 7018 else if (Subtarget->isPICStyleStubPIC()) 7019 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7020 7021 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7022 OpFlag); 7023 DebugLoc DL = JT->getDebugLoc(); 7024 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7025 7026 // With PIC, the address is actually $g + Offset. 7027 if (OpFlag) 7028 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7029 DAG.getNode(X86ISD::GlobalBaseReg, 7030 DebugLoc(), getPointerTy()), 7031 Result); 7032 7033 return Result; 7034} 7035 7036SDValue 7037X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7038 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7039 7040 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7041 // global base reg. 7042 unsigned char OpFlag = 0; 7043 unsigned WrapperKind = X86ISD::Wrapper; 7044 CodeModel::Model M = getTargetMachine().getCodeModel(); 7045 7046 if (Subtarget->isPICStyleRIPRel() && 7047 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7048 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7049 OpFlag = X86II::MO_GOTPCREL; 7050 WrapperKind = X86ISD::WrapperRIP; 7051 } else if (Subtarget->isPICStyleGOT()) { 7052 OpFlag = X86II::MO_GOT; 7053 } else if (Subtarget->isPICStyleStubPIC()) { 7054 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7055 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7056 OpFlag = X86II::MO_DARWIN_NONLAZY; 7057 } 7058 7059 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7060 7061 DebugLoc DL = Op.getDebugLoc(); 7062 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7063 7064 7065 // With PIC, the address is actually $g + Offset. 7066 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7067 !Subtarget->is64Bit()) { 7068 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7069 DAG.getNode(X86ISD::GlobalBaseReg, 7070 DebugLoc(), getPointerTy()), 7071 Result); 7072 } 7073 7074 // For symbols that require a load from a stub to get the address, emit the 7075 // load. 7076 if (isGlobalStubReference(OpFlag)) 7077 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7078 MachinePointerInfo::getGOT(), false, false, false, 0); 7079 7080 return Result; 7081} 7082 7083SDValue 7084X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7085 // Create the TargetBlockAddressAddress node. 7086 unsigned char OpFlags = 7087 Subtarget->ClassifyBlockAddressReference(); 7088 CodeModel::Model M = getTargetMachine().getCodeModel(); 7089 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7090 DebugLoc dl = Op.getDebugLoc(); 7091 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7092 /*isTarget=*/true, OpFlags); 7093 7094 if (Subtarget->isPICStyleRIPRel() && 7095 (M == CodeModel::Small || M == CodeModel::Kernel)) 7096 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7097 else 7098 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7099 7100 // With PIC, the address is actually $g + Offset. 7101 if (isGlobalRelativeToPICBase(OpFlags)) { 7102 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7103 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7104 Result); 7105 } 7106 7107 return Result; 7108} 7109 7110SDValue 7111X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7112 int64_t Offset, 7113 SelectionDAG &DAG) const { 7114 // Create the TargetGlobalAddress node, folding in the constant 7115 // offset if it is legal. 7116 unsigned char OpFlags = 7117 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7118 CodeModel::Model M = getTargetMachine().getCodeModel(); 7119 SDValue Result; 7120 if (OpFlags == X86II::MO_NO_FLAG && 7121 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7122 // A direct static reference to a global. 7123 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7124 Offset = 0; 7125 } else { 7126 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7127 } 7128 7129 if (Subtarget->isPICStyleRIPRel() && 7130 (M == CodeModel::Small || M == CodeModel::Kernel)) 7131 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7132 else 7133 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7134 7135 // With PIC, the address is actually $g + Offset. 7136 if (isGlobalRelativeToPICBase(OpFlags)) { 7137 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7138 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7139 Result); 7140 } 7141 7142 // For globals that require a load from a stub to get the address, emit the 7143 // load. 7144 if (isGlobalStubReference(OpFlags)) 7145 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7146 MachinePointerInfo::getGOT(), false, false, false, 0); 7147 7148 // If there was a non-zero offset that we didn't fold, create an explicit 7149 // addition for it. 7150 if (Offset != 0) 7151 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7152 DAG.getConstant(Offset, getPointerTy())); 7153 7154 return Result; 7155} 7156 7157SDValue 7158X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7159 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7160 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7161 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7162} 7163 7164static SDValue 7165GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7166 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7167 unsigned char OperandFlags) { 7168 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7169 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7170 DebugLoc dl = GA->getDebugLoc(); 7171 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7172 GA->getValueType(0), 7173 GA->getOffset(), 7174 OperandFlags); 7175 if (InFlag) { 7176 SDValue Ops[] = { Chain, TGA, *InFlag }; 7177 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7178 } else { 7179 SDValue Ops[] = { Chain, TGA }; 7180 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7181 } 7182 7183 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7184 MFI->setAdjustsStack(true); 7185 7186 SDValue Flag = Chain.getValue(1); 7187 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7188} 7189 7190// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7191static SDValue 7192LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7193 const EVT PtrVT) { 7194 SDValue InFlag; 7195 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7196 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7197 DAG.getNode(X86ISD::GlobalBaseReg, 7198 DebugLoc(), PtrVT), InFlag); 7199 InFlag = Chain.getValue(1); 7200 7201 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7202} 7203 7204// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7205static SDValue 7206LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7207 const EVT PtrVT) { 7208 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7209 X86::RAX, X86II::MO_TLSGD); 7210} 7211 7212// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7213// "local exec" model. 7214static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7215 const EVT PtrVT, TLSModel::Model model, 7216 bool is64Bit) { 7217 DebugLoc dl = GA->getDebugLoc(); 7218 7219 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7220 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7221 is64Bit ? 257 : 256)); 7222 7223 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7224 DAG.getIntPtrConstant(0), 7225 MachinePointerInfo(Ptr), 7226 false, false, false, 0); 7227 7228 unsigned char OperandFlags = 0; 7229 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7230 // initialexec. 7231 unsigned WrapperKind = X86ISD::Wrapper; 7232 if (model == TLSModel::LocalExec) { 7233 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7234 } else if (is64Bit) { 7235 assert(model == TLSModel::InitialExec); 7236 OperandFlags = X86II::MO_GOTTPOFF; 7237 WrapperKind = X86ISD::WrapperRIP; 7238 } else { 7239 assert(model == TLSModel::InitialExec); 7240 OperandFlags = X86II::MO_INDNTPOFF; 7241 } 7242 7243 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7244 // exec) 7245 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7246 GA->getValueType(0), 7247 GA->getOffset(), OperandFlags); 7248 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7249 7250 if (model == TLSModel::InitialExec) 7251 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7252 MachinePointerInfo::getGOT(), false, false, false, 0); 7253 7254 // The address of the thread local variable is the add of the thread 7255 // pointer with the offset of the variable. 7256 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7257} 7258 7259SDValue 7260X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7261 7262 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7263 const GlobalValue *GV = GA->getGlobal(); 7264 7265 if (Subtarget->isTargetELF()) { 7266 // TODO: implement the "local dynamic" model 7267 // TODO: implement the "initial exec"model for pic executables 7268 7269 // If GV is an alias then use the aliasee for determining 7270 // thread-localness. 7271 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7272 GV = GA->resolveAliasedGlobal(false); 7273 7274 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7275 7276 switch (model) { 7277 case TLSModel::GeneralDynamic: 7278 case TLSModel::LocalDynamic: // not implemented 7279 if (Subtarget->is64Bit()) 7280 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7281 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7282 7283 case TLSModel::InitialExec: 7284 case TLSModel::LocalExec: 7285 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7286 Subtarget->is64Bit()); 7287 } 7288 } else if (Subtarget->isTargetDarwin()) { 7289 // Darwin only has one model of TLS. Lower to that. 7290 unsigned char OpFlag = 0; 7291 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7292 X86ISD::WrapperRIP : X86ISD::Wrapper; 7293 7294 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7295 // global base reg. 7296 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7297 !Subtarget->is64Bit(); 7298 if (PIC32) 7299 OpFlag = X86II::MO_TLVP_PIC_BASE; 7300 else 7301 OpFlag = X86II::MO_TLVP; 7302 DebugLoc DL = Op.getDebugLoc(); 7303 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7304 GA->getValueType(0), 7305 GA->getOffset(), OpFlag); 7306 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7307 7308 // With PIC32, the address is actually $g + Offset. 7309 if (PIC32) 7310 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7311 DAG.getNode(X86ISD::GlobalBaseReg, 7312 DebugLoc(), getPointerTy()), 7313 Offset); 7314 7315 // Lowering the machine isd will make sure everything is in the right 7316 // location. 7317 SDValue Chain = DAG.getEntryNode(); 7318 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7319 SDValue Args[] = { Chain, Offset }; 7320 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7321 7322 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7323 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7324 MFI->setAdjustsStack(true); 7325 7326 // And our return value (tls address) is in the standard call return value 7327 // location. 7328 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7329 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7330 Chain.getValue(1)); 7331 } else if (Subtarget->isTargetWindows()) { 7332 // Just use the implicit TLS architecture 7333 // Need to generate someting similar to: 7334 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7335 // ; from TEB 7336 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7337 // mov rcx, qword [rdx+rcx*8] 7338 // mov eax, .tls$:tlsvar 7339 // [rax+rcx] contains the address 7340 // Windows 64bit: gs:0x58 7341 // Windows 32bit: fs:__tls_array 7342 7343 // If GV is an alias then use the aliasee for determining 7344 // thread-localness. 7345 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7346 GV = GA->resolveAliasedGlobal(false); 7347 DebugLoc dl = GA->getDebugLoc(); 7348 SDValue Chain = DAG.getEntryNode(); 7349 7350 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7351 // %gs:0x58 (64-bit). 7352 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7353 ? Type::getInt8PtrTy(*DAG.getContext(), 7354 256) 7355 : Type::getInt32PtrTy(*DAG.getContext(), 7356 257)); 7357 7358 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7359 Subtarget->is64Bit() 7360 ? DAG.getIntPtrConstant(0x58) 7361 : DAG.getExternalSymbol("_tls_array", 7362 getPointerTy()), 7363 MachinePointerInfo(Ptr), 7364 false, false, false, 0); 7365 7366 // Load the _tls_index variable 7367 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7368 if (Subtarget->is64Bit()) 7369 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7370 IDX, MachinePointerInfo(), MVT::i32, 7371 false, false, 0); 7372 else 7373 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7374 false, false, false, 0); 7375 7376 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7377 getPointerTy()); 7378 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7379 7380 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7381 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7382 false, false, false, 0); 7383 7384 // Get the offset of start of .tls section 7385 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7386 GA->getValueType(0), 7387 GA->getOffset(), X86II::MO_SECREL); 7388 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7389 7390 // The address of the thread local variable is the add of the thread 7391 // pointer with the offset of the variable. 7392 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7393 } 7394 7395 llvm_unreachable("TLS not implemented for this target."); 7396} 7397 7398 7399/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7400/// and take a 2 x i32 value to shift plus a shift amount. 7401SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7402 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7403 EVT VT = Op.getValueType(); 7404 unsigned VTBits = VT.getSizeInBits(); 7405 DebugLoc dl = Op.getDebugLoc(); 7406 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7407 SDValue ShOpLo = Op.getOperand(0); 7408 SDValue ShOpHi = Op.getOperand(1); 7409 SDValue ShAmt = Op.getOperand(2); 7410 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7411 DAG.getConstant(VTBits - 1, MVT::i8)) 7412 : DAG.getConstant(0, VT); 7413 7414 SDValue Tmp2, Tmp3; 7415 if (Op.getOpcode() == ISD::SHL_PARTS) { 7416 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7417 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7418 } else { 7419 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7420 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7421 } 7422 7423 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7424 DAG.getConstant(VTBits, MVT::i8)); 7425 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7426 AndNode, DAG.getConstant(0, MVT::i8)); 7427 7428 SDValue Hi, Lo; 7429 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7430 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7431 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7432 7433 if (Op.getOpcode() == ISD::SHL_PARTS) { 7434 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7435 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7436 } else { 7437 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7438 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7439 } 7440 7441 SDValue Ops[2] = { Lo, Hi }; 7442 return DAG.getMergeValues(Ops, 2, dl); 7443} 7444 7445SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7446 SelectionDAG &DAG) const { 7447 EVT SrcVT = Op.getOperand(0).getValueType(); 7448 7449 if (SrcVT.isVector()) 7450 return SDValue(); 7451 7452 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7453 "Unknown SINT_TO_FP to lower!"); 7454 7455 // These are really Legal; return the operand so the caller accepts it as 7456 // Legal. 7457 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7458 return Op; 7459 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7460 Subtarget->is64Bit()) { 7461 return Op; 7462 } 7463 7464 DebugLoc dl = Op.getDebugLoc(); 7465 unsigned Size = SrcVT.getSizeInBits()/8; 7466 MachineFunction &MF = DAG.getMachineFunction(); 7467 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7468 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7469 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7470 StackSlot, 7471 MachinePointerInfo::getFixedStack(SSFI), 7472 false, false, 0); 7473 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7474} 7475 7476SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7477 SDValue StackSlot, 7478 SelectionDAG &DAG) const { 7479 // Build the FILD 7480 DebugLoc DL = Op.getDebugLoc(); 7481 SDVTList Tys; 7482 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7483 if (useSSE) 7484 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7485 else 7486 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7487 7488 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7489 7490 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7491 MachineMemOperand *MMO; 7492 if (FI) { 7493 int SSFI = FI->getIndex(); 7494 MMO = 7495 DAG.getMachineFunction() 7496 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7497 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7498 } else { 7499 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7500 StackSlot = StackSlot.getOperand(1); 7501 } 7502 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7503 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7504 X86ISD::FILD, DL, 7505 Tys, Ops, array_lengthof(Ops), 7506 SrcVT, MMO); 7507 7508 if (useSSE) { 7509 Chain = Result.getValue(1); 7510 SDValue InFlag = Result.getValue(2); 7511 7512 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7513 // shouldn't be necessary except that RFP cannot be live across 7514 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7515 MachineFunction &MF = DAG.getMachineFunction(); 7516 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7517 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7518 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7519 Tys = DAG.getVTList(MVT::Other); 7520 SDValue Ops[] = { 7521 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7522 }; 7523 MachineMemOperand *MMO = 7524 DAG.getMachineFunction() 7525 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7526 MachineMemOperand::MOStore, SSFISize, SSFISize); 7527 7528 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7529 Ops, array_lengthof(Ops), 7530 Op.getValueType(), MMO); 7531 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7532 MachinePointerInfo::getFixedStack(SSFI), 7533 false, false, false, 0); 7534 } 7535 7536 return Result; 7537} 7538 7539// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7540SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7541 SelectionDAG &DAG) const { 7542 // This algorithm is not obvious. Here it is what we're trying to output: 7543 /* 7544 movq %rax, %xmm0 7545 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7546 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7547 #ifdef __SSE3__ 7548 haddpd %xmm0, %xmm0 7549 #else 7550 pshufd $0x4e, %xmm0, %xmm1 7551 addpd %xmm1, %xmm0 7552 #endif 7553 */ 7554 7555 DebugLoc dl = Op.getDebugLoc(); 7556 LLVMContext *Context = DAG.getContext(); 7557 7558 // Build some magic constants. 7559 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7560 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7561 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7562 7563 SmallVector<Constant*,2> CV1; 7564 CV1.push_back( 7565 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7566 CV1.push_back( 7567 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7568 Constant *C1 = ConstantVector::get(CV1); 7569 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7570 7571 // Load the 64-bit value into an XMM register. 7572 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7573 Op.getOperand(0)); 7574 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7575 MachinePointerInfo::getConstantPool(), 7576 false, false, false, 16); 7577 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7578 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7579 CLod0); 7580 7581 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7582 MachinePointerInfo::getConstantPool(), 7583 false, false, false, 16); 7584 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7585 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7586 SDValue Result; 7587 7588 if (Subtarget->hasSSE3()) { 7589 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7590 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7591 } else { 7592 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7593 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7594 S2F, 0x4E, DAG); 7595 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7596 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7597 Sub); 7598 } 7599 7600 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7601 DAG.getIntPtrConstant(0)); 7602} 7603 7604// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7605SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7606 SelectionDAG &DAG) const { 7607 DebugLoc dl = Op.getDebugLoc(); 7608 // FP constant to bias correct the final result. 7609 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7610 MVT::f64); 7611 7612 // Load the 32-bit value into an XMM register. 7613 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7614 Op.getOperand(0)); 7615 7616 // Zero out the upper parts of the register. 7617 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7618 7619 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7620 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7621 DAG.getIntPtrConstant(0)); 7622 7623 // Or the load with the bias. 7624 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7625 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7626 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7627 MVT::v2f64, Load)), 7628 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7629 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7630 MVT::v2f64, Bias))); 7631 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7632 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7633 DAG.getIntPtrConstant(0)); 7634 7635 // Subtract the bias. 7636 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7637 7638 // Handle final rounding. 7639 EVT DestVT = Op.getValueType(); 7640 7641 if (DestVT.bitsLT(MVT::f64)) { 7642 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7643 DAG.getIntPtrConstant(0)); 7644 } else if (DestVT.bitsGT(MVT::f64)) { 7645 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7646 } 7647 7648 // Handle final rounding. 7649 return Sub; 7650} 7651 7652SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7653 SelectionDAG &DAG) const { 7654 SDValue N0 = Op.getOperand(0); 7655 DebugLoc dl = Op.getDebugLoc(); 7656 7657 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7658 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7659 // the optimization here. 7660 if (DAG.SignBitIsZero(N0)) 7661 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7662 7663 EVT SrcVT = N0.getValueType(); 7664 EVT DstVT = Op.getValueType(); 7665 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7666 return LowerUINT_TO_FP_i64(Op, DAG); 7667 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7668 return LowerUINT_TO_FP_i32(Op, DAG); 7669 else if (Subtarget->is64Bit() && 7670 SrcVT == MVT::i64 && DstVT == MVT::f32) 7671 return SDValue(); 7672 7673 // Make a 64-bit buffer, and use it to build an FILD. 7674 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7675 if (SrcVT == MVT::i32) { 7676 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7677 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7678 getPointerTy(), StackSlot, WordOff); 7679 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7680 StackSlot, MachinePointerInfo(), 7681 false, false, 0); 7682 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7683 OffsetSlot, MachinePointerInfo(), 7684 false, false, 0); 7685 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7686 return Fild; 7687 } 7688 7689 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7690 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7691 StackSlot, MachinePointerInfo(), 7692 false, false, 0); 7693 // For i64 source, we need to add the appropriate power of 2 if the input 7694 // was negative. This is the same as the optimization in 7695 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7696 // we must be careful to do the computation in x87 extended precision, not 7697 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7698 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7699 MachineMemOperand *MMO = 7700 DAG.getMachineFunction() 7701 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7702 MachineMemOperand::MOLoad, 8, 8); 7703 7704 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7705 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7706 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7707 MVT::i64, MMO); 7708 7709 APInt FF(32, 0x5F800000ULL); 7710 7711 // Check whether the sign bit is set. 7712 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7713 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7714 ISD::SETLT); 7715 7716 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7717 SDValue FudgePtr = DAG.getConstantPool( 7718 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7719 getPointerTy()); 7720 7721 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7722 SDValue Zero = DAG.getIntPtrConstant(0); 7723 SDValue Four = DAG.getIntPtrConstant(4); 7724 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7725 Zero, Four); 7726 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7727 7728 // Load the value out, extending it from f32 to f80. 7729 // FIXME: Avoid the extend by constructing the right constant pool? 7730 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7731 FudgePtr, MachinePointerInfo::getConstantPool(), 7732 MVT::f32, false, false, 4); 7733 // Extend everything to 80 bits to force it to be done on x87. 7734 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7735 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7736} 7737 7738std::pair<SDValue,SDValue> X86TargetLowering:: 7739FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7740 DebugLoc DL = Op.getDebugLoc(); 7741 7742 EVT DstTy = Op.getValueType(); 7743 7744 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7745 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7746 DstTy = MVT::i64; 7747 } 7748 7749 assert(DstTy.getSimpleVT() <= MVT::i64 && 7750 DstTy.getSimpleVT() >= MVT::i16 && 7751 "Unknown FP_TO_INT to lower!"); 7752 7753 // These are really Legal. 7754 if (DstTy == MVT::i32 && 7755 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7756 return std::make_pair(SDValue(), SDValue()); 7757 if (Subtarget->is64Bit() && 7758 DstTy == MVT::i64 && 7759 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7760 return std::make_pair(SDValue(), SDValue()); 7761 7762 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7763 // stack slot, or into the FTOL runtime function. 7764 MachineFunction &MF = DAG.getMachineFunction(); 7765 unsigned MemSize = DstTy.getSizeInBits()/8; 7766 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7767 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7768 7769 unsigned Opc; 7770 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7771 Opc = X86ISD::WIN_FTOL; 7772 else 7773 switch (DstTy.getSimpleVT().SimpleTy) { 7774 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7775 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7776 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7777 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7778 } 7779 7780 SDValue Chain = DAG.getEntryNode(); 7781 SDValue Value = Op.getOperand(0); 7782 EVT TheVT = Op.getOperand(0).getValueType(); 7783 // FIXME This causes a redundant load/store if the SSE-class value is already 7784 // in memory, such as if it is on the callstack. 7785 if (isScalarFPTypeInSSEReg(TheVT)) { 7786 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7787 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7788 MachinePointerInfo::getFixedStack(SSFI), 7789 false, false, 0); 7790 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7791 SDValue Ops[] = { 7792 Chain, StackSlot, DAG.getValueType(TheVT) 7793 }; 7794 7795 MachineMemOperand *MMO = 7796 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7797 MachineMemOperand::MOLoad, MemSize, MemSize); 7798 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7799 DstTy, MMO); 7800 Chain = Value.getValue(1); 7801 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7802 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7803 } 7804 7805 MachineMemOperand *MMO = 7806 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7807 MachineMemOperand::MOStore, MemSize, MemSize); 7808 7809 if (Opc != X86ISD::WIN_FTOL) { 7810 // Build the FP_TO_INT*_IN_MEM 7811 SDValue Ops[] = { Chain, Value, StackSlot }; 7812 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7813 Ops, 3, DstTy, MMO); 7814 return std::make_pair(FIST, StackSlot); 7815 } else { 7816 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7817 DAG.getVTList(MVT::Other, MVT::Glue), 7818 Chain, Value); 7819 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7820 MVT::i32, ftol.getValue(1)); 7821 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7822 MVT::i32, eax.getValue(2)); 7823 SDValue Ops[] = { eax, edx }; 7824 SDValue pair = IsReplace 7825 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7826 : DAG.getMergeValues(Ops, 2, DL); 7827 return std::make_pair(pair, SDValue()); 7828 } 7829} 7830 7831SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7832 SelectionDAG &DAG) const { 7833 if (Op.getValueType().isVector()) 7834 return SDValue(); 7835 7836 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7837 /*IsSigned=*/ true, /*IsReplace=*/ false); 7838 SDValue FIST = Vals.first, StackSlot = Vals.second; 7839 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7840 if (FIST.getNode() == 0) return Op; 7841 7842 if (StackSlot.getNode()) 7843 // Load the result. 7844 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7845 FIST, StackSlot, MachinePointerInfo(), 7846 false, false, false, 0); 7847 else 7848 // The node is the result. 7849 return FIST; 7850} 7851 7852SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7853 SelectionDAG &DAG) const { 7854 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7855 /*IsSigned=*/ false, /*IsReplace=*/ false); 7856 SDValue FIST = Vals.first, StackSlot = Vals.second; 7857 assert(FIST.getNode() && "Unexpected failure"); 7858 7859 if (StackSlot.getNode()) 7860 // Load the result. 7861 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7862 FIST, StackSlot, MachinePointerInfo(), 7863 false, false, false, 0); 7864 else 7865 // The node is the result. 7866 return FIST; 7867} 7868 7869SDValue X86TargetLowering::LowerFABS(SDValue Op, 7870 SelectionDAG &DAG) const { 7871 LLVMContext *Context = DAG.getContext(); 7872 DebugLoc dl = Op.getDebugLoc(); 7873 EVT VT = Op.getValueType(); 7874 EVT EltVT = VT; 7875 if (VT.isVector()) 7876 EltVT = VT.getVectorElementType(); 7877 Constant *C; 7878 if (EltVT == MVT::f64) { 7879 C = ConstantVector::getSplat(2, 7880 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7881 } else { 7882 C = ConstantVector::getSplat(4, 7883 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7884 } 7885 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7886 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7887 MachinePointerInfo::getConstantPool(), 7888 false, false, false, 16); 7889 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7890} 7891 7892SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7893 LLVMContext *Context = DAG.getContext(); 7894 DebugLoc dl = Op.getDebugLoc(); 7895 EVT VT = Op.getValueType(); 7896 EVT EltVT = VT; 7897 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7898 if (VT.isVector()) { 7899 EltVT = VT.getVectorElementType(); 7900 NumElts = VT.getVectorNumElements(); 7901 } 7902 Constant *C; 7903 if (EltVT == MVT::f64) 7904 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7905 else 7906 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7907 C = ConstantVector::getSplat(NumElts, C); 7908 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7909 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7910 MachinePointerInfo::getConstantPool(), 7911 false, false, false, 16); 7912 if (VT.isVector()) { 7913 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7914 return DAG.getNode(ISD::BITCAST, dl, VT, 7915 DAG.getNode(ISD::XOR, dl, XORVT, 7916 DAG.getNode(ISD::BITCAST, dl, XORVT, 7917 Op.getOperand(0)), 7918 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7919 } else { 7920 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7921 } 7922} 7923 7924SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7925 LLVMContext *Context = DAG.getContext(); 7926 SDValue Op0 = Op.getOperand(0); 7927 SDValue Op1 = Op.getOperand(1); 7928 DebugLoc dl = Op.getDebugLoc(); 7929 EVT VT = Op.getValueType(); 7930 EVT SrcVT = Op1.getValueType(); 7931 7932 // If second operand is smaller, extend it first. 7933 if (SrcVT.bitsLT(VT)) { 7934 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7935 SrcVT = VT; 7936 } 7937 // And if it is bigger, shrink it first. 7938 if (SrcVT.bitsGT(VT)) { 7939 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7940 SrcVT = VT; 7941 } 7942 7943 // At this point the operands and the result should have the same 7944 // type, and that won't be f80 since that is not custom lowered. 7945 7946 // First get the sign bit of second operand. 7947 SmallVector<Constant*,4> CV; 7948 if (SrcVT == MVT::f64) { 7949 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7950 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7951 } else { 7952 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7953 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7954 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7955 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7956 } 7957 Constant *C = ConstantVector::get(CV); 7958 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7959 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7960 MachinePointerInfo::getConstantPool(), 7961 false, false, false, 16); 7962 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7963 7964 // Shift sign bit right or left if the two operands have different types. 7965 if (SrcVT.bitsGT(VT)) { 7966 // Op0 is MVT::f32, Op1 is MVT::f64. 7967 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7968 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7969 DAG.getConstant(32, MVT::i32)); 7970 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7971 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7972 DAG.getIntPtrConstant(0)); 7973 } 7974 7975 // Clear first operand sign bit. 7976 CV.clear(); 7977 if (VT == MVT::f64) { 7978 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7979 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7980 } else { 7981 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7982 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7983 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7984 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7985 } 7986 C = ConstantVector::get(CV); 7987 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7988 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7989 MachinePointerInfo::getConstantPool(), 7990 false, false, false, 16); 7991 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7992 7993 // Or the value with the sign bit. 7994 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7995} 7996 7997SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7998 SDValue N0 = Op.getOperand(0); 7999 DebugLoc dl = Op.getDebugLoc(); 8000 EVT VT = Op.getValueType(); 8001 8002 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8003 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8004 DAG.getConstant(1, VT)); 8005 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8006} 8007 8008/// Emit nodes that will be selected as "test Op0,Op0", or something 8009/// equivalent. 8010SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8011 SelectionDAG &DAG) const { 8012 DebugLoc dl = Op.getDebugLoc(); 8013 8014 // CF and OF aren't always set the way we want. Determine which 8015 // of these we need. 8016 bool NeedCF = false; 8017 bool NeedOF = false; 8018 switch (X86CC) { 8019 default: break; 8020 case X86::COND_A: case X86::COND_AE: 8021 case X86::COND_B: case X86::COND_BE: 8022 NeedCF = true; 8023 break; 8024 case X86::COND_G: case X86::COND_GE: 8025 case X86::COND_L: case X86::COND_LE: 8026 case X86::COND_O: case X86::COND_NO: 8027 NeedOF = true; 8028 break; 8029 } 8030 8031 // See if we can use the EFLAGS value from the operand instead of 8032 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8033 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8034 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8035 // Emit a CMP with 0, which is the TEST pattern. 8036 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8037 DAG.getConstant(0, Op.getValueType())); 8038 8039 unsigned Opcode = 0; 8040 unsigned NumOperands = 0; 8041 switch (Op.getNode()->getOpcode()) { 8042 case ISD::ADD: 8043 // Due to an isel shortcoming, be conservative if this add is likely to be 8044 // selected as part of a load-modify-store instruction. When the root node 8045 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8046 // uses of other nodes in the match, such as the ADD in this case. This 8047 // leads to the ADD being left around and reselected, with the result being 8048 // two adds in the output. Alas, even if none our users are stores, that 8049 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8050 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8051 // climbing the DAG back to the root, and it doesn't seem to be worth the 8052 // effort. 8053 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8054 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8055 if (UI->getOpcode() != ISD::CopyToReg && 8056 UI->getOpcode() != ISD::SETCC && 8057 UI->getOpcode() != ISD::STORE) 8058 goto default_case; 8059 8060 if (ConstantSDNode *C = 8061 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8062 // An add of one will be selected as an INC. 8063 if (C->getAPIntValue() == 1) { 8064 Opcode = X86ISD::INC; 8065 NumOperands = 1; 8066 break; 8067 } 8068 8069 // An add of negative one (subtract of one) will be selected as a DEC. 8070 if (C->getAPIntValue().isAllOnesValue()) { 8071 Opcode = X86ISD::DEC; 8072 NumOperands = 1; 8073 break; 8074 } 8075 } 8076 8077 // Otherwise use a regular EFLAGS-setting add. 8078 Opcode = X86ISD::ADD; 8079 NumOperands = 2; 8080 break; 8081 case ISD::AND: { 8082 // If the primary and result isn't used, don't bother using X86ISD::AND, 8083 // because a TEST instruction will be better. 8084 bool NonFlagUse = false; 8085 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8086 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8087 SDNode *User = *UI; 8088 unsigned UOpNo = UI.getOperandNo(); 8089 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8090 // Look pass truncate. 8091 UOpNo = User->use_begin().getOperandNo(); 8092 User = *User->use_begin(); 8093 } 8094 8095 if (User->getOpcode() != ISD::BRCOND && 8096 User->getOpcode() != ISD::SETCC && 8097 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8098 NonFlagUse = true; 8099 break; 8100 } 8101 } 8102 8103 if (!NonFlagUse) 8104 break; 8105 } 8106 // FALL THROUGH 8107 case ISD::SUB: 8108 case ISD::OR: 8109 case ISD::XOR: 8110 // Due to the ISEL shortcoming noted above, be conservative if this op is 8111 // likely to be selected as part of a load-modify-store instruction. 8112 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8113 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8114 if (UI->getOpcode() == ISD::STORE) 8115 goto default_case; 8116 8117 // Otherwise use a regular EFLAGS-setting instruction. 8118 switch (Op.getNode()->getOpcode()) { 8119 default: llvm_unreachable("unexpected operator!"); 8120 case ISD::SUB: Opcode = X86ISD::SUB; break; 8121 case ISD::OR: Opcode = X86ISD::OR; break; 8122 case ISD::XOR: Opcode = X86ISD::XOR; break; 8123 case ISD::AND: Opcode = X86ISD::AND; break; 8124 } 8125 8126 NumOperands = 2; 8127 break; 8128 case X86ISD::ADD: 8129 case X86ISD::SUB: 8130 case X86ISD::INC: 8131 case X86ISD::DEC: 8132 case X86ISD::OR: 8133 case X86ISD::XOR: 8134 case X86ISD::AND: 8135 return SDValue(Op.getNode(), 1); 8136 default: 8137 default_case: 8138 break; 8139 } 8140 8141 if (Opcode == 0) 8142 // Emit a CMP with 0, which is the TEST pattern. 8143 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8144 DAG.getConstant(0, Op.getValueType())); 8145 8146 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8147 SmallVector<SDValue, 4> Ops; 8148 for (unsigned i = 0; i != NumOperands; ++i) 8149 Ops.push_back(Op.getOperand(i)); 8150 8151 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8152 DAG.ReplaceAllUsesWith(Op, New); 8153 return SDValue(New.getNode(), 1); 8154} 8155 8156/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8157/// equivalent. 8158SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8159 SelectionDAG &DAG) const { 8160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8161 if (C->getAPIntValue() == 0) 8162 return EmitTest(Op0, X86CC, DAG); 8163 8164 DebugLoc dl = Op0.getDebugLoc(); 8165 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8166} 8167 8168/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8169/// if it's possible. 8170SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8171 DebugLoc dl, SelectionDAG &DAG) const { 8172 SDValue Op0 = And.getOperand(0); 8173 SDValue Op1 = And.getOperand(1); 8174 if (Op0.getOpcode() == ISD::TRUNCATE) 8175 Op0 = Op0.getOperand(0); 8176 if (Op1.getOpcode() == ISD::TRUNCATE) 8177 Op1 = Op1.getOperand(0); 8178 8179 SDValue LHS, RHS; 8180 if (Op1.getOpcode() == ISD::SHL) 8181 std::swap(Op0, Op1); 8182 if (Op0.getOpcode() == ISD::SHL) { 8183 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8184 if (And00C->getZExtValue() == 1) { 8185 // If we looked past a truncate, check that it's only truncating away 8186 // known zeros. 8187 unsigned BitWidth = Op0.getValueSizeInBits(); 8188 unsigned AndBitWidth = And.getValueSizeInBits(); 8189 if (BitWidth > AndBitWidth) { 8190 APInt Zeros, Ones; 8191 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8192 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8193 return SDValue(); 8194 } 8195 LHS = Op1; 8196 RHS = Op0.getOperand(1); 8197 } 8198 } else if (Op1.getOpcode() == ISD::Constant) { 8199 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8200 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8201 SDValue AndLHS = Op0; 8202 8203 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8204 LHS = AndLHS.getOperand(0); 8205 RHS = AndLHS.getOperand(1); 8206 } 8207 8208 // Use BT if the immediate can't be encoded in a TEST instruction. 8209 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8210 LHS = AndLHS; 8211 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8212 } 8213 } 8214 8215 if (LHS.getNode()) { 8216 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8217 // instruction. Since the shift amount is in-range-or-undefined, we know 8218 // that doing a bittest on the i32 value is ok. We extend to i32 because 8219 // the encoding for the i16 version is larger than the i32 version. 8220 // Also promote i16 to i32 for performance / code size reason. 8221 if (LHS.getValueType() == MVT::i8 || 8222 LHS.getValueType() == MVT::i16) 8223 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8224 8225 // If the operand types disagree, extend the shift amount to match. Since 8226 // BT ignores high bits (like shifts) we can use anyextend. 8227 if (LHS.getValueType() != RHS.getValueType()) 8228 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8229 8230 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8231 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8232 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8233 DAG.getConstant(Cond, MVT::i8), BT); 8234 } 8235 8236 return SDValue(); 8237} 8238 8239SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8240 8241 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8242 8243 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8244 SDValue Op0 = Op.getOperand(0); 8245 SDValue Op1 = Op.getOperand(1); 8246 DebugLoc dl = Op.getDebugLoc(); 8247 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8248 8249 // Optimize to BT if possible. 8250 // Lower (X & (1 << N)) == 0 to BT(X, N). 8251 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8252 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8253 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8254 Op1.getOpcode() == ISD::Constant && 8255 cast<ConstantSDNode>(Op1)->isNullValue() && 8256 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8257 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8258 if (NewSetCC.getNode()) 8259 return NewSetCC; 8260 } 8261 8262 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8263 // these. 8264 if (Op1.getOpcode() == ISD::Constant && 8265 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8266 cast<ConstantSDNode>(Op1)->isNullValue()) && 8267 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8268 8269 // If the input is a setcc, then reuse the input setcc or use a new one with 8270 // the inverted condition. 8271 if (Op0.getOpcode() == X86ISD::SETCC) { 8272 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8273 bool Invert = (CC == ISD::SETNE) ^ 8274 cast<ConstantSDNode>(Op1)->isNullValue(); 8275 if (!Invert) return Op0; 8276 8277 CCode = X86::GetOppositeBranchCondition(CCode); 8278 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8279 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8280 } 8281 } 8282 8283 bool isFP = Op1.getValueType().isFloatingPoint(); 8284 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8285 if (X86CC == X86::COND_INVALID) 8286 return SDValue(); 8287 8288 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8289 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8290 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8291} 8292 8293// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8294// ones, and then concatenate the result back. 8295static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8296 EVT VT = Op.getValueType(); 8297 8298 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8299 "Unsupported value type for operation"); 8300 8301 int NumElems = VT.getVectorNumElements(); 8302 DebugLoc dl = Op.getDebugLoc(); 8303 SDValue CC = Op.getOperand(2); 8304 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8305 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8306 8307 // Extract the LHS vectors 8308 SDValue LHS = Op.getOperand(0); 8309 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8310 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8311 8312 // Extract the RHS vectors 8313 SDValue RHS = Op.getOperand(1); 8314 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8315 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8316 8317 // Issue the operation on the smaller types and concatenate the result back 8318 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8319 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8320 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8321 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8322 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8323} 8324 8325 8326SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8327 SDValue Cond; 8328 SDValue Op0 = Op.getOperand(0); 8329 SDValue Op1 = Op.getOperand(1); 8330 SDValue CC = Op.getOperand(2); 8331 EVT VT = Op.getValueType(); 8332 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8333 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8334 DebugLoc dl = Op.getDebugLoc(); 8335 8336 if (isFP) { 8337 unsigned SSECC = 8; 8338 EVT EltVT = Op0.getValueType().getVectorElementType(); 8339 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8340 8341 bool Swap = false; 8342 8343 // SSE Condition code mapping: 8344 // 0 - EQ 8345 // 1 - LT 8346 // 2 - LE 8347 // 3 - UNORD 8348 // 4 - NEQ 8349 // 5 - NLT 8350 // 6 - NLE 8351 // 7 - ORD 8352 switch (SetCCOpcode) { 8353 default: break; 8354 case ISD::SETOEQ: 8355 case ISD::SETEQ: SSECC = 0; break; 8356 case ISD::SETOGT: 8357 case ISD::SETGT: Swap = true; // Fallthrough 8358 case ISD::SETLT: 8359 case ISD::SETOLT: SSECC = 1; break; 8360 case ISD::SETOGE: 8361 case ISD::SETGE: Swap = true; // Fallthrough 8362 case ISD::SETLE: 8363 case ISD::SETOLE: SSECC = 2; break; 8364 case ISD::SETUO: SSECC = 3; break; 8365 case ISD::SETUNE: 8366 case ISD::SETNE: SSECC = 4; break; 8367 case ISD::SETULE: Swap = true; 8368 case ISD::SETUGE: SSECC = 5; break; 8369 case ISD::SETULT: Swap = true; 8370 case ISD::SETUGT: SSECC = 6; break; 8371 case ISD::SETO: SSECC = 7; break; 8372 } 8373 if (Swap) 8374 std::swap(Op0, Op1); 8375 8376 // In the two special cases we can't handle, emit two comparisons. 8377 if (SSECC == 8) { 8378 if (SetCCOpcode == ISD::SETUEQ) { 8379 SDValue UNORD, EQ; 8380 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8381 DAG.getConstant(3, MVT::i8)); 8382 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8383 DAG.getConstant(0, MVT::i8)); 8384 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8385 } else if (SetCCOpcode == ISD::SETONE) { 8386 SDValue ORD, NEQ; 8387 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8388 DAG.getConstant(7, MVT::i8)); 8389 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8390 DAG.getConstant(4, MVT::i8)); 8391 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8392 } 8393 llvm_unreachable("Illegal FP comparison"); 8394 } 8395 // Handle all other FP comparisons here. 8396 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8397 DAG.getConstant(SSECC, MVT::i8)); 8398 } 8399 8400 // Break 256-bit integer vector compare into smaller ones. 8401 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8402 return Lower256IntVSETCC(Op, DAG); 8403 8404 // We are handling one of the integer comparisons here. Since SSE only has 8405 // GT and EQ comparisons for integer, swapping operands and multiple 8406 // operations may be required for some comparisons. 8407 unsigned Opc = 0; 8408 bool Swap = false, Invert = false, FlipSigns = false; 8409 8410 switch (SetCCOpcode) { 8411 default: break; 8412 case ISD::SETNE: Invert = true; 8413 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8414 case ISD::SETLT: Swap = true; 8415 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8416 case ISD::SETGE: Swap = true; 8417 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8418 case ISD::SETULT: Swap = true; 8419 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8420 case ISD::SETUGE: Swap = true; 8421 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8422 } 8423 if (Swap) 8424 std::swap(Op0, Op1); 8425 8426 // Check that the operation in question is available (most are plain SSE2, 8427 // but PCMPGTQ and PCMPEQQ have different requirements). 8428 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8429 return SDValue(); 8430 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8431 return SDValue(); 8432 8433 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8434 // bits of the inputs before performing those operations. 8435 if (FlipSigns) { 8436 EVT EltVT = VT.getVectorElementType(); 8437 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8438 EltVT); 8439 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8440 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8441 SignBits.size()); 8442 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8443 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8444 } 8445 8446 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8447 8448 // If the logical-not of the result is required, perform that now. 8449 if (Invert) 8450 Result = DAG.getNOT(dl, Result, VT); 8451 8452 return Result; 8453} 8454 8455// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8456static bool isX86LogicalCmp(SDValue Op) { 8457 unsigned Opc = Op.getNode()->getOpcode(); 8458 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8459 return true; 8460 if (Op.getResNo() == 1 && 8461 (Opc == X86ISD::ADD || 8462 Opc == X86ISD::SUB || 8463 Opc == X86ISD::ADC || 8464 Opc == X86ISD::SBB || 8465 Opc == X86ISD::SMUL || 8466 Opc == X86ISD::UMUL || 8467 Opc == X86ISD::INC || 8468 Opc == X86ISD::DEC || 8469 Opc == X86ISD::OR || 8470 Opc == X86ISD::XOR || 8471 Opc == X86ISD::AND)) 8472 return true; 8473 8474 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8475 return true; 8476 8477 return false; 8478} 8479 8480static bool isZero(SDValue V) { 8481 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8482 return C && C->isNullValue(); 8483} 8484 8485static bool isAllOnes(SDValue V) { 8486 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8487 return C && C->isAllOnesValue(); 8488} 8489 8490SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8491 bool addTest = true; 8492 SDValue Cond = Op.getOperand(0); 8493 SDValue Op1 = Op.getOperand(1); 8494 SDValue Op2 = Op.getOperand(2); 8495 DebugLoc DL = Op.getDebugLoc(); 8496 SDValue CC; 8497 8498 if (Cond.getOpcode() == ISD::SETCC) { 8499 SDValue NewCond = LowerSETCC(Cond, DAG); 8500 if (NewCond.getNode()) 8501 Cond = NewCond; 8502 } 8503 8504 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8505 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8506 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8507 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8508 if (Cond.getOpcode() == X86ISD::SETCC && 8509 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8510 isZero(Cond.getOperand(1).getOperand(1))) { 8511 SDValue Cmp = Cond.getOperand(1); 8512 8513 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8514 8515 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8516 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8517 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8518 8519 SDValue CmpOp0 = Cmp.getOperand(0); 8520 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8521 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8522 8523 SDValue Res = // Res = 0 or -1. 8524 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8525 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8526 8527 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8528 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8529 8530 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8531 if (N2C == 0 || !N2C->isNullValue()) 8532 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8533 return Res; 8534 } 8535 } 8536 8537 // Look past (and (setcc_carry (cmp ...)), 1). 8538 if (Cond.getOpcode() == ISD::AND && 8539 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8541 if (C && C->getAPIntValue() == 1) 8542 Cond = Cond.getOperand(0); 8543 } 8544 8545 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8546 // setting operand in place of the X86ISD::SETCC. 8547 unsigned CondOpcode = Cond.getOpcode(); 8548 if (CondOpcode == X86ISD::SETCC || 8549 CondOpcode == X86ISD::SETCC_CARRY) { 8550 CC = Cond.getOperand(0); 8551 8552 SDValue Cmp = Cond.getOperand(1); 8553 unsigned Opc = Cmp.getOpcode(); 8554 EVT VT = Op.getValueType(); 8555 8556 bool IllegalFPCMov = false; 8557 if (VT.isFloatingPoint() && !VT.isVector() && 8558 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8559 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8560 8561 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8562 Opc == X86ISD::BT) { // FIXME 8563 Cond = Cmp; 8564 addTest = false; 8565 } 8566 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8567 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8568 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8569 Cond.getOperand(0).getValueType() != MVT::i8)) { 8570 SDValue LHS = Cond.getOperand(0); 8571 SDValue RHS = Cond.getOperand(1); 8572 unsigned X86Opcode; 8573 unsigned X86Cond; 8574 SDVTList VTs; 8575 switch (CondOpcode) { 8576 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8577 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8578 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8579 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8580 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8581 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8582 default: llvm_unreachable("unexpected overflowing operator"); 8583 } 8584 if (CondOpcode == ISD::UMULO) 8585 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8586 MVT::i32); 8587 else 8588 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8589 8590 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8591 8592 if (CondOpcode == ISD::UMULO) 8593 Cond = X86Op.getValue(2); 8594 else 8595 Cond = X86Op.getValue(1); 8596 8597 CC = DAG.getConstant(X86Cond, MVT::i8); 8598 addTest = false; 8599 } 8600 8601 if (addTest) { 8602 // Look pass the truncate. 8603 if (Cond.getOpcode() == ISD::TRUNCATE) 8604 Cond = Cond.getOperand(0); 8605 8606 // We know the result of AND is compared against zero. Try to match 8607 // it to BT. 8608 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8609 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8610 if (NewSetCC.getNode()) { 8611 CC = NewSetCC.getOperand(0); 8612 Cond = NewSetCC.getOperand(1); 8613 addTest = false; 8614 } 8615 } 8616 } 8617 8618 if (addTest) { 8619 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8620 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8621 } 8622 8623 // a < b ? -1 : 0 -> RES = ~setcc_carry 8624 // a < b ? 0 : -1 -> RES = setcc_carry 8625 // a >= b ? -1 : 0 -> RES = setcc_carry 8626 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8627 if (Cond.getOpcode() == X86ISD::CMP) { 8628 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8629 8630 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8631 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8632 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8633 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8634 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8635 return DAG.getNOT(DL, Res, Res.getValueType()); 8636 return Res; 8637 } 8638 } 8639 8640 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8641 // condition is true. 8642 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8643 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8644 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8645} 8646 8647// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8648// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8649// from the AND / OR. 8650static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8651 Opc = Op.getOpcode(); 8652 if (Opc != ISD::OR && Opc != ISD::AND) 8653 return false; 8654 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8655 Op.getOperand(0).hasOneUse() && 8656 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8657 Op.getOperand(1).hasOneUse()); 8658} 8659 8660// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8661// 1 and that the SETCC node has a single use. 8662static bool isXor1OfSetCC(SDValue Op) { 8663 if (Op.getOpcode() != ISD::XOR) 8664 return false; 8665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8666 if (N1C && N1C->getAPIntValue() == 1) { 8667 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8668 Op.getOperand(0).hasOneUse(); 8669 } 8670 return false; 8671} 8672 8673SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8674 bool addTest = true; 8675 SDValue Chain = Op.getOperand(0); 8676 SDValue Cond = Op.getOperand(1); 8677 SDValue Dest = Op.getOperand(2); 8678 DebugLoc dl = Op.getDebugLoc(); 8679 SDValue CC; 8680 bool Inverted = false; 8681 8682 if (Cond.getOpcode() == ISD::SETCC) { 8683 // Check for setcc([su]{add,sub,mul}o == 0). 8684 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8685 isa<ConstantSDNode>(Cond.getOperand(1)) && 8686 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8687 Cond.getOperand(0).getResNo() == 1 && 8688 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8689 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8690 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8691 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8692 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8693 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8694 Inverted = true; 8695 Cond = Cond.getOperand(0); 8696 } else { 8697 SDValue NewCond = LowerSETCC(Cond, DAG); 8698 if (NewCond.getNode()) 8699 Cond = NewCond; 8700 } 8701 } 8702#if 0 8703 // FIXME: LowerXALUO doesn't handle these!! 8704 else if (Cond.getOpcode() == X86ISD::ADD || 8705 Cond.getOpcode() == X86ISD::SUB || 8706 Cond.getOpcode() == X86ISD::SMUL || 8707 Cond.getOpcode() == X86ISD::UMUL) 8708 Cond = LowerXALUO(Cond, DAG); 8709#endif 8710 8711 // Look pass (and (setcc_carry (cmp ...)), 1). 8712 if (Cond.getOpcode() == ISD::AND && 8713 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8714 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8715 if (C && C->getAPIntValue() == 1) 8716 Cond = Cond.getOperand(0); 8717 } 8718 8719 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8720 // setting operand in place of the X86ISD::SETCC. 8721 unsigned CondOpcode = Cond.getOpcode(); 8722 if (CondOpcode == X86ISD::SETCC || 8723 CondOpcode == X86ISD::SETCC_CARRY) { 8724 CC = Cond.getOperand(0); 8725 8726 SDValue Cmp = Cond.getOperand(1); 8727 unsigned Opc = Cmp.getOpcode(); 8728 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8729 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8730 Cond = Cmp; 8731 addTest = false; 8732 } else { 8733 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8734 default: break; 8735 case X86::COND_O: 8736 case X86::COND_B: 8737 // These can only come from an arithmetic instruction with overflow, 8738 // e.g. SADDO, UADDO. 8739 Cond = Cond.getNode()->getOperand(1); 8740 addTest = false; 8741 break; 8742 } 8743 } 8744 } 8745 CondOpcode = Cond.getOpcode(); 8746 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8747 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8748 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8749 Cond.getOperand(0).getValueType() != MVT::i8)) { 8750 SDValue LHS = Cond.getOperand(0); 8751 SDValue RHS = Cond.getOperand(1); 8752 unsigned X86Opcode; 8753 unsigned X86Cond; 8754 SDVTList VTs; 8755 switch (CondOpcode) { 8756 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8757 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8758 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8759 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8760 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8761 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8762 default: llvm_unreachable("unexpected overflowing operator"); 8763 } 8764 if (Inverted) 8765 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8766 if (CondOpcode == ISD::UMULO) 8767 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8768 MVT::i32); 8769 else 8770 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8771 8772 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8773 8774 if (CondOpcode == ISD::UMULO) 8775 Cond = X86Op.getValue(2); 8776 else 8777 Cond = X86Op.getValue(1); 8778 8779 CC = DAG.getConstant(X86Cond, MVT::i8); 8780 addTest = false; 8781 } else { 8782 unsigned CondOpc; 8783 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8784 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8785 if (CondOpc == ISD::OR) { 8786 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8787 // two branches instead of an explicit OR instruction with a 8788 // separate test. 8789 if (Cmp == Cond.getOperand(1).getOperand(1) && 8790 isX86LogicalCmp(Cmp)) { 8791 CC = Cond.getOperand(0).getOperand(0); 8792 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8793 Chain, Dest, CC, Cmp); 8794 CC = Cond.getOperand(1).getOperand(0); 8795 Cond = Cmp; 8796 addTest = false; 8797 } 8798 } else { // ISD::AND 8799 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8800 // two branches instead of an explicit AND instruction with a 8801 // separate test. However, we only do this if this block doesn't 8802 // have a fall-through edge, because this requires an explicit 8803 // jmp when the condition is false. 8804 if (Cmp == Cond.getOperand(1).getOperand(1) && 8805 isX86LogicalCmp(Cmp) && 8806 Op.getNode()->hasOneUse()) { 8807 X86::CondCode CCode = 8808 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8809 CCode = X86::GetOppositeBranchCondition(CCode); 8810 CC = DAG.getConstant(CCode, MVT::i8); 8811 SDNode *User = *Op.getNode()->use_begin(); 8812 // Look for an unconditional branch following this conditional branch. 8813 // We need this because we need to reverse the successors in order 8814 // to implement FCMP_OEQ. 8815 if (User->getOpcode() == ISD::BR) { 8816 SDValue FalseBB = User->getOperand(1); 8817 SDNode *NewBR = 8818 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8819 assert(NewBR == User); 8820 (void)NewBR; 8821 Dest = FalseBB; 8822 8823 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8824 Chain, Dest, CC, Cmp); 8825 X86::CondCode CCode = 8826 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8827 CCode = X86::GetOppositeBranchCondition(CCode); 8828 CC = DAG.getConstant(CCode, MVT::i8); 8829 Cond = Cmp; 8830 addTest = false; 8831 } 8832 } 8833 } 8834 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8835 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8836 // It should be transformed during dag combiner except when the condition 8837 // is set by a arithmetics with overflow node. 8838 X86::CondCode CCode = 8839 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8840 CCode = X86::GetOppositeBranchCondition(CCode); 8841 CC = DAG.getConstant(CCode, MVT::i8); 8842 Cond = Cond.getOperand(0).getOperand(1); 8843 addTest = false; 8844 } else if (Cond.getOpcode() == ISD::SETCC && 8845 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8846 // For FCMP_OEQ, we can emit 8847 // two branches instead of an explicit AND instruction with a 8848 // separate test. However, we only do this if this block doesn't 8849 // have a fall-through edge, because this requires an explicit 8850 // jmp when the condition is false. 8851 if (Op.getNode()->hasOneUse()) { 8852 SDNode *User = *Op.getNode()->use_begin(); 8853 // Look for an unconditional branch following this conditional branch. 8854 // We need this because we need to reverse the successors in order 8855 // to implement FCMP_OEQ. 8856 if (User->getOpcode() == ISD::BR) { 8857 SDValue FalseBB = User->getOperand(1); 8858 SDNode *NewBR = 8859 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8860 assert(NewBR == User); 8861 (void)NewBR; 8862 Dest = FalseBB; 8863 8864 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8865 Cond.getOperand(0), Cond.getOperand(1)); 8866 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8867 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8868 Chain, Dest, CC, Cmp); 8869 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8870 Cond = Cmp; 8871 addTest = false; 8872 } 8873 } 8874 } else if (Cond.getOpcode() == ISD::SETCC && 8875 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8876 // For FCMP_UNE, we can emit 8877 // two branches instead of an explicit AND instruction with a 8878 // separate test. However, we only do this if this block doesn't 8879 // have a fall-through edge, because this requires an explicit 8880 // jmp when the condition is false. 8881 if (Op.getNode()->hasOneUse()) { 8882 SDNode *User = *Op.getNode()->use_begin(); 8883 // Look for an unconditional branch following this conditional branch. 8884 // We need this because we need to reverse the successors in order 8885 // to implement FCMP_UNE. 8886 if (User->getOpcode() == ISD::BR) { 8887 SDValue FalseBB = User->getOperand(1); 8888 SDNode *NewBR = 8889 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8890 assert(NewBR == User); 8891 (void)NewBR; 8892 8893 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8894 Cond.getOperand(0), Cond.getOperand(1)); 8895 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8896 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8897 Chain, Dest, CC, Cmp); 8898 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8899 Cond = Cmp; 8900 addTest = false; 8901 Dest = FalseBB; 8902 } 8903 } 8904 } 8905 } 8906 8907 if (addTest) { 8908 // Look pass the truncate. 8909 if (Cond.getOpcode() == ISD::TRUNCATE) 8910 Cond = Cond.getOperand(0); 8911 8912 // We know the result of AND is compared against zero. Try to match 8913 // it to BT. 8914 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8915 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8916 if (NewSetCC.getNode()) { 8917 CC = NewSetCC.getOperand(0); 8918 Cond = NewSetCC.getOperand(1); 8919 addTest = false; 8920 } 8921 } 8922 } 8923 8924 if (addTest) { 8925 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8926 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8927 } 8928 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8929 Chain, Dest, CC, Cond); 8930} 8931 8932 8933// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8934// Calls to _alloca is needed to probe the stack when allocating more than 4k 8935// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8936// that the guard pages used by the OS virtual memory manager are allocated in 8937// correct sequence. 8938SDValue 8939X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8940 SelectionDAG &DAG) const { 8941 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8942 getTargetMachine().Options.EnableSegmentedStacks) && 8943 "This should be used only on Windows targets or when segmented stacks " 8944 "are being used"); 8945 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8946 DebugLoc dl = Op.getDebugLoc(); 8947 8948 // Get the inputs. 8949 SDValue Chain = Op.getOperand(0); 8950 SDValue Size = Op.getOperand(1); 8951 // FIXME: Ensure alignment here 8952 8953 bool Is64Bit = Subtarget->is64Bit(); 8954 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8955 8956 if (getTargetMachine().Options.EnableSegmentedStacks) { 8957 MachineFunction &MF = DAG.getMachineFunction(); 8958 MachineRegisterInfo &MRI = MF.getRegInfo(); 8959 8960 if (Is64Bit) { 8961 // The 64 bit implementation of segmented stacks needs to clobber both r10 8962 // r11. This makes it impossible to use it along with nested parameters. 8963 const Function *F = MF.getFunction(); 8964 8965 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8966 I != E; I++) 8967 if (I->hasNestAttr()) 8968 report_fatal_error("Cannot use segmented stacks with functions that " 8969 "have nested arguments."); 8970 } 8971 8972 const TargetRegisterClass *AddrRegClass = 8973 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8974 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8975 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8976 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8977 DAG.getRegister(Vreg, SPTy)); 8978 SDValue Ops1[2] = { Value, Chain }; 8979 return DAG.getMergeValues(Ops1, 2, dl); 8980 } else { 8981 SDValue Flag; 8982 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8983 8984 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8985 Flag = Chain.getValue(1); 8986 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8987 8988 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8989 Flag = Chain.getValue(1); 8990 8991 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8992 8993 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8994 return DAG.getMergeValues(Ops1, 2, dl); 8995 } 8996} 8997 8998SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8999 MachineFunction &MF = DAG.getMachineFunction(); 9000 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9001 9002 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9003 DebugLoc DL = Op.getDebugLoc(); 9004 9005 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9006 // vastart just stores the address of the VarArgsFrameIndex slot into the 9007 // memory location argument. 9008 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9009 getPointerTy()); 9010 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9011 MachinePointerInfo(SV), false, false, 0); 9012 } 9013 9014 // __va_list_tag: 9015 // gp_offset (0 - 6 * 8) 9016 // fp_offset (48 - 48 + 8 * 16) 9017 // overflow_arg_area (point to parameters coming in memory). 9018 // reg_save_area 9019 SmallVector<SDValue, 8> MemOps; 9020 SDValue FIN = Op.getOperand(1); 9021 // Store gp_offset 9022 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9023 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9024 MVT::i32), 9025 FIN, MachinePointerInfo(SV), false, false, 0); 9026 MemOps.push_back(Store); 9027 9028 // Store fp_offset 9029 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9030 FIN, DAG.getIntPtrConstant(4)); 9031 Store = DAG.getStore(Op.getOperand(0), DL, 9032 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9033 MVT::i32), 9034 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9035 MemOps.push_back(Store); 9036 9037 // Store ptr to overflow_arg_area 9038 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9039 FIN, DAG.getIntPtrConstant(4)); 9040 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9041 getPointerTy()); 9042 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9043 MachinePointerInfo(SV, 8), 9044 false, false, 0); 9045 MemOps.push_back(Store); 9046 9047 // Store ptr to reg_save_area. 9048 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9049 FIN, DAG.getIntPtrConstant(8)); 9050 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9051 getPointerTy()); 9052 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9053 MachinePointerInfo(SV, 16), false, false, 0); 9054 MemOps.push_back(Store); 9055 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9056 &MemOps[0], MemOps.size()); 9057} 9058 9059SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9060 assert(Subtarget->is64Bit() && 9061 "LowerVAARG only handles 64-bit va_arg!"); 9062 assert((Subtarget->isTargetLinux() || 9063 Subtarget->isTargetDarwin()) && 9064 "Unhandled target in LowerVAARG"); 9065 assert(Op.getNode()->getNumOperands() == 4); 9066 SDValue Chain = Op.getOperand(0); 9067 SDValue SrcPtr = Op.getOperand(1); 9068 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9069 unsigned Align = Op.getConstantOperandVal(3); 9070 DebugLoc dl = Op.getDebugLoc(); 9071 9072 EVT ArgVT = Op.getNode()->getValueType(0); 9073 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9074 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9075 uint8_t ArgMode; 9076 9077 // Decide which area this value should be read from. 9078 // TODO: Implement the AMD64 ABI in its entirety. This simple 9079 // selection mechanism works only for the basic types. 9080 if (ArgVT == MVT::f80) { 9081 llvm_unreachable("va_arg for f80 not yet implemented"); 9082 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9083 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9084 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9085 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9086 } else { 9087 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9088 } 9089 9090 if (ArgMode == 2) { 9091 // Sanity Check: Make sure using fp_offset makes sense. 9092 assert(!getTargetMachine().Options.UseSoftFloat && 9093 !(DAG.getMachineFunction() 9094 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9095 Subtarget->hasSSE1()); 9096 } 9097 9098 // Insert VAARG_64 node into the DAG 9099 // VAARG_64 returns two values: Variable Argument Address, Chain 9100 SmallVector<SDValue, 11> InstOps; 9101 InstOps.push_back(Chain); 9102 InstOps.push_back(SrcPtr); 9103 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9104 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9105 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9106 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9107 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9108 VTs, &InstOps[0], InstOps.size(), 9109 MVT::i64, 9110 MachinePointerInfo(SV), 9111 /*Align=*/0, 9112 /*Volatile=*/false, 9113 /*ReadMem=*/true, 9114 /*WriteMem=*/true); 9115 Chain = VAARG.getValue(1); 9116 9117 // Load the next argument and return it 9118 return DAG.getLoad(ArgVT, dl, 9119 Chain, 9120 VAARG, 9121 MachinePointerInfo(), 9122 false, false, false, 0); 9123} 9124 9125SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9126 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9127 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9128 SDValue Chain = Op.getOperand(0); 9129 SDValue DstPtr = Op.getOperand(1); 9130 SDValue SrcPtr = Op.getOperand(2); 9131 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9132 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9133 DebugLoc DL = Op.getDebugLoc(); 9134 9135 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9136 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9137 false, 9138 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9139} 9140 9141// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9142// may or may not be a constant. Takes immediate version of shift as input. 9143static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9144 SDValue SrcOp, SDValue ShAmt, 9145 SelectionDAG &DAG) { 9146 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9147 9148 if (isa<ConstantSDNode>(ShAmt)) { 9149 switch (Opc) { 9150 default: llvm_unreachable("Unknown target vector shift node"); 9151 case X86ISD::VSHLI: 9152 case X86ISD::VSRLI: 9153 case X86ISD::VSRAI: 9154 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9155 } 9156 } 9157 9158 // Change opcode to non-immediate version 9159 switch (Opc) { 9160 default: llvm_unreachable("Unknown target vector shift node"); 9161 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9162 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9163 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9164 } 9165 9166 // Need to build a vector containing shift amount 9167 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9168 SDValue ShOps[4]; 9169 ShOps[0] = ShAmt; 9170 ShOps[1] = DAG.getConstant(0, MVT::i32); 9171 ShOps[2] = DAG.getUNDEF(MVT::i32); 9172 ShOps[3] = DAG.getUNDEF(MVT::i32); 9173 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9174 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9175 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9176} 9177 9178SDValue 9179X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9180 DebugLoc dl = Op.getDebugLoc(); 9181 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9182 switch (IntNo) { 9183 default: return SDValue(); // Don't custom lower most intrinsics. 9184 // Comparison intrinsics. 9185 case Intrinsic::x86_sse_comieq_ss: 9186 case Intrinsic::x86_sse_comilt_ss: 9187 case Intrinsic::x86_sse_comile_ss: 9188 case Intrinsic::x86_sse_comigt_ss: 9189 case Intrinsic::x86_sse_comige_ss: 9190 case Intrinsic::x86_sse_comineq_ss: 9191 case Intrinsic::x86_sse_ucomieq_ss: 9192 case Intrinsic::x86_sse_ucomilt_ss: 9193 case Intrinsic::x86_sse_ucomile_ss: 9194 case Intrinsic::x86_sse_ucomigt_ss: 9195 case Intrinsic::x86_sse_ucomige_ss: 9196 case Intrinsic::x86_sse_ucomineq_ss: 9197 case Intrinsic::x86_sse2_comieq_sd: 9198 case Intrinsic::x86_sse2_comilt_sd: 9199 case Intrinsic::x86_sse2_comile_sd: 9200 case Intrinsic::x86_sse2_comigt_sd: 9201 case Intrinsic::x86_sse2_comige_sd: 9202 case Intrinsic::x86_sse2_comineq_sd: 9203 case Intrinsic::x86_sse2_ucomieq_sd: 9204 case Intrinsic::x86_sse2_ucomilt_sd: 9205 case Intrinsic::x86_sse2_ucomile_sd: 9206 case Intrinsic::x86_sse2_ucomigt_sd: 9207 case Intrinsic::x86_sse2_ucomige_sd: 9208 case Intrinsic::x86_sse2_ucomineq_sd: { 9209 unsigned Opc = 0; 9210 ISD::CondCode CC = ISD::SETCC_INVALID; 9211 switch (IntNo) { 9212 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9213 case Intrinsic::x86_sse_comieq_ss: 9214 case Intrinsic::x86_sse2_comieq_sd: 9215 Opc = X86ISD::COMI; 9216 CC = ISD::SETEQ; 9217 break; 9218 case Intrinsic::x86_sse_comilt_ss: 9219 case Intrinsic::x86_sse2_comilt_sd: 9220 Opc = X86ISD::COMI; 9221 CC = ISD::SETLT; 9222 break; 9223 case Intrinsic::x86_sse_comile_ss: 9224 case Intrinsic::x86_sse2_comile_sd: 9225 Opc = X86ISD::COMI; 9226 CC = ISD::SETLE; 9227 break; 9228 case Intrinsic::x86_sse_comigt_ss: 9229 case Intrinsic::x86_sse2_comigt_sd: 9230 Opc = X86ISD::COMI; 9231 CC = ISD::SETGT; 9232 break; 9233 case Intrinsic::x86_sse_comige_ss: 9234 case Intrinsic::x86_sse2_comige_sd: 9235 Opc = X86ISD::COMI; 9236 CC = ISD::SETGE; 9237 break; 9238 case Intrinsic::x86_sse_comineq_ss: 9239 case Intrinsic::x86_sse2_comineq_sd: 9240 Opc = X86ISD::COMI; 9241 CC = ISD::SETNE; 9242 break; 9243 case Intrinsic::x86_sse_ucomieq_ss: 9244 case Intrinsic::x86_sse2_ucomieq_sd: 9245 Opc = X86ISD::UCOMI; 9246 CC = ISD::SETEQ; 9247 break; 9248 case Intrinsic::x86_sse_ucomilt_ss: 9249 case Intrinsic::x86_sse2_ucomilt_sd: 9250 Opc = X86ISD::UCOMI; 9251 CC = ISD::SETLT; 9252 break; 9253 case Intrinsic::x86_sse_ucomile_ss: 9254 case Intrinsic::x86_sse2_ucomile_sd: 9255 Opc = X86ISD::UCOMI; 9256 CC = ISD::SETLE; 9257 break; 9258 case Intrinsic::x86_sse_ucomigt_ss: 9259 case Intrinsic::x86_sse2_ucomigt_sd: 9260 Opc = X86ISD::UCOMI; 9261 CC = ISD::SETGT; 9262 break; 9263 case Intrinsic::x86_sse_ucomige_ss: 9264 case Intrinsic::x86_sse2_ucomige_sd: 9265 Opc = X86ISD::UCOMI; 9266 CC = ISD::SETGE; 9267 break; 9268 case Intrinsic::x86_sse_ucomineq_ss: 9269 case Intrinsic::x86_sse2_ucomineq_sd: 9270 Opc = X86ISD::UCOMI; 9271 CC = ISD::SETNE; 9272 break; 9273 } 9274 9275 SDValue LHS = Op.getOperand(1); 9276 SDValue RHS = Op.getOperand(2); 9277 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9278 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9279 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9280 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9281 DAG.getConstant(X86CC, MVT::i8), Cond); 9282 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9283 } 9284 // XOP comparison intrinsics 9285 case Intrinsic::x86_xop_vpcomltb: 9286 case Intrinsic::x86_xop_vpcomltw: 9287 case Intrinsic::x86_xop_vpcomltd: 9288 case Intrinsic::x86_xop_vpcomltq: 9289 case Intrinsic::x86_xop_vpcomltub: 9290 case Intrinsic::x86_xop_vpcomltuw: 9291 case Intrinsic::x86_xop_vpcomltud: 9292 case Intrinsic::x86_xop_vpcomltuq: 9293 case Intrinsic::x86_xop_vpcomleb: 9294 case Intrinsic::x86_xop_vpcomlew: 9295 case Intrinsic::x86_xop_vpcomled: 9296 case Intrinsic::x86_xop_vpcomleq: 9297 case Intrinsic::x86_xop_vpcomleub: 9298 case Intrinsic::x86_xop_vpcomleuw: 9299 case Intrinsic::x86_xop_vpcomleud: 9300 case Intrinsic::x86_xop_vpcomleuq: 9301 case Intrinsic::x86_xop_vpcomgtb: 9302 case Intrinsic::x86_xop_vpcomgtw: 9303 case Intrinsic::x86_xop_vpcomgtd: 9304 case Intrinsic::x86_xop_vpcomgtq: 9305 case Intrinsic::x86_xop_vpcomgtub: 9306 case Intrinsic::x86_xop_vpcomgtuw: 9307 case Intrinsic::x86_xop_vpcomgtud: 9308 case Intrinsic::x86_xop_vpcomgtuq: 9309 case Intrinsic::x86_xop_vpcomgeb: 9310 case Intrinsic::x86_xop_vpcomgew: 9311 case Intrinsic::x86_xop_vpcomged: 9312 case Intrinsic::x86_xop_vpcomgeq: 9313 case Intrinsic::x86_xop_vpcomgeub: 9314 case Intrinsic::x86_xop_vpcomgeuw: 9315 case Intrinsic::x86_xop_vpcomgeud: 9316 case Intrinsic::x86_xop_vpcomgeuq: 9317 case Intrinsic::x86_xop_vpcomeqb: 9318 case Intrinsic::x86_xop_vpcomeqw: 9319 case Intrinsic::x86_xop_vpcomeqd: 9320 case Intrinsic::x86_xop_vpcomeqq: 9321 case Intrinsic::x86_xop_vpcomequb: 9322 case Intrinsic::x86_xop_vpcomequw: 9323 case Intrinsic::x86_xop_vpcomequd: 9324 case Intrinsic::x86_xop_vpcomequq: 9325 case Intrinsic::x86_xop_vpcomneb: 9326 case Intrinsic::x86_xop_vpcomnew: 9327 case Intrinsic::x86_xop_vpcomned: 9328 case Intrinsic::x86_xop_vpcomneq: 9329 case Intrinsic::x86_xop_vpcomneub: 9330 case Intrinsic::x86_xop_vpcomneuw: 9331 case Intrinsic::x86_xop_vpcomneud: 9332 case Intrinsic::x86_xop_vpcomneuq: 9333 case Intrinsic::x86_xop_vpcomfalseb: 9334 case Intrinsic::x86_xop_vpcomfalsew: 9335 case Intrinsic::x86_xop_vpcomfalsed: 9336 case Intrinsic::x86_xop_vpcomfalseq: 9337 case Intrinsic::x86_xop_vpcomfalseub: 9338 case Intrinsic::x86_xop_vpcomfalseuw: 9339 case Intrinsic::x86_xop_vpcomfalseud: 9340 case Intrinsic::x86_xop_vpcomfalseuq: 9341 case Intrinsic::x86_xop_vpcomtrueb: 9342 case Intrinsic::x86_xop_vpcomtruew: 9343 case Intrinsic::x86_xop_vpcomtrued: 9344 case Intrinsic::x86_xop_vpcomtrueq: 9345 case Intrinsic::x86_xop_vpcomtrueub: 9346 case Intrinsic::x86_xop_vpcomtrueuw: 9347 case Intrinsic::x86_xop_vpcomtrueud: 9348 case Intrinsic::x86_xop_vpcomtrueuq: { 9349 unsigned CC = 0; 9350 unsigned Opc = 0; 9351 9352 switch (IntNo) { 9353 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9354 case Intrinsic::x86_xop_vpcomltb: 9355 case Intrinsic::x86_xop_vpcomltw: 9356 case Intrinsic::x86_xop_vpcomltd: 9357 case Intrinsic::x86_xop_vpcomltq: 9358 CC = 0; 9359 Opc = X86ISD::VPCOM; 9360 break; 9361 case Intrinsic::x86_xop_vpcomltub: 9362 case Intrinsic::x86_xop_vpcomltuw: 9363 case Intrinsic::x86_xop_vpcomltud: 9364 case Intrinsic::x86_xop_vpcomltuq: 9365 CC = 0; 9366 Opc = X86ISD::VPCOMU; 9367 break; 9368 case Intrinsic::x86_xop_vpcomleb: 9369 case Intrinsic::x86_xop_vpcomlew: 9370 case Intrinsic::x86_xop_vpcomled: 9371 case Intrinsic::x86_xop_vpcomleq: 9372 CC = 1; 9373 Opc = X86ISD::VPCOM; 9374 break; 9375 case Intrinsic::x86_xop_vpcomleub: 9376 case Intrinsic::x86_xop_vpcomleuw: 9377 case Intrinsic::x86_xop_vpcomleud: 9378 case Intrinsic::x86_xop_vpcomleuq: 9379 CC = 1; 9380 Opc = X86ISD::VPCOMU; 9381 break; 9382 case Intrinsic::x86_xop_vpcomgtb: 9383 case Intrinsic::x86_xop_vpcomgtw: 9384 case Intrinsic::x86_xop_vpcomgtd: 9385 case Intrinsic::x86_xop_vpcomgtq: 9386 CC = 2; 9387 Opc = X86ISD::VPCOM; 9388 break; 9389 case Intrinsic::x86_xop_vpcomgtub: 9390 case Intrinsic::x86_xop_vpcomgtuw: 9391 case Intrinsic::x86_xop_vpcomgtud: 9392 case Intrinsic::x86_xop_vpcomgtuq: 9393 CC = 2; 9394 Opc = X86ISD::VPCOMU; 9395 break; 9396 case Intrinsic::x86_xop_vpcomgeb: 9397 case Intrinsic::x86_xop_vpcomgew: 9398 case Intrinsic::x86_xop_vpcomged: 9399 case Intrinsic::x86_xop_vpcomgeq: 9400 CC = 3; 9401 Opc = X86ISD::VPCOM; 9402 break; 9403 case Intrinsic::x86_xop_vpcomgeub: 9404 case Intrinsic::x86_xop_vpcomgeuw: 9405 case Intrinsic::x86_xop_vpcomgeud: 9406 case Intrinsic::x86_xop_vpcomgeuq: 9407 CC = 3; 9408 Opc = X86ISD::VPCOMU; 9409 break; 9410 case Intrinsic::x86_xop_vpcomeqb: 9411 case Intrinsic::x86_xop_vpcomeqw: 9412 case Intrinsic::x86_xop_vpcomeqd: 9413 case Intrinsic::x86_xop_vpcomeqq: 9414 CC = 4; 9415 Opc = X86ISD::VPCOM; 9416 break; 9417 case Intrinsic::x86_xop_vpcomequb: 9418 case Intrinsic::x86_xop_vpcomequw: 9419 case Intrinsic::x86_xop_vpcomequd: 9420 case Intrinsic::x86_xop_vpcomequq: 9421 CC = 4; 9422 Opc = X86ISD::VPCOMU; 9423 break; 9424 case Intrinsic::x86_xop_vpcomneb: 9425 case Intrinsic::x86_xop_vpcomnew: 9426 case Intrinsic::x86_xop_vpcomned: 9427 case Intrinsic::x86_xop_vpcomneq: 9428 CC = 5; 9429 Opc = X86ISD::VPCOM; 9430 break; 9431 case Intrinsic::x86_xop_vpcomneub: 9432 case Intrinsic::x86_xop_vpcomneuw: 9433 case Intrinsic::x86_xop_vpcomneud: 9434 case Intrinsic::x86_xop_vpcomneuq: 9435 CC = 5; 9436 Opc = X86ISD::VPCOMU; 9437 break; 9438 case Intrinsic::x86_xop_vpcomfalseb: 9439 case Intrinsic::x86_xop_vpcomfalsew: 9440 case Intrinsic::x86_xop_vpcomfalsed: 9441 case Intrinsic::x86_xop_vpcomfalseq: 9442 CC = 6; 9443 Opc = X86ISD::VPCOM; 9444 break; 9445 case Intrinsic::x86_xop_vpcomfalseub: 9446 case Intrinsic::x86_xop_vpcomfalseuw: 9447 case Intrinsic::x86_xop_vpcomfalseud: 9448 case Intrinsic::x86_xop_vpcomfalseuq: 9449 CC = 6; 9450 Opc = X86ISD::VPCOMU; 9451 break; 9452 case Intrinsic::x86_xop_vpcomtrueb: 9453 case Intrinsic::x86_xop_vpcomtruew: 9454 case Intrinsic::x86_xop_vpcomtrued: 9455 case Intrinsic::x86_xop_vpcomtrueq: 9456 CC = 7; 9457 Opc = X86ISD::VPCOM; 9458 break; 9459 case Intrinsic::x86_xop_vpcomtrueub: 9460 case Intrinsic::x86_xop_vpcomtrueuw: 9461 case Intrinsic::x86_xop_vpcomtrueud: 9462 case Intrinsic::x86_xop_vpcomtrueuq: 9463 CC = 7; 9464 Opc = X86ISD::VPCOMU; 9465 break; 9466 } 9467 9468 SDValue LHS = Op.getOperand(1); 9469 SDValue RHS = Op.getOperand(2); 9470 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9471 DAG.getConstant(CC, MVT::i8)); 9472 } 9473 9474 // Arithmetic intrinsics. 9475 case Intrinsic::x86_sse2_pmulu_dq: 9476 case Intrinsic::x86_avx2_pmulu_dq: 9477 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9478 Op.getOperand(1), Op.getOperand(2)); 9479 case Intrinsic::x86_sse3_hadd_ps: 9480 case Intrinsic::x86_sse3_hadd_pd: 9481 case Intrinsic::x86_avx_hadd_ps_256: 9482 case Intrinsic::x86_avx_hadd_pd_256: 9483 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9484 Op.getOperand(1), Op.getOperand(2)); 9485 case Intrinsic::x86_sse3_hsub_ps: 9486 case Intrinsic::x86_sse3_hsub_pd: 9487 case Intrinsic::x86_avx_hsub_ps_256: 9488 case Intrinsic::x86_avx_hsub_pd_256: 9489 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9490 Op.getOperand(1), Op.getOperand(2)); 9491 case Intrinsic::x86_ssse3_phadd_w_128: 9492 case Intrinsic::x86_ssse3_phadd_d_128: 9493 case Intrinsic::x86_avx2_phadd_w: 9494 case Intrinsic::x86_avx2_phadd_d: 9495 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9496 Op.getOperand(1), Op.getOperand(2)); 9497 case Intrinsic::x86_ssse3_phsub_w_128: 9498 case Intrinsic::x86_ssse3_phsub_d_128: 9499 case Intrinsic::x86_avx2_phsub_w: 9500 case Intrinsic::x86_avx2_phsub_d: 9501 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9502 Op.getOperand(1), Op.getOperand(2)); 9503 case Intrinsic::x86_avx2_psllv_d: 9504 case Intrinsic::x86_avx2_psllv_q: 9505 case Intrinsic::x86_avx2_psllv_d_256: 9506 case Intrinsic::x86_avx2_psllv_q_256: 9507 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9508 Op.getOperand(1), Op.getOperand(2)); 9509 case Intrinsic::x86_avx2_psrlv_d: 9510 case Intrinsic::x86_avx2_psrlv_q: 9511 case Intrinsic::x86_avx2_psrlv_d_256: 9512 case Intrinsic::x86_avx2_psrlv_q_256: 9513 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9514 Op.getOperand(1), Op.getOperand(2)); 9515 case Intrinsic::x86_avx2_psrav_d: 9516 case Intrinsic::x86_avx2_psrav_d_256: 9517 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9518 Op.getOperand(1), Op.getOperand(2)); 9519 case Intrinsic::x86_ssse3_pshuf_b_128: 9520 case Intrinsic::x86_avx2_pshuf_b: 9521 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9522 Op.getOperand(1), Op.getOperand(2)); 9523 case Intrinsic::x86_ssse3_psign_b_128: 9524 case Intrinsic::x86_ssse3_psign_w_128: 9525 case Intrinsic::x86_ssse3_psign_d_128: 9526 case Intrinsic::x86_avx2_psign_b: 9527 case Intrinsic::x86_avx2_psign_w: 9528 case Intrinsic::x86_avx2_psign_d: 9529 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9530 Op.getOperand(1), Op.getOperand(2)); 9531 case Intrinsic::x86_sse41_insertps: 9532 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9533 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9534 case Intrinsic::x86_avx_vperm2f128_ps_256: 9535 case Intrinsic::x86_avx_vperm2f128_pd_256: 9536 case Intrinsic::x86_avx_vperm2f128_si_256: 9537 case Intrinsic::x86_avx2_vperm2i128: 9538 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9539 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9540 case Intrinsic::x86_avx_vpermil_ps: 9541 case Intrinsic::x86_avx_vpermil_pd: 9542 case Intrinsic::x86_avx_vpermil_ps_256: 9543 case Intrinsic::x86_avx_vpermil_pd_256: 9544 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(), 9545 Op.getOperand(1), Op.getOperand(2)); 9546 9547 // ptest and testp intrinsics. The intrinsic these come from are designed to 9548 // return an integer value, not just an instruction so lower it to the ptest 9549 // or testp pattern and a setcc for the result. 9550 case Intrinsic::x86_sse41_ptestz: 9551 case Intrinsic::x86_sse41_ptestc: 9552 case Intrinsic::x86_sse41_ptestnzc: 9553 case Intrinsic::x86_avx_ptestz_256: 9554 case Intrinsic::x86_avx_ptestc_256: 9555 case Intrinsic::x86_avx_ptestnzc_256: 9556 case Intrinsic::x86_avx_vtestz_ps: 9557 case Intrinsic::x86_avx_vtestc_ps: 9558 case Intrinsic::x86_avx_vtestnzc_ps: 9559 case Intrinsic::x86_avx_vtestz_pd: 9560 case Intrinsic::x86_avx_vtestc_pd: 9561 case Intrinsic::x86_avx_vtestnzc_pd: 9562 case Intrinsic::x86_avx_vtestz_ps_256: 9563 case Intrinsic::x86_avx_vtestc_ps_256: 9564 case Intrinsic::x86_avx_vtestnzc_ps_256: 9565 case Intrinsic::x86_avx_vtestz_pd_256: 9566 case Intrinsic::x86_avx_vtestc_pd_256: 9567 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9568 bool IsTestPacked = false; 9569 unsigned X86CC = 0; 9570 switch (IntNo) { 9571 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9572 case Intrinsic::x86_avx_vtestz_ps: 9573 case Intrinsic::x86_avx_vtestz_pd: 9574 case Intrinsic::x86_avx_vtestz_ps_256: 9575 case Intrinsic::x86_avx_vtestz_pd_256: 9576 IsTestPacked = true; // Fallthrough 9577 case Intrinsic::x86_sse41_ptestz: 9578 case Intrinsic::x86_avx_ptestz_256: 9579 // ZF = 1 9580 X86CC = X86::COND_E; 9581 break; 9582 case Intrinsic::x86_avx_vtestc_ps: 9583 case Intrinsic::x86_avx_vtestc_pd: 9584 case Intrinsic::x86_avx_vtestc_ps_256: 9585 case Intrinsic::x86_avx_vtestc_pd_256: 9586 IsTestPacked = true; // Fallthrough 9587 case Intrinsic::x86_sse41_ptestc: 9588 case Intrinsic::x86_avx_ptestc_256: 9589 // CF = 1 9590 X86CC = X86::COND_B; 9591 break; 9592 case Intrinsic::x86_avx_vtestnzc_ps: 9593 case Intrinsic::x86_avx_vtestnzc_pd: 9594 case Intrinsic::x86_avx_vtestnzc_ps_256: 9595 case Intrinsic::x86_avx_vtestnzc_pd_256: 9596 IsTestPacked = true; // Fallthrough 9597 case Intrinsic::x86_sse41_ptestnzc: 9598 case Intrinsic::x86_avx_ptestnzc_256: 9599 // ZF and CF = 0 9600 X86CC = X86::COND_A; 9601 break; 9602 } 9603 9604 SDValue LHS = Op.getOperand(1); 9605 SDValue RHS = Op.getOperand(2); 9606 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9607 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9608 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9609 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9610 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9611 } 9612 9613 // SSE/AVX shift intrinsics 9614 case Intrinsic::x86_sse2_psll_w: 9615 case Intrinsic::x86_sse2_psll_d: 9616 case Intrinsic::x86_sse2_psll_q: 9617 case Intrinsic::x86_avx2_psll_w: 9618 case Intrinsic::x86_avx2_psll_d: 9619 case Intrinsic::x86_avx2_psll_q: 9620 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9621 Op.getOperand(1), Op.getOperand(2)); 9622 case Intrinsic::x86_sse2_psrl_w: 9623 case Intrinsic::x86_sse2_psrl_d: 9624 case Intrinsic::x86_sse2_psrl_q: 9625 case Intrinsic::x86_avx2_psrl_w: 9626 case Intrinsic::x86_avx2_psrl_d: 9627 case Intrinsic::x86_avx2_psrl_q: 9628 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9629 Op.getOperand(1), Op.getOperand(2)); 9630 case Intrinsic::x86_sse2_psra_w: 9631 case Intrinsic::x86_sse2_psra_d: 9632 case Intrinsic::x86_avx2_psra_w: 9633 case Intrinsic::x86_avx2_psra_d: 9634 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9635 Op.getOperand(1), Op.getOperand(2)); 9636 case Intrinsic::x86_sse2_pslli_w: 9637 case Intrinsic::x86_sse2_pslli_d: 9638 case Intrinsic::x86_sse2_pslli_q: 9639 case Intrinsic::x86_avx2_pslli_w: 9640 case Intrinsic::x86_avx2_pslli_d: 9641 case Intrinsic::x86_avx2_pslli_q: 9642 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9643 Op.getOperand(1), Op.getOperand(2), DAG); 9644 case Intrinsic::x86_sse2_psrli_w: 9645 case Intrinsic::x86_sse2_psrli_d: 9646 case Intrinsic::x86_sse2_psrli_q: 9647 case Intrinsic::x86_avx2_psrli_w: 9648 case Intrinsic::x86_avx2_psrli_d: 9649 case Intrinsic::x86_avx2_psrli_q: 9650 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9651 Op.getOperand(1), Op.getOperand(2), DAG); 9652 case Intrinsic::x86_sse2_psrai_w: 9653 case Intrinsic::x86_sse2_psrai_d: 9654 case Intrinsic::x86_avx2_psrai_w: 9655 case Intrinsic::x86_avx2_psrai_d: 9656 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9657 Op.getOperand(1), Op.getOperand(2), DAG); 9658 // Fix vector shift instructions where the last operand is a non-immediate 9659 // i32 value. 9660 case Intrinsic::x86_mmx_pslli_w: 9661 case Intrinsic::x86_mmx_pslli_d: 9662 case Intrinsic::x86_mmx_pslli_q: 9663 case Intrinsic::x86_mmx_psrli_w: 9664 case Intrinsic::x86_mmx_psrli_d: 9665 case Intrinsic::x86_mmx_psrli_q: 9666 case Intrinsic::x86_mmx_psrai_w: 9667 case Intrinsic::x86_mmx_psrai_d: { 9668 SDValue ShAmt = Op.getOperand(2); 9669 if (isa<ConstantSDNode>(ShAmt)) 9670 return SDValue(); 9671 9672 unsigned NewIntNo = 0; 9673 switch (IntNo) { 9674 case Intrinsic::x86_mmx_pslli_w: 9675 NewIntNo = Intrinsic::x86_mmx_psll_w; 9676 break; 9677 case Intrinsic::x86_mmx_pslli_d: 9678 NewIntNo = Intrinsic::x86_mmx_psll_d; 9679 break; 9680 case Intrinsic::x86_mmx_pslli_q: 9681 NewIntNo = Intrinsic::x86_mmx_psll_q; 9682 break; 9683 case Intrinsic::x86_mmx_psrli_w: 9684 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9685 break; 9686 case Intrinsic::x86_mmx_psrli_d: 9687 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9688 break; 9689 case Intrinsic::x86_mmx_psrli_q: 9690 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9691 break; 9692 case Intrinsic::x86_mmx_psrai_w: 9693 NewIntNo = Intrinsic::x86_mmx_psra_w; 9694 break; 9695 case Intrinsic::x86_mmx_psrai_d: 9696 NewIntNo = Intrinsic::x86_mmx_psra_d; 9697 break; 9698 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9699 } 9700 9701 // The vector shift intrinsics with scalars uses 32b shift amounts but 9702 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9703 // to be zero. 9704 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9705 DAG.getConstant(0, MVT::i32)); 9706// FIXME this must be lowered to get rid of the invalid type. 9707 9708 EVT VT = Op.getValueType(); 9709 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9710 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9711 DAG.getConstant(NewIntNo, MVT::i32), 9712 Op.getOperand(1), ShAmt); 9713 } 9714 } 9715} 9716 9717SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9718 SelectionDAG &DAG) const { 9719 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9720 MFI->setReturnAddressIsTaken(true); 9721 9722 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9723 DebugLoc dl = Op.getDebugLoc(); 9724 9725 if (Depth > 0) { 9726 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9727 SDValue Offset = 9728 DAG.getConstant(TD->getPointerSize(), 9729 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9730 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9731 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9732 FrameAddr, Offset), 9733 MachinePointerInfo(), false, false, false, 0); 9734 } 9735 9736 // Just load the return address. 9737 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9738 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9739 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9740} 9741 9742SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9743 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9744 MFI->setFrameAddressIsTaken(true); 9745 9746 EVT VT = Op.getValueType(); 9747 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9748 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9749 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9750 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9751 while (Depth--) 9752 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9753 MachinePointerInfo(), 9754 false, false, false, 0); 9755 return FrameAddr; 9756} 9757 9758SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9759 SelectionDAG &DAG) const { 9760 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9761} 9762 9763SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9764 MachineFunction &MF = DAG.getMachineFunction(); 9765 SDValue Chain = Op.getOperand(0); 9766 SDValue Offset = Op.getOperand(1); 9767 SDValue Handler = Op.getOperand(2); 9768 DebugLoc dl = Op.getDebugLoc(); 9769 9770 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9771 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9772 getPointerTy()); 9773 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9774 9775 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9776 DAG.getIntPtrConstant(TD->getPointerSize())); 9777 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9778 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9779 false, false, 0); 9780 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9781 MF.getRegInfo().addLiveOut(StoreAddrReg); 9782 9783 return DAG.getNode(X86ISD::EH_RETURN, dl, 9784 MVT::Other, 9785 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9786} 9787 9788SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9789 SelectionDAG &DAG) const { 9790 return Op.getOperand(0); 9791} 9792 9793SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9794 SelectionDAG &DAG) const { 9795 SDValue Root = Op.getOperand(0); 9796 SDValue Trmp = Op.getOperand(1); // trampoline 9797 SDValue FPtr = Op.getOperand(2); // nested function 9798 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9799 DebugLoc dl = Op.getDebugLoc(); 9800 9801 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9802 9803 if (Subtarget->is64Bit()) { 9804 SDValue OutChains[6]; 9805 9806 // Large code-model. 9807 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9808 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9809 9810 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9811 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9812 9813 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9814 9815 // Load the pointer to the nested function into R11. 9816 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9817 SDValue Addr = Trmp; 9818 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9819 Addr, MachinePointerInfo(TrmpAddr), 9820 false, false, 0); 9821 9822 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9823 DAG.getConstant(2, MVT::i64)); 9824 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9825 MachinePointerInfo(TrmpAddr, 2), 9826 false, false, 2); 9827 9828 // Load the 'nest' parameter value into R10. 9829 // R10 is specified in X86CallingConv.td 9830 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9831 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9832 DAG.getConstant(10, MVT::i64)); 9833 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9834 Addr, MachinePointerInfo(TrmpAddr, 10), 9835 false, false, 0); 9836 9837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9838 DAG.getConstant(12, MVT::i64)); 9839 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9840 MachinePointerInfo(TrmpAddr, 12), 9841 false, false, 2); 9842 9843 // Jump to the nested function. 9844 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9846 DAG.getConstant(20, MVT::i64)); 9847 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9848 Addr, MachinePointerInfo(TrmpAddr, 20), 9849 false, false, 0); 9850 9851 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9852 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9853 DAG.getConstant(22, MVT::i64)); 9854 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9855 MachinePointerInfo(TrmpAddr, 22), 9856 false, false, 0); 9857 9858 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9859 } else { 9860 const Function *Func = 9861 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9862 CallingConv::ID CC = Func->getCallingConv(); 9863 unsigned NestReg; 9864 9865 switch (CC) { 9866 default: 9867 llvm_unreachable("Unsupported calling convention"); 9868 case CallingConv::C: 9869 case CallingConv::X86_StdCall: { 9870 // Pass 'nest' parameter in ECX. 9871 // Must be kept in sync with X86CallingConv.td 9872 NestReg = X86::ECX; 9873 9874 // Check that ECX wasn't needed by an 'inreg' parameter. 9875 FunctionType *FTy = Func->getFunctionType(); 9876 const AttrListPtr &Attrs = Func->getAttributes(); 9877 9878 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9879 unsigned InRegCount = 0; 9880 unsigned Idx = 1; 9881 9882 for (FunctionType::param_iterator I = FTy->param_begin(), 9883 E = FTy->param_end(); I != E; ++I, ++Idx) 9884 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9885 // FIXME: should only count parameters that are lowered to integers. 9886 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9887 9888 if (InRegCount > 2) { 9889 report_fatal_error("Nest register in use - reduce number of inreg" 9890 " parameters!"); 9891 } 9892 } 9893 break; 9894 } 9895 case CallingConv::X86_FastCall: 9896 case CallingConv::X86_ThisCall: 9897 case CallingConv::Fast: 9898 // Pass 'nest' parameter in EAX. 9899 // Must be kept in sync with X86CallingConv.td 9900 NestReg = X86::EAX; 9901 break; 9902 } 9903 9904 SDValue OutChains[4]; 9905 SDValue Addr, Disp; 9906 9907 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9908 DAG.getConstant(10, MVT::i32)); 9909 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9910 9911 // This is storing the opcode for MOV32ri. 9912 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9913 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9914 OutChains[0] = DAG.getStore(Root, dl, 9915 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9916 Trmp, MachinePointerInfo(TrmpAddr), 9917 false, false, 0); 9918 9919 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9920 DAG.getConstant(1, MVT::i32)); 9921 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9922 MachinePointerInfo(TrmpAddr, 1), 9923 false, false, 1); 9924 9925 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9926 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9927 DAG.getConstant(5, MVT::i32)); 9928 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9929 MachinePointerInfo(TrmpAddr, 5), 9930 false, false, 1); 9931 9932 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9933 DAG.getConstant(6, MVT::i32)); 9934 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9935 MachinePointerInfo(TrmpAddr, 6), 9936 false, false, 1); 9937 9938 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9939 } 9940} 9941 9942SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9943 SelectionDAG &DAG) const { 9944 /* 9945 The rounding mode is in bits 11:10 of FPSR, and has the following 9946 settings: 9947 00 Round to nearest 9948 01 Round to -inf 9949 10 Round to +inf 9950 11 Round to 0 9951 9952 FLT_ROUNDS, on the other hand, expects the following: 9953 -1 Undefined 9954 0 Round to 0 9955 1 Round to nearest 9956 2 Round to +inf 9957 3 Round to -inf 9958 9959 To perform the conversion, we do: 9960 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9961 */ 9962 9963 MachineFunction &MF = DAG.getMachineFunction(); 9964 const TargetMachine &TM = MF.getTarget(); 9965 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9966 unsigned StackAlignment = TFI.getStackAlignment(); 9967 EVT VT = Op.getValueType(); 9968 DebugLoc DL = Op.getDebugLoc(); 9969 9970 // Save FP Control Word to stack slot 9971 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9972 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9973 9974 9975 MachineMemOperand *MMO = 9976 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9977 MachineMemOperand::MOStore, 2, 2); 9978 9979 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9980 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9981 DAG.getVTList(MVT::Other), 9982 Ops, 2, MVT::i16, MMO); 9983 9984 // Load FP Control Word from stack slot 9985 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9986 MachinePointerInfo(), false, false, false, 0); 9987 9988 // Transform as necessary 9989 SDValue CWD1 = 9990 DAG.getNode(ISD::SRL, DL, MVT::i16, 9991 DAG.getNode(ISD::AND, DL, MVT::i16, 9992 CWD, DAG.getConstant(0x800, MVT::i16)), 9993 DAG.getConstant(11, MVT::i8)); 9994 SDValue CWD2 = 9995 DAG.getNode(ISD::SRL, DL, MVT::i16, 9996 DAG.getNode(ISD::AND, DL, MVT::i16, 9997 CWD, DAG.getConstant(0x400, MVT::i16)), 9998 DAG.getConstant(9, MVT::i8)); 9999 10000 SDValue RetVal = 10001 DAG.getNode(ISD::AND, DL, MVT::i16, 10002 DAG.getNode(ISD::ADD, DL, MVT::i16, 10003 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10004 DAG.getConstant(1, MVT::i16)), 10005 DAG.getConstant(3, MVT::i16)); 10006 10007 10008 return DAG.getNode((VT.getSizeInBits() < 16 ? 10009 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10010} 10011 10012SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10013 EVT VT = Op.getValueType(); 10014 EVT OpVT = VT; 10015 unsigned NumBits = VT.getSizeInBits(); 10016 DebugLoc dl = Op.getDebugLoc(); 10017 10018 Op = Op.getOperand(0); 10019 if (VT == MVT::i8) { 10020 // Zero extend to i32 since there is not an i8 bsr. 10021 OpVT = MVT::i32; 10022 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10023 } 10024 10025 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10026 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10027 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10028 10029 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10030 SDValue Ops[] = { 10031 Op, 10032 DAG.getConstant(NumBits+NumBits-1, OpVT), 10033 DAG.getConstant(X86::COND_E, MVT::i8), 10034 Op.getValue(1) 10035 }; 10036 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10037 10038 // Finally xor with NumBits-1. 10039 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10040 10041 if (VT == MVT::i8) 10042 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10043 return Op; 10044} 10045 10046SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10047 SelectionDAG &DAG) const { 10048 EVT VT = Op.getValueType(); 10049 EVT OpVT = VT; 10050 unsigned NumBits = VT.getSizeInBits(); 10051 DebugLoc dl = Op.getDebugLoc(); 10052 10053 Op = Op.getOperand(0); 10054 if (VT == MVT::i8) { 10055 // Zero extend to i32 since there is not an i8 bsr. 10056 OpVT = MVT::i32; 10057 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10058 } 10059 10060 // Issue a bsr (scan bits in reverse). 10061 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10062 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10063 10064 // And xor with NumBits-1. 10065 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10066 10067 if (VT == MVT::i8) 10068 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10069 return Op; 10070} 10071 10072SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10073 EVT VT = Op.getValueType(); 10074 unsigned NumBits = VT.getSizeInBits(); 10075 DebugLoc dl = Op.getDebugLoc(); 10076 Op = Op.getOperand(0); 10077 10078 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10079 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10080 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10081 10082 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10083 SDValue Ops[] = { 10084 Op, 10085 DAG.getConstant(NumBits, VT), 10086 DAG.getConstant(X86::COND_E, MVT::i8), 10087 Op.getValue(1) 10088 }; 10089 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10090} 10091 10092// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10093// ones, and then concatenate the result back. 10094static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10095 EVT VT = Op.getValueType(); 10096 10097 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10098 "Unsupported value type for operation"); 10099 10100 int NumElems = VT.getVectorNumElements(); 10101 DebugLoc dl = Op.getDebugLoc(); 10102 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10103 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10104 10105 // Extract the LHS vectors 10106 SDValue LHS = Op.getOperand(0); 10107 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10108 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10109 10110 // Extract the RHS vectors 10111 SDValue RHS = Op.getOperand(1); 10112 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10113 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10114 10115 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10116 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10117 10118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10119 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10120 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10121} 10122 10123SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10124 assert(Op.getValueType().getSizeInBits() == 256 && 10125 Op.getValueType().isInteger() && 10126 "Only handle AVX 256-bit vector integer operation"); 10127 return Lower256IntArith(Op, DAG); 10128} 10129 10130SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10131 assert(Op.getValueType().getSizeInBits() == 256 && 10132 Op.getValueType().isInteger() && 10133 "Only handle AVX 256-bit vector integer operation"); 10134 return Lower256IntArith(Op, DAG); 10135} 10136 10137SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10138 EVT VT = Op.getValueType(); 10139 10140 // Decompose 256-bit ops into smaller 128-bit ops. 10141 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10142 return Lower256IntArith(Op, DAG); 10143 10144 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10145 "Only know how to lower V2I64/V4I64 multiply"); 10146 10147 DebugLoc dl = Op.getDebugLoc(); 10148 10149 // Ahi = psrlqi(a, 32); 10150 // Bhi = psrlqi(b, 32); 10151 // 10152 // AloBlo = pmuludq(a, b); 10153 // AloBhi = pmuludq(a, Bhi); 10154 // AhiBlo = pmuludq(Ahi, b); 10155 10156 // AloBhi = psllqi(AloBhi, 32); 10157 // AhiBlo = psllqi(AhiBlo, 32); 10158 // return AloBlo + AloBhi + AhiBlo; 10159 10160 SDValue A = Op.getOperand(0); 10161 SDValue B = Op.getOperand(1); 10162 10163 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10164 10165 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10166 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10167 10168 // Bit cast to 32-bit vectors for MULUDQ 10169 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10170 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10171 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10172 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10173 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10174 10175 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10176 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10177 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10178 10179 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10180 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10181 10182 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10183 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10184} 10185 10186SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10187 10188 EVT VT = Op.getValueType(); 10189 DebugLoc dl = Op.getDebugLoc(); 10190 SDValue R = Op.getOperand(0); 10191 SDValue Amt = Op.getOperand(1); 10192 LLVMContext *Context = DAG.getContext(); 10193 10194 if (!Subtarget->hasSSE2()) 10195 return SDValue(); 10196 10197 // Optimize shl/srl/sra with constant shift amount. 10198 if (isSplatVector(Amt.getNode())) { 10199 SDValue SclrAmt = Amt->getOperand(0); 10200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10201 uint64_t ShiftAmt = C->getZExtValue(); 10202 10203 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10204 (Subtarget->hasAVX2() && 10205 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10206 if (Op.getOpcode() == ISD::SHL) 10207 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10208 DAG.getConstant(ShiftAmt, MVT::i32)); 10209 if (Op.getOpcode() == ISD::SRL) 10210 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10211 DAG.getConstant(ShiftAmt, MVT::i32)); 10212 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10213 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10214 DAG.getConstant(ShiftAmt, MVT::i32)); 10215 } 10216 10217 if (VT == MVT::v16i8) { 10218 if (Op.getOpcode() == ISD::SHL) { 10219 // Make a large shift. 10220 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10221 DAG.getConstant(ShiftAmt, MVT::i32)); 10222 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10223 // Zero out the rightmost bits. 10224 SmallVector<SDValue, 16> V(16, 10225 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10226 MVT::i8)); 10227 return DAG.getNode(ISD::AND, dl, VT, SHL, 10228 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10229 } 10230 if (Op.getOpcode() == ISD::SRL) { 10231 // Make a large shift. 10232 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10233 DAG.getConstant(ShiftAmt, MVT::i32)); 10234 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10235 // Zero out the leftmost bits. 10236 SmallVector<SDValue, 16> V(16, 10237 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10238 MVT::i8)); 10239 return DAG.getNode(ISD::AND, dl, VT, SRL, 10240 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10241 } 10242 if (Op.getOpcode() == ISD::SRA) { 10243 if (ShiftAmt == 7) { 10244 // R s>> 7 === R s< 0 10245 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10246 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10247 } 10248 10249 // R s>> a === ((R u>> a) ^ m) - m 10250 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10251 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10252 MVT::i8)); 10253 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10254 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10255 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10256 return Res; 10257 } 10258 } 10259 10260 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10261 if (Op.getOpcode() == ISD::SHL) { 10262 // Make a large shift. 10263 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10264 DAG.getConstant(ShiftAmt, MVT::i32)); 10265 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10266 // Zero out the rightmost bits. 10267 SmallVector<SDValue, 32> V(32, 10268 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10269 MVT::i8)); 10270 return DAG.getNode(ISD::AND, dl, VT, SHL, 10271 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10272 } 10273 if (Op.getOpcode() == ISD::SRL) { 10274 // Make a large shift. 10275 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10276 DAG.getConstant(ShiftAmt, MVT::i32)); 10277 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10278 // Zero out the leftmost bits. 10279 SmallVector<SDValue, 32> V(32, 10280 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10281 MVT::i8)); 10282 return DAG.getNode(ISD::AND, dl, VT, SRL, 10283 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10284 } 10285 if (Op.getOpcode() == ISD::SRA) { 10286 if (ShiftAmt == 7) { 10287 // R s>> 7 === R s< 0 10288 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10289 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10290 } 10291 10292 // R s>> a === ((R u>> a) ^ m) - m 10293 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10294 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10295 MVT::i8)); 10296 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10297 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10298 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10299 return Res; 10300 } 10301 } 10302 } 10303 } 10304 10305 // Lower SHL with variable shift amount. 10306 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10307 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10308 DAG.getConstant(23, MVT::i32)); 10309 10310 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10311 Constant *C = ConstantDataVector::get(*Context, CV); 10312 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10313 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10314 MachinePointerInfo::getConstantPool(), 10315 false, false, false, 16); 10316 10317 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10318 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10319 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10320 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10321 } 10322 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10323 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10324 10325 // a = a << 5; 10326 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10327 DAG.getConstant(5, MVT::i32)); 10328 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10329 10330 // Turn 'a' into a mask suitable for VSELECT 10331 SDValue VSelM = DAG.getConstant(0x80, VT); 10332 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10333 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10334 10335 SDValue CM1 = DAG.getConstant(0x0f, VT); 10336 SDValue CM2 = DAG.getConstant(0x3f, VT); 10337 10338 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10339 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10340 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10341 DAG.getConstant(4, MVT::i32), DAG); 10342 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10343 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10344 10345 // a += a 10346 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10347 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10348 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10349 10350 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10351 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10352 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10353 DAG.getConstant(2, MVT::i32), DAG); 10354 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10355 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10356 10357 // a += a 10358 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10359 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10360 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10361 10362 // return VSELECT(r, r+r, a); 10363 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10364 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10365 return R; 10366 } 10367 10368 // Decompose 256-bit shifts into smaller 128-bit shifts. 10369 if (VT.getSizeInBits() == 256) { 10370 unsigned NumElems = VT.getVectorNumElements(); 10371 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10372 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10373 10374 // Extract the two vectors 10375 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10376 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10377 DAG, dl); 10378 10379 // Recreate the shift amount vectors 10380 SDValue Amt1, Amt2; 10381 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10382 // Constant shift amount 10383 SmallVector<SDValue, 4> Amt1Csts; 10384 SmallVector<SDValue, 4> Amt2Csts; 10385 for (unsigned i = 0; i != NumElems/2; ++i) 10386 Amt1Csts.push_back(Amt->getOperand(i)); 10387 for (unsigned i = NumElems/2; i != NumElems; ++i) 10388 Amt2Csts.push_back(Amt->getOperand(i)); 10389 10390 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10391 &Amt1Csts[0], NumElems/2); 10392 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10393 &Amt2Csts[0], NumElems/2); 10394 } else { 10395 // Variable shift amount 10396 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10397 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10398 DAG, dl); 10399 } 10400 10401 // Issue new vector shifts for the smaller types 10402 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10403 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10404 10405 // Concatenate the result back 10406 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10407 } 10408 10409 return SDValue(); 10410} 10411 10412SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10413 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10414 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10415 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10416 // has only one use. 10417 SDNode *N = Op.getNode(); 10418 SDValue LHS = N->getOperand(0); 10419 SDValue RHS = N->getOperand(1); 10420 unsigned BaseOp = 0; 10421 unsigned Cond = 0; 10422 DebugLoc DL = Op.getDebugLoc(); 10423 switch (Op.getOpcode()) { 10424 default: llvm_unreachable("Unknown ovf instruction!"); 10425 case ISD::SADDO: 10426 // A subtract of one will be selected as a INC. Note that INC doesn't 10427 // set CF, so we can't do this for UADDO. 10428 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10429 if (C->isOne()) { 10430 BaseOp = X86ISD::INC; 10431 Cond = X86::COND_O; 10432 break; 10433 } 10434 BaseOp = X86ISD::ADD; 10435 Cond = X86::COND_O; 10436 break; 10437 case ISD::UADDO: 10438 BaseOp = X86ISD::ADD; 10439 Cond = X86::COND_B; 10440 break; 10441 case ISD::SSUBO: 10442 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10443 // set CF, so we can't do this for USUBO. 10444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10445 if (C->isOne()) { 10446 BaseOp = X86ISD::DEC; 10447 Cond = X86::COND_O; 10448 break; 10449 } 10450 BaseOp = X86ISD::SUB; 10451 Cond = X86::COND_O; 10452 break; 10453 case ISD::USUBO: 10454 BaseOp = X86ISD::SUB; 10455 Cond = X86::COND_B; 10456 break; 10457 case ISD::SMULO: 10458 BaseOp = X86ISD::SMUL; 10459 Cond = X86::COND_O; 10460 break; 10461 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10462 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10463 MVT::i32); 10464 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10465 10466 SDValue SetCC = 10467 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10468 DAG.getConstant(X86::COND_O, MVT::i32), 10469 SDValue(Sum.getNode(), 2)); 10470 10471 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10472 } 10473 } 10474 10475 // Also sets EFLAGS. 10476 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10477 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10478 10479 SDValue SetCC = 10480 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10481 DAG.getConstant(Cond, MVT::i32), 10482 SDValue(Sum.getNode(), 1)); 10483 10484 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10485} 10486 10487SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10488 SelectionDAG &DAG) const { 10489 DebugLoc dl = Op.getDebugLoc(); 10490 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10491 EVT VT = Op.getValueType(); 10492 10493 if (!Subtarget->hasSSE2() || !VT.isVector()) 10494 return SDValue(); 10495 10496 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10497 ExtraVT.getScalarType().getSizeInBits(); 10498 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10499 10500 switch (VT.getSimpleVT().SimpleTy) { 10501 default: return SDValue(); 10502 case MVT::v8i32: 10503 case MVT::v16i16: 10504 if (!Subtarget->hasAVX()) 10505 return SDValue(); 10506 if (!Subtarget->hasAVX2()) { 10507 // needs to be split 10508 int NumElems = VT.getVectorNumElements(); 10509 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10510 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10511 10512 // Extract the LHS vectors 10513 SDValue LHS = Op.getOperand(0); 10514 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10515 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10516 10517 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10518 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10519 10520 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10521 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10522 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10523 ExtraNumElems/2); 10524 SDValue Extra = DAG.getValueType(ExtraVT); 10525 10526 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10527 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10528 10529 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10530 } 10531 // fall through 10532 case MVT::v4i32: 10533 case MVT::v8i16: { 10534 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10535 Op.getOperand(0), ShAmt, DAG); 10536 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10537 } 10538 } 10539} 10540 10541 10542SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10543 DebugLoc dl = Op.getDebugLoc(); 10544 10545 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10546 // There isn't any reason to disable it if the target processor supports it. 10547 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10548 SDValue Chain = Op.getOperand(0); 10549 SDValue Zero = DAG.getConstant(0, MVT::i32); 10550 SDValue Ops[] = { 10551 DAG.getRegister(X86::ESP, MVT::i32), // Base 10552 DAG.getTargetConstant(1, MVT::i8), // Scale 10553 DAG.getRegister(0, MVT::i32), // Index 10554 DAG.getTargetConstant(0, MVT::i32), // Disp 10555 DAG.getRegister(0, MVT::i32), // Segment. 10556 Zero, 10557 Chain 10558 }; 10559 SDNode *Res = 10560 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10561 array_lengthof(Ops)); 10562 return SDValue(Res, 0); 10563 } 10564 10565 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10566 if (!isDev) 10567 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10568 10569 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10570 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10571 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10572 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10573 10574 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10575 if (!Op1 && !Op2 && !Op3 && Op4) 10576 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10577 10578 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10579 if (Op1 && !Op2 && !Op3 && !Op4) 10580 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10581 10582 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10583 // (MFENCE)>; 10584 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10585} 10586 10587SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10588 SelectionDAG &DAG) const { 10589 DebugLoc dl = Op.getDebugLoc(); 10590 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10591 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10592 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10593 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10594 10595 // The only fence that needs an instruction is a sequentially-consistent 10596 // cross-thread fence. 10597 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10598 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10599 // no-sse2). There isn't any reason to disable it if the target processor 10600 // supports it. 10601 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10602 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10603 10604 SDValue Chain = Op.getOperand(0); 10605 SDValue Zero = DAG.getConstant(0, MVT::i32); 10606 SDValue Ops[] = { 10607 DAG.getRegister(X86::ESP, MVT::i32), // Base 10608 DAG.getTargetConstant(1, MVT::i8), // Scale 10609 DAG.getRegister(0, MVT::i32), // Index 10610 DAG.getTargetConstant(0, MVT::i32), // Disp 10611 DAG.getRegister(0, MVT::i32), // Segment. 10612 Zero, 10613 Chain 10614 }; 10615 SDNode *Res = 10616 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10617 array_lengthof(Ops)); 10618 return SDValue(Res, 0); 10619 } 10620 10621 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10622 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10623} 10624 10625 10626SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10627 EVT T = Op.getValueType(); 10628 DebugLoc DL = Op.getDebugLoc(); 10629 unsigned Reg = 0; 10630 unsigned size = 0; 10631 switch(T.getSimpleVT().SimpleTy) { 10632 default: llvm_unreachable("Invalid value type!"); 10633 case MVT::i8: Reg = X86::AL; size = 1; break; 10634 case MVT::i16: Reg = X86::AX; size = 2; break; 10635 case MVT::i32: Reg = X86::EAX; size = 4; break; 10636 case MVT::i64: 10637 assert(Subtarget->is64Bit() && "Node not type legal!"); 10638 Reg = X86::RAX; size = 8; 10639 break; 10640 } 10641 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10642 Op.getOperand(2), SDValue()); 10643 SDValue Ops[] = { cpIn.getValue(0), 10644 Op.getOperand(1), 10645 Op.getOperand(3), 10646 DAG.getTargetConstant(size, MVT::i8), 10647 cpIn.getValue(1) }; 10648 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10649 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10650 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10651 Ops, 5, T, MMO); 10652 SDValue cpOut = 10653 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10654 return cpOut; 10655} 10656 10657SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10658 SelectionDAG &DAG) const { 10659 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10660 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10661 SDValue TheChain = Op.getOperand(0); 10662 DebugLoc dl = Op.getDebugLoc(); 10663 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10664 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10665 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10666 rax.getValue(2)); 10667 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10668 DAG.getConstant(32, MVT::i8)); 10669 SDValue Ops[] = { 10670 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10671 rdx.getValue(1) 10672 }; 10673 return DAG.getMergeValues(Ops, 2, dl); 10674} 10675 10676SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10677 SelectionDAG &DAG) const { 10678 EVT SrcVT = Op.getOperand(0).getValueType(); 10679 EVT DstVT = Op.getValueType(); 10680 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10681 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10682 assert((DstVT == MVT::i64 || 10683 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10684 "Unexpected custom BITCAST"); 10685 // i64 <=> MMX conversions are Legal. 10686 if (SrcVT==MVT::i64 && DstVT.isVector()) 10687 return Op; 10688 if (DstVT==MVT::i64 && SrcVT.isVector()) 10689 return Op; 10690 // MMX <=> MMX conversions are Legal. 10691 if (SrcVT.isVector() && DstVT.isVector()) 10692 return Op; 10693 // All other conversions need to be expanded. 10694 return SDValue(); 10695} 10696 10697SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10698 SDNode *Node = Op.getNode(); 10699 DebugLoc dl = Node->getDebugLoc(); 10700 EVT T = Node->getValueType(0); 10701 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10702 DAG.getConstant(0, T), Node->getOperand(2)); 10703 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10704 cast<AtomicSDNode>(Node)->getMemoryVT(), 10705 Node->getOperand(0), 10706 Node->getOperand(1), negOp, 10707 cast<AtomicSDNode>(Node)->getSrcValue(), 10708 cast<AtomicSDNode>(Node)->getAlignment(), 10709 cast<AtomicSDNode>(Node)->getOrdering(), 10710 cast<AtomicSDNode>(Node)->getSynchScope()); 10711} 10712 10713static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10714 SDNode *Node = Op.getNode(); 10715 DebugLoc dl = Node->getDebugLoc(); 10716 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10717 10718 // Convert seq_cst store -> xchg 10719 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10720 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10721 // (The only way to get a 16-byte store is cmpxchg16b) 10722 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10723 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10724 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10725 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10726 cast<AtomicSDNode>(Node)->getMemoryVT(), 10727 Node->getOperand(0), 10728 Node->getOperand(1), Node->getOperand(2), 10729 cast<AtomicSDNode>(Node)->getMemOperand(), 10730 cast<AtomicSDNode>(Node)->getOrdering(), 10731 cast<AtomicSDNode>(Node)->getSynchScope()); 10732 return Swap.getValue(1); 10733 } 10734 // Other atomic stores have a simple pattern. 10735 return Op; 10736} 10737 10738static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10739 EVT VT = Op.getNode()->getValueType(0); 10740 10741 // Let legalize expand this if it isn't a legal type yet. 10742 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10743 return SDValue(); 10744 10745 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10746 10747 unsigned Opc; 10748 bool ExtraOp = false; 10749 switch (Op.getOpcode()) { 10750 default: llvm_unreachable("Invalid code"); 10751 case ISD::ADDC: Opc = X86ISD::ADD; break; 10752 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10753 case ISD::SUBC: Opc = X86ISD::SUB; break; 10754 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10755 } 10756 10757 if (!ExtraOp) 10758 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10759 Op.getOperand(1)); 10760 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10761 Op.getOperand(1), Op.getOperand(2)); 10762} 10763 10764/// LowerOperation - Provide custom lowering hooks for some operations. 10765/// 10766SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10767 switch (Op.getOpcode()) { 10768 default: llvm_unreachable("Should not custom lower this!"); 10769 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10770 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10771 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10772 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10773 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10774 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10775 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10776 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10777 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10778 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10779 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10780 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10781 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10782 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10783 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10784 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10785 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10786 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10787 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10788 case ISD::SHL_PARTS: 10789 case ISD::SRA_PARTS: 10790 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10791 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10792 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10793 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10794 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10795 case ISD::FABS: return LowerFABS(Op, DAG); 10796 case ISD::FNEG: return LowerFNEG(Op, DAG); 10797 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10798 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10799 case ISD::SETCC: return LowerSETCC(Op, DAG); 10800 case ISD::SELECT: return LowerSELECT(Op, DAG); 10801 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10802 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10803 case ISD::VASTART: return LowerVASTART(Op, DAG); 10804 case ISD::VAARG: return LowerVAARG(Op, DAG); 10805 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10806 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10807 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10808 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10809 case ISD::FRAME_TO_ARGS_OFFSET: 10810 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10811 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10812 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10813 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10814 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10815 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10816 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10817 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10818 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10819 case ISD::MUL: return LowerMUL(Op, DAG); 10820 case ISD::SRA: 10821 case ISD::SRL: 10822 case ISD::SHL: return LowerShift(Op, DAG); 10823 case ISD::SADDO: 10824 case ISD::UADDO: 10825 case ISD::SSUBO: 10826 case ISD::USUBO: 10827 case ISD::SMULO: 10828 case ISD::UMULO: return LowerXALUO(Op, DAG); 10829 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10830 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10831 case ISD::ADDC: 10832 case ISD::ADDE: 10833 case ISD::SUBC: 10834 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10835 case ISD::ADD: return LowerADD(Op, DAG); 10836 case ISD::SUB: return LowerSUB(Op, DAG); 10837 } 10838} 10839 10840static void ReplaceATOMIC_LOAD(SDNode *Node, 10841 SmallVectorImpl<SDValue> &Results, 10842 SelectionDAG &DAG) { 10843 DebugLoc dl = Node->getDebugLoc(); 10844 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10845 10846 // Convert wide load -> cmpxchg8b/cmpxchg16b 10847 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10848 // (The only way to get a 16-byte load is cmpxchg16b) 10849 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10850 SDValue Zero = DAG.getConstant(0, VT); 10851 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10852 Node->getOperand(0), 10853 Node->getOperand(1), Zero, Zero, 10854 cast<AtomicSDNode>(Node)->getMemOperand(), 10855 cast<AtomicSDNode>(Node)->getOrdering(), 10856 cast<AtomicSDNode>(Node)->getSynchScope()); 10857 Results.push_back(Swap.getValue(0)); 10858 Results.push_back(Swap.getValue(1)); 10859} 10860 10861void X86TargetLowering:: 10862ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10863 SelectionDAG &DAG, unsigned NewOp) const { 10864 DebugLoc dl = Node->getDebugLoc(); 10865 assert (Node->getValueType(0) == MVT::i64 && 10866 "Only know how to expand i64 atomics"); 10867 10868 SDValue Chain = Node->getOperand(0); 10869 SDValue In1 = Node->getOperand(1); 10870 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10871 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10872 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10873 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10874 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10875 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10876 SDValue Result = 10877 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10878 cast<MemSDNode>(Node)->getMemOperand()); 10879 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10880 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10881 Results.push_back(Result.getValue(2)); 10882} 10883 10884/// ReplaceNodeResults - Replace a node with an illegal result type 10885/// with a new node built out of custom code. 10886void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10887 SmallVectorImpl<SDValue>&Results, 10888 SelectionDAG &DAG) const { 10889 DebugLoc dl = N->getDebugLoc(); 10890 switch (N->getOpcode()) { 10891 default: 10892 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10893 case ISD::SIGN_EXTEND_INREG: 10894 case ISD::ADDC: 10895 case ISD::ADDE: 10896 case ISD::SUBC: 10897 case ISD::SUBE: 10898 // We don't want to expand or promote these. 10899 return; 10900 case ISD::FP_TO_SINT: 10901 case ISD::FP_TO_UINT: { 10902 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 10903 10904 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 10905 return; 10906 10907 std::pair<SDValue,SDValue> Vals = 10908 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 10909 SDValue FIST = Vals.first, StackSlot = Vals.second; 10910 if (FIST.getNode() != 0) { 10911 EVT VT = N->getValueType(0); 10912 // Return a load from the stack slot. 10913 if (StackSlot.getNode() != 0) 10914 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10915 MachinePointerInfo(), 10916 false, false, false, 0)); 10917 else 10918 Results.push_back(FIST); 10919 } 10920 return; 10921 } 10922 case ISD::READCYCLECOUNTER: { 10923 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10924 SDValue TheChain = N->getOperand(0); 10925 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10926 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10927 rd.getValue(1)); 10928 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10929 eax.getValue(2)); 10930 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10931 SDValue Ops[] = { eax, edx }; 10932 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10933 Results.push_back(edx.getValue(1)); 10934 return; 10935 } 10936 case ISD::ATOMIC_CMP_SWAP: { 10937 EVT T = N->getValueType(0); 10938 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10939 bool Regs64bit = T == MVT::i128; 10940 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10941 SDValue cpInL, cpInH; 10942 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10943 DAG.getConstant(0, HalfT)); 10944 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10945 DAG.getConstant(1, HalfT)); 10946 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10947 Regs64bit ? X86::RAX : X86::EAX, 10948 cpInL, SDValue()); 10949 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10950 Regs64bit ? X86::RDX : X86::EDX, 10951 cpInH, cpInL.getValue(1)); 10952 SDValue swapInL, swapInH; 10953 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10954 DAG.getConstant(0, HalfT)); 10955 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10956 DAG.getConstant(1, HalfT)); 10957 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10958 Regs64bit ? X86::RBX : X86::EBX, 10959 swapInL, cpInH.getValue(1)); 10960 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10961 Regs64bit ? X86::RCX : X86::ECX, 10962 swapInH, swapInL.getValue(1)); 10963 SDValue Ops[] = { swapInH.getValue(0), 10964 N->getOperand(1), 10965 swapInH.getValue(1) }; 10966 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10967 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10968 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10969 X86ISD::LCMPXCHG8_DAG; 10970 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10971 Ops, 3, T, MMO); 10972 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10973 Regs64bit ? X86::RAX : X86::EAX, 10974 HalfT, Result.getValue(1)); 10975 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10976 Regs64bit ? X86::RDX : X86::EDX, 10977 HalfT, cpOutL.getValue(2)); 10978 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10979 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10980 Results.push_back(cpOutH.getValue(1)); 10981 return; 10982 } 10983 case ISD::ATOMIC_LOAD_ADD: 10984 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10985 return; 10986 case ISD::ATOMIC_LOAD_AND: 10987 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10988 return; 10989 case ISD::ATOMIC_LOAD_NAND: 10990 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10991 return; 10992 case ISD::ATOMIC_LOAD_OR: 10993 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10994 return; 10995 case ISD::ATOMIC_LOAD_SUB: 10996 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10997 return; 10998 case ISD::ATOMIC_LOAD_XOR: 10999 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11000 return; 11001 case ISD::ATOMIC_SWAP: 11002 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11003 return; 11004 case ISD::ATOMIC_LOAD: 11005 ReplaceATOMIC_LOAD(N, Results, DAG); 11006 } 11007} 11008 11009const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11010 switch (Opcode) { 11011 default: return NULL; 11012 case X86ISD::BSF: return "X86ISD::BSF"; 11013 case X86ISD::BSR: return "X86ISD::BSR"; 11014 case X86ISD::SHLD: return "X86ISD::SHLD"; 11015 case X86ISD::SHRD: return "X86ISD::SHRD"; 11016 case X86ISD::FAND: return "X86ISD::FAND"; 11017 case X86ISD::FOR: return "X86ISD::FOR"; 11018 case X86ISD::FXOR: return "X86ISD::FXOR"; 11019 case X86ISD::FSRL: return "X86ISD::FSRL"; 11020 case X86ISD::FILD: return "X86ISD::FILD"; 11021 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11022 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11023 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11024 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11025 case X86ISD::FLD: return "X86ISD::FLD"; 11026 case X86ISD::FST: return "X86ISD::FST"; 11027 case X86ISD::CALL: return "X86ISD::CALL"; 11028 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11029 case X86ISD::BT: return "X86ISD::BT"; 11030 case X86ISD::CMP: return "X86ISD::CMP"; 11031 case X86ISD::COMI: return "X86ISD::COMI"; 11032 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11033 case X86ISD::SETCC: return "X86ISD::SETCC"; 11034 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11035 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11036 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11037 case X86ISD::CMOV: return "X86ISD::CMOV"; 11038 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11039 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11040 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11041 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11042 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11043 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11044 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11045 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11046 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11047 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11048 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11049 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11050 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11051 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11052 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11053 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11054 case X86ISD::HADD: return "X86ISD::HADD"; 11055 case X86ISD::HSUB: return "X86ISD::HSUB"; 11056 case X86ISD::FHADD: return "X86ISD::FHADD"; 11057 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11058 case X86ISD::FMAX: return "X86ISD::FMAX"; 11059 case X86ISD::FMIN: return "X86ISD::FMIN"; 11060 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11061 case X86ISD::FRCP: return "X86ISD::FRCP"; 11062 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11063 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11064 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11065 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11066 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11067 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11068 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11069 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11070 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11071 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11072 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11073 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11074 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11075 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11076 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11077 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11078 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11079 case X86ISD::VSHL: return "X86ISD::VSHL"; 11080 case X86ISD::VSRL: return "X86ISD::VSRL"; 11081 case X86ISD::VSRA: return "X86ISD::VSRA"; 11082 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11083 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11084 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11085 case X86ISD::CMPP: return "X86ISD::CMPP"; 11086 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11087 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11088 case X86ISD::ADD: return "X86ISD::ADD"; 11089 case X86ISD::SUB: return "X86ISD::SUB"; 11090 case X86ISD::ADC: return "X86ISD::ADC"; 11091 case X86ISD::SBB: return "X86ISD::SBB"; 11092 case X86ISD::SMUL: return "X86ISD::SMUL"; 11093 case X86ISD::UMUL: return "X86ISD::UMUL"; 11094 case X86ISD::INC: return "X86ISD::INC"; 11095 case X86ISD::DEC: return "X86ISD::DEC"; 11096 case X86ISD::OR: return "X86ISD::OR"; 11097 case X86ISD::XOR: return "X86ISD::XOR"; 11098 case X86ISD::AND: return "X86ISD::AND"; 11099 case X86ISD::ANDN: return "X86ISD::ANDN"; 11100 case X86ISD::BLSI: return "X86ISD::BLSI"; 11101 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11102 case X86ISD::BLSR: return "X86ISD::BLSR"; 11103 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11104 case X86ISD::PTEST: return "X86ISD::PTEST"; 11105 case X86ISD::TESTP: return "X86ISD::TESTP"; 11106 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11107 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11108 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11109 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11110 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11111 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11112 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11113 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11114 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11115 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11116 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11117 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11118 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11119 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11120 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11121 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11122 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11123 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11124 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11125 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11126 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11127 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11128 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11129 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11130 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11131 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11132 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11133 } 11134} 11135 11136// isLegalAddressingMode - Return true if the addressing mode represented 11137// by AM is legal for this target, for a load/store of the specified type. 11138bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11139 Type *Ty) const { 11140 // X86 supports extremely general addressing modes. 11141 CodeModel::Model M = getTargetMachine().getCodeModel(); 11142 Reloc::Model R = getTargetMachine().getRelocationModel(); 11143 11144 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11145 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11146 return false; 11147 11148 if (AM.BaseGV) { 11149 unsigned GVFlags = 11150 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11151 11152 // If a reference to this global requires an extra load, we can't fold it. 11153 if (isGlobalStubReference(GVFlags)) 11154 return false; 11155 11156 // If BaseGV requires a register for the PIC base, we cannot also have a 11157 // BaseReg specified. 11158 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11159 return false; 11160 11161 // If lower 4G is not available, then we must use rip-relative addressing. 11162 if ((M != CodeModel::Small || R != Reloc::Static) && 11163 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11164 return false; 11165 } 11166 11167 switch (AM.Scale) { 11168 case 0: 11169 case 1: 11170 case 2: 11171 case 4: 11172 case 8: 11173 // These scales always work. 11174 break; 11175 case 3: 11176 case 5: 11177 case 9: 11178 // These scales are formed with basereg+scalereg. Only accept if there is 11179 // no basereg yet. 11180 if (AM.HasBaseReg) 11181 return false; 11182 break; 11183 default: // Other stuff never works. 11184 return false; 11185 } 11186 11187 return true; 11188} 11189 11190 11191bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11192 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11193 return false; 11194 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11195 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11196 if (NumBits1 <= NumBits2) 11197 return false; 11198 return true; 11199} 11200 11201bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11202 if (!VT1.isInteger() || !VT2.isInteger()) 11203 return false; 11204 unsigned NumBits1 = VT1.getSizeInBits(); 11205 unsigned NumBits2 = VT2.getSizeInBits(); 11206 if (NumBits1 <= NumBits2) 11207 return false; 11208 return true; 11209} 11210 11211bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11212 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11213 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11214} 11215 11216bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11217 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11218 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11219} 11220 11221bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11222 // i16 instructions are longer (0x66 prefix) and potentially slower. 11223 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11224} 11225 11226/// isShuffleMaskLegal - Targets can use this to indicate that they only 11227/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11228/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11229/// are assumed to be legal. 11230bool 11231X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11232 EVT VT) const { 11233 // Very little shuffling can be done for 64-bit vectors right now. 11234 if (VT.getSizeInBits() == 64) 11235 return false; 11236 11237 // FIXME: pshufb, blends, shifts. 11238 return (VT.getVectorNumElements() == 2 || 11239 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11240 isMOVLMask(M, VT) || 11241 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11242 isPSHUFDMask(M, VT) || 11243 isPSHUFHWMask(M, VT) || 11244 isPSHUFLWMask(M, VT) || 11245 isPALIGNRMask(M, VT, Subtarget) || 11246 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11247 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11248 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11249 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11250} 11251 11252bool 11253X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11254 EVT VT) const { 11255 unsigned NumElts = VT.getVectorNumElements(); 11256 // FIXME: This collection of masks seems suspect. 11257 if (NumElts == 2) 11258 return true; 11259 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11260 return (isMOVLMask(Mask, VT) || 11261 isCommutedMOVLMask(Mask, VT, true) || 11262 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11263 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11264 } 11265 return false; 11266} 11267 11268//===----------------------------------------------------------------------===// 11269// X86 Scheduler Hooks 11270//===----------------------------------------------------------------------===// 11271 11272// private utility function 11273MachineBasicBlock * 11274X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11275 MachineBasicBlock *MBB, 11276 unsigned regOpc, 11277 unsigned immOpc, 11278 unsigned LoadOpc, 11279 unsigned CXchgOpc, 11280 unsigned notOpc, 11281 unsigned EAXreg, 11282 const TargetRegisterClass *RC, 11283 bool invSrc) const { 11284 // For the atomic bitwise operator, we generate 11285 // thisMBB: 11286 // newMBB: 11287 // ld t1 = [bitinstr.addr] 11288 // op t2 = t1, [bitinstr.val] 11289 // mov EAX = t1 11290 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11291 // bz newMBB 11292 // fallthrough -->nextMBB 11293 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11294 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11295 MachineFunction::iterator MBBIter = MBB; 11296 ++MBBIter; 11297 11298 /// First build the CFG 11299 MachineFunction *F = MBB->getParent(); 11300 MachineBasicBlock *thisMBB = MBB; 11301 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11302 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11303 F->insert(MBBIter, newMBB); 11304 F->insert(MBBIter, nextMBB); 11305 11306 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11307 nextMBB->splice(nextMBB->begin(), thisMBB, 11308 llvm::next(MachineBasicBlock::iterator(bInstr)), 11309 thisMBB->end()); 11310 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11311 11312 // Update thisMBB to fall through to newMBB 11313 thisMBB->addSuccessor(newMBB); 11314 11315 // newMBB jumps to itself and fall through to nextMBB 11316 newMBB->addSuccessor(nextMBB); 11317 newMBB->addSuccessor(newMBB); 11318 11319 // Insert instructions into newMBB based on incoming instruction 11320 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11321 "unexpected number of operands"); 11322 DebugLoc dl = bInstr->getDebugLoc(); 11323 MachineOperand& destOper = bInstr->getOperand(0); 11324 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11325 int numArgs = bInstr->getNumOperands() - 1; 11326 for (int i=0; i < numArgs; ++i) 11327 argOpers[i] = &bInstr->getOperand(i+1); 11328 11329 // x86 address has 4 operands: base, index, scale, and displacement 11330 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11331 int valArgIndx = lastAddrIndx + 1; 11332 11333 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11334 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11335 for (int i=0; i <= lastAddrIndx; ++i) 11336 (*MIB).addOperand(*argOpers[i]); 11337 11338 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11339 if (invSrc) { 11340 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11341 } 11342 else 11343 tt = t1; 11344 11345 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11346 assert((argOpers[valArgIndx]->isReg() || 11347 argOpers[valArgIndx]->isImm()) && 11348 "invalid operand"); 11349 if (argOpers[valArgIndx]->isReg()) 11350 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11351 else 11352 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11353 MIB.addReg(tt); 11354 (*MIB).addOperand(*argOpers[valArgIndx]); 11355 11356 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11357 MIB.addReg(t1); 11358 11359 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11360 for (int i=0; i <= lastAddrIndx; ++i) 11361 (*MIB).addOperand(*argOpers[i]); 11362 MIB.addReg(t2); 11363 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11364 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11365 bInstr->memoperands_end()); 11366 11367 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11368 MIB.addReg(EAXreg); 11369 11370 // insert branch 11371 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11372 11373 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11374 return nextMBB; 11375} 11376 11377// private utility function: 64 bit atomics on 32 bit host. 11378MachineBasicBlock * 11379X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11380 MachineBasicBlock *MBB, 11381 unsigned regOpcL, 11382 unsigned regOpcH, 11383 unsigned immOpcL, 11384 unsigned immOpcH, 11385 bool invSrc) const { 11386 // For the atomic bitwise operator, we generate 11387 // thisMBB (instructions are in pairs, except cmpxchg8b) 11388 // ld t1,t2 = [bitinstr.addr] 11389 // newMBB: 11390 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11391 // op t5, t6 <- out1, out2, [bitinstr.val] 11392 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11393 // mov ECX, EBX <- t5, t6 11394 // mov EAX, EDX <- t1, t2 11395 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11396 // mov t3, t4 <- EAX, EDX 11397 // bz newMBB 11398 // result in out1, out2 11399 // fallthrough -->nextMBB 11400 11401 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11402 const unsigned LoadOpc = X86::MOV32rm; 11403 const unsigned NotOpc = X86::NOT32r; 11404 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11405 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11406 MachineFunction::iterator MBBIter = MBB; 11407 ++MBBIter; 11408 11409 /// First build the CFG 11410 MachineFunction *F = MBB->getParent(); 11411 MachineBasicBlock *thisMBB = MBB; 11412 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11413 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11414 F->insert(MBBIter, newMBB); 11415 F->insert(MBBIter, nextMBB); 11416 11417 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11418 nextMBB->splice(nextMBB->begin(), thisMBB, 11419 llvm::next(MachineBasicBlock::iterator(bInstr)), 11420 thisMBB->end()); 11421 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11422 11423 // Update thisMBB to fall through to newMBB 11424 thisMBB->addSuccessor(newMBB); 11425 11426 // newMBB jumps to itself and fall through to nextMBB 11427 newMBB->addSuccessor(nextMBB); 11428 newMBB->addSuccessor(newMBB); 11429 11430 DebugLoc dl = bInstr->getDebugLoc(); 11431 // Insert instructions into newMBB based on incoming instruction 11432 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11433 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11434 "unexpected number of operands"); 11435 MachineOperand& dest1Oper = bInstr->getOperand(0); 11436 MachineOperand& dest2Oper = bInstr->getOperand(1); 11437 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11438 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11439 argOpers[i] = &bInstr->getOperand(i+2); 11440 11441 // We use some of the operands multiple times, so conservatively just 11442 // clear any kill flags that might be present. 11443 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11444 argOpers[i]->setIsKill(false); 11445 } 11446 11447 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11448 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11449 11450 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11451 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11452 for (int i=0; i <= lastAddrIndx; ++i) 11453 (*MIB).addOperand(*argOpers[i]); 11454 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11455 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11456 // add 4 to displacement. 11457 for (int i=0; i <= lastAddrIndx-2; ++i) 11458 (*MIB).addOperand(*argOpers[i]); 11459 MachineOperand newOp3 = *(argOpers[3]); 11460 if (newOp3.isImm()) 11461 newOp3.setImm(newOp3.getImm()+4); 11462 else 11463 newOp3.setOffset(newOp3.getOffset()+4); 11464 (*MIB).addOperand(newOp3); 11465 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11466 11467 // t3/4 are defined later, at the bottom of the loop 11468 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11469 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11470 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11471 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11472 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11473 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11474 11475 // The subsequent operations should be using the destination registers of 11476 //the PHI instructions. 11477 if (invSrc) { 11478 t1 = F->getRegInfo().createVirtualRegister(RC); 11479 t2 = F->getRegInfo().createVirtualRegister(RC); 11480 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11481 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11482 } else { 11483 t1 = dest1Oper.getReg(); 11484 t2 = dest2Oper.getReg(); 11485 } 11486 11487 int valArgIndx = lastAddrIndx + 1; 11488 assert((argOpers[valArgIndx]->isReg() || 11489 argOpers[valArgIndx]->isImm()) && 11490 "invalid operand"); 11491 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11492 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11493 if (argOpers[valArgIndx]->isReg()) 11494 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11495 else 11496 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11497 if (regOpcL != X86::MOV32rr) 11498 MIB.addReg(t1); 11499 (*MIB).addOperand(*argOpers[valArgIndx]); 11500 assert(argOpers[valArgIndx + 1]->isReg() == 11501 argOpers[valArgIndx]->isReg()); 11502 assert(argOpers[valArgIndx + 1]->isImm() == 11503 argOpers[valArgIndx]->isImm()); 11504 if (argOpers[valArgIndx + 1]->isReg()) 11505 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11506 else 11507 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11508 if (regOpcH != X86::MOV32rr) 11509 MIB.addReg(t2); 11510 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11511 11512 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11513 MIB.addReg(t1); 11514 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11515 MIB.addReg(t2); 11516 11517 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11518 MIB.addReg(t5); 11519 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11520 MIB.addReg(t6); 11521 11522 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11523 for (int i=0; i <= lastAddrIndx; ++i) 11524 (*MIB).addOperand(*argOpers[i]); 11525 11526 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11527 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11528 bInstr->memoperands_end()); 11529 11530 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11531 MIB.addReg(X86::EAX); 11532 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11533 MIB.addReg(X86::EDX); 11534 11535 // insert branch 11536 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11537 11538 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11539 return nextMBB; 11540} 11541 11542// private utility function 11543MachineBasicBlock * 11544X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11545 MachineBasicBlock *MBB, 11546 unsigned cmovOpc) const { 11547 // For the atomic min/max operator, we generate 11548 // thisMBB: 11549 // newMBB: 11550 // ld t1 = [min/max.addr] 11551 // mov t2 = [min/max.val] 11552 // cmp t1, t2 11553 // cmov[cond] t2 = t1 11554 // mov EAX = t1 11555 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11556 // bz newMBB 11557 // fallthrough -->nextMBB 11558 // 11559 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11560 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11561 MachineFunction::iterator MBBIter = MBB; 11562 ++MBBIter; 11563 11564 /// First build the CFG 11565 MachineFunction *F = MBB->getParent(); 11566 MachineBasicBlock *thisMBB = MBB; 11567 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11568 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11569 F->insert(MBBIter, newMBB); 11570 F->insert(MBBIter, nextMBB); 11571 11572 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11573 nextMBB->splice(nextMBB->begin(), thisMBB, 11574 llvm::next(MachineBasicBlock::iterator(mInstr)), 11575 thisMBB->end()); 11576 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11577 11578 // Update thisMBB to fall through to newMBB 11579 thisMBB->addSuccessor(newMBB); 11580 11581 // newMBB jumps to newMBB and fall through to nextMBB 11582 newMBB->addSuccessor(nextMBB); 11583 newMBB->addSuccessor(newMBB); 11584 11585 DebugLoc dl = mInstr->getDebugLoc(); 11586 // Insert instructions into newMBB based on incoming instruction 11587 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11588 "unexpected number of operands"); 11589 MachineOperand& destOper = mInstr->getOperand(0); 11590 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11591 int numArgs = mInstr->getNumOperands() - 1; 11592 for (int i=0; i < numArgs; ++i) 11593 argOpers[i] = &mInstr->getOperand(i+1); 11594 11595 // x86 address has 4 operands: base, index, scale, and displacement 11596 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11597 int valArgIndx = lastAddrIndx + 1; 11598 11599 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11600 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11601 for (int i=0; i <= lastAddrIndx; ++i) 11602 (*MIB).addOperand(*argOpers[i]); 11603 11604 // We only support register and immediate values 11605 assert((argOpers[valArgIndx]->isReg() || 11606 argOpers[valArgIndx]->isImm()) && 11607 "invalid operand"); 11608 11609 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11610 if (argOpers[valArgIndx]->isReg()) 11611 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11612 else 11613 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11614 (*MIB).addOperand(*argOpers[valArgIndx]); 11615 11616 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11617 MIB.addReg(t1); 11618 11619 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11620 MIB.addReg(t1); 11621 MIB.addReg(t2); 11622 11623 // Generate movc 11624 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11625 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11626 MIB.addReg(t2); 11627 MIB.addReg(t1); 11628 11629 // Cmp and exchange if none has modified the memory location 11630 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11631 for (int i=0; i <= lastAddrIndx; ++i) 11632 (*MIB).addOperand(*argOpers[i]); 11633 MIB.addReg(t3); 11634 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11635 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11636 mInstr->memoperands_end()); 11637 11638 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11639 MIB.addReg(X86::EAX); 11640 11641 // insert branch 11642 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11643 11644 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11645 return nextMBB; 11646} 11647 11648// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11649// or XMM0_V32I8 in AVX all of this code can be replaced with that 11650// in the .td file. 11651MachineBasicBlock * 11652X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11653 unsigned numArgs, bool memArg) const { 11654 assert(Subtarget->hasSSE42() && 11655 "Target must have SSE4.2 or AVX features enabled"); 11656 11657 DebugLoc dl = MI->getDebugLoc(); 11658 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11659 unsigned Opc; 11660 if (!Subtarget->hasAVX()) { 11661 if (memArg) 11662 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11663 else 11664 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11665 } else { 11666 if (memArg) 11667 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11668 else 11669 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11670 } 11671 11672 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11673 for (unsigned i = 0; i < numArgs; ++i) { 11674 MachineOperand &Op = MI->getOperand(i+1); 11675 if (!(Op.isReg() && Op.isImplicit())) 11676 MIB.addOperand(Op); 11677 } 11678 BuildMI(*BB, MI, dl, 11679 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11680 MI->getOperand(0).getReg()) 11681 .addReg(X86::XMM0); 11682 11683 MI->eraseFromParent(); 11684 return BB; 11685} 11686 11687MachineBasicBlock * 11688X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11689 DebugLoc dl = MI->getDebugLoc(); 11690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11691 11692 // Address into RAX/EAX, other two args into ECX, EDX. 11693 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11694 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11695 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11696 for (int i = 0; i < X86::AddrNumOperands; ++i) 11697 MIB.addOperand(MI->getOperand(i)); 11698 11699 unsigned ValOps = X86::AddrNumOperands; 11700 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11701 .addReg(MI->getOperand(ValOps).getReg()); 11702 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11703 .addReg(MI->getOperand(ValOps+1).getReg()); 11704 11705 // The instruction doesn't actually take any operands though. 11706 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11707 11708 MI->eraseFromParent(); // The pseudo is gone now. 11709 return BB; 11710} 11711 11712MachineBasicBlock * 11713X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11714 DebugLoc dl = MI->getDebugLoc(); 11715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11716 11717 // First arg in ECX, the second in EAX. 11718 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11719 .addReg(MI->getOperand(0).getReg()); 11720 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11721 .addReg(MI->getOperand(1).getReg()); 11722 11723 // The instruction doesn't actually take any operands though. 11724 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11725 11726 MI->eraseFromParent(); // The pseudo is gone now. 11727 return BB; 11728} 11729 11730MachineBasicBlock * 11731X86TargetLowering::EmitVAARG64WithCustomInserter( 11732 MachineInstr *MI, 11733 MachineBasicBlock *MBB) const { 11734 // Emit va_arg instruction on X86-64. 11735 11736 // Operands to this pseudo-instruction: 11737 // 0 ) Output : destination address (reg) 11738 // 1-5) Input : va_list address (addr, i64mem) 11739 // 6 ) ArgSize : Size (in bytes) of vararg type 11740 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11741 // 8 ) Align : Alignment of type 11742 // 9 ) EFLAGS (implicit-def) 11743 11744 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11745 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11746 11747 unsigned DestReg = MI->getOperand(0).getReg(); 11748 MachineOperand &Base = MI->getOperand(1); 11749 MachineOperand &Scale = MI->getOperand(2); 11750 MachineOperand &Index = MI->getOperand(3); 11751 MachineOperand &Disp = MI->getOperand(4); 11752 MachineOperand &Segment = MI->getOperand(5); 11753 unsigned ArgSize = MI->getOperand(6).getImm(); 11754 unsigned ArgMode = MI->getOperand(7).getImm(); 11755 unsigned Align = MI->getOperand(8).getImm(); 11756 11757 // Memory Reference 11758 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11759 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11760 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11761 11762 // Machine Information 11763 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11764 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11765 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11766 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11767 DebugLoc DL = MI->getDebugLoc(); 11768 11769 // struct va_list { 11770 // i32 gp_offset 11771 // i32 fp_offset 11772 // i64 overflow_area (address) 11773 // i64 reg_save_area (address) 11774 // } 11775 // sizeof(va_list) = 24 11776 // alignment(va_list) = 8 11777 11778 unsigned TotalNumIntRegs = 6; 11779 unsigned TotalNumXMMRegs = 8; 11780 bool UseGPOffset = (ArgMode == 1); 11781 bool UseFPOffset = (ArgMode == 2); 11782 unsigned MaxOffset = TotalNumIntRegs * 8 + 11783 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11784 11785 /* Align ArgSize to a multiple of 8 */ 11786 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11787 bool NeedsAlign = (Align > 8); 11788 11789 MachineBasicBlock *thisMBB = MBB; 11790 MachineBasicBlock *overflowMBB; 11791 MachineBasicBlock *offsetMBB; 11792 MachineBasicBlock *endMBB; 11793 11794 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11795 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11796 unsigned OffsetReg = 0; 11797 11798 if (!UseGPOffset && !UseFPOffset) { 11799 // If we only pull from the overflow region, we don't create a branch. 11800 // We don't need to alter control flow. 11801 OffsetDestReg = 0; // unused 11802 OverflowDestReg = DestReg; 11803 11804 offsetMBB = NULL; 11805 overflowMBB = thisMBB; 11806 endMBB = thisMBB; 11807 } else { 11808 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11809 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11810 // If not, pull from overflow_area. (branch to overflowMBB) 11811 // 11812 // thisMBB 11813 // | . 11814 // | . 11815 // offsetMBB overflowMBB 11816 // | . 11817 // | . 11818 // endMBB 11819 11820 // Registers for the PHI in endMBB 11821 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11822 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11823 11824 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11825 MachineFunction *MF = MBB->getParent(); 11826 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11827 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11828 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11829 11830 MachineFunction::iterator MBBIter = MBB; 11831 ++MBBIter; 11832 11833 // Insert the new basic blocks 11834 MF->insert(MBBIter, offsetMBB); 11835 MF->insert(MBBIter, overflowMBB); 11836 MF->insert(MBBIter, endMBB); 11837 11838 // Transfer the remainder of MBB and its successor edges to endMBB. 11839 endMBB->splice(endMBB->begin(), thisMBB, 11840 llvm::next(MachineBasicBlock::iterator(MI)), 11841 thisMBB->end()); 11842 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11843 11844 // Make offsetMBB and overflowMBB successors of thisMBB 11845 thisMBB->addSuccessor(offsetMBB); 11846 thisMBB->addSuccessor(overflowMBB); 11847 11848 // endMBB is a successor of both offsetMBB and overflowMBB 11849 offsetMBB->addSuccessor(endMBB); 11850 overflowMBB->addSuccessor(endMBB); 11851 11852 // Load the offset value into a register 11853 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11854 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11855 .addOperand(Base) 11856 .addOperand(Scale) 11857 .addOperand(Index) 11858 .addDisp(Disp, UseFPOffset ? 4 : 0) 11859 .addOperand(Segment) 11860 .setMemRefs(MMOBegin, MMOEnd); 11861 11862 // Check if there is enough room left to pull this argument. 11863 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11864 .addReg(OffsetReg) 11865 .addImm(MaxOffset + 8 - ArgSizeA8); 11866 11867 // Branch to "overflowMBB" if offset >= max 11868 // Fall through to "offsetMBB" otherwise 11869 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11870 .addMBB(overflowMBB); 11871 } 11872 11873 // In offsetMBB, emit code to use the reg_save_area. 11874 if (offsetMBB) { 11875 assert(OffsetReg != 0); 11876 11877 // Read the reg_save_area address. 11878 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11879 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11880 .addOperand(Base) 11881 .addOperand(Scale) 11882 .addOperand(Index) 11883 .addDisp(Disp, 16) 11884 .addOperand(Segment) 11885 .setMemRefs(MMOBegin, MMOEnd); 11886 11887 // Zero-extend the offset 11888 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11889 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11890 .addImm(0) 11891 .addReg(OffsetReg) 11892 .addImm(X86::sub_32bit); 11893 11894 // Add the offset to the reg_save_area to get the final address. 11895 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11896 .addReg(OffsetReg64) 11897 .addReg(RegSaveReg); 11898 11899 // Compute the offset for the next argument 11900 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11901 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11902 .addReg(OffsetReg) 11903 .addImm(UseFPOffset ? 16 : 8); 11904 11905 // Store it back into the va_list. 11906 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11907 .addOperand(Base) 11908 .addOperand(Scale) 11909 .addOperand(Index) 11910 .addDisp(Disp, UseFPOffset ? 4 : 0) 11911 .addOperand(Segment) 11912 .addReg(NextOffsetReg) 11913 .setMemRefs(MMOBegin, MMOEnd); 11914 11915 // Jump to endMBB 11916 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11917 .addMBB(endMBB); 11918 } 11919 11920 // 11921 // Emit code to use overflow area 11922 // 11923 11924 // Load the overflow_area address into a register. 11925 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11926 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11927 .addOperand(Base) 11928 .addOperand(Scale) 11929 .addOperand(Index) 11930 .addDisp(Disp, 8) 11931 .addOperand(Segment) 11932 .setMemRefs(MMOBegin, MMOEnd); 11933 11934 // If we need to align it, do so. Otherwise, just copy the address 11935 // to OverflowDestReg. 11936 if (NeedsAlign) { 11937 // Align the overflow address 11938 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11939 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11940 11941 // aligned_addr = (addr + (align-1)) & ~(align-1) 11942 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11943 .addReg(OverflowAddrReg) 11944 .addImm(Align-1); 11945 11946 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11947 .addReg(TmpReg) 11948 .addImm(~(uint64_t)(Align-1)); 11949 } else { 11950 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11951 .addReg(OverflowAddrReg); 11952 } 11953 11954 // Compute the next overflow address after this argument. 11955 // (the overflow address should be kept 8-byte aligned) 11956 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11957 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11958 .addReg(OverflowDestReg) 11959 .addImm(ArgSizeA8); 11960 11961 // Store the new overflow address. 11962 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11963 .addOperand(Base) 11964 .addOperand(Scale) 11965 .addOperand(Index) 11966 .addDisp(Disp, 8) 11967 .addOperand(Segment) 11968 .addReg(NextAddrReg) 11969 .setMemRefs(MMOBegin, MMOEnd); 11970 11971 // If we branched, emit the PHI to the front of endMBB. 11972 if (offsetMBB) { 11973 BuildMI(*endMBB, endMBB->begin(), DL, 11974 TII->get(X86::PHI), DestReg) 11975 .addReg(OffsetDestReg).addMBB(offsetMBB) 11976 .addReg(OverflowDestReg).addMBB(overflowMBB); 11977 } 11978 11979 // Erase the pseudo instruction 11980 MI->eraseFromParent(); 11981 11982 return endMBB; 11983} 11984 11985MachineBasicBlock * 11986X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11987 MachineInstr *MI, 11988 MachineBasicBlock *MBB) const { 11989 // Emit code to save XMM registers to the stack. The ABI says that the 11990 // number of registers to save is given in %al, so it's theoretically 11991 // possible to do an indirect jump trick to avoid saving all of them, 11992 // however this code takes a simpler approach and just executes all 11993 // of the stores if %al is non-zero. It's less code, and it's probably 11994 // easier on the hardware branch predictor, and stores aren't all that 11995 // expensive anyway. 11996 11997 // Create the new basic blocks. One block contains all the XMM stores, 11998 // and one block is the final destination regardless of whether any 11999 // stores were performed. 12000 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12001 MachineFunction *F = MBB->getParent(); 12002 MachineFunction::iterator MBBIter = MBB; 12003 ++MBBIter; 12004 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12005 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12006 F->insert(MBBIter, XMMSaveMBB); 12007 F->insert(MBBIter, EndMBB); 12008 12009 // Transfer the remainder of MBB and its successor edges to EndMBB. 12010 EndMBB->splice(EndMBB->begin(), MBB, 12011 llvm::next(MachineBasicBlock::iterator(MI)), 12012 MBB->end()); 12013 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12014 12015 // The original block will now fall through to the XMM save block. 12016 MBB->addSuccessor(XMMSaveMBB); 12017 // The XMMSaveMBB will fall through to the end block. 12018 XMMSaveMBB->addSuccessor(EndMBB); 12019 12020 // Now add the instructions. 12021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12022 DebugLoc DL = MI->getDebugLoc(); 12023 12024 unsigned CountReg = MI->getOperand(0).getReg(); 12025 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12026 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12027 12028 if (!Subtarget->isTargetWin64()) { 12029 // If %al is 0, branch around the XMM save block. 12030 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12031 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12032 MBB->addSuccessor(EndMBB); 12033 } 12034 12035 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12036 // In the XMM save block, save all the XMM argument registers. 12037 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12038 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12039 MachineMemOperand *MMO = 12040 F->getMachineMemOperand( 12041 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12042 MachineMemOperand::MOStore, 12043 /*Size=*/16, /*Align=*/16); 12044 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12045 .addFrameIndex(RegSaveFrameIndex) 12046 .addImm(/*Scale=*/1) 12047 .addReg(/*IndexReg=*/0) 12048 .addImm(/*Disp=*/Offset) 12049 .addReg(/*Segment=*/0) 12050 .addReg(MI->getOperand(i).getReg()) 12051 .addMemOperand(MMO); 12052 } 12053 12054 MI->eraseFromParent(); // The pseudo instruction is gone now. 12055 12056 return EndMBB; 12057} 12058 12059// The EFLAGS operand of SelectItr might be missing a kill marker 12060// because there were multiple uses of EFLAGS, and ISel didn't know 12061// which to mark. Figure out whether SelectItr should have had a 12062// kill marker, and set it if it should. Returns the correct kill 12063// marker value. 12064static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12065 MachineBasicBlock* BB, 12066 const TargetRegisterInfo* TRI) { 12067 // Scan forward through BB for a use/def of EFLAGS. 12068 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12069 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12070 const MachineInstr& mi = *miI; 12071 if (mi.readsRegister(X86::EFLAGS)) 12072 return false; 12073 if (mi.definesRegister(X86::EFLAGS)) 12074 break; // Should have kill-flag - update below. 12075 } 12076 12077 // If we hit the end of the block, check whether EFLAGS is live into a 12078 // successor. 12079 if (miI == BB->end()) { 12080 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12081 sEnd = BB->succ_end(); 12082 sItr != sEnd; ++sItr) { 12083 MachineBasicBlock* succ = *sItr; 12084 if (succ->isLiveIn(X86::EFLAGS)) 12085 return false; 12086 } 12087 } 12088 12089 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12090 // out. SelectMI should have a kill flag on EFLAGS. 12091 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12092 return true; 12093} 12094 12095MachineBasicBlock * 12096X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12097 MachineBasicBlock *BB) const { 12098 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12099 DebugLoc DL = MI->getDebugLoc(); 12100 12101 // To "insert" a SELECT_CC instruction, we actually have to insert the 12102 // diamond control-flow pattern. The incoming instruction knows the 12103 // destination vreg to set, the condition code register to branch on, the 12104 // true/false values to select between, and a branch opcode to use. 12105 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12106 MachineFunction::iterator It = BB; 12107 ++It; 12108 12109 // thisMBB: 12110 // ... 12111 // TrueVal = ... 12112 // cmpTY ccX, r1, r2 12113 // bCC copy1MBB 12114 // fallthrough --> copy0MBB 12115 MachineBasicBlock *thisMBB = BB; 12116 MachineFunction *F = BB->getParent(); 12117 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12118 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12119 F->insert(It, copy0MBB); 12120 F->insert(It, sinkMBB); 12121 12122 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12123 // live into the sink and copy blocks. 12124 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12125 if (!MI->killsRegister(X86::EFLAGS) && 12126 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12127 copy0MBB->addLiveIn(X86::EFLAGS); 12128 sinkMBB->addLiveIn(X86::EFLAGS); 12129 } 12130 12131 // Transfer the remainder of BB and its successor edges to sinkMBB. 12132 sinkMBB->splice(sinkMBB->begin(), BB, 12133 llvm::next(MachineBasicBlock::iterator(MI)), 12134 BB->end()); 12135 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12136 12137 // Add the true and fallthrough blocks as its successors. 12138 BB->addSuccessor(copy0MBB); 12139 BB->addSuccessor(sinkMBB); 12140 12141 // Create the conditional branch instruction. 12142 unsigned Opc = 12143 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12144 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12145 12146 // copy0MBB: 12147 // %FalseValue = ... 12148 // # fallthrough to sinkMBB 12149 copy0MBB->addSuccessor(sinkMBB); 12150 12151 // sinkMBB: 12152 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12153 // ... 12154 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12155 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12156 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12157 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12158 12159 MI->eraseFromParent(); // The pseudo instruction is gone now. 12160 return sinkMBB; 12161} 12162 12163MachineBasicBlock * 12164X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12165 bool Is64Bit) const { 12166 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12167 DebugLoc DL = MI->getDebugLoc(); 12168 MachineFunction *MF = BB->getParent(); 12169 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12170 12171 assert(getTargetMachine().Options.EnableSegmentedStacks); 12172 12173 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12174 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12175 12176 // BB: 12177 // ... [Till the alloca] 12178 // If stacklet is not large enough, jump to mallocMBB 12179 // 12180 // bumpMBB: 12181 // Allocate by subtracting from RSP 12182 // Jump to continueMBB 12183 // 12184 // mallocMBB: 12185 // Allocate by call to runtime 12186 // 12187 // continueMBB: 12188 // ... 12189 // [rest of original BB] 12190 // 12191 12192 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12193 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12194 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12195 12196 MachineRegisterInfo &MRI = MF->getRegInfo(); 12197 const TargetRegisterClass *AddrRegClass = 12198 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12199 12200 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12201 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12202 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12203 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12204 sizeVReg = MI->getOperand(1).getReg(), 12205 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12206 12207 MachineFunction::iterator MBBIter = BB; 12208 ++MBBIter; 12209 12210 MF->insert(MBBIter, bumpMBB); 12211 MF->insert(MBBIter, mallocMBB); 12212 MF->insert(MBBIter, continueMBB); 12213 12214 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12215 (MachineBasicBlock::iterator(MI)), BB->end()); 12216 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12217 12218 // Add code to the main basic block to check if the stack limit has been hit, 12219 // and if so, jump to mallocMBB otherwise to bumpMBB. 12220 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12221 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12222 .addReg(tmpSPVReg).addReg(sizeVReg); 12223 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12224 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12225 .addReg(SPLimitVReg); 12226 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12227 12228 // bumpMBB simply decreases the stack pointer, since we know the current 12229 // stacklet has enough space. 12230 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12231 .addReg(SPLimitVReg); 12232 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12233 .addReg(SPLimitVReg); 12234 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12235 12236 // Calls into a routine in libgcc to allocate more space from the heap. 12237 const uint32_t *RegMask = 12238 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12239 if (Is64Bit) { 12240 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12241 .addReg(sizeVReg); 12242 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12243 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12244 .addRegMask(RegMask) 12245 .addReg(X86::RAX, RegState::ImplicitDefine); 12246 } else { 12247 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12248 .addImm(12); 12249 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12250 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12251 .addExternalSymbol("__morestack_allocate_stack_space") 12252 .addRegMask(RegMask) 12253 .addReg(X86::EAX, RegState::ImplicitDefine); 12254 } 12255 12256 if (!Is64Bit) 12257 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12258 .addImm(16); 12259 12260 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12261 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12262 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12263 12264 // Set up the CFG correctly. 12265 BB->addSuccessor(bumpMBB); 12266 BB->addSuccessor(mallocMBB); 12267 mallocMBB->addSuccessor(continueMBB); 12268 bumpMBB->addSuccessor(continueMBB); 12269 12270 // Take care of the PHI nodes. 12271 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12272 MI->getOperand(0).getReg()) 12273 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12274 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12275 12276 // Delete the original pseudo instruction. 12277 MI->eraseFromParent(); 12278 12279 // And we're done. 12280 return continueMBB; 12281} 12282 12283MachineBasicBlock * 12284X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12285 MachineBasicBlock *BB) const { 12286 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12287 DebugLoc DL = MI->getDebugLoc(); 12288 12289 assert(!Subtarget->isTargetEnvMacho()); 12290 12291 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12292 // non-trivial part is impdef of ESP. 12293 12294 if (Subtarget->isTargetWin64()) { 12295 if (Subtarget->isTargetCygMing()) { 12296 // ___chkstk(Mingw64): 12297 // Clobbers R10, R11, RAX and EFLAGS. 12298 // Updates RSP. 12299 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12300 .addExternalSymbol("___chkstk") 12301 .addReg(X86::RAX, RegState::Implicit) 12302 .addReg(X86::RSP, RegState::Implicit) 12303 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12304 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12305 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12306 } else { 12307 // __chkstk(MSVCRT): does not update stack pointer. 12308 // Clobbers R10, R11 and EFLAGS. 12309 // FIXME: RAX(allocated size) might be reused and not killed. 12310 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12311 .addExternalSymbol("__chkstk") 12312 .addReg(X86::RAX, RegState::Implicit) 12313 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12314 // RAX has the offset to subtracted from RSP. 12315 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12316 .addReg(X86::RSP) 12317 .addReg(X86::RAX); 12318 } 12319 } else { 12320 const char *StackProbeSymbol = 12321 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12322 12323 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12324 .addExternalSymbol(StackProbeSymbol) 12325 .addReg(X86::EAX, RegState::Implicit) 12326 .addReg(X86::ESP, RegState::Implicit) 12327 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12328 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12329 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12330 } 12331 12332 MI->eraseFromParent(); // The pseudo instruction is gone now. 12333 return BB; 12334} 12335 12336MachineBasicBlock * 12337X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12338 MachineBasicBlock *BB) const { 12339 // This is pretty easy. We're taking the value that we received from 12340 // our load from the relocation, sticking it in either RDI (x86-64) 12341 // or EAX and doing an indirect call. The return value will then 12342 // be in the normal return register. 12343 const X86InstrInfo *TII 12344 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12345 DebugLoc DL = MI->getDebugLoc(); 12346 MachineFunction *F = BB->getParent(); 12347 12348 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12349 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12350 12351 // Get a register mask for the lowered call. 12352 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12353 // proper register mask. 12354 const uint32_t *RegMask = 12355 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12356 if (Subtarget->is64Bit()) { 12357 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12358 TII->get(X86::MOV64rm), X86::RDI) 12359 .addReg(X86::RIP) 12360 .addImm(0).addReg(0) 12361 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12362 MI->getOperand(3).getTargetFlags()) 12363 .addReg(0); 12364 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12365 addDirectMem(MIB, X86::RDI); 12366 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12367 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12368 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12369 TII->get(X86::MOV32rm), X86::EAX) 12370 .addReg(0) 12371 .addImm(0).addReg(0) 12372 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12373 MI->getOperand(3).getTargetFlags()) 12374 .addReg(0); 12375 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12376 addDirectMem(MIB, X86::EAX); 12377 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12378 } else { 12379 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12380 TII->get(X86::MOV32rm), X86::EAX) 12381 .addReg(TII->getGlobalBaseReg(F)) 12382 .addImm(0).addReg(0) 12383 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12384 MI->getOperand(3).getTargetFlags()) 12385 .addReg(0); 12386 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12387 addDirectMem(MIB, X86::EAX); 12388 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12389 } 12390 12391 MI->eraseFromParent(); // The pseudo instruction is gone now. 12392 return BB; 12393} 12394 12395MachineBasicBlock * 12396X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12397 MachineBasicBlock *BB) const { 12398 switch (MI->getOpcode()) { 12399 default: llvm_unreachable("Unexpected instr type to insert"); 12400 case X86::TAILJMPd64: 12401 case X86::TAILJMPr64: 12402 case X86::TAILJMPm64: 12403 llvm_unreachable("TAILJMP64 would not be touched here."); 12404 case X86::TCRETURNdi64: 12405 case X86::TCRETURNri64: 12406 case X86::TCRETURNmi64: 12407 return BB; 12408 case X86::WIN_ALLOCA: 12409 return EmitLoweredWinAlloca(MI, BB); 12410 case X86::SEG_ALLOCA_32: 12411 return EmitLoweredSegAlloca(MI, BB, false); 12412 case X86::SEG_ALLOCA_64: 12413 return EmitLoweredSegAlloca(MI, BB, true); 12414 case X86::TLSCall_32: 12415 case X86::TLSCall_64: 12416 return EmitLoweredTLSCall(MI, BB); 12417 case X86::CMOV_GR8: 12418 case X86::CMOV_FR32: 12419 case X86::CMOV_FR64: 12420 case X86::CMOV_V4F32: 12421 case X86::CMOV_V2F64: 12422 case X86::CMOV_V2I64: 12423 case X86::CMOV_V8F32: 12424 case X86::CMOV_V4F64: 12425 case X86::CMOV_V4I64: 12426 case X86::CMOV_GR16: 12427 case X86::CMOV_GR32: 12428 case X86::CMOV_RFP32: 12429 case X86::CMOV_RFP64: 12430 case X86::CMOV_RFP80: 12431 return EmitLoweredSelect(MI, BB); 12432 12433 case X86::FP32_TO_INT16_IN_MEM: 12434 case X86::FP32_TO_INT32_IN_MEM: 12435 case X86::FP32_TO_INT64_IN_MEM: 12436 case X86::FP64_TO_INT16_IN_MEM: 12437 case X86::FP64_TO_INT32_IN_MEM: 12438 case X86::FP64_TO_INT64_IN_MEM: 12439 case X86::FP80_TO_INT16_IN_MEM: 12440 case X86::FP80_TO_INT32_IN_MEM: 12441 case X86::FP80_TO_INT64_IN_MEM: { 12442 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12443 DebugLoc DL = MI->getDebugLoc(); 12444 12445 // Change the floating point control register to use "round towards zero" 12446 // mode when truncating to an integer value. 12447 MachineFunction *F = BB->getParent(); 12448 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12449 addFrameReference(BuildMI(*BB, MI, DL, 12450 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12451 12452 // Load the old value of the high byte of the control word... 12453 unsigned OldCW = 12454 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12455 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12456 CWFrameIdx); 12457 12458 // Set the high part to be round to zero... 12459 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12460 .addImm(0xC7F); 12461 12462 // Reload the modified control word now... 12463 addFrameReference(BuildMI(*BB, MI, DL, 12464 TII->get(X86::FLDCW16m)), CWFrameIdx); 12465 12466 // Restore the memory image of control word to original value 12467 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12468 .addReg(OldCW); 12469 12470 // Get the X86 opcode to use. 12471 unsigned Opc; 12472 switch (MI->getOpcode()) { 12473 default: llvm_unreachable("illegal opcode!"); 12474 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12475 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12476 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12477 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12478 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12479 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12480 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12481 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12482 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12483 } 12484 12485 X86AddressMode AM; 12486 MachineOperand &Op = MI->getOperand(0); 12487 if (Op.isReg()) { 12488 AM.BaseType = X86AddressMode::RegBase; 12489 AM.Base.Reg = Op.getReg(); 12490 } else { 12491 AM.BaseType = X86AddressMode::FrameIndexBase; 12492 AM.Base.FrameIndex = Op.getIndex(); 12493 } 12494 Op = MI->getOperand(1); 12495 if (Op.isImm()) 12496 AM.Scale = Op.getImm(); 12497 Op = MI->getOperand(2); 12498 if (Op.isImm()) 12499 AM.IndexReg = Op.getImm(); 12500 Op = MI->getOperand(3); 12501 if (Op.isGlobal()) { 12502 AM.GV = Op.getGlobal(); 12503 } else { 12504 AM.Disp = Op.getImm(); 12505 } 12506 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12507 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12508 12509 // Reload the original control word now. 12510 addFrameReference(BuildMI(*BB, MI, DL, 12511 TII->get(X86::FLDCW16m)), CWFrameIdx); 12512 12513 MI->eraseFromParent(); // The pseudo instruction is gone now. 12514 return BB; 12515 } 12516 // String/text processing lowering. 12517 case X86::PCMPISTRM128REG: 12518 case X86::VPCMPISTRM128REG: 12519 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12520 case X86::PCMPISTRM128MEM: 12521 case X86::VPCMPISTRM128MEM: 12522 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12523 case X86::PCMPESTRM128REG: 12524 case X86::VPCMPESTRM128REG: 12525 return EmitPCMP(MI, BB, 5, false /* in mem */); 12526 case X86::PCMPESTRM128MEM: 12527 case X86::VPCMPESTRM128MEM: 12528 return EmitPCMP(MI, BB, 5, true /* in mem */); 12529 12530 // Thread synchronization. 12531 case X86::MONITOR: 12532 return EmitMonitor(MI, BB); 12533 case X86::MWAIT: 12534 return EmitMwait(MI, BB); 12535 12536 // Atomic Lowering. 12537 case X86::ATOMAND32: 12538 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12539 X86::AND32ri, X86::MOV32rm, 12540 X86::LCMPXCHG32, 12541 X86::NOT32r, X86::EAX, 12542 X86::GR32RegisterClass); 12543 case X86::ATOMOR32: 12544 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12545 X86::OR32ri, X86::MOV32rm, 12546 X86::LCMPXCHG32, 12547 X86::NOT32r, X86::EAX, 12548 X86::GR32RegisterClass); 12549 case X86::ATOMXOR32: 12550 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12551 X86::XOR32ri, X86::MOV32rm, 12552 X86::LCMPXCHG32, 12553 X86::NOT32r, X86::EAX, 12554 X86::GR32RegisterClass); 12555 case X86::ATOMNAND32: 12556 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12557 X86::AND32ri, X86::MOV32rm, 12558 X86::LCMPXCHG32, 12559 X86::NOT32r, X86::EAX, 12560 X86::GR32RegisterClass, true); 12561 case X86::ATOMMIN32: 12562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12563 case X86::ATOMMAX32: 12564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12565 case X86::ATOMUMIN32: 12566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12567 case X86::ATOMUMAX32: 12568 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12569 12570 case X86::ATOMAND16: 12571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12572 X86::AND16ri, X86::MOV16rm, 12573 X86::LCMPXCHG16, 12574 X86::NOT16r, X86::AX, 12575 X86::GR16RegisterClass); 12576 case X86::ATOMOR16: 12577 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12578 X86::OR16ri, X86::MOV16rm, 12579 X86::LCMPXCHG16, 12580 X86::NOT16r, X86::AX, 12581 X86::GR16RegisterClass); 12582 case X86::ATOMXOR16: 12583 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12584 X86::XOR16ri, X86::MOV16rm, 12585 X86::LCMPXCHG16, 12586 X86::NOT16r, X86::AX, 12587 X86::GR16RegisterClass); 12588 case X86::ATOMNAND16: 12589 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12590 X86::AND16ri, X86::MOV16rm, 12591 X86::LCMPXCHG16, 12592 X86::NOT16r, X86::AX, 12593 X86::GR16RegisterClass, true); 12594 case X86::ATOMMIN16: 12595 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12596 case X86::ATOMMAX16: 12597 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12598 case X86::ATOMUMIN16: 12599 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12600 case X86::ATOMUMAX16: 12601 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12602 12603 case X86::ATOMAND8: 12604 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12605 X86::AND8ri, X86::MOV8rm, 12606 X86::LCMPXCHG8, 12607 X86::NOT8r, X86::AL, 12608 X86::GR8RegisterClass); 12609 case X86::ATOMOR8: 12610 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12611 X86::OR8ri, X86::MOV8rm, 12612 X86::LCMPXCHG8, 12613 X86::NOT8r, X86::AL, 12614 X86::GR8RegisterClass); 12615 case X86::ATOMXOR8: 12616 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12617 X86::XOR8ri, X86::MOV8rm, 12618 X86::LCMPXCHG8, 12619 X86::NOT8r, X86::AL, 12620 X86::GR8RegisterClass); 12621 case X86::ATOMNAND8: 12622 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12623 X86::AND8ri, X86::MOV8rm, 12624 X86::LCMPXCHG8, 12625 X86::NOT8r, X86::AL, 12626 X86::GR8RegisterClass, true); 12627 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12628 // This group is for 64-bit host. 12629 case X86::ATOMAND64: 12630 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12631 X86::AND64ri32, X86::MOV64rm, 12632 X86::LCMPXCHG64, 12633 X86::NOT64r, X86::RAX, 12634 X86::GR64RegisterClass); 12635 case X86::ATOMOR64: 12636 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12637 X86::OR64ri32, X86::MOV64rm, 12638 X86::LCMPXCHG64, 12639 X86::NOT64r, X86::RAX, 12640 X86::GR64RegisterClass); 12641 case X86::ATOMXOR64: 12642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12643 X86::XOR64ri32, X86::MOV64rm, 12644 X86::LCMPXCHG64, 12645 X86::NOT64r, X86::RAX, 12646 X86::GR64RegisterClass); 12647 case X86::ATOMNAND64: 12648 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12649 X86::AND64ri32, X86::MOV64rm, 12650 X86::LCMPXCHG64, 12651 X86::NOT64r, X86::RAX, 12652 X86::GR64RegisterClass, true); 12653 case X86::ATOMMIN64: 12654 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12655 case X86::ATOMMAX64: 12656 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12657 case X86::ATOMUMIN64: 12658 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12659 case X86::ATOMUMAX64: 12660 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12661 12662 // This group does 64-bit operations on a 32-bit host. 12663 case X86::ATOMAND6432: 12664 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12665 X86::AND32rr, X86::AND32rr, 12666 X86::AND32ri, X86::AND32ri, 12667 false); 12668 case X86::ATOMOR6432: 12669 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12670 X86::OR32rr, X86::OR32rr, 12671 X86::OR32ri, X86::OR32ri, 12672 false); 12673 case X86::ATOMXOR6432: 12674 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12675 X86::XOR32rr, X86::XOR32rr, 12676 X86::XOR32ri, X86::XOR32ri, 12677 false); 12678 case X86::ATOMNAND6432: 12679 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12680 X86::AND32rr, X86::AND32rr, 12681 X86::AND32ri, X86::AND32ri, 12682 true); 12683 case X86::ATOMADD6432: 12684 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12685 X86::ADD32rr, X86::ADC32rr, 12686 X86::ADD32ri, X86::ADC32ri, 12687 false); 12688 case X86::ATOMSUB6432: 12689 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12690 X86::SUB32rr, X86::SBB32rr, 12691 X86::SUB32ri, X86::SBB32ri, 12692 false); 12693 case X86::ATOMSWAP6432: 12694 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12695 X86::MOV32rr, X86::MOV32rr, 12696 X86::MOV32ri, X86::MOV32ri, 12697 false); 12698 case X86::VASTART_SAVE_XMM_REGS: 12699 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12700 12701 case X86::VAARG_64: 12702 return EmitVAARG64WithCustomInserter(MI, BB); 12703 } 12704} 12705 12706//===----------------------------------------------------------------------===// 12707// X86 Optimization Hooks 12708//===----------------------------------------------------------------------===// 12709 12710void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12711 APInt &KnownZero, 12712 APInt &KnownOne, 12713 const SelectionDAG &DAG, 12714 unsigned Depth) const { 12715 unsigned BitWidth = KnownZero.getBitWidth(); 12716 unsigned Opc = Op.getOpcode(); 12717 assert((Opc >= ISD::BUILTIN_OP_END || 12718 Opc == ISD::INTRINSIC_WO_CHAIN || 12719 Opc == ISD::INTRINSIC_W_CHAIN || 12720 Opc == ISD::INTRINSIC_VOID) && 12721 "Should use MaskedValueIsZero if you don't know whether Op" 12722 " is a target node!"); 12723 12724 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12725 switch (Opc) { 12726 default: break; 12727 case X86ISD::ADD: 12728 case X86ISD::SUB: 12729 case X86ISD::ADC: 12730 case X86ISD::SBB: 12731 case X86ISD::SMUL: 12732 case X86ISD::UMUL: 12733 case X86ISD::INC: 12734 case X86ISD::DEC: 12735 case X86ISD::OR: 12736 case X86ISD::XOR: 12737 case X86ISD::AND: 12738 // These nodes' second result is a boolean. 12739 if (Op.getResNo() == 0) 12740 break; 12741 // Fallthrough 12742 case X86ISD::SETCC: 12743 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12744 break; 12745 case ISD::INTRINSIC_WO_CHAIN: { 12746 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12747 unsigned NumLoBits = 0; 12748 switch (IntId) { 12749 default: break; 12750 case Intrinsic::x86_sse_movmsk_ps: 12751 case Intrinsic::x86_avx_movmsk_ps_256: 12752 case Intrinsic::x86_sse2_movmsk_pd: 12753 case Intrinsic::x86_avx_movmsk_pd_256: 12754 case Intrinsic::x86_mmx_pmovmskb: 12755 case Intrinsic::x86_sse2_pmovmskb_128: 12756 case Intrinsic::x86_avx2_pmovmskb: { 12757 // High bits of movmskp{s|d}, pmovmskb are known zero. 12758 switch (IntId) { 12759 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12760 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12761 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12762 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12763 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12764 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12765 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12766 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12767 } 12768 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12769 break; 12770 } 12771 } 12772 break; 12773 } 12774 } 12775} 12776 12777unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12778 unsigned Depth) const { 12779 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12780 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12781 return Op.getValueType().getScalarType().getSizeInBits(); 12782 12783 // Fallback case. 12784 return 1; 12785} 12786 12787/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12788/// node is a GlobalAddress + offset. 12789bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12790 const GlobalValue* &GA, 12791 int64_t &Offset) const { 12792 if (N->getOpcode() == X86ISD::Wrapper) { 12793 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12794 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12795 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12796 return true; 12797 } 12798 } 12799 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12800} 12801 12802/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12803/// same as extracting the high 128-bit part of 256-bit vector and then 12804/// inserting the result into the low part of a new 256-bit vector 12805static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12806 EVT VT = SVOp->getValueType(0); 12807 int NumElems = VT.getVectorNumElements(); 12808 12809 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12810 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12811 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12812 SVOp->getMaskElt(j) >= 0) 12813 return false; 12814 12815 return true; 12816} 12817 12818/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12819/// same as extracting the low 128-bit part of 256-bit vector and then 12820/// inserting the result into the high part of a new 256-bit vector 12821static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12822 EVT VT = SVOp->getValueType(0); 12823 int NumElems = VT.getVectorNumElements(); 12824 12825 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12826 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12827 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12828 SVOp->getMaskElt(j) >= 0) 12829 return false; 12830 12831 return true; 12832} 12833 12834/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12835static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12836 TargetLowering::DAGCombinerInfo &DCI, 12837 const X86Subtarget* Subtarget) { 12838 DebugLoc dl = N->getDebugLoc(); 12839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12840 SDValue V1 = SVOp->getOperand(0); 12841 SDValue V2 = SVOp->getOperand(1); 12842 EVT VT = SVOp->getValueType(0); 12843 int NumElems = VT.getVectorNumElements(); 12844 12845 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12846 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12847 // 12848 // 0,0,0,... 12849 // | 12850 // V UNDEF BUILD_VECTOR UNDEF 12851 // \ / \ / 12852 // CONCAT_VECTOR CONCAT_VECTOR 12853 // \ / 12854 // \ / 12855 // RESULT: V + zero extended 12856 // 12857 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12858 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12859 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12860 return SDValue(); 12861 12862 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12863 return SDValue(); 12864 12865 // To match the shuffle mask, the first half of the mask should 12866 // be exactly the first vector, and all the rest a splat with the 12867 // first element of the second one. 12868 for (int i = 0; i < NumElems/2; ++i) 12869 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12870 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12871 return SDValue(); 12872 12873 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12874 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12875 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12876 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12877 SDValue ResNode = 12878 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12879 Ld->getMemoryVT(), 12880 Ld->getPointerInfo(), 12881 Ld->getAlignment(), 12882 false/*isVolatile*/, true/*ReadMem*/, 12883 false/*WriteMem*/); 12884 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12885 } 12886 12887 // Emit a zeroed vector and insert the desired subvector on its 12888 // first half. 12889 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12890 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12891 DAG.getConstant(0, MVT::i32), DAG, dl); 12892 return DCI.CombineTo(N, InsV); 12893 } 12894 12895 //===--------------------------------------------------------------------===// 12896 // Combine some shuffles into subvector extracts and inserts: 12897 // 12898 12899 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12900 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12901 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12902 DAG, dl); 12903 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12904 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12905 return DCI.CombineTo(N, InsV); 12906 } 12907 12908 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12909 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12910 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12911 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12912 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12913 return DCI.CombineTo(N, InsV); 12914 } 12915 12916 return SDValue(); 12917} 12918 12919/// PerformShuffleCombine - Performs several different shuffle combines. 12920static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12921 TargetLowering::DAGCombinerInfo &DCI, 12922 const X86Subtarget *Subtarget) { 12923 DebugLoc dl = N->getDebugLoc(); 12924 EVT VT = N->getValueType(0); 12925 12926 // Don't create instructions with illegal types after legalize types has run. 12927 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12928 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12929 return SDValue(); 12930 12931 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12932 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12933 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12934 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 12935 12936 // Only handle 128 wide vector from here on. 12937 if (VT.getSizeInBits() != 128) 12938 return SDValue(); 12939 12940 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12941 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12942 // consecutive, non-overlapping, and in the right order. 12943 SmallVector<SDValue, 16> Elts; 12944 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12945 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12946 12947 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12948} 12949 12950 12951/// PerformTruncateCombine - Converts truncate operation to 12952/// a sequence of vector shuffle operations. 12953/// It is possible when we truncate 256-bit vector to 128-bit vector 12954 12955SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 12956 DAGCombinerInfo &DCI) const { 12957 if (!DCI.isBeforeLegalizeOps()) 12958 return SDValue(); 12959 12960 if (!Subtarget->hasAVX()) return SDValue(); 12961 12962 EVT VT = N->getValueType(0); 12963 SDValue Op = N->getOperand(0); 12964 EVT OpVT = Op.getValueType(); 12965 DebugLoc dl = N->getDebugLoc(); 12966 12967 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 12968 12969 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12970 DAG.getIntPtrConstant(0)); 12971 12972 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12973 DAG.getIntPtrConstant(2)); 12974 12975 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12976 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12977 12978 // PSHUFD 12979 int ShufMask1[] = {0, 2, 0, 0}; 12980 12981 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 12982 ShufMask1); 12983 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 12984 ShufMask1); 12985 12986 // MOVLHPS 12987 int ShufMask2[] = {0, 1, 4, 5}; 12988 12989 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 12990 } 12991 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 12992 12993 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12994 DAG.getIntPtrConstant(0)); 12995 12996 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12997 DAG.getIntPtrConstant(4)); 12998 12999 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13000 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13001 13002 // PSHUFB 13003 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13004 -1, -1, -1, -1, -1, -1, -1, -1}; 13005 13006 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 13007 DAG.getUNDEF(MVT::v16i8), 13008 ShufMask1); 13009 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 13010 DAG.getUNDEF(MVT::v16i8), 13011 ShufMask1); 13012 13013 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13014 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13015 13016 // MOVLHPS 13017 int ShufMask2[] = {0, 1, 4, 5}; 13018 13019 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13020 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13021 } 13022 13023 return SDValue(); 13024} 13025 13026/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13027/// specific shuffle of a load can be folded into a single element load. 13028/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13029/// shuffles have been customed lowered so we need to handle those here. 13030static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13031 TargetLowering::DAGCombinerInfo &DCI) { 13032 if (DCI.isBeforeLegalizeOps()) 13033 return SDValue(); 13034 13035 SDValue InVec = N->getOperand(0); 13036 SDValue EltNo = N->getOperand(1); 13037 13038 if (!isa<ConstantSDNode>(EltNo)) 13039 return SDValue(); 13040 13041 EVT VT = InVec.getValueType(); 13042 13043 bool HasShuffleIntoBitcast = false; 13044 if (InVec.getOpcode() == ISD::BITCAST) { 13045 // Don't duplicate a load with other uses. 13046 if (!InVec.hasOneUse()) 13047 return SDValue(); 13048 EVT BCVT = InVec.getOperand(0).getValueType(); 13049 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13050 return SDValue(); 13051 InVec = InVec.getOperand(0); 13052 HasShuffleIntoBitcast = true; 13053 } 13054 13055 if (!isTargetShuffle(InVec.getOpcode())) 13056 return SDValue(); 13057 13058 // Don't duplicate a load with other uses. 13059 if (!InVec.hasOneUse()) 13060 return SDValue(); 13061 13062 SmallVector<int, 16> ShuffleMask; 13063 bool UnaryShuffle; 13064 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 13065 return SDValue(); 13066 13067 // Select the input vector, guarding against out of range extract vector. 13068 unsigned NumElems = VT.getVectorNumElements(); 13069 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13070 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13071 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13072 : InVec.getOperand(1); 13073 13074 // If inputs to shuffle are the same for both ops, then allow 2 uses 13075 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13076 13077 if (LdNode.getOpcode() == ISD::BITCAST) { 13078 // Don't duplicate a load with other uses. 13079 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13080 return SDValue(); 13081 13082 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13083 LdNode = LdNode.getOperand(0); 13084 } 13085 13086 if (!ISD::isNormalLoad(LdNode.getNode())) 13087 return SDValue(); 13088 13089 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13090 13091 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13092 return SDValue(); 13093 13094 if (HasShuffleIntoBitcast) { 13095 // If there's a bitcast before the shuffle, check if the load type and 13096 // alignment is valid. 13097 unsigned Align = LN0->getAlignment(); 13098 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13099 unsigned NewAlign = TLI.getTargetData()-> 13100 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13101 13102 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13103 return SDValue(); 13104 } 13105 13106 // All checks match so transform back to vector_shuffle so that DAG combiner 13107 // can finish the job 13108 DebugLoc dl = N->getDebugLoc(); 13109 13110 // Create shuffle node taking into account the case that its a unary shuffle 13111 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13112 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13113 InVec.getOperand(0), Shuffle, 13114 &ShuffleMask[0]); 13115 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13116 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13117 EltNo); 13118} 13119 13120/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13121/// generation and convert it from being a bunch of shuffles and extracts 13122/// to a simple store and scalar loads to extract the elements. 13123static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13124 TargetLowering::DAGCombinerInfo &DCI) { 13125 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13126 if (NewOp.getNode()) 13127 return NewOp; 13128 13129 SDValue InputVector = N->getOperand(0); 13130 13131 // Only operate on vectors of 4 elements, where the alternative shuffling 13132 // gets to be more expensive. 13133 if (InputVector.getValueType() != MVT::v4i32) 13134 return SDValue(); 13135 13136 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13137 // single use which is a sign-extend or zero-extend, and all elements are 13138 // used. 13139 SmallVector<SDNode *, 4> Uses; 13140 unsigned ExtractedElements = 0; 13141 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13142 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13143 if (UI.getUse().getResNo() != InputVector.getResNo()) 13144 return SDValue(); 13145 13146 SDNode *Extract = *UI; 13147 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13148 return SDValue(); 13149 13150 if (Extract->getValueType(0) != MVT::i32) 13151 return SDValue(); 13152 if (!Extract->hasOneUse()) 13153 return SDValue(); 13154 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13155 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13156 return SDValue(); 13157 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13158 return SDValue(); 13159 13160 // Record which element was extracted. 13161 ExtractedElements |= 13162 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13163 13164 Uses.push_back(Extract); 13165 } 13166 13167 // If not all the elements were used, this may not be worthwhile. 13168 if (ExtractedElements != 15) 13169 return SDValue(); 13170 13171 // Ok, we've now decided to do the transformation. 13172 DebugLoc dl = InputVector.getDebugLoc(); 13173 13174 // Store the value to a temporary stack slot. 13175 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13176 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13177 MachinePointerInfo(), false, false, 0); 13178 13179 // Replace each use (extract) with a load of the appropriate element. 13180 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13181 UE = Uses.end(); UI != UE; ++UI) { 13182 SDNode *Extract = *UI; 13183 13184 // cOMpute the element's address. 13185 SDValue Idx = Extract->getOperand(1); 13186 unsigned EltSize = 13187 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13188 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13189 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13190 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13191 13192 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13193 StackPtr, OffsetVal); 13194 13195 // Load the scalar. 13196 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13197 ScalarAddr, MachinePointerInfo(), 13198 false, false, false, 0); 13199 13200 // Replace the exact with the load. 13201 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13202 } 13203 13204 // The replacement was made in place; don't return anything. 13205 return SDValue(); 13206} 13207 13208/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13209/// nodes. 13210static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13211 TargetLowering::DAGCombinerInfo &DCI, 13212 const X86Subtarget *Subtarget) { 13213 13214 13215 DebugLoc DL = N->getDebugLoc(); 13216 SDValue Cond = N->getOperand(0); 13217 // Get the LHS/RHS of the select. 13218 SDValue LHS = N->getOperand(1); 13219 SDValue RHS = N->getOperand(2); 13220 EVT VT = LHS.getValueType(); 13221 13222 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13223 // instructions match the semantics of the common C idiom x<y?x:y but not 13224 // x<=y?x:y, because of how they handle negative zero (which can be 13225 // ignored in unsafe-math mode). 13226 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13227 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13228 (Subtarget->hasSSE2() || 13229 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13230 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13231 13232 unsigned Opcode = 0; 13233 // Check for x CC y ? x : y. 13234 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13235 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13236 switch (CC) { 13237 default: break; 13238 case ISD::SETULT: 13239 // Converting this to a min would handle NaNs incorrectly, and swapping 13240 // the operands would cause it to handle comparisons between positive 13241 // and negative zero incorrectly. 13242 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13243 if (!DAG.getTarget().Options.UnsafeFPMath && 13244 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13245 break; 13246 std::swap(LHS, RHS); 13247 } 13248 Opcode = X86ISD::FMIN; 13249 break; 13250 case ISD::SETOLE: 13251 // Converting this to a min would handle comparisons between positive 13252 // and negative zero incorrectly. 13253 if (!DAG.getTarget().Options.UnsafeFPMath && 13254 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13255 break; 13256 Opcode = X86ISD::FMIN; 13257 break; 13258 case ISD::SETULE: 13259 // Converting this to a min would handle both negative zeros and NaNs 13260 // incorrectly, but we can swap the operands to fix both. 13261 std::swap(LHS, RHS); 13262 case ISD::SETOLT: 13263 case ISD::SETLT: 13264 case ISD::SETLE: 13265 Opcode = X86ISD::FMIN; 13266 break; 13267 13268 case ISD::SETOGE: 13269 // Converting this to a max would handle comparisons between positive 13270 // and negative zero incorrectly. 13271 if (!DAG.getTarget().Options.UnsafeFPMath && 13272 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13273 break; 13274 Opcode = X86ISD::FMAX; 13275 break; 13276 case ISD::SETUGT: 13277 // Converting this to a max would handle NaNs incorrectly, and swapping 13278 // the operands would cause it to handle comparisons between positive 13279 // and negative zero incorrectly. 13280 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13281 if (!DAG.getTarget().Options.UnsafeFPMath && 13282 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13283 break; 13284 std::swap(LHS, RHS); 13285 } 13286 Opcode = X86ISD::FMAX; 13287 break; 13288 case ISD::SETUGE: 13289 // Converting this to a max would handle both negative zeros and NaNs 13290 // incorrectly, but we can swap the operands to fix both. 13291 std::swap(LHS, RHS); 13292 case ISD::SETOGT: 13293 case ISD::SETGT: 13294 case ISD::SETGE: 13295 Opcode = X86ISD::FMAX; 13296 break; 13297 } 13298 // Check for x CC y ? y : x -- a min/max with reversed arms. 13299 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13300 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13301 switch (CC) { 13302 default: break; 13303 case ISD::SETOGE: 13304 // Converting this to a min would handle comparisons between positive 13305 // and negative zero incorrectly, and swapping the operands would 13306 // cause it to handle NaNs incorrectly. 13307 if (!DAG.getTarget().Options.UnsafeFPMath && 13308 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13309 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13310 break; 13311 std::swap(LHS, RHS); 13312 } 13313 Opcode = X86ISD::FMIN; 13314 break; 13315 case ISD::SETUGT: 13316 // Converting this to a min would handle NaNs incorrectly. 13317 if (!DAG.getTarget().Options.UnsafeFPMath && 13318 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13319 break; 13320 Opcode = X86ISD::FMIN; 13321 break; 13322 case ISD::SETUGE: 13323 // Converting this to a min would handle both negative zeros and NaNs 13324 // incorrectly, but we can swap the operands to fix both. 13325 std::swap(LHS, RHS); 13326 case ISD::SETOGT: 13327 case ISD::SETGT: 13328 case ISD::SETGE: 13329 Opcode = X86ISD::FMIN; 13330 break; 13331 13332 case ISD::SETULT: 13333 // Converting this to a max would handle NaNs incorrectly. 13334 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13335 break; 13336 Opcode = X86ISD::FMAX; 13337 break; 13338 case ISD::SETOLE: 13339 // Converting this to a max would handle comparisons between positive 13340 // and negative zero incorrectly, and swapping the operands would 13341 // cause it to handle NaNs incorrectly. 13342 if (!DAG.getTarget().Options.UnsafeFPMath && 13343 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13344 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13345 break; 13346 std::swap(LHS, RHS); 13347 } 13348 Opcode = X86ISD::FMAX; 13349 break; 13350 case ISD::SETULE: 13351 // Converting this to a max would handle both negative zeros and NaNs 13352 // incorrectly, but we can swap the operands to fix both. 13353 std::swap(LHS, RHS); 13354 case ISD::SETOLT: 13355 case ISD::SETLT: 13356 case ISD::SETLE: 13357 Opcode = X86ISD::FMAX; 13358 break; 13359 } 13360 } 13361 13362 if (Opcode) 13363 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13364 } 13365 13366 // If this is a select between two integer constants, try to do some 13367 // optimizations. 13368 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13369 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13370 // Don't do this for crazy integer types. 13371 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13372 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13373 // so that TrueC (the true value) is larger than FalseC. 13374 bool NeedsCondInvert = false; 13375 13376 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13377 // Efficiently invertible. 13378 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13379 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13380 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13381 NeedsCondInvert = true; 13382 std::swap(TrueC, FalseC); 13383 } 13384 13385 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13386 if (FalseC->getAPIntValue() == 0 && 13387 TrueC->getAPIntValue().isPowerOf2()) { 13388 if (NeedsCondInvert) // Invert the condition if needed. 13389 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13390 DAG.getConstant(1, Cond.getValueType())); 13391 13392 // Zero extend the condition if needed. 13393 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13394 13395 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13396 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13397 DAG.getConstant(ShAmt, MVT::i8)); 13398 } 13399 13400 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13401 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13402 if (NeedsCondInvert) // Invert the condition if needed. 13403 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13404 DAG.getConstant(1, Cond.getValueType())); 13405 13406 // Zero extend the condition if needed. 13407 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13408 FalseC->getValueType(0), Cond); 13409 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13410 SDValue(FalseC, 0)); 13411 } 13412 13413 // Optimize cases that will turn into an LEA instruction. This requires 13414 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13415 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13416 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13417 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13418 13419 bool isFastMultiplier = false; 13420 if (Diff < 10) { 13421 switch ((unsigned char)Diff) { 13422 default: break; 13423 case 1: // result = add base, cond 13424 case 2: // result = lea base( , cond*2) 13425 case 3: // result = lea base(cond, cond*2) 13426 case 4: // result = lea base( , cond*4) 13427 case 5: // result = lea base(cond, cond*4) 13428 case 8: // result = lea base( , cond*8) 13429 case 9: // result = lea base(cond, cond*8) 13430 isFastMultiplier = true; 13431 break; 13432 } 13433 } 13434 13435 if (isFastMultiplier) { 13436 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13437 if (NeedsCondInvert) // Invert the condition if needed. 13438 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13439 DAG.getConstant(1, Cond.getValueType())); 13440 13441 // Zero extend the condition if needed. 13442 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13443 Cond); 13444 // Scale the condition by the difference. 13445 if (Diff != 1) 13446 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13447 DAG.getConstant(Diff, Cond.getValueType())); 13448 13449 // Add the base if non-zero. 13450 if (FalseC->getAPIntValue() != 0) 13451 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13452 SDValue(FalseC, 0)); 13453 return Cond; 13454 } 13455 } 13456 } 13457 } 13458 13459 // Canonicalize max and min: 13460 // (x > y) ? x : y -> (x >= y) ? x : y 13461 // (x < y) ? x : y -> (x <= y) ? x : y 13462 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13463 // the need for an extra compare 13464 // against zero. e.g. 13465 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13466 // subl %esi, %edi 13467 // testl %edi, %edi 13468 // movl $0, %eax 13469 // cmovgl %edi, %eax 13470 // => 13471 // xorl %eax, %eax 13472 // subl %esi, $edi 13473 // cmovsl %eax, %edi 13474 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13475 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13476 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13477 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13478 switch (CC) { 13479 default: break; 13480 case ISD::SETLT: 13481 case ISD::SETGT: { 13482 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13483 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13484 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13485 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13486 } 13487 } 13488 } 13489 13490 // If we know that this node is legal then we know that it is going to be 13491 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13492 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13493 // to simplify previous instructions. 13494 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13495 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13496 !DCI.isBeforeLegalize() && 13497 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13498 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13499 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13500 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13501 13502 APInt KnownZero, KnownOne; 13503 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13504 DCI.isBeforeLegalizeOps()); 13505 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13506 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13507 DCI.CommitTargetLoweringOpt(TLO); 13508 } 13509 13510 return SDValue(); 13511} 13512 13513/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13514static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13515 TargetLowering::DAGCombinerInfo &DCI) { 13516 DebugLoc DL = N->getDebugLoc(); 13517 13518 // If the flag operand isn't dead, don't touch this CMOV. 13519 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13520 return SDValue(); 13521 13522 SDValue FalseOp = N->getOperand(0); 13523 SDValue TrueOp = N->getOperand(1); 13524 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13525 SDValue Cond = N->getOperand(3); 13526 if (CC == X86::COND_E || CC == X86::COND_NE) { 13527 switch (Cond.getOpcode()) { 13528 default: break; 13529 case X86ISD::BSR: 13530 case X86ISD::BSF: 13531 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13532 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13533 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13534 } 13535 } 13536 13537 // If this is a select between two integer constants, try to do some 13538 // optimizations. Note that the operands are ordered the opposite of SELECT 13539 // operands. 13540 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13541 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13542 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13543 // larger than FalseC (the false value). 13544 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13545 CC = X86::GetOppositeBranchCondition(CC); 13546 std::swap(TrueC, FalseC); 13547 } 13548 13549 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13550 // This is efficient for any integer data type (including i8/i16) and 13551 // shift amount. 13552 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13553 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13554 DAG.getConstant(CC, MVT::i8), Cond); 13555 13556 // Zero extend the condition if needed. 13557 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13558 13559 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13560 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13561 DAG.getConstant(ShAmt, MVT::i8)); 13562 if (N->getNumValues() == 2) // Dead flag value? 13563 return DCI.CombineTo(N, Cond, SDValue()); 13564 return Cond; 13565 } 13566 13567 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13568 // for any integer data type, including i8/i16. 13569 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13570 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13571 DAG.getConstant(CC, MVT::i8), Cond); 13572 13573 // Zero extend the condition if needed. 13574 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13575 FalseC->getValueType(0), Cond); 13576 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13577 SDValue(FalseC, 0)); 13578 13579 if (N->getNumValues() == 2) // Dead flag value? 13580 return DCI.CombineTo(N, Cond, SDValue()); 13581 return Cond; 13582 } 13583 13584 // Optimize cases that will turn into an LEA instruction. This requires 13585 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13586 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13587 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13588 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13589 13590 bool isFastMultiplier = false; 13591 if (Diff < 10) { 13592 switch ((unsigned char)Diff) { 13593 default: break; 13594 case 1: // result = add base, cond 13595 case 2: // result = lea base( , cond*2) 13596 case 3: // result = lea base(cond, cond*2) 13597 case 4: // result = lea base( , cond*4) 13598 case 5: // result = lea base(cond, cond*4) 13599 case 8: // result = lea base( , cond*8) 13600 case 9: // result = lea base(cond, cond*8) 13601 isFastMultiplier = true; 13602 break; 13603 } 13604 } 13605 13606 if (isFastMultiplier) { 13607 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13608 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13609 DAG.getConstant(CC, MVT::i8), Cond); 13610 // Zero extend the condition if needed. 13611 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13612 Cond); 13613 // Scale the condition by the difference. 13614 if (Diff != 1) 13615 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13616 DAG.getConstant(Diff, Cond.getValueType())); 13617 13618 // Add the base if non-zero. 13619 if (FalseC->getAPIntValue() != 0) 13620 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13621 SDValue(FalseC, 0)); 13622 if (N->getNumValues() == 2) // Dead flag value? 13623 return DCI.CombineTo(N, Cond, SDValue()); 13624 return Cond; 13625 } 13626 } 13627 } 13628 } 13629 return SDValue(); 13630} 13631 13632 13633/// PerformMulCombine - Optimize a single multiply with constant into two 13634/// in order to implement it with two cheaper instructions, e.g. 13635/// LEA + SHL, LEA + LEA. 13636static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13637 TargetLowering::DAGCombinerInfo &DCI) { 13638 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13639 return SDValue(); 13640 13641 EVT VT = N->getValueType(0); 13642 if (VT != MVT::i64) 13643 return SDValue(); 13644 13645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13646 if (!C) 13647 return SDValue(); 13648 uint64_t MulAmt = C->getZExtValue(); 13649 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13650 return SDValue(); 13651 13652 uint64_t MulAmt1 = 0; 13653 uint64_t MulAmt2 = 0; 13654 if ((MulAmt % 9) == 0) { 13655 MulAmt1 = 9; 13656 MulAmt2 = MulAmt / 9; 13657 } else if ((MulAmt % 5) == 0) { 13658 MulAmt1 = 5; 13659 MulAmt2 = MulAmt / 5; 13660 } else if ((MulAmt % 3) == 0) { 13661 MulAmt1 = 3; 13662 MulAmt2 = MulAmt / 3; 13663 } 13664 if (MulAmt2 && 13665 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13666 DebugLoc DL = N->getDebugLoc(); 13667 13668 if (isPowerOf2_64(MulAmt2) && 13669 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13670 // If second multiplifer is pow2, issue it first. We want the multiply by 13671 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13672 // is an add. 13673 std::swap(MulAmt1, MulAmt2); 13674 13675 SDValue NewMul; 13676 if (isPowerOf2_64(MulAmt1)) 13677 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13678 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13679 else 13680 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13681 DAG.getConstant(MulAmt1, VT)); 13682 13683 if (isPowerOf2_64(MulAmt2)) 13684 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13685 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13686 else 13687 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13688 DAG.getConstant(MulAmt2, VT)); 13689 13690 // Do not add new nodes to DAG combiner worklist. 13691 DCI.CombineTo(N, NewMul, false); 13692 } 13693 return SDValue(); 13694} 13695 13696static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13697 SDValue N0 = N->getOperand(0); 13698 SDValue N1 = N->getOperand(1); 13699 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13700 EVT VT = N0.getValueType(); 13701 13702 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13703 // since the result of setcc_c is all zero's or all ones. 13704 if (VT.isInteger() && !VT.isVector() && 13705 N1C && N0.getOpcode() == ISD::AND && 13706 N0.getOperand(1).getOpcode() == ISD::Constant) { 13707 SDValue N00 = N0.getOperand(0); 13708 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13709 ((N00.getOpcode() == ISD::ANY_EXTEND || 13710 N00.getOpcode() == ISD::ZERO_EXTEND) && 13711 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13712 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13713 APInt ShAmt = N1C->getAPIntValue(); 13714 Mask = Mask.shl(ShAmt); 13715 if (Mask != 0) 13716 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13717 N00, DAG.getConstant(Mask, VT)); 13718 } 13719 } 13720 13721 13722 // Hardware support for vector shifts is sparse which makes us scalarize the 13723 // vector operations in many cases. Also, on sandybridge ADD is faster than 13724 // shl. 13725 // (shl V, 1) -> add V,V 13726 if (isSplatVector(N1.getNode())) { 13727 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13728 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13729 // We shift all of the values by one. In many cases we do not have 13730 // hardware support for this operation. This is better expressed as an ADD 13731 // of two values. 13732 if (N1C && (1 == N1C->getZExtValue())) { 13733 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13734 } 13735 } 13736 13737 return SDValue(); 13738} 13739 13740/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13741/// when possible. 13742static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13743 TargetLowering::DAGCombinerInfo &DCI, 13744 const X86Subtarget *Subtarget) { 13745 EVT VT = N->getValueType(0); 13746 if (N->getOpcode() == ISD::SHL) { 13747 SDValue V = PerformSHLCombine(N, DAG); 13748 if (V.getNode()) return V; 13749 } 13750 13751 // On X86 with SSE2 support, we can transform this to a vector shift if 13752 // all elements are shifted by the same amount. We can't do this in legalize 13753 // because the a constant vector is typically transformed to a constant pool 13754 // so we have no knowledge of the shift amount. 13755 if (!Subtarget->hasSSE2()) 13756 return SDValue(); 13757 13758 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13759 (!Subtarget->hasAVX2() || 13760 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13761 return SDValue(); 13762 13763 SDValue ShAmtOp = N->getOperand(1); 13764 EVT EltVT = VT.getVectorElementType(); 13765 DebugLoc DL = N->getDebugLoc(); 13766 SDValue BaseShAmt = SDValue(); 13767 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13768 unsigned NumElts = VT.getVectorNumElements(); 13769 unsigned i = 0; 13770 for (; i != NumElts; ++i) { 13771 SDValue Arg = ShAmtOp.getOperand(i); 13772 if (Arg.getOpcode() == ISD::UNDEF) continue; 13773 BaseShAmt = Arg; 13774 break; 13775 } 13776 // Handle the case where the build_vector is all undef 13777 // FIXME: Should DAG allow this? 13778 if (i == NumElts) 13779 return SDValue(); 13780 13781 for (; i != NumElts; ++i) { 13782 SDValue Arg = ShAmtOp.getOperand(i); 13783 if (Arg.getOpcode() == ISD::UNDEF) continue; 13784 if (Arg != BaseShAmt) { 13785 return SDValue(); 13786 } 13787 } 13788 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13789 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13790 SDValue InVec = ShAmtOp.getOperand(0); 13791 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13792 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13793 unsigned i = 0; 13794 for (; i != NumElts; ++i) { 13795 SDValue Arg = InVec.getOperand(i); 13796 if (Arg.getOpcode() == ISD::UNDEF) continue; 13797 BaseShAmt = Arg; 13798 break; 13799 } 13800 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13802 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13803 if (C->getZExtValue() == SplatIdx) 13804 BaseShAmt = InVec.getOperand(1); 13805 } 13806 } 13807 if (BaseShAmt.getNode() == 0) { 13808 // Don't create instructions with illegal types after legalize 13809 // types has run. 13810 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13811 !DCI.isBeforeLegalize()) 13812 return SDValue(); 13813 13814 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13815 DAG.getIntPtrConstant(0)); 13816 } 13817 } else 13818 return SDValue(); 13819 13820 // The shift amount is an i32. 13821 if (EltVT.bitsGT(MVT::i32)) 13822 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13823 else if (EltVT.bitsLT(MVT::i32)) 13824 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13825 13826 // The shift amount is identical so we can do a vector shift. 13827 SDValue ValOp = N->getOperand(0); 13828 switch (N->getOpcode()) { 13829 default: 13830 llvm_unreachable("Unknown shift opcode!"); 13831 case ISD::SHL: 13832 switch (VT.getSimpleVT().SimpleTy) { 13833 default: return SDValue(); 13834 case MVT::v2i64: 13835 case MVT::v4i32: 13836 case MVT::v8i16: 13837 case MVT::v4i64: 13838 case MVT::v8i32: 13839 case MVT::v16i16: 13840 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13841 } 13842 case ISD::SRA: 13843 switch (VT.getSimpleVT().SimpleTy) { 13844 default: return SDValue(); 13845 case MVT::v4i32: 13846 case MVT::v8i16: 13847 case MVT::v8i32: 13848 case MVT::v16i16: 13849 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13850 } 13851 case ISD::SRL: 13852 switch (VT.getSimpleVT().SimpleTy) { 13853 default: return SDValue(); 13854 case MVT::v2i64: 13855 case MVT::v4i32: 13856 case MVT::v8i16: 13857 case MVT::v4i64: 13858 case MVT::v8i32: 13859 case MVT::v16i16: 13860 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13861 } 13862 } 13863} 13864 13865 13866// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13867// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13868// and friends. Likewise for OR -> CMPNEQSS. 13869static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13870 TargetLowering::DAGCombinerInfo &DCI, 13871 const X86Subtarget *Subtarget) { 13872 unsigned opcode; 13873 13874 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13875 // we're requiring SSE2 for both. 13876 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13877 SDValue N0 = N->getOperand(0); 13878 SDValue N1 = N->getOperand(1); 13879 SDValue CMP0 = N0->getOperand(1); 13880 SDValue CMP1 = N1->getOperand(1); 13881 DebugLoc DL = N->getDebugLoc(); 13882 13883 // The SETCCs should both refer to the same CMP. 13884 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13885 return SDValue(); 13886 13887 SDValue CMP00 = CMP0->getOperand(0); 13888 SDValue CMP01 = CMP0->getOperand(1); 13889 EVT VT = CMP00.getValueType(); 13890 13891 if (VT == MVT::f32 || VT == MVT::f64) { 13892 bool ExpectingFlags = false; 13893 // Check for any users that want flags: 13894 for (SDNode::use_iterator UI = N->use_begin(), 13895 UE = N->use_end(); 13896 !ExpectingFlags && UI != UE; ++UI) 13897 switch (UI->getOpcode()) { 13898 default: 13899 case ISD::BR_CC: 13900 case ISD::BRCOND: 13901 case ISD::SELECT: 13902 ExpectingFlags = true; 13903 break; 13904 case ISD::CopyToReg: 13905 case ISD::SIGN_EXTEND: 13906 case ISD::ZERO_EXTEND: 13907 case ISD::ANY_EXTEND: 13908 break; 13909 } 13910 13911 if (!ExpectingFlags) { 13912 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13913 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13914 13915 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13916 X86::CondCode tmp = cc0; 13917 cc0 = cc1; 13918 cc1 = tmp; 13919 } 13920 13921 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13922 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13923 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13924 X86ISD::NodeType NTOperator = is64BitFP ? 13925 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13926 // FIXME: need symbolic constants for these magic numbers. 13927 // See X86ATTInstPrinter.cpp:printSSECC(). 13928 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13929 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13930 DAG.getConstant(x86cc, MVT::i8)); 13931 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13932 OnesOrZeroesF); 13933 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13934 DAG.getConstant(1, MVT::i32)); 13935 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13936 return OneBitOfTruth; 13937 } 13938 } 13939 } 13940 } 13941 return SDValue(); 13942} 13943 13944/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13945/// so it can be folded inside ANDNP. 13946static bool CanFoldXORWithAllOnes(const SDNode *N) { 13947 EVT VT = N->getValueType(0); 13948 13949 // Match direct AllOnes for 128 and 256-bit vectors 13950 if (ISD::isBuildVectorAllOnes(N)) 13951 return true; 13952 13953 // Look through a bit convert. 13954 if (N->getOpcode() == ISD::BITCAST) 13955 N = N->getOperand(0).getNode(); 13956 13957 // Sometimes the operand may come from a insert_subvector building a 256-bit 13958 // allones vector 13959 if (VT.getSizeInBits() == 256 && 13960 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13961 SDValue V1 = N->getOperand(0); 13962 SDValue V2 = N->getOperand(1); 13963 13964 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13965 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13966 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13967 ISD::isBuildVectorAllOnes(V2.getNode())) 13968 return true; 13969 } 13970 13971 return false; 13972} 13973 13974static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13975 TargetLowering::DAGCombinerInfo &DCI, 13976 const X86Subtarget *Subtarget) { 13977 if (DCI.isBeforeLegalizeOps()) 13978 return SDValue(); 13979 13980 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13981 if (R.getNode()) 13982 return R; 13983 13984 EVT VT = N->getValueType(0); 13985 13986 // Create ANDN, BLSI, and BLSR instructions 13987 // BLSI is X & (-X) 13988 // BLSR is X & (X-1) 13989 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13990 SDValue N0 = N->getOperand(0); 13991 SDValue N1 = N->getOperand(1); 13992 DebugLoc DL = N->getDebugLoc(); 13993 13994 // Check LHS for not 13995 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13996 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13997 // Check RHS for not 13998 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13999 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14000 14001 // Check LHS for neg 14002 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14003 isZero(N0.getOperand(0))) 14004 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14005 14006 // Check RHS for neg 14007 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14008 isZero(N1.getOperand(0))) 14009 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14010 14011 // Check LHS for X-1 14012 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14013 isAllOnes(N0.getOperand(1))) 14014 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14015 14016 // Check RHS for X-1 14017 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14018 isAllOnes(N1.getOperand(1))) 14019 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14020 14021 return SDValue(); 14022 } 14023 14024 // Want to form ANDNP nodes: 14025 // 1) In the hopes of then easily combining them with OR and AND nodes 14026 // to form PBLEND/PSIGN. 14027 // 2) To match ANDN packed intrinsics 14028 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14029 return SDValue(); 14030 14031 SDValue N0 = N->getOperand(0); 14032 SDValue N1 = N->getOperand(1); 14033 DebugLoc DL = N->getDebugLoc(); 14034 14035 // Check LHS for vnot 14036 if (N0.getOpcode() == ISD::XOR && 14037 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14038 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14039 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14040 14041 // Check RHS for vnot 14042 if (N1.getOpcode() == ISD::XOR && 14043 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14044 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14045 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14046 14047 return SDValue(); 14048} 14049 14050static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14051 TargetLowering::DAGCombinerInfo &DCI, 14052 const X86Subtarget *Subtarget) { 14053 if (DCI.isBeforeLegalizeOps()) 14054 return SDValue(); 14055 14056 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14057 if (R.getNode()) 14058 return R; 14059 14060 EVT VT = N->getValueType(0); 14061 14062 SDValue N0 = N->getOperand(0); 14063 SDValue N1 = N->getOperand(1); 14064 14065 // look for psign/blend 14066 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14067 if (!Subtarget->hasSSSE3() || 14068 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14069 return SDValue(); 14070 14071 // Canonicalize pandn to RHS 14072 if (N0.getOpcode() == X86ISD::ANDNP) 14073 std::swap(N0, N1); 14074 // or (and (m, y), (pandn m, x)) 14075 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14076 SDValue Mask = N1.getOperand(0); 14077 SDValue X = N1.getOperand(1); 14078 SDValue Y; 14079 if (N0.getOperand(0) == Mask) 14080 Y = N0.getOperand(1); 14081 if (N0.getOperand(1) == Mask) 14082 Y = N0.getOperand(0); 14083 14084 // Check to see if the mask appeared in both the AND and ANDNP and 14085 if (!Y.getNode()) 14086 return SDValue(); 14087 14088 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14089 // Look through mask bitcast. 14090 if (Mask.getOpcode() == ISD::BITCAST) 14091 Mask = Mask.getOperand(0); 14092 if (X.getOpcode() == ISD::BITCAST) 14093 X = X.getOperand(0); 14094 if (Y.getOpcode() == ISD::BITCAST) 14095 Y = Y.getOperand(0); 14096 14097 EVT MaskVT = Mask.getValueType(); 14098 14099 // Validate that the Mask operand is a vector sra node. 14100 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14101 // there is no psrai.b 14102 if (Mask.getOpcode() != X86ISD::VSRAI) 14103 return SDValue(); 14104 14105 // Check that the SRA is all signbits. 14106 SDValue SraC = Mask.getOperand(1); 14107 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14108 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14109 if ((SraAmt + 1) != EltBits) 14110 return SDValue(); 14111 14112 DebugLoc DL = N->getDebugLoc(); 14113 14114 // Now we know we at least have a plendvb with the mask val. See if 14115 // we can form a psignb/w/d. 14116 // psign = x.type == y.type == mask.type && y = sub(0, x); 14117 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14118 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14119 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14120 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14121 "Unsupported VT for PSIGN"); 14122 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14123 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14124 } 14125 // PBLENDVB only available on SSE 4.1 14126 if (!Subtarget->hasSSE41()) 14127 return SDValue(); 14128 14129 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14130 14131 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14132 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14133 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14134 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14135 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14136 } 14137 } 14138 14139 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14140 return SDValue(); 14141 14142 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14143 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14144 std::swap(N0, N1); 14145 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14146 return SDValue(); 14147 if (!N0.hasOneUse() || !N1.hasOneUse()) 14148 return SDValue(); 14149 14150 SDValue ShAmt0 = N0.getOperand(1); 14151 if (ShAmt0.getValueType() != MVT::i8) 14152 return SDValue(); 14153 SDValue ShAmt1 = N1.getOperand(1); 14154 if (ShAmt1.getValueType() != MVT::i8) 14155 return SDValue(); 14156 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14157 ShAmt0 = ShAmt0.getOperand(0); 14158 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14159 ShAmt1 = ShAmt1.getOperand(0); 14160 14161 DebugLoc DL = N->getDebugLoc(); 14162 unsigned Opc = X86ISD::SHLD; 14163 SDValue Op0 = N0.getOperand(0); 14164 SDValue Op1 = N1.getOperand(0); 14165 if (ShAmt0.getOpcode() == ISD::SUB) { 14166 Opc = X86ISD::SHRD; 14167 std::swap(Op0, Op1); 14168 std::swap(ShAmt0, ShAmt1); 14169 } 14170 14171 unsigned Bits = VT.getSizeInBits(); 14172 if (ShAmt1.getOpcode() == ISD::SUB) { 14173 SDValue Sum = ShAmt1.getOperand(0); 14174 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14175 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14176 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14177 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14178 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14179 return DAG.getNode(Opc, DL, VT, 14180 Op0, Op1, 14181 DAG.getNode(ISD::TRUNCATE, DL, 14182 MVT::i8, ShAmt0)); 14183 } 14184 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14185 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14186 if (ShAmt0C && 14187 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14188 return DAG.getNode(Opc, DL, VT, 14189 N0.getOperand(0), N1.getOperand(0), 14190 DAG.getNode(ISD::TRUNCATE, DL, 14191 MVT::i8, ShAmt0)); 14192 } 14193 14194 return SDValue(); 14195} 14196 14197// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14198static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14199 TargetLowering::DAGCombinerInfo &DCI, 14200 const X86Subtarget *Subtarget) { 14201 if (DCI.isBeforeLegalizeOps()) 14202 return SDValue(); 14203 14204 EVT VT = N->getValueType(0); 14205 14206 if (VT != MVT::i32 && VT != MVT::i64) 14207 return SDValue(); 14208 14209 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14210 14211 // Create BLSMSK instructions by finding X ^ (X-1) 14212 SDValue N0 = N->getOperand(0); 14213 SDValue N1 = N->getOperand(1); 14214 DebugLoc DL = N->getDebugLoc(); 14215 14216 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14217 isAllOnes(N0.getOperand(1))) 14218 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14219 14220 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14221 isAllOnes(N1.getOperand(1))) 14222 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14223 14224 return SDValue(); 14225} 14226 14227/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14228static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14229 const X86Subtarget *Subtarget) { 14230 LoadSDNode *Ld = cast<LoadSDNode>(N); 14231 EVT RegVT = Ld->getValueType(0); 14232 EVT MemVT = Ld->getMemoryVT(); 14233 DebugLoc dl = Ld->getDebugLoc(); 14234 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14235 14236 ISD::LoadExtType Ext = Ld->getExtensionType(); 14237 14238 // If this is a vector EXT Load then attempt to optimize it using a 14239 // shuffle. We need SSE4 for the shuffles. 14240 // TODO: It is possible to support ZExt by zeroing the undef values 14241 // during the shuffle phase or after the shuffle. 14242 if (RegVT.isVector() && RegVT.isInteger() && 14243 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14244 assert(MemVT != RegVT && "Cannot extend to the same type"); 14245 assert(MemVT.isVector() && "Must load a vector from memory"); 14246 14247 unsigned NumElems = RegVT.getVectorNumElements(); 14248 unsigned RegSz = RegVT.getSizeInBits(); 14249 unsigned MemSz = MemVT.getSizeInBits(); 14250 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14251 // All sizes must be a power of two 14252 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14253 14254 // Attempt to load the original value using a single load op. 14255 // Find a scalar type which is equal to the loaded word size. 14256 MVT SclrLoadTy = MVT::i8; 14257 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14258 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14259 MVT Tp = (MVT::SimpleValueType)tp; 14260 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14261 SclrLoadTy = Tp; 14262 break; 14263 } 14264 } 14265 14266 // Proceed if a load word is found. 14267 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14268 14269 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14270 RegSz/SclrLoadTy.getSizeInBits()); 14271 14272 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14273 RegSz/MemVT.getScalarType().getSizeInBits()); 14274 // Can't shuffle using an illegal type. 14275 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14276 14277 // Perform a single load. 14278 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14279 Ld->getBasePtr(), 14280 Ld->getPointerInfo(), Ld->isVolatile(), 14281 Ld->isNonTemporal(), Ld->isInvariant(), 14282 Ld->getAlignment()); 14283 14284 // Insert the word loaded into a vector. 14285 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14286 LoadUnitVecVT, ScalarLoad); 14287 14288 // Bitcast the loaded value to a vector of the original element type, in 14289 // the size of the target vector type. 14290 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14291 ScalarInVector); 14292 unsigned SizeRatio = RegSz/MemSz; 14293 14294 // Redistribute the loaded elements into the different locations. 14295 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14296 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14297 14298 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14299 DAG.getUNDEF(SlicedVec.getValueType()), 14300 ShuffleVec.data()); 14301 14302 // Bitcast to the requested type. 14303 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14304 // Replace the original load with the new sequence 14305 // and return the new chain. 14306 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14307 return SDValue(ScalarLoad.getNode(), 1); 14308 } 14309 14310 return SDValue(); 14311} 14312 14313/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14314static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14315 const X86Subtarget *Subtarget) { 14316 StoreSDNode *St = cast<StoreSDNode>(N); 14317 EVT VT = St->getValue().getValueType(); 14318 EVT StVT = St->getMemoryVT(); 14319 DebugLoc dl = St->getDebugLoc(); 14320 SDValue StoredVal = St->getOperand(1); 14321 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14322 14323 // If we are saving a concatenation of two XMM registers, perform two stores. 14324 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14325 // 128-bit ones. If in the future the cost becomes only one memory access the 14326 // first version would be better. 14327 if (VT.getSizeInBits() == 256 && 14328 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14329 StoredVal.getNumOperands() == 2) { 14330 14331 SDValue Value0 = StoredVal.getOperand(0); 14332 SDValue Value1 = StoredVal.getOperand(1); 14333 14334 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14335 SDValue Ptr0 = St->getBasePtr(); 14336 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14337 14338 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14339 St->getPointerInfo(), St->isVolatile(), 14340 St->isNonTemporal(), St->getAlignment()); 14341 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14342 St->getPointerInfo(), St->isVolatile(), 14343 St->isNonTemporal(), St->getAlignment()); 14344 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14345 } 14346 14347 // Optimize trunc store (of multiple scalars) to shuffle and store. 14348 // First, pack all of the elements in one place. Next, store to memory 14349 // in fewer chunks. 14350 if (St->isTruncatingStore() && VT.isVector()) { 14351 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14352 unsigned NumElems = VT.getVectorNumElements(); 14353 assert(StVT != VT && "Cannot truncate to the same type"); 14354 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14355 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14356 14357 // From, To sizes and ElemCount must be pow of two 14358 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14359 // We are going to use the original vector elt for storing. 14360 // Accumulated smaller vector elements must be a multiple of the store size. 14361 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14362 14363 unsigned SizeRatio = FromSz / ToSz; 14364 14365 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14366 14367 // Create a type on which we perform the shuffle 14368 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14369 StVT.getScalarType(), NumElems*SizeRatio); 14370 14371 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14372 14373 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14374 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14375 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14376 14377 // Can't shuffle using an illegal type 14378 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14379 14380 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14381 DAG.getUNDEF(WideVec.getValueType()), 14382 ShuffleVec.data()); 14383 // At this point all of the data is stored at the bottom of the 14384 // register. We now need to save it to mem. 14385 14386 // Find the largest store unit 14387 MVT StoreType = MVT::i8; 14388 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14389 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14390 MVT Tp = (MVT::SimpleValueType)tp; 14391 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14392 StoreType = Tp; 14393 } 14394 14395 // Bitcast the original vector into a vector of store-size units 14396 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14397 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14398 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14399 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14400 SmallVector<SDValue, 8> Chains; 14401 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14402 TLI.getPointerTy()); 14403 SDValue Ptr = St->getBasePtr(); 14404 14405 // Perform one or more big stores into memory. 14406 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14407 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14408 StoreType, ShuffWide, 14409 DAG.getIntPtrConstant(i)); 14410 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14411 St->getPointerInfo(), St->isVolatile(), 14412 St->isNonTemporal(), St->getAlignment()); 14413 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14414 Chains.push_back(Ch); 14415 } 14416 14417 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14418 Chains.size()); 14419 } 14420 14421 14422 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14423 // the FP state in cases where an emms may be missing. 14424 // A preferable solution to the general problem is to figure out the right 14425 // places to insert EMMS. This qualifies as a quick hack. 14426 14427 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14428 if (VT.getSizeInBits() != 64) 14429 return SDValue(); 14430 14431 const Function *F = DAG.getMachineFunction().getFunction(); 14432 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14433 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14434 && Subtarget->hasSSE2(); 14435 if ((VT.isVector() || 14436 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14437 isa<LoadSDNode>(St->getValue()) && 14438 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14439 St->getChain().hasOneUse() && !St->isVolatile()) { 14440 SDNode* LdVal = St->getValue().getNode(); 14441 LoadSDNode *Ld = 0; 14442 int TokenFactorIndex = -1; 14443 SmallVector<SDValue, 8> Ops; 14444 SDNode* ChainVal = St->getChain().getNode(); 14445 // Must be a store of a load. We currently handle two cases: the load 14446 // is a direct child, and it's under an intervening TokenFactor. It is 14447 // possible to dig deeper under nested TokenFactors. 14448 if (ChainVal == LdVal) 14449 Ld = cast<LoadSDNode>(St->getChain()); 14450 else if (St->getValue().hasOneUse() && 14451 ChainVal->getOpcode() == ISD::TokenFactor) { 14452 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14453 if (ChainVal->getOperand(i).getNode() == LdVal) { 14454 TokenFactorIndex = i; 14455 Ld = cast<LoadSDNode>(St->getValue()); 14456 } else 14457 Ops.push_back(ChainVal->getOperand(i)); 14458 } 14459 } 14460 14461 if (!Ld || !ISD::isNormalLoad(Ld)) 14462 return SDValue(); 14463 14464 // If this is not the MMX case, i.e. we are just turning i64 load/store 14465 // into f64 load/store, avoid the transformation if there are multiple 14466 // uses of the loaded value. 14467 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14468 return SDValue(); 14469 14470 DebugLoc LdDL = Ld->getDebugLoc(); 14471 DebugLoc StDL = N->getDebugLoc(); 14472 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14473 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14474 // pair instead. 14475 if (Subtarget->is64Bit() || F64IsLegal) { 14476 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14477 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14478 Ld->getPointerInfo(), Ld->isVolatile(), 14479 Ld->isNonTemporal(), Ld->isInvariant(), 14480 Ld->getAlignment()); 14481 SDValue NewChain = NewLd.getValue(1); 14482 if (TokenFactorIndex != -1) { 14483 Ops.push_back(NewChain); 14484 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14485 Ops.size()); 14486 } 14487 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14488 St->getPointerInfo(), 14489 St->isVolatile(), St->isNonTemporal(), 14490 St->getAlignment()); 14491 } 14492 14493 // Otherwise, lower to two pairs of 32-bit loads / stores. 14494 SDValue LoAddr = Ld->getBasePtr(); 14495 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14496 DAG.getConstant(4, MVT::i32)); 14497 14498 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14499 Ld->getPointerInfo(), 14500 Ld->isVolatile(), Ld->isNonTemporal(), 14501 Ld->isInvariant(), Ld->getAlignment()); 14502 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14503 Ld->getPointerInfo().getWithOffset(4), 14504 Ld->isVolatile(), Ld->isNonTemporal(), 14505 Ld->isInvariant(), 14506 MinAlign(Ld->getAlignment(), 4)); 14507 14508 SDValue NewChain = LoLd.getValue(1); 14509 if (TokenFactorIndex != -1) { 14510 Ops.push_back(LoLd); 14511 Ops.push_back(HiLd); 14512 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14513 Ops.size()); 14514 } 14515 14516 LoAddr = St->getBasePtr(); 14517 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14518 DAG.getConstant(4, MVT::i32)); 14519 14520 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14521 St->getPointerInfo(), 14522 St->isVolatile(), St->isNonTemporal(), 14523 St->getAlignment()); 14524 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14525 St->getPointerInfo().getWithOffset(4), 14526 St->isVolatile(), 14527 St->isNonTemporal(), 14528 MinAlign(St->getAlignment(), 4)); 14529 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14530 } 14531 return SDValue(); 14532} 14533 14534/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14535/// and return the operands for the horizontal operation in LHS and RHS. A 14536/// horizontal operation performs the binary operation on successive elements 14537/// of its first operand, then on successive elements of its second operand, 14538/// returning the resulting values in a vector. For example, if 14539/// A = < float a0, float a1, float a2, float a3 > 14540/// and 14541/// B = < float b0, float b1, float b2, float b3 > 14542/// then the result of doing a horizontal operation on A and B is 14543/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14544/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14545/// A horizontal-op B, for some already available A and B, and if so then LHS is 14546/// set to A, RHS to B, and the routine returns 'true'. 14547/// Note that the binary operation should have the property that if one of the 14548/// operands is UNDEF then the result is UNDEF. 14549static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14550 // Look for the following pattern: if 14551 // A = < float a0, float a1, float a2, float a3 > 14552 // B = < float b0, float b1, float b2, float b3 > 14553 // and 14554 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14555 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14556 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14557 // which is A horizontal-op B. 14558 14559 // At least one of the operands should be a vector shuffle. 14560 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14561 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14562 return false; 14563 14564 EVT VT = LHS.getValueType(); 14565 14566 assert((VT.is128BitVector() || VT.is256BitVector()) && 14567 "Unsupported vector type for horizontal add/sub"); 14568 14569 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14570 // operate independently on 128-bit lanes. 14571 unsigned NumElts = VT.getVectorNumElements(); 14572 unsigned NumLanes = VT.getSizeInBits()/128; 14573 unsigned NumLaneElts = NumElts / NumLanes; 14574 assert((NumLaneElts % 2 == 0) && 14575 "Vector type should have an even number of elements in each lane"); 14576 unsigned HalfLaneElts = NumLaneElts/2; 14577 14578 // View LHS in the form 14579 // LHS = VECTOR_SHUFFLE A, B, LMask 14580 // If LHS is not a shuffle then pretend it is the shuffle 14581 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14582 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14583 // type VT. 14584 SDValue A, B; 14585 SmallVector<int, 16> LMask(NumElts); 14586 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14587 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14588 A = LHS.getOperand(0); 14589 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14590 B = LHS.getOperand(1); 14591 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14592 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14593 } else { 14594 if (LHS.getOpcode() != ISD::UNDEF) 14595 A = LHS; 14596 for (unsigned i = 0; i != NumElts; ++i) 14597 LMask[i] = i; 14598 } 14599 14600 // Likewise, view RHS in the form 14601 // RHS = VECTOR_SHUFFLE C, D, RMask 14602 SDValue C, D; 14603 SmallVector<int, 16> RMask(NumElts); 14604 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14605 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14606 C = RHS.getOperand(0); 14607 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14608 D = RHS.getOperand(1); 14609 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14610 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14611 } else { 14612 if (RHS.getOpcode() != ISD::UNDEF) 14613 C = RHS; 14614 for (unsigned i = 0; i != NumElts; ++i) 14615 RMask[i] = i; 14616 } 14617 14618 // Check that the shuffles are both shuffling the same vectors. 14619 if (!(A == C && B == D) && !(A == D && B == C)) 14620 return false; 14621 14622 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14623 if (!A.getNode() && !B.getNode()) 14624 return false; 14625 14626 // If A and B occur in reverse order in RHS, then "swap" them (which means 14627 // rewriting the mask). 14628 if (A != C) 14629 CommuteVectorShuffleMask(RMask, NumElts); 14630 14631 // At this point LHS and RHS are equivalent to 14632 // LHS = VECTOR_SHUFFLE A, B, LMask 14633 // RHS = VECTOR_SHUFFLE A, B, RMask 14634 // Check that the masks correspond to performing a horizontal operation. 14635 for (unsigned i = 0; i != NumElts; ++i) { 14636 int LIdx = LMask[i], RIdx = RMask[i]; 14637 14638 // Ignore any UNDEF components. 14639 if (LIdx < 0 || RIdx < 0 || 14640 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14641 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14642 continue; 14643 14644 // Check that successive elements are being operated on. If not, this is 14645 // not a horizontal operation. 14646 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14647 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14648 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14649 if (!(LIdx == Index && RIdx == Index + 1) && 14650 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14651 return false; 14652 } 14653 14654 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14655 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14656 return true; 14657} 14658 14659/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14660static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14661 const X86Subtarget *Subtarget) { 14662 EVT VT = N->getValueType(0); 14663 SDValue LHS = N->getOperand(0); 14664 SDValue RHS = N->getOperand(1); 14665 14666 // Try to synthesize horizontal adds from adds of shuffles. 14667 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14668 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14669 isHorizontalBinOp(LHS, RHS, true)) 14670 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14671 return SDValue(); 14672} 14673 14674/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14675static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14676 const X86Subtarget *Subtarget) { 14677 EVT VT = N->getValueType(0); 14678 SDValue LHS = N->getOperand(0); 14679 SDValue RHS = N->getOperand(1); 14680 14681 // Try to synthesize horizontal subs from subs of shuffles. 14682 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14683 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14684 isHorizontalBinOp(LHS, RHS, false)) 14685 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14686 return SDValue(); 14687} 14688 14689/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14690/// X86ISD::FXOR nodes. 14691static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14692 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14693 // F[X]OR(0.0, x) -> x 14694 // F[X]OR(x, 0.0) -> x 14695 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14696 if (C->getValueAPF().isPosZero()) 14697 return N->getOperand(1); 14698 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14699 if (C->getValueAPF().isPosZero()) 14700 return N->getOperand(0); 14701 return SDValue(); 14702} 14703 14704/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14705static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14706 // FAND(0.0, x) -> 0.0 14707 // FAND(x, 0.0) -> 0.0 14708 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14709 if (C->getValueAPF().isPosZero()) 14710 return N->getOperand(0); 14711 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14712 if (C->getValueAPF().isPosZero()) 14713 return N->getOperand(1); 14714 return SDValue(); 14715} 14716 14717static SDValue PerformBTCombine(SDNode *N, 14718 SelectionDAG &DAG, 14719 TargetLowering::DAGCombinerInfo &DCI) { 14720 // BT ignores high bits in the bit index operand. 14721 SDValue Op1 = N->getOperand(1); 14722 if (Op1.hasOneUse()) { 14723 unsigned BitWidth = Op1.getValueSizeInBits(); 14724 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14725 APInt KnownZero, KnownOne; 14726 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14727 !DCI.isBeforeLegalizeOps()); 14728 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14729 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14730 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14731 DCI.CommitTargetLoweringOpt(TLO); 14732 } 14733 return SDValue(); 14734} 14735 14736static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14737 SDValue Op = N->getOperand(0); 14738 if (Op.getOpcode() == ISD::BITCAST) 14739 Op = Op.getOperand(0); 14740 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14741 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14742 VT.getVectorElementType().getSizeInBits() == 14743 OpVT.getVectorElementType().getSizeInBits()) { 14744 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14745 } 14746 return SDValue(); 14747} 14748 14749static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14750 TargetLowering::DAGCombinerInfo &DCI, 14751 const X86Subtarget *Subtarget) { 14752 if (!DCI.isBeforeLegalizeOps()) 14753 return SDValue(); 14754 14755 if (!Subtarget->hasAVX()) 14756 return SDValue(); 14757 14758 // Optimize vectors in AVX mode 14759 // Sign extend v8i16 to v8i32 and 14760 // v4i32 to v4i64 14761 // 14762 // Divide input vector into two parts 14763 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14764 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14765 // concat the vectors to original VT 14766 14767 EVT VT = N->getValueType(0); 14768 SDValue Op = N->getOperand(0); 14769 EVT OpVT = Op.getValueType(); 14770 DebugLoc dl = N->getDebugLoc(); 14771 14772 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14773 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14774 14775 unsigned NumElems = OpVT.getVectorNumElements(); 14776 SmallVector<int,8> ShufMask1(NumElems, -1); 14777 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; 14778 14779 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14780 ShufMask1.data()); 14781 14782 SmallVector<int,8> ShufMask2(NumElems, -1); 14783 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; 14784 14785 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14786 ShufMask2.data()); 14787 14788 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14789 VT.getVectorNumElements()/2); 14790 14791 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14792 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14793 14794 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14795 } 14796 return SDValue(); 14797} 14798 14799static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14800 const X86Subtarget *Subtarget) { 14801 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14802 // (and (i32 x86isd::setcc_carry), 1) 14803 // This eliminates the zext. This transformation is necessary because 14804 // ISD::SETCC is always legalized to i8. 14805 DebugLoc dl = N->getDebugLoc(); 14806 SDValue N0 = N->getOperand(0); 14807 EVT VT = N->getValueType(0); 14808 EVT OpVT = N0.getValueType(); 14809 14810 if (N0.getOpcode() == ISD::AND && 14811 N0.hasOneUse() && 14812 N0.getOperand(0).hasOneUse()) { 14813 SDValue N00 = N0.getOperand(0); 14814 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14815 return SDValue(); 14816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14817 if (!C || C->getZExtValue() != 1) 14818 return SDValue(); 14819 return DAG.getNode(ISD::AND, dl, VT, 14820 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14821 N00.getOperand(0), N00.getOperand(1)), 14822 DAG.getConstant(1, VT)); 14823 } 14824 // Optimize vectors in AVX mode: 14825 // 14826 // v8i16 -> v8i32 14827 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14828 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14829 // Concat upper and lower parts. 14830 // 14831 // v4i32 -> v4i64 14832 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14833 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14834 // Concat upper and lower parts. 14835 // 14836 if (Subtarget->hasAVX()) { 14837 14838 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14839 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14840 14841 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14842 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14843 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14844 14845 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14846 VT.getVectorNumElements()/2); 14847 14848 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14849 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14850 14851 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14852 } 14853 } 14854 14855 14856 return SDValue(); 14857} 14858 14859// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14860static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14861 unsigned X86CC = N->getConstantOperandVal(0); 14862 SDValue EFLAG = N->getOperand(1); 14863 DebugLoc DL = N->getDebugLoc(); 14864 14865 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14866 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14867 // cases. 14868 if (X86CC == X86::COND_B) 14869 return DAG.getNode(ISD::AND, DL, MVT::i8, 14870 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14871 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14872 DAG.getConstant(1, MVT::i8)); 14873 14874 return SDValue(); 14875} 14876 14877static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14878 const X86TargetLowering *XTLI) { 14879 SDValue Op0 = N->getOperand(0); 14880 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14881 // a 32-bit target where SSE doesn't support i64->FP operations. 14882 if (Op0.getOpcode() == ISD::LOAD) { 14883 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14884 EVT VT = Ld->getValueType(0); 14885 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14886 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14887 !XTLI->getSubtarget()->is64Bit() && 14888 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14889 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14890 Ld->getChain(), Op0, DAG); 14891 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14892 return FILDChain; 14893 } 14894 } 14895 return SDValue(); 14896} 14897 14898// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14899static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14900 X86TargetLowering::DAGCombinerInfo &DCI) { 14901 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14902 // the result is either zero or one (depending on the input carry bit). 14903 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14904 if (X86::isZeroNode(N->getOperand(0)) && 14905 X86::isZeroNode(N->getOperand(1)) && 14906 // We don't have a good way to replace an EFLAGS use, so only do this when 14907 // dead right now. 14908 SDValue(N, 1).use_empty()) { 14909 DebugLoc DL = N->getDebugLoc(); 14910 EVT VT = N->getValueType(0); 14911 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14912 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14913 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14914 DAG.getConstant(X86::COND_B,MVT::i8), 14915 N->getOperand(2)), 14916 DAG.getConstant(1, VT)); 14917 return DCI.CombineTo(N, Res1, CarryOut); 14918 } 14919 14920 return SDValue(); 14921} 14922 14923// fold (add Y, (sete X, 0)) -> adc 0, Y 14924// (add Y, (setne X, 0)) -> sbb -1, Y 14925// (sub (sete X, 0), Y) -> sbb 0, Y 14926// (sub (setne X, 0), Y) -> adc -1, Y 14927static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14928 DebugLoc DL = N->getDebugLoc(); 14929 14930 // Look through ZExts. 14931 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14932 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14933 return SDValue(); 14934 14935 SDValue SetCC = Ext.getOperand(0); 14936 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14937 return SDValue(); 14938 14939 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14940 if (CC != X86::COND_E && CC != X86::COND_NE) 14941 return SDValue(); 14942 14943 SDValue Cmp = SetCC.getOperand(1); 14944 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14945 !X86::isZeroNode(Cmp.getOperand(1)) || 14946 !Cmp.getOperand(0).getValueType().isInteger()) 14947 return SDValue(); 14948 14949 SDValue CmpOp0 = Cmp.getOperand(0); 14950 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14951 DAG.getConstant(1, CmpOp0.getValueType())); 14952 14953 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14954 if (CC == X86::COND_NE) 14955 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14956 DL, OtherVal.getValueType(), OtherVal, 14957 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14958 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14959 DL, OtherVal.getValueType(), OtherVal, 14960 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14961} 14962 14963/// PerformADDCombine - Do target-specific dag combines on integer adds. 14964static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14965 const X86Subtarget *Subtarget) { 14966 EVT VT = N->getValueType(0); 14967 SDValue Op0 = N->getOperand(0); 14968 SDValue Op1 = N->getOperand(1); 14969 14970 // Try to synthesize horizontal adds from adds of shuffles. 14971 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14972 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14973 isHorizontalBinOp(Op0, Op1, true)) 14974 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14975 14976 return OptimizeConditionalInDecrement(N, DAG); 14977} 14978 14979static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14980 const X86Subtarget *Subtarget) { 14981 SDValue Op0 = N->getOperand(0); 14982 SDValue Op1 = N->getOperand(1); 14983 14984 // X86 can't encode an immediate LHS of a sub. See if we can push the 14985 // negation into a preceding instruction. 14986 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14987 // If the RHS of the sub is a XOR with one use and a constant, invert the 14988 // immediate. Then add one to the LHS of the sub so we can turn 14989 // X-Y -> X+~Y+1, saving one register. 14990 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14991 isa<ConstantSDNode>(Op1.getOperand(1))) { 14992 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14993 EVT VT = Op0.getValueType(); 14994 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14995 Op1.getOperand(0), 14996 DAG.getConstant(~XorC, VT)); 14997 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14998 DAG.getConstant(C->getAPIntValue()+1, VT)); 14999 } 15000 } 15001 15002 // Try to synthesize horizontal adds from adds of shuffles. 15003 EVT VT = N->getValueType(0); 15004 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15005 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15006 isHorizontalBinOp(Op0, Op1, true)) 15007 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15008 15009 return OptimizeConditionalInDecrement(N, DAG); 15010} 15011 15012SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15013 DAGCombinerInfo &DCI) const { 15014 SelectionDAG &DAG = DCI.DAG; 15015 switch (N->getOpcode()) { 15016 default: break; 15017 case ISD::EXTRACT_VECTOR_ELT: 15018 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15019 case ISD::VSELECT: 15020 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15021 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15022 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15023 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15024 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15025 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15026 case ISD::SHL: 15027 case ISD::SRA: 15028 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15029 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15030 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15031 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15032 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15033 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15034 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15035 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15036 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15037 case X86ISD::FXOR: 15038 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15039 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15040 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15041 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15042 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 15043 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15044 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15045 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15046 case X86ISD::SHUFP: // Handle all target specific shuffles 15047 case X86ISD::PALIGN: 15048 case X86ISD::UNPCKH: 15049 case X86ISD::UNPCKL: 15050 case X86ISD::MOVHLPS: 15051 case X86ISD::MOVLHPS: 15052 case X86ISD::PSHUFD: 15053 case X86ISD::PSHUFHW: 15054 case X86ISD::PSHUFLW: 15055 case X86ISD::MOVSS: 15056 case X86ISD::MOVSD: 15057 case X86ISD::VPERMILP: 15058 case X86ISD::VPERM2X128: 15059 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15060 } 15061 15062 return SDValue(); 15063} 15064 15065/// isTypeDesirableForOp - Return true if the target has native support for 15066/// the specified value type and it is 'desirable' to use the type for the 15067/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15068/// instruction encodings are longer and some i16 instructions are slow. 15069bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15070 if (!isTypeLegal(VT)) 15071 return false; 15072 if (VT != MVT::i16) 15073 return true; 15074 15075 switch (Opc) { 15076 default: 15077 return true; 15078 case ISD::LOAD: 15079 case ISD::SIGN_EXTEND: 15080 case ISD::ZERO_EXTEND: 15081 case ISD::ANY_EXTEND: 15082 case ISD::SHL: 15083 case ISD::SRL: 15084 case ISD::SUB: 15085 case ISD::ADD: 15086 case ISD::MUL: 15087 case ISD::AND: 15088 case ISD::OR: 15089 case ISD::XOR: 15090 return false; 15091 } 15092} 15093 15094/// IsDesirableToPromoteOp - This method query the target whether it is 15095/// beneficial for dag combiner to promote the specified node. If true, it 15096/// should return the desired promotion type by reference. 15097bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15098 EVT VT = Op.getValueType(); 15099 if (VT != MVT::i16) 15100 return false; 15101 15102 bool Promote = false; 15103 bool Commute = false; 15104 switch (Op.getOpcode()) { 15105 default: break; 15106 case ISD::LOAD: { 15107 LoadSDNode *LD = cast<LoadSDNode>(Op); 15108 // If the non-extending load has a single use and it's not live out, then it 15109 // might be folded. 15110 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15111 Op.hasOneUse()*/) { 15112 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15113 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15114 // The only case where we'd want to promote LOAD (rather then it being 15115 // promoted as an operand is when it's only use is liveout. 15116 if (UI->getOpcode() != ISD::CopyToReg) 15117 return false; 15118 } 15119 } 15120 Promote = true; 15121 break; 15122 } 15123 case ISD::SIGN_EXTEND: 15124 case ISD::ZERO_EXTEND: 15125 case ISD::ANY_EXTEND: 15126 Promote = true; 15127 break; 15128 case ISD::SHL: 15129 case ISD::SRL: { 15130 SDValue N0 = Op.getOperand(0); 15131 // Look out for (store (shl (load), x)). 15132 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15133 return false; 15134 Promote = true; 15135 break; 15136 } 15137 case ISD::ADD: 15138 case ISD::MUL: 15139 case ISD::AND: 15140 case ISD::OR: 15141 case ISD::XOR: 15142 Commute = true; 15143 // fallthrough 15144 case ISD::SUB: { 15145 SDValue N0 = Op.getOperand(0); 15146 SDValue N1 = Op.getOperand(1); 15147 if (!Commute && MayFoldLoad(N1)) 15148 return false; 15149 // Avoid disabling potential load folding opportunities. 15150 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15151 return false; 15152 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15153 return false; 15154 Promote = true; 15155 } 15156 } 15157 15158 PVT = MVT::i32; 15159 return Promote; 15160} 15161 15162//===----------------------------------------------------------------------===// 15163// X86 Inline Assembly Support 15164//===----------------------------------------------------------------------===// 15165 15166namespace { 15167 // Helper to match a string separated by whitespace. 15168 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15169 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15170 15171 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15172 StringRef piece(*args[i]); 15173 if (!s.startswith(piece)) // Check if the piece matches. 15174 return false; 15175 15176 s = s.substr(piece.size()); 15177 StringRef::size_type pos = s.find_first_not_of(" \t"); 15178 if (pos == 0) // We matched a prefix. 15179 return false; 15180 15181 s = s.substr(pos); 15182 } 15183 15184 return s.empty(); 15185 } 15186 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15187} 15188 15189bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15190 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15191 15192 std::string AsmStr = IA->getAsmString(); 15193 15194 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15195 if (!Ty || Ty->getBitWidth() % 16 != 0) 15196 return false; 15197 15198 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15199 SmallVector<StringRef, 4> AsmPieces; 15200 SplitString(AsmStr, AsmPieces, ";\n"); 15201 15202 switch (AsmPieces.size()) { 15203 default: return false; 15204 case 1: 15205 // FIXME: this should verify that we are targeting a 486 or better. If not, 15206 // we will turn this bswap into something that will be lowered to logical 15207 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15208 // lower so don't worry about this. 15209 // bswap $0 15210 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15211 matchAsm(AsmPieces[0], "bswapl", "$0") || 15212 matchAsm(AsmPieces[0], "bswapq", "$0") || 15213 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15214 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15215 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15216 // No need to check constraints, nothing other than the equivalent of 15217 // "=r,0" would be valid here. 15218 return IntrinsicLowering::LowerToByteSwap(CI); 15219 } 15220 15221 // rorw $$8, ${0:w} --> llvm.bswap.i16 15222 if (CI->getType()->isIntegerTy(16) && 15223 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15224 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15225 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15226 AsmPieces.clear(); 15227 const std::string &ConstraintsStr = IA->getConstraintString(); 15228 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15229 std::sort(AsmPieces.begin(), AsmPieces.end()); 15230 if (AsmPieces.size() == 4 && 15231 AsmPieces[0] == "~{cc}" && 15232 AsmPieces[1] == "~{dirflag}" && 15233 AsmPieces[2] == "~{flags}" && 15234 AsmPieces[3] == "~{fpsr}") 15235 return IntrinsicLowering::LowerToByteSwap(CI); 15236 } 15237 break; 15238 case 3: 15239 if (CI->getType()->isIntegerTy(32) && 15240 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15241 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15242 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15243 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15244 AsmPieces.clear(); 15245 const std::string &ConstraintsStr = IA->getConstraintString(); 15246 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15247 std::sort(AsmPieces.begin(), AsmPieces.end()); 15248 if (AsmPieces.size() == 4 && 15249 AsmPieces[0] == "~{cc}" && 15250 AsmPieces[1] == "~{dirflag}" && 15251 AsmPieces[2] == "~{flags}" && 15252 AsmPieces[3] == "~{fpsr}") 15253 return IntrinsicLowering::LowerToByteSwap(CI); 15254 } 15255 15256 if (CI->getType()->isIntegerTy(64)) { 15257 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15258 if (Constraints.size() >= 2 && 15259 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15260 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15261 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15262 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15263 matchAsm(AsmPieces[1], "bswap", "%edx") && 15264 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15265 return IntrinsicLowering::LowerToByteSwap(CI); 15266 } 15267 } 15268 break; 15269 } 15270 return false; 15271} 15272 15273 15274 15275/// getConstraintType - Given a constraint letter, return the type of 15276/// constraint it is for this target. 15277X86TargetLowering::ConstraintType 15278X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15279 if (Constraint.size() == 1) { 15280 switch (Constraint[0]) { 15281 case 'R': 15282 case 'q': 15283 case 'Q': 15284 case 'f': 15285 case 't': 15286 case 'u': 15287 case 'y': 15288 case 'x': 15289 case 'Y': 15290 case 'l': 15291 return C_RegisterClass; 15292 case 'a': 15293 case 'b': 15294 case 'c': 15295 case 'd': 15296 case 'S': 15297 case 'D': 15298 case 'A': 15299 return C_Register; 15300 case 'I': 15301 case 'J': 15302 case 'K': 15303 case 'L': 15304 case 'M': 15305 case 'N': 15306 case 'G': 15307 case 'C': 15308 case 'e': 15309 case 'Z': 15310 return C_Other; 15311 default: 15312 break; 15313 } 15314 } 15315 return TargetLowering::getConstraintType(Constraint); 15316} 15317 15318/// Examine constraint type and operand type and determine a weight value. 15319/// This object must already have been set up with the operand type 15320/// and the current alternative constraint selected. 15321TargetLowering::ConstraintWeight 15322 X86TargetLowering::getSingleConstraintMatchWeight( 15323 AsmOperandInfo &info, const char *constraint) const { 15324 ConstraintWeight weight = CW_Invalid; 15325 Value *CallOperandVal = info.CallOperandVal; 15326 // If we don't have a value, we can't do a match, 15327 // but allow it at the lowest weight. 15328 if (CallOperandVal == NULL) 15329 return CW_Default; 15330 Type *type = CallOperandVal->getType(); 15331 // Look at the constraint type. 15332 switch (*constraint) { 15333 default: 15334 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15335 case 'R': 15336 case 'q': 15337 case 'Q': 15338 case 'a': 15339 case 'b': 15340 case 'c': 15341 case 'd': 15342 case 'S': 15343 case 'D': 15344 case 'A': 15345 if (CallOperandVal->getType()->isIntegerTy()) 15346 weight = CW_SpecificReg; 15347 break; 15348 case 'f': 15349 case 't': 15350 case 'u': 15351 if (type->isFloatingPointTy()) 15352 weight = CW_SpecificReg; 15353 break; 15354 case 'y': 15355 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15356 weight = CW_SpecificReg; 15357 break; 15358 case 'x': 15359 case 'Y': 15360 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15361 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15362 weight = CW_Register; 15363 break; 15364 case 'I': 15365 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15366 if (C->getZExtValue() <= 31) 15367 weight = CW_Constant; 15368 } 15369 break; 15370 case 'J': 15371 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15372 if (C->getZExtValue() <= 63) 15373 weight = CW_Constant; 15374 } 15375 break; 15376 case 'K': 15377 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15378 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15379 weight = CW_Constant; 15380 } 15381 break; 15382 case 'L': 15383 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15384 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15385 weight = CW_Constant; 15386 } 15387 break; 15388 case 'M': 15389 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15390 if (C->getZExtValue() <= 3) 15391 weight = CW_Constant; 15392 } 15393 break; 15394 case 'N': 15395 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15396 if (C->getZExtValue() <= 0xff) 15397 weight = CW_Constant; 15398 } 15399 break; 15400 case 'G': 15401 case 'C': 15402 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15403 weight = CW_Constant; 15404 } 15405 break; 15406 case 'e': 15407 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15408 if ((C->getSExtValue() >= -0x80000000LL) && 15409 (C->getSExtValue() <= 0x7fffffffLL)) 15410 weight = CW_Constant; 15411 } 15412 break; 15413 case 'Z': 15414 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15415 if (C->getZExtValue() <= 0xffffffff) 15416 weight = CW_Constant; 15417 } 15418 break; 15419 } 15420 return weight; 15421} 15422 15423/// LowerXConstraint - try to replace an X constraint, which matches anything, 15424/// with another that has more specific requirements based on the type of the 15425/// corresponding operand. 15426const char *X86TargetLowering:: 15427LowerXConstraint(EVT ConstraintVT) const { 15428 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15429 // 'f' like normal targets. 15430 if (ConstraintVT.isFloatingPoint()) { 15431 if (Subtarget->hasSSE2()) 15432 return "Y"; 15433 if (Subtarget->hasSSE1()) 15434 return "x"; 15435 } 15436 15437 return TargetLowering::LowerXConstraint(ConstraintVT); 15438} 15439 15440/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15441/// vector. If it is invalid, don't add anything to Ops. 15442void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15443 std::string &Constraint, 15444 std::vector<SDValue>&Ops, 15445 SelectionDAG &DAG) const { 15446 SDValue Result(0, 0); 15447 15448 // Only support length 1 constraints for now. 15449 if (Constraint.length() > 1) return; 15450 15451 char ConstraintLetter = Constraint[0]; 15452 switch (ConstraintLetter) { 15453 default: break; 15454 case 'I': 15455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15456 if (C->getZExtValue() <= 31) { 15457 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15458 break; 15459 } 15460 } 15461 return; 15462 case 'J': 15463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15464 if (C->getZExtValue() <= 63) { 15465 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15466 break; 15467 } 15468 } 15469 return; 15470 case 'K': 15471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15472 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15473 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15474 break; 15475 } 15476 } 15477 return; 15478 case 'N': 15479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15480 if (C->getZExtValue() <= 255) { 15481 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15482 break; 15483 } 15484 } 15485 return; 15486 case 'e': { 15487 // 32-bit signed value 15488 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15489 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15490 C->getSExtValue())) { 15491 // Widen to 64 bits here to get it sign extended. 15492 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15493 break; 15494 } 15495 // FIXME gcc accepts some relocatable values here too, but only in certain 15496 // memory models; it's complicated. 15497 } 15498 return; 15499 } 15500 case 'Z': { 15501 // 32-bit unsigned value 15502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15503 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15504 C->getZExtValue())) { 15505 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15506 break; 15507 } 15508 } 15509 // FIXME gcc accepts some relocatable values here too, but only in certain 15510 // memory models; it's complicated. 15511 return; 15512 } 15513 case 'i': { 15514 // Literal immediates are always ok. 15515 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15516 // Widen to 64 bits here to get it sign extended. 15517 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15518 break; 15519 } 15520 15521 // In any sort of PIC mode addresses need to be computed at runtime by 15522 // adding in a register or some sort of table lookup. These can't 15523 // be used as immediates. 15524 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15525 return; 15526 15527 // If we are in non-pic codegen mode, we allow the address of a global (with 15528 // an optional displacement) to be used with 'i'. 15529 GlobalAddressSDNode *GA = 0; 15530 int64_t Offset = 0; 15531 15532 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15533 while (1) { 15534 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15535 Offset += GA->getOffset(); 15536 break; 15537 } else if (Op.getOpcode() == ISD::ADD) { 15538 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15539 Offset += C->getZExtValue(); 15540 Op = Op.getOperand(0); 15541 continue; 15542 } 15543 } else if (Op.getOpcode() == ISD::SUB) { 15544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15545 Offset += -C->getZExtValue(); 15546 Op = Op.getOperand(0); 15547 continue; 15548 } 15549 } 15550 15551 // Otherwise, this isn't something we can handle, reject it. 15552 return; 15553 } 15554 15555 const GlobalValue *GV = GA->getGlobal(); 15556 // If we require an extra load to get this address, as in PIC mode, we 15557 // can't accept it. 15558 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15559 getTargetMachine()))) 15560 return; 15561 15562 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15563 GA->getValueType(0), Offset); 15564 break; 15565 } 15566 } 15567 15568 if (Result.getNode()) { 15569 Ops.push_back(Result); 15570 return; 15571 } 15572 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15573} 15574 15575std::pair<unsigned, const TargetRegisterClass*> 15576X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15577 EVT VT) const { 15578 // First, see if this is a constraint that directly corresponds to an LLVM 15579 // register class. 15580 if (Constraint.size() == 1) { 15581 // GCC Constraint Letters 15582 switch (Constraint[0]) { 15583 default: break; 15584 // TODO: Slight differences here in allocation order and leaving 15585 // RIP in the class. Do they matter any more here than they do 15586 // in the normal allocation? 15587 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15588 if (Subtarget->is64Bit()) { 15589 if (VT == MVT::i32 || VT == MVT::f32) 15590 return std::make_pair(0U, X86::GR32RegisterClass); 15591 else if (VT == MVT::i16) 15592 return std::make_pair(0U, X86::GR16RegisterClass); 15593 else if (VT == MVT::i8 || VT == MVT::i1) 15594 return std::make_pair(0U, X86::GR8RegisterClass); 15595 else if (VT == MVT::i64 || VT == MVT::f64) 15596 return std::make_pair(0U, X86::GR64RegisterClass); 15597 break; 15598 } 15599 // 32-bit fallthrough 15600 case 'Q': // Q_REGS 15601 if (VT == MVT::i32 || VT == MVT::f32) 15602 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15603 else if (VT == MVT::i16) 15604 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15605 else if (VT == MVT::i8 || VT == MVT::i1) 15606 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15607 else if (VT == MVT::i64) 15608 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15609 break; 15610 case 'r': // GENERAL_REGS 15611 case 'l': // INDEX_REGS 15612 if (VT == MVT::i8 || VT == MVT::i1) 15613 return std::make_pair(0U, X86::GR8RegisterClass); 15614 if (VT == MVT::i16) 15615 return std::make_pair(0U, X86::GR16RegisterClass); 15616 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15617 return std::make_pair(0U, X86::GR32RegisterClass); 15618 return std::make_pair(0U, X86::GR64RegisterClass); 15619 case 'R': // LEGACY_REGS 15620 if (VT == MVT::i8 || VT == MVT::i1) 15621 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15622 if (VT == MVT::i16) 15623 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15624 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15625 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15626 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15627 case 'f': // FP Stack registers. 15628 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15629 // value to the correct fpstack register class. 15630 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15631 return std::make_pair(0U, X86::RFP32RegisterClass); 15632 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15633 return std::make_pair(0U, X86::RFP64RegisterClass); 15634 return std::make_pair(0U, X86::RFP80RegisterClass); 15635 case 'y': // MMX_REGS if MMX allowed. 15636 if (!Subtarget->hasMMX()) break; 15637 return std::make_pair(0U, X86::VR64RegisterClass); 15638 case 'Y': // SSE_REGS if SSE2 allowed 15639 if (!Subtarget->hasSSE2()) break; 15640 // FALL THROUGH. 15641 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15642 if (!Subtarget->hasSSE1()) break; 15643 15644 switch (VT.getSimpleVT().SimpleTy) { 15645 default: break; 15646 // Scalar SSE types. 15647 case MVT::f32: 15648 case MVT::i32: 15649 return std::make_pair(0U, X86::FR32RegisterClass); 15650 case MVT::f64: 15651 case MVT::i64: 15652 return std::make_pair(0U, X86::FR64RegisterClass); 15653 // Vector types. 15654 case MVT::v16i8: 15655 case MVT::v8i16: 15656 case MVT::v4i32: 15657 case MVT::v2i64: 15658 case MVT::v4f32: 15659 case MVT::v2f64: 15660 return std::make_pair(0U, X86::VR128RegisterClass); 15661 // AVX types. 15662 case MVT::v32i8: 15663 case MVT::v16i16: 15664 case MVT::v8i32: 15665 case MVT::v4i64: 15666 case MVT::v8f32: 15667 case MVT::v4f64: 15668 return std::make_pair(0U, X86::VR256RegisterClass); 15669 15670 } 15671 break; 15672 } 15673 } 15674 15675 // Use the default implementation in TargetLowering to convert the register 15676 // constraint into a member of a register class. 15677 std::pair<unsigned, const TargetRegisterClass*> Res; 15678 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15679 15680 // Not found as a standard register? 15681 if (Res.second == 0) { 15682 // Map st(0) -> st(7) -> ST0 15683 if (Constraint.size() == 7 && Constraint[0] == '{' && 15684 tolower(Constraint[1]) == 's' && 15685 tolower(Constraint[2]) == 't' && 15686 Constraint[3] == '(' && 15687 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15688 Constraint[5] == ')' && 15689 Constraint[6] == '}') { 15690 15691 Res.first = X86::ST0+Constraint[4]-'0'; 15692 Res.second = X86::RFP80RegisterClass; 15693 return Res; 15694 } 15695 15696 // GCC allows "st(0)" to be called just plain "st". 15697 if (StringRef("{st}").equals_lower(Constraint)) { 15698 Res.first = X86::ST0; 15699 Res.second = X86::RFP80RegisterClass; 15700 return Res; 15701 } 15702 15703 // flags -> EFLAGS 15704 if (StringRef("{flags}").equals_lower(Constraint)) { 15705 Res.first = X86::EFLAGS; 15706 Res.second = X86::CCRRegisterClass; 15707 return Res; 15708 } 15709 15710 // 'A' means EAX + EDX. 15711 if (Constraint == "A") { 15712 Res.first = X86::EAX; 15713 Res.second = X86::GR32_ADRegisterClass; 15714 return Res; 15715 } 15716 return Res; 15717 } 15718 15719 // Otherwise, check to see if this is a register class of the wrong value 15720 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15721 // turn into {ax},{dx}. 15722 if (Res.second->hasType(VT)) 15723 return Res; // Correct type already, nothing to do. 15724 15725 // All of the single-register GCC register classes map their values onto 15726 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15727 // really want an 8-bit or 32-bit register, map to the appropriate register 15728 // class and return the appropriate register. 15729 if (Res.second == X86::GR16RegisterClass) { 15730 if (VT == MVT::i8) { 15731 unsigned DestReg = 0; 15732 switch (Res.first) { 15733 default: break; 15734 case X86::AX: DestReg = X86::AL; break; 15735 case X86::DX: DestReg = X86::DL; break; 15736 case X86::CX: DestReg = X86::CL; break; 15737 case X86::BX: DestReg = X86::BL; break; 15738 } 15739 if (DestReg) { 15740 Res.first = DestReg; 15741 Res.second = X86::GR8RegisterClass; 15742 } 15743 } else if (VT == MVT::i32) { 15744 unsigned DestReg = 0; 15745 switch (Res.first) { 15746 default: break; 15747 case X86::AX: DestReg = X86::EAX; break; 15748 case X86::DX: DestReg = X86::EDX; break; 15749 case X86::CX: DestReg = X86::ECX; break; 15750 case X86::BX: DestReg = X86::EBX; break; 15751 case X86::SI: DestReg = X86::ESI; break; 15752 case X86::DI: DestReg = X86::EDI; break; 15753 case X86::BP: DestReg = X86::EBP; break; 15754 case X86::SP: DestReg = X86::ESP; break; 15755 } 15756 if (DestReg) { 15757 Res.first = DestReg; 15758 Res.second = X86::GR32RegisterClass; 15759 } 15760 } else if (VT == MVT::i64) { 15761 unsigned DestReg = 0; 15762 switch (Res.first) { 15763 default: break; 15764 case X86::AX: DestReg = X86::RAX; break; 15765 case X86::DX: DestReg = X86::RDX; break; 15766 case X86::CX: DestReg = X86::RCX; break; 15767 case X86::BX: DestReg = X86::RBX; break; 15768 case X86::SI: DestReg = X86::RSI; break; 15769 case X86::DI: DestReg = X86::RDI; break; 15770 case X86::BP: DestReg = X86::RBP; break; 15771 case X86::SP: DestReg = X86::RSP; break; 15772 } 15773 if (DestReg) { 15774 Res.first = DestReg; 15775 Res.second = X86::GR64RegisterClass; 15776 } 15777 } 15778 } else if (Res.second == X86::FR32RegisterClass || 15779 Res.second == X86::FR64RegisterClass || 15780 Res.second == X86::VR128RegisterClass) { 15781 // Handle references to XMM physical registers that got mapped into the 15782 // wrong class. This can happen with constraints like {xmm0} where the 15783 // target independent register mapper will just pick the first match it can 15784 // find, ignoring the required type. 15785 if (VT == MVT::f32) 15786 Res.second = X86::FR32RegisterClass; 15787 else if (VT == MVT::f64) 15788 Res.second = X86::FR64RegisterClass; 15789 else if (X86::VR128RegisterClass->hasType(VT)) 15790 Res.second = X86::VR128RegisterClass; 15791 } 15792 15793 return Res; 15794} 15795