X86ISelLowering.cpp revision 96428cea3d87aaac2e520a0df8f51c857ebf9cbd
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/MC/MCAsmInfo.h" 40#include "llvm/MC/MCContext.h" 41#include "llvm/MC/MCExpr.h" 42#include "llvm/MC/MCSymbol.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/Support/CallSite.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetOptions.h" 55using namespace llvm; 56using namespace dwarf; 57 58STATISTIC(NumTailCalls, "Number of tail calls"); 59 60// Forward declarations. 61static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64static SDValue Insert128BitVector(SDValue Result, 65 SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl); 69 70static SDValue Extract128BitVector(SDValue Vec, 71 SDValue Idx, 72 SelectionDAG &DAG, 73 DebugLoc dl); 74 75/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 76/// sets things up to match to an AVX VEXTRACTF128 instruction or a 77/// simple subregister reference. Idx is an index in the 128 bits we 78/// want. It need not be aligned to a 128-bit bounday. That makes 79/// lowering EXTRACT_VECTOR_ELT operations easier. 80static SDValue Extract128BitVector(SDValue Vec, 81 SDValue Idx, 82 SelectionDAG &DAG, 83 DebugLoc dl) { 84 EVT VT = Vec.getValueType(); 85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 86 EVT ElVT = VT.getVectorElementType(); 87 int Factor = VT.getSizeInBits()/128; 88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 89 VT.getVectorNumElements()/Factor); 90 91 // Extract from UNDEF is UNDEF. 92 if (Vec.getOpcode() == ISD::UNDEF) 93 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 94 95 if (isa<ConstantSDNode>(Idx)) { 96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 97 98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 99 // we can match to VEXTRACTF128. 100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 101 102 // This is the index of the first element of the 128-bit chunk 103 // we want. 104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 105 * ElemsPerChunk); 106 107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 109 VecIdx); 110 111 return Result; 112 } 113 114 return SDValue(); 115} 116 117/// Generate a DAG to put 128-bits into a vector > 128 bits. This 118/// sets things up to match to an AVX VINSERTF128 instruction or a 119/// simple superregister reference. Idx is an index in the 128 bits 120/// we want. It need not be aligned to a 128-bit bounday. That makes 121/// lowering INSERT_VECTOR_ELT operations easier. 122static SDValue Insert128BitVector(SDValue Result, 123 SDValue Vec, 124 SDValue Idx, 125 SelectionDAG &DAG, 126 DebugLoc dl) { 127 if (isa<ConstantSDNode>(Idx)) { 128 EVT VT = Vec.getValueType(); 129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 130 131 EVT ElVT = VT.getVectorElementType(); 132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 133 EVT ResultVT = Result.getValueType(); 134 135 // Insert the relevant 128 bits. 136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 137 138 // This is the index of the first element of the 128-bit chunk 139 // we want. 140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 141 * ElemsPerChunk); 142 143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 145 VecIdx); 146 return Result; 147 } 148 149 return SDValue(); 150} 151 152static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 154 bool is64Bit = Subtarget->is64Bit(); 155 156 if (Subtarget->isTargetEnvMacho()) { 157 if (is64Bit) 158 return new X8664_MachoTargetObjectFile(); 159 return new TargetLoweringObjectFileMachO(); 160 } 161 162 if (Subtarget->isTargetELF()) 163 return new TargetLoweringObjectFileELF(); 164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 165 return new TargetLoweringObjectFileCOFF(); 166 llvm_unreachable("unknown subtarget type"); 167} 168 169X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 170 : TargetLowering(TM, createTLOF(TM)) { 171 Subtarget = &TM.getSubtarget<X86Subtarget>(); 172 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX(); 173 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX(); 174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 175 176 RegInfo = TM.getRegisterInfo(); 177 TD = getTargetData(); 178 179 // Set up the TargetLowering object. 180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 181 182 // X86 is weird, it always uses i8 for shift amounts and setcc results. 183 setBooleanContents(ZeroOrOneBooleanContent); 184 185 // For 64-bit since we have so many registers use the ILP scheduler, for 186 // 32-bit code use the register pressure specific scheduling. 187 if (Subtarget->is64Bit()) 188 setSchedulingPreference(Sched::ILP); 189 else 190 setSchedulingPreference(Sched::RegPressure); 191 setStackPointerRegisterToSaveRestore(X86StackPtr); 192 193 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 194 // Setup Windows compiler runtime calls. 195 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 196 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 197 setLibcallName(RTLIB::SREM_I64, "_allrem"); 198 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 199 setLibcallName(RTLIB::MUL_I64, "_allmul"); 200 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 201 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 202 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 203 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 209 } 210 211 if (Subtarget->isTargetDarwin()) { 212 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 213 setUseUnderscoreSetJmp(false); 214 setUseUnderscoreLongJmp(false); 215 } else if (Subtarget->isTargetMingw()) { 216 // MS runtime is weird: it exports _setjmp, but longjmp! 217 setUseUnderscoreSetJmp(true); 218 setUseUnderscoreLongJmp(false); 219 } else { 220 setUseUnderscoreSetJmp(true); 221 setUseUnderscoreLongJmp(true); 222 } 223 224 // Set up the register classes. 225 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 226 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 227 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 228 if (Subtarget->is64Bit()) 229 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 230 231 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 232 233 // We don't accept any truncstore of integer registers. 234 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 235 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 237 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 238 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 239 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 240 241 // SETOEQ and SETUNE require checking two conditions. 242 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 248 249 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 250 // operation. 251 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 252 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 254 255 if (Subtarget->is64Bit()) { 256 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 257 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 258 } else if (!UseSoftFloat) { 259 // We have an algorithm for SSE2->double, and we turn this into a 260 // 64-bit FILD followed by conditional FADD for other targets. 261 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 262 // We have an algorithm for SSE2, and we turn this into a 64-bit 263 // FILD for other targets. 264 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 265 } 266 267 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 268 // this operation. 269 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 270 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 271 272 if (!UseSoftFloat) { 273 // SSE has no i16 to fp conversion, only i32 274 if (X86ScalarSSEf32) { 275 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 276 // f32 and f64 cases are Legal, f80 case is not 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 278 } else { 279 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 280 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 281 } 282 } else { 283 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 284 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 285 } 286 287 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 288 // are Legal, f80 is custom lowered. 289 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 290 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 291 292 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 293 // this operation. 294 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 295 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 296 297 if (X86ScalarSSEf32) { 298 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 299 // f32 and f64 cases are Legal, f80 case is not 300 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 301 } else { 302 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 303 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 304 } 305 306 // Handle FP_TO_UINT by promoting the destination to a larger signed 307 // conversion. 308 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 309 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 311 312 if (Subtarget->is64Bit()) { 313 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 315 } else if (!UseSoftFloat) { 316 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 317 // Expand FP_TO_UINT into a select. 318 // FIXME: We would like to use a Custom expander here eventually to do 319 // the optimal thing for SSE vs. the default expansion in the legalizer. 320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 321 else 322 // With SSE3 we can use fisttpll to convert to a signed i64; without 323 // SSE, we're stuck with a fistpll. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 325 } 326 327 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 328 if (!X86ScalarSSEf64) { 329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 333 // Without SSE, i64->f64 goes through memory. 334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 335 } 336 } 337 338 // Scalar integer divide and remainder are lowered to use operations that 339 // produce two results, to match the available instructions. This exposes 340 // the two-result form to trivial CSE, which is able to combine x/y and x%y 341 // into a single instruction. 342 // 343 // Scalar integer multiply-high is also lowered to use two-result 344 // operations, to match the available instructions. However, plain multiply 345 // (low) operations are left as Legal, as there are single-result 346 // instructions for this in x86. Using the two-result multiply instructions 347 // when both high and low results are needed must be arranged by dagcombine. 348 for (unsigned i = 0, e = 4; i != e; ++i) { 349 MVT VT = IntVTs[i]; 350 setOperationAction(ISD::MULHS, VT, Expand); 351 setOperationAction(ISD::MULHU, VT, Expand); 352 setOperationAction(ISD::SDIV, VT, Expand); 353 setOperationAction(ISD::UDIV, VT, Expand); 354 setOperationAction(ISD::SREM, VT, Expand); 355 setOperationAction(ISD::UREM, VT, Expand); 356 357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 358 setOperationAction(ISD::ADDC, VT, Custom); 359 setOperationAction(ISD::ADDE, VT, Custom); 360 setOperationAction(ISD::SUBC, VT, Custom); 361 setOperationAction(ISD::SUBE, VT, Custom); 362 } 363 364 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 365 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 366 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 368 if (Subtarget->is64Bit()) 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f64 , Expand); 376 setOperationAction(ISD::FREM , MVT::f80 , Expand); 377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 378 379 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 380 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 381 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 382 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 383 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 384 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 385 if (Subtarget->is64Bit()) { 386 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 387 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 388 } 389 390 if (Subtarget->hasPOPCNT()) { 391 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 392 } else { 393 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 394 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 395 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 396 if (Subtarget->is64Bit()) 397 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 398 } 399 400 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 401 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 402 403 // These should be promoted to a larger select which is supported. 404 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 405 // X86 wants to expand cmov itself. 406 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 407 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 408 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 409 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 410 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 411 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 412 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 413 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 414 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 415 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 416 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 417 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 418 if (Subtarget->is64Bit()) { 419 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 420 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 421 } 422 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 423 424 // Darwin ABI issue. 425 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 426 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 427 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 428 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 429 if (Subtarget->is64Bit()) 430 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 431 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 432 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 433 if (Subtarget->is64Bit()) { 434 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 435 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 436 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 437 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 438 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 439 } 440 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 441 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 442 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 443 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 444 if (Subtarget->is64Bit()) { 445 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 446 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 447 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 448 } 449 450 if (Subtarget->hasXMM()) 451 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 452 453 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 454 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 455 456 // On X86 and X86-64, atomic operations are lowered to locked instructions. 457 // Locked instructions, in turn, have implicit fence semantics (all memory 458 // operations are flushed before issuing the locked instruction, and they 459 // are not buffered), so we can fold away the common pattern of 460 // fence-atomic-fence. 461 setShouldFoldAtomicFences(true); 462 463 // Expand certain atomics 464 for (unsigned i = 0, e = 4; i != e; ++i) { 465 MVT VT = IntVTs[i]; 466 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 467 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 468 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 469 } 470 471 if (!Subtarget->is64Bit()) { 472 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 473 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 474 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 475 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 476 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 477 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 478 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 479 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 480 } 481 482 if (Subtarget->hasCmpxchg16b()) { 483 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 484 } 485 486 // FIXME - use subtarget debug flags 487 if (!Subtarget->isTargetDarwin() && 488 !Subtarget->isTargetELF() && 489 !Subtarget->isTargetCygMing()) { 490 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 491 } 492 493 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 494 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 495 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 496 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 497 if (Subtarget->is64Bit()) { 498 setExceptionPointerRegister(X86::RAX); 499 setExceptionSelectorRegister(X86::RDX); 500 } else { 501 setExceptionPointerRegister(X86::EAX); 502 setExceptionSelectorRegister(X86::EDX); 503 } 504 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 505 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 506 507 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 508 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 509 510 setOperationAction(ISD::TRAP, MVT::Other, Legal); 511 512 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 513 setOperationAction(ISD::VASTART , MVT::Other, Custom); 514 setOperationAction(ISD::VAEND , MVT::Other, Expand); 515 if (Subtarget->is64Bit()) { 516 setOperationAction(ISD::VAARG , MVT::Other, Custom); 517 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 518 } else { 519 setOperationAction(ISD::VAARG , MVT::Other, Expand); 520 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 521 } 522 523 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 524 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 525 526 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 527 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 528 MVT::i64 : MVT::i32, Custom); 529 else if (EnableSegmentedStacks) 530 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 531 MVT::i64 : MVT::i32, Custom); 532 else 533 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 534 MVT::i64 : MVT::i32, Expand); 535 536 if (!UseSoftFloat && X86ScalarSSEf64) { 537 // f32 and f64 use SSE. 538 // Set up the FP register classes. 539 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 540 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 541 542 // Use ANDPD to simulate FABS. 543 setOperationAction(ISD::FABS , MVT::f64, Custom); 544 setOperationAction(ISD::FABS , MVT::f32, Custom); 545 546 // Use XORP to simulate FNEG. 547 setOperationAction(ISD::FNEG , MVT::f64, Custom); 548 setOperationAction(ISD::FNEG , MVT::f32, Custom); 549 550 // Use ANDPD and ORPD to simulate FCOPYSIGN. 551 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 552 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 553 554 // Lower this to FGETSIGNx86 plus an AND. 555 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 556 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 557 558 // We don't support sin/cos/fmod 559 setOperationAction(ISD::FSIN , MVT::f64, Expand); 560 setOperationAction(ISD::FCOS , MVT::f64, Expand); 561 setOperationAction(ISD::FSIN , MVT::f32, Expand); 562 setOperationAction(ISD::FCOS , MVT::f32, Expand); 563 564 // Expand FP immediates into loads from the stack, except for the special 565 // cases we handle. 566 addLegalFPImmediate(APFloat(+0.0)); // xorpd 567 addLegalFPImmediate(APFloat(+0.0f)); // xorps 568 } else if (!UseSoftFloat && X86ScalarSSEf32) { 569 // Use SSE for f32, x87 for f64. 570 // Set up the FP register classes. 571 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 572 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 573 574 // Use ANDPS to simulate FABS. 575 setOperationAction(ISD::FABS , MVT::f32, Custom); 576 577 // Use XORP to simulate FNEG. 578 setOperationAction(ISD::FNEG , MVT::f32, Custom); 579 580 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 581 582 // Use ANDPS and ORPS to simulate FCOPYSIGN. 583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 585 586 // We don't support sin/cos/fmod 587 setOperationAction(ISD::FSIN , MVT::f32, Expand); 588 setOperationAction(ISD::FCOS , MVT::f32, Expand); 589 590 // Special cases we handle for FP constants. 591 addLegalFPImmediate(APFloat(+0.0f)); // xorps 592 addLegalFPImmediate(APFloat(+0.0)); // FLD0 593 addLegalFPImmediate(APFloat(+1.0)); // FLD1 594 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 595 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 596 597 if (!UnsafeFPMath) { 598 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 599 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 600 } 601 } else if (!UseSoftFloat) { 602 // f32 and f64 in x87. 603 // Set up the FP register classes. 604 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 605 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 606 607 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 608 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 609 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 610 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 611 612 if (!UnsafeFPMath) { 613 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 614 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 615 } 616 addLegalFPImmediate(APFloat(+0.0)); // FLD0 617 addLegalFPImmediate(APFloat(+1.0)); // FLD1 618 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 619 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 620 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 621 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 622 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 623 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 624 } 625 626 // We don't support FMA. 627 setOperationAction(ISD::FMA, MVT::f64, Expand); 628 setOperationAction(ISD::FMA, MVT::f32, Expand); 629 630 // Long double always uses X87. 631 if (!UseSoftFloat) { 632 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 633 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 634 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 635 { 636 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 637 addLegalFPImmediate(TmpFlt); // FLD0 638 TmpFlt.changeSign(); 639 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 640 641 bool ignored; 642 APFloat TmpFlt2(+1.0); 643 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 644 &ignored); 645 addLegalFPImmediate(TmpFlt2); // FLD1 646 TmpFlt2.changeSign(); 647 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 648 } 649 650 if (!UnsafeFPMath) { 651 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 652 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 653 } 654 655 setOperationAction(ISD::FMA, MVT::f80, Expand); 656 } 657 658 // Always use a library call for pow. 659 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 660 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 661 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 662 663 setOperationAction(ISD::FLOG, MVT::f80, Expand); 664 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 665 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 666 setOperationAction(ISD::FEXP, MVT::f80, Expand); 667 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 668 669 // First set operation action for all vector types to either promote 670 // (for widening) or expand (for scalarization). Then we will selectively 671 // turn on ones that can be effectively codegen'd. 672 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 673 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 674 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 675 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 676 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 677 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 678 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 679 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 680 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 681 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 682 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 683 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 684 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 685 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 689 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 691 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 692 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 703 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 724 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 728 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 729 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 730 setTruncStoreAction((MVT::SimpleValueType)VT, 731 (MVT::SimpleValueType)InnerVT, Expand); 732 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 733 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 734 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 735 } 736 737 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 738 // with -msoft-float, disable use of MMX as well. 739 if (!UseSoftFloat && Subtarget->hasMMX()) { 740 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 741 // No operations on x86mmx supported, everything uses intrinsics. 742 } 743 744 // MMX-sized vectors (other than x86mmx) are expected to be expanded 745 // into smaller operations. 746 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 747 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 748 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 749 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 750 setOperationAction(ISD::AND, MVT::v8i8, Expand); 751 setOperationAction(ISD::AND, MVT::v4i16, Expand); 752 setOperationAction(ISD::AND, MVT::v2i32, Expand); 753 setOperationAction(ISD::AND, MVT::v1i64, Expand); 754 setOperationAction(ISD::OR, MVT::v8i8, Expand); 755 setOperationAction(ISD::OR, MVT::v4i16, Expand); 756 setOperationAction(ISD::OR, MVT::v2i32, Expand); 757 setOperationAction(ISD::OR, MVT::v1i64, Expand); 758 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 759 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 760 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 761 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 762 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 763 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 764 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 765 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 766 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 767 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 768 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 769 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 770 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 771 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 772 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 773 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 774 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 775 776 if (!UseSoftFloat && Subtarget->hasXMM()) { 777 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 778 779 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 780 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 781 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 782 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 783 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 784 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 788 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 789 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 790 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 791 } 792 793 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 794 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 795 796 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 797 // registers cannot be used even for integer operations. 798 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 799 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 800 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 801 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 802 803 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 804 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 805 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 806 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 807 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 808 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 809 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 810 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 811 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 812 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 813 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 814 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 815 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 816 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 817 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 818 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 819 820 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 821 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 822 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 823 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 824 825 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 826 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 827 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 828 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 829 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 830 831 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 832 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 833 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 834 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 835 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 836 837 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 838 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 839 EVT VT = (MVT::SimpleValueType)i; 840 // Do not attempt to custom lower non-power-of-2 vectors 841 if (!isPowerOf2_32(VT.getVectorNumElements())) 842 continue; 843 // Do not attempt to custom lower non-128-bit vectors 844 if (!VT.is128BitVector()) 845 continue; 846 setOperationAction(ISD::BUILD_VECTOR, 847 VT.getSimpleVT().SimpleTy, Custom); 848 setOperationAction(ISD::VECTOR_SHUFFLE, 849 VT.getSimpleVT().SimpleTy, Custom); 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 851 VT.getSimpleVT().SimpleTy, Custom); 852 } 853 854 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 855 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 856 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 857 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 859 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 860 861 if (Subtarget->is64Bit()) { 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 864 } 865 866 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 867 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 868 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 869 EVT VT = SVT; 870 871 // Do not attempt to promote non-128-bit vectors 872 if (!VT.is128BitVector()) 873 continue; 874 875 setOperationAction(ISD::AND, SVT, Promote); 876 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 877 setOperationAction(ISD::OR, SVT, Promote); 878 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 879 setOperationAction(ISD::XOR, SVT, Promote); 880 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 881 setOperationAction(ISD::LOAD, SVT, Promote); 882 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 883 setOperationAction(ISD::SELECT, SVT, Promote); 884 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 885 } 886 887 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 888 889 // Custom lower v2i64 and v2f64 selects. 890 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 891 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 892 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 893 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 894 895 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 896 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 897 } 898 899 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 900 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 901 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 902 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 903 setOperationAction(ISD::FRINT, MVT::f32, Legal); 904 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 905 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 906 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 907 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 908 setOperationAction(ISD::FRINT, MVT::f64, Legal); 909 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 910 911 // FIXME: Do we need to handle scalar-to-vector here? 912 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 913 914 // Can turn SHL into an integer multiply. 915 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 916 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 917 918 // i8 and i16 vectors are custom , because the source register and source 919 // source memory operand types are not the same width. f32 vectors are 920 // custom since the immediate controlling the insert encodes additional 921 // information. 922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 925 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 926 927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 928 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 929 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 930 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 931 932 if (Subtarget->is64Bit()) { 933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 934 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 935 } 936 } 937 938 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) { 939 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 940 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 941 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 942 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 943 944 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 945 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 946 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 947 948 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 949 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 950 } 951 952 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 953 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 954 955 if (!UseSoftFloat && Subtarget->hasAVX()) { 956 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 957 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 958 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 959 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 960 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 961 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 962 963 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 964 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 965 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 966 967 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 968 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 969 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 970 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 971 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 972 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 973 974 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 975 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 976 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 977 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 978 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 979 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 980 981 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 982 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 983 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 984 985 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 986 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 987 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 988 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 989 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 990 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 991 992 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 993 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 994 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 995 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 996 997 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 998 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 999 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1000 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1001 1002 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1003 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1004 1005 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 1006 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 1007 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 1008 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom); 1009 1010 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1011 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1012 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1013 1014 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1015 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1016 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1017 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1018 1019 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1020 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1021 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1022 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1023 1024 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1025 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1026 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1027 // Don't lower v32i8 because there is no 128-bit byte mul 1028 1029 // Custom lower several nodes for 256-bit types. 1030 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1031 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1032 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1033 EVT VT = SVT; 1034 1035 // Extract subvector is special because the value type 1036 // (result) is 128-bit but the source is 256-bit wide. 1037 if (VT.is128BitVector()) 1038 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1039 1040 // Do not attempt to custom lower other non-256-bit vectors 1041 if (!VT.is256BitVector()) 1042 continue; 1043 1044 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1045 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1046 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1047 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1048 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1049 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1050 } 1051 1052 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1053 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1054 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1055 EVT VT = SVT; 1056 1057 // Do not attempt to promote non-256-bit vectors 1058 if (!VT.is256BitVector()) 1059 continue; 1060 1061 setOperationAction(ISD::AND, SVT, Promote); 1062 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1063 setOperationAction(ISD::OR, SVT, Promote); 1064 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1065 setOperationAction(ISD::XOR, SVT, Promote); 1066 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1067 setOperationAction(ISD::LOAD, SVT, Promote); 1068 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1069 setOperationAction(ISD::SELECT, SVT, Promote); 1070 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1071 } 1072 } 1073 1074 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1075 // of this type with custom code. 1076 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1077 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1078 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1079 } 1080 1081 // We want to custom lower some of our intrinsics. 1082 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1083 1084 1085 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1086 // handle type legalization for these operations here. 1087 // 1088 // FIXME: We really should do custom legalization for addition and 1089 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1090 // than generic legalization for 64-bit multiplication-with-overflow, though. 1091 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1092 // Add/Sub/Mul with overflow operations are custom lowered. 1093 MVT VT = IntVTs[i]; 1094 setOperationAction(ISD::SADDO, VT, Custom); 1095 setOperationAction(ISD::UADDO, VT, Custom); 1096 setOperationAction(ISD::SSUBO, VT, Custom); 1097 setOperationAction(ISD::USUBO, VT, Custom); 1098 setOperationAction(ISD::SMULO, VT, Custom); 1099 setOperationAction(ISD::UMULO, VT, Custom); 1100 } 1101 1102 // There are no 8-bit 3-address imul/mul instructions 1103 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1104 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1105 1106 if (!Subtarget->is64Bit()) { 1107 // These libcalls are not available in 32-bit. 1108 setLibcallName(RTLIB::SHL_I128, 0); 1109 setLibcallName(RTLIB::SRL_I128, 0); 1110 setLibcallName(RTLIB::SRA_I128, 0); 1111 } 1112 1113 // We have target-specific dag combine patterns for the following nodes: 1114 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1115 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1116 setTargetDAGCombine(ISD::BUILD_VECTOR); 1117 setTargetDAGCombine(ISD::SELECT); 1118 setTargetDAGCombine(ISD::SHL); 1119 setTargetDAGCombine(ISD::SRA); 1120 setTargetDAGCombine(ISD::SRL); 1121 setTargetDAGCombine(ISD::OR); 1122 setTargetDAGCombine(ISD::AND); 1123 setTargetDAGCombine(ISD::ADD); 1124 setTargetDAGCombine(ISD::SUB); 1125 setTargetDAGCombine(ISD::STORE); 1126 setTargetDAGCombine(ISD::ZERO_EXTEND); 1127 setTargetDAGCombine(ISD::SINT_TO_FP); 1128 if (Subtarget->is64Bit()) 1129 setTargetDAGCombine(ISD::MUL); 1130 1131 computeRegisterProperties(); 1132 1133 // On Darwin, -Os means optimize for size without hurting performance, 1134 // do not reduce the limit. 1135 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1136 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1137 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1138 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1139 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1140 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1141 setPrefLoopAlignment(16); 1142 benefitFromCodePlacementOpt = true; 1143 1144 setPrefFunctionAlignment(4); 1145} 1146 1147 1148MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1149 return MVT::i8; 1150} 1151 1152 1153/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1154/// the desired ByVal argument alignment. 1155static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1156 if (MaxAlign == 16) 1157 return; 1158 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1159 if (VTy->getBitWidth() == 128) 1160 MaxAlign = 16; 1161 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1162 unsigned EltAlign = 0; 1163 getMaxByValAlign(ATy->getElementType(), EltAlign); 1164 if (EltAlign > MaxAlign) 1165 MaxAlign = EltAlign; 1166 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1167 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1168 unsigned EltAlign = 0; 1169 getMaxByValAlign(STy->getElementType(i), EltAlign); 1170 if (EltAlign > MaxAlign) 1171 MaxAlign = EltAlign; 1172 if (MaxAlign == 16) 1173 break; 1174 } 1175 } 1176 return; 1177} 1178 1179/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1180/// function arguments in the caller parameter area. For X86, aggregates 1181/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1182/// are at 4-byte boundaries. 1183unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1184 if (Subtarget->is64Bit()) { 1185 // Max of 8 and alignment of type. 1186 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1187 if (TyAlign > 8) 1188 return TyAlign; 1189 return 8; 1190 } 1191 1192 unsigned Align = 4; 1193 if (Subtarget->hasXMM()) 1194 getMaxByValAlign(Ty, Align); 1195 return Align; 1196} 1197 1198/// getOptimalMemOpType - Returns the target specific optimal type for load 1199/// and store operations as a result of memset, memcpy, and memmove 1200/// lowering. If DstAlign is zero that means it's safe to destination 1201/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1202/// means there isn't a need to check it against alignment requirement, 1203/// probably because the source does not need to be loaded. If 1204/// 'NonScalarIntSafe' is true, that means it's safe to return a 1205/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1206/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1207/// constant so it does not need to be loaded. 1208/// It returns EVT::Other if the type should be determined using generic 1209/// target-independent logic. 1210EVT 1211X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1212 unsigned DstAlign, unsigned SrcAlign, 1213 bool NonScalarIntSafe, 1214 bool MemcpyStrSrc, 1215 MachineFunction &MF) const { 1216 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1217 // linux. This is because the stack realignment code can't handle certain 1218 // cases like PR2962. This should be removed when PR2962 is fixed. 1219 const Function *F = MF.getFunction(); 1220 if (NonScalarIntSafe && 1221 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1222 if (Size >= 16 && 1223 (Subtarget->isUnalignedMemAccessFast() || 1224 ((DstAlign == 0 || DstAlign >= 16) && 1225 (SrcAlign == 0 || SrcAlign >= 16))) && 1226 Subtarget->getStackAlignment() >= 16) { 1227 if (Subtarget->hasSSE2()) 1228 return MVT::v4i32; 1229 if (Subtarget->hasSSE1()) 1230 return MVT::v4f32; 1231 } else if (!MemcpyStrSrc && Size >= 8 && 1232 !Subtarget->is64Bit() && 1233 Subtarget->getStackAlignment() >= 8 && 1234 Subtarget->hasXMMInt()) { 1235 // Do not use f64 to lower memcpy if source is string constant. It's 1236 // better to use i32 to avoid the loads. 1237 return MVT::f64; 1238 } 1239 } 1240 if (Subtarget->is64Bit() && Size >= 8) 1241 return MVT::i64; 1242 return MVT::i32; 1243} 1244 1245/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1246/// current function. The returned value is a member of the 1247/// MachineJumpTableInfo::JTEntryKind enum. 1248unsigned X86TargetLowering::getJumpTableEncoding() const { 1249 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1250 // symbol. 1251 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1252 Subtarget->isPICStyleGOT()) 1253 return MachineJumpTableInfo::EK_Custom32; 1254 1255 // Otherwise, use the normal jump table encoding heuristics. 1256 return TargetLowering::getJumpTableEncoding(); 1257} 1258 1259const MCExpr * 1260X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1261 const MachineBasicBlock *MBB, 1262 unsigned uid,MCContext &Ctx) const{ 1263 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1264 Subtarget->isPICStyleGOT()); 1265 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1266 // entries. 1267 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1268 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1269} 1270 1271/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1272/// jumptable. 1273SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1274 SelectionDAG &DAG) const { 1275 if (!Subtarget->is64Bit()) 1276 // This doesn't have DebugLoc associated with it, but is not really the 1277 // same as a Register. 1278 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1279 return Table; 1280} 1281 1282/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1283/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1284/// MCExpr. 1285const MCExpr *X86TargetLowering:: 1286getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1287 MCContext &Ctx) const { 1288 // X86-64 uses RIP relative addressing based on the jump table label. 1289 if (Subtarget->isPICStyleRIPRel()) 1290 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1291 1292 // Otherwise, the reference is relative to the PIC base. 1293 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1294} 1295 1296// FIXME: Why this routine is here? Move to RegInfo! 1297std::pair<const TargetRegisterClass*, uint8_t> 1298X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1299 const TargetRegisterClass *RRC = 0; 1300 uint8_t Cost = 1; 1301 switch (VT.getSimpleVT().SimpleTy) { 1302 default: 1303 return TargetLowering::findRepresentativeClass(VT); 1304 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1305 RRC = (Subtarget->is64Bit() 1306 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1307 break; 1308 case MVT::x86mmx: 1309 RRC = X86::VR64RegisterClass; 1310 break; 1311 case MVT::f32: case MVT::f64: 1312 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1313 case MVT::v4f32: case MVT::v2f64: 1314 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1315 case MVT::v4f64: 1316 RRC = X86::VR128RegisterClass; 1317 break; 1318 } 1319 return std::make_pair(RRC, Cost); 1320} 1321 1322bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1323 unsigned &Offset) const { 1324 if (!Subtarget->isTargetLinux()) 1325 return false; 1326 1327 if (Subtarget->is64Bit()) { 1328 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1329 Offset = 0x28; 1330 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1331 AddressSpace = 256; 1332 else 1333 AddressSpace = 257; 1334 } else { 1335 // %gs:0x14 on i386 1336 Offset = 0x14; 1337 AddressSpace = 256; 1338 } 1339 return true; 1340} 1341 1342 1343//===----------------------------------------------------------------------===// 1344// Return Value Calling Convention Implementation 1345//===----------------------------------------------------------------------===// 1346 1347#include "X86GenCallingConv.inc" 1348 1349bool 1350X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1351 MachineFunction &MF, bool isVarArg, 1352 const SmallVectorImpl<ISD::OutputArg> &Outs, 1353 LLVMContext &Context) const { 1354 SmallVector<CCValAssign, 16> RVLocs; 1355 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1356 RVLocs, Context); 1357 return CCInfo.CheckReturn(Outs, RetCC_X86); 1358} 1359 1360SDValue 1361X86TargetLowering::LowerReturn(SDValue Chain, 1362 CallingConv::ID CallConv, bool isVarArg, 1363 const SmallVectorImpl<ISD::OutputArg> &Outs, 1364 const SmallVectorImpl<SDValue> &OutVals, 1365 DebugLoc dl, SelectionDAG &DAG) const { 1366 MachineFunction &MF = DAG.getMachineFunction(); 1367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1368 1369 SmallVector<CCValAssign, 16> RVLocs; 1370 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1371 RVLocs, *DAG.getContext()); 1372 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1373 1374 // Add the regs to the liveout set for the function. 1375 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1376 for (unsigned i = 0; i != RVLocs.size(); ++i) 1377 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1378 MRI.addLiveOut(RVLocs[i].getLocReg()); 1379 1380 SDValue Flag; 1381 1382 SmallVector<SDValue, 6> RetOps; 1383 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1384 // Operand #1 = Bytes To Pop 1385 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1386 MVT::i16)); 1387 1388 // Copy the result values into the output registers. 1389 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1390 CCValAssign &VA = RVLocs[i]; 1391 assert(VA.isRegLoc() && "Can only return in registers!"); 1392 SDValue ValToCopy = OutVals[i]; 1393 EVT ValVT = ValToCopy.getValueType(); 1394 1395 // If this is x86-64, and we disabled SSE, we can't return FP values, 1396 // or SSE or MMX vectors. 1397 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1398 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1399 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1400 report_fatal_error("SSE register return with SSE disabled"); 1401 } 1402 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1403 // llvm-gcc has never done it right and no one has noticed, so this 1404 // should be OK for now. 1405 if (ValVT == MVT::f64 && 1406 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1407 report_fatal_error("SSE2 register return with SSE2 disabled"); 1408 1409 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1410 // the RET instruction and handled by the FP Stackifier. 1411 if (VA.getLocReg() == X86::ST0 || 1412 VA.getLocReg() == X86::ST1) { 1413 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1414 // change the value to the FP stack register class. 1415 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1416 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1417 RetOps.push_back(ValToCopy); 1418 // Don't emit a copytoreg. 1419 continue; 1420 } 1421 1422 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1423 // which is returned in RAX / RDX. 1424 if (Subtarget->is64Bit()) { 1425 if (ValVT == MVT::x86mmx) { 1426 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1427 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1428 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1429 ValToCopy); 1430 // If we don't have SSE2 available, convert to v4f32 so the generated 1431 // register is legal. 1432 if (!Subtarget->hasSSE2()) 1433 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1434 } 1435 } 1436 } 1437 1438 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1439 Flag = Chain.getValue(1); 1440 } 1441 1442 // The x86-64 ABI for returning structs by value requires that we copy 1443 // the sret argument into %rax for the return. We saved the argument into 1444 // a virtual register in the entry block, so now we copy the value out 1445 // and into %rax. 1446 if (Subtarget->is64Bit() && 1447 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1448 MachineFunction &MF = DAG.getMachineFunction(); 1449 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1450 unsigned Reg = FuncInfo->getSRetReturnReg(); 1451 assert(Reg && 1452 "SRetReturnReg should have been set in LowerFormalArguments()."); 1453 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1454 1455 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1456 Flag = Chain.getValue(1); 1457 1458 // RAX now acts like a return value. 1459 MRI.addLiveOut(X86::RAX); 1460 } 1461 1462 RetOps[0] = Chain; // Update chain. 1463 1464 // Add the flag if we have it. 1465 if (Flag.getNode()) 1466 RetOps.push_back(Flag); 1467 1468 return DAG.getNode(X86ISD::RET_FLAG, dl, 1469 MVT::Other, &RetOps[0], RetOps.size()); 1470} 1471 1472bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1473 if (N->getNumValues() != 1) 1474 return false; 1475 if (!N->hasNUsesOfValue(1, 0)) 1476 return false; 1477 1478 SDNode *Copy = *N->use_begin(); 1479 if (Copy->getOpcode() != ISD::CopyToReg && 1480 Copy->getOpcode() != ISD::FP_EXTEND) 1481 return false; 1482 1483 bool HasRet = false; 1484 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1485 UI != UE; ++UI) { 1486 if (UI->getOpcode() != X86ISD::RET_FLAG) 1487 return false; 1488 HasRet = true; 1489 } 1490 1491 return HasRet; 1492} 1493 1494EVT 1495X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1496 ISD::NodeType ExtendKind) const { 1497 MVT ReturnMVT; 1498 // TODO: Is this also valid on 32-bit? 1499 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1500 ReturnMVT = MVT::i8; 1501 else 1502 ReturnMVT = MVT::i32; 1503 1504 EVT MinVT = getRegisterType(Context, ReturnMVT); 1505 return VT.bitsLT(MinVT) ? MinVT : VT; 1506} 1507 1508/// LowerCallResult - Lower the result values of a call into the 1509/// appropriate copies out of appropriate physical registers. 1510/// 1511SDValue 1512X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1513 CallingConv::ID CallConv, bool isVarArg, 1514 const SmallVectorImpl<ISD::InputArg> &Ins, 1515 DebugLoc dl, SelectionDAG &DAG, 1516 SmallVectorImpl<SDValue> &InVals) const { 1517 1518 // Assign locations to each value returned by this call. 1519 SmallVector<CCValAssign, 16> RVLocs; 1520 bool Is64Bit = Subtarget->is64Bit(); 1521 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1522 getTargetMachine(), RVLocs, *DAG.getContext()); 1523 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1524 1525 // Copy all of the result registers out of their specified physreg. 1526 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1527 CCValAssign &VA = RVLocs[i]; 1528 EVT CopyVT = VA.getValVT(); 1529 1530 // If this is x86-64, and we disabled SSE, we can't return FP values 1531 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1532 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1533 report_fatal_error("SSE register return with SSE disabled"); 1534 } 1535 1536 SDValue Val; 1537 1538 // If this is a call to a function that returns an fp value on the floating 1539 // point stack, we must guarantee the the value is popped from the stack, so 1540 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1541 // if the return value is not used. We use the FpPOP_RETVAL instruction 1542 // instead. 1543 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1544 // If we prefer to use the value in xmm registers, copy it out as f80 and 1545 // use a truncate to move it from fp stack reg to xmm reg. 1546 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1547 SDValue Ops[] = { Chain, InFlag }; 1548 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1549 MVT::Other, MVT::Glue, Ops, 2), 1); 1550 Val = Chain.getValue(0); 1551 1552 // Round the f80 to the right size, which also moves it to the appropriate 1553 // xmm register. 1554 if (CopyVT != VA.getValVT()) 1555 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1556 // This truncation won't change the value. 1557 DAG.getIntPtrConstant(1)); 1558 } else { 1559 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1560 CopyVT, InFlag).getValue(1); 1561 Val = Chain.getValue(0); 1562 } 1563 InFlag = Chain.getValue(2); 1564 InVals.push_back(Val); 1565 } 1566 1567 return Chain; 1568} 1569 1570 1571//===----------------------------------------------------------------------===// 1572// C & StdCall & Fast Calling Convention implementation 1573//===----------------------------------------------------------------------===// 1574// StdCall calling convention seems to be standard for many Windows' API 1575// routines and around. It differs from C calling convention just a little: 1576// callee should clean up the stack, not caller. Symbols should be also 1577// decorated in some fancy way :) It doesn't support any vector arguments. 1578// For info on fast calling convention see Fast Calling Convention (tail call) 1579// implementation LowerX86_32FastCCCallTo. 1580 1581/// CallIsStructReturn - Determines whether a call uses struct return 1582/// semantics. 1583static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1584 if (Outs.empty()) 1585 return false; 1586 1587 return Outs[0].Flags.isSRet(); 1588} 1589 1590/// ArgsAreStructReturn - Determines whether a function uses struct 1591/// return semantics. 1592static bool 1593ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1594 if (Ins.empty()) 1595 return false; 1596 1597 return Ins[0].Flags.isSRet(); 1598} 1599 1600/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1601/// by "Src" to address "Dst" with size and alignment information specified by 1602/// the specific parameter attribute. The copy will be passed as a byval 1603/// function parameter. 1604static SDValue 1605CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1606 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1607 DebugLoc dl) { 1608 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1609 1610 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1611 /*isVolatile*/false, /*AlwaysInline=*/true, 1612 MachinePointerInfo(), MachinePointerInfo()); 1613} 1614 1615/// IsTailCallConvention - Return true if the calling convention is one that 1616/// supports tail call optimization. 1617static bool IsTailCallConvention(CallingConv::ID CC) { 1618 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1619} 1620 1621bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1622 if (!CI->isTailCall()) 1623 return false; 1624 1625 CallSite CS(CI); 1626 CallingConv::ID CalleeCC = CS.getCallingConv(); 1627 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1628 return false; 1629 1630 return true; 1631} 1632 1633/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1634/// a tailcall target by changing its ABI. 1635static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1636 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1637} 1638 1639SDValue 1640X86TargetLowering::LowerMemArgument(SDValue Chain, 1641 CallingConv::ID CallConv, 1642 const SmallVectorImpl<ISD::InputArg> &Ins, 1643 DebugLoc dl, SelectionDAG &DAG, 1644 const CCValAssign &VA, 1645 MachineFrameInfo *MFI, 1646 unsigned i) const { 1647 // Create the nodes corresponding to a load from this parameter slot. 1648 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1649 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1650 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1651 EVT ValVT; 1652 1653 // If value is passed by pointer we have address passed instead of the value 1654 // itself. 1655 if (VA.getLocInfo() == CCValAssign::Indirect) 1656 ValVT = VA.getLocVT(); 1657 else 1658 ValVT = VA.getValVT(); 1659 1660 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1661 // changed with more analysis. 1662 // In case of tail call optimization mark all arguments mutable. Since they 1663 // could be overwritten by lowering of arguments in case of a tail call. 1664 if (Flags.isByVal()) { 1665 unsigned Bytes = Flags.getByValSize(); 1666 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1667 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1668 return DAG.getFrameIndex(FI, getPointerTy()); 1669 } else { 1670 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1671 VA.getLocMemOffset(), isImmutable); 1672 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1673 return DAG.getLoad(ValVT, dl, Chain, FIN, 1674 MachinePointerInfo::getFixedStack(FI), 1675 false, false, 0); 1676 } 1677} 1678 1679SDValue 1680X86TargetLowering::LowerFormalArguments(SDValue Chain, 1681 CallingConv::ID CallConv, 1682 bool isVarArg, 1683 const SmallVectorImpl<ISD::InputArg> &Ins, 1684 DebugLoc dl, 1685 SelectionDAG &DAG, 1686 SmallVectorImpl<SDValue> &InVals) 1687 const { 1688 MachineFunction &MF = DAG.getMachineFunction(); 1689 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1690 1691 const Function* Fn = MF.getFunction(); 1692 if (Fn->hasExternalLinkage() && 1693 Subtarget->isTargetCygMing() && 1694 Fn->getName() == "main") 1695 FuncInfo->setForceFramePointer(true); 1696 1697 MachineFrameInfo *MFI = MF.getFrameInfo(); 1698 bool Is64Bit = Subtarget->is64Bit(); 1699 bool IsWin64 = Subtarget->isTargetWin64(); 1700 1701 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1702 "Var args not supported with calling convention fastcc or ghc"); 1703 1704 // Assign locations to all of the incoming arguments. 1705 SmallVector<CCValAssign, 16> ArgLocs; 1706 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1707 ArgLocs, *DAG.getContext()); 1708 1709 // Allocate shadow area for Win64 1710 if (IsWin64) { 1711 CCInfo.AllocateStack(32, 8); 1712 } 1713 1714 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1715 1716 unsigned LastVal = ~0U; 1717 SDValue ArgValue; 1718 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1719 CCValAssign &VA = ArgLocs[i]; 1720 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1721 // places. 1722 assert(VA.getValNo() != LastVal && 1723 "Don't support value assigned to multiple locs yet"); 1724 LastVal = VA.getValNo(); 1725 1726 if (VA.isRegLoc()) { 1727 EVT RegVT = VA.getLocVT(); 1728 TargetRegisterClass *RC = NULL; 1729 if (RegVT == MVT::i32) 1730 RC = X86::GR32RegisterClass; 1731 else if (Is64Bit && RegVT == MVT::i64) 1732 RC = X86::GR64RegisterClass; 1733 else if (RegVT == MVT::f32) 1734 RC = X86::FR32RegisterClass; 1735 else if (RegVT == MVT::f64) 1736 RC = X86::FR64RegisterClass; 1737 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1738 RC = X86::VR256RegisterClass; 1739 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1740 RC = X86::VR128RegisterClass; 1741 else if (RegVT == MVT::x86mmx) 1742 RC = X86::VR64RegisterClass; 1743 else 1744 llvm_unreachable("Unknown argument type!"); 1745 1746 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1747 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1748 1749 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1750 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1751 // right size. 1752 if (VA.getLocInfo() == CCValAssign::SExt) 1753 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1754 DAG.getValueType(VA.getValVT())); 1755 else if (VA.getLocInfo() == CCValAssign::ZExt) 1756 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1757 DAG.getValueType(VA.getValVT())); 1758 else if (VA.getLocInfo() == CCValAssign::BCvt) 1759 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1760 1761 if (VA.isExtInLoc()) { 1762 // Handle MMX values passed in XMM regs. 1763 if (RegVT.isVector()) { 1764 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1765 ArgValue); 1766 } else 1767 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1768 } 1769 } else { 1770 assert(VA.isMemLoc()); 1771 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1772 } 1773 1774 // If value is passed via pointer - do a load. 1775 if (VA.getLocInfo() == CCValAssign::Indirect) 1776 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1777 MachinePointerInfo(), false, false, 0); 1778 1779 InVals.push_back(ArgValue); 1780 } 1781 1782 // The x86-64 ABI for returning structs by value requires that we copy 1783 // the sret argument into %rax for the return. Save the argument into 1784 // a virtual register so that we can access it from the return points. 1785 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1786 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1787 unsigned Reg = FuncInfo->getSRetReturnReg(); 1788 if (!Reg) { 1789 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1790 FuncInfo->setSRetReturnReg(Reg); 1791 } 1792 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1794 } 1795 1796 unsigned StackSize = CCInfo.getNextStackOffset(); 1797 // Align stack specially for tail calls. 1798 if (FuncIsMadeTailCallSafe(CallConv)) 1799 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1800 1801 // If the function takes variable number of arguments, make a frame index for 1802 // the start of the first vararg value... for expansion of llvm.va_start. 1803 if (isVarArg) { 1804 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1805 CallConv != CallingConv::X86_ThisCall)) { 1806 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1807 } 1808 if (Is64Bit) { 1809 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1810 1811 // FIXME: We should really autogenerate these arrays 1812 static const unsigned GPR64ArgRegsWin64[] = { 1813 X86::RCX, X86::RDX, X86::R8, X86::R9 1814 }; 1815 static const unsigned GPR64ArgRegs64Bit[] = { 1816 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1817 }; 1818 static const unsigned XMMArgRegs64Bit[] = { 1819 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1820 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1821 }; 1822 const unsigned *GPR64ArgRegs; 1823 unsigned NumXMMRegs = 0; 1824 1825 if (IsWin64) { 1826 // The XMM registers which might contain var arg parameters are shadowed 1827 // in their paired GPR. So we only need to save the GPR to their home 1828 // slots. 1829 TotalNumIntRegs = 4; 1830 GPR64ArgRegs = GPR64ArgRegsWin64; 1831 } else { 1832 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1833 GPR64ArgRegs = GPR64ArgRegs64Bit; 1834 1835 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1836 } 1837 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1838 TotalNumIntRegs); 1839 1840 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1841 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1842 "SSE register cannot be used when SSE is disabled!"); 1843 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1844 "SSE register cannot be used when SSE is disabled!"); 1845 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1846 // Kernel mode asks for SSE to be disabled, so don't push them 1847 // on the stack. 1848 TotalNumXMMRegs = 0; 1849 1850 if (IsWin64) { 1851 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1852 // Get to the caller-allocated home save location. Add 8 to account 1853 // for the return address. 1854 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1855 FuncInfo->setRegSaveFrameIndex( 1856 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1857 // Fixup to set vararg frame on shadow area (4 x i64). 1858 if (NumIntRegs < 4) 1859 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1860 } else { 1861 // For X86-64, if there are vararg parameters that are passed via 1862 // registers, then we must store them to their spots on the stack so they 1863 // may be loaded by deferencing the result of va_next. 1864 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1865 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1866 FuncInfo->setRegSaveFrameIndex( 1867 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1868 false)); 1869 } 1870 1871 // Store the integer parameter registers. 1872 SmallVector<SDValue, 8> MemOps; 1873 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1874 getPointerTy()); 1875 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1876 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1877 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1878 DAG.getIntPtrConstant(Offset)); 1879 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1880 X86::GR64RegisterClass); 1881 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1882 SDValue Store = 1883 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1884 MachinePointerInfo::getFixedStack( 1885 FuncInfo->getRegSaveFrameIndex(), Offset), 1886 false, false, 0); 1887 MemOps.push_back(Store); 1888 Offset += 8; 1889 } 1890 1891 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1892 // Now store the XMM (fp + vector) parameter registers. 1893 SmallVector<SDValue, 11> SaveXMMOps; 1894 SaveXMMOps.push_back(Chain); 1895 1896 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1897 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1898 SaveXMMOps.push_back(ALVal); 1899 1900 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1901 FuncInfo->getRegSaveFrameIndex())); 1902 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1903 FuncInfo->getVarArgsFPOffset())); 1904 1905 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1906 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1907 X86::VR128RegisterClass); 1908 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1909 SaveXMMOps.push_back(Val); 1910 } 1911 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1912 MVT::Other, 1913 &SaveXMMOps[0], SaveXMMOps.size())); 1914 } 1915 1916 if (!MemOps.empty()) 1917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1918 &MemOps[0], MemOps.size()); 1919 } 1920 } 1921 1922 // Some CCs need callee pop. 1923 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 1924 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1925 } else { 1926 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1927 // If this is an sret function, the return should pop the hidden pointer. 1928 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1929 FuncInfo->setBytesToPopOnReturn(4); 1930 } 1931 1932 if (!Is64Bit) { 1933 // RegSaveFrameIndex is X86-64 only. 1934 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1935 if (CallConv == CallingConv::X86_FastCall || 1936 CallConv == CallingConv::X86_ThisCall) 1937 // fastcc functions can't have varargs. 1938 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1939 } 1940 1941 FuncInfo->setArgumentStackSize(StackSize); 1942 1943 return Chain; 1944} 1945 1946SDValue 1947X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1948 SDValue StackPtr, SDValue Arg, 1949 DebugLoc dl, SelectionDAG &DAG, 1950 const CCValAssign &VA, 1951 ISD::ArgFlagsTy Flags) const { 1952 unsigned LocMemOffset = VA.getLocMemOffset(); 1953 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1954 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1955 if (Flags.isByVal()) 1956 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1957 1958 return DAG.getStore(Chain, dl, Arg, PtrOff, 1959 MachinePointerInfo::getStack(LocMemOffset), 1960 false, false, 0); 1961} 1962 1963/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1964/// optimization is performed and it is required. 1965SDValue 1966X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1967 SDValue &OutRetAddr, SDValue Chain, 1968 bool IsTailCall, bool Is64Bit, 1969 int FPDiff, DebugLoc dl) const { 1970 // Adjust the Return address stack slot. 1971 EVT VT = getPointerTy(); 1972 OutRetAddr = getReturnAddressFrameIndex(DAG); 1973 1974 // Load the "old" Return address. 1975 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1976 false, false, 0); 1977 return SDValue(OutRetAddr.getNode(), 1); 1978} 1979 1980/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 1981/// optimization is performed and it is required (FPDiff!=0). 1982static SDValue 1983EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1984 SDValue Chain, SDValue RetAddrFrIdx, 1985 bool Is64Bit, int FPDiff, DebugLoc dl) { 1986 // Store the return address to the appropriate stack slot. 1987 if (!FPDiff) return Chain; 1988 // Calculate the new stack slot for the return address. 1989 int SlotSize = Is64Bit ? 8 : 4; 1990 int NewReturnAddrFI = 1991 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1992 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1993 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1994 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1995 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 1996 false, false, 0); 1997 return Chain; 1998} 1999 2000SDValue 2001X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2002 CallingConv::ID CallConv, bool isVarArg, 2003 bool &isTailCall, 2004 const SmallVectorImpl<ISD::OutputArg> &Outs, 2005 const SmallVectorImpl<SDValue> &OutVals, 2006 const SmallVectorImpl<ISD::InputArg> &Ins, 2007 DebugLoc dl, SelectionDAG &DAG, 2008 SmallVectorImpl<SDValue> &InVals) const { 2009 MachineFunction &MF = DAG.getMachineFunction(); 2010 bool Is64Bit = Subtarget->is64Bit(); 2011 bool IsWin64 = Subtarget->isTargetWin64(); 2012 bool IsStructRet = CallIsStructReturn(Outs); 2013 bool IsSibcall = false; 2014 2015 if (isTailCall) { 2016 // Check if it's really possible to do a tail call. 2017 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2018 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2019 Outs, OutVals, Ins, DAG); 2020 2021 // Sibcalls are automatically detected tailcalls which do not require 2022 // ABI changes. 2023 if (!GuaranteedTailCallOpt && isTailCall) 2024 IsSibcall = true; 2025 2026 if (isTailCall) 2027 ++NumTailCalls; 2028 } 2029 2030 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2031 "Var args not supported with calling convention fastcc or ghc"); 2032 2033 // Analyze operands of the call, assigning locations to each operand. 2034 SmallVector<CCValAssign, 16> ArgLocs; 2035 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2036 ArgLocs, *DAG.getContext()); 2037 2038 // Allocate shadow area for Win64 2039 if (IsWin64) { 2040 CCInfo.AllocateStack(32, 8); 2041 } 2042 2043 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2044 2045 // Get a count of how many bytes are to be pushed on the stack. 2046 unsigned NumBytes = CCInfo.getNextStackOffset(); 2047 if (IsSibcall) 2048 // This is a sibcall. The memory operands are available in caller's 2049 // own caller's stack. 2050 NumBytes = 0; 2051 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2052 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2053 2054 int FPDiff = 0; 2055 if (isTailCall && !IsSibcall) { 2056 // Lower arguments at fp - stackoffset + fpdiff. 2057 unsigned NumBytesCallerPushed = 2058 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2059 FPDiff = NumBytesCallerPushed - NumBytes; 2060 2061 // Set the delta of movement of the returnaddr stackslot. 2062 // But only set if delta is greater than previous delta. 2063 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2064 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2065 } 2066 2067 if (!IsSibcall) 2068 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2069 2070 SDValue RetAddrFrIdx; 2071 // Load return address for tail calls. 2072 if (isTailCall && FPDiff) 2073 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2074 Is64Bit, FPDiff, dl); 2075 2076 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2077 SmallVector<SDValue, 8> MemOpChains; 2078 SDValue StackPtr; 2079 2080 // Walk the register/memloc assignments, inserting copies/loads. In the case 2081 // of tail call optimization arguments are handle later. 2082 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2083 CCValAssign &VA = ArgLocs[i]; 2084 EVT RegVT = VA.getLocVT(); 2085 SDValue Arg = OutVals[i]; 2086 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2087 bool isByVal = Flags.isByVal(); 2088 2089 // Promote the value if needed. 2090 switch (VA.getLocInfo()) { 2091 default: llvm_unreachable("Unknown loc info!"); 2092 case CCValAssign::Full: break; 2093 case CCValAssign::SExt: 2094 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2095 break; 2096 case CCValAssign::ZExt: 2097 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2098 break; 2099 case CCValAssign::AExt: 2100 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2101 // Special case: passing MMX values in XMM registers. 2102 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2103 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2104 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2105 } else 2106 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2107 break; 2108 case CCValAssign::BCvt: 2109 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2110 break; 2111 case CCValAssign::Indirect: { 2112 // Store the argument. 2113 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2114 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2115 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2116 MachinePointerInfo::getFixedStack(FI), 2117 false, false, 0); 2118 Arg = SpillSlot; 2119 break; 2120 } 2121 } 2122 2123 if (VA.isRegLoc()) { 2124 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2125 if (isVarArg && IsWin64) { 2126 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2127 // shadow reg if callee is a varargs function. 2128 unsigned ShadowReg = 0; 2129 switch (VA.getLocReg()) { 2130 case X86::XMM0: ShadowReg = X86::RCX; break; 2131 case X86::XMM1: ShadowReg = X86::RDX; break; 2132 case X86::XMM2: ShadowReg = X86::R8; break; 2133 case X86::XMM3: ShadowReg = X86::R9; break; 2134 } 2135 if (ShadowReg) 2136 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2137 } 2138 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2139 assert(VA.isMemLoc()); 2140 if (StackPtr.getNode() == 0) 2141 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2142 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2143 dl, DAG, VA, Flags)); 2144 } 2145 } 2146 2147 if (!MemOpChains.empty()) 2148 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2149 &MemOpChains[0], MemOpChains.size()); 2150 2151 // Build a sequence of copy-to-reg nodes chained together with token chain 2152 // and flag operands which copy the outgoing args into registers. 2153 SDValue InFlag; 2154 // Tail call byval lowering might overwrite argument registers so in case of 2155 // tail call optimization the copies to registers are lowered later. 2156 if (!isTailCall) 2157 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2158 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2159 RegsToPass[i].second, InFlag); 2160 InFlag = Chain.getValue(1); 2161 } 2162 2163 if (Subtarget->isPICStyleGOT()) { 2164 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2165 // GOT pointer. 2166 if (!isTailCall) { 2167 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2168 DAG.getNode(X86ISD::GlobalBaseReg, 2169 DebugLoc(), getPointerTy()), 2170 InFlag); 2171 InFlag = Chain.getValue(1); 2172 } else { 2173 // If we are tail calling and generating PIC/GOT style code load the 2174 // address of the callee into ECX. The value in ecx is used as target of 2175 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2176 // for tail calls on PIC/GOT architectures. Normally we would just put the 2177 // address of GOT into ebx and then call target@PLT. But for tail calls 2178 // ebx would be restored (since ebx is callee saved) before jumping to the 2179 // target@PLT. 2180 2181 // Note: The actual moving to ECX is done further down. 2182 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2183 if (G && !G->getGlobal()->hasHiddenVisibility() && 2184 !G->getGlobal()->hasProtectedVisibility()) 2185 Callee = LowerGlobalAddress(Callee, DAG); 2186 else if (isa<ExternalSymbolSDNode>(Callee)) 2187 Callee = LowerExternalSymbol(Callee, DAG); 2188 } 2189 } 2190 2191 if (Is64Bit && isVarArg && !IsWin64) { 2192 // From AMD64 ABI document: 2193 // For calls that may call functions that use varargs or stdargs 2194 // (prototype-less calls or calls to functions containing ellipsis (...) in 2195 // the declaration) %al is used as hidden argument to specify the number 2196 // of SSE registers used. The contents of %al do not need to match exactly 2197 // the number of registers, but must be an ubound on the number of SSE 2198 // registers used and is in the range 0 - 8 inclusive. 2199 2200 // Count the number of XMM registers allocated. 2201 static const unsigned XMMArgRegs[] = { 2202 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2203 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2204 }; 2205 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2206 assert((Subtarget->hasXMM() || !NumXMMRegs) 2207 && "SSE registers cannot be used when SSE is disabled"); 2208 2209 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2210 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2211 InFlag = Chain.getValue(1); 2212 } 2213 2214 2215 // For tail calls lower the arguments to the 'real' stack slot. 2216 if (isTailCall) { 2217 // Force all the incoming stack arguments to be loaded from the stack 2218 // before any new outgoing arguments are stored to the stack, because the 2219 // outgoing stack slots may alias the incoming argument stack slots, and 2220 // the alias isn't otherwise explicit. This is slightly more conservative 2221 // than necessary, because it means that each store effectively depends 2222 // on every argument instead of just those arguments it would clobber. 2223 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2224 2225 SmallVector<SDValue, 8> MemOpChains2; 2226 SDValue FIN; 2227 int FI = 0; 2228 // Do not flag preceding copytoreg stuff together with the following stuff. 2229 InFlag = SDValue(); 2230 if (GuaranteedTailCallOpt) { 2231 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2232 CCValAssign &VA = ArgLocs[i]; 2233 if (VA.isRegLoc()) 2234 continue; 2235 assert(VA.isMemLoc()); 2236 SDValue Arg = OutVals[i]; 2237 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2238 // Create frame index. 2239 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2240 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2241 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2242 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2243 2244 if (Flags.isByVal()) { 2245 // Copy relative to framepointer. 2246 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2247 if (StackPtr.getNode() == 0) 2248 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2249 getPointerTy()); 2250 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2251 2252 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2253 ArgChain, 2254 Flags, DAG, dl)); 2255 } else { 2256 // Store relative to framepointer. 2257 MemOpChains2.push_back( 2258 DAG.getStore(ArgChain, dl, Arg, FIN, 2259 MachinePointerInfo::getFixedStack(FI), 2260 false, false, 0)); 2261 } 2262 } 2263 } 2264 2265 if (!MemOpChains2.empty()) 2266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2267 &MemOpChains2[0], MemOpChains2.size()); 2268 2269 // Copy arguments to their registers. 2270 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2271 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2272 RegsToPass[i].second, InFlag); 2273 InFlag = Chain.getValue(1); 2274 } 2275 InFlag =SDValue(); 2276 2277 // Store the return address to the appropriate stack slot. 2278 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2279 FPDiff, dl); 2280 } 2281 2282 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2283 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2284 // In the 64-bit large code model, we have to make all calls 2285 // through a register, since the call instruction's 32-bit 2286 // pc-relative offset may not be large enough to hold the whole 2287 // address. 2288 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2289 // If the callee is a GlobalAddress node (quite common, every direct call 2290 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2291 // it. 2292 2293 // We should use extra load for direct calls to dllimported functions in 2294 // non-JIT mode. 2295 const GlobalValue *GV = G->getGlobal(); 2296 if (!GV->hasDLLImportLinkage()) { 2297 unsigned char OpFlags = 0; 2298 bool ExtraLoad = false; 2299 unsigned WrapperKind = ISD::DELETED_NODE; 2300 2301 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2302 // external symbols most go through the PLT in PIC mode. If the symbol 2303 // has hidden or protected visibility, or if it is static or local, then 2304 // we don't need to use the PLT - we can directly call it. 2305 if (Subtarget->isTargetELF() && 2306 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2307 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2308 OpFlags = X86II::MO_PLT; 2309 } else if (Subtarget->isPICStyleStubAny() && 2310 (GV->isDeclaration() || GV->isWeakForLinker()) && 2311 (!Subtarget->getTargetTriple().isMacOSX() || 2312 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2313 // PC-relative references to external symbols should go through $stub, 2314 // unless we're building with the leopard linker or later, which 2315 // automatically synthesizes these stubs. 2316 OpFlags = X86II::MO_DARWIN_STUB; 2317 } else if (Subtarget->isPICStyleRIPRel() && 2318 isa<Function>(GV) && 2319 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2320 // If the function is marked as non-lazy, generate an indirect call 2321 // which loads from the GOT directly. This avoids runtime overhead 2322 // at the cost of eager binding (and one extra byte of encoding). 2323 OpFlags = X86II::MO_GOTPCREL; 2324 WrapperKind = X86ISD::WrapperRIP; 2325 ExtraLoad = true; 2326 } 2327 2328 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2329 G->getOffset(), OpFlags); 2330 2331 // Add a wrapper if needed. 2332 if (WrapperKind != ISD::DELETED_NODE) 2333 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2334 // Add extra indirection if needed. 2335 if (ExtraLoad) 2336 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2337 MachinePointerInfo::getGOT(), 2338 false, false, 0); 2339 } 2340 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2341 unsigned char OpFlags = 0; 2342 2343 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2344 // external symbols should go through the PLT. 2345 if (Subtarget->isTargetELF() && 2346 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2347 OpFlags = X86II::MO_PLT; 2348 } else if (Subtarget->isPICStyleStubAny() && 2349 (!Subtarget->getTargetTriple().isMacOSX() || 2350 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2351 // PC-relative references to external symbols should go through $stub, 2352 // unless we're building with the leopard linker or later, which 2353 // automatically synthesizes these stubs. 2354 OpFlags = X86II::MO_DARWIN_STUB; 2355 } 2356 2357 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2358 OpFlags); 2359 } 2360 2361 // Returns a chain & a flag for retval copy to use. 2362 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2363 SmallVector<SDValue, 8> Ops; 2364 2365 if (!IsSibcall && isTailCall) { 2366 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2367 DAG.getIntPtrConstant(0, true), InFlag); 2368 InFlag = Chain.getValue(1); 2369 } 2370 2371 Ops.push_back(Chain); 2372 Ops.push_back(Callee); 2373 2374 if (isTailCall) 2375 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2376 2377 // Add argument registers to the end of the list so that they are known live 2378 // into the call. 2379 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2380 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2381 RegsToPass[i].second.getValueType())); 2382 2383 // Add an implicit use GOT pointer in EBX. 2384 if (!isTailCall && Subtarget->isPICStyleGOT()) 2385 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2386 2387 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2388 if (Is64Bit && isVarArg && !IsWin64) 2389 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2390 2391 if (InFlag.getNode()) 2392 Ops.push_back(InFlag); 2393 2394 if (isTailCall) { 2395 // We used to do: 2396 //// If this is the first return lowered for this function, add the regs 2397 //// to the liveout set for the function. 2398 // This isn't right, although it's probably harmless on x86; liveouts 2399 // should be computed from returns not tail calls. Consider a void 2400 // function making a tail call to a function returning int. 2401 return DAG.getNode(X86ISD::TC_RETURN, dl, 2402 NodeTys, &Ops[0], Ops.size()); 2403 } 2404 2405 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2406 InFlag = Chain.getValue(1); 2407 2408 // Create the CALLSEQ_END node. 2409 unsigned NumBytesForCalleeToPush; 2410 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2411 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2412 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2413 // If this is a call to a struct-return function, the callee 2414 // pops the hidden struct pointer, so we have to push it back. 2415 // This is common for Darwin/X86, Linux & Mingw32 targets. 2416 NumBytesForCalleeToPush = 4; 2417 else 2418 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2419 2420 // Returns a flag for retval copy to use. 2421 if (!IsSibcall) { 2422 Chain = DAG.getCALLSEQ_END(Chain, 2423 DAG.getIntPtrConstant(NumBytes, true), 2424 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2425 true), 2426 InFlag); 2427 InFlag = Chain.getValue(1); 2428 } 2429 2430 // Handle result values, copying them out of physregs into vregs that we 2431 // return. 2432 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2433 Ins, dl, DAG, InVals); 2434} 2435 2436 2437//===----------------------------------------------------------------------===// 2438// Fast Calling Convention (tail call) implementation 2439//===----------------------------------------------------------------------===// 2440 2441// Like std call, callee cleans arguments, convention except that ECX is 2442// reserved for storing the tail called function address. Only 2 registers are 2443// free for argument passing (inreg). Tail call optimization is performed 2444// provided: 2445// * tailcallopt is enabled 2446// * caller/callee are fastcc 2447// On X86_64 architecture with GOT-style position independent code only local 2448// (within module) calls are supported at the moment. 2449// To keep the stack aligned according to platform abi the function 2450// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2451// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2452// If a tail called function callee has more arguments than the caller the 2453// caller needs to make sure that there is room to move the RETADDR to. This is 2454// achieved by reserving an area the size of the argument delta right after the 2455// original REtADDR, but before the saved framepointer or the spilled registers 2456// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2457// stack layout: 2458// arg1 2459// arg2 2460// RETADDR 2461// [ new RETADDR 2462// move area ] 2463// (possible EBP) 2464// ESI 2465// EDI 2466// local1 .. 2467 2468/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2469/// for a 16 byte align requirement. 2470unsigned 2471X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2472 SelectionDAG& DAG) const { 2473 MachineFunction &MF = DAG.getMachineFunction(); 2474 const TargetMachine &TM = MF.getTarget(); 2475 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2476 unsigned StackAlignment = TFI.getStackAlignment(); 2477 uint64_t AlignMask = StackAlignment - 1; 2478 int64_t Offset = StackSize; 2479 uint64_t SlotSize = TD->getPointerSize(); 2480 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2481 // Number smaller than 12 so just add the difference. 2482 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2483 } else { 2484 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2485 Offset = ((~AlignMask) & Offset) + StackAlignment + 2486 (StackAlignment-SlotSize); 2487 } 2488 return Offset; 2489} 2490 2491/// MatchingStackOffset - Return true if the given stack call argument is 2492/// already available in the same position (relatively) of the caller's 2493/// incoming argument stack. 2494static 2495bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2496 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2497 const X86InstrInfo *TII) { 2498 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2499 int FI = INT_MAX; 2500 if (Arg.getOpcode() == ISD::CopyFromReg) { 2501 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2502 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2503 return false; 2504 MachineInstr *Def = MRI->getVRegDef(VR); 2505 if (!Def) 2506 return false; 2507 if (!Flags.isByVal()) { 2508 if (!TII->isLoadFromStackSlot(Def, FI)) 2509 return false; 2510 } else { 2511 unsigned Opcode = Def->getOpcode(); 2512 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2513 Def->getOperand(1).isFI()) { 2514 FI = Def->getOperand(1).getIndex(); 2515 Bytes = Flags.getByValSize(); 2516 } else 2517 return false; 2518 } 2519 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2520 if (Flags.isByVal()) 2521 // ByVal argument is passed in as a pointer but it's now being 2522 // dereferenced. e.g. 2523 // define @foo(%struct.X* %A) { 2524 // tail call @bar(%struct.X* byval %A) 2525 // } 2526 return false; 2527 SDValue Ptr = Ld->getBasePtr(); 2528 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2529 if (!FINode) 2530 return false; 2531 FI = FINode->getIndex(); 2532 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2533 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2534 FI = FINode->getIndex(); 2535 Bytes = Flags.getByValSize(); 2536 } else 2537 return false; 2538 2539 assert(FI != INT_MAX); 2540 if (!MFI->isFixedObjectIndex(FI)) 2541 return false; 2542 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2543} 2544 2545/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2546/// for tail call optimization. Targets which want to do tail call 2547/// optimization should implement this function. 2548bool 2549X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2550 CallingConv::ID CalleeCC, 2551 bool isVarArg, 2552 bool isCalleeStructRet, 2553 bool isCallerStructRet, 2554 const SmallVectorImpl<ISD::OutputArg> &Outs, 2555 const SmallVectorImpl<SDValue> &OutVals, 2556 const SmallVectorImpl<ISD::InputArg> &Ins, 2557 SelectionDAG& DAG) const { 2558 if (!IsTailCallConvention(CalleeCC) && 2559 CalleeCC != CallingConv::C) 2560 return false; 2561 2562 // If -tailcallopt is specified, make fastcc functions tail-callable. 2563 const MachineFunction &MF = DAG.getMachineFunction(); 2564 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2565 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2566 bool CCMatch = CallerCC == CalleeCC; 2567 2568 if (GuaranteedTailCallOpt) { 2569 if (IsTailCallConvention(CalleeCC) && CCMatch) 2570 return true; 2571 return false; 2572 } 2573 2574 // Look for obvious safe cases to perform tail call optimization that do not 2575 // require ABI changes. This is what gcc calls sibcall. 2576 2577 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2578 // emit a special epilogue. 2579 if (RegInfo->needsStackRealignment(MF)) 2580 return false; 2581 2582 // Also avoid sibcall optimization if either caller or callee uses struct 2583 // return semantics. 2584 if (isCalleeStructRet || isCallerStructRet) 2585 return false; 2586 2587 // An stdcall caller is expected to clean up its arguments; the callee 2588 // isn't going to do that. 2589 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2590 return false; 2591 2592 // Do not sibcall optimize vararg calls unless all arguments are passed via 2593 // registers. 2594 if (isVarArg && !Outs.empty()) { 2595 2596 // Optimizing for varargs on Win64 is unlikely to be safe without 2597 // additional testing. 2598 if (Subtarget->isTargetWin64()) 2599 return false; 2600 2601 SmallVector<CCValAssign, 16> ArgLocs; 2602 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2603 getTargetMachine(), ArgLocs, *DAG.getContext()); 2604 2605 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2606 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2607 if (!ArgLocs[i].isRegLoc()) 2608 return false; 2609 } 2610 2611 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2612 // Therefore if it's not used by the call it is not safe to optimize this into 2613 // a sibcall. 2614 bool Unused = false; 2615 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2616 if (!Ins[i].Used) { 2617 Unused = true; 2618 break; 2619 } 2620 } 2621 if (Unused) { 2622 SmallVector<CCValAssign, 16> RVLocs; 2623 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2624 getTargetMachine(), RVLocs, *DAG.getContext()); 2625 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2626 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2627 CCValAssign &VA = RVLocs[i]; 2628 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2629 return false; 2630 } 2631 } 2632 2633 // If the calling conventions do not match, then we'd better make sure the 2634 // results are returned in the same way as what the caller expects. 2635 if (!CCMatch) { 2636 SmallVector<CCValAssign, 16> RVLocs1; 2637 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2638 getTargetMachine(), RVLocs1, *DAG.getContext()); 2639 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2640 2641 SmallVector<CCValAssign, 16> RVLocs2; 2642 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2643 getTargetMachine(), RVLocs2, *DAG.getContext()); 2644 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2645 2646 if (RVLocs1.size() != RVLocs2.size()) 2647 return false; 2648 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2649 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2650 return false; 2651 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2652 return false; 2653 if (RVLocs1[i].isRegLoc()) { 2654 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2655 return false; 2656 } else { 2657 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2658 return false; 2659 } 2660 } 2661 } 2662 2663 // If the callee takes no arguments then go on to check the results of the 2664 // call. 2665 if (!Outs.empty()) { 2666 // Check if stack adjustment is needed. For now, do not do this if any 2667 // argument is passed on the stack. 2668 SmallVector<CCValAssign, 16> ArgLocs; 2669 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2670 getTargetMachine(), ArgLocs, *DAG.getContext()); 2671 2672 // Allocate shadow area for Win64 2673 if (Subtarget->isTargetWin64()) { 2674 CCInfo.AllocateStack(32, 8); 2675 } 2676 2677 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2678 if (CCInfo.getNextStackOffset()) { 2679 MachineFunction &MF = DAG.getMachineFunction(); 2680 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2681 return false; 2682 2683 // Check if the arguments are already laid out in the right way as 2684 // the caller's fixed stack objects. 2685 MachineFrameInfo *MFI = MF.getFrameInfo(); 2686 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2687 const X86InstrInfo *TII = 2688 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2689 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2690 CCValAssign &VA = ArgLocs[i]; 2691 SDValue Arg = OutVals[i]; 2692 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2693 if (VA.getLocInfo() == CCValAssign::Indirect) 2694 return false; 2695 if (!VA.isRegLoc()) { 2696 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2697 MFI, MRI, TII)) 2698 return false; 2699 } 2700 } 2701 } 2702 2703 // If the tailcall address may be in a register, then make sure it's 2704 // possible to register allocate for it. In 32-bit, the call address can 2705 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2706 // callee-saved registers are restored. These happen to be the same 2707 // registers used to pass 'inreg' arguments so watch out for those. 2708 if (!Subtarget->is64Bit() && 2709 !isa<GlobalAddressSDNode>(Callee) && 2710 !isa<ExternalSymbolSDNode>(Callee)) { 2711 unsigned NumInRegs = 0; 2712 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2713 CCValAssign &VA = ArgLocs[i]; 2714 if (!VA.isRegLoc()) 2715 continue; 2716 unsigned Reg = VA.getLocReg(); 2717 switch (Reg) { 2718 default: break; 2719 case X86::EAX: case X86::EDX: case X86::ECX: 2720 if (++NumInRegs == 3) 2721 return false; 2722 break; 2723 } 2724 } 2725 } 2726 } 2727 2728 return true; 2729} 2730 2731FastISel * 2732X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2733 return X86::createFastISel(funcInfo); 2734} 2735 2736 2737//===----------------------------------------------------------------------===// 2738// Other Lowering Hooks 2739//===----------------------------------------------------------------------===// 2740 2741static bool MayFoldLoad(SDValue Op) { 2742 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2743} 2744 2745static bool MayFoldIntoStore(SDValue Op) { 2746 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2747} 2748 2749static bool isTargetShuffle(unsigned Opcode) { 2750 switch(Opcode) { 2751 default: return false; 2752 case X86ISD::PSHUFD: 2753 case X86ISD::PSHUFHW: 2754 case X86ISD::PSHUFLW: 2755 case X86ISD::SHUFPD: 2756 case X86ISD::PALIGN: 2757 case X86ISD::SHUFPS: 2758 case X86ISD::MOVLHPS: 2759 case X86ISD::MOVLHPD: 2760 case X86ISD::MOVHLPS: 2761 case X86ISD::MOVLPS: 2762 case X86ISD::MOVLPD: 2763 case X86ISD::MOVSHDUP: 2764 case X86ISD::MOVSLDUP: 2765 case X86ISD::MOVDDUP: 2766 case X86ISD::MOVSS: 2767 case X86ISD::MOVSD: 2768 case X86ISD::UNPCKLPS: 2769 case X86ISD::UNPCKLPD: 2770 case X86ISD::VUNPCKLPSY: 2771 case X86ISD::VUNPCKLPDY: 2772 case X86ISD::PUNPCKLWD: 2773 case X86ISD::PUNPCKLBW: 2774 case X86ISD::PUNPCKLDQ: 2775 case X86ISD::PUNPCKLQDQ: 2776 case X86ISD::UNPCKHPS: 2777 case X86ISD::UNPCKHPD: 2778 case X86ISD::VUNPCKHPSY: 2779 case X86ISD::VUNPCKHPDY: 2780 case X86ISD::PUNPCKHWD: 2781 case X86ISD::PUNPCKHBW: 2782 case X86ISD::PUNPCKHDQ: 2783 case X86ISD::PUNPCKHQDQ: 2784 case X86ISD::VPERMILPS: 2785 case X86ISD::VPERMILPSY: 2786 case X86ISD::VPERMILPD: 2787 case X86ISD::VPERMILPDY: 2788 case X86ISD::VPERM2F128: 2789 return true; 2790 } 2791 return false; 2792} 2793 2794static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2795 SDValue V1, SelectionDAG &DAG) { 2796 switch(Opc) { 2797 default: llvm_unreachable("Unknown x86 shuffle node"); 2798 case X86ISD::MOVSHDUP: 2799 case X86ISD::MOVSLDUP: 2800 case X86ISD::MOVDDUP: 2801 return DAG.getNode(Opc, dl, VT, V1); 2802 } 2803 2804 return SDValue(); 2805} 2806 2807static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2808 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2809 switch(Opc) { 2810 default: llvm_unreachable("Unknown x86 shuffle node"); 2811 case X86ISD::PSHUFD: 2812 case X86ISD::PSHUFHW: 2813 case X86ISD::PSHUFLW: 2814 case X86ISD::VPERMILPS: 2815 case X86ISD::VPERMILPSY: 2816 case X86ISD::VPERMILPD: 2817 case X86ISD::VPERMILPDY: 2818 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2819 } 2820 2821 return SDValue(); 2822} 2823 2824static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2825 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2826 switch(Opc) { 2827 default: llvm_unreachable("Unknown x86 shuffle node"); 2828 case X86ISD::PALIGN: 2829 case X86ISD::SHUFPD: 2830 case X86ISD::SHUFPS: 2831 case X86ISD::VPERM2F128: 2832 return DAG.getNode(Opc, dl, VT, V1, V2, 2833 DAG.getConstant(TargetMask, MVT::i8)); 2834 } 2835 return SDValue(); 2836} 2837 2838static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2839 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2840 switch(Opc) { 2841 default: llvm_unreachable("Unknown x86 shuffle node"); 2842 case X86ISD::MOVLHPS: 2843 case X86ISD::MOVLHPD: 2844 case X86ISD::MOVHLPS: 2845 case X86ISD::MOVLPS: 2846 case X86ISD::MOVLPD: 2847 case X86ISD::MOVSS: 2848 case X86ISD::MOVSD: 2849 case X86ISD::UNPCKLPS: 2850 case X86ISD::UNPCKLPD: 2851 case X86ISD::VUNPCKLPSY: 2852 case X86ISD::VUNPCKLPDY: 2853 case X86ISD::PUNPCKLWD: 2854 case X86ISD::PUNPCKLBW: 2855 case X86ISD::PUNPCKLDQ: 2856 case X86ISD::PUNPCKLQDQ: 2857 case X86ISD::UNPCKHPS: 2858 case X86ISD::UNPCKHPD: 2859 case X86ISD::VUNPCKHPSY: 2860 case X86ISD::VUNPCKHPDY: 2861 case X86ISD::PUNPCKHWD: 2862 case X86ISD::PUNPCKHBW: 2863 case X86ISD::PUNPCKHDQ: 2864 case X86ISD::PUNPCKHQDQ: 2865 return DAG.getNode(Opc, dl, VT, V1, V2); 2866 } 2867 return SDValue(); 2868} 2869 2870SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2871 MachineFunction &MF = DAG.getMachineFunction(); 2872 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2873 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2874 2875 if (ReturnAddrIndex == 0) { 2876 // Set up a frame object for the return address. 2877 uint64_t SlotSize = TD->getPointerSize(); 2878 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2879 false); 2880 FuncInfo->setRAIndex(ReturnAddrIndex); 2881 } 2882 2883 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2884} 2885 2886 2887bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2888 bool hasSymbolicDisplacement) { 2889 // Offset should fit into 32 bit immediate field. 2890 if (!isInt<32>(Offset)) 2891 return false; 2892 2893 // If we don't have a symbolic displacement - we don't have any extra 2894 // restrictions. 2895 if (!hasSymbolicDisplacement) 2896 return true; 2897 2898 // FIXME: Some tweaks might be needed for medium code model. 2899 if (M != CodeModel::Small && M != CodeModel::Kernel) 2900 return false; 2901 2902 // For small code model we assume that latest object is 16MB before end of 31 2903 // bits boundary. We may also accept pretty large negative constants knowing 2904 // that all objects are in the positive half of address space. 2905 if (M == CodeModel::Small && Offset < 16*1024*1024) 2906 return true; 2907 2908 // For kernel code model we know that all object resist in the negative half 2909 // of 32bits address space. We may not accept negative offsets, since they may 2910 // be just off and we may accept pretty large positive ones. 2911 if (M == CodeModel::Kernel && Offset > 0) 2912 return true; 2913 2914 return false; 2915} 2916 2917/// isCalleePop - Determines whether the callee is required to pop its 2918/// own arguments. Callee pop is necessary to support tail calls. 2919bool X86::isCalleePop(CallingConv::ID CallingConv, 2920 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2921 if (IsVarArg) 2922 return false; 2923 2924 switch (CallingConv) { 2925 default: 2926 return false; 2927 case CallingConv::X86_StdCall: 2928 return !is64Bit; 2929 case CallingConv::X86_FastCall: 2930 return !is64Bit; 2931 case CallingConv::X86_ThisCall: 2932 return !is64Bit; 2933 case CallingConv::Fast: 2934 return TailCallOpt; 2935 case CallingConv::GHC: 2936 return TailCallOpt; 2937 } 2938} 2939 2940/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2941/// specific condition code, returning the condition code and the LHS/RHS of the 2942/// comparison to make. 2943static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2944 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2945 if (!isFP) { 2946 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2947 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2948 // X > -1 -> X == 0, jump !sign. 2949 RHS = DAG.getConstant(0, RHS.getValueType()); 2950 return X86::COND_NS; 2951 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2952 // X < 0 -> X == 0, jump on sign. 2953 return X86::COND_S; 2954 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2955 // X < 1 -> X <= 0 2956 RHS = DAG.getConstant(0, RHS.getValueType()); 2957 return X86::COND_LE; 2958 } 2959 } 2960 2961 switch (SetCCOpcode) { 2962 default: llvm_unreachable("Invalid integer condition!"); 2963 case ISD::SETEQ: return X86::COND_E; 2964 case ISD::SETGT: return X86::COND_G; 2965 case ISD::SETGE: return X86::COND_GE; 2966 case ISD::SETLT: return X86::COND_L; 2967 case ISD::SETLE: return X86::COND_LE; 2968 case ISD::SETNE: return X86::COND_NE; 2969 case ISD::SETULT: return X86::COND_B; 2970 case ISD::SETUGT: return X86::COND_A; 2971 case ISD::SETULE: return X86::COND_BE; 2972 case ISD::SETUGE: return X86::COND_AE; 2973 } 2974 } 2975 2976 // First determine if it is required or is profitable to flip the operands. 2977 2978 // If LHS is a foldable load, but RHS is not, flip the condition. 2979 if (ISD::isNON_EXTLoad(LHS.getNode()) && 2980 !ISD::isNON_EXTLoad(RHS.getNode())) { 2981 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2982 std::swap(LHS, RHS); 2983 } 2984 2985 switch (SetCCOpcode) { 2986 default: break; 2987 case ISD::SETOLT: 2988 case ISD::SETOLE: 2989 case ISD::SETUGT: 2990 case ISD::SETUGE: 2991 std::swap(LHS, RHS); 2992 break; 2993 } 2994 2995 // On a floating point condition, the flags are set as follows: 2996 // ZF PF CF op 2997 // 0 | 0 | 0 | X > Y 2998 // 0 | 0 | 1 | X < Y 2999 // 1 | 0 | 0 | X == Y 3000 // 1 | 1 | 1 | unordered 3001 switch (SetCCOpcode) { 3002 default: llvm_unreachable("Condcode should be pre-legalized away"); 3003 case ISD::SETUEQ: 3004 case ISD::SETEQ: return X86::COND_E; 3005 case ISD::SETOLT: // flipped 3006 case ISD::SETOGT: 3007 case ISD::SETGT: return X86::COND_A; 3008 case ISD::SETOLE: // flipped 3009 case ISD::SETOGE: 3010 case ISD::SETGE: return X86::COND_AE; 3011 case ISD::SETUGT: // flipped 3012 case ISD::SETULT: 3013 case ISD::SETLT: return X86::COND_B; 3014 case ISD::SETUGE: // flipped 3015 case ISD::SETULE: 3016 case ISD::SETLE: return X86::COND_BE; 3017 case ISD::SETONE: 3018 case ISD::SETNE: return X86::COND_NE; 3019 case ISD::SETUO: return X86::COND_P; 3020 case ISD::SETO: return X86::COND_NP; 3021 case ISD::SETOEQ: 3022 case ISD::SETUNE: return X86::COND_INVALID; 3023 } 3024} 3025 3026/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3027/// code. Current x86 isa includes the following FP cmov instructions: 3028/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3029static bool hasFPCMov(unsigned X86CC) { 3030 switch (X86CC) { 3031 default: 3032 return false; 3033 case X86::COND_B: 3034 case X86::COND_BE: 3035 case X86::COND_E: 3036 case X86::COND_P: 3037 case X86::COND_A: 3038 case X86::COND_AE: 3039 case X86::COND_NE: 3040 case X86::COND_NP: 3041 return true; 3042 } 3043} 3044 3045/// isFPImmLegal - Returns true if the target can instruction select the 3046/// specified FP immediate natively. If false, the legalizer will 3047/// materialize the FP immediate as a load from a constant pool. 3048bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3049 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3050 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3051 return true; 3052 } 3053 return false; 3054} 3055 3056/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3057/// the specified range (L, H]. 3058static bool isUndefOrInRange(int Val, int Low, int Hi) { 3059 return (Val < 0) || (Val >= Low && Val < Hi); 3060} 3061 3062/// isUndefOrInRange - Return true if every element in Mask, begining 3063/// from position Pos and ending in Pos+Size, falls within the specified 3064/// range (L, L+Pos]. or is undef. 3065static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3066 int Pos, int Size, int Low, int Hi) { 3067 for (int i = Pos, e = Pos+Size; i != e; ++i) 3068 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3069 return false; 3070 return true; 3071} 3072 3073/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3074/// specified value. 3075static bool isUndefOrEqual(int Val, int CmpVal) { 3076 if (Val < 0 || Val == CmpVal) 3077 return true; 3078 return false; 3079} 3080 3081/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3082/// from position Pos and ending in Pos+Size, falls within the specified 3083/// sequential range (L, L+Pos]. or is undef. 3084static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3085 int Pos, int Size, int Low) { 3086 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3087 if (!isUndefOrEqual(Mask[i], Low)) 3088 return false; 3089 return true; 3090} 3091 3092/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3093/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3094/// the second operand. 3095static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3096 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3097 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3098 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3099 return (Mask[0] < 2 && Mask[1] < 2); 3100 return false; 3101} 3102 3103bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3104 SmallVector<int, 8> M; 3105 N->getMask(M); 3106 return ::isPSHUFDMask(M, N->getValueType(0)); 3107} 3108 3109/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3110/// is suitable for input to PSHUFHW. 3111static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3112 if (VT != MVT::v8i16) 3113 return false; 3114 3115 // Lower quadword copied in order or undef. 3116 for (int i = 0; i != 4; ++i) 3117 if (Mask[i] >= 0 && Mask[i] != i) 3118 return false; 3119 3120 // Upper quadword shuffled. 3121 for (int i = 4; i != 8; ++i) 3122 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3123 return false; 3124 3125 return true; 3126} 3127 3128bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3129 SmallVector<int, 8> M; 3130 N->getMask(M); 3131 return ::isPSHUFHWMask(M, N->getValueType(0)); 3132} 3133 3134/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3135/// is suitable for input to PSHUFLW. 3136static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3137 if (VT != MVT::v8i16) 3138 return false; 3139 3140 // Upper quadword copied in order. 3141 for (int i = 4; i != 8; ++i) 3142 if (Mask[i] >= 0 && Mask[i] != i) 3143 return false; 3144 3145 // Lower quadword shuffled. 3146 for (int i = 0; i != 4; ++i) 3147 if (Mask[i] >= 4) 3148 return false; 3149 3150 return true; 3151} 3152 3153bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3154 SmallVector<int, 8> M; 3155 N->getMask(M); 3156 return ::isPSHUFLWMask(M, N->getValueType(0)); 3157} 3158 3159/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3160/// is suitable for input to PALIGNR. 3161static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3162 bool hasSSSE3) { 3163 int i, e = VT.getVectorNumElements(); 3164 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3165 return false; 3166 3167 // Do not handle v2i64 / v2f64 shuffles with palignr. 3168 if (e < 4 || !hasSSSE3) 3169 return false; 3170 3171 for (i = 0; i != e; ++i) 3172 if (Mask[i] >= 0) 3173 break; 3174 3175 // All undef, not a palignr. 3176 if (i == e) 3177 return false; 3178 3179 // Make sure we're shifting in the right direction. 3180 if (Mask[i] <= i) 3181 return false; 3182 3183 int s = Mask[i] - i; 3184 3185 // Check the rest of the elements to see if they are consecutive. 3186 for (++i; i != e; ++i) { 3187 int m = Mask[i]; 3188 if (m >= 0 && m != s+i) 3189 return false; 3190 } 3191 return true; 3192} 3193 3194/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand 3195/// specifies a shuffle of elements that is suitable for input to 256-bit 3196/// VSHUFPSY. 3197static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3198 const X86Subtarget *Subtarget) { 3199 int NumElems = VT.getVectorNumElements(); 3200 3201 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3202 return false; 3203 3204 if (NumElems != 8) 3205 return false; 3206 3207 // VSHUFPSY divides the resulting vector into 4 chunks. 3208 // The sources are also splitted into 4 chunks, and each destination 3209 // chunk must come from a different source chunk. 3210 // 3211 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3212 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3213 // 3214 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3215 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3216 // 3217 int QuarterSize = NumElems/4; 3218 int HalfSize = QuarterSize*2; 3219 for (int i = 0; i < QuarterSize; ++i) 3220 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3221 return false; 3222 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3223 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3224 return false; 3225 3226 // The mask of the second half must be the same as the first but with 3227 // the appropriate offsets. This works in the same way as VPERMILPS 3228 // works with masks. 3229 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { 3230 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3231 return false; 3232 int FstHalfIdx = i-HalfSize; 3233 if (Mask[FstHalfIdx] < 0) 3234 continue; 3235 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3236 return false; 3237 } 3238 for (int i = QuarterSize*3; i < NumElems; ++i) { 3239 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3240 return false; 3241 int FstHalfIdx = i-HalfSize; 3242 if (Mask[FstHalfIdx] < 0) 3243 continue; 3244 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3245 return false; 3246 3247 } 3248 3249 return true; 3250} 3251 3252/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle 3253/// the specified VECTOR_MASK mask with VSHUFPSY instruction. 3254static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { 3255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3256 EVT VT = SVOp->getValueType(0); 3257 int NumElems = VT.getVectorNumElements(); 3258 3259 assert(NumElems == 8 && VT.getSizeInBits() == 256 && 3260 "Only supports v8i32 and v8f32 types"); 3261 3262 int HalfSize = NumElems/2; 3263 unsigned Mask = 0; 3264 for (int i = 0; i != NumElems ; ++i) { 3265 if (SVOp->getMaskElt(i) < 0) 3266 continue; 3267 // The mask of the first half must be equal to the second one. 3268 unsigned Shamt = (i%HalfSize)*2; 3269 unsigned Elt = SVOp->getMaskElt(i) % HalfSize; 3270 Mask |= Elt << Shamt; 3271 } 3272 3273 return Mask; 3274} 3275 3276/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand 3277/// specifies a shuffle of elements that is suitable for input to 256-bit 3278/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS 3279/// version and the mask of the second half isn't binded with the first 3280/// one. 3281static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3282 const X86Subtarget *Subtarget) { 3283 int NumElems = VT.getVectorNumElements(); 3284 3285 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3286 return false; 3287 3288 if (NumElems != 4) 3289 return false; 3290 3291 // VSHUFPSY divides the resulting vector into 4 chunks. 3292 // The sources are also splitted into 4 chunks, and each destination 3293 // chunk must come from a different source chunk. 3294 // 3295 // SRC1 => X3 X2 X1 X0 3296 // SRC2 => Y3 Y2 Y1 Y0 3297 // 3298 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 3299 // 3300 int QuarterSize = NumElems/4; 3301 int HalfSize = QuarterSize*2; 3302 for (int i = 0; i < QuarterSize; ++i) 3303 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3304 return false; 3305 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3306 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3307 return false; 3308 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) 3309 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3310 return false; 3311 for (int i = QuarterSize*3; i < NumElems; ++i) 3312 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3313 return false; 3314 3315 return true; 3316} 3317 3318/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle 3319/// the specified VECTOR_MASK mask with VSHUFPDY instruction. 3320static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { 3321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3322 EVT VT = SVOp->getValueType(0); 3323 int NumElems = VT.getVectorNumElements(); 3324 3325 assert(NumElems == 4 && VT.getSizeInBits() == 256 && 3326 "Only supports v4i64 and v4f64 types"); 3327 3328 int HalfSize = NumElems/2; 3329 unsigned Mask = 0; 3330 for (int i = 0; i != NumElems ; ++i) { 3331 if (SVOp->getMaskElt(i) < 0) 3332 continue; 3333 int Elt = SVOp->getMaskElt(i) % HalfSize; 3334 Mask |= Elt << i; 3335 } 3336 3337 return Mask; 3338} 3339 3340/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3341/// specifies a shuffle of elements that is suitable for input to 128-bit 3342/// SHUFPS and SHUFPD. 3343static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3344 int NumElems = VT.getVectorNumElements(); 3345 3346 if (VT.getSizeInBits() != 128) 3347 return false; 3348 3349 if (NumElems != 2 && NumElems != 4) 3350 return false; 3351 3352 int Half = NumElems / 2; 3353 for (int i = 0; i < Half; ++i) 3354 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3355 return false; 3356 for (int i = Half; i < NumElems; ++i) 3357 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3358 return false; 3359 3360 return true; 3361} 3362 3363bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3364 SmallVector<int, 8> M; 3365 N->getMask(M); 3366 return ::isSHUFPMask(M, N->getValueType(0)); 3367} 3368 3369/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3370/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3371/// half elements to come from vector 1 (which would equal the dest.) and 3372/// the upper half to come from vector 2. 3373static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3374 int NumElems = VT.getVectorNumElements(); 3375 3376 if (NumElems != 2 && NumElems != 4) 3377 return false; 3378 3379 int Half = NumElems / 2; 3380 for (int i = 0; i < Half; ++i) 3381 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3382 return false; 3383 for (int i = Half; i < NumElems; ++i) 3384 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3385 return false; 3386 return true; 3387} 3388 3389static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3390 SmallVector<int, 8> M; 3391 N->getMask(M); 3392 return isCommutedSHUFPMask(M, N->getValueType(0)); 3393} 3394 3395/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3396/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3397bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3398 EVT VT = N->getValueType(0); 3399 unsigned NumElems = VT.getVectorNumElements(); 3400 3401 if (VT.getSizeInBits() != 128) 3402 return false; 3403 3404 if (NumElems != 4) 3405 return false; 3406 3407 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3408 return isUndefOrEqual(N->getMaskElt(0), 6) && 3409 isUndefOrEqual(N->getMaskElt(1), 7) && 3410 isUndefOrEqual(N->getMaskElt(2), 2) && 3411 isUndefOrEqual(N->getMaskElt(3), 3); 3412} 3413 3414/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3415/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3416/// <2, 3, 2, 3> 3417bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3418 EVT VT = N->getValueType(0); 3419 unsigned NumElems = VT.getVectorNumElements(); 3420 3421 if (VT.getSizeInBits() != 128) 3422 return false; 3423 3424 if (NumElems != 4) 3425 return false; 3426 3427 return isUndefOrEqual(N->getMaskElt(0), 2) && 3428 isUndefOrEqual(N->getMaskElt(1), 3) && 3429 isUndefOrEqual(N->getMaskElt(2), 2) && 3430 isUndefOrEqual(N->getMaskElt(3), 3); 3431} 3432 3433/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3434/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3435bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3436 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3437 3438 if (NumElems != 2 && NumElems != 4) 3439 return false; 3440 3441 for (unsigned i = 0; i < NumElems/2; ++i) 3442 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3443 return false; 3444 3445 for (unsigned i = NumElems/2; i < NumElems; ++i) 3446 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3447 return false; 3448 3449 return true; 3450} 3451 3452/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3453/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3454bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3455 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3456 3457 if ((NumElems != 2 && NumElems != 4) 3458 || N->getValueType(0).getSizeInBits() > 128) 3459 return false; 3460 3461 for (unsigned i = 0; i < NumElems/2; ++i) 3462 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3463 return false; 3464 3465 for (unsigned i = 0; i < NumElems/2; ++i) 3466 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3467 return false; 3468 3469 return true; 3470} 3471 3472/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3473/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3474static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3475 bool V2IsSplat = false) { 3476 int NumElts = VT.getVectorNumElements(); 3477 3478 assert((VT.is128BitVector() || VT.is256BitVector()) && 3479 "Unsupported vector type for unpckh"); 3480 3481 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3482 return false; 3483 3484 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3485 // independently on 128-bit lanes. 3486 unsigned NumLanes = VT.getSizeInBits()/128; 3487 unsigned NumLaneElts = NumElts/NumLanes; 3488 3489 unsigned Start = 0; 3490 unsigned End = NumLaneElts; 3491 for (unsigned s = 0; s < NumLanes; ++s) { 3492 for (unsigned i = Start, j = s * NumLaneElts; 3493 i != End; 3494 i += 2, ++j) { 3495 int BitI = Mask[i]; 3496 int BitI1 = Mask[i+1]; 3497 if (!isUndefOrEqual(BitI, j)) 3498 return false; 3499 if (V2IsSplat) { 3500 if (!isUndefOrEqual(BitI1, NumElts)) 3501 return false; 3502 } else { 3503 if (!isUndefOrEqual(BitI1, j + NumElts)) 3504 return false; 3505 } 3506 } 3507 // Process the next 128 bits. 3508 Start += NumLaneElts; 3509 End += NumLaneElts; 3510 } 3511 3512 return true; 3513} 3514 3515bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3516 SmallVector<int, 8> M; 3517 N->getMask(M); 3518 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3519} 3520 3521/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3522/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3523static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3524 bool V2IsSplat = false) { 3525 int NumElts = VT.getVectorNumElements(); 3526 3527 assert((VT.is128BitVector() || VT.is256BitVector()) && 3528 "Unsupported vector type for unpckh"); 3529 3530 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3531 return false; 3532 3533 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3534 // independently on 128-bit lanes. 3535 unsigned NumLanes = VT.getSizeInBits()/128; 3536 unsigned NumLaneElts = NumElts/NumLanes; 3537 3538 unsigned Start = 0; 3539 unsigned End = NumLaneElts; 3540 for (unsigned l = 0; l != NumLanes; ++l) { 3541 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3542 i != End; i += 2, ++j) { 3543 int BitI = Mask[i]; 3544 int BitI1 = Mask[i+1]; 3545 if (!isUndefOrEqual(BitI, j)) 3546 return false; 3547 if (V2IsSplat) { 3548 if (isUndefOrEqual(BitI1, NumElts)) 3549 return false; 3550 } else { 3551 if (!isUndefOrEqual(BitI1, j+NumElts)) 3552 return false; 3553 } 3554 } 3555 // Process the next 128 bits. 3556 Start += NumLaneElts; 3557 End += NumLaneElts; 3558 } 3559 return true; 3560} 3561 3562bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3563 SmallVector<int, 8> M; 3564 N->getMask(M); 3565 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3566} 3567 3568/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3569/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3570/// <0, 0, 1, 1> 3571static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3572 int NumElems = VT.getVectorNumElements(); 3573 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3574 return false; 3575 3576 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3577 // FIXME: Need a better way to get rid of this, there's no latency difference 3578 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3579 // the former later. We should also remove the "_undef" special mask. 3580 if (NumElems == 4 && VT.getSizeInBits() == 256) 3581 return false; 3582 3583 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3584 // independently on 128-bit lanes. 3585 unsigned NumLanes = VT.getSizeInBits() / 128; 3586 unsigned NumLaneElts = NumElems / NumLanes; 3587 3588 for (unsigned s = 0; s < NumLanes; ++s) { 3589 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3590 i != NumLaneElts * (s + 1); 3591 i += 2, ++j) { 3592 int BitI = Mask[i]; 3593 int BitI1 = Mask[i+1]; 3594 3595 if (!isUndefOrEqual(BitI, j)) 3596 return false; 3597 if (!isUndefOrEqual(BitI1, j)) 3598 return false; 3599 } 3600 } 3601 3602 return true; 3603} 3604 3605bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3606 SmallVector<int, 8> M; 3607 N->getMask(M); 3608 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3609} 3610 3611/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3612/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3613/// <2, 2, 3, 3> 3614static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3615 int NumElems = VT.getVectorNumElements(); 3616 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3617 return false; 3618 3619 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3620 int BitI = Mask[i]; 3621 int BitI1 = Mask[i+1]; 3622 if (!isUndefOrEqual(BitI, j)) 3623 return false; 3624 if (!isUndefOrEqual(BitI1, j)) 3625 return false; 3626 } 3627 return true; 3628} 3629 3630bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3631 SmallVector<int, 8> M; 3632 N->getMask(M); 3633 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3634} 3635 3636/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3637/// specifies a shuffle of elements that is suitable for input to MOVSS, 3638/// MOVSD, and MOVD, i.e. setting the lowest element. 3639static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3640 if (VT.getVectorElementType().getSizeInBits() < 32) 3641 return false; 3642 3643 int NumElts = VT.getVectorNumElements(); 3644 3645 if (!isUndefOrEqual(Mask[0], NumElts)) 3646 return false; 3647 3648 for (int i = 1; i < NumElts; ++i) 3649 if (!isUndefOrEqual(Mask[i], i)) 3650 return false; 3651 3652 return true; 3653} 3654 3655bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3656 SmallVector<int, 8> M; 3657 N->getMask(M); 3658 return ::isMOVLMask(M, N->getValueType(0)); 3659} 3660 3661/// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered 3662/// as permutations between 128-bit chunks or halves. As an example: this 3663/// shuffle bellow: 3664/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3665/// The first half comes from the second half of V1 and the second half from the 3666/// the second half of V2. 3667static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3668 const X86Subtarget *Subtarget) { 3669 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3670 return false; 3671 3672 // The shuffle result is divided into half A and half B. In total the two 3673 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3674 // B must come from C, D, E or F. 3675 int HalfSize = VT.getVectorNumElements()/2; 3676 bool MatchA = false, MatchB = false; 3677 3678 // Check if A comes from one of C, D, E, F. 3679 for (int Half = 0; Half < 4; ++Half) { 3680 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3681 MatchA = true; 3682 break; 3683 } 3684 } 3685 3686 // Check if B comes from one of C, D, E, F. 3687 for (int Half = 0; Half < 4; ++Half) { 3688 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3689 MatchB = true; 3690 break; 3691 } 3692 } 3693 3694 return MatchA && MatchB; 3695} 3696 3697/// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle 3698/// the specified VECTOR_MASK mask with VPERM2F128 instructions. 3699static unsigned getShuffleVPERM2F128Immediate(SDNode *N) { 3700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3701 EVT VT = SVOp->getValueType(0); 3702 3703 int HalfSize = VT.getVectorNumElements()/2; 3704 3705 int FstHalf = 0, SndHalf = 0; 3706 for (int i = 0; i < HalfSize; ++i) { 3707 if (SVOp->getMaskElt(i) > 0) { 3708 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3709 break; 3710 } 3711 } 3712 for (int i = HalfSize; i < HalfSize*2; ++i) { 3713 if (SVOp->getMaskElt(i) > 0) { 3714 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3715 break; 3716 } 3717 } 3718 3719 return (FstHalf | (SndHalf << 4)); 3720} 3721 3722/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3723/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3724/// Note that VPERMIL mask matching is different depending whether theunderlying 3725/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3726/// to the same elements of the low, but to the higher half of the source. 3727/// In VPERMILPD the two lanes could be shuffled independently of each other 3728/// with the same restriction that lanes can't be crossed. 3729static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3730 const X86Subtarget *Subtarget) { 3731 int NumElts = VT.getVectorNumElements(); 3732 int NumLanes = VT.getSizeInBits()/128; 3733 3734 if (!Subtarget->hasAVX()) 3735 return false; 3736 3737 // Match any permutation of 128-bit vector with 64-bit types 3738 if (NumLanes == 1 && NumElts != 2) 3739 return false; 3740 3741 // Only match 256-bit with 32 types 3742 if (VT.getSizeInBits() == 256 && NumElts != 4) 3743 return false; 3744 3745 // The mask on the high lane is independent of the low. Both can match 3746 // any element in inside its own lane, but can't cross. 3747 int LaneSize = NumElts/NumLanes; 3748 for (int l = 0; l < NumLanes; ++l) 3749 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3750 int LaneStart = l*LaneSize; 3751 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3752 return false; 3753 } 3754 3755 return true; 3756} 3757 3758/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3759/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3760/// Note that VPERMIL mask matching is different depending whether theunderlying 3761/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3762/// to the same elements of the low, but to the higher half of the source. 3763/// In VPERMILPD the two lanes could be shuffled independently of each other 3764/// with the same restriction that lanes can't be crossed. 3765static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3766 const X86Subtarget *Subtarget) { 3767 unsigned NumElts = VT.getVectorNumElements(); 3768 unsigned NumLanes = VT.getSizeInBits()/128; 3769 3770 if (!Subtarget->hasAVX()) 3771 return false; 3772 3773 // Match any permutation of 128-bit vector with 32-bit types 3774 if (NumLanes == 1 && NumElts != 4) 3775 return false; 3776 3777 // Only match 256-bit with 32 types 3778 if (VT.getSizeInBits() == 256 && NumElts != 8) 3779 return false; 3780 3781 // The mask on the high lane should be the same as the low. Actually, 3782 // they can differ if any of the corresponding index in a lane is undef 3783 // and the other stays in range. 3784 int LaneSize = NumElts/NumLanes; 3785 for (int i = 0; i < LaneSize; ++i) { 3786 int HighElt = i+LaneSize; 3787 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3788 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3789 3790 if (!HighValid || !LowValid) 3791 return false; 3792 if (Mask[i] < 0 || Mask[HighElt] < 0) 3793 continue; 3794 if (Mask[HighElt]-Mask[i] != LaneSize) 3795 return false; 3796 } 3797 3798 return true; 3799} 3800 3801/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3802/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3803static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3804 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3805 EVT VT = SVOp->getValueType(0); 3806 3807 int NumElts = VT.getVectorNumElements(); 3808 int NumLanes = VT.getSizeInBits()/128; 3809 int LaneSize = NumElts/NumLanes; 3810 3811 // Although the mask is equal for both lanes do it twice to get the cases 3812 // where a mask will match because the same mask element is undef on the 3813 // first half but valid on the second. This would get pathological cases 3814 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3815 unsigned Mask = 0; 3816 for (int l = 0; l < NumLanes; ++l) { 3817 for (int i = 0; i < LaneSize; ++i) { 3818 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3819 if (MaskElt < 0) 3820 continue; 3821 if (MaskElt >= LaneSize) 3822 MaskElt -= LaneSize; 3823 Mask |= MaskElt << (i*2); 3824 } 3825 } 3826 3827 return Mask; 3828} 3829 3830/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3831/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3832static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3833 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3834 EVT VT = SVOp->getValueType(0); 3835 3836 int NumElts = VT.getVectorNumElements(); 3837 int NumLanes = VT.getSizeInBits()/128; 3838 3839 unsigned Mask = 0; 3840 int LaneSize = NumElts/NumLanes; 3841 for (int l = 0; l < NumLanes; ++l) 3842 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3843 int MaskElt = SVOp->getMaskElt(i); 3844 if (MaskElt < 0) 3845 continue; 3846 Mask |= (MaskElt-l*LaneSize) << i; 3847 } 3848 3849 return Mask; 3850} 3851 3852/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3853/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3854/// element of vector 2 and the other elements to come from vector 1 in order. 3855static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3856 bool V2IsSplat = false, bool V2IsUndef = false) { 3857 int NumOps = VT.getVectorNumElements(); 3858 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3859 return false; 3860 3861 if (!isUndefOrEqual(Mask[0], 0)) 3862 return false; 3863 3864 for (int i = 1; i < NumOps; ++i) 3865 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3866 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3867 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3868 return false; 3869 3870 return true; 3871} 3872 3873static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3874 bool V2IsUndef = false) { 3875 SmallVector<int, 8> M; 3876 N->getMask(M); 3877 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3878} 3879 3880/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3881/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3882/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3883bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3884 const X86Subtarget *Subtarget) { 3885 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3886 return false; 3887 3888 // The second vector must be undef 3889 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3890 return false; 3891 3892 EVT VT = N->getValueType(0); 3893 unsigned NumElems = VT.getVectorNumElements(); 3894 3895 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3896 (VT.getSizeInBits() == 256 && NumElems != 8)) 3897 return false; 3898 3899 // "i+1" is the value the indexed mask element must have 3900 for (unsigned i = 0; i < NumElems; i += 2) 3901 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3902 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3903 return false; 3904 3905 return true; 3906} 3907 3908/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3909/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3910/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3911bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3912 const X86Subtarget *Subtarget) { 3913 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3914 return false; 3915 3916 // The second vector must be undef 3917 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3918 return false; 3919 3920 EVT VT = N->getValueType(0); 3921 unsigned NumElems = VT.getVectorNumElements(); 3922 3923 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3924 (VT.getSizeInBits() == 256 && NumElems != 8)) 3925 return false; 3926 3927 // "i" is the value the indexed mask element must have 3928 for (unsigned i = 0; i < NumElems; i += 2) 3929 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3930 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3931 return false; 3932 3933 return true; 3934} 3935 3936/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3937/// specifies a shuffle of elements that is suitable for input to 256-bit 3938/// version of MOVDDUP. 3939static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, 3940 const X86Subtarget *Subtarget) { 3941 EVT VT = N->getValueType(0); 3942 int NumElts = VT.getVectorNumElements(); 3943 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; 3944 3945 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || 3946 !V2IsUndef || NumElts != 4) 3947 return false; 3948 3949 for (int i = 0; i != NumElts/2; ++i) 3950 if (!isUndefOrEqual(N->getMaskElt(i), 0)) 3951 return false; 3952 for (int i = NumElts/2; i != NumElts; ++i) 3953 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) 3954 return false; 3955 return true; 3956} 3957 3958/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3959/// specifies a shuffle of elements that is suitable for input to 128-bit 3960/// version of MOVDDUP. 3961bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3962 EVT VT = N->getValueType(0); 3963 3964 if (VT.getSizeInBits() != 128) 3965 return false; 3966 3967 int e = VT.getVectorNumElements() / 2; 3968 for (int i = 0; i < e; ++i) 3969 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3970 return false; 3971 for (int i = 0; i < e; ++i) 3972 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3973 return false; 3974 return true; 3975} 3976 3977/// isVEXTRACTF128Index - Return true if the specified 3978/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3979/// suitable for input to VEXTRACTF128. 3980bool X86::isVEXTRACTF128Index(SDNode *N) { 3981 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3982 return false; 3983 3984 // The index should be aligned on a 128-bit boundary. 3985 uint64_t Index = 3986 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3987 3988 unsigned VL = N->getValueType(0).getVectorNumElements(); 3989 unsigned VBits = N->getValueType(0).getSizeInBits(); 3990 unsigned ElSize = VBits / VL; 3991 bool Result = (Index * ElSize) % 128 == 0; 3992 3993 return Result; 3994} 3995 3996/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3997/// operand specifies a subvector insert that is suitable for input to 3998/// VINSERTF128. 3999bool X86::isVINSERTF128Index(SDNode *N) { 4000 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4001 return false; 4002 4003 // The index should be aligned on a 128-bit boundary. 4004 uint64_t Index = 4005 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4006 4007 unsigned VL = N->getValueType(0).getVectorNumElements(); 4008 unsigned VBits = N->getValueType(0).getSizeInBits(); 4009 unsigned ElSize = VBits / VL; 4010 bool Result = (Index * ElSize) % 128 == 0; 4011 4012 return Result; 4013} 4014 4015/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4016/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4017unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 4018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4019 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 4020 4021 unsigned Shift = (NumOperands == 4) ? 2 : 1; 4022 unsigned Mask = 0; 4023 for (int i = 0; i < NumOperands; ++i) { 4024 int Val = SVOp->getMaskElt(NumOperands-i-1); 4025 if (Val < 0) Val = 0; 4026 if (Val >= NumOperands) Val -= NumOperands; 4027 Mask |= Val; 4028 if (i != NumOperands - 1) 4029 Mask <<= Shift; 4030 } 4031 return Mask; 4032} 4033 4034/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4035/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4036unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 4037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4038 unsigned Mask = 0; 4039 // 8 nodes, but we only care about the last 4. 4040 for (unsigned i = 7; i >= 4; --i) { 4041 int Val = SVOp->getMaskElt(i); 4042 if (Val >= 0) 4043 Mask |= (Val - 4); 4044 if (i != 4) 4045 Mask <<= 2; 4046 } 4047 return Mask; 4048} 4049 4050/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4051/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4052unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4054 unsigned Mask = 0; 4055 // 8 nodes, but we only care about the first 4. 4056 for (int i = 3; i >= 0; --i) { 4057 int Val = SVOp->getMaskElt(i); 4058 if (Val >= 0) 4059 Mask |= Val; 4060 if (i != 0) 4061 Mask <<= 2; 4062 } 4063 return Mask; 4064} 4065 4066/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4067/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4068unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 4069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4070 EVT VVT = N->getValueType(0); 4071 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 4072 int Val = 0; 4073 4074 unsigned i, e; 4075 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 4076 Val = SVOp->getMaskElt(i); 4077 if (Val >= 0) 4078 break; 4079 } 4080 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4081 return (Val - i) * EltSize; 4082} 4083 4084/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4085/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4086/// instructions. 4087unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4088 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4089 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4090 4091 uint64_t Index = 4092 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4093 4094 EVT VecVT = N->getOperand(0).getValueType(); 4095 EVT ElVT = VecVT.getVectorElementType(); 4096 4097 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4098 return Index / NumElemsPerChunk; 4099} 4100 4101/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4102/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4103/// instructions. 4104unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4105 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4106 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4107 4108 uint64_t Index = 4109 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4110 4111 EVT VecVT = N->getValueType(0); 4112 EVT ElVT = VecVT.getVectorElementType(); 4113 4114 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4115 return Index / NumElemsPerChunk; 4116} 4117 4118/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4119/// constant +0.0. 4120bool X86::isZeroNode(SDValue Elt) { 4121 return ((isa<ConstantSDNode>(Elt) && 4122 cast<ConstantSDNode>(Elt)->isNullValue()) || 4123 (isa<ConstantFPSDNode>(Elt) && 4124 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4125} 4126 4127/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4128/// their permute mask. 4129static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4130 SelectionDAG &DAG) { 4131 EVT VT = SVOp->getValueType(0); 4132 unsigned NumElems = VT.getVectorNumElements(); 4133 SmallVector<int, 8> MaskVec; 4134 4135 for (unsigned i = 0; i != NumElems; ++i) { 4136 int idx = SVOp->getMaskElt(i); 4137 if (idx < 0) 4138 MaskVec.push_back(idx); 4139 else if (idx < (int)NumElems) 4140 MaskVec.push_back(idx + NumElems); 4141 else 4142 MaskVec.push_back(idx - NumElems); 4143 } 4144 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4145 SVOp->getOperand(0), &MaskVec[0]); 4146} 4147 4148/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 4149/// the two vector operands have swapped position. 4150static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 4151 unsigned NumElems = VT.getVectorNumElements(); 4152 for (unsigned i = 0; i != NumElems; ++i) { 4153 int idx = Mask[i]; 4154 if (idx < 0) 4155 continue; 4156 else if (idx < (int)NumElems) 4157 Mask[i] = idx + NumElems; 4158 else 4159 Mask[i] = idx - NumElems; 4160 } 4161} 4162 4163/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4164/// match movhlps. The lower half elements should come from upper half of 4165/// V1 (and in order), and the upper half elements should come from the upper 4166/// half of V2 (and in order). 4167static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4168 EVT VT = Op->getValueType(0); 4169 if (VT.getSizeInBits() != 128) 4170 return false; 4171 if (VT.getVectorNumElements() != 4) 4172 return false; 4173 for (unsigned i = 0, e = 2; i != e; ++i) 4174 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4175 return false; 4176 for (unsigned i = 2; i != 4; ++i) 4177 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4178 return false; 4179 return true; 4180} 4181 4182/// isScalarLoadToVector - Returns true if the node is a scalar load that 4183/// is promoted to a vector. It also returns the LoadSDNode by reference if 4184/// required. 4185static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4186 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4187 return false; 4188 N = N->getOperand(0).getNode(); 4189 if (!ISD::isNON_EXTLoad(N)) 4190 return false; 4191 if (LD) 4192 *LD = cast<LoadSDNode>(N); 4193 return true; 4194} 4195 4196/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4197/// match movlp{s|d}. The lower half elements should come from lower half of 4198/// V1 (and in order), and the upper half elements should come from the upper 4199/// half of V2 (and in order). And since V1 will become the source of the 4200/// MOVLP, it must be either a vector load or a scalar load to vector. 4201static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4202 ShuffleVectorSDNode *Op) { 4203 EVT VT = Op->getValueType(0); 4204 if (VT.getSizeInBits() != 128) 4205 return false; 4206 4207 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4208 return false; 4209 // Is V2 is a vector load, don't do this transformation. We will try to use 4210 // load folding shufps op. 4211 if (ISD::isNON_EXTLoad(V2)) 4212 return false; 4213 4214 unsigned NumElems = VT.getVectorNumElements(); 4215 4216 if (NumElems != 2 && NumElems != 4) 4217 return false; 4218 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4219 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4220 return false; 4221 for (unsigned i = NumElems/2; i != NumElems; ++i) 4222 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4223 return false; 4224 return true; 4225} 4226 4227/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4228/// all the same. 4229static bool isSplatVector(SDNode *N) { 4230 if (N->getOpcode() != ISD::BUILD_VECTOR) 4231 return false; 4232 4233 SDValue SplatValue = N->getOperand(0); 4234 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4235 if (N->getOperand(i) != SplatValue) 4236 return false; 4237 return true; 4238} 4239 4240/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4241/// to an zero vector. 4242/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4243static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4244 SDValue V1 = N->getOperand(0); 4245 SDValue V2 = N->getOperand(1); 4246 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4247 for (unsigned i = 0; i != NumElems; ++i) { 4248 int Idx = N->getMaskElt(i); 4249 if (Idx >= (int)NumElems) { 4250 unsigned Opc = V2.getOpcode(); 4251 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4252 continue; 4253 if (Opc != ISD::BUILD_VECTOR || 4254 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4255 return false; 4256 } else if (Idx >= 0) { 4257 unsigned Opc = V1.getOpcode(); 4258 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4259 continue; 4260 if (Opc != ISD::BUILD_VECTOR || 4261 !X86::isZeroNode(V1.getOperand(Idx))) 4262 return false; 4263 } 4264 } 4265 return true; 4266} 4267 4268/// getZeroVector - Returns a vector of specified type with all zero elements. 4269/// 4270static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 4271 DebugLoc dl) { 4272 assert(VT.isVector() && "Expected a vector type"); 4273 4274 // Always build SSE zero vectors as <4 x i32> bitcasted 4275 // to their dest type. This ensures they get CSE'd. 4276 SDValue Vec; 4277 if (VT.getSizeInBits() == 128) { // SSE 4278 if (HasSSE2) { // SSE2 4279 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4281 } else { // SSE1 4282 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4283 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4284 } 4285 } else if (VT.getSizeInBits() == 256) { // AVX 4286 // 256-bit logic and arithmetic instructions in AVX are 4287 // all floating-point, no support for integer ops. Default 4288 // to emitting fp zeroed vectors then. 4289 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4290 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4291 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4292 } 4293 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4294} 4295 4296/// getOnesVector - Returns a vector of specified type with all bits set. 4297/// Always build ones vectors as <4 x i32>. For 256-bit types, use two 4298/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 4299/// original type, ensuring they get CSE'd. 4300static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4301 assert(VT.isVector() && "Expected a vector type"); 4302 assert((VT.is128BitVector() || VT.is256BitVector()) 4303 && "Expected a 128-bit or 256-bit vector type"); 4304 4305 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4306 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 4307 Cst, Cst, Cst, Cst); 4308 4309 if (VT.is256BitVector()) { 4310 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4311 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4312 Vec = Insert128BitVector(InsV, Vec, 4313 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4314 } 4315 4316 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4317} 4318 4319/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4320/// that point to V2 points to its first element. 4321static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4322 EVT VT = SVOp->getValueType(0); 4323 unsigned NumElems = VT.getVectorNumElements(); 4324 4325 bool Changed = false; 4326 SmallVector<int, 8> MaskVec; 4327 SVOp->getMask(MaskVec); 4328 4329 for (unsigned i = 0; i != NumElems; ++i) { 4330 if (MaskVec[i] > (int)NumElems) { 4331 MaskVec[i] = NumElems; 4332 Changed = true; 4333 } 4334 } 4335 if (Changed) 4336 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4337 SVOp->getOperand(1), &MaskVec[0]); 4338 return SDValue(SVOp, 0); 4339} 4340 4341/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4342/// operation of specified width. 4343static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4344 SDValue V2) { 4345 unsigned NumElems = VT.getVectorNumElements(); 4346 SmallVector<int, 8> Mask; 4347 Mask.push_back(NumElems); 4348 for (unsigned i = 1; i != NumElems; ++i) 4349 Mask.push_back(i); 4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4351} 4352 4353/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4354static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4355 SDValue V2) { 4356 unsigned NumElems = VT.getVectorNumElements(); 4357 SmallVector<int, 8> Mask; 4358 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4359 Mask.push_back(i); 4360 Mask.push_back(i + NumElems); 4361 } 4362 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4363} 4364 4365/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4366static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4367 SDValue V2) { 4368 unsigned NumElems = VT.getVectorNumElements(); 4369 unsigned Half = NumElems/2; 4370 SmallVector<int, 8> Mask; 4371 for (unsigned i = 0; i != Half; ++i) { 4372 Mask.push_back(i + Half); 4373 Mask.push_back(i + NumElems + Half); 4374 } 4375 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4376} 4377 4378// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4379// a generic shuffle instruction because the target has no such instructions. 4380// Generate shuffles which repeat i16 and i8 several times until they can be 4381// represented by v4f32 and then be manipulated by target suported shuffles. 4382static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4383 EVT VT = V.getValueType(); 4384 int NumElems = VT.getVectorNumElements(); 4385 DebugLoc dl = V.getDebugLoc(); 4386 4387 while (NumElems > 4) { 4388 if (EltNo < NumElems/2) { 4389 V = getUnpackl(DAG, dl, VT, V, V); 4390 } else { 4391 V = getUnpackh(DAG, dl, VT, V, V); 4392 EltNo -= NumElems/2; 4393 } 4394 NumElems >>= 1; 4395 } 4396 return V; 4397} 4398 4399/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4400static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4401 EVT VT = V.getValueType(); 4402 DebugLoc dl = V.getDebugLoc(); 4403 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4404 && "Vector size not supported"); 4405 4406 if (VT.getSizeInBits() == 128) { 4407 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4408 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4409 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4410 &SplatMask[0]); 4411 } else { 4412 // To use VPERMILPS to splat scalars, the second half of indicies must 4413 // refer to the higher part, which is a duplication of the lower one, 4414 // because VPERMILPS can only handle in-lane permutations. 4415 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4416 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4417 4418 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4419 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4420 &SplatMask[0]); 4421 } 4422 4423 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4424} 4425 4426/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4427static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4428 EVT SrcVT = SV->getValueType(0); 4429 SDValue V1 = SV->getOperand(0); 4430 DebugLoc dl = SV->getDebugLoc(); 4431 4432 int EltNo = SV->getSplatIndex(); 4433 int NumElems = SrcVT.getVectorNumElements(); 4434 unsigned Size = SrcVT.getSizeInBits(); 4435 4436 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4437 "Unknown how to promote splat for type"); 4438 4439 // Extract the 128-bit part containing the splat element and update 4440 // the splat element index when it refers to the higher register. 4441 if (Size == 256) { 4442 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4443 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4444 if (Idx > 0) 4445 EltNo -= NumElems/2; 4446 } 4447 4448 // All i16 and i8 vector types can't be used directly by a generic shuffle 4449 // instruction because the target has no such instruction. Generate shuffles 4450 // which repeat i16 and i8 several times until they fit in i32, and then can 4451 // be manipulated by target suported shuffles. 4452 EVT EltVT = SrcVT.getVectorElementType(); 4453 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4454 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4455 4456 // Recreate the 256-bit vector and place the same 128-bit vector 4457 // into the low and high part. This is necessary because we want 4458 // to use VPERM* to shuffle the vectors 4459 if (Size == 256) { 4460 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4461 DAG.getConstant(0, MVT::i32), DAG, dl); 4462 V1 = Insert128BitVector(InsV, V1, 4463 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4464 } 4465 4466 return getLegalSplat(DAG, V1, EltNo); 4467} 4468 4469/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4470/// vector of zero or undef vector. This produces a shuffle where the low 4471/// element of V2 is swizzled into the zero/undef vector, landing at element 4472/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4473static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4474 bool isZero, bool HasSSE2, 4475 SelectionDAG &DAG) { 4476 EVT VT = V2.getValueType(); 4477 SDValue V1 = isZero 4478 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4479 unsigned NumElems = VT.getVectorNumElements(); 4480 SmallVector<int, 16> MaskVec; 4481 for (unsigned i = 0; i != NumElems; ++i) 4482 // If this is the insertion idx, put the low elt of V2 here. 4483 MaskVec.push_back(i == Idx ? NumElems : i); 4484 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4485} 4486 4487/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4488/// element of the result of the vector shuffle. 4489static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4490 unsigned Depth) { 4491 if (Depth == 6) 4492 return SDValue(); // Limit search depth. 4493 4494 SDValue V = SDValue(N, 0); 4495 EVT VT = V.getValueType(); 4496 unsigned Opcode = V.getOpcode(); 4497 4498 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4499 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4500 Index = SV->getMaskElt(Index); 4501 4502 if (Index < 0) 4503 return DAG.getUNDEF(VT.getVectorElementType()); 4504 4505 int NumElems = VT.getVectorNumElements(); 4506 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4507 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4508 } 4509 4510 // Recurse into target specific vector shuffles to find scalars. 4511 if (isTargetShuffle(Opcode)) { 4512 int NumElems = VT.getVectorNumElements(); 4513 SmallVector<unsigned, 16> ShuffleMask; 4514 SDValue ImmN; 4515 4516 switch(Opcode) { 4517 case X86ISD::SHUFPS: 4518 case X86ISD::SHUFPD: 4519 ImmN = N->getOperand(N->getNumOperands()-1); 4520 DecodeSHUFPSMask(NumElems, 4521 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4522 ShuffleMask); 4523 break; 4524 case X86ISD::PUNPCKHBW: 4525 case X86ISD::PUNPCKHWD: 4526 case X86ISD::PUNPCKHDQ: 4527 case X86ISD::PUNPCKHQDQ: 4528 DecodePUNPCKHMask(NumElems, ShuffleMask); 4529 break; 4530 case X86ISD::UNPCKHPS: 4531 case X86ISD::UNPCKHPD: 4532 case X86ISD::VUNPCKHPSY: 4533 case X86ISD::VUNPCKHPDY: 4534 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4535 break; 4536 case X86ISD::PUNPCKLBW: 4537 case X86ISD::PUNPCKLWD: 4538 case X86ISD::PUNPCKLDQ: 4539 case X86ISD::PUNPCKLQDQ: 4540 DecodePUNPCKLMask(VT, ShuffleMask); 4541 break; 4542 case X86ISD::UNPCKLPS: 4543 case X86ISD::UNPCKLPD: 4544 case X86ISD::VUNPCKLPSY: 4545 case X86ISD::VUNPCKLPDY: 4546 DecodeUNPCKLPMask(VT, ShuffleMask); 4547 break; 4548 case X86ISD::MOVHLPS: 4549 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4550 break; 4551 case X86ISD::MOVLHPS: 4552 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4553 break; 4554 case X86ISD::PSHUFD: 4555 ImmN = N->getOperand(N->getNumOperands()-1); 4556 DecodePSHUFMask(NumElems, 4557 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4558 ShuffleMask); 4559 break; 4560 case X86ISD::PSHUFHW: 4561 ImmN = N->getOperand(N->getNumOperands()-1); 4562 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4563 ShuffleMask); 4564 break; 4565 case X86ISD::PSHUFLW: 4566 ImmN = N->getOperand(N->getNumOperands()-1); 4567 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4568 ShuffleMask); 4569 break; 4570 case X86ISD::MOVSS: 4571 case X86ISD::MOVSD: { 4572 // The index 0 always comes from the first element of the second source, 4573 // this is why MOVSS and MOVSD are used in the first place. The other 4574 // elements come from the other positions of the first source vector. 4575 unsigned OpNum = (Index == 0) ? 1 : 0; 4576 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4577 Depth+1); 4578 } 4579 case X86ISD::VPERMILPS: 4580 ImmN = N->getOperand(N->getNumOperands()-1); 4581 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4582 ShuffleMask); 4583 break; 4584 case X86ISD::VPERMILPSY: 4585 ImmN = N->getOperand(N->getNumOperands()-1); 4586 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4587 ShuffleMask); 4588 break; 4589 case X86ISD::VPERMILPD: 4590 ImmN = N->getOperand(N->getNumOperands()-1); 4591 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4592 ShuffleMask); 4593 break; 4594 case X86ISD::VPERMILPDY: 4595 ImmN = N->getOperand(N->getNumOperands()-1); 4596 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4597 ShuffleMask); 4598 break; 4599 case X86ISD::VPERM2F128: 4600 ImmN = N->getOperand(N->getNumOperands()-1); 4601 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4602 ShuffleMask); 4603 break; 4604 default: 4605 assert("not implemented for target shuffle node"); 4606 return SDValue(); 4607 } 4608 4609 Index = ShuffleMask[Index]; 4610 if (Index < 0) 4611 return DAG.getUNDEF(VT.getVectorElementType()); 4612 4613 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4614 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4615 Depth+1); 4616 } 4617 4618 // Actual nodes that may contain scalar elements 4619 if (Opcode == ISD::BITCAST) { 4620 V = V.getOperand(0); 4621 EVT SrcVT = V.getValueType(); 4622 unsigned NumElems = VT.getVectorNumElements(); 4623 4624 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4625 return SDValue(); 4626 } 4627 4628 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4629 return (Index == 0) ? V.getOperand(0) 4630 : DAG.getUNDEF(VT.getVectorElementType()); 4631 4632 if (V.getOpcode() == ISD::BUILD_VECTOR) 4633 return V.getOperand(Index); 4634 4635 return SDValue(); 4636} 4637 4638/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4639/// shuffle operation which come from a consecutively from a zero. The 4640/// search can start in two different directions, from left or right. 4641static 4642unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4643 bool ZerosFromLeft, SelectionDAG &DAG) { 4644 int i = 0; 4645 4646 while (i < NumElems) { 4647 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4648 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4649 if (!(Elt.getNode() && 4650 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4651 break; 4652 ++i; 4653 } 4654 4655 return i; 4656} 4657 4658/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4659/// MaskE correspond consecutively to elements from one of the vector operands, 4660/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4661static 4662bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4663 int OpIdx, int NumElems, unsigned &OpNum) { 4664 bool SeenV1 = false; 4665 bool SeenV2 = false; 4666 4667 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4668 int Idx = SVOp->getMaskElt(i); 4669 // Ignore undef indicies 4670 if (Idx < 0) 4671 continue; 4672 4673 if (Idx < NumElems) 4674 SeenV1 = true; 4675 else 4676 SeenV2 = true; 4677 4678 // Only accept consecutive elements from the same vector 4679 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4680 return false; 4681 } 4682 4683 OpNum = SeenV1 ? 0 : 1; 4684 return true; 4685} 4686 4687/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4688/// logical left shift of a vector. 4689static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4690 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4691 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4692 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4693 false /* check zeros from right */, DAG); 4694 unsigned OpSrc; 4695 4696 if (!NumZeros) 4697 return false; 4698 4699 // Considering the elements in the mask that are not consecutive zeros, 4700 // check if they consecutively come from only one of the source vectors. 4701 // 4702 // V1 = {X, A, B, C} 0 4703 // \ \ \ / 4704 // vector_shuffle V1, V2 <1, 2, 3, X> 4705 // 4706 if (!isShuffleMaskConsecutive(SVOp, 4707 0, // Mask Start Index 4708 NumElems-NumZeros-1, // Mask End Index 4709 NumZeros, // Where to start looking in the src vector 4710 NumElems, // Number of elements in vector 4711 OpSrc)) // Which source operand ? 4712 return false; 4713 4714 isLeft = false; 4715 ShAmt = NumZeros; 4716 ShVal = SVOp->getOperand(OpSrc); 4717 return true; 4718} 4719 4720/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4721/// logical left shift of a vector. 4722static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4723 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4724 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4725 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4726 true /* check zeros from left */, DAG); 4727 unsigned OpSrc; 4728 4729 if (!NumZeros) 4730 return false; 4731 4732 // Considering the elements in the mask that are not consecutive zeros, 4733 // check if they consecutively come from only one of the source vectors. 4734 // 4735 // 0 { A, B, X, X } = V2 4736 // / \ / / 4737 // vector_shuffle V1, V2 <X, X, 4, 5> 4738 // 4739 if (!isShuffleMaskConsecutive(SVOp, 4740 NumZeros, // Mask Start Index 4741 NumElems-1, // Mask End Index 4742 0, // Where to start looking in the src vector 4743 NumElems, // Number of elements in vector 4744 OpSrc)) // Which source operand ? 4745 return false; 4746 4747 isLeft = true; 4748 ShAmt = NumZeros; 4749 ShVal = SVOp->getOperand(OpSrc); 4750 return true; 4751} 4752 4753/// isVectorShift - Returns true if the shuffle can be implemented as a 4754/// logical left or right shift of a vector. 4755static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4756 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4757 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4758 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4759 return true; 4760 4761 return false; 4762} 4763 4764/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4765/// 4766static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4767 unsigned NumNonZero, unsigned NumZero, 4768 SelectionDAG &DAG, 4769 const TargetLowering &TLI) { 4770 if (NumNonZero > 8) 4771 return SDValue(); 4772 4773 DebugLoc dl = Op.getDebugLoc(); 4774 SDValue V(0, 0); 4775 bool First = true; 4776 for (unsigned i = 0; i < 16; ++i) { 4777 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4778 if (ThisIsNonZero && First) { 4779 if (NumZero) 4780 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4781 else 4782 V = DAG.getUNDEF(MVT::v8i16); 4783 First = false; 4784 } 4785 4786 if ((i & 1) != 0) { 4787 SDValue ThisElt(0, 0), LastElt(0, 0); 4788 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4789 if (LastIsNonZero) { 4790 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4791 MVT::i16, Op.getOperand(i-1)); 4792 } 4793 if (ThisIsNonZero) { 4794 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4795 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4796 ThisElt, DAG.getConstant(8, MVT::i8)); 4797 if (LastIsNonZero) 4798 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4799 } else 4800 ThisElt = LastElt; 4801 4802 if (ThisElt.getNode()) 4803 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4804 DAG.getIntPtrConstant(i/2)); 4805 } 4806 } 4807 4808 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4809} 4810 4811/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4812/// 4813static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4814 unsigned NumNonZero, unsigned NumZero, 4815 SelectionDAG &DAG, 4816 const TargetLowering &TLI) { 4817 if (NumNonZero > 4) 4818 return SDValue(); 4819 4820 DebugLoc dl = Op.getDebugLoc(); 4821 SDValue V(0, 0); 4822 bool First = true; 4823 for (unsigned i = 0; i < 8; ++i) { 4824 bool isNonZero = (NonZeros & (1 << i)) != 0; 4825 if (isNonZero) { 4826 if (First) { 4827 if (NumZero) 4828 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4829 else 4830 V = DAG.getUNDEF(MVT::v8i16); 4831 First = false; 4832 } 4833 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4834 MVT::v8i16, V, Op.getOperand(i), 4835 DAG.getIntPtrConstant(i)); 4836 } 4837 } 4838 4839 return V; 4840} 4841 4842/// getVShift - Return a vector logical shift node. 4843/// 4844static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4845 unsigned NumBits, SelectionDAG &DAG, 4846 const TargetLowering &TLI, DebugLoc dl) { 4847 EVT ShVT = MVT::v2i64; 4848 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4849 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4850 return DAG.getNode(ISD::BITCAST, dl, VT, 4851 DAG.getNode(Opc, dl, ShVT, SrcOp, 4852 DAG.getConstant(NumBits, 4853 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4854} 4855 4856SDValue 4857X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4858 SelectionDAG &DAG) const { 4859 4860 // Check if the scalar load can be widened into a vector load. And if 4861 // the address is "base + cst" see if the cst can be "absorbed" into 4862 // the shuffle mask. 4863 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4864 SDValue Ptr = LD->getBasePtr(); 4865 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4866 return SDValue(); 4867 EVT PVT = LD->getValueType(0); 4868 if (PVT != MVT::i32 && PVT != MVT::f32) 4869 return SDValue(); 4870 4871 int FI = -1; 4872 int64_t Offset = 0; 4873 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4874 FI = FINode->getIndex(); 4875 Offset = 0; 4876 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4877 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4878 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4879 Offset = Ptr.getConstantOperandVal(1); 4880 Ptr = Ptr.getOperand(0); 4881 } else { 4882 return SDValue(); 4883 } 4884 4885 // FIXME: 256-bit vector instructions don't require a strict alignment, 4886 // improve this code to support it better. 4887 unsigned RequiredAlign = VT.getSizeInBits()/8; 4888 SDValue Chain = LD->getChain(); 4889 // Make sure the stack object alignment is at least 16 or 32. 4890 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4891 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4892 if (MFI->isFixedObjectIndex(FI)) { 4893 // Can't change the alignment. FIXME: It's possible to compute 4894 // the exact stack offset and reference FI + adjust offset instead. 4895 // If someone *really* cares about this. That's the way to implement it. 4896 return SDValue(); 4897 } else { 4898 MFI->setObjectAlignment(FI, RequiredAlign); 4899 } 4900 } 4901 4902 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4903 // Ptr + (Offset & ~15). 4904 if (Offset < 0) 4905 return SDValue(); 4906 if ((Offset % RequiredAlign) & 3) 4907 return SDValue(); 4908 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4909 if (StartOffset) 4910 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4911 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4912 4913 int EltNo = (Offset - StartOffset) >> 2; 4914 int NumElems = VT.getVectorNumElements(); 4915 4916 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4917 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4918 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4919 LD->getPointerInfo().getWithOffset(StartOffset), 4920 false, false, 0); 4921 4922 // Canonicalize it to a v4i32 or v8i32 shuffle. 4923 SmallVector<int, 8> Mask; 4924 for (int i = 0; i < NumElems; ++i) 4925 Mask.push_back(EltNo); 4926 4927 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4928 return DAG.getNode(ISD::BITCAST, dl, NVT, 4929 DAG.getVectorShuffle(CanonVT, dl, V1, 4930 DAG.getUNDEF(CanonVT),&Mask[0])); 4931 } 4932 4933 return SDValue(); 4934} 4935 4936/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4937/// vector of type 'VT', see if the elements can be replaced by a single large 4938/// load which has the same value as a build_vector whose operands are 'elts'. 4939/// 4940/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4941/// 4942/// FIXME: we'd also like to handle the case where the last elements are zero 4943/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4944/// There's even a handy isZeroNode for that purpose. 4945static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4946 DebugLoc &DL, SelectionDAG &DAG) { 4947 EVT EltVT = VT.getVectorElementType(); 4948 unsigned NumElems = Elts.size(); 4949 4950 LoadSDNode *LDBase = NULL; 4951 unsigned LastLoadedElt = -1U; 4952 4953 // For each element in the initializer, see if we've found a load or an undef. 4954 // If we don't find an initial load element, or later load elements are 4955 // non-consecutive, bail out. 4956 for (unsigned i = 0; i < NumElems; ++i) { 4957 SDValue Elt = Elts[i]; 4958 4959 if (!Elt.getNode() || 4960 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4961 return SDValue(); 4962 if (!LDBase) { 4963 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4964 return SDValue(); 4965 LDBase = cast<LoadSDNode>(Elt.getNode()); 4966 LastLoadedElt = i; 4967 continue; 4968 } 4969 if (Elt.getOpcode() == ISD::UNDEF) 4970 continue; 4971 4972 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4973 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4974 return SDValue(); 4975 LastLoadedElt = i; 4976 } 4977 4978 // If we have found an entire vector of loads and undefs, then return a large 4979 // load of the entire vector width starting at the base pointer. If we found 4980 // consecutive loads for the low half, generate a vzext_load node. 4981 if (LastLoadedElt == NumElems - 1) { 4982 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4983 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4984 LDBase->getPointerInfo(), 4985 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4986 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4987 LDBase->getPointerInfo(), 4988 LDBase->isVolatile(), LDBase->isNonTemporal(), 4989 LDBase->getAlignment()); 4990 } else if (NumElems == 4 && LastLoadedElt == 1 && 4991 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4992 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4993 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4994 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, 4995 Ops, 2, MVT::i32, 4996 LDBase->getMemOperand()); 4997 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4998 } 4999 return SDValue(); 5000} 5001 5002SDValue 5003X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5004 DebugLoc dl = Op.getDebugLoc(); 5005 5006 EVT VT = Op.getValueType(); 5007 EVT ExtVT = VT.getVectorElementType(); 5008 unsigned NumElems = Op.getNumOperands(); 5009 5010 // Vectors containing all zeros can be matched by pxor and xorps later 5011 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5012 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5013 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5014 if (Op.getValueType() == MVT::v4i32 || 5015 Op.getValueType() == MVT::v8i32) 5016 return Op; 5017 5018 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 5019 } 5020 5021 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5022 // vectors or broken into v4i32 operations on 256-bit vectors. 5023 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5024 if (Op.getValueType() == MVT::v4i32) 5025 return Op; 5026 5027 return getOnesVector(Op.getValueType(), DAG, dl); 5028 } 5029 5030 unsigned EVTBits = ExtVT.getSizeInBits(); 5031 5032 unsigned NumZero = 0; 5033 unsigned NumNonZero = 0; 5034 unsigned NonZeros = 0; 5035 bool IsAllConstants = true; 5036 SmallSet<SDValue, 8> Values; 5037 for (unsigned i = 0; i < NumElems; ++i) { 5038 SDValue Elt = Op.getOperand(i); 5039 if (Elt.getOpcode() == ISD::UNDEF) 5040 continue; 5041 Values.insert(Elt); 5042 if (Elt.getOpcode() != ISD::Constant && 5043 Elt.getOpcode() != ISD::ConstantFP) 5044 IsAllConstants = false; 5045 if (X86::isZeroNode(Elt)) 5046 NumZero++; 5047 else { 5048 NonZeros |= (1 << i); 5049 NumNonZero++; 5050 } 5051 } 5052 5053 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5054 if (NumNonZero == 0) 5055 return DAG.getUNDEF(VT); 5056 5057 // Special case for single non-zero, non-undef, element. 5058 if (NumNonZero == 1) { 5059 unsigned Idx = CountTrailingZeros_32(NonZeros); 5060 SDValue Item = Op.getOperand(Idx); 5061 5062 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5063 // the value are obviously zero, truncate the value to i32 and do the 5064 // insertion that way. Only do this if the value is non-constant or if the 5065 // value is a constant being inserted into element 0. It is cheaper to do 5066 // a constant pool load than it is to do a movd + shuffle. 5067 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5068 (!IsAllConstants || Idx == 0)) { 5069 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5070 // Handle SSE only. 5071 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5072 EVT VecVT = MVT::v4i32; 5073 unsigned VecElts = 4; 5074 5075 // Truncate the value (which may itself be a constant) to i32, and 5076 // convert it to a vector with movd (S2V+shuffle to zero extend). 5077 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5078 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5079 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5080 Subtarget->hasSSE2(), DAG); 5081 5082 // Now we have our 32-bit value zero extended in the low element of 5083 // a vector. If Idx != 0, swizzle it into place. 5084 if (Idx != 0) { 5085 SmallVector<int, 4> Mask; 5086 Mask.push_back(Idx); 5087 for (unsigned i = 1; i != VecElts; ++i) 5088 Mask.push_back(i); 5089 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5090 DAG.getUNDEF(Item.getValueType()), 5091 &Mask[0]); 5092 } 5093 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5094 } 5095 } 5096 5097 // If we have a constant or non-constant insertion into the low element of 5098 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5099 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5100 // depending on what the source datatype is. 5101 if (Idx == 0) { 5102 if (NumZero == 0) { 5103 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5104 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5105 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5106 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5107 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5108 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 5109 DAG); 5110 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5111 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5112 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5113 EVT MiddleVT = MVT::v4i32; 5114 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 5115 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5116 Subtarget->hasSSE2(), DAG); 5117 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5118 } 5119 } 5120 5121 // Is it a vector logical left shift? 5122 if (NumElems == 2 && Idx == 1 && 5123 X86::isZeroNode(Op.getOperand(0)) && 5124 !X86::isZeroNode(Op.getOperand(1))) { 5125 unsigned NumBits = VT.getSizeInBits(); 5126 return getVShift(true, VT, 5127 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5128 VT, Op.getOperand(1)), 5129 NumBits/2, DAG, *this, dl); 5130 } 5131 5132 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5133 return SDValue(); 5134 5135 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5136 // is a non-constant being inserted into an element other than the low one, 5137 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5138 // movd/movss) to move this into the low element, then shuffle it into 5139 // place. 5140 if (EVTBits == 32) { 5141 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5142 5143 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5144 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5145 Subtarget->hasSSE2(), DAG); 5146 SmallVector<int, 8> MaskVec; 5147 for (unsigned i = 0; i < NumElems; i++) 5148 MaskVec.push_back(i == Idx ? 0 : 1); 5149 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5150 } 5151 } 5152 5153 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5154 if (Values.size() == 1) { 5155 if (EVTBits == 32) { 5156 // Instead of a shuffle like this: 5157 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5158 // Check if it's possible to issue this instead. 5159 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5160 unsigned Idx = CountTrailingZeros_32(NonZeros); 5161 SDValue Item = Op.getOperand(Idx); 5162 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5163 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5164 } 5165 return SDValue(); 5166 } 5167 5168 // A vector full of immediates; various special cases are already 5169 // handled, so this is best done with a single constant-pool load. 5170 if (IsAllConstants) 5171 return SDValue(); 5172 5173 // For AVX-length vectors, build the individual 128-bit pieces and use 5174 // shuffles to put them in place. 5175 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5176 SmallVector<SDValue, 32> V; 5177 for (unsigned i = 0; i < NumElems; ++i) 5178 V.push_back(Op.getOperand(i)); 5179 5180 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5181 5182 // Build both the lower and upper subvector. 5183 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5184 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5185 NumElems/2); 5186 5187 // Recreate the wider vector with the lower and upper part. 5188 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5189 DAG.getConstant(0, MVT::i32), DAG, dl); 5190 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5191 DAG, dl); 5192 } 5193 5194 // Let legalizer expand 2-wide build_vectors. 5195 if (EVTBits == 64) { 5196 if (NumNonZero == 1) { 5197 // One half is zero or undef. 5198 unsigned Idx = CountTrailingZeros_32(NonZeros); 5199 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5200 Op.getOperand(Idx)); 5201 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5202 Subtarget->hasSSE2(), DAG); 5203 } 5204 return SDValue(); 5205 } 5206 5207 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5208 if (EVTBits == 8 && NumElems == 16) { 5209 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5210 *this); 5211 if (V.getNode()) return V; 5212 } 5213 5214 if (EVTBits == 16 && NumElems == 8) { 5215 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5216 *this); 5217 if (V.getNode()) return V; 5218 } 5219 5220 // If element VT is == 32 bits, turn it into a number of shuffles. 5221 SmallVector<SDValue, 8> V; 5222 V.resize(NumElems); 5223 if (NumElems == 4 && NumZero > 0) { 5224 for (unsigned i = 0; i < 4; ++i) { 5225 bool isZero = !(NonZeros & (1 << i)); 5226 if (isZero) 5227 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5228 else 5229 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5230 } 5231 5232 for (unsigned i = 0; i < 2; ++i) { 5233 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5234 default: break; 5235 case 0: 5236 V[i] = V[i*2]; // Must be a zero vector. 5237 break; 5238 case 1: 5239 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5240 break; 5241 case 2: 5242 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5243 break; 5244 case 3: 5245 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5246 break; 5247 } 5248 } 5249 5250 SmallVector<int, 8> MaskVec; 5251 bool Reverse = (NonZeros & 0x3) == 2; 5252 for (unsigned i = 0; i < 2; ++i) 5253 MaskVec.push_back(Reverse ? 1-i : i); 5254 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5255 for (unsigned i = 0; i < 2; ++i) 5256 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5257 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5258 } 5259 5260 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5261 // Check for a build vector of consecutive loads. 5262 for (unsigned i = 0; i < NumElems; ++i) 5263 V[i] = Op.getOperand(i); 5264 5265 // Check for elements which are consecutive loads. 5266 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5267 if (LD.getNode()) 5268 return LD; 5269 5270 // For SSE 4.1, use insertps to put the high elements into the low element. 5271 if (getSubtarget()->hasSSE41()) { 5272 SDValue Result; 5273 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5274 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5275 else 5276 Result = DAG.getUNDEF(VT); 5277 5278 for (unsigned i = 1; i < NumElems; ++i) { 5279 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5280 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5281 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5282 } 5283 return Result; 5284 } 5285 5286 // Otherwise, expand into a number of unpckl*, start by extending each of 5287 // our (non-undef) elements to the full vector width with the element in the 5288 // bottom slot of the vector (which generates no code for SSE). 5289 for (unsigned i = 0; i < NumElems; ++i) { 5290 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5291 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5292 else 5293 V[i] = DAG.getUNDEF(VT); 5294 } 5295 5296 // Next, we iteratively mix elements, e.g. for v4f32: 5297 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5298 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5299 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5300 unsigned EltStride = NumElems >> 1; 5301 while (EltStride != 0) { 5302 for (unsigned i = 0; i < EltStride; ++i) { 5303 // If V[i+EltStride] is undef and this is the first round of mixing, 5304 // then it is safe to just drop this shuffle: V[i] is already in the 5305 // right place, the one element (since it's the first round) being 5306 // inserted as undef can be dropped. This isn't safe for successive 5307 // rounds because they will permute elements within both vectors. 5308 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5309 EltStride == NumElems/2) 5310 continue; 5311 5312 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5313 } 5314 EltStride >>= 1; 5315 } 5316 return V[0]; 5317 } 5318 return SDValue(); 5319} 5320 5321// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5322// them in a MMX register. This is better than doing a stack convert. 5323static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5324 DebugLoc dl = Op.getDebugLoc(); 5325 EVT ResVT = Op.getValueType(); 5326 5327 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5328 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5329 int Mask[2]; 5330 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5331 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5332 InVec = Op.getOperand(1); 5333 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5334 unsigned NumElts = ResVT.getVectorNumElements(); 5335 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5336 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5337 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5338 } else { 5339 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5340 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5341 Mask[0] = 0; Mask[1] = 2; 5342 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5343 } 5344 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5345} 5346 5347// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5348// to create 256-bit vectors from two other 128-bit ones. 5349static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5350 DebugLoc dl = Op.getDebugLoc(); 5351 EVT ResVT = Op.getValueType(); 5352 5353 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5354 5355 SDValue V1 = Op.getOperand(0); 5356 SDValue V2 = Op.getOperand(1); 5357 unsigned NumElems = ResVT.getVectorNumElements(); 5358 5359 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5360 DAG.getConstant(0, MVT::i32), DAG, dl); 5361 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5362 DAG, dl); 5363} 5364 5365SDValue 5366X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5367 EVT ResVT = Op.getValueType(); 5368 5369 assert(Op.getNumOperands() == 2); 5370 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5371 "Unsupported CONCAT_VECTORS for value type"); 5372 5373 // We support concatenate two MMX registers and place them in a MMX register. 5374 // This is better than doing a stack convert. 5375 if (ResVT.is128BitVector()) 5376 return LowerMMXCONCAT_VECTORS(Op, DAG); 5377 5378 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5379 // from two other 128-bit ones. 5380 return LowerAVXCONCAT_VECTORS(Op, DAG); 5381} 5382 5383// v8i16 shuffles - Prefer shuffles in the following order: 5384// 1. [all] pshuflw, pshufhw, optional move 5385// 2. [ssse3] 1 x pshufb 5386// 3. [ssse3] 2 x pshufb + 1 x por 5387// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5388SDValue 5389X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5390 SelectionDAG &DAG) const { 5391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5392 SDValue V1 = SVOp->getOperand(0); 5393 SDValue V2 = SVOp->getOperand(1); 5394 DebugLoc dl = SVOp->getDebugLoc(); 5395 SmallVector<int, 8> MaskVals; 5396 5397 // Determine if more than 1 of the words in each of the low and high quadwords 5398 // of the result come from the same quadword of one of the two inputs. Undef 5399 // mask values count as coming from any quadword, for better codegen. 5400 SmallVector<unsigned, 4> LoQuad(4); 5401 SmallVector<unsigned, 4> HiQuad(4); 5402 BitVector InputQuads(4); 5403 for (unsigned i = 0; i < 8; ++i) { 5404 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 5405 int EltIdx = SVOp->getMaskElt(i); 5406 MaskVals.push_back(EltIdx); 5407 if (EltIdx < 0) { 5408 ++Quad[0]; 5409 ++Quad[1]; 5410 ++Quad[2]; 5411 ++Quad[3]; 5412 continue; 5413 } 5414 ++Quad[EltIdx / 4]; 5415 InputQuads.set(EltIdx / 4); 5416 } 5417 5418 int BestLoQuad = -1; 5419 unsigned MaxQuad = 1; 5420 for (unsigned i = 0; i < 4; ++i) { 5421 if (LoQuad[i] > MaxQuad) { 5422 BestLoQuad = i; 5423 MaxQuad = LoQuad[i]; 5424 } 5425 } 5426 5427 int BestHiQuad = -1; 5428 MaxQuad = 1; 5429 for (unsigned i = 0; i < 4; ++i) { 5430 if (HiQuad[i] > MaxQuad) { 5431 BestHiQuad = i; 5432 MaxQuad = HiQuad[i]; 5433 } 5434 } 5435 5436 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5437 // of the two input vectors, shuffle them into one input vector so only a 5438 // single pshufb instruction is necessary. If There are more than 2 input 5439 // quads, disable the next transformation since it does not help SSSE3. 5440 bool V1Used = InputQuads[0] || InputQuads[1]; 5441 bool V2Used = InputQuads[2] || InputQuads[3]; 5442 if (Subtarget->hasSSSE3()) { 5443 if (InputQuads.count() == 2 && V1Used && V2Used) { 5444 BestLoQuad = InputQuads.find_first(); 5445 BestHiQuad = InputQuads.find_next(BestLoQuad); 5446 } 5447 if (InputQuads.count() > 2) { 5448 BestLoQuad = -1; 5449 BestHiQuad = -1; 5450 } 5451 } 5452 5453 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5454 // the shuffle mask. If a quad is scored as -1, that means that it contains 5455 // words from all 4 input quadwords. 5456 SDValue NewV; 5457 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5458 SmallVector<int, 8> MaskV; 5459 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5460 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5461 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5462 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5463 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5464 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5465 5466 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5467 // source words for the shuffle, to aid later transformations. 5468 bool AllWordsInNewV = true; 5469 bool InOrder[2] = { true, true }; 5470 for (unsigned i = 0; i != 8; ++i) { 5471 int idx = MaskVals[i]; 5472 if (idx != (int)i) 5473 InOrder[i/4] = false; 5474 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5475 continue; 5476 AllWordsInNewV = false; 5477 break; 5478 } 5479 5480 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5481 if (AllWordsInNewV) { 5482 for (int i = 0; i != 8; ++i) { 5483 int idx = MaskVals[i]; 5484 if (idx < 0) 5485 continue; 5486 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5487 if ((idx != i) && idx < 4) 5488 pshufhw = false; 5489 if ((idx != i) && idx > 3) 5490 pshuflw = false; 5491 } 5492 V1 = NewV; 5493 V2Used = false; 5494 BestLoQuad = 0; 5495 BestHiQuad = 1; 5496 } 5497 5498 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5499 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5500 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5501 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5502 unsigned TargetMask = 0; 5503 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5504 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5505 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5506 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5507 V1 = NewV.getOperand(0); 5508 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5509 } 5510 } 5511 5512 // If we have SSSE3, and all words of the result are from 1 input vector, 5513 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5514 // is present, fall back to case 4. 5515 if (Subtarget->hasSSSE3()) { 5516 SmallVector<SDValue,16> pshufbMask; 5517 5518 // If we have elements from both input vectors, set the high bit of the 5519 // shuffle mask element to zero out elements that come from V2 in the V1 5520 // mask, and elements that come from V1 in the V2 mask, so that the two 5521 // results can be OR'd together. 5522 bool TwoInputs = V1Used && V2Used; 5523 for (unsigned i = 0; i != 8; ++i) { 5524 int EltIdx = MaskVals[i] * 2; 5525 if (TwoInputs && (EltIdx >= 16)) { 5526 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5527 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5528 continue; 5529 } 5530 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5531 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5532 } 5533 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5534 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5535 DAG.getNode(ISD::BUILD_VECTOR, dl, 5536 MVT::v16i8, &pshufbMask[0], 16)); 5537 if (!TwoInputs) 5538 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5539 5540 // Calculate the shuffle mask for the second input, shuffle it, and 5541 // OR it with the first shuffled input. 5542 pshufbMask.clear(); 5543 for (unsigned i = 0; i != 8; ++i) { 5544 int EltIdx = MaskVals[i] * 2; 5545 if (EltIdx < 16) { 5546 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5547 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5548 continue; 5549 } 5550 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5551 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5552 } 5553 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5554 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5555 DAG.getNode(ISD::BUILD_VECTOR, dl, 5556 MVT::v16i8, &pshufbMask[0], 16)); 5557 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5558 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5559 } 5560 5561 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5562 // and update MaskVals with new element order. 5563 BitVector InOrder(8); 5564 if (BestLoQuad >= 0) { 5565 SmallVector<int, 8> MaskV; 5566 for (int i = 0; i != 4; ++i) { 5567 int idx = MaskVals[i]; 5568 if (idx < 0) { 5569 MaskV.push_back(-1); 5570 InOrder.set(i); 5571 } else if ((idx / 4) == BestLoQuad) { 5572 MaskV.push_back(idx & 3); 5573 InOrder.set(i); 5574 } else { 5575 MaskV.push_back(-1); 5576 } 5577 } 5578 for (unsigned i = 4; i != 8; ++i) 5579 MaskV.push_back(i); 5580 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5581 &MaskV[0]); 5582 5583 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5584 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5585 NewV.getOperand(0), 5586 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5587 DAG); 5588 } 5589 5590 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5591 // and update MaskVals with the new element order. 5592 if (BestHiQuad >= 0) { 5593 SmallVector<int, 8> MaskV; 5594 for (unsigned i = 0; i != 4; ++i) 5595 MaskV.push_back(i); 5596 for (unsigned i = 4; i != 8; ++i) { 5597 int idx = MaskVals[i]; 5598 if (idx < 0) { 5599 MaskV.push_back(-1); 5600 InOrder.set(i); 5601 } else if ((idx / 4) == BestHiQuad) { 5602 MaskV.push_back((idx & 3) + 4); 5603 InOrder.set(i); 5604 } else { 5605 MaskV.push_back(-1); 5606 } 5607 } 5608 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5609 &MaskV[0]); 5610 5611 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5612 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5613 NewV.getOperand(0), 5614 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5615 DAG); 5616 } 5617 5618 // In case BestHi & BestLo were both -1, which means each quadword has a word 5619 // from each of the four input quadwords, calculate the InOrder bitvector now 5620 // before falling through to the insert/extract cleanup. 5621 if (BestLoQuad == -1 && BestHiQuad == -1) { 5622 NewV = V1; 5623 for (int i = 0; i != 8; ++i) 5624 if (MaskVals[i] < 0 || MaskVals[i] == i) 5625 InOrder.set(i); 5626 } 5627 5628 // The other elements are put in the right place using pextrw and pinsrw. 5629 for (unsigned i = 0; i != 8; ++i) { 5630 if (InOrder[i]) 5631 continue; 5632 int EltIdx = MaskVals[i]; 5633 if (EltIdx < 0) 5634 continue; 5635 SDValue ExtOp = (EltIdx < 8) 5636 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5637 DAG.getIntPtrConstant(EltIdx)) 5638 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5639 DAG.getIntPtrConstant(EltIdx - 8)); 5640 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5641 DAG.getIntPtrConstant(i)); 5642 } 5643 return NewV; 5644} 5645 5646// v16i8 shuffles - Prefer shuffles in the following order: 5647// 1. [ssse3] 1 x pshufb 5648// 2. [ssse3] 2 x pshufb + 1 x por 5649// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5650static 5651SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5652 SelectionDAG &DAG, 5653 const X86TargetLowering &TLI) { 5654 SDValue V1 = SVOp->getOperand(0); 5655 SDValue V2 = SVOp->getOperand(1); 5656 DebugLoc dl = SVOp->getDebugLoc(); 5657 SmallVector<int, 16> MaskVals; 5658 SVOp->getMask(MaskVals); 5659 5660 // If we have SSSE3, case 1 is generated when all result bytes come from 5661 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5662 // present, fall back to case 3. 5663 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5664 bool V1Only = true; 5665 bool V2Only = true; 5666 for (unsigned i = 0; i < 16; ++i) { 5667 int EltIdx = MaskVals[i]; 5668 if (EltIdx < 0) 5669 continue; 5670 if (EltIdx < 16) 5671 V2Only = false; 5672 else 5673 V1Only = false; 5674 } 5675 5676 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5677 if (TLI.getSubtarget()->hasSSSE3()) { 5678 SmallVector<SDValue,16> pshufbMask; 5679 5680 // If all result elements are from one input vector, then only translate 5681 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5682 // 5683 // Otherwise, we have elements from both input vectors, and must zero out 5684 // elements that come from V2 in the first mask, and V1 in the second mask 5685 // so that we can OR them together. 5686 bool TwoInputs = !(V1Only || V2Only); 5687 for (unsigned i = 0; i != 16; ++i) { 5688 int EltIdx = MaskVals[i]; 5689 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5690 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5691 continue; 5692 } 5693 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5694 } 5695 // If all the elements are from V2, assign it to V1 and return after 5696 // building the first pshufb. 5697 if (V2Only) 5698 V1 = V2; 5699 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5700 DAG.getNode(ISD::BUILD_VECTOR, dl, 5701 MVT::v16i8, &pshufbMask[0], 16)); 5702 if (!TwoInputs) 5703 return V1; 5704 5705 // Calculate the shuffle mask for the second input, shuffle it, and 5706 // OR it with the first shuffled input. 5707 pshufbMask.clear(); 5708 for (unsigned i = 0; i != 16; ++i) { 5709 int EltIdx = MaskVals[i]; 5710 if (EltIdx < 16) { 5711 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5712 continue; 5713 } 5714 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5715 } 5716 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5717 DAG.getNode(ISD::BUILD_VECTOR, dl, 5718 MVT::v16i8, &pshufbMask[0], 16)); 5719 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5720 } 5721 5722 // No SSSE3 - Calculate in place words and then fix all out of place words 5723 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5724 // the 16 different words that comprise the two doublequadword input vectors. 5725 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5726 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5727 SDValue NewV = V2Only ? V2 : V1; 5728 for (int i = 0; i != 8; ++i) { 5729 int Elt0 = MaskVals[i*2]; 5730 int Elt1 = MaskVals[i*2+1]; 5731 5732 // This word of the result is all undef, skip it. 5733 if (Elt0 < 0 && Elt1 < 0) 5734 continue; 5735 5736 // This word of the result is already in the correct place, skip it. 5737 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5738 continue; 5739 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5740 continue; 5741 5742 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5743 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5744 SDValue InsElt; 5745 5746 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5747 // using a single extract together, load it and store it. 5748 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5749 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5750 DAG.getIntPtrConstant(Elt1 / 2)); 5751 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5752 DAG.getIntPtrConstant(i)); 5753 continue; 5754 } 5755 5756 // If Elt1 is defined, extract it from the appropriate source. If the 5757 // source byte is not also odd, shift the extracted word left 8 bits 5758 // otherwise clear the bottom 8 bits if we need to do an or. 5759 if (Elt1 >= 0) { 5760 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5761 DAG.getIntPtrConstant(Elt1 / 2)); 5762 if ((Elt1 & 1) == 0) 5763 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5764 DAG.getConstant(8, 5765 TLI.getShiftAmountTy(InsElt.getValueType()))); 5766 else if (Elt0 >= 0) 5767 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5768 DAG.getConstant(0xFF00, MVT::i16)); 5769 } 5770 // If Elt0 is defined, extract it from the appropriate source. If the 5771 // source byte is not also even, shift the extracted word right 8 bits. If 5772 // Elt1 was also defined, OR the extracted values together before 5773 // inserting them in the result. 5774 if (Elt0 >= 0) { 5775 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5776 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5777 if ((Elt0 & 1) != 0) 5778 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5779 DAG.getConstant(8, 5780 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5781 else if (Elt1 >= 0) 5782 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5783 DAG.getConstant(0x00FF, MVT::i16)); 5784 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5785 : InsElt0; 5786 } 5787 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5788 DAG.getIntPtrConstant(i)); 5789 } 5790 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5791} 5792 5793/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5794/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5795/// done when every pair / quad of shuffle mask elements point to elements in 5796/// the right sequence. e.g. 5797/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5798static 5799SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5800 SelectionDAG &DAG, DebugLoc dl) { 5801 EVT VT = SVOp->getValueType(0); 5802 SDValue V1 = SVOp->getOperand(0); 5803 SDValue V2 = SVOp->getOperand(1); 5804 unsigned NumElems = VT.getVectorNumElements(); 5805 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5806 EVT NewVT; 5807 switch (VT.getSimpleVT().SimpleTy) { 5808 default: assert(false && "Unexpected!"); 5809 case MVT::v4f32: NewVT = MVT::v2f64; break; 5810 case MVT::v4i32: NewVT = MVT::v2i64; break; 5811 case MVT::v8i16: NewVT = MVT::v4i32; break; 5812 case MVT::v16i8: NewVT = MVT::v4i32; break; 5813 } 5814 5815 int Scale = NumElems / NewWidth; 5816 SmallVector<int, 8> MaskVec; 5817 for (unsigned i = 0; i < NumElems; i += Scale) { 5818 int StartIdx = -1; 5819 for (int j = 0; j < Scale; ++j) { 5820 int EltIdx = SVOp->getMaskElt(i+j); 5821 if (EltIdx < 0) 5822 continue; 5823 if (StartIdx == -1) 5824 StartIdx = EltIdx - (EltIdx % Scale); 5825 if (EltIdx != StartIdx + j) 5826 return SDValue(); 5827 } 5828 if (StartIdx == -1) 5829 MaskVec.push_back(-1); 5830 else 5831 MaskVec.push_back(StartIdx / Scale); 5832 } 5833 5834 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5835 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5836 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5837} 5838 5839/// getVZextMovL - Return a zero-extending vector move low node. 5840/// 5841static SDValue getVZextMovL(EVT VT, EVT OpVT, 5842 SDValue SrcOp, SelectionDAG &DAG, 5843 const X86Subtarget *Subtarget, DebugLoc dl) { 5844 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5845 LoadSDNode *LD = NULL; 5846 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5847 LD = dyn_cast<LoadSDNode>(SrcOp); 5848 if (!LD) { 5849 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5850 // instead. 5851 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5852 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5853 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5854 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5855 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5856 // PR2108 5857 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5858 return DAG.getNode(ISD::BITCAST, dl, VT, 5859 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5860 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5861 OpVT, 5862 SrcOp.getOperand(0) 5863 .getOperand(0)))); 5864 } 5865 } 5866 } 5867 5868 return DAG.getNode(ISD::BITCAST, dl, VT, 5869 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5870 DAG.getNode(ISD::BITCAST, dl, 5871 OpVT, SrcOp))); 5872} 5873 5874/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5875/// shuffle node referes to only one lane in the sources. 5876static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5877 EVT VT = SVOp->getValueType(0); 5878 int NumElems = VT.getVectorNumElements(); 5879 int HalfSize = NumElems/2; 5880 SmallVector<int, 16> M; 5881 SVOp->getMask(M); 5882 bool MatchA = false, MatchB = false; 5883 5884 for (int l = 0; l < NumElems*2; l += HalfSize) { 5885 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5886 MatchA = true; 5887 break; 5888 } 5889 } 5890 5891 for (int l = 0; l < NumElems*2; l += HalfSize) { 5892 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5893 MatchB = true; 5894 break; 5895 } 5896 } 5897 5898 return MatchA && MatchB; 5899} 5900 5901/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5902/// which could not be matched by any known target speficic shuffle 5903static SDValue 5904LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5905 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5906 // If each half of a vector shuffle node referes to only one lane in the 5907 // source vectors, extract each used 128-bit lane and shuffle them using 5908 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5909 // the work to the legalizer. 5910 DebugLoc dl = SVOp->getDebugLoc(); 5911 EVT VT = SVOp->getValueType(0); 5912 int NumElems = VT.getVectorNumElements(); 5913 int HalfSize = NumElems/2; 5914 5915 // Extract the reference for each half 5916 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5917 int FstVecOpNum = 0, SndVecOpNum = 0; 5918 for (int i = 0; i < HalfSize; ++i) { 5919 int Elt = SVOp->getMaskElt(i); 5920 if (SVOp->getMaskElt(i) < 0) 5921 continue; 5922 FstVecOpNum = Elt/NumElems; 5923 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5924 break; 5925 } 5926 for (int i = HalfSize; i < NumElems; ++i) { 5927 int Elt = SVOp->getMaskElt(i); 5928 if (SVOp->getMaskElt(i) < 0) 5929 continue; 5930 SndVecOpNum = Elt/NumElems; 5931 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5932 break; 5933 } 5934 5935 // Extract the subvectors 5936 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 5937 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 5938 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 5939 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 5940 5941 // Generate 128-bit shuffles 5942 SmallVector<int, 16> MaskV1, MaskV2; 5943 for (int i = 0; i < HalfSize; ++i) { 5944 int Elt = SVOp->getMaskElt(i); 5945 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5946 } 5947 for (int i = HalfSize; i < NumElems; ++i) { 5948 int Elt = SVOp->getMaskElt(i); 5949 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5950 } 5951 5952 EVT NVT = V1.getValueType(); 5953 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 5954 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 5955 5956 // Concatenate the result back 5957 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 5958 DAG.getConstant(0, MVT::i32), DAG, dl); 5959 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5960 DAG, dl); 5961 } 5962 5963 return SDValue(); 5964} 5965 5966/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5967/// 4 elements, and match them with several different shuffle types. 5968static SDValue 5969LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5970 SDValue V1 = SVOp->getOperand(0); 5971 SDValue V2 = SVOp->getOperand(1); 5972 DebugLoc dl = SVOp->getDebugLoc(); 5973 EVT VT = SVOp->getValueType(0); 5974 5975 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5976 5977 SmallVector<std::pair<int, int>, 8> Locs; 5978 Locs.resize(4); 5979 SmallVector<int, 8> Mask1(4U, -1); 5980 SmallVector<int, 8> PermMask; 5981 SVOp->getMask(PermMask); 5982 5983 unsigned NumHi = 0; 5984 unsigned NumLo = 0; 5985 for (unsigned i = 0; i != 4; ++i) { 5986 int Idx = PermMask[i]; 5987 if (Idx < 0) { 5988 Locs[i] = std::make_pair(-1, -1); 5989 } else { 5990 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5991 if (Idx < 4) { 5992 Locs[i] = std::make_pair(0, NumLo); 5993 Mask1[NumLo] = Idx; 5994 NumLo++; 5995 } else { 5996 Locs[i] = std::make_pair(1, NumHi); 5997 if (2+NumHi < 4) 5998 Mask1[2+NumHi] = Idx; 5999 NumHi++; 6000 } 6001 } 6002 } 6003 6004 if (NumLo <= 2 && NumHi <= 2) { 6005 // If no more than two elements come from either vector. This can be 6006 // implemented with two shuffles. First shuffle gather the elements. 6007 // The second shuffle, which takes the first shuffle as both of its 6008 // vector operands, put the elements into the right order. 6009 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6010 6011 SmallVector<int, 8> Mask2(4U, -1); 6012 6013 for (unsigned i = 0; i != 4; ++i) { 6014 if (Locs[i].first == -1) 6015 continue; 6016 else { 6017 unsigned Idx = (i < 2) ? 0 : 4; 6018 Idx += Locs[i].first * 2 + Locs[i].second; 6019 Mask2[i] = Idx; 6020 } 6021 } 6022 6023 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6024 } else if (NumLo == 3 || NumHi == 3) { 6025 // Otherwise, we must have three elements from one vector, call it X, and 6026 // one element from the other, call it Y. First, use a shufps to build an 6027 // intermediate vector with the one element from Y and the element from X 6028 // that will be in the same half in the final destination (the indexes don't 6029 // matter). Then, use a shufps to build the final vector, taking the half 6030 // containing the element from Y from the intermediate, and the other half 6031 // from X. 6032 if (NumHi == 3) { 6033 // Normalize it so the 3 elements come from V1. 6034 CommuteVectorShuffleMask(PermMask, VT); 6035 std::swap(V1, V2); 6036 } 6037 6038 // Find the element from V2. 6039 unsigned HiIndex; 6040 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6041 int Val = PermMask[HiIndex]; 6042 if (Val < 0) 6043 continue; 6044 if (Val >= 4) 6045 break; 6046 } 6047 6048 Mask1[0] = PermMask[HiIndex]; 6049 Mask1[1] = -1; 6050 Mask1[2] = PermMask[HiIndex^1]; 6051 Mask1[3] = -1; 6052 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6053 6054 if (HiIndex >= 2) { 6055 Mask1[0] = PermMask[0]; 6056 Mask1[1] = PermMask[1]; 6057 Mask1[2] = HiIndex & 1 ? 6 : 4; 6058 Mask1[3] = HiIndex & 1 ? 4 : 6; 6059 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6060 } else { 6061 Mask1[0] = HiIndex & 1 ? 2 : 0; 6062 Mask1[1] = HiIndex & 1 ? 0 : 2; 6063 Mask1[2] = PermMask[2]; 6064 Mask1[3] = PermMask[3]; 6065 if (Mask1[2] >= 0) 6066 Mask1[2] += 4; 6067 if (Mask1[3] >= 0) 6068 Mask1[3] += 4; 6069 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6070 } 6071 } 6072 6073 // Break it into (shuffle shuffle_hi, shuffle_lo). 6074 Locs.clear(); 6075 Locs.resize(4); 6076 SmallVector<int,8> LoMask(4U, -1); 6077 SmallVector<int,8> HiMask(4U, -1); 6078 6079 SmallVector<int,8> *MaskPtr = &LoMask; 6080 unsigned MaskIdx = 0; 6081 unsigned LoIdx = 0; 6082 unsigned HiIdx = 2; 6083 for (unsigned i = 0; i != 4; ++i) { 6084 if (i == 2) { 6085 MaskPtr = &HiMask; 6086 MaskIdx = 1; 6087 LoIdx = 0; 6088 HiIdx = 2; 6089 } 6090 int Idx = PermMask[i]; 6091 if (Idx < 0) { 6092 Locs[i] = std::make_pair(-1, -1); 6093 } else if (Idx < 4) { 6094 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6095 (*MaskPtr)[LoIdx] = Idx; 6096 LoIdx++; 6097 } else { 6098 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6099 (*MaskPtr)[HiIdx] = Idx; 6100 HiIdx++; 6101 } 6102 } 6103 6104 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6105 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6106 SmallVector<int, 8> MaskOps; 6107 for (unsigned i = 0; i != 4; ++i) { 6108 if (Locs[i].first == -1) { 6109 MaskOps.push_back(-1); 6110 } else { 6111 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6112 MaskOps.push_back(Idx); 6113 } 6114 } 6115 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6116} 6117 6118static bool MayFoldVectorLoad(SDValue V) { 6119 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6120 V = V.getOperand(0); 6121 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6122 V = V.getOperand(0); 6123 if (MayFoldLoad(V)) 6124 return true; 6125 return false; 6126} 6127 6128// FIXME: the version above should always be used. Since there's 6129// a bug where several vector shuffles can't be folded because the 6130// DAG is not updated during lowering and a node claims to have two 6131// uses while it only has one, use this version, and let isel match 6132// another instruction if the load really happens to have more than 6133// one use. Remove this version after this bug get fixed. 6134// rdar://8434668, PR8156 6135static bool RelaxedMayFoldVectorLoad(SDValue V) { 6136 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6137 V = V.getOperand(0); 6138 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6139 V = V.getOperand(0); 6140 if (ISD::isNormalLoad(V.getNode())) 6141 return true; 6142 return false; 6143} 6144 6145/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6146/// a vector extract, and if both can be later optimized into a single load. 6147/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6148/// here because otherwise a target specific shuffle node is going to be 6149/// emitted for this shuffle, and the optimization not done. 6150/// FIXME: This is probably not the best approach, but fix the problem 6151/// until the right path is decided. 6152static 6153bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6154 const TargetLowering &TLI) { 6155 EVT VT = V.getValueType(); 6156 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6157 6158 // Be sure that the vector shuffle is present in a pattern like this: 6159 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6160 if (!V.hasOneUse()) 6161 return false; 6162 6163 SDNode *N = *V.getNode()->use_begin(); 6164 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6165 return false; 6166 6167 SDValue EltNo = N->getOperand(1); 6168 if (!isa<ConstantSDNode>(EltNo)) 6169 return false; 6170 6171 // If the bit convert changed the number of elements, it is unsafe 6172 // to examine the mask. 6173 bool HasShuffleIntoBitcast = false; 6174 if (V.getOpcode() == ISD::BITCAST) { 6175 EVT SrcVT = V.getOperand(0).getValueType(); 6176 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6177 return false; 6178 V = V.getOperand(0); 6179 HasShuffleIntoBitcast = true; 6180 } 6181 6182 // Select the input vector, guarding against out of range extract vector. 6183 unsigned NumElems = VT.getVectorNumElements(); 6184 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6185 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6186 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6187 6188 // Skip one more bit_convert if necessary 6189 if (V.getOpcode() == ISD::BITCAST) 6190 V = V.getOperand(0); 6191 6192 if (ISD::isNormalLoad(V.getNode())) { 6193 // Is the original load suitable? 6194 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6195 6196 // FIXME: avoid the multi-use bug that is preventing lots of 6197 // of foldings to be detected, this is still wrong of course, but 6198 // give the temporary desired behavior, and if it happens that 6199 // the load has real more uses, during isel it will not fold, and 6200 // will generate poor code. 6201 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 6202 return false; 6203 6204 if (!HasShuffleIntoBitcast) 6205 return true; 6206 6207 // If there's a bitcast before the shuffle, check if the load type and 6208 // alignment is valid. 6209 unsigned Align = LN0->getAlignment(); 6210 unsigned NewAlign = 6211 TLI.getTargetData()->getABITypeAlignment( 6212 VT.getTypeForEVT(*DAG.getContext())); 6213 6214 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6215 return false; 6216 } 6217 6218 return true; 6219} 6220 6221static 6222SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6223 EVT VT = Op.getValueType(); 6224 6225 // Canonizalize to v2f64. 6226 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6227 return DAG.getNode(ISD::BITCAST, dl, VT, 6228 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6229 V1, DAG)); 6230} 6231 6232static 6233SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6234 bool HasSSE2) { 6235 SDValue V1 = Op.getOperand(0); 6236 SDValue V2 = Op.getOperand(1); 6237 EVT VT = Op.getValueType(); 6238 6239 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6240 6241 if (HasSSE2 && VT == MVT::v2f64) 6242 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6243 6244 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6245 return DAG.getNode(ISD::BITCAST, dl, VT, 6246 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6247 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6248 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6249} 6250 6251static 6252SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6253 SDValue V1 = Op.getOperand(0); 6254 SDValue V2 = Op.getOperand(1); 6255 EVT VT = Op.getValueType(); 6256 6257 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6258 "unsupported shuffle type"); 6259 6260 if (V2.getOpcode() == ISD::UNDEF) 6261 V2 = V1; 6262 6263 // v4i32 or v4f32 6264 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6265} 6266 6267static inline unsigned getSHUFPOpcode(EVT VT) { 6268 switch(VT.getSimpleVT().SimpleTy) { 6269 case MVT::v8i32: // Use fp unit for int unpack. 6270 case MVT::v8f32: 6271 case MVT::v4i32: // Use fp unit for int unpack. 6272 case MVT::v4f32: return X86ISD::SHUFPS; 6273 case MVT::v4i64: // Use fp unit for int unpack. 6274 case MVT::v4f64: 6275 case MVT::v2i64: // Use fp unit for int unpack. 6276 case MVT::v2f64: return X86ISD::SHUFPD; 6277 default: 6278 llvm_unreachable("Unknown type for shufp*"); 6279 } 6280 return 0; 6281} 6282 6283static 6284SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6285 SDValue V1 = Op.getOperand(0); 6286 SDValue V2 = Op.getOperand(1); 6287 EVT VT = Op.getValueType(); 6288 unsigned NumElems = VT.getVectorNumElements(); 6289 6290 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6291 // operand of these instructions is only memory, so check if there's a 6292 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6293 // same masks. 6294 bool CanFoldLoad = false; 6295 6296 // Trivial case, when V2 comes from a load. 6297 if (MayFoldVectorLoad(V2)) 6298 CanFoldLoad = true; 6299 6300 // When V1 is a load, it can be folded later into a store in isel, example: 6301 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6302 // turns into: 6303 // (MOVLPSmr addr:$src1, VR128:$src2) 6304 // So, recognize this potential and also use MOVLPS or MOVLPD 6305 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6306 CanFoldLoad = true; 6307 6308 // Both of them can't be memory operations though. 6309 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 6310 CanFoldLoad = false; 6311 6312 if (CanFoldLoad) { 6313 if (HasSSE2 && NumElems == 2) 6314 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6315 6316 if (NumElems == 4) 6317 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6318 } 6319 6320 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6321 // movl and movlp will both match v2i64, but v2i64 is never matched by 6322 // movl earlier because we make it strict to avoid messing with the movlp load 6323 // folding logic (see the code above getMOVLP call). Match it here then, 6324 // this is horrible, but will stay like this until we move all shuffle 6325 // matching to x86 specific nodes. Note that for the 1st condition all 6326 // types are matched with movsd. 6327 if (HasSSE2) { 6328 if (NumElems == 2) 6329 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6330 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6331 } 6332 6333 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6334 6335 // Invert the operand order and use SHUFPS to match it. 6336 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, 6337 X86::getShuffleSHUFImmediate(SVOp), DAG); 6338} 6339 6340static inline unsigned getUNPCKLOpcode(EVT VT) { 6341 switch(VT.getSimpleVT().SimpleTy) { 6342 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 6343 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 6344 case MVT::v4f32: return X86ISD::UNPCKLPS; 6345 case MVT::v2f64: return X86ISD::UNPCKLPD; 6346 case MVT::v8i32: // Use fp unit for int unpack. 6347 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 6348 case MVT::v4i64: // Use fp unit for int unpack. 6349 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 6350 case MVT::v16i8: return X86ISD::PUNPCKLBW; 6351 case MVT::v8i16: return X86ISD::PUNPCKLWD; 6352 default: 6353 llvm_unreachable("Unknown type for unpckl"); 6354 } 6355 return 0; 6356} 6357 6358static inline unsigned getUNPCKHOpcode(EVT VT) { 6359 switch(VT.getSimpleVT().SimpleTy) { 6360 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 6361 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 6362 case MVT::v4f32: return X86ISD::UNPCKHPS; 6363 case MVT::v2f64: return X86ISD::UNPCKHPD; 6364 case MVT::v8i32: // Use fp unit for int unpack. 6365 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 6366 case MVT::v4i64: // Use fp unit for int unpack. 6367 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 6368 case MVT::v16i8: return X86ISD::PUNPCKHBW; 6369 case MVT::v8i16: return X86ISD::PUNPCKHWD; 6370 default: 6371 llvm_unreachable("Unknown type for unpckh"); 6372 } 6373 return 0; 6374} 6375 6376static inline unsigned getVPERMILOpcode(EVT VT) { 6377 switch(VT.getSimpleVT().SimpleTy) { 6378 case MVT::v4i32: 6379 case MVT::v4f32: return X86ISD::VPERMILPS; 6380 case MVT::v2i64: 6381 case MVT::v2f64: return X86ISD::VPERMILPD; 6382 case MVT::v8i32: 6383 case MVT::v8f32: return X86ISD::VPERMILPSY; 6384 case MVT::v4i64: 6385 case MVT::v4f64: return X86ISD::VPERMILPDY; 6386 default: 6387 llvm_unreachable("Unknown type for vpermil"); 6388 } 6389 return 0; 6390} 6391 6392/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 6393/// a vbroadcast node. The nodes are suitable whenever we can fold a load coming 6394/// from a 32 or 64 bit scalar. Update Op to the desired load to be folded. 6395static bool isVectorBroadcast(SDValue &Op) { 6396 EVT VT = Op.getValueType(); 6397 bool Is256 = VT.getSizeInBits() == 256; 6398 6399 assert((VT.getSizeInBits() == 128 || Is256) && 6400 "Unsupported type for vbroadcast node"); 6401 6402 SDValue V = Op; 6403 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6404 V = V.getOperand(0); 6405 6406 if (Is256 && !(V.hasOneUse() && 6407 V.getOpcode() == ISD::INSERT_SUBVECTOR && 6408 V.getOperand(0).getOpcode() == ISD::UNDEF)) 6409 return false; 6410 6411 if (Is256) 6412 V = V.getOperand(1); 6413 6414 if (!V.hasOneUse()) 6415 return false; 6416 6417 // Check the source scalar_to_vector type. 256-bit broadcasts are 6418 // supported for 32/64-bit sizes, while 128-bit ones are only supported 6419 // for 32-bit scalars. 6420 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR) 6421 return false; 6422 6423 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits(); 6424 if (ScalarSize != 32 && ScalarSize != 64) 6425 return false; 6426 if (!Is256 && ScalarSize == 64) 6427 return false; 6428 6429 V = V.getOperand(0); 6430 if (!MayFoldLoad(V)) 6431 return false; 6432 6433 // Return the load node 6434 Op = V; 6435 return true; 6436} 6437 6438static 6439SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6440 const TargetLowering &TLI, 6441 const X86Subtarget *Subtarget) { 6442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6443 EVT VT = Op.getValueType(); 6444 DebugLoc dl = Op.getDebugLoc(); 6445 SDValue V1 = Op.getOperand(0); 6446 SDValue V2 = Op.getOperand(1); 6447 6448 if (isZeroShuffle(SVOp)) 6449 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 6450 6451 // Handle splat operations 6452 if (SVOp->isSplat()) { 6453 unsigned NumElem = VT.getVectorNumElements(); 6454 int Size = VT.getSizeInBits(); 6455 // Special case, this is the only place now where it's allowed to return 6456 // a vector_shuffle operation without using a target specific node, because 6457 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6458 // this be moved to DAGCombine instead? 6459 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6460 return Op; 6461 6462 // Use vbroadcast whenever the splat comes from a foldable load 6463 if (Subtarget->hasAVX() && isVectorBroadcast(V1)) 6464 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1); 6465 6466 // Handle splats by matching through known shuffle masks 6467 if ((Size == 128 && NumElem <= 4) || 6468 (Size == 256 && NumElem < 8)) 6469 return SDValue(); 6470 6471 // All remaning splats are promoted to target supported vector shuffles. 6472 return PromoteSplat(SVOp, DAG); 6473 } 6474 6475 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6476 // do it! 6477 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6478 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6479 if (NewOp.getNode()) 6480 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6481 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6482 // FIXME: Figure out a cleaner way to do this. 6483 // Try to make use of movq to zero out the top part. 6484 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6485 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6486 if (NewOp.getNode()) { 6487 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6488 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6489 DAG, Subtarget, dl); 6490 } 6491 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6492 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6493 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6494 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6495 DAG, Subtarget, dl); 6496 } 6497 } 6498 return SDValue(); 6499} 6500 6501SDValue 6502X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6503 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6504 SDValue V1 = Op.getOperand(0); 6505 SDValue V2 = Op.getOperand(1); 6506 EVT VT = Op.getValueType(); 6507 DebugLoc dl = Op.getDebugLoc(); 6508 unsigned NumElems = VT.getVectorNumElements(); 6509 bool isMMX = VT.getSizeInBits() == 64; 6510 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6511 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6512 bool V1IsSplat = false; 6513 bool V2IsSplat = false; 6514 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 6515 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 6516 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); 6517 MachineFunction &MF = DAG.getMachineFunction(); 6518 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6519 6520 // Shuffle operations on MMX not supported. 6521 if (isMMX) 6522 return Op; 6523 6524 // Vector shuffle lowering takes 3 steps: 6525 // 6526 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6527 // narrowing and commutation of operands should be handled. 6528 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6529 // shuffle nodes. 6530 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6531 // so the shuffle can be broken into other shuffles and the legalizer can 6532 // try the lowering again. 6533 // 6534 // The general ideia is that no vector_shuffle operation should be left to 6535 // be matched during isel, all of them must be converted to a target specific 6536 // node here. 6537 6538 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6539 // narrowing and commutation of operands should be handled. The actual code 6540 // doesn't include all of those, work in progress... 6541 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6542 if (NewOp.getNode()) 6543 return NewOp; 6544 6545 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6546 // unpckh_undef). Only use pshufd if speed is more important than size. 6547 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6548 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6549 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6550 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6551 6552 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && 6553 RelaxedMayFoldVectorLoad(V1)) 6554 return getMOVDDup(Op, dl, V1, DAG); 6555 6556 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6557 return getMOVHighToLow(Op, dl, DAG); 6558 6559 // Use to match splats 6560 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6561 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6562 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6563 6564 if (X86::isPSHUFDMask(SVOp)) { 6565 // The actual implementation will match the mask in the if above and then 6566 // during isel it can match several different instructions, not only pshufd 6567 // as its name says, sad but true, emulate the behavior for now... 6568 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6569 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6570 6571 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6572 6573 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6574 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6575 6576 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, 6577 TargetMask, DAG); 6578 } 6579 6580 // Check if this can be converted into a logical shift. 6581 bool isLeft = false; 6582 unsigned ShAmt = 0; 6583 SDValue ShVal; 6584 bool isShift = getSubtarget()->hasSSE2() && 6585 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6586 if (isShift && ShVal.hasOneUse()) { 6587 // If the shifted value has multiple uses, it may be cheaper to use 6588 // v_set0 + movlhps or movhlps, etc. 6589 EVT EltVT = VT.getVectorElementType(); 6590 ShAmt *= EltVT.getSizeInBits(); 6591 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6592 } 6593 6594 if (X86::isMOVLMask(SVOp)) { 6595 if (V1IsUndef) 6596 return V2; 6597 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6598 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6599 if (!X86::isMOVLPMask(SVOp)) { 6600 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6601 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6602 6603 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6604 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6605 } 6606 } 6607 6608 // FIXME: fold these into legal mask. 6609 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6610 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6611 6612 if (X86::isMOVHLPSMask(SVOp)) 6613 return getMOVHighToLow(Op, dl, DAG); 6614 6615 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6616 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6617 6618 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6619 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6620 6621 if (X86::isMOVLPMask(SVOp)) 6622 return getMOVLP(Op, dl, DAG, HasSSE2); 6623 6624 if (ShouldXformToMOVHLPS(SVOp) || 6625 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6626 return CommuteVectorShuffle(SVOp, DAG); 6627 6628 if (isShift) { 6629 // No better options. Use a vshl / vsrl. 6630 EVT EltVT = VT.getVectorElementType(); 6631 ShAmt *= EltVT.getSizeInBits(); 6632 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6633 } 6634 6635 bool Commuted = false; 6636 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6637 // 1,1,1,1 -> v8i16 though. 6638 V1IsSplat = isSplatVector(V1.getNode()); 6639 V2IsSplat = isSplatVector(V2.getNode()); 6640 6641 // Canonicalize the splat or undef, if present, to be on the RHS. 6642 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6643 Op = CommuteVectorShuffle(SVOp, DAG); 6644 SVOp = cast<ShuffleVectorSDNode>(Op); 6645 V1 = SVOp->getOperand(0); 6646 V2 = SVOp->getOperand(1); 6647 std::swap(V1IsSplat, V2IsSplat); 6648 std::swap(V1IsUndef, V2IsUndef); 6649 Commuted = true; 6650 } 6651 6652 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6653 // Shuffling low element of v1 into undef, just return v1. 6654 if (V2IsUndef) 6655 return V1; 6656 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6657 // the instruction selector will not match, so get a canonical MOVL with 6658 // swapped operands to undo the commute. 6659 return getMOVL(DAG, dl, VT, V2, V1); 6660 } 6661 6662 if (X86::isUNPCKLMask(SVOp)) 6663 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6664 6665 if (X86::isUNPCKHMask(SVOp)) 6666 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6667 6668 if (V2IsSplat) { 6669 // Normalize mask so all entries that point to V2 points to its first 6670 // element then try to match unpck{h|l} again. If match, return a 6671 // new vector_shuffle with the corrected mask. 6672 SDValue NewMask = NormalizeMask(SVOp, DAG); 6673 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6674 if (NSVOp != SVOp) { 6675 if (X86::isUNPCKLMask(NSVOp, true)) { 6676 return NewMask; 6677 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6678 return NewMask; 6679 } 6680 } 6681 } 6682 6683 if (Commuted) { 6684 // Commute is back and try unpck* again. 6685 // FIXME: this seems wrong. 6686 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6687 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6688 6689 if (X86::isUNPCKLMask(NewSVOp)) 6690 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6691 6692 if (X86::isUNPCKHMask(NewSVOp)) 6693 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6694 } 6695 6696 // Normalize the node to match x86 shuffle ops if needed 6697 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6698 return CommuteVectorShuffle(SVOp, DAG); 6699 6700 // The checks below are all present in isShuffleMaskLegal, but they are 6701 // inlined here right now to enable us to directly emit target specific 6702 // nodes, and remove one by one until they don't return Op anymore. 6703 SmallVector<int, 16> M; 6704 SVOp->getMask(M); 6705 6706 if (isPALIGNRMask(M, VT, HasSSSE3)) 6707 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6708 X86::getShufflePALIGNRImmediate(SVOp), 6709 DAG); 6710 6711 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6712 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6713 if (VT == MVT::v2f64) 6714 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6715 if (VT == MVT::v2i64) 6716 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6717 } 6718 6719 if (isPSHUFHWMask(M, VT)) 6720 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6721 X86::getShufflePSHUFHWImmediate(SVOp), 6722 DAG); 6723 6724 if (isPSHUFLWMask(M, VT)) 6725 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6726 X86::getShufflePSHUFLWImmediate(SVOp), 6727 DAG); 6728 6729 if (isSHUFPMask(M, VT)) 6730 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6731 X86::getShuffleSHUFImmediate(SVOp), DAG); 6732 6733 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6734 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6735 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6736 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6737 6738 //===--------------------------------------------------------------------===// 6739 // Generate target specific nodes for 128 or 256-bit shuffles only 6740 // supported in the AVX instruction set. 6741 // 6742 6743 // Handle VMOVDDUPY permutations 6744 if (isMOVDDUPYMask(SVOp, Subtarget)) 6745 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6746 6747 // Handle VPERMILPS* permutations 6748 if (isVPERMILPSMask(M, VT, Subtarget)) 6749 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6750 getShuffleVPERMILPSImmediate(SVOp), DAG); 6751 6752 // Handle VPERMILPD* permutations 6753 if (isVPERMILPDMask(M, VT, Subtarget)) 6754 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6755 getShuffleVPERMILPDImmediate(SVOp), DAG); 6756 6757 // Handle VPERM2F128 permutations 6758 if (isVPERM2F128Mask(M, VT, Subtarget)) 6759 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, 6760 getShuffleVPERM2F128Immediate(SVOp), DAG); 6761 6762 // Handle VSHUFPSY permutations 6763 if (isVSHUFPSYMask(M, VT, Subtarget)) 6764 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6765 getShuffleVSHUFPSYImmediate(SVOp), DAG); 6766 6767 // Handle VSHUFPDY permutations 6768 if (isVSHUFPDYMask(M, VT, Subtarget)) 6769 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6770 getShuffleVSHUFPDYImmediate(SVOp), DAG); 6771 6772 //===--------------------------------------------------------------------===// 6773 // Since no target specific shuffle was selected for this generic one, 6774 // lower it into other known shuffles. FIXME: this isn't true yet, but 6775 // this is the plan. 6776 // 6777 6778 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6779 if (VT == MVT::v8i16) { 6780 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6781 if (NewOp.getNode()) 6782 return NewOp; 6783 } 6784 6785 if (VT == MVT::v16i8) { 6786 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6787 if (NewOp.getNode()) 6788 return NewOp; 6789 } 6790 6791 // Handle all 128-bit wide vectors with 4 elements, and match them with 6792 // several different shuffle types. 6793 if (NumElems == 4 && VT.getSizeInBits() == 128) 6794 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6795 6796 // Handle general 256-bit shuffles 6797 if (VT.is256BitVector()) 6798 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6799 6800 return SDValue(); 6801} 6802 6803SDValue 6804X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6805 SelectionDAG &DAG) const { 6806 EVT VT = Op.getValueType(); 6807 DebugLoc dl = Op.getDebugLoc(); 6808 6809 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6810 return SDValue(); 6811 6812 if (VT.getSizeInBits() == 8) { 6813 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6814 Op.getOperand(0), Op.getOperand(1)); 6815 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6816 DAG.getValueType(VT)); 6817 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6818 } else if (VT.getSizeInBits() == 16) { 6819 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6820 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6821 if (Idx == 0) 6822 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6823 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6824 DAG.getNode(ISD::BITCAST, dl, 6825 MVT::v4i32, 6826 Op.getOperand(0)), 6827 Op.getOperand(1))); 6828 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6829 Op.getOperand(0), Op.getOperand(1)); 6830 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6831 DAG.getValueType(VT)); 6832 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6833 } else if (VT == MVT::f32) { 6834 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6835 // the result back to FR32 register. It's only worth matching if the 6836 // result has a single use which is a store or a bitcast to i32. And in 6837 // the case of a store, it's not worth it if the index is a constant 0, 6838 // because a MOVSSmr can be used instead, which is smaller and faster. 6839 if (!Op.hasOneUse()) 6840 return SDValue(); 6841 SDNode *User = *Op.getNode()->use_begin(); 6842 if ((User->getOpcode() != ISD::STORE || 6843 (isa<ConstantSDNode>(Op.getOperand(1)) && 6844 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6845 (User->getOpcode() != ISD::BITCAST || 6846 User->getValueType(0) != MVT::i32)) 6847 return SDValue(); 6848 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6849 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6850 Op.getOperand(0)), 6851 Op.getOperand(1)); 6852 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6853 } else if (VT == MVT::i32) { 6854 // ExtractPS works with constant index. 6855 if (isa<ConstantSDNode>(Op.getOperand(1))) 6856 return Op; 6857 } 6858 return SDValue(); 6859} 6860 6861 6862SDValue 6863X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6864 SelectionDAG &DAG) const { 6865 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6866 return SDValue(); 6867 6868 SDValue Vec = Op.getOperand(0); 6869 EVT VecVT = Vec.getValueType(); 6870 6871 // If this is a 256-bit vector result, first extract the 128-bit vector and 6872 // then extract the element from the 128-bit vector. 6873 if (VecVT.getSizeInBits() == 256) { 6874 DebugLoc dl = Op.getNode()->getDebugLoc(); 6875 unsigned NumElems = VecVT.getVectorNumElements(); 6876 SDValue Idx = Op.getOperand(1); 6877 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6878 6879 // Get the 128-bit vector. 6880 bool Upper = IdxVal >= NumElems/2; 6881 Vec = Extract128BitVector(Vec, 6882 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6883 6884 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6885 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6886 } 6887 6888 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6889 6890 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 6891 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6892 if (Res.getNode()) 6893 return Res; 6894 } 6895 6896 EVT VT = Op.getValueType(); 6897 DebugLoc dl = Op.getDebugLoc(); 6898 // TODO: handle v16i8. 6899 if (VT.getSizeInBits() == 16) { 6900 SDValue Vec = Op.getOperand(0); 6901 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6902 if (Idx == 0) 6903 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6904 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6905 DAG.getNode(ISD::BITCAST, dl, 6906 MVT::v4i32, Vec), 6907 Op.getOperand(1))); 6908 // Transform it so it match pextrw which produces a 32-bit result. 6909 EVT EltVT = MVT::i32; 6910 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6911 Op.getOperand(0), Op.getOperand(1)); 6912 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6913 DAG.getValueType(VT)); 6914 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6915 } else if (VT.getSizeInBits() == 32) { 6916 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6917 if (Idx == 0) 6918 return Op; 6919 6920 // SHUFPS the element to the lowest double word, then movss. 6921 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6922 EVT VVT = Op.getOperand(0).getValueType(); 6923 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6924 DAG.getUNDEF(VVT), Mask); 6925 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6926 DAG.getIntPtrConstant(0)); 6927 } else if (VT.getSizeInBits() == 64) { 6928 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6929 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6930 // to match extract_elt for f64. 6931 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6932 if (Idx == 0) 6933 return Op; 6934 6935 // UNPCKHPD the element to the lowest double word, then movsd. 6936 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6937 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6938 int Mask[2] = { 1, -1 }; 6939 EVT VVT = Op.getOperand(0).getValueType(); 6940 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6941 DAG.getUNDEF(VVT), Mask); 6942 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6943 DAG.getIntPtrConstant(0)); 6944 } 6945 6946 return SDValue(); 6947} 6948 6949SDValue 6950X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6951 SelectionDAG &DAG) const { 6952 EVT VT = Op.getValueType(); 6953 EVT EltVT = VT.getVectorElementType(); 6954 DebugLoc dl = Op.getDebugLoc(); 6955 6956 SDValue N0 = Op.getOperand(0); 6957 SDValue N1 = Op.getOperand(1); 6958 SDValue N2 = Op.getOperand(2); 6959 6960 if (VT.getSizeInBits() == 256) 6961 return SDValue(); 6962 6963 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6964 isa<ConstantSDNode>(N2)) { 6965 unsigned Opc; 6966 if (VT == MVT::v8i16) 6967 Opc = X86ISD::PINSRW; 6968 else if (VT == MVT::v16i8) 6969 Opc = X86ISD::PINSRB; 6970 else 6971 Opc = X86ISD::PINSRB; 6972 6973 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6974 // argument. 6975 if (N1.getValueType() != MVT::i32) 6976 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6977 if (N2.getValueType() != MVT::i32) 6978 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6979 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6980 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6981 // Bits [7:6] of the constant are the source select. This will always be 6982 // zero here. The DAG Combiner may combine an extract_elt index into these 6983 // bits. For example (insert (extract, 3), 2) could be matched by putting 6984 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6985 // Bits [5:4] of the constant are the destination select. This is the 6986 // value of the incoming immediate. 6987 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6988 // combine either bitwise AND or insert of float 0.0 to set these bits. 6989 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6990 // Create this as a scalar to vector.. 6991 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6992 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6993 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 6994 // PINSR* works with constant index. 6995 return Op; 6996 } 6997 return SDValue(); 6998} 6999 7000SDValue 7001X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7002 EVT VT = Op.getValueType(); 7003 EVT EltVT = VT.getVectorElementType(); 7004 7005 DebugLoc dl = Op.getDebugLoc(); 7006 SDValue N0 = Op.getOperand(0); 7007 SDValue N1 = Op.getOperand(1); 7008 SDValue N2 = Op.getOperand(2); 7009 7010 // If this is a 256-bit vector result, first extract the 128-bit vector, 7011 // insert the element into the extracted half and then place it back. 7012 if (VT.getSizeInBits() == 256) { 7013 if (!isa<ConstantSDNode>(N2)) 7014 return SDValue(); 7015 7016 // Get the desired 128-bit vector half. 7017 unsigned NumElems = VT.getVectorNumElements(); 7018 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7019 bool Upper = IdxVal >= NumElems/2; 7020 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 7021 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 7022 7023 // Insert the element into the desired half. 7024 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 7025 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 7026 7027 // Insert the changed part back to the 256-bit vector 7028 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 7029 } 7030 7031 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 7032 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7033 7034 if (EltVT == MVT::i8) 7035 return SDValue(); 7036 7037 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7038 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7039 // as its second argument. 7040 if (N1.getValueType() != MVT::i32) 7041 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7042 if (N2.getValueType() != MVT::i32) 7043 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7044 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7045 } 7046 return SDValue(); 7047} 7048 7049SDValue 7050X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7051 LLVMContext *Context = DAG.getContext(); 7052 DebugLoc dl = Op.getDebugLoc(); 7053 EVT OpVT = Op.getValueType(); 7054 7055 // If this is a 256-bit vector result, first insert into a 128-bit 7056 // vector and then insert into the 256-bit vector. 7057 if (OpVT.getSizeInBits() > 128) { 7058 // Insert into a 128-bit vector. 7059 EVT VT128 = EVT::getVectorVT(*Context, 7060 OpVT.getVectorElementType(), 7061 OpVT.getVectorNumElements() / 2); 7062 7063 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7064 7065 // Insert the 128-bit vector. 7066 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7067 DAG.getConstant(0, MVT::i32), 7068 DAG, dl); 7069 } 7070 7071 if (Op.getValueType() == MVT::v1i64 && 7072 Op.getOperand(0).getValueType() == MVT::i64) 7073 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7074 7075 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7076 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7077 "Expected an SSE type!"); 7078 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7079 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7080} 7081 7082// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7083// a simple subregister reference or explicit instructions to grab 7084// upper bits of a vector. 7085SDValue 7086X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7087 if (Subtarget->hasAVX()) { 7088 DebugLoc dl = Op.getNode()->getDebugLoc(); 7089 SDValue Vec = Op.getNode()->getOperand(0); 7090 SDValue Idx = Op.getNode()->getOperand(1); 7091 7092 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7093 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7094 return Extract128BitVector(Vec, Idx, DAG, dl); 7095 } 7096 } 7097 return SDValue(); 7098} 7099 7100// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7101// simple superregister reference or explicit instructions to insert 7102// the upper bits of a vector. 7103SDValue 7104X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7105 if (Subtarget->hasAVX()) { 7106 DebugLoc dl = Op.getNode()->getDebugLoc(); 7107 SDValue Vec = Op.getNode()->getOperand(0); 7108 SDValue SubVec = Op.getNode()->getOperand(1); 7109 SDValue Idx = Op.getNode()->getOperand(2); 7110 7111 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7112 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7113 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7114 } 7115 } 7116 return SDValue(); 7117} 7118 7119// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7120// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7121// one of the above mentioned nodes. It has to be wrapped because otherwise 7122// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7123// be used to form addressing mode. These wrapped nodes will be selected 7124// into MOV32ri. 7125SDValue 7126X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7127 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7128 7129 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7130 // global base reg. 7131 unsigned char OpFlag = 0; 7132 unsigned WrapperKind = X86ISD::Wrapper; 7133 CodeModel::Model M = getTargetMachine().getCodeModel(); 7134 7135 if (Subtarget->isPICStyleRIPRel() && 7136 (M == CodeModel::Small || M == CodeModel::Kernel)) 7137 WrapperKind = X86ISD::WrapperRIP; 7138 else if (Subtarget->isPICStyleGOT()) 7139 OpFlag = X86II::MO_GOTOFF; 7140 else if (Subtarget->isPICStyleStubPIC()) 7141 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7142 7143 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7144 CP->getAlignment(), 7145 CP->getOffset(), OpFlag); 7146 DebugLoc DL = CP->getDebugLoc(); 7147 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7148 // With PIC, the address is actually $g + Offset. 7149 if (OpFlag) { 7150 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7151 DAG.getNode(X86ISD::GlobalBaseReg, 7152 DebugLoc(), getPointerTy()), 7153 Result); 7154 } 7155 7156 return Result; 7157} 7158 7159SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7160 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7161 7162 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7163 // global base reg. 7164 unsigned char OpFlag = 0; 7165 unsigned WrapperKind = X86ISD::Wrapper; 7166 CodeModel::Model M = getTargetMachine().getCodeModel(); 7167 7168 if (Subtarget->isPICStyleRIPRel() && 7169 (M == CodeModel::Small || M == CodeModel::Kernel)) 7170 WrapperKind = X86ISD::WrapperRIP; 7171 else if (Subtarget->isPICStyleGOT()) 7172 OpFlag = X86II::MO_GOTOFF; 7173 else if (Subtarget->isPICStyleStubPIC()) 7174 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7175 7176 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7177 OpFlag); 7178 DebugLoc DL = JT->getDebugLoc(); 7179 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7180 7181 // With PIC, the address is actually $g + Offset. 7182 if (OpFlag) 7183 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7184 DAG.getNode(X86ISD::GlobalBaseReg, 7185 DebugLoc(), getPointerTy()), 7186 Result); 7187 7188 return Result; 7189} 7190 7191SDValue 7192X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7193 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7194 7195 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7196 // global base reg. 7197 unsigned char OpFlag = 0; 7198 unsigned WrapperKind = X86ISD::Wrapper; 7199 CodeModel::Model M = getTargetMachine().getCodeModel(); 7200 7201 if (Subtarget->isPICStyleRIPRel() && 7202 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7203 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7204 OpFlag = X86II::MO_GOTPCREL; 7205 WrapperKind = X86ISD::WrapperRIP; 7206 } else if (Subtarget->isPICStyleGOT()) { 7207 OpFlag = X86II::MO_GOT; 7208 } else if (Subtarget->isPICStyleStubPIC()) { 7209 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7210 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7211 OpFlag = X86II::MO_DARWIN_NONLAZY; 7212 } 7213 7214 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7215 7216 DebugLoc DL = Op.getDebugLoc(); 7217 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7218 7219 7220 // With PIC, the address is actually $g + Offset. 7221 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7222 !Subtarget->is64Bit()) { 7223 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7224 DAG.getNode(X86ISD::GlobalBaseReg, 7225 DebugLoc(), getPointerTy()), 7226 Result); 7227 } 7228 7229 // For symbols that require a load from a stub to get the address, emit the 7230 // load. 7231 if (isGlobalStubReference(OpFlag)) 7232 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7233 MachinePointerInfo::getGOT(), false, false, 0); 7234 7235 return Result; 7236} 7237 7238SDValue 7239X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7240 // Create the TargetBlockAddressAddress node. 7241 unsigned char OpFlags = 7242 Subtarget->ClassifyBlockAddressReference(); 7243 CodeModel::Model M = getTargetMachine().getCodeModel(); 7244 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7245 DebugLoc dl = Op.getDebugLoc(); 7246 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7247 /*isTarget=*/true, OpFlags); 7248 7249 if (Subtarget->isPICStyleRIPRel() && 7250 (M == CodeModel::Small || M == CodeModel::Kernel)) 7251 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7252 else 7253 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7254 7255 // With PIC, the address is actually $g + Offset. 7256 if (isGlobalRelativeToPICBase(OpFlags)) { 7257 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7258 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7259 Result); 7260 } 7261 7262 return Result; 7263} 7264 7265SDValue 7266X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7267 int64_t Offset, 7268 SelectionDAG &DAG) const { 7269 // Create the TargetGlobalAddress node, folding in the constant 7270 // offset if it is legal. 7271 unsigned char OpFlags = 7272 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7273 CodeModel::Model M = getTargetMachine().getCodeModel(); 7274 SDValue Result; 7275 if (OpFlags == X86II::MO_NO_FLAG && 7276 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7277 // A direct static reference to a global. 7278 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7279 Offset = 0; 7280 } else { 7281 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7282 } 7283 7284 if (Subtarget->isPICStyleRIPRel() && 7285 (M == CodeModel::Small || M == CodeModel::Kernel)) 7286 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7287 else 7288 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7289 7290 // With PIC, the address is actually $g + Offset. 7291 if (isGlobalRelativeToPICBase(OpFlags)) { 7292 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7293 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7294 Result); 7295 } 7296 7297 // For globals that require a load from a stub to get the address, emit the 7298 // load. 7299 if (isGlobalStubReference(OpFlags)) 7300 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7301 MachinePointerInfo::getGOT(), false, false, 0); 7302 7303 // If there was a non-zero offset that we didn't fold, create an explicit 7304 // addition for it. 7305 if (Offset != 0) 7306 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7307 DAG.getConstant(Offset, getPointerTy())); 7308 7309 return Result; 7310} 7311 7312SDValue 7313X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7314 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7315 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7316 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7317} 7318 7319static SDValue 7320GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7321 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7322 unsigned char OperandFlags) { 7323 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7324 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7325 DebugLoc dl = GA->getDebugLoc(); 7326 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7327 GA->getValueType(0), 7328 GA->getOffset(), 7329 OperandFlags); 7330 if (InFlag) { 7331 SDValue Ops[] = { Chain, TGA, *InFlag }; 7332 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7333 } else { 7334 SDValue Ops[] = { Chain, TGA }; 7335 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7336 } 7337 7338 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7339 MFI->setAdjustsStack(true); 7340 7341 SDValue Flag = Chain.getValue(1); 7342 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7343} 7344 7345// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7346static SDValue 7347LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7348 const EVT PtrVT) { 7349 SDValue InFlag; 7350 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7351 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7352 DAG.getNode(X86ISD::GlobalBaseReg, 7353 DebugLoc(), PtrVT), InFlag); 7354 InFlag = Chain.getValue(1); 7355 7356 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7357} 7358 7359// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7360static SDValue 7361LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7362 const EVT PtrVT) { 7363 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7364 X86::RAX, X86II::MO_TLSGD); 7365} 7366 7367// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7368// "local exec" model. 7369static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7370 const EVT PtrVT, TLSModel::Model model, 7371 bool is64Bit) { 7372 DebugLoc dl = GA->getDebugLoc(); 7373 7374 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7375 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7376 is64Bit ? 257 : 256)); 7377 7378 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7379 DAG.getIntPtrConstant(0), 7380 MachinePointerInfo(Ptr), false, false, 0); 7381 7382 unsigned char OperandFlags = 0; 7383 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7384 // initialexec. 7385 unsigned WrapperKind = X86ISD::Wrapper; 7386 if (model == TLSModel::LocalExec) { 7387 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7388 } else if (is64Bit) { 7389 assert(model == TLSModel::InitialExec); 7390 OperandFlags = X86II::MO_GOTTPOFF; 7391 WrapperKind = X86ISD::WrapperRIP; 7392 } else { 7393 assert(model == TLSModel::InitialExec); 7394 OperandFlags = X86II::MO_INDNTPOFF; 7395 } 7396 7397 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7398 // exec) 7399 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7400 GA->getValueType(0), 7401 GA->getOffset(), OperandFlags); 7402 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7403 7404 if (model == TLSModel::InitialExec) 7405 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7406 MachinePointerInfo::getGOT(), false, false, 0); 7407 7408 // The address of the thread local variable is the add of the thread 7409 // pointer with the offset of the variable. 7410 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7411} 7412 7413SDValue 7414X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7415 7416 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7417 const GlobalValue *GV = GA->getGlobal(); 7418 7419 if (Subtarget->isTargetELF()) { 7420 // TODO: implement the "local dynamic" model 7421 // TODO: implement the "initial exec"model for pic executables 7422 7423 // If GV is an alias then use the aliasee for determining 7424 // thread-localness. 7425 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7426 GV = GA->resolveAliasedGlobal(false); 7427 7428 TLSModel::Model model 7429 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7430 7431 switch (model) { 7432 case TLSModel::GeneralDynamic: 7433 case TLSModel::LocalDynamic: // not implemented 7434 if (Subtarget->is64Bit()) 7435 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7436 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7437 7438 case TLSModel::InitialExec: 7439 case TLSModel::LocalExec: 7440 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7441 Subtarget->is64Bit()); 7442 } 7443 } else if (Subtarget->isTargetDarwin()) { 7444 // Darwin only has one model of TLS. Lower to that. 7445 unsigned char OpFlag = 0; 7446 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7447 X86ISD::WrapperRIP : X86ISD::Wrapper; 7448 7449 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7450 // global base reg. 7451 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7452 !Subtarget->is64Bit(); 7453 if (PIC32) 7454 OpFlag = X86II::MO_TLVP_PIC_BASE; 7455 else 7456 OpFlag = X86II::MO_TLVP; 7457 DebugLoc DL = Op.getDebugLoc(); 7458 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7459 GA->getValueType(0), 7460 GA->getOffset(), OpFlag); 7461 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7462 7463 // With PIC32, the address is actually $g + Offset. 7464 if (PIC32) 7465 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7466 DAG.getNode(X86ISD::GlobalBaseReg, 7467 DebugLoc(), getPointerTy()), 7468 Offset); 7469 7470 // Lowering the machine isd will make sure everything is in the right 7471 // location. 7472 SDValue Chain = DAG.getEntryNode(); 7473 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7474 SDValue Args[] = { Chain, Offset }; 7475 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7476 7477 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7478 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7479 MFI->setAdjustsStack(true); 7480 7481 // And our return value (tls address) is in the standard call return value 7482 // location. 7483 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7484 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 7485 } 7486 7487 assert(false && 7488 "TLS not implemented for this target."); 7489 7490 llvm_unreachable("Unreachable"); 7491 return SDValue(); 7492} 7493 7494 7495/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7496/// take a 2 x i32 value to shift plus a shift amount. 7497SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7498 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7499 EVT VT = Op.getValueType(); 7500 unsigned VTBits = VT.getSizeInBits(); 7501 DebugLoc dl = Op.getDebugLoc(); 7502 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7503 SDValue ShOpLo = Op.getOperand(0); 7504 SDValue ShOpHi = Op.getOperand(1); 7505 SDValue ShAmt = Op.getOperand(2); 7506 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7507 DAG.getConstant(VTBits - 1, MVT::i8)) 7508 : DAG.getConstant(0, VT); 7509 7510 SDValue Tmp2, Tmp3; 7511 if (Op.getOpcode() == ISD::SHL_PARTS) { 7512 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7513 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7514 } else { 7515 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7516 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7517 } 7518 7519 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7520 DAG.getConstant(VTBits, MVT::i8)); 7521 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7522 AndNode, DAG.getConstant(0, MVT::i8)); 7523 7524 SDValue Hi, Lo; 7525 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7526 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7527 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7528 7529 if (Op.getOpcode() == ISD::SHL_PARTS) { 7530 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7531 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7532 } else { 7533 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7534 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7535 } 7536 7537 SDValue Ops[2] = { Lo, Hi }; 7538 return DAG.getMergeValues(Ops, 2, dl); 7539} 7540 7541SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7542 SelectionDAG &DAG) const { 7543 EVT SrcVT = Op.getOperand(0).getValueType(); 7544 7545 if (SrcVT.isVector()) 7546 return SDValue(); 7547 7548 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7549 "Unknown SINT_TO_FP to lower!"); 7550 7551 // These are really Legal; return the operand so the caller accepts it as 7552 // Legal. 7553 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7554 return Op; 7555 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7556 Subtarget->is64Bit()) { 7557 return Op; 7558 } 7559 7560 DebugLoc dl = Op.getDebugLoc(); 7561 unsigned Size = SrcVT.getSizeInBits()/8; 7562 MachineFunction &MF = DAG.getMachineFunction(); 7563 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7564 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7565 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7566 StackSlot, 7567 MachinePointerInfo::getFixedStack(SSFI), 7568 false, false, 0); 7569 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7570} 7571 7572SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7573 SDValue StackSlot, 7574 SelectionDAG &DAG) const { 7575 // Build the FILD 7576 DebugLoc DL = Op.getDebugLoc(); 7577 SDVTList Tys; 7578 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7579 if (useSSE) 7580 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7581 else 7582 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7583 7584 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7585 7586 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7587 MachineMemOperand *MMO; 7588 if (FI) { 7589 int SSFI = FI->getIndex(); 7590 MMO = 7591 DAG.getMachineFunction() 7592 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7593 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7594 } else { 7595 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7596 StackSlot = StackSlot.getOperand(1); 7597 } 7598 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7599 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7600 X86ISD::FILD, DL, 7601 Tys, Ops, array_lengthof(Ops), 7602 SrcVT, MMO); 7603 7604 if (useSSE) { 7605 Chain = Result.getValue(1); 7606 SDValue InFlag = Result.getValue(2); 7607 7608 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7609 // shouldn't be necessary except that RFP cannot be live across 7610 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7611 MachineFunction &MF = DAG.getMachineFunction(); 7612 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7613 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7614 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7615 Tys = DAG.getVTList(MVT::Other); 7616 SDValue Ops[] = { 7617 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7618 }; 7619 MachineMemOperand *MMO = 7620 DAG.getMachineFunction() 7621 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7622 MachineMemOperand::MOStore, SSFISize, SSFISize); 7623 7624 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7625 Ops, array_lengthof(Ops), 7626 Op.getValueType(), MMO); 7627 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7628 MachinePointerInfo::getFixedStack(SSFI), 7629 false, false, 0); 7630 } 7631 7632 return Result; 7633} 7634 7635// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7636SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7637 SelectionDAG &DAG) const { 7638 // This algorithm is not obvious. Here it is in C code, more or less: 7639 /* 7640 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7641 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7642 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7643 7644 // Copy ints to xmm registers. 7645 __m128i xh = _mm_cvtsi32_si128( hi ); 7646 __m128i xl = _mm_cvtsi32_si128( lo ); 7647 7648 // Combine into low half of a single xmm register. 7649 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7650 __m128d d; 7651 double sd; 7652 7653 // Merge in appropriate exponents to give the integer bits the right 7654 // magnitude. 7655 x = _mm_unpacklo_epi32( x, exp ); 7656 7657 // Subtract away the biases to deal with the IEEE-754 double precision 7658 // implicit 1. 7659 d = _mm_sub_pd( (__m128d) x, bias ); 7660 7661 // All conversions up to here are exact. The correctly rounded result is 7662 // calculated using the current rounding mode using the following 7663 // horizontal add. 7664 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7665 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7666 // store doesn't really need to be here (except 7667 // maybe to zero the other double) 7668 return sd; 7669 } 7670 */ 7671 7672 DebugLoc dl = Op.getDebugLoc(); 7673 LLVMContext *Context = DAG.getContext(); 7674 7675 // Build some magic constants. 7676 std::vector<Constant*> CV0; 7677 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7678 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7679 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7680 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7681 Constant *C0 = ConstantVector::get(CV0); 7682 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7683 7684 std::vector<Constant*> CV1; 7685 CV1.push_back( 7686 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7687 CV1.push_back( 7688 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7689 Constant *C1 = ConstantVector::get(CV1); 7690 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7691 7692 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7693 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7694 Op.getOperand(0), 7695 DAG.getIntPtrConstant(1))); 7696 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7697 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7698 Op.getOperand(0), 7699 DAG.getIntPtrConstant(0))); 7700 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7701 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7702 MachinePointerInfo::getConstantPool(), 7703 false, false, 16); 7704 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7705 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7706 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7707 MachinePointerInfo::getConstantPool(), 7708 false, false, 16); 7709 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7710 7711 // Add the halves; easiest way is to swap them into another reg first. 7712 int ShufMask[2] = { 1, -1 }; 7713 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7714 DAG.getUNDEF(MVT::v2f64), ShufMask); 7715 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7716 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7717 DAG.getIntPtrConstant(0)); 7718} 7719 7720// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7721SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7722 SelectionDAG &DAG) const { 7723 DebugLoc dl = Op.getDebugLoc(); 7724 // FP constant to bias correct the final result. 7725 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7726 MVT::f64); 7727 7728 // Load the 32-bit value into an XMM register. 7729 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7730 Op.getOperand(0)); 7731 7732 // Zero out the upper parts of the register. 7733 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG); 7734 7735 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7736 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7737 DAG.getIntPtrConstant(0)); 7738 7739 // Or the load with the bias. 7740 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7741 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7742 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7743 MVT::v2f64, Load)), 7744 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7745 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7746 MVT::v2f64, Bias))); 7747 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7748 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7749 DAG.getIntPtrConstant(0)); 7750 7751 // Subtract the bias. 7752 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7753 7754 // Handle final rounding. 7755 EVT DestVT = Op.getValueType(); 7756 7757 if (DestVT.bitsLT(MVT::f64)) { 7758 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7759 DAG.getIntPtrConstant(0)); 7760 } else if (DestVT.bitsGT(MVT::f64)) { 7761 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7762 } 7763 7764 // Handle final rounding. 7765 return Sub; 7766} 7767 7768SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7769 SelectionDAG &DAG) const { 7770 SDValue N0 = Op.getOperand(0); 7771 DebugLoc dl = Op.getDebugLoc(); 7772 7773 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7774 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7775 // the optimization here. 7776 if (DAG.SignBitIsZero(N0)) 7777 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7778 7779 EVT SrcVT = N0.getValueType(); 7780 EVT DstVT = Op.getValueType(); 7781 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7782 return LowerUINT_TO_FP_i64(Op, DAG); 7783 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7784 return LowerUINT_TO_FP_i32(Op, DAG); 7785 7786 // Make a 64-bit buffer, and use it to build an FILD. 7787 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7788 if (SrcVT == MVT::i32) { 7789 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7790 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7791 getPointerTy(), StackSlot, WordOff); 7792 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7793 StackSlot, MachinePointerInfo(), 7794 false, false, 0); 7795 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7796 OffsetSlot, MachinePointerInfo(), 7797 false, false, 0); 7798 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7799 return Fild; 7800 } 7801 7802 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7803 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7804 StackSlot, MachinePointerInfo(), 7805 false, false, 0); 7806 // For i64 source, we need to add the appropriate power of 2 if the input 7807 // was negative. This is the same as the optimization in 7808 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7809 // we must be careful to do the computation in x87 extended precision, not 7810 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7811 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7812 MachineMemOperand *MMO = 7813 DAG.getMachineFunction() 7814 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7815 MachineMemOperand::MOLoad, 8, 8); 7816 7817 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7818 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7819 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7820 MVT::i64, MMO); 7821 7822 APInt FF(32, 0x5F800000ULL); 7823 7824 // Check whether the sign bit is set. 7825 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7826 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7827 ISD::SETLT); 7828 7829 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7830 SDValue FudgePtr = DAG.getConstantPool( 7831 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7832 getPointerTy()); 7833 7834 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7835 SDValue Zero = DAG.getIntPtrConstant(0); 7836 SDValue Four = DAG.getIntPtrConstant(4); 7837 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7838 Zero, Four); 7839 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7840 7841 // Load the value out, extending it from f32 to f80. 7842 // FIXME: Avoid the extend by constructing the right constant pool? 7843 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7844 FudgePtr, MachinePointerInfo::getConstantPool(), 7845 MVT::f32, false, false, 4); 7846 // Extend everything to 80 bits to force it to be done on x87. 7847 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7848 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7849} 7850 7851std::pair<SDValue,SDValue> X86TargetLowering:: 7852FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7853 DebugLoc DL = Op.getDebugLoc(); 7854 7855 EVT DstTy = Op.getValueType(); 7856 7857 if (!IsSigned) { 7858 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7859 DstTy = MVT::i64; 7860 } 7861 7862 assert(DstTy.getSimpleVT() <= MVT::i64 && 7863 DstTy.getSimpleVT() >= MVT::i16 && 7864 "Unknown FP_TO_SINT to lower!"); 7865 7866 // These are really Legal. 7867 if (DstTy == MVT::i32 && 7868 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7869 return std::make_pair(SDValue(), SDValue()); 7870 if (Subtarget->is64Bit() && 7871 DstTy == MVT::i64 && 7872 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7873 return std::make_pair(SDValue(), SDValue()); 7874 7875 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7876 // stack slot. 7877 MachineFunction &MF = DAG.getMachineFunction(); 7878 unsigned MemSize = DstTy.getSizeInBits()/8; 7879 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7880 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7881 7882 7883 7884 unsigned Opc; 7885 switch (DstTy.getSimpleVT().SimpleTy) { 7886 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7887 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7888 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7889 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7890 } 7891 7892 SDValue Chain = DAG.getEntryNode(); 7893 SDValue Value = Op.getOperand(0); 7894 EVT TheVT = Op.getOperand(0).getValueType(); 7895 if (isScalarFPTypeInSSEReg(TheVT)) { 7896 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7897 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7898 MachinePointerInfo::getFixedStack(SSFI), 7899 false, false, 0); 7900 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7901 SDValue Ops[] = { 7902 Chain, StackSlot, DAG.getValueType(TheVT) 7903 }; 7904 7905 MachineMemOperand *MMO = 7906 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7907 MachineMemOperand::MOLoad, MemSize, MemSize); 7908 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7909 DstTy, MMO); 7910 Chain = Value.getValue(1); 7911 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7912 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7913 } 7914 7915 MachineMemOperand *MMO = 7916 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7917 MachineMemOperand::MOStore, MemSize, MemSize); 7918 7919 // Build the FP_TO_INT*_IN_MEM 7920 SDValue Ops[] = { Chain, Value, StackSlot }; 7921 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7922 Ops, 3, DstTy, MMO); 7923 7924 return std::make_pair(FIST, StackSlot); 7925} 7926 7927SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7928 SelectionDAG &DAG) const { 7929 if (Op.getValueType().isVector()) 7930 return SDValue(); 7931 7932 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7933 SDValue FIST = Vals.first, StackSlot = Vals.second; 7934 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7935 if (FIST.getNode() == 0) return Op; 7936 7937 // Load the result. 7938 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7939 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7940} 7941 7942SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7943 SelectionDAG &DAG) const { 7944 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7945 SDValue FIST = Vals.first, StackSlot = Vals.second; 7946 assert(FIST.getNode() && "Unexpected failure"); 7947 7948 // Load the result. 7949 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7950 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7951} 7952 7953SDValue X86TargetLowering::LowerFABS(SDValue Op, 7954 SelectionDAG &DAG) const { 7955 LLVMContext *Context = DAG.getContext(); 7956 DebugLoc dl = Op.getDebugLoc(); 7957 EVT VT = Op.getValueType(); 7958 EVT EltVT = VT; 7959 if (VT.isVector()) 7960 EltVT = VT.getVectorElementType(); 7961 std::vector<Constant*> CV; 7962 if (EltVT == MVT::f64) { 7963 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7964 CV.push_back(C); 7965 CV.push_back(C); 7966 } else { 7967 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7968 CV.push_back(C); 7969 CV.push_back(C); 7970 CV.push_back(C); 7971 CV.push_back(C); 7972 } 7973 Constant *C = ConstantVector::get(CV); 7974 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7975 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7976 MachinePointerInfo::getConstantPool(), 7977 false, false, 16); 7978 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7979} 7980 7981SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7982 LLVMContext *Context = DAG.getContext(); 7983 DebugLoc dl = Op.getDebugLoc(); 7984 EVT VT = Op.getValueType(); 7985 EVT EltVT = VT; 7986 if (VT.isVector()) 7987 EltVT = VT.getVectorElementType(); 7988 std::vector<Constant*> CV; 7989 if (EltVT == MVT::f64) { 7990 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7991 CV.push_back(C); 7992 CV.push_back(C); 7993 } else { 7994 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7995 CV.push_back(C); 7996 CV.push_back(C); 7997 CV.push_back(C); 7998 CV.push_back(C); 7999 } 8000 Constant *C = ConstantVector::get(CV); 8001 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8002 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8003 MachinePointerInfo::getConstantPool(), 8004 false, false, 16); 8005 if (VT.isVector()) { 8006 return DAG.getNode(ISD::BITCAST, dl, VT, 8007 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 8008 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8009 Op.getOperand(0)), 8010 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 8011 } else { 8012 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8013 } 8014} 8015 8016SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8017 LLVMContext *Context = DAG.getContext(); 8018 SDValue Op0 = Op.getOperand(0); 8019 SDValue Op1 = Op.getOperand(1); 8020 DebugLoc dl = Op.getDebugLoc(); 8021 EVT VT = Op.getValueType(); 8022 EVT SrcVT = Op1.getValueType(); 8023 8024 // If second operand is smaller, extend it first. 8025 if (SrcVT.bitsLT(VT)) { 8026 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8027 SrcVT = VT; 8028 } 8029 // And if it is bigger, shrink it first. 8030 if (SrcVT.bitsGT(VT)) { 8031 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8032 SrcVT = VT; 8033 } 8034 8035 // At this point the operands and the result should have the same 8036 // type, and that won't be f80 since that is not custom lowered. 8037 8038 // First get the sign bit of second operand. 8039 std::vector<Constant*> CV; 8040 if (SrcVT == MVT::f64) { 8041 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8042 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8043 } else { 8044 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8045 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8046 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8047 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8048 } 8049 Constant *C = ConstantVector::get(CV); 8050 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8051 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8052 MachinePointerInfo::getConstantPool(), 8053 false, false, 16); 8054 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8055 8056 // Shift sign bit right or left if the two operands have different types. 8057 if (SrcVT.bitsGT(VT)) { 8058 // Op0 is MVT::f32, Op1 is MVT::f64. 8059 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8060 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8061 DAG.getConstant(32, MVT::i32)); 8062 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8063 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8064 DAG.getIntPtrConstant(0)); 8065 } 8066 8067 // Clear first operand sign bit. 8068 CV.clear(); 8069 if (VT == MVT::f64) { 8070 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8071 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8072 } else { 8073 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8074 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8075 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8076 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8077 } 8078 C = ConstantVector::get(CV); 8079 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8080 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8081 MachinePointerInfo::getConstantPool(), 8082 false, false, 16); 8083 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8084 8085 // Or the value with the sign bit. 8086 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8087} 8088 8089SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8090 SDValue N0 = Op.getOperand(0); 8091 DebugLoc dl = Op.getDebugLoc(); 8092 EVT VT = Op.getValueType(); 8093 8094 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8095 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8096 DAG.getConstant(1, VT)); 8097 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8098} 8099 8100/// Emit nodes that will be selected as "test Op0,Op0", or something 8101/// equivalent. 8102SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8103 SelectionDAG &DAG) const { 8104 DebugLoc dl = Op.getDebugLoc(); 8105 8106 // CF and OF aren't always set the way we want. Determine which 8107 // of these we need. 8108 bool NeedCF = false; 8109 bool NeedOF = false; 8110 switch (X86CC) { 8111 default: break; 8112 case X86::COND_A: case X86::COND_AE: 8113 case X86::COND_B: case X86::COND_BE: 8114 NeedCF = true; 8115 break; 8116 case X86::COND_G: case X86::COND_GE: 8117 case X86::COND_L: case X86::COND_LE: 8118 case X86::COND_O: case X86::COND_NO: 8119 NeedOF = true; 8120 break; 8121 } 8122 8123 // See if we can use the EFLAGS value from the operand instead of 8124 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8125 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8126 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8127 // Emit a CMP with 0, which is the TEST pattern. 8128 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8129 DAG.getConstant(0, Op.getValueType())); 8130 8131 unsigned Opcode = 0; 8132 unsigned NumOperands = 0; 8133 switch (Op.getNode()->getOpcode()) { 8134 case ISD::ADD: 8135 // Due to an isel shortcoming, be conservative if this add is likely to be 8136 // selected as part of a load-modify-store instruction. When the root node 8137 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8138 // uses of other nodes in the match, such as the ADD in this case. This 8139 // leads to the ADD being left around and reselected, with the result being 8140 // two adds in the output. Alas, even if none our users are stores, that 8141 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8142 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8143 // climbing the DAG back to the root, and it doesn't seem to be worth the 8144 // effort. 8145 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8146 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8147 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 8148 goto default_case; 8149 8150 if (ConstantSDNode *C = 8151 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8152 // An add of one will be selected as an INC. 8153 if (C->getAPIntValue() == 1) { 8154 Opcode = X86ISD::INC; 8155 NumOperands = 1; 8156 break; 8157 } 8158 8159 // An add of negative one (subtract of one) will be selected as a DEC. 8160 if (C->getAPIntValue().isAllOnesValue()) { 8161 Opcode = X86ISD::DEC; 8162 NumOperands = 1; 8163 break; 8164 } 8165 } 8166 8167 // Otherwise use a regular EFLAGS-setting add. 8168 Opcode = X86ISD::ADD; 8169 NumOperands = 2; 8170 break; 8171 case ISD::AND: { 8172 // If the primary and result isn't used, don't bother using X86ISD::AND, 8173 // because a TEST instruction will be better. 8174 bool NonFlagUse = false; 8175 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8176 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8177 SDNode *User = *UI; 8178 unsigned UOpNo = UI.getOperandNo(); 8179 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8180 // Look pass truncate. 8181 UOpNo = User->use_begin().getOperandNo(); 8182 User = *User->use_begin(); 8183 } 8184 8185 if (User->getOpcode() != ISD::BRCOND && 8186 User->getOpcode() != ISD::SETCC && 8187 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8188 NonFlagUse = true; 8189 break; 8190 } 8191 } 8192 8193 if (!NonFlagUse) 8194 break; 8195 } 8196 // FALL THROUGH 8197 case ISD::SUB: 8198 case ISD::OR: 8199 case ISD::XOR: 8200 // Due to the ISEL shortcoming noted above, be conservative if this op is 8201 // likely to be selected as part of a load-modify-store instruction. 8202 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8203 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8204 if (UI->getOpcode() == ISD::STORE) 8205 goto default_case; 8206 8207 // Otherwise use a regular EFLAGS-setting instruction. 8208 switch (Op.getNode()->getOpcode()) { 8209 default: llvm_unreachable("unexpected operator!"); 8210 case ISD::SUB: Opcode = X86ISD::SUB; break; 8211 case ISD::OR: Opcode = X86ISD::OR; break; 8212 case ISD::XOR: Opcode = X86ISD::XOR; break; 8213 case ISD::AND: Opcode = X86ISD::AND; break; 8214 } 8215 8216 NumOperands = 2; 8217 break; 8218 case X86ISD::ADD: 8219 case X86ISD::SUB: 8220 case X86ISD::INC: 8221 case X86ISD::DEC: 8222 case X86ISD::OR: 8223 case X86ISD::XOR: 8224 case X86ISD::AND: 8225 return SDValue(Op.getNode(), 1); 8226 default: 8227 default_case: 8228 break; 8229 } 8230 8231 if (Opcode == 0) 8232 // Emit a CMP with 0, which is the TEST pattern. 8233 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8234 DAG.getConstant(0, Op.getValueType())); 8235 8236 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8237 SmallVector<SDValue, 4> Ops; 8238 for (unsigned i = 0; i != NumOperands; ++i) 8239 Ops.push_back(Op.getOperand(i)); 8240 8241 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8242 DAG.ReplaceAllUsesWith(Op, New); 8243 return SDValue(New.getNode(), 1); 8244} 8245 8246/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8247/// equivalent. 8248SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8249 SelectionDAG &DAG) const { 8250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8251 if (C->getAPIntValue() == 0) 8252 return EmitTest(Op0, X86CC, DAG); 8253 8254 DebugLoc dl = Op0.getDebugLoc(); 8255 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8256} 8257 8258/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8259/// if it's possible. 8260SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8261 DebugLoc dl, SelectionDAG &DAG) const { 8262 SDValue Op0 = And.getOperand(0); 8263 SDValue Op1 = And.getOperand(1); 8264 if (Op0.getOpcode() == ISD::TRUNCATE) 8265 Op0 = Op0.getOperand(0); 8266 if (Op1.getOpcode() == ISD::TRUNCATE) 8267 Op1 = Op1.getOperand(0); 8268 8269 SDValue LHS, RHS; 8270 if (Op1.getOpcode() == ISD::SHL) 8271 std::swap(Op0, Op1); 8272 if (Op0.getOpcode() == ISD::SHL) { 8273 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8274 if (And00C->getZExtValue() == 1) { 8275 // If we looked past a truncate, check that it's only truncating away 8276 // known zeros. 8277 unsigned BitWidth = Op0.getValueSizeInBits(); 8278 unsigned AndBitWidth = And.getValueSizeInBits(); 8279 if (BitWidth > AndBitWidth) { 8280 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8281 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8282 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8283 return SDValue(); 8284 } 8285 LHS = Op1; 8286 RHS = Op0.getOperand(1); 8287 } 8288 } else if (Op1.getOpcode() == ISD::Constant) { 8289 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8290 SDValue AndLHS = Op0; 8291 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 8292 LHS = AndLHS.getOperand(0); 8293 RHS = AndLHS.getOperand(1); 8294 } 8295 } 8296 8297 if (LHS.getNode()) { 8298 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8299 // instruction. Since the shift amount is in-range-or-undefined, we know 8300 // that doing a bittest on the i32 value is ok. We extend to i32 because 8301 // the encoding for the i16 version is larger than the i32 version. 8302 // Also promote i16 to i32 for performance / code size reason. 8303 if (LHS.getValueType() == MVT::i8 || 8304 LHS.getValueType() == MVT::i16) 8305 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8306 8307 // If the operand types disagree, extend the shift amount to match. Since 8308 // BT ignores high bits (like shifts) we can use anyextend. 8309 if (LHS.getValueType() != RHS.getValueType()) 8310 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8311 8312 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8313 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8314 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8315 DAG.getConstant(Cond, MVT::i8), BT); 8316 } 8317 8318 return SDValue(); 8319} 8320 8321SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8322 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8323 SDValue Op0 = Op.getOperand(0); 8324 SDValue Op1 = Op.getOperand(1); 8325 DebugLoc dl = Op.getDebugLoc(); 8326 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8327 8328 // Optimize to BT if possible. 8329 // Lower (X & (1 << N)) == 0 to BT(X, N). 8330 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8331 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8332 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8333 Op1.getOpcode() == ISD::Constant && 8334 cast<ConstantSDNode>(Op1)->isNullValue() && 8335 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8336 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8337 if (NewSetCC.getNode()) 8338 return NewSetCC; 8339 } 8340 8341 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8342 // these. 8343 if (Op1.getOpcode() == ISD::Constant && 8344 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8345 cast<ConstantSDNode>(Op1)->isNullValue()) && 8346 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8347 8348 // If the input is a setcc, then reuse the input setcc or use a new one with 8349 // the inverted condition. 8350 if (Op0.getOpcode() == X86ISD::SETCC) { 8351 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8352 bool Invert = (CC == ISD::SETNE) ^ 8353 cast<ConstantSDNode>(Op1)->isNullValue(); 8354 if (!Invert) return Op0; 8355 8356 CCode = X86::GetOppositeBranchCondition(CCode); 8357 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8358 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8359 } 8360 } 8361 8362 bool isFP = Op1.getValueType().isFloatingPoint(); 8363 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8364 if (X86CC == X86::COND_INVALID) 8365 return SDValue(); 8366 8367 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8368 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8369 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8370} 8371 8372// Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8373// ones, and then concatenate the result back. 8374static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) { 8375 EVT VT = Op.getValueType(); 8376 8377 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC && 8378 "Unsupported value type for operation"); 8379 8380 int NumElems = VT.getVectorNumElements(); 8381 DebugLoc dl = Op.getDebugLoc(); 8382 SDValue CC = Op.getOperand(2); 8383 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8384 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8385 8386 // Extract the LHS vectors 8387 SDValue LHS = Op.getOperand(0); 8388 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8389 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8390 8391 // Extract the RHS vectors 8392 SDValue RHS = Op.getOperand(1); 8393 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8394 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8395 8396 // Issue the operation on the smaller types and concatenate the result back 8397 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8398 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8399 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8400 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8401 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8402} 8403 8404 8405SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8406 SDValue Cond; 8407 SDValue Op0 = Op.getOperand(0); 8408 SDValue Op1 = Op.getOperand(1); 8409 SDValue CC = Op.getOperand(2); 8410 EVT VT = Op.getValueType(); 8411 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8412 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8413 DebugLoc dl = Op.getDebugLoc(); 8414 8415 if (isFP) { 8416 unsigned SSECC = 8; 8417 EVT EltVT = Op0.getValueType().getVectorElementType(); 8418 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8419 8420 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8421 bool Swap = false; 8422 8423 switch (SetCCOpcode) { 8424 default: break; 8425 case ISD::SETOEQ: 8426 case ISD::SETEQ: SSECC = 0; break; 8427 case ISD::SETOGT: 8428 case ISD::SETGT: Swap = true; // Fallthrough 8429 case ISD::SETLT: 8430 case ISD::SETOLT: SSECC = 1; break; 8431 case ISD::SETOGE: 8432 case ISD::SETGE: Swap = true; // Fallthrough 8433 case ISD::SETLE: 8434 case ISD::SETOLE: SSECC = 2; break; 8435 case ISD::SETUO: SSECC = 3; break; 8436 case ISD::SETUNE: 8437 case ISD::SETNE: SSECC = 4; break; 8438 case ISD::SETULE: Swap = true; 8439 case ISD::SETUGE: SSECC = 5; break; 8440 case ISD::SETULT: Swap = true; 8441 case ISD::SETUGT: SSECC = 6; break; 8442 case ISD::SETO: SSECC = 7; break; 8443 } 8444 if (Swap) 8445 std::swap(Op0, Op1); 8446 8447 // In the two special cases we can't handle, emit two comparisons. 8448 if (SSECC == 8) { 8449 if (SetCCOpcode == ISD::SETUEQ) { 8450 SDValue UNORD, EQ; 8451 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8452 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8453 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8454 } 8455 else if (SetCCOpcode == ISD::SETONE) { 8456 SDValue ORD, NEQ; 8457 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8458 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8459 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8460 } 8461 llvm_unreachable("Illegal FP comparison"); 8462 } 8463 // Handle all other FP comparisons here. 8464 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8465 } 8466 8467 // Break 256-bit integer vector compare into smaller ones. 8468 if (!isFP && VT.getSizeInBits() == 256) 8469 return Lower256IntVETCC(Op, DAG); 8470 8471 // We are handling one of the integer comparisons here. Since SSE only has 8472 // GT and EQ comparisons for integer, swapping operands and multiple 8473 // operations may be required for some comparisons. 8474 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8475 bool Swap = false, Invert = false, FlipSigns = false; 8476 8477 switch (VT.getSimpleVT().SimpleTy) { 8478 default: break; 8479 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8480 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8481 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8482 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8483 } 8484 8485 switch (SetCCOpcode) { 8486 default: break; 8487 case ISD::SETNE: Invert = true; 8488 case ISD::SETEQ: Opc = EQOpc; break; 8489 case ISD::SETLT: Swap = true; 8490 case ISD::SETGT: Opc = GTOpc; break; 8491 case ISD::SETGE: Swap = true; 8492 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8493 case ISD::SETULT: Swap = true; 8494 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8495 case ISD::SETUGE: Swap = true; 8496 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8497 } 8498 if (Swap) 8499 std::swap(Op0, Op1); 8500 8501 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8502 // bits of the inputs before performing those operations. 8503 if (FlipSigns) { 8504 EVT EltVT = VT.getVectorElementType(); 8505 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8506 EltVT); 8507 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8508 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8509 SignBits.size()); 8510 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8511 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8512 } 8513 8514 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8515 8516 // If the logical-not of the result is required, perform that now. 8517 if (Invert) 8518 Result = DAG.getNOT(dl, Result, VT); 8519 8520 return Result; 8521} 8522 8523// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8524static bool isX86LogicalCmp(SDValue Op) { 8525 unsigned Opc = Op.getNode()->getOpcode(); 8526 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8527 return true; 8528 if (Op.getResNo() == 1 && 8529 (Opc == X86ISD::ADD || 8530 Opc == X86ISD::SUB || 8531 Opc == X86ISD::ADC || 8532 Opc == X86ISD::SBB || 8533 Opc == X86ISD::SMUL || 8534 Opc == X86ISD::UMUL || 8535 Opc == X86ISD::INC || 8536 Opc == X86ISD::DEC || 8537 Opc == X86ISD::OR || 8538 Opc == X86ISD::XOR || 8539 Opc == X86ISD::AND)) 8540 return true; 8541 8542 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8543 return true; 8544 8545 return false; 8546} 8547 8548static bool isZero(SDValue V) { 8549 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8550 return C && C->isNullValue(); 8551} 8552 8553static bool isAllOnes(SDValue V) { 8554 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8555 return C && C->isAllOnesValue(); 8556} 8557 8558SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8559 bool addTest = true; 8560 SDValue Cond = Op.getOperand(0); 8561 SDValue Op1 = Op.getOperand(1); 8562 SDValue Op2 = Op.getOperand(2); 8563 DebugLoc DL = Op.getDebugLoc(); 8564 SDValue CC; 8565 8566 if (Cond.getOpcode() == ISD::SETCC) { 8567 SDValue NewCond = LowerSETCC(Cond, DAG); 8568 if (NewCond.getNode()) 8569 Cond = NewCond; 8570 } 8571 8572 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8573 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8574 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8575 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8576 if (Cond.getOpcode() == X86ISD::SETCC && 8577 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8578 isZero(Cond.getOperand(1).getOperand(1))) { 8579 SDValue Cmp = Cond.getOperand(1); 8580 8581 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8582 8583 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8584 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8585 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8586 8587 SDValue CmpOp0 = Cmp.getOperand(0); 8588 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8589 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8590 8591 SDValue Res = // Res = 0 or -1. 8592 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8593 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8594 8595 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8596 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8597 8598 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8599 if (N2C == 0 || !N2C->isNullValue()) 8600 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8601 return Res; 8602 } 8603 } 8604 8605 // Look past (and (setcc_carry (cmp ...)), 1). 8606 if (Cond.getOpcode() == ISD::AND && 8607 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8608 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8609 if (C && C->getAPIntValue() == 1) 8610 Cond = Cond.getOperand(0); 8611 } 8612 8613 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8614 // setting operand in place of the X86ISD::SETCC. 8615 if (Cond.getOpcode() == X86ISD::SETCC || 8616 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8617 CC = Cond.getOperand(0); 8618 8619 SDValue Cmp = Cond.getOperand(1); 8620 unsigned Opc = Cmp.getOpcode(); 8621 EVT VT = Op.getValueType(); 8622 8623 bool IllegalFPCMov = false; 8624 if (VT.isFloatingPoint() && !VT.isVector() && 8625 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8626 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8627 8628 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8629 Opc == X86ISD::BT) { // FIXME 8630 Cond = Cmp; 8631 addTest = false; 8632 } 8633 } 8634 8635 if (addTest) { 8636 // Look pass the truncate. 8637 if (Cond.getOpcode() == ISD::TRUNCATE) 8638 Cond = Cond.getOperand(0); 8639 8640 // We know the result of AND is compared against zero. Try to match 8641 // it to BT. 8642 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8643 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8644 if (NewSetCC.getNode()) { 8645 CC = NewSetCC.getOperand(0); 8646 Cond = NewSetCC.getOperand(1); 8647 addTest = false; 8648 } 8649 } 8650 } 8651 8652 if (addTest) { 8653 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8654 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8655 } 8656 8657 // a < b ? -1 : 0 -> RES = ~setcc_carry 8658 // a < b ? 0 : -1 -> RES = setcc_carry 8659 // a >= b ? -1 : 0 -> RES = setcc_carry 8660 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8661 if (Cond.getOpcode() == X86ISD::CMP) { 8662 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8663 8664 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8665 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8666 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8667 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8668 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8669 return DAG.getNOT(DL, Res, Res.getValueType()); 8670 return Res; 8671 } 8672 } 8673 8674 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8675 // condition is true. 8676 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8677 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8678 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8679} 8680 8681// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8682// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8683// from the AND / OR. 8684static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8685 Opc = Op.getOpcode(); 8686 if (Opc != ISD::OR && Opc != ISD::AND) 8687 return false; 8688 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8689 Op.getOperand(0).hasOneUse() && 8690 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8691 Op.getOperand(1).hasOneUse()); 8692} 8693 8694// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8695// 1 and that the SETCC node has a single use. 8696static bool isXor1OfSetCC(SDValue Op) { 8697 if (Op.getOpcode() != ISD::XOR) 8698 return false; 8699 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8700 if (N1C && N1C->getAPIntValue() == 1) { 8701 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8702 Op.getOperand(0).hasOneUse(); 8703 } 8704 return false; 8705} 8706 8707SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8708 bool addTest = true; 8709 SDValue Chain = Op.getOperand(0); 8710 SDValue Cond = Op.getOperand(1); 8711 SDValue Dest = Op.getOperand(2); 8712 DebugLoc dl = Op.getDebugLoc(); 8713 SDValue CC; 8714 8715 if (Cond.getOpcode() == ISD::SETCC) { 8716 SDValue NewCond = LowerSETCC(Cond, DAG); 8717 if (NewCond.getNode()) 8718 Cond = NewCond; 8719 } 8720#if 0 8721 // FIXME: LowerXALUO doesn't handle these!! 8722 else if (Cond.getOpcode() == X86ISD::ADD || 8723 Cond.getOpcode() == X86ISD::SUB || 8724 Cond.getOpcode() == X86ISD::SMUL || 8725 Cond.getOpcode() == X86ISD::UMUL) 8726 Cond = LowerXALUO(Cond, DAG); 8727#endif 8728 8729 // Look pass (and (setcc_carry (cmp ...)), 1). 8730 if (Cond.getOpcode() == ISD::AND && 8731 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8732 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8733 if (C && C->getAPIntValue() == 1) 8734 Cond = Cond.getOperand(0); 8735 } 8736 8737 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8738 // setting operand in place of the X86ISD::SETCC. 8739 if (Cond.getOpcode() == X86ISD::SETCC || 8740 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8741 CC = Cond.getOperand(0); 8742 8743 SDValue Cmp = Cond.getOperand(1); 8744 unsigned Opc = Cmp.getOpcode(); 8745 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8746 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8747 Cond = Cmp; 8748 addTest = false; 8749 } else { 8750 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8751 default: break; 8752 case X86::COND_O: 8753 case X86::COND_B: 8754 // These can only come from an arithmetic instruction with overflow, 8755 // e.g. SADDO, UADDO. 8756 Cond = Cond.getNode()->getOperand(1); 8757 addTest = false; 8758 break; 8759 } 8760 } 8761 } else { 8762 unsigned CondOpc; 8763 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8764 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8765 if (CondOpc == ISD::OR) { 8766 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8767 // two branches instead of an explicit OR instruction with a 8768 // separate test. 8769 if (Cmp == Cond.getOperand(1).getOperand(1) && 8770 isX86LogicalCmp(Cmp)) { 8771 CC = Cond.getOperand(0).getOperand(0); 8772 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8773 Chain, Dest, CC, Cmp); 8774 CC = Cond.getOperand(1).getOperand(0); 8775 Cond = Cmp; 8776 addTest = false; 8777 } 8778 } else { // ISD::AND 8779 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8780 // two branches instead of an explicit AND instruction with a 8781 // separate test. However, we only do this if this block doesn't 8782 // have a fall-through edge, because this requires an explicit 8783 // jmp when the condition is false. 8784 if (Cmp == Cond.getOperand(1).getOperand(1) && 8785 isX86LogicalCmp(Cmp) && 8786 Op.getNode()->hasOneUse()) { 8787 X86::CondCode CCode = 8788 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8789 CCode = X86::GetOppositeBranchCondition(CCode); 8790 CC = DAG.getConstant(CCode, MVT::i8); 8791 SDNode *User = *Op.getNode()->use_begin(); 8792 // Look for an unconditional branch following this conditional branch. 8793 // We need this because we need to reverse the successors in order 8794 // to implement FCMP_OEQ. 8795 if (User->getOpcode() == ISD::BR) { 8796 SDValue FalseBB = User->getOperand(1); 8797 SDNode *NewBR = 8798 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8799 assert(NewBR == User); 8800 (void)NewBR; 8801 Dest = FalseBB; 8802 8803 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8804 Chain, Dest, CC, Cmp); 8805 X86::CondCode CCode = 8806 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8807 CCode = X86::GetOppositeBranchCondition(CCode); 8808 CC = DAG.getConstant(CCode, MVT::i8); 8809 Cond = Cmp; 8810 addTest = false; 8811 } 8812 } 8813 } 8814 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8815 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8816 // It should be transformed during dag combiner except when the condition 8817 // is set by a arithmetics with overflow node. 8818 X86::CondCode CCode = 8819 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8820 CCode = X86::GetOppositeBranchCondition(CCode); 8821 CC = DAG.getConstant(CCode, MVT::i8); 8822 Cond = Cond.getOperand(0).getOperand(1); 8823 addTest = false; 8824 } 8825 } 8826 8827 if (addTest) { 8828 // Look pass the truncate. 8829 if (Cond.getOpcode() == ISD::TRUNCATE) 8830 Cond = Cond.getOperand(0); 8831 8832 // We know the result of AND is compared against zero. Try to match 8833 // it to BT. 8834 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8835 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8836 if (NewSetCC.getNode()) { 8837 CC = NewSetCC.getOperand(0); 8838 Cond = NewSetCC.getOperand(1); 8839 addTest = false; 8840 } 8841 } 8842 } 8843 8844 if (addTest) { 8845 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8846 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8847 } 8848 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8849 Chain, Dest, CC, Cond); 8850} 8851 8852 8853// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8854// Calls to _alloca is needed to probe the stack when allocating more than 4k 8855// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8856// that the guard pages used by the OS virtual memory manager are allocated in 8857// correct sequence. 8858SDValue 8859X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8860 SelectionDAG &DAG) const { 8861 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8862 EnableSegmentedStacks) && 8863 "This should be used only on Windows targets or when segmented stacks " 8864 "are being used"); 8865 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8866 DebugLoc dl = Op.getDebugLoc(); 8867 8868 // Get the inputs. 8869 SDValue Chain = Op.getOperand(0); 8870 SDValue Size = Op.getOperand(1); 8871 // FIXME: Ensure alignment here 8872 8873 bool Is64Bit = Subtarget->is64Bit(); 8874 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8875 8876 if (EnableSegmentedStacks) { 8877 MachineFunction &MF = DAG.getMachineFunction(); 8878 MachineRegisterInfo &MRI = MF.getRegInfo(); 8879 8880 if (Is64Bit) { 8881 // The 64 bit implementation of segmented stacks needs to clobber both r10 8882 // r11. This makes it impossible to use it along with nested parameters. 8883 const Function *F = MF.getFunction(); 8884 8885 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8886 I != E; I++) 8887 if (I->hasNestAttr()) 8888 report_fatal_error("Cannot use segmented stacks with functions that " 8889 "have nested arguments."); 8890 } 8891 8892 const TargetRegisterClass *AddrRegClass = 8893 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8894 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8895 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8896 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8897 DAG.getRegister(Vreg, SPTy)); 8898 SDValue Ops1[2] = { Value, Chain }; 8899 return DAG.getMergeValues(Ops1, 2, dl); 8900 } else { 8901 SDValue Flag; 8902 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8903 8904 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8905 Flag = Chain.getValue(1); 8906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8907 8908 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8909 Flag = Chain.getValue(1); 8910 8911 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8912 8913 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8914 return DAG.getMergeValues(Ops1, 2, dl); 8915 } 8916} 8917 8918SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8919 MachineFunction &MF = DAG.getMachineFunction(); 8920 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8921 8922 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8923 DebugLoc DL = Op.getDebugLoc(); 8924 8925 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8926 // vastart just stores the address of the VarArgsFrameIndex slot into the 8927 // memory location argument. 8928 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8929 getPointerTy()); 8930 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8931 MachinePointerInfo(SV), false, false, 0); 8932 } 8933 8934 // __va_list_tag: 8935 // gp_offset (0 - 6 * 8) 8936 // fp_offset (48 - 48 + 8 * 16) 8937 // overflow_arg_area (point to parameters coming in memory). 8938 // reg_save_area 8939 SmallVector<SDValue, 8> MemOps; 8940 SDValue FIN = Op.getOperand(1); 8941 // Store gp_offset 8942 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8943 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8944 MVT::i32), 8945 FIN, MachinePointerInfo(SV), false, false, 0); 8946 MemOps.push_back(Store); 8947 8948 // Store fp_offset 8949 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8950 FIN, DAG.getIntPtrConstant(4)); 8951 Store = DAG.getStore(Op.getOperand(0), DL, 8952 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8953 MVT::i32), 8954 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8955 MemOps.push_back(Store); 8956 8957 // Store ptr to overflow_arg_area 8958 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8959 FIN, DAG.getIntPtrConstant(4)); 8960 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8961 getPointerTy()); 8962 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8963 MachinePointerInfo(SV, 8), 8964 false, false, 0); 8965 MemOps.push_back(Store); 8966 8967 // Store ptr to reg_save_area. 8968 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8969 FIN, DAG.getIntPtrConstant(8)); 8970 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 8971 getPointerTy()); 8972 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 8973 MachinePointerInfo(SV, 16), false, false, 0); 8974 MemOps.push_back(Store); 8975 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 8976 &MemOps[0], MemOps.size()); 8977} 8978 8979SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 8980 assert(Subtarget->is64Bit() && 8981 "LowerVAARG only handles 64-bit va_arg!"); 8982 assert((Subtarget->isTargetLinux() || 8983 Subtarget->isTargetDarwin()) && 8984 "Unhandled target in LowerVAARG"); 8985 assert(Op.getNode()->getNumOperands() == 4); 8986 SDValue Chain = Op.getOperand(0); 8987 SDValue SrcPtr = Op.getOperand(1); 8988 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8989 unsigned Align = Op.getConstantOperandVal(3); 8990 DebugLoc dl = Op.getDebugLoc(); 8991 8992 EVT ArgVT = Op.getNode()->getValueType(0); 8993 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 8994 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 8995 uint8_t ArgMode; 8996 8997 // Decide which area this value should be read from. 8998 // TODO: Implement the AMD64 ABI in its entirety. This simple 8999 // selection mechanism works only for the basic types. 9000 if (ArgVT == MVT::f80) { 9001 llvm_unreachable("va_arg for f80 not yet implemented"); 9002 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9003 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9004 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9005 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9006 } else { 9007 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9008 } 9009 9010 if (ArgMode == 2) { 9011 // Sanity Check: Make sure using fp_offset makes sense. 9012 assert(!UseSoftFloat && 9013 !(DAG.getMachineFunction() 9014 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9015 Subtarget->hasXMM()); 9016 } 9017 9018 // Insert VAARG_64 node into the DAG 9019 // VAARG_64 returns two values: Variable Argument Address, Chain 9020 SmallVector<SDValue, 11> InstOps; 9021 InstOps.push_back(Chain); 9022 InstOps.push_back(SrcPtr); 9023 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9024 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9025 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9026 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9027 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9028 VTs, &InstOps[0], InstOps.size(), 9029 MVT::i64, 9030 MachinePointerInfo(SV), 9031 /*Align=*/0, 9032 /*Volatile=*/false, 9033 /*ReadMem=*/true, 9034 /*WriteMem=*/true); 9035 Chain = VAARG.getValue(1); 9036 9037 // Load the next argument and return it 9038 return DAG.getLoad(ArgVT, dl, 9039 Chain, 9040 VAARG, 9041 MachinePointerInfo(), 9042 false, false, 0); 9043} 9044 9045SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9046 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9047 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9048 SDValue Chain = Op.getOperand(0); 9049 SDValue DstPtr = Op.getOperand(1); 9050 SDValue SrcPtr = Op.getOperand(2); 9051 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9052 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9053 DebugLoc DL = Op.getDebugLoc(); 9054 9055 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9056 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9057 false, 9058 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9059} 9060 9061SDValue 9062X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9063 DebugLoc dl = Op.getDebugLoc(); 9064 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9065 switch (IntNo) { 9066 default: return SDValue(); // Don't custom lower most intrinsics. 9067 // Comparison intrinsics. 9068 case Intrinsic::x86_sse_comieq_ss: 9069 case Intrinsic::x86_sse_comilt_ss: 9070 case Intrinsic::x86_sse_comile_ss: 9071 case Intrinsic::x86_sse_comigt_ss: 9072 case Intrinsic::x86_sse_comige_ss: 9073 case Intrinsic::x86_sse_comineq_ss: 9074 case Intrinsic::x86_sse_ucomieq_ss: 9075 case Intrinsic::x86_sse_ucomilt_ss: 9076 case Intrinsic::x86_sse_ucomile_ss: 9077 case Intrinsic::x86_sse_ucomigt_ss: 9078 case Intrinsic::x86_sse_ucomige_ss: 9079 case Intrinsic::x86_sse_ucomineq_ss: 9080 case Intrinsic::x86_sse2_comieq_sd: 9081 case Intrinsic::x86_sse2_comilt_sd: 9082 case Intrinsic::x86_sse2_comile_sd: 9083 case Intrinsic::x86_sse2_comigt_sd: 9084 case Intrinsic::x86_sse2_comige_sd: 9085 case Intrinsic::x86_sse2_comineq_sd: 9086 case Intrinsic::x86_sse2_ucomieq_sd: 9087 case Intrinsic::x86_sse2_ucomilt_sd: 9088 case Intrinsic::x86_sse2_ucomile_sd: 9089 case Intrinsic::x86_sse2_ucomigt_sd: 9090 case Intrinsic::x86_sse2_ucomige_sd: 9091 case Intrinsic::x86_sse2_ucomineq_sd: { 9092 unsigned Opc = 0; 9093 ISD::CondCode CC = ISD::SETCC_INVALID; 9094 switch (IntNo) { 9095 default: break; 9096 case Intrinsic::x86_sse_comieq_ss: 9097 case Intrinsic::x86_sse2_comieq_sd: 9098 Opc = X86ISD::COMI; 9099 CC = ISD::SETEQ; 9100 break; 9101 case Intrinsic::x86_sse_comilt_ss: 9102 case Intrinsic::x86_sse2_comilt_sd: 9103 Opc = X86ISD::COMI; 9104 CC = ISD::SETLT; 9105 break; 9106 case Intrinsic::x86_sse_comile_ss: 9107 case Intrinsic::x86_sse2_comile_sd: 9108 Opc = X86ISD::COMI; 9109 CC = ISD::SETLE; 9110 break; 9111 case Intrinsic::x86_sse_comigt_ss: 9112 case Intrinsic::x86_sse2_comigt_sd: 9113 Opc = X86ISD::COMI; 9114 CC = ISD::SETGT; 9115 break; 9116 case Intrinsic::x86_sse_comige_ss: 9117 case Intrinsic::x86_sse2_comige_sd: 9118 Opc = X86ISD::COMI; 9119 CC = ISD::SETGE; 9120 break; 9121 case Intrinsic::x86_sse_comineq_ss: 9122 case Intrinsic::x86_sse2_comineq_sd: 9123 Opc = X86ISD::COMI; 9124 CC = ISD::SETNE; 9125 break; 9126 case Intrinsic::x86_sse_ucomieq_ss: 9127 case Intrinsic::x86_sse2_ucomieq_sd: 9128 Opc = X86ISD::UCOMI; 9129 CC = ISD::SETEQ; 9130 break; 9131 case Intrinsic::x86_sse_ucomilt_ss: 9132 case Intrinsic::x86_sse2_ucomilt_sd: 9133 Opc = X86ISD::UCOMI; 9134 CC = ISD::SETLT; 9135 break; 9136 case Intrinsic::x86_sse_ucomile_ss: 9137 case Intrinsic::x86_sse2_ucomile_sd: 9138 Opc = X86ISD::UCOMI; 9139 CC = ISD::SETLE; 9140 break; 9141 case Intrinsic::x86_sse_ucomigt_ss: 9142 case Intrinsic::x86_sse2_ucomigt_sd: 9143 Opc = X86ISD::UCOMI; 9144 CC = ISD::SETGT; 9145 break; 9146 case Intrinsic::x86_sse_ucomige_ss: 9147 case Intrinsic::x86_sse2_ucomige_sd: 9148 Opc = X86ISD::UCOMI; 9149 CC = ISD::SETGE; 9150 break; 9151 case Intrinsic::x86_sse_ucomineq_ss: 9152 case Intrinsic::x86_sse2_ucomineq_sd: 9153 Opc = X86ISD::UCOMI; 9154 CC = ISD::SETNE; 9155 break; 9156 } 9157 9158 SDValue LHS = Op.getOperand(1); 9159 SDValue RHS = Op.getOperand(2); 9160 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9161 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9162 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9163 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9164 DAG.getConstant(X86CC, MVT::i8), Cond); 9165 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9166 } 9167 // ptest and testp intrinsics. The intrinsic these come from are designed to 9168 // return an integer value, not just an instruction so lower it to the ptest 9169 // or testp pattern and a setcc for the result. 9170 case Intrinsic::x86_sse41_ptestz: 9171 case Intrinsic::x86_sse41_ptestc: 9172 case Intrinsic::x86_sse41_ptestnzc: 9173 case Intrinsic::x86_avx_ptestz_256: 9174 case Intrinsic::x86_avx_ptestc_256: 9175 case Intrinsic::x86_avx_ptestnzc_256: 9176 case Intrinsic::x86_avx_vtestz_ps: 9177 case Intrinsic::x86_avx_vtestc_ps: 9178 case Intrinsic::x86_avx_vtestnzc_ps: 9179 case Intrinsic::x86_avx_vtestz_pd: 9180 case Intrinsic::x86_avx_vtestc_pd: 9181 case Intrinsic::x86_avx_vtestnzc_pd: 9182 case Intrinsic::x86_avx_vtestz_ps_256: 9183 case Intrinsic::x86_avx_vtestc_ps_256: 9184 case Intrinsic::x86_avx_vtestnzc_ps_256: 9185 case Intrinsic::x86_avx_vtestz_pd_256: 9186 case Intrinsic::x86_avx_vtestc_pd_256: 9187 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9188 bool IsTestPacked = false; 9189 unsigned X86CC = 0; 9190 switch (IntNo) { 9191 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9192 case Intrinsic::x86_avx_vtestz_ps: 9193 case Intrinsic::x86_avx_vtestz_pd: 9194 case Intrinsic::x86_avx_vtestz_ps_256: 9195 case Intrinsic::x86_avx_vtestz_pd_256: 9196 IsTestPacked = true; // Fallthrough 9197 case Intrinsic::x86_sse41_ptestz: 9198 case Intrinsic::x86_avx_ptestz_256: 9199 // ZF = 1 9200 X86CC = X86::COND_E; 9201 break; 9202 case Intrinsic::x86_avx_vtestc_ps: 9203 case Intrinsic::x86_avx_vtestc_pd: 9204 case Intrinsic::x86_avx_vtestc_ps_256: 9205 case Intrinsic::x86_avx_vtestc_pd_256: 9206 IsTestPacked = true; // Fallthrough 9207 case Intrinsic::x86_sse41_ptestc: 9208 case Intrinsic::x86_avx_ptestc_256: 9209 // CF = 1 9210 X86CC = X86::COND_B; 9211 break; 9212 case Intrinsic::x86_avx_vtestnzc_ps: 9213 case Intrinsic::x86_avx_vtestnzc_pd: 9214 case Intrinsic::x86_avx_vtestnzc_ps_256: 9215 case Intrinsic::x86_avx_vtestnzc_pd_256: 9216 IsTestPacked = true; // Fallthrough 9217 case Intrinsic::x86_sse41_ptestnzc: 9218 case Intrinsic::x86_avx_ptestnzc_256: 9219 // ZF and CF = 0 9220 X86CC = X86::COND_A; 9221 break; 9222 } 9223 9224 SDValue LHS = Op.getOperand(1); 9225 SDValue RHS = Op.getOperand(2); 9226 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9227 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9228 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9229 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9230 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9231 } 9232 9233 // Fix vector shift instructions where the last operand is a non-immediate 9234 // i32 value. 9235 case Intrinsic::x86_sse2_pslli_w: 9236 case Intrinsic::x86_sse2_pslli_d: 9237 case Intrinsic::x86_sse2_pslli_q: 9238 case Intrinsic::x86_sse2_psrli_w: 9239 case Intrinsic::x86_sse2_psrli_d: 9240 case Intrinsic::x86_sse2_psrli_q: 9241 case Intrinsic::x86_sse2_psrai_w: 9242 case Intrinsic::x86_sse2_psrai_d: 9243 case Intrinsic::x86_mmx_pslli_w: 9244 case Intrinsic::x86_mmx_pslli_d: 9245 case Intrinsic::x86_mmx_pslli_q: 9246 case Intrinsic::x86_mmx_psrli_w: 9247 case Intrinsic::x86_mmx_psrli_d: 9248 case Intrinsic::x86_mmx_psrli_q: 9249 case Intrinsic::x86_mmx_psrai_w: 9250 case Intrinsic::x86_mmx_psrai_d: { 9251 SDValue ShAmt = Op.getOperand(2); 9252 if (isa<ConstantSDNode>(ShAmt)) 9253 return SDValue(); 9254 9255 unsigned NewIntNo = 0; 9256 EVT ShAmtVT = MVT::v4i32; 9257 switch (IntNo) { 9258 case Intrinsic::x86_sse2_pslli_w: 9259 NewIntNo = Intrinsic::x86_sse2_psll_w; 9260 break; 9261 case Intrinsic::x86_sse2_pslli_d: 9262 NewIntNo = Intrinsic::x86_sse2_psll_d; 9263 break; 9264 case Intrinsic::x86_sse2_pslli_q: 9265 NewIntNo = Intrinsic::x86_sse2_psll_q; 9266 break; 9267 case Intrinsic::x86_sse2_psrli_w: 9268 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9269 break; 9270 case Intrinsic::x86_sse2_psrli_d: 9271 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9272 break; 9273 case Intrinsic::x86_sse2_psrli_q: 9274 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9275 break; 9276 case Intrinsic::x86_sse2_psrai_w: 9277 NewIntNo = Intrinsic::x86_sse2_psra_w; 9278 break; 9279 case Intrinsic::x86_sse2_psrai_d: 9280 NewIntNo = Intrinsic::x86_sse2_psra_d; 9281 break; 9282 default: { 9283 ShAmtVT = MVT::v2i32; 9284 switch (IntNo) { 9285 case Intrinsic::x86_mmx_pslli_w: 9286 NewIntNo = Intrinsic::x86_mmx_psll_w; 9287 break; 9288 case Intrinsic::x86_mmx_pslli_d: 9289 NewIntNo = Intrinsic::x86_mmx_psll_d; 9290 break; 9291 case Intrinsic::x86_mmx_pslli_q: 9292 NewIntNo = Intrinsic::x86_mmx_psll_q; 9293 break; 9294 case Intrinsic::x86_mmx_psrli_w: 9295 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9296 break; 9297 case Intrinsic::x86_mmx_psrli_d: 9298 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9299 break; 9300 case Intrinsic::x86_mmx_psrli_q: 9301 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9302 break; 9303 case Intrinsic::x86_mmx_psrai_w: 9304 NewIntNo = Intrinsic::x86_mmx_psra_w; 9305 break; 9306 case Intrinsic::x86_mmx_psrai_d: 9307 NewIntNo = Intrinsic::x86_mmx_psra_d; 9308 break; 9309 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9310 } 9311 break; 9312 } 9313 } 9314 9315 // The vector shift intrinsics with scalars uses 32b shift amounts but 9316 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9317 // to be zero. 9318 SDValue ShOps[4]; 9319 ShOps[0] = ShAmt; 9320 ShOps[1] = DAG.getConstant(0, MVT::i32); 9321 if (ShAmtVT == MVT::v4i32) { 9322 ShOps[2] = DAG.getUNDEF(MVT::i32); 9323 ShOps[3] = DAG.getUNDEF(MVT::i32); 9324 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9325 } else { 9326 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9327// FIXME this must be lowered to get rid of the invalid type. 9328 } 9329 9330 EVT VT = Op.getValueType(); 9331 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9332 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9333 DAG.getConstant(NewIntNo, MVT::i32), 9334 Op.getOperand(1), ShAmt); 9335 } 9336 } 9337} 9338 9339SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9340 SelectionDAG &DAG) const { 9341 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9342 MFI->setReturnAddressIsTaken(true); 9343 9344 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9345 DebugLoc dl = Op.getDebugLoc(); 9346 9347 if (Depth > 0) { 9348 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9349 SDValue Offset = 9350 DAG.getConstant(TD->getPointerSize(), 9351 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9352 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9353 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9354 FrameAddr, Offset), 9355 MachinePointerInfo(), false, false, 0); 9356 } 9357 9358 // Just load the return address. 9359 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9360 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9361 RetAddrFI, MachinePointerInfo(), false, false, 0); 9362} 9363 9364SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9365 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9366 MFI->setFrameAddressIsTaken(true); 9367 9368 EVT VT = Op.getValueType(); 9369 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9370 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9371 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9372 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9373 while (Depth--) 9374 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9375 MachinePointerInfo(), 9376 false, false, 0); 9377 return FrameAddr; 9378} 9379 9380SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9381 SelectionDAG &DAG) const { 9382 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9383} 9384 9385SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9386 MachineFunction &MF = DAG.getMachineFunction(); 9387 SDValue Chain = Op.getOperand(0); 9388 SDValue Offset = Op.getOperand(1); 9389 SDValue Handler = Op.getOperand(2); 9390 DebugLoc dl = Op.getDebugLoc(); 9391 9392 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9393 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9394 getPointerTy()); 9395 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9396 9397 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9398 DAG.getIntPtrConstant(TD->getPointerSize())); 9399 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9400 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9401 false, false, 0); 9402 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9403 MF.getRegInfo().addLiveOut(StoreAddrReg); 9404 9405 return DAG.getNode(X86ISD::EH_RETURN, dl, 9406 MVT::Other, 9407 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9408} 9409 9410SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9411 SelectionDAG &DAG) const { 9412 return Op.getOperand(0); 9413} 9414 9415SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9416 SelectionDAG &DAG) const { 9417 SDValue Root = Op.getOperand(0); 9418 SDValue Trmp = Op.getOperand(1); // trampoline 9419 SDValue FPtr = Op.getOperand(2); // nested function 9420 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9421 DebugLoc dl = Op.getDebugLoc(); 9422 9423 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9424 9425 if (Subtarget->is64Bit()) { 9426 SDValue OutChains[6]; 9427 9428 // Large code-model. 9429 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9430 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9431 9432 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9433 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9434 9435 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9436 9437 // Load the pointer to the nested function into R11. 9438 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9439 SDValue Addr = Trmp; 9440 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9441 Addr, MachinePointerInfo(TrmpAddr), 9442 false, false, 0); 9443 9444 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9445 DAG.getConstant(2, MVT::i64)); 9446 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9447 MachinePointerInfo(TrmpAddr, 2), 9448 false, false, 2); 9449 9450 // Load the 'nest' parameter value into R10. 9451 // R10 is specified in X86CallingConv.td 9452 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9453 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9454 DAG.getConstant(10, MVT::i64)); 9455 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9456 Addr, MachinePointerInfo(TrmpAddr, 10), 9457 false, false, 0); 9458 9459 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9460 DAG.getConstant(12, MVT::i64)); 9461 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9462 MachinePointerInfo(TrmpAddr, 12), 9463 false, false, 2); 9464 9465 // Jump to the nested function. 9466 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9468 DAG.getConstant(20, MVT::i64)); 9469 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9470 Addr, MachinePointerInfo(TrmpAddr, 20), 9471 false, false, 0); 9472 9473 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9474 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9475 DAG.getConstant(22, MVT::i64)); 9476 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9477 MachinePointerInfo(TrmpAddr, 22), 9478 false, false, 0); 9479 9480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9481 } else { 9482 const Function *Func = 9483 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9484 CallingConv::ID CC = Func->getCallingConv(); 9485 unsigned NestReg; 9486 9487 switch (CC) { 9488 default: 9489 llvm_unreachable("Unsupported calling convention"); 9490 case CallingConv::C: 9491 case CallingConv::X86_StdCall: { 9492 // Pass 'nest' parameter in ECX. 9493 // Must be kept in sync with X86CallingConv.td 9494 NestReg = X86::ECX; 9495 9496 // Check that ECX wasn't needed by an 'inreg' parameter. 9497 FunctionType *FTy = Func->getFunctionType(); 9498 const AttrListPtr &Attrs = Func->getAttributes(); 9499 9500 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9501 unsigned InRegCount = 0; 9502 unsigned Idx = 1; 9503 9504 for (FunctionType::param_iterator I = FTy->param_begin(), 9505 E = FTy->param_end(); I != E; ++I, ++Idx) 9506 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9507 // FIXME: should only count parameters that are lowered to integers. 9508 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9509 9510 if (InRegCount > 2) { 9511 report_fatal_error("Nest register in use - reduce number of inreg" 9512 " parameters!"); 9513 } 9514 } 9515 break; 9516 } 9517 case CallingConv::X86_FastCall: 9518 case CallingConv::X86_ThisCall: 9519 case CallingConv::Fast: 9520 // Pass 'nest' parameter in EAX. 9521 // Must be kept in sync with X86CallingConv.td 9522 NestReg = X86::EAX; 9523 break; 9524 } 9525 9526 SDValue OutChains[4]; 9527 SDValue Addr, Disp; 9528 9529 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9530 DAG.getConstant(10, MVT::i32)); 9531 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9532 9533 // This is storing the opcode for MOV32ri. 9534 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9535 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9536 OutChains[0] = DAG.getStore(Root, dl, 9537 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9538 Trmp, MachinePointerInfo(TrmpAddr), 9539 false, false, 0); 9540 9541 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9542 DAG.getConstant(1, MVT::i32)); 9543 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9544 MachinePointerInfo(TrmpAddr, 1), 9545 false, false, 1); 9546 9547 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9548 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9549 DAG.getConstant(5, MVT::i32)); 9550 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9551 MachinePointerInfo(TrmpAddr, 5), 9552 false, false, 1); 9553 9554 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9555 DAG.getConstant(6, MVT::i32)); 9556 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9557 MachinePointerInfo(TrmpAddr, 6), 9558 false, false, 1); 9559 9560 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9561 } 9562} 9563 9564SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9565 SelectionDAG &DAG) const { 9566 /* 9567 The rounding mode is in bits 11:10 of FPSR, and has the following 9568 settings: 9569 00 Round to nearest 9570 01 Round to -inf 9571 10 Round to +inf 9572 11 Round to 0 9573 9574 FLT_ROUNDS, on the other hand, expects the following: 9575 -1 Undefined 9576 0 Round to 0 9577 1 Round to nearest 9578 2 Round to +inf 9579 3 Round to -inf 9580 9581 To perform the conversion, we do: 9582 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9583 */ 9584 9585 MachineFunction &MF = DAG.getMachineFunction(); 9586 const TargetMachine &TM = MF.getTarget(); 9587 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9588 unsigned StackAlignment = TFI.getStackAlignment(); 9589 EVT VT = Op.getValueType(); 9590 DebugLoc DL = Op.getDebugLoc(); 9591 9592 // Save FP Control Word to stack slot 9593 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9594 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9595 9596 9597 MachineMemOperand *MMO = 9598 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9599 MachineMemOperand::MOStore, 2, 2); 9600 9601 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9602 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9603 DAG.getVTList(MVT::Other), 9604 Ops, 2, MVT::i16, MMO); 9605 9606 // Load FP Control Word from stack slot 9607 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9608 MachinePointerInfo(), false, false, 0); 9609 9610 // Transform as necessary 9611 SDValue CWD1 = 9612 DAG.getNode(ISD::SRL, DL, MVT::i16, 9613 DAG.getNode(ISD::AND, DL, MVT::i16, 9614 CWD, DAG.getConstant(0x800, MVT::i16)), 9615 DAG.getConstant(11, MVT::i8)); 9616 SDValue CWD2 = 9617 DAG.getNode(ISD::SRL, DL, MVT::i16, 9618 DAG.getNode(ISD::AND, DL, MVT::i16, 9619 CWD, DAG.getConstant(0x400, MVT::i16)), 9620 DAG.getConstant(9, MVT::i8)); 9621 9622 SDValue RetVal = 9623 DAG.getNode(ISD::AND, DL, MVT::i16, 9624 DAG.getNode(ISD::ADD, DL, MVT::i16, 9625 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9626 DAG.getConstant(1, MVT::i16)), 9627 DAG.getConstant(3, MVT::i16)); 9628 9629 9630 return DAG.getNode((VT.getSizeInBits() < 16 ? 9631 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9632} 9633 9634SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9635 EVT VT = Op.getValueType(); 9636 EVT OpVT = VT; 9637 unsigned NumBits = VT.getSizeInBits(); 9638 DebugLoc dl = Op.getDebugLoc(); 9639 9640 Op = Op.getOperand(0); 9641 if (VT == MVT::i8) { 9642 // Zero extend to i32 since there is not an i8 bsr. 9643 OpVT = MVT::i32; 9644 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9645 } 9646 9647 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9648 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9649 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9650 9651 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9652 SDValue Ops[] = { 9653 Op, 9654 DAG.getConstant(NumBits+NumBits-1, OpVT), 9655 DAG.getConstant(X86::COND_E, MVT::i8), 9656 Op.getValue(1) 9657 }; 9658 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9659 9660 // Finally xor with NumBits-1. 9661 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9662 9663 if (VT == MVT::i8) 9664 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9665 return Op; 9666} 9667 9668SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9669 EVT VT = Op.getValueType(); 9670 EVT OpVT = VT; 9671 unsigned NumBits = VT.getSizeInBits(); 9672 DebugLoc dl = Op.getDebugLoc(); 9673 9674 Op = Op.getOperand(0); 9675 if (VT == MVT::i8) { 9676 OpVT = MVT::i32; 9677 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9678 } 9679 9680 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9681 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9682 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9683 9684 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9685 SDValue Ops[] = { 9686 Op, 9687 DAG.getConstant(NumBits, OpVT), 9688 DAG.getConstant(X86::COND_E, MVT::i8), 9689 Op.getValue(1) 9690 }; 9691 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9692 9693 if (VT == MVT::i8) 9694 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9695 return Op; 9696} 9697 9698// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9699// ones, and then concatenate the result back. 9700static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9701 EVT VT = Op.getValueType(); 9702 9703 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9704 "Unsupported value type for operation"); 9705 9706 int NumElems = VT.getVectorNumElements(); 9707 DebugLoc dl = Op.getDebugLoc(); 9708 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9709 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9710 9711 // Extract the LHS vectors 9712 SDValue LHS = Op.getOperand(0); 9713 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9714 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9715 9716 // Extract the RHS vectors 9717 SDValue RHS = Op.getOperand(1); 9718 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9719 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9720 9721 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9722 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9723 9724 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9725 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9726 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9727} 9728 9729SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9730 assert(Op.getValueType().getSizeInBits() == 256 && 9731 Op.getValueType().isInteger() && 9732 "Only handle AVX 256-bit vector integer operation"); 9733 return Lower256IntArith(Op, DAG); 9734} 9735 9736SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9737 assert(Op.getValueType().getSizeInBits() == 256 && 9738 Op.getValueType().isInteger() && 9739 "Only handle AVX 256-bit vector integer operation"); 9740 return Lower256IntArith(Op, DAG); 9741} 9742 9743SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9744 EVT VT = Op.getValueType(); 9745 9746 // Decompose 256-bit ops into smaller 128-bit ops. 9747 if (VT.getSizeInBits() == 256) 9748 return Lower256IntArith(Op, DAG); 9749 9750 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9751 DebugLoc dl = Op.getDebugLoc(); 9752 9753 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9754 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9755 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9756 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9757 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9758 // 9759 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9760 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9761 // return AloBlo + AloBhi + AhiBlo; 9762 9763 SDValue A = Op.getOperand(0); 9764 SDValue B = Op.getOperand(1); 9765 9766 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9767 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9768 A, DAG.getConstant(32, MVT::i32)); 9769 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9770 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9771 B, DAG.getConstant(32, MVT::i32)); 9772 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9773 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9774 A, B); 9775 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9776 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9777 A, Bhi); 9778 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9779 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9780 Ahi, B); 9781 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9782 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9783 AloBhi, DAG.getConstant(32, MVT::i32)); 9784 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9785 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9786 AhiBlo, DAG.getConstant(32, MVT::i32)); 9787 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9788 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9789 return Res; 9790} 9791 9792SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 9793 9794 EVT VT = Op.getValueType(); 9795 DebugLoc dl = Op.getDebugLoc(); 9796 SDValue R = Op.getOperand(0); 9797 SDValue Amt = Op.getOperand(1); 9798 LLVMContext *Context = DAG.getContext(); 9799 9800 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 9801 return SDValue(); 9802 9803 // Decompose 256-bit shifts into smaller 128-bit shifts. 9804 if (VT.getSizeInBits() == 256) { 9805 int NumElems = VT.getVectorNumElements(); 9806 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9807 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9808 9809 // Extract the two vectors 9810 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 9811 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 9812 DAG, dl); 9813 9814 // Recreate the shift amount vectors 9815 SDValue Amt1, Amt2; 9816 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 9817 // Constant shift amount 9818 SmallVector<SDValue, 4> Amt1Csts; 9819 SmallVector<SDValue, 4> Amt2Csts; 9820 for (int i = 0; i < NumElems/2; ++i) 9821 Amt1Csts.push_back(Amt->getOperand(i)); 9822 for (int i = NumElems/2; i < NumElems; ++i) 9823 Amt2Csts.push_back(Amt->getOperand(i)); 9824 9825 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9826 &Amt1Csts[0], NumElems/2); 9827 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9828 &Amt2Csts[0], NumElems/2); 9829 } else { 9830 // Variable shift amount 9831 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 9832 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 9833 DAG, dl); 9834 } 9835 9836 // Issue new vector shifts for the smaller types 9837 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 9838 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 9839 9840 // Concatenate the result back 9841 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 9842 } 9843 9844 // Optimize shl/srl/sra with constant shift amount. 9845 if (isSplatVector(Amt.getNode())) { 9846 SDValue SclrAmt = Amt->getOperand(0); 9847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 9848 uint64_t ShiftAmt = C->getZExtValue(); 9849 9850 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 9851 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9852 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9853 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9854 9855 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 9856 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9857 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9858 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9859 9860 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 9861 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9862 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9863 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9864 9865 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 9866 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9867 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9868 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9869 9870 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 9871 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9872 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9873 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9874 9875 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 9876 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9877 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9878 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9879 9880 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 9881 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9882 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9883 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9884 9885 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 9886 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9887 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9888 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9889 } 9890 } 9891 9892 // Lower SHL with variable shift amount. 9893 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 9894 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9895 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9896 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 9897 9898 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 9899 9900 std::vector<Constant*> CV(4, CI); 9901 Constant *C = ConstantVector::get(CV); 9902 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9903 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9904 MachinePointerInfo::getConstantPool(), 9905 false, false, 16); 9906 9907 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 9908 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 9909 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 9910 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 9911 } 9912 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 9913 // a = a << 5; 9914 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9915 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9916 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 9917 9918 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 9919 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 9920 9921 std::vector<Constant*> CVM1(16, CM1); 9922 std::vector<Constant*> CVM2(16, CM2); 9923 Constant *C = ConstantVector::get(CVM1); 9924 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9925 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9926 MachinePointerInfo::getConstantPool(), 9927 false, false, 16); 9928 9929 // r = pblendv(r, psllw(r & (char16)15, 4), a); 9930 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9931 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9932 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9933 DAG.getConstant(4, MVT::i32)); 9934 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9935 // a += a 9936 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9937 9938 C = ConstantVector::get(CVM2); 9939 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9940 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9941 MachinePointerInfo::getConstantPool(), 9942 false, false, 16); 9943 9944 // r = pblendv(r, psllw(r & (char16)63, 2), a); 9945 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9946 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9947 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9948 DAG.getConstant(2, MVT::i32)); 9949 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9950 // a += a 9951 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9952 9953 // return pblendv(r, r+r, a); 9954 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, 9955 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 9956 return R; 9957 } 9958 return SDValue(); 9959} 9960 9961SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 9962 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 9963 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 9964 // looks for this combo and may remove the "setcc" instruction if the "setcc" 9965 // has only one use. 9966 SDNode *N = Op.getNode(); 9967 SDValue LHS = N->getOperand(0); 9968 SDValue RHS = N->getOperand(1); 9969 unsigned BaseOp = 0; 9970 unsigned Cond = 0; 9971 DebugLoc DL = Op.getDebugLoc(); 9972 switch (Op.getOpcode()) { 9973 default: llvm_unreachable("Unknown ovf instruction!"); 9974 case ISD::SADDO: 9975 // A subtract of one will be selected as a INC. Note that INC doesn't 9976 // set CF, so we can't do this for UADDO. 9977 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9978 if (C->isOne()) { 9979 BaseOp = X86ISD::INC; 9980 Cond = X86::COND_O; 9981 break; 9982 } 9983 BaseOp = X86ISD::ADD; 9984 Cond = X86::COND_O; 9985 break; 9986 case ISD::UADDO: 9987 BaseOp = X86ISD::ADD; 9988 Cond = X86::COND_B; 9989 break; 9990 case ISD::SSUBO: 9991 // A subtract of one will be selected as a DEC. Note that DEC doesn't 9992 // set CF, so we can't do this for USUBO. 9993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9994 if (C->isOne()) { 9995 BaseOp = X86ISD::DEC; 9996 Cond = X86::COND_O; 9997 break; 9998 } 9999 BaseOp = X86ISD::SUB; 10000 Cond = X86::COND_O; 10001 break; 10002 case ISD::USUBO: 10003 BaseOp = X86ISD::SUB; 10004 Cond = X86::COND_B; 10005 break; 10006 case ISD::SMULO: 10007 BaseOp = X86ISD::SMUL; 10008 Cond = X86::COND_O; 10009 break; 10010 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10011 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10012 MVT::i32); 10013 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10014 10015 SDValue SetCC = 10016 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10017 DAG.getConstant(X86::COND_O, MVT::i32), 10018 SDValue(Sum.getNode(), 2)); 10019 10020 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10021 } 10022 } 10023 10024 // Also sets EFLAGS. 10025 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10026 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10027 10028 SDValue SetCC = 10029 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10030 DAG.getConstant(Cond, MVT::i32), 10031 SDValue(Sum.getNode(), 1)); 10032 10033 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10034} 10035 10036SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 10037 DebugLoc dl = Op.getDebugLoc(); 10038 SDNode* Node = Op.getNode(); 10039 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 10040 EVT VT = Node->getValueType(0); 10041 10042 if (Subtarget->hasSSE2() && VT.isVector()) { 10043 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10044 ExtraVT.getScalarType().getSizeInBits(); 10045 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10046 10047 unsigned SHLIntrinsicsID = 0; 10048 unsigned SRAIntrinsicsID = 0; 10049 switch (VT.getSimpleVT().SimpleTy) { 10050 default: 10051 return SDValue(); 10052 case MVT::v2i64: { 10053 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q; 10054 SRAIntrinsicsID = 0; 10055 break; 10056 } 10057 case MVT::v4i32: { 10058 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10059 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10060 break; 10061 } 10062 case MVT::v8i16: { 10063 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10064 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10065 break; 10066 } 10067 } 10068 10069 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10070 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10071 Node->getOperand(0), ShAmt); 10072 10073 // In case of 1 bit sext, no need to shr 10074 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; 10075 10076 if (SRAIntrinsicsID) { 10077 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10078 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10079 Tmp1, ShAmt); 10080 } 10081 return Tmp1; 10082 } 10083 10084 return SDValue(); 10085} 10086 10087 10088SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10089 DebugLoc dl = Op.getDebugLoc(); 10090 10091 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10092 // There isn't any reason to disable it if the target processor supports it. 10093 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10094 SDValue Chain = Op.getOperand(0); 10095 SDValue Zero = DAG.getConstant(0, MVT::i32); 10096 SDValue Ops[] = { 10097 DAG.getRegister(X86::ESP, MVT::i32), // Base 10098 DAG.getTargetConstant(1, MVT::i8), // Scale 10099 DAG.getRegister(0, MVT::i32), // Index 10100 DAG.getTargetConstant(0, MVT::i32), // Disp 10101 DAG.getRegister(0, MVT::i32), // Segment. 10102 Zero, 10103 Chain 10104 }; 10105 SDNode *Res = 10106 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10107 array_lengthof(Ops)); 10108 return SDValue(Res, 0); 10109 } 10110 10111 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10112 if (!isDev) 10113 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10114 10115 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10116 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10117 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10118 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10119 10120 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10121 if (!Op1 && !Op2 && !Op3 && Op4) 10122 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10123 10124 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10125 if (Op1 && !Op2 && !Op3 && !Op4) 10126 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10127 10128 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10129 // (MFENCE)>; 10130 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10131} 10132 10133SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10134 SelectionDAG &DAG) const { 10135 DebugLoc dl = Op.getDebugLoc(); 10136 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10137 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10138 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10139 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10140 10141 // The only fence that needs an instruction is a sequentially-consistent 10142 // cross-thread fence. 10143 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10144 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10145 // no-sse2). There isn't any reason to disable it if the target processor 10146 // supports it. 10147 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10148 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10149 10150 SDValue Chain = Op.getOperand(0); 10151 SDValue Zero = DAG.getConstant(0, MVT::i32); 10152 SDValue Ops[] = { 10153 DAG.getRegister(X86::ESP, MVT::i32), // Base 10154 DAG.getTargetConstant(1, MVT::i8), // Scale 10155 DAG.getRegister(0, MVT::i32), // Index 10156 DAG.getTargetConstant(0, MVT::i32), // Disp 10157 DAG.getRegister(0, MVT::i32), // Segment. 10158 Zero, 10159 Chain 10160 }; 10161 SDNode *Res = 10162 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10163 array_lengthof(Ops)); 10164 return SDValue(Res, 0); 10165 } 10166 10167 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10168 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10169} 10170 10171 10172SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10173 EVT T = Op.getValueType(); 10174 DebugLoc DL = Op.getDebugLoc(); 10175 unsigned Reg = 0; 10176 unsigned size = 0; 10177 switch(T.getSimpleVT().SimpleTy) { 10178 default: 10179 assert(false && "Invalid value type!"); 10180 case MVT::i8: Reg = X86::AL; size = 1; break; 10181 case MVT::i16: Reg = X86::AX; size = 2; break; 10182 case MVT::i32: Reg = X86::EAX; size = 4; break; 10183 case MVT::i64: 10184 assert(Subtarget->is64Bit() && "Node not type legal!"); 10185 Reg = X86::RAX; size = 8; 10186 break; 10187 } 10188 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10189 Op.getOperand(2), SDValue()); 10190 SDValue Ops[] = { cpIn.getValue(0), 10191 Op.getOperand(1), 10192 Op.getOperand(3), 10193 DAG.getTargetConstant(size, MVT::i8), 10194 cpIn.getValue(1) }; 10195 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10196 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10197 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10198 Ops, 5, T, MMO); 10199 SDValue cpOut = 10200 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10201 return cpOut; 10202} 10203 10204SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10205 SelectionDAG &DAG) const { 10206 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10207 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10208 SDValue TheChain = Op.getOperand(0); 10209 DebugLoc dl = Op.getDebugLoc(); 10210 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10211 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10212 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10213 rax.getValue(2)); 10214 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10215 DAG.getConstant(32, MVT::i8)); 10216 SDValue Ops[] = { 10217 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10218 rdx.getValue(1) 10219 }; 10220 return DAG.getMergeValues(Ops, 2, dl); 10221} 10222 10223SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10224 SelectionDAG &DAG) const { 10225 EVT SrcVT = Op.getOperand(0).getValueType(); 10226 EVT DstVT = Op.getValueType(); 10227 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10228 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10229 assert((DstVT == MVT::i64 || 10230 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10231 "Unexpected custom BITCAST"); 10232 // i64 <=> MMX conversions are Legal. 10233 if (SrcVT==MVT::i64 && DstVT.isVector()) 10234 return Op; 10235 if (DstVT==MVT::i64 && SrcVT.isVector()) 10236 return Op; 10237 // MMX <=> MMX conversions are Legal. 10238 if (SrcVT.isVector() && DstVT.isVector()) 10239 return Op; 10240 // All other conversions need to be expanded. 10241 return SDValue(); 10242} 10243 10244SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10245 SDNode *Node = Op.getNode(); 10246 DebugLoc dl = Node->getDebugLoc(); 10247 EVT T = Node->getValueType(0); 10248 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10249 DAG.getConstant(0, T), Node->getOperand(2)); 10250 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10251 cast<AtomicSDNode>(Node)->getMemoryVT(), 10252 Node->getOperand(0), 10253 Node->getOperand(1), negOp, 10254 cast<AtomicSDNode>(Node)->getSrcValue(), 10255 cast<AtomicSDNode>(Node)->getAlignment(), 10256 cast<AtomicSDNode>(Node)->getOrdering(), 10257 cast<AtomicSDNode>(Node)->getSynchScope()); 10258} 10259 10260static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10261 SDNode *Node = Op.getNode(); 10262 DebugLoc dl = Node->getDebugLoc(); 10263 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10264 10265 // Convert seq_cst store -> xchg 10266 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10267 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10268 // (The only way to get a 16-byte store is cmpxchg16b) 10269 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10270 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10271 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10272 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10273 cast<AtomicSDNode>(Node)->getMemoryVT(), 10274 Node->getOperand(0), 10275 Node->getOperand(1), Node->getOperand(2), 10276 cast<AtomicSDNode>(Node)->getMemOperand(), 10277 cast<AtomicSDNode>(Node)->getOrdering(), 10278 cast<AtomicSDNode>(Node)->getSynchScope()); 10279 return Swap.getValue(1); 10280 } 10281 // Other atomic stores have a simple pattern. 10282 return Op; 10283} 10284 10285static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10286 EVT VT = Op.getNode()->getValueType(0); 10287 10288 // Let legalize expand this if it isn't a legal type yet. 10289 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10290 return SDValue(); 10291 10292 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10293 10294 unsigned Opc; 10295 bool ExtraOp = false; 10296 switch (Op.getOpcode()) { 10297 default: assert(0 && "Invalid code"); 10298 case ISD::ADDC: Opc = X86ISD::ADD; break; 10299 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10300 case ISD::SUBC: Opc = X86ISD::SUB; break; 10301 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10302 } 10303 10304 if (!ExtraOp) 10305 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10306 Op.getOperand(1)); 10307 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10308 Op.getOperand(1), Op.getOperand(2)); 10309} 10310 10311/// LowerOperation - Provide custom lowering hooks for some operations. 10312/// 10313SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10314 switch (Op.getOpcode()) { 10315 default: llvm_unreachable("Should not custom lower this!"); 10316 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10317 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10318 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10319 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10320 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10321 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10322 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10323 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10324 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10325 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10326 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10327 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10328 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10329 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10330 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10331 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10332 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10333 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10334 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10335 case ISD::SHL_PARTS: 10336 case ISD::SRA_PARTS: 10337 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10338 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10339 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10340 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10341 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10342 case ISD::FABS: return LowerFABS(Op, DAG); 10343 case ISD::FNEG: return LowerFNEG(Op, DAG); 10344 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10345 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10346 case ISD::SETCC: return LowerSETCC(Op, DAG); 10347 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 10348 case ISD::SELECT: return LowerSELECT(Op, DAG); 10349 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10350 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10351 case ISD::VASTART: return LowerVASTART(Op, DAG); 10352 case ISD::VAARG: return LowerVAARG(Op, DAG); 10353 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10354 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10355 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10356 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10357 case ISD::FRAME_TO_ARGS_OFFSET: 10358 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10359 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10360 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10361 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10362 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10363 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10364 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10365 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10366 case ISD::MUL: return LowerMUL(Op, DAG); 10367 case ISD::SRA: 10368 case ISD::SRL: 10369 case ISD::SHL: return LowerShift(Op, DAG); 10370 case ISD::SADDO: 10371 case ISD::UADDO: 10372 case ISD::SSUBO: 10373 case ISD::USUBO: 10374 case ISD::SMULO: 10375 case ISD::UMULO: return LowerXALUO(Op, DAG); 10376 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10377 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10378 case ISD::ADDC: 10379 case ISD::ADDE: 10380 case ISD::SUBC: 10381 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10382 case ISD::ADD: return LowerADD(Op, DAG); 10383 case ISD::SUB: return LowerSUB(Op, DAG); 10384 } 10385} 10386 10387static void ReplaceATOMIC_LOAD(SDNode *Node, 10388 SmallVectorImpl<SDValue> &Results, 10389 SelectionDAG &DAG) { 10390 DebugLoc dl = Node->getDebugLoc(); 10391 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10392 10393 // Convert wide load -> cmpxchg8b/cmpxchg16b 10394 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10395 // (The only way to get a 16-byte load is cmpxchg16b) 10396 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10397 SDValue Zero = DAG.getConstant(0, VT); 10398 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10399 Node->getOperand(0), 10400 Node->getOperand(1), Zero, Zero, 10401 cast<AtomicSDNode>(Node)->getMemOperand(), 10402 cast<AtomicSDNode>(Node)->getOrdering(), 10403 cast<AtomicSDNode>(Node)->getSynchScope()); 10404 Results.push_back(Swap.getValue(0)); 10405 Results.push_back(Swap.getValue(1)); 10406} 10407 10408void X86TargetLowering:: 10409ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10410 SelectionDAG &DAG, unsigned NewOp) const { 10411 EVT T = Node->getValueType(0); 10412 DebugLoc dl = Node->getDebugLoc(); 10413 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 10414 10415 SDValue Chain = Node->getOperand(0); 10416 SDValue In1 = Node->getOperand(1); 10417 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10418 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10419 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10420 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10421 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10422 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10423 SDValue Result = 10424 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10425 cast<MemSDNode>(Node)->getMemOperand()); 10426 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10427 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10428 Results.push_back(Result.getValue(2)); 10429} 10430 10431/// ReplaceNodeResults - Replace a node with an illegal result type 10432/// with a new node built out of custom code. 10433void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10434 SmallVectorImpl<SDValue>&Results, 10435 SelectionDAG &DAG) const { 10436 DebugLoc dl = N->getDebugLoc(); 10437 switch (N->getOpcode()) { 10438 default: 10439 assert(false && "Do not know how to custom type legalize this operation!"); 10440 return; 10441 case ISD::SIGN_EXTEND_INREG: 10442 case ISD::ADDC: 10443 case ISD::ADDE: 10444 case ISD::SUBC: 10445 case ISD::SUBE: 10446 // We don't want to expand or promote these. 10447 return; 10448 case ISD::FP_TO_SINT: { 10449 std::pair<SDValue,SDValue> Vals = 10450 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10451 SDValue FIST = Vals.first, StackSlot = Vals.second; 10452 if (FIST.getNode() != 0) { 10453 EVT VT = N->getValueType(0); 10454 // Return a load from the stack slot. 10455 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10456 MachinePointerInfo(), false, false, 0)); 10457 } 10458 return; 10459 } 10460 case ISD::READCYCLECOUNTER: { 10461 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10462 SDValue TheChain = N->getOperand(0); 10463 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10464 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10465 rd.getValue(1)); 10466 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10467 eax.getValue(2)); 10468 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10469 SDValue Ops[] = { eax, edx }; 10470 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10471 Results.push_back(edx.getValue(1)); 10472 return; 10473 } 10474 case ISD::ATOMIC_CMP_SWAP: { 10475 EVT T = N->getValueType(0); 10476 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10477 bool Regs64bit = T == MVT::i128; 10478 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10479 SDValue cpInL, cpInH; 10480 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10481 DAG.getConstant(0, HalfT)); 10482 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10483 DAG.getConstant(1, HalfT)); 10484 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10485 Regs64bit ? X86::RAX : X86::EAX, 10486 cpInL, SDValue()); 10487 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10488 Regs64bit ? X86::RDX : X86::EDX, 10489 cpInH, cpInL.getValue(1)); 10490 SDValue swapInL, swapInH; 10491 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10492 DAG.getConstant(0, HalfT)); 10493 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10494 DAG.getConstant(1, HalfT)); 10495 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10496 Regs64bit ? X86::RBX : X86::EBX, 10497 swapInL, cpInH.getValue(1)); 10498 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10499 Regs64bit ? X86::RCX : X86::ECX, 10500 swapInH, swapInL.getValue(1)); 10501 SDValue Ops[] = { swapInH.getValue(0), 10502 N->getOperand(1), 10503 swapInH.getValue(1) }; 10504 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10505 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10506 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10507 X86ISD::LCMPXCHG8_DAG; 10508 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10509 Ops, 3, T, MMO); 10510 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10511 Regs64bit ? X86::RAX : X86::EAX, 10512 HalfT, Result.getValue(1)); 10513 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10514 Regs64bit ? X86::RDX : X86::EDX, 10515 HalfT, cpOutL.getValue(2)); 10516 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10517 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10518 Results.push_back(cpOutH.getValue(1)); 10519 return; 10520 } 10521 case ISD::ATOMIC_LOAD_ADD: 10522 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10523 return; 10524 case ISD::ATOMIC_LOAD_AND: 10525 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10526 return; 10527 case ISD::ATOMIC_LOAD_NAND: 10528 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10529 return; 10530 case ISD::ATOMIC_LOAD_OR: 10531 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10532 return; 10533 case ISD::ATOMIC_LOAD_SUB: 10534 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10535 return; 10536 case ISD::ATOMIC_LOAD_XOR: 10537 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10538 return; 10539 case ISD::ATOMIC_SWAP: 10540 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10541 return; 10542 case ISD::ATOMIC_LOAD: 10543 ReplaceATOMIC_LOAD(N, Results, DAG); 10544 } 10545} 10546 10547const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10548 switch (Opcode) { 10549 default: return NULL; 10550 case X86ISD::BSF: return "X86ISD::BSF"; 10551 case X86ISD::BSR: return "X86ISD::BSR"; 10552 case X86ISD::SHLD: return "X86ISD::SHLD"; 10553 case X86ISD::SHRD: return "X86ISD::SHRD"; 10554 case X86ISD::FAND: return "X86ISD::FAND"; 10555 case X86ISD::FOR: return "X86ISD::FOR"; 10556 case X86ISD::FXOR: return "X86ISD::FXOR"; 10557 case X86ISD::FSRL: return "X86ISD::FSRL"; 10558 case X86ISD::FILD: return "X86ISD::FILD"; 10559 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10560 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10561 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10562 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10563 case X86ISD::FLD: return "X86ISD::FLD"; 10564 case X86ISD::FST: return "X86ISD::FST"; 10565 case X86ISD::CALL: return "X86ISD::CALL"; 10566 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10567 case X86ISD::BT: return "X86ISD::BT"; 10568 case X86ISD::CMP: return "X86ISD::CMP"; 10569 case X86ISD::COMI: return "X86ISD::COMI"; 10570 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10571 case X86ISD::SETCC: return "X86ISD::SETCC"; 10572 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10573 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10574 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10575 case X86ISD::CMOV: return "X86ISD::CMOV"; 10576 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10577 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10578 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10579 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10580 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10581 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10582 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10583 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10584 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10585 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10586 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10587 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10588 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10589 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10590 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 10591 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 10592 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 10593 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB"; 10594 case X86ISD::FMAX: return "X86ISD::FMAX"; 10595 case X86ISD::FMIN: return "X86ISD::FMIN"; 10596 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10597 case X86ISD::FRCP: return "X86ISD::FRCP"; 10598 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10599 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10600 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10601 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10602 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10603 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10604 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10605 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10606 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10607 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10608 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10609 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10610 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10611 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10612 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10613 case X86ISD::VSHL: return "X86ISD::VSHL"; 10614 case X86ISD::VSRL: return "X86ISD::VSRL"; 10615 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10616 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10617 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10618 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10619 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10620 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10621 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10622 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10623 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10624 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10625 case X86ISD::ADD: return "X86ISD::ADD"; 10626 case X86ISD::SUB: return "X86ISD::SUB"; 10627 case X86ISD::ADC: return "X86ISD::ADC"; 10628 case X86ISD::SBB: return "X86ISD::SBB"; 10629 case X86ISD::SMUL: return "X86ISD::SMUL"; 10630 case X86ISD::UMUL: return "X86ISD::UMUL"; 10631 case X86ISD::INC: return "X86ISD::INC"; 10632 case X86ISD::DEC: return "X86ISD::DEC"; 10633 case X86ISD::OR: return "X86ISD::OR"; 10634 case X86ISD::XOR: return "X86ISD::XOR"; 10635 case X86ISD::AND: return "X86ISD::AND"; 10636 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10637 case X86ISD::PTEST: return "X86ISD::PTEST"; 10638 case X86ISD::TESTP: return "X86ISD::TESTP"; 10639 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10640 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10641 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10642 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10643 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10644 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10645 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 10646 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 10647 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10648 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10649 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10650 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 10651 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10652 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10653 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10654 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10655 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10656 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10657 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10658 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10659 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10660 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 10661 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 10662 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 10663 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 10664 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 10665 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 10666 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 10667 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 10668 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 10669 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 10670 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 10671 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 10672 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 10673 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 10674 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 10675 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 10676 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 10677 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 10678 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128"; 10679 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10680 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10681 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10682 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10683 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 10684 } 10685} 10686 10687// isLegalAddressingMode - Return true if the addressing mode represented 10688// by AM is legal for this target, for a load/store of the specified type. 10689bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10690 Type *Ty) const { 10691 // X86 supports extremely general addressing modes. 10692 CodeModel::Model M = getTargetMachine().getCodeModel(); 10693 Reloc::Model R = getTargetMachine().getRelocationModel(); 10694 10695 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10696 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10697 return false; 10698 10699 if (AM.BaseGV) { 10700 unsigned GVFlags = 10701 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 10702 10703 // If a reference to this global requires an extra load, we can't fold it. 10704 if (isGlobalStubReference(GVFlags)) 10705 return false; 10706 10707 // If BaseGV requires a register for the PIC base, we cannot also have a 10708 // BaseReg specified. 10709 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 10710 return false; 10711 10712 // If lower 4G is not available, then we must use rip-relative addressing. 10713 if ((M != CodeModel::Small || R != Reloc::Static) && 10714 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 10715 return false; 10716 } 10717 10718 switch (AM.Scale) { 10719 case 0: 10720 case 1: 10721 case 2: 10722 case 4: 10723 case 8: 10724 // These scales always work. 10725 break; 10726 case 3: 10727 case 5: 10728 case 9: 10729 // These scales are formed with basereg+scalereg. Only accept if there is 10730 // no basereg yet. 10731 if (AM.HasBaseReg) 10732 return false; 10733 break; 10734 default: // Other stuff never works. 10735 return false; 10736 } 10737 10738 return true; 10739} 10740 10741 10742bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 10743 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 10744 return false; 10745 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 10746 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 10747 if (NumBits1 <= NumBits2) 10748 return false; 10749 return true; 10750} 10751 10752bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 10753 if (!VT1.isInteger() || !VT2.isInteger()) 10754 return false; 10755 unsigned NumBits1 = VT1.getSizeInBits(); 10756 unsigned NumBits2 = VT2.getSizeInBits(); 10757 if (NumBits1 <= NumBits2) 10758 return false; 10759 return true; 10760} 10761 10762bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 10763 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10764 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 10765} 10766 10767bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 10768 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10769 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 10770} 10771 10772bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 10773 // i16 instructions are longer (0x66 prefix) and potentially slower. 10774 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 10775} 10776 10777/// isShuffleMaskLegal - Targets can use this to indicate that they only 10778/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 10779/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 10780/// are assumed to be legal. 10781bool 10782X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 10783 EVT VT) const { 10784 // Very little shuffling can be done for 64-bit vectors right now. 10785 if (VT.getSizeInBits() == 64) 10786 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 10787 10788 // FIXME: pshufb, blends, shifts. 10789 return (VT.getVectorNumElements() == 2 || 10790 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 10791 isMOVLMask(M, VT) || 10792 isSHUFPMask(M, VT) || 10793 isPSHUFDMask(M, VT) || 10794 isPSHUFHWMask(M, VT) || 10795 isPSHUFLWMask(M, VT) || 10796 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 10797 isUNPCKLMask(M, VT) || 10798 isUNPCKHMask(M, VT) || 10799 isUNPCKL_v_undef_Mask(M, VT) || 10800 isUNPCKH_v_undef_Mask(M, VT)); 10801} 10802 10803bool 10804X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 10805 EVT VT) const { 10806 unsigned NumElts = VT.getVectorNumElements(); 10807 // FIXME: This collection of masks seems suspect. 10808 if (NumElts == 2) 10809 return true; 10810 if (NumElts == 4 && VT.getSizeInBits() == 128) { 10811 return (isMOVLMask(Mask, VT) || 10812 isCommutedMOVLMask(Mask, VT, true) || 10813 isSHUFPMask(Mask, VT) || 10814 isCommutedSHUFPMask(Mask, VT)); 10815 } 10816 return false; 10817} 10818 10819//===----------------------------------------------------------------------===// 10820// X86 Scheduler Hooks 10821//===----------------------------------------------------------------------===// 10822 10823// private utility function 10824MachineBasicBlock * 10825X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 10826 MachineBasicBlock *MBB, 10827 unsigned regOpc, 10828 unsigned immOpc, 10829 unsigned LoadOpc, 10830 unsigned CXchgOpc, 10831 unsigned notOpc, 10832 unsigned EAXreg, 10833 TargetRegisterClass *RC, 10834 bool invSrc) const { 10835 // For the atomic bitwise operator, we generate 10836 // thisMBB: 10837 // newMBB: 10838 // ld t1 = [bitinstr.addr] 10839 // op t2 = t1, [bitinstr.val] 10840 // mov EAX = t1 10841 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10842 // bz newMBB 10843 // fallthrough -->nextMBB 10844 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10845 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10846 MachineFunction::iterator MBBIter = MBB; 10847 ++MBBIter; 10848 10849 /// First build the CFG 10850 MachineFunction *F = MBB->getParent(); 10851 MachineBasicBlock *thisMBB = MBB; 10852 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10853 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10854 F->insert(MBBIter, newMBB); 10855 F->insert(MBBIter, nextMBB); 10856 10857 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10858 nextMBB->splice(nextMBB->begin(), thisMBB, 10859 llvm::next(MachineBasicBlock::iterator(bInstr)), 10860 thisMBB->end()); 10861 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10862 10863 // Update thisMBB to fall through to newMBB 10864 thisMBB->addSuccessor(newMBB); 10865 10866 // newMBB jumps to itself and fall through to nextMBB 10867 newMBB->addSuccessor(nextMBB); 10868 newMBB->addSuccessor(newMBB); 10869 10870 // Insert instructions into newMBB based on incoming instruction 10871 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10872 "unexpected number of operands"); 10873 DebugLoc dl = bInstr->getDebugLoc(); 10874 MachineOperand& destOper = bInstr->getOperand(0); 10875 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10876 int numArgs = bInstr->getNumOperands() - 1; 10877 for (int i=0; i < numArgs; ++i) 10878 argOpers[i] = &bInstr->getOperand(i+1); 10879 10880 // x86 address has 4 operands: base, index, scale, and displacement 10881 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10882 int valArgIndx = lastAddrIndx + 1; 10883 10884 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10885 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 10886 for (int i=0; i <= lastAddrIndx; ++i) 10887 (*MIB).addOperand(*argOpers[i]); 10888 10889 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 10890 if (invSrc) { 10891 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 10892 } 10893 else 10894 tt = t1; 10895 10896 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10897 assert((argOpers[valArgIndx]->isReg() || 10898 argOpers[valArgIndx]->isImm()) && 10899 "invalid operand"); 10900 if (argOpers[valArgIndx]->isReg()) 10901 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 10902 else 10903 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 10904 MIB.addReg(tt); 10905 (*MIB).addOperand(*argOpers[valArgIndx]); 10906 10907 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 10908 MIB.addReg(t1); 10909 10910 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 10911 for (int i=0; i <= lastAddrIndx; ++i) 10912 (*MIB).addOperand(*argOpers[i]); 10913 MIB.addReg(t2); 10914 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10915 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10916 bInstr->memoperands_end()); 10917 10918 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10919 MIB.addReg(EAXreg); 10920 10921 // insert branch 10922 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10923 10924 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10925 return nextMBB; 10926} 10927 10928// private utility function: 64 bit atomics on 32 bit host. 10929MachineBasicBlock * 10930X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 10931 MachineBasicBlock *MBB, 10932 unsigned regOpcL, 10933 unsigned regOpcH, 10934 unsigned immOpcL, 10935 unsigned immOpcH, 10936 bool invSrc) const { 10937 // For the atomic bitwise operator, we generate 10938 // thisMBB (instructions are in pairs, except cmpxchg8b) 10939 // ld t1,t2 = [bitinstr.addr] 10940 // newMBB: 10941 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 10942 // op t5, t6 <- out1, out2, [bitinstr.val] 10943 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 10944 // mov ECX, EBX <- t5, t6 10945 // mov EAX, EDX <- t1, t2 10946 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 10947 // mov t3, t4 <- EAX, EDX 10948 // bz newMBB 10949 // result in out1, out2 10950 // fallthrough -->nextMBB 10951 10952 const TargetRegisterClass *RC = X86::GR32RegisterClass; 10953 const unsigned LoadOpc = X86::MOV32rm; 10954 const unsigned NotOpc = X86::NOT32r; 10955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10956 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10957 MachineFunction::iterator MBBIter = MBB; 10958 ++MBBIter; 10959 10960 /// First build the CFG 10961 MachineFunction *F = MBB->getParent(); 10962 MachineBasicBlock *thisMBB = MBB; 10963 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10964 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10965 F->insert(MBBIter, newMBB); 10966 F->insert(MBBIter, nextMBB); 10967 10968 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10969 nextMBB->splice(nextMBB->begin(), thisMBB, 10970 llvm::next(MachineBasicBlock::iterator(bInstr)), 10971 thisMBB->end()); 10972 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10973 10974 // Update thisMBB to fall through to newMBB 10975 thisMBB->addSuccessor(newMBB); 10976 10977 // newMBB jumps to itself and fall through to nextMBB 10978 newMBB->addSuccessor(nextMBB); 10979 newMBB->addSuccessor(newMBB); 10980 10981 DebugLoc dl = bInstr->getDebugLoc(); 10982 // Insert instructions into newMBB based on incoming instruction 10983 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 10984 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 10985 "unexpected number of operands"); 10986 MachineOperand& dest1Oper = bInstr->getOperand(0); 10987 MachineOperand& dest2Oper = bInstr->getOperand(1); 10988 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10989 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 10990 argOpers[i] = &bInstr->getOperand(i+2); 10991 10992 // We use some of the operands multiple times, so conservatively just 10993 // clear any kill flags that might be present. 10994 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 10995 argOpers[i]->setIsKill(false); 10996 } 10997 10998 // x86 address has 5 operands: base, index, scale, displacement, and segment. 10999 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11000 11001 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11002 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11003 for (int i=0; i <= lastAddrIndx; ++i) 11004 (*MIB).addOperand(*argOpers[i]); 11005 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11006 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11007 // add 4 to displacement. 11008 for (int i=0; i <= lastAddrIndx-2; ++i) 11009 (*MIB).addOperand(*argOpers[i]); 11010 MachineOperand newOp3 = *(argOpers[3]); 11011 if (newOp3.isImm()) 11012 newOp3.setImm(newOp3.getImm()+4); 11013 else 11014 newOp3.setOffset(newOp3.getOffset()+4); 11015 (*MIB).addOperand(newOp3); 11016 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11017 11018 // t3/4 are defined later, at the bottom of the loop 11019 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11020 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11021 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11022 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11023 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11024 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11025 11026 // The subsequent operations should be using the destination registers of 11027 //the PHI instructions. 11028 if (invSrc) { 11029 t1 = F->getRegInfo().createVirtualRegister(RC); 11030 t2 = F->getRegInfo().createVirtualRegister(RC); 11031 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11032 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11033 } else { 11034 t1 = dest1Oper.getReg(); 11035 t2 = dest2Oper.getReg(); 11036 } 11037 11038 int valArgIndx = lastAddrIndx + 1; 11039 assert((argOpers[valArgIndx]->isReg() || 11040 argOpers[valArgIndx]->isImm()) && 11041 "invalid operand"); 11042 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11043 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11044 if (argOpers[valArgIndx]->isReg()) 11045 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11046 else 11047 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11048 if (regOpcL != X86::MOV32rr) 11049 MIB.addReg(t1); 11050 (*MIB).addOperand(*argOpers[valArgIndx]); 11051 assert(argOpers[valArgIndx + 1]->isReg() == 11052 argOpers[valArgIndx]->isReg()); 11053 assert(argOpers[valArgIndx + 1]->isImm() == 11054 argOpers[valArgIndx]->isImm()); 11055 if (argOpers[valArgIndx + 1]->isReg()) 11056 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11057 else 11058 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11059 if (regOpcH != X86::MOV32rr) 11060 MIB.addReg(t2); 11061 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11062 11063 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11064 MIB.addReg(t1); 11065 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11066 MIB.addReg(t2); 11067 11068 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11069 MIB.addReg(t5); 11070 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11071 MIB.addReg(t6); 11072 11073 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11074 for (int i=0; i <= lastAddrIndx; ++i) 11075 (*MIB).addOperand(*argOpers[i]); 11076 11077 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11078 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11079 bInstr->memoperands_end()); 11080 11081 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11082 MIB.addReg(X86::EAX); 11083 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11084 MIB.addReg(X86::EDX); 11085 11086 // insert branch 11087 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11088 11089 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11090 return nextMBB; 11091} 11092 11093// private utility function 11094MachineBasicBlock * 11095X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11096 MachineBasicBlock *MBB, 11097 unsigned cmovOpc) const { 11098 // For the atomic min/max operator, we generate 11099 // thisMBB: 11100 // newMBB: 11101 // ld t1 = [min/max.addr] 11102 // mov t2 = [min/max.val] 11103 // cmp t1, t2 11104 // cmov[cond] t2 = t1 11105 // mov EAX = t1 11106 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11107 // bz newMBB 11108 // fallthrough -->nextMBB 11109 // 11110 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11111 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11112 MachineFunction::iterator MBBIter = MBB; 11113 ++MBBIter; 11114 11115 /// First build the CFG 11116 MachineFunction *F = MBB->getParent(); 11117 MachineBasicBlock *thisMBB = MBB; 11118 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11119 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11120 F->insert(MBBIter, newMBB); 11121 F->insert(MBBIter, nextMBB); 11122 11123 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11124 nextMBB->splice(nextMBB->begin(), thisMBB, 11125 llvm::next(MachineBasicBlock::iterator(mInstr)), 11126 thisMBB->end()); 11127 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11128 11129 // Update thisMBB to fall through to newMBB 11130 thisMBB->addSuccessor(newMBB); 11131 11132 // newMBB jumps to newMBB and fall through to nextMBB 11133 newMBB->addSuccessor(nextMBB); 11134 newMBB->addSuccessor(newMBB); 11135 11136 DebugLoc dl = mInstr->getDebugLoc(); 11137 // Insert instructions into newMBB based on incoming instruction 11138 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11139 "unexpected number of operands"); 11140 MachineOperand& destOper = mInstr->getOperand(0); 11141 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11142 int numArgs = mInstr->getNumOperands() - 1; 11143 for (int i=0; i < numArgs; ++i) 11144 argOpers[i] = &mInstr->getOperand(i+1); 11145 11146 // x86 address has 4 operands: base, index, scale, and displacement 11147 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11148 int valArgIndx = lastAddrIndx + 1; 11149 11150 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11151 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11152 for (int i=0; i <= lastAddrIndx; ++i) 11153 (*MIB).addOperand(*argOpers[i]); 11154 11155 // We only support register and immediate values 11156 assert((argOpers[valArgIndx]->isReg() || 11157 argOpers[valArgIndx]->isImm()) && 11158 "invalid operand"); 11159 11160 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11161 if (argOpers[valArgIndx]->isReg()) 11162 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11163 else 11164 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11165 (*MIB).addOperand(*argOpers[valArgIndx]); 11166 11167 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11168 MIB.addReg(t1); 11169 11170 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11171 MIB.addReg(t1); 11172 MIB.addReg(t2); 11173 11174 // Generate movc 11175 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11176 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11177 MIB.addReg(t2); 11178 MIB.addReg(t1); 11179 11180 // Cmp and exchange if none has modified the memory location 11181 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11182 for (int i=0; i <= lastAddrIndx; ++i) 11183 (*MIB).addOperand(*argOpers[i]); 11184 MIB.addReg(t3); 11185 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11186 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11187 mInstr->memoperands_end()); 11188 11189 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11190 MIB.addReg(X86::EAX); 11191 11192 // insert branch 11193 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11194 11195 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11196 return nextMBB; 11197} 11198 11199// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11200// or XMM0_V32I8 in AVX all of this code can be replaced with that 11201// in the .td file. 11202MachineBasicBlock * 11203X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11204 unsigned numArgs, bool memArg) const { 11205 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 11206 "Target must have SSE4.2 or AVX features enabled"); 11207 11208 DebugLoc dl = MI->getDebugLoc(); 11209 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11210 unsigned Opc; 11211 if (!Subtarget->hasAVX()) { 11212 if (memArg) 11213 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11214 else 11215 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11216 } else { 11217 if (memArg) 11218 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11219 else 11220 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11221 } 11222 11223 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11224 for (unsigned i = 0; i < numArgs; ++i) { 11225 MachineOperand &Op = MI->getOperand(i+1); 11226 if (!(Op.isReg() && Op.isImplicit())) 11227 MIB.addOperand(Op); 11228 } 11229 BuildMI(*BB, MI, dl, 11230 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11231 MI->getOperand(0).getReg()) 11232 .addReg(X86::XMM0); 11233 11234 MI->eraseFromParent(); 11235 return BB; 11236} 11237 11238MachineBasicBlock * 11239X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11240 DebugLoc dl = MI->getDebugLoc(); 11241 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11242 11243 // Address into RAX/EAX, other two args into ECX, EDX. 11244 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11245 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11246 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11247 for (int i = 0; i < X86::AddrNumOperands; ++i) 11248 MIB.addOperand(MI->getOperand(i)); 11249 11250 unsigned ValOps = X86::AddrNumOperands; 11251 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11252 .addReg(MI->getOperand(ValOps).getReg()); 11253 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11254 .addReg(MI->getOperand(ValOps+1).getReg()); 11255 11256 // The instruction doesn't actually take any operands though. 11257 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11258 11259 MI->eraseFromParent(); // The pseudo is gone now. 11260 return BB; 11261} 11262 11263MachineBasicBlock * 11264X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11265 DebugLoc dl = MI->getDebugLoc(); 11266 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11267 11268 // First arg in ECX, the second in EAX. 11269 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11270 .addReg(MI->getOperand(0).getReg()); 11271 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11272 .addReg(MI->getOperand(1).getReg()); 11273 11274 // The instruction doesn't actually take any operands though. 11275 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11276 11277 MI->eraseFromParent(); // The pseudo is gone now. 11278 return BB; 11279} 11280 11281MachineBasicBlock * 11282X86TargetLowering::EmitVAARG64WithCustomInserter( 11283 MachineInstr *MI, 11284 MachineBasicBlock *MBB) const { 11285 // Emit va_arg instruction on X86-64. 11286 11287 // Operands to this pseudo-instruction: 11288 // 0 ) Output : destination address (reg) 11289 // 1-5) Input : va_list address (addr, i64mem) 11290 // 6 ) ArgSize : Size (in bytes) of vararg type 11291 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11292 // 8 ) Align : Alignment of type 11293 // 9 ) EFLAGS (implicit-def) 11294 11295 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11296 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11297 11298 unsigned DestReg = MI->getOperand(0).getReg(); 11299 MachineOperand &Base = MI->getOperand(1); 11300 MachineOperand &Scale = MI->getOperand(2); 11301 MachineOperand &Index = MI->getOperand(3); 11302 MachineOperand &Disp = MI->getOperand(4); 11303 MachineOperand &Segment = MI->getOperand(5); 11304 unsigned ArgSize = MI->getOperand(6).getImm(); 11305 unsigned ArgMode = MI->getOperand(7).getImm(); 11306 unsigned Align = MI->getOperand(8).getImm(); 11307 11308 // Memory Reference 11309 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11310 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11311 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11312 11313 // Machine Information 11314 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11315 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11316 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11317 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11318 DebugLoc DL = MI->getDebugLoc(); 11319 11320 // struct va_list { 11321 // i32 gp_offset 11322 // i32 fp_offset 11323 // i64 overflow_area (address) 11324 // i64 reg_save_area (address) 11325 // } 11326 // sizeof(va_list) = 24 11327 // alignment(va_list) = 8 11328 11329 unsigned TotalNumIntRegs = 6; 11330 unsigned TotalNumXMMRegs = 8; 11331 bool UseGPOffset = (ArgMode == 1); 11332 bool UseFPOffset = (ArgMode == 2); 11333 unsigned MaxOffset = TotalNumIntRegs * 8 + 11334 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11335 11336 /* Align ArgSize to a multiple of 8 */ 11337 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11338 bool NeedsAlign = (Align > 8); 11339 11340 MachineBasicBlock *thisMBB = MBB; 11341 MachineBasicBlock *overflowMBB; 11342 MachineBasicBlock *offsetMBB; 11343 MachineBasicBlock *endMBB; 11344 11345 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11346 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11347 unsigned OffsetReg = 0; 11348 11349 if (!UseGPOffset && !UseFPOffset) { 11350 // If we only pull from the overflow region, we don't create a branch. 11351 // We don't need to alter control flow. 11352 OffsetDestReg = 0; // unused 11353 OverflowDestReg = DestReg; 11354 11355 offsetMBB = NULL; 11356 overflowMBB = thisMBB; 11357 endMBB = thisMBB; 11358 } else { 11359 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11360 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11361 // If not, pull from overflow_area. (branch to overflowMBB) 11362 // 11363 // thisMBB 11364 // | . 11365 // | . 11366 // offsetMBB overflowMBB 11367 // | . 11368 // | . 11369 // endMBB 11370 11371 // Registers for the PHI in endMBB 11372 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11373 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11374 11375 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11376 MachineFunction *MF = MBB->getParent(); 11377 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11378 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11379 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11380 11381 MachineFunction::iterator MBBIter = MBB; 11382 ++MBBIter; 11383 11384 // Insert the new basic blocks 11385 MF->insert(MBBIter, offsetMBB); 11386 MF->insert(MBBIter, overflowMBB); 11387 MF->insert(MBBIter, endMBB); 11388 11389 // Transfer the remainder of MBB and its successor edges to endMBB. 11390 endMBB->splice(endMBB->begin(), thisMBB, 11391 llvm::next(MachineBasicBlock::iterator(MI)), 11392 thisMBB->end()); 11393 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11394 11395 // Make offsetMBB and overflowMBB successors of thisMBB 11396 thisMBB->addSuccessor(offsetMBB); 11397 thisMBB->addSuccessor(overflowMBB); 11398 11399 // endMBB is a successor of both offsetMBB and overflowMBB 11400 offsetMBB->addSuccessor(endMBB); 11401 overflowMBB->addSuccessor(endMBB); 11402 11403 // Load the offset value into a register 11404 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11405 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11406 .addOperand(Base) 11407 .addOperand(Scale) 11408 .addOperand(Index) 11409 .addDisp(Disp, UseFPOffset ? 4 : 0) 11410 .addOperand(Segment) 11411 .setMemRefs(MMOBegin, MMOEnd); 11412 11413 // Check if there is enough room left to pull this argument. 11414 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11415 .addReg(OffsetReg) 11416 .addImm(MaxOffset + 8 - ArgSizeA8); 11417 11418 // Branch to "overflowMBB" if offset >= max 11419 // Fall through to "offsetMBB" otherwise 11420 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11421 .addMBB(overflowMBB); 11422 } 11423 11424 // In offsetMBB, emit code to use the reg_save_area. 11425 if (offsetMBB) { 11426 assert(OffsetReg != 0); 11427 11428 // Read the reg_save_area address. 11429 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11430 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11431 .addOperand(Base) 11432 .addOperand(Scale) 11433 .addOperand(Index) 11434 .addDisp(Disp, 16) 11435 .addOperand(Segment) 11436 .setMemRefs(MMOBegin, MMOEnd); 11437 11438 // Zero-extend the offset 11439 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11440 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11441 .addImm(0) 11442 .addReg(OffsetReg) 11443 .addImm(X86::sub_32bit); 11444 11445 // Add the offset to the reg_save_area to get the final address. 11446 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11447 .addReg(OffsetReg64) 11448 .addReg(RegSaveReg); 11449 11450 // Compute the offset for the next argument 11451 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11452 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11453 .addReg(OffsetReg) 11454 .addImm(UseFPOffset ? 16 : 8); 11455 11456 // Store it back into the va_list. 11457 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11458 .addOperand(Base) 11459 .addOperand(Scale) 11460 .addOperand(Index) 11461 .addDisp(Disp, UseFPOffset ? 4 : 0) 11462 .addOperand(Segment) 11463 .addReg(NextOffsetReg) 11464 .setMemRefs(MMOBegin, MMOEnd); 11465 11466 // Jump to endMBB 11467 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11468 .addMBB(endMBB); 11469 } 11470 11471 // 11472 // Emit code to use overflow area 11473 // 11474 11475 // Load the overflow_area address into a register. 11476 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11477 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11478 .addOperand(Base) 11479 .addOperand(Scale) 11480 .addOperand(Index) 11481 .addDisp(Disp, 8) 11482 .addOperand(Segment) 11483 .setMemRefs(MMOBegin, MMOEnd); 11484 11485 // If we need to align it, do so. Otherwise, just copy the address 11486 // to OverflowDestReg. 11487 if (NeedsAlign) { 11488 // Align the overflow address 11489 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11490 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11491 11492 // aligned_addr = (addr + (align-1)) & ~(align-1) 11493 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11494 .addReg(OverflowAddrReg) 11495 .addImm(Align-1); 11496 11497 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11498 .addReg(TmpReg) 11499 .addImm(~(uint64_t)(Align-1)); 11500 } else { 11501 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11502 .addReg(OverflowAddrReg); 11503 } 11504 11505 // Compute the next overflow address after this argument. 11506 // (the overflow address should be kept 8-byte aligned) 11507 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11508 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11509 .addReg(OverflowDestReg) 11510 .addImm(ArgSizeA8); 11511 11512 // Store the new overflow address. 11513 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11514 .addOperand(Base) 11515 .addOperand(Scale) 11516 .addOperand(Index) 11517 .addDisp(Disp, 8) 11518 .addOperand(Segment) 11519 .addReg(NextAddrReg) 11520 .setMemRefs(MMOBegin, MMOEnd); 11521 11522 // If we branched, emit the PHI to the front of endMBB. 11523 if (offsetMBB) { 11524 BuildMI(*endMBB, endMBB->begin(), DL, 11525 TII->get(X86::PHI), DestReg) 11526 .addReg(OffsetDestReg).addMBB(offsetMBB) 11527 .addReg(OverflowDestReg).addMBB(overflowMBB); 11528 } 11529 11530 // Erase the pseudo instruction 11531 MI->eraseFromParent(); 11532 11533 return endMBB; 11534} 11535 11536MachineBasicBlock * 11537X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11538 MachineInstr *MI, 11539 MachineBasicBlock *MBB) const { 11540 // Emit code to save XMM registers to the stack. The ABI says that the 11541 // number of registers to save is given in %al, so it's theoretically 11542 // possible to do an indirect jump trick to avoid saving all of them, 11543 // however this code takes a simpler approach and just executes all 11544 // of the stores if %al is non-zero. It's less code, and it's probably 11545 // easier on the hardware branch predictor, and stores aren't all that 11546 // expensive anyway. 11547 11548 // Create the new basic blocks. One block contains all the XMM stores, 11549 // and one block is the final destination regardless of whether any 11550 // stores were performed. 11551 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11552 MachineFunction *F = MBB->getParent(); 11553 MachineFunction::iterator MBBIter = MBB; 11554 ++MBBIter; 11555 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11556 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11557 F->insert(MBBIter, XMMSaveMBB); 11558 F->insert(MBBIter, EndMBB); 11559 11560 // Transfer the remainder of MBB and its successor edges to EndMBB. 11561 EndMBB->splice(EndMBB->begin(), MBB, 11562 llvm::next(MachineBasicBlock::iterator(MI)), 11563 MBB->end()); 11564 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11565 11566 // The original block will now fall through to the XMM save block. 11567 MBB->addSuccessor(XMMSaveMBB); 11568 // The XMMSaveMBB will fall through to the end block. 11569 XMMSaveMBB->addSuccessor(EndMBB); 11570 11571 // Now add the instructions. 11572 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11573 DebugLoc DL = MI->getDebugLoc(); 11574 11575 unsigned CountReg = MI->getOperand(0).getReg(); 11576 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11577 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11578 11579 if (!Subtarget->isTargetWin64()) { 11580 // If %al is 0, branch around the XMM save block. 11581 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11582 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11583 MBB->addSuccessor(EndMBB); 11584 } 11585 11586 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11587 // In the XMM save block, save all the XMM argument registers. 11588 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11589 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11590 MachineMemOperand *MMO = 11591 F->getMachineMemOperand( 11592 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11593 MachineMemOperand::MOStore, 11594 /*Size=*/16, /*Align=*/16); 11595 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11596 .addFrameIndex(RegSaveFrameIndex) 11597 .addImm(/*Scale=*/1) 11598 .addReg(/*IndexReg=*/0) 11599 .addImm(/*Disp=*/Offset) 11600 .addReg(/*Segment=*/0) 11601 .addReg(MI->getOperand(i).getReg()) 11602 .addMemOperand(MMO); 11603 } 11604 11605 MI->eraseFromParent(); // The pseudo instruction is gone now. 11606 11607 return EndMBB; 11608} 11609 11610MachineBasicBlock * 11611X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11612 MachineBasicBlock *BB) const { 11613 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11614 DebugLoc DL = MI->getDebugLoc(); 11615 11616 // To "insert" a SELECT_CC instruction, we actually have to insert the 11617 // diamond control-flow pattern. The incoming instruction knows the 11618 // destination vreg to set, the condition code register to branch on, the 11619 // true/false values to select between, and a branch opcode to use. 11620 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11621 MachineFunction::iterator It = BB; 11622 ++It; 11623 11624 // thisMBB: 11625 // ... 11626 // TrueVal = ... 11627 // cmpTY ccX, r1, r2 11628 // bCC copy1MBB 11629 // fallthrough --> copy0MBB 11630 MachineBasicBlock *thisMBB = BB; 11631 MachineFunction *F = BB->getParent(); 11632 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11633 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11634 F->insert(It, copy0MBB); 11635 F->insert(It, sinkMBB); 11636 11637 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11638 // live into the sink and copy blocks. 11639 if (!MI->killsRegister(X86::EFLAGS)) { 11640 copy0MBB->addLiveIn(X86::EFLAGS); 11641 sinkMBB->addLiveIn(X86::EFLAGS); 11642 } 11643 11644 // Transfer the remainder of BB and its successor edges to sinkMBB. 11645 sinkMBB->splice(sinkMBB->begin(), BB, 11646 llvm::next(MachineBasicBlock::iterator(MI)), 11647 BB->end()); 11648 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11649 11650 // Add the true and fallthrough blocks as its successors. 11651 BB->addSuccessor(copy0MBB); 11652 BB->addSuccessor(sinkMBB); 11653 11654 // Create the conditional branch instruction. 11655 unsigned Opc = 11656 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11657 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11658 11659 // copy0MBB: 11660 // %FalseValue = ... 11661 // # fallthrough to sinkMBB 11662 copy0MBB->addSuccessor(sinkMBB); 11663 11664 // sinkMBB: 11665 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11666 // ... 11667 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11668 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11669 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11670 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11671 11672 MI->eraseFromParent(); // The pseudo instruction is gone now. 11673 return sinkMBB; 11674} 11675 11676MachineBasicBlock * 11677X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 11678 bool Is64Bit) const { 11679 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11680 DebugLoc DL = MI->getDebugLoc(); 11681 MachineFunction *MF = BB->getParent(); 11682 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11683 11684 assert(EnableSegmentedStacks); 11685 11686 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 11687 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 11688 11689 // BB: 11690 // ... [Till the alloca] 11691 // If stacklet is not large enough, jump to mallocMBB 11692 // 11693 // bumpMBB: 11694 // Allocate by subtracting from RSP 11695 // Jump to continueMBB 11696 // 11697 // mallocMBB: 11698 // Allocate by call to runtime 11699 // 11700 // continueMBB: 11701 // ... 11702 // [rest of original BB] 11703 // 11704 11705 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11706 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11707 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11708 11709 MachineRegisterInfo &MRI = MF->getRegInfo(); 11710 const TargetRegisterClass *AddrRegClass = 11711 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 11712 11713 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11714 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11715 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 11716 sizeVReg = MI->getOperand(1).getReg(), 11717 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 11718 11719 MachineFunction::iterator MBBIter = BB; 11720 ++MBBIter; 11721 11722 MF->insert(MBBIter, bumpMBB); 11723 MF->insert(MBBIter, mallocMBB); 11724 MF->insert(MBBIter, continueMBB); 11725 11726 continueMBB->splice(continueMBB->begin(), BB, llvm::next 11727 (MachineBasicBlock::iterator(MI)), BB->end()); 11728 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 11729 11730 // Add code to the main basic block to check if the stack limit has been hit, 11731 // and if so, jump to mallocMBB otherwise to bumpMBB. 11732 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 11733 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg) 11734 .addReg(tmpSPVReg).addReg(sizeVReg); 11735 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 11736 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 11737 .addReg(tmpSPVReg); 11738 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 11739 11740 // bumpMBB simply decreases the stack pointer, since we know the current 11741 // stacklet has enough space. 11742 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 11743 .addReg(tmpSPVReg); 11744 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 11745 .addReg(tmpSPVReg); 11746 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11747 11748 // Calls into a routine in libgcc to allocate more space from the heap. 11749 if (Is64Bit) { 11750 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 11751 .addReg(sizeVReg); 11752 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 11753 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 11754 } else { 11755 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 11756 .addImm(12); 11757 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 11758 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 11759 .addExternalSymbol("__morestack_allocate_stack_space"); 11760 } 11761 11762 if (!Is64Bit) 11763 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 11764 .addImm(16); 11765 11766 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 11767 .addReg(Is64Bit ? X86::RAX : X86::EAX); 11768 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11769 11770 // Set up the CFG correctly. 11771 BB->addSuccessor(bumpMBB); 11772 BB->addSuccessor(mallocMBB); 11773 mallocMBB->addSuccessor(continueMBB); 11774 bumpMBB->addSuccessor(continueMBB); 11775 11776 // Take care of the PHI nodes. 11777 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 11778 MI->getOperand(0).getReg()) 11779 .addReg(mallocPtrVReg).addMBB(mallocMBB) 11780 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 11781 11782 // Delete the original pseudo instruction. 11783 MI->eraseFromParent(); 11784 11785 // And we're done. 11786 return continueMBB; 11787} 11788 11789MachineBasicBlock * 11790X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 11791 MachineBasicBlock *BB) const { 11792 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11793 DebugLoc DL = MI->getDebugLoc(); 11794 11795 assert(!Subtarget->isTargetEnvMacho()); 11796 11797 // The lowering is pretty easy: we're just emitting the call to _alloca. The 11798 // non-trivial part is impdef of ESP. 11799 11800 if (Subtarget->isTargetWin64()) { 11801 if (Subtarget->isTargetCygMing()) { 11802 // ___chkstk(Mingw64): 11803 // Clobbers R10, R11, RAX and EFLAGS. 11804 // Updates RSP. 11805 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11806 .addExternalSymbol("___chkstk") 11807 .addReg(X86::RAX, RegState::Implicit) 11808 .addReg(X86::RSP, RegState::Implicit) 11809 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 11810 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 11811 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11812 } else { 11813 // __chkstk(MSVCRT): does not update stack pointer. 11814 // Clobbers R10, R11 and EFLAGS. 11815 // FIXME: RAX(allocated size) might be reused and not killed. 11816 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11817 .addExternalSymbol("__chkstk") 11818 .addReg(X86::RAX, RegState::Implicit) 11819 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11820 // RAX has the offset to subtracted from RSP. 11821 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 11822 .addReg(X86::RSP) 11823 .addReg(X86::RAX); 11824 } 11825 } else { 11826 const char *StackProbeSymbol = 11827 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 11828 11829 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 11830 .addExternalSymbol(StackProbeSymbol) 11831 .addReg(X86::EAX, RegState::Implicit) 11832 .addReg(X86::ESP, RegState::Implicit) 11833 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 11834 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 11835 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11836 } 11837 11838 MI->eraseFromParent(); // The pseudo instruction is gone now. 11839 return BB; 11840} 11841 11842MachineBasicBlock * 11843X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 11844 MachineBasicBlock *BB) const { 11845 // This is pretty easy. We're taking the value that we received from 11846 // our load from the relocation, sticking it in either RDI (x86-64) 11847 // or EAX and doing an indirect call. The return value will then 11848 // be in the normal return register. 11849 const X86InstrInfo *TII 11850 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 11851 DebugLoc DL = MI->getDebugLoc(); 11852 MachineFunction *F = BB->getParent(); 11853 11854 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 11855 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 11856 11857 if (Subtarget->is64Bit()) { 11858 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11859 TII->get(X86::MOV64rm), X86::RDI) 11860 .addReg(X86::RIP) 11861 .addImm(0).addReg(0) 11862 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11863 MI->getOperand(3).getTargetFlags()) 11864 .addReg(0); 11865 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 11866 addDirectMem(MIB, X86::RDI); 11867 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 11868 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11869 TII->get(X86::MOV32rm), X86::EAX) 11870 .addReg(0) 11871 .addImm(0).addReg(0) 11872 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11873 MI->getOperand(3).getTargetFlags()) 11874 .addReg(0); 11875 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11876 addDirectMem(MIB, X86::EAX); 11877 } else { 11878 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11879 TII->get(X86::MOV32rm), X86::EAX) 11880 .addReg(TII->getGlobalBaseReg(F)) 11881 .addImm(0).addReg(0) 11882 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11883 MI->getOperand(3).getTargetFlags()) 11884 .addReg(0); 11885 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11886 addDirectMem(MIB, X86::EAX); 11887 } 11888 11889 MI->eraseFromParent(); // The pseudo instruction is gone now. 11890 return BB; 11891} 11892 11893MachineBasicBlock * 11894X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 11895 MachineBasicBlock *BB) const { 11896 switch (MI->getOpcode()) { 11897 default: assert(false && "Unexpected instr type to insert"); 11898 case X86::TAILJMPd64: 11899 case X86::TAILJMPr64: 11900 case X86::TAILJMPm64: 11901 assert(!"TAILJMP64 would not be touched here."); 11902 case X86::TCRETURNdi64: 11903 case X86::TCRETURNri64: 11904 case X86::TCRETURNmi64: 11905 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 11906 // On AMD64, additional defs should be added before register allocation. 11907 if (!Subtarget->isTargetWin64()) { 11908 MI->addRegisterDefined(X86::RSI); 11909 MI->addRegisterDefined(X86::RDI); 11910 MI->addRegisterDefined(X86::XMM6); 11911 MI->addRegisterDefined(X86::XMM7); 11912 MI->addRegisterDefined(X86::XMM8); 11913 MI->addRegisterDefined(X86::XMM9); 11914 MI->addRegisterDefined(X86::XMM10); 11915 MI->addRegisterDefined(X86::XMM11); 11916 MI->addRegisterDefined(X86::XMM12); 11917 MI->addRegisterDefined(X86::XMM13); 11918 MI->addRegisterDefined(X86::XMM14); 11919 MI->addRegisterDefined(X86::XMM15); 11920 } 11921 return BB; 11922 case X86::WIN_ALLOCA: 11923 return EmitLoweredWinAlloca(MI, BB); 11924 case X86::SEG_ALLOCA_32: 11925 return EmitLoweredSegAlloca(MI, BB, false); 11926 case X86::SEG_ALLOCA_64: 11927 return EmitLoweredSegAlloca(MI, BB, true); 11928 case X86::TLSCall_32: 11929 case X86::TLSCall_64: 11930 return EmitLoweredTLSCall(MI, BB); 11931 case X86::CMOV_GR8: 11932 case X86::CMOV_FR32: 11933 case X86::CMOV_FR64: 11934 case X86::CMOV_V4F32: 11935 case X86::CMOV_V2F64: 11936 case X86::CMOV_V2I64: 11937 case X86::CMOV_V8F32: 11938 case X86::CMOV_V4F64: 11939 case X86::CMOV_V4I64: 11940 case X86::CMOV_GR16: 11941 case X86::CMOV_GR32: 11942 case X86::CMOV_RFP32: 11943 case X86::CMOV_RFP64: 11944 case X86::CMOV_RFP80: 11945 return EmitLoweredSelect(MI, BB); 11946 11947 case X86::FP32_TO_INT16_IN_MEM: 11948 case X86::FP32_TO_INT32_IN_MEM: 11949 case X86::FP32_TO_INT64_IN_MEM: 11950 case X86::FP64_TO_INT16_IN_MEM: 11951 case X86::FP64_TO_INT32_IN_MEM: 11952 case X86::FP64_TO_INT64_IN_MEM: 11953 case X86::FP80_TO_INT16_IN_MEM: 11954 case X86::FP80_TO_INT32_IN_MEM: 11955 case X86::FP80_TO_INT64_IN_MEM: { 11956 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11957 DebugLoc DL = MI->getDebugLoc(); 11958 11959 // Change the floating point control register to use "round towards zero" 11960 // mode when truncating to an integer value. 11961 MachineFunction *F = BB->getParent(); 11962 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 11963 addFrameReference(BuildMI(*BB, MI, DL, 11964 TII->get(X86::FNSTCW16m)), CWFrameIdx); 11965 11966 // Load the old value of the high byte of the control word... 11967 unsigned OldCW = 11968 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 11969 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 11970 CWFrameIdx); 11971 11972 // Set the high part to be round to zero... 11973 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 11974 .addImm(0xC7F); 11975 11976 // Reload the modified control word now... 11977 addFrameReference(BuildMI(*BB, MI, DL, 11978 TII->get(X86::FLDCW16m)), CWFrameIdx); 11979 11980 // Restore the memory image of control word to original value 11981 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 11982 .addReg(OldCW); 11983 11984 // Get the X86 opcode to use. 11985 unsigned Opc; 11986 switch (MI->getOpcode()) { 11987 default: llvm_unreachable("illegal opcode!"); 11988 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 11989 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 11990 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 11991 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 11992 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 11993 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 11994 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 11995 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 11996 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 11997 } 11998 11999 X86AddressMode AM; 12000 MachineOperand &Op = MI->getOperand(0); 12001 if (Op.isReg()) { 12002 AM.BaseType = X86AddressMode::RegBase; 12003 AM.Base.Reg = Op.getReg(); 12004 } else { 12005 AM.BaseType = X86AddressMode::FrameIndexBase; 12006 AM.Base.FrameIndex = Op.getIndex(); 12007 } 12008 Op = MI->getOperand(1); 12009 if (Op.isImm()) 12010 AM.Scale = Op.getImm(); 12011 Op = MI->getOperand(2); 12012 if (Op.isImm()) 12013 AM.IndexReg = Op.getImm(); 12014 Op = MI->getOperand(3); 12015 if (Op.isGlobal()) { 12016 AM.GV = Op.getGlobal(); 12017 } else { 12018 AM.Disp = Op.getImm(); 12019 } 12020 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12021 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12022 12023 // Reload the original control word now. 12024 addFrameReference(BuildMI(*BB, MI, DL, 12025 TII->get(X86::FLDCW16m)), CWFrameIdx); 12026 12027 MI->eraseFromParent(); // The pseudo instruction is gone now. 12028 return BB; 12029 } 12030 // String/text processing lowering. 12031 case X86::PCMPISTRM128REG: 12032 case X86::VPCMPISTRM128REG: 12033 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12034 case X86::PCMPISTRM128MEM: 12035 case X86::VPCMPISTRM128MEM: 12036 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12037 case X86::PCMPESTRM128REG: 12038 case X86::VPCMPESTRM128REG: 12039 return EmitPCMP(MI, BB, 5, false /* in mem */); 12040 case X86::PCMPESTRM128MEM: 12041 case X86::VPCMPESTRM128MEM: 12042 return EmitPCMP(MI, BB, 5, true /* in mem */); 12043 12044 // Thread synchronization. 12045 case X86::MONITOR: 12046 return EmitMonitor(MI, BB); 12047 case X86::MWAIT: 12048 return EmitMwait(MI, BB); 12049 12050 // Atomic Lowering. 12051 case X86::ATOMAND32: 12052 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12053 X86::AND32ri, X86::MOV32rm, 12054 X86::LCMPXCHG32, 12055 X86::NOT32r, X86::EAX, 12056 X86::GR32RegisterClass); 12057 case X86::ATOMOR32: 12058 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12059 X86::OR32ri, X86::MOV32rm, 12060 X86::LCMPXCHG32, 12061 X86::NOT32r, X86::EAX, 12062 X86::GR32RegisterClass); 12063 case X86::ATOMXOR32: 12064 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12065 X86::XOR32ri, X86::MOV32rm, 12066 X86::LCMPXCHG32, 12067 X86::NOT32r, X86::EAX, 12068 X86::GR32RegisterClass); 12069 case X86::ATOMNAND32: 12070 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12071 X86::AND32ri, X86::MOV32rm, 12072 X86::LCMPXCHG32, 12073 X86::NOT32r, X86::EAX, 12074 X86::GR32RegisterClass, true); 12075 case X86::ATOMMIN32: 12076 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12077 case X86::ATOMMAX32: 12078 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12079 case X86::ATOMUMIN32: 12080 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12081 case X86::ATOMUMAX32: 12082 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12083 12084 case X86::ATOMAND16: 12085 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12086 X86::AND16ri, X86::MOV16rm, 12087 X86::LCMPXCHG16, 12088 X86::NOT16r, X86::AX, 12089 X86::GR16RegisterClass); 12090 case X86::ATOMOR16: 12091 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12092 X86::OR16ri, X86::MOV16rm, 12093 X86::LCMPXCHG16, 12094 X86::NOT16r, X86::AX, 12095 X86::GR16RegisterClass); 12096 case X86::ATOMXOR16: 12097 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12098 X86::XOR16ri, X86::MOV16rm, 12099 X86::LCMPXCHG16, 12100 X86::NOT16r, X86::AX, 12101 X86::GR16RegisterClass); 12102 case X86::ATOMNAND16: 12103 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12104 X86::AND16ri, X86::MOV16rm, 12105 X86::LCMPXCHG16, 12106 X86::NOT16r, X86::AX, 12107 X86::GR16RegisterClass, true); 12108 case X86::ATOMMIN16: 12109 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12110 case X86::ATOMMAX16: 12111 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12112 case X86::ATOMUMIN16: 12113 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12114 case X86::ATOMUMAX16: 12115 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12116 12117 case X86::ATOMAND8: 12118 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12119 X86::AND8ri, X86::MOV8rm, 12120 X86::LCMPXCHG8, 12121 X86::NOT8r, X86::AL, 12122 X86::GR8RegisterClass); 12123 case X86::ATOMOR8: 12124 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12125 X86::OR8ri, X86::MOV8rm, 12126 X86::LCMPXCHG8, 12127 X86::NOT8r, X86::AL, 12128 X86::GR8RegisterClass); 12129 case X86::ATOMXOR8: 12130 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12131 X86::XOR8ri, X86::MOV8rm, 12132 X86::LCMPXCHG8, 12133 X86::NOT8r, X86::AL, 12134 X86::GR8RegisterClass); 12135 case X86::ATOMNAND8: 12136 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12137 X86::AND8ri, X86::MOV8rm, 12138 X86::LCMPXCHG8, 12139 X86::NOT8r, X86::AL, 12140 X86::GR8RegisterClass, true); 12141 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12142 // This group is for 64-bit host. 12143 case X86::ATOMAND64: 12144 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12145 X86::AND64ri32, X86::MOV64rm, 12146 X86::LCMPXCHG64, 12147 X86::NOT64r, X86::RAX, 12148 X86::GR64RegisterClass); 12149 case X86::ATOMOR64: 12150 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12151 X86::OR64ri32, X86::MOV64rm, 12152 X86::LCMPXCHG64, 12153 X86::NOT64r, X86::RAX, 12154 X86::GR64RegisterClass); 12155 case X86::ATOMXOR64: 12156 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12157 X86::XOR64ri32, X86::MOV64rm, 12158 X86::LCMPXCHG64, 12159 X86::NOT64r, X86::RAX, 12160 X86::GR64RegisterClass); 12161 case X86::ATOMNAND64: 12162 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12163 X86::AND64ri32, X86::MOV64rm, 12164 X86::LCMPXCHG64, 12165 X86::NOT64r, X86::RAX, 12166 X86::GR64RegisterClass, true); 12167 case X86::ATOMMIN64: 12168 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12169 case X86::ATOMMAX64: 12170 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12171 case X86::ATOMUMIN64: 12172 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12173 case X86::ATOMUMAX64: 12174 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12175 12176 // This group does 64-bit operations on a 32-bit host. 12177 case X86::ATOMAND6432: 12178 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12179 X86::AND32rr, X86::AND32rr, 12180 X86::AND32ri, X86::AND32ri, 12181 false); 12182 case X86::ATOMOR6432: 12183 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12184 X86::OR32rr, X86::OR32rr, 12185 X86::OR32ri, X86::OR32ri, 12186 false); 12187 case X86::ATOMXOR6432: 12188 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12189 X86::XOR32rr, X86::XOR32rr, 12190 X86::XOR32ri, X86::XOR32ri, 12191 false); 12192 case X86::ATOMNAND6432: 12193 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12194 X86::AND32rr, X86::AND32rr, 12195 X86::AND32ri, X86::AND32ri, 12196 true); 12197 case X86::ATOMADD6432: 12198 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12199 X86::ADD32rr, X86::ADC32rr, 12200 X86::ADD32ri, X86::ADC32ri, 12201 false); 12202 case X86::ATOMSUB6432: 12203 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12204 X86::SUB32rr, X86::SBB32rr, 12205 X86::SUB32ri, X86::SBB32ri, 12206 false); 12207 case X86::ATOMSWAP6432: 12208 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12209 X86::MOV32rr, X86::MOV32rr, 12210 X86::MOV32ri, X86::MOV32ri, 12211 false); 12212 case X86::VASTART_SAVE_XMM_REGS: 12213 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12214 12215 case X86::VAARG_64: 12216 return EmitVAARG64WithCustomInserter(MI, BB); 12217 } 12218} 12219 12220//===----------------------------------------------------------------------===// 12221// X86 Optimization Hooks 12222//===----------------------------------------------------------------------===// 12223 12224void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12225 const APInt &Mask, 12226 APInt &KnownZero, 12227 APInt &KnownOne, 12228 const SelectionDAG &DAG, 12229 unsigned Depth) const { 12230 unsigned Opc = Op.getOpcode(); 12231 assert((Opc >= ISD::BUILTIN_OP_END || 12232 Opc == ISD::INTRINSIC_WO_CHAIN || 12233 Opc == ISD::INTRINSIC_W_CHAIN || 12234 Opc == ISD::INTRINSIC_VOID) && 12235 "Should use MaskedValueIsZero if you don't know whether Op" 12236 " is a target node!"); 12237 12238 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12239 switch (Opc) { 12240 default: break; 12241 case X86ISD::ADD: 12242 case X86ISD::SUB: 12243 case X86ISD::ADC: 12244 case X86ISD::SBB: 12245 case X86ISD::SMUL: 12246 case X86ISD::UMUL: 12247 case X86ISD::INC: 12248 case X86ISD::DEC: 12249 case X86ISD::OR: 12250 case X86ISD::XOR: 12251 case X86ISD::AND: 12252 // These nodes' second result is a boolean. 12253 if (Op.getResNo() == 0) 12254 break; 12255 // Fallthrough 12256 case X86ISD::SETCC: 12257 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12258 Mask.getBitWidth() - 1); 12259 break; 12260 } 12261} 12262 12263unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12264 unsigned Depth) const { 12265 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12266 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12267 return Op.getValueType().getScalarType().getSizeInBits(); 12268 12269 // Fallback case. 12270 return 1; 12271} 12272 12273/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12274/// node is a GlobalAddress + offset. 12275bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12276 const GlobalValue* &GA, 12277 int64_t &Offset) const { 12278 if (N->getOpcode() == X86ISD::Wrapper) { 12279 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12280 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12281 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12282 return true; 12283 } 12284 } 12285 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12286} 12287 12288/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12289/// same as extracting the high 128-bit part of 256-bit vector and then 12290/// inserting the result into the low part of a new 256-bit vector 12291static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12292 EVT VT = SVOp->getValueType(0); 12293 int NumElems = VT.getVectorNumElements(); 12294 12295 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12296 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12297 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12298 SVOp->getMaskElt(j) >= 0) 12299 return false; 12300 12301 return true; 12302} 12303 12304/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12305/// same as extracting the low 128-bit part of 256-bit vector and then 12306/// inserting the result into the high part of a new 256-bit vector 12307static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12308 EVT VT = SVOp->getValueType(0); 12309 int NumElems = VT.getVectorNumElements(); 12310 12311 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12312 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12313 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12314 SVOp->getMaskElt(j) >= 0) 12315 return false; 12316 12317 return true; 12318} 12319 12320/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12321static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12322 TargetLowering::DAGCombinerInfo &DCI) { 12323 DebugLoc dl = N->getDebugLoc(); 12324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12325 SDValue V1 = SVOp->getOperand(0); 12326 SDValue V2 = SVOp->getOperand(1); 12327 EVT VT = SVOp->getValueType(0); 12328 int NumElems = VT.getVectorNumElements(); 12329 12330 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12331 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12332 // 12333 // 0,0,0,... 12334 // | 12335 // V UNDEF BUILD_VECTOR UNDEF 12336 // \ / \ / 12337 // CONCAT_VECTOR CONCAT_VECTOR 12338 // \ / 12339 // \ / 12340 // RESULT: V + zero extended 12341 // 12342 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12343 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12344 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12345 return SDValue(); 12346 12347 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12348 return SDValue(); 12349 12350 // To match the shuffle mask, the first half of the mask should 12351 // be exactly the first vector, and all the rest a splat with the 12352 // first element of the second one. 12353 for (int i = 0; i < NumElems/2; ++i) 12354 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12355 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12356 return SDValue(); 12357 12358 // Emit a zeroed vector and insert the desired subvector on its 12359 // first half. 12360 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 12361 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12362 DAG.getConstant(0, MVT::i32), DAG, dl); 12363 return DCI.CombineTo(N, InsV); 12364 } 12365 12366 //===--------------------------------------------------------------------===// 12367 // Combine some shuffles into subvector extracts and inserts: 12368 // 12369 12370 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12371 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12372 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12373 DAG, dl); 12374 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12375 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12376 return DCI.CombineTo(N, InsV); 12377 } 12378 12379 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12380 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12381 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12382 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12383 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12384 return DCI.CombineTo(N, InsV); 12385 } 12386 12387 return SDValue(); 12388} 12389 12390/// PerformShuffleCombine - Performs several different shuffle combines. 12391static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12392 TargetLowering::DAGCombinerInfo &DCI, 12393 const X86Subtarget *Subtarget) { 12394 DebugLoc dl = N->getDebugLoc(); 12395 EVT VT = N->getValueType(0); 12396 12397 // Don't create instructions with illegal types after legalize types has run. 12398 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12399 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12400 return SDValue(); 12401 12402 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12403 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12404 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12405 return PerformShuffleCombine256(N, DAG, DCI); 12406 12407 // Only handle 128 wide vector from here on. 12408 if (VT.getSizeInBits() != 128) 12409 return SDValue(); 12410 12411 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12412 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12413 // consecutive, non-overlapping, and in the right order. 12414 SmallVector<SDValue, 16> Elts; 12415 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12416 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12417 12418 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12419} 12420 12421/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12422/// generation and convert it from being a bunch of shuffles and extracts 12423/// to a simple store and scalar loads to extract the elements. 12424static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12425 const TargetLowering &TLI) { 12426 SDValue InputVector = N->getOperand(0); 12427 12428 // Only operate on vectors of 4 elements, where the alternative shuffling 12429 // gets to be more expensive. 12430 if (InputVector.getValueType() != MVT::v4i32) 12431 return SDValue(); 12432 12433 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12434 // single use which is a sign-extend or zero-extend, and all elements are 12435 // used. 12436 SmallVector<SDNode *, 4> Uses; 12437 unsigned ExtractedElements = 0; 12438 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12439 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12440 if (UI.getUse().getResNo() != InputVector.getResNo()) 12441 return SDValue(); 12442 12443 SDNode *Extract = *UI; 12444 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12445 return SDValue(); 12446 12447 if (Extract->getValueType(0) != MVT::i32) 12448 return SDValue(); 12449 if (!Extract->hasOneUse()) 12450 return SDValue(); 12451 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12452 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12453 return SDValue(); 12454 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12455 return SDValue(); 12456 12457 // Record which element was extracted. 12458 ExtractedElements |= 12459 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12460 12461 Uses.push_back(Extract); 12462 } 12463 12464 // If not all the elements were used, this may not be worthwhile. 12465 if (ExtractedElements != 15) 12466 return SDValue(); 12467 12468 // Ok, we've now decided to do the transformation. 12469 DebugLoc dl = InputVector.getDebugLoc(); 12470 12471 // Store the value to a temporary stack slot. 12472 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12473 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12474 MachinePointerInfo(), false, false, 0); 12475 12476 // Replace each use (extract) with a load of the appropriate element. 12477 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12478 UE = Uses.end(); UI != UE; ++UI) { 12479 SDNode *Extract = *UI; 12480 12481 // cOMpute the element's address. 12482 SDValue Idx = Extract->getOperand(1); 12483 unsigned EltSize = 12484 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12485 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12486 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12487 12488 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12489 StackPtr, OffsetVal); 12490 12491 // Load the scalar. 12492 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12493 ScalarAddr, MachinePointerInfo(), 12494 false, false, 0); 12495 12496 // Replace the exact with the load. 12497 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12498 } 12499 12500 // The replacement was made in place; don't return anything. 12501 return SDValue(); 12502} 12503 12504/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 12505static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12506 const X86Subtarget *Subtarget) { 12507 DebugLoc DL = N->getDebugLoc(); 12508 SDValue Cond = N->getOperand(0); 12509 // Get the LHS/RHS of the select. 12510 SDValue LHS = N->getOperand(1); 12511 SDValue RHS = N->getOperand(2); 12512 12513 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12514 // instructions match the semantics of the common C idiom x<y?x:y but not 12515 // x<=y?x:y, because of how they handle negative zero (which can be 12516 // ignored in unsafe-math mode). 12517 if (Subtarget->hasSSE2() && 12518 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 12519 Cond.getOpcode() == ISD::SETCC) { 12520 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12521 12522 unsigned Opcode = 0; 12523 // Check for x CC y ? x : y. 12524 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12525 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12526 switch (CC) { 12527 default: break; 12528 case ISD::SETULT: 12529 // Converting this to a min would handle NaNs incorrectly, and swapping 12530 // the operands would cause it to handle comparisons between positive 12531 // and negative zero incorrectly. 12532 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12533 if (!UnsafeFPMath && 12534 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12535 break; 12536 std::swap(LHS, RHS); 12537 } 12538 Opcode = X86ISD::FMIN; 12539 break; 12540 case ISD::SETOLE: 12541 // Converting this to a min would handle comparisons between positive 12542 // and negative zero incorrectly. 12543 if (!UnsafeFPMath && 12544 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12545 break; 12546 Opcode = X86ISD::FMIN; 12547 break; 12548 case ISD::SETULE: 12549 // Converting this to a min would handle both negative zeros and NaNs 12550 // incorrectly, but we can swap the operands to fix both. 12551 std::swap(LHS, RHS); 12552 case ISD::SETOLT: 12553 case ISD::SETLT: 12554 case ISD::SETLE: 12555 Opcode = X86ISD::FMIN; 12556 break; 12557 12558 case ISD::SETOGE: 12559 // Converting this to a max would handle comparisons between positive 12560 // and negative zero incorrectly. 12561 if (!UnsafeFPMath && 12562 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12563 break; 12564 Opcode = X86ISD::FMAX; 12565 break; 12566 case ISD::SETUGT: 12567 // Converting this to a max would handle NaNs incorrectly, and swapping 12568 // the operands would cause it to handle comparisons between positive 12569 // and negative zero incorrectly. 12570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12571 if (!UnsafeFPMath && 12572 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12573 break; 12574 std::swap(LHS, RHS); 12575 } 12576 Opcode = X86ISD::FMAX; 12577 break; 12578 case ISD::SETUGE: 12579 // Converting this to a max would handle both negative zeros and NaNs 12580 // incorrectly, but we can swap the operands to fix both. 12581 std::swap(LHS, RHS); 12582 case ISD::SETOGT: 12583 case ISD::SETGT: 12584 case ISD::SETGE: 12585 Opcode = X86ISD::FMAX; 12586 break; 12587 } 12588 // Check for x CC y ? y : x -- a min/max with reversed arms. 12589 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12590 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12591 switch (CC) { 12592 default: break; 12593 case ISD::SETOGE: 12594 // Converting this to a min would handle comparisons between positive 12595 // and negative zero incorrectly, and swapping the operands would 12596 // cause it to handle NaNs incorrectly. 12597 if (!UnsafeFPMath && 12598 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12599 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12600 break; 12601 std::swap(LHS, RHS); 12602 } 12603 Opcode = X86ISD::FMIN; 12604 break; 12605 case ISD::SETUGT: 12606 // Converting this to a min would handle NaNs incorrectly. 12607 if (!UnsafeFPMath && 12608 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12609 break; 12610 Opcode = X86ISD::FMIN; 12611 break; 12612 case ISD::SETUGE: 12613 // Converting this to a min would handle both negative zeros and NaNs 12614 // incorrectly, but we can swap the operands to fix both. 12615 std::swap(LHS, RHS); 12616 case ISD::SETOGT: 12617 case ISD::SETGT: 12618 case ISD::SETGE: 12619 Opcode = X86ISD::FMIN; 12620 break; 12621 12622 case ISD::SETULT: 12623 // Converting this to a max would handle NaNs incorrectly. 12624 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12625 break; 12626 Opcode = X86ISD::FMAX; 12627 break; 12628 case ISD::SETOLE: 12629 // Converting this to a max would handle comparisons between positive 12630 // and negative zero incorrectly, and swapping the operands would 12631 // cause it to handle NaNs incorrectly. 12632 if (!UnsafeFPMath && 12633 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 12634 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12635 break; 12636 std::swap(LHS, RHS); 12637 } 12638 Opcode = X86ISD::FMAX; 12639 break; 12640 case ISD::SETULE: 12641 // Converting this to a max would handle both negative zeros and NaNs 12642 // incorrectly, but we can swap the operands to fix both. 12643 std::swap(LHS, RHS); 12644 case ISD::SETOLT: 12645 case ISD::SETLT: 12646 case ISD::SETLE: 12647 Opcode = X86ISD::FMAX; 12648 break; 12649 } 12650 } 12651 12652 if (Opcode) 12653 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 12654 } 12655 12656 // If this is a select between two integer constants, try to do some 12657 // optimizations. 12658 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 12659 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 12660 // Don't do this for crazy integer types. 12661 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 12662 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 12663 // so that TrueC (the true value) is larger than FalseC. 12664 bool NeedsCondInvert = false; 12665 12666 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 12667 // Efficiently invertible. 12668 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 12669 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 12670 isa<ConstantSDNode>(Cond.getOperand(1))))) { 12671 NeedsCondInvert = true; 12672 std::swap(TrueC, FalseC); 12673 } 12674 12675 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 12676 if (FalseC->getAPIntValue() == 0 && 12677 TrueC->getAPIntValue().isPowerOf2()) { 12678 if (NeedsCondInvert) // Invert the condition if needed. 12679 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12680 DAG.getConstant(1, Cond.getValueType())); 12681 12682 // Zero extend the condition if needed. 12683 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 12684 12685 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12686 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 12687 DAG.getConstant(ShAmt, MVT::i8)); 12688 } 12689 12690 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 12691 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12692 if (NeedsCondInvert) // Invert the condition if needed. 12693 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12694 DAG.getConstant(1, Cond.getValueType())); 12695 12696 // Zero extend the condition if needed. 12697 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12698 FalseC->getValueType(0), Cond); 12699 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12700 SDValue(FalseC, 0)); 12701 } 12702 12703 // Optimize cases that will turn into an LEA instruction. This requires 12704 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12705 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12706 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12707 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12708 12709 bool isFastMultiplier = false; 12710 if (Diff < 10) { 12711 switch ((unsigned char)Diff) { 12712 default: break; 12713 case 1: // result = add base, cond 12714 case 2: // result = lea base( , cond*2) 12715 case 3: // result = lea base(cond, cond*2) 12716 case 4: // result = lea base( , cond*4) 12717 case 5: // result = lea base(cond, cond*4) 12718 case 8: // result = lea base( , cond*8) 12719 case 9: // result = lea base(cond, cond*8) 12720 isFastMultiplier = true; 12721 break; 12722 } 12723 } 12724 12725 if (isFastMultiplier) { 12726 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12727 if (NeedsCondInvert) // Invert the condition if needed. 12728 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12729 DAG.getConstant(1, Cond.getValueType())); 12730 12731 // Zero extend the condition if needed. 12732 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12733 Cond); 12734 // Scale the condition by the difference. 12735 if (Diff != 1) 12736 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12737 DAG.getConstant(Diff, Cond.getValueType())); 12738 12739 // Add the base if non-zero. 12740 if (FalseC->getAPIntValue() != 0) 12741 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12742 SDValue(FalseC, 0)); 12743 return Cond; 12744 } 12745 } 12746 } 12747 } 12748 12749 return SDValue(); 12750} 12751 12752/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 12753static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 12754 TargetLowering::DAGCombinerInfo &DCI) { 12755 DebugLoc DL = N->getDebugLoc(); 12756 12757 // If the flag operand isn't dead, don't touch this CMOV. 12758 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 12759 return SDValue(); 12760 12761 SDValue FalseOp = N->getOperand(0); 12762 SDValue TrueOp = N->getOperand(1); 12763 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 12764 SDValue Cond = N->getOperand(3); 12765 if (CC == X86::COND_E || CC == X86::COND_NE) { 12766 switch (Cond.getOpcode()) { 12767 default: break; 12768 case X86ISD::BSR: 12769 case X86ISD::BSF: 12770 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 12771 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 12772 return (CC == X86::COND_E) ? FalseOp : TrueOp; 12773 } 12774 } 12775 12776 // If this is a select between two integer constants, try to do some 12777 // optimizations. Note that the operands are ordered the opposite of SELECT 12778 // operands. 12779 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 12780 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 12781 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 12782 // larger than FalseC (the false value). 12783 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 12784 CC = X86::GetOppositeBranchCondition(CC); 12785 std::swap(TrueC, FalseC); 12786 } 12787 12788 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 12789 // This is efficient for any integer data type (including i8/i16) and 12790 // shift amount. 12791 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 12792 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12793 DAG.getConstant(CC, MVT::i8), Cond); 12794 12795 // Zero extend the condition if needed. 12796 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 12797 12798 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12799 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 12800 DAG.getConstant(ShAmt, MVT::i8)); 12801 if (N->getNumValues() == 2) // Dead flag value? 12802 return DCI.CombineTo(N, Cond, SDValue()); 12803 return Cond; 12804 } 12805 12806 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 12807 // for any integer data type, including i8/i16. 12808 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12809 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12810 DAG.getConstant(CC, MVT::i8), Cond); 12811 12812 // Zero extend the condition if needed. 12813 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12814 FalseC->getValueType(0), Cond); 12815 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12816 SDValue(FalseC, 0)); 12817 12818 if (N->getNumValues() == 2) // Dead flag value? 12819 return DCI.CombineTo(N, Cond, SDValue()); 12820 return Cond; 12821 } 12822 12823 // Optimize cases that will turn into an LEA instruction. This requires 12824 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12825 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12826 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12827 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12828 12829 bool isFastMultiplier = false; 12830 if (Diff < 10) { 12831 switch ((unsigned char)Diff) { 12832 default: break; 12833 case 1: // result = add base, cond 12834 case 2: // result = lea base( , cond*2) 12835 case 3: // result = lea base(cond, cond*2) 12836 case 4: // result = lea base( , cond*4) 12837 case 5: // result = lea base(cond, cond*4) 12838 case 8: // result = lea base( , cond*8) 12839 case 9: // result = lea base(cond, cond*8) 12840 isFastMultiplier = true; 12841 break; 12842 } 12843 } 12844 12845 if (isFastMultiplier) { 12846 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12847 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12848 DAG.getConstant(CC, MVT::i8), Cond); 12849 // Zero extend the condition if needed. 12850 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12851 Cond); 12852 // Scale the condition by the difference. 12853 if (Diff != 1) 12854 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12855 DAG.getConstant(Diff, Cond.getValueType())); 12856 12857 // Add the base if non-zero. 12858 if (FalseC->getAPIntValue() != 0) 12859 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12860 SDValue(FalseC, 0)); 12861 if (N->getNumValues() == 2) // Dead flag value? 12862 return DCI.CombineTo(N, Cond, SDValue()); 12863 return Cond; 12864 } 12865 } 12866 } 12867 } 12868 return SDValue(); 12869} 12870 12871 12872/// PerformMulCombine - Optimize a single multiply with constant into two 12873/// in order to implement it with two cheaper instructions, e.g. 12874/// LEA + SHL, LEA + LEA. 12875static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 12876 TargetLowering::DAGCombinerInfo &DCI) { 12877 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 12878 return SDValue(); 12879 12880 EVT VT = N->getValueType(0); 12881 if (VT != MVT::i64) 12882 return SDValue(); 12883 12884 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 12885 if (!C) 12886 return SDValue(); 12887 uint64_t MulAmt = C->getZExtValue(); 12888 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 12889 return SDValue(); 12890 12891 uint64_t MulAmt1 = 0; 12892 uint64_t MulAmt2 = 0; 12893 if ((MulAmt % 9) == 0) { 12894 MulAmt1 = 9; 12895 MulAmt2 = MulAmt / 9; 12896 } else if ((MulAmt % 5) == 0) { 12897 MulAmt1 = 5; 12898 MulAmt2 = MulAmt / 5; 12899 } else if ((MulAmt % 3) == 0) { 12900 MulAmt1 = 3; 12901 MulAmt2 = MulAmt / 3; 12902 } 12903 if (MulAmt2 && 12904 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 12905 DebugLoc DL = N->getDebugLoc(); 12906 12907 if (isPowerOf2_64(MulAmt2) && 12908 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 12909 // If second multiplifer is pow2, issue it first. We want the multiply by 12910 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 12911 // is an add. 12912 std::swap(MulAmt1, MulAmt2); 12913 12914 SDValue NewMul; 12915 if (isPowerOf2_64(MulAmt1)) 12916 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 12917 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 12918 else 12919 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 12920 DAG.getConstant(MulAmt1, VT)); 12921 12922 if (isPowerOf2_64(MulAmt2)) 12923 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 12924 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 12925 else 12926 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 12927 DAG.getConstant(MulAmt2, VT)); 12928 12929 // Do not add new nodes to DAG combiner worklist. 12930 DCI.CombineTo(N, NewMul, false); 12931 } 12932 return SDValue(); 12933} 12934 12935static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 12936 SDValue N0 = N->getOperand(0); 12937 SDValue N1 = N->getOperand(1); 12938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 12939 EVT VT = N0.getValueType(); 12940 12941 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 12942 // since the result of setcc_c is all zero's or all ones. 12943 if (N1C && N0.getOpcode() == ISD::AND && 12944 N0.getOperand(1).getOpcode() == ISD::Constant) { 12945 SDValue N00 = N0.getOperand(0); 12946 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 12947 ((N00.getOpcode() == ISD::ANY_EXTEND || 12948 N00.getOpcode() == ISD::ZERO_EXTEND) && 12949 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 12950 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 12951 APInt ShAmt = N1C->getAPIntValue(); 12952 Mask = Mask.shl(ShAmt); 12953 if (Mask != 0) 12954 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 12955 N00, DAG.getConstant(Mask, VT)); 12956 } 12957 } 12958 12959 return SDValue(); 12960} 12961 12962/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 12963/// when possible. 12964static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 12965 const X86Subtarget *Subtarget) { 12966 EVT VT = N->getValueType(0); 12967 if (!VT.isVector() && VT.isInteger() && 12968 N->getOpcode() == ISD::SHL) 12969 return PerformSHLCombine(N, DAG); 12970 12971 // On X86 with SSE2 support, we can transform this to a vector shift if 12972 // all elements are shifted by the same amount. We can't do this in legalize 12973 // because the a constant vector is typically transformed to a constant pool 12974 // so we have no knowledge of the shift amount. 12975 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 12976 return SDValue(); 12977 12978 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 12979 return SDValue(); 12980 12981 SDValue ShAmtOp = N->getOperand(1); 12982 EVT EltVT = VT.getVectorElementType(); 12983 DebugLoc DL = N->getDebugLoc(); 12984 SDValue BaseShAmt = SDValue(); 12985 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 12986 unsigned NumElts = VT.getVectorNumElements(); 12987 unsigned i = 0; 12988 for (; i != NumElts; ++i) { 12989 SDValue Arg = ShAmtOp.getOperand(i); 12990 if (Arg.getOpcode() == ISD::UNDEF) continue; 12991 BaseShAmt = Arg; 12992 break; 12993 } 12994 for (; i != NumElts; ++i) { 12995 SDValue Arg = ShAmtOp.getOperand(i); 12996 if (Arg.getOpcode() == ISD::UNDEF) continue; 12997 if (Arg != BaseShAmt) { 12998 return SDValue(); 12999 } 13000 } 13001 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13002 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13003 SDValue InVec = ShAmtOp.getOperand(0); 13004 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13005 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13006 unsigned i = 0; 13007 for (; i != NumElts; ++i) { 13008 SDValue Arg = InVec.getOperand(i); 13009 if (Arg.getOpcode() == ISD::UNDEF) continue; 13010 BaseShAmt = Arg; 13011 break; 13012 } 13013 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13015 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13016 if (C->getZExtValue() == SplatIdx) 13017 BaseShAmt = InVec.getOperand(1); 13018 } 13019 } 13020 if (BaseShAmt.getNode() == 0) 13021 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13022 DAG.getIntPtrConstant(0)); 13023 } else 13024 return SDValue(); 13025 13026 // The shift amount is an i32. 13027 if (EltVT.bitsGT(MVT::i32)) 13028 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13029 else if (EltVT.bitsLT(MVT::i32)) 13030 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13031 13032 // The shift amount is identical so we can do a vector shift. 13033 SDValue ValOp = N->getOperand(0); 13034 switch (N->getOpcode()) { 13035 default: 13036 llvm_unreachable("Unknown shift opcode!"); 13037 break; 13038 case ISD::SHL: 13039 if (VT == MVT::v2i64) 13040 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13041 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13042 ValOp, BaseShAmt); 13043 if (VT == MVT::v4i32) 13044 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13045 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13046 ValOp, BaseShAmt); 13047 if (VT == MVT::v8i16) 13048 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13049 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13050 ValOp, BaseShAmt); 13051 break; 13052 case ISD::SRA: 13053 if (VT == MVT::v4i32) 13054 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13055 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13056 ValOp, BaseShAmt); 13057 if (VT == MVT::v8i16) 13058 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13059 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13060 ValOp, BaseShAmt); 13061 break; 13062 case ISD::SRL: 13063 if (VT == MVT::v2i64) 13064 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13065 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13066 ValOp, BaseShAmt); 13067 if (VT == MVT::v4i32) 13068 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13069 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13070 ValOp, BaseShAmt); 13071 if (VT == MVT::v8i16) 13072 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13073 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13074 ValOp, BaseShAmt); 13075 break; 13076 } 13077 return SDValue(); 13078} 13079 13080 13081// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13082// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13083// and friends. Likewise for OR -> CMPNEQSS. 13084static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13085 TargetLowering::DAGCombinerInfo &DCI, 13086 const X86Subtarget *Subtarget) { 13087 unsigned opcode; 13088 13089 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13090 // we're requiring SSE2 for both. 13091 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13092 SDValue N0 = N->getOperand(0); 13093 SDValue N1 = N->getOperand(1); 13094 SDValue CMP0 = N0->getOperand(1); 13095 SDValue CMP1 = N1->getOperand(1); 13096 DebugLoc DL = N->getDebugLoc(); 13097 13098 // The SETCCs should both refer to the same CMP. 13099 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13100 return SDValue(); 13101 13102 SDValue CMP00 = CMP0->getOperand(0); 13103 SDValue CMP01 = CMP0->getOperand(1); 13104 EVT VT = CMP00.getValueType(); 13105 13106 if (VT == MVT::f32 || VT == MVT::f64) { 13107 bool ExpectingFlags = false; 13108 // Check for any users that want flags: 13109 for (SDNode::use_iterator UI = N->use_begin(), 13110 UE = N->use_end(); 13111 !ExpectingFlags && UI != UE; ++UI) 13112 switch (UI->getOpcode()) { 13113 default: 13114 case ISD::BR_CC: 13115 case ISD::BRCOND: 13116 case ISD::SELECT: 13117 ExpectingFlags = true; 13118 break; 13119 case ISD::CopyToReg: 13120 case ISD::SIGN_EXTEND: 13121 case ISD::ZERO_EXTEND: 13122 case ISD::ANY_EXTEND: 13123 break; 13124 } 13125 13126 if (!ExpectingFlags) { 13127 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13128 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13129 13130 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13131 X86::CondCode tmp = cc0; 13132 cc0 = cc1; 13133 cc1 = tmp; 13134 } 13135 13136 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13137 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13138 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13139 X86ISD::NodeType NTOperator = is64BitFP ? 13140 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13141 // FIXME: need symbolic constants for these magic numbers. 13142 // See X86ATTInstPrinter.cpp:printSSECC(). 13143 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13144 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13145 DAG.getConstant(x86cc, MVT::i8)); 13146 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13147 OnesOrZeroesF); 13148 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13149 DAG.getConstant(1, MVT::i32)); 13150 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13151 return OneBitOfTruth; 13152 } 13153 } 13154 } 13155 } 13156 return SDValue(); 13157} 13158 13159/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13160/// so it can be folded inside ANDNP. 13161static bool CanFoldXORWithAllOnes(const SDNode *N) { 13162 EVT VT = N->getValueType(0); 13163 13164 // Match direct AllOnes for 128 and 256-bit vectors 13165 if (ISD::isBuildVectorAllOnes(N)) 13166 return true; 13167 13168 // Look through a bit convert. 13169 if (N->getOpcode() == ISD::BITCAST) 13170 N = N->getOperand(0).getNode(); 13171 13172 // Sometimes the operand may come from a insert_subvector building a 256-bit 13173 // allones vector 13174 if (VT.getSizeInBits() == 256 && 13175 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13176 SDValue V1 = N->getOperand(0); 13177 SDValue V2 = N->getOperand(1); 13178 13179 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13180 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13181 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13182 ISD::isBuildVectorAllOnes(V2.getNode())) 13183 return true; 13184 } 13185 13186 return false; 13187} 13188 13189static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13190 TargetLowering::DAGCombinerInfo &DCI, 13191 const X86Subtarget *Subtarget) { 13192 if (DCI.isBeforeLegalizeOps()) 13193 return SDValue(); 13194 13195 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13196 if (R.getNode()) 13197 return R; 13198 13199 // Want to form ANDNP nodes: 13200 // 1) In the hopes of then easily combining them with OR and AND nodes 13201 // to form PBLEND/PSIGN. 13202 // 2) To match ANDN packed intrinsics 13203 EVT VT = N->getValueType(0); 13204 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13205 return SDValue(); 13206 13207 SDValue N0 = N->getOperand(0); 13208 SDValue N1 = N->getOperand(1); 13209 DebugLoc DL = N->getDebugLoc(); 13210 13211 // Check LHS for vnot 13212 if (N0.getOpcode() == ISD::XOR && 13213 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13214 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13215 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13216 13217 // Check RHS for vnot 13218 if (N1.getOpcode() == ISD::XOR && 13219 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13220 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13221 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13222 13223 return SDValue(); 13224} 13225 13226static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13227 TargetLowering::DAGCombinerInfo &DCI, 13228 const X86Subtarget *Subtarget) { 13229 if (DCI.isBeforeLegalizeOps()) 13230 return SDValue(); 13231 13232 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13233 if (R.getNode()) 13234 return R; 13235 13236 EVT VT = N->getValueType(0); 13237 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 13238 return SDValue(); 13239 13240 SDValue N0 = N->getOperand(0); 13241 SDValue N1 = N->getOperand(1); 13242 13243 // look for psign/blend 13244 if (Subtarget->hasSSSE3()) { 13245 if (VT == MVT::v2i64) { 13246 // Canonicalize pandn to RHS 13247 if (N0.getOpcode() == X86ISD::ANDNP) 13248 std::swap(N0, N1); 13249 // or (and (m, x), (pandn m, y)) 13250 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13251 SDValue Mask = N1.getOperand(0); 13252 SDValue X = N1.getOperand(1); 13253 SDValue Y; 13254 if (N0.getOperand(0) == Mask) 13255 Y = N0.getOperand(1); 13256 if (N0.getOperand(1) == Mask) 13257 Y = N0.getOperand(0); 13258 13259 // Check to see if the mask appeared in both the AND and ANDNP and 13260 if (!Y.getNode()) 13261 return SDValue(); 13262 13263 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13264 if (Mask.getOpcode() != ISD::BITCAST || 13265 X.getOpcode() != ISD::BITCAST || 13266 Y.getOpcode() != ISD::BITCAST) 13267 return SDValue(); 13268 13269 // Look through mask bitcast. 13270 Mask = Mask.getOperand(0); 13271 EVT MaskVT = Mask.getValueType(); 13272 13273 // Validate that the Mask operand is a vector sra node. The sra node 13274 // will be an intrinsic. 13275 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13276 return SDValue(); 13277 13278 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13279 // there is no psrai.b 13280 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13281 case Intrinsic::x86_sse2_psrai_w: 13282 case Intrinsic::x86_sse2_psrai_d: 13283 break; 13284 default: return SDValue(); 13285 } 13286 13287 // Check that the SRA is all signbits. 13288 SDValue SraC = Mask.getOperand(2); 13289 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13290 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13291 if ((SraAmt + 1) != EltBits) 13292 return SDValue(); 13293 13294 DebugLoc DL = N->getDebugLoc(); 13295 13296 // Now we know we at least have a plendvb with the mask val. See if 13297 // we can form a psignb/w/d. 13298 // psign = x.type == y.type == mask.type && y = sub(0, x); 13299 X = X.getOperand(0); 13300 Y = Y.getOperand(0); 13301 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13302 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13303 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 13304 unsigned Opc = 0; 13305 switch (EltBits) { 13306 case 8: Opc = X86ISD::PSIGNB; break; 13307 case 16: Opc = X86ISD::PSIGNW; break; 13308 case 32: Opc = X86ISD::PSIGND; break; 13309 default: break; 13310 } 13311 if (Opc) { 13312 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 13313 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 13314 } 13315 } 13316 // PBLENDVB only available on SSE 4.1 13317 if (!Subtarget->hasSSE41()) 13318 return SDValue(); 13319 13320 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 13321 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 13322 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 13323 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask); 13324 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 13325 } 13326 } 13327 } 13328 13329 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13330 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13331 std::swap(N0, N1); 13332 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13333 return SDValue(); 13334 if (!N0.hasOneUse() || !N1.hasOneUse()) 13335 return SDValue(); 13336 13337 SDValue ShAmt0 = N0.getOperand(1); 13338 if (ShAmt0.getValueType() != MVT::i8) 13339 return SDValue(); 13340 SDValue ShAmt1 = N1.getOperand(1); 13341 if (ShAmt1.getValueType() != MVT::i8) 13342 return SDValue(); 13343 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13344 ShAmt0 = ShAmt0.getOperand(0); 13345 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13346 ShAmt1 = ShAmt1.getOperand(0); 13347 13348 DebugLoc DL = N->getDebugLoc(); 13349 unsigned Opc = X86ISD::SHLD; 13350 SDValue Op0 = N0.getOperand(0); 13351 SDValue Op1 = N1.getOperand(0); 13352 if (ShAmt0.getOpcode() == ISD::SUB) { 13353 Opc = X86ISD::SHRD; 13354 std::swap(Op0, Op1); 13355 std::swap(ShAmt0, ShAmt1); 13356 } 13357 13358 unsigned Bits = VT.getSizeInBits(); 13359 if (ShAmt1.getOpcode() == ISD::SUB) { 13360 SDValue Sum = ShAmt1.getOperand(0); 13361 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13362 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13363 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13364 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13365 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13366 return DAG.getNode(Opc, DL, VT, 13367 Op0, Op1, 13368 DAG.getNode(ISD::TRUNCATE, DL, 13369 MVT::i8, ShAmt0)); 13370 } 13371 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13372 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13373 if (ShAmt0C && 13374 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13375 return DAG.getNode(Opc, DL, VT, 13376 N0.getOperand(0), N1.getOperand(0), 13377 DAG.getNode(ISD::TRUNCATE, DL, 13378 MVT::i8, ShAmt0)); 13379 } 13380 13381 return SDValue(); 13382} 13383 13384/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 13385static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 13386 const X86Subtarget *Subtarget) { 13387 StoreSDNode *St = cast<StoreSDNode>(N); 13388 EVT VT = St->getValue().getValueType(); 13389 EVT StVT = St->getMemoryVT(); 13390 DebugLoc dl = St->getDebugLoc(); 13391 SDValue StoredVal = St->getOperand(1); 13392 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13393 13394 // If we are saving a concatination of two XMM registers, perform two stores. 13395 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 13396 // 128-bit ones. If in the future the cost becomes only one memory access the 13397 // first version would be better. 13398 if (VT.getSizeInBits() == 256 && 13399 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 13400 StoredVal.getNumOperands() == 2) { 13401 13402 SDValue Value0 = StoredVal.getOperand(0); 13403 SDValue Value1 = StoredVal.getOperand(1); 13404 13405 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 13406 SDValue Ptr0 = St->getBasePtr(); 13407 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 13408 13409 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 13410 St->getPointerInfo(), St->isVolatile(), 13411 St->isNonTemporal(), St->getAlignment()); 13412 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 13413 St->getPointerInfo(), St->isVolatile(), 13414 St->isNonTemporal(), St->getAlignment()); 13415 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 13416 } 13417 13418 // Optimize trunc store (of multiple scalars) to shuffle and store. 13419 // First, pack all of the elements in one place. Next, store to memory 13420 // in fewer chunks. 13421 if (St->isTruncatingStore() && VT.isVector()) { 13422 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13423 unsigned NumElems = VT.getVectorNumElements(); 13424 assert(StVT != VT && "Cannot truncate to the same type"); 13425 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 13426 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 13427 13428 // From, To sizes and ElemCount must be pow of two 13429 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 13430 // We are going to use the original vector elt for storing. 13431 // accumulated smaller vector elements must be a multiple of bigger size. 13432 if (0 != (NumElems * ToSz) % FromSz) return SDValue(); 13433 unsigned SizeRatio = FromSz / ToSz; 13434 13435 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 13436 13437 // Create a type on which we perform the shuffle 13438 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 13439 StVT.getScalarType(), NumElems*SizeRatio); 13440 13441 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 13442 13443 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 13444 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13445 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 13446 13447 // Can't shuffle using an illegal type 13448 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13449 13450 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 13451 DAG.getUNDEF(WideVec.getValueType()), 13452 ShuffleVec.data()); 13453 // At this point all of the data is stored at the bottom of the 13454 // register. We now need to save it to mem. 13455 13456 // Find the largest store unit 13457 MVT StoreType = MVT::i8; 13458 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13459 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13460 MVT Tp = (MVT::SimpleValueType)tp; 13461 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 13462 StoreType = Tp; 13463 } 13464 13465 // Bitcast the original vector into a vector of store-size units 13466 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 13467 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 13468 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 13469 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 13470 SmallVector<SDValue, 8> Chains; 13471 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 13472 TLI.getPointerTy()); 13473 SDValue Ptr = St->getBasePtr(); 13474 13475 // Perform one or more big stores into memory. 13476 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 13477 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 13478 StoreType, ShuffWide, 13479 DAG.getIntPtrConstant(i)); 13480 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 13481 St->getPointerInfo(), St->isVolatile(), 13482 St->isNonTemporal(), St->getAlignment()); 13483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 13484 Chains.push_back(Ch); 13485 } 13486 13487 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 13488 Chains.size()); 13489 } 13490 13491 13492 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 13493 // the FP state in cases where an emms may be missing. 13494 // A preferable solution to the general problem is to figure out the right 13495 // places to insert EMMS. This qualifies as a quick hack. 13496 13497 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 13498 if (VT.getSizeInBits() != 64) 13499 return SDValue(); 13500 13501 const Function *F = DAG.getMachineFunction().getFunction(); 13502 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 13503 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 13504 && Subtarget->hasSSE2(); 13505 if ((VT.isVector() || 13506 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 13507 isa<LoadSDNode>(St->getValue()) && 13508 !cast<LoadSDNode>(St->getValue())->isVolatile() && 13509 St->getChain().hasOneUse() && !St->isVolatile()) { 13510 SDNode* LdVal = St->getValue().getNode(); 13511 LoadSDNode *Ld = 0; 13512 int TokenFactorIndex = -1; 13513 SmallVector<SDValue, 8> Ops; 13514 SDNode* ChainVal = St->getChain().getNode(); 13515 // Must be a store of a load. We currently handle two cases: the load 13516 // is a direct child, and it's under an intervening TokenFactor. It is 13517 // possible to dig deeper under nested TokenFactors. 13518 if (ChainVal == LdVal) 13519 Ld = cast<LoadSDNode>(St->getChain()); 13520 else if (St->getValue().hasOneUse() && 13521 ChainVal->getOpcode() == ISD::TokenFactor) { 13522 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 13523 if (ChainVal->getOperand(i).getNode() == LdVal) { 13524 TokenFactorIndex = i; 13525 Ld = cast<LoadSDNode>(St->getValue()); 13526 } else 13527 Ops.push_back(ChainVal->getOperand(i)); 13528 } 13529 } 13530 13531 if (!Ld || !ISD::isNormalLoad(Ld)) 13532 return SDValue(); 13533 13534 // If this is not the MMX case, i.e. we are just turning i64 load/store 13535 // into f64 load/store, avoid the transformation if there are multiple 13536 // uses of the loaded value. 13537 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 13538 return SDValue(); 13539 13540 DebugLoc LdDL = Ld->getDebugLoc(); 13541 DebugLoc StDL = N->getDebugLoc(); 13542 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 13543 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 13544 // pair instead. 13545 if (Subtarget->is64Bit() || F64IsLegal) { 13546 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 13547 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 13548 Ld->getPointerInfo(), Ld->isVolatile(), 13549 Ld->isNonTemporal(), Ld->getAlignment()); 13550 SDValue NewChain = NewLd.getValue(1); 13551 if (TokenFactorIndex != -1) { 13552 Ops.push_back(NewChain); 13553 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13554 Ops.size()); 13555 } 13556 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 13557 St->getPointerInfo(), 13558 St->isVolatile(), St->isNonTemporal(), 13559 St->getAlignment()); 13560 } 13561 13562 // Otherwise, lower to two pairs of 32-bit loads / stores. 13563 SDValue LoAddr = Ld->getBasePtr(); 13564 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 13565 DAG.getConstant(4, MVT::i32)); 13566 13567 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 13568 Ld->getPointerInfo(), 13569 Ld->isVolatile(), Ld->isNonTemporal(), 13570 Ld->getAlignment()); 13571 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 13572 Ld->getPointerInfo().getWithOffset(4), 13573 Ld->isVolatile(), Ld->isNonTemporal(), 13574 MinAlign(Ld->getAlignment(), 4)); 13575 13576 SDValue NewChain = LoLd.getValue(1); 13577 if (TokenFactorIndex != -1) { 13578 Ops.push_back(LoLd); 13579 Ops.push_back(HiLd); 13580 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13581 Ops.size()); 13582 } 13583 13584 LoAddr = St->getBasePtr(); 13585 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 13586 DAG.getConstant(4, MVT::i32)); 13587 13588 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 13589 St->getPointerInfo(), 13590 St->isVolatile(), St->isNonTemporal(), 13591 St->getAlignment()); 13592 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 13593 St->getPointerInfo().getWithOffset(4), 13594 St->isVolatile(), 13595 St->isNonTemporal(), 13596 MinAlign(St->getAlignment(), 4)); 13597 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 13598 } 13599 return SDValue(); 13600} 13601 13602/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 13603/// X86ISD::FXOR nodes. 13604static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 13605 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 13606 // F[X]OR(0.0, x) -> x 13607 // F[X]OR(x, 0.0) -> x 13608 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13609 if (C->getValueAPF().isPosZero()) 13610 return N->getOperand(1); 13611 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13612 if (C->getValueAPF().isPosZero()) 13613 return N->getOperand(0); 13614 return SDValue(); 13615} 13616 13617/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 13618static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 13619 // FAND(0.0, x) -> 0.0 13620 // FAND(x, 0.0) -> 0.0 13621 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13622 if (C->getValueAPF().isPosZero()) 13623 return N->getOperand(0); 13624 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13625 if (C->getValueAPF().isPosZero()) 13626 return N->getOperand(1); 13627 return SDValue(); 13628} 13629 13630static SDValue PerformBTCombine(SDNode *N, 13631 SelectionDAG &DAG, 13632 TargetLowering::DAGCombinerInfo &DCI) { 13633 // BT ignores high bits in the bit index operand. 13634 SDValue Op1 = N->getOperand(1); 13635 if (Op1.hasOneUse()) { 13636 unsigned BitWidth = Op1.getValueSizeInBits(); 13637 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 13638 APInt KnownZero, KnownOne; 13639 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 13640 !DCI.isBeforeLegalizeOps()); 13641 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13642 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 13643 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 13644 DCI.CommitTargetLoweringOpt(TLO); 13645 } 13646 return SDValue(); 13647} 13648 13649static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 13650 SDValue Op = N->getOperand(0); 13651 if (Op.getOpcode() == ISD::BITCAST) 13652 Op = Op.getOperand(0); 13653 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 13654 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 13655 VT.getVectorElementType().getSizeInBits() == 13656 OpVT.getVectorElementType().getSizeInBits()) { 13657 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 13658 } 13659 return SDValue(); 13660} 13661 13662static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 13663 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 13664 // (and (i32 x86isd::setcc_carry), 1) 13665 // This eliminates the zext. This transformation is necessary because 13666 // ISD::SETCC is always legalized to i8. 13667 DebugLoc dl = N->getDebugLoc(); 13668 SDValue N0 = N->getOperand(0); 13669 EVT VT = N->getValueType(0); 13670 if (N0.getOpcode() == ISD::AND && 13671 N0.hasOneUse() && 13672 N0.getOperand(0).hasOneUse()) { 13673 SDValue N00 = N0.getOperand(0); 13674 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 13675 return SDValue(); 13676 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 13677 if (!C || C->getZExtValue() != 1) 13678 return SDValue(); 13679 return DAG.getNode(ISD::AND, dl, VT, 13680 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 13681 N00.getOperand(0), N00.getOperand(1)), 13682 DAG.getConstant(1, VT)); 13683 } 13684 13685 return SDValue(); 13686} 13687 13688// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 13689static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 13690 unsigned X86CC = N->getConstantOperandVal(0); 13691 SDValue EFLAG = N->getOperand(1); 13692 DebugLoc DL = N->getDebugLoc(); 13693 13694 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 13695 // a zext and produces an all-ones bit which is more useful than 0/1 in some 13696 // cases. 13697 if (X86CC == X86::COND_B) 13698 return DAG.getNode(ISD::AND, DL, MVT::i8, 13699 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 13700 DAG.getConstant(X86CC, MVT::i8), EFLAG), 13701 DAG.getConstant(1, MVT::i8)); 13702 13703 return SDValue(); 13704} 13705 13706static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 13707 const X86TargetLowering *XTLI) { 13708 SDValue Op0 = N->getOperand(0); 13709 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 13710 // a 32-bit target where SSE doesn't support i64->FP operations. 13711 if (Op0.getOpcode() == ISD::LOAD) { 13712 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 13713 EVT VT = Ld->getValueType(0); 13714 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 13715 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 13716 !XTLI->getSubtarget()->is64Bit() && 13717 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 13718 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 13719 Ld->getChain(), Op0, DAG); 13720 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 13721 return FILDChain; 13722 } 13723 } 13724 return SDValue(); 13725} 13726 13727// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 13728static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 13729 X86TargetLowering::DAGCombinerInfo &DCI) { 13730 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 13731 // the result is either zero or one (depending on the input carry bit). 13732 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 13733 if (X86::isZeroNode(N->getOperand(0)) && 13734 X86::isZeroNode(N->getOperand(1)) && 13735 // We don't have a good way to replace an EFLAGS use, so only do this when 13736 // dead right now. 13737 SDValue(N, 1).use_empty()) { 13738 DebugLoc DL = N->getDebugLoc(); 13739 EVT VT = N->getValueType(0); 13740 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 13741 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 13742 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 13743 DAG.getConstant(X86::COND_B,MVT::i8), 13744 N->getOperand(2)), 13745 DAG.getConstant(1, VT)); 13746 return DCI.CombineTo(N, Res1, CarryOut); 13747 } 13748 13749 return SDValue(); 13750} 13751 13752// fold (add Y, (sete X, 0)) -> adc 0, Y 13753// (add Y, (setne X, 0)) -> sbb -1, Y 13754// (sub (sete X, 0), Y) -> sbb 0, Y 13755// (sub (setne X, 0), Y) -> adc -1, Y 13756static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 13757 DebugLoc DL = N->getDebugLoc(); 13758 13759 // Look through ZExts. 13760 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 13761 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 13762 return SDValue(); 13763 13764 SDValue SetCC = Ext.getOperand(0); 13765 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 13766 return SDValue(); 13767 13768 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 13769 if (CC != X86::COND_E && CC != X86::COND_NE) 13770 return SDValue(); 13771 13772 SDValue Cmp = SetCC.getOperand(1); 13773 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 13774 !X86::isZeroNode(Cmp.getOperand(1)) || 13775 !Cmp.getOperand(0).getValueType().isInteger()) 13776 return SDValue(); 13777 13778 SDValue CmpOp0 = Cmp.getOperand(0); 13779 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 13780 DAG.getConstant(1, CmpOp0.getValueType())); 13781 13782 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 13783 if (CC == X86::COND_NE) 13784 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 13785 DL, OtherVal.getValueType(), OtherVal, 13786 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 13787 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 13788 DL, OtherVal.getValueType(), OtherVal, 13789 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 13790} 13791 13792static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 13793 SDValue Op0 = N->getOperand(0); 13794 SDValue Op1 = N->getOperand(1); 13795 13796 // X86 can't encode an immediate LHS of a sub. See if we can push the 13797 // negation into a preceding instruction. 13798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 13799 // If the RHS of the sub is a XOR with one use and a constant, invert the 13800 // immediate. Then add one to the LHS of the sub so we can turn 13801 // X-Y -> X+~Y+1, saving one register. 13802 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 13803 isa<ConstantSDNode>(Op1.getOperand(1))) { 13804 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 13805 EVT VT = Op0.getValueType(); 13806 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 13807 Op1.getOperand(0), 13808 DAG.getConstant(~XorC, VT)); 13809 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 13810 DAG.getConstant(C->getAPIntValue()+1, VT)); 13811 } 13812 } 13813 13814 return OptimizeConditionalInDecrement(N, DAG); 13815} 13816 13817SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 13818 DAGCombinerInfo &DCI) const { 13819 SelectionDAG &DAG = DCI.DAG; 13820 switch (N->getOpcode()) { 13821 default: break; 13822 case ISD::EXTRACT_VECTOR_ELT: 13823 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 13824 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 13825 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 13826 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 13827 case ISD::SUB: return PerformSubCombine(N, DAG); 13828 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 13829 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 13830 case ISD::SHL: 13831 case ISD::SRA: 13832 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 13833 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 13834 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 13835 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 13836 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 13837 case X86ISD::FXOR: 13838 case X86ISD::FOR: return PerformFORCombine(N, DAG); 13839 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 13840 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 13841 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 13842 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 13843 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 13844 case X86ISD::SHUFPS: // Handle all target specific shuffles 13845 case X86ISD::SHUFPD: 13846 case X86ISD::PALIGN: 13847 case X86ISD::PUNPCKHBW: 13848 case X86ISD::PUNPCKHWD: 13849 case X86ISD::PUNPCKHDQ: 13850 case X86ISD::PUNPCKHQDQ: 13851 case X86ISD::UNPCKHPS: 13852 case X86ISD::UNPCKHPD: 13853 case X86ISD::VUNPCKHPSY: 13854 case X86ISD::VUNPCKHPDY: 13855 case X86ISD::PUNPCKLBW: 13856 case X86ISD::PUNPCKLWD: 13857 case X86ISD::PUNPCKLDQ: 13858 case X86ISD::PUNPCKLQDQ: 13859 case X86ISD::UNPCKLPS: 13860 case X86ISD::UNPCKLPD: 13861 case X86ISD::VUNPCKLPSY: 13862 case X86ISD::VUNPCKLPDY: 13863 case X86ISD::MOVHLPS: 13864 case X86ISD::MOVLHPS: 13865 case X86ISD::PSHUFD: 13866 case X86ISD::PSHUFHW: 13867 case X86ISD::PSHUFLW: 13868 case X86ISD::MOVSS: 13869 case X86ISD::MOVSD: 13870 case X86ISD::VPERMILPS: 13871 case X86ISD::VPERMILPSY: 13872 case X86ISD::VPERMILPD: 13873 case X86ISD::VPERMILPDY: 13874 case X86ISD::VPERM2F128: 13875 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 13876 } 13877 13878 return SDValue(); 13879} 13880 13881/// isTypeDesirableForOp - Return true if the target has native support for 13882/// the specified value type and it is 'desirable' to use the type for the 13883/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 13884/// instruction encodings are longer and some i16 instructions are slow. 13885bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 13886 if (!isTypeLegal(VT)) 13887 return false; 13888 if (VT != MVT::i16) 13889 return true; 13890 13891 switch (Opc) { 13892 default: 13893 return true; 13894 case ISD::LOAD: 13895 case ISD::SIGN_EXTEND: 13896 case ISD::ZERO_EXTEND: 13897 case ISD::ANY_EXTEND: 13898 case ISD::SHL: 13899 case ISD::SRL: 13900 case ISD::SUB: 13901 case ISD::ADD: 13902 case ISD::MUL: 13903 case ISD::AND: 13904 case ISD::OR: 13905 case ISD::XOR: 13906 return false; 13907 } 13908} 13909 13910/// IsDesirableToPromoteOp - This method query the target whether it is 13911/// beneficial for dag combiner to promote the specified node. If true, it 13912/// should return the desired promotion type by reference. 13913bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 13914 EVT VT = Op.getValueType(); 13915 if (VT != MVT::i16) 13916 return false; 13917 13918 bool Promote = false; 13919 bool Commute = false; 13920 switch (Op.getOpcode()) { 13921 default: break; 13922 case ISD::LOAD: { 13923 LoadSDNode *LD = cast<LoadSDNode>(Op); 13924 // If the non-extending load has a single use and it's not live out, then it 13925 // might be folded. 13926 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 13927 Op.hasOneUse()*/) { 13928 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 13929 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 13930 // The only case where we'd want to promote LOAD (rather then it being 13931 // promoted as an operand is when it's only use is liveout. 13932 if (UI->getOpcode() != ISD::CopyToReg) 13933 return false; 13934 } 13935 } 13936 Promote = true; 13937 break; 13938 } 13939 case ISD::SIGN_EXTEND: 13940 case ISD::ZERO_EXTEND: 13941 case ISD::ANY_EXTEND: 13942 Promote = true; 13943 break; 13944 case ISD::SHL: 13945 case ISD::SRL: { 13946 SDValue N0 = Op.getOperand(0); 13947 // Look out for (store (shl (load), x)). 13948 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 13949 return false; 13950 Promote = true; 13951 break; 13952 } 13953 case ISD::ADD: 13954 case ISD::MUL: 13955 case ISD::AND: 13956 case ISD::OR: 13957 case ISD::XOR: 13958 Commute = true; 13959 // fallthrough 13960 case ISD::SUB: { 13961 SDValue N0 = Op.getOperand(0); 13962 SDValue N1 = Op.getOperand(1); 13963 if (!Commute && MayFoldLoad(N1)) 13964 return false; 13965 // Avoid disabling potential load folding opportunities. 13966 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 13967 return false; 13968 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 13969 return false; 13970 Promote = true; 13971 } 13972 } 13973 13974 PVT = MVT::i32; 13975 return Promote; 13976} 13977 13978//===----------------------------------------------------------------------===// 13979// X86 Inline Assembly Support 13980//===----------------------------------------------------------------------===// 13981 13982bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 13983 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 13984 13985 std::string AsmStr = IA->getAsmString(); 13986 13987 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 13988 SmallVector<StringRef, 4> AsmPieces; 13989 SplitString(AsmStr, AsmPieces, ";\n"); 13990 13991 switch (AsmPieces.size()) { 13992 default: return false; 13993 case 1: 13994 AsmStr = AsmPieces[0]; 13995 AsmPieces.clear(); 13996 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 13997 13998 // FIXME: this should verify that we are targeting a 486 or better. If not, 13999 // we will turn this bswap into something that will be lowered to logical ops 14000 // instead of emitting the bswap asm. For now, we don't support 486 or lower 14001 // so don't worry about this. 14002 // bswap $0 14003 if (AsmPieces.size() == 2 && 14004 (AsmPieces[0] == "bswap" || 14005 AsmPieces[0] == "bswapq" || 14006 AsmPieces[0] == "bswapl") && 14007 (AsmPieces[1] == "$0" || 14008 AsmPieces[1] == "${0:q}")) { 14009 // No need to check constraints, nothing other than the equivalent of 14010 // "=r,0" would be valid here. 14011 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14012 if (!Ty || Ty->getBitWidth() % 16 != 0) 14013 return false; 14014 return IntrinsicLowering::LowerToByteSwap(CI); 14015 } 14016 // rorw $$8, ${0:w} --> llvm.bswap.i16 14017 if (CI->getType()->isIntegerTy(16) && 14018 AsmPieces.size() == 3 && 14019 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 14020 AsmPieces[1] == "$$8," && 14021 AsmPieces[2] == "${0:w}" && 14022 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14023 AsmPieces.clear(); 14024 const std::string &ConstraintsStr = IA->getConstraintString(); 14025 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14026 std::sort(AsmPieces.begin(), AsmPieces.end()); 14027 if (AsmPieces.size() == 4 && 14028 AsmPieces[0] == "~{cc}" && 14029 AsmPieces[1] == "~{dirflag}" && 14030 AsmPieces[2] == "~{flags}" && 14031 AsmPieces[3] == "~{fpsr}") { 14032 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14033 if (!Ty || Ty->getBitWidth() % 16 != 0) 14034 return false; 14035 return IntrinsicLowering::LowerToByteSwap(CI); 14036 } 14037 } 14038 break; 14039 case 3: 14040 if (CI->getType()->isIntegerTy(32) && 14041 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14042 SmallVector<StringRef, 4> Words; 14043 SplitString(AsmPieces[0], Words, " \t,"); 14044 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14045 Words[2] == "${0:w}") { 14046 Words.clear(); 14047 SplitString(AsmPieces[1], Words, " \t,"); 14048 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 14049 Words[2] == "$0") { 14050 Words.clear(); 14051 SplitString(AsmPieces[2], Words, " \t,"); 14052 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14053 Words[2] == "${0:w}") { 14054 AsmPieces.clear(); 14055 const std::string &ConstraintsStr = IA->getConstraintString(); 14056 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14057 std::sort(AsmPieces.begin(), AsmPieces.end()); 14058 if (AsmPieces.size() == 4 && 14059 AsmPieces[0] == "~{cc}" && 14060 AsmPieces[1] == "~{dirflag}" && 14061 AsmPieces[2] == "~{flags}" && 14062 AsmPieces[3] == "~{fpsr}") { 14063 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14064 if (!Ty || Ty->getBitWidth() % 16 != 0) 14065 return false; 14066 return IntrinsicLowering::LowerToByteSwap(CI); 14067 } 14068 } 14069 } 14070 } 14071 } 14072 14073 if (CI->getType()->isIntegerTy(64)) { 14074 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14075 if (Constraints.size() >= 2 && 14076 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14077 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14078 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14079 SmallVector<StringRef, 4> Words; 14080 SplitString(AsmPieces[0], Words, " \t"); 14081 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 14082 Words.clear(); 14083 SplitString(AsmPieces[1], Words, " \t"); 14084 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 14085 Words.clear(); 14086 SplitString(AsmPieces[2], Words, " \t,"); 14087 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 14088 Words[2] == "%edx") { 14089 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14090 if (!Ty || Ty->getBitWidth() % 16 != 0) 14091 return false; 14092 return IntrinsicLowering::LowerToByteSwap(CI); 14093 } 14094 } 14095 } 14096 } 14097 } 14098 break; 14099 } 14100 return false; 14101} 14102 14103 14104 14105/// getConstraintType - Given a constraint letter, return the type of 14106/// constraint it is for this target. 14107X86TargetLowering::ConstraintType 14108X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14109 if (Constraint.size() == 1) { 14110 switch (Constraint[0]) { 14111 case 'R': 14112 case 'q': 14113 case 'Q': 14114 case 'f': 14115 case 't': 14116 case 'u': 14117 case 'y': 14118 case 'x': 14119 case 'Y': 14120 case 'l': 14121 return C_RegisterClass; 14122 case 'a': 14123 case 'b': 14124 case 'c': 14125 case 'd': 14126 case 'S': 14127 case 'D': 14128 case 'A': 14129 return C_Register; 14130 case 'I': 14131 case 'J': 14132 case 'K': 14133 case 'L': 14134 case 'M': 14135 case 'N': 14136 case 'G': 14137 case 'C': 14138 case 'e': 14139 case 'Z': 14140 return C_Other; 14141 default: 14142 break; 14143 } 14144 } 14145 return TargetLowering::getConstraintType(Constraint); 14146} 14147 14148/// Examine constraint type and operand type and determine a weight value. 14149/// This object must already have been set up with the operand type 14150/// and the current alternative constraint selected. 14151TargetLowering::ConstraintWeight 14152 X86TargetLowering::getSingleConstraintMatchWeight( 14153 AsmOperandInfo &info, const char *constraint) const { 14154 ConstraintWeight weight = CW_Invalid; 14155 Value *CallOperandVal = info.CallOperandVal; 14156 // If we don't have a value, we can't do a match, 14157 // but allow it at the lowest weight. 14158 if (CallOperandVal == NULL) 14159 return CW_Default; 14160 Type *type = CallOperandVal->getType(); 14161 // Look at the constraint type. 14162 switch (*constraint) { 14163 default: 14164 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14165 case 'R': 14166 case 'q': 14167 case 'Q': 14168 case 'a': 14169 case 'b': 14170 case 'c': 14171 case 'd': 14172 case 'S': 14173 case 'D': 14174 case 'A': 14175 if (CallOperandVal->getType()->isIntegerTy()) 14176 weight = CW_SpecificReg; 14177 break; 14178 case 'f': 14179 case 't': 14180 case 'u': 14181 if (type->isFloatingPointTy()) 14182 weight = CW_SpecificReg; 14183 break; 14184 case 'y': 14185 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14186 weight = CW_SpecificReg; 14187 break; 14188 case 'x': 14189 case 'Y': 14190 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 14191 weight = CW_Register; 14192 break; 14193 case 'I': 14194 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14195 if (C->getZExtValue() <= 31) 14196 weight = CW_Constant; 14197 } 14198 break; 14199 case 'J': 14200 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14201 if (C->getZExtValue() <= 63) 14202 weight = CW_Constant; 14203 } 14204 break; 14205 case 'K': 14206 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14207 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 14208 weight = CW_Constant; 14209 } 14210 break; 14211 case 'L': 14212 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14213 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 14214 weight = CW_Constant; 14215 } 14216 break; 14217 case 'M': 14218 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14219 if (C->getZExtValue() <= 3) 14220 weight = CW_Constant; 14221 } 14222 break; 14223 case 'N': 14224 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14225 if (C->getZExtValue() <= 0xff) 14226 weight = CW_Constant; 14227 } 14228 break; 14229 case 'G': 14230 case 'C': 14231 if (dyn_cast<ConstantFP>(CallOperandVal)) { 14232 weight = CW_Constant; 14233 } 14234 break; 14235 case 'e': 14236 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14237 if ((C->getSExtValue() >= -0x80000000LL) && 14238 (C->getSExtValue() <= 0x7fffffffLL)) 14239 weight = CW_Constant; 14240 } 14241 break; 14242 case 'Z': 14243 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14244 if (C->getZExtValue() <= 0xffffffff) 14245 weight = CW_Constant; 14246 } 14247 break; 14248 } 14249 return weight; 14250} 14251 14252/// LowerXConstraint - try to replace an X constraint, which matches anything, 14253/// with another that has more specific requirements based on the type of the 14254/// corresponding operand. 14255const char *X86TargetLowering:: 14256LowerXConstraint(EVT ConstraintVT) const { 14257 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 14258 // 'f' like normal targets. 14259 if (ConstraintVT.isFloatingPoint()) { 14260 if (Subtarget->hasXMMInt()) 14261 return "Y"; 14262 if (Subtarget->hasXMM()) 14263 return "x"; 14264 } 14265 14266 return TargetLowering::LowerXConstraint(ConstraintVT); 14267} 14268 14269/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 14270/// vector. If it is invalid, don't add anything to Ops. 14271void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 14272 std::string &Constraint, 14273 std::vector<SDValue>&Ops, 14274 SelectionDAG &DAG) const { 14275 SDValue Result(0, 0); 14276 14277 // Only support length 1 constraints for now. 14278 if (Constraint.length() > 1) return; 14279 14280 char ConstraintLetter = Constraint[0]; 14281 switch (ConstraintLetter) { 14282 default: break; 14283 case 'I': 14284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14285 if (C->getZExtValue() <= 31) { 14286 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14287 break; 14288 } 14289 } 14290 return; 14291 case 'J': 14292 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14293 if (C->getZExtValue() <= 63) { 14294 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14295 break; 14296 } 14297 } 14298 return; 14299 case 'K': 14300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14301 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 14302 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14303 break; 14304 } 14305 } 14306 return; 14307 case 'N': 14308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14309 if (C->getZExtValue() <= 255) { 14310 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14311 break; 14312 } 14313 } 14314 return; 14315 case 'e': { 14316 // 32-bit signed value 14317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14318 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14319 C->getSExtValue())) { 14320 // Widen to 64 bits here to get it sign extended. 14321 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 14322 break; 14323 } 14324 // FIXME gcc accepts some relocatable values here too, but only in certain 14325 // memory models; it's complicated. 14326 } 14327 return; 14328 } 14329 case 'Z': { 14330 // 32-bit unsigned value 14331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14332 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14333 C->getZExtValue())) { 14334 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14335 break; 14336 } 14337 } 14338 // FIXME gcc accepts some relocatable values here too, but only in certain 14339 // memory models; it's complicated. 14340 return; 14341 } 14342 case 'i': { 14343 // Literal immediates are always ok. 14344 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 14345 // Widen to 64 bits here to get it sign extended. 14346 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 14347 break; 14348 } 14349 14350 // In any sort of PIC mode addresses need to be computed at runtime by 14351 // adding in a register or some sort of table lookup. These can't 14352 // be used as immediates. 14353 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 14354 return; 14355 14356 // If we are in non-pic codegen mode, we allow the address of a global (with 14357 // an optional displacement) to be used with 'i'. 14358 GlobalAddressSDNode *GA = 0; 14359 int64_t Offset = 0; 14360 14361 // Match either (GA), (GA+C), (GA+C1+C2), etc. 14362 while (1) { 14363 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 14364 Offset += GA->getOffset(); 14365 break; 14366 } else if (Op.getOpcode() == ISD::ADD) { 14367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14368 Offset += C->getZExtValue(); 14369 Op = Op.getOperand(0); 14370 continue; 14371 } 14372 } else if (Op.getOpcode() == ISD::SUB) { 14373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14374 Offset += -C->getZExtValue(); 14375 Op = Op.getOperand(0); 14376 continue; 14377 } 14378 } 14379 14380 // Otherwise, this isn't something we can handle, reject it. 14381 return; 14382 } 14383 14384 const GlobalValue *GV = GA->getGlobal(); 14385 // If we require an extra load to get this address, as in PIC mode, we 14386 // can't accept it. 14387 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 14388 getTargetMachine()))) 14389 return; 14390 14391 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 14392 GA->getValueType(0), Offset); 14393 break; 14394 } 14395 } 14396 14397 if (Result.getNode()) { 14398 Ops.push_back(Result); 14399 return; 14400 } 14401 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 14402} 14403 14404std::pair<unsigned, const TargetRegisterClass*> 14405X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 14406 EVT VT) const { 14407 // First, see if this is a constraint that directly corresponds to an LLVM 14408 // register class. 14409 if (Constraint.size() == 1) { 14410 // GCC Constraint Letters 14411 switch (Constraint[0]) { 14412 default: break; 14413 // TODO: Slight differences here in allocation order and leaving 14414 // RIP in the class. Do they matter any more here than they do 14415 // in the normal allocation? 14416 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 14417 if (Subtarget->is64Bit()) { 14418 if (VT == MVT::i32 || VT == MVT::f32) 14419 return std::make_pair(0U, X86::GR32RegisterClass); 14420 else if (VT == MVT::i16) 14421 return std::make_pair(0U, X86::GR16RegisterClass); 14422 else if (VT == MVT::i8 || VT == MVT::i1) 14423 return std::make_pair(0U, X86::GR8RegisterClass); 14424 else if (VT == MVT::i64 || VT == MVT::f64) 14425 return std::make_pair(0U, X86::GR64RegisterClass); 14426 break; 14427 } 14428 // 32-bit fallthrough 14429 case 'Q': // Q_REGS 14430 if (VT == MVT::i32 || VT == MVT::f32) 14431 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 14432 else if (VT == MVT::i16) 14433 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 14434 else if (VT == MVT::i8 || VT == MVT::i1) 14435 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 14436 else if (VT == MVT::i64) 14437 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 14438 break; 14439 case 'r': // GENERAL_REGS 14440 case 'l': // INDEX_REGS 14441 if (VT == MVT::i8 || VT == MVT::i1) 14442 return std::make_pair(0U, X86::GR8RegisterClass); 14443 if (VT == MVT::i16) 14444 return std::make_pair(0U, X86::GR16RegisterClass); 14445 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 14446 return std::make_pair(0U, X86::GR32RegisterClass); 14447 return std::make_pair(0U, X86::GR64RegisterClass); 14448 case 'R': // LEGACY_REGS 14449 if (VT == MVT::i8 || VT == MVT::i1) 14450 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 14451 if (VT == MVT::i16) 14452 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 14453 if (VT == MVT::i32 || !Subtarget->is64Bit()) 14454 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 14455 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 14456 case 'f': // FP Stack registers. 14457 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 14458 // value to the correct fpstack register class. 14459 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 14460 return std::make_pair(0U, X86::RFP32RegisterClass); 14461 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 14462 return std::make_pair(0U, X86::RFP64RegisterClass); 14463 return std::make_pair(0U, X86::RFP80RegisterClass); 14464 case 'y': // MMX_REGS if MMX allowed. 14465 if (!Subtarget->hasMMX()) break; 14466 return std::make_pair(0U, X86::VR64RegisterClass); 14467 case 'Y': // SSE_REGS if SSE2 allowed 14468 if (!Subtarget->hasXMMInt()) break; 14469 // FALL THROUGH. 14470 case 'x': // SSE_REGS if SSE1 allowed 14471 if (!Subtarget->hasXMM()) break; 14472 14473 switch (VT.getSimpleVT().SimpleTy) { 14474 default: break; 14475 // Scalar SSE types. 14476 case MVT::f32: 14477 case MVT::i32: 14478 return std::make_pair(0U, X86::FR32RegisterClass); 14479 case MVT::f64: 14480 case MVT::i64: 14481 return std::make_pair(0U, X86::FR64RegisterClass); 14482 // Vector types. 14483 case MVT::v16i8: 14484 case MVT::v8i16: 14485 case MVT::v4i32: 14486 case MVT::v2i64: 14487 case MVT::v4f32: 14488 case MVT::v2f64: 14489 return std::make_pair(0U, X86::VR128RegisterClass); 14490 } 14491 break; 14492 } 14493 } 14494 14495 // Use the default implementation in TargetLowering to convert the register 14496 // constraint into a member of a register class. 14497 std::pair<unsigned, const TargetRegisterClass*> Res; 14498 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 14499 14500 // Not found as a standard register? 14501 if (Res.second == 0) { 14502 // Map st(0) -> st(7) -> ST0 14503 if (Constraint.size() == 7 && Constraint[0] == '{' && 14504 tolower(Constraint[1]) == 's' && 14505 tolower(Constraint[2]) == 't' && 14506 Constraint[3] == '(' && 14507 (Constraint[4] >= '0' && Constraint[4] <= '7') && 14508 Constraint[5] == ')' && 14509 Constraint[6] == '}') { 14510 14511 Res.first = X86::ST0+Constraint[4]-'0'; 14512 Res.second = X86::RFP80RegisterClass; 14513 return Res; 14514 } 14515 14516 // GCC allows "st(0)" to be called just plain "st". 14517 if (StringRef("{st}").equals_lower(Constraint)) { 14518 Res.first = X86::ST0; 14519 Res.second = X86::RFP80RegisterClass; 14520 return Res; 14521 } 14522 14523 // flags -> EFLAGS 14524 if (StringRef("{flags}").equals_lower(Constraint)) { 14525 Res.first = X86::EFLAGS; 14526 Res.second = X86::CCRRegisterClass; 14527 return Res; 14528 } 14529 14530 // 'A' means EAX + EDX. 14531 if (Constraint == "A") { 14532 Res.first = X86::EAX; 14533 Res.second = X86::GR32_ADRegisterClass; 14534 return Res; 14535 } 14536 return Res; 14537 } 14538 14539 // Otherwise, check to see if this is a register class of the wrong value 14540 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 14541 // turn into {ax},{dx}. 14542 if (Res.second->hasType(VT)) 14543 return Res; // Correct type already, nothing to do. 14544 14545 // All of the single-register GCC register classes map their values onto 14546 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 14547 // really want an 8-bit or 32-bit register, map to the appropriate register 14548 // class and return the appropriate register. 14549 if (Res.second == X86::GR16RegisterClass) { 14550 if (VT == MVT::i8) { 14551 unsigned DestReg = 0; 14552 switch (Res.first) { 14553 default: break; 14554 case X86::AX: DestReg = X86::AL; break; 14555 case X86::DX: DestReg = X86::DL; break; 14556 case X86::CX: DestReg = X86::CL; break; 14557 case X86::BX: DestReg = X86::BL; break; 14558 } 14559 if (DestReg) { 14560 Res.first = DestReg; 14561 Res.second = X86::GR8RegisterClass; 14562 } 14563 } else if (VT == MVT::i32) { 14564 unsigned DestReg = 0; 14565 switch (Res.first) { 14566 default: break; 14567 case X86::AX: DestReg = X86::EAX; break; 14568 case X86::DX: DestReg = X86::EDX; break; 14569 case X86::CX: DestReg = X86::ECX; break; 14570 case X86::BX: DestReg = X86::EBX; break; 14571 case X86::SI: DestReg = X86::ESI; break; 14572 case X86::DI: DestReg = X86::EDI; break; 14573 case X86::BP: DestReg = X86::EBP; break; 14574 case X86::SP: DestReg = X86::ESP; break; 14575 } 14576 if (DestReg) { 14577 Res.first = DestReg; 14578 Res.second = X86::GR32RegisterClass; 14579 } 14580 } else if (VT == MVT::i64) { 14581 unsigned DestReg = 0; 14582 switch (Res.first) { 14583 default: break; 14584 case X86::AX: DestReg = X86::RAX; break; 14585 case X86::DX: DestReg = X86::RDX; break; 14586 case X86::CX: DestReg = X86::RCX; break; 14587 case X86::BX: DestReg = X86::RBX; break; 14588 case X86::SI: DestReg = X86::RSI; break; 14589 case X86::DI: DestReg = X86::RDI; break; 14590 case X86::BP: DestReg = X86::RBP; break; 14591 case X86::SP: DestReg = X86::RSP; break; 14592 } 14593 if (DestReg) { 14594 Res.first = DestReg; 14595 Res.second = X86::GR64RegisterClass; 14596 } 14597 } 14598 } else if (Res.second == X86::FR32RegisterClass || 14599 Res.second == X86::FR64RegisterClass || 14600 Res.second == X86::VR128RegisterClass) { 14601 // Handle references to XMM physical registers that got mapped into the 14602 // wrong class. This can happen with constraints like {xmm0} where the 14603 // target independent register mapper will just pick the first match it can 14604 // find, ignoring the required type. 14605 if (VT == MVT::f32) 14606 Res.second = X86::FR32RegisterClass; 14607 else if (VT == MVT::f64) 14608 Res.second = X86::FR64RegisterClass; 14609 else if (X86::VR128RegisterClass->hasType(VT)) 14610 Res.second = X86::VR128RegisterClass; 14611 } 14612 14613 return Res; 14614} 14615