X86ISelLowering.cpp revision 96908b17ae7df4c838853a41df9a4c034b435446
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86ShuffleDecode.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/PseudoSourceValue.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VectorExtras.h" 47#include "llvm/Support/CommandLine.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53using namespace llvm; 54using namespace dwarf; 55 56STATISTIC(NumTailCalls, "Number of tail calls"); 57 58static cl::opt<bool> 59DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 60 61// Forward declarations. 62static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 63 SDValue V2); 64 65static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 66 67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 68 69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) { 70 if (is64Bit) return new X8664_MachoTargetObjectFile(); 71 return new TargetLoweringObjectFileMachO(); 72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){ 73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM); 74 return new X8632_ELFTargetObjectFile(TM); 75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) { 76 return new TargetLoweringObjectFileCOFF(); 77 } 78 llvm_unreachable("unknown subtarget type"); 79} 80 81X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 82 : TargetLowering(TM, createTLOF(TM)) { 83 Subtarget = &TM.getSubtarget<X86Subtarget>(); 84 X86ScalarSSEf64 = Subtarget->hasSSE2(); 85 X86ScalarSSEf32 = Subtarget->hasSSE1(); 86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 87 88 RegInfo = TM.getRegisterInfo(); 89 TD = getTargetData(); 90 91 // Set up the TargetLowering object. 92 93 // X86 is weird, it always uses i8 for shift amounts and setcc results. 94 setShiftAmountType(MVT::i8); 95 setBooleanContents(ZeroOrOneBooleanContent); 96 setSchedulingPreference(Sched::RegPressure); 97 setStackPointerRegisterToSaveRestore(X86StackPtr); 98 99 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 100 // Setup Windows compiler runtime calls. 101 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 102 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 103 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 104 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 105 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 106 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 107 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 108 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 109 } 110 111 if (Subtarget->isTargetDarwin()) { 112 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 113 setUseUnderscoreSetJmp(false); 114 setUseUnderscoreLongJmp(false); 115 } else if (Subtarget->isTargetMingw()) { 116 // MS runtime is weird: it exports _setjmp, but longjmp! 117 setUseUnderscoreSetJmp(true); 118 setUseUnderscoreLongJmp(false); 119 } else { 120 setUseUnderscoreSetJmp(true); 121 setUseUnderscoreLongJmp(true); 122 } 123 124 // Set up the register classes. 125 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 126 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 127 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 128 if (Subtarget->is64Bit()) 129 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 130 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 132 133 // We don't accept any truncstore of integer registers. 134 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 135 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 136 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 137 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 139 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 140 141 // SETOEQ and SETUNE require checking two conditions. 142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 148 149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 150 // operation. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 154 155 if (Subtarget->is64Bit()) { 156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 158 } else if (!UseSoftFloat) { 159 // We have an algorithm for SSE2->double, and we turn this into a 160 // 64-bit FILD followed by conditional FADD for other targets. 161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 162 // We have an algorithm for SSE2, and we turn this into a 64-bit 163 // FILD for other targets. 164 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 165 } 166 167 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 168 // this operation. 169 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 170 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 171 172 if (!UseSoftFloat) { 173 // SSE has no i16 to fp conversion, only i32 174 if (X86ScalarSSEf32) { 175 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 176 // f32 and f64 cases are Legal, f80 case is not 177 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 178 } else { 179 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 180 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 181 } 182 } else { 183 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 184 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 185 } 186 187 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 188 // are Legal, f80 is custom lowered. 189 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 190 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 191 192 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 193 // this operation. 194 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 195 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 196 197 if (X86ScalarSSEf32) { 198 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 199 // f32 and f64 cases are Legal, f80 case is not 200 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 201 } else { 202 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 203 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 204 } 205 206 // Handle FP_TO_UINT by promoting the destination to a larger signed 207 // conversion. 208 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 209 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 210 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 211 212 if (Subtarget->is64Bit()) { 213 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 215 } else if (!UseSoftFloat) { 216 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 217 // Expand FP_TO_UINT into a select. 218 // FIXME: We would like to use a Custom expander here eventually to do 219 // the optimal thing for SSE vs. the default expansion in the legalizer. 220 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 221 else 222 // With SSE3 we can use fisttpll to convert to a signed i64; without 223 // SSE, we're stuck with a fistpll. 224 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 225 } 226 227 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 228 if (!X86ScalarSSEf64) { 229 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 230 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 231 if (Subtarget->is64Bit()) { 232 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 233 // Without SSE, i64->f64 goes through memory. 234 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 235 } 236 } 237 238 // Scalar integer divide and remainder are lowered to use operations that 239 // produce two results, to match the available instructions. This exposes 240 // the two-result form to trivial CSE, which is able to combine x/y and x%y 241 // into a single instruction. 242 // 243 // Scalar integer multiply-high is also lowered to use two-result 244 // operations, to match the available instructions. However, plain multiply 245 // (low) operations are left as Legal, as there are single-result 246 // instructions for this in x86. Using the two-result multiply instructions 247 // when both high and low results are needed must be arranged by dagcombine. 248 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 249 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 250 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 251 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 252 setOperationAction(ISD::SREM , MVT::i8 , Expand); 253 setOperationAction(ISD::UREM , MVT::i8 , Expand); 254 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 255 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 256 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 257 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 258 setOperationAction(ISD::SREM , MVT::i16 , Expand); 259 setOperationAction(ISD::UREM , MVT::i16 , Expand); 260 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 261 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 262 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 263 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 264 setOperationAction(ISD::SREM , MVT::i32 , Expand); 265 setOperationAction(ISD::UREM , MVT::i32 , Expand); 266 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 267 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 268 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 269 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 270 setOperationAction(ISD::SREM , MVT::i64 , Expand); 271 setOperationAction(ISD::UREM , MVT::i64 , Expand); 272 273 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 274 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 275 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 276 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 277 if (Subtarget->is64Bit()) 278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 280 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 281 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 282 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 283 setOperationAction(ISD::FREM , MVT::f32 , Expand); 284 setOperationAction(ISD::FREM , MVT::f64 , Expand); 285 setOperationAction(ISD::FREM , MVT::f80 , Expand); 286 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 287 288 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 289 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 290 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 291 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 292 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 293 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 294 if (Subtarget->is64Bit()) { 295 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 296 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 297 } 298 299 if (Subtarget->hasPOPCNT()) { 300 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 301 } else { 302 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 303 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 304 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 305 if (Subtarget->is64Bit()) 306 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 307 } 308 309 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 310 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 311 312 // These should be promoted to a larger select which is supported. 313 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 314 // X86 wants to expand cmov itself. 315 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 316 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 317 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 318 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 319 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 320 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 321 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 322 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 323 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 324 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 325 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 326 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 327 if (Subtarget->is64Bit()) { 328 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 329 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 330 } 331 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 332 333 // Darwin ABI issue. 334 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 335 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 336 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 337 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 338 if (Subtarget->is64Bit()) 339 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 340 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 341 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 342 if (Subtarget->is64Bit()) { 343 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 344 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 345 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 346 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 347 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 348 } 349 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 350 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 351 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 352 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 353 if (Subtarget->is64Bit()) { 354 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 355 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 356 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 357 } 358 359 if (Subtarget->hasSSE1()) 360 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 361 362 // We may not have a libcall for MEMBARRIER so we should lower this. 363 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 364 365 // On X86 and X86-64, atomic operations are lowered to locked instructions. 366 // Locked instructions, in turn, have implicit fence semantics (all memory 367 // operations are flushed before issuing the locked instruction, and they 368 // are not buffered), so we can fold away the common pattern of 369 // fence-atomic-fence. 370 setShouldFoldAtomicFences(true); 371 372 // Expand certain atomics 373 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 374 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 375 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 376 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 377 378 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 381 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 382 383 if (!Subtarget->is64Bit()) { 384 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 385 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 386 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 387 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 388 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 389 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 390 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 391 } 392 393 // FIXME - use subtarget debug flags 394 if (!Subtarget->isTargetDarwin() && 395 !Subtarget->isTargetELF() && 396 !Subtarget->isTargetCygMing()) { 397 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 398 } 399 400 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 401 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 402 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 403 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 404 if (Subtarget->is64Bit()) { 405 setExceptionPointerRegister(X86::RAX); 406 setExceptionSelectorRegister(X86::RDX); 407 } else { 408 setExceptionPointerRegister(X86::EAX); 409 setExceptionSelectorRegister(X86::EDX); 410 } 411 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 412 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 413 414 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 415 416 setOperationAction(ISD::TRAP, MVT::Other, Legal); 417 418 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 419 setOperationAction(ISD::VASTART , MVT::Other, Custom); 420 setOperationAction(ISD::VAEND , MVT::Other, Expand); 421 if (Subtarget->is64Bit()) { 422 setOperationAction(ISD::VAARG , MVT::Other, Custom); 423 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 424 } else { 425 setOperationAction(ISD::VAARG , MVT::Other, Expand); 426 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 427 } 428 429 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 430 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 431 if (Subtarget->is64Bit()) 432 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 433 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) 434 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 435 else 436 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 437 438 if (!UseSoftFloat && X86ScalarSSEf64) { 439 // f32 and f64 use SSE. 440 // Set up the FP register classes. 441 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 442 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 443 444 // Use ANDPD to simulate FABS. 445 setOperationAction(ISD::FABS , MVT::f64, Custom); 446 setOperationAction(ISD::FABS , MVT::f32, Custom); 447 448 // Use XORP to simulate FNEG. 449 setOperationAction(ISD::FNEG , MVT::f64, Custom); 450 setOperationAction(ISD::FNEG , MVT::f32, Custom); 451 452 // Use ANDPD and ORPD to simulate FCOPYSIGN. 453 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 454 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 455 456 // We don't support sin/cos/fmod 457 setOperationAction(ISD::FSIN , MVT::f64, Expand); 458 setOperationAction(ISD::FCOS , MVT::f64, Expand); 459 setOperationAction(ISD::FSIN , MVT::f32, Expand); 460 setOperationAction(ISD::FCOS , MVT::f32, Expand); 461 462 // Expand FP immediates into loads from the stack, except for the special 463 // cases we handle. 464 addLegalFPImmediate(APFloat(+0.0)); // xorpd 465 addLegalFPImmediate(APFloat(+0.0f)); // xorps 466 } else if (!UseSoftFloat && X86ScalarSSEf32) { 467 // Use SSE for f32, x87 for f64. 468 // Set up the FP register classes. 469 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 470 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 471 472 // Use ANDPS to simulate FABS. 473 setOperationAction(ISD::FABS , MVT::f32, Custom); 474 475 // Use XORP to simulate FNEG. 476 setOperationAction(ISD::FNEG , MVT::f32, Custom); 477 478 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 479 480 // Use ANDPS and ORPS to simulate FCOPYSIGN. 481 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 482 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 483 484 // We don't support sin/cos/fmod 485 setOperationAction(ISD::FSIN , MVT::f32, Expand); 486 setOperationAction(ISD::FCOS , MVT::f32, Expand); 487 488 // Special cases we handle for FP constants. 489 addLegalFPImmediate(APFloat(+0.0f)); // xorps 490 addLegalFPImmediate(APFloat(+0.0)); // FLD0 491 addLegalFPImmediate(APFloat(+1.0)); // FLD1 492 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 493 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 494 495 if (!UnsafeFPMath) { 496 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 497 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 498 } 499 } else if (!UseSoftFloat) { 500 // f32 and f64 in x87. 501 // Set up the FP register classes. 502 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 503 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 504 505 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 506 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 507 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 508 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 509 510 if (!UnsafeFPMath) { 511 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 512 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 513 } 514 addLegalFPImmediate(APFloat(+0.0)); // FLD0 515 addLegalFPImmediate(APFloat(+1.0)); // FLD1 516 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 517 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 518 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 519 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 520 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 521 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 522 } 523 524 // Long double always uses X87. 525 if (!UseSoftFloat) { 526 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 527 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 528 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 529 { 530 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 531 addLegalFPImmediate(TmpFlt); // FLD0 532 TmpFlt.changeSign(); 533 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 534 535 bool ignored; 536 APFloat TmpFlt2(+1.0); 537 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 538 &ignored); 539 addLegalFPImmediate(TmpFlt2); // FLD1 540 TmpFlt2.changeSign(); 541 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 542 } 543 544 if (!UnsafeFPMath) { 545 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 546 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 547 } 548 } 549 550 // Always use a library call for pow. 551 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 552 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 553 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 554 555 setOperationAction(ISD::FLOG, MVT::f80, Expand); 556 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 557 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 558 setOperationAction(ISD::FEXP, MVT::f80, Expand); 559 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 560 561 // First set operation action for all vector types to either promote 562 // (for widening) or expand (for scalarization). Then we will selectively 563 // turn on ones that can be effectively codegen'd. 564 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 565 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 566 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 581 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 582 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 607 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 608 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 610 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 611 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 612 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 613 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 614 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 615 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 616 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 617 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 618 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 619 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 620 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 621 setTruncStoreAction((MVT::SimpleValueType)VT, 622 (MVT::SimpleValueType)InnerVT, Expand); 623 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 624 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 625 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 626 } 627 628 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 629 // with -msoft-float, disable use of MMX as well. 630 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 631 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 632 // No operations on x86mmx supported, everything uses intrinsics. 633 } 634 635 // MMX-sized vectors (other than x86mmx) are expected to be expanded 636 // into smaller operations. 637 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 638 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 639 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 640 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 641 setOperationAction(ISD::AND, MVT::v8i8, Expand); 642 setOperationAction(ISD::AND, MVT::v4i16, Expand); 643 setOperationAction(ISD::AND, MVT::v2i32, Expand); 644 setOperationAction(ISD::AND, MVT::v1i64, Expand); 645 setOperationAction(ISD::OR, MVT::v8i8, Expand); 646 setOperationAction(ISD::OR, MVT::v4i16, Expand); 647 setOperationAction(ISD::OR, MVT::v2i32, Expand); 648 setOperationAction(ISD::OR, MVT::v1i64, Expand); 649 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 650 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 651 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 652 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 653 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 654 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 655 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 656 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 658 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 659 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 660 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 661 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 662 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 663 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 664 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 665 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 666 667 if (!UseSoftFloat && Subtarget->hasSSE1()) { 668 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 669 670 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 671 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 672 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 673 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 674 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 675 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 676 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 678 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 679 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 680 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 681 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 682 } 683 684 if (!UseSoftFloat && Subtarget->hasSSE2()) { 685 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 686 687 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 688 // registers cannot be used even for integer operations. 689 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 690 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 691 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 692 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 693 694 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 695 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 696 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 697 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 698 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 699 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 700 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 701 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 702 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 703 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 704 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 705 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 706 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 707 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 708 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 709 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 710 711 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 712 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 713 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 714 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 715 716 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 717 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 718 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 719 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 720 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 721 722 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 723 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 724 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 725 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 726 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 727 728 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 729 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 730 EVT VT = (MVT::SimpleValueType)i; 731 // Do not attempt to custom lower non-power-of-2 vectors 732 if (!isPowerOf2_32(VT.getVectorNumElements())) 733 continue; 734 // Do not attempt to custom lower non-128-bit vectors 735 if (!VT.is128BitVector()) 736 continue; 737 setOperationAction(ISD::BUILD_VECTOR, 738 VT.getSimpleVT().SimpleTy, Custom); 739 setOperationAction(ISD::VECTOR_SHUFFLE, 740 VT.getSimpleVT().SimpleTy, Custom); 741 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 742 VT.getSimpleVT().SimpleTy, Custom); 743 } 744 745 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 746 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 747 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 748 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 749 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 750 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 751 752 if (Subtarget->is64Bit()) { 753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 754 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 755 } 756 757 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 758 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 759 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 760 EVT VT = SVT; 761 762 // Do not attempt to promote non-128-bit vectors 763 if (!VT.is128BitVector()) 764 continue; 765 766 setOperationAction(ISD::AND, SVT, Promote); 767 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 768 setOperationAction(ISD::OR, SVT, Promote); 769 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 770 setOperationAction(ISD::XOR, SVT, Promote); 771 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 772 setOperationAction(ISD::LOAD, SVT, Promote); 773 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 774 setOperationAction(ISD::SELECT, SVT, Promote); 775 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 776 } 777 778 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 779 780 // Custom lower v2i64 and v2f64 selects. 781 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 782 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 783 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 784 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 785 786 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 787 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 788 } 789 790 if (Subtarget->hasSSE41()) { 791 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 792 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 793 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 794 setOperationAction(ISD::FRINT, MVT::f32, Legal); 795 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 796 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 797 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 798 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 799 setOperationAction(ISD::FRINT, MVT::f64, Legal); 800 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 801 802 // FIXME: Do we need to handle scalar-to-vector here? 803 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 804 805 // Can turn SHL into an integer multiply. 806 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 807 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 808 809 // i8 and i16 vectors are custom , because the source register and source 810 // source memory operand types are not the same width. f32 vectors are 811 // custom since the immediate controlling the insert encodes additional 812 // information. 813 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 817 818 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 819 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 822 823 if (Subtarget->is64Bit()) { 824 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 826 } 827 } 828 829 if (Subtarget->hasSSE42()) { 830 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 831 } 832 833 if (!UseSoftFloat && Subtarget->hasAVX()) { 834 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 835 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 836 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 837 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 838 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 839 840 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 841 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 842 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 843 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 844 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 845 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 846 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 847 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 848 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 849 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 850 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 851 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 852 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 853 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 854 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 855 856 // Operations to consider commented out -v16i16 v32i8 857 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 858 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 859 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 860 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 861 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 862 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 863 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 864 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 865 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 866 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 867 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 868 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 869 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 870 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 871 872 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 873 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 874 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 875 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 876 877 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 878 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 879 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 882 883 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 884 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 887 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 889 890#if 0 891 // Not sure we want to do this since there are no 256-bit integer 892 // operations in AVX 893 894 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 895 // This includes 256-bit vectors 896 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 897 EVT VT = (MVT::SimpleValueType)i; 898 899 // Do not attempt to custom lower non-power-of-2 vectors 900 if (!isPowerOf2_32(VT.getVectorNumElements())) 901 continue; 902 903 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 904 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 906 } 907 908 if (Subtarget->is64Bit()) { 909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 910 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 911 } 912#endif 913 914#if 0 915 // Not sure we want to do this since there are no 256-bit integer 916 // operations in AVX 917 918 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 919 // Including 256-bit vectors 920 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 921 EVT VT = (MVT::SimpleValueType)i; 922 923 if (!VT.is256BitVector()) { 924 continue; 925 } 926 setOperationAction(ISD::AND, VT, Promote); 927 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 928 setOperationAction(ISD::OR, VT, Promote); 929 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 930 setOperationAction(ISD::XOR, VT, Promote); 931 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 932 setOperationAction(ISD::LOAD, VT, Promote); 933 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 934 setOperationAction(ISD::SELECT, VT, Promote); 935 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 936 } 937 938 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 939#endif 940 } 941 942 // We want to custom lower some of our intrinsics. 943 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 944 945 // Add/Sub/Mul with overflow operations are custom lowered. 946 setOperationAction(ISD::SADDO, MVT::i32, Custom); 947 setOperationAction(ISD::UADDO, MVT::i32, Custom); 948 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 949 setOperationAction(ISD::USUBO, MVT::i32, Custom); 950 setOperationAction(ISD::SMULO, MVT::i32, Custom); 951 952 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 953 // handle type legalization for these operations here. 954 // 955 // FIXME: We really should do custom legalization for addition and 956 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 957 // than generic legalization for 64-bit multiplication-with-overflow, though. 958 if (Subtarget->is64Bit()) { 959 setOperationAction(ISD::SADDO, MVT::i64, Custom); 960 setOperationAction(ISD::UADDO, MVT::i64, Custom); 961 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 962 setOperationAction(ISD::USUBO, MVT::i64, Custom); 963 setOperationAction(ISD::SMULO, MVT::i64, Custom); 964 } 965 966 if (!Subtarget->is64Bit()) { 967 // These libcalls are not available in 32-bit. 968 setLibcallName(RTLIB::SHL_I128, 0); 969 setLibcallName(RTLIB::SRL_I128, 0); 970 setLibcallName(RTLIB::SRA_I128, 0); 971 } 972 973 // We have target-specific dag combine patterns for the following nodes: 974 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 975 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 976 setTargetDAGCombine(ISD::BUILD_VECTOR); 977 setTargetDAGCombine(ISD::SELECT); 978 setTargetDAGCombine(ISD::SHL); 979 setTargetDAGCombine(ISD::SRA); 980 setTargetDAGCombine(ISD::SRL); 981 setTargetDAGCombine(ISD::OR); 982 setTargetDAGCombine(ISD::STORE); 983 setTargetDAGCombine(ISD::ZERO_EXTEND); 984 if (Subtarget->is64Bit()) 985 setTargetDAGCombine(ISD::MUL); 986 987 computeRegisterProperties(); 988 989 // FIXME: These should be based on subtarget info. Plus, the values should 990 // be smaller when we are in optimizing for size mode. 991 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 992 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 993 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 994 setPrefLoopAlignment(16); 995 benefitFromCodePlacementOpt = true; 996} 997 998 999MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1000 return MVT::i8; 1001} 1002 1003 1004/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1005/// the desired ByVal argument alignment. 1006static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1007 if (MaxAlign == 16) 1008 return; 1009 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1010 if (VTy->getBitWidth() == 128) 1011 MaxAlign = 16; 1012 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1013 unsigned EltAlign = 0; 1014 getMaxByValAlign(ATy->getElementType(), EltAlign); 1015 if (EltAlign > MaxAlign) 1016 MaxAlign = EltAlign; 1017 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1018 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1019 unsigned EltAlign = 0; 1020 getMaxByValAlign(STy->getElementType(i), EltAlign); 1021 if (EltAlign > MaxAlign) 1022 MaxAlign = EltAlign; 1023 if (MaxAlign == 16) 1024 break; 1025 } 1026 } 1027 return; 1028} 1029 1030/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1031/// function arguments in the caller parameter area. For X86, aggregates 1032/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1033/// are at 4-byte boundaries. 1034unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1035 if (Subtarget->is64Bit()) { 1036 // Max of 8 and alignment of type. 1037 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1038 if (TyAlign > 8) 1039 return TyAlign; 1040 return 8; 1041 } 1042 1043 unsigned Align = 4; 1044 if (Subtarget->hasSSE1()) 1045 getMaxByValAlign(Ty, Align); 1046 return Align; 1047} 1048 1049/// getOptimalMemOpType - Returns the target specific optimal type for load 1050/// and store operations as a result of memset, memcpy, and memmove 1051/// lowering. If DstAlign is zero that means it's safe to destination 1052/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1053/// means there isn't a need to check it against alignment requirement, 1054/// probably because the source does not need to be loaded. If 1055/// 'NonScalarIntSafe' is true, that means it's safe to return a 1056/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1057/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1058/// constant so it does not need to be loaded. 1059/// It returns EVT::Other if the type should be determined using generic 1060/// target-independent logic. 1061EVT 1062X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1063 unsigned DstAlign, unsigned SrcAlign, 1064 bool NonScalarIntSafe, 1065 bool MemcpyStrSrc, 1066 MachineFunction &MF) const { 1067 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1068 // linux. This is because the stack realignment code can't handle certain 1069 // cases like PR2962. This should be removed when PR2962 is fixed. 1070 const Function *F = MF.getFunction(); 1071 if (NonScalarIntSafe && 1072 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1073 if (Size >= 16 && 1074 (Subtarget->isUnalignedMemAccessFast() || 1075 ((DstAlign == 0 || DstAlign >= 16) && 1076 (SrcAlign == 0 || SrcAlign >= 16))) && 1077 Subtarget->getStackAlignment() >= 16) { 1078 if (Subtarget->hasSSE2()) 1079 return MVT::v4i32; 1080 if (Subtarget->hasSSE1()) 1081 return MVT::v4f32; 1082 } else if (!MemcpyStrSrc && Size >= 8 && 1083 !Subtarget->is64Bit() && 1084 Subtarget->getStackAlignment() >= 8 && 1085 Subtarget->hasSSE2()) { 1086 // Do not use f64 to lower memcpy if source is string constant. It's 1087 // better to use i32 to avoid the loads. 1088 return MVT::f64; 1089 } 1090 } 1091 if (Subtarget->is64Bit() && Size >= 8) 1092 return MVT::i64; 1093 return MVT::i32; 1094} 1095 1096/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1097/// current function. The returned value is a member of the 1098/// MachineJumpTableInfo::JTEntryKind enum. 1099unsigned X86TargetLowering::getJumpTableEncoding() const { 1100 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1101 // symbol. 1102 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1103 Subtarget->isPICStyleGOT()) 1104 return MachineJumpTableInfo::EK_Custom32; 1105 1106 // Otherwise, use the normal jump table encoding heuristics. 1107 return TargetLowering::getJumpTableEncoding(); 1108} 1109 1110const MCExpr * 1111X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1112 const MachineBasicBlock *MBB, 1113 unsigned uid,MCContext &Ctx) const{ 1114 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1115 Subtarget->isPICStyleGOT()); 1116 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1117 // entries. 1118 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1119 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1120} 1121 1122/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1123/// jumptable. 1124SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1125 SelectionDAG &DAG) const { 1126 if (!Subtarget->is64Bit()) 1127 // This doesn't have DebugLoc associated with it, but is not really the 1128 // same as a Register. 1129 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1130 return Table; 1131} 1132 1133/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1134/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1135/// MCExpr. 1136const MCExpr *X86TargetLowering:: 1137getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1138 MCContext &Ctx) const { 1139 // X86-64 uses RIP relative addressing based on the jump table label. 1140 if (Subtarget->isPICStyleRIPRel()) 1141 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1142 1143 // Otherwise, the reference is relative to the PIC base. 1144 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1145} 1146 1147/// getFunctionAlignment - Return the Log2 alignment of this function. 1148unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1149 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1150} 1151 1152std::pair<const TargetRegisterClass*, uint8_t> 1153X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1154 const TargetRegisterClass *RRC = 0; 1155 uint8_t Cost = 1; 1156 switch (VT.getSimpleVT().SimpleTy) { 1157 default: 1158 return TargetLowering::findRepresentativeClass(VT); 1159 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1160 RRC = (Subtarget->is64Bit() 1161 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1162 break; 1163 case MVT::x86mmx: 1164 RRC = X86::VR64RegisterClass; 1165 break; 1166 case MVT::f32: case MVT::f64: 1167 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1168 case MVT::v4f32: case MVT::v2f64: 1169 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1170 case MVT::v4f64: 1171 RRC = X86::VR128RegisterClass; 1172 break; 1173 } 1174 return std::make_pair(RRC, Cost); 1175} 1176 1177unsigned 1178X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, 1179 MachineFunction &MF) const { 1180 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 1181 1182 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; 1183 switch (RC->getID()) { 1184 default: 1185 return 0; 1186 case X86::GR32RegClassID: 1187 return 4 - FPDiff; 1188 case X86::GR64RegClassID: 1189 return 8 - FPDiff; 1190 case X86::VR128RegClassID: 1191 return Subtarget->is64Bit() ? 10 : 4; 1192 case X86::VR64RegClassID: 1193 return 4; 1194 } 1195} 1196 1197bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1198 unsigned &Offset) const { 1199 if (!Subtarget->isTargetLinux()) 1200 return false; 1201 1202 if (Subtarget->is64Bit()) { 1203 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1204 Offset = 0x28; 1205 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1206 AddressSpace = 256; 1207 else 1208 AddressSpace = 257; 1209 } else { 1210 // %gs:0x14 on i386 1211 Offset = 0x14; 1212 AddressSpace = 256; 1213 } 1214 return true; 1215} 1216 1217 1218//===----------------------------------------------------------------------===// 1219// Return Value Calling Convention Implementation 1220//===----------------------------------------------------------------------===// 1221 1222#include "X86GenCallingConv.inc" 1223 1224bool 1225X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1226 const SmallVectorImpl<ISD::OutputArg> &Outs, 1227 LLVMContext &Context) const { 1228 SmallVector<CCValAssign, 16> RVLocs; 1229 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1230 RVLocs, Context); 1231 return CCInfo.CheckReturn(Outs, RetCC_X86); 1232} 1233 1234SDValue 1235X86TargetLowering::LowerReturn(SDValue Chain, 1236 CallingConv::ID CallConv, bool isVarArg, 1237 const SmallVectorImpl<ISD::OutputArg> &Outs, 1238 const SmallVectorImpl<SDValue> &OutVals, 1239 DebugLoc dl, SelectionDAG &DAG) const { 1240 MachineFunction &MF = DAG.getMachineFunction(); 1241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1242 1243 SmallVector<CCValAssign, 16> RVLocs; 1244 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1245 RVLocs, *DAG.getContext()); 1246 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1247 1248 // Add the regs to the liveout set for the function. 1249 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1250 for (unsigned i = 0; i != RVLocs.size(); ++i) 1251 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1252 MRI.addLiveOut(RVLocs[i].getLocReg()); 1253 1254 SDValue Flag; 1255 1256 SmallVector<SDValue, 6> RetOps; 1257 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1258 // Operand #1 = Bytes To Pop 1259 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1260 MVT::i16)); 1261 1262 // Copy the result values into the output registers. 1263 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1264 CCValAssign &VA = RVLocs[i]; 1265 assert(VA.isRegLoc() && "Can only return in registers!"); 1266 SDValue ValToCopy = OutVals[i]; 1267 EVT ValVT = ValToCopy.getValueType(); 1268 1269 // If this is x86-64, and we disabled SSE, we can't return FP values, 1270 // or SSE or MMX vectors. 1271 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1272 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1273 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1274 report_fatal_error("SSE register return with SSE disabled"); 1275 } 1276 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1277 // llvm-gcc has never done it right and no one has noticed, so this 1278 // should be OK for now. 1279 if (ValVT == MVT::f64 && 1280 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1281 report_fatal_error("SSE2 register return with SSE2 disabled"); 1282 1283 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1284 // the RET instruction and handled by the FP Stackifier. 1285 if (VA.getLocReg() == X86::ST0 || 1286 VA.getLocReg() == X86::ST1) { 1287 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1288 // change the value to the FP stack register class. 1289 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1290 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1291 RetOps.push_back(ValToCopy); 1292 // Don't emit a copytoreg. 1293 continue; 1294 } 1295 1296 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1297 // which is returned in RAX / RDX. 1298 if (Subtarget->is64Bit()) { 1299 if (ValVT == MVT::x86mmx) { 1300 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1301 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1302 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1303 ValToCopy); 1304 // If we don't have SSE2 available, convert to v4f32 so the generated 1305 // register is legal. 1306 if (!Subtarget->hasSSE2()) 1307 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1308 } 1309 } 1310 } 1311 1312 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1313 Flag = Chain.getValue(1); 1314 } 1315 1316 // The x86-64 ABI for returning structs by value requires that we copy 1317 // the sret argument into %rax for the return. We saved the argument into 1318 // a virtual register in the entry block, so now we copy the value out 1319 // and into %rax. 1320 if (Subtarget->is64Bit() && 1321 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1322 MachineFunction &MF = DAG.getMachineFunction(); 1323 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1324 unsigned Reg = FuncInfo->getSRetReturnReg(); 1325 assert(Reg && 1326 "SRetReturnReg should have been set in LowerFormalArguments()."); 1327 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1328 1329 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1330 Flag = Chain.getValue(1); 1331 1332 // RAX now acts like a return value. 1333 MRI.addLiveOut(X86::RAX); 1334 } 1335 1336 RetOps[0] = Chain; // Update chain. 1337 1338 // Add the flag if we have it. 1339 if (Flag.getNode()) 1340 RetOps.push_back(Flag); 1341 1342 return DAG.getNode(X86ISD::RET_FLAG, dl, 1343 MVT::Other, &RetOps[0], RetOps.size()); 1344} 1345 1346bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1347 if (N->getNumValues() != 1) 1348 return false; 1349 if (!N->hasNUsesOfValue(1, 0)) 1350 return false; 1351 1352 SDNode *Copy = *N->use_begin(); 1353 if (Copy->getOpcode() != ISD::CopyToReg && 1354 Copy->getOpcode() != ISD::FP_EXTEND) 1355 return false; 1356 1357 bool HasRet = false; 1358 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1359 UI != UE; ++UI) { 1360 if (UI->getOpcode() != X86ISD::RET_FLAG) 1361 return false; 1362 HasRet = true; 1363 } 1364 1365 return HasRet; 1366} 1367 1368/// LowerCallResult - Lower the result values of a call into the 1369/// appropriate copies out of appropriate physical registers. 1370/// 1371SDValue 1372X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1373 CallingConv::ID CallConv, bool isVarArg, 1374 const SmallVectorImpl<ISD::InputArg> &Ins, 1375 DebugLoc dl, SelectionDAG &DAG, 1376 SmallVectorImpl<SDValue> &InVals) const { 1377 1378 // Assign locations to each value returned by this call. 1379 SmallVector<CCValAssign, 16> RVLocs; 1380 bool Is64Bit = Subtarget->is64Bit(); 1381 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1382 RVLocs, *DAG.getContext()); 1383 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1384 1385 // Copy all of the result registers out of their specified physreg. 1386 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1387 CCValAssign &VA = RVLocs[i]; 1388 EVT CopyVT = VA.getValVT(); 1389 1390 // If this is x86-64, and we disabled SSE, we can't return FP values 1391 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1392 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1393 report_fatal_error("SSE register return with SSE disabled"); 1394 } 1395 1396 SDValue Val; 1397 1398 // If this is a call to a function that returns an fp value on the floating 1399 // point stack, we must guarantee the the value is popped from the stack, so 1400 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1401 // if the return value is not used. We use the FpGET_ST0 instructions 1402 // instead. 1403 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1404 // If we prefer to use the value in xmm registers, copy it out as f80 and 1405 // use a truncate to move it from fp stack reg to xmm reg. 1406 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1407 bool isST0 = VA.getLocReg() == X86::ST0; 1408 unsigned Opc = 0; 1409 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; 1410 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; 1411 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; 1412 SDValue Ops[] = { Chain, InFlag }; 1413 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag, 1414 Ops, 2), 1); 1415 Val = Chain.getValue(0); 1416 1417 // Round the f80 to the right size, which also moves it to the appropriate 1418 // xmm register. 1419 if (CopyVT != VA.getValVT()) 1420 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1421 // This truncation won't change the value. 1422 DAG.getIntPtrConstant(1)); 1423 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1424 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1425 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1426 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1427 MVT::v2i64, InFlag).getValue(1); 1428 Val = Chain.getValue(0); 1429 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1430 Val, DAG.getConstant(0, MVT::i64)); 1431 } else { 1432 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1433 MVT::i64, InFlag).getValue(1); 1434 Val = Chain.getValue(0); 1435 } 1436 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val); 1437 } else { 1438 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1439 CopyVT, InFlag).getValue(1); 1440 Val = Chain.getValue(0); 1441 } 1442 InFlag = Chain.getValue(2); 1443 InVals.push_back(Val); 1444 } 1445 1446 return Chain; 1447} 1448 1449 1450//===----------------------------------------------------------------------===// 1451// C & StdCall & Fast Calling Convention implementation 1452//===----------------------------------------------------------------------===// 1453// StdCall calling convention seems to be standard for many Windows' API 1454// routines and around. It differs from C calling convention just a little: 1455// callee should clean up the stack, not caller. Symbols should be also 1456// decorated in some fancy way :) It doesn't support any vector arguments. 1457// For info on fast calling convention see Fast Calling Convention (tail call) 1458// implementation LowerX86_32FastCCCallTo. 1459 1460/// CallIsStructReturn - Determines whether a call uses struct return 1461/// semantics. 1462static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1463 if (Outs.empty()) 1464 return false; 1465 1466 return Outs[0].Flags.isSRet(); 1467} 1468 1469/// ArgsAreStructReturn - Determines whether a function uses struct 1470/// return semantics. 1471static bool 1472ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1473 if (Ins.empty()) 1474 return false; 1475 1476 return Ins[0].Flags.isSRet(); 1477} 1478 1479/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1480/// by "Src" to address "Dst" with size and alignment information specified by 1481/// the specific parameter attribute. The copy will be passed as a byval 1482/// function parameter. 1483static SDValue 1484CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1485 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1486 DebugLoc dl) { 1487 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1488 1489 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1490 /*isVolatile*/false, /*AlwaysInline=*/true, 1491 MachinePointerInfo(), MachinePointerInfo()); 1492} 1493 1494/// IsTailCallConvention - Return true if the calling convention is one that 1495/// supports tail call optimization. 1496static bool IsTailCallConvention(CallingConv::ID CC) { 1497 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1498} 1499 1500/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1501/// a tailcall target by changing its ABI. 1502static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1503 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1504} 1505 1506SDValue 1507X86TargetLowering::LowerMemArgument(SDValue Chain, 1508 CallingConv::ID CallConv, 1509 const SmallVectorImpl<ISD::InputArg> &Ins, 1510 DebugLoc dl, SelectionDAG &DAG, 1511 const CCValAssign &VA, 1512 MachineFrameInfo *MFI, 1513 unsigned i) const { 1514 // Create the nodes corresponding to a load from this parameter slot. 1515 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1516 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1517 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1518 EVT ValVT; 1519 1520 // If value is passed by pointer we have address passed instead of the value 1521 // itself. 1522 if (VA.getLocInfo() == CCValAssign::Indirect) 1523 ValVT = VA.getLocVT(); 1524 else 1525 ValVT = VA.getValVT(); 1526 1527 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1528 // changed with more analysis. 1529 // In case of tail call optimization mark all arguments mutable. Since they 1530 // could be overwritten by lowering of arguments in case of a tail call. 1531 if (Flags.isByVal()) { 1532 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1533 VA.getLocMemOffset(), isImmutable); 1534 return DAG.getFrameIndex(FI, getPointerTy()); 1535 } else { 1536 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1537 VA.getLocMemOffset(), isImmutable); 1538 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1539 return DAG.getLoad(ValVT, dl, Chain, FIN, 1540 MachinePointerInfo::getFixedStack(FI), 1541 false, false, 0); 1542 } 1543} 1544 1545SDValue 1546X86TargetLowering::LowerFormalArguments(SDValue Chain, 1547 CallingConv::ID CallConv, 1548 bool isVarArg, 1549 const SmallVectorImpl<ISD::InputArg> &Ins, 1550 DebugLoc dl, 1551 SelectionDAG &DAG, 1552 SmallVectorImpl<SDValue> &InVals) 1553 const { 1554 MachineFunction &MF = DAG.getMachineFunction(); 1555 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1556 1557 const Function* Fn = MF.getFunction(); 1558 if (Fn->hasExternalLinkage() && 1559 Subtarget->isTargetCygMing() && 1560 Fn->getName() == "main") 1561 FuncInfo->setForceFramePointer(true); 1562 1563 MachineFrameInfo *MFI = MF.getFrameInfo(); 1564 bool Is64Bit = Subtarget->is64Bit(); 1565 bool IsWin64 = Subtarget->isTargetWin64(); 1566 1567 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1568 "Var args not supported with calling convention fastcc or ghc"); 1569 1570 // Assign locations to all of the incoming arguments. 1571 SmallVector<CCValAssign, 16> ArgLocs; 1572 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1573 ArgLocs, *DAG.getContext()); 1574 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1575 1576 unsigned LastVal = ~0U; 1577 SDValue ArgValue; 1578 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1579 CCValAssign &VA = ArgLocs[i]; 1580 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1581 // places. 1582 assert(VA.getValNo() != LastVal && 1583 "Don't support value assigned to multiple locs yet"); 1584 LastVal = VA.getValNo(); 1585 1586 if (VA.isRegLoc()) { 1587 EVT RegVT = VA.getLocVT(); 1588 TargetRegisterClass *RC = NULL; 1589 if (RegVT == MVT::i32) 1590 RC = X86::GR32RegisterClass; 1591 else if (Is64Bit && RegVT == MVT::i64) 1592 RC = X86::GR64RegisterClass; 1593 else if (RegVT == MVT::f32) 1594 RC = X86::FR32RegisterClass; 1595 else if (RegVT == MVT::f64) 1596 RC = X86::FR64RegisterClass; 1597 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1598 RC = X86::VR256RegisterClass; 1599 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1600 RC = X86::VR128RegisterClass; 1601 else if (RegVT == MVT::x86mmx) 1602 RC = X86::VR64RegisterClass; 1603 else 1604 llvm_unreachable("Unknown argument type!"); 1605 1606 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1607 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1608 1609 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1610 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1611 // right size. 1612 if (VA.getLocInfo() == CCValAssign::SExt) 1613 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1614 DAG.getValueType(VA.getValVT())); 1615 else if (VA.getLocInfo() == CCValAssign::ZExt) 1616 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1617 DAG.getValueType(VA.getValVT())); 1618 else if (VA.getLocInfo() == CCValAssign::BCvt) 1619 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1620 1621 if (VA.isExtInLoc()) { 1622 // Handle MMX values passed in XMM regs. 1623 if (RegVT.isVector()) { 1624 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1625 ArgValue); 1626 } else 1627 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1628 } 1629 } else { 1630 assert(VA.isMemLoc()); 1631 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1632 } 1633 1634 // If value is passed via pointer - do a load. 1635 if (VA.getLocInfo() == CCValAssign::Indirect) 1636 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1637 MachinePointerInfo(), false, false, 0); 1638 1639 InVals.push_back(ArgValue); 1640 } 1641 1642 // The x86-64 ABI for returning structs by value requires that we copy 1643 // the sret argument into %rax for the return. Save the argument into 1644 // a virtual register so that we can access it from the return points. 1645 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1646 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1647 unsigned Reg = FuncInfo->getSRetReturnReg(); 1648 if (!Reg) { 1649 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1650 FuncInfo->setSRetReturnReg(Reg); 1651 } 1652 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1653 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1654 } 1655 1656 unsigned StackSize = CCInfo.getNextStackOffset(); 1657 // Align stack specially for tail calls. 1658 if (FuncIsMadeTailCallSafe(CallConv)) 1659 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1660 1661 // If the function takes variable number of arguments, make a frame index for 1662 // the start of the first vararg value... for expansion of llvm.va_start. 1663 if (isVarArg) { 1664 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1665 CallConv != CallingConv::X86_ThisCall))) { 1666 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1667 } 1668 if (Is64Bit) { 1669 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1670 1671 // FIXME: We should really autogenerate these arrays 1672 static const unsigned GPR64ArgRegsWin64[] = { 1673 X86::RCX, X86::RDX, X86::R8, X86::R9 1674 }; 1675 static const unsigned GPR64ArgRegs64Bit[] = { 1676 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1677 }; 1678 static const unsigned XMMArgRegs64Bit[] = { 1679 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1680 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1681 }; 1682 const unsigned *GPR64ArgRegs; 1683 unsigned NumXMMRegs = 0; 1684 1685 if (IsWin64) { 1686 // The XMM registers which might contain var arg parameters are shadowed 1687 // in their paired GPR. So we only need to save the GPR to their home 1688 // slots. 1689 TotalNumIntRegs = 4; 1690 GPR64ArgRegs = GPR64ArgRegsWin64; 1691 } else { 1692 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1693 GPR64ArgRegs = GPR64ArgRegs64Bit; 1694 1695 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1696 } 1697 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1698 TotalNumIntRegs); 1699 1700 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1701 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1702 "SSE register cannot be used when SSE is disabled!"); 1703 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1704 "SSE register cannot be used when SSE is disabled!"); 1705 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1706 // Kernel mode asks for SSE to be disabled, so don't push them 1707 // on the stack. 1708 TotalNumXMMRegs = 0; 1709 1710 if (IsWin64) { 1711 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo(); 1712 // Get to the caller-allocated home save location. Add 8 to account 1713 // for the return address. 1714 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1715 FuncInfo->setRegSaveFrameIndex( 1716 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1717 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1718 } else { 1719 // For X86-64, if there are vararg parameters that are passed via 1720 // registers, then we must store them to their spots on the stack so they 1721 // may be loaded by deferencing the result of va_next. 1722 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1723 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1724 FuncInfo->setRegSaveFrameIndex( 1725 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1726 false)); 1727 } 1728 1729 // Store the integer parameter registers. 1730 SmallVector<SDValue, 8> MemOps; 1731 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1732 getPointerTy()); 1733 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1734 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1735 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1736 DAG.getIntPtrConstant(Offset)); 1737 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1738 X86::GR64RegisterClass); 1739 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1740 SDValue Store = 1741 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1742 MachinePointerInfo::getFixedStack( 1743 FuncInfo->getRegSaveFrameIndex(), Offset), 1744 false, false, 0); 1745 MemOps.push_back(Store); 1746 Offset += 8; 1747 } 1748 1749 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1750 // Now store the XMM (fp + vector) parameter registers. 1751 SmallVector<SDValue, 11> SaveXMMOps; 1752 SaveXMMOps.push_back(Chain); 1753 1754 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1755 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1756 SaveXMMOps.push_back(ALVal); 1757 1758 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1759 FuncInfo->getRegSaveFrameIndex())); 1760 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1761 FuncInfo->getVarArgsFPOffset())); 1762 1763 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1764 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1765 X86::VR128RegisterClass); 1766 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1767 SaveXMMOps.push_back(Val); 1768 } 1769 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1770 MVT::Other, 1771 &SaveXMMOps[0], SaveXMMOps.size())); 1772 } 1773 1774 if (!MemOps.empty()) 1775 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1776 &MemOps[0], MemOps.size()); 1777 } 1778 } 1779 1780 // Some CCs need callee pop. 1781 if (Subtarget->IsCalleePop(isVarArg, CallConv)) { 1782 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1783 } else { 1784 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1785 // If this is an sret function, the return should pop the hidden pointer. 1786 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1787 FuncInfo->setBytesToPopOnReturn(4); 1788 } 1789 1790 if (!Is64Bit) { 1791 // RegSaveFrameIndex is X86-64 only. 1792 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1793 if (CallConv == CallingConv::X86_FastCall || 1794 CallConv == CallingConv::X86_ThisCall) 1795 // fastcc functions can't have varargs. 1796 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1797 } 1798 1799 return Chain; 1800} 1801 1802SDValue 1803X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1804 SDValue StackPtr, SDValue Arg, 1805 DebugLoc dl, SelectionDAG &DAG, 1806 const CCValAssign &VA, 1807 ISD::ArgFlagsTy Flags) const { 1808 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1809 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1810 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1811 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1812 if (Flags.isByVal()) 1813 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1814 1815 return DAG.getStore(Chain, dl, Arg, PtrOff, 1816 MachinePointerInfo::getStack(LocMemOffset), 1817 false, false, 0); 1818} 1819 1820/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1821/// optimization is performed and it is required. 1822SDValue 1823X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1824 SDValue &OutRetAddr, SDValue Chain, 1825 bool IsTailCall, bool Is64Bit, 1826 int FPDiff, DebugLoc dl) const { 1827 // Adjust the Return address stack slot. 1828 EVT VT = getPointerTy(); 1829 OutRetAddr = getReturnAddressFrameIndex(DAG); 1830 1831 // Load the "old" Return address. 1832 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1833 false, false, 0); 1834 return SDValue(OutRetAddr.getNode(), 1); 1835} 1836 1837/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1838/// optimization is performed and it is required (FPDiff!=0). 1839static SDValue 1840EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1841 SDValue Chain, SDValue RetAddrFrIdx, 1842 bool Is64Bit, int FPDiff, DebugLoc dl) { 1843 // Store the return address to the appropriate stack slot. 1844 if (!FPDiff) return Chain; 1845 // Calculate the new stack slot for the return address. 1846 int SlotSize = Is64Bit ? 8 : 4; 1847 int NewReturnAddrFI = 1848 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1849 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1850 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1851 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1852 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 1853 false, false, 0); 1854 return Chain; 1855} 1856 1857SDValue 1858X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1859 CallingConv::ID CallConv, bool isVarArg, 1860 bool &isTailCall, 1861 const SmallVectorImpl<ISD::OutputArg> &Outs, 1862 const SmallVectorImpl<SDValue> &OutVals, 1863 const SmallVectorImpl<ISD::InputArg> &Ins, 1864 DebugLoc dl, SelectionDAG &DAG, 1865 SmallVectorImpl<SDValue> &InVals) const { 1866 MachineFunction &MF = DAG.getMachineFunction(); 1867 bool Is64Bit = Subtarget->is64Bit(); 1868 bool IsStructRet = CallIsStructReturn(Outs); 1869 bool IsSibcall = false; 1870 1871 if (isTailCall) { 1872 // Check if it's really possible to do a tail call. 1873 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1874 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1875 Outs, OutVals, Ins, DAG); 1876 1877 // Sibcalls are automatically detected tailcalls which do not require 1878 // ABI changes. 1879 if (!GuaranteedTailCallOpt && isTailCall) 1880 IsSibcall = true; 1881 1882 if (isTailCall) 1883 ++NumTailCalls; 1884 } 1885 1886 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1887 "Var args not supported with calling convention fastcc or ghc"); 1888 1889 // Analyze operands of the call, assigning locations to each operand. 1890 SmallVector<CCValAssign, 16> ArgLocs; 1891 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1892 ArgLocs, *DAG.getContext()); 1893 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 1894 1895 // Get a count of how many bytes are to be pushed on the stack. 1896 unsigned NumBytes = CCInfo.getNextStackOffset(); 1897 if (IsSibcall) 1898 // This is a sibcall. The memory operands are available in caller's 1899 // own caller's stack. 1900 NumBytes = 0; 1901 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1902 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1903 1904 int FPDiff = 0; 1905 if (isTailCall && !IsSibcall) { 1906 // Lower arguments at fp - stackoffset + fpdiff. 1907 unsigned NumBytesCallerPushed = 1908 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1909 FPDiff = NumBytesCallerPushed - NumBytes; 1910 1911 // Set the delta of movement of the returnaddr stackslot. 1912 // But only set if delta is greater than previous delta. 1913 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1914 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1915 } 1916 1917 if (!IsSibcall) 1918 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1919 1920 SDValue RetAddrFrIdx; 1921 // Load return adress for tail calls. 1922 if (isTailCall && FPDiff) 1923 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1924 Is64Bit, FPDiff, dl); 1925 1926 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1927 SmallVector<SDValue, 8> MemOpChains; 1928 SDValue StackPtr; 1929 1930 // Walk the register/memloc assignments, inserting copies/loads. In the case 1931 // of tail call optimization arguments are handle later. 1932 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1933 CCValAssign &VA = ArgLocs[i]; 1934 EVT RegVT = VA.getLocVT(); 1935 SDValue Arg = OutVals[i]; 1936 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1937 bool isByVal = Flags.isByVal(); 1938 1939 // Promote the value if needed. 1940 switch (VA.getLocInfo()) { 1941 default: llvm_unreachable("Unknown loc info!"); 1942 case CCValAssign::Full: break; 1943 case CCValAssign::SExt: 1944 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1945 break; 1946 case CCValAssign::ZExt: 1947 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1948 break; 1949 case CCValAssign::AExt: 1950 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1951 // Special case: passing MMX values in XMM registers. 1952 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 1953 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1954 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1955 } else 1956 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1957 break; 1958 case CCValAssign::BCvt: 1959 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 1960 break; 1961 case CCValAssign::Indirect: { 1962 // Store the argument. 1963 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1964 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1965 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1966 MachinePointerInfo::getFixedStack(FI), 1967 false, false, 0); 1968 Arg = SpillSlot; 1969 break; 1970 } 1971 } 1972 1973 if (VA.isRegLoc()) { 1974 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1975 if (isVarArg && Subtarget->isTargetWin64()) { 1976 // Win64 ABI requires argument XMM reg to be copied to the corresponding 1977 // shadow reg if callee is a varargs function. 1978 unsigned ShadowReg = 0; 1979 switch (VA.getLocReg()) { 1980 case X86::XMM0: ShadowReg = X86::RCX; break; 1981 case X86::XMM1: ShadowReg = X86::RDX; break; 1982 case X86::XMM2: ShadowReg = X86::R8; break; 1983 case X86::XMM3: ShadowReg = X86::R9; break; 1984 } 1985 if (ShadowReg) 1986 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 1987 } 1988 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1989 assert(VA.isMemLoc()); 1990 if (StackPtr.getNode() == 0) 1991 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1992 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1993 dl, DAG, VA, Flags)); 1994 } 1995 } 1996 1997 if (!MemOpChains.empty()) 1998 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1999 &MemOpChains[0], MemOpChains.size()); 2000 2001 // Build a sequence of copy-to-reg nodes chained together with token chain 2002 // and flag operands which copy the outgoing args into registers. 2003 SDValue InFlag; 2004 // Tail call byval lowering might overwrite argument registers so in case of 2005 // tail call optimization the copies to registers are lowered later. 2006 if (!isTailCall) 2007 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2008 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2009 RegsToPass[i].second, InFlag); 2010 InFlag = Chain.getValue(1); 2011 } 2012 2013 if (Subtarget->isPICStyleGOT()) { 2014 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2015 // GOT pointer. 2016 if (!isTailCall) { 2017 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2018 DAG.getNode(X86ISD::GlobalBaseReg, 2019 DebugLoc(), getPointerTy()), 2020 InFlag); 2021 InFlag = Chain.getValue(1); 2022 } else { 2023 // If we are tail calling and generating PIC/GOT style code load the 2024 // address of the callee into ECX. The value in ecx is used as target of 2025 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2026 // for tail calls on PIC/GOT architectures. Normally we would just put the 2027 // address of GOT into ebx and then call target@PLT. But for tail calls 2028 // ebx would be restored (since ebx is callee saved) before jumping to the 2029 // target@PLT. 2030 2031 // Note: The actual moving to ECX is done further down. 2032 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2033 if (G && !G->getGlobal()->hasHiddenVisibility() && 2034 !G->getGlobal()->hasProtectedVisibility()) 2035 Callee = LowerGlobalAddress(Callee, DAG); 2036 else if (isa<ExternalSymbolSDNode>(Callee)) 2037 Callee = LowerExternalSymbol(Callee, DAG); 2038 } 2039 } 2040 2041 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { 2042 // From AMD64 ABI document: 2043 // For calls that may call functions that use varargs or stdargs 2044 // (prototype-less calls or calls to functions containing ellipsis (...) in 2045 // the declaration) %al is used as hidden argument to specify the number 2046 // of SSE registers used. The contents of %al do not need to match exactly 2047 // the number of registers, but must be an ubound on the number of SSE 2048 // registers used and is in the range 0 - 8 inclusive. 2049 2050 // Count the number of XMM registers allocated. 2051 static const unsigned XMMArgRegs[] = { 2052 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2053 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2054 }; 2055 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2056 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2057 && "SSE registers cannot be used when SSE is disabled"); 2058 2059 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2060 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2061 InFlag = Chain.getValue(1); 2062 } 2063 2064 2065 // For tail calls lower the arguments to the 'real' stack slot. 2066 if (isTailCall) { 2067 // Force all the incoming stack arguments to be loaded from the stack 2068 // before any new outgoing arguments are stored to the stack, because the 2069 // outgoing stack slots may alias the incoming argument stack slots, and 2070 // the alias isn't otherwise explicit. This is slightly more conservative 2071 // than necessary, because it means that each store effectively depends 2072 // on every argument instead of just those arguments it would clobber. 2073 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2074 2075 SmallVector<SDValue, 8> MemOpChains2; 2076 SDValue FIN; 2077 int FI = 0; 2078 // Do not flag preceeding copytoreg stuff together with the following stuff. 2079 InFlag = SDValue(); 2080 if (GuaranteedTailCallOpt) { 2081 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2082 CCValAssign &VA = ArgLocs[i]; 2083 if (VA.isRegLoc()) 2084 continue; 2085 assert(VA.isMemLoc()); 2086 SDValue Arg = OutVals[i]; 2087 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2088 // Create frame index. 2089 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2090 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2091 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2092 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2093 2094 if (Flags.isByVal()) { 2095 // Copy relative to framepointer. 2096 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2097 if (StackPtr.getNode() == 0) 2098 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2099 getPointerTy()); 2100 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2101 2102 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2103 ArgChain, 2104 Flags, DAG, dl)); 2105 } else { 2106 // Store relative to framepointer. 2107 MemOpChains2.push_back( 2108 DAG.getStore(ArgChain, dl, Arg, FIN, 2109 MachinePointerInfo::getFixedStack(FI), 2110 false, false, 0)); 2111 } 2112 } 2113 } 2114 2115 if (!MemOpChains2.empty()) 2116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2117 &MemOpChains2[0], MemOpChains2.size()); 2118 2119 // Copy arguments to their registers. 2120 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2121 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2122 RegsToPass[i].second, InFlag); 2123 InFlag = Chain.getValue(1); 2124 } 2125 InFlag =SDValue(); 2126 2127 // Store the return address to the appropriate stack slot. 2128 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2129 FPDiff, dl); 2130 } 2131 2132 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2133 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2134 // In the 64-bit large code model, we have to make all calls 2135 // through a register, since the call instruction's 32-bit 2136 // pc-relative offset may not be large enough to hold the whole 2137 // address. 2138 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2139 // If the callee is a GlobalAddress node (quite common, every direct call 2140 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2141 // it. 2142 2143 // We should use extra load for direct calls to dllimported functions in 2144 // non-JIT mode. 2145 const GlobalValue *GV = G->getGlobal(); 2146 if (!GV->hasDLLImportLinkage()) { 2147 unsigned char OpFlags = 0; 2148 2149 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2150 // external symbols most go through the PLT in PIC mode. If the symbol 2151 // has hidden or protected visibility, or if it is static or local, then 2152 // we don't need to use the PLT - we can directly call it. 2153 if (Subtarget->isTargetELF() && 2154 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2155 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2156 OpFlags = X86II::MO_PLT; 2157 } else if (Subtarget->isPICStyleStubAny() && 2158 (GV->isDeclaration() || GV->isWeakForLinker()) && 2159 Subtarget->getDarwinVers() < 9) { 2160 // PC-relative references to external symbols should go through $stub, 2161 // unless we're building with the leopard linker or later, which 2162 // automatically synthesizes these stubs. 2163 OpFlags = X86II::MO_DARWIN_STUB; 2164 } 2165 2166 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2167 G->getOffset(), OpFlags); 2168 } 2169 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2170 unsigned char OpFlags = 0; 2171 2172 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2173 // external symbols should go through the PLT. 2174 if (Subtarget->isTargetELF() && 2175 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2176 OpFlags = X86II::MO_PLT; 2177 } else if (Subtarget->isPICStyleStubAny() && 2178 Subtarget->getDarwinVers() < 9) { 2179 // PC-relative references to external symbols should go through $stub, 2180 // unless we're building with the leopard linker or later, which 2181 // automatically synthesizes these stubs. 2182 OpFlags = X86II::MO_DARWIN_STUB; 2183 } 2184 2185 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2186 OpFlags); 2187 } 2188 2189 // Returns a chain & a flag for retval copy to use. 2190 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2191 SmallVector<SDValue, 8> Ops; 2192 2193 if (!IsSibcall && isTailCall) { 2194 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2195 DAG.getIntPtrConstant(0, true), InFlag); 2196 InFlag = Chain.getValue(1); 2197 } 2198 2199 Ops.push_back(Chain); 2200 Ops.push_back(Callee); 2201 2202 if (isTailCall) 2203 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2204 2205 // Add argument registers to the end of the list so that they are known live 2206 // into the call. 2207 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2208 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2209 RegsToPass[i].second.getValueType())); 2210 2211 // Add an implicit use GOT pointer in EBX. 2212 if (!isTailCall && Subtarget->isPICStyleGOT()) 2213 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2214 2215 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2216 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) 2217 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2218 2219 if (InFlag.getNode()) 2220 Ops.push_back(InFlag); 2221 2222 if (isTailCall) { 2223 // We used to do: 2224 //// If this is the first return lowered for this function, add the regs 2225 //// to the liveout set for the function. 2226 // This isn't right, although it's probably harmless on x86; liveouts 2227 // should be computed from returns not tail calls. Consider a void 2228 // function making a tail call to a function returning int. 2229 return DAG.getNode(X86ISD::TC_RETURN, dl, 2230 NodeTys, &Ops[0], Ops.size()); 2231 } 2232 2233 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2234 InFlag = Chain.getValue(1); 2235 2236 // Create the CALLSEQ_END node. 2237 unsigned NumBytesForCalleeToPush; 2238 if (Subtarget->IsCalleePop(isVarArg, CallConv)) 2239 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2240 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2241 // If this is a call to a struct-return function, the callee 2242 // pops the hidden struct pointer, so we have to push it back. 2243 // This is common for Darwin/X86, Linux & Mingw32 targets. 2244 NumBytesForCalleeToPush = 4; 2245 else 2246 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2247 2248 // Returns a flag for retval copy to use. 2249 if (!IsSibcall) { 2250 Chain = DAG.getCALLSEQ_END(Chain, 2251 DAG.getIntPtrConstant(NumBytes, true), 2252 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2253 true), 2254 InFlag); 2255 InFlag = Chain.getValue(1); 2256 } 2257 2258 // Handle result values, copying them out of physregs into vregs that we 2259 // return. 2260 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2261 Ins, dl, DAG, InVals); 2262} 2263 2264 2265//===----------------------------------------------------------------------===// 2266// Fast Calling Convention (tail call) implementation 2267//===----------------------------------------------------------------------===// 2268 2269// Like std call, callee cleans arguments, convention except that ECX is 2270// reserved for storing the tail called function address. Only 2 registers are 2271// free for argument passing (inreg). Tail call optimization is performed 2272// provided: 2273// * tailcallopt is enabled 2274// * caller/callee are fastcc 2275// On X86_64 architecture with GOT-style position independent code only local 2276// (within module) calls are supported at the moment. 2277// To keep the stack aligned according to platform abi the function 2278// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2279// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2280// If a tail called function callee has more arguments than the caller the 2281// caller needs to make sure that there is room to move the RETADDR to. This is 2282// achieved by reserving an area the size of the argument delta right after the 2283// original REtADDR, but before the saved framepointer or the spilled registers 2284// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2285// stack layout: 2286// arg1 2287// arg2 2288// RETADDR 2289// [ new RETADDR 2290// move area ] 2291// (possible EBP) 2292// ESI 2293// EDI 2294// local1 .. 2295 2296/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2297/// for a 16 byte align requirement. 2298unsigned 2299X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2300 SelectionDAG& DAG) const { 2301 MachineFunction &MF = DAG.getMachineFunction(); 2302 const TargetMachine &TM = MF.getTarget(); 2303 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2304 unsigned StackAlignment = TFI.getStackAlignment(); 2305 uint64_t AlignMask = StackAlignment - 1; 2306 int64_t Offset = StackSize; 2307 uint64_t SlotSize = TD->getPointerSize(); 2308 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2309 // Number smaller than 12 so just add the difference. 2310 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2311 } else { 2312 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2313 Offset = ((~AlignMask) & Offset) + StackAlignment + 2314 (StackAlignment-SlotSize); 2315 } 2316 return Offset; 2317} 2318 2319/// MatchingStackOffset - Return true if the given stack call argument is 2320/// already available in the same position (relatively) of the caller's 2321/// incoming argument stack. 2322static 2323bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2324 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2325 const X86InstrInfo *TII) { 2326 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2327 int FI = INT_MAX; 2328 if (Arg.getOpcode() == ISD::CopyFromReg) { 2329 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2330 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2331 return false; 2332 MachineInstr *Def = MRI->getVRegDef(VR); 2333 if (!Def) 2334 return false; 2335 if (!Flags.isByVal()) { 2336 if (!TII->isLoadFromStackSlot(Def, FI)) 2337 return false; 2338 } else { 2339 unsigned Opcode = Def->getOpcode(); 2340 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2341 Def->getOperand(1).isFI()) { 2342 FI = Def->getOperand(1).getIndex(); 2343 Bytes = Flags.getByValSize(); 2344 } else 2345 return false; 2346 } 2347 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2348 if (Flags.isByVal()) 2349 // ByVal argument is passed in as a pointer but it's now being 2350 // dereferenced. e.g. 2351 // define @foo(%struct.X* %A) { 2352 // tail call @bar(%struct.X* byval %A) 2353 // } 2354 return false; 2355 SDValue Ptr = Ld->getBasePtr(); 2356 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2357 if (!FINode) 2358 return false; 2359 FI = FINode->getIndex(); 2360 } else 2361 return false; 2362 2363 assert(FI != INT_MAX); 2364 if (!MFI->isFixedObjectIndex(FI)) 2365 return false; 2366 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2367} 2368 2369/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2370/// for tail call optimization. Targets which want to do tail call 2371/// optimization should implement this function. 2372bool 2373X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2374 CallingConv::ID CalleeCC, 2375 bool isVarArg, 2376 bool isCalleeStructRet, 2377 bool isCallerStructRet, 2378 const SmallVectorImpl<ISD::OutputArg> &Outs, 2379 const SmallVectorImpl<SDValue> &OutVals, 2380 const SmallVectorImpl<ISD::InputArg> &Ins, 2381 SelectionDAG& DAG) const { 2382 if (!IsTailCallConvention(CalleeCC) && 2383 CalleeCC != CallingConv::C) 2384 return false; 2385 2386 // If -tailcallopt is specified, make fastcc functions tail-callable. 2387 const MachineFunction &MF = DAG.getMachineFunction(); 2388 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2389 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2390 bool CCMatch = CallerCC == CalleeCC; 2391 2392 if (GuaranteedTailCallOpt) { 2393 if (IsTailCallConvention(CalleeCC) && CCMatch) 2394 return true; 2395 return false; 2396 } 2397 2398 // Look for obvious safe cases to perform tail call optimization that do not 2399 // require ABI changes. This is what gcc calls sibcall. 2400 2401 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2402 // emit a special epilogue. 2403 if (RegInfo->needsStackRealignment(MF)) 2404 return false; 2405 2406 // Do not sibcall optimize vararg calls unless the call site is not passing 2407 // any arguments. 2408 if (isVarArg && !Outs.empty()) 2409 return false; 2410 2411 // Also avoid sibcall optimization if either caller or callee uses struct 2412 // return semantics. 2413 if (isCalleeStructRet || isCallerStructRet) 2414 return false; 2415 2416 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2417 // Therefore if it's not used by the call it is not safe to optimize this into 2418 // a sibcall. 2419 bool Unused = false; 2420 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2421 if (!Ins[i].Used) { 2422 Unused = true; 2423 break; 2424 } 2425 } 2426 if (Unused) { 2427 SmallVector<CCValAssign, 16> RVLocs; 2428 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2429 RVLocs, *DAG.getContext()); 2430 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2431 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2432 CCValAssign &VA = RVLocs[i]; 2433 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2434 return false; 2435 } 2436 } 2437 2438 // If the calling conventions do not match, then we'd better make sure the 2439 // results are returned in the same way as what the caller expects. 2440 if (!CCMatch) { 2441 SmallVector<CCValAssign, 16> RVLocs1; 2442 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 2443 RVLocs1, *DAG.getContext()); 2444 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2445 2446 SmallVector<CCValAssign, 16> RVLocs2; 2447 CCState CCInfo2(CallerCC, false, getTargetMachine(), 2448 RVLocs2, *DAG.getContext()); 2449 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2450 2451 if (RVLocs1.size() != RVLocs2.size()) 2452 return false; 2453 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2454 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2455 return false; 2456 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2457 return false; 2458 if (RVLocs1[i].isRegLoc()) { 2459 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2460 return false; 2461 } else { 2462 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2463 return false; 2464 } 2465 } 2466 } 2467 2468 // If the callee takes no arguments then go on to check the results of the 2469 // call. 2470 if (!Outs.empty()) { 2471 // Check if stack adjustment is needed. For now, do not do this if any 2472 // argument is passed on the stack. 2473 SmallVector<CCValAssign, 16> ArgLocs; 2474 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2475 ArgLocs, *DAG.getContext()); 2476 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2477 if (CCInfo.getNextStackOffset()) { 2478 MachineFunction &MF = DAG.getMachineFunction(); 2479 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2480 return false; 2481 if (Subtarget->isTargetWin64()) 2482 // Win64 ABI has additional complications. 2483 return false; 2484 2485 // Check if the arguments are already laid out in the right way as 2486 // the caller's fixed stack objects. 2487 MachineFrameInfo *MFI = MF.getFrameInfo(); 2488 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2489 const X86InstrInfo *TII = 2490 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2491 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2492 CCValAssign &VA = ArgLocs[i]; 2493 SDValue Arg = OutVals[i]; 2494 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2495 if (VA.getLocInfo() == CCValAssign::Indirect) 2496 return false; 2497 if (!VA.isRegLoc()) { 2498 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2499 MFI, MRI, TII)) 2500 return false; 2501 } 2502 } 2503 } 2504 2505 // If the tailcall address may be in a register, then make sure it's 2506 // possible to register allocate for it. In 32-bit, the call address can 2507 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2508 // callee-saved registers are restored. These happen to be the same 2509 // registers used to pass 'inreg' arguments so watch out for those. 2510 if (!Subtarget->is64Bit() && 2511 !isa<GlobalAddressSDNode>(Callee) && 2512 !isa<ExternalSymbolSDNode>(Callee)) { 2513 unsigned NumInRegs = 0; 2514 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2515 CCValAssign &VA = ArgLocs[i]; 2516 if (!VA.isRegLoc()) 2517 continue; 2518 unsigned Reg = VA.getLocReg(); 2519 switch (Reg) { 2520 default: break; 2521 case X86::EAX: case X86::EDX: case X86::ECX: 2522 if (++NumInRegs == 3) 2523 return false; 2524 break; 2525 } 2526 } 2527 } 2528 } 2529 2530 // An stdcall caller is expected to clean up its arguments; the callee 2531 // isn't going to do that. 2532 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2533 return false; 2534 2535 return true; 2536} 2537 2538FastISel * 2539X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2540 return X86::createFastISel(funcInfo); 2541} 2542 2543 2544//===----------------------------------------------------------------------===// 2545// Other Lowering Hooks 2546//===----------------------------------------------------------------------===// 2547 2548static bool MayFoldLoad(SDValue Op) { 2549 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2550} 2551 2552static bool MayFoldIntoStore(SDValue Op) { 2553 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2554} 2555 2556static bool isTargetShuffle(unsigned Opcode) { 2557 switch(Opcode) { 2558 default: return false; 2559 case X86ISD::PSHUFD: 2560 case X86ISD::PSHUFHW: 2561 case X86ISD::PSHUFLW: 2562 case X86ISD::SHUFPD: 2563 case X86ISD::PALIGN: 2564 case X86ISD::SHUFPS: 2565 case X86ISD::MOVLHPS: 2566 case X86ISD::MOVLHPD: 2567 case X86ISD::MOVHLPS: 2568 case X86ISD::MOVLPS: 2569 case X86ISD::MOVLPD: 2570 case X86ISD::MOVSHDUP: 2571 case X86ISD::MOVSLDUP: 2572 case X86ISD::MOVDDUP: 2573 case X86ISD::MOVSS: 2574 case X86ISD::MOVSD: 2575 case X86ISD::UNPCKLPS: 2576 case X86ISD::UNPCKLPD: 2577 case X86ISD::PUNPCKLWD: 2578 case X86ISD::PUNPCKLBW: 2579 case X86ISD::PUNPCKLDQ: 2580 case X86ISD::PUNPCKLQDQ: 2581 case X86ISD::UNPCKHPS: 2582 case X86ISD::UNPCKHPD: 2583 case X86ISD::PUNPCKHWD: 2584 case X86ISD::PUNPCKHBW: 2585 case X86ISD::PUNPCKHDQ: 2586 case X86ISD::PUNPCKHQDQ: 2587 return true; 2588 } 2589 return false; 2590} 2591 2592static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2593 SDValue V1, SelectionDAG &DAG) { 2594 switch(Opc) { 2595 default: llvm_unreachable("Unknown x86 shuffle node"); 2596 case X86ISD::MOVSHDUP: 2597 case X86ISD::MOVSLDUP: 2598 case X86ISD::MOVDDUP: 2599 return DAG.getNode(Opc, dl, VT, V1); 2600 } 2601 2602 return SDValue(); 2603} 2604 2605static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2606 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2607 switch(Opc) { 2608 default: llvm_unreachable("Unknown x86 shuffle node"); 2609 case X86ISD::PSHUFD: 2610 case X86ISD::PSHUFHW: 2611 case X86ISD::PSHUFLW: 2612 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2613 } 2614 2615 return SDValue(); 2616} 2617 2618static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2619 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2620 switch(Opc) { 2621 default: llvm_unreachable("Unknown x86 shuffle node"); 2622 case X86ISD::PALIGN: 2623 case X86ISD::SHUFPD: 2624 case X86ISD::SHUFPS: 2625 return DAG.getNode(Opc, dl, VT, V1, V2, 2626 DAG.getConstant(TargetMask, MVT::i8)); 2627 } 2628 return SDValue(); 2629} 2630 2631static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2632 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2633 switch(Opc) { 2634 default: llvm_unreachable("Unknown x86 shuffle node"); 2635 case X86ISD::MOVLHPS: 2636 case X86ISD::MOVLHPD: 2637 case X86ISD::MOVHLPS: 2638 case X86ISD::MOVLPS: 2639 case X86ISD::MOVLPD: 2640 case X86ISD::MOVSS: 2641 case X86ISD::MOVSD: 2642 case X86ISD::UNPCKLPS: 2643 case X86ISD::UNPCKLPD: 2644 case X86ISD::PUNPCKLWD: 2645 case X86ISD::PUNPCKLBW: 2646 case X86ISD::PUNPCKLDQ: 2647 case X86ISD::PUNPCKLQDQ: 2648 case X86ISD::UNPCKHPS: 2649 case X86ISD::UNPCKHPD: 2650 case X86ISD::PUNPCKHWD: 2651 case X86ISD::PUNPCKHBW: 2652 case X86ISD::PUNPCKHDQ: 2653 case X86ISD::PUNPCKHQDQ: 2654 return DAG.getNode(Opc, dl, VT, V1, V2); 2655 } 2656 return SDValue(); 2657} 2658 2659SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2660 MachineFunction &MF = DAG.getMachineFunction(); 2661 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2662 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2663 2664 if (ReturnAddrIndex == 0) { 2665 // Set up a frame object for the return address. 2666 uint64_t SlotSize = TD->getPointerSize(); 2667 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2668 false); 2669 FuncInfo->setRAIndex(ReturnAddrIndex); 2670 } 2671 2672 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2673} 2674 2675 2676bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2677 bool hasSymbolicDisplacement) { 2678 // Offset should fit into 32 bit immediate field. 2679 if (!isInt<32>(Offset)) 2680 return false; 2681 2682 // If we don't have a symbolic displacement - we don't have any extra 2683 // restrictions. 2684 if (!hasSymbolicDisplacement) 2685 return true; 2686 2687 // FIXME: Some tweaks might be needed for medium code model. 2688 if (M != CodeModel::Small && M != CodeModel::Kernel) 2689 return false; 2690 2691 // For small code model we assume that latest object is 16MB before end of 31 2692 // bits boundary. We may also accept pretty large negative constants knowing 2693 // that all objects are in the positive half of address space. 2694 if (M == CodeModel::Small && Offset < 16*1024*1024) 2695 return true; 2696 2697 // For kernel code model we know that all object resist in the negative half 2698 // of 32bits address space. We may not accept negative offsets, since they may 2699 // be just off and we may accept pretty large positive ones. 2700 if (M == CodeModel::Kernel && Offset > 0) 2701 return true; 2702 2703 return false; 2704} 2705 2706/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2707/// specific condition code, returning the condition code and the LHS/RHS of the 2708/// comparison to make. 2709static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2710 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2711 if (!isFP) { 2712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2713 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2714 // X > -1 -> X == 0, jump !sign. 2715 RHS = DAG.getConstant(0, RHS.getValueType()); 2716 return X86::COND_NS; 2717 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2718 // X < 0 -> X == 0, jump on sign. 2719 return X86::COND_S; 2720 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2721 // X < 1 -> X <= 0 2722 RHS = DAG.getConstant(0, RHS.getValueType()); 2723 return X86::COND_LE; 2724 } 2725 } 2726 2727 switch (SetCCOpcode) { 2728 default: llvm_unreachable("Invalid integer condition!"); 2729 case ISD::SETEQ: return X86::COND_E; 2730 case ISD::SETGT: return X86::COND_G; 2731 case ISD::SETGE: return X86::COND_GE; 2732 case ISD::SETLT: return X86::COND_L; 2733 case ISD::SETLE: return X86::COND_LE; 2734 case ISD::SETNE: return X86::COND_NE; 2735 case ISD::SETULT: return X86::COND_B; 2736 case ISD::SETUGT: return X86::COND_A; 2737 case ISD::SETULE: return X86::COND_BE; 2738 case ISD::SETUGE: return X86::COND_AE; 2739 } 2740 } 2741 2742 // First determine if it is required or is profitable to flip the operands. 2743 2744 // If LHS is a foldable load, but RHS is not, flip the condition. 2745 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2746 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2747 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2748 std::swap(LHS, RHS); 2749 } 2750 2751 switch (SetCCOpcode) { 2752 default: break; 2753 case ISD::SETOLT: 2754 case ISD::SETOLE: 2755 case ISD::SETUGT: 2756 case ISD::SETUGE: 2757 std::swap(LHS, RHS); 2758 break; 2759 } 2760 2761 // On a floating point condition, the flags are set as follows: 2762 // ZF PF CF op 2763 // 0 | 0 | 0 | X > Y 2764 // 0 | 0 | 1 | X < Y 2765 // 1 | 0 | 0 | X == Y 2766 // 1 | 1 | 1 | unordered 2767 switch (SetCCOpcode) { 2768 default: llvm_unreachable("Condcode should be pre-legalized away"); 2769 case ISD::SETUEQ: 2770 case ISD::SETEQ: return X86::COND_E; 2771 case ISD::SETOLT: // flipped 2772 case ISD::SETOGT: 2773 case ISD::SETGT: return X86::COND_A; 2774 case ISD::SETOLE: // flipped 2775 case ISD::SETOGE: 2776 case ISD::SETGE: return X86::COND_AE; 2777 case ISD::SETUGT: // flipped 2778 case ISD::SETULT: 2779 case ISD::SETLT: return X86::COND_B; 2780 case ISD::SETUGE: // flipped 2781 case ISD::SETULE: 2782 case ISD::SETLE: return X86::COND_BE; 2783 case ISD::SETONE: 2784 case ISD::SETNE: return X86::COND_NE; 2785 case ISD::SETUO: return X86::COND_P; 2786 case ISD::SETO: return X86::COND_NP; 2787 case ISD::SETOEQ: 2788 case ISD::SETUNE: return X86::COND_INVALID; 2789 } 2790} 2791 2792/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2793/// code. Current x86 isa includes the following FP cmov instructions: 2794/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2795static bool hasFPCMov(unsigned X86CC) { 2796 switch (X86CC) { 2797 default: 2798 return false; 2799 case X86::COND_B: 2800 case X86::COND_BE: 2801 case X86::COND_E: 2802 case X86::COND_P: 2803 case X86::COND_A: 2804 case X86::COND_AE: 2805 case X86::COND_NE: 2806 case X86::COND_NP: 2807 return true; 2808 } 2809} 2810 2811/// isFPImmLegal - Returns true if the target can instruction select the 2812/// specified FP immediate natively. If false, the legalizer will 2813/// materialize the FP immediate as a load from a constant pool. 2814bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2815 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2816 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2817 return true; 2818 } 2819 return false; 2820} 2821 2822/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2823/// the specified range (L, H]. 2824static bool isUndefOrInRange(int Val, int Low, int Hi) { 2825 return (Val < 0) || (Val >= Low && Val < Hi); 2826} 2827 2828/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2829/// specified value. 2830static bool isUndefOrEqual(int Val, int CmpVal) { 2831 if (Val < 0 || Val == CmpVal) 2832 return true; 2833 return false; 2834} 2835 2836/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2837/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2838/// the second operand. 2839static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2840 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 2841 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2842 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2843 return (Mask[0] < 2 && Mask[1] < 2); 2844 return false; 2845} 2846 2847bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2848 SmallVector<int, 8> M; 2849 N->getMask(M); 2850 return ::isPSHUFDMask(M, N->getValueType(0)); 2851} 2852 2853/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2854/// is suitable for input to PSHUFHW. 2855static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2856 if (VT != MVT::v8i16) 2857 return false; 2858 2859 // Lower quadword copied in order or undef. 2860 for (int i = 0; i != 4; ++i) 2861 if (Mask[i] >= 0 && Mask[i] != i) 2862 return false; 2863 2864 // Upper quadword shuffled. 2865 for (int i = 4; i != 8; ++i) 2866 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2867 return false; 2868 2869 return true; 2870} 2871 2872bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2873 SmallVector<int, 8> M; 2874 N->getMask(M); 2875 return ::isPSHUFHWMask(M, N->getValueType(0)); 2876} 2877 2878/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2879/// is suitable for input to PSHUFLW. 2880static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2881 if (VT != MVT::v8i16) 2882 return false; 2883 2884 // Upper quadword copied in order. 2885 for (int i = 4; i != 8; ++i) 2886 if (Mask[i] >= 0 && Mask[i] != i) 2887 return false; 2888 2889 // Lower quadword shuffled. 2890 for (int i = 0; i != 4; ++i) 2891 if (Mask[i] >= 4) 2892 return false; 2893 2894 return true; 2895} 2896 2897bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2898 SmallVector<int, 8> M; 2899 N->getMask(M); 2900 return ::isPSHUFLWMask(M, N->getValueType(0)); 2901} 2902 2903/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2904/// is suitable for input to PALIGNR. 2905static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2906 bool hasSSSE3) { 2907 int i, e = VT.getVectorNumElements(); 2908 2909 // Do not handle v2i64 / v2f64 shuffles with palignr. 2910 if (e < 4 || !hasSSSE3) 2911 return false; 2912 2913 for (i = 0; i != e; ++i) 2914 if (Mask[i] >= 0) 2915 break; 2916 2917 // All undef, not a palignr. 2918 if (i == e) 2919 return false; 2920 2921 // Determine if it's ok to perform a palignr with only the LHS, since we 2922 // don't have access to the actual shuffle elements to see if RHS is undef. 2923 bool Unary = Mask[i] < (int)e; 2924 bool NeedsUnary = false; 2925 2926 int s = Mask[i] - i; 2927 2928 // Check the rest of the elements to see if they are consecutive. 2929 for (++i; i != e; ++i) { 2930 int m = Mask[i]; 2931 if (m < 0) 2932 continue; 2933 2934 Unary = Unary && (m < (int)e); 2935 NeedsUnary = NeedsUnary || (m < s); 2936 2937 if (NeedsUnary && !Unary) 2938 return false; 2939 if (Unary && m != ((s+i) & (e-1))) 2940 return false; 2941 if (!Unary && m != (s+i)) 2942 return false; 2943 } 2944 return true; 2945} 2946 2947bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2948 SmallVector<int, 8> M; 2949 N->getMask(M); 2950 return ::isPALIGNRMask(M, N->getValueType(0), true); 2951} 2952 2953/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2954/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2955static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2956 int NumElems = VT.getVectorNumElements(); 2957 if (NumElems != 2 && NumElems != 4) 2958 return false; 2959 2960 int Half = NumElems / 2; 2961 for (int i = 0; i < Half; ++i) 2962 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2963 return false; 2964 for (int i = Half; i < NumElems; ++i) 2965 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2966 return false; 2967 2968 return true; 2969} 2970 2971bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2972 SmallVector<int, 8> M; 2973 N->getMask(M); 2974 return ::isSHUFPMask(M, N->getValueType(0)); 2975} 2976 2977/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2978/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2979/// half elements to come from vector 1 (which would equal the dest.) and 2980/// the upper half to come from vector 2. 2981static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2982 int NumElems = VT.getVectorNumElements(); 2983 2984 if (NumElems != 2 && NumElems != 4) 2985 return false; 2986 2987 int Half = NumElems / 2; 2988 for (int i = 0; i < Half; ++i) 2989 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2990 return false; 2991 for (int i = Half; i < NumElems; ++i) 2992 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2993 return false; 2994 return true; 2995} 2996 2997static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2998 SmallVector<int, 8> M; 2999 N->getMask(M); 3000 return isCommutedSHUFPMask(M, N->getValueType(0)); 3001} 3002 3003/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3004/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3005bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3006 if (N->getValueType(0).getVectorNumElements() != 4) 3007 return false; 3008 3009 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3010 return isUndefOrEqual(N->getMaskElt(0), 6) && 3011 isUndefOrEqual(N->getMaskElt(1), 7) && 3012 isUndefOrEqual(N->getMaskElt(2), 2) && 3013 isUndefOrEqual(N->getMaskElt(3), 3); 3014} 3015 3016/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3017/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3018/// <2, 3, 2, 3> 3019bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3020 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3021 3022 if (NumElems != 4) 3023 return false; 3024 3025 return isUndefOrEqual(N->getMaskElt(0), 2) && 3026 isUndefOrEqual(N->getMaskElt(1), 3) && 3027 isUndefOrEqual(N->getMaskElt(2), 2) && 3028 isUndefOrEqual(N->getMaskElt(3), 3); 3029} 3030 3031/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3032/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3033bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3034 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3035 3036 if (NumElems != 2 && NumElems != 4) 3037 return false; 3038 3039 for (unsigned i = 0; i < NumElems/2; ++i) 3040 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3041 return false; 3042 3043 for (unsigned i = NumElems/2; i < NumElems; ++i) 3044 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3045 return false; 3046 3047 return true; 3048} 3049 3050/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3051/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3052bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3053 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3054 3055 if (NumElems != 2 && NumElems != 4) 3056 return false; 3057 3058 for (unsigned i = 0; i < NumElems/2; ++i) 3059 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3060 return false; 3061 3062 for (unsigned i = 0; i < NumElems/2; ++i) 3063 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3064 return false; 3065 3066 return true; 3067} 3068 3069/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3070/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3071static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3072 bool V2IsSplat = false) { 3073 int NumElts = VT.getVectorNumElements(); 3074 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3075 return false; 3076 3077 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3078 int BitI = Mask[i]; 3079 int BitI1 = Mask[i+1]; 3080 if (!isUndefOrEqual(BitI, j)) 3081 return false; 3082 if (V2IsSplat) { 3083 if (!isUndefOrEqual(BitI1, NumElts)) 3084 return false; 3085 } else { 3086 if (!isUndefOrEqual(BitI1, j + NumElts)) 3087 return false; 3088 } 3089 } 3090 return true; 3091} 3092 3093bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3094 SmallVector<int, 8> M; 3095 N->getMask(M); 3096 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3097} 3098 3099/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3100/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3101static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3102 bool V2IsSplat = false) { 3103 int NumElts = VT.getVectorNumElements(); 3104 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3105 return false; 3106 3107 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3108 int BitI = Mask[i]; 3109 int BitI1 = Mask[i+1]; 3110 if (!isUndefOrEqual(BitI, j + NumElts/2)) 3111 return false; 3112 if (V2IsSplat) { 3113 if (isUndefOrEqual(BitI1, NumElts)) 3114 return false; 3115 } else { 3116 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 3117 return false; 3118 } 3119 } 3120 return true; 3121} 3122 3123bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3124 SmallVector<int, 8> M; 3125 N->getMask(M); 3126 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3127} 3128 3129/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3130/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3131/// <0, 0, 1, 1> 3132static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3133 int NumElems = VT.getVectorNumElements(); 3134 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3135 return false; 3136 3137 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 3138 int BitI = Mask[i]; 3139 int BitI1 = Mask[i+1]; 3140 if (!isUndefOrEqual(BitI, j)) 3141 return false; 3142 if (!isUndefOrEqual(BitI1, j)) 3143 return false; 3144 } 3145 return true; 3146} 3147 3148bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3149 SmallVector<int, 8> M; 3150 N->getMask(M); 3151 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3152} 3153 3154/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3155/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3156/// <2, 2, 3, 3> 3157static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3158 int NumElems = VT.getVectorNumElements(); 3159 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3160 return false; 3161 3162 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3163 int BitI = Mask[i]; 3164 int BitI1 = Mask[i+1]; 3165 if (!isUndefOrEqual(BitI, j)) 3166 return false; 3167 if (!isUndefOrEqual(BitI1, j)) 3168 return false; 3169 } 3170 return true; 3171} 3172 3173bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3174 SmallVector<int, 8> M; 3175 N->getMask(M); 3176 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3177} 3178 3179/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3180/// specifies a shuffle of elements that is suitable for input to MOVSS, 3181/// MOVSD, and MOVD, i.e. setting the lowest element. 3182static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3183 if (VT.getVectorElementType().getSizeInBits() < 32) 3184 return false; 3185 3186 int NumElts = VT.getVectorNumElements(); 3187 3188 if (!isUndefOrEqual(Mask[0], NumElts)) 3189 return false; 3190 3191 for (int i = 1; i < NumElts; ++i) 3192 if (!isUndefOrEqual(Mask[i], i)) 3193 return false; 3194 3195 return true; 3196} 3197 3198bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3199 SmallVector<int, 8> M; 3200 N->getMask(M); 3201 return ::isMOVLMask(M, N->getValueType(0)); 3202} 3203 3204/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3205/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3206/// element of vector 2 and the other elements to come from vector 1 in order. 3207static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3208 bool V2IsSplat = false, bool V2IsUndef = false) { 3209 int NumOps = VT.getVectorNumElements(); 3210 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3211 return false; 3212 3213 if (!isUndefOrEqual(Mask[0], 0)) 3214 return false; 3215 3216 for (int i = 1; i < NumOps; ++i) 3217 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3218 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3219 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3220 return false; 3221 3222 return true; 3223} 3224 3225static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3226 bool V2IsUndef = false) { 3227 SmallVector<int, 8> M; 3228 N->getMask(M); 3229 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3230} 3231 3232/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3233/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3234bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3235 if (N->getValueType(0).getVectorNumElements() != 4) 3236 return false; 3237 3238 // Expect 1, 1, 3, 3 3239 for (unsigned i = 0; i < 2; ++i) { 3240 int Elt = N->getMaskElt(i); 3241 if (Elt >= 0 && Elt != 1) 3242 return false; 3243 } 3244 3245 bool HasHi = false; 3246 for (unsigned i = 2; i < 4; ++i) { 3247 int Elt = N->getMaskElt(i); 3248 if (Elt >= 0 && Elt != 3) 3249 return false; 3250 if (Elt == 3) 3251 HasHi = true; 3252 } 3253 // Don't use movshdup if it can be done with a shufps. 3254 // FIXME: verify that matching u, u, 3, 3 is what we want. 3255 return HasHi; 3256} 3257 3258/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3259/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3260bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3261 if (N->getValueType(0).getVectorNumElements() != 4) 3262 return false; 3263 3264 // Expect 0, 0, 2, 2 3265 for (unsigned i = 0; i < 2; ++i) 3266 if (N->getMaskElt(i) > 0) 3267 return false; 3268 3269 bool HasHi = false; 3270 for (unsigned i = 2; i < 4; ++i) { 3271 int Elt = N->getMaskElt(i); 3272 if (Elt >= 0 && Elt != 2) 3273 return false; 3274 if (Elt == 2) 3275 HasHi = true; 3276 } 3277 // Don't use movsldup if it can be done with a shufps. 3278 return HasHi; 3279} 3280 3281/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3282/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3283bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3284 int e = N->getValueType(0).getVectorNumElements() / 2; 3285 3286 for (int i = 0; i < e; ++i) 3287 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3288 return false; 3289 for (int i = 0; i < e; ++i) 3290 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3291 return false; 3292 return true; 3293} 3294 3295/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3296/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3297unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3299 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3300 3301 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3302 unsigned Mask = 0; 3303 for (int i = 0; i < NumOperands; ++i) { 3304 int Val = SVOp->getMaskElt(NumOperands-i-1); 3305 if (Val < 0) Val = 0; 3306 if (Val >= NumOperands) Val -= NumOperands; 3307 Mask |= Val; 3308 if (i != NumOperands - 1) 3309 Mask <<= Shift; 3310 } 3311 return Mask; 3312} 3313 3314/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3315/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3316unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3318 unsigned Mask = 0; 3319 // 8 nodes, but we only care about the last 4. 3320 for (unsigned i = 7; i >= 4; --i) { 3321 int Val = SVOp->getMaskElt(i); 3322 if (Val >= 0) 3323 Mask |= (Val - 4); 3324 if (i != 4) 3325 Mask <<= 2; 3326 } 3327 return Mask; 3328} 3329 3330/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3331/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3332unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3334 unsigned Mask = 0; 3335 // 8 nodes, but we only care about the first 4. 3336 for (int i = 3; i >= 0; --i) { 3337 int Val = SVOp->getMaskElt(i); 3338 if (Val >= 0) 3339 Mask |= Val; 3340 if (i != 0) 3341 Mask <<= 2; 3342 } 3343 return Mask; 3344} 3345 3346/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3347/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3348unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3350 EVT VVT = N->getValueType(0); 3351 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3352 int Val = 0; 3353 3354 unsigned i, e; 3355 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3356 Val = SVOp->getMaskElt(i); 3357 if (Val >= 0) 3358 break; 3359 } 3360 return (Val - i) * EltSize; 3361} 3362 3363/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3364/// constant +0.0. 3365bool X86::isZeroNode(SDValue Elt) { 3366 return ((isa<ConstantSDNode>(Elt) && 3367 cast<ConstantSDNode>(Elt)->isNullValue()) || 3368 (isa<ConstantFPSDNode>(Elt) && 3369 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3370} 3371 3372/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3373/// their permute mask. 3374static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3375 SelectionDAG &DAG) { 3376 EVT VT = SVOp->getValueType(0); 3377 unsigned NumElems = VT.getVectorNumElements(); 3378 SmallVector<int, 8> MaskVec; 3379 3380 for (unsigned i = 0; i != NumElems; ++i) { 3381 int idx = SVOp->getMaskElt(i); 3382 if (idx < 0) 3383 MaskVec.push_back(idx); 3384 else if (idx < (int)NumElems) 3385 MaskVec.push_back(idx + NumElems); 3386 else 3387 MaskVec.push_back(idx - NumElems); 3388 } 3389 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3390 SVOp->getOperand(0), &MaskVec[0]); 3391} 3392 3393/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3394/// the two vector operands have swapped position. 3395static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3396 unsigned NumElems = VT.getVectorNumElements(); 3397 for (unsigned i = 0; i != NumElems; ++i) { 3398 int idx = Mask[i]; 3399 if (idx < 0) 3400 continue; 3401 else if (idx < (int)NumElems) 3402 Mask[i] = idx + NumElems; 3403 else 3404 Mask[i] = idx - NumElems; 3405 } 3406} 3407 3408/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3409/// match movhlps. The lower half elements should come from upper half of 3410/// V1 (and in order), and the upper half elements should come from the upper 3411/// half of V2 (and in order). 3412static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3413 if (Op->getValueType(0).getVectorNumElements() != 4) 3414 return false; 3415 for (unsigned i = 0, e = 2; i != e; ++i) 3416 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3417 return false; 3418 for (unsigned i = 2; i != 4; ++i) 3419 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3420 return false; 3421 return true; 3422} 3423 3424/// isScalarLoadToVector - Returns true if the node is a scalar load that 3425/// is promoted to a vector. It also returns the LoadSDNode by reference if 3426/// required. 3427static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3428 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3429 return false; 3430 N = N->getOperand(0).getNode(); 3431 if (!ISD::isNON_EXTLoad(N)) 3432 return false; 3433 if (LD) 3434 *LD = cast<LoadSDNode>(N); 3435 return true; 3436} 3437 3438/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3439/// match movlp{s|d}. The lower half elements should come from lower half of 3440/// V1 (and in order), and the upper half elements should come from the upper 3441/// half of V2 (and in order). And since V1 will become the source of the 3442/// MOVLP, it must be either a vector load or a scalar load to vector. 3443static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3444 ShuffleVectorSDNode *Op) { 3445 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3446 return false; 3447 // Is V2 is a vector load, don't do this transformation. We will try to use 3448 // load folding shufps op. 3449 if (ISD::isNON_EXTLoad(V2)) 3450 return false; 3451 3452 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3453 3454 if (NumElems != 2 && NumElems != 4) 3455 return false; 3456 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3457 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3458 return false; 3459 for (unsigned i = NumElems/2; i != NumElems; ++i) 3460 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3461 return false; 3462 return true; 3463} 3464 3465/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3466/// all the same. 3467static bool isSplatVector(SDNode *N) { 3468 if (N->getOpcode() != ISD::BUILD_VECTOR) 3469 return false; 3470 3471 SDValue SplatValue = N->getOperand(0); 3472 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3473 if (N->getOperand(i) != SplatValue) 3474 return false; 3475 return true; 3476} 3477 3478/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3479/// to an zero vector. 3480/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3481static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3482 SDValue V1 = N->getOperand(0); 3483 SDValue V2 = N->getOperand(1); 3484 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3485 for (unsigned i = 0; i != NumElems; ++i) { 3486 int Idx = N->getMaskElt(i); 3487 if (Idx >= (int)NumElems) { 3488 unsigned Opc = V2.getOpcode(); 3489 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3490 continue; 3491 if (Opc != ISD::BUILD_VECTOR || 3492 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3493 return false; 3494 } else if (Idx >= 0) { 3495 unsigned Opc = V1.getOpcode(); 3496 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3497 continue; 3498 if (Opc != ISD::BUILD_VECTOR || 3499 !X86::isZeroNode(V1.getOperand(Idx))) 3500 return false; 3501 } 3502 } 3503 return true; 3504} 3505 3506/// getZeroVector - Returns a vector of specified type with all zero elements. 3507/// 3508static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3509 DebugLoc dl) { 3510 assert(VT.isVector() && "Expected a vector type"); 3511 3512 // Always build SSE zero vectors as <4 x i32> bitcasted 3513 // to their dest type. This ensures they get CSE'd. 3514 SDValue Vec; 3515 if (VT.getSizeInBits() == 128) { // SSE 3516 if (HasSSE2) { // SSE2 3517 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3518 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3519 } else { // SSE1 3520 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3521 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3522 } 3523 } else if (VT.getSizeInBits() == 256) { // AVX 3524 // 256-bit logic and arithmetic instructions in AVX are 3525 // all floating-point, no support for integer ops. Default 3526 // to emitting fp zeroed vectors then. 3527 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3528 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3529 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3530 } 3531 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3532} 3533 3534/// getOnesVector - Returns a vector of specified type with all bits set. 3535/// 3536static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3537 assert(VT.isVector() && "Expected a vector type"); 3538 3539 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3540 // type. This ensures they get CSE'd. 3541 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3542 SDValue Vec; 3543 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3544 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3545} 3546 3547 3548/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3549/// that point to V2 points to its first element. 3550static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3551 EVT VT = SVOp->getValueType(0); 3552 unsigned NumElems = VT.getVectorNumElements(); 3553 3554 bool Changed = false; 3555 SmallVector<int, 8> MaskVec; 3556 SVOp->getMask(MaskVec); 3557 3558 for (unsigned i = 0; i != NumElems; ++i) { 3559 if (MaskVec[i] > (int)NumElems) { 3560 MaskVec[i] = NumElems; 3561 Changed = true; 3562 } 3563 } 3564 if (Changed) 3565 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3566 SVOp->getOperand(1), &MaskVec[0]); 3567 return SDValue(SVOp, 0); 3568} 3569 3570/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3571/// operation of specified width. 3572static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3573 SDValue V2) { 3574 unsigned NumElems = VT.getVectorNumElements(); 3575 SmallVector<int, 8> Mask; 3576 Mask.push_back(NumElems); 3577 for (unsigned i = 1; i != NumElems; ++i) 3578 Mask.push_back(i); 3579 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3580} 3581 3582/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3583static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3584 SDValue V2) { 3585 unsigned NumElems = VT.getVectorNumElements(); 3586 SmallVector<int, 8> Mask; 3587 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3588 Mask.push_back(i); 3589 Mask.push_back(i + NumElems); 3590 } 3591 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3592} 3593 3594/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3595static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3596 SDValue V2) { 3597 unsigned NumElems = VT.getVectorNumElements(); 3598 unsigned Half = NumElems/2; 3599 SmallVector<int, 8> Mask; 3600 for (unsigned i = 0; i != Half; ++i) { 3601 Mask.push_back(i + Half); 3602 Mask.push_back(i + NumElems + Half); 3603 } 3604 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3605} 3606 3607/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32. 3608static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 3609 EVT PVT = MVT::v4f32; 3610 EVT VT = SV->getValueType(0); 3611 DebugLoc dl = SV->getDebugLoc(); 3612 SDValue V1 = SV->getOperand(0); 3613 int NumElems = VT.getVectorNumElements(); 3614 int EltNo = SV->getSplatIndex(); 3615 3616 // unpack elements to the correct location 3617 while (NumElems > 4) { 3618 if (EltNo < NumElems/2) { 3619 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3620 } else { 3621 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3622 EltNo -= NumElems/2; 3623 } 3624 NumElems >>= 1; 3625 } 3626 3627 // Perform the splat. 3628 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3629 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1); 3630 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3631 return DAG.getNode(ISD::BITCAST, dl, VT, V1); 3632} 3633 3634/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3635/// vector of zero or undef vector. This produces a shuffle where the low 3636/// element of V2 is swizzled into the zero/undef vector, landing at element 3637/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3638static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3639 bool isZero, bool HasSSE2, 3640 SelectionDAG &DAG) { 3641 EVT VT = V2.getValueType(); 3642 SDValue V1 = isZero 3643 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3644 unsigned NumElems = VT.getVectorNumElements(); 3645 SmallVector<int, 16> MaskVec; 3646 for (unsigned i = 0; i != NumElems; ++i) 3647 // If this is the insertion idx, put the low elt of V2 here. 3648 MaskVec.push_back(i == Idx ? NumElems : i); 3649 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3650} 3651 3652/// getShuffleScalarElt - Returns the scalar element that will make up the ith 3653/// element of the result of the vector shuffle. 3654SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 3655 unsigned Depth) { 3656 if (Depth == 6) 3657 return SDValue(); // Limit search depth. 3658 3659 SDValue V = SDValue(N, 0); 3660 EVT VT = V.getValueType(); 3661 unsigned Opcode = V.getOpcode(); 3662 3663 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 3664 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 3665 Index = SV->getMaskElt(Index); 3666 3667 if (Index < 0) 3668 return DAG.getUNDEF(VT.getVectorElementType()); 3669 3670 int NumElems = VT.getVectorNumElements(); 3671 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 3672 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 3673 } 3674 3675 // Recurse into target specific vector shuffles to find scalars. 3676 if (isTargetShuffle(Opcode)) { 3677 int NumElems = VT.getVectorNumElements(); 3678 SmallVector<unsigned, 16> ShuffleMask; 3679 SDValue ImmN; 3680 3681 switch(Opcode) { 3682 case X86ISD::SHUFPS: 3683 case X86ISD::SHUFPD: 3684 ImmN = N->getOperand(N->getNumOperands()-1); 3685 DecodeSHUFPSMask(NumElems, 3686 cast<ConstantSDNode>(ImmN)->getZExtValue(), 3687 ShuffleMask); 3688 break; 3689 case X86ISD::PUNPCKHBW: 3690 case X86ISD::PUNPCKHWD: 3691 case X86ISD::PUNPCKHDQ: 3692 case X86ISD::PUNPCKHQDQ: 3693 DecodePUNPCKHMask(NumElems, ShuffleMask); 3694 break; 3695 case X86ISD::UNPCKHPS: 3696 case X86ISD::UNPCKHPD: 3697 DecodeUNPCKHPMask(NumElems, ShuffleMask); 3698 break; 3699 case X86ISD::PUNPCKLBW: 3700 case X86ISD::PUNPCKLWD: 3701 case X86ISD::PUNPCKLDQ: 3702 case X86ISD::PUNPCKLQDQ: 3703 DecodePUNPCKLMask(NumElems, ShuffleMask); 3704 break; 3705 case X86ISD::UNPCKLPS: 3706 case X86ISD::UNPCKLPD: 3707 DecodeUNPCKLPMask(NumElems, ShuffleMask); 3708 break; 3709 case X86ISD::MOVHLPS: 3710 DecodeMOVHLPSMask(NumElems, ShuffleMask); 3711 break; 3712 case X86ISD::MOVLHPS: 3713 DecodeMOVLHPSMask(NumElems, ShuffleMask); 3714 break; 3715 case X86ISD::PSHUFD: 3716 ImmN = N->getOperand(N->getNumOperands()-1); 3717 DecodePSHUFMask(NumElems, 3718 cast<ConstantSDNode>(ImmN)->getZExtValue(), 3719 ShuffleMask); 3720 break; 3721 case X86ISD::PSHUFHW: 3722 ImmN = N->getOperand(N->getNumOperands()-1); 3723 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 3724 ShuffleMask); 3725 break; 3726 case X86ISD::PSHUFLW: 3727 ImmN = N->getOperand(N->getNumOperands()-1); 3728 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 3729 ShuffleMask); 3730 break; 3731 case X86ISD::MOVSS: 3732 case X86ISD::MOVSD: { 3733 // The index 0 always comes from the first element of the second source, 3734 // this is why MOVSS and MOVSD are used in the first place. The other 3735 // elements come from the other positions of the first source vector. 3736 unsigned OpNum = (Index == 0) ? 1 : 0; 3737 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 3738 Depth+1); 3739 } 3740 default: 3741 assert("not implemented for target shuffle node"); 3742 return SDValue(); 3743 } 3744 3745 Index = ShuffleMask[Index]; 3746 if (Index < 0) 3747 return DAG.getUNDEF(VT.getVectorElementType()); 3748 3749 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 3750 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 3751 Depth+1); 3752 } 3753 3754 // Actual nodes that may contain scalar elements 3755 if (Opcode == ISD::BITCAST) { 3756 V = V.getOperand(0); 3757 EVT SrcVT = V.getValueType(); 3758 unsigned NumElems = VT.getVectorNumElements(); 3759 3760 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 3761 return SDValue(); 3762 } 3763 3764 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 3765 return (Index == 0) ? V.getOperand(0) 3766 : DAG.getUNDEF(VT.getVectorElementType()); 3767 3768 if (V.getOpcode() == ISD::BUILD_VECTOR) 3769 return V.getOperand(Index); 3770 3771 return SDValue(); 3772} 3773 3774/// getNumOfConsecutiveZeros - Return the number of elements of a vector 3775/// shuffle operation which come from a consecutively from a zero. The 3776/// search can start in two diferent directions, from left or right. 3777static 3778unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 3779 bool ZerosFromLeft, SelectionDAG &DAG) { 3780 int i = 0; 3781 3782 while (i < NumElems) { 3783 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 3784 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 3785 if (!(Elt.getNode() && 3786 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 3787 break; 3788 ++i; 3789 } 3790 3791 return i; 3792} 3793 3794/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 3795/// MaskE correspond consecutively to elements from one of the vector operands, 3796/// starting from its index OpIdx. Also tell OpNum which source vector operand. 3797static 3798bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 3799 int OpIdx, int NumElems, unsigned &OpNum) { 3800 bool SeenV1 = false; 3801 bool SeenV2 = false; 3802 3803 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 3804 int Idx = SVOp->getMaskElt(i); 3805 // Ignore undef indicies 3806 if (Idx < 0) 3807 continue; 3808 3809 if (Idx < NumElems) 3810 SeenV1 = true; 3811 else 3812 SeenV2 = true; 3813 3814 // Only accept consecutive elements from the same vector 3815 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 3816 return false; 3817 } 3818 3819 OpNum = SeenV1 ? 0 : 1; 3820 return true; 3821} 3822 3823/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 3824/// logical left shift of a vector. 3825static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3826 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3827 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3828 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3829 false /* check zeros from right */, DAG); 3830 unsigned OpSrc; 3831 3832 if (!NumZeros) 3833 return false; 3834 3835 // Considering the elements in the mask that are not consecutive zeros, 3836 // check if they consecutively come from only one of the source vectors. 3837 // 3838 // V1 = {X, A, B, C} 0 3839 // \ \ \ / 3840 // vector_shuffle V1, V2 <1, 2, 3, X> 3841 // 3842 if (!isShuffleMaskConsecutive(SVOp, 3843 0, // Mask Start Index 3844 NumElems-NumZeros-1, // Mask End Index 3845 NumZeros, // Where to start looking in the src vector 3846 NumElems, // Number of elements in vector 3847 OpSrc)) // Which source operand ? 3848 return false; 3849 3850 isLeft = false; 3851 ShAmt = NumZeros; 3852 ShVal = SVOp->getOperand(OpSrc); 3853 return true; 3854} 3855 3856/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 3857/// logical left shift of a vector. 3858static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3859 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3860 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3861 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3862 true /* check zeros from left */, DAG); 3863 unsigned OpSrc; 3864 3865 if (!NumZeros) 3866 return false; 3867 3868 // Considering the elements in the mask that are not consecutive zeros, 3869 // check if they consecutively come from only one of the source vectors. 3870 // 3871 // 0 { A, B, X, X } = V2 3872 // / \ / / 3873 // vector_shuffle V1, V2 <X, X, 4, 5> 3874 // 3875 if (!isShuffleMaskConsecutive(SVOp, 3876 NumZeros, // Mask Start Index 3877 NumElems-1, // Mask End Index 3878 0, // Where to start looking in the src vector 3879 NumElems, // Number of elements in vector 3880 OpSrc)) // Which source operand ? 3881 return false; 3882 3883 isLeft = true; 3884 ShAmt = NumZeros; 3885 ShVal = SVOp->getOperand(OpSrc); 3886 return true; 3887} 3888 3889/// isVectorShift - Returns true if the shuffle can be implemented as a 3890/// logical left or right shift of a vector. 3891static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3892 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3893 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 3894 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 3895 return true; 3896 3897 return false; 3898} 3899 3900/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3901/// 3902static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3903 unsigned NumNonZero, unsigned NumZero, 3904 SelectionDAG &DAG, 3905 const TargetLowering &TLI) { 3906 if (NumNonZero > 8) 3907 return SDValue(); 3908 3909 DebugLoc dl = Op.getDebugLoc(); 3910 SDValue V(0, 0); 3911 bool First = true; 3912 for (unsigned i = 0; i < 16; ++i) { 3913 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3914 if (ThisIsNonZero && First) { 3915 if (NumZero) 3916 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3917 else 3918 V = DAG.getUNDEF(MVT::v8i16); 3919 First = false; 3920 } 3921 3922 if ((i & 1) != 0) { 3923 SDValue ThisElt(0, 0), LastElt(0, 0); 3924 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3925 if (LastIsNonZero) { 3926 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3927 MVT::i16, Op.getOperand(i-1)); 3928 } 3929 if (ThisIsNonZero) { 3930 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3931 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3932 ThisElt, DAG.getConstant(8, MVT::i8)); 3933 if (LastIsNonZero) 3934 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3935 } else 3936 ThisElt = LastElt; 3937 3938 if (ThisElt.getNode()) 3939 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3940 DAG.getIntPtrConstant(i/2)); 3941 } 3942 } 3943 3944 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 3945} 3946 3947/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3948/// 3949static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3950 unsigned NumNonZero, unsigned NumZero, 3951 SelectionDAG &DAG, 3952 const TargetLowering &TLI) { 3953 if (NumNonZero > 4) 3954 return SDValue(); 3955 3956 DebugLoc dl = Op.getDebugLoc(); 3957 SDValue V(0, 0); 3958 bool First = true; 3959 for (unsigned i = 0; i < 8; ++i) { 3960 bool isNonZero = (NonZeros & (1 << i)) != 0; 3961 if (isNonZero) { 3962 if (First) { 3963 if (NumZero) 3964 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3965 else 3966 V = DAG.getUNDEF(MVT::v8i16); 3967 First = false; 3968 } 3969 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3970 MVT::v8i16, V, Op.getOperand(i), 3971 DAG.getIntPtrConstant(i)); 3972 } 3973 } 3974 3975 return V; 3976} 3977 3978/// getVShift - Return a vector logical shift node. 3979/// 3980static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3981 unsigned NumBits, SelectionDAG &DAG, 3982 const TargetLowering &TLI, DebugLoc dl) { 3983 EVT ShVT = MVT::v2i64; 3984 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3985 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 3986 return DAG.getNode(ISD::BITCAST, dl, VT, 3987 DAG.getNode(Opc, dl, ShVT, SrcOp, 3988 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3989} 3990 3991SDValue 3992X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3993 SelectionDAG &DAG) const { 3994 3995 // Check if the scalar load can be widened into a vector load. And if 3996 // the address is "base + cst" see if the cst can be "absorbed" into 3997 // the shuffle mask. 3998 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3999 SDValue Ptr = LD->getBasePtr(); 4000 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4001 return SDValue(); 4002 EVT PVT = LD->getValueType(0); 4003 if (PVT != MVT::i32 && PVT != MVT::f32) 4004 return SDValue(); 4005 4006 int FI = -1; 4007 int64_t Offset = 0; 4008 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4009 FI = FINode->getIndex(); 4010 Offset = 0; 4011 } else if (Ptr.getOpcode() == ISD::ADD && 4012 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4013 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4014 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4015 Offset = Ptr.getConstantOperandVal(1); 4016 Ptr = Ptr.getOperand(0); 4017 } else { 4018 return SDValue(); 4019 } 4020 4021 SDValue Chain = LD->getChain(); 4022 // Make sure the stack object alignment is at least 16. 4023 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4024 if (DAG.InferPtrAlignment(Ptr) < 16) { 4025 if (MFI->isFixedObjectIndex(FI)) { 4026 // Can't change the alignment. FIXME: It's possible to compute 4027 // the exact stack offset and reference FI + adjust offset instead. 4028 // If someone *really* cares about this. That's the way to implement it. 4029 return SDValue(); 4030 } else { 4031 MFI->setObjectAlignment(FI, 16); 4032 } 4033 } 4034 4035 // (Offset % 16) must be multiple of 4. Then address is then 4036 // Ptr + (Offset & ~15). 4037 if (Offset < 0) 4038 return SDValue(); 4039 if ((Offset % 16) & 3) 4040 return SDValue(); 4041 int64_t StartOffset = Offset & ~15; 4042 if (StartOffset) 4043 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4044 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4045 4046 int EltNo = (Offset - StartOffset) >> 2; 4047 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 4048 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 4049 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr, 4050 LD->getPointerInfo().getWithOffset(StartOffset), 4051 false, false, 0); 4052 // Canonicalize it to a v4i32 shuffle. 4053 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); 4054 return DAG.getNode(ISD::BITCAST, dl, VT, 4055 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 4056 DAG.getUNDEF(MVT::v4i32),&Mask[0])); 4057 } 4058 4059 return SDValue(); 4060} 4061 4062/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4063/// vector of type 'VT', see if the elements can be replaced by a single large 4064/// load which has the same value as a build_vector whose operands are 'elts'. 4065/// 4066/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4067/// 4068/// FIXME: we'd also like to handle the case where the last elements are zero 4069/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4070/// There's even a handy isZeroNode for that purpose. 4071static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4072 DebugLoc &DL, SelectionDAG &DAG) { 4073 EVT EltVT = VT.getVectorElementType(); 4074 unsigned NumElems = Elts.size(); 4075 4076 LoadSDNode *LDBase = NULL; 4077 unsigned LastLoadedElt = -1U; 4078 4079 // For each element in the initializer, see if we've found a load or an undef. 4080 // If we don't find an initial load element, or later load elements are 4081 // non-consecutive, bail out. 4082 for (unsigned i = 0; i < NumElems; ++i) { 4083 SDValue Elt = Elts[i]; 4084 4085 if (!Elt.getNode() || 4086 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4087 return SDValue(); 4088 if (!LDBase) { 4089 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4090 return SDValue(); 4091 LDBase = cast<LoadSDNode>(Elt.getNode()); 4092 LastLoadedElt = i; 4093 continue; 4094 } 4095 if (Elt.getOpcode() == ISD::UNDEF) 4096 continue; 4097 4098 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4099 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4100 return SDValue(); 4101 LastLoadedElt = i; 4102 } 4103 4104 // If we have found an entire vector of loads and undefs, then return a large 4105 // load of the entire vector width starting at the base pointer. If we found 4106 // consecutive loads for the low half, generate a vzext_load node. 4107 if (LastLoadedElt == NumElems - 1) { 4108 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4109 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4110 LDBase->getPointerInfo(), 4111 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4112 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4113 LDBase->getPointerInfo(), 4114 LDBase->isVolatile(), LDBase->isNonTemporal(), 4115 LDBase->getAlignment()); 4116 } else if (NumElems == 4 && LastLoadedElt == 1) { 4117 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4118 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4119 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, 4120 Ops, 2, MVT::i32, 4121 LDBase->getMemOperand()); 4122 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4123 } 4124 return SDValue(); 4125} 4126 4127SDValue 4128X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4129 DebugLoc dl = Op.getDebugLoc(); 4130 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1. 4131 // All one's are handled with pcmpeqd. In AVX, zero's are handled with 4132 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd 4133 // is present, so AllOnes is ignored. 4134 if (ISD::isBuildVectorAllZeros(Op.getNode()) || 4135 (Op.getValueType().getSizeInBits() != 256 && 4136 ISD::isBuildVectorAllOnes(Op.getNode()))) { 4137 // Canonicalize this to <4 x i32> (SSE) to 4138 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 4139 // eliminated on x86-32 hosts. 4140 if (Op.getValueType() == MVT::v4i32) 4141 return Op; 4142 4143 if (ISD::isBuildVectorAllOnes(Op.getNode())) 4144 return getOnesVector(Op.getValueType(), DAG, dl); 4145 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4146 } 4147 4148 EVT VT = Op.getValueType(); 4149 EVT ExtVT = VT.getVectorElementType(); 4150 unsigned EVTBits = ExtVT.getSizeInBits(); 4151 4152 unsigned NumElems = Op.getNumOperands(); 4153 unsigned NumZero = 0; 4154 unsigned NumNonZero = 0; 4155 unsigned NonZeros = 0; 4156 bool IsAllConstants = true; 4157 SmallSet<SDValue, 8> Values; 4158 for (unsigned i = 0; i < NumElems; ++i) { 4159 SDValue Elt = Op.getOperand(i); 4160 if (Elt.getOpcode() == ISD::UNDEF) 4161 continue; 4162 Values.insert(Elt); 4163 if (Elt.getOpcode() != ISD::Constant && 4164 Elt.getOpcode() != ISD::ConstantFP) 4165 IsAllConstants = false; 4166 if (X86::isZeroNode(Elt)) 4167 NumZero++; 4168 else { 4169 NonZeros |= (1 << i); 4170 NumNonZero++; 4171 } 4172 } 4173 4174 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4175 if (NumNonZero == 0) 4176 return DAG.getUNDEF(VT); 4177 4178 // Special case for single non-zero, non-undef, element. 4179 if (NumNonZero == 1) { 4180 unsigned Idx = CountTrailingZeros_32(NonZeros); 4181 SDValue Item = Op.getOperand(Idx); 4182 4183 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4184 // the value are obviously zero, truncate the value to i32 and do the 4185 // insertion that way. Only do this if the value is non-constant or if the 4186 // value is a constant being inserted into element 0. It is cheaper to do 4187 // a constant pool load than it is to do a movd + shuffle. 4188 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4189 (!IsAllConstants || Idx == 0)) { 4190 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4191 // Handle SSE only. 4192 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 4193 EVT VecVT = MVT::v4i32; 4194 unsigned VecElts = 4; 4195 4196 // Truncate the value (which may itself be a constant) to i32, and 4197 // convert it to a vector with movd (S2V+shuffle to zero extend). 4198 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4199 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4200 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4201 Subtarget->hasSSE2(), DAG); 4202 4203 // Now we have our 32-bit value zero extended in the low element of 4204 // a vector. If Idx != 0, swizzle it into place. 4205 if (Idx != 0) { 4206 SmallVector<int, 4> Mask; 4207 Mask.push_back(Idx); 4208 for (unsigned i = 1; i != VecElts; ++i) 4209 Mask.push_back(i); 4210 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4211 DAG.getUNDEF(Item.getValueType()), 4212 &Mask[0]); 4213 } 4214 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 4215 } 4216 } 4217 4218 // If we have a constant or non-constant insertion into the low element of 4219 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4220 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4221 // depending on what the source datatype is. 4222 if (Idx == 0) { 4223 if (NumZero == 0) { 4224 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4225 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4226 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4227 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4228 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4229 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4230 DAG); 4231 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4232 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4233 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 4234 EVT MiddleVT = MVT::v4i32; 4235 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4236 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4237 Subtarget->hasSSE2(), DAG); 4238 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 4239 } 4240 } 4241 4242 // Is it a vector logical left shift? 4243 if (NumElems == 2 && Idx == 1 && 4244 X86::isZeroNode(Op.getOperand(0)) && 4245 !X86::isZeroNode(Op.getOperand(1))) { 4246 unsigned NumBits = VT.getSizeInBits(); 4247 return getVShift(true, VT, 4248 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4249 VT, Op.getOperand(1)), 4250 NumBits/2, DAG, *this, dl); 4251 } 4252 4253 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4254 return SDValue(); 4255 4256 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4257 // is a non-constant being inserted into an element other than the low one, 4258 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4259 // movd/movss) to move this into the low element, then shuffle it into 4260 // place. 4261 if (EVTBits == 32) { 4262 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4263 4264 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4265 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4266 Subtarget->hasSSE2(), DAG); 4267 SmallVector<int, 8> MaskVec; 4268 for (unsigned i = 0; i < NumElems; i++) 4269 MaskVec.push_back(i == Idx ? 0 : 1); 4270 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4271 } 4272 } 4273 4274 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4275 if (Values.size() == 1) { 4276 if (EVTBits == 32) { 4277 // Instead of a shuffle like this: 4278 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4279 // Check if it's possible to issue this instead. 4280 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4281 unsigned Idx = CountTrailingZeros_32(NonZeros); 4282 SDValue Item = Op.getOperand(Idx); 4283 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4284 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4285 } 4286 return SDValue(); 4287 } 4288 4289 // A vector full of immediates; various special cases are already 4290 // handled, so this is best done with a single constant-pool load. 4291 if (IsAllConstants) 4292 return SDValue(); 4293 4294 // Let legalizer expand 2-wide build_vectors. 4295 if (EVTBits == 64) { 4296 if (NumNonZero == 1) { 4297 // One half is zero or undef. 4298 unsigned Idx = CountTrailingZeros_32(NonZeros); 4299 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4300 Op.getOperand(Idx)); 4301 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4302 Subtarget->hasSSE2(), DAG); 4303 } 4304 return SDValue(); 4305 } 4306 4307 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4308 if (EVTBits == 8 && NumElems == 16) { 4309 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4310 *this); 4311 if (V.getNode()) return V; 4312 } 4313 4314 if (EVTBits == 16 && NumElems == 8) { 4315 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4316 *this); 4317 if (V.getNode()) return V; 4318 } 4319 4320 // If element VT is == 32 bits, turn it into a number of shuffles. 4321 SmallVector<SDValue, 8> V; 4322 V.resize(NumElems); 4323 if (NumElems == 4 && NumZero > 0) { 4324 for (unsigned i = 0; i < 4; ++i) { 4325 bool isZero = !(NonZeros & (1 << i)); 4326 if (isZero) 4327 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4328 else 4329 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4330 } 4331 4332 for (unsigned i = 0; i < 2; ++i) { 4333 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4334 default: break; 4335 case 0: 4336 V[i] = V[i*2]; // Must be a zero vector. 4337 break; 4338 case 1: 4339 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4340 break; 4341 case 2: 4342 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4343 break; 4344 case 3: 4345 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4346 break; 4347 } 4348 } 4349 4350 SmallVector<int, 8> MaskVec; 4351 bool Reverse = (NonZeros & 0x3) == 2; 4352 for (unsigned i = 0; i < 2; ++i) 4353 MaskVec.push_back(Reverse ? 1-i : i); 4354 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4355 for (unsigned i = 0; i < 2; ++i) 4356 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4357 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4358 } 4359 4360 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4361 // Check for a build vector of consecutive loads. 4362 for (unsigned i = 0; i < NumElems; ++i) 4363 V[i] = Op.getOperand(i); 4364 4365 // Check for elements which are consecutive loads. 4366 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4367 if (LD.getNode()) 4368 return LD; 4369 4370 // For SSE 4.1, use insertps to put the high elements into the low element. 4371 if (getSubtarget()->hasSSE41()) { 4372 SDValue Result; 4373 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4374 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4375 else 4376 Result = DAG.getUNDEF(VT); 4377 4378 for (unsigned i = 1; i < NumElems; ++i) { 4379 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4380 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4381 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4382 } 4383 return Result; 4384 } 4385 4386 // Otherwise, expand into a number of unpckl*, start by extending each of 4387 // our (non-undef) elements to the full vector width with the element in the 4388 // bottom slot of the vector (which generates no code for SSE). 4389 for (unsigned i = 0; i < NumElems; ++i) { 4390 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4391 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4392 else 4393 V[i] = DAG.getUNDEF(VT); 4394 } 4395 4396 // Next, we iteratively mix elements, e.g. for v4f32: 4397 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 4398 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 4399 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 4400 unsigned EltStride = NumElems >> 1; 4401 while (EltStride != 0) { 4402 for (unsigned i = 0; i < EltStride; ++i) { 4403 // If V[i+EltStride] is undef and this is the first round of mixing, 4404 // then it is safe to just drop this shuffle: V[i] is already in the 4405 // right place, the one element (since it's the first round) being 4406 // inserted as undef can be dropped. This isn't safe for successive 4407 // rounds because they will permute elements within both vectors. 4408 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 4409 EltStride == NumElems/2) 4410 continue; 4411 4412 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 4413 } 4414 EltStride >>= 1; 4415 } 4416 return V[0]; 4417 } 4418 return SDValue(); 4419} 4420 4421SDValue 4422X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 4423 // We support concatenate two MMX registers and place them in a MMX 4424 // register. This is better than doing a stack convert. 4425 DebugLoc dl = Op.getDebugLoc(); 4426 EVT ResVT = Op.getValueType(); 4427 assert(Op.getNumOperands() == 2); 4428 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 4429 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 4430 int Mask[2]; 4431 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 4432 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4433 InVec = Op.getOperand(1); 4434 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4435 unsigned NumElts = ResVT.getVectorNumElements(); 4436 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 4437 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 4438 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 4439 } else { 4440 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 4441 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4442 Mask[0] = 0; Mask[1] = 2; 4443 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 4444 } 4445 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 4446} 4447 4448// v8i16 shuffles - Prefer shuffles in the following order: 4449// 1. [all] pshuflw, pshufhw, optional move 4450// 2. [ssse3] 1 x pshufb 4451// 3. [ssse3] 2 x pshufb + 1 x por 4452// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4453SDValue 4454X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 4455 SelectionDAG &DAG) const { 4456 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4457 SDValue V1 = SVOp->getOperand(0); 4458 SDValue V2 = SVOp->getOperand(1); 4459 DebugLoc dl = SVOp->getDebugLoc(); 4460 SmallVector<int, 8> MaskVals; 4461 4462 // Determine if more than 1 of the words in each of the low and high quadwords 4463 // of the result come from the same quadword of one of the two inputs. Undef 4464 // mask values count as coming from any quadword, for better codegen. 4465 SmallVector<unsigned, 4> LoQuad(4); 4466 SmallVector<unsigned, 4> HiQuad(4); 4467 BitVector InputQuads(4); 4468 for (unsigned i = 0; i < 8; ++i) { 4469 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4470 int EltIdx = SVOp->getMaskElt(i); 4471 MaskVals.push_back(EltIdx); 4472 if (EltIdx < 0) { 4473 ++Quad[0]; 4474 ++Quad[1]; 4475 ++Quad[2]; 4476 ++Quad[3]; 4477 continue; 4478 } 4479 ++Quad[EltIdx / 4]; 4480 InputQuads.set(EltIdx / 4); 4481 } 4482 4483 int BestLoQuad = -1; 4484 unsigned MaxQuad = 1; 4485 for (unsigned i = 0; i < 4; ++i) { 4486 if (LoQuad[i] > MaxQuad) { 4487 BestLoQuad = i; 4488 MaxQuad = LoQuad[i]; 4489 } 4490 } 4491 4492 int BestHiQuad = -1; 4493 MaxQuad = 1; 4494 for (unsigned i = 0; i < 4; ++i) { 4495 if (HiQuad[i] > MaxQuad) { 4496 BestHiQuad = i; 4497 MaxQuad = HiQuad[i]; 4498 } 4499 } 4500 4501 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4502 // of the two input vectors, shuffle them into one input vector so only a 4503 // single pshufb instruction is necessary. If There are more than 2 input 4504 // quads, disable the next transformation since it does not help SSSE3. 4505 bool V1Used = InputQuads[0] || InputQuads[1]; 4506 bool V2Used = InputQuads[2] || InputQuads[3]; 4507 if (Subtarget->hasSSSE3()) { 4508 if (InputQuads.count() == 2 && V1Used && V2Used) { 4509 BestLoQuad = InputQuads.find_first(); 4510 BestHiQuad = InputQuads.find_next(BestLoQuad); 4511 } 4512 if (InputQuads.count() > 2) { 4513 BestLoQuad = -1; 4514 BestHiQuad = -1; 4515 } 4516 } 4517 4518 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4519 // the shuffle mask. If a quad is scored as -1, that means that it contains 4520 // words from all 4 input quadwords. 4521 SDValue NewV; 4522 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4523 SmallVector<int, 8> MaskV; 4524 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4525 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4526 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4527 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 4528 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 4529 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 4530 4531 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4532 // source words for the shuffle, to aid later transformations. 4533 bool AllWordsInNewV = true; 4534 bool InOrder[2] = { true, true }; 4535 for (unsigned i = 0; i != 8; ++i) { 4536 int idx = MaskVals[i]; 4537 if (idx != (int)i) 4538 InOrder[i/4] = false; 4539 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4540 continue; 4541 AllWordsInNewV = false; 4542 break; 4543 } 4544 4545 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4546 if (AllWordsInNewV) { 4547 for (int i = 0; i != 8; ++i) { 4548 int idx = MaskVals[i]; 4549 if (idx < 0) 4550 continue; 4551 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4552 if ((idx != i) && idx < 4) 4553 pshufhw = false; 4554 if ((idx != i) && idx > 3) 4555 pshuflw = false; 4556 } 4557 V1 = NewV; 4558 V2Used = false; 4559 BestLoQuad = 0; 4560 BestHiQuad = 1; 4561 } 4562 4563 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4564 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4565 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4566 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 4567 unsigned TargetMask = 0; 4568 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4569 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4570 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 4571 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 4572 V1 = NewV.getOperand(0); 4573 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 4574 } 4575 } 4576 4577 // If we have SSSE3, and all words of the result are from 1 input vector, 4578 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4579 // is present, fall back to case 4. 4580 if (Subtarget->hasSSSE3()) { 4581 SmallVector<SDValue,16> pshufbMask; 4582 4583 // If we have elements from both input vectors, set the high bit of the 4584 // shuffle mask element to zero out elements that come from V2 in the V1 4585 // mask, and elements that come from V1 in the V2 mask, so that the two 4586 // results can be OR'd together. 4587 bool TwoInputs = V1Used && V2Used; 4588 for (unsigned i = 0; i != 8; ++i) { 4589 int EltIdx = MaskVals[i] * 2; 4590 if (TwoInputs && (EltIdx >= 16)) { 4591 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4592 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4593 continue; 4594 } 4595 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4596 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4597 } 4598 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 4599 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4600 DAG.getNode(ISD::BUILD_VECTOR, dl, 4601 MVT::v16i8, &pshufbMask[0], 16)); 4602 if (!TwoInputs) 4603 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 4604 4605 // Calculate the shuffle mask for the second input, shuffle it, and 4606 // OR it with the first shuffled input. 4607 pshufbMask.clear(); 4608 for (unsigned i = 0; i != 8; ++i) { 4609 int EltIdx = MaskVals[i] * 2; 4610 if (EltIdx < 16) { 4611 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4612 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4613 continue; 4614 } 4615 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4616 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4617 } 4618 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 4619 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4620 DAG.getNode(ISD::BUILD_VECTOR, dl, 4621 MVT::v16i8, &pshufbMask[0], 16)); 4622 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4623 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 4624 } 4625 4626 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4627 // and update MaskVals with new element order. 4628 BitVector InOrder(8); 4629 if (BestLoQuad >= 0) { 4630 SmallVector<int, 8> MaskV; 4631 for (int i = 0; i != 4; ++i) { 4632 int idx = MaskVals[i]; 4633 if (idx < 0) { 4634 MaskV.push_back(-1); 4635 InOrder.set(i); 4636 } else if ((idx / 4) == BestLoQuad) { 4637 MaskV.push_back(idx & 3); 4638 InOrder.set(i); 4639 } else { 4640 MaskV.push_back(-1); 4641 } 4642 } 4643 for (unsigned i = 4; i != 8; ++i) 4644 MaskV.push_back(i); 4645 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4646 &MaskV[0]); 4647 4648 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4649 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 4650 NewV.getOperand(0), 4651 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 4652 DAG); 4653 } 4654 4655 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4656 // and update MaskVals with the new element order. 4657 if (BestHiQuad >= 0) { 4658 SmallVector<int, 8> MaskV; 4659 for (unsigned i = 0; i != 4; ++i) 4660 MaskV.push_back(i); 4661 for (unsigned i = 4; i != 8; ++i) { 4662 int idx = MaskVals[i]; 4663 if (idx < 0) { 4664 MaskV.push_back(-1); 4665 InOrder.set(i); 4666 } else if ((idx / 4) == BestHiQuad) { 4667 MaskV.push_back((idx & 3) + 4); 4668 InOrder.set(i); 4669 } else { 4670 MaskV.push_back(-1); 4671 } 4672 } 4673 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4674 &MaskV[0]); 4675 4676 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4677 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 4678 NewV.getOperand(0), 4679 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 4680 DAG); 4681 } 4682 4683 // In case BestHi & BestLo were both -1, which means each quadword has a word 4684 // from each of the four input quadwords, calculate the InOrder bitvector now 4685 // before falling through to the insert/extract cleanup. 4686 if (BestLoQuad == -1 && BestHiQuad == -1) { 4687 NewV = V1; 4688 for (int i = 0; i != 8; ++i) 4689 if (MaskVals[i] < 0 || MaskVals[i] == i) 4690 InOrder.set(i); 4691 } 4692 4693 // The other elements are put in the right place using pextrw and pinsrw. 4694 for (unsigned i = 0; i != 8; ++i) { 4695 if (InOrder[i]) 4696 continue; 4697 int EltIdx = MaskVals[i]; 4698 if (EltIdx < 0) 4699 continue; 4700 SDValue ExtOp = (EltIdx < 8) 4701 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4702 DAG.getIntPtrConstant(EltIdx)) 4703 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4704 DAG.getIntPtrConstant(EltIdx - 8)); 4705 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4706 DAG.getIntPtrConstant(i)); 4707 } 4708 return NewV; 4709} 4710 4711// v16i8 shuffles - Prefer shuffles in the following order: 4712// 1. [ssse3] 1 x pshufb 4713// 2. [ssse3] 2 x pshufb + 1 x por 4714// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4715static 4716SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4717 SelectionDAG &DAG, 4718 const X86TargetLowering &TLI) { 4719 SDValue V1 = SVOp->getOperand(0); 4720 SDValue V2 = SVOp->getOperand(1); 4721 DebugLoc dl = SVOp->getDebugLoc(); 4722 SmallVector<int, 16> MaskVals; 4723 SVOp->getMask(MaskVals); 4724 4725 // If we have SSSE3, case 1 is generated when all result bytes come from 4726 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4727 // present, fall back to case 3. 4728 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4729 bool V1Only = true; 4730 bool V2Only = true; 4731 for (unsigned i = 0; i < 16; ++i) { 4732 int EltIdx = MaskVals[i]; 4733 if (EltIdx < 0) 4734 continue; 4735 if (EltIdx < 16) 4736 V2Only = false; 4737 else 4738 V1Only = false; 4739 } 4740 4741 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4742 if (TLI.getSubtarget()->hasSSSE3()) { 4743 SmallVector<SDValue,16> pshufbMask; 4744 4745 // If all result elements are from one input vector, then only translate 4746 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4747 // 4748 // Otherwise, we have elements from both input vectors, and must zero out 4749 // elements that come from V2 in the first mask, and V1 in the second mask 4750 // so that we can OR them together. 4751 bool TwoInputs = !(V1Only || V2Only); 4752 for (unsigned i = 0; i != 16; ++i) { 4753 int EltIdx = MaskVals[i]; 4754 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4755 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4756 continue; 4757 } 4758 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4759 } 4760 // If all the elements are from V2, assign it to V1 and return after 4761 // building the first pshufb. 4762 if (V2Only) 4763 V1 = V2; 4764 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4765 DAG.getNode(ISD::BUILD_VECTOR, dl, 4766 MVT::v16i8, &pshufbMask[0], 16)); 4767 if (!TwoInputs) 4768 return V1; 4769 4770 // Calculate the shuffle mask for the second input, shuffle it, and 4771 // OR it with the first shuffled input. 4772 pshufbMask.clear(); 4773 for (unsigned i = 0; i != 16; ++i) { 4774 int EltIdx = MaskVals[i]; 4775 if (EltIdx < 16) { 4776 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4777 continue; 4778 } 4779 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4780 } 4781 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4782 DAG.getNode(ISD::BUILD_VECTOR, dl, 4783 MVT::v16i8, &pshufbMask[0], 16)); 4784 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4785 } 4786 4787 // No SSSE3 - Calculate in place words and then fix all out of place words 4788 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4789 // the 16 different words that comprise the two doublequadword input vectors. 4790 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 4791 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 4792 SDValue NewV = V2Only ? V2 : V1; 4793 for (int i = 0; i != 8; ++i) { 4794 int Elt0 = MaskVals[i*2]; 4795 int Elt1 = MaskVals[i*2+1]; 4796 4797 // This word of the result is all undef, skip it. 4798 if (Elt0 < 0 && Elt1 < 0) 4799 continue; 4800 4801 // This word of the result is already in the correct place, skip it. 4802 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4803 continue; 4804 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4805 continue; 4806 4807 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4808 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4809 SDValue InsElt; 4810 4811 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4812 // using a single extract together, load it and store it. 4813 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4814 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4815 DAG.getIntPtrConstant(Elt1 / 2)); 4816 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4817 DAG.getIntPtrConstant(i)); 4818 continue; 4819 } 4820 4821 // If Elt1 is defined, extract it from the appropriate source. If the 4822 // source byte is not also odd, shift the extracted word left 8 bits 4823 // otherwise clear the bottom 8 bits if we need to do an or. 4824 if (Elt1 >= 0) { 4825 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4826 DAG.getIntPtrConstant(Elt1 / 2)); 4827 if ((Elt1 & 1) == 0) 4828 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4829 DAG.getConstant(8, TLI.getShiftAmountTy())); 4830 else if (Elt0 >= 0) 4831 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4832 DAG.getConstant(0xFF00, MVT::i16)); 4833 } 4834 // If Elt0 is defined, extract it from the appropriate source. If the 4835 // source byte is not also even, shift the extracted word right 8 bits. If 4836 // Elt1 was also defined, OR the extracted values together before 4837 // inserting them in the result. 4838 if (Elt0 >= 0) { 4839 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4840 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4841 if ((Elt0 & 1) != 0) 4842 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4843 DAG.getConstant(8, TLI.getShiftAmountTy())); 4844 else if (Elt1 >= 0) 4845 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4846 DAG.getConstant(0x00FF, MVT::i16)); 4847 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4848 : InsElt0; 4849 } 4850 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4851 DAG.getIntPtrConstant(i)); 4852 } 4853 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 4854} 4855 4856/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4857/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 4858/// done when every pair / quad of shuffle mask elements point to elements in 4859/// the right sequence. e.g. 4860/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 4861static 4862SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4863 SelectionDAG &DAG, DebugLoc dl) { 4864 EVT VT = SVOp->getValueType(0); 4865 SDValue V1 = SVOp->getOperand(0); 4866 SDValue V2 = SVOp->getOperand(1); 4867 unsigned NumElems = VT.getVectorNumElements(); 4868 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4869 EVT NewVT; 4870 switch (VT.getSimpleVT().SimpleTy) { 4871 default: assert(false && "Unexpected!"); 4872 case MVT::v4f32: NewVT = MVT::v2f64; break; 4873 case MVT::v4i32: NewVT = MVT::v2i64; break; 4874 case MVT::v8i16: NewVT = MVT::v4i32; break; 4875 case MVT::v16i8: NewVT = MVT::v4i32; break; 4876 } 4877 4878 int Scale = NumElems / NewWidth; 4879 SmallVector<int, 8> MaskVec; 4880 for (unsigned i = 0; i < NumElems; i += Scale) { 4881 int StartIdx = -1; 4882 for (int j = 0; j < Scale; ++j) { 4883 int EltIdx = SVOp->getMaskElt(i+j); 4884 if (EltIdx < 0) 4885 continue; 4886 if (StartIdx == -1) 4887 StartIdx = EltIdx - (EltIdx % Scale); 4888 if (EltIdx != StartIdx + j) 4889 return SDValue(); 4890 } 4891 if (StartIdx == -1) 4892 MaskVec.push_back(-1); 4893 else 4894 MaskVec.push_back(StartIdx / Scale); 4895 } 4896 4897 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 4898 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 4899 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4900} 4901 4902/// getVZextMovL - Return a zero-extending vector move low node. 4903/// 4904static SDValue getVZextMovL(EVT VT, EVT OpVT, 4905 SDValue SrcOp, SelectionDAG &DAG, 4906 const X86Subtarget *Subtarget, DebugLoc dl) { 4907 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4908 LoadSDNode *LD = NULL; 4909 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4910 LD = dyn_cast<LoadSDNode>(SrcOp); 4911 if (!LD) { 4912 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4913 // instead. 4914 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4915 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 4916 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4917 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 4918 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4919 // PR2108 4920 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4921 return DAG.getNode(ISD::BITCAST, dl, VT, 4922 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4923 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4924 OpVT, 4925 SrcOp.getOperand(0) 4926 .getOperand(0)))); 4927 } 4928 } 4929 } 4930 4931 return DAG.getNode(ISD::BITCAST, dl, VT, 4932 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4933 DAG.getNode(ISD::BITCAST, dl, 4934 OpVT, SrcOp))); 4935} 4936 4937/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4938/// shuffles. 4939static SDValue 4940LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4941 SDValue V1 = SVOp->getOperand(0); 4942 SDValue V2 = SVOp->getOperand(1); 4943 DebugLoc dl = SVOp->getDebugLoc(); 4944 EVT VT = SVOp->getValueType(0); 4945 4946 SmallVector<std::pair<int, int>, 8> Locs; 4947 Locs.resize(4); 4948 SmallVector<int, 8> Mask1(4U, -1); 4949 SmallVector<int, 8> PermMask; 4950 SVOp->getMask(PermMask); 4951 4952 unsigned NumHi = 0; 4953 unsigned NumLo = 0; 4954 for (unsigned i = 0; i != 4; ++i) { 4955 int Idx = PermMask[i]; 4956 if (Idx < 0) { 4957 Locs[i] = std::make_pair(-1, -1); 4958 } else { 4959 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4960 if (Idx < 4) { 4961 Locs[i] = std::make_pair(0, NumLo); 4962 Mask1[NumLo] = Idx; 4963 NumLo++; 4964 } else { 4965 Locs[i] = std::make_pair(1, NumHi); 4966 if (2+NumHi < 4) 4967 Mask1[2+NumHi] = Idx; 4968 NumHi++; 4969 } 4970 } 4971 } 4972 4973 if (NumLo <= 2 && NumHi <= 2) { 4974 // If no more than two elements come from either vector. This can be 4975 // implemented with two shuffles. First shuffle gather the elements. 4976 // The second shuffle, which takes the first shuffle as both of its 4977 // vector operands, put the elements into the right order. 4978 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4979 4980 SmallVector<int, 8> Mask2(4U, -1); 4981 4982 for (unsigned i = 0; i != 4; ++i) { 4983 if (Locs[i].first == -1) 4984 continue; 4985 else { 4986 unsigned Idx = (i < 2) ? 0 : 4; 4987 Idx += Locs[i].first * 2 + Locs[i].second; 4988 Mask2[i] = Idx; 4989 } 4990 } 4991 4992 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4993 } else if (NumLo == 3 || NumHi == 3) { 4994 // Otherwise, we must have three elements from one vector, call it X, and 4995 // one element from the other, call it Y. First, use a shufps to build an 4996 // intermediate vector with the one element from Y and the element from X 4997 // that will be in the same half in the final destination (the indexes don't 4998 // matter). Then, use a shufps to build the final vector, taking the half 4999 // containing the element from Y from the intermediate, and the other half 5000 // from X. 5001 if (NumHi == 3) { 5002 // Normalize it so the 3 elements come from V1. 5003 CommuteVectorShuffleMask(PermMask, VT); 5004 std::swap(V1, V2); 5005 } 5006 5007 // Find the element from V2. 5008 unsigned HiIndex; 5009 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 5010 int Val = PermMask[HiIndex]; 5011 if (Val < 0) 5012 continue; 5013 if (Val >= 4) 5014 break; 5015 } 5016 5017 Mask1[0] = PermMask[HiIndex]; 5018 Mask1[1] = -1; 5019 Mask1[2] = PermMask[HiIndex^1]; 5020 Mask1[3] = -1; 5021 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5022 5023 if (HiIndex >= 2) { 5024 Mask1[0] = PermMask[0]; 5025 Mask1[1] = PermMask[1]; 5026 Mask1[2] = HiIndex & 1 ? 6 : 4; 5027 Mask1[3] = HiIndex & 1 ? 4 : 6; 5028 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5029 } else { 5030 Mask1[0] = HiIndex & 1 ? 2 : 0; 5031 Mask1[1] = HiIndex & 1 ? 0 : 2; 5032 Mask1[2] = PermMask[2]; 5033 Mask1[3] = PermMask[3]; 5034 if (Mask1[2] >= 0) 5035 Mask1[2] += 4; 5036 if (Mask1[3] >= 0) 5037 Mask1[3] += 4; 5038 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 5039 } 5040 } 5041 5042 // Break it into (shuffle shuffle_hi, shuffle_lo). 5043 Locs.clear(); 5044 SmallVector<int,8> LoMask(4U, -1); 5045 SmallVector<int,8> HiMask(4U, -1); 5046 5047 SmallVector<int,8> *MaskPtr = &LoMask; 5048 unsigned MaskIdx = 0; 5049 unsigned LoIdx = 0; 5050 unsigned HiIdx = 2; 5051 for (unsigned i = 0; i != 4; ++i) { 5052 if (i == 2) { 5053 MaskPtr = &HiMask; 5054 MaskIdx = 1; 5055 LoIdx = 0; 5056 HiIdx = 2; 5057 } 5058 int Idx = PermMask[i]; 5059 if (Idx < 0) { 5060 Locs[i] = std::make_pair(-1, -1); 5061 } else if (Idx < 4) { 5062 Locs[i] = std::make_pair(MaskIdx, LoIdx); 5063 (*MaskPtr)[LoIdx] = Idx; 5064 LoIdx++; 5065 } else { 5066 Locs[i] = std::make_pair(MaskIdx, HiIdx); 5067 (*MaskPtr)[HiIdx] = Idx; 5068 HiIdx++; 5069 } 5070 } 5071 5072 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 5073 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 5074 SmallVector<int, 8> MaskOps; 5075 for (unsigned i = 0; i != 4; ++i) { 5076 if (Locs[i].first == -1) { 5077 MaskOps.push_back(-1); 5078 } else { 5079 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5080 MaskOps.push_back(Idx); 5081 } 5082 } 5083 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5084} 5085 5086static bool MayFoldVectorLoad(SDValue V) { 5087 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5088 V = V.getOperand(0); 5089 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5090 V = V.getOperand(0); 5091 if (MayFoldLoad(V)) 5092 return true; 5093 return false; 5094} 5095 5096// FIXME: the version above should always be used. Since there's 5097// a bug where several vector shuffles can't be folded because the 5098// DAG is not updated during lowering and a node claims to have two 5099// uses while it only has one, use this version, and let isel match 5100// another instruction if the load really happens to have more than 5101// one use. Remove this version after this bug get fixed. 5102// rdar://8434668, PR8156 5103static bool RelaxedMayFoldVectorLoad(SDValue V) { 5104 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5105 V = V.getOperand(0); 5106 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5107 V = V.getOperand(0); 5108 if (ISD::isNormalLoad(V.getNode())) 5109 return true; 5110 return false; 5111} 5112 5113/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 5114/// a vector extract, and if both can be later optimized into a single load. 5115/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 5116/// here because otherwise a target specific shuffle node is going to be 5117/// emitted for this shuffle, and the optimization not done. 5118/// FIXME: This is probably not the best approach, but fix the problem 5119/// until the right path is decided. 5120static 5121bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 5122 const TargetLowering &TLI) { 5123 EVT VT = V.getValueType(); 5124 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 5125 5126 // Be sure that the vector shuffle is present in a pattern like this: 5127 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 5128 if (!V.hasOneUse()) 5129 return false; 5130 5131 SDNode *N = *V.getNode()->use_begin(); 5132 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 5133 return false; 5134 5135 SDValue EltNo = N->getOperand(1); 5136 if (!isa<ConstantSDNode>(EltNo)) 5137 return false; 5138 5139 // If the bit convert changed the number of elements, it is unsafe 5140 // to examine the mask. 5141 bool HasShuffleIntoBitcast = false; 5142 if (V.getOpcode() == ISD::BITCAST) { 5143 EVT SrcVT = V.getOperand(0).getValueType(); 5144 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 5145 return false; 5146 V = V.getOperand(0); 5147 HasShuffleIntoBitcast = true; 5148 } 5149 5150 // Select the input vector, guarding against out of range extract vector. 5151 unsigned NumElems = VT.getVectorNumElements(); 5152 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5153 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 5154 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 5155 5156 // Skip one more bit_convert if necessary 5157 if (V.getOpcode() == ISD::BITCAST) 5158 V = V.getOperand(0); 5159 5160 if (ISD::isNormalLoad(V.getNode())) { 5161 // Is the original load suitable? 5162 LoadSDNode *LN0 = cast<LoadSDNode>(V); 5163 5164 // FIXME: avoid the multi-use bug that is preventing lots of 5165 // of foldings to be detected, this is still wrong of course, but 5166 // give the temporary desired behavior, and if it happens that 5167 // the load has real more uses, during isel it will not fold, and 5168 // will generate poor code. 5169 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 5170 return false; 5171 5172 if (!HasShuffleIntoBitcast) 5173 return true; 5174 5175 // If there's a bitcast before the shuffle, check if the load type and 5176 // alignment is valid. 5177 unsigned Align = LN0->getAlignment(); 5178 unsigned NewAlign = 5179 TLI.getTargetData()->getABITypeAlignment( 5180 VT.getTypeForEVT(*DAG.getContext())); 5181 5182 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 5183 return false; 5184 } 5185 5186 return true; 5187} 5188 5189static 5190SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 5191 EVT VT = Op.getValueType(); 5192 5193 // Canonizalize to v2f64. 5194 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 5195 return DAG.getNode(ISD::BITCAST, dl, VT, 5196 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 5197 V1, DAG)); 5198} 5199 5200static 5201SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5202 bool HasSSE2) { 5203 SDValue V1 = Op.getOperand(0); 5204 SDValue V2 = Op.getOperand(1); 5205 EVT VT = Op.getValueType(); 5206 5207 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5208 5209 if (HasSSE2 && VT == MVT::v2f64) 5210 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5211 5212 // v4f32 or v4i32 5213 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5214} 5215 5216static 5217SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 5218 SDValue V1 = Op.getOperand(0); 5219 SDValue V2 = Op.getOperand(1); 5220 EVT VT = Op.getValueType(); 5221 5222 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 5223 "unsupported shuffle type"); 5224 5225 if (V2.getOpcode() == ISD::UNDEF) 5226 V2 = V1; 5227 5228 // v4i32 or v4f32 5229 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 5230} 5231 5232static 5233SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 5234 SDValue V1 = Op.getOperand(0); 5235 SDValue V2 = Op.getOperand(1); 5236 EVT VT = Op.getValueType(); 5237 unsigned NumElems = VT.getVectorNumElements(); 5238 5239 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 5240 // operand of these instructions is only memory, so check if there's a 5241 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 5242 // same masks. 5243 bool CanFoldLoad = false; 5244 5245 // Trivial case, when V2 comes from a load. 5246 if (MayFoldVectorLoad(V2)) 5247 CanFoldLoad = true; 5248 5249 // When V1 is a load, it can be folded later into a store in isel, example: 5250 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 5251 // turns into: 5252 // (MOVLPSmr addr:$src1, VR128:$src2) 5253 // So, recognize this potential and also use MOVLPS or MOVLPD 5254 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 5255 CanFoldLoad = true; 5256 5257 if (CanFoldLoad) { 5258 if (HasSSE2 && NumElems == 2) 5259 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 5260 5261 if (NumElems == 4) 5262 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 5263 } 5264 5265 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5266 // movl and movlp will both match v2i64, but v2i64 is never matched by 5267 // movl earlier because we make it strict to avoid messing with the movlp load 5268 // folding logic (see the code above getMOVLP call). Match it here then, 5269 // this is horrible, but will stay like this until we move all shuffle 5270 // matching to x86 specific nodes. Note that for the 1st condition all 5271 // types are matched with movsd. 5272 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) 5273 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5274 else if (HasSSE2) 5275 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5276 5277 5278 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 5279 5280 // Invert the operand order and use SHUFPS to match it. 5281 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, 5282 X86::getShuffleSHUFImmediate(SVOp), DAG); 5283} 5284 5285static inline unsigned getUNPCKLOpcode(EVT VT) { 5286 switch(VT.getSimpleVT().SimpleTy) { 5287 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 5288 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 5289 case MVT::v4f32: return X86ISD::UNPCKLPS; 5290 case MVT::v2f64: return X86ISD::UNPCKLPD; 5291 case MVT::v16i8: return X86ISD::PUNPCKLBW; 5292 case MVT::v8i16: return X86ISD::PUNPCKLWD; 5293 default: 5294 llvm_unreachable("Unknow type for unpckl"); 5295 } 5296 return 0; 5297} 5298 5299static inline unsigned getUNPCKHOpcode(EVT VT) { 5300 switch(VT.getSimpleVT().SimpleTy) { 5301 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 5302 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 5303 case MVT::v4f32: return X86ISD::UNPCKHPS; 5304 case MVT::v2f64: return X86ISD::UNPCKHPD; 5305 case MVT::v16i8: return X86ISD::PUNPCKHBW; 5306 case MVT::v8i16: return X86ISD::PUNPCKHWD; 5307 default: 5308 llvm_unreachable("Unknow type for unpckh"); 5309 } 5310 return 0; 5311} 5312 5313static 5314SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 5315 const TargetLowering &TLI, 5316 const X86Subtarget *Subtarget) { 5317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5318 EVT VT = Op.getValueType(); 5319 DebugLoc dl = Op.getDebugLoc(); 5320 SDValue V1 = Op.getOperand(0); 5321 SDValue V2 = Op.getOperand(1); 5322 5323 if (isZeroShuffle(SVOp)) 5324 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5325 5326 // Handle splat operations 5327 if (SVOp->isSplat()) { 5328 // Special case, this is the only place now where it's 5329 // allowed to return a vector_shuffle operation without 5330 // using a target specific node, because *hopefully* it 5331 // will be optimized away by the dag combiner. 5332 if (VT.getVectorNumElements() <= 4 && 5333 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 5334 return Op; 5335 5336 // Handle splats by matching through known masks 5337 if (VT.getVectorNumElements() <= 4) 5338 return SDValue(); 5339 5340 // Canonicalize all of the remaining to v4f32. 5341 return PromoteSplat(SVOp, DAG); 5342 } 5343 5344 // If the shuffle can be profitably rewritten as a narrower shuffle, then 5345 // do it! 5346 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 5347 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5348 if (NewOp.getNode()) 5349 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 5350 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 5351 // FIXME: Figure out a cleaner way to do this. 5352 // Try to make use of movq to zero out the top part. 5353 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 5354 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5355 if (NewOp.getNode()) { 5356 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 5357 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 5358 DAG, Subtarget, dl); 5359 } 5360 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 5361 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5362 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 5363 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 5364 DAG, Subtarget, dl); 5365 } 5366 } 5367 return SDValue(); 5368} 5369 5370SDValue 5371X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 5372 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5373 SDValue V1 = Op.getOperand(0); 5374 SDValue V2 = Op.getOperand(1); 5375 EVT VT = Op.getValueType(); 5376 DebugLoc dl = Op.getDebugLoc(); 5377 unsigned NumElems = VT.getVectorNumElements(); 5378 bool isMMX = VT.getSizeInBits() == 64; 5379 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 5380 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 5381 bool V1IsSplat = false; 5382 bool V2IsSplat = false; 5383 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 5384 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 5385 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); 5386 MachineFunction &MF = DAG.getMachineFunction(); 5387 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 5388 5389 // Shuffle operations on MMX not supported. 5390 if (isMMX) 5391 return Op; 5392 5393 // Vector shuffle lowering takes 3 steps: 5394 // 5395 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 5396 // narrowing and commutation of operands should be handled. 5397 // 2) Matching of shuffles with known shuffle masks to x86 target specific 5398 // shuffle nodes. 5399 // 3) Rewriting of unmatched masks into new generic shuffle operations, 5400 // so the shuffle can be broken into other shuffles and the legalizer can 5401 // try the lowering again. 5402 // 5403 // The general ideia is that no vector_shuffle operation should be left to 5404 // be matched during isel, all of them must be converted to a target specific 5405 // node here. 5406 5407 // Normalize the input vectors. Here splats, zeroed vectors, profitable 5408 // narrowing and commutation of operands should be handled. The actual code 5409 // doesn't include all of those, work in progress... 5410 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 5411 if (NewOp.getNode()) 5412 return NewOp; 5413 5414 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 5415 // unpckh_undef). Only use pshufd if speed is more important than size. 5416 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 5417 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5418 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 5419 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 5420 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5421 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5422 5423 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && 5424 RelaxedMayFoldVectorLoad(V1)) 5425 return getMOVDDup(Op, dl, V1, DAG); 5426 5427 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 5428 return getMOVHighToLow(Op, dl, DAG); 5429 5430 // Use to match splats 5431 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && 5432 (VT == MVT::v2f64 || VT == MVT::v2i64)) 5433 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5434 5435 if (X86::isPSHUFDMask(SVOp)) { 5436 // The actual implementation will match the mask in the if above and then 5437 // during isel it can match several different instructions, not only pshufd 5438 // as its name says, sad but true, emulate the behavior for now... 5439 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 5440 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 5441 5442 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5443 5444 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 5445 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 5446 5447 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5448 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 5449 TargetMask, DAG); 5450 5451 if (VT == MVT::v4f32) 5452 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 5453 TargetMask, DAG); 5454 } 5455 5456 // Check if this can be converted into a logical shift. 5457 bool isLeft = false; 5458 unsigned ShAmt = 0; 5459 SDValue ShVal; 5460 bool isShift = getSubtarget()->hasSSE2() && 5461 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 5462 if (isShift && ShVal.hasOneUse()) { 5463 // If the shifted value has multiple uses, it may be cheaper to use 5464 // v_set0 + movlhps or movhlps, etc. 5465 EVT EltVT = VT.getVectorElementType(); 5466 ShAmt *= EltVT.getSizeInBits(); 5467 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5468 } 5469 5470 if (X86::isMOVLMask(SVOp)) { 5471 if (V1IsUndef) 5472 return V2; 5473 if (ISD::isBuildVectorAllZeros(V1.getNode())) 5474 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 5475 if (!X86::isMOVLPMask(SVOp)) { 5476 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5477 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5478 5479 if (VT == MVT::v4i32 || VT == MVT::v4f32) 5480 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5481 } 5482 } 5483 5484 // FIXME: fold these into legal mask. 5485 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 5486 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 5487 5488 if (X86::isMOVHLPSMask(SVOp)) 5489 return getMOVHighToLow(Op, dl, DAG); 5490 5491 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5492 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 5493 5494 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5495 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 5496 5497 if (X86::isMOVLPMask(SVOp)) 5498 return getMOVLP(Op, dl, DAG, HasSSE2); 5499 5500 if (ShouldXformToMOVHLPS(SVOp) || 5501 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 5502 return CommuteVectorShuffle(SVOp, DAG); 5503 5504 if (isShift) { 5505 // No better options. Use a vshl / vsrl. 5506 EVT EltVT = VT.getVectorElementType(); 5507 ShAmt *= EltVT.getSizeInBits(); 5508 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5509 } 5510 5511 bool Commuted = false; 5512 // FIXME: This should also accept a bitcast of a splat? Be careful, not 5513 // 1,1,1,1 -> v8i16 though. 5514 V1IsSplat = isSplatVector(V1.getNode()); 5515 V2IsSplat = isSplatVector(V2.getNode()); 5516 5517 // Canonicalize the splat or undef, if present, to be on the RHS. 5518 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 5519 Op = CommuteVectorShuffle(SVOp, DAG); 5520 SVOp = cast<ShuffleVectorSDNode>(Op); 5521 V1 = SVOp->getOperand(0); 5522 V2 = SVOp->getOperand(1); 5523 std::swap(V1IsSplat, V2IsSplat); 5524 std::swap(V1IsUndef, V2IsUndef); 5525 Commuted = true; 5526 } 5527 5528 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 5529 // Shuffling low element of v1 into undef, just return v1. 5530 if (V2IsUndef) 5531 return V1; 5532 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 5533 // the instruction selector will not match, so get a canonical MOVL with 5534 // swapped operands to undo the commute. 5535 return getMOVL(DAG, dl, VT, V2, V1); 5536 } 5537 5538 if (X86::isUNPCKLMask(SVOp)) 5539 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 5540 5541 if (X86::isUNPCKHMask(SVOp)) 5542 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 5543 5544 if (V2IsSplat) { 5545 // Normalize mask so all entries that point to V2 points to its first 5546 // element then try to match unpck{h|l} again. If match, return a 5547 // new vector_shuffle with the corrected mask. 5548 SDValue NewMask = NormalizeMask(SVOp, DAG); 5549 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 5550 if (NSVOp != SVOp) { 5551 if (X86::isUNPCKLMask(NSVOp, true)) { 5552 return NewMask; 5553 } else if (X86::isUNPCKHMask(NSVOp, true)) { 5554 return NewMask; 5555 } 5556 } 5557 } 5558 5559 if (Commuted) { 5560 // Commute is back and try unpck* again. 5561 // FIXME: this seems wrong. 5562 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 5563 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 5564 5565 if (X86::isUNPCKLMask(NewSVOp)) 5566 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 5567 5568 if (X86::isUNPCKHMask(NewSVOp)) 5569 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 5570 } 5571 5572 // Normalize the node to match x86 shuffle ops if needed 5573 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 5574 return CommuteVectorShuffle(SVOp, DAG); 5575 5576 // The checks below are all present in isShuffleMaskLegal, but they are 5577 // inlined here right now to enable us to directly emit target specific 5578 // nodes, and remove one by one until they don't return Op anymore. 5579 SmallVector<int, 16> M; 5580 SVOp->getMask(M); 5581 5582 if (isPALIGNRMask(M, VT, HasSSSE3)) 5583 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 5584 X86::getShufflePALIGNRImmediate(SVOp), 5585 DAG); 5586 5587 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 5588 SVOp->getSplatIndex() == 0 && V2IsUndef) { 5589 if (VT == MVT::v2f64) 5590 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 5591 if (VT == MVT::v2i64) 5592 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 5593 } 5594 5595 if (isPSHUFHWMask(M, VT)) 5596 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 5597 X86::getShufflePSHUFHWImmediate(SVOp), 5598 DAG); 5599 5600 if (isPSHUFLWMask(M, VT)) 5601 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 5602 X86::getShufflePSHUFLWImmediate(SVOp), 5603 DAG); 5604 5605 if (isSHUFPMask(M, VT)) { 5606 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5607 if (VT == MVT::v4f32 || VT == MVT::v4i32) 5608 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, 5609 TargetMask, DAG); 5610 if (VT == MVT::v2f64 || VT == MVT::v2i64) 5611 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, 5612 TargetMask, DAG); 5613 } 5614 5615 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 5616 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5617 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 5618 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 5619 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5620 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5621 5622 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 5623 if (VT == MVT::v8i16) { 5624 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 5625 if (NewOp.getNode()) 5626 return NewOp; 5627 } 5628 5629 if (VT == MVT::v16i8) { 5630 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 5631 if (NewOp.getNode()) 5632 return NewOp; 5633 } 5634 5635 // Handle all 4 wide cases with a number of shuffles. 5636 if (NumElems == 4) 5637 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 5638 5639 return SDValue(); 5640} 5641 5642SDValue 5643X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 5644 SelectionDAG &DAG) const { 5645 EVT VT = Op.getValueType(); 5646 DebugLoc dl = Op.getDebugLoc(); 5647 if (VT.getSizeInBits() == 8) { 5648 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 5649 Op.getOperand(0), Op.getOperand(1)); 5650 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5651 DAG.getValueType(VT)); 5652 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5653 } else if (VT.getSizeInBits() == 16) { 5654 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5655 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 5656 if (Idx == 0) 5657 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5659 DAG.getNode(ISD::BITCAST, dl, 5660 MVT::v4i32, 5661 Op.getOperand(0)), 5662 Op.getOperand(1))); 5663 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 5664 Op.getOperand(0), Op.getOperand(1)); 5665 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5666 DAG.getValueType(VT)); 5667 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5668 } else if (VT == MVT::f32) { 5669 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 5670 // the result back to FR32 register. It's only worth matching if the 5671 // result has a single use which is a store or a bitcast to i32. And in 5672 // the case of a store, it's not worth it if the index is a constant 0, 5673 // because a MOVSSmr can be used instead, which is smaller and faster. 5674 if (!Op.hasOneUse()) 5675 return SDValue(); 5676 SDNode *User = *Op.getNode()->use_begin(); 5677 if ((User->getOpcode() != ISD::STORE || 5678 (isa<ConstantSDNode>(Op.getOperand(1)) && 5679 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 5680 (User->getOpcode() != ISD::BITCAST || 5681 User->getValueType(0) != MVT::i32)) 5682 return SDValue(); 5683 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5684 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 5685 Op.getOperand(0)), 5686 Op.getOperand(1)); 5687 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 5688 } else if (VT == MVT::i32) { 5689 // ExtractPS works with constant index. 5690 if (isa<ConstantSDNode>(Op.getOperand(1))) 5691 return Op; 5692 } 5693 return SDValue(); 5694} 5695 5696 5697SDValue 5698X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5699 SelectionDAG &DAG) const { 5700 if (!isa<ConstantSDNode>(Op.getOperand(1))) 5701 return SDValue(); 5702 5703 if (Subtarget->hasSSE41()) { 5704 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 5705 if (Res.getNode()) 5706 return Res; 5707 } 5708 5709 EVT VT = Op.getValueType(); 5710 DebugLoc dl = Op.getDebugLoc(); 5711 // TODO: handle v16i8. 5712 if (VT.getSizeInBits() == 16) { 5713 SDValue Vec = Op.getOperand(0); 5714 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5715 if (Idx == 0) 5716 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5717 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5718 DAG.getNode(ISD::BITCAST, dl, 5719 MVT::v4i32, Vec), 5720 Op.getOperand(1))); 5721 // Transform it so it match pextrw which produces a 32-bit result. 5722 EVT EltVT = MVT::i32; 5723 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 5724 Op.getOperand(0), Op.getOperand(1)); 5725 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 5726 DAG.getValueType(VT)); 5727 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5728 } else if (VT.getSizeInBits() == 32) { 5729 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5730 if (Idx == 0) 5731 return Op; 5732 5733 // SHUFPS the element to the lowest double word, then movss. 5734 int Mask[4] = { Idx, -1, -1, -1 }; 5735 EVT VVT = Op.getOperand(0).getValueType(); 5736 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5737 DAG.getUNDEF(VVT), Mask); 5738 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5739 DAG.getIntPtrConstant(0)); 5740 } else if (VT.getSizeInBits() == 64) { 5741 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 5742 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 5743 // to match extract_elt for f64. 5744 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5745 if (Idx == 0) 5746 return Op; 5747 5748 // UNPCKHPD the element to the lowest double word, then movsd. 5749 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 5750 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 5751 int Mask[2] = { 1, -1 }; 5752 EVT VVT = Op.getOperand(0).getValueType(); 5753 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5754 DAG.getUNDEF(VVT), Mask); 5755 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5756 DAG.getIntPtrConstant(0)); 5757 } 5758 5759 return SDValue(); 5760} 5761 5762SDValue 5763X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 5764 SelectionDAG &DAG) const { 5765 EVT VT = Op.getValueType(); 5766 EVT EltVT = VT.getVectorElementType(); 5767 DebugLoc dl = Op.getDebugLoc(); 5768 5769 SDValue N0 = Op.getOperand(0); 5770 SDValue N1 = Op.getOperand(1); 5771 SDValue N2 = Op.getOperand(2); 5772 5773 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 5774 isa<ConstantSDNode>(N2)) { 5775 unsigned Opc; 5776 if (VT == MVT::v8i16) 5777 Opc = X86ISD::PINSRW; 5778 else if (VT == MVT::v16i8) 5779 Opc = X86ISD::PINSRB; 5780 else 5781 Opc = X86ISD::PINSRB; 5782 5783 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 5784 // argument. 5785 if (N1.getValueType() != MVT::i32) 5786 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5787 if (N2.getValueType() != MVT::i32) 5788 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5789 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 5790 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 5791 // Bits [7:6] of the constant are the source select. This will always be 5792 // zero here. The DAG Combiner may combine an extract_elt index into these 5793 // bits. For example (insert (extract, 3), 2) could be matched by putting 5794 // the '3' into bits [7:6] of X86ISD::INSERTPS. 5795 // Bits [5:4] of the constant are the destination select. This is the 5796 // value of the incoming immediate. 5797 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 5798 // combine either bitwise AND or insert of float 0.0 to set these bits. 5799 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 5800 // Create this as a scalar to vector.. 5801 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 5802 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 5803 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 5804 // PINSR* works with constant index. 5805 return Op; 5806 } 5807 return SDValue(); 5808} 5809 5810SDValue 5811X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 5812 EVT VT = Op.getValueType(); 5813 EVT EltVT = VT.getVectorElementType(); 5814 5815 if (Subtarget->hasSSE41()) 5816 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 5817 5818 if (EltVT == MVT::i8) 5819 return SDValue(); 5820 5821 DebugLoc dl = Op.getDebugLoc(); 5822 SDValue N0 = Op.getOperand(0); 5823 SDValue N1 = Op.getOperand(1); 5824 SDValue N2 = Op.getOperand(2); 5825 5826 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 5827 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 5828 // as its second argument. 5829 if (N1.getValueType() != MVT::i32) 5830 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5831 if (N2.getValueType() != MVT::i32) 5832 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5833 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 5834 } 5835 return SDValue(); 5836} 5837 5838SDValue 5839X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5840 DebugLoc dl = Op.getDebugLoc(); 5841 5842 if (Op.getValueType() == MVT::v1i64 && 5843 Op.getOperand(0).getValueType() == MVT::i64) 5844 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 5845 5846 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 5847 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 5848 "Expected an SSE type!"); 5849 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 5850 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 5851} 5852 5853// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5854// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5855// one of the above mentioned nodes. It has to be wrapped because otherwise 5856// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5857// be used to form addressing mode. These wrapped nodes will be selected 5858// into MOV32ri. 5859SDValue 5860X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 5861 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5862 5863 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5864 // global base reg. 5865 unsigned char OpFlag = 0; 5866 unsigned WrapperKind = X86ISD::Wrapper; 5867 CodeModel::Model M = getTargetMachine().getCodeModel(); 5868 5869 if (Subtarget->isPICStyleRIPRel() && 5870 (M == CodeModel::Small || M == CodeModel::Kernel)) 5871 WrapperKind = X86ISD::WrapperRIP; 5872 else if (Subtarget->isPICStyleGOT()) 5873 OpFlag = X86II::MO_GOTOFF; 5874 else if (Subtarget->isPICStyleStubPIC()) 5875 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5876 5877 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5878 CP->getAlignment(), 5879 CP->getOffset(), OpFlag); 5880 DebugLoc DL = CP->getDebugLoc(); 5881 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5882 // With PIC, the address is actually $g + Offset. 5883 if (OpFlag) { 5884 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5885 DAG.getNode(X86ISD::GlobalBaseReg, 5886 DebugLoc(), getPointerTy()), 5887 Result); 5888 } 5889 5890 return Result; 5891} 5892 5893SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 5894 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5895 5896 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5897 // global base reg. 5898 unsigned char OpFlag = 0; 5899 unsigned WrapperKind = X86ISD::Wrapper; 5900 CodeModel::Model M = getTargetMachine().getCodeModel(); 5901 5902 if (Subtarget->isPICStyleRIPRel() && 5903 (M == CodeModel::Small || M == CodeModel::Kernel)) 5904 WrapperKind = X86ISD::WrapperRIP; 5905 else if (Subtarget->isPICStyleGOT()) 5906 OpFlag = X86II::MO_GOTOFF; 5907 else if (Subtarget->isPICStyleStubPIC()) 5908 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5909 5910 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5911 OpFlag); 5912 DebugLoc DL = JT->getDebugLoc(); 5913 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5914 5915 // With PIC, the address is actually $g + Offset. 5916 if (OpFlag) 5917 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5918 DAG.getNode(X86ISD::GlobalBaseReg, 5919 DebugLoc(), getPointerTy()), 5920 Result); 5921 5922 return Result; 5923} 5924 5925SDValue 5926X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 5927 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5928 5929 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5930 // global base reg. 5931 unsigned char OpFlag = 0; 5932 unsigned WrapperKind = X86ISD::Wrapper; 5933 CodeModel::Model M = getTargetMachine().getCodeModel(); 5934 5935 if (Subtarget->isPICStyleRIPRel() && 5936 (M == CodeModel::Small || M == CodeModel::Kernel)) 5937 WrapperKind = X86ISD::WrapperRIP; 5938 else if (Subtarget->isPICStyleGOT()) 5939 OpFlag = X86II::MO_GOTOFF; 5940 else if (Subtarget->isPICStyleStubPIC()) 5941 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5942 5943 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5944 5945 DebugLoc DL = Op.getDebugLoc(); 5946 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5947 5948 5949 // With PIC, the address is actually $g + Offset. 5950 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5951 !Subtarget->is64Bit()) { 5952 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5953 DAG.getNode(X86ISD::GlobalBaseReg, 5954 DebugLoc(), getPointerTy()), 5955 Result); 5956 } 5957 5958 return Result; 5959} 5960 5961SDValue 5962X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 5963 // Create the TargetBlockAddressAddress node. 5964 unsigned char OpFlags = 5965 Subtarget->ClassifyBlockAddressReference(); 5966 CodeModel::Model M = getTargetMachine().getCodeModel(); 5967 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5968 DebugLoc dl = Op.getDebugLoc(); 5969 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5970 /*isTarget=*/true, OpFlags); 5971 5972 if (Subtarget->isPICStyleRIPRel() && 5973 (M == CodeModel::Small || M == CodeModel::Kernel)) 5974 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5975 else 5976 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5977 5978 // With PIC, the address is actually $g + Offset. 5979 if (isGlobalRelativeToPICBase(OpFlags)) { 5980 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5981 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5982 Result); 5983 } 5984 5985 return Result; 5986} 5987 5988SDValue 5989X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5990 int64_t Offset, 5991 SelectionDAG &DAG) const { 5992 // Create the TargetGlobalAddress node, folding in the constant 5993 // offset if it is legal. 5994 unsigned char OpFlags = 5995 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5996 CodeModel::Model M = getTargetMachine().getCodeModel(); 5997 SDValue Result; 5998 if (OpFlags == X86II::MO_NO_FLAG && 5999 X86::isOffsetSuitableForCodeModel(Offset, M)) { 6000 // A direct static reference to a global. 6001 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 6002 Offset = 0; 6003 } else { 6004 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 6005 } 6006 6007 if (Subtarget->isPICStyleRIPRel() && 6008 (M == CodeModel::Small || M == CodeModel::Kernel)) 6009 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6010 else 6011 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6012 6013 // With PIC, the address is actually $g + Offset. 6014 if (isGlobalRelativeToPICBase(OpFlags)) { 6015 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6016 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6017 Result); 6018 } 6019 6020 // For globals that require a load from a stub to get the address, emit the 6021 // load. 6022 if (isGlobalStubReference(OpFlags)) 6023 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 6024 MachinePointerInfo::getGOT(), false, false, 0); 6025 6026 // If there was a non-zero offset that we didn't fold, create an explicit 6027 // addition for it. 6028 if (Offset != 0) 6029 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 6030 DAG.getConstant(Offset, getPointerTy())); 6031 6032 return Result; 6033} 6034 6035SDValue 6036X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 6037 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 6038 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 6039 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 6040} 6041 6042static SDValue 6043GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 6044 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 6045 unsigned char OperandFlags) { 6046 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6047 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6048 DebugLoc dl = GA->getDebugLoc(); 6049 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6050 GA->getValueType(0), 6051 GA->getOffset(), 6052 OperandFlags); 6053 if (InFlag) { 6054 SDValue Ops[] = { Chain, TGA, *InFlag }; 6055 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 6056 } else { 6057 SDValue Ops[] = { Chain, TGA }; 6058 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 6059 } 6060 6061 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 6062 MFI->setAdjustsStack(true); 6063 6064 SDValue Flag = Chain.getValue(1); 6065 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 6066} 6067 6068// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 6069static SDValue 6070LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6071 const EVT PtrVT) { 6072 SDValue InFlag; 6073 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 6074 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 6075 DAG.getNode(X86ISD::GlobalBaseReg, 6076 DebugLoc(), PtrVT), InFlag); 6077 InFlag = Chain.getValue(1); 6078 6079 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 6080} 6081 6082// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 6083static SDValue 6084LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6085 const EVT PtrVT) { 6086 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 6087 X86::RAX, X86II::MO_TLSGD); 6088} 6089 6090// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 6091// "local exec" model. 6092static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6093 const EVT PtrVT, TLSModel::Model model, 6094 bool is64Bit) { 6095 DebugLoc dl = GA->getDebugLoc(); 6096 6097 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 6098 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 6099 is64Bit ? 257 : 256)); 6100 6101 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 6102 DAG.getIntPtrConstant(0), 6103 MachinePointerInfo(Ptr), false, false, 0); 6104 6105 unsigned char OperandFlags = 0; 6106 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 6107 // initialexec. 6108 unsigned WrapperKind = X86ISD::Wrapper; 6109 if (model == TLSModel::LocalExec) { 6110 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 6111 } else if (is64Bit) { 6112 assert(model == TLSModel::InitialExec); 6113 OperandFlags = X86II::MO_GOTTPOFF; 6114 WrapperKind = X86ISD::WrapperRIP; 6115 } else { 6116 assert(model == TLSModel::InitialExec); 6117 OperandFlags = X86II::MO_INDNTPOFF; 6118 } 6119 6120 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 6121 // exec) 6122 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6123 GA->getValueType(0), 6124 GA->getOffset(), OperandFlags); 6125 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 6126 6127 if (model == TLSModel::InitialExec) 6128 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 6129 MachinePointerInfo::getGOT(), false, false, 0); 6130 6131 // The address of the thread local variable is the add of the thread 6132 // pointer with the offset of the variable. 6133 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 6134} 6135 6136SDValue 6137X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 6138 6139 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 6140 const GlobalValue *GV = GA->getGlobal(); 6141 6142 if (Subtarget->isTargetELF()) { 6143 // TODO: implement the "local dynamic" model 6144 // TODO: implement the "initial exec"model for pic executables 6145 6146 // If GV is an alias then use the aliasee for determining 6147 // thread-localness. 6148 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 6149 GV = GA->resolveAliasedGlobal(false); 6150 6151 TLSModel::Model model 6152 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 6153 6154 switch (model) { 6155 case TLSModel::GeneralDynamic: 6156 case TLSModel::LocalDynamic: // not implemented 6157 if (Subtarget->is64Bit()) 6158 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 6159 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 6160 6161 case TLSModel::InitialExec: 6162 case TLSModel::LocalExec: 6163 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 6164 Subtarget->is64Bit()); 6165 } 6166 } else if (Subtarget->isTargetDarwin()) { 6167 // Darwin only has one model of TLS. Lower to that. 6168 unsigned char OpFlag = 0; 6169 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 6170 X86ISD::WrapperRIP : X86ISD::Wrapper; 6171 6172 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6173 // global base reg. 6174 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 6175 !Subtarget->is64Bit(); 6176 if (PIC32) 6177 OpFlag = X86II::MO_TLVP_PIC_BASE; 6178 else 6179 OpFlag = X86II::MO_TLVP; 6180 DebugLoc DL = Op.getDebugLoc(); 6181 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 6182 getPointerTy(), 6183 GA->getOffset(), OpFlag); 6184 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6185 6186 // With PIC32, the address is actually $g + Offset. 6187 if (PIC32) 6188 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6189 DAG.getNode(X86ISD::GlobalBaseReg, 6190 DebugLoc(), getPointerTy()), 6191 Offset); 6192 6193 // Lowering the machine isd will make sure everything is in the right 6194 // location. 6195 SDValue Args[] = { Offset }; 6196 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1); 6197 6198 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 6199 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6200 MFI->setAdjustsStack(true); 6201 6202 // And our return value (tls address) is in the standard call return value 6203 // location. 6204 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 6205 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 6206 } 6207 6208 assert(false && 6209 "TLS not implemented for this target."); 6210 6211 llvm_unreachable("Unreachable"); 6212 return SDValue(); 6213} 6214 6215 6216/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 6217/// take a 2 x i32 value to shift plus a shift amount. 6218SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 6219 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 6220 EVT VT = Op.getValueType(); 6221 unsigned VTBits = VT.getSizeInBits(); 6222 DebugLoc dl = Op.getDebugLoc(); 6223 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 6224 SDValue ShOpLo = Op.getOperand(0); 6225 SDValue ShOpHi = Op.getOperand(1); 6226 SDValue ShAmt = Op.getOperand(2); 6227 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 6228 DAG.getConstant(VTBits - 1, MVT::i8)) 6229 : DAG.getConstant(0, VT); 6230 6231 SDValue Tmp2, Tmp3; 6232 if (Op.getOpcode() == ISD::SHL_PARTS) { 6233 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 6234 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 6235 } else { 6236 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 6237 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 6238 } 6239 6240 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 6241 DAG.getConstant(VTBits, MVT::i8)); 6242 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6243 AndNode, DAG.getConstant(0, MVT::i8)); 6244 6245 SDValue Hi, Lo; 6246 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6247 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 6248 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 6249 6250 if (Op.getOpcode() == ISD::SHL_PARTS) { 6251 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 6252 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 6253 } else { 6254 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 6255 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 6256 } 6257 6258 SDValue Ops[2] = { Lo, Hi }; 6259 return DAG.getMergeValues(Ops, 2, dl); 6260} 6261 6262SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 6263 SelectionDAG &DAG) const { 6264 EVT SrcVT = Op.getOperand(0).getValueType(); 6265 6266 if (SrcVT.isVector()) 6267 return SDValue(); 6268 6269 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 6270 "Unknown SINT_TO_FP to lower!"); 6271 6272 // These are really Legal; return the operand so the caller accepts it as 6273 // Legal. 6274 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 6275 return Op; 6276 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 6277 Subtarget->is64Bit()) { 6278 return Op; 6279 } 6280 6281 DebugLoc dl = Op.getDebugLoc(); 6282 unsigned Size = SrcVT.getSizeInBits()/8; 6283 MachineFunction &MF = DAG.getMachineFunction(); 6284 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 6285 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6286 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6287 StackSlot, 6288 MachinePointerInfo::getFixedStack(SSFI), 6289 false, false, 0); 6290 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 6291} 6292 6293SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 6294 SDValue StackSlot, 6295 SelectionDAG &DAG) const { 6296 // Build the FILD 6297 DebugLoc DL = Op.getDebugLoc(); 6298 SDVTList Tys; 6299 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 6300 if (useSSE) 6301 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 6302 else 6303 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 6304 6305 unsigned ByteSize = SrcVT.getSizeInBits()/8; 6306 6307 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 6308 MachineMemOperand *MMO = 6309 DAG.getMachineFunction() 6310 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6311 MachineMemOperand::MOLoad, ByteSize, ByteSize); 6312 6313 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 6314 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 6315 X86ISD::FILD, DL, 6316 Tys, Ops, array_lengthof(Ops), 6317 SrcVT, MMO); 6318 6319 if (useSSE) { 6320 Chain = Result.getValue(1); 6321 SDValue InFlag = Result.getValue(2); 6322 6323 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 6324 // shouldn't be necessary except that RFP cannot be live across 6325 // multiple blocks. When stackifier is fixed, they can be uncoupled. 6326 MachineFunction &MF = DAG.getMachineFunction(); 6327 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 6328 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 6329 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6330 Tys = DAG.getVTList(MVT::Other); 6331 SDValue Ops[] = { 6332 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 6333 }; 6334 MachineMemOperand *MMO = 6335 DAG.getMachineFunction() 6336 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6337 MachineMemOperand::MOStore, SSFISize, SSFISize); 6338 6339 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 6340 Ops, array_lengthof(Ops), 6341 Op.getValueType(), MMO); 6342 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 6343 MachinePointerInfo::getFixedStack(SSFI), 6344 false, false, 0); 6345 } 6346 6347 return Result; 6348} 6349 6350// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 6351SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 6352 SelectionDAG &DAG) const { 6353 // This algorithm is not obvious. Here it is in C code, more or less: 6354 /* 6355 double uint64_to_double( uint32_t hi, uint32_t lo ) { 6356 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 6357 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 6358 6359 // Copy ints to xmm registers. 6360 __m128i xh = _mm_cvtsi32_si128( hi ); 6361 __m128i xl = _mm_cvtsi32_si128( lo ); 6362 6363 // Combine into low half of a single xmm register. 6364 __m128i x = _mm_unpacklo_epi32( xh, xl ); 6365 __m128d d; 6366 double sd; 6367 6368 // Merge in appropriate exponents to give the integer bits the right 6369 // magnitude. 6370 x = _mm_unpacklo_epi32( x, exp ); 6371 6372 // Subtract away the biases to deal with the IEEE-754 double precision 6373 // implicit 1. 6374 d = _mm_sub_pd( (__m128d) x, bias ); 6375 6376 // All conversions up to here are exact. The correctly rounded result is 6377 // calculated using the current rounding mode using the following 6378 // horizontal add. 6379 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 6380 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 6381 // store doesn't really need to be here (except 6382 // maybe to zero the other double) 6383 return sd; 6384 } 6385 */ 6386 6387 DebugLoc dl = Op.getDebugLoc(); 6388 LLVMContext *Context = DAG.getContext(); 6389 6390 // Build some magic constants. 6391 std::vector<Constant*> CV0; 6392 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 6393 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 6394 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6395 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6396 Constant *C0 = ConstantVector::get(CV0); 6397 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 6398 6399 std::vector<Constant*> CV1; 6400 CV1.push_back( 6401 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 6402 CV1.push_back( 6403 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 6404 Constant *C1 = ConstantVector::get(CV1); 6405 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 6406 6407 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6408 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6409 Op.getOperand(0), 6410 DAG.getIntPtrConstant(1))); 6411 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6412 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6413 Op.getOperand(0), 6414 DAG.getIntPtrConstant(0))); 6415 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 6416 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 6417 MachinePointerInfo::getConstantPool(), 6418 false, false, 16); 6419 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 6420 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 6421 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 6422 MachinePointerInfo::getConstantPool(), 6423 false, false, 16); 6424 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 6425 6426 // Add the halves; easiest way is to swap them into another reg first. 6427 int ShufMask[2] = { 1, -1 }; 6428 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 6429 DAG.getUNDEF(MVT::v2f64), ShufMask); 6430 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 6431 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 6432 DAG.getIntPtrConstant(0)); 6433} 6434 6435// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 6436SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 6437 SelectionDAG &DAG) const { 6438 DebugLoc dl = Op.getDebugLoc(); 6439 // FP constant to bias correct the final result. 6440 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 6441 MVT::f64); 6442 6443 // Load the 32-bit value into an XMM register. 6444 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6445 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6446 Op.getOperand(0), 6447 DAG.getIntPtrConstant(0))); 6448 6449 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6450 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 6451 DAG.getIntPtrConstant(0)); 6452 6453 // Or the load with the bias. 6454 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 6455 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 6456 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6457 MVT::v2f64, Load)), 6458 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 6459 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6460 MVT::v2f64, Bias))); 6461 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6462 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 6463 DAG.getIntPtrConstant(0)); 6464 6465 // Subtract the bias. 6466 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 6467 6468 // Handle final rounding. 6469 EVT DestVT = Op.getValueType(); 6470 6471 if (DestVT.bitsLT(MVT::f64)) { 6472 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6473 DAG.getIntPtrConstant(0)); 6474 } else if (DestVT.bitsGT(MVT::f64)) { 6475 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6476 } 6477 6478 // Handle final rounding. 6479 return Sub; 6480} 6481 6482SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 6483 SelectionDAG &DAG) const { 6484 SDValue N0 = Op.getOperand(0); 6485 DebugLoc dl = Op.getDebugLoc(); 6486 6487 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 6488 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 6489 // the optimization here. 6490 if (DAG.SignBitIsZero(N0)) 6491 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 6492 6493 EVT SrcVT = N0.getValueType(); 6494 EVT DstVT = Op.getValueType(); 6495 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 6496 return LowerUINT_TO_FP_i64(Op, DAG); 6497 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 6498 return LowerUINT_TO_FP_i32(Op, DAG); 6499 6500 // Make a 64-bit buffer, and use it to build an FILD. 6501 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 6502 if (SrcVT == MVT::i32) { 6503 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 6504 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 6505 getPointerTy(), StackSlot, WordOff); 6506 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6507 StackSlot, MachinePointerInfo(), 6508 false, false, 0); 6509 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 6510 OffsetSlot, MachinePointerInfo(), 6511 false, false, 0); 6512 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 6513 return Fild; 6514 } 6515 6516 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 6517 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6518 StackSlot, MachinePointerInfo(), 6519 false, false, 0); 6520 // For i64 source, we need to add the appropriate power of 2 if the input 6521 // was negative. This is the same as the optimization in 6522 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 6523 // we must be careful to do the computation in x87 extended precision, not 6524 // in SSE. (The generic code can't know it's OK to do this, or how to.) 6525 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 6526 MachineMemOperand *MMO = 6527 DAG.getMachineFunction() 6528 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6529 MachineMemOperand::MOLoad, 8, 8); 6530 6531 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 6532 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 6533 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 6534 MVT::i64, MMO); 6535 6536 APInt FF(32, 0x5F800000ULL); 6537 6538 // Check whether the sign bit is set. 6539 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 6540 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 6541 ISD::SETLT); 6542 6543 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 6544 SDValue FudgePtr = DAG.getConstantPool( 6545 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 6546 getPointerTy()); 6547 6548 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 6549 SDValue Zero = DAG.getIntPtrConstant(0); 6550 SDValue Four = DAG.getIntPtrConstant(4); 6551 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 6552 Zero, Four); 6553 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 6554 6555 // Load the value out, extending it from f32 to f80. 6556 // FIXME: Avoid the extend by constructing the right constant pool? 6557 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(), 6558 FudgePtr, MachinePointerInfo::getConstantPool(), 6559 MVT::f32, false, false, 4); 6560 // Extend everything to 80 bits to force it to be done on x87. 6561 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 6562 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 6563} 6564 6565std::pair<SDValue,SDValue> X86TargetLowering:: 6566FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 6567 DebugLoc DL = Op.getDebugLoc(); 6568 6569 EVT DstTy = Op.getValueType(); 6570 6571 if (!IsSigned) { 6572 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 6573 DstTy = MVT::i64; 6574 } 6575 6576 assert(DstTy.getSimpleVT() <= MVT::i64 && 6577 DstTy.getSimpleVT() >= MVT::i16 && 6578 "Unknown FP_TO_SINT to lower!"); 6579 6580 // These are really Legal. 6581 if (DstTy == MVT::i32 && 6582 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6583 return std::make_pair(SDValue(), SDValue()); 6584 if (Subtarget->is64Bit() && 6585 DstTy == MVT::i64 && 6586 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6587 return std::make_pair(SDValue(), SDValue()); 6588 6589 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 6590 // stack slot. 6591 MachineFunction &MF = DAG.getMachineFunction(); 6592 unsigned MemSize = DstTy.getSizeInBits()/8; 6593 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6594 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6595 6596 6597 6598 unsigned Opc; 6599 switch (DstTy.getSimpleVT().SimpleTy) { 6600 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 6601 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 6602 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 6603 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 6604 } 6605 6606 SDValue Chain = DAG.getEntryNode(); 6607 SDValue Value = Op.getOperand(0); 6608 EVT TheVT = Op.getOperand(0).getValueType(); 6609 if (isScalarFPTypeInSSEReg(TheVT)) { 6610 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 6611 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 6612 MachinePointerInfo::getFixedStack(SSFI), 6613 false, false, 0); 6614 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 6615 SDValue Ops[] = { 6616 Chain, StackSlot, DAG.getValueType(TheVT) 6617 }; 6618 6619 MachineMemOperand *MMO = 6620 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6621 MachineMemOperand::MOLoad, MemSize, MemSize); 6622 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 6623 DstTy, MMO); 6624 Chain = Value.getValue(1); 6625 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6626 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6627 } 6628 6629 MachineMemOperand *MMO = 6630 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6631 MachineMemOperand::MOStore, MemSize, MemSize); 6632 6633 // Build the FP_TO_INT*_IN_MEM 6634 SDValue Ops[] = { Chain, Value, StackSlot }; 6635 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 6636 Ops, 3, DstTy, MMO); 6637 6638 return std::make_pair(FIST, StackSlot); 6639} 6640 6641SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 6642 SelectionDAG &DAG) const { 6643 if (Op.getValueType().isVector()) 6644 return SDValue(); 6645 6646 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 6647 SDValue FIST = Vals.first, StackSlot = Vals.second; 6648 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 6649 if (FIST.getNode() == 0) return Op; 6650 6651 // Load the result. 6652 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6653 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 6654} 6655 6656SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 6657 SelectionDAG &DAG) const { 6658 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 6659 SDValue FIST = Vals.first, StackSlot = Vals.second; 6660 assert(FIST.getNode() && "Unexpected failure"); 6661 6662 // Load the result. 6663 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6664 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 6665} 6666 6667SDValue X86TargetLowering::LowerFABS(SDValue Op, 6668 SelectionDAG &DAG) const { 6669 LLVMContext *Context = DAG.getContext(); 6670 DebugLoc dl = Op.getDebugLoc(); 6671 EVT VT = Op.getValueType(); 6672 EVT EltVT = VT; 6673 if (VT.isVector()) 6674 EltVT = VT.getVectorElementType(); 6675 std::vector<Constant*> CV; 6676 if (EltVT == MVT::f64) { 6677 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 6678 CV.push_back(C); 6679 CV.push_back(C); 6680 } else { 6681 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 6682 CV.push_back(C); 6683 CV.push_back(C); 6684 CV.push_back(C); 6685 CV.push_back(C); 6686 } 6687 Constant *C = ConstantVector::get(CV); 6688 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6689 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6690 MachinePointerInfo::getConstantPool(), 6691 false, false, 16); 6692 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 6693} 6694 6695SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 6696 LLVMContext *Context = DAG.getContext(); 6697 DebugLoc dl = Op.getDebugLoc(); 6698 EVT VT = Op.getValueType(); 6699 EVT EltVT = VT; 6700 if (VT.isVector()) 6701 EltVT = VT.getVectorElementType(); 6702 std::vector<Constant*> CV; 6703 if (EltVT == MVT::f64) { 6704 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 6705 CV.push_back(C); 6706 CV.push_back(C); 6707 } else { 6708 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 6709 CV.push_back(C); 6710 CV.push_back(C); 6711 CV.push_back(C); 6712 CV.push_back(C); 6713 } 6714 Constant *C = ConstantVector::get(CV); 6715 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6716 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6717 MachinePointerInfo::getConstantPool(), 6718 false, false, 16); 6719 if (VT.isVector()) { 6720 return DAG.getNode(ISD::BITCAST, dl, VT, 6721 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 6722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 6723 Op.getOperand(0)), 6724 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 6725 } else { 6726 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 6727 } 6728} 6729 6730SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 6731 LLVMContext *Context = DAG.getContext(); 6732 SDValue Op0 = Op.getOperand(0); 6733 SDValue Op1 = Op.getOperand(1); 6734 DebugLoc dl = Op.getDebugLoc(); 6735 EVT VT = Op.getValueType(); 6736 EVT SrcVT = Op1.getValueType(); 6737 6738 // If second operand is smaller, extend it first. 6739 if (SrcVT.bitsLT(VT)) { 6740 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 6741 SrcVT = VT; 6742 } 6743 // And if it is bigger, shrink it first. 6744 if (SrcVT.bitsGT(VT)) { 6745 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 6746 SrcVT = VT; 6747 } 6748 6749 // At this point the operands and the result should have the same 6750 // type, and that won't be f80 since that is not custom lowered. 6751 6752 // First get the sign bit of second operand. 6753 std::vector<Constant*> CV; 6754 if (SrcVT == MVT::f64) { 6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 6756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6757 } else { 6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 6759 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6760 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6761 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6762 } 6763 Constant *C = ConstantVector::get(CV); 6764 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6765 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 6766 MachinePointerInfo::getConstantPool(), 6767 false, false, 16); 6768 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 6769 6770 // Shift sign bit right or left if the two operands have different types. 6771 if (SrcVT.bitsGT(VT)) { 6772 // Op0 is MVT::f32, Op1 is MVT::f64. 6773 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 6774 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 6775 DAG.getConstant(32, MVT::i32)); 6776 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 6777 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 6778 DAG.getIntPtrConstant(0)); 6779 } 6780 6781 // Clear first operand sign bit. 6782 CV.clear(); 6783 if (VT == MVT::f64) { 6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 6785 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6786 } else { 6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 6788 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6789 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6790 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6791 } 6792 C = ConstantVector::get(CV); 6793 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6794 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6795 MachinePointerInfo::getConstantPool(), 6796 false, false, 16); 6797 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 6798 6799 // Or the value with the sign bit. 6800 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 6801} 6802 6803/// Emit nodes that will be selected as "test Op0,Op0", or something 6804/// equivalent. 6805SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 6806 SelectionDAG &DAG) const { 6807 DebugLoc dl = Op.getDebugLoc(); 6808 6809 // CF and OF aren't always set the way we want. Determine which 6810 // of these we need. 6811 bool NeedCF = false; 6812 bool NeedOF = false; 6813 switch (X86CC) { 6814 default: break; 6815 case X86::COND_A: case X86::COND_AE: 6816 case X86::COND_B: case X86::COND_BE: 6817 NeedCF = true; 6818 break; 6819 case X86::COND_G: case X86::COND_GE: 6820 case X86::COND_L: case X86::COND_LE: 6821 case X86::COND_O: case X86::COND_NO: 6822 NeedOF = true; 6823 break; 6824 } 6825 6826 // See if we can use the EFLAGS value from the operand instead of 6827 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 6828 // we prove that the arithmetic won't overflow, we can't use OF or CF. 6829 if (Op.getResNo() != 0 || NeedOF || NeedCF) 6830 // Emit a CMP with 0, which is the TEST pattern. 6831 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6832 DAG.getConstant(0, Op.getValueType())); 6833 6834 unsigned Opcode = 0; 6835 unsigned NumOperands = 0; 6836 switch (Op.getNode()->getOpcode()) { 6837 case ISD::ADD: 6838 // Due to an isel shortcoming, be conservative if this add is likely to be 6839 // selected as part of a load-modify-store instruction. When the root node 6840 // in a match is a store, isel doesn't know how to remap non-chain non-flag 6841 // uses of other nodes in the match, such as the ADD in this case. This 6842 // leads to the ADD being left around and reselected, with the result being 6843 // two adds in the output. Alas, even if none our users are stores, that 6844 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 6845 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 6846 // climbing the DAG back to the root, and it doesn't seem to be worth the 6847 // effort. 6848 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6849 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6850 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 6851 goto default_case; 6852 6853 if (ConstantSDNode *C = 6854 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 6855 // An add of one will be selected as an INC. 6856 if (C->getAPIntValue() == 1) { 6857 Opcode = X86ISD::INC; 6858 NumOperands = 1; 6859 break; 6860 } 6861 6862 // An add of negative one (subtract of one) will be selected as a DEC. 6863 if (C->getAPIntValue().isAllOnesValue()) { 6864 Opcode = X86ISD::DEC; 6865 NumOperands = 1; 6866 break; 6867 } 6868 } 6869 6870 // Otherwise use a regular EFLAGS-setting add. 6871 Opcode = X86ISD::ADD; 6872 NumOperands = 2; 6873 break; 6874 case ISD::AND: { 6875 // If the primary and result isn't used, don't bother using X86ISD::AND, 6876 // because a TEST instruction will be better. 6877 bool NonFlagUse = false; 6878 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6879 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 6880 SDNode *User = *UI; 6881 unsigned UOpNo = UI.getOperandNo(); 6882 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 6883 // Look pass truncate. 6884 UOpNo = User->use_begin().getOperandNo(); 6885 User = *User->use_begin(); 6886 } 6887 6888 if (User->getOpcode() != ISD::BRCOND && 6889 User->getOpcode() != ISD::SETCC && 6890 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 6891 NonFlagUse = true; 6892 break; 6893 } 6894 } 6895 6896 if (!NonFlagUse) 6897 break; 6898 } 6899 // FALL THROUGH 6900 case ISD::SUB: 6901 case ISD::OR: 6902 case ISD::XOR: 6903 // Due to the ISEL shortcoming noted above, be conservative if this op is 6904 // likely to be selected as part of a load-modify-store instruction. 6905 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6906 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6907 if (UI->getOpcode() == ISD::STORE) 6908 goto default_case; 6909 6910 // Otherwise use a regular EFLAGS-setting instruction. 6911 switch (Op.getNode()->getOpcode()) { 6912 default: llvm_unreachable("unexpected operator!"); 6913 case ISD::SUB: Opcode = X86ISD::SUB; break; 6914 case ISD::OR: Opcode = X86ISD::OR; break; 6915 case ISD::XOR: Opcode = X86ISD::XOR; break; 6916 case ISD::AND: Opcode = X86ISD::AND; break; 6917 } 6918 6919 NumOperands = 2; 6920 break; 6921 case X86ISD::ADD: 6922 case X86ISD::SUB: 6923 case X86ISD::INC: 6924 case X86ISD::DEC: 6925 case X86ISD::OR: 6926 case X86ISD::XOR: 6927 case X86ISD::AND: 6928 return SDValue(Op.getNode(), 1); 6929 default: 6930 default_case: 6931 break; 6932 } 6933 6934 if (Opcode == 0) 6935 // Emit a CMP with 0, which is the TEST pattern. 6936 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6937 DAG.getConstant(0, Op.getValueType())); 6938 6939 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 6940 SmallVector<SDValue, 4> Ops; 6941 for (unsigned i = 0; i != NumOperands; ++i) 6942 Ops.push_back(Op.getOperand(i)); 6943 6944 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 6945 DAG.ReplaceAllUsesWith(Op, New); 6946 return SDValue(New.getNode(), 1); 6947} 6948 6949/// Emit nodes that will be selected as "cmp Op0,Op1", or something 6950/// equivalent. 6951SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 6952 SelectionDAG &DAG) const { 6953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 6954 if (C->getAPIntValue() == 0) 6955 return EmitTest(Op0, X86CC, DAG); 6956 6957 DebugLoc dl = Op0.getDebugLoc(); 6958 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 6959} 6960 6961/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 6962/// if it's possible. 6963SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 6964 DebugLoc dl, SelectionDAG &DAG) const { 6965 SDValue Op0 = And.getOperand(0); 6966 SDValue Op1 = And.getOperand(1); 6967 if (Op0.getOpcode() == ISD::TRUNCATE) 6968 Op0 = Op0.getOperand(0); 6969 if (Op1.getOpcode() == ISD::TRUNCATE) 6970 Op1 = Op1.getOperand(0); 6971 6972 SDValue LHS, RHS; 6973 if (Op1.getOpcode() == ISD::SHL) 6974 std::swap(Op0, Op1); 6975 if (Op0.getOpcode() == ISD::SHL) { 6976 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6977 if (And00C->getZExtValue() == 1) { 6978 // If we looked past a truncate, check that it's only truncating away 6979 // known zeros. 6980 unsigned BitWidth = Op0.getValueSizeInBits(); 6981 unsigned AndBitWidth = And.getValueSizeInBits(); 6982 if (BitWidth > AndBitWidth) { 6983 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 6984 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 6985 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 6986 return SDValue(); 6987 } 6988 LHS = Op1; 6989 RHS = Op0.getOperand(1); 6990 } 6991 } else if (Op1.getOpcode() == ISD::Constant) { 6992 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6993 SDValue AndLHS = Op0; 6994 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6995 LHS = AndLHS.getOperand(0); 6996 RHS = AndLHS.getOperand(1); 6997 } 6998 } 6999 7000 if (LHS.getNode()) { 7001 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 7002 // instruction. Since the shift amount is in-range-or-undefined, we know 7003 // that doing a bittest on the i32 value is ok. We extend to i32 because 7004 // the encoding for the i16 version is larger than the i32 version. 7005 // Also promote i16 to i32 for performance / code size reason. 7006 if (LHS.getValueType() == MVT::i8 || 7007 LHS.getValueType() == MVT::i16) 7008 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 7009 7010 // If the operand types disagree, extend the shift amount to match. Since 7011 // BT ignores high bits (like shifts) we can use anyextend. 7012 if (LHS.getValueType() != RHS.getValueType()) 7013 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 7014 7015 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 7016 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 7017 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7018 DAG.getConstant(Cond, MVT::i8), BT); 7019 } 7020 7021 return SDValue(); 7022} 7023 7024SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 7025 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 7026 SDValue Op0 = Op.getOperand(0); 7027 SDValue Op1 = Op.getOperand(1); 7028 DebugLoc dl = Op.getDebugLoc(); 7029 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 7030 7031 // Optimize to BT if possible. 7032 // Lower (X & (1 << N)) == 0 to BT(X, N). 7033 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 7034 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 7035 if (Op0.getOpcode() == ISD::AND && 7036 Op0.hasOneUse() && 7037 Op1.getOpcode() == ISD::Constant && 7038 cast<ConstantSDNode>(Op1)->isNullValue() && 7039 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7040 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 7041 if (NewSetCC.getNode()) 7042 return NewSetCC; 7043 } 7044 7045 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 7046 if (Op0.getOpcode() == X86ISD::SETCC && 7047 Op1.getOpcode() == ISD::Constant && 7048 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 7049 cast<ConstantSDNode>(Op1)->isNullValue()) && 7050 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7051 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 7052 bool Invert = (CC == ISD::SETNE) ^ 7053 cast<ConstantSDNode>(Op1)->isNullValue(); 7054 if (Invert) 7055 CCode = X86::GetOppositeBranchCondition(CCode); 7056 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7057 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 7058 } 7059 7060 bool isFP = Op1.getValueType().isFloatingPoint(); 7061 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 7062 if (X86CC == X86::COND_INVALID) 7063 return SDValue(); 7064 7065 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 7066 7067 // Use sbb x, x to materialize carry bit into a GPR. 7068 if (X86CC == X86::COND_B) 7069 return DAG.getNode(ISD::AND, dl, MVT::i8, 7070 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 7071 DAG.getConstant(X86CC, MVT::i8), Cond), 7072 DAG.getConstant(1, MVT::i8)); 7073 7074 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7075 DAG.getConstant(X86CC, MVT::i8), Cond); 7076} 7077 7078SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 7079 SDValue Cond; 7080 SDValue Op0 = Op.getOperand(0); 7081 SDValue Op1 = Op.getOperand(1); 7082 SDValue CC = Op.getOperand(2); 7083 EVT VT = Op.getValueType(); 7084 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 7085 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 7086 DebugLoc dl = Op.getDebugLoc(); 7087 7088 if (isFP) { 7089 unsigned SSECC = 8; 7090 EVT VT0 = Op0.getValueType(); 7091 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 7092 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 7093 bool Swap = false; 7094 7095 switch (SetCCOpcode) { 7096 default: break; 7097 case ISD::SETOEQ: 7098 case ISD::SETEQ: SSECC = 0; break; 7099 case ISD::SETOGT: 7100 case ISD::SETGT: Swap = true; // Fallthrough 7101 case ISD::SETLT: 7102 case ISD::SETOLT: SSECC = 1; break; 7103 case ISD::SETOGE: 7104 case ISD::SETGE: Swap = true; // Fallthrough 7105 case ISD::SETLE: 7106 case ISD::SETOLE: SSECC = 2; break; 7107 case ISD::SETUO: SSECC = 3; break; 7108 case ISD::SETUNE: 7109 case ISD::SETNE: SSECC = 4; break; 7110 case ISD::SETULE: Swap = true; 7111 case ISD::SETUGE: SSECC = 5; break; 7112 case ISD::SETULT: Swap = true; 7113 case ISD::SETUGT: SSECC = 6; break; 7114 case ISD::SETO: SSECC = 7; break; 7115 } 7116 if (Swap) 7117 std::swap(Op0, Op1); 7118 7119 // In the two special cases we can't handle, emit two comparisons. 7120 if (SSECC == 8) { 7121 if (SetCCOpcode == ISD::SETUEQ) { 7122 SDValue UNORD, EQ; 7123 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 7124 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 7125 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 7126 } 7127 else if (SetCCOpcode == ISD::SETONE) { 7128 SDValue ORD, NEQ; 7129 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 7130 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 7131 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 7132 } 7133 llvm_unreachable("Illegal FP comparison"); 7134 } 7135 // Handle all other FP comparisons here. 7136 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 7137 } 7138 7139 // We are handling one of the integer comparisons here. Since SSE only has 7140 // GT and EQ comparisons for integer, swapping operands and multiple 7141 // operations may be required for some comparisons. 7142 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 7143 bool Swap = false, Invert = false, FlipSigns = false; 7144 7145 switch (VT.getSimpleVT().SimpleTy) { 7146 default: break; 7147 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 7148 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 7149 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 7150 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 7151 } 7152 7153 switch (SetCCOpcode) { 7154 default: break; 7155 case ISD::SETNE: Invert = true; 7156 case ISD::SETEQ: Opc = EQOpc; break; 7157 case ISD::SETLT: Swap = true; 7158 case ISD::SETGT: Opc = GTOpc; break; 7159 case ISD::SETGE: Swap = true; 7160 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 7161 case ISD::SETULT: Swap = true; 7162 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 7163 case ISD::SETUGE: Swap = true; 7164 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 7165 } 7166 if (Swap) 7167 std::swap(Op0, Op1); 7168 7169 // Since SSE has no unsigned integer comparisons, we need to flip the sign 7170 // bits of the inputs before performing those operations. 7171 if (FlipSigns) { 7172 EVT EltVT = VT.getVectorElementType(); 7173 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 7174 EltVT); 7175 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 7176 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 7177 SignBits.size()); 7178 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 7179 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 7180 } 7181 7182 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 7183 7184 // If the logical-not of the result is required, perform that now. 7185 if (Invert) 7186 Result = DAG.getNOT(dl, Result, VT); 7187 7188 return Result; 7189} 7190 7191// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 7192static bool isX86LogicalCmp(SDValue Op) { 7193 unsigned Opc = Op.getNode()->getOpcode(); 7194 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 7195 return true; 7196 if (Op.getResNo() == 1 && 7197 (Opc == X86ISD::ADD || 7198 Opc == X86ISD::SUB || 7199 Opc == X86ISD::SMUL || 7200 Opc == X86ISD::UMUL || 7201 Opc == X86ISD::INC || 7202 Opc == X86ISD::DEC || 7203 Opc == X86ISD::OR || 7204 Opc == X86ISD::XOR || 7205 Opc == X86ISD::AND)) 7206 return true; 7207 7208 return false; 7209} 7210 7211static bool isZero(SDValue V) { 7212 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 7213 return C && C->isNullValue(); 7214} 7215 7216static bool isAllOnes(SDValue V) { 7217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 7218 return C && C->isAllOnesValue(); 7219} 7220 7221SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 7222 bool addTest = true; 7223 SDValue Cond = Op.getOperand(0); 7224 SDValue Op1 = Op.getOperand(1); 7225 SDValue Op2 = Op.getOperand(2); 7226 DebugLoc DL = Op.getDebugLoc(); 7227 SDValue CC; 7228 7229 if (Cond.getOpcode() == ISD::SETCC) { 7230 SDValue NewCond = LowerSETCC(Cond, DAG); 7231 if (NewCond.getNode()) 7232 Cond = NewCond; 7233 } 7234 7235 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 7236 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 7237 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 7238 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 7239 if (Cond.getOpcode() == X86ISD::SETCC && 7240 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 7241 isZero(Cond.getOperand(1).getOperand(1))) { 7242 SDValue Cmp = Cond.getOperand(1); 7243 7244 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 7245 7246 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 7247 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 7248 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 7249 7250 SDValue CmpOp0 = Cmp.getOperand(0); 7251 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 7252 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 7253 7254 SDValue Res = // Res = 0 or -1. 7255 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 7256 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 7257 7258 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 7259 Res = DAG.getNOT(DL, Res, Res.getValueType()); 7260 7261 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 7262 if (N2C == 0 || !N2C->isNullValue()) 7263 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 7264 return Res; 7265 } 7266 } 7267 7268 // Look past (and (setcc_carry (cmp ...)), 1). 7269 if (Cond.getOpcode() == ISD::AND && 7270 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 7271 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 7272 if (C && C->getAPIntValue() == 1) 7273 Cond = Cond.getOperand(0); 7274 } 7275 7276 // If condition flag is set by a X86ISD::CMP, then use it as the condition 7277 // setting operand in place of the X86ISD::SETCC. 7278 if (Cond.getOpcode() == X86ISD::SETCC || 7279 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 7280 CC = Cond.getOperand(0); 7281 7282 SDValue Cmp = Cond.getOperand(1); 7283 unsigned Opc = Cmp.getOpcode(); 7284 EVT VT = Op.getValueType(); 7285 7286 bool IllegalFPCMov = false; 7287 if (VT.isFloatingPoint() && !VT.isVector() && 7288 !isScalarFPTypeInSSEReg(VT)) // FPStack? 7289 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 7290 7291 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 7292 Opc == X86ISD::BT) { // FIXME 7293 Cond = Cmp; 7294 addTest = false; 7295 } 7296 } 7297 7298 if (addTest) { 7299 // Look pass the truncate. 7300 if (Cond.getOpcode() == ISD::TRUNCATE) 7301 Cond = Cond.getOperand(0); 7302 7303 // We know the result of AND is compared against zero. Try to match 7304 // it to BT. 7305 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7306 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 7307 if (NewSetCC.getNode()) { 7308 CC = NewSetCC.getOperand(0); 7309 Cond = NewSetCC.getOperand(1); 7310 addTest = false; 7311 } 7312 } 7313 } 7314 7315 if (addTest) { 7316 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7317 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7318 } 7319 7320 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 7321 // condition is true. 7322 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 7323 SDValue Ops[] = { Op2, Op1, CC, Cond }; 7324 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 7325} 7326 7327// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 7328// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 7329// from the AND / OR. 7330static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 7331 Opc = Op.getOpcode(); 7332 if (Opc != ISD::OR && Opc != ISD::AND) 7333 return false; 7334 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7335 Op.getOperand(0).hasOneUse() && 7336 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 7337 Op.getOperand(1).hasOneUse()); 7338} 7339 7340// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 7341// 1 and that the SETCC node has a single use. 7342static bool isXor1OfSetCC(SDValue Op) { 7343 if (Op.getOpcode() != ISD::XOR) 7344 return false; 7345 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7346 if (N1C && N1C->getAPIntValue() == 1) { 7347 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7348 Op.getOperand(0).hasOneUse(); 7349 } 7350 return false; 7351} 7352 7353SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 7354 bool addTest = true; 7355 SDValue Chain = Op.getOperand(0); 7356 SDValue Cond = Op.getOperand(1); 7357 SDValue Dest = Op.getOperand(2); 7358 DebugLoc dl = Op.getDebugLoc(); 7359 SDValue CC; 7360 7361 if (Cond.getOpcode() == ISD::SETCC) { 7362 SDValue NewCond = LowerSETCC(Cond, DAG); 7363 if (NewCond.getNode()) 7364 Cond = NewCond; 7365 } 7366#if 0 7367 // FIXME: LowerXALUO doesn't handle these!! 7368 else if (Cond.getOpcode() == X86ISD::ADD || 7369 Cond.getOpcode() == X86ISD::SUB || 7370 Cond.getOpcode() == X86ISD::SMUL || 7371 Cond.getOpcode() == X86ISD::UMUL) 7372 Cond = LowerXALUO(Cond, DAG); 7373#endif 7374 7375 // Look pass (and (setcc_carry (cmp ...)), 1). 7376 if (Cond.getOpcode() == ISD::AND && 7377 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 7378 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 7379 if (C && C->getAPIntValue() == 1) 7380 Cond = Cond.getOperand(0); 7381 } 7382 7383 // If condition flag is set by a X86ISD::CMP, then use it as the condition 7384 // setting operand in place of the X86ISD::SETCC. 7385 if (Cond.getOpcode() == X86ISD::SETCC || 7386 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 7387 CC = Cond.getOperand(0); 7388 7389 SDValue Cmp = Cond.getOperand(1); 7390 unsigned Opc = Cmp.getOpcode(); 7391 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 7392 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 7393 Cond = Cmp; 7394 addTest = false; 7395 } else { 7396 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 7397 default: break; 7398 case X86::COND_O: 7399 case X86::COND_B: 7400 // These can only come from an arithmetic instruction with overflow, 7401 // e.g. SADDO, UADDO. 7402 Cond = Cond.getNode()->getOperand(1); 7403 addTest = false; 7404 break; 7405 } 7406 } 7407 } else { 7408 unsigned CondOpc; 7409 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 7410 SDValue Cmp = Cond.getOperand(0).getOperand(1); 7411 if (CondOpc == ISD::OR) { 7412 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 7413 // two branches instead of an explicit OR instruction with a 7414 // separate test. 7415 if (Cmp == Cond.getOperand(1).getOperand(1) && 7416 isX86LogicalCmp(Cmp)) { 7417 CC = Cond.getOperand(0).getOperand(0); 7418 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7419 Chain, Dest, CC, Cmp); 7420 CC = Cond.getOperand(1).getOperand(0); 7421 Cond = Cmp; 7422 addTest = false; 7423 } 7424 } else { // ISD::AND 7425 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 7426 // two branches instead of an explicit AND instruction with a 7427 // separate test. However, we only do this if this block doesn't 7428 // have a fall-through edge, because this requires an explicit 7429 // jmp when the condition is false. 7430 if (Cmp == Cond.getOperand(1).getOperand(1) && 7431 isX86LogicalCmp(Cmp) && 7432 Op.getNode()->hasOneUse()) { 7433 X86::CondCode CCode = 7434 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7435 CCode = X86::GetOppositeBranchCondition(CCode); 7436 CC = DAG.getConstant(CCode, MVT::i8); 7437 SDNode *User = *Op.getNode()->use_begin(); 7438 // Look for an unconditional branch following this conditional branch. 7439 // We need this because we need to reverse the successors in order 7440 // to implement FCMP_OEQ. 7441 if (User->getOpcode() == ISD::BR) { 7442 SDValue FalseBB = User->getOperand(1); 7443 SDNode *NewBR = 7444 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 7445 assert(NewBR == User); 7446 (void)NewBR; 7447 Dest = FalseBB; 7448 7449 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7450 Chain, Dest, CC, Cmp); 7451 X86::CondCode CCode = 7452 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 7453 CCode = X86::GetOppositeBranchCondition(CCode); 7454 CC = DAG.getConstant(CCode, MVT::i8); 7455 Cond = Cmp; 7456 addTest = false; 7457 } 7458 } 7459 } 7460 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 7461 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 7462 // It should be transformed during dag combiner except when the condition 7463 // is set by a arithmetics with overflow node. 7464 X86::CondCode CCode = 7465 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7466 CCode = X86::GetOppositeBranchCondition(CCode); 7467 CC = DAG.getConstant(CCode, MVT::i8); 7468 Cond = Cond.getOperand(0).getOperand(1); 7469 addTest = false; 7470 } 7471 } 7472 7473 if (addTest) { 7474 // Look pass the truncate. 7475 if (Cond.getOpcode() == ISD::TRUNCATE) 7476 Cond = Cond.getOperand(0); 7477 7478 // We know the result of AND is compared against zero. Try to match 7479 // it to BT. 7480 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7481 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 7482 if (NewSetCC.getNode()) { 7483 CC = NewSetCC.getOperand(0); 7484 Cond = NewSetCC.getOperand(1); 7485 addTest = false; 7486 } 7487 } 7488 } 7489 7490 if (addTest) { 7491 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7492 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7493 } 7494 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7495 Chain, Dest, CC, Cond); 7496} 7497 7498 7499// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 7500// Calls to _alloca is needed to probe the stack when allocating more than 4k 7501// bytes in one go. Touching the stack at 4K increments is necessary to ensure 7502// that the guard pages used by the OS virtual memory manager are allocated in 7503// correct sequence. 7504SDValue 7505X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 7506 SelectionDAG &DAG) const { 7507 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && 7508 "This should be used only on Windows targets"); 7509 DebugLoc dl = Op.getDebugLoc(); 7510 7511 // Get the inputs. 7512 SDValue Chain = Op.getOperand(0); 7513 SDValue Size = Op.getOperand(1); 7514 // FIXME: Ensure alignment here 7515 7516 SDValue Flag; 7517 7518 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 7519 7520 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 7521 Flag = Chain.getValue(1); 7522 7523 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 7524 7525 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 7526 Flag = Chain.getValue(1); 7527 7528 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 7529 7530 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 7531 return DAG.getMergeValues(Ops1, 2, dl); 7532} 7533 7534SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 7535 MachineFunction &MF = DAG.getMachineFunction(); 7536 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 7537 7538 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 7539 DebugLoc DL = Op.getDebugLoc(); 7540 7541 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 7542 // vastart just stores the address of the VarArgsFrameIndex slot into the 7543 // memory location argument. 7544 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7545 getPointerTy()); 7546 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 7547 MachinePointerInfo(SV), false, false, 0); 7548 } 7549 7550 // __va_list_tag: 7551 // gp_offset (0 - 6 * 8) 7552 // fp_offset (48 - 48 + 8 * 16) 7553 // overflow_arg_area (point to parameters coming in memory). 7554 // reg_save_area 7555 SmallVector<SDValue, 8> MemOps; 7556 SDValue FIN = Op.getOperand(1); 7557 // Store gp_offset 7558 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 7559 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 7560 MVT::i32), 7561 FIN, MachinePointerInfo(SV), false, false, 0); 7562 MemOps.push_back(Store); 7563 7564 // Store fp_offset 7565 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7566 FIN, DAG.getIntPtrConstant(4)); 7567 Store = DAG.getStore(Op.getOperand(0), DL, 7568 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 7569 MVT::i32), 7570 FIN, MachinePointerInfo(SV, 4), false, false, 0); 7571 MemOps.push_back(Store); 7572 7573 // Store ptr to overflow_arg_area 7574 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7575 FIN, DAG.getIntPtrConstant(4)); 7576 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7577 getPointerTy()); 7578 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 7579 MachinePointerInfo(SV, 8), 7580 false, false, 0); 7581 MemOps.push_back(Store); 7582 7583 // Store ptr to reg_save_area. 7584 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7585 FIN, DAG.getIntPtrConstant(8)); 7586 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 7587 getPointerTy()); 7588 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 7589 MachinePointerInfo(SV, 16), false, false, 0); 7590 MemOps.push_back(Store); 7591 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 7592 &MemOps[0], MemOps.size()); 7593} 7594 7595SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 7596 assert(Subtarget->is64Bit() && 7597 "LowerVAARG only handles 64-bit va_arg!"); 7598 assert((Subtarget->isTargetLinux() || 7599 Subtarget->isTargetDarwin()) && 7600 "Unhandled target in LowerVAARG"); 7601 assert(Op.getNode()->getNumOperands() == 4); 7602 SDValue Chain = Op.getOperand(0); 7603 SDValue SrcPtr = Op.getOperand(1); 7604 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 7605 unsigned Align = Op.getConstantOperandVal(3); 7606 DebugLoc dl = Op.getDebugLoc(); 7607 7608 EVT ArgVT = Op.getNode()->getValueType(0); 7609 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 7610 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 7611 uint8_t ArgMode; 7612 7613 // Decide which area this value should be read from. 7614 // TODO: Implement the AMD64 ABI in its entirety. This simple 7615 // selection mechanism works only for the basic types. 7616 if (ArgVT == MVT::f80) { 7617 llvm_unreachable("va_arg for f80 not yet implemented"); 7618 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 7619 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 7620 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 7621 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 7622 } else { 7623 llvm_unreachable("Unhandled argument type in LowerVAARG"); 7624 } 7625 7626 if (ArgMode == 2) { 7627 // Sanity Check: Make sure using fp_offset makes sense. 7628 assert(!UseSoftFloat && 7629 !(DAG.getMachineFunction() 7630 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 7631 Subtarget->hasSSE1()); 7632 } 7633 7634 // Insert VAARG_64 node into the DAG 7635 // VAARG_64 returns two values: Variable Argument Address, Chain 7636 SmallVector<SDValue, 11> InstOps; 7637 InstOps.push_back(Chain); 7638 InstOps.push_back(SrcPtr); 7639 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 7640 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 7641 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 7642 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 7643 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 7644 VTs, &InstOps[0], InstOps.size(), 7645 MVT::i64, 7646 MachinePointerInfo(SV), 7647 /*Align=*/0, 7648 /*Volatile=*/false, 7649 /*ReadMem=*/true, 7650 /*WriteMem=*/true); 7651 Chain = VAARG.getValue(1); 7652 7653 // Load the next argument and return it 7654 return DAG.getLoad(ArgVT, dl, 7655 Chain, 7656 VAARG, 7657 MachinePointerInfo(), 7658 false, false, 0); 7659} 7660 7661SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 7662 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 7663 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 7664 SDValue Chain = Op.getOperand(0); 7665 SDValue DstPtr = Op.getOperand(1); 7666 SDValue SrcPtr = Op.getOperand(2); 7667 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 7668 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7669 DebugLoc DL = Op.getDebugLoc(); 7670 7671 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 7672 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 7673 false, 7674 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 7675} 7676 7677SDValue 7678X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 7679 DebugLoc dl = Op.getDebugLoc(); 7680 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7681 switch (IntNo) { 7682 default: return SDValue(); // Don't custom lower most intrinsics. 7683 // Comparison intrinsics. 7684 case Intrinsic::x86_sse_comieq_ss: 7685 case Intrinsic::x86_sse_comilt_ss: 7686 case Intrinsic::x86_sse_comile_ss: 7687 case Intrinsic::x86_sse_comigt_ss: 7688 case Intrinsic::x86_sse_comige_ss: 7689 case Intrinsic::x86_sse_comineq_ss: 7690 case Intrinsic::x86_sse_ucomieq_ss: 7691 case Intrinsic::x86_sse_ucomilt_ss: 7692 case Intrinsic::x86_sse_ucomile_ss: 7693 case Intrinsic::x86_sse_ucomigt_ss: 7694 case Intrinsic::x86_sse_ucomige_ss: 7695 case Intrinsic::x86_sse_ucomineq_ss: 7696 case Intrinsic::x86_sse2_comieq_sd: 7697 case Intrinsic::x86_sse2_comilt_sd: 7698 case Intrinsic::x86_sse2_comile_sd: 7699 case Intrinsic::x86_sse2_comigt_sd: 7700 case Intrinsic::x86_sse2_comige_sd: 7701 case Intrinsic::x86_sse2_comineq_sd: 7702 case Intrinsic::x86_sse2_ucomieq_sd: 7703 case Intrinsic::x86_sse2_ucomilt_sd: 7704 case Intrinsic::x86_sse2_ucomile_sd: 7705 case Intrinsic::x86_sse2_ucomigt_sd: 7706 case Intrinsic::x86_sse2_ucomige_sd: 7707 case Intrinsic::x86_sse2_ucomineq_sd: { 7708 unsigned Opc = 0; 7709 ISD::CondCode CC = ISD::SETCC_INVALID; 7710 switch (IntNo) { 7711 default: break; 7712 case Intrinsic::x86_sse_comieq_ss: 7713 case Intrinsic::x86_sse2_comieq_sd: 7714 Opc = X86ISD::COMI; 7715 CC = ISD::SETEQ; 7716 break; 7717 case Intrinsic::x86_sse_comilt_ss: 7718 case Intrinsic::x86_sse2_comilt_sd: 7719 Opc = X86ISD::COMI; 7720 CC = ISD::SETLT; 7721 break; 7722 case Intrinsic::x86_sse_comile_ss: 7723 case Intrinsic::x86_sse2_comile_sd: 7724 Opc = X86ISD::COMI; 7725 CC = ISD::SETLE; 7726 break; 7727 case Intrinsic::x86_sse_comigt_ss: 7728 case Intrinsic::x86_sse2_comigt_sd: 7729 Opc = X86ISD::COMI; 7730 CC = ISD::SETGT; 7731 break; 7732 case Intrinsic::x86_sse_comige_ss: 7733 case Intrinsic::x86_sse2_comige_sd: 7734 Opc = X86ISD::COMI; 7735 CC = ISD::SETGE; 7736 break; 7737 case Intrinsic::x86_sse_comineq_ss: 7738 case Intrinsic::x86_sse2_comineq_sd: 7739 Opc = X86ISD::COMI; 7740 CC = ISD::SETNE; 7741 break; 7742 case Intrinsic::x86_sse_ucomieq_ss: 7743 case Intrinsic::x86_sse2_ucomieq_sd: 7744 Opc = X86ISD::UCOMI; 7745 CC = ISD::SETEQ; 7746 break; 7747 case Intrinsic::x86_sse_ucomilt_ss: 7748 case Intrinsic::x86_sse2_ucomilt_sd: 7749 Opc = X86ISD::UCOMI; 7750 CC = ISD::SETLT; 7751 break; 7752 case Intrinsic::x86_sse_ucomile_ss: 7753 case Intrinsic::x86_sse2_ucomile_sd: 7754 Opc = X86ISD::UCOMI; 7755 CC = ISD::SETLE; 7756 break; 7757 case Intrinsic::x86_sse_ucomigt_ss: 7758 case Intrinsic::x86_sse2_ucomigt_sd: 7759 Opc = X86ISD::UCOMI; 7760 CC = ISD::SETGT; 7761 break; 7762 case Intrinsic::x86_sse_ucomige_ss: 7763 case Intrinsic::x86_sse2_ucomige_sd: 7764 Opc = X86ISD::UCOMI; 7765 CC = ISD::SETGE; 7766 break; 7767 case Intrinsic::x86_sse_ucomineq_ss: 7768 case Intrinsic::x86_sse2_ucomineq_sd: 7769 Opc = X86ISD::UCOMI; 7770 CC = ISD::SETNE; 7771 break; 7772 } 7773 7774 SDValue LHS = Op.getOperand(1); 7775 SDValue RHS = Op.getOperand(2); 7776 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 7777 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 7778 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 7779 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7780 DAG.getConstant(X86CC, MVT::i8), Cond); 7781 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7782 } 7783 // ptest and testp intrinsics. The intrinsic these come from are designed to 7784 // return an integer value, not just an instruction so lower it to the ptest 7785 // or testp pattern and a setcc for the result. 7786 case Intrinsic::x86_sse41_ptestz: 7787 case Intrinsic::x86_sse41_ptestc: 7788 case Intrinsic::x86_sse41_ptestnzc: 7789 case Intrinsic::x86_avx_ptestz_256: 7790 case Intrinsic::x86_avx_ptestc_256: 7791 case Intrinsic::x86_avx_ptestnzc_256: 7792 case Intrinsic::x86_avx_vtestz_ps: 7793 case Intrinsic::x86_avx_vtestc_ps: 7794 case Intrinsic::x86_avx_vtestnzc_ps: 7795 case Intrinsic::x86_avx_vtestz_pd: 7796 case Intrinsic::x86_avx_vtestc_pd: 7797 case Intrinsic::x86_avx_vtestnzc_pd: 7798 case Intrinsic::x86_avx_vtestz_ps_256: 7799 case Intrinsic::x86_avx_vtestc_ps_256: 7800 case Intrinsic::x86_avx_vtestnzc_ps_256: 7801 case Intrinsic::x86_avx_vtestz_pd_256: 7802 case Intrinsic::x86_avx_vtestc_pd_256: 7803 case Intrinsic::x86_avx_vtestnzc_pd_256: { 7804 bool IsTestPacked = false; 7805 unsigned X86CC = 0; 7806 switch (IntNo) { 7807 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 7808 case Intrinsic::x86_avx_vtestz_ps: 7809 case Intrinsic::x86_avx_vtestz_pd: 7810 case Intrinsic::x86_avx_vtestz_ps_256: 7811 case Intrinsic::x86_avx_vtestz_pd_256: 7812 IsTestPacked = true; // Fallthrough 7813 case Intrinsic::x86_sse41_ptestz: 7814 case Intrinsic::x86_avx_ptestz_256: 7815 // ZF = 1 7816 X86CC = X86::COND_E; 7817 break; 7818 case Intrinsic::x86_avx_vtestc_ps: 7819 case Intrinsic::x86_avx_vtestc_pd: 7820 case Intrinsic::x86_avx_vtestc_ps_256: 7821 case Intrinsic::x86_avx_vtestc_pd_256: 7822 IsTestPacked = true; // Fallthrough 7823 case Intrinsic::x86_sse41_ptestc: 7824 case Intrinsic::x86_avx_ptestc_256: 7825 // CF = 1 7826 X86CC = X86::COND_B; 7827 break; 7828 case Intrinsic::x86_avx_vtestnzc_ps: 7829 case Intrinsic::x86_avx_vtestnzc_pd: 7830 case Intrinsic::x86_avx_vtestnzc_ps_256: 7831 case Intrinsic::x86_avx_vtestnzc_pd_256: 7832 IsTestPacked = true; // Fallthrough 7833 case Intrinsic::x86_sse41_ptestnzc: 7834 case Intrinsic::x86_avx_ptestnzc_256: 7835 // ZF and CF = 0 7836 X86CC = X86::COND_A; 7837 break; 7838 } 7839 7840 SDValue LHS = Op.getOperand(1); 7841 SDValue RHS = Op.getOperand(2); 7842 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 7843 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 7844 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 7845 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 7846 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7847 } 7848 7849 // Fix vector shift instructions where the last operand is a non-immediate 7850 // i32 value. 7851 case Intrinsic::x86_sse2_pslli_w: 7852 case Intrinsic::x86_sse2_pslli_d: 7853 case Intrinsic::x86_sse2_pslli_q: 7854 case Intrinsic::x86_sse2_psrli_w: 7855 case Intrinsic::x86_sse2_psrli_d: 7856 case Intrinsic::x86_sse2_psrli_q: 7857 case Intrinsic::x86_sse2_psrai_w: 7858 case Intrinsic::x86_sse2_psrai_d: 7859 case Intrinsic::x86_mmx_pslli_w: 7860 case Intrinsic::x86_mmx_pslli_d: 7861 case Intrinsic::x86_mmx_pslli_q: 7862 case Intrinsic::x86_mmx_psrli_w: 7863 case Intrinsic::x86_mmx_psrli_d: 7864 case Intrinsic::x86_mmx_psrli_q: 7865 case Intrinsic::x86_mmx_psrai_w: 7866 case Intrinsic::x86_mmx_psrai_d: { 7867 SDValue ShAmt = Op.getOperand(2); 7868 if (isa<ConstantSDNode>(ShAmt)) 7869 return SDValue(); 7870 7871 unsigned NewIntNo = 0; 7872 EVT ShAmtVT = MVT::v4i32; 7873 switch (IntNo) { 7874 case Intrinsic::x86_sse2_pslli_w: 7875 NewIntNo = Intrinsic::x86_sse2_psll_w; 7876 break; 7877 case Intrinsic::x86_sse2_pslli_d: 7878 NewIntNo = Intrinsic::x86_sse2_psll_d; 7879 break; 7880 case Intrinsic::x86_sse2_pslli_q: 7881 NewIntNo = Intrinsic::x86_sse2_psll_q; 7882 break; 7883 case Intrinsic::x86_sse2_psrli_w: 7884 NewIntNo = Intrinsic::x86_sse2_psrl_w; 7885 break; 7886 case Intrinsic::x86_sse2_psrli_d: 7887 NewIntNo = Intrinsic::x86_sse2_psrl_d; 7888 break; 7889 case Intrinsic::x86_sse2_psrli_q: 7890 NewIntNo = Intrinsic::x86_sse2_psrl_q; 7891 break; 7892 case Intrinsic::x86_sse2_psrai_w: 7893 NewIntNo = Intrinsic::x86_sse2_psra_w; 7894 break; 7895 case Intrinsic::x86_sse2_psrai_d: 7896 NewIntNo = Intrinsic::x86_sse2_psra_d; 7897 break; 7898 default: { 7899 ShAmtVT = MVT::v2i32; 7900 switch (IntNo) { 7901 case Intrinsic::x86_mmx_pslli_w: 7902 NewIntNo = Intrinsic::x86_mmx_psll_w; 7903 break; 7904 case Intrinsic::x86_mmx_pslli_d: 7905 NewIntNo = Intrinsic::x86_mmx_psll_d; 7906 break; 7907 case Intrinsic::x86_mmx_pslli_q: 7908 NewIntNo = Intrinsic::x86_mmx_psll_q; 7909 break; 7910 case Intrinsic::x86_mmx_psrli_w: 7911 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7912 break; 7913 case Intrinsic::x86_mmx_psrli_d: 7914 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7915 break; 7916 case Intrinsic::x86_mmx_psrli_q: 7917 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7918 break; 7919 case Intrinsic::x86_mmx_psrai_w: 7920 NewIntNo = Intrinsic::x86_mmx_psra_w; 7921 break; 7922 case Intrinsic::x86_mmx_psrai_d: 7923 NewIntNo = Intrinsic::x86_mmx_psra_d; 7924 break; 7925 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7926 } 7927 break; 7928 } 7929 } 7930 7931 // The vector shift intrinsics with scalars uses 32b shift amounts but 7932 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7933 // to be zero. 7934 SDValue ShOps[4]; 7935 ShOps[0] = ShAmt; 7936 ShOps[1] = DAG.getConstant(0, MVT::i32); 7937 if (ShAmtVT == MVT::v4i32) { 7938 ShOps[2] = DAG.getUNDEF(MVT::i32); 7939 ShOps[3] = DAG.getUNDEF(MVT::i32); 7940 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7941 } else { 7942 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7943// FIXME this must be lowered to get rid of the invalid type. 7944 } 7945 7946 EVT VT = Op.getValueType(); 7947 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 7948 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7949 DAG.getConstant(NewIntNo, MVT::i32), 7950 Op.getOperand(1), ShAmt); 7951 } 7952 } 7953} 7954 7955SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 7956 SelectionDAG &DAG) const { 7957 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7958 MFI->setReturnAddressIsTaken(true); 7959 7960 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7961 DebugLoc dl = Op.getDebugLoc(); 7962 7963 if (Depth > 0) { 7964 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7965 SDValue Offset = 7966 DAG.getConstant(TD->getPointerSize(), 7967 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7968 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7969 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7970 FrameAddr, Offset), 7971 MachinePointerInfo(), false, false, 0); 7972 } 7973 7974 // Just load the return address. 7975 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7976 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7977 RetAddrFI, MachinePointerInfo(), false, false, 0); 7978} 7979 7980SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 7981 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7982 MFI->setFrameAddressIsTaken(true); 7983 7984 EVT VT = Op.getValueType(); 7985 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7986 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7987 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7988 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7989 while (Depth--) 7990 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 7991 MachinePointerInfo(), 7992 false, false, 0); 7993 return FrameAddr; 7994} 7995 7996SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7997 SelectionDAG &DAG) const { 7998 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7999} 8000 8001SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 8002 MachineFunction &MF = DAG.getMachineFunction(); 8003 SDValue Chain = Op.getOperand(0); 8004 SDValue Offset = Op.getOperand(1); 8005 SDValue Handler = Op.getOperand(2); 8006 DebugLoc dl = Op.getDebugLoc(); 8007 8008 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 8009 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 8010 getPointerTy()); 8011 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 8012 8013 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 8014 DAG.getIntPtrConstant(TD->getPointerSize())); 8015 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 8016 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 8017 false, false, 0); 8018 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 8019 MF.getRegInfo().addLiveOut(StoreAddrReg); 8020 8021 return DAG.getNode(X86ISD::EH_RETURN, dl, 8022 MVT::Other, 8023 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 8024} 8025 8026SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 8027 SelectionDAG &DAG) const { 8028 SDValue Root = Op.getOperand(0); 8029 SDValue Trmp = Op.getOperand(1); // trampoline 8030 SDValue FPtr = Op.getOperand(2); // nested function 8031 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 8032 DebugLoc dl = Op.getDebugLoc(); 8033 8034 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8035 8036 if (Subtarget->is64Bit()) { 8037 SDValue OutChains[6]; 8038 8039 // Large code-model. 8040 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 8041 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 8042 8043 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 8044 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 8045 8046 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 8047 8048 // Load the pointer to the nested function into R11. 8049 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 8050 SDValue Addr = Trmp; 8051 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8052 Addr, MachinePointerInfo(TrmpAddr), 8053 false, false, 0); 8054 8055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8056 DAG.getConstant(2, MVT::i64)); 8057 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 8058 MachinePointerInfo(TrmpAddr, 2), 8059 false, false, 2); 8060 8061 // Load the 'nest' parameter value into R10. 8062 // R10 is specified in X86CallingConv.td 8063 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 8064 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8065 DAG.getConstant(10, MVT::i64)); 8066 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8067 Addr, MachinePointerInfo(TrmpAddr, 10), 8068 false, false, 0); 8069 8070 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8071 DAG.getConstant(12, MVT::i64)); 8072 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 8073 MachinePointerInfo(TrmpAddr, 12), 8074 false, false, 2); 8075 8076 // Jump to the nested function. 8077 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 8078 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8079 DAG.getConstant(20, MVT::i64)); 8080 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8081 Addr, MachinePointerInfo(TrmpAddr, 20), 8082 false, false, 0); 8083 8084 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 8085 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8086 DAG.getConstant(22, MVT::i64)); 8087 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 8088 MachinePointerInfo(TrmpAddr, 22), 8089 false, false, 0); 8090 8091 SDValue Ops[] = 8092 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 8093 return DAG.getMergeValues(Ops, 2, dl); 8094 } else { 8095 const Function *Func = 8096 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 8097 CallingConv::ID CC = Func->getCallingConv(); 8098 unsigned NestReg; 8099 8100 switch (CC) { 8101 default: 8102 llvm_unreachable("Unsupported calling convention"); 8103 case CallingConv::C: 8104 case CallingConv::X86_StdCall: { 8105 // Pass 'nest' parameter in ECX. 8106 // Must be kept in sync with X86CallingConv.td 8107 NestReg = X86::ECX; 8108 8109 // Check that ECX wasn't needed by an 'inreg' parameter. 8110 const FunctionType *FTy = Func->getFunctionType(); 8111 const AttrListPtr &Attrs = Func->getAttributes(); 8112 8113 if (!Attrs.isEmpty() && !Func->isVarArg()) { 8114 unsigned InRegCount = 0; 8115 unsigned Idx = 1; 8116 8117 for (FunctionType::param_iterator I = FTy->param_begin(), 8118 E = FTy->param_end(); I != E; ++I, ++Idx) 8119 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 8120 // FIXME: should only count parameters that are lowered to integers. 8121 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 8122 8123 if (InRegCount > 2) { 8124 report_fatal_error("Nest register in use - reduce number of inreg" 8125 " parameters!"); 8126 } 8127 } 8128 break; 8129 } 8130 case CallingConv::X86_FastCall: 8131 case CallingConv::X86_ThisCall: 8132 case CallingConv::Fast: 8133 // Pass 'nest' parameter in EAX. 8134 // Must be kept in sync with X86CallingConv.td 8135 NestReg = X86::EAX; 8136 break; 8137 } 8138 8139 SDValue OutChains[4]; 8140 SDValue Addr, Disp; 8141 8142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8143 DAG.getConstant(10, MVT::i32)); 8144 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 8145 8146 // This is storing the opcode for MOV32ri. 8147 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 8148 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 8149 OutChains[0] = DAG.getStore(Root, dl, 8150 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 8151 Trmp, MachinePointerInfo(TrmpAddr), 8152 false, false, 0); 8153 8154 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8155 DAG.getConstant(1, MVT::i32)); 8156 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 8157 MachinePointerInfo(TrmpAddr, 1), 8158 false, false, 1); 8159 8160 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 8161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8162 DAG.getConstant(5, MVT::i32)); 8163 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 8164 MachinePointerInfo(TrmpAddr, 5), 8165 false, false, 1); 8166 8167 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8168 DAG.getConstant(6, MVT::i32)); 8169 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 8170 MachinePointerInfo(TrmpAddr, 6), 8171 false, false, 1); 8172 8173 SDValue Ops[] = 8174 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 8175 return DAG.getMergeValues(Ops, 2, dl); 8176 } 8177} 8178 8179SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 8180 SelectionDAG &DAG) const { 8181 /* 8182 The rounding mode is in bits 11:10 of FPSR, and has the following 8183 settings: 8184 00 Round to nearest 8185 01 Round to -inf 8186 10 Round to +inf 8187 11 Round to 0 8188 8189 FLT_ROUNDS, on the other hand, expects the following: 8190 -1 Undefined 8191 0 Round to 0 8192 1 Round to nearest 8193 2 Round to +inf 8194 3 Round to -inf 8195 8196 To perform the conversion, we do: 8197 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 8198 */ 8199 8200 MachineFunction &MF = DAG.getMachineFunction(); 8201 const TargetMachine &TM = MF.getTarget(); 8202 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 8203 unsigned StackAlignment = TFI.getStackAlignment(); 8204 EVT VT = Op.getValueType(); 8205 DebugLoc DL = Op.getDebugLoc(); 8206 8207 // Save FP Control Word to stack slot 8208 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 8209 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8210 8211 8212 MachineMemOperand *MMO = 8213 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8214 MachineMemOperand::MOStore, 2, 2); 8215 8216 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 8217 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 8218 DAG.getVTList(MVT::Other), 8219 Ops, 2, MVT::i16, MMO); 8220 8221 // Load FP Control Word from stack slot 8222 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 8223 MachinePointerInfo(), false, false, 0); 8224 8225 // Transform as necessary 8226 SDValue CWD1 = 8227 DAG.getNode(ISD::SRL, DL, MVT::i16, 8228 DAG.getNode(ISD::AND, DL, MVT::i16, 8229 CWD, DAG.getConstant(0x800, MVT::i16)), 8230 DAG.getConstant(11, MVT::i8)); 8231 SDValue CWD2 = 8232 DAG.getNode(ISD::SRL, DL, MVT::i16, 8233 DAG.getNode(ISD::AND, DL, MVT::i16, 8234 CWD, DAG.getConstant(0x400, MVT::i16)), 8235 DAG.getConstant(9, MVT::i8)); 8236 8237 SDValue RetVal = 8238 DAG.getNode(ISD::AND, DL, MVT::i16, 8239 DAG.getNode(ISD::ADD, DL, MVT::i16, 8240 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 8241 DAG.getConstant(1, MVT::i16)), 8242 DAG.getConstant(3, MVT::i16)); 8243 8244 8245 return DAG.getNode((VT.getSizeInBits() < 16 ? 8246 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 8247} 8248 8249SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 8250 EVT VT = Op.getValueType(); 8251 EVT OpVT = VT; 8252 unsigned NumBits = VT.getSizeInBits(); 8253 DebugLoc dl = Op.getDebugLoc(); 8254 8255 Op = Op.getOperand(0); 8256 if (VT == MVT::i8) { 8257 // Zero extend to i32 since there is not an i8 bsr. 8258 OpVT = MVT::i32; 8259 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 8260 } 8261 8262 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 8263 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 8264 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 8265 8266 // If src is zero (i.e. bsr sets ZF), returns NumBits. 8267 SDValue Ops[] = { 8268 Op, 8269 DAG.getConstant(NumBits+NumBits-1, OpVT), 8270 DAG.getConstant(X86::COND_E, MVT::i8), 8271 Op.getValue(1) 8272 }; 8273 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 8274 8275 // Finally xor with NumBits-1. 8276 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 8277 8278 if (VT == MVT::i8) 8279 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 8280 return Op; 8281} 8282 8283SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 8284 EVT VT = Op.getValueType(); 8285 EVT OpVT = VT; 8286 unsigned NumBits = VT.getSizeInBits(); 8287 DebugLoc dl = Op.getDebugLoc(); 8288 8289 Op = Op.getOperand(0); 8290 if (VT == MVT::i8) { 8291 OpVT = MVT::i32; 8292 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 8293 } 8294 8295 // Issue a bsf (scan bits forward) which also sets EFLAGS. 8296 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 8297 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 8298 8299 // If src is zero (i.e. bsf sets ZF), returns NumBits. 8300 SDValue Ops[] = { 8301 Op, 8302 DAG.getConstant(NumBits, OpVT), 8303 DAG.getConstant(X86::COND_E, MVT::i8), 8304 Op.getValue(1) 8305 }; 8306 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 8307 8308 if (VT == MVT::i8) 8309 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 8310 return Op; 8311} 8312 8313SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 8314 EVT VT = Op.getValueType(); 8315 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 8316 DebugLoc dl = Op.getDebugLoc(); 8317 8318 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 8319 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 8320 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 8321 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 8322 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 8323 // 8324 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 8325 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 8326 // return AloBlo + AloBhi + AhiBlo; 8327 8328 SDValue A = Op.getOperand(0); 8329 SDValue B = Op.getOperand(1); 8330 8331 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8332 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8333 A, DAG.getConstant(32, MVT::i32)); 8334 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8335 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8336 B, DAG.getConstant(32, MVT::i32)); 8337 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8338 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8339 A, B); 8340 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8341 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8342 A, Bhi); 8343 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8344 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8345 Ahi, B); 8346 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8347 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8348 AloBhi, DAG.getConstant(32, MVT::i32)); 8349 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8350 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8351 AhiBlo, DAG.getConstant(32, MVT::i32)); 8352 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 8353 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 8354 return Res; 8355} 8356 8357SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { 8358 EVT VT = Op.getValueType(); 8359 DebugLoc dl = Op.getDebugLoc(); 8360 SDValue R = Op.getOperand(0); 8361 8362 LLVMContext *Context = DAG.getContext(); 8363 8364 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later"); 8365 8366 if (VT == MVT::v4i32) { 8367 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8368 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8369 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 8370 8371 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 8372 8373 std::vector<Constant*> CV(4, CI); 8374 Constant *C = ConstantVector::get(CV); 8375 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8376 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8377 MachinePointerInfo::getConstantPool(), 8378 false, false, 16); 8379 8380 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 8381 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 8382 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 8383 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 8384 } 8385 if (VT == MVT::v16i8) { 8386 // a = a << 5; 8387 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8388 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8389 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 8390 8391 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 8392 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 8393 8394 std::vector<Constant*> CVM1(16, CM1); 8395 std::vector<Constant*> CVM2(16, CM2); 8396 Constant *C = ConstantVector::get(CVM1); 8397 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8398 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8399 MachinePointerInfo::getConstantPool(), 8400 false, false, 16); 8401 8402 // r = pblendv(r, psllw(r & (char16)15, 4), a); 8403 M = DAG.getNode(ISD::AND, dl, VT, R, M); 8404 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8405 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8406 DAG.getConstant(4, MVT::i32)); 8407 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8408 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8409 R, M, Op); 8410 // a += a 8411 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8412 8413 C = ConstantVector::get(CVM2); 8414 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8415 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8416 MachinePointerInfo::getConstantPool(), 8417 false, false, 16); 8418 8419 // r = pblendv(r, psllw(r & (char16)63, 2), a); 8420 M = DAG.getNode(ISD::AND, dl, VT, R, M); 8421 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8422 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8423 DAG.getConstant(2, MVT::i32)); 8424 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8425 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8426 R, M, Op); 8427 // a += a 8428 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8429 8430 // return pblendv(r, r+r, a); 8431 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8432 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8433 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 8434 return R; 8435 } 8436 return SDValue(); 8437} 8438 8439SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 8440 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 8441 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 8442 // looks for this combo and may remove the "setcc" instruction if the "setcc" 8443 // has only one use. 8444 SDNode *N = Op.getNode(); 8445 SDValue LHS = N->getOperand(0); 8446 SDValue RHS = N->getOperand(1); 8447 unsigned BaseOp = 0; 8448 unsigned Cond = 0; 8449 DebugLoc dl = Op.getDebugLoc(); 8450 8451 switch (Op.getOpcode()) { 8452 default: llvm_unreachable("Unknown ovf instruction!"); 8453 case ISD::SADDO: 8454 // A subtract of one will be selected as a INC. Note that INC doesn't 8455 // set CF, so we can't do this for UADDO. 8456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 8457 if (C->getAPIntValue() == 1) { 8458 BaseOp = X86ISD::INC; 8459 Cond = X86::COND_O; 8460 break; 8461 } 8462 BaseOp = X86ISD::ADD; 8463 Cond = X86::COND_O; 8464 break; 8465 case ISD::UADDO: 8466 BaseOp = X86ISD::ADD; 8467 Cond = X86::COND_B; 8468 break; 8469 case ISD::SSUBO: 8470 // A subtract of one will be selected as a DEC. Note that DEC doesn't 8471 // set CF, so we can't do this for USUBO. 8472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 8473 if (C->getAPIntValue() == 1) { 8474 BaseOp = X86ISD::DEC; 8475 Cond = X86::COND_O; 8476 break; 8477 } 8478 BaseOp = X86ISD::SUB; 8479 Cond = X86::COND_O; 8480 break; 8481 case ISD::USUBO: 8482 BaseOp = X86ISD::SUB; 8483 Cond = X86::COND_B; 8484 break; 8485 case ISD::SMULO: 8486 BaseOp = X86ISD::SMUL; 8487 Cond = X86::COND_O; 8488 break; 8489 case ISD::UMULO: 8490 BaseOp = X86ISD::UMUL; 8491 Cond = X86::COND_B; 8492 break; 8493 } 8494 8495 // Also sets EFLAGS. 8496 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 8497 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 8498 8499 SDValue SetCC = 8500 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 8501 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 8502 8503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 8504 return Sum; 8505} 8506 8507SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 8508 DebugLoc dl = Op.getDebugLoc(); 8509 8510 if (!Subtarget->hasSSE2()) { 8511 SDValue Chain = Op.getOperand(0); 8512 SDValue Zero = DAG.getConstant(0, 8513 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8514 SDValue Ops[] = { 8515 DAG.getRegister(X86::ESP, MVT::i32), // Base 8516 DAG.getTargetConstant(1, MVT::i8), // Scale 8517 DAG.getRegister(0, MVT::i32), // Index 8518 DAG.getTargetConstant(0, MVT::i32), // Disp 8519 DAG.getRegister(0, MVT::i32), // Segment. 8520 Zero, 8521 Chain 8522 }; 8523 SDNode *Res = 8524 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 8525 array_lengthof(Ops)); 8526 return SDValue(Res, 0); 8527 } 8528 8529 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 8530 if (!isDev) 8531 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 8532 8533 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 8534 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 8535 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 8536 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 8537 8538 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 8539 if (!Op1 && !Op2 && !Op3 && Op4) 8540 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 8541 8542 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 8543 if (Op1 && !Op2 && !Op3 && !Op4) 8544 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 8545 8546 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 8547 // (MFENCE)>; 8548 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 8549} 8550 8551SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 8552 EVT T = Op.getValueType(); 8553 DebugLoc DL = Op.getDebugLoc(); 8554 unsigned Reg = 0; 8555 unsigned size = 0; 8556 switch(T.getSimpleVT().SimpleTy) { 8557 default: 8558 assert(false && "Invalid value type!"); 8559 case MVT::i8: Reg = X86::AL; size = 1; break; 8560 case MVT::i16: Reg = X86::AX; size = 2; break; 8561 case MVT::i32: Reg = X86::EAX; size = 4; break; 8562 case MVT::i64: 8563 assert(Subtarget->is64Bit() && "Node not type legal!"); 8564 Reg = X86::RAX; size = 8; 8565 break; 8566 } 8567 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 8568 Op.getOperand(2), SDValue()); 8569 SDValue Ops[] = { cpIn.getValue(0), 8570 Op.getOperand(1), 8571 Op.getOperand(3), 8572 DAG.getTargetConstant(size, MVT::i8), 8573 cpIn.getValue(1) }; 8574 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8575 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 8576 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 8577 Ops, 5, T, MMO); 8578 SDValue cpOut = 8579 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 8580 return cpOut; 8581} 8582 8583SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 8584 SelectionDAG &DAG) const { 8585 assert(Subtarget->is64Bit() && "Result not type legalized?"); 8586 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8587 SDValue TheChain = Op.getOperand(0); 8588 DebugLoc dl = Op.getDebugLoc(); 8589 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8590 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 8591 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 8592 rax.getValue(2)); 8593 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 8594 DAG.getConstant(32, MVT::i8)); 8595 SDValue Ops[] = { 8596 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 8597 rdx.getValue(1) 8598 }; 8599 return DAG.getMergeValues(Ops, 2, dl); 8600} 8601 8602SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 8603 SelectionDAG &DAG) const { 8604 EVT SrcVT = Op.getOperand(0).getValueType(); 8605 EVT DstVT = Op.getValueType(); 8606 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && 8607 Subtarget->hasMMX() && !DisableMMX) && 8608 "Unexpected custom BITCAST"); 8609 assert((DstVT == MVT::i64 || 8610 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 8611 "Unexpected custom BITCAST"); 8612 // i64 <=> MMX conversions are Legal. 8613 if (SrcVT==MVT::i64 && DstVT.isVector()) 8614 return Op; 8615 if (DstVT==MVT::i64 && SrcVT.isVector()) 8616 return Op; 8617 // MMX <=> MMX conversions are Legal. 8618 if (SrcVT.isVector() && DstVT.isVector()) 8619 return Op; 8620 // All other conversions need to be expanded. 8621 return SDValue(); 8622} 8623SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 8624 SDNode *Node = Op.getNode(); 8625 DebugLoc dl = Node->getDebugLoc(); 8626 EVT T = Node->getValueType(0); 8627 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 8628 DAG.getConstant(0, T), Node->getOperand(2)); 8629 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 8630 cast<AtomicSDNode>(Node)->getMemoryVT(), 8631 Node->getOperand(0), 8632 Node->getOperand(1), negOp, 8633 cast<AtomicSDNode>(Node)->getSrcValue(), 8634 cast<AtomicSDNode>(Node)->getAlignment()); 8635} 8636 8637/// LowerOperation - Provide custom lowering hooks for some operations. 8638/// 8639SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 8640 switch (Op.getOpcode()) { 8641 default: llvm_unreachable("Should not custom lower this!"); 8642 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 8643 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 8644 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 8645 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 8646 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 8647 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 8648 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 8649 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 8650 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 8651 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 8652 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 8653 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 8654 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 8655 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 8656 case ISD::SHL_PARTS: 8657 case ISD::SRA_PARTS: 8658 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 8659 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 8660 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 8661 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 8662 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 8663 case ISD::FABS: return LowerFABS(Op, DAG); 8664 case ISD::FNEG: return LowerFNEG(Op, DAG); 8665 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 8666 case ISD::SETCC: return LowerSETCC(Op, DAG); 8667 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 8668 case ISD::SELECT: return LowerSELECT(Op, DAG); 8669 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 8670 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 8671 case ISD::VASTART: return LowerVASTART(Op, DAG); 8672 case ISD::VAARG: return LowerVAARG(Op, DAG); 8673 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 8674 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 8675 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 8676 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 8677 case ISD::FRAME_TO_ARGS_OFFSET: 8678 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 8679 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 8680 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 8681 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 8682 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 8683 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 8684 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 8685 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 8686 case ISD::SHL: return LowerSHL(Op, DAG); 8687 case ISD::SADDO: 8688 case ISD::UADDO: 8689 case ISD::SSUBO: 8690 case ISD::USUBO: 8691 case ISD::SMULO: 8692 case ISD::UMULO: return LowerXALUO(Op, DAG); 8693 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 8694 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 8695 } 8696} 8697 8698void X86TargetLowering:: 8699ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 8700 SelectionDAG &DAG, unsigned NewOp) const { 8701 EVT T = Node->getValueType(0); 8702 DebugLoc dl = Node->getDebugLoc(); 8703 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 8704 8705 SDValue Chain = Node->getOperand(0); 8706 SDValue In1 = Node->getOperand(1); 8707 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8708 Node->getOperand(2), DAG.getIntPtrConstant(0)); 8709 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8710 Node->getOperand(2), DAG.getIntPtrConstant(1)); 8711 SDValue Ops[] = { Chain, In1, In2L, In2H }; 8712 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 8713 SDValue Result = 8714 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 8715 cast<MemSDNode>(Node)->getMemOperand()); 8716 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 8717 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8718 Results.push_back(Result.getValue(2)); 8719} 8720 8721/// ReplaceNodeResults - Replace a node with an illegal result type 8722/// with a new node built out of custom code. 8723void X86TargetLowering::ReplaceNodeResults(SDNode *N, 8724 SmallVectorImpl<SDValue>&Results, 8725 SelectionDAG &DAG) const { 8726 DebugLoc dl = N->getDebugLoc(); 8727 switch (N->getOpcode()) { 8728 default: 8729 assert(false && "Do not know how to custom type legalize this operation!"); 8730 return; 8731 case ISD::FP_TO_SINT: { 8732 std::pair<SDValue,SDValue> Vals = 8733 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 8734 SDValue FIST = Vals.first, StackSlot = Vals.second; 8735 if (FIST.getNode() != 0) { 8736 EVT VT = N->getValueType(0); 8737 // Return a load from the stack slot. 8738 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 8739 MachinePointerInfo(), false, false, 0)); 8740 } 8741 return; 8742 } 8743 case ISD::READCYCLECOUNTER: { 8744 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8745 SDValue TheChain = N->getOperand(0); 8746 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8747 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 8748 rd.getValue(1)); 8749 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 8750 eax.getValue(2)); 8751 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 8752 SDValue Ops[] = { eax, edx }; 8753 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 8754 Results.push_back(edx.getValue(1)); 8755 return; 8756 } 8757 case ISD::ATOMIC_CMP_SWAP: { 8758 EVT T = N->getValueType(0); 8759 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 8760 SDValue cpInL, cpInH; 8761 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8762 DAG.getConstant(0, MVT::i32)); 8763 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8764 DAG.getConstant(1, MVT::i32)); 8765 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 8766 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 8767 cpInL.getValue(1)); 8768 SDValue swapInL, swapInH; 8769 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8770 DAG.getConstant(0, MVT::i32)); 8771 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8772 DAG.getConstant(1, MVT::i32)); 8773 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 8774 cpInH.getValue(1)); 8775 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 8776 swapInL.getValue(1)); 8777 SDValue Ops[] = { swapInH.getValue(0), 8778 N->getOperand(1), 8779 swapInH.getValue(1) }; 8780 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8781 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 8782 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, 8783 Ops, 3, T, MMO); 8784 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 8785 MVT::i32, Result.getValue(1)); 8786 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 8787 MVT::i32, cpOutL.getValue(2)); 8788 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 8789 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8790 Results.push_back(cpOutH.getValue(1)); 8791 return; 8792 } 8793 case ISD::ATOMIC_LOAD_ADD: 8794 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 8795 return; 8796 case ISD::ATOMIC_LOAD_AND: 8797 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 8798 return; 8799 case ISD::ATOMIC_LOAD_NAND: 8800 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 8801 return; 8802 case ISD::ATOMIC_LOAD_OR: 8803 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 8804 return; 8805 case ISD::ATOMIC_LOAD_SUB: 8806 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 8807 return; 8808 case ISD::ATOMIC_LOAD_XOR: 8809 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 8810 return; 8811 case ISD::ATOMIC_SWAP: 8812 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 8813 return; 8814 } 8815} 8816 8817const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 8818 switch (Opcode) { 8819 default: return NULL; 8820 case X86ISD::BSF: return "X86ISD::BSF"; 8821 case X86ISD::BSR: return "X86ISD::BSR"; 8822 case X86ISD::SHLD: return "X86ISD::SHLD"; 8823 case X86ISD::SHRD: return "X86ISD::SHRD"; 8824 case X86ISD::FAND: return "X86ISD::FAND"; 8825 case X86ISD::FOR: return "X86ISD::FOR"; 8826 case X86ISD::FXOR: return "X86ISD::FXOR"; 8827 case X86ISD::FSRL: return "X86ISD::FSRL"; 8828 case X86ISD::FILD: return "X86ISD::FILD"; 8829 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 8830 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 8831 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 8832 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 8833 case X86ISD::FLD: return "X86ISD::FLD"; 8834 case X86ISD::FST: return "X86ISD::FST"; 8835 case X86ISD::CALL: return "X86ISD::CALL"; 8836 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 8837 case X86ISD::BT: return "X86ISD::BT"; 8838 case X86ISD::CMP: return "X86ISD::CMP"; 8839 case X86ISD::COMI: return "X86ISD::COMI"; 8840 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 8841 case X86ISD::SETCC: return "X86ISD::SETCC"; 8842 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 8843 case X86ISD::CMOV: return "X86ISD::CMOV"; 8844 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 8845 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 8846 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 8847 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 8848 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 8849 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 8850 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 8851 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 8852 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 8853 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 8854 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 8855 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 8856 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 8857 case X86ISD::FMAX: return "X86ISD::FMAX"; 8858 case X86ISD::FMIN: return "X86ISD::FMIN"; 8859 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 8860 case X86ISD::FRCP: return "X86ISD::FRCP"; 8861 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 8862 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 8863 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 8864 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 8865 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 8866 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 8867 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 8868 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 8869 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 8870 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 8871 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 8872 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 8873 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 8874 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 8875 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 8876 case X86ISD::VSHL: return "X86ISD::VSHL"; 8877 case X86ISD::VSRL: return "X86ISD::VSRL"; 8878 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 8879 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 8880 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 8881 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 8882 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 8883 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 8884 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 8885 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 8886 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 8887 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 8888 case X86ISD::ADD: return "X86ISD::ADD"; 8889 case X86ISD::SUB: return "X86ISD::SUB"; 8890 case X86ISD::SMUL: return "X86ISD::SMUL"; 8891 case X86ISD::UMUL: return "X86ISD::UMUL"; 8892 case X86ISD::INC: return "X86ISD::INC"; 8893 case X86ISD::DEC: return "X86ISD::DEC"; 8894 case X86ISD::OR: return "X86ISD::OR"; 8895 case X86ISD::XOR: return "X86ISD::XOR"; 8896 case X86ISD::AND: return "X86ISD::AND"; 8897 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 8898 case X86ISD::PTEST: return "X86ISD::PTEST"; 8899 case X86ISD::TESTP: return "X86ISD::TESTP"; 8900 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 8901 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 8902 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 8903 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 8904 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 8905 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 8906 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 8907 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 8908 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 8909 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 8910 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 8911 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 8912 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 8913 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 8914 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 8915 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 8916 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 8917 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 8918 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 8919 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 8920 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 8921 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 8922 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 8923 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 8924 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 8925 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 8926 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 8927 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 8928 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 8929 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 8930 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 8931 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 8932 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 8933 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 8934 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 8935 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 8936 } 8937} 8938 8939// isLegalAddressingMode - Return true if the addressing mode represented 8940// by AM is legal for this target, for a load/store of the specified type. 8941bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 8942 const Type *Ty) const { 8943 // X86 supports extremely general addressing modes. 8944 CodeModel::Model M = getTargetMachine().getCodeModel(); 8945 Reloc::Model R = getTargetMachine().getRelocationModel(); 8946 8947 // X86 allows a sign-extended 32-bit immediate field as a displacement. 8948 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 8949 return false; 8950 8951 if (AM.BaseGV) { 8952 unsigned GVFlags = 8953 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 8954 8955 // If a reference to this global requires an extra load, we can't fold it. 8956 if (isGlobalStubReference(GVFlags)) 8957 return false; 8958 8959 // If BaseGV requires a register for the PIC base, we cannot also have a 8960 // BaseReg specified. 8961 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 8962 return false; 8963 8964 // If lower 4G is not available, then we must use rip-relative addressing. 8965 if ((M != CodeModel::Small || R != Reloc::Static) && 8966 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 8967 return false; 8968 } 8969 8970 switch (AM.Scale) { 8971 case 0: 8972 case 1: 8973 case 2: 8974 case 4: 8975 case 8: 8976 // These scales always work. 8977 break; 8978 case 3: 8979 case 5: 8980 case 9: 8981 // These scales are formed with basereg+scalereg. Only accept if there is 8982 // no basereg yet. 8983 if (AM.HasBaseReg) 8984 return false; 8985 break; 8986 default: // Other stuff never works. 8987 return false; 8988 } 8989 8990 return true; 8991} 8992 8993 8994bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 8995 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 8996 return false; 8997 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 8998 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 8999 if (NumBits1 <= NumBits2) 9000 return false; 9001 return true; 9002} 9003 9004bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 9005 if (!VT1.isInteger() || !VT2.isInteger()) 9006 return false; 9007 unsigned NumBits1 = VT1.getSizeInBits(); 9008 unsigned NumBits2 = VT2.getSizeInBits(); 9009 if (NumBits1 <= NumBits2) 9010 return false; 9011 return true; 9012} 9013 9014bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 9015 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 9016 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 9017} 9018 9019bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 9020 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 9021 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 9022} 9023 9024bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 9025 // i16 instructions are longer (0x66 prefix) and potentially slower. 9026 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 9027} 9028 9029/// isShuffleMaskLegal - Targets can use this to indicate that they only 9030/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 9031/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 9032/// are assumed to be legal. 9033bool 9034X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 9035 EVT VT) const { 9036 // Very little shuffling can be done for 64-bit vectors right now. 9037 if (VT.getSizeInBits() == 64) 9038 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 9039 9040 // FIXME: pshufb, blends, shifts. 9041 return (VT.getVectorNumElements() == 2 || 9042 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 9043 isMOVLMask(M, VT) || 9044 isSHUFPMask(M, VT) || 9045 isPSHUFDMask(M, VT) || 9046 isPSHUFHWMask(M, VT) || 9047 isPSHUFLWMask(M, VT) || 9048 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 9049 isUNPCKLMask(M, VT) || 9050 isUNPCKHMask(M, VT) || 9051 isUNPCKL_v_undef_Mask(M, VT) || 9052 isUNPCKH_v_undef_Mask(M, VT)); 9053} 9054 9055bool 9056X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 9057 EVT VT) const { 9058 unsigned NumElts = VT.getVectorNumElements(); 9059 // FIXME: This collection of masks seems suspect. 9060 if (NumElts == 2) 9061 return true; 9062 if (NumElts == 4 && VT.getSizeInBits() == 128) { 9063 return (isMOVLMask(Mask, VT) || 9064 isCommutedMOVLMask(Mask, VT, true) || 9065 isSHUFPMask(Mask, VT) || 9066 isCommutedSHUFPMask(Mask, VT)); 9067 } 9068 return false; 9069} 9070 9071//===----------------------------------------------------------------------===// 9072// X86 Scheduler Hooks 9073//===----------------------------------------------------------------------===// 9074 9075// private utility function 9076MachineBasicBlock * 9077X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 9078 MachineBasicBlock *MBB, 9079 unsigned regOpc, 9080 unsigned immOpc, 9081 unsigned LoadOpc, 9082 unsigned CXchgOpc, 9083 unsigned notOpc, 9084 unsigned EAXreg, 9085 TargetRegisterClass *RC, 9086 bool invSrc) const { 9087 // For the atomic bitwise operator, we generate 9088 // thisMBB: 9089 // newMBB: 9090 // ld t1 = [bitinstr.addr] 9091 // op t2 = t1, [bitinstr.val] 9092 // mov EAX = t1 9093 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 9094 // bz newMBB 9095 // fallthrough -->nextMBB 9096 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9097 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9098 MachineFunction::iterator MBBIter = MBB; 9099 ++MBBIter; 9100 9101 /// First build the CFG 9102 MachineFunction *F = MBB->getParent(); 9103 MachineBasicBlock *thisMBB = MBB; 9104 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9105 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9106 F->insert(MBBIter, newMBB); 9107 F->insert(MBBIter, nextMBB); 9108 9109 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9110 nextMBB->splice(nextMBB->begin(), thisMBB, 9111 llvm::next(MachineBasicBlock::iterator(bInstr)), 9112 thisMBB->end()); 9113 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9114 9115 // Update thisMBB to fall through to newMBB 9116 thisMBB->addSuccessor(newMBB); 9117 9118 // newMBB jumps to itself and fall through to nextMBB 9119 newMBB->addSuccessor(nextMBB); 9120 newMBB->addSuccessor(newMBB); 9121 9122 // Insert instructions into newMBB based on incoming instruction 9123 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 9124 "unexpected number of operands"); 9125 DebugLoc dl = bInstr->getDebugLoc(); 9126 MachineOperand& destOper = bInstr->getOperand(0); 9127 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9128 int numArgs = bInstr->getNumOperands() - 1; 9129 for (int i=0; i < numArgs; ++i) 9130 argOpers[i] = &bInstr->getOperand(i+1); 9131 9132 // x86 address has 4 operands: base, index, scale, and displacement 9133 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9134 int valArgIndx = lastAddrIndx + 1; 9135 9136 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 9137 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 9138 for (int i=0; i <= lastAddrIndx; ++i) 9139 (*MIB).addOperand(*argOpers[i]); 9140 9141 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 9142 if (invSrc) { 9143 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 9144 } 9145 else 9146 tt = t1; 9147 9148 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 9149 assert((argOpers[valArgIndx]->isReg() || 9150 argOpers[valArgIndx]->isImm()) && 9151 "invalid operand"); 9152 if (argOpers[valArgIndx]->isReg()) 9153 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 9154 else 9155 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 9156 MIB.addReg(tt); 9157 (*MIB).addOperand(*argOpers[valArgIndx]); 9158 9159 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 9160 MIB.addReg(t1); 9161 9162 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 9163 for (int i=0; i <= lastAddrIndx; ++i) 9164 (*MIB).addOperand(*argOpers[i]); 9165 MIB.addReg(t2); 9166 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9167 (*MIB).setMemRefs(bInstr->memoperands_begin(), 9168 bInstr->memoperands_end()); 9169 9170 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 9171 MIB.addReg(EAXreg); 9172 9173 // insert branch 9174 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9175 9176 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 9177 return nextMBB; 9178} 9179 9180// private utility function: 64 bit atomics on 32 bit host. 9181MachineBasicBlock * 9182X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 9183 MachineBasicBlock *MBB, 9184 unsigned regOpcL, 9185 unsigned regOpcH, 9186 unsigned immOpcL, 9187 unsigned immOpcH, 9188 bool invSrc) const { 9189 // For the atomic bitwise operator, we generate 9190 // thisMBB (instructions are in pairs, except cmpxchg8b) 9191 // ld t1,t2 = [bitinstr.addr] 9192 // newMBB: 9193 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 9194 // op t5, t6 <- out1, out2, [bitinstr.val] 9195 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 9196 // mov ECX, EBX <- t5, t6 9197 // mov EAX, EDX <- t1, t2 9198 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 9199 // mov t3, t4 <- EAX, EDX 9200 // bz newMBB 9201 // result in out1, out2 9202 // fallthrough -->nextMBB 9203 9204 const TargetRegisterClass *RC = X86::GR32RegisterClass; 9205 const unsigned LoadOpc = X86::MOV32rm; 9206 const unsigned NotOpc = X86::NOT32r; 9207 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9208 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9209 MachineFunction::iterator MBBIter = MBB; 9210 ++MBBIter; 9211 9212 /// First build the CFG 9213 MachineFunction *F = MBB->getParent(); 9214 MachineBasicBlock *thisMBB = MBB; 9215 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9216 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9217 F->insert(MBBIter, newMBB); 9218 F->insert(MBBIter, nextMBB); 9219 9220 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9221 nextMBB->splice(nextMBB->begin(), thisMBB, 9222 llvm::next(MachineBasicBlock::iterator(bInstr)), 9223 thisMBB->end()); 9224 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9225 9226 // Update thisMBB to fall through to newMBB 9227 thisMBB->addSuccessor(newMBB); 9228 9229 // newMBB jumps to itself and fall through to nextMBB 9230 newMBB->addSuccessor(nextMBB); 9231 newMBB->addSuccessor(newMBB); 9232 9233 DebugLoc dl = bInstr->getDebugLoc(); 9234 // Insert instructions into newMBB based on incoming instruction 9235 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 9236 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 9237 "unexpected number of operands"); 9238 MachineOperand& dest1Oper = bInstr->getOperand(0); 9239 MachineOperand& dest2Oper = bInstr->getOperand(1); 9240 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9241 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 9242 argOpers[i] = &bInstr->getOperand(i+2); 9243 9244 // We use some of the operands multiple times, so conservatively just 9245 // clear any kill flags that might be present. 9246 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 9247 argOpers[i]->setIsKill(false); 9248 } 9249 9250 // x86 address has 5 operands: base, index, scale, displacement, and segment. 9251 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9252 9253 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 9254 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 9255 for (int i=0; i <= lastAddrIndx; ++i) 9256 (*MIB).addOperand(*argOpers[i]); 9257 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 9258 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 9259 // add 4 to displacement. 9260 for (int i=0; i <= lastAddrIndx-2; ++i) 9261 (*MIB).addOperand(*argOpers[i]); 9262 MachineOperand newOp3 = *(argOpers[3]); 9263 if (newOp3.isImm()) 9264 newOp3.setImm(newOp3.getImm()+4); 9265 else 9266 newOp3.setOffset(newOp3.getOffset()+4); 9267 (*MIB).addOperand(newOp3); 9268 (*MIB).addOperand(*argOpers[lastAddrIndx]); 9269 9270 // t3/4 are defined later, at the bottom of the loop 9271 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 9272 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 9273 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 9274 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 9275 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 9276 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 9277 9278 // The subsequent operations should be using the destination registers of 9279 //the PHI instructions. 9280 if (invSrc) { 9281 t1 = F->getRegInfo().createVirtualRegister(RC); 9282 t2 = F->getRegInfo().createVirtualRegister(RC); 9283 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 9284 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 9285 } else { 9286 t1 = dest1Oper.getReg(); 9287 t2 = dest2Oper.getReg(); 9288 } 9289 9290 int valArgIndx = lastAddrIndx + 1; 9291 assert((argOpers[valArgIndx]->isReg() || 9292 argOpers[valArgIndx]->isImm()) && 9293 "invalid operand"); 9294 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 9295 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 9296 if (argOpers[valArgIndx]->isReg()) 9297 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 9298 else 9299 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 9300 if (regOpcL != X86::MOV32rr) 9301 MIB.addReg(t1); 9302 (*MIB).addOperand(*argOpers[valArgIndx]); 9303 assert(argOpers[valArgIndx + 1]->isReg() == 9304 argOpers[valArgIndx]->isReg()); 9305 assert(argOpers[valArgIndx + 1]->isImm() == 9306 argOpers[valArgIndx]->isImm()); 9307 if (argOpers[valArgIndx + 1]->isReg()) 9308 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 9309 else 9310 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 9311 if (regOpcH != X86::MOV32rr) 9312 MIB.addReg(t2); 9313 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 9314 9315 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 9316 MIB.addReg(t1); 9317 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 9318 MIB.addReg(t2); 9319 9320 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 9321 MIB.addReg(t5); 9322 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 9323 MIB.addReg(t6); 9324 9325 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 9326 for (int i=0; i <= lastAddrIndx; ++i) 9327 (*MIB).addOperand(*argOpers[i]); 9328 9329 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9330 (*MIB).setMemRefs(bInstr->memoperands_begin(), 9331 bInstr->memoperands_end()); 9332 9333 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 9334 MIB.addReg(X86::EAX); 9335 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 9336 MIB.addReg(X86::EDX); 9337 9338 // insert branch 9339 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9340 9341 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 9342 return nextMBB; 9343} 9344 9345// private utility function 9346MachineBasicBlock * 9347X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 9348 MachineBasicBlock *MBB, 9349 unsigned cmovOpc) const { 9350 // For the atomic min/max operator, we generate 9351 // thisMBB: 9352 // newMBB: 9353 // ld t1 = [min/max.addr] 9354 // mov t2 = [min/max.val] 9355 // cmp t1, t2 9356 // cmov[cond] t2 = t1 9357 // mov EAX = t1 9358 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 9359 // bz newMBB 9360 // fallthrough -->nextMBB 9361 // 9362 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9363 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9364 MachineFunction::iterator MBBIter = MBB; 9365 ++MBBIter; 9366 9367 /// First build the CFG 9368 MachineFunction *F = MBB->getParent(); 9369 MachineBasicBlock *thisMBB = MBB; 9370 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9371 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9372 F->insert(MBBIter, newMBB); 9373 F->insert(MBBIter, nextMBB); 9374 9375 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9376 nextMBB->splice(nextMBB->begin(), thisMBB, 9377 llvm::next(MachineBasicBlock::iterator(mInstr)), 9378 thisMBB->end()); 9379 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9380 9381 // Update thisMBB to fall through to newMBB 9382 thisMBB->addSuccessor(newMBB); 9383 9384 // newMBB jumps to newMBB and fall through to nextMBB 9385 newMBB->addSuccessor(nextMBB); 9386 newMBB->addSuccessor(newMBB); 9387 9388 DebugLoc dl = mInstr->getDebugLoc(); 9389 // Insert instructions into newMBB based on incoming instruction 9390 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 9391 "unexpected number of operands"); 9392 MachineOperand& destOper = mInstr->getOperand(0); 9393 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9394 int numArgs = mInstr->getNumOperands() - 1; 9395 for (int i=0; i < numArgs; ++i) 9396 argOpers[i] = &mInstr->getOperand(i+1); 9397 9398 // x86 address has 4 operands: base, index, scale, and displacement 9399 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9400 int valArgIndx = lastAddrIndx + 1; 9401 9402 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9403 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 9404 for (int i=0; i <= lastAddrIndx; ++i) 9405 (*MIB).addOperand(*argOpers[i]); 9406 9407 // We only support register and immediate values 9408 assert((argOpers[valArgIndx]->isReg() || 9409 argOpers[valArgIndx]->isImm()) && 9410 "invalid operand"); 9411 9412 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9413 if (argOpers[valArgIndx]->isReg()) 9414 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 9415 else 9416 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 9417 (*MIB).addOperand(*argOpers[valArgIndx]); 9418 9419 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 9420 MIB.addReg(t1); 9421 9422 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 9423 MIB.addReg(t1); 9424 MIB.addReg(t2); 9425 9426 // Generate movc 9427 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9428 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 9429 MIB.addReg(t2); 9430 MIB.addReg(t1); 9431 9432 // Cmp and exchange if none has modified the memory location 9433 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 9434 for (int i=0; i <= lastAddrIndx; ++i) 9435 (*MIB).addOperand(*argOpers[i]); 9436 MIB.addReg(t3); 9437 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9438 (*MIB).setMemRefs(mInstr->memoperands_begin(), 9439 mInstr->memoperands_end()); 9440 9441 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 9442 MIB.addReg(X86::EAX); 9443 9444 // insert branch 9445 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9446 9447 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 9448 return nextMBB; 9449} 9450 9451// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 9452// or XMM0_V32I8 in AVX all of this code can be replaced with that 9453// in the .td file. 9454MachineBasicBlock * 9455X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 9456 unsigned numArgs, bool memArg) const { 9457 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 9458 "Target must have SSE4.2 or AVX features enabled"); 9459 9460 DebugLoc dl = MI->getDebugLoc(); 9461 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9462 unsigned Opc; 9463 if (!Subtarget->hasAVX()) { 9464 if (memArg) 9465 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 9466 else 9467 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 9468 } else { 9469 if (memArg) 9470 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 9471 else 9472 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 9473 } 9474 9475 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 9476 for (unsigned i = 0; i < numArgs; ++i) { 9477 MachineOperand &Op = MI->getOperand(i+1); 9478 if (!(Op.isReg() && Op.isImplicit())) 9479 MIB.addOperand(Op); 9480 } 9481 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 9482 .addReg(X86::XMM0); 9483 9484 MI->eraseFromParent(); 9485 return BB; 9486} 9487 9488MachineBasicBlock * 9489X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 9490 DebugLoc dl = MI->getDebugLoc(); 9491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9492 9493 // Address into RAX/EAX, other two args into ECX, EDX. 9494 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 9495 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 9496 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 9497 for (int i = 0; i < X86::AddrNumOperands; ++i) 9498 MIB.addOperand(MI->getOperand(i)); 9499 9500 unsigned ValOps = X86::AddrNumOperands; 9501 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 9502 .addReg(MI->getOperand(ValOps).getReg()); 9503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 9504 .addReg(MI->getOperand(ValOps+1).getReg()); 9505 9506 // The instruction doesn't actually take any operands though. 9507 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 9508 9509 MI->eraseFromParent(); // The pseudo is gone now. 9510 return BB; 9511} 9512 9513MachineBasicBlock * 9514X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 9515 DebugLoc dl = MI->getDebugLoc(); 9516 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9517 9518 // First arg in ECX, the second in EAX. 9519 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 9520 .addReg(MI->getOperand(0).getReg()); 9521 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 9522 .addReg(MI->getOperand(1).getReg()); 9523 9524 // The instruction doesn't actually take any operands though. 9525 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 9526 9527 MI->eraseFromParent(); // The pseudo is gone now. 9528 return BB; 9529} 9530 9531MachineBasicBlock * 9532X86TargetLowering::EmitVAARG64WithCustomInserter( 9533 MachineInstr *MI, 9534 MachineBasicBlock *MBB) const { 9535 // Emit va_arg instruction on X86-64. 9536 9537 // Operands to this pseudo-instruction: 9538 // 0 ) Output : destination address (reg) 9539 // 1-5) Input : va_list address (addr, i64mem) 9540 // 6 ) ArgSize : Size (in bytes) of vararg type 9541 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 9542 // 8 ) Align : Alignment of type 9543 // 9 ) EFLAGS (implicit-def) 9544 9545 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 9546 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 9547 9548 unsigned DestReg = MI->getOperand(0).getReg(); 9549 MachineOperand &Base = MI->getOperand(1); 9550 MachineOperand &Scale = MI->getOperand(2); 9551 MachineOperand &Index = MI->getOperand(3); 9552 MachineOperand &Disp = MI->getOperand(4); 9553 MachineOperand &Segment = MI->getOperand(5); 9554 unsigned ArgSize = MI->getOperand(6).getImm(); 9555 unsigned ArgMode = MI->getOperand(7).getImm(); 9556 unsigned Align = MI->getOperand(8).getImm(); 9557 9558 // Memory Reference 9559 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 9560 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 9561 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 9562 9563 // Machine Information 9564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9565 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 9566 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 9567 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 9568 DebugLoc DL = MI->getDebugLoc(); 9569 9570 // struct va_list { 9571 // i32 gp_offset 9572 // i32 fp_offset 9573 // i64 overflow_area (address) 9574 // i64 reg_save_area (address) 9575 // } 9576 // sizeof(va_list) = 24 9577 // alignment(va_list) = 8 9578 9579 unsigned TotalNumIntRegs = 6; 9580 unsigned TotalNumXMMRegs = 8; 9581 bool UseGPOffset = (ArgMode == 1); 9582 bool UseFPOffset = (ArgMode == 2); 9583 unsigned MaxOffset = TotalNumIntRegs * 8 + 9584 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 9585 9586 /* Align ArgSize to a multiple of 8 */ 9587 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 9588 bool NeedsAlign = (Align > 8); 9589 9590 MachineBasicBlock *thisMBB = MBB; 9591 MachineBasicBlock *overflowMBB; 9592 MachineBasicBlock *offsetMBB; 9593 MachineBasicBlock *endMBB; 9594 9595 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 9596 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 9597 unsigned OffsetReg = 0; 9598 9599 if (!UseGPOffset && !UseFPOffset) { 9600 // If we only pull from the overflow region, we don't create a branch. 9601 // We don't need to alter control flow. 9602 OffsetDestReg = 0; // unused 9603 OverflowDestReg = DestReg; 9604 9605 offsetMBB = NULL; 9606 overflowMBB = thisMBB; 9607 endMBB = thisMBB; 9608 } else { 9609 // First emit code to check if gp_offset (or fp_offset) is below the bound. 9610 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 9611 // If not, pull from overflow_area. (branch to overflowMBB) 9612 // 9613 // thisMBB 9614 // | . 9615 // | . 9616 // offsetMBB overflowMBB 9617 // | . 9618 // | . 9619 // endMBB 9620 9621 // Registers for the PHI in endMBB 9622 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 9623 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 9624 9625 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9626 MachineFunction *MF = MBB->getParent(); 9627 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 9628 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 9629 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 9630 9631 MachineFunction::iterator MBBIter = MBB; 9632 ++MBBIter; 9633 9634 // Insert the new basic blocks 9635 MF->insert(MBBIter, offsetMBB); 9636 MF->insert(MBBIter, overflowMBB); 9637 MF->insert(MBBIter, endMBB); 9638 9639 // Transfer the remainder of MBB and its successor edges to endMBB. 9640 endMBB->splice(endMBB->begin(), thisMBB, 9641 llvm::next(MachineBasicBlock::iterator(MI)), 9642 thisMBB->end()); 9643 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9644 9645 // Make offsetMBB and overflowMBB successors of thisMBB 9646 thisMBB->addSuccessor(offsetMBB); 9647 thisMBB->addSuccessor(overflowMBB); 9648 9649 // endMBB is a successor of both offsetMBB and overflowMBB 9650 offsetMBB->addSuccessor(endMBB); 9651 overflowMBB->addSuccessor(endMBB); 9652 9653 // Load the offset value into a register 9654 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 9655 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 9656 .addOperand(Base) 9657 .addOperand(Scale) 9658 .addOperand(Index) 9659 .addDisp(Disp, UseFPOffset ? 4 : 0) 9660 .addOperand(Segment) 9661 .setMemRefs(MMOBegin, MMOEnd); 9662 9663 // Check if there is enough room left to pull this argument. 9664 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 9665 .addReg(OffsetReg) 9666 .addImm(MaxOffset + 8 - ArgSizeA8); 9667 9668 // Branch to "overflowMBB" if offset >= max 9669 // Fall through to "offsetMBB" otherwise 9670 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 9671 .addMBB(overflowMBB); 9672 } 9673 9674 // In offsetMBB, emit code to use the reg_save_area. 9675 if (offsetMBB) { 9676 assert(OffsetReg != 0); 9677 9678 // Read the reg_save_area address. 9679 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 9680 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 9681 .addOperand(Base) 9682 .addOperand(Scale) 9683 .addOperand(Index) 9684 .addDisp(Disp, 16) 9685 .addOperand(Segment) 9686 .setMemRefs(MMOBegin, MMOEnd); 9687 9688 // Zero-extend the offset 9689 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 9690 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 9691 .addImm(0) 9692 .addReg(OffsetReg) 9693 .addImm(X86::sub_32bit); 9694 9695 // Add the offset to the reg_save_area to get the final address. 9696 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 9697 .addReg(OffsetReg64) 9698 .addReg(RegSaveReg); 9699 9700 // Compute the offset for the next argument 9701 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 9702 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 9703 .addReg(OffsetReg) 9704 .addImm(UseFPOffset ? 16 : 8); 9705 9706 // Store it back into the va_list. 9707 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 9708 .addOperand(Base) 9709 .addOperand(Scale) 9710 .addOperand(Index) 9711 .addDisp(Disp, UseFPOffset ? 4 : 0) 9712 .addOperand(Segment) 9713 .addReg(NextOffsetReg) 9714 .setMemRefs(MMOBegin, MMOEnd); 9715 9716 // Jump to endMBB 9717 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 9718 .addMBB(endMBB); 9719 } 9720 9721 // 9722 // Emit code to use overflow area 9723 // 9724 9725 // Load the overflow_area address into a register. 9726 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 9727 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 9728 .addOperand(Base) 9729 .addOperand(Scale) 9730 .addOperand(Index) 9731 .addDisp(Disp, 8) 9732 .addOperand(Segment) 9733 .setMemRefs(MMOBegin, MMOEnd); 9734 9735 // If we need to align it, do so. Otherwise, just copy the address 9736 // to OverflowDestReg. 9737 if (NeedsAlign) { 9738 // Align the overflow address 9739 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 9740 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 9741 9742 // aligned_addr = (addr + (align-1)) & ~(align-1) 9743 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 9744 .addReg(OverflowAddrReg) 9745 .addImm(Align-1); 9746 9747 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 9748 .addReg(TmpReg) 9749 .addImm(~(uint64_t)(Align-1)); 9750 } else { 9751 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 9752 .addReg(OverflowAddrReg); 9753 } 9754 9755 // Compute the next overflow address after this argument. 9756 // (the overflow address should be kept 8-byte aligned) 9757 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 9758 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 9759 .addReg(OverflowDestReg) 9760 .addImm(ArgSizeA8); 9761 9762 // Store the new overflow address. 9763 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 9764 .addOperand(Base) 9765 .addOperand(Scale) 9766 .addOperand(Index) 9767 .addDisp(Disp, 8) 9768 .addOperand(Segment) 9769 .addReg(NextAddrReg) 9770 .setMemRefs(MMOBegin, MMOEnd); 9771 9772 // If we branched, emit the PHI to the front of endMBB. 9773 if (offsetMBB) { 9774 BuildMI(*endMBB, endMBB->begin(), DL, 9775 TII->get(X86::PHI), DestReg) 9776 .addReg(OffsetDestReg).addMBB(offsetMBB) 9777 .addReg(OverflowDestReg).addMBB(overflowMBB); 9778 } 9779 9780 // Erase the pseudo instruction 9781 MI->eraseFromParent(); 9782 9783 return endMBB; 9784} 9785 9786MachineBasicBlock * 9787X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 9788 MachineInstr *MI, 9789 MachineBasicBlock *MBB) const { 9790 // Emit code to save XMM registers to the stack. The ABI says that the 9791 // number of registers to save is given in %al, so it's theoretically 9792 // possible to do an indirect jump trick to avoid saving all of them, 9793 // however this code takes a simpler approach and just executes all 9794 // of the stores if %al is non-zero. It's less code, and it's probably 9795 // easier on the hardware branch predictor, and stores aren't all that 9796 // expensive anyway. 9797 9798 // Create the new basic blocks. One block contains all the XMM stores, 9799 // and one block is the final destination regardless of whether any 9800 // stores were performed. 9801 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9802 MachineFunction *F = MBB->getParent(); 9803 MachineFunction::iterator MBBIter = MBB; 9804 ++MBBIter; 9805 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 9806 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 9807 F->insert(MBBIter, XMMSaveMBB); 9808 F->insert(MBBIter, EndMBB); 9809 9810 // Transfer the remainder of MBB and its successor edges to EndMBB. 9811 EndMBB->splice(EndMBB->begin(), MBB, 9812 llvm::next(MachineBasicBlock::iterator(MI)), 9813 MBB->end()); 9814 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 9815 9816 // The original block will now fall through to the XMM save block. 9817 MBB->addSuccessor(XMMSaveMBB); 9818 // The XMMSaveMBB will fall through to the end block. 9819 XMMSaveMBB->addSuccessor(EndMBB); 9820 9821 // Now add the instructions. 9822 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9823 DebugLoc DL = MI->getDebugLoc(); 9824 9825 unsigned CountReg = MI->getOperand(0).getReg(); 9826 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 9827 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 9828 9829 if (!Subtarget->isTargetWin64()) { 9830 // If %al is 0, branch around the XMM save block. 9831 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 9832 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 9833 MBB->addSuccessor(EndMBB); 9834 } 9835 9836 // In the XMM save block, save all the XMM argument registers. 9837 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 9838 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 9839 MachineMemOperand *MMO = 9840 F->getMachineMemOperand( 9841 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 9842 MachineMemOperand::MOStore, 9843 /*Size=*/16, /*Align=*/16); 9844 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 9845 .addFrameIndex(RegSaveFrameIndex) 9846 .addImm(/*Scale=*/1) 9847 .addReg(/*IndexReg=*/0) 9848 .addImm(/*Disp=*/Offset) 9849 .addReg(/*Segment=*/0) 9850 .addReg(MI->getOperand(i).getReg()) 9851 .addMemOperand(MMO); 9852 } 9853 9854 MI->eraseFromParent(); // The pseudo instruction is gone now. 9855 9856 return EndMBB; 9857} 9858 9859MachineBasicBlock * 9860X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 9861 MachineBasicBlock *BB) const { 9862 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9863 DebugLoc DL = MI->getDebugLoc(); 9864 9865 // To "insert" a SELECT_CC instruction, we actually have to insert the 9866 // diamond control-flow pattern. The incoming instruction knows the 9867 // destination vreg to set, the condition code register to branch on, the 9868 // true/false values to select between, and a branch opcode to use. 9869 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 9870 MachineFunction::iterator It = BB; 9871 ++It; 9872 9873 // thisMBB: 9874 // ... 9875 // TrueVal = ... 9876 // cmpTY ccX, r1, r2 9877 // bCC copy1MBB 9878 // fallthrough --> copy0MBB 9879 MachineBasicBlock *thisMBB = BB; 9880 MachineFunction *F = BB->getParent(); 9881 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 9882 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 9883 F->insert(It, copy0MBB); 9884 F->insert(It, sinkMBB); 9885 9886 // If the EFLAGS register isn't dead in the terminator, then claim that it's 9887 // live into the sink and copy blocks. 9888 const MachineFunction *MF = BB->getParent(); 9889 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 9890 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 9891 9892 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 9893 const MachineOperand &MO = MI->getOperand(I); 9894 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 9895 unsigned Reg = MO.getReg(); 9896 if (Reg != X86::EFLAGS) continue; 9897 copy0MBB->addLiveIn(Reg); 9898 sinkMBB->addLiveIn(Reg); 9899 } 9900 9901 // Transfer the remainder of BB and its successor edges to sinkMBB. 9902 sinkMBB->splice(sinkMBB->begin(), BB, 9903 llvm::next(MachineBasicBlock::iterator(MI)), 9904 BB->end()); 9905 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 9906 9907 // Add the true and fallthrough blocks as its successors. 9908 BB->addSuccessor(copy0MBB); 9909 BB->addSuccessor(sinkMBB); 9910 9911 // Create the conditional branch instruction. 9912 unsigned Opc = 9913 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 9914 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 9915 9916 // copy0MBB: 9917 // %FalseValue = ... 9918 // # fallthrough to sinkMBB 9919 copy0MBB->addSuccessor(sinkMBB); 9920 9921 // sinkMBB: 9922 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 9923 // ... 9924 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 9925 TII->get(X86::PHI), MI->getOperand(0).getReg()) 9926 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 9927 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 9928 9929 MI->eraseFromParent(); // The pseudo instruction is gone now. 9930 return sinkMBB; 9931} 9932 9933MachineBasicBlock * 9934X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 9935 MachineBasicBlock *BB) const { 9936 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9937 DebugLoc DL = MI->getDebugLoc(); 9938 9939 // The lowering is pretty easy: we're just emitting the call to _alloca. The 9940 // non-trivial part is impdef of ESP. 9941 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 9942 // mingw-w64. 9943 9944 const char *StackProbeSymbol = 9945 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 9946 9947 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 9948 .addExternalSymbol(StackProbeSymbol) 9949 .addReg(X86::EAX, RegState::Implicit) 9950 .addReg(X86::ESP, RegState::Implicit) 9951 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 9952 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 9953 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 9954 9955 MI->eraseFromParent(); // The pseudo instruction is gone now. 9956 return BB; 9957} 9958 9959MachineBasicBlock * 9960X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 9961 MachineBasicBlock *BB) const { 9962 // This is pretty easy. We're taking the value that we received from 9963 // our load from the relocation, sticking it in either RDI (x86-64) 9964 // or EAX and doing an indirect call. The return value will then 9965 // be in the normal return register. 9966 const X86InstrInfo *TII 9967 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 9968 DebugLoc DL = MI->getDebugLoc(); 9969 MachineFunction *F = BB->getParent(); 9970 9971 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 9972 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 9973 9974 if (Subtarget->is64Bit()) { 9975 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9976 TII->get(X86::MOV64rm), X86::RDI) 9977 .addReg(X86::RIP) 9978 .addImm(0).addReg(0) 9979 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9980 MI->getOperand(3).getTargetFlags()) 9981 .addReg(0); 9982 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 9983 addDirectMem(MIB, X86::RDI); 9984 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 9985 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9986 TII->get(X86::MOV32rm), X86::EAX) 9987 .addReg(0) 9988 .addImm(0).addReg(0) 9989 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9990 MI->getOperand(3).getTargetFlags()) 9991 .addReg(0); 9992 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 9993 addDirectMem(MIB, X86::EAX); 9994 } else { 9995 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9996 TII->get(X86::MOV32rm), X86::EAX) 9997 .addReg(TII->getGlobalBaseReg(F)) 9998 .addImm(0).addReg(0) 9999 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 10000 MI->getOperand(3).getTargetFlags()) 10001 .addReg(0); 10002 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 10003 addDirectMem(MIB, X86::EAX); 10004 } 10005 10006 MI->eraseFromParent(); // The pseudo instruction is gone now. 10007 return BB; 10008} 10009 10010MachineBasicBlock * 10011X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 10012 MachineBasicBlock *BB) const { 10013 switch (MI->getOpcode()) { 10014 default: assert(false && "Unexpected instr type to insert"); 10015 case X86::WIN_ALLOCA: 10016 return EmitLoweredWinAlloca(MI, BB); 10017 case X86::TLSCall_32: 10018 case X86::TLSCall_64: 10019 return EmitLoweredTLSCall(MI, BB); 10020 case X86::CMOV_GR8: 10021 case X86::CMOV_FR32: 10022 case X86::CMOV_FR64: 10023 case X86::CMOV_V4F32: 10024 case X86::CMOV_V2F64: 10025 case X86::CMOV_V2I64: 10026 case X86::CMOV_GR16: 10027 case X86::CMOV_GR32: 10028 case X86::CMOV_RFP32: 10029 case X86::CMOV_RFP64: 10030 case X86::CMOV_RFP80: 10031 return EmitLoweredSelect(MI, BB); 10032 10033 case X86::FP32_TO_INT16_IN_MEM: 10034 case X86::FP32_TO_INT32_IN_MEM: 10035 case X86::FP32_TO_INT64_IN_MEM: 10036 case X86::FP64_TO_INT16_IN_MEM: 10037 case X86::FP64_TO_INT32_IN_MEM: 10038 case X86::FP64_TO_INT64_IN_MEM: 10039 case X86::FP80_TO_INT16_IN_MEM: 10040 case X86::FP80_TO_INT32_IN_MEM: 10041 case X86::FP80_TO_INT64_IN_MEM: { 10042 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10043 DebugLoc DL = MI->getDebugLoc(); 10044 10045 // Change the floating point control register to use "round towards zero" 10046 // mode when truncating to an integer value. 10047 MachineFunction *F = BB->getParent(); 10048 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 10049 addFrameReference(BuildMI(*BB, MI, DL, 10050 TII->get(X86::FNSTCW16m)), CWFrameIdx); 10051 10052 // Load the old value of the high byte of the control word... 10053 unsigned OldCW = 10054 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 10055 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 10056 CWFrameIdx); 10057 10058 // Set the high part to be round to zero... 10059 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 10060 .addImm(0xC7F); 10061 10062 // Reload the modified control word now... 10063 addFrameReference(BuildMI(*BB, MI, DL, 10064 TII->get(X86::FLDCW16m)), CWFrameIdx); 10065 10066 // Restore the memory image of control word to original value 10067 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 10068 .addReg(OldCW); 10069 10070 // Get the X86 opcode to use. 10071 unsigned Opc; 10072 switch (MI->getOpcode()) { 10073 default: llvm_unreachable("illegal opcode!"); 10074 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 10075 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 10076 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 10077 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 10078 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 10079 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 10080 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 10081 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 10082 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 10083 } 10084 10085 X86AddressMode AM; 10086 MachineOperand &Op = MI->getOperand(0); 10087 if (Op.isReg()) { 10088 AM.BaseType = X86AddressMode::RegBase; 10089 AM.Base.Reg = Op.getReg(); 10090 } else { 10091 AM.BaseType = X86AddressMode::FrameIndexBase; 10092 AM.Base.FrameIndex = Op.getIndex(); 10093 } 10094 Op = MI->getOperand(1); 10095 if (Op.isImm()) 10096 AM.Scale = Op.getImm(); 10097 Op = MI->getOperand(2); 10098 if (Op.isImm()) 10099 AM.IndexReg = Op.getImm(); 10100 Op = MI->getOperand(3); 10101 if (Op.isGlobal()) { 10102 AM.GV = Op.getGlobal(); 10103 } else { 10104 AM.Disp = Op.getImm(); 10105 } 10106 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 10107 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 10108 10109 // Reload the original control word now. 10110 addFrameReference(BuildMI(*BB, MI, DL, 10111 TII->get(X86::FLDCW16m)), CWFrameIdx); 10112 10113 MI->eraseFromParent(); // The pseudo instruction is gone now. 10114 return BB; 10115 } 10116 // String/text processing lowering. 10117 case X86::PCMPISTRM128REG: 10118 case X86::VPCMPISTRM128REG: 10119 return EmitPCMP(MI, BB, 3, false /* in-mem */); 10120 case X86::PCMPISTRM128MEM: 10121 case X86::VPCMPISTRM128MEM: 10122 return EmitPCMP(MI, BB, 3, true /* in-mem */); 10123 case X86::PCMPESTRM128REG: 10124 case X86::VPCMPESTRM128REG: 10125 return EmitPCMP(MI, BB, 5, false /* in mem */); 10126 case X86::PCMPESTRM128MEM: 10127 case X86::VPCMPESTRM128MEM: 10128 return EmitPCMP(MI, BB, 5, true /* in mem */); 10129 10130 // Thread synchronization. 10131 case X86::MONITOR: 10132 return EmitMonitor(MI, BB); 10133 case X86::MWAIT: 10134 return EmitMwait(MI, BB); 10135 10136 // Atomic Lowering. 10137 case X86::ATOMAND32: 10138 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 10139 X86::AND32ri, X86::MOV32rm, 10140 X86::LCMPXCHG32, 10141 X86::NOT32r, X86::EAX, 10142 X86::GR32RegisterClass); 10143 case X86::ATOMOR32: 10144 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 10145 X86::OR32ri, X86::MOV32rm, 10146 X86::LCMPXCHG32, 10147 X86::NOT32r, X86::EAX, 10148 X86::GR32RegisterClass); 10149 case X86::ATOMXOR32: 10150 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 10151 X86::XOR32ri, X86::MOV32rm, 10152 X86::LCMPXCHG32, 10153 X86::NOT32r, X86::EAX, 10154 X86::GR32RegisterClass); 10155 case X86::ATOMNAND32: 10156 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 10157 X86::AND32ri, X86::MOV32rm, 10158 X86::LCMPXCHG32, 10159 X86::NOT32r, X86::EAX, 10160 X86::GR32RegisterClass, true); 10161 case X86::ATOMMIN32: 10162 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 10163 case X86::ATOMMAX32: 10164 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 10165 case X86::ATOMUMIN32: 10166 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 10167 case X86::ATOMUMAX32: 10168 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 10169 10170 case X86::ATOMAND16: 10171 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 10172 X86::AND16ri, X86::MOV16rm, 10173 X86::LCMPXCHG16, 10174 X86::NOT16r, X86::AX, 10175 X86::GR16RegisterClass); 10176 case X86::ATOMOR16: 10177 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 10178 X86::OR16ri, X86::MOV16rm, 10179 X86::LCMPXCHG16, 10180 X86::NOT16r, X86::AX, 10181 X86::GR16RegisterClass); 10182 case X86::ATOMXOR16: 10183 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 10184 X86::XOR16ri, X86::MOV16rm, 10185 X86::LCMPXCHG16, 10186 X86::NOT16r, X86::AX, 10187 X86::GR16RegisterClass); 10188 case X86::ATOMNAND16: 10189 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 10190 X86::AND16ri, X86::MOV16rm, 10191 X86::LCMPXCHG16, 10192 X86::NOT16r, X86::AX, 10193 X86::GR16RegisterClass, true); 10194 case X86::ATOMMIN16: 10195 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 10196 case X86::ATOMMAX16: 10197 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 10198 case X86::ATOMUMIN16: 10199 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 10200 case X86::ATOMUMAX16: 10201 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 10202 10203 case X86::ATOMAND8: 10204 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 10205 X86::AND8ri, X86::MOV8rm, 10206 X86::LCMPXCHG8, 10207 X86::NOT8r, X86::AL, 10208 X86::GR8RegisterClass); 10209 case X86::ATOMOR8: 10210 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 10211 X86::OR8ri, X86::MOV8rm, 10212 X86::LCMPXCHG8, 10213 X86::NOT8r, X86::AL, 10214 X86::GR8RegisterClass); 10215 case X86::ATOMXOR8: 10216 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 10217 X86::XOR8ri, X86::MOV8rm, 10218 X86::LCMPXCHG8, 10219 X86::NOT8r, X86::AL, 10220 X86::GR8RegisterClass); 10221 case X86::ATOMNAND8: 10222 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 10223 X86::AND8ri, X86::MOV8rm, 10224 X86::LCMPXCHG8, 10225 X86::NOT8r, X86::AL, 10226 X86::GR8RegisterClass, true); 10227 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 10228 // This group is for 64-bit host. 10229 case X86::ATOMAND64: 10230 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 10231 X86::AND64ri32, X86::MOV64rm, 10232 X86::LCMPXCHG64, 10233 X86::NOT64r, X86::RAX, 10234 X86::GR64RegisterClass); 10235 case X86::ATOMOR64: 10236 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 10237 X86::OR64ri32, X86::MOV64rm, 10238 X86::LCMPXCHG64, 10239 X86::NOT64r, X86::RAX, 10240 X86::GR64RegisterClass); 10241 case X86::ATOMXOR64: 10242 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 10243 X86::XOR64ri32, X86::MOV64rm, 10244 X86::LCMPXCHG64, 10245 X86::NOT64r, X86::RAX, 10246 X86::GR64RegisterClass); 10247 case X86::ATOMNAND64: 10248 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 10249 X86::AND64ri32, X86::MOV64rm, 10250 X86::LCMPXCHG64, 10251 X86::NOT64r, X86::RAX, 10252 X86::GR64RegisterClass, true); 10253 case X86::ATOMMIN64: 10254 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 10255 case X86::ATOMMAX64: 10256 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 10257 case X86::ATOMUMIN64: 10258 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 10259 case X86::ATOMUMAX64: 10260 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 10261 10262 // This group does 64-bit operations on a 32-bit host. 10263 case X86::ATOMAND6432: 10264 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10265 X86::AND32rr, X86::AND32rr, 10266 X86::AND32ri, X86::AND32ri, 10267 false); 10268 case X86::ATOMOR6432: 10269 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10270 X86::OR32rr, X86::OR32rr, 10271 X86::OR32ri, X86::OR32ri, 10272 false); 10273 case X86::ATOMXOR6432: 10274 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10275 X86::XOR32rr, X86::XOR32rr, 10276 X86::XOR32ri, X86::XOR32ri, 10277 false); 10278 case X86::ATOMNAND6432: 10279 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10280 X86::AND32rr, X86::AND32rr, 10281 X86::AND32ri, X86::AND32ri, 10282 true); 10283 case X86::ATOMADD6432: 10284 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10285 X86::ADD32rr, X86::ADC32rr, 10286 X86::ADD32ri, X86::ADC32ri, 10287 false); 10288 case X86::ATOMSUB6432: 10289 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10290 X86::SUB32rr, X86::SBB32rr, 10291 X86::SUB32ri, X86::SBB32ri, 10292 false); 10293 case X86::ATOMSWAP6432: 10294 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10295 X86::MOV32rr, X86::MOV32rr, 10296 X86::MOV32ri, X86::MOV32ri, 10297 false); 10298 case X86::VASTART_SAVE_XMM_REGS: 10299 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 10300 10301 case X86::VAARG_64: 10302 return EmitVAARG64WithCustomInserter(MI, BB); 10303 } 10304} 10305 10306//===----------------------------------------------------------------------===// 10307// X86 Optimization Hooks 10308//===----------------------------------------------------------------------===// 10309 10310void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 10311 const APInt &Mask, 10312 APInt &KnownZero, 10313 APInt &KnownOne, 10314 const SelectionDAG &DAG, 10315 unsigned Depth) const { 10316 unsigned Opc = Op.getOpcode(); 10317 assert((Opc >= ISD::BUILTIN_OP_END || 10318 Opc == ISD::INTRINSIC_WO_CHAIN || 10319 Opc == ISD::INTRINSIC_W_CHAIN || 10320 Opc == ISD::INTRINSIC_VOID) && 10321 "Should use MaskedValueIsZero if you don't know whether Op" 10322 " is a target node!"); 10323 10324 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 10325 switch (Opc) { 10326 default: break; 10327 case X86ISD::ADD: 10328 case X86ISD::SUB: 10329 case X86ISD::SMUL: 10330 case X86ISD::UMUL: 10331 case X86ISD::INC: 10332 case X86ISD::DEC: 10333 case X86ISD::OR: 10334 case X86ISD::XOR: 10335 case X86ISD::AND: 10336 // These nodes' second result is a boolean. 10337 if (Op.getResNo() == 0) 10338 break; 10339 // Fallthrough 10340 case X86ISD::SETCC: 10341 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 10342 Mask.getBitWidth() - 1); 10343 break; 10344 } 10345} 10346 10347unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 10348 unsigned Depth) const { 10349 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 10350 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 10351 return Op.getValueType().getScalarType().getSizeInBits(); 10352 10353 // Fallback case. 10354 return 1; 10355} 10356 10357/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 10358/// node is a GlobalAddress + offset. 10359bool X86TargetLowering::isGAPlusOffset(SDNode *N, 10360 const GlobalValue* &GA, 10361 int64_t &Offset) const { 10362 if (N->getOpcode() == X86ISD::Wrapper) { 10363 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 10364 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 10365 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 10366 return true; 10367 } 10368 } 10369 return TargetLowering::isGAPlusOffset(N, GA, Offset); 10370} 10371 10372/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 10373/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 10374/// if the load addresses are consecutive, non-overlapping, and in the right 10375/// order. 10376static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 10377 const TargetLowering &TLI) { 10378 DebugLoc dl = N->getDebugLoc(); 10379 EVT VT = N->getValueType(0); 10380 10381 if (VT.getSizeInBits() != 128) 10382 return SDValue(); 10383 10384 SmallVector<SDValue, 16> Elts; 10385 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 10386 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 10387 10388 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 10389} 10390 10391/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 10392/// generation and convert it from being a bunch of shuffles and extracts 10393/// to a simple store and scalar loads to extract the elements. 10394static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 10395 const TargetLowering &TLI) { 10396 SDValue InputVector = N->getOperand(0); 10397 10398 // Only operate on vectors of 4 elements, where the alternative shuffling 10399 // gets to be more expensive. 10400 if (InputVector.getValueType() != MVT::v4i32) 10401 return SDValue(); 10402 10403 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 10404 // single use which is a sign-extend or zero-extend, and all elements are 10405 // used. 10406 SmallVector<SDNode *, 4> Uses; 10407 unsigned ExtractedElements = 0; 10408 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 10409 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 10410 if (UI.getUse().getResNo() != InputVector.getResNo()) 10411 return SDValue(); 10412 10413 SDNode *Extract = *UI; 10414 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 10415 return SDValue(); 10416 10417 if (Extract->getValueType(0) != MVT::i32) 10418 return SDValue(); 10419 if (!Extract->hasOneUse()) 10420 return SDValue(); 10421 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 10422 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 10423 return SDValue(); 10424 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 10425 return SDValue(); 10426 10427 // Record which element was extracted. 10428 ExtractedElements |= 10429 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 10430 10431 Uses.push_back(Extract); 10432 } 10433 10434 // If not all the elements were used, this may not be worthwhile. 10435 if (ExtractedElements != 15) 10436 return SDValue(); 10437 10438 // Ok, we've now decided to do the transformation. 10439 DebugLoc dl = InputVector.getDebugLoc(); 10440 10441 // Store the value to a temporary stack slot. 10442 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 10443 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 10444 MachinePointerInfo(), false, false, 0); 10445 10446 // Replace each use (extract) with a load of the appropriate element. 10447 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 10448 UE = Uses.end(); UI != UE; ++UI) { 10449 SDNode *Extract = *UI; 10450 10451 // Compute the element's address. 10452 SDValue Idx = Extract->getOperand(1); 10453 unsigned EltSize = 10454 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 10455 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 10456 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 10457 10458 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), 10459 StackPtr, OffsetVal); 10460 10461 // Load the scalar. 10462 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 10463 ScalarAddr, MachinePointerInfo(), 10464 false, false, 0); 10465 10466 // Replace the exact with the load. 10467 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 10468 } 10469 10470 // The replacement was made in place; don't return anything. 10471 return SDValue(); 10472} 10473 10474/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 10475static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 10476 const X86Subtarget *Subtarget) { 10477 DebugLoc DL = N->getDebugLoc(); 10478 SDValue Cond = N->getOperand(0); 10479 // Get the LHS/RHS of the select. 10480 SDValue LHS = N->getOperand(1); 10481 SDValue RHS = N->getOperand(2); 10482 10483 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 10484 // instructions match the semantics of the common C idiom x<y?x:y but not 10485 // x<=y?x:y, because of how they handle negative zero (which can be 10486 // ignored in unsafe-math mode). 10487 if (Subtarget->hasSSE2() && 10488 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 10489 Cond.getOpcode() == ISD::SETCC) { 10490 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 10491 10492 unsigned Opcode = 0; 10493 // Check for x CC y ? x : y. 10494 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 10495 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 10496 switch (CC) { 10497 default: break; 10498 case ISD::SETULT: 10499 // Converting this to a min would handle NaNs incorrectly, and swapping 10500 // the operands would cause it to handle comparisons between positive 10501 // and negative zero incorrectly. 10502 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 10503 if (!UnsafeFPMath && 10504 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 10505 break; 10506 std::swap(LHS, RHS); 10507 } 10508 Opcode = X86ISD::FMIN; 10509 break; 10510 case ISD::SETOLE: 10511 // Converting this to a min would handle comparisons between positive 10512 // and negative zero incorrectly. 10513 if (!UnsafeFPMath && 10514 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 10515 break; 10516 Opcode = X86ISD::FMIN; 10517 break; 10518 case ISD::SETULE: 10519 // Converting this to a min would handle both negative zeros and NaNs 10520 // incorrectly, but we can swap the operands to fix both. 10521 std::swap(LHS, RHS); 10522 case ISD::SETOLT: 10523 case ISD::SETLT: 10524 case ISD::SETLE: 10525 Opcode = X86ISD::FMIN; 10526 break; 10527 10528 case ISD::SETOGE: 10529 // Converting this to a max would handle comparisons between positive 10530 // and negative zero incorrectly. 10531 if (!UnsafeFPMath && 10532 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 10533 break; 10534 Opcode = X86ISD::FMAX; 10535 break; 10536 case ISD::SETUGT: 10537 // Converting this to a max would handle NaNs incorrectly, and swapping 10538 // the operands would cause it to handle comparisons between positive 10539 // and negative zero incorrectly. 10540 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 10541 if (!UnsafeFPMath && 10542 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 10543 break; 10544 std::swap(LHS, RHS); 10545 } 10546 Opcode = X86ISD::FMAX; 10547 break; 10548 case ISD::SETUGE: 10549 // Converting this to a max would handle both negative zeros and NaNs 10550 // incorrectly, but we can swap the operands to fix both. 10551 std::swap(LHS, RHS); 10552 case ISD::SETOGT: 10553 case ISD::SETGT: 10554 case ISD::SETGE: 10555 Opcode = X86ISD::FMAX; 10556 break; 10557 } 10558 // Check for x CC y ? y : x -- a min/max with reversed arms. 10559 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 10560 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 10561 switch (CC) { 10562 default: break; 10563 case ISD::SETOGE: 10564 // Converting this to a min would handle comparisons between positive 10565 // and negative zero incorrectly, and swapping the operands would 10566 // cause it to handle NaNs incorrectly. 10567 if (!UnsafeFPMath && 10568 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 10569 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 10570 break; 10571 std::swap(LHS, RHS); 10572 } 10573 Opcode = X86ISD::FMIN; 10574 break; 10575 case ISD::SETUGT: 10576 // Converting this to a min would handle NaNs incorrectly. 10577 if (!UnsafeFPMath && 10578 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 10579 break; 10580 Opcode = X86ISD::FMIN; 10581 break; 10582 case ISD::SETUGE: 10583 // Converting this to a min would handle both negative zeros and NaNs 10584 // incorrectly, but we can swap the operands to fix both. 10585 std::swap(LHS, RHS); 10586 case ISD::SETOGT: 10587 case ISD::SETGT: 10588 case ISD::SETGE: 10589 Opcode = X86ISD::FMIN; 10590 break; 10591 10592 case ISD::SETULT: 10593 // Converting this to a max would handle NaNs incorrectly. 10594 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 10595 break; 10596 Opcode = X86ISD::FMAX; 10597 break; 10598 case ISD::SETOLE: 10599 // Converting this to a max would handle comparisons between positive 10600 // and negative zero incorrectly, and swapping the operands would 10601 // cause it to handle NaNs incorrectly. 10602 if (!UnsafeFPMath && 10603 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 10604 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 10605 break; 10606 std::swap(LHS, RHS); 10607 } 10608 Opcode = X86ISD::FMAX; 10609 break; 10610 case ISD::SETULE: 10611 // Converting this to a max would handle both negative zeros and NaNs 10612 // incorrectly, but we can swap the operands to fix both. 10613 std::swap(LHS, RHS); 10614 case ISD::SETOLT: 10615 case ISD::SETLT: 10616 case ISD::SETLE: 10617 Opcode = X86ISD::FMAX; 10618 break; 10619 } 10620 } 10621 10622 if (Opcode) 10623 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 10624 } 10625 10626 // If this is a select between two integer constants, try to do some 10627 // optimizations. 10628 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 10629 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 10630 // Don't do this for crazy integer types. 10631 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 10632 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 10633 // so that TrueC (the true value) is larger than FalseC. 10634 bool NeedsCondInvert = false; 10635 10636 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 10637 // Efficiently invertible. 10638 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 10639 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 10640 isa<ConstantSDNode>(Cond.getOperand(1))))) { 10641 NeedsCondInvert = true; 10642 std::swap(TrueC, FalseC); 10643 } 10644 10645 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 10646 if (FalseC->getAPIntValue() == 0 && 10647 TrueC->getAPIntValue().isPowerOf2()) { 10648 if (NeedsCondInvert) // Invert the condition if needed. 10649 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 10650 DAG.getConstant(1, Cond.getValueType())); 10651 10652 // Zero extend the condition if needed. 10653 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 10654 10655 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 10656 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 10657 DAG.getConstant(ShAmt, MVT::i8)); 10658 } 10659 10660 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 10661 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 10662 if (NeedsCondInvert) // Invert the condition if needed. 10663 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 10664 DAG.getConstant(1, Cond.getValueType())); 10665 10666 // Zero extend the condition if needed. 10667 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 10668 FalseC->getValueType(0), Cond); 10669 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10670 SDValue(FalseC, 0)); 10671 } 10672 10673 // Optimize cases that will turn into an LEA instruction. This requires 10674 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 10675 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 10676 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 10677 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 10678 10679 bool isFastMultiplier = false; 10680 if (Diff < 10) { 10681 switch ((unsigned char)Diff) { 10682 default: break; 10683 case 1: // result = add base, cond 10684 case 2: // result = lea base( , cond*2) 10685 case 3: // result = lea base(cond, cond*2) 10686 case 4: // result = lea base( , cond*4) 10687 case 5: // result = lea base(cond, cond*4) 10688 case 8: // result = lea base( , cond*8) 10689 case 9: // result = lea base(cond, cond*8) 10690 isFastMultiplier = true; 10691 break; 10692 } 10693 } 10694 10695 if (isFastMultiplier) { 10696 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 10697 if (NeedsCondInvert) // Invert the condition if needed. 10698 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 10699 DAG.getConstant(1, Cond.getValueType())); 10700 10701 // Zero extend the condition if needed. 10702 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 10703 Cond); 10704 // Scale the condition by the difference. 10705 if (Diff != 1) 10706 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 10707 DAG.getConstant(Diff, Cond.getValueType())); 10708 10709 // Add the base if non-zero. 10710 if (FalseC->getAPIntValue() != 0) 10711 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10712 SDValue(FalseC, 0)); 10713 return Cond; 10714 } 10715 } 10716 } 10717 } 10718 10719 return SDValue(); 10720} 10721 10722/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 10723static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 10724 TargetLowering::DAGCombinerInfo &DCI) { 10725 DebugLoc DL = N->getDebugLoc(); 10726 10727 // If the flag operand isn't dead, don't touch this CMOV. 10728 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 10729 return SDValue(); 10730 10731 // If this is a select between two integer constants, try to do some 10732 // optimizations. Note that the operands are ordered the opposite of SELECT 10733 // operands. 10734 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 10735 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 10736 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 10737 // larger than FalseC (the false value). 10738 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 10739 10740 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 10741 CC = X86::GetOppositeBranchCondition(CC); 10742 std::swap(TrueC, FalseC); 10743 } 10744 10745 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 10746 // This is efficient for any integer data type (including i8/i16) and 10747 // shift amount. 10748 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 10749 SDValue Cond = N->getOperand(3); 10750 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10751 DAG.getConstant(CC, MVT::i8), Cond); 10752 10753 // Zero extend the condition if needed. 10754 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 10755 10756 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 10757 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 10758 DAG.getConstant(ShAmt, MVT::i8)); 10759 if (N->getNumValues() == 2) // Dead flag value? 10760 return DCI.CombineTo(N, Cond, SDValue()); 10761 return Cond; 10762 } 10763 10764 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 10765 // for any integer data type, including i8/i16. 10766 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 10767 SDValue Cond = N->getOperand(3); 10768 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10769 DAG.getConstant(CC, MVT::i8), Cond); 10770 10771 // Zero extend the condition if needed. 10772 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 10773 FalseC->getValueType(0), Cond); 10774 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10775 SDValue(FalseC, 0)); 10776 10777 if (N->getNumValues() == 2) // Dead flag value? 10778 return DCI.CombineTo(N, Cond, SDValue()); 10779 return Cond; 10780 } 10781 10782 // Optimize cases that will turn into an LEA instruction. This requires 10783 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 10784 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 10785 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 10786 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 10787 10788 bool isFastMultiplier = false; 10789 if (Diff < 10) { 10790 switch ((unsigned char)Diff) { 10791 default: break; 10792 case 1: // result = add base, cond 10793 case 2: // result = lea base( , cond*2) 10794 case 3: // result = lea base(cond, cond*2) 10795 case 4: // result = lea base( , cond*4) 10796 case 5: // result = lea base(cond, cond*4) 10797 case 8: // result = lea base( , cond*8) 10798 case 9: // result = lea base(cond, cond*8) 10799 isFastMultiplier = true; 10800 break; 10801 } 10802 } 10803 10804 if (isFastMultiplier) { 10805 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 10806 SDValue Cond = N->getOperand(3); 10807 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10808 DAG.getConstant(CC, MVT::i8), Cond); 10809 // Zero extend the condition if needed. 10810 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 10811 Cond); 10812 // Scale the condition by the difference. 10813 if (Diff != 1) 10814 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 10815 DAG.getConstant(Diff, Cond.getValueType())); 10816 10817 // Add the base if non-zero. 10818 if (FalseC->getAPIntValue() != 0) 10819 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10820 SDValue(FalseC, 0)); 10821 if (N->getNumValues() == 2) // Dead flag value? 10822 return DCI.CombineTo(N, Cond, SDValue()); 10823 return Cond; 10824 } 10825 } 10826 } 10827 } 10828 return SDValue(); 10829} 10830 10831 10832/// PerformMulCombine - Optimize a single multiply with constant into two 10833/// in order to implement it with two cheaper instructions, e.g. 10834/// LEA + SHL, LEA + LEA. 10835static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 10836 TargetLowering::DAGCombinerInfo &DCI) { 10837 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 10838 return SDValue(); 10839 10840 EVT VT = N->getValueType(0); 10841 if (VT != MVT::i64) 10842 return SDValue(); 10843 10844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 10845 if (!C) 10846 return SDValue(); 10847 uint64_t MulAmt = C->getZExtValue(); 10848 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 10849 return SDValue(); 10850 10851 uint64_t MulAmt1 = 0; 10852 uint64_t MulAmt2 = 0; 10853 if ((MulAmt % 9) == 0) { 10854 MulAmt1 = 9; 10855 MulAmt2 = MulAmt / 9; 10856 } else if ((MulAmt % 5) == 0) { 10857 MulAmt1 = 5; 10858 MulAmt2 = MulAmt / 5; 10859 } else if ((MulAmt % 3) == 0) { 10860 MulAmt1 = 3; 10861 MulAmt2 = MulAmt / 3; 10862 } 10863 if (MulAmt2 && 10864 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 10865 DebugLoc DL = N->getDebugLoc(); 10866 10867 if (isPowerOf2_64(MulAmt2) && 10868 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 10869 // If second multiplifer is pow2, issue it first. We want the multiply by 10870 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 10871 // is an add. 10872 std::swap(MulAmt1, MulAmt2); 10873 10874 SDValue NewMul; 10875 if (isPowerOf2_64(MulAmt1)) 10876 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 10877 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 10878 else 10879 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 10880 DAG.getConstant(MulAmt1, VT)); 10881 10882 if (isPowerOf2_64(MulAmt2)) 10883 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 10884 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 10885 else 10886 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 10887 DAG.getConstant(MulAmt2, VT)); 10888 10889 // Do not add new nodes to DAG combiner worklist. 10890 DCI.CombineTo(N, NewMul, false); 10891 } 10892 return SDValue(); 10893} 10894 10895static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 10896 SDValue N0 = N->getOperand(0); 10897 SDValue N1 = N->getOperand(1); 10898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 10899 EVT VT = N0.getValueType(); 10900 10901 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 10902 // since the result of setcc_c is all zero's or all ones. 10903 if (N1C && N0.getOpcode() == ISD::AND && 10904 N0.getOperand(1).getOpcode() == ISD::Constant) { 10905 SDValue N00 = N0.getOperand(0); 10906 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 10907 ((N00.getOpcode() == ISD::ANY_EXTEND || 10908 N00.getOpcode() == ISD::ZERO_EXTEND) && 10909 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 10910 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 10911 APInt ShAmt = N1C->getAPIntValue(); 10912 Mask = Mask.shl(ShAmt); 10913 if (Mask != 0) 10914 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 10915 N00, DAG.getConstant(Mask, VT)); 10916 } 10917 } 10918 10919 return SDValue(); 10920} 10921 10922/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 10923/// when possible. 10924static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 10925 const X86Subtarget *Subtarget) { 10926 EVT VT = N->getValueType(0); 10927 if (!VT.isVector() && VT.isInteger() && 10928 N->getOpcode() == ISD::SHL) 10929 return PerformSHLCombine(N, DAG); 10930 10931 // On X86 with SSE2 support, we can transform this to a vector shift if 10932 // all elements are shifted by the same amount. We can't do this in legalize 10933 // because the a constant vector is typically transformed to a constant pool 10934 // so we have no knowledge of the shift amount. 10935 if (!Subtarget->hasSSE2()) 10936 return SDValue(); 10937 10938 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 10939 return SDValue(); 10940 10941 SDValue ShAmtOp = N->getOperand(1); 10942 EVT EltVT = VT.getVectorElementType(); 10943 DebugLoc DL = N->getDebugLoc(); 10944 SDValue BaseShAmt = SDValue(); 10945 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 10946 unsigned NumElts = VT.getVectorNumElements(); 10947 unsigned i = 0; 10948 for (; i != NumElts; ++i) { 10949 SDValue Arg = ShAmtOp.getOperand(i); 10950 if (Arg.getOpcode() == ISD::UNDEF) continue; 10951 BaseShAmt = Arg; 10952 break; 10953 } 10954 for (; i != NumElts; ++i) { 10955 SDValue Arg = ShAmtOp.getOperand(i); 10956 if (Arg.getOpcode() == ISD::UNDEF) continue; 10957 if (Arg != BaseShAmt) { 10958 return SDValue(); 10959 } 10960 } 10961 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 10962 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 10963 SDValue InVec = ShAmtOp.getOperand(0); 10964 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 10965 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 10966 unsigned i = 0; 10967 for (; i != NumElts; ++i) { 10968 SDValue Arg = InVec.getOperand(i); 10969 if (Arg.getOpcode() == ISD::UNDEF) continue; 10970 BaseShAmt = Arg; 10971 break; 10972 } 10973 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 10974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 10975 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 10976 if (C->getZExtValue() == SplatIdx) 10977 BaseShAmt = InVec.getOperand(1); 10978 } 10979 } 10980 if (BaseShAmt.getNode() == 0) 10981 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 10982 DAG.getIntPtrConstant(0)); 10983 } else 10984 return SDValue(); 10985 10986 // The shift amount is an i32. 10987 if (EltVT.bitsGT(MVT::i32)) 10988 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 10989 else if (EltVT.bitsLT(MVT::i32)) 10990 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 10991 10992 // The shift amount is identical so we can do a vector shift. 10993 SDValue ValOp = N->getOperand(0); 10994 switch (N->getOpcode()) { 10995 default: 10996 llvm_unreachable("Unknown shift opcode!"); 10997 break; 10998 case ISD::SHL: 10999 if (VT == MVT::v2i64) 11000 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11001 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 11002 ValOp, BaseShAmt); 11003 if (VT == MVT::v4i32) 11004 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11005 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 11006 ValOp, BaseShAmt); 11007 if (VT == MVT::v8i16) 11008 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11009 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 11010 ValOp, BaseShAmt); 11011 break; 11012 case ISD::SRA: 11013 if (VT == MVT::v4i32) 11014 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11015 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 11016 ValOp, BaseShAmt); 11017 if (VT == MVT::v8i16) 11018 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11019 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 11020 ValOp, BaseShAmt); 11021 break; 11022 case ISD::SRL: 11023 if (VT == MVT::v2i64) 11024 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11025 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 11026 ValOp, BaseShAmt); 11027 if (VT == MVT::v4i32) 11028 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11029 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 11030 ValOp, BaseShAmt); 11031 if (VT == MVT::v8i16) 11032 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11033 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 11034 ValOp, BaseShAmt); 11035 break; 11036 } 11037 return SDValue(); 11038} 11039 11040static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 11041 TargetLowering::DAGCombinerInfo &DCI, 11042 const X86Subtarget *Subtarget) { 11043 if (DCI.isBeforeLegalizeOps()) 11044 return SDValue(); 11045 11046 EVT VT = N->getValueType(0); 11047 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 11048 return SDValue(); 11049 11050 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 11051 SDValue N0 = N->getOperand(0); 11052 SDValue N1 = N->getOperand(1); 11053 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 11054 std::swap(N0, N1); 11055 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 11056 return SDValue(); 11057 if (!N0.hasOneUse() || !N1.hasOneUse()) 11058 return SDValue(); 11059 11060 SDValue ShAmt0 = N0.getOperand(1); 11061 if (ShAmt0.getValueType() != MVT::i8) 11062 return SDValue(); 11063 SDValue ShAmt1 = N1.getOperand(1); 11064 if (ShAmt1.getValueType() != MVT::i8) 11065 return SDValue(); 11066 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 11067 ShAmt0 = ShAmt0.getOperand(0); 11068 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 11069 ShAmt1 = ShAmt1.getOperand(0); 11070 11071 DebugLoc DL = N->getDebugLoc(); 11072 unsigned Opc = X86ISD::SHLD; 11073 SDValue Op0 = N0.getOperand(0); 11074 SDValue Op1 = N1.getOperand(0); 11075 if (ShAmt0.getOpcode() == ISD::SUB) { 11076 Opc = X86ISD::SHRD; 11077 std::swap(Op0, Op1); 11078 std::swap(ShAmt0, ShAmt1); 11079 } 11080 11081 unsigned Bits = VT.getSizeInBits(); 11082 if (ShAmt1.getOpcode() == ISD::SUB) { 11083 SDValue Sum = ShAmt1.getOperand(0); 11084 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 11085 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 11086 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 11087 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 11088 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 11089 return DAG.getNode(Opc, DL, VT, 11090 Op0, Op1, 11091 DAG.getNode(ISD::TRUNCATE, DL, 11092 MVT::i8, ShAmt0)); 11093 } 11094 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 11095 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 11096 if (ShAmt0C && 11097 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 11098 return DAG.getNode(Opc, DL, VT, 11099 N0.getOperand(0), N1.getOperand(0), 11100 DAG.getNode(ISD::TRUNCATE, DL, 11101 MVT::i8, ShAmt0)); 11102 } 11103 11104 return SDValue(); 11105} 11106 11107/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 11108static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 11109 const X86Subtarget *Subtarget) { 11110 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 11111 // the FP state in cases where an emms may be missing. 11112 // A preferable solution to the general problem is to figure out the right 11113 // places to insert EMMS. This qualifies as a quick hack. 11114 11115 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 11116 StoreSDNode *St = cast<StoreSDNode>(N); 11117 EVT VT = St->getValue().getValueType(); 11118 if (VT.getSizeInBits() != 64) 11119 return SDValue(); 11120 11121 const Function *F = DAG.getMachineFunction().getFunction(); 11122 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 11123 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 11124 && Subtarget->hasSSE2(); 11125 if ((VT.isVector() || 11126 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 11127 isa<LoadSDNode>(St->getValue()) && 11128 !cast<LoadSDNode>(St->getValue())->isVolatile() && 11129 St->getChain().hasOneUse() && !St->isVolatile()) { 11130 SDNode* LdVal = St->getValue().getNode(); 11131 LoadSDNode *Ld = 0; 11132 int TokenFactorIndex = -1; 11133 SmallVector<SDValue, 8> Ops; 11134 SDNode* ChainVal = St->getChain().getNode(); 11135 // Must be a store of a load. We currently handle two cases: the load 11136 // is a direct child, and it's under an intervening TokenFactor. It is 11137 // possible to dig deeper under nested TokenFactors. 11138 if (ChainVal == LdVal) 11139 Ld = cast<LoadSDNode>(St->getChain()); 11140 else if (St->getValue().hasOneUse() && 11141 ChainVal->getOpcode() == ISD::TokenFactor) { 11142 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 11143 if (ChainVal->getOperand(i).getNode() == LdVal) { 11144 TokenFactorIndex = i; 11145 Ld = cast<LoadSDNode>(St->getValue()); 11146 } else 11147 Ops.push_back(ChainVal->getOperand(i)); 11148 } 11149 } 11150 11151 if (!Ld || !ISD::isNormalLoad(Ld)) 11152 return SDValue(); 11153 11154 // If this is not the MMX case, i.e. we are just turning i64 load/store 11155 // into f64 load/store, avoid the transformation if there are multiple 11156 // uses of the loaded value. 11157 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 11158 return SDValue(); 11159 11160 DebugLoc LdDL = Ld->getDebugLoc(); 11161 DebugLoc StDL = N->getDebugLoc(); 11162 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 11163 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 11164 // pair instead. 11165 if (Subtarget->is64Bit() || F64IsLegal) { 11166 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 11167 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 11168 Ld->getPointerInfo(), Ld->isVolatile(), 11169 Ld->isNonTemporal(), Ld->getAlignment()); 11170 SDValue NewChain = NewLd.getValue(1); 11171 if (TokenFactorIndex != -1) { 11172 Ops.push_back(NewChain); 11173 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 11174 Ops.size()); 11175 } 11176 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 11177 St->getPointerInfo(), 11178 St->isVolatile(), St->isNonTemporal(), 11179 St->getAlignment()); 11180 } 11181 11182 // Otherwise, lower to two pairs of 32-bit loads / stores. 11183 SDValue LoAddr = Ld->getBasePtr(); 11184 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 11185 DAG.getConstant(4, MVT::i32)); 11186 11187 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 11188 Ld->getPointerInfo(), 11189 Ld->isVolatile(), Ld->isNonTemporal(), 11190 Ld->getAlignment()); 11191 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 11192 Ld->getPointerInfo().getWithOffset(4), 11193 Ld->isVolatile(), Ld->isNonTemporal(), 11194 MinAlign(Ld->getAlignment(), 4)); 11195 11196 SDValue NewChain = LoLd.getValue(1); 11197 if (TokenFactorIndex != -1) { 11198 Ops.push_back(LoLd); 11199 Ops.push_back(HiLd); 11200 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 11201 Ops.size()); 11202 } 11203 11204 LoAddr = St->getBasePtr(); 11205 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 11206 DAG.getConstant(4, MVT::i32)); 11207 11208 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 11209 St->getPointerInfo(), 11210 St->isVolatile(), St->isNonTemporal(), 11211 St->getAlignment()); 11212 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 11213 St->getPointerInfo().getWithOffset(4), 11214 St->isVolatile(), 11215 St->isNonTemporal(), 11216 MinAlign(St->getAlignment(), 4)); 11217 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 11218 } 11219 return SDValue(); 11220} 11221 11222/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 11223/// X86ISD::FXOR nodes. 11224static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 11225 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 11226 // F[X]OR(0.0, x) -> x 11227 // F[X]OR(x, 0.0) -> x 11228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 11229 if (C->getValueAPF().isPosZero()) 11230 return N->getOperand(1); 11231 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 11232 if (C->getValueAPF().isPosZero()) 11233 return N->getOperand(0); 11234 return SDValue(); 11235} 11236 11237/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 11238static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 11239 // FAND(0.0, x) -> 0.0 11240 // FAND(x, 0.0) -> 0.0 11241 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 11242 if (C->getValueAPF().isPosZero()) 11243 return N->getOperand(0); 11244 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 11245 if (C->getValueAPF().isPosZero()) 11246 return N->getOperand(1); 11247 return SDValue(); 11248} 11249 11250static SDValue PerformBTCombine(SDNode *N, 11251 SelectionDAG &DAG, 11252 TargetLowering::DAGCombinerInfo &DCI) { 11253 // BT ignores high bits in the bit index operand. 11254 SDValue Op1 = N->getOperand(1); 11255 if (Op1.hasOneUse()) { 11256 unsigned BitWidth = Op1.getValueSizeInBits(); 11257 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 11258 APInt KnownZero, KnownOne; 11259 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 11260 !DCI.isBeforeLegalizeOps()); 11261 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11262 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 11263 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 11264 DCI.CommitTargetLoweringOpt(TLO); 11265 } 11266 return SDValue(); 11267} 11268 11269static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 11270 SDValue Op = N->getOperand(0); 11271 if (Op.getOpcode() == ISD::BITCAST) 11272 Op = Op.getOperand(0); 11273 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 11274 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 11275 VT.getVectorElementType().getSizeInBits() == 11276 OpVT.getVectorElementType().getSizeInBits()) { 11277 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 11278 } 11279 return SDValue(); 11280} 11281 11282static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 11283 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 11284 // (and (i32 x86isd::setcc_carry), 1) 11285 // This eliminates the zext. This transformation is necessary because 11286 // ISD::SETCC is always legalized to i8. 11287 DebugLoc dl = N->getDebugLoc(); 11288 SDValue N0 = N->getOperand(0); 11289 EVT VT = N->getValueType(0); 11290 if (N0.getOpcode() == ISD::AND && 11291 N0.hasOneUse() && 11292 N0.getOperand(0).hasOneUse()) { 11293 SDValue N00 = N0.getOperand(0); 11294 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 11295 return SDValue(); 11296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 11297 if (!C || C->getZExtValue() != 1) 11298 return SDValue(); 11299 return DAG.getNode(ISD::AND, dl, VT, 11300 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 11301 N00.getOperand(0), N00.getOperand(1)), 11302 DAG.getConstant(1, VT)); 11303 } 11304 11305 return SDValue(); 11306} 11307 11308SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 11309 DAGCombinerInfo &DCI) const { 11310 SelectionDAG &DAG = DCI.DAG; 11311 switch (N->getOpcode()) { 11312 default: break; 11313 case ISD::EXTRACT_VECTOR_ELT: 11314 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 11315 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 11316 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 11317 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 11318 case ISD::SHL: 11319 case ISD::SRA: 11320 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 11321 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 11322 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 11323 case X86ISD::FXOR: 11324 case X86ISD::FOR: return PerformFORCombine(N, DAG); 11325 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 11326 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 11327 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 11328 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 11329 case X86ISD::SHUFPS: // Handle all target specific shuffles 11330 case X86ISD::SHUFPD: 11331 case X86ISD::PALIGN: 11332 case X86ISD::PUNPCKHBW: 11333 case X86ISD::PUNPCKHWD: 11334 case X86ISD::PUNPCKHDQ: 11335 case X86ISD::PUNPCKHQDQ: 11336 case X86ISD::UNPCKHPS: 11337 case X86ISD::UNPCKHPD: 11338 case X86ISD::PUNPCKLBW: 11339 case X86ISD::PUNPCKLWD: 11340 case X86ISD::PUNPCKLDQ: 11341 case X86ISD::PUNPCKLQDQ: 11342 case X86ISD::UNPCKLPS: 11343 case X86ISD::UNPCKLPD: 11344 case X86ISD::MOVHLPS: 11345 case X86ISD::MOVLHPS: 11346 case X86ISD::PSHUFD: 11347 case X86ISD::PSHUFHW: 11348 case X86ISD::PSHUFLW: 11349 case X86ISD::MOVSS: 11350 case X86ISD::MOVSD: 11351 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 11352 } 11353 11354 return SDValue(); 11355} 11356 11357/// isTypeDesirableForOp - Return true if the target has native support for 11358/// the specified value type and it is 'desirable' to use the type for the 11359/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 11360/// instruction encodings are longer and some i16 instructions are slow. 11361bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 11362 if (!isTypeLegal(VT)) 11363 return false; 11364 if (VT != MVT::i16) 11365 return true; 11366 11367 switch (Opc) { 11368 default: 11369 return true; 11370 case ISD::LOAD: 11371 case ISD::SIGN_EXTEND: 11372 case ISD::ZERO_EXTEND: 11373 case ISD::ANY_EXTEND: 11374 case ISD::SHL: 11375 case ISD::SRL: 11376 case ISD::SUB: 11377 case ISD::ADD: 11378 case ISD::MUL: 11379 case ISD::AND: 11380 case ISD::OR: 11381 case ISD::XOR: 11382 return false; 11383 } 11384} 11385 11386/// IsDesirableToPromoteOp - This method query the target whether it is 11387/// beneficial for dag combiner to promote the specified node. If true, it 11388/// should return the desired promotion type by reference. 11389bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 11390 EVT VT = Op.getValueType(); 11391 if (VT != MVT::i16) 11392 return false; 11393 11394 bool Promote = false; 11395 bool Commute = false; 11396 switch (Op.getOpcode()) { 11397 default: break; 11398 case ISD::LOAD: { 11399 LoadSDNode *LD = cast<LoadSDNode>(Op); 11400 // If the non-extending load has a single use and it's not live out, then it 11401 // might be folded. 11402 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 11403 Op.hasOneUse()*/) { 11404 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 11405 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 11406 // The only case where we'd want to promote LOAD (rather then it being 11407 // promoted as an operand is when it's only use is liveout. 11408 if (UI->getOpcode() != ISD::CopyToReg) 11409 return false; 11410 } 11411 } 11412 Promote = true; 11413 break; 11414 } 11415 case ISD::SIGN_EXTEND: 11416 case ISD::ZERO_EXTEND: 11417 case ISD::ANY_EXTEND: 11418 Promote = true; 11419 break; 11420 case ISD::SHL: 11421 case ISD::SRL: { 11422 SDValue N0 = Op.getOperand(0); 11423 // Look out for (store (shl (load), x)). 11424 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 11425 return false; 11426 Promote = true; 11427 break; 11428 } 11429 case ISD::ADD: 11430 case ISD::MUL: 11431 case ISD::AND: 11432 case ISD::OR: 11433 case ISD::XOR: 11434 Commute = true; 11435 // fallthrough 11436 case ISD::SUB: { 11437 SDValue N0 = Op.getOperand(0); 11438 SDValue N1 = Op.getOperand(1); 11439 if (!Commute && MayFoldLoad(N1)) 11440 return false; 11441 // Avoid disabling potential load folding opportunities. 11442 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 11443 return false; 11444 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 11445 return false; 11446 Promote = true; 11447 } 11448 } 11449 11450 PVT = MVT::i32; 11451 return Promote; 11452} 11453 11454//===----------------------------------------------------------------------===// 11455// X86 Inline Assembly Support 11456//===----------------------------------------------------------------------===// 11457 11458static bool LowerToBSwap(CallInst *CI) { 11459 // FIXME: this should verify that we are targetting a 486 or better. If not, 11460 // we will turn this bswap into something that will be lowered to logical ops 11461 // instead of emitting the bswap asm. For now, we don't support 486 or lower 11462 // so don't worry about this. 11463 11464 // Verify this is a simple bswap. 11465 if (CI->getNumArgOperands() != 1 || 11466 CI->getType() != CI->getArgOperand(0)->getType() || 11467 !CI->getType()->isIntegerTy()) 11468 return false; 11469 11470 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 11471 if (!Ty || Ty->getBitWidth() % 16 != 0) 11472 return false; 11473 11474 // Okay, we can do this xform, do so now. 11475 const Type *Tys[] = { Ty }; 11476 Module *M = CI->getParent()->getParent()->getParent(); 11477 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 11478 11479 Value *Op = CI->getArgOperand(0); 11480 Op = CallInst::Create(Int, Op, CI->getName(), CI); 11481 11482 CI->replaceAllUsesWith(Op); 11483 CI->eraseFromParent(); 11484 return true; 11485} 11486 11487bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 11488 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 11489 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 11490 11491 std::string AsmStr = IA->getAsmString(); 11492 11493 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 11494 SmallVector<StringRef, 4> AsmPieces; 11495 SplitString(AsmStr, AsmPieces, ";\n"); 11496 11497 switch (AsmPieces.size()) { 11498 default: return false; 11499 case 1: 11500 AsmStr = AsmPieces[0]; 11501 AsmPieces.clear(); 11502 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 11503 11504 // bswap $0 11505 if (AsmPieces.size() == 2 && 11506 (AsmPieces[0] == "bswap" || 11507 AsmPieces[0] == "bswapq" || 11508 AsmPieces[0] == "bswapl") && 11509 (AsmPieces[1] == "$0" || 11510 AsmPieces[1] == "${0:q}")) { 11511 // No need to check constraints, nothing other than the equivalent of 11512 // "=r,0" would be valid here. 11513 return LowerToBSwap(CI); 11514 } 11515 // rorw $$8, ${0:w} --> llvm.bswap.i16 11516 if (CI->getType()->isIntegerTy(16) && 11517 AsmPieces.size() == 3 && 11518 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 11519 AsmPieces[1] == "$$8," && 11520 AsmPieces[2] == "${0:w}" && 11521 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 11522 AsmPieces.clear(); 11523 const std::string &Constraints = IA->getConstraintString(); 11524 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 11525 std::sort(AsmPieces.begin(), AsmPieces.end()); 11526 if (AsmPieces.size() == 4 && 11527 AsmPieces[0] == "~{cc}" && 11528 AsmPieces[1] == "~{dirflag}" && 11529 AsmPieces[2] == "~{flags}" && 11530 AsmPieces[3] == "~{fpsr}") { 11531 return LowerToBSwap(CI); 11532 } 11533 } 11534 break; 11535 case 3: 11536 if (CI->getType()->isIntegerTy(32) && 11537 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 11538 SmallVector<StringRef, 4> Words; 11539 SplitString(AsmPieces[0], Words, " \t,"); 11540 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 11541 Words[2] == "${0:w}") { 11542 Words.clear(); 11543 SplitString(AsmPieces[1], Words, " \t,"); 11544 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 11545 Words[2] == "$0") { 11546 Words.clear(); 11547 SplitString(AsmPieces[2], Words, " \t,"); 11548 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 11549 Words[2] == "${0:w}") { 11550 AsmPieces.clear(); 11551 const std::string &Constraints = IA->getConstraintString(); 11552 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 11553 std::sort(AsmPieces.begin(), AsmPieces.end()); 11554 if (AsmPieces.size() == 4 && 11555 AsmPieces[0] == "~{cc}" && 11556 AsmPieces[1] == "~{dirflag}" && 11557 AsmPieces[2] == "~{flags}" && 11558 AsmPieces[3] == "~{fpsr}") { 11559 return LowerToBSwap(CI); 11560 } 11561 } 11562 } 11563 } 11564 } 11565 if (CI->getType()->isIntegerTy(64) && 11566 Constraints.size() >= 2 && 11567 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 11568 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 11569 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 11570 SmallVector<StringRef, 4> Words; 11571 SplitString(AsmPieces[0], Words, " \t"); 11572 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 11573 Words.clear(); 11574 SplitString(AsmPieces[1], Words, " \t"); 11575 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 11576 Words.clear(); 11577 SplitString(AsmPieces[2], Words, " \t,"); 11578 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 11579 Words[2] == "%edx") { 11580 return LowerToBSwap(CI); 11581 } 11582 } 11583 } 11584 } 11585 break; 11586 } 11587 return false; 11588} 11589 11590 11591 11592/// getConstraintType - Given a constraint letter, return the type of 11593/// constraint it is for this target. 11594X86TargetLowering::ConstraintType 11595X86TargetLowering::getConstraintType(const std::string &Constraint) const { 11596 if (Constraint.size() == 1) { 11597 switch (Constraint[0]) { 11598 case 'R': 11599 case 'q': 11600 case 'Q': 11601 case 'f': 11602 case 't': 11603 case 'u': 11604 case 'y': 11605 case 'x': 11606 case 'Y': 11607 return C_RegisterClass; 11608 case 'a': 11609 case 'b': 11610 case 'c': 11611 case 'd': 11612 case 'S': 11613 case 'D': 11614 case 'A': 11615 return C_Register; 11616 case 'I': 11617 case 'J': 11618 case 'K': 11619 case 'L': 11620 case 'M': 11621 case 'N': 11622 case 'G': 11623 case 'C': 11624 case 'e': 11625 case 'Z': 11626 return C_Other; 11627 default: 11628 break; 11629 } 11630 } 11631 return TargetLowering::getConstraintType(Constraint); 11632} 11633 11634/// Examine constraint type and operand type and determine a weight value. 11635/// This object must already have been set up with the operand type 11636/// and the current alternative constraint selected. 11637TargetLowering::ConstraintWeight 11638 X86TargetLowering::getSingleConstraintMatchWeight( 11639 AsmOperandInfo &info, const char *constraint) const { 11640 ConstraintWeight weight = CW_Invalid; 11641 Value *CallOperandVal = info.CallOperandVal; 11642 // If we don't have a value, we can't do a match, 11643 // but allow it at the lowest weight. 11644 if (CallOperandVal == NULL) 11645 return CW_Default; 11646 const Type *type = CallOperandVal->getType(); 11647 // Look at the constraint type. 11648 switch (*constraint) { 11649 default: 11650 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 11651 case 'R': 11652 case 'q': 11653 case 'Q': 11654 case 'a': 11655 case 'b': 11656 case 'c': 11657 case 'd': 11658 case 'S': 11659 case 'D': 11660 case 'A': 11661 if (CallOperandVal->getType()->isIntegerTy()) 11662 weight = CW_SpecificReg; 11663 break; 11664 case 'f': 11665 case 't': 11666 case 'u': 11667 if (type->isFloatingPointTy()) 11668 weight = CW_SpecificReg; 11669 break; 11670 case 'y': 11671 if (type->isX86_MMXTy() && !DisableMMX && Subtarget->hasMMX()) 11672 weight = CW_SpecificReg; 11673 break; 11674 case 'x': 11675 case 'Y': 11676 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) 11677 weight = CW_Register; 11678 break; 11679 case 'I': 11680 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 11681 if (C->getZExtValue() <= 31) 11682 weight = CW_Constant; 11683 } 11684 break; 11685 case 'J': 11686 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11687 if (C->getZExtValue() <= 63) 11688 weight = CW_Constant; 11689 } 11690 break; 11691 case 'K': 11692 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11693 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 11694 weight = CW_Constant; 11695 } 11696 break; 11697 case 'L': 11698 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11699 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 11700 weight = CW_Constant; 11701 } 11702 break; 11703 case 'M': 11704 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11705 if (C->getZExtValue() <= 3) 11706 weight = CW_Constant; 11707 } 11708 break; 11709 case 'N': 11710 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11711 if (C->getZExtValue() <= 0xff) 11712 weight = CW_Constant; 11713 } 11714 break; 11715 case 'G': 11716 case 'C': 11717 if (dyn_cast<ConstantFP>(CallOperandVal)) { 11718 weight = CW_Constant; 11719 } 11720 break; 11721 case 'e': 11722 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11723 if ((C->getSExtValue() >= -0x80000000LL) && 11724 (C->getSExtValue() <= 0x7fffffffLL)) 11725 weight = CW_Constant; 11726 } 11727 break; 11728 case 'Z': 11729 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 11730 if (C->getZExtValue() <= 0xffffffff) 11731 weight = CW_Constant; 11732 } 11733 break; 11734 } 11735 return weight; 11736} 11737 11738/// LowerXConstraint - try to replace an X constraint, which matches anything, 11739/// with another that has more specific requirements based on the type of the 11740/// corresponding operand. 11741const char *X86TargetLowering:: 11742LowerXConstraint(EVT ConstraintVT) const { 11743 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 11744 // 'f' like normal targets. 11745 if (ConstraintVT.isFloatingPoint()) { 11746 if (Subtarget->hasSSE2()) 11747 return "Y"; 11748 if (Subtarget->hasSSE1()) 11749 return "x"; 11750 } 11751 11752 return TargetLowering::LowerXConstraint(ConstraintVT); 11753} 11754 11755/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 11756/// vector. If it is invalid, don't add anything to Ops. 11757void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 11758 char Constraint, 11759 std::vector<SDValue>&Ops, 11760 SelectionDAG &DAG) const { 11761 SDValue Result(0, 0); 11762 11763 switch (Constraint) { 11764 default: break; 11765 case 'I': 11766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11767 if (C->getZExtValue() <= 31) { 11768 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 11769 break; 11770 } 11771 } 11772 return; 11773 case 'J': 11774 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11775 if (C->getZExtValue() <= 63) { 11776 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 11777 break; 11778 } 11779 } 11780 return; 11781 case 'K': 11782 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11783 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 11784 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 11785 break; 11786 } 11787 } 11788 return; 11789 case 'N': 11790 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11791 if (C->getZExtValue() <= 255) { 11792 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 11793 break; 11794 } 11795 } 11796 return; 11797 case 'e': { 11798 // 32-bit signed value 11799 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11800 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 11801 C->getSExtValue())) { 11802 // Widen to 64 bits here to get it sign extended. 11803 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 11804 break; 11805 } 11806 // FIXME gcc accepts some relocatable values here too, but only in certain 11807 // memory models; it's complicated. 11808 } 11809 return; 11810 } 11811 case 'Z': { 11812 // 32-bit unsigned value 11813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 11814 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 11815 C->getZExtValue())) { 11816 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 11817 break; 11818 } 11819 } 11820 // FIXME gcc accepts some relocatable values here too, but only in certain 11821 // memory models; it's complicated. 11822 return; 11823 } 11824 case 'i': { 11825 // Literal immediates are always ok. 11826 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 11827 // Widen to 64 bits here to get it sign extended. 11828 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 11829 break; 11830 } 11831 11832 // In any sort of PIC mode addresses need to be computed at runtime by 11833 // adding in a register or some sort of table lookup. These can't 11834 // be used as immediates. 11835 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 11836 return; 11837 11838 // If we are in non-pic codegen mode, we allow the address of a global (with 11839 // an optional displacement) to be used with 'i'. 11840 GlobalAddressSDNode *GA = 0; 11841 int64_t Offset = 0; 11842 11843 // Match either (GA), (GA+C), (GA+C1+C2), etc. 11844 while (1) { 11845 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 11846 Offset += GA->getOffset(); 11847 break; 11848 } else if (Op.getOpcode() == ISD::ADD) { 11849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 11850 Offset += C->getZExtValue(); 11851 Op = Op.getOperand(0); 11852 continue; 11853 } 11854 } else if (Op.getOpcode() == ISD::SUB) { 11855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 11856 Offset += -C->getZExtValue(); 11857 Op = Op.getOperand(0); 11858 continue; 11859 } 11860 } 11861 11862 // Otherwise, this isn't something we can handle, reject it. 11863 return; 11864 } 11865 11866 const GlobalValue *GV = GA->getGlobal(); 11867 // If we require an extra load to get this address, as in PIC mode, we 11868 // can't accept it. 11869 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 11870 getTargetMachine()))) 11871 return; 11872 11873 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 11874 GA->getValueType(0), Offset); 11875 break; 11876 } 11877 } 11878 11879 if (Result.getNode()) { 11880 Ops.push_back(Result); 11881 return; 11882 } 11883 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 11884} 11885 11886std::vector<unsigned> X86TargetLowering:: 11887getRegClassForInlineAsmConstraint(const std::string &Constraint, 11888 EVT VT) const { 11889 if (Constraint.size() == 1) { 11890 // FIXME: not handling fp-stack yet! 11891 switch (Constraint[0]) { // GCC X86 Constraint Letters 11892 default: break; // Unknown constraint letter 11893 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 11894 if (Subtarget->is64Bit()) { 11895 if (VT == MVT::i32) 11896 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 11897 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 11898 X86::R10D,X86::R11D,X86::R12D, 11899 X86::R13D,X86::R14D,X86::R15D, 11900 X86::EBP, X86::ESP, 0); 11901 else if (VT == MVT::i16) 11902 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 11903 X86::SI, X86::DI, X86::R8W,X86::R9W, 11904 X86::R10W,X86::R11W,X86::R12W, 11905 X86::R13W,X86::R14W,X86::R15W, 11906 X86::BP, X86::SP, 0); 11907 else if (VT == MVT::i8) 11908 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 11909 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 11910 X86::R10B,X86::R11B,X86::R12B, 11911 X86::R13B,X86::R14B,X86::R15B, 11912 X86::BPL, X86::SPL, 0); 11913 11914 else if (VT == MVT::i64) 11915 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 11916 X86::RSI, X86::RDI, X86::R8, X86::R9, 11917 X86::R10, X86::R11, X86::R12, 11918 X86::R13, X86::R14, X86::R15, 11919 X86::RBP, X86::RSP, 0); 11920 11921 break; 11922 } 11923 // 32-bit fallthrough 11924 case 'Q': // Q_REGS 11925 if (VT == MVT::i32) 11926 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 11927 else if (VT == MVT::i16) 11928 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 11929 else if (VT == MVT::i8) 11930 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 11931 else if (VT == MVT::i64) 11932 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 11933 break; 11934 } 11935 } 11936 11937 return std::vector<unsigned>(); 11938} 11939 11940std::pair<unsigned, const TargetRegisterClass*> 11941X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 11942 EVT VT) const { 11943 // First, see if this is a constraint that directly corresponds to an LLVM 11944 // register class. 11945 if (Constraint.size() == 1) { 11946 // GCC Constraint Letters 11947 switch (Constraint[0]) { 11948 default: break; 11949 case 'r': // GENERAL_REGS 11950 case 'l': // INDEX_REGS 11951 if (VT == MVT::i8) 11952 return std::make_pair(0U, X86::GR8RegisterClass); 11953 if (VT == MVT::i16) 11954 return std::make_pair(0U, X86::GR16RegisterClass); 11955 if (VT == MVT::i32 || !Subtarget->is64Bit()) 11956 return std::make_pair(0U, X86::GR32RegisterClass); 11957 return std::make_pair(0U, X86::GR64RegisterClass); 11958 case 'R': // LEGACY_REGS 11959 if (VT == MVT::i8) 11960 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 11961 if (VT == MVT::i16) 11962 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 11963 if (VT == MVT::i32 || !Subtarget->is64Bit()) 11964 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 11965 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 11966 case 'f': // FP Stack registers. 11967 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 11968 // value to the correct fpstack register class. 11969 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 11970 return std::make_pair(0U, X86::RFP32RegisterClass); 11971 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 11972 return std::make_pair(0U, X86::RFP64RegisterClass); 11973 return std::make_pair(0U, X86::RFP80RegisterClass); 11974 case 'y': // MMX_REGS if MMX allowed. 11975 if (!Subtarget->hasMMX()) break; 11976 return std::make_pair(0U, X86::VR64RegisterClass); 11977 case 'Y': // SSE_REGS if SSE2 allowed 11978 if (!Subtarget->hasSSE2()) break; 11979 // FALL THROUGH. 11980 case 'x': // SSE_REGS if SSE1 allowed 11981 if (!Subtarget->hasSSE1()) break; 11982 11983 switch (VT.getSimpleVT().SimpleTy) { 11984 default: break; 11985 // Scalar SSE types. 11986 case MVT::f32: 11987 case MVT::i32: 11988 return std::make_pair(0U, X86::FR32RegisterClass); 11989 case MVT::f64: 11990 case MVT::i64: 11991 return std::make_pair(0U, X86::FR64RegisterClass); 11992 // Vector types. 11993 case MVT::v16i8: 11994 case MVT::v8i16: 11995 case MVT::v4i32: 11996 case MVT::v2i64: 11997 case MVT::v4f32: 11998 case MVT::v2f64: 11999 return std::make_pair(0U, X86::VR128RegisterClass); 12000 } 12001 break; 12002 } 12003 } 12004 12005 // Use the default implementation in TargetLowering to convert the register 12006 // constraint into a member of a register class. 12007 std::pair<unsigned, const TargetRegisterClass*> Res; 12008 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 12009 12010 // Not found as a standard register? 12011 if (Res.second == 0) { 12012 // Map st(0) -> st(7) -> ST0 12013 if (Constraint.size() == 7 && Constraint[0] == '{' && 12014 tolower(Constraint[1]) == 's' && 12015 tolower(Constraint[2]) == 't' && 12016 Constraint[3] == '(' && 12017 (Constraint[4] >= '0' && Constraint[4] <= '7') && 12018 Constraint[5] == ')' && 12019 Constraint[6] == '}') { 12020 12021 Res.first = X86::ST0+Constraint[4]-'0'; 12022 Res.second = X86::RFP80RegisterClass; 12023 return Res; 12024 } 12025 12026 // GCC allows "st(0)" to be called just plain "st". 12027 if (StringRef("{st}").equals_lower(Constraint)) { 12028 Res.first = X86::ST0; 12029 Res.second = X86::RFP80RegisterClass; 12030 return Res; 12031 } 12032 12033 // flags -> EFLAGS 12034 if (StringRef("{flags}").equals_lower(Constraint)) { 12035 Res.first = X86::EFLAGS; 12036 Res.second = X86::CCRRegisterClass; 12037 return Res; 12038 } 12039 12040 // 'A' means EAX + EDX. 12041 if (Constraint == "A") { 12042 Res.first = X86::EAX; 12043 Res.second = X86::GR32_ADRegisterClass; 12044 return Res; 12045 } 12046 return Res; 12047 } 12048 12049 // Otherwise, check to see if this is a register class of the wrong value 12050 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 12051 // turn into {ax},{dx}. 12052 if (Res.second->hasType(VT)) 12053 return Res; // Correct type already, nothing to do. 12054 12055 // All of the single-register GCC register classes map their values onto 12056 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 12057 // really want an 8-bit or 32-bit register, map to the appropriate register 12058 // class and return the appropriate register. 12059 if (Res.second == X86::GR16RegisterClass) { 12060 if (VT == MVT::i8) { 12061 unsigned DestReg = 0; 12062 switch (Res.first) { 12063 default: break; 12064 case X86::AX: DestReg = X86::AL; break; 12065 case X86::DX: DestReg = X86::DL; break; 12066 case X86::CX: DestReg = X86::CL; break; 12067 case X86::BX: DestReg = X86::BL; break; 12068 } 12069 if (DestReg) { 12070 Res.first = DestReg; 12071 Res.second = X86::GR8RegisterClass; 12072 } 12073 } else if (VT == MVT::i32) { 12074 unsigned DestReg = 0; 12075 switch (Res.first) { 12076 default: break; 12077 case X86::AX: DestReg = X86::EAX; break; 12078 case X86::DX: DestReg = X86::EDX; break; 12079 case X86::CX: DestReg = X86::ECX; break; 12080 case X86::BX: DestReg = X86::EBX; break; 12081 case X86::SI: DestReg = X86::ESI; break; 12082 case X86::DI: DestReg = X86::EDI; break; 12083 case X86::BP: DestReg = X86::EBP; break; 12084 case X86::SP: DestReg = X86::ESP; break; 12085 } 12086 if (DestReg) { 12087 Res.first = DestReg; 12088 Res.second = X86::GR32RegisterClass; 12089 } 12090 } else if (VT == MVT::i64) { 12091 unsigned DestReg = 0; 12092 switch (Res.first) { 12093 default: break; 12094 case X86::AX: DestReg = X86::RAX; break; 12095 case X86::DX: DestReg = X86::RDX; break; 12096 case X86::CX: DestReg = X86::RCX; break; 12097 case X86::BX: DestReg = X86::RBX; break; 12098 case X86::SI: DestReg = X86::RSI; break; 12099 case X86::DI: DestReg = X86::RDI; break; 12100 case X86::BP: DestReg = X86::RBP; break; 12101 case X86::SP: DestReg = X86::RSP; break; 12102 } 12103 if (DestReg) { 12104 Res.first = DestReg; 12105 Res.second = X86::GR64RegisterClass; 12106 } 12107 } 12108 } else if (Res.second == X86::FR32RegisterClass || 12109 Res.second == X86::FR64RegisterClass || 12110 Res.second == X86::VR128RegisterClass) { 12111 // Handle references to XMM physical registers that got mapped into the 12112 // wrong class. This can happen with constraints like {xmm0} where the 12113 // target independent register mapper will just pick the first match it can 12114 // find, ignoring the required type. 12115 if (VT == MVT::f32) 12116 Res.second = X86::FR32RegisterClass; 12117 else if (VT == MVT::f64) 12118 Res.second = X86::FR64RegisterClass; 12119 else if (X86::VR128RegisterClass->hasType(VT)) 12120 Res.second = X86::VR128RegisterClass; 12121 } 12122 12123 return Res; 12124} 12125