X86ISelLowering.cpp revision a16d441430440d9255fe16441cea7a38e8f3c461
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VariadicFunction.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetOptions.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasSSE2(); 172 X86ScalarSSEf32 = Subtarget->hasSSE1(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 185 186 // For 64-bit since we have so many registers use the ILP scheduler, for 187 // 32-bit code use the register pressure specific scheduling. 188 if (Subtarget->is64Bit()) 189 setSchedulingPreference(Sched::ILP); 190 else 191 setSchedulingPreference(Sched::RegPressure); 192 setStackPointerRegisterToSaveRestore(X86StackPtr); 193 194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 195 // Setup Windows compiler runtime calls. 196 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 198 setLibcallName(RTLIB::SREM_I64, "_allrem"); 199 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 200 setLibcallName(RTLIB::MUL_I64, "_allmul"); 201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 210 } 211 212 if (Subtarget->isTargetDarwin()) { 213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 214 setUseUnderscoreSetJmp(false); 215 setUseUnderscoreLongJmp(false); 216 } else if (Subtarget->isTargetMingw()) { 217 // MS runtime is weird: it exports _setjmp, but longjmp! 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(false); 220 } else { 221 setUseUnderscoreSetJmp(true); 222 setUseUnderscoreLongJmp(true); 223 } 224 225 // Set up the register classes. 226 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 227 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 228 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 229 if (Subtarget->is64Bit()) 230 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 231 232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 234 // We don't accept any truncstore of integer registers. 235 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 240 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 241 242 // SETOEQ and SETUNE require checking two conditions. 243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 249 250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 251 // operation. 252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 259 } else if (!TM.Options.UseSoftFloat) { 260 // We have an algorithm for SSE2->double, and we turn this into a 261 // 64-bit FILD followed by conditional FADD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 // We have an algorithm for SSE2, and we turn this into a 64-bit 264 // FILD for other targets. 265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 266 } 267 268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 269 // this operation. 270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 272 273 if (!TM.Options.UseSoftFloat) { 274 // SSE has no i16 to fp conversion, only i32 275 if (X86ScalarSSEf32) { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 // f32 and f64 cases are Legal, f80 case is not 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } else { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 282 } 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 286 } 287 288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 289 // are Legal, f80 is custom lowered. 290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 292 293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 294 // this operation. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 297 298 if (X86ScalarSSEf32) { 299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 300 // f32 and f64 cases are Legal, f80 case is not 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } else { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 305 } 306 307 // Handle FP_TO_UINT by promoting the destination to a larger signed 308 // conversion. 309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 312 313 if (Subtarget->is64Bit()) { 314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 316 } else if (!TM.Options.UseSoftFloat) { 317 // Since AVX is a superset of SSE3, only check for SSE here. 318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 319 // Expand FP_TO_UINT into a select. 320 // FIXME: We would like to use a Custom expander here eventually to do 321 // the optimal thing for SSE vs. the default expansion in the legalizer. 322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 323 else 324 // With SSE3 we can use fisttpll to convert to a signed i64; without 325 // SSE, we're stuck with a fistpll. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 327 } 328 329 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 330 if (!X86ScalarSSEf64) { 331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 333 if (Subtarget->is64Bit()) { 334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 335 // Without SSE, i64->f64 goes through memory. 336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 337 } 338 } 339 340 // Scalar integer divide and remainder are lowered to use operations that 341 // produce two results, to match the available instructions. This exposes 342 // the two-result form to trivial CSE, which is able to combine x/y and x%y 343 // into a single instruction. 344 // 345 // Scalar integer multiply-high is also lowered to use two-result 346 // operations, to match the available instructions. However, plain multiply 347 // (low) operations are left as Legal, as there are single-result 348 // instructions for this in x86. Using the two-result multiply instructions 349 // when both high and low results are needed must be arranged by dagcombine. 350 for (unsigned i = 0, e = 4; i != e; ++i) { 351 MVT VT = IntVTs[i]; 352 setOperationAction(ISD::MULHS, VT, Expand); 353 setOperationAction(ISD::MULHU, VT, Expand); 354 setOperationAction(ISD::SDIV, VT, Expand); 355 setOperationAction(ISD::UDIV, VT, Expand); 356 setOperationAction(ISD::SREM, VT, Expand); 357 setOperationAction(ISD::UREM, VT, Expand); 358 359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 360 setOperationAction(ISD::ADDC, VT, Custom); 361 setOperationAction(ISD::ADDE, VT, Custom); 362 setOperationAction(ISD::SUBC, VT, Custom); 363 setOperationAction(ISD::SUBE, VT, Custom); 364 } 365 366 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 367 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 368 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f64 , Expand); 378 setOperationAction(ISD::FREM , MVT::f80 , Expand); 379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 380 381 // Promote the i8 variants and force them on up to i32 which has a shorter 382 // encoding. 383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 387 if (Subtarget->hasBMI()) { 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 390 if (Subtarget->is64Bit()) 391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 392 } else { 393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 395 if (Subtarget->is64Bit()) 396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 397 } 398 399 if (Subtarget->hasLZCNT()) { 400 // When promoting the i8 variants, force them to i32 for a shorter 401 // encoding. 402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 408 if (Subtarget->is64Bit()) 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 410 } else { 411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 417 if (Subtarget->is64Bit()) { 418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 420 } 421 } 422 423 if (Subtarget->hasPOPCNT()) { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 425 } else { 426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 429 if (Subtarget->is64Bit()) 430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 431 } 432 433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 435 436 // These should be promoted to a larger select which is supported. 437 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 438 // X86 wants to expand cmov itself. 439 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 440 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 441 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 443 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 444 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 446 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 449 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 450 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 451 if (Subtarget->is64Bit()) { 452 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 453 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 454 } 455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 456 457 // Darwin ABI issue. 458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 462 if (Subtarget->is64Bit()) 463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 466 if (Subtarget->is64Bit()) { 467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 472 } 473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 477 if (Subtarget->is64Bit()) { 478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 481 } 482 483 if (Subtarget->hasSSE1()) 484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 485 486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 488 489 // On X86 and X86-64, atomic operations are lowered to locked instructions. 490 // Locked instructions, in turn, have implicit fence semantics (all memory 491 // operations are flushed before issuing the locked instruction, and they 492 // are not buffered), so we can fold away the common pattern of 493 // fence-atomic-fence. 494 setShouldFoldAtomicFences(true); 495 496 // Expand certain atomics 497 for (unsigned i = 0, e = 4; i != e; ++i) { 498 MVT VT = IntVTs[i]; 499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 502 } 503 504 if (!Subtarget->is64Bit()) { 505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 513 } 514 515 if (Subtarget->hasCmpxchg16b()) { 516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 517 } 518 519 // FIXME - use subtarget debug flags 520 if (!Subtarget->isTargetDarwin() && 521 !Subtarget->isTargetELF() && 522 !Subtarget->isTargetCygMing()) { 523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 524 } 525 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 530 if (Subtarget->is64Bit()) { 531 setExceptionPointerRegister(X86::RAX); 532 setExceptionSelectorRegister(X86::RDX); 533 } else { 534 setExceptionPointerRegister(X86::EAX); 535 setExceptionSelectorRegister(X86::EDX); 536 } 537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 539 540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 542 543 setOperationAction(ISD::TRAP, MVT::Other, Legal); 544 545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 546 setOperationAction(ISD::VASTART , MVT::Other, Custom); 547 setOperationAction(ISD::VAEND , MVT::Other, Expand); 548 if (Subtarget->is64Bit()) { 549 setOperationAction(ISD::VAARG , MVT::Other, Custom); 550 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 551 } else { 552 setOperationAction(ISD::VAARG , MVT::Other, Expand); 553 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 554 } 555 556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 558 559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Custom); 562 else if (TM.Options.EnableSegmentedStacks) 563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 564 MVT::i64 : MVT::i32, Custom); 565 else 566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 567 MVT::i64 : MVT::i32, Expand); 568 569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 570 // f32 and f64 use SSE. 571 // Set up the FP register classes. 572 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 573 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 574 575 // Use ANDPD to simulate FABS. 576 setOperationAction(ISD::FABS , MVT::f64, Custom); 577 setOperationAction(ISD::FABS , MVT::f32, Custom); 578 579 // Use XORP to simulate FNEG. 580 setOperationAction(ISD::FNEG , MVT::f64, Custom); 581 setOperationAction(ISD::FNEG , MVT::f32, Custom); 582 583 // Use ANDPD and ORPD to simulate FCOPYSIGN. 584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 586 587 // Lower this to FGETSIGNx86 plus an AND. 588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 590 591 // We don't support sin/cos/fmod 592 setOperationAction(ISD::FSIN , MVT::f64, Expand); 593 setOperationAction(ISD::FCOS , MVT::f64, Expand); 594 setOperationAction(ISD::FSIN , MVT::f32, Expand); 595 setOperationAction(ISD::FCOS , MVT::f32, Expand); 596 597 // Expand FP immediates into loads from the stack, except for the special 598 // cases we handle. 599 addLegalFPImmediate(APFloat(+0.0)); // xorpd 600 addLegalFPImmediate(APFloat(+0.0f)); // xorps 601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 602 // Use SSE for f32, x87 for f64. 603 // Set up the FP register classes. 604 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 605 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 606 607 // Use ANDPS to simulate FABS. 608 setOperationAction(ISD::FABS , MVT::f32, Custom); 609 610 // Use XORP to simulate FNEG. 611 setOperationAction(ISD::FNEG , MVT::f32, Custom); 612 613 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 614 615 // Use ANDPS and ORPS to simulate FCOPYSIGN. 616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 618 619 // We don't support sin/cos/fmod 620 setOperationAction(ISD::FSIN , MVT::f32, Expand); 621 setOperationAction(ISD::FCOS , MVT::f32, Expand); 622 623 // Special cases we handle for FP constants. 624 addLegalFPImmediate(APFloat(+0.0f)); // xorps 625 addLegalFPImmediate(APFloat(+0.0)); // FLD0 626 addLegalFPImmediate(APFloat(+1.0)); // FLD1 627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 629 630 if (!TM.Options.UnsafeFPMath) { 631 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 632 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 633 } 634 } else if (!TM.Options.UseSoftFloat) { 635 // f32 and f64 in x87. 636 // Set up the FP register classes. 637 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 638 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 639 640 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 641 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 644 645 if (!TM.Options.UnsafeFPMath) { 646 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 647 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 648 } 649 addLegalFPImmediate(APFloat(+0.0)); // FLD0 650 addLegalFPImmediate(APFloat(+1.0)); // FLD1 651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 657 } 658 659 // We don't support FMA. 660 setOperationAction(ISD::FMA, MVT::f64, Expand); 661 setOperationAction(ISD::FMA, MVT::f32, Expand); 662 663 // Long double always uses X87. 664 if (!TM.Options.UseSoftFloat) { 665 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 666 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 668 { 669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 670 addLegalFPImmediate(TmpFlt); // FLD0 671 TmpFlt.changeSign(); 672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 673 674 bool ignored; 675 APFloat TmpFlt2(+1.0); 676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 677 &ignored); 678 addLegalFPImmediate(TmpFlt2); // FLD1 679 TmpFlt2.changeSign(); 680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 681 } 682 683 if (!TM.Options.UnsafeFPMath) { 684 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 685 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 686 } 687 688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 689 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 691 setOperationAction(ISD::FRINT, MVT::f80, Expand); 692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 693 setOperationAction(ISD::FMA, MVT::f80, Expand); 694 } 695 696 // Always use a library call for pow. 697 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 698 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 699 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 700 701 setOperationAction(ISD::FLOG, MVT::f80, Expand); 702 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 703 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 704 setOperationAction(ISD::FEXP, MVT::f80, Expand); 705 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 706 707 // First set operation action for all vector types to either promote 708 // (for widening) or expand (for scalarization). Then we will selectively 709 // turn on ones that can be effectively codegen'd. 710 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 711 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 764 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 769 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 770 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 771 setTruncStoreAction((MVT::SimpleValueType)VT, 772 (MVT::SimpleValueType)InnerVT, Expand); 773 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 775 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 776 } 777 778 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 779 // with -msoft-float, disable use of MMX as well. 780 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 781 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 782 // No operations on x86mmx supported, everything uses intrinsics. 783 } 784 785 // MMX-sized vectors (other than x86mmx) are expected to be expanded 786 // into smaller operations. 787 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 788 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 789 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 790 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 791 setOperationAction(ISD::AND, MVT::v8i8, Expand); 792 setOperationAction(ISD::AND, MVT::v4i16, Expand); 793 setOperationAction(ISD::AND, MVT::v2i32, Expand); 794 setOperationAction(ISD::AND, MVT::v1i64, Expand); 795 setOperationAction(ISD::OR, MVT::v8i8, Expand); 796 setOperationAction(ISD::OR, MVT::v4i16, Expand); 797 setOperationAction(ISD::OR, MVT::v2i32, Expand); 798 setOperationAction(ISD::OR, MVT::v1i64, Expand); 799 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 800 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 801 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 802 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 808 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 809 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 810 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 811 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 814 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 815 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 816 817 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 818 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 819 820 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 821 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 822 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 823 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 824 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 825 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 826 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 827 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 830 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 831 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 832 } 833 834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 835 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 836 837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 838 // registers cannot be used even for integer operations. 839 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 841 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 842 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 843 844 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 845 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 846 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 847 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 848 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 849 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 850 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 851 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 852 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 853 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 854 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 860 861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 865 866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 871 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 877 878 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 880 EVT VT = (MVT::SimpleValueType)i; 881 // Do not attempt to custom lower non-power-of-2 vectors 882 if (!isPowerOf2_32(VT.getVectorNumElements())) 883 continue; 884 // Do not attempt to custom lower non-128-bit vectors 885 if (!VT.is128BitVector()) 886 continue; 887 setOperationAction(ISD::BUILD_VECTOR, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::VECTOR_SHUFFLE, 890 VT.getSimpleVT().SimpleTy, Custom); 891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 892 VT.getSimpleVT().SimpleTy, Custom); 893 } 894 895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 901 902 if (Subtarget->is64Bit()) { 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 905 } 906 907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 909 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 910 EVT VT = SVT; 911 912 // Do not attempt to promote non-128-bit vectors 913 if (!VT.is128BitVector()) 914 continue; 915 916 setOperationAction(ISD::AND, SVT, Promote); 917 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 918 setOperationAction(ISD::OR, SVT, Promote); 919 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 920 setOperationAction(ISD::XOR, SVT, Promote); 921 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 922 setOperationAction(ISD::LOAD, SVT, Promote); 923 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 924 setOperationAction(ISD::SELECT, SVT, Promote); 925 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 926 } 927 928 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 929 930 // Custom lower v2i64 and v2f64 selects. 931 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 932 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 933 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 934 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 935 936 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 937 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 938 } 939 940 if (Subtarget->hasSSE41()) { 941 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 942 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 944 setOperationAction(ISD::FRINT, MVT::f32, Legal); 945 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 946 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 947 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 948 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 949 setOperationAction(ISD::FRINT, MVT::f64, Legal); 950 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 951 952 // FIXME: Do we need to handle scalar-to-vector here? 953 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 954 955 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 958 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 959 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 960 961 // i8 and i16 vectors are custom , because the source register and source 962 // source memory operand types are not the same width. f32 vectors are 963 // custom since the immediate controlling the insert encodes additional 964 // information. 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 969 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 974 975 // FIXME: these should be Legal but thats only for the case where 976 // the index is constant. For now custom expand to deal with that. 977 if (Subtarget->is64Bit()) { 978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 980 } 981 } 982 983 if (Subtarget->hasSSE2()) { 984 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 986 987 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 988 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 989 990 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 991 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 992 993 if (Subtarget->hasAVX2()) { 994 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 995 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 996 997 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 998 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 999 1000 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1001 } else { 1002 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1003 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1004 1005 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1006 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1007 1008 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1009 } 1010 } 1011 1012 if (Subtarget->hasSSE42()) 1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1014 1015 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1016 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1020 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1021 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1022 1023 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1024 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1025 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1026 1027 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1031 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1033 1034 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1038 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1040 1041 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1042 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1043 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1044 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1051 1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1060 1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1065 1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1069 1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1074 1075 if (Subtarget->hasAVX2()) { 1076 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1077 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1078 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1079 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1080 1081 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1082 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1083 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1084 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1085 1086 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1087 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1088 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1089 // Don't lower v32i8 because there is no 128-bit byte mul 1090 1091 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1092 1093 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1094 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1095 1096 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1097 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1098 1099 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1100 } else { 1101 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1102 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1103 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1104 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1105 1106 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1107 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1108 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1109 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1110 1111 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1112 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1113 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1114 // Don't lower v32i8 because there is no 128-bit byte mul 1115 1116 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1117 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1118 1119 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1120 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1121 1122 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1123 } 1124 1125 // Custom lower several nodes for 256-bit types. 1126 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1127 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1128 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1129 EVT VT = SVT; 1130 1131 // Extract subvector is special because the value type 1132 // (result) is 128-bit but the source is 256-bit wide. 1133 if (VT.is128BitVector()) 1134 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1135 1136 // Do not attempt to custom lower other non-256-bit vectors 1137 if (!VT.is256BitVector()) 1138 continue; 1139 1140 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1141 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1142 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1144 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1145 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1146 } 1147 1148 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1149 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1150 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1151 EVT VT = SVT; 1152 1153 // Do not attempt to promote non-256-bit vectors 1154 if (!VT.is256BitVector()) 1155 continue; 1156 1157 setOperationAction(ISD::AND, SVT, Promote); 1158 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1159 setOperationAction(ISD::OR, SVT, Promote); 1160 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::XOR, SVT, Promote); 1162 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1163 setOperationAction(ISD::LOAD, SVT, Promote); 1164 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1165 setOperationAction(ISD::SELECT, SVT, Promote); 1166 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1167 } 1168 } 1169 1170 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1171 // of this type with custom code. 1172 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1173 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1174 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1175 Custom); 1176 } 1177 1178 // We want to custom lower some of our intrinsics. 1179 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1180 1181 1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1183 // handle type legalization for these operations here. 1184 // 1185 // FIXME: We really should do custom legalization for addition and 1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1187 // than generic legalization for 64-bit multiplication-with-overflow, though. 1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1189 // Add/Sub/Mul with overflow operations are custom lowered. 1190 MVT VT = IntVTs[i]; 1191 setOperationAction(ISD::SADDO, VT, Custom); 1192 setOperationAction(ISD::UADDO, VT, Custom); 1193 setOperationAction(ISD::SSUBO, VT, Custom); 1194 setOperationAction(ISD::USUBO, VT, Custom); 1195 setOperationAction(ISD::SMULO, VT, Custom); 1196 setOperationAction(ISD::UMULO, VT, Custom); 1197 } 1198 1199 // There are no 8-bit 3-address imul/mul instructions 1200 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1201 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1202 1203 if (!Subtarget->is64Bit()) { 1204 // These libcalls are not available in 32-bit. 1205 setLibcallName(RTLIB::SHL_I128, 0); 1206 setLibcallName(RTLIB::SRL_I128, 0); 1207 setLibcallName(RTLIB::SRA_I128, 0); 1208 } 1209 1210 // We have target-specific dag combine patterns for the following nodes: 1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1213 setTargetDAGCombine(ISD::VSELECT); 1214 setTargetDAGCombine(ISD::SELECT); 1215 setTargetDAGCombine(ISD::SHL); 1216 setTargetDAGCombine(ISD::SRA); 1217 setTargetDAGCombine(ISD::SRL); 1218 setTargetDAGCombine(ISD::OR); 1219 setTargetDAGCombine(ISD::AND); 1220 setTargetDAGCombine(ISD::ADD); 1221 setTargetDAGCombine(ISD::FADD); 1222 setTargetDAGCombine(ISD::FSUB); 1223 setTargetDAGCombine(ISD::SUB); 1224 setTargetDAGCombine(ISD::LOAD); 1225 setTargetDAGCombine(ISD::STORE); 1226 setTargetDAGCombine(ISD::ZERO_EXTEND); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->getStackAlignment() >= 32) { 1331 if (Subtarget->hasAVX2()) 1332 return MVT::v8i32; 1333 if (Subtarget->hasAVX()) 1334 return MVT::v8f32; 1335 } 1336 if (Subtarget->hasSSE2()) 1337 return MVT::v4i32; 1338 if (Subtarget->hasSSE1()) 1339 return MVT::v4f32; 1340 } else if (!MemcpyStrSrc && Size >= 8 && 1341 !Subtarget->is64Bit() && 1342 Subtarget->getStackAlignment() >= 8 && 1343 Subtarget->hasSSE2()) { 1344 // Do not use f64 to lower memcpy if source is string constant. It's 1345 // better to use i32 to avoid the loads. 1346 return MVT::f64; 1347 } 1348 } 1349 if (Subtarget->is64Bit() && Size >= 8) 1350 return MVT::i64; 1351 return MVT::i32; 1352} 1353 1354/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1355/// current function. The returned value is a member of the 1356/// MachineJumpTableInfo::JTEntryKind enum. 1357unsigned X86TargetLowering::getJumpTableEncoding() const { 1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1359 // symbol. 1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1361 Subtarget->isPICStyleGOT()) 1362 return MachineJumpTableInfo::EK_Custom32; 1363 1364 // Otherwise, use the normal jump table encoding heuristics. 1365 return TargetLowering::getJumpTableEncoding(); 1366} 1367 1368const MCExpr * 1369X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1370 const MachineBasicBlock *MBB, 1371 unsigned uid,MCContext &Ctx) const{ 1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1373 Subtarget->isPICStyleGOT()); 1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1375 // entries. 1376 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1377 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1378} 1379 1380/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1381/// jumptable. 1382SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1383 SelectionDAG &DAG) const { 1384 if (!Subtarget->is64Bit()) 1385 // This doesn't have DebugLoc associated with it, but is not really the 1386 // same as a Register. 1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1388 return Table; 1389} 1390 1391/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1392/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1393/// MCExpr. 1394const MCExpr *X86TargetLowering:: 1395getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1396 MCContext &Ctx) const { 1397 // X86-64 uses RIP relative addressing based on the jump table label. 1398 if (Subtarget->isPICStyleRIPRel()) 1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1400 1401 // Otherwise, the reference is relative to the PIC base. 1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1403} 1404 1405// FIXME: Why this routine is here? Move to RegInfo! 1406std::pair<const TargetRegisterClass*, uint8_t> 1407X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1408 const TargetRegisterClass *RRC = 0; 1409 uint8_t Cost = 1; 1410 switch (VT.getSimpleVT().SimpleTy) { 1411 default: 1412 return TargetLowering::findRepresentativeClass(VT); 1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1414 RRC = (Subtarget->is64Bit() 1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1416 break; 1417 case MVT::x86mmx: 1418 RRC = X86::VR64RegisterClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = X86::VR128RegisterClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDNode *Copy = *N->use_begin(); 1588 if (Copy->getOpcode() != ISD::CopyToReg && 1589 Copy->getOpcode() != ISD::FP_EXTEND) 1590 return false; 1591 1592 bool HasRet = false; 1593 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1594 UI != UE; ++UI) { 1595 if (UI->getOpcode() != X86ISD::RET_FLAG) 1596 return false; 1597 HasRet = true; 1598 } 1599 1600 return HasRet; 1601} 1602 1603EVT 1604X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1605 ISD::NodeType ExtendKind) const { 1606 MVT ReturnMVT; 1607 // TODO: Is this also valid on 32-bit? 1608 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1609 ReturnMVT = MVT::i8; 1610 else 1611 ReturnMVT = MVT::i32; 1612 1613 EVT MinVT = getRegisterType(Context, ReturnMVT); 1614 return VT.bitsLT(MinVT) ? MinVT : VT; 1615} 1616 1617/// LowerCallResult - Lower the result values of a call into the 1618/// appropriate copies out of appropriate physical registers. 1619/// 1620SDValue 1621X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1622 CallingConv::ID CallConv, bool isVarArg, 1623 const SmallVectorImpl<ISD::InputArg> &Ins, 1624 DebugLoc dl, SelectionDAG &DAG, 1625 SmallVectorImpl<SDValue> &InVals) const { 1626 1627 // Assign locations to each value returned by this call. 1628 SmallVector<CCValAssign, 16> RVLocs; 1629 bool Is64Bit = Subtarget->is64Bit(); 1630 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1631 getTargetMachine(), RVLocs, *DAG.getContext()); 1632 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1633 1634 // Copy all of the result registers out of their specified physreg. 1635 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1636 CCValAssign &VA = RVLocs[i]; 1637 EVT CopyVT = VA.getValVT(); 1638 1639 // If this is x86-64, and we disabled SSE, we can't return FP values 1640 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1641 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1642 report_fatal_error("SSE register return with SSE disabled"); 1643 } 1644 1645 SDValue Val; 1646 1647 // If this is a call to a function that returns an fp value on the floating 1648 // point stack, we must guarantee the the value is popped from the stack, so 1649 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1650 // if the return value is not used. We use the FpPOP_RETVAL instruction 1651 // instead. 1652 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1653 // If we prefer to use the value in xmm registers, copy it out as f80 and 1654 // use a truncate to move it from fp stack reg to xmm reg. 1655 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1656 SDValue Ops[] = { Chain, InFlag }; 1657 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1658 MVT::Other, MVT::Glue, Ops, 2), 1); 1659 Val = Chain.getValue(0); 1660 1661 // Round the f80 to the right size, which also moves it to the appropriate 1662 // xmm register. 1663 if (CopyVT != VA.getValVT()) 1664 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1665 // This truncation won't change the value. 1666 DAG.getIntPtrConstant(1)); 1667 } else { 1668 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1669 CopyVT, InFlag).getValue(1); 1670 Val = Chain.getValue(0); 1671 } 1672 InFlag = Chain.getValue(2); 1673 InVals.push_back(Val); 1674 } 1675 1676 return Chain; 1677} 1678 1679 1680//===----------------------------------------------------------------------===// 1681// C & StdCall & Fast Calling Convention implementation 1682//===----------------------------------------------------------------------===// 1683// StdCall calling convention seems to be standard for many Windows' API 1684// routines and around. It differs from C calling convention just a little: 1685// callee should clean up the stack, not caller. Symbols should be also 1686// decorated in some fancy way :) It doesn't support any vector arguments. 1687// For info on fast calling convention see Fast Calling Convention (tail call) 1688// implementation LowerX86_32FastCCCallTo. 1689 1690/// CallIsStructReturn - Determines whether a call uses struct return 1691/// semantics. 1692static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1693 if (Outs.empty()) 1694 return false; 1695 1696 return Outs[0].Flags.isSRet(); 1697} 1698 1699/// ArgsAreStructReturn - Determines whether a function uses struct 1700/// return semantics. 1701static bool 1702ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1703 if (Ins.empty()) 1704 return false; 1705 1706 return Ins[0].Flags.isSRet(); 1707} 1708 1709/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1710/// by "Src" to address "Dst" with size and alignment information specified by 1711/// the specific parameter attribute. The copy will be passed as a byval 1712/// function parameter. 1713static SDValue 1714CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1715 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1716 DebugLoc dl) { 1717 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1718 1719 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1720 /*isVolatile*/false, /*AlwaysInline=*/true, 1721 MachinePointerInfo(), MachinePointerInfo()); 1722} 1723 1724/// IsTailCallConvention - Return true if the calling convention is one that 1725/// supports tail call optimization. 1726static bool IsTailCallConvention(CallingConv::ID CC) { 1727 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1728} 1729 1730bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1731 if (!CI->isTailCall()) 1732 return false; 1733 1734 CallSite CS(CI); 1735 CallingConv::ID CalleeCC = CS.getCallingConv(); 1736 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1737 return false; 1738 1739 return true; 1740} 1741 1742/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1743/// a tailcall target by changing its ABI. 1744static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1745 bool GuaranteedTailCallOpt) { 1746 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1747} 1748 1749SDValue 1750X86TargetLowering::LowerMemArgument(SDValue Chain, 1751 CallingConv::ID CallConv, 1752 const SmallVectorImpl<ISD::InputArg> &Ins, 1753 DebugLoc dl, SelectionDAG &DAG, 1754 const CCValAssign &VA, 1755 MachineFrameInfo *MFI, 1756 unsigned i) const { 1757 // Create the nodes corresponding to a load from this parameter slot. 1758 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1759 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1760 getTargetMachine().Options.GuaranteedTailCallOpt); 1761 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1762 EVT ValVT; 1763 1764 // If value is passed by pointer we have address passed instead of the value 1765 // itself. 1766 if (VA.getLocInfo() == CCValAssign::Indirect) 1767 ValVT = VA.getLocVT(); 1768 else 1769 ValVT = VA.getValVT(); 1770 1771 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1772 // changed with more analysis. 1773 // In case of tail call optimization mark all arguments mutable. Since they 1774 // could be overwritten by lowering of arguments in case of a tail call. 1775 if (Flags.isByVal()) { 1776 unsigned Bytes = Flags.getByValSize(); 1777 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1778 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1779 return DAG.getFrameIndex(FI, getPointerTy()); 1780 } else { 1781 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1782 VA.getLocMemOffset(), isImmutable); 1783 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1784 return DAG.getLoad(ValVT, dl, Chain, FIN, 1785 MachinePointerInfo::getFixedStack(FI), 1786 false, false, false, 0); 1787 } 1788} 1789 1790SDValue 1791X86TargetLowering::LowerFormalArguments(SDValue Chain, 1792 CallingConv::ID CallConv, 1793 bool isVarArg, 1794 const SmallVectorImpl<ISD::InputArg> &Ins, 1795 DebugLoc dl, 1796 SelectionDAG &DAG, 1797 SmallVectorImpl<SDValue> &InVals) 1798 const { 1799 MachineFunction &MF = DAG.getMachineFunction(); 1800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1801 1802 const Function* Fn = MF.getFunction(); 1803 if (Fn->hasExternalLinkage() && 1804 Subtarget->isTargetCygMing() && 1805 Fn->getName() == "main") 1806 FuncInfo->setForceFramePointer(true); 1807 1808 MachineFrameInfo *MFI = MF.getFrameInfo(); 1809 bool Is64Bit = Subtarget->is64Bit(); 1810 bool IsWin64 = Subtarget->isTargetWin64(); 1811 1812 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1813 "Var args not supported with calling convention fastcc or ghc"); 1814 1815 // Assign locations to all of the incoming arguments. 1816 SmallVector<CCValAssign, 16> ArgLocs; 1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1818 ArgLocs, *DAG.getContext()); 1819 1820 // Allocate shadow area for Win64 1821 if (IsWin64) { 1822 CCInfo.AllocateStack(32, 8); 1823 } 1824 1825 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1826 1827 unsigned LastVal = ~0U; 1828 SDValue ArgValue; 1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1830 CCValAssign &VA = ArgLocs[i]; 1831 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1832 // places. 1833 assert(VA.getValNo() != LastVal && 1834 "Don't support value assigned to multiple locs yet"); 1835 (void)LastVal; 1836 LastVal = VA.getValNo(); 1837 1838 if (VA.isRegLoc()) { 1839 EVT RegVT = VA.getLocVT(); 1840 TargetRegisterClass *RC = NULL; 1841 if (RegVT == MVT::i32) 1842 RC = X86::GR32RegisterClass; 1843 else if (Is64Bit && RegVT == MVT::i64) 1844 RC = X86::GR64RegisterClass; 1845 else if (RegVT == MVT::f32) 1846 RC = X86::FR32RegisterClass; 1847 else if (RegVT == MVT::f64) 1848 RC = X86::FR64RegisterClass; 1849 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1850 RC = X86::VR256RegisterClass; 1851 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1852 RC = X86::VR128RegisterClass; 1853 else if (RegVT == MVT::x86mmx) 1854 RC = X86::VR64RegisterClass; 1855 else 1856 llvm_unreachable("Unknown argument type!"); 1857 1858 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1859 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1860 1861 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1862 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1863 // right size. 1864 if (VA.getLocInfo() == CCValAssign::SExt) 1865 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1866 DAG.getValueType(VA.getValVT())); 1867 else if (VA.getLocInfo() == CCValAssign::ZExt) 1868 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1869 DAG.getValueType(VA.getValVT())); 1870 else if (VA.getLocInfo() == CCValAssign::BCvt) 1871 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1872 1873 if (VA.isExtInLoc()) { 1874 // Handle MMX values passed in XMM regs. 1875 if (RegVT.isVector()) { 1876 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1877 ArgValue); 1878 } else 1879 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1880 } 1881 } else { 1882 assert(VA.isMemLoc()); 1883 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1884 } 1885 1886 // If value is passed via pointer - do a load. 1887 if (VA.getLocInfo() == CCValAssign::Indirect) 1888 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1889 MachinePointerInfo(), false, false, false, 0); 1890 1891 InVals.push_back(ArgValue); 1892 } 1893 1894 // The x86-64 ABI for returning structs by value requires that we copy 1895 // the sret argument into %rax for the return. Save the argument into 1896 // a virtual register so that we can access it from the return points. 1897 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1898 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1899 unsigned Reg = FuncInfo->getSRetReturnReg(); 1900 if (!Reg) { 1901 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1902 FuncInfo->setSRetReturnReg(Reg); 1903 } 1904 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1906 } 1907 1908 unsigned StackSize = CCInfo.getNextStackOffset(); 1909 // Align stack specially for tail calls. 1910 if (FuncIsMadeTailCallSafe(CallConv, 1911 MF.getTarget().Options.GuaranteedTailCallOpt)) 1912 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1913 1914 // If the function takes variable number of arguments, make a frame index for 1915 // the start of the first vararg value... for expansion of llvm.va_start. 1916 if (isVarArg) { 1917 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1918 CallConv != CallingConv::X86_ThisCall)) { 1919 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1920 } 1921 if (Is64Bit) { 1922 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1923 1924 // FIXME: We should really autogenerate these arrays 1925 static const unsigned GPR64ArgRegsWin64[] = { 1926 X86::RCX, X86::RDX, X86::R8, X86::R9 1927 }; 1928 static const unsigned GPR64ArgRegs64Bit[] = { 1929 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1930 }; 1931 static const unsigned XMMArgRegs64Bit[] = { 1932 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1933 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1934 }; 1935 const unsigned *GPR64ArgRegs; 1936 unsigned NumXMMRegs = 0; 1937 1938 if (IsWin64) { 1939 // The XMM registers which might contain var arg parameters are shadowed 1940 // in their paired GPR. So we only need to save the GPR to their home 1941 // slots. 1942 TotalNumIntRegs = 4; 1943 GPR64ArgRegs = GPR64ArgRegsWin64; 1944 } else { 1945 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1946 GPR64ArgRegs = GPR64ArgRegs64Bit; 1947 1948 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1949 TotalNumXMMRegs); 1950 } 1951 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1952 TotalNumIntRegs); 1953 1954 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1955 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1956 "SSE register cannot be used when SSE is disabled!"); 1957 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1958 NoImplicitFloatOps) && 1959 "SSE register cannot be used when SSE is disabled!"); 1960 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1961 !Subtarget->hasSSE1()) 1962 // Kernel mode asks for SSE to be disabled, so don't push them 1963 // on the stack. 1964 TotalNumXMMRegs = 0; 1965 1966 if (IsWin64) { 1967 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1968 // Get to the caller-allocated home save location. Add 8 to account 1969 // for the return address. 1970 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1971 FuncInfo->setRegSaveFrameIndex( 1972 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1973 // Fixup to set vararg frame on shadow area (4 x i64). 1974 if (NumIntRegs < 4) 1975 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1976 } else { 1977 // For X86-64, if there are vararg parameters that are passed via 1978 // registers, then we must store them to their spots on the stack so 1979 // they may be loaded by deferencing the result of va_next. 1980 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1981 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1984 false)); 1985 } 1986 1987 // Store the integer parameter registers. 1988 SmallVector<SDValue, 8> MemOps; 1989 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1990 getPointerTy()); 1991 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1992 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1993 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1994 DAG.getIntPtrConstant(Offset)); 1995 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1996 X86::GR64RegisterClass); 1997 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1998 SDValue Store = 1999 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2000 MachinePointerInfo::getFixedStack( 2001 FuncInfo->getRegSaveFrameIndex(), Offset), 2002 false, false, 0); 2003 MemOps.push_back(Store); 2004 Offset += 8; 2005 } 2006 2007 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2008 // Now store the XMM (fp + vector) parameter registers. 2009 SmallVector<SDValue, 11> SaveXMMOps; 2010 SaveXMMOps.push_back(Chain); 2011 2012 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2013 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2014 SaveXMMOps.push_back(ALVal); 2015 2016 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2017 FuncInfo->getRegSaveFrameIndex())); 2018 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2019 FuncInfo->getVarArgsFPOffset())); 2020 2021 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2022 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2023 X86::VR128RegisterClass); 2024 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2025 SaveXMMOps.push_back(Val); 2026 } 2027 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2028 MVT::Other, 2029 &SaveXMMOps[0], SaveXMMOps.size())); 2030 } 2031 2032 if (!MemOps.empty()) 2033 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2034 &MemOps[0], MemOps.size()); 2035 } 2036 } 2037 2038 // Some CCs need callee pop. 2039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2040 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2041 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2042 } else { 2043 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2044 // If this is an sret function, the return should pop the hidden pointer. 2045 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 2046 FuncInfo->setBytesToPopOnReturn(4); 2047 } 2048 2049 if (!Is64Bit) { 2050 // RegSaveFrameIndex is X86-64 only. 2051 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2052 if (CallConv == CallingConv::X86_FastCall || 2053 CallConv == CallingConv::X86_ThisCall) 2054 // fastcc functions can't have varargs. 2055 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2056 } 2057 2058 FuncInfo->setArgumentStackSize(StackSize); 2059 2060 return Chain; 2061} 2062 2063SDValue 2064X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2065 SDValue StackPtr, SDValue Arg, 2066 DebugLoc dl, SelectionDAG &DAG, 2067 const CCValAssign &VA, 2068 ISD::ArgFlagsTy Flags) const { 2069 unsigned LocMemOffset = VA.getLocMemOffset(); 2070 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2071 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2072 if (Flags.isByVal()) 2073 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2074 2075 return DAG.getStore(Chain, dl, Arg, PtrOff, 2076 MachinePointerInfo::getStack(LocMemOffset), 2077 false, false, 0); 2078} 2079 2080/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2081/// optimization is performed and it is required. 2082SDValue 2083X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2084 SDValue &OutRetAddr, SDValue Chain, 2085 bool IsTailCall, bool Is64Bit, 2086 int FPDiff, DebugLoc dl) const { 2087 // Adjust the Return address stack slot. 2088 EVT VT = getPointerTy(); 2089 OutRetAddr = getReturnAddressFrameIndex(DAG); 2090 2091 // Load the "old" Return address. 2092 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2093 false, false, false, 0); 2094 return SDValue(OutRetAddr.getNode(), 1); 2095} 2096 2097/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2098/// optimization is performed and it is required (FPDiff!=0). 2099static SDValue 2100EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2101 SDValue Chain, SDValue RetAddrFrIdx, 2102 bool Is64Bit, int FPDiff, DebugLoc dl) { 2103 // Store the return address to the appropriate stack slot. 2104 if (!FPDiff) return Chain; 2105 // Calculate the new stack slot for the return address. 2106 int SlotSize = Is64Bit ? 8 : 4; 2107 int NewReturnAddrFI = 2108 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2109 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2110 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2111 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2112 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2113 false, false, 0); 2114 return Chain; 2115} 2116 2117SDValue 2118X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2119 CallingConv::ID CallConv, bool isVarArg, 2120 bool &isTailCall, 2121 const SmallVectorImpl<ISD::OutputArg> &Outs, 2122 const SmallVectorImpl<SDValue> &OutVals, 2123 const SmallVectorImpl<ISD::InputArg> &Ins, 2124 DebugLoc dl, SelectionDAG &DAG, 2125 SmallVectorImpl<SDValue> &InVals) const { 2126 MachineFunction &MF = DAG.getMachineFunction(); 2127 bool Is64Bit = Subtarget->is64Bit(); 2128 bool IsWin64 = Subtarget->isTargetWin64(); 2129 bool IsStructRet = CallIsStructReturn(Outs); 2130 bool IsSibcall = false; 2131 2132 if (isTailCall) { 2133 // Check if it's really possible to do a tail call. 2134 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2135 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2136 Outs, OutVals, Ins, DAG); 2137 2138 // Sibcalls are automatically detected tailcalls which do not require 2139 // ABI changes. 2140 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2141 IsSibcall = true; 2142 2143 if (isTailCall) 2144 ++NumTailCalls; 2145 } 2146 2147 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2148 "Var args not supported with calling convention fastcc or ghc"); 2149 2150 // Analyze operands of the call, assigning locations to each operand. 2151 SmallVector<CCValAssign, 16> ArgLocs; 2152 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2153 ArgLocs, *DAG.getContext()); 2154 2155 // Allocate shadow area for Win64 2156 if (IsWin64) { 2157 CCInfo.AllocateStack(32, 8); 2158 } 2159 2160 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2161 2162 // Get a count of how many bytes are to be pushed on the stack. 2163 unsigned NumBytes = CCInfo.getNextStackOffset(); 2164 if (IsSibcall) 2165 // This is a sibcall. The memory operands are available in caller's 2166 // own caller's stack. 2167 NumBytes = 0; 2168 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2169 IsTailCallConvention(CallConv)) 2170 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2171 2172 int FPDiff = 0; 2173 if (isTailCall && !IsSibcall) { 2174 // Lower arguments at fp - stackoffset + fpdiff. 2175 unsigned NumBytesCallerPushed = 2176 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2177 FPDiff = NumBytesCallerPushed - NumBytes; 2178 2179 // Set the delta of movement of the returnaddr stackslot. 2180 // But only set if delta is greater than previous delta. 2181 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2182 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2183 } 2184 2185 if (!IsSibcall) 2186 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2187 2188 SDValue RetAddrFrIdx; 2189 // Load return address for tail calls. 2190 if (isTailCall && FPDiff) 2191 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2192 Is64Bit, FPDiff, dl); 2193 2194 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2195 SmallVector<SDValue, 8> MemOpChains; 2196 SDValue StackPtr; 2197 2198 // Walk the register/memloc assignments, inserting copies/loads. In the case 2199 // of tail call optimization arguments are handle later. 2200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2201 CCValAssign &VA = ArgLocs[i]; 2202 EVT RegVT = VA.getLocVT(); 2203 SDValue Arg = OutVals[i]; 2204 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2205 bool isByVal = Flags.isByVal(); 2206 2207 // Promote the value if needed. 2208 switch (VA.getLocInfo()) { 2209 default: llvm_unreachable("Unknown loc info!"); 2210 case CCValAssign::Full: break; 2211 case CCValAssign::SExt: 2212 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2213 break; 2214 case CCValAssign::ZExt: 2215 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2216 break; 2217 case CCValAssign::AExt: 2218 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2219 // Special case: passing MMX values in XMM registers. 2220 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2221 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2222 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2223 } else 2224 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2225 break; 2226 case CCValAssign::BCvt: 2227 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2228 break; 2229 case CCValAssign::Indirect: { 2230 // Store the argument. 2231 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2232 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2233 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2234 MachinePointerInfo::getFixedStack(FI), 2235 false, false, 0); 2236 Arg = SpillSlot; 2237 break; 2238 } 2239 } 2240 2241 if (VA.isRegLoc()) { 2242 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2243 if (isVarArg && IsWin64) { 2244 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2245 // shadow reg if callee is a varargs function. 2246 unsigned ShadowReg = 0; 2247 switch (VA.getLocReg()) { 2248 case X86::XMM0: ShadowReg = X86::RCX; break; 2249 case X86::XMM1: ShadowReg = X86::RDX; break; 2250 case X86::XMM2: ShadowReg = X86::R8; break; 2251 case X86::XMM3: ShadowReg = X86::R9; break; 2252 } 2253 if (ShadowReg) 2254 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2255 } 2256 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2257 assert(VA.isMemLoc()); 2258 if (StackPtr.getNode() == 0) 2259 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2260 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2261 dl, DAG, VA, Flags)); 2262 } 2263 } 2264 2265 if (!MemOpChains.empty()) 2266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2267 &MemOpChains[0], MemOpChains.size()); 2268 2269 // Build a sequence of copy-to-reg nodes chained together with token chain 2270 // and flag operands which copy the outgoing args into registers. 2271 SDValue InFlag; 2272 // Tail call byval lowering might overwrite argument registers so in case of 2273 // tail call optimization the copies to registers are lowered later. 2274 if (!isTailCall) 2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2276 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2277 RegsToPass[i].second, InFlag); 2278 InFlag = Chain.getValue(1); 2279 } 2280 2281 if (Subtarget->isPICStyleGOT()) { 2282 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2283 // GOT pointer. 2284 if (!isTailCall) { 2285 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2286 DAG.getNode(X86ISD::GlobalBaseReg, 2287 DebugLoc(), getPointerTy()), 2288 InFlag); 2289 InFlag = Chain.getValue(1); 2290 } else { 2291 // If we are tail calling and generating PIC/GOT style code load the 2292 // address of the callee into ECX. The value in ecx is used as target of 2293 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2294 // for tail calls on PIC/GOT architectures. Normally we would just put the 2295 // address of GOT into ebx and then call target@PLT. But for tail calls 2296 // ebx would be restored (since ebx is callee saved) before jumping to the 2297 // target@PLT. 2298 2299 // Note: The actual moving to ECX is done further down. 2300 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2301 if (G && !G->getGlobal()->hasHiddenVisibility() && 2302 !G->getGlobal()->hasProtectedVisibility()) 2303 Callee = LowerGlobalAddress(Callee, DAG); 2304 else if (isa<ExternalSymbolSDNode>(Callee)) 2305 Callee = LowerExternalSymbol(Callee, DAG); 2306 } 2307 } 2308 2309 if (Is64Bit && isVarArg && !IsWin64) { 2310 // From AMD64 ABI document: 2311 // For calls that may call functions that use varargs or stdargs 2312 // (prototype-less calls or calls to functions containing ellipsis (...) in 2313 // the declaration) %al is used as hidden argument to specify the number 2314 // of SSE registers used. The contents of %al do not need to match exactly 2315 // the number of registers, but must be an ubound on the number of SSE 2316 // registers used and is in the range 0 - 8 inclusive. 2317 2318 // Count the number of XMM registers allocated. 2319 static const unsigned XMMArgRegs[] = { 2320 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2321 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2322 }; 2323 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2324 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2325 && "SSE registers cannot be used when SSE is disabled"); 2326 2327 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2328 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2329 InFlag = Chain.getValue(1); 2330 } 2331 2332 2333 // For tail calls lower the arguments to the 'real' stack slot. 2334 if (isTailCall) { 2335 // Force all the incoming stack arguments to be loaded from the stack 2336 // before any new outgoing arguments are stored to the stack, because the 2337 // outgoing stack slots may alias the incoming argument stack slots, and 2338 // the alias isn't otherwise explicit. This is slightly more conservative 2339 // than necessary, because it means that each store effectively depends 2340 // on every argument instead of just those arguments it would clobber. 2341 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2342 2343 SmallVector<SDValue, 8> MemOpChains2; 2344 SDValue FIN; 2345 int FI = 0; 2346 // Do not flag preceding copytoreg stuff together with the following stuff. 2347 InFlag = SDValue(); 2348 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2349 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2350 CCValAssign &VA = ArgLocs[i]; 2351 if (VA.isRegLoc()) 2352 continue; 2353 assert(VA.isMemLoc()); 2354 SDValue Arg = OutVals[i]; 2355 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2356 // Create frame index. 2357 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2358 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2359 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2360 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2361 2362 if (Flags.isByVal()) { 2363 // Copy relative to framepointer. 2364 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2365 if (StackPtr.getNode() == 0) 2366 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2367 getPointerTy()); 2368 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2369 2370 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2371 ArgChain, 2372 Flags, DAG, dl)); 2373 } else { 2374 // Store relative to framepointer. 2375 MemOpChains2.push_back( 2376 DAG.getStore(ArgChain, dl, Arg, FIN, 2377 MachinePointerInfo::getFixedStack(FI), 2378 false, false, 0)); 2379 } 2380 } 2381 } 2382 2383 if (!MemOpChains2.empty()) 2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2385 &MemOpChains2[0], MemOpChains2.size()); 2386 2387 // Copy arguments to their registers. 2388 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2389 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2390 RegsToPass[i].second, InFlag); 2391 InFlag = Chain.getValue(1); 2392 } 2393 InFlag =SDValue(); 2394 2395 // Store the return address to the appropriate stack slot. 2396 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2397 FPDiff, dl); 2398 } 2399 2400 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2401 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2402 // In the 64-bit large code model, we have to make all calls 2403 // through a register, since the call instruction's 32-bit 2404 // pc-relative offset may not be large enough to hold the whole 2405 // address. 2406 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2407 // If the callee is a GlobalAddress node (quite common, every direct call 2408 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2409 // it. 2410 2411 // We should use extra load for direct calls to dllimported functions in 2412 // non-JIT mode. 2413 const GlobalValue *GV = G->getGlobal(); 2414 if (!GV->hasDLLImportLinkage()) { 2415 unsigned char OpFlags = 0; 2416 bool ExtraLoad = false; 2417 unsigned WrapperKind = ISD::DELETED_NODE; 2418 2419 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2420 // external symbols most go through the PLT in PIC mode. If the symbol 2421 // has hidden or protected visibility, or if it is static or local, then 2422 // we don't need to use the PLT - we can directly call it. 2423 if (Subtarget->isTargetELF() && 2424 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2425 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2426 OpFlags = X86II::MO_PLT; 2427 } else if (Subtarget->isPICStyleStubAny() && 2428 (GV->isDeclaration() || GV->isWeakForLinker()) && 2429 (!Subtarget->getTargetTriple().isMacOSX() || 2430 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2431 // PC-relative references to external symbols should go through $stub, 2432 // unless we're building with the leopard linker or later, which 2433 // automatically synthesizes these stubs. 2434 OpFlags = X86II::MO_DARWIN_STUB; 2435 } else if (Subtarget->isPICStyleRIPRel() && 2436 isa<Function>(GV) && 2437 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2438 // If the function is marked as non-lazy, generate an indirect call 2439 // which loads from the GOT directly. This avoids runtime overhead 2440 // at the cost of eager binding (and one extra byte of encoding). 2441 OpFlags = X86II::MO_GOTPCREL; 2442 WrapperKind = X86ISD::WrapperRIP; 2443 ExtraLoad = true; 2444 } 2445 2446 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2447 G->getOffset(), OpFlags); 2448 2449 // Add a wrapper if needed. 2450 if (WrapperKind != ISD::DELETED_NODE) 2451 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2452 // Add extra indirection if needed. 2453 if (ExtraLoad) 2454 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2455 MachinePointerInfo::getGOT(), 2456 false, false, false, 0); 2457 } 2458 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2459 unsigned char OpFlags = 0; 2460 2461 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2462 // external symbols should go through the PLT. 2463 if (Subtarget->isTargetELF() && 2464 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2465 OpFlags = X86II::MO_PLT; 2466 } else if (Subtarget->isPICStyleStubAny() && 2467 (!Subtarget->getTargetTriple().isMacOSX() || 2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2469 // PC-relative references to external symbols should go through $stub, 2470 // unless we're building with the leopard linker or later, which 2471 // automatically synthesizes these stubs. 2472 OpFlags = X86II::MO_DARWIN_STUB; 2473 } 2474 2475 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2476 OpFlags); 2477 } 2478 2479 // Returns a chain & a flag for retval copy to use. 2480 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2481 SmallVector<SDValue, 8> Ops; 2482 2483 if (!IsSibcall && isTailCall) { 2484 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2485 DAG.getIntPtrConstant(0, true), InFlag); 2486 InFlag = Chain.getValue(1); 2487 } 2488 2489 Ops.push_back(Chain); 2490 Ops.push_back(Callee); 2491 2492 if (isTailCall) 2493 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2494 2495 // Add argument registers to the end of the list so that they are known live 2496 // into the call. 2497 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2498 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2499 RegsToPass[i].second.getValueType())); 2500 2501 // Add an implicit use GOT pointer in EBX. 2502 if (!isTailCall && Subtarget->isPICStyleGOT()) 2503 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2504 2505 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2506 if (Is64Bit && isVarArg && !IsWin64) 2507 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2508 2509 if (InFlag.getNode()) 2510 Ops.push_back(InFlag); 2511 2512 if (isTailCall) { 2513 // We used to do: 2514 //// If this is the first return lowered for this function, add the regs 2515 //// to the liveout set for the function. 2516 // This isn't right, although it's probably harmless on x86; liveouts 2517 // should be computed from returns not tail calls. Consider a void 2518 // function making a tail call to a function returning int. 2519 return DAG.getNode(X86ISD::TC_RETURN, dl, 2520 NodeTys, &Ops[0], Ops.size()); 2521 } 2522 2523 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2524 InFlag = Chain.getValue(1); 2525 2526 // Create the CALLSEQ_END node. 2527 unsigned NumBytesForCalleeToPush; 2528 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2529 getTargetMachine().Options.GuaranteedTailCallOpt)) 2530 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2531 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2532 // If this is a call to a struct-return function, the callee 2533 // pops the hidden struct pointer, so we have to push it back. 2534 // This is common for Darwin/X86, Linux & Mingw32 targets. 2535 NumBytesForCalleeToPush = 4; 2536 else 2537 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2538 2539 // Returns a flag for retval copy to use. 2540 if (!IsSibcall) { 2541 Chain = DAG.getCALLSEQ_END(Chain, 2542 DAG.getIntPtrConstant(NumBytes, true), 2543 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2544 true), 2545 InFlag); 2546 InFlag = Chain.getValue(1); 2547 } 2548 2549 // Handle result values, copying them out of physregs into vregs that we 2550 // return. 2551 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2552 Ins, dl, DAG, InVals); 2553} 2554 2555 2556//===----------------------------------------------------------------------===// 2557// Fast Calling Convention (tail call) implementation 2558//===----------------------------------------------------------------------===// 2559 2560// Like std call, callee cleans arguments, convention except that ECX is 2561// reserved for storing the tail called function address. Only 2 registers are 2562// free for argument passing (inreg). Tail call optimization is performed 2563// provided: 2564// * tailcallopt is enabled 2565// * caller/callee are fastcc 2566// On X86_64 architecture with GOT-style position independent code only local 2567// (within module) calls are supported at the moment. 2568// To keep the stack aligned according to platform abi the function 2569// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2570// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2571// If a tail called function callee has more arguments than the caller the 2572// caller needs to make sure that there is room to move the RETADDR to. This is 2573// achieved by reserving an area the size of the argument delta right after the 2574// original REtADDR, but before the saved framepointer or the spilled registers 2575// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2576// stack layout: 2577// arg1 2578// arg2 2579// RETADDR 2580// [ new RETADDR 2581// move area ] 2582// (possible EBP) 2583// ESI 2584// EDI 2585// local1 .. 2586 2587/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2588/// for a 16 byte align requirement. 2589unsigned 2590X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2591 SelectionDAG& DAG) const { 2592 MachineFunction &MF = DAG.getMachineFunction(); 2593 const TargetMachine &TM = MF.getTarget(); 2594 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2595 unsigned StackAlignment = TFI.getStackAlignment(); 2596 uint64_t AlignMask = StackAlignment - 1; 2597 int64_t Offset = StackSize; 2598 uint64_t SlotSize = TD->getPointerSize(); 2599 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2600 // Number smaller than 12 so just add the difference. 2601 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2602 } else { 2603 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2604 Offset = ((~AlignMask) & Offset) + StackAlignment + 2605 (StackAlignment-SlotSize); 2606 } 2607 return Offset; 2608} 2609 2610/// MatchingStackOffset - Return true if the given stack call argument is 2611/// already available in the same position (relatively) of the caller's 2612/// incoming argument stack. 2613static 2614bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2615 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2616 const X86InstrInfo *TII) { 2617 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2618 int FI = INT_MAX; 2619 if (Arg.getOpcode() == ISD::CopyFromReg) { 2620 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2621 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2622 return false; 2623 MachineInstr *Def = MRI->getVRegDef(VR); 2624 if (!Def) 2625 return false; 2626 if (!Flags.isByVal()) { 2627 if (!TII->isLoadFromStackSlot(Def, FI)) 2628 return false; 2629 } else { 2630 unsigned Opcode = Def->getOpcode(); 2631 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2632 Def->getOperand(1).isFI()) { 2633 FI = Def->getOperand(1).getIndex(); 2634 Bytes = Flags.getByValSize(); 2635 } else 2636 return false; 2637 } 2638 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2639 if (Flags.isByVal()) 2640 // ByVal argument is passed in as a pointer but it's now being 2641 // dereferenced. e.g. 2642 // define @foo(%struct.X* %A) { 2643 // tail call @bar(%struct.X* byval %A) 2644 // } 2645 return false; 2646 SDValue Ptr = Ld->getBasePtr(); 2647 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2648 if (!FINode) 2649 return false; 2650 FI = FINode->getIndex(); 2651 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2652 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2653 FI = FINode->getIndex(); 2654 Bytes = Flags.getByValSize(); 2655 } else 2656 return false; 2657 2658 assert(FI != INT_MAX); 2659 if (!MFI->isFixedObjectIndex(FI)) 2660 return false; 2661 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2662} 2663 2664/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2665/// for tail call optimization. Targets which want to do tail call 2666/// optimization should implement this function. 2667bool 2668X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2669 CallingConv::ID CalleeCC, 2670 bool isVarArg, 2671 bool isCalleeStructRet, 2672 bool isCallerStructRet, 2673 const SmallVectorImpl<ISD::OutputArg> &Outs, 2674 const SmallVectorImpl<SDValue> &OutVals, 2675 const SmallVectorImpl<ISD::InputArg> &Ins, 2676 SelectionDAG& DAG) const { 2677 if (!IsTailCallConvention(CalleeCC) && 2678 CalleeCC != CallingConv::C) 2679 return false; 2680 2681 // If -tailcallopt is specified, make fastcc functions tail-callable. 2682 const MachineFunction &MF = DAG.getMachineFunction(); 2683 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2684 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2685 bool CCMatch = CallerCC == CalleeCC; 2686 2687 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2688 if (IsTailCallConvention(CalleeCC) && CCMatch) 2689 return true; 2690 return false; 2691 } 2692 2693 // Look for obvious safe cases to perform tail call optimization that do not 2694 // require ABI changes. This is what gcc calls sibcall. 2695 2696 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2697 // emit a special epilogue. 2698 if (RegInfo->needsStackRealignment(MF)) 2699 return false; 2700 2701 // Also avoid sibcall optimization if either caller or callee uses struct 2702 // return semantics. 2703 if (isCalleeStructRet || isCallerStructRet) 2704 return false; 2705 2706 // An stdcall caller is expected to clean up its arguments; the callee 2707 // isn't going to do that. 2708 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2709 return false; 2710 2711 // Do not sibcall optimize vararg calls unless all arguments are passed via 2712 // registers. 2713 if (isVarArg && !Outs.empty()) { 2714 2715 // Optimizing for varargs on Win64 is unlikely to be safe without 2716 // additional testing. 2717 if (Subtarget->isTargetWin64()) 2718 return false; 2719 2720 SmallVector<CCValAssign, 16> ArgLocs; 2721 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2722 getTargetMachine(), ArgLocs, *DAG.getContext()); 2723 2724 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2725 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2726 if (!ArgLocs[i].isRegLoc()) 2727 return false; 2728 } 2729 2730 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2731 // stack. Therefore, if it's not used by the call it is not safe to optimize 2732 // this into a sibcall. 2733 bool Unused = false; 2734 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2735 if (!Ins[i].Used) { 2736 Unused = true; 2737 break; 2738 } 2739 } 2740 if (Unused) { 2741 SmallVector<CCValAssign, 16> RVLocs; 2742 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2743 getTargetMachine(), RVLocs, *DAG.getContext()); 2744 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2745 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2746 CCValAssign &VA = RVLocs[i]; 2747 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2748 return false; 2749 } 2750 } 2751 2752 // If the calling conventions do not match, then we'd better make sure the 2753 // results are returned in the same way as what the caller expects. 2754 if (!CCMatch) { 2755 SmallVector<CCValAssign, 16> RVLocs1; 2756 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2757 getTargetMachine(), RVLocs1, *DAG.getContext()); 2758 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2759 2760 SmallVector<CCValAssign, 16> RVLocs2; 2761 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2762 getTargetMachine(), RVLocs2, *DAG.getContext()); 2763 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2764 2765 if (RVLocs1.size() != RVLocs2.size()) 2766 return false; 2767 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2768 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2769 return false; 2770 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2771 return false; 2772 if (RVLocs1[i].isRegLoc()) { 2773 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2774 return false; 2775 } else { 2776 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2777 return false; 2778 } 2779 } 2780 } 2781 2782 // If the callee takes no arguments then go on to check the results of the 2783 // call. 2784 if (!Outs.empty()) { 2785 // Check if stack adjustment is needed. For now, do not do this if any 2786 // argument is passed on the stack. 2787 SmallVector<CCValAssign, 16> ArgLocs; 2788 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2789 getTargetMachine(), ArgLocs, *DAG.getContext()); 2790 2791 // Allocate shadow area for Win64 2792 if (Subtarget->isTargetWin64()) { 2793 CCInfo.AllocateStack(32, 8); 2794 } 2795 2796 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2797 if (CCInfo.getNextStackOffset()) { 2798 MachineFunction &MF = DAG.getMachineFunction(); 2799 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2800 return false; 2801 2802 // Check if the arguments are already laid out in the right way as 2803 // the caller's fixed stack objects. 2804 MachineFrameInfo *MFI = MF.getFrameInfo(); 2805 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2806 const X86InstrInfo *TII = 2807 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2808 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2809 CCValAssign &VA = ArgLocs[i]; 2810 SDValue Arg = OutVals[i]; 2811 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2812 if (VA.getLocInfo() == CCValAssign::Indirect) 2813 return false; 2814 if (!VA.isRegLoc()) { 2815 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2816 MFI, MRI, TII)) 2817 return false; 2818 } 2819 } 2820 } 2821 2822 // If the tailcall address may be in a register, then make sure it's 2823 // possible to register allocate for it. In 32-bit, the call address can 2824 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2825 // callee-saved registers are restored. These happen to be the same 2826 // registers used to pass 'inreg' arguments so watch out for those. 2827 if (!Subtarget->is64Bit() && 2828 !isa<GlobalAddressSDNode>(Callee) && 2829 !isa<ExternalSymbolSDNode>(Callee)) { 2830 unsigned NumInRegs = 0; 2831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2832 CCValAssign &VA = ArgLocs[i]; 2833 if (!VA.isRegLoc()) 2834 continue; 2835 unsigned Reg = VA.getLocReg(); 2836 switch (Reg) { 2837 default: break; 2838 case X86::EAX: case X86::EDX: case X86::ECX: 2839 if (++NumInRegs == 3) 2840 return false; 2841 break; 2842 } 2843 } 2844 } 2845 } 2846 2847 return true; 2848} 2849 2850FastISel * 2851X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2852 return X86::createFastISel(funcInfo); 2853} 2854 2855 2856//===----------------------------------------------------------------------===// 2857// Other Lowering Hooks 2858//===----------------------------------------------------------------------===// 2859 2860static bool MayFoldLoad(SDValue Op) { 2861 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2862} 2863 2864static bool MayFoldIntoStore(SDValue Op) { 2865 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2866} 2867 2868static bool isTargetShuffle(unsigned Opcode) { 2869 switch(Opcode) { 2870 default: return false; 2871 case X86ISD::PSHUFD: 2872 case X86ISD::PSHUFHW: 2873 case X86ISD::PSHUFLW: 2874 case X86ISD::SHUFP: 2875 case X86ISD::PALIGN: 2876 case X86ISD::MOVLHPS: 2877 case X86ISD::MOVLHPD: 2878 case X86ISD::MOVHLPS: 2879 case X86ISD::MOVLPS: 2880 case X86ISD::MOVLPD: 2881 case X86ISD::MOVSHDUP: 2882 case X86ISD::MOVSLDUP: 2883 case X86ISD::MOVDDUP: 2884 case X86ISD::MOVSS: 2885 case X86ISD::MOVSD: 2886 case X86ISD::UNPCKL: 2887 case X86ISD::UNPCKH: 2888 case X86ISD::VPERMILP: 2889 case X86ISD::VPERM2X128: 2890 return true; 2891 } 2892 return false; 2893} 2894 2895static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2896 SDValue V1, SelectionDAG &DAG) { 2897 switch(Opc) { 2898 default: llvm_unreachable("Unknown x86 shuffle node"); 2899 case X86ISD::MOVSHDUP: 2900 case X86ISD::MOVSLDUP: 2901 case X86ISD::MOVDDUP: 2902 return DAG.getNode(Opc, dl, VT, V1); 2903 } 2904 2905 return SDValue(); 2906} 2907 2908static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2909 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2910 switch(Opc) { 2911 default: llvm_unreachable("Unknown x86 shuffle node"); 2912 case X86ISD::PSHUFD: 2913 case X86ISD::PSHUFHW: 2914 case X86ISD::PSHUFLW: 2915 case X86ISD::VPERMILP: 2916 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2917 } 2918 2919 return SDValue(); 2920} 2921 2922static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2923 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2924 switch(Opc) { 2925 default: llvm_unreachable("Unknown x86 shuffle node"); 2926 case X86ISD::PALIGN: 2927 case X86ISD::SHUFP: 2928 case X86ISD::VPERM2X128: 2929 return DAG.getNode(Opc, dl, VT, V1, V2, 2930 DAG.getConstant(TargetMask, MVT::i8)); 2931 } 2932 return SDValue(); 2933} 2934 2935static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2936 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2937 switch(Opc) { 2938 default: llvm_unreachable("Unknown x86 shuffle node"); 2939 case X86ISD::MOVLHPS: 2940 case X86ISD::MOVLHPD: 2941 case X86ISD::MOVHLPS: 2942 case X86ISD::MOVLPS: 2943 case X86ISD::MOVLPD: 2944 case X86ISD::MOVSS: 2945 case X86ISD::MOVSD: 2946 case X86ISD::UNPCKL: 2947 case X86ISD::UNPCKH: 2948 return DAG.getNode(Opc, dl, VT, V1, V2); 2949 } 2950 return SDValue(); 2951} 2952 2953SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2954 MachineFunction &MF = DAG.getMachineFunction(); 2955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2956 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2957 2958 if (ReturnAddrIndex == 0) { 2959 // Set up a frame object for the return address. 2960 uint64_t SlotSize = TD->getPointerSize(); 2961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2962 false); 2963 FuncInfo->setRAIndex(ReturnAddrIndex); 2964 } 2965 2966 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2967} 2968 2969 2970bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2971 bool hasSymbolicDisplacement) { 2972 // Offset should fit into 32 bit immediate field. 2973 if (!isInt<32>(Offset)) 2974 return false; 2975 2976 // If we don't have a symbolic displacement - we don't have any extra 2977 // restrictions. 2978 if (!hasSymbolicDisplacement) 2979 return true; 2980 2981 // FIXME: Some tweaks might be needed for medium code model. 2982 if (M != CodeModel::Small && M != CodeModel::Kernel) 2983 return false; 2984 2985 // For small code model we assume that latest object is 16MB before end of 31 2986 // bits boundary. We may also accept pretty large negative constants knowing 2987 // that all objects are in the positive half of address space. 2988 if (M == CodeModel::Small && Offset < 16*1024*1024) 2989 return true; 2990 2991 // For kernel code model we know that all object resist in the negative half 2992 // of 32bits address space. We may not accept negative offsets, since they may 2993 // be just off and we may accept pretty large positive ones. 2994 if (M == CodeModel::Kernel && Offset > 0) 2995 return true; 2996 2997 return false; 2998} 2999 3000/// isCalleePop - Determines whether the callee is required to pop its 3001/// own arguments. Callee pop is necessary to support tail calls. 3002bool X86::isCalleePop(CallingConv::ID CallingConv, 3003 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3004 if (IsVarArg) 3005 return false; 3006 3007 switch (CallingConv) { 3008 default: 3009 return false; 3010 case CallingConv::X86_StdCall: 3011 return !is64Bit; 3012 case CallingConv::X86_FastCall: 3013 return !is64Bit; 3014 case CallingConv::X86_ThisCall: 3015 return !is64Bit; 3016 case CallingConv::Fast: 3017 return TailCallOpt; 3018 case CallingConv::GHC: 3019 return TailCallOpt; 3020 } 3021} 3022 3023/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3024/// specific condition code, returning the condition code and the LHS/RHS of the 3025/// comparison to make. 3026static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3027 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3028 if (!isFP) { 3029 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3030 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3031 // X > -1 -> X == 0, jump !sign. 3032 RHS = DAG.getConstant(0, RHS.getValueType()); 3033 return X86::COND_NS; 3034 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3035 // X < 0 -> X == 0, jump on sign. 3036 return X86::COND_S; 3037 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3038 // X < 1 -> X <= 0 3039 RHS = DAG.getConstant(0, RHS.getValueType()); 3040 return X86::COND_LE; 3041 } 3042 } 3043 3044 switch (SetCCOpcode) { 3045 default: llvm_unreachable("Invalid integer condition!"); 3046 case ISD::SETEQ: return X86::COND_E; 3047 case ISD::SETGT: return X86::COND_G; 3048 case ISD::SETGE: return X86::COND_GE; 3049 case ISD::SETLT: return X86::COND_L; 3050 case ISD::SETLE: return X86::COND_LE; 3051 case ISD::SETNE: return X86::COND_NE; 3052 case ISD::SETULT: return X86::COND_B; 3053 case ISD::SETUGT: return X86::COND_A; 3054 case ISD::SETULE: return X86::COND_BE; 3055 case ISD::SETUGE: return X86::COND_AE; 3056 } 3057 } 3058 3059 // First determine if it is required or is profitable to flip the operands. 3060 3061 // If LHS is a foldable load, but RHS is not, flip the condition. 3062 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3063 !ISD::isNON_EXTLoad(RHS.getNode())) { 3064 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3065 std::swap(LHS, RHS); 3066 } 3067 3068 switch (SetCCOpcode) { 3069 default: break; 3070 case ISD::SETOLT: 3071 case ISD::SETOLE: 3072 case ISD::SETUGT: 3073 case ISD::SETUGE: 3074 std::swap(LHS, RHS); 3075 break; 3076 } 3077 3078 // On a floating point condition, the flags are set as follows: 3079 // ZF PF CF op 3080 // 0 | 0 | 0 | X > Y 3081 // 0 | 0 | 1 | X < Y 3082 // 1 | 0 | 0 | X == Y 3083 // 1 | 1 | 1 | unordered 3084 switch (SetCCOpcode) { 3085 default: llvm_unreachable("Condcode should be pre-legalized away"); 3086 case ISD::SETUEQ: 3087 case ISD::SETEQ: return X86::COND_E; 3088 case ISD::SETOLT: // flipped 3089 case ISD::SETOGT: 3090 case ISD::SETGT: return X86::COND_A; 3091 case ISD::SETOLE: // flipped 3092 case ISD::SETOGE: 3093 case ISD::SETGE: return X86::COND_AE; 3094 case ISD::SETUGT: // flipped 3095 case ISD::SETULT: 3096 case ISD::SETLT: return X86::COND_B; 3097 case ISD::SETUGE: // flipped 3098 case ISD::SETULE: 3099 case ISD::SETLE: return X86::COND_BE; 3100 case ISD::SETONE: 3101 case ISD::SETNE: return X86::COND_NE; 3102 case ISD::SETUO: return X86::COND_P; 3103 case ISD::SETO: return X86::COND_NP; 3104 case ISD::SETOEQ: 3105 case ISD::SETUNE: return X86::COND_INVALID; 3106 } 3107} 3108 3109/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3110/// code. Current x86 isa includes the following FP cmov instructions: 3111/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3112static bool hasFPCMov(unsigned X86CC) { 3113 switch (X86CC) { 3114 default: 3115 return false; 3116 case X86::COND_B: 3117 case X86::COND_BE: 3118 case X86::COND_E: 3119 case X86::COND_P: 3120 case X86::COND_A: 3121 case X86::COND_AE: 3122 case X86::COND_NE: 3123 case X86::COND_NP: 3124 return true; 3125 } 3126} 3127 3128/// isFPImmLegal - Returns true if the target can instruction select the 3129/// specified FP immediate natively. If false, the legalizer will 3130/// materialize the FP immediate as a load from a constant pool. 3131bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3132 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3133 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3134 return true; 3135 } 3136 return false; 3137} 3138 3139/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3140/// the specified range (L, H]. 3141static bool isUndefOrInRange(int Val, int Low, int Hi) { 3142 return (Val < 0) || (Val >= Low && Val < Hi); 3143} 3144 3145/// isUndefOrInRange - Return true if every element in Mask, begining 3146/// from position Pos and ending in Pos+Size, falls within the specified 3147/// range (L, L+Pos]. or is undef. 3148static bool isUndefOrInRange(ArrayRef<int> Mask, 3149 int Pos, int Size, int Low, int Hi) { 3150 for (int i = Pos, e = Pos+Size; i != e; ++i) 3151 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3152 return false; 3153 return true; 3154} 3155 3156/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3157/// specified value. 3158static bool isUndefOrEqual(int Val, int CmpVal) { 3159 if (Val < 0 || Val == CmpVal) 3160 return true; 3161 return false; 3162} 3163 3164/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3165/// from position Pos and ending in Pos+Size, falls within the specified 3166/// sequential range (L, L+Pos]. or is undef. 3167static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3168 int Pos, int Size, int Low) { 3169 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3170 if (!isUndefOrEqual(Mask[i], Low)) 3171 return false; 3172 return true; 3173} 3174 3175/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3176/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3177/// the second operand. 3178static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3179 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3180 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3181 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3182 return (Mask[0] < 2 && Mask[1] < 2); 3183 return false; 3184} 3185 3186bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3187 return ::isPSHUFDMask(N->getMask(), N->getValueType(0)); 3188} 3189 3190/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3191/// is suitable for input to PSHUFHW. 3192static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3193 if (VT != MVT::v8i16) 3194 return false; 3195 3196 // Lower quadword copied in order or undef. 3197 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3198 return false; 3199 3200 // Upper quadword shuffled. 3201 for (unsigned i = 4; i != 8; ++i) 3202 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3203 return false; 3204 3205 return true; 3206} 3207 3208bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3209 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0)); 3210} 3211 3212/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3213/// is suitable for input to PSHUFLW. 3214static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3215 if (VT != MVT::v8i16) 3216 return false; 3217 3218 // Upper quadword copied in order. 3219 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3220 return false; 3221 3222 // Lower quadword shuffled. 3223 for (unsigned i = 0; i != 4; ++i) 3224 if (Mask[i] >= 4) 3225 return false; 3226 3227 return true; 3228} 3229 3230bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3231 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0)); 3232} 3233 3234/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3235/// is suitable for input to PALIGNR. 3236static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, bool hasSSSE3) { 3237 int i, e = VT.getVectorNumElements(); 3238 if (VT.getSizeInBits() != 128) 3239 return false; 3240 3241 // Do not handle v2i64 / v2f64 shuffles with palignr. 3242 if (e < 4 || !hasSSSE3) 3243 return false; 3244 3245 for (i = 0; i != e; ++i) 3246 if (Mask[i] >= 0) 3247 break; 3248 3249 // All undef, not a palignr. 3250 if (i == e) 3251 return false; 3252 3253 // Make sure we're shifting in the right direction. 3254 if (Mask[i] <= i) 3255 return false; 3256 3257 int s = Mask[i] - i; 3258 3259 // Check the rest of the elements to see if they are consecutive. 3260 for (++i; i != e; ++i) { 3261 int m = Mask[i]; 3262 if (m >= 0 && m != s+i) 3263 return false; 3264 } 3265 return true; 3266} 3267 3268/// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand 3269/// specifies a shuffle of elements that is suitable for input to 256-bit 3270/// VSHUFPSY. 3271static bool isVSHUFPYMask(ArrayRef<int> Mask, EVT VT, 3272 bool HasAVX, bool Commuted = false) { 3273 int NumElems = VT.getVectorNumElements(); 3274 3275 if (!HasAVX || VT.getSizeInBits() != 256) 3276 return false; 3277 3278 if (NumElems != 4 && NumElems != 8) 3279 return false; 3280 3281 // VSHUFPSY divides the resulting vector into 4 chunks. 3282 // The sources are also splitted into 4 chunks, and each destination 3283 // chunk must come from a different source chunk. 3284 // 3285 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3286 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3287 // 3288 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3289 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3290 // 3291 // VSHUFPDY divides the resulting vector into 4 chunks. 3292 // The sources are also splitted into 4 chunks, and each destination 3293 // chunk must come from a different source chunk. 3294 // 3295 // SRC1 => X3 X2 X1 X0 3296 // SRC2 => Y3 Y2 Y1 Y0 3297 // 3298 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3299 // 3300 unsigned QuarterSize = NumElems/4; 3301 unsigned HalfSize = QuarterSize*2; 3302 for (unsigned l = 0; l != 2; ++l) { 3303 unsigned LaneStart = l*HalfSize; 3304 for (unsigned s = 0; s != 2; ++s) { 3305 unsigned QuarterStart = s*QuarterSize; 3306 unsigned Src = (Commuted) ? (1-s) : s; 3307 unsigned SrcStart = Src*NumElems + LaneStart; 3308 for (unsigned i = 0; i != QuarterSize; ++i) { 3309 int Idx = Mask[i+QuarterStart+LaneStart]; 3310 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize)) 3311 return false; 3312 // For VSHUFPSY, the mask of the second half must be the same as the 3313 // first but with the appropriate offsets. This works in the same way as 3314 // VPERMILPS works with masks. 3315 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0) 3316 continue; 3317 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart)) 3318 return false; 3319 } 3320 } 3321 } 3322 3323 return true; 3324} 3325 3326/// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle 3327/// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions. 3328static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) { 3329 EVT VT = SVOp->getValueType(0); 3330 unsigned NumElems = VT.getVectorNumElements(); 3331 3332 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types"); 3333 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types"); 3334 3335 unsigned HalfSize = NumElems/2; 3336 unsigned Mul = (NumElems == 8) ? 2 : 1; 3337 unsigned Mask = 0; 3338 for (unsigned i = 0; i != NumElems; ++i) { 3339 int Elt = SVOp->getMaskElt(i); 3340 if (Elt < 0) 3341 continue; 3342 Elt %= HalfSize; 3343 unsigned Shamt = i; 3344 // For VSHUFPSY, the mask of the first half must be equal to the second one. 3345 if (NumElems == 8) Shamt %= HalfSize; 3346 Mask |= Elt << (Shamt*Mul); 3347 } 3348 3349 return Mask; 3350} 3351 3352/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3353/// the two vector operands have swapped position. 3354static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3355 unsigned NumElems) { 3356 for (unsigned i = 0; i != NumElems; ++i) { 3357 int idx = Mask[i]; 3358 if (idx < 0) 3359 continue; 3360 else if (idx < (int)NumElems) 3361 Mask[i] = idx + NumElems; 3362 else 3363 Mask[i] = idx - NumElems; 3364 } 3365} 3366 3367/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3368/// specifies a shuffle of elements that is suitable for input to 128-bit 3369/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3370/// reverse of what x86 shuffles want. 3371static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool Commuted = false) { 3372 unsigned NumElems = VT.getVectorNumElements(); 3373 3374 if (VT.getSizeInBits() != 128) 3375 return false; 3376 3377 if (NumElems != 2 && NumElems != 4) 3378 return false; 3379 3380 unsigned Half = NumElems / 2; 3381 unsigned SrcStart = Commuted ? NumElems : 0; 3382 for (unsigned i = 0; i != Half; ++i) 3383 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3384 return false; 3385 SrcStart = Commuted ? 0 : NumElems; 3386 for (unsigned i = Half; i != NumElems; ++i) 3387 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3388 return false; 3389 3390 return true; 3391} 3392 3393bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3394 return ::isSHUFPMask(N->getMask(), N->getValueType(0)); 3395} 3396 3397/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3398/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3399bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3400 EVT VT = N->getValueType(0); 3401 unsigned NumElems = VT.getVectorNumElements(); 3402 3403 if (VT.getSizeInBits() != 128) 3404 return false; 3405 3406 if (NumElems != 4) 3407 return false; 3408 3409 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3410 return isUndefOrEqual(N->getMaskElt(0), 6) && 3411 isUndefOrEqual(N->getMaskElt(1), 7) && 3412 isUndefOrEqual(N->getMaskElt(2), 2) && 3413 isUndefOrEqual(N->getMaskElt(3), 3); 3414} 3415 3416/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3417/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3418/// <2, 3, 2, 3> 3419bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3420 EVT VT = N->getValueType(0); 3421 unsigned NumElems = VT.getVectorNumElements(); 3422 3423 if (VT.getSizeInBits() != 128) 3424 return false; 3425 3426 if (NumElems != 4) 3427 return false; 3428 3429 return isUndefOrEqual(N->getMaskElt(0), 2) && 3430 isUndefOrEqual(N->getMaskElt(1), 3) && 3431 isUndefOrEqual(N->getMaskElt(2), 2) && 3432 isUndefOrEqual(N->getMaskElt(3), 3); 3433} 3434 3435/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3436/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3437bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3438 EVT VT = N->getValueType(0); 3439 3440 if (VT.getSizeInBits() != 128) 3441 return false; 3442 3443 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3444 3445 if (NumElems != 2 && NumElems != 4) 3446 return false; 3447 3448 for (unsigned i = 0; i < NumElems/2; ++i) 3449 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3450 return false; 3451 3452 for (unsigned i = NumElems/2; i < NumElems; ++i) 3453 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3454 return false; 3455 3456 return true; 3457} 3458 3459/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3460/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3461bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3462 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3463 3464 if ((NumElems != 2 && NumElems != 4) 3465 || N->getValueType(0).getSizeInBits() > 128) 3466 return false; 3467 3468 for (unsigned i = 0; i < NumElems/2; ++i) 3469 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3470 return false; 3471 3472 for (unsigned i = 0; i < NumElems/2; ++i) 3473 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3474 return false; 3475 3476 return true; 3477} 3478 3479/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3480/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3481static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3482 bool HasAVX2, bool V2IsSplat = false) { 3483 unsigned NumElts = VT.getVectorNumElements(); 3484 3485 assert((VT.is128BitVector() || VT.is256BitVector()) && 3486 "Unsupported vector type for unpckh"); 3487 3488 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3489 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3490 return false; 3491 3492 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3493 // independently on 128-bit lanes. 3494 unsigned NumLanes = VT.getSizeInBits()/128; 3495 unsigned NumLaneElts = NumElts/NumLanes; 3496 3497 for (unsigned l = 0; l != NumLanes; ++l) { 3498 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3499 i != (l+1)*NumLaneElts; 3500 i += 2, ++j) { 3501 int BitI = Mask[i]; 3502 int BitI1 = Mask[i+1]; 3503 if (!isUndefOrEqual(BitI, j)) 3504 return false; 3505 if (V2IsSplat) { 3506 if (!isUndefOrEqual(BitI1, NumElts)) 3507 return false; 3508 } else { 3509 if (!isUndefOrEqual(BitI1, j + NumElts)) 3510 return false; 3511 } 3512 } 3513 } 3514 3515 return true; 3516} 3517 3518bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3519 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3520} 3521 3522/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3523/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3524static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3525 bool HasAVX2, bool V2IsSplat = false) { 3526 unsigned NumElts = VT.getVectorNumElements(); 3527 3528 assert((VT.is128BitVector() || VT.is256BitVector()) && 3529 "Unsupported vector type for unpckh"); 3530 3531 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3532 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3533 return false; 3534 3535 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3536 // independently on 128-bit lanes. 3537 unsigned NumLanes = VT.getSizeInBits()/128; 3538 unsigned NumLaneElts = NumElts/NumLanes; 3539 3540 for (unsigned l = 0; l != NumLanes; ++l) { 3541 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3542 i != (l+1)*NumLaneElts; i += 2, ++j) { 3543 int BitI = Mask[i]; 3544 int BitI1 = Mask[i+1]; 3545 if (!isUndefOrEqual(BitI, j)) 3546 return false; 3547 if (V2IsSplat) { 3548 if (isUndefOrEqual(BitI1, NumElts)) 3549 return false; 3550 } else { 3551 if (!isUndefOrEqual(BitI1, j+NumElts)) 3552 return false; 3553 } 3554 } 3555 } 3556 return true; 3557} 3558 3559bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3560 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3561} 3562 3563/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3564/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3565/// <0, 0, 1, 1> 3566static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3567 bool HasAVX2) { 3568 unsigned NumElts = VT.getVectorNumElements(); 3569 3570 assert((VT.is128BitVector() || VT.is256BitVector()) && 3571 "Unsupported vector type for unpckh"); 3572 3573 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3574 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3575 return false; 3576 3577 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3578 // FIXME: Need a better way to get rid of this, there's no latency difference 3579 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3580 // the former later. We should also remove the "_undef" special mask. 3581 if (NumElts == 4 && VT.getSizeInBits() == 256) 3582 return false; 3583 3584 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3585 // independently on 128-bit lanes. 3586 unsigned NumLanes = VT.getSizeInBits()/128; 3587 unsigned NumLaneElts = NumElts/NumLanes; 3588 3589 for (unsigned l = 0; l != NumLanes; ++l) { 3590 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3591 i != (l+1)*NumLaneElts; 3592 i += 2, ++j) { 3593 int BitI = Mask[i]; 3594 int BitI1 = Mask[i+1]; 3595 3596 if (!isUndefOrEqual(BitI, j)) 3597 return false; 3598 if (!isUndefOrEqual(BitI1, j)) 3599 return false; 3600 } 3601 } 3602 3603 return true; 3604} 3605 3606bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3607 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3608} 3609 3610/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3611/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3612/// <2, 2, 3, 3> 3613static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3614 unsigned NumElts = VT.getVectorNumElements(); 3615 3616 assert((VT.is128BitVector() || VT.is256BitVector()) && 3617 "Unsupported vector type for unpckh"); 3618 3619 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3620 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3621 return false; 3622 3623 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3624 // independently on 128-bit lanes. 3625 unsigned NumLanes = VT.getSizeInBits()/128; 3626 unsigned NumLaneElts = NumElts/NumLanes; 3627 3628 for (unsigned l = 0; l != NumLanes; ++l) { 3629 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3630 i != (l+1)*NumLaneElts; i += 2, ++j) { 3631 int BitI = Mask[i]; 3632 int BitI1 = Mask[i+1]; 3633 if (!isUndefOrEqual(BitI, j)) 3634 return false; 3635 if (!isUndefOrEqual(BitI1, j)) 3636 return false; 3637 } 3638 } 3639 return true; 3640} 3641 3642bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3643 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3644} 3645 3646/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3647/// specifies a shuffle of elements that is suitable for input to MOVSS, 3648/// MOVSD, and MOVD, i.e. setting the lowest element. 3649static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3650 if (VT.getVectorElementType().getSizeInBits() < 32) 3651 return false; 3652 if (VT.getSizeInBits() == 256) 3653 return false; 3654 3655 unsigned NumElts = VT.getVectorNumElements(); 3656 3657 if (!isUndefOrEqual(Mask[0], NumElts)) 3658 return false; 3659 3660 for (unsigned i = 1; i != NumElts; ++i) 3661 if (!isUndefOrEqual(Mask[i], i)) 3662 return false; 3663 3664 return true; 3665} 3666 3667bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3668 return ::isMOVLMask(N->getMask(), N->getValueType(0)); 3669} 3670 3671/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3672/// as permutations between 128-bit chunks or halves. As an example: this 3673/// shuffle bellow: 3674/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3675/// The first half comes from the second half of V1 and the second half from the 3676/// the second half of V2. 3677static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3678 if (!HasAVX || VT.getSizeInBits() != 256) 3679 return false; 3680 3681 // The shuffle result is divided into half A and half B. In total the two 3682 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3683 // B must come from C, D, E or F. 3684 unsigned HalfSize = VT.getVectorNumElements()/2; 3685 bool MatchA = false, MatchB = false; 3686 3687 // Check if A comes from one of C, D, E, F. 3688 for (unsigned Half = 0; Half != 4; ++Half) { 3689 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3690 MatchA = true; 3691 break; 3692 } 3693 } 3694 3695 // Check if B comes from one of C, D, E, F. 3696 for (unsigned Half = 0; Half != 4; ++Half) { 3697 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3698 MatchB = true; 3699 break; 3700 } 3701 } 3702 3703 return MatchA && MatchB; 3704} 3705 3706/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3707/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3708static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3709 EVT VT = SVOp->getValueType(0); 3710 3711 unsigned HalfSize = VT.getVectorNumElements()/2; 3712 3713 unsigned FstHalf = 0, SndHalf = 0; 3714 for (unsigned i = 0; i < HalfSize; ++i) { 3715 if (SVOp->getMaskElt(i) > 0) { 3716 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3717 break; 3718 } 3719 } 3720 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3721 if (SVOp->getMaskElt(i) > 0) { 3722 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3723 break; 3724 } 3725 } 3726 3727 return (FstHalf | (SndHalf << 4)); 3728} 3729 3730/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3731/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3732/// Note that VPERMIL mask matching is different depending whether theunderlying 3733/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3734/// to the same elements of the low, but to the higher half of the source. 3735/// In VPERMILPD the two lanes could be shuffled independently of each other 3736/// with the same restriction that lanes can't be crossed. 3737static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3738 if (!HasAVX) 3739 return false; 3740 3741 unsigned NumElts = VT.getVectorNumElements(); 3742 // Only match 256-bit with 32/64-bit types 3743 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3744 return false; 3745 3746 unsigned NumLanes = VT.getSizeInBits()/128; 3747 unsigned LaneSize = NumElts/NumLanes; 3748 for (unsigned l = 0; l != NumLanes; ++l) { 3749 unsigned LaneStart = l*LaneSize; 3750 for (unsigned i = 0; i != LaneSize; ++i) { 3751 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize)) 3752 return false; 3753 if (NumElts == 4 || l == 0) 3754 continue; 3755 // VPERMILPS handling 3756 if (Mask[i] < 0) 3757 continue; 3758 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart)) 3759 return false; 3760 } 3761 } 3762 3763 return true; 3764} 3765 3766/// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle 3767/// the specified VECTOR_MASK mask with VPERMILPS/D* instructions. 3768static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) { 3769 EVT VT = SVOp->getValueType(0); 3770 3771 unsigned NumElts = VT.getVectorNumElements(); 3772 unsigned NumLanes = VT.getSizeInBits()/128; 3773 unsigned LaneSize = NumElts/NumLanes; 3774 3775 // Although the mask is equal for both lanes do it twice to get the cases 3776 // where a mask will match because the same mask element is undef on the 3777 // first half but valid on the second. This would get pathological cases 3778 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3779 unsigned Shift = (LaneSize == 4) ? 2 : 1; 3780 unsigned Mask = 0; 3781 for (unsigned i = 0; i != NumElts; ++i) { 3782 int MaskElt = SVOp->getMaskElt(i); 3783 if (MaskElt < 0) 3784 continue; 3785 MaskElt %= LaneSize; 3786 unsigned Shamt = i; 3787 // VPERMILPSY, the mask of the first half must be equal to the second one 3788 if (NumElts == 8) Shamt %= LaneSize; 3789 Mask |= MaskElt << (Shamt*Shift); 3790 } 3791 3792 return Mask; 3793} 3794 3795/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3796/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3797/// element of vector 2 and the other elements to come from vector 1 in order. 3798static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3799 bool V2IsSplat = false, bool V2IsUndef = false) { 3800 unsigned NumOps = VT.getVectorNumElements(); 3801 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3802 return false; 3803 3804 if (!isUndefOrEqual(Mask[0], 0)) 3805 return false; 3806 3807 for (unsigned i = 1; i != NumOps; ++i) 3808 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3809 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3810 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3811 return false; 3812 3813 return true; 3814} 3815 3816static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3817 bool V2IsUndef = false) { 3818 return isCommutedMOVLMask(N->getMask(), N->getValueType(0), 3819 V2IsSplat, V2IsUndef); 3820} 3821 3822/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3823/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3824/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3825bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3826 const X86Subtarget *Subtarget) { 3827 if (!Subtarget->hasSSE3()) 3828 return false; 3829 3830 // The second vector must be undef 3831 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3832 return false; 3833 3834 EVT VT = N->getValueType(0); 3835 unsigned NumElems = VT.getVectorNumElements(); 3836 3837 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3838 (VT.getSizeInBits() == 256 && NumElems != 8)) 3839 return false; 3840 3841 // "i+1" is the value the indexed mask element must have 3842 for (unsigned i = 0; i < NumElems; i += 2) 3843 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3844 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3845 return false; 3846 3847 return true; 3848} 3849 3850/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3851/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3852/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3853bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3854 const X86Subtarget *Subtarget) { 3855 if (!Subtarget->hasSSE3()) 3856 return false; 3857 3858 // The second vector must be undef 3859 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3860 return false; 3861 3862 EVT VT = N->getValueType(0); 3863 unsigned NumElems = VT.getVectorNumElements(); 3864 3865 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3866 (VT.getSizeInBits() == 256 && NumElems != 8)) 3867 return false; 3868 3869 // "i" is the value the indexed mask element must have 3870 for (unsigned i = 0; i != NumElems; i += 2) 3871 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3872 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3873 return false; 3874 3875 return true; 3876} 3877 3878/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3879/// specifies a shuffle of elements that is suitable for input to 256-bit 3880/// version of MOVDDUP. 3881static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3882 unsigned NumElts = VT.getVectorNumElements(); 3883 3884 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3885 return false; 3886 3887 for (unsigned i = 0; i != NumElts/2; ++i) 3888 if (!isUndefOrEqual(Mask[i], 0)) 3889 return false; 3890 for (unsigned i = NumElts/2; i != NumElts; ++i) 3891 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3892 return false; 3893 return true; 3894} 3895 3896/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3897/// specifies a shuffle of elements that is suitable for input to 128-bit 3898/// version of MOVDDUP. 3899bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3900 EVT VT = N->getValueType(0); 3901 3902 if (VT.getSizeInBits() != 128) 3903 return false; 3904 3905 unsigned e = VT.getVectorNumElements() / 2; 3906 for (unsigned i = 0; i != e; ++i) 3907 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3908 return false; 3909 for (unsigned i = 0; i != e; ++i) 3910 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3911 return false; 3912 return true; 3913} 3914 3915/// isVEXTRACTF128Index - Return true if the specified 3916/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3917/// suitable for input to VEXTRACTF128. 3918bool X86::isVEXTRACTF128Index(SDNode *N) { 3919 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3920 return false; 3921 3922 // The index should be aligned on a 128-bit boundary. 3923 uint64_t Index = 3924 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3925 3926 unsigned VL = N->getValueType(0).getVectorNumElements(); 3927 unsigned VBits = N->getValueType(0).getSizeInBits(); 3928 unsigned ElSize = VBits / VL; 3929 bool Result = (Index * ElSize) % 128 == 0; 3930 3931 return Result; 3932} 3933 3934/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3935/// operand specifies a subvector insert that is suitable for input to 3936/// VINSERTF128. 3937bool X86::isVINSERTF128Index(SDNode *N) { 3938 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3939 return false; 3940 3941 // The index should be aligned on a 128-bit boundary. 3942 uint64_t Index = 3943 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3944 3945 unsigned VL = N->getValueType(0).getVectorNumElements(); 3946 unsigned VBits = N->getValueType(0).getSizeInBits(); 3947 unsigned ElSize = VBits / VL; 3948 bool Result = (Index * ElSize) % 128 == 0; 3949 3950 return Result; 3951} 3952 3953/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3954/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3955unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3956 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3957 unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3958 3959 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3960 unsigned Mask = 0; 3961 for (unsigned i = 0; i != NumOperands; ++i) { 3962 int Val = SVOp->getMaskElt(NumOperands-i-1); 3963 if (Val < 0) Val = 0; 3964 if (Val >= (int)NumOperands) Val -= NumOperands; 3965 Mask |= Val; 3966 if (i != NumOperands - 1) 3967 Mask <<= Shift; 3968 } 3969 return Mask; 3970} 3971 3972/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3973/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3974unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3975 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3976 unsigned Mask = 0; 3977 // 8 nodes, but we only care about the last 4. 3978 for (unsigned i = 7; i >= 4; --i) { 3979 int Val = SVOp->getMaskElt(i); 3980 if (Val >= 0) 3981 Mask |= (Val - 4); 3982 if (i != 4) 3983 Mask <<= 2; 3984 } 3985 return Mask; 3986} 3987 3988/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3989/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3990unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3991 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3992 unsigned Mask = 0; 3993 // 8 nodes, but we only care about the first 4. 3994 for (int i = 3; i >= 0; --i) { 3995 int Val = SVOp->getMaskElt(i); 3996 if (Val >= 0) 3997 Mask |= Val; 3998 if (i != 0) 3999 Mask <<= 2; 4000 } 4001 return Mask; 4002} 4003 4004/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4005/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4006static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4007 EVT VT = SVOp->getValueType(0); 4008 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4009 int Val = 0; 4010 4011 unsigned i, e; 4012 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4013 Val = SVOp->getMaskElt(i); 4014 if (Val >= 0) 4015 break; 4016 } 4017 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4018 return (Val - i) * EltSize; 4019} 4020 4021/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4022/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4023/// instructions. 4024unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4025 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4026 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4027 4028 uint64_t Index = 4029 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4030 4031 EVT VecVT = N->getOperand(0).getValueType(); 4032 EVT ElVT = VecVT.getVectorElementType(); 4033 4034 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4035 return Index / NumElemsPerChunk; 4036} 4037 4038/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4039/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4040/// instructions. 4041unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4042 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4043 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4044 4045 uint64_t Index = 4046 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4047 4048 EVT VecVT = N->getValueType(0); 4049 EVT ElVT = VecVT.getVectorElementType(); 4050 4051 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4052 return Index / NumElemsPerChunk; 4053} 4054 4055/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4056/// constant +0.0. 4057bool X86::isZeroNode(SDValue Elt) { 4058 return ((isa<ConstantSDNode>(Elt) && 4059 cast<ConstantSDNode>(Elt)->isNullValue()) || 4060 (isa<ConstantFPSDNode>(Elt) && 4061 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4062} 4063 4064/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4065/// their permute mask. 4066static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4067 SelectionDAG &DAG) { 4068 EVT VT = SVOp->getValueType(0); 4069 unsigned NumElems = VT.getVectorNumElements(); 4070 SmallVector<int, 8> MaskVec; 4071 4072 for (unsigned i = 0; i != NumElems; ++i) { 4073 int idx = SVOp->getMaskElt(i); 4074 if (idx < 0) 4075 MaskVec.push_back(idx); 4076 else if (idx < (int)NumElems) 4077 MaskVec.push_back(idx + NumElems); 4078 else 4079 MaskVec.push_back(idx - NumElems); 4080 } 4081 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4082 SVOp->getOperand(0), &MaskVec[0]); 4083} 4084 4085/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4086/// match movhlps. The lower half elements should come from upper half of 4087/// V1 (and in order), and the upper half elements should come from the upper 4088/// half of V2 (and in order). 4089static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4090 EVT VT = Op->getValueType(0); 4091 if (VT.getSizeInBits() != 128) 4092 return false; 4093 if (VT.getVectorNumElements() != 4) 4094 return false; 4095 for (unsigned i = 0, e = 2; i != e; ++i) 4096 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4097 return false; 4098 for (unsigned i = 2; i != 4; ++i) 4099 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4100 return false; 4101 return true; 4102} 4103 4104/// isScalarLoadToVector - Returns true if the node is a scalar load that 4105/// is promoted to a vector. It also returns the LoadSDNode by reference if 4106/// required. 4107static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4108 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4109 return false; 4110 N = N->getOperand(0).getNode(); 4111 if (!ISD::isNON_EXTLoad(N)) 4112 return false; 4113 if (LD) 4114 *LD = cast<LoadSDNode>(N); 4115 return true; 4116} 4117 4118// Test whether the given value is a vector value which will be legalized 4119// into a load. 4120static bool WillBeConstantPoolLoad(SDNode *N) { 4121 if (N->getOpcode() != ISD::BUILD_VECTOR) 4122 return false; 4123 4124 // Check for any non-constant elements. 4125 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4126 switch (N->getOperand(i).getNode()->getOpcode()) { 4127 case ISD::UNDEF: 4128 case ISD::ConstantFP: 4129 case ISD::Constant: 4130 break; 4131 default: 4132 return false; 4133 } 4134 4135 // Vectors of all-zeros and all-ones are materialized with special 4136 // instructions rather than being loaded. 4137 return !ISD::isBuildVectorAllZeros(N) && 4138 !ISD::isBuildVectorAllOnes(N); 4139} 4140 4141/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4142/// match movlp{s|d}. The lower half elements should come from lower half of 4143/// V1 (and in order), and the upper half elements should come from the upper 4144/// half of V2 (and in order). And since V1 will become the source of the 4145/// MOVLP, it must be either a vector load or a scalar load to vector. 4146static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4147 ShuffleVectorSDNode *Op) { 4148 EVT VT = Op->getValueType(0); 4149 if (VT.getSizeInBits() != 128) 4150 return false; 4151 4152 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4153 return false; 4154 // Is V2 is a vector load, don't do this transformation. We will try to use 4155 // load folding shufps op. 4156 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4157 return false; 4158 4159 unsigned NumElems = VT.getVectorNumElements(); 4160 4161 if (NumElems != 2 && NumElems != 4) 4162 return false; 4163 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4164 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4165 return false; 4166 for (unsigned i = NumElems/2; i != NumElems; ++i) 4167 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4168 return false; 4169 return true; 4170} 4171 4172/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4173/// all the same. 4174static bool isSplatVector(SDNode *N) { 4175 if (N->getOpcode() != ISD::BUILD_VECTOR) 4176 return false; 4177 4178 SDValue SplatValue = N->getOperand(0); 4179 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4180 if (N->getOperand(i) != SplatValue) 4181 return false; 4182 return true; 4183} 4184 4185/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4186/// to an zero vector. 4187/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4188static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4189 SDValue V1 = N->getOperand(0); 4190 SDValue V2 = N->getOperand(1); 4191 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4192 for (unsigned i = 0; i != NumElems; ++i) { 4193 int Idx = N->getMaskElt(i); 4194 if (Idx >= (int)NumElems) { 4195 unsigned Opc = V2.getOpcode(); 4196 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4197 continue; 4198 if (Opc != ISD::BUILD_VECTOR || 4199 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4200 return false; 4201 } else if (Idx >= 0) { 4202 unsigned Opc = V1.getOpcode(); 4203 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4204 continue; 4205 if (Opc != ISD::BUILD_VECTOR || 4206 !X86::isZeroNode(V1.getOperand(Idx))) 4207 return false; 4208 } 4209 } 4210 return true; 4211} 4212 4213/// getZeroVector - Returns a vector of specified type with all zero elements. 4214/// 4215static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2, 4216 SelectionDAG &DAG, DebugLoc dl) { 4217 assert(VT.isVector() && "Expected a vector type"); 4218 4219 // Always build SSE zero vectors as <4 x i32> bitcasted 4220 // to their dest type. This ensures they get CSE'd. 4221 SDValue Vec; 4222 if (VT.getSizeInBits() == 128) { // SSE 4223 if (HasSSE2) { // SSE2 4224 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4225 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4226 } else { // SSE1 4227 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4228 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4229 } 4230 } else if (VT.getSizeInBits() == 256) { // AVX 4231 if (HasAVX2) { // AVX2 4232 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4233 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4235 } else { 4236 // 256-bit logic and arithmetic instructions in AVX are all 4237 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4238 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4239 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4240 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4241 } 4242 } 4243 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4244} 4245 4246/// getOnesVector - Returns a vector of specified type with all bits set. 4247/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4248/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4249/// Then bitcast to their original type, ensuring they get CSE'd. 4250static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4251 DebugLoc dl) { 4252 assert(VT.isVector() && "Expected a vector type"); 4253 assert((VT.is128BitVector() || VT.is256BitVector()) 4254 && "Expected a 128-bit or 256-bit vector type"); 4255 4256 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4257 SDValue Vec; 4258 if (VT.getSizeInBits() == 256) { 4259 if (HasAVX2) { // AVX2 4260 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4262 } else { // AVX 4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4264 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4265 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4266 Vec = Insert128BitVector(InsV, Vec, 4267 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4268 } 4269 } else { 4270 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4271 } 4272 4273 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4274} 4275 4276/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4277/// that point to V2 points to its first element. 4278static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4279 EVT VT = SVOp->getValueType(0); 4280 unsigned NumElems = VT.getVectorNumElements(); 4281 4282 bool Changed = false; 4283 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end()); 4284 4285 for (unsigned i = 0; i != NumElems; ++i) { 4286 if (MaskVec[i] > (int)NumElems) { 4287 MaskVec[i] = NumElems; 4288 Changed = true; 4289 } 4290 } 4291 if (Changed) 4292 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4293 SVOp->getOperand(1), &MaskVec[0]); 4294 return SDValue(SVOp, 0); 4295} 4296 4297/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4298/// operation of specified width. 4299static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4300 SDValue V2) { 4301 unsigned NumElems = VT.getVectorNumElements(); 4302 SmallVector<int, 8> Mask; 4303 Mask.push_back(NumElems); 4304 for (unsigned i = 1; i != NumElems; ++i) 4305 Mask.push_back(i); 4306 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4307} 4308 4309/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4310static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4311 SDValue V2) { 4312 unsigned NumElems = VT.getVectorNumElements(); 4313 SmallVector<int, 8> Mask; 4314 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4315 Mask.push_back(i); 4316 Mask.push_back(i + NumElems); 4317 } 4318 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4319} 4320 4321/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4322static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4323 SDValue V2) { 4324 unsigned NumElems = VT.getVectorNumElements(); 4325 unsigned Half = NumElems/2; 4326 SmallVector<int, 8> Mask; 4327 for (unsigned i = 0; i != Half; ++i) { 4328 Mask.push_back(i + Half); 4329 Mask.push_back(i + NumElems + Half); 4330 } 4331 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4332} 4333 4334// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4335// a generic shuffle instruction because the target has no such instructions. 4336// Generate shuffles which repeat i16 and i8 several times until they can be 4337// represented by v4f32 and then be manipulated by target suported shuffles. 4338static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4339 EVT VT = V.getValueType(); 4340 int NumElems = VT.getVectorNumElements(); 4341 DebugLoc dl = V.getDebugLoc(); 4342 4343 while (NumElems > 4) { 4344 if (EltNo < NumElems/2) { 4345 V = getUnpackl(DAG, dl, VT, V, V); 4346 } else { 4347 V = getUnpackh(DAG, dl, VT, V, V); 4348 EltNo -= NumElems/2; 4349 } 4350 NumElems >>= 1; 4351 } 4352 return V; 4353} 4354 4355/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4356static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4357 EVT VT = V.getValueType(); 4358 DebugLoc dl = V.getDebugLoc(); 4359 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4360 && "Vector size not supported"); 4361 4362 if (VT.getSizeInBits() == 128) { 4363 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4364 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4365 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4366 &SplatMask[0]); 4367 } else { 4368 // To use VPERMILPS to splat scalars, the second half of indicies must 4369 // refer to the higher part, which is a duplication of the lower one, 4370 // because VPERMILPS can only handle in-lane permutations. 4371 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4372 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4373 4374 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4375 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4376 &SplatMask[0]); 4377 } 4378 4379 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4380} 4381 4382/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4383static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4384 EVT SrcVT = SV->getValueType(0); 4385 SDValue V1 = SV->getOperand(0); 4386 DebugLoc dl = SV->getDebugLoc(); 4387 4388 int EltNo = SV->getSplatIndex(); 4389 int NumElems = SrcVT.getVectorNumElements(); 4390 unsigned Size = SrcVT.getSizeInBits(); 4391 4392 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4393 "Unknown how to promote splat for type"); 4394 4395 // Extract the 128-bit part containing the splat element and update 4396 // the splat element index when it refers to the higher register. 4397 if (Size == 256) { 4398 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4399 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4400 if (Idx > 0) 4401 EltNo -= NumElems/2; 4402 } 4403 4404 // All i16 and i8 vector types can't be used directly by a generic shuffle 4405 // instruction because the target has no such instruction. Generate shuffles 4406 // which repeat i16 and i8 several times until they fit in i32, and then can 4407 // be manipulated by target suported shuffles. 4408 EVT EltVT = SrcVT.getVectorElementType(); 4409 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4410 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4411 4412 // Recreate the 256-bit vector and place the same 128-bit vector 4413 // into the low and high part. This is necessary because we want 4414 // to use VPERM* to shuffle the vectors 4415 if (Size == 256) { 4416 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4417 DAG.getConstant(0, MVT::i32), DAG, dl); 4418 V1 = Insert128BitVector(InsV, V1, 4419 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4420 } 4421 4422 return getLegalSplat(DAG, V1, EltNo); 4423} 4424 4425/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4426/// vector of zero or undef vector. This produces a shuffle where the low 4427/// element of V2 is swizzled into the zero/undef vector, landing at element 4428/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4429static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4430 bool IsZero, 4431 const X86Subtarget *Subtarget, 4432 SelectionDAG &DAG) { 4433 EVT VT = V2.getValueType(); 4434 SDValue V1 = IsZero 4435 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG, 4436 V2.getDebugLoc()) : DAG.getUNDEF(VT); 4437 unsigned NumElems = VT.getVectorNumElements(); 4438 SmallVector<int, 16> MaskVec; 4439 for (unsigned i = 0; i != NumElems; ++i) 4440 // If this is the insertion idx, put the low elt of V2 here. 4441 MaskVec.push_back(i == Idx ? NumElems : i); 4442 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4443} 4444 4445/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4446/// element of the result of the vector shuffle. 4447static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4448 unsigned Depth) { 4449 if (Depth == 6) 4450 return SDValue(); // Limit search depth. 4451 4452 SDValue V = SDValue(N, 0); 4453 EVT VT = V.getValueType(); 4454 unsigned Opcode = V.getOpcode(); 4455 4456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4458 Index = SV->getMaskElt(Index); 4459 4460 if (Index < 0) 4461 return DAG.getUNDEF(VT.getVectorElementType()); 4462 4463 int NumElems = VT.getVectorNumElements(); 4464 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4465 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4466 } 4467 4468 // Recurse into target specific vector shuffles to find scalars. 4469 if (isTargetShuffle(Opcode)) { 4470 int NumElems = VT.getVectorNumElements(); 4471 SmallVector<unsigned, 16> ShuffleMask; 4472 SDValue ImmN; 4473 4474 switch(Opcode) { 4475 case X86ISD::SHUFP: 4476 ImmN = N->getOperand(N->getNumOperands()-1); 4477 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4478 ShuffleMask); 4479 break; 4480 case X86ISD::UNPCKH: 4481 DecodeUNPCKHMask(VT, ShuffleMask); 4482 break; 4483 case X86ISD::UNPCKL: 4484 DecodeUNPCKLMask(VT, ShuffleMask); 4485 break; 4486 case X86ISD::MOVHLPS: 4487 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4488 break; 4489 case X86ISD::MOVLHPS: 4490 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4491 break; 4492 case X86ISD::PSHUFD: 4493 ImmN = N->getOperand(N->getNumOperands()-1); 4494 DecodePSHUFMask(NumElems, 4495 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4496 ShuffleMask); 4497 break; 4498 case X86ISD::PSHUFHW: 4499 ImmN = N->getOperand(N->getNumOperands()-1); 4500 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4501 ShuffleMask); 4502 break; 4503 case X86ISD::PSHUFLW: 4504 ImmN = N->getOperand(N->getNumOperands()-1); 4505 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4506 ShuffleMask); 4507 break; 4508 case X86ISD::MOVSS: 4509 case X86ISD::MOVSD: { 4510 // The index 0 always comes from the first element of the second source, 4511 // this is why MOVSS and MOVSD are used in the first place. The other 4512 // elements come from the other positions of the first source vector. 4513 unsigned OpNum = (Index == 0) ? 1 : 0; 4514 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4515 Depth+1); 4516 } 4517 case X86ISD::VPERMILP: 4518 ImmN = N->getOperand(N->getNumOperands()-1); 4519 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4520 ShuffleMask); 4521 break; 4522 case X86ISD::VPERM2X128: 4523 ImmN = N->getOperand(N->getNumOperands()-1); 4524 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4525 ShuffleMask); 4526 break; 4527 case X86ISD::MOVDDUP: 4528 case X86ISD::MOVLHPD: 4529 case X86ISD::MOVLPD: 4530 case X86ISD::MOVLPS: 4531 case X86ISD::MOVSHDUP: 4532 case X86ISD::MOVSLDUP: 4533 case X86ISD::PALIGN: 4534 return SDValue(); // Not yet implemented. 4535 default: 4536 assert(0 && "unknown target shuffle node"); 4537 return SDValue(); 4538 } 4539 4540 Index = ShuffleMask[Index]; 4541 if (Index < 0) 4542 return DAG.getUNDEF(VT.getVectorElementType()); 4543 4544 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4545 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4546 Depth+1); 4547 } 4548 4549 // Actual nodes that may contain scalar elements 4550 if (Opcode == ISD::BITCAST) { 4551 V = V.getOperand(0); 4552 EVT SrcVT = V.getValueType(); 4553 unsigned NumElems = VT.getVectorNumElements(); 4554 4555 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4556 return SDValue(); 4557 } 4558 4559 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4560 return (Index == 0) ? V.getOperand(0) 4561 : DAG.getUNDEF(VT.getVectorElementType()); 4562 4563 if (V.getOpcode() == ISD::BUILD_VECTOR) 4564 return V.getOperand(Index); 4565 4566 return SDValue(); 4567} 4568 4569/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4570/// shuffle operation which come from a consecutively from a zero. The 4571/// search can start in two different directions, from left or right. 4572static 4573unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4574 bool ZerosFromLeft, SelectionDAG &DAG) { 4575 int i = 0; 4576 4577 while (i < NumElems) { 4578 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4579 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4580 if (!(Elt.getNode() && 4581 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4582 break; 4583 ++i; 4584 } 4585 4586 return i; 4587} 4588 4589/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4590/// MaskE correspond consecutively to elements from one of the vector operands, 4591/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4592static 4593bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4594 int OpIdx, int NumElems, unsigned &OpNum) { 4595 bool SeenV1 = false; 4596 bool SeenV2 = false; 4597 4598 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4599 int Idx = SVOp->getMaskElt(i); 4600 // Ignore undef indicies 4601 if (Idx < 0) 4602 continue; 4603 4604 if (Idx < NumElems) 4605 SeenV1 = true; 4606 else 4607 SeenV2 = true; 4608 4609 // Only accept consecutive elements from the same vector 4610 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4611 return false; 4612 } 4613 4614 OpNum = SeenV1 ? 0 : 1; 4615 return true; 4616} 4617 4618/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4619/// logical left shift of a vector. 4620static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4621 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4622 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4623 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4624 false /* check zeros from right */, DAG); 4625 unsigned OpSrc; 4626 4627 if (!NumZeros) 4628 return false; 4629 4630 // Considering the elements in the mask that are not consecutive zeros, 4631 // check if they consecutively come from only one of the source vectors. 4632 // 4633 // V1 = {X, A, B, C} 0 4634 // \ \ \ / 4635 // vector_shuffle V1, V2 <1, 2, 3, X> 4636 // 4637 if (!isShuffleMaskConsecutive(SVOp, 4638 0, // Mask Start Index 4639 NumElems-NumZeros-1, // Mask End Index 4640 NumZeros, // Where to start looking in the src vector 4641 NumElems, // Number of elements in vector 4642 OpSrc)) // Which source operand ? 4643 return false; 4644 4645 isLeft = false; 4646 ShAmt = NumZeros; 4647 ShVal = SVOp->getOperand(OpSrc); 4648 return true; 4649} 4650 4651/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4652/// logical left shift of a vector. 4653static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4654 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4655 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4656 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4657 true /* check zeros from left */, DAG); 4658 unsigned OpSrc; 4659 4660 if (!NumZeros) 4661 return false; 4662 4663 // Considering the elements in the mask that are not consecutive zeros, 4664 // check if they consecutively come from only one of the source vectors. 4665 // 4666 // 0 { A, B, X, X } = V2 4667 // / \ / / 4668 // vector_shuffle V1, V2 <X, X, 4, 5> 4669 // 4670 if (!isShuffleMaskConsecutive(SVOp, 4671 NumZeros, // Mask Start Index 4672 NumElems-1, // Mask End Index 4673 0, // Where to start looking in the src vector 4674 NumElems, // Number of elements in vector 4675 OpSrc)) // Which source operand ? 4676 return false; 4677 4678 isLeft = true; 4679 ShAmt = NumZeros; 4680 ShVal = SVOp->getOperand(OpSrc); 4681 return true; 4682} 4683 4684/// isVectorShift - Returns true if the shuffle can be implemented as a 4685/// logical left or right shift of a vector. 4686static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4687 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4688 // Although the logic below support any bitwidth size, there are no 4689 // shift instructions which handle more than 128-bit vectors. 4690 if (SVOp->getValueType(0).getSizeInBits() > 128) 4691 return false; 4692 4693 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4694 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4695 return true; 4696 4697 return false; 4698} 4699 4700/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4701/// 4702static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4703 unsigned NumNonZero, unsigned NumZero, 4704 SelectionDAG &DAG, 4705 const TargetLowering &TLI) { 4706 if (NumNonZero > 8) 4707 return SDValue(); 4708 4709 DebugLoc dl = Op.getDebugLoc(); 4710 SDValue V(0, 0); 4711 bool First = true; 4712 for (unsigned i = 0; i < 16; ++i) { 4713 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4714 if (ThisIsNonZero && First) { 4715 if (NumZero) 4716 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false, 4717 DAG, dl); 4718 else 4719 V = DAG.getUNDEF(MVT::v8i16); 4720 First = false; 4721 } 4722 4723 if ((i & 1) != 0) { 4724 SDValue ThisElt(0, 0), LastElt(0, 0); 4725 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4726 if (LastIsNonZero) { 4727 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4728 MVT::i16, Op.getOperand(i-1)); 4729 } 4730 if (ThisIsNonZero) { 4731 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4732 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4733 ThisElt, DAG.getConstant(8, MVT::i8)); 4734 if (LastIsNonZero) 4735 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4736 } else 4737 ThisElt = LastElt; 4738 4739 if (ThisElt.getNode()) 4740 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4741 DAG.getIntPtrConstant(i/2)); 4742 } 4743 } 4744 4745 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4746} 4747 4748/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4749/// 4750static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4751 unsigned NumNonZero, unsigned NumZero, 4752 SelectionDAG &DAG, 4753 const TargetLowering &TLI) { 4754 if (NumNonZero > 4) 4755 return SDValue(); 4756 4757 DebugLoc dl = Op.getDebugLoc(); 4758 SDValue V(0, 0); 4759 bool First = true; 4760 for (unsigned i = 0; i < 8; ++i) { 4761 bool isNonZero = (NonZeros & (1 << i)) != 0; 4762 if (isNonZero) { 4763 if (First) { 4764 if (NumZero) 4765 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false, 4766 DAG, dl); 4767 else 4768 V = DAG.getUNDEF(MVT::v8i16); 4769 First = false; 4770 } 4771 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4772 MVT::v8i16, V, Op.getOperand(i), 4773 DAG.getIntPtrConstant(i)); 4774 } 4775 } 4776 4777 return V; 4778} 4779 4780/// getVShift - Return a vector logical shift node. 4781/// 4782static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4783 unsigned NumBits, SelectionDAG &DAG, 4784 const TargetLowering &TLI, DebugLoc dl) { 4785 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4786 EVT ShVT = MVT::v2i64; 4787 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4788 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4789 return DAG.getNode(ISD::BITCAST, dl, VT, 4790 DAG.getNode(Opc, dl, ShVT, SrcOp, 4791 DAG.getConstant(NumBits, 4792 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4793} 4794 4795SDValue 4796X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4797 SelectionDAG &DAG) const { 4798 4799 // Check if the scalar load can be widened into a vector load. And if 4800 // the address is "base + cst" see if the cst can be "absorbed" into 4801 // the shuffle mask. 4802 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4803 SDValue Ptr = LD->getBasePtr(); 4804 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4805 return SDValue(); 4806 EVT PVT = LD->getValueType(0); 4807 if (PVT != MVT::i32 && PVT != MVT::f32) 4808 return SDValue(); 4809 4810 int FI = -1; 4811 int64_t Offset = 0; 4812 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4813 FI = FINode->getIndex(); 4814 Offset = 0; 4815 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4816 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4817 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4818 Offset = Ptr.getConstantOperandVal(1); 4819 Ptr = Ptr.getOperand(0); 4820 } else { 4821 return SDValue(); 4822 } 4823 4824 // FIXME: 256-bit vector instructions don't require a strict alignment, 4825 // improve this code to support it better. 4826 unsigned RequiredAlign = VT.getSizeInBits()/8; 4827 SDValue Chain = LD->getChain(); 4828 // Make sure the stack object alignment is at least 16 or 32. 4829 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4830 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4831 if (MFI->isFixedObjectIndex(FI)) { 4832 // Can't change the alignment. FIXME: It's possible to compute 4833 // the exact stack offset and reference FI + adjust offset instead. 4834 // If someone *really* cares about this. That's the way to implement it. 4835 return SDValue(); 4836 } else { 4837 MFI->setObjectAlignment(FI, RequiredAlign); 4838 } 4839 } 4840 4841 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4842 // Ptr + (Offset & ~15). 4843 if (Offset < 0) 4844 return SDValue(); 4845 if ((Offset % RequiredAlign) & 3) 4846 return SDValue(); 4847 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4848 if (StartOffset) 4849 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4850 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4851 4852 int EltNo = (Offset - StartOffset) >> 2; 4853 int NumElems = VT.getVectorNumElements(); 4854 4855 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4856 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4857 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4858 LD->getPointerInfo().getWithOffset(StartOffset), 4859 false, false, false, 0); 4860 4861 // Canonicalize it to a v4i32 or v8i32 shuffle. 4862 SmallVector<int, 8> Mask; 4863 for (int i = 0; i < NumElems; ++i) 4864 Mask.push_back(EltNo); 4865 4866 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4867 return DAG.getNode(ISD::BITCAST, dl, NVT, 4868 DAG.getVectorShuffle(CanonVT, dl, V1, 4869 DAG.getUNDEF(CanonVT),&Mask[0])); 4870 } 4871 4872 return SDValue(); 4873} 4874 4875/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4876/// vector of type 'VT', see if the elements can be replaced by a single large 4877/// load which has the same value as a build_vector whose operands are 'elts'. 4878/// 4879/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4880/// 4881/// FIXME: we'd also like to handle the case where the last elements are zero 4882/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4883/// There's even a handy isZeroNode for that purpose. 4884static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4885 DebugLoc &DL, SelectionDAG &DAG) { 4886 EVT EltVT = VT.getVectorElementType(); 4887 unsigned NumElems = Elts.size(); 4888 4889 LoadSDNode *LDBase = NULL; 4890 unsigned LastLoadedElt = -1U; 4891 4892 // For each element in the initializer, see if we've found a load or an undef. 4893 // If we don't find an initial load element, or later load elements are 4894 // non-consecutive, bail out. 4895 for (unsigned i = 0; i < NumElems; ++i) { 4896 SDValue Elt = Elts[i]; 4897 4898 if (!Elt.getNode() || 4899 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4900 return SDValue(); 4901 if (!LDBase) { 4902 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4903 return SDValue(); 4904 LDBase = cast<LoadSDNode>(Elt.getNode()); 4905 LastLoadedElt = i; 4906 continue; 4907 } 4908 if (Elt.getOpcode() == ISD::UNDEF) 4909 continue; 4910 4911 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4912 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4913 return SDValue(); 4914 LastLoadedElt = i; 4915 } 4916 4917 // If we have found an entire vector of loads and undefs, then return a large 4918 // load of the entire vector width starting at the base pointer. If we found 4919 // consecutive loads for the low half, generate a vzext_load node. 4920 if (LastLoadedElt == NumElems - 1) { 4921 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4922 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4923 LDBase->getPointerInfo(), 4924 LDBase->isVolatile(), LDBase->isNonTemporal(), 4925 LDBase->isInvariant(), 0); 4926 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4927 LDBase->getPointerInfo(), 4928 LDBase->isVolatile(), LDBase->isNonTemporal(), 4929 LDBase->isInvariant(), LDBase->getAlignment()); 4930 } else if (NumElems == 4 && LastLoadedElt == 1 && 4931 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4932 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4933 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4934 SDValue ResNode = 4935 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4936 LDBase->getPointerInfo(), 4937 LDBase->getAlignment(), 4938 false/*isVolatile*/, true/*ReadMem*/, 4939 false/*WriteMem*/); 4940 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4941 } 4942 return SDValue(); 4943} 4944 4945/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4946/// a vbroadcast node. We support two patterns: 4947/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4948/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4949/// a scalar load. 4950/// The scalar load node is returned when a pattern is found, 4951/// or SDValue() otherwise. 4952static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4953 if (!Subtarget->hasAVX()) 4954 return SDValue(); 4955 4956 EVT VT = Op.getValueType(); 4957 SDValue V = Op; 4958 4959 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4960 V = V.getOperand(0); 4961 4962 //A suspected load to be broadcasted. 4963 SDValue Ld; 4964 4965 switch (V.getOpcode()) { 4966 default: 4967 // Unknown pattern found. 4968 return SDValue(); 4969 4970 case ISD::BUILD_VECTOR: { 4971 // The BUILD_VECTOR node must be a splat. 4972 if (!isSplatVector(V.getNode())) 4973 return SDValue(); 4974 4975 Ld = V.getOperand(0); 4976 4977 // The suspected load node has several users. Make sure that all 4978 // of its users are from the BUILD_VECTOR node. 4979 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4980 return SDValue(); 4981 break; 4982 } 4983 4984 case ISD::VECTOR_SHUFFLE: { 4985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4986 4987 // Shuffles must have a splat mask where the first element is 4988 // broadcasted. 4989 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4990 return SDValue(); 4991 4992 SDValue Sc = Op.getOperand(0); 4993 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4994 return SDValue(); 4995 4996 Ld = Sc.getOperand(0); 4997 4998 // The scalar_to_vector node and the suspected 4999 // load node must have exactly one user. 5000 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 5001 return SDValue(); 5002 break; 5003 } 5004 } 5005 5006 // The scalar source must be a normal load. 5007 if (!ISD::isNormalLoad(Ld.getNode())) 5008 return SDValue(); 5009 5010 bool Is256 = VT.getSizeInBits() == 256; 5011 bool Is128 = VT.getSizeInBits() == 128; 5012 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5013 5014 // VBroadcast to YMM 5015 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5016 return Ld; 5017 5018 // VBroadcast to XMM 5019 if (Is128 && (ScalarSize == 32)) 5020 return Ld; 5021 5022 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5023 // double since there is vbroadcastsd xmm 5024 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5025 // VBroadcast to YMM 5026 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5027 return Ld; 5028 5029 // VBroadcast to XMM 5030 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5031 return Ld; 5032 } 5033 5034 // Unsupported broadcast. 5035 return SDValue(); 5036} 5037 5038SDValue 5039X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5040 DebugLoc dl = Op.getDebugLoc(); 5041 5042 EVT VT = Op.getValueType(); 5043 EVT ExtVT = VT.getVectorElementType(); 5044 unsigned NumElems = Op.getNumOperands(); 5045 5046 // Vectors containing all zeros can be matched by pxor and xorps later 5047 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5048 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5049 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5050 if (Op.getValueType() == MVT::v4i32 || 5051 Op.getValueType() == MVT::v8i32) 5052 return Op; 5053 5054 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), 5055 Subtarget->hasAVX2(), DAG, dl); 5056 } 5057 5058 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5059 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5060 // vpcmpeqd on 256-bit vectors. 5061 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5062 if (Op.getValueType() == MVT::v4i32 || 5063 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2())) 5064 return Op; 5065 5066 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); 5067 } 5068 5069 SDValue LD = isVectorBroadcast(Op, Subtarget); 5070 if (LD.getNode()) 5071 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5072 5073 unsigned EVTBits = ExtVT.getSizeInBits(); 5074 5075 unsigned NumZero = 0; 5076 unsigned NumNonZero = 0; 5077 unsigned NonZeros = 0; 5078 bool IsAllConstants = true; 5079 SmallSet<SDValue, 8> Values; 5080 for (unsigned i = 0; i < NumElems; ++i) { 5081 SDValue Elt = Op.getOperand(i); 5082 if (Elt.getOpcode() == ISD::UNDEF) 5083 continue; 5084 Values.insert(Elt); 5085 if (Elt.getOpcode() != ISD::Constant && 5086 Elt.getOpcode() != ISD::ConstantFP) 5087 IsAllConstants = false; 5088 if (X86::isZeroNode(Elt)) 5089 NumZero++; 5090 else { 5091 NonZeros |= (1 << i); 5092 NumNonZero++; 5093 } 5094 } 5095 5096 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5097 if (NumNonZero == 0) 5098 return DAG.getUNDEF(VT); 5099 5100 // Special case for single non-zero, non-undef, element. 5101 if (NumNonZero == 1) { 5102 unsigned Idx = CountTrailingZeros_32(NonZeros); 5103 SDValue Item = Op.getOperand(Idx); 5104 5105 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5106 // the value are obviously zero, truncate the value to i32 and do the 5107 // insertion that way. Only do this if the value is non-constant or if the 5108 // value is a constant being inserted into element 0. It is cheaper to do 5109 // a constant pool load than it is to do a movd + shuffle. 5110 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5111 (!IsAllConstants || Idx == 0)) { 5112 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5113 // Handle SSE only. 5114 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5115 EVT VecVT = MVT::v4i32; 5116 unsigned VecElts = 4; 5117 5118 // Truncate the value (which may itself be a constant) to i32, and 5119 // convert it to a vector with movd (S2V+shuffle to zero extend). 5120 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5121 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5122 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5123 5124 // Now we have our 32-bit value zero extended in the low element of 5125 // a vector. If Idx != 0, swizzle it into place. 5126 if (Idx != 0) { 5127 SmallVector<int, 4> Mask; 5128 Mask.push_back(Idx); 5129 for (unsigned i = 1; i != VecElts; ++i) 5130 Mask.push_back(i); 5131 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5132 DAG.getUNDEF(Item.getValueType()), 5133 &Mask[0]); 5134 } 5135 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5136 } 5137 } 5138 5139 // If we have a constant or non-constant insertion into the low element of 5140 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5141 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5142 // depending on what the source datatype is. 5143 if (Idx == 0) { 5144 if (NumZero == 0) 5145 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5146 5147 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5148 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5149 if (VT.getSizeInBits() == 256) { 5150 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(), 5151 Subtarget->hasAVX2(), DAG, dl); 5152 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5153 Item, DAG.getIntPtrConstant(0)); 5154 } 5155 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5156 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5157 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5158 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5159 } 5160 5161 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5162 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5163 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5164 if (VT.getSizeInBits() == 256) { 5165 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(), 5166 Subtarget->hasAVX2(), DAG, dl); 5167 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5168 DAG, dl); 5169 } else { 5170 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5171 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5172 } 5173 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5174 } 5175 } 5176 5177 // Is it a vector logical left shift? 5178 if (NumElems == 2 && Idx == 1 && 5179 X86::isZeroNode(Op.getOperand(0)) && 5180 !X86::isZeroNode(Op.getOperand(1))) { 5181 unsigned NumBits = VT.getSizeInBits(); 5182 return getVShift(true, VT, 5183 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5184 VT, Op.getOperand(1)), 5185 NumBits/2, DAG, *this, dl); 5186 } 5187 5188 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5189 return SDValue(); 5190 5191 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5192 // is a non-constant being inserted into an element other than the low one, 5193 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5194 // movd/movss) to move this into the low element, then shuffle it into 5195 // place. 5196 if (EVTBits == 32) { 5197 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5198 5199 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5200 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5201 SmallVector<int, 8> MaskVec; 5202 for (unsigned i = 0; i < NumElems; i++) 5203 MaskVec.push_back(i == Idx ? 0 : 1); 5204 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5205 } 5206 } 5207 5208 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5209 if (Values.size() == 1) { 5210 if (EVTBits == 32) { 5211 // Instead of a shuffle like this: 5212 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5213 // Check if it's possible to issue this instead. 5214 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5215 unsigned Idx = CountTrailingZeros_32(NonZeros); 5216 SDValue Item = Op.getOperand(Idx); 5217 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5218 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5219 } 5220 return SDValue(); 5221 } 5222 5223 // A vector full of immediates; various special cases are already 5224 // handled, so this is best done with a single constant-pool load. 5225 if (IsAllConstants) 5226 return SDValue(); 5227 5228 // For AVX-length vectors, build the individual 128-bit pieces and use 5229 // shuffles to put them in place. 5230 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5231 SmallVector<SDValue, 32> V; 5232 for (unsigned i = 0; i < NumElems; ++i) 5233 V.push_back(Op.getOperand(i)); 5234 5235 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5236 5237 // Build both the lower and upper subvector. 5238 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5239 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5240 NumElems/2); 5241 5242 // Recreate the wider vector with the lower and upper part. 5243 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5244 DAG.getConstant(0, MVT::i32), DAG, dl); 5245 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5246 DAG, dl); 5247 } 5248 5249 // Let legalizer expand 2-wide build_vectors. 5250 if (EVTBits == 64) { 5251 if (NumNonZero == 1) { 5252 // One half is zero or undef. 5253 unsigned Idx = CountTrailingZeros_32(NonZeros); 5254 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5255 Op.getOperand(Idx)); 5256 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5257 } 5258 return SDValue(); 5259 } 5260 5261 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5262 if (EVTBits == 8 && NumElems == 16) { 5263 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5264 *this); 5265 if (V.getNode()) return V; 5266 } 5267 5268 if (EVTBits == 16 && NumElems == 8) { 5269 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5270 *this); 5271 if (V.getNode()) return V; 5272 } 5273 5274 // If element VT is == 32 bits, turn it into a number of shuffles. 5275 SmallVector<SDValue, 8> V; 5276 V.resize(NumElems); 5277 if (NumElems == 4 && NumZero > 0) { 5278 for (unsigned i = 0; i < 4; ++i) { 5279 bool isZero = !(NonZeros & (1 << i)); 5280 if (isZero) 5281 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), 5282 DAG, dl); 5283 else 5284 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5285 } 5286 5287 for (unsigned i = 0; i < 2; ++i) { 5288 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5289 default: break; 5290 case 0: 5291 V[i] = V[i*2]; // Must be a zero vector. 5292 break; 5293 case 1: 5294 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5295 break; 5296 case 2: 5297 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5298 break; 5299 case 3: 5300 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5301 break; 5302 } 5303 } 5304 5305 SmallVector<int, 8> MaskVec; 5306 bool Reverse = (NonZeros & 0x3) == 2; 5307 for (unsigned i = 0; i < 2; ++i) 5308 MaskVec.push_back(Reverse ? 1-i : i); 5309 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5310 for (unsigned i = 0; i < 2; ++i) 5311 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5312 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5313 } 5314 5315 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5316 // Check for a build vector of consecutive loads. 5317 for (unsigned i = 0; i < NumElems; ++i) 5318 V[i] = Op.getOperand(i); 5319 5320 // Check for elements which are consecutive loads. 5321 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5322 if (LD.getNode()) 5323 return LD; 5324 5325 // For SSE 4.1, use insertps to put the high elements into the low element. 5326 if (getSubtarget()->hasSSE41()) { 5327 SDValue Result; 5328 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5329 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5330 else 5331 Result = DAG.getUNDEF(VT); 5332 5333 for (unsigned i = 1; i < NumElems; ++i) { 5334 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5335 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5336 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5337 } 5338 return Result; 5339 } 5340 5341 // Otherwise, expand into a number of unpckl*, start by extending each of 5342 // our (non-undef) elements to the full vector width with the element in the 5343 // bottom slot of the vector (which generates no code for SSE). 5344 for (unsigned i = 0; i < NumElems; ++i) { 5345 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5346 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5347 else 5348 V[i] = DAG.getUNDEF(VT); 5349 } 5350 5351 // Next, we iteratively mix elements, e.g. for v4f32: 5352 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5353 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5354 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5355 unsigned EltStride = NumElems >> 1; 5356 while (EltStride != 0) { 5357 for (unsigned i = 0; i < EltStride; ++i) { 5358 // If V[i+EltStride] is undef and this is the first round of mixing, 5359 // then it is safe to just drop this shuffle: V[i] is already in the 5360 // right place, the one element (since it's the first round) being 5361 // inserted as undef can be dropped. This isn't safe for successive 5362 // rounds because they will permute elements within both vectors. 5363 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5364 EltStride == NumElems/2) 5365 continue; 5366 5367 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5368 } 5369 EltStride >>= 1; 5370 } 5371 return V[0]; 5372 } 5373 return SDValue(); 5374} 5375 5376// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5377// them in a MMX register. This is better than doing a stack convert. 5378static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5379 DebugLoc dl = Op.getDebugLoc(); 5380 EVT ResVT = Op.getValueType(); 5381 5382 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5383 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5384 int Mask[2]; 5385 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5386 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5387 InVec = Op.getOperand(1); 5388 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5389 unsigned NumElts = ResVT.getVectorNumElements(); 5390 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5391 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5392 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5393 } else { 5394 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5395 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5396 Mask[0] = 0; Mask[1] = 2; 5397 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5398 } 5399 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5400} 5401 5402// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5403// to create 256-bit vectors from two other 128-bit ones. 5404static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5405 DebugLoc dl = Op.getDebugLoc(); 5406 EVT ResVT = Op.getValueType(); 5407 5408 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5409 5410 SDValue V1 = Op.getOperand(0); 5411 SDValue V2 = Op.getOperand(1); 5412 unsigned NumElems = ResVT.getVectorNumElements(); 5413 5414 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5415 DAG.getConstant(0, MVT::i32), DAG, dl); 5416 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5417 DAG, dl); 5418} 5419 5420SDValue 5421X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5422 EVT ResVT = Op.getValueType(); 5423 5424 assert(Op.getNumOperands() == 2); 5425 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5426 "Unsupported CONCAT_VECTORS for value type"); 5427 5428 // We support concatenate two MMX registers and place them in a MMX register. 5429 // This is better than doing a stack convert. 5430 if (ResVT.is128BitVector()) 5431 return LowerMMXCONCAT_VECTORS(Op, DAG); 5432 5433 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5434 // from two other 128-bit ones. 5435 return LowerAVXCONCAT_VECTORS(Op, DAG); 5436} 5437 5438// v8i16 shuffles - Prefer shuffles in the following order: 5439// 1. [all] pshuflw, pshufhw, optional move 5440// 2. [ssse3] 1 x pshufb 5441// 3. [ssse3] 2 x pshufb + 1 x por 5442// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5443SDValue 5444X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5445 SelectionDAG &DAG) const { 5446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5447 SDValue V1 = SVOp->getOperand(0); 5448 SDValue V2 = SVOp->getOperand(1); 5449 DebugLoc dl = SVOp->getDebugLoc(); 5450 SmallVector<int, 8> MaskVals; 5451 5452 // Determine if more than 1 of the words in each of the low and high quadwords 5453 // of the result come from the same quadword of one of the two inputs. Undef 5454 // mask values count as coming from any quadword, for better codegen. 5455 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5456 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5457 BitVector InputQuads(4); 5458 for (unsigned i = 0; i < 8; ++i) { 5459 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5460 int EltIdx = SVOp->getMaskElt(i); 5461 MaskVals.push_back(EltIdx); 5462 if (EltIdx < 0) { 5463 ++Quad[0]; 5464 ++Quad[1]; 5465 ++Quad[2]; 5466 ++Quad[3]; 5467 continue; 5468 } 5469 ++Quad[EltIdx / 4]; 5470 InputQuads.set(EltIdx / 4); 5471 } 5472 5473 int BestLoQuad = -1; 5474 unsigned MaxQuad = 1; 5475 for (unsigned i = 0; i < 4; ++i) { 5476 if (LoQuad[i] > MaxQuad) { 5477 BestLoQuad = i; 5478 MaxQuad = LoQuad[i]; 5479 } 5480 } 5481 5482 int BestHiQuad = -1; 5483 MaxQuad = 1; 5484 for (unsigned i = 0; i < 4; ++i) { 5485 if (HiQuad[i] > MaxQuad) { 5486 BestHiQuad = i; 5487 MaxQuad = HiQuad[i]; 5488 } 5489 } 5490 5491 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5492 // of the two input vectors, shuffle them into one input vector so only a 5493 // single pshufb instruction is necessary. If There are more than 2 input 5494 // quads, disable the next transformation since it does not help SSSE3. 5495 bool V1Used = InputQuads[0] || InputQuads[1]; 5496 bool V2Used = InputQuads[2] || InputQuads[3]; 5497 if (Subtarget->hasSSSE3()) { 5498 if (InputQuads.count() == 2 && V1Used && V2Used) { 5499 BestLoQuad = InputQuads.find_first(); 5500 BestHiQuad = InputQuads.find_next(BestLoQuad); 5501 } 5502 if (InputQuads.count() > 2) { 5503 BestLoQuad = -1; 5504 BestHiQuad = -1; 5505 } 5506 } 5507 5508 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5509 // the shuffle mask. If a quad is scored as -1, that means that it contains 5510 // words from all 4 input quadwords. 5511 SDValue NewV; 5512 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5513 SmallVector<int, 8> MaskV; 5514 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5515 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5516 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5517 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5518 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5519 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5520 5521 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5522 // source words for the shuffle, to aid later transformations. 5523 bool AllWordsInNewV = true; 5524 bool InOrder[2] = { true, true }; 5525 for (unsigned i = 0; i != 8; ++i) { 5526 int idx = MaskVals[i]; 5527 if (idx != (int)i) 5528 InOrder[i/4] = false; 5529 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5530 continue; 5531 AllWordsInNewV = false; 5532 break; 5533 } 5534 5535 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5536 if (AllWordsInNewV) { 5537 for (int i = 0; i != 8; ++i) { 5538 int idx = MaskVals[i]; 5539 if (idx < 0) 5540 continue; 5541 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5542 if ((idx != i) && idx < 4) 5543 pshufhw = false; 5544 if ((idx != i) && idx > 3) 5545 pshuflw = false; 5546 } 5547 V1 = NewV; 5548 V2Used = false; 5549 BestLoQuad = 0; 5550 BestHiQuad = 1; 5551 } 5552 5553 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5554 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5555 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5556 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5557 unsigned TargetMask = 0; 5558 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5559 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5560 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5561 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5562 V1 = NewV.getOperand(0); 5563 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5564 } 5565 } 5566 5567 // If we have SSSE3, and all words of the result are from 1 input vector, 5568 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5569 // is present, fall back to case 4. 5570 if (Subtarget->hasSSSE3()) { 5571 SmallVector<SDValue,16> pshufbMask; 5572 5573 // If we have elements from both input vectors, set the high bit of the 5574 // shuffle mask element to zero out elements that come from V2 in the V1 5575 // mask, and elements that come from V1 in the V2 mask, so that the two 5576 // results can be OR'd together. 5577 bool TwoInputs = V1Used && V2Used; 5578 for (unsigned i = 0; i != 8; ++i) { 5579 int EltIdx = MaskVals[i] * 2; 5580 if (TwoInputs && (EltIdx >= 16)) { 5581 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5582 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5583 continue; 5584 } 5585 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5586 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5587 } 5588 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5589 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5590 DAG.getNode(ISD::BUILD_VECTOR, dl, 5591 MVT::v16i8, &pshufbMask[0], 16)); 5592 if (!TwoInputs) 5593 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5594 5595 // Calculate the shuffle mask for the second input, shuffle it, and 5596 // OR it with the first shuffled input. 5597 pshufbMask.clear(); 5598 for (unsigned i = 0; i != 8; ++i) { 5599 int EltIdx = MaskVals[i] * 2; 5600 if (EltIdx < 16) { 5601 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5602 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5603 continue; 5604 } 5605 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5606 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5607 } 5608 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5609 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5610 DAG.getNode(ISD::BUILD_VECTOR, dl, 5611 MVT::v16i8, &pshufbMask[0], 16)); 5612 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5613 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5614 } 5615 5616 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5617 // and update MaskVals with new element order. 5618 BitVector InOrder(8); 5619 if (BestLoQuad >= 0) { 5620 SmallVector<int, 8> MaskV; 5621 for (int i = 0; i != 4; ++i) { 5622 int idx = MaskVals[i]; 5623 if (idx < 0) { 5624 MaskV.push_back(-1); 5625 InOrder.set(i); 5626 } else if ((idx / 4) == BestLoQuad) { 5627 MaskV.push_back(idx & 3); 5628 InOrder.set(i); 5629 } else { 5630 MaskV.push_back(-1); 5631 } 5632 } 5633 for (unsigned i = 4; i != 8; ++i) 5634 MaskV.push_back(i); 5635 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5636 &MaskV[0]); 5637 5638 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5639 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5640 NewV.getOperand(0), 5641 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5642 DAG); 5643 } 5644 5645 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5646 // and update MaskVals with the new element order. 5647 if (BestHiQuad >= 0) { 5648 SmallVector<int, 8> MaskV; 5649 for (unsigned i = 0; i != 4; ++i) 5650 MaskV.push_back(i); 5651 for (unsigned i = 4; i != 8; ++i) { 5652 int idx = MaskVals[i]; 5653 if (idx < 0) { 5654 MaskV.push_back(-1); 5655 InOrder.set(i); 5656 } else if ((idx / 4) == BestHiQuad) { 5657 MaskV.push_back((idx & 3) + 4); 5658 InOrder.set(i); 5659 } else { 5660 MaskV.push_back(-1); 5661 } 5662 } 5663 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5664 &MaskV[0]); 5665 5666 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5667 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5668 NewV.getOperand(0), 5669 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5670 DAG); 5671 } 5672 5673 // In case BestHi & BestLo were both -1, which means each quadword has a word 5674 // from each of the four input quadwords, calculate the InOrder bitvector now 5675 // before falling through to the insert/extract cleanup. 5676 if (BestLoQuad == -1 && BestHiQuad == -1) { 5677 NewV = V1; 5678 for (int i = 0; i != 8; ++i) 5679 if (MaskVals[i] < 0 || MaskVals[i] == i) 5680 InOrder.set(i); 5681 } 5682 5683 // The other elements are put in the right place using pextrw and pinsrw. 5684 for (unsigned i = 0; i != 8; ++i) { 5685 if (InOrder[i]) 5686 continue; 5687 int EltIdx = MaskVals[i]; 5688 if (EltIdx < 0) 5689 continue; 5690 SDValue ExtOp = (EltIdx < 8) 5691 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5692 DAG.getIntPtrConstant(EltIdx)) 5693 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5694 DAG.getIntPtrConstant(EltIdx - 8)); 5695 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5696 DAG.getIntPtrConstant(i)); 5697 } 5698 return NewV; 5699} 5700 5701// v16i8 shuffles - Prefer shuffles in the following order: 5702// 1. [ssse3] 1 x pshufb 5703// 2. [ssse3] 2 x pshufb + 1 x por 5704// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5705static 5706SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5707 SelectionDAG &DAG, 5708 const X86TargetLowering &TLI) { 5709 SDValue V1 = SVOp->getOperand(0); 5710 SDValue V2 = SVOp->getOperand(1); 5711 DebugLoc dl = SVOp->getDebugLoc(); 5712 ArrayRef<int> MaskVals = SVOp->getMask(); 5713 5714 // If we have SSSE3, case 1 is generated when all result bytes come from 5715 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5716 // present, fall back to case 3. 5717 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5718 bool V1Only = true; 5719 bool V2Only = true; 5720 for (unsigned i = 0; i < 16; ++i) { 5721 int EltIdx = MaskVals[i]; 5722 if (EltIdx < 0) 5723 continue; 5724 if (EltIdx < 16) 5725 V2Only = false; 5726 else 5727 V1Only = false; 5728 } 5729 5730 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5731 if (TLI.getSubtarget()->hasSSSE3()) { 5732 SmallVector<SDValue,16> pshufbMask; 5733 5734 // If all result elements are from one input vector, then only translate 5735 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5736 // 5737 // Otherwise, we have elements from both input vectors, and must zero out 5738 // elements that come from V2 in the first mask, and V1 in the second mask 5739 // so that we can OR them together. 5740 bool TwoInputs = !(V1Only || V2Only); 5741 for (unsigned i = 0; i != 16; ++i) { 5742 int EltIdx = MaskVals[i]; 5743 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5744 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5745 continue; 5746 } 5747 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5748 } 5749 // If all the elements are from V2, assign it to V1 and return after 5750 // building the first pshufb. 5751 if (V2Only) 5752 V1 = V2; 5753 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5754 DAG.getNode(ISD::BUILD_VECTOR, dl, 5755 MVT::v16i8, &pshufbMask[0], 16)); 5756 if (!TwoInputs) 5757 return V1; 5758 5759 // Calculate the shuffle mask for the second input, shuffle it, and 5760 // OR it with the first shuffled input. 5761 pshufbMask.clear(); 5762 for (unsigned i = 0; i != 16; ++i) { 5763 int EltIdx = MaskVals[i]; 5764 if (EltIdx < 16) { 5765 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5766 continue; 5767 } 5768 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5769 } 5770 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5771 DAG.getNode(ISD::BUILD_VECTOR, dl, 5772 MVT::v16i8, &pshufbMask[0], 16)); 5773 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5774 } 5775 5776 // No SSSE3 - Calculate in place words and then fix all out of place words 5777 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5778 // the 16 different words that comprise the two doublequadword input vectors. 5779 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5780 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5781 SDValue NewV = V2Only ? V2 : V1; 5782 for (int i = 0; i != 8; ++i) { 5783 int Elt0 = MaskVals[i*2]; 5784 int Elt1 = MaskVals[i*2+1]; 5785 5786 // This word of the result is all undef, skip it. 5787 if (Elt0 < 0 && Elt1 < 0) 5788 continue; 5789 5790 // This word of the result is already in the correct place, skip it. 5791 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5792 continue; 5793 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5794 continue; 5795 5796 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5797 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5798 SDValue InsElt; 5799 5800 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5801 // using a single extract together, load it and store it. 5802 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5803 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5804 DAG.getIntPtrConstant(Elt1 / 2)); 5805 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5806 DAG.getIntPtrConstant(i)); 5807 continue; 5808 } 5809 5810 // If Elt1 is defined, extract it from the appropriate source. If the 5811 // source byte is not also odd, shift the extracted word left 8 bits 5812 // otherwise clear the bottom 8 bits if we need to do an or. 5813 if (Elt1 >= 0) { 5814 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5815 DAG.getIntPtrConstant(Elt1 / 2)); 5816 if ((Elt1 & 1) == 0) 5817 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5818 DAG.getConstant(8, 5819 TLI.getShiftAmountTy(InsElt.getValueType()))); 5820 else if (Elt0 >= 0) 5821 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5822 DAG.getConstant(0xFF00, MVT::i16)); 5823 } 5824 // If Elt0 is defined, extract it from the appropriate source. If the 5825 // source byte is not also even, shift the extracted word right 8 bits. If 5826 // Elt1 was also defined, OR the extracted values together before 5827 // inserting them in the result. 5828 if (Elt0 >= 0) { 5829 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5830 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5831 if ((Elt0 & 1) != 0) 5832 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5833 DAG.getConstant(8, 5834 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5835 else if (Elt1 >= 0) 5836 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5837 DAG.getConstant(0x00FF, MVT::i16)); 5838 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5839 : InsElt0; 5840 } 5841 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5842 DAG.getIntPtrConstant(i)); 5843 } 5844 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5845} 5846 5847/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5848/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5849/// done when every pair / quad of shuffle mask elements point to elements in 5850/// the right sequence. e.g. 5851/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5852static 5853SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5854 SelectionDAG &DAG, DebugLoc dl) { 5855 EVT VT = SVOp->getValueType(0); 5856 SDValue V1 = SVOp->getOperand(0); 5857 SDValue V2 = SVOp->getOperand(1); 5858 unsigned NumElems = VT.getVectorNumElements(); 5859 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5860 EVT NewVT; 5861 switch (VT.getSimpleVT().SimpleTy) { 5862 default: assert(false && "Unexpected!"); 5863 case MVT::v4f32: NewVT = MVT::v2f64; break; 5864 case MVT::v4i32: NewVT = MVT::v2i64; break; 5865 case MVT::v8i16: NewVT = MVT::v4i32; break; 5866 case MVT::v16i8: NewVT = MVT::v4i32; break; 5867 } 5868 5869 int Scale = NumElems / NewWidth; 5870 SmallVector<int, 8> MaskVec; 5871 for (unsigned i = 0; i < NumElems; i += Scale) { 5872 int StartIdx = -1; 5873 for (int j = 0; j < Scale; ++j) { 5874 int EltIdx = SVOp->getMaskElt(i+j); 5875 if (EltIdx < 0) 5876 continue; 5877 if (StartIdx == -1) 5878 StartIdx = EltIdx - (EltIdx % Scale); 5879 if (EltIdx != StartIdx + j) 5880 return SDValue(); 5881 } 5882 if (StartIdx == -1) 5883 MaskVec.push_back(-1); 5884 else 5885 MaskVec.push_back(StartIdx / Scale); 5886 } 5887 5888 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5889 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5890 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5891} 5892 5893/// getVZextMovL - Return a zero-extending vector move low node. 5894/// 5895static SDValue getVZextMovL(EVT VT, EVT OpVT, 5896 SDValue SrcOp, SelectionDAG &DAG, 5897 const X86Subtarget *Subtarget, DebugLoc dl) { 5898 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5899 LoadSDNode *LD = NULL; 5900 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5901 LD = dyn_cast<LoadSDNode>(SrcOp); 5902 if (!LD) { 5903 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5904 // instead. 5905 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5906 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5907 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5908 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5909 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5910 // PR2108 5911 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5912 return DAG.getNode(ISD::BITCAST, dl, VT, 5913 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5914 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5915 OpVT, 5916 SrcOp.getOperand(0) 5917 .getOperand(0)))); 5918 } 5919 } 5920 } 5921 5922 return DAG.getNode(ISD::BITCAST, dl, VT, 5923 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5924 DAG.getNode(ISD::BITCAST, dl, 5925 OpVT, SrcOp))); 5926} 5927 5928/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5929/// shuffle node referes to only one lane in the sources. 5930static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5931 EVT VT = SVOp->getValueType(0); 5932 int NumElems = VT.getVectorNumElements(); 5933 int HalfSize = NumElems/2; 5934 ArrayRef<int> M = SVOp->getMask(); 5935 bool MatchA = false, MatchB = false; 5936 5937 for (int l = 0; l < NumElems*2; l += HalfSize) { 5938 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5939 MatchA = true; 5940 break; 5941 } 5942 } 5943 5944 for (int l = 0; l < NumElems*2; l += HalfSize) { 5945 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5946 MatchB = true; 5947 break; 5948 } 5949 } 5950 5951 return MatchA && MatchB; 5952} 5953 5954/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5955/// which could not be matched by any known target speficic shuffle 5956static SDValue 5957LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5958 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5959 // If each half of a vector shuffle node referes to only one lane in the 5960 // source vectors, extract each used 128-bit lane and shuffle them using 5961 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5962 // the work to the legalizer. 5963 DebugLoc dl = SVOp->getDebugLoc(); 5964 EVT VT = SVOp->getValueType(0); 5965 int NumElems = VT.getVectorNumElements(); 5966 int HalfSize = NumElems/2; 5967 5968 // Extract the reference for each half 5969 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5970 int FstVecOpNum = 0, SndVecOpNum = 0; 5971 for (int i = 0; i < HalfSize; ++i) { 5972 int Elt = SVOp->getMaskElt(i); 5973 if (SVOp->getMaskElt(i) < 0) 5974 continue; 5975 FstVecOpNum = Elt/NumElems; 5976 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5977 break; 5978 } 5979 for (int i = HalfSize; i < NumElems; ++i) { 5980 int Elt = SVOp->getMaskElt(i); 5981 if (SVOp->getMaskElt(i) < 0) 5982 continue; 5983 SndVecOpNum = Elt/NumElems; 5984 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5985 break; 5986 } 5987 5988 // Extract the subvectors 5989 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 5990 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 5991 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 5992 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 5993 5994 // Generate 128-bit shuffles 5995 SmallVector<int, 16> MaskV1, MaskV2; 5996 for (int i = 0; i < HalfSize; ++i) { 5997 int Elt = SVOp->getMaskElt(i); 5998 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5999 } 6000 for (int i = HalfSize; i < NumElems; ++i) { 6001 int Elt = SVOp->getMaskElt(i); 6002 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6003 } 6004 6005 EVT NVT = V1.getValueType(); 6006 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 6007 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 6008 6009 // Concatenate the result back 6010 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6011 DAG.getConstant(0, MVT::i32), DAG, dl); 6012 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6013 DAG, dl); 6014 } 6015 6016 return SDValue(); 6017} 6018 6019/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6020/// 4 elements, and match them with several different shuffle types. 6021static SDValue 6022LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6023 SDValue V1 = SVOp->getOperand(0); 6024 SDValue V2 = SVOp->getOperand(1); 6025 DebugLoc dl = SVOp->getDebugLoc(); 6026 EVT VT = SVOp->getValueType(0); 6027 6028 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6029 6030 SmallVector<std::pair<int, int>, 8> Locs; 6031 Locs.resize(4); 6032 SmallVector<int, 8> Mask1(4U, -1); 6033 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6034 6035 unsigned NumHi = 0; 6036 unsigned NumLo = 0; 6037 for (unsigned i = 0; i != 4; ++i) { 6038 int Idx = PermMask[i]; 6039 if (Idx < 0) { 6040 Locs[i] = std::make_pair(-1, -1); 6041 } else { 6042 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6043 if (Idx < 4) { 6044 Locs[i] = std::make_pair(0, NumLo); 6045 Mask1[NumLo] = Idx; 6046 NumLo++; 6047 } else { 6048 Locs[i] = std::make_pair(1, NumHi); 6049 if (2+NumHi < 4) 6050 Mask1[2+NumHi] = Idx; 6051 NumHi++; 6052 } 6053 } 6054 } 6055 6056 if (NumLo <= 2 && NumHi <= 2) { 6057 // If no more than two elements come from either vector. This can be 6058 // implemented with two shuffles. First shuffle gather the elements. 6059 // The second shuffle, which takes the first shuffle as both of its 6060 // vector operands, put the elements into the right order. 6061 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6062 6063 SmallVector<int, 8> Mask2(4U, -1); 6064 6065 for (unsigned i = 0; i != 4; ++i) { 6066 if (Locs[i].first == -1) 6067 continue; 6068 else { 6069 unsigned Idx = (i < 2) ? 0 : 4; 6070 Idx += Locs[i].first * 2 + Locs[i].second; 6071 Mask2[i] = Idx; 6072 } 6073 } 6074 6075 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6076 } else if (NumLo == 3 || NumHi == 3) { 6077 // Otherwise, we must have three elements from one vector, call it X, and 6078 // one element from the other, call it Y. First, use a shufps to build an 6079 // intermediate vector with the one element from Y and the element from X 6080 // that will be in the same half in the final destination (the indexes don't 6081 // matter). Then, use a shufps to build the final vector, taking the half 6082 // containing the element from Y from the intermediate, and the other half 6083 // from X. 6084 if (NumHi == 3) { 6085 // Normalize it so the 3 elements come from V1. 6086 CommuteVectorShuffleMask(PermMask, 4); 6087 std::swap(V1, V2); 6088 } 6089 6090 // Find the element from V2. 6091 unsigned HiIndex; 6092 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6093 int Val = PermMask[HiIndex]; 6094 if (Val < 0) 6095 continue; 6096 if (Val >= 4) 6097 break; 6098 } 6099 6100 Mask1[0] = PermMask[HiIndex]; 6101 Mask1[1] = -1; 6102 Mask1[2] = PermMask[HiIndex^1]; 6103 Mask1[3] = -1; 6104 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6105 6106 if (HiIndex >= 2) { 6107 Mask1[0] = PermMask[0]; 6108 Mask1[1] = PermMask[1]; 6109 Mask1[2] = HiIndex & 1 ? 6 : 4; 6110 Mask1[3] = HiIndex & 1 ? 4 : 6; 6111 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6112 } else { 6113 Mask1[0] = HiIndex & 1 ? 2 : 0; 6114 Mask1[1] = HiIndex & 1 ? 0 : 2; 6115 Mask1[2] = PermMask[2]; 6116 Mask1[3] = PermMask[3]; 6117 if (Mask1[2] >= 0) 6118 Mask1[2] += 4; 6119 if (Mask1[3] >= 0) 6120 Mask1[3] += 4; 6121 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6122 } 6123 } 6124 6125 // Break it into (shuffle shuffle_hi, shuffle_lo). 6126 Locs.clear(); 6127 Locs.resize(4); 6128 SmallVector<int,8> LoMask(4U, -1); 6129 SmallVector<int,8> HiMask(4U, -1); 6130 6131 SmallVector<int,8> *MaskPtr = &LoMask; 6132 unsigned MaskIdx = 0; 6133 unsigned LoIdx = 0; 6134 unsigned HiIdx = 2; 6135 for (unsigned i = 0; i != 4; ++i) { 6136 if (i == 2) { 6137 MaskPtr = &HiMask; 6138 MaskIdx = 1; 6139 LoIdx = 0; 6140 HiIdx = 2; 6141 } 6142 int Idx = PermMask[i]; 6143 if (Idx < 0) { 6144 Locs[i] = std::make_pair(-1, -1); 6145 } else if (Idx < 4) { 6146 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6147 (*MaskPtr)[LoIdx] = Idx; 6148 LoIdx++; 6149 } else { 6150 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6151 (*MaskPtr)[HiIdx] = Idx; 6152 HiIdx++; 6153 } 6154 } 6155 6156 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6157 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6158 SmallVector<int, 8> MaskOps; 6159 for (unsigned i = 0; i != 4; ++i) { 6160 if (Locs[i].first == -1) { 6161 MaskOps.push_back(-1); 6162 } else { 6163 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6164 MaskOps.push_back(Idx); 6165 } 6166 } 6167 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6168} 6169 6170static bool MayFoldVectorLoad(SDValue V) { 6171 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6172 V = V.getOperand(0); 6173 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6174 V = V.getOperand(0); 6175 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6176 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6177 // BUILD_VECTOR (load), undef 6178 V = V.getOperand(0); 6179 if (MayFoldLoad(V)) 6180 return true; 6181 return false; 6182} 6183 6184// FIXME: the version above should always be used. Since there's 6185// a bug where several vector shuffles can't be folded because the 6186// DAG is not updated during lowering and a node claims to have two 6187// uses while it only has one, use this version, and let isel match 6188// another instruction if the load really happens to have more than 6189// one use. Remove this version after this bug get fixed. 6190// rdar://8434668, PR8156 6191static bool RelaxedMayFoldVectorLoad(SDValue V) { 6192 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6193 V = V.getOperand(0); 6194 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6195 V = V.getOperand(0); 6196 if (ISD::isNormalLoad(V.getNode())) 6197 return true; 6198 return false; 6199} 6200 6201/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6202/// a vector extract, and if both can be later optimized into a single load. 6203/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6204/// here because otherwise a target specific shuffle node is going to be 6205/// emitted for this shuffle, and the optimization not done. 6206/// FIXME: This is probably not the best approach, but fix the problem 6207/// until the right path is decided. 6208static 6209bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6210 const TargetLowering &TLI) { 6211 EVT VT = V.getValueType(); 6212 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6213 6214 // Be sure that the vector shuffle is present in a pattern like this: 6215 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6216 if (!V.hasOneUse()) 6217 return false; 6218 6219 SDNode *N = *V.getNode()->use_begin(); 6220 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6221 return false; 6222 6223 SDValue EltNo = N->getOperand(1); 6224 if (!isa<ConstantSDNode>(EltNo)) 6225 return false; 6226 6227 // If the bit convert changed the number of elements, it is unsafe 6228 // to examine the mask. 6229 bool HasShuffleIntoBitcast = false; 6230 if (V.getOpcode() == ISD::BITCAST) { 6231 EVT SrcVT = V.getOperand(0).getValueType(); 6232 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6233 return false; 6234 V = V.getOperand(0); 6235 HasShuffleIntoBitcast = true; 6236 } 6237 6238 // Select the input vector, guarding against out of range extract vector. 6239 unsigned NumElems = VT.getVectorNumElements(); 6240 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6241 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6242 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6243 6244 // If we are accessing the upper part of a YMM register 6245 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of 6246 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point 6247 // because the legalization of N did not happen yet. 6248 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256) 6249 return false; 6250 6251 // Skip one more bit_convert if necessary 6252 if (V.getOpcode() == ISD::BITCAST) 6253 V = V.getOperand(0); 6254 6255 if (!ISD::isNormalLoad(V.getNode())) 6256 return false; 6257 6258 // Is the original load suitable? 6259 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6260 6261 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6262 return false; 6263 6264 if (!HasShuffleIntoBitcast) 6265 return true; 6266 6267 // If there's a bitcast before the shuffle, check if the load type and 6268 // alignment is valid. 6269 unsigned Align = LN0->getAlignment(); 6270 unsigned NewAlign = 6271 TLI.getTargetData()->getABITypeAlignment( 6272 VT.getTypeForEVT(*DAG.getContext())); 6273 6274 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6275 return false; 6276 6277 return true; 6278} 6279 6280static 6281SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6282 EVT VT = Op.getValueType(); 6283 6284 // Canonizalize to v2f64. 6285 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6286 return DAG.getNode(ISD::BITCAST, dl, VT, 6287 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6288 V1, DAG)); 6289} 6290 6291static 6292SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6293 bool HasSSE2) { 6294 SDValue V1 = Op.getOperand(0); 6295 SDValue V2 = Op.getOperand(1); 6296 EVT VT = Op.getValueType(); 6297 6298 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6299 6300 if (HasSSE2 && VT == MVT::v2f64) 6301 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6302 6303 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6304 return DAG.getNode(ISD::BITCAST, dl, VT, 6305 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6306 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6307 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6308} 6309 6310static 6311SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6312 SDValue V1 = Op.getOperand(0); 6313 SDValue V2 = Op.getOperand(1); 6314 EVT VT = Op.getValueType(); 6315 6316 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6317 "unsupported shuffle type"); 6318 6319 if (V2.getOpcode() == ISD::UNDEF) 6320 V2 = V1; 6321 6322 // v4i32 or v4f32 6323 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6324} 6325 6326static 6327SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6328 SDValue V1 = Op.getOperand(0); 6329 SDValue V2 = Op.getOperand(1); 6330 EVT VT = Op.getValueType(); 6331 unsigned NumElems = VT.getVectorNumElements(); 6332 6333 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6334 // operand of these instructions is only memory, so check if there's a 6335 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6336 // same masks. 6337 bool CanFoldLoad = false; 6338 6339 // Trivial case, when V2 comes from a load. 6340 if (MayFoldVectorLoad(V2)) 6341 CanFoldLoad = true; 6342 6343 // When V1 is a load, it can be folded later into a store in isel, example: 6344 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6345 // turns into: 6346 // (MOVLPSmr addr:$src1, VR128:$src2) 6347 // So, recognize this potential and also use MOVLPS or MOVLPD 6348 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6349 CanFoldLoad = true; 6350 6351 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6352 if (CanFoldLoad) { 6353 if (HasSSE2 && NumElems == 2) 6354 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6355 6356 if (NumElems == 4) 6357 // If we don't care about the second element, procede to use movss. 6358 if (SVOp->getMaskElt(1) != -1) 6359 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6360 } 6361 6362 // movl and movlp will both match v2i64, but v2i64 is never matched by 6363 // movl earlier because we make it strict to avoid messing with the movlp load 6364 // folding logic (see the code above getMOVLP call). Match it here then, 6365 // this is horrible, but will stay like this until we move all shuffle 6366 // matching to x86 specific nodes. Note that for the 1st condition all 6367 // types are matched with movsd. 6368 if (HasSSE2) { 6369 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6370 // as to remove this logic from here, as much as possible 6371 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6372 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6373 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6374 } 6375 6376 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6377 6378 // Invert the operand order and use SHUFPS to match it. 6379 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6380 X86::getShuffleSHUFImmediate(SVOp), DAG); 6381} 6382 6383static 6384SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6385 const TargetLowering &TLI, 6386 const X86Subtarget *Subtarget) { 6387 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6388 EVT VT = Op.getValueType(); 6389 DebugLoc dl = Op.getDebugLoc(); 6390 SDValue V1 = Op.getOperand(0); 6391 SDValue V2 = Op.getOperand(1); 6392 6393 if (isZeroShuffle(SVOp)) 6394 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), 6395 DAG, dl); 6396 6397 // Handle splat operations 6398 if (SVOp->isSplat()) { 6399 unsigned NumElem = VT.getVectorNumElements(); 6400 int Size = VT.getSizeInBits(); 6401 // Special case, this is the only place now where it's allowed to return 6402 // a vector_shuffle operation without using a target specific node, because 6403 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6404 // this be moved to DAGCombine instead? 6405 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6406 return Op; 6407 6408 // Use vbroadcast whenever the splat comes from a foldable load 6409 SDValue LD = isVectorBroadcast(Op, Subtarget); 6410 if (LD.getNode()) 6411 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6412 6413 // Handle splats by matching through known shuffle masks 6414 if ((Size == 128 && NumElem <= 4) || 6415 (Size == 256 && NumElem < 8)) 6416 return SDValue(); 6417 6418 // All remaning splats are promoted to target supported vector shuffles. 6419 return PromoteSplat(SVOp, DAG); 6420 } 6421 6422 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6423 // do it! 6424 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6425 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6426 if (NewOp.getNode()) 6427 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6428 } else if ((VT == MVT::v4i32 || 6429 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6430 // FIXME: Figure out a cleaner way to do this. 6431 // Try to make use of movq to zero out the top part. 6432 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6433 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6434 if (NewOp.getNode()) { 6435 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6436 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6437 DAG, Subtarget, dl); 6438 } 6439 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6440 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6441 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6442 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6443 DAG, Subtarget, dl); 6444 } 6445 } 6446 return SDValue(); 6447} 6448 6449SDValue 6450X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6452 SDValue V1 = Op.getOperand(0); 6453 SDValue V2 = Op.getOperand(1); 6454 EVT VT = Op.getValueType(); 6455 DebugLoc dl = Op.getDebugLoc(); 6456 unsigned NumElems = VT.getVectorNumElements(); 6457 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6458 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6459 bool V1IsSplat = false; 6460 bool V2IsSplat = false; 6461 bool HasSSE2 = Subtarget->hasSSE2(); 6462 bool HasAVX = Subtarget->hasAVX(); 6463 bool HasAVX2 = Subtarget->hasAVX2(); 6464 MachineFunction &MF = DAG.getMachineFunction(); 6465 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6466 6467 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6468 6469 if (V1IsUndef && V2IsUndef) 6470 return DAG.getUNDEF(VT); 6471 6472 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6473 6474 // Vector shuffle lowering takes 3 steps: 6475 // 6476 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6477 // narrowing and commutation of operands should be handled. 6478 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6479 // shuffle nodes. 6480 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6481 // so the shuffle can be broken into other shuffles and the legalizer can 6482 // try the lowering again. 6483 // 6484 // The general idea is that no vector_shuffle operation should be left to 6485 // be matched during isel, all of them must be converted to a target specific 6486 // node here. 6487 6488 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6489 // narrowing and commutation of operands should be handled. The actual code 6490 // doesn't include all of those, work in progress... 6491 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6492 if (NewOp.getNode()) 6493 return NewOp; 6494 6495 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6496 // unpckh_undef). Only use pshufd if speed is more important than size. 6497 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2)) 6498 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6499 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2)) 6500 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6501 6502 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() && 6503 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6504 return getMOVDDup(Op, dl, V1, DAG); 6505 6506 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6507 return getMOVHighToLow(Op, dl, DAG); 6508 6509 // Use to match splats 6510 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6511 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6512 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6513 6514 if (X86::isPSHUFDMask(SVOp)) { 6515 // The actual implementation will match the mask in the if above and then 6516 // during isel it can match several different instructions, not only pshufd 6517 // as its name says, sad but true, emulate the behavior for now... 6518 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6519 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6520 6521 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6522 6523 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6524 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6525 6526 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6527 TargetMask, DAG); 6528 } 6529 6530 // Check if this can be converted into a logical shift. 6531 bool isLeft = false; 6532 unsigned ShAmt = 0; 6533 SDValue ShVal; 6534 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6535 if (isShift && ShVal.hasOneUse()) { 6536 // If the shifted value has multiple uses, it may be cheaper to use 6537 // v_set0 + movlhps or movhlps, etc. 6538 EVT EltVT = VT.getVectorElementType(); 6539 ShAmt *= EltVT.getSizeInBits(); 6540 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6541 } 6542 6543 if (X86::isMOVLMask(SVOp)) { 6544 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6545 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6546 if (!X86::isMOVLPMask(SVOp)) { 6547 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6548 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6549 6550 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6551 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6552 } 6553 } 6554 6555 // FIXME: fold these into legal mask. 6556 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6557 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6558 6559 if (X86::isMOVHLPSMask(SVOp)) 6560 return getMOVHighToLow(Op, dl, DAG); 6561 6562 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6563 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6564 6565 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6566 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6567 6568 if (X86::isMOVLPMask(SVOp)) 6569 return getMOVLP(Op, dl, DAG, HasSSE2); 6570 6571 if (ShouldXformToMOVHLPS(SVOp) || 6572 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6573 return CommuteVectorShuffle(SVOp, DAG); 6574 6575 if (isShift) { 6576 // No better options. Use a vshl / vsrl. 6577 EVT EltVT = VT.getVectorElementType(); 6578 ShAmt *= EltVT.getSizeInBits(); 6579 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6580 } 6581 6582 bool Commuted = false; 6583 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6584 // 1,1,1,1 -> v8i16 though. 6585 V1IsSplat = isSplatVector(V1.getNode()); 6586 V2IsSplat = isSplatVector(V2.getNode()); 6587 6588 // Canonicalize the splat or undef, if present, to be on the RHS. 6589 if (V1IsSplat && !V2IsSplat) { 6590 Op = CommuteVectorShuffle(SVOp, DAG); 6591 SVOp = cast<ShuffleVectorSDNode>(Op); 6592 V1 = SVOp->getOperand(0); 6593 V2 = SVOp->getOperand(1); 6594 std::swap(V1IsSplat, V2IsSplat); 6595 Commuted = true; 6596 } 6597 6598 ArrayRef<int> M = SVOp->getMask(); 6599 6600 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6601 // Shuffling low element of v1 into undef, just return v1. 6602 if (V2IsUndef) 6603 return V1; 6604 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6605 // the instruction selector will not match, so get a canonical MOVL with 6606 // swapped operands to undo the commute. 6607 return getMOVL(DAG, dl, VT, V2, V1); 6608 } 6609 6610 if (isUNPCKLMask(M, VT, HasAVX2)) 6611 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6612 6613 if (isUNPCKHMask(M, VT, HasAVX2)) 6614 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6615 6616 if (V2IsSplat) { 6617 // Normalize mask so all entries that point to V2 points to its first 6618 // element then try to match unpck{h|l} again. If match, return a 6619 // new vector_shuffle with the corrected mask. 6620 SDValue NewMask = NormalizeMask(SVOp, DAG); 6621 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6622 if (NSVOp != SVOp) { 6623 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6624 return NewMask; 6625 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6626 return NewMask; 6627 } 6628 } 6629 } 6630 6631 if (Commuted) { 6632 // Commute is back and try unpck* again. 6633 // FIXME: this seems wrong. 6634 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6635 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6636 6637 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6638 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); 6639 6640 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6641 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); 6642 } 6643 6644 // Normalize the node to match x86 shuffle ops if needed 6645 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) || 6646 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true))) 6647 return CommuteVectorShuffle(SVOp, DAG); 6648 6649 // The checks below are all present in isShuffleMaskLegal, but they are 6650 // inlined here right now to enable us to directly emit target specific 6651 // nodes, and remove one by one until they don't return Op anymore. 6652 6653 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) 6654 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6655 getShufflePALIGNRImmediate(SVOp), 6656 DAG); 6657 6658 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6659 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6660 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6661 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6662 } 6663 6664 if (isPSHUFHWMask(M, VT)) 6665 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6666 X86::getShufflePSHUFHWImmediate(SVOp), 6667 DAG); 6668 6669 if (isPSHUFLWMask(M, VT)) 6670 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6671 X86::getShufflePSHUFLWImmediate(SVOp), 6672 DAG); 6673 6674 if (isSHUFPMask(M, VT)) 6675 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6676 X86::getShuffleSHUFImmediate(SVOp), DAG); 6677 6678 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6679 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6680 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6681 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6682 6683 //===--------------------------------------------------------------------===// 6684 // Generate target specific nodes for 128 or 256-bit shuffles only 6685 // supported in the AVX instruction set. 6686 // 6687 6688 // Handle VMOVDDUPY permutations 6689 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6690 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6691 6692 // Handle VPERMILPS/D* permutations 6693 if (isVPERMILPMask(M, VT, HasAVX)) 6694 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6695 getShuffleVPERMILPImmediate(SVOp), DAG); 6696 6697 // Handle VPERM2F128/VPERM2I128 permutations 6698 if (isVPERM2X128Mask(M, VT, HasAVX)) 6699 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6700 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6701 6702 // Handle VSHUFPS/DY permutations 6703 if (isVSHUFPYMask(M, VT, HasAVX)) 6704 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6705 getShuffleVSHUFPYImmediate(SVOp), DAG); 6706 6707 //===--------------------------------------------------------------------===// 6708 // Since no target specific shuffle was selected for this generic one, 6709 // lower it into other known shuffles. FIXME: this isn't true yet, but 6710 // this is the plan. 6711 // 6712 6713 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6714 if (VT == MVT::v8i16) { 6715 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6716 if (NewOp.getNode()) 6717 return NewOp; 6718 } 6719 6720 if (VT == MVT::v16i8) { 6721 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6722 if (NewOp.getNode()) 6723 return NewOp; 6724 } 6725 6726 // Handle all 128-bit wide vectors with 4 elements, and match them with 6727 // several different shuffle types. 6728 if (NumElems == 4 && VT.getSizeInBits() == 128) 6729 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6730 6731 // Handle general 256-bit shuffles 6732 if (VT.is256BitVector()) 6733 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6734 6735 return SDValue(); 6736} 6737 6738SDValue 6739X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6740 SelectionDAG &DAG) const { 6741 EVT VT = Op.getValueType(); 6742 DebugLoc dl = Op.getDebugLoc(); 6743 6744 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6745 return SDValue(); 6746 6747 if (VT.getSizeInBits() == 8) { 6748 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6749 Op.getOperand(0), Op.getOperand(1)); 6750 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6751 DAG.getValueType(VT)); 6752 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6753 } else if (VT.getSizeInBits() == 16) { 6754 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6755 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6756 if (Idx == 0) 6757 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6758 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6759 DAG.getNode(ISD::BITCAST, dl, 6760 MVT::v4i32, 6761 Op.getOperand(0)), 6762 Op.getOperand(1))); 6763 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6764 Op.getOperand(0), Op.getOperand(1)); 6765 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6766 DAG.getValueType(VT)); 6767 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6768 } else if (VT == MVT::f32) { 6769 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6770 // the result back to FR32 register. It's only worth matching if the 6771 // result has a single use which is a store or a bitcast to i32. And in 6772 // the case of a store, it's not worth it if the index is a constant 0, 6773 // because a MOVSSmr can be used instead, which is smaller and faster. 6774 if (!Op.hasOneUse()) 6775 return SDValue(); 6776 SDNode *User = *Op.getNode()->use_begin(); 6777 if ((User->getOpcode() != ISD::STORE || 6778 (isa<ConstantSDNode>(Op.getOperand(1)) && 6779 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6780 (User->getOpcode() != ISD::BITCAST || 6781 User->getValueType(0) != MVT::i32)) 6782 return SDValue(); 6783 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6784 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6785 Op.getOperand(0)), 6786 Op.getOperand(1)); 6787 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6788 } else if (VT == MVT::i32 || VT == MVT::i64) { 6789 // ExtractPS/pextrq works with constant index. 6790 if (isa<ConstantSDNode>(Op.getOperand(1))) 6791 return Op; 6792 } 6793 return SDValue(); 6794} 6795 6796 6797SDValue 6798X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6799 SelectionDAG &DAG) const { 6800 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6801 return SDValue(); 6802 6803 SDValue Vec = Op.getOperand(0); 6804 EVT VecVT = Vec.getValueType(); 6805 6806 // If this is a 256-bit vector result, first extract the 128-bit vector and 6807 // then extract the element from the 128-bit vector. 6808 if (VecVT.getSizeInBits() == 256) { 6809 DebugLoc dl = Op.getNode()->getDebugLoc(); 6810 unsigned NumElems = VecVT.getVectorNumElements(); 6811 SDValue Idx = Op.getOperand(1); 6812 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6813 6814 // Get the 128-bit vector. 6815 bool Upper = IdxVal >= NumElems/2; 6816 Vec = Extract128BitVector(Vec, 6817 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6818 6819 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6820 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6821 } 6822 6823 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6824 6825 if (Subtarget->hasSSE41()) { 6826 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6827 if (Res.getNode()) 6828 return Res; 6829 } 6830 6831 EVT VT = Op.getValueType(); 6832 DebugLoc dl = Op.getDebugLoc(); 6833 // TODO: handle v16i8. 6834 if (VT.getSizeInBits() == 16) { 6835 SDValue Vec = Op.getOperand(0); 6836 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6837 if (Idx == 0) 6838 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6839 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6840 DAG.getNode(ISD::BITCAST, dl, 6841 MVT::v4i32, Vec), 6842 Op.getOperand(1))); 6843 // Transform it so it match pextrw which produces a 32-bit result. 6844 EVT EltVT = MVT::i32; 6845 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6846 Op.getOperand(0), Op.getOperand(1)); 6847 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6848 DAG.getValueType(VT)); 6849 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6850 } else if (VT.getSizeInBits() == 32) { 6851 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6852 if (Idx == 0) 6853 return Op; 6854 6855 // SHUFPS the element to the lowest double word, then movss. 6856 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6857 EVT VVT = Op.getOperand(0).getValueType(); 6858 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6859 DAG.getUNDEF(VVT), Mask); 6860 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6861 DAG.getIntPtrConstant(0)); 6862 } else if (VT.getSizeInBits() == 64) { 6863 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6864 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6865 // to match extract_elt for f64. 6866 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6867 if (Idx == 0) 6868 return Op; 6869 6870 // UNPCKHPD the element to the lowest double word, then movsd. 6871 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6872 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6873 int Mask[2] = { 1, -1 }; 6874 EVT VVT = Op.getOperand(0).getValueType(); 6875 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6876 DAG.getUNDEF(VVT), Mask); 6877 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6878 DAG.getIntPtrConstant(0)); 6879 } 6880 6881 return SDValue(); 6882} 6883 6884SDValue 6885X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6886 SelectionDAG &DAG) const { 6887 EVT VT = Op.getValueType(); 6888 EVT EltVT = VT.getVectorElementType(); 6889 DebugLoc dl = Op.getDebugLoc(); 6890 6891 SDValue N0 = Op.getOperand(0); 6892 SDValue N1 = Op.getOperand(1); 6893 SDValue N2 = Op.getOperand(2); 6894 6895 if (VT.getSizeInBits() == 256) 6896 return SDValue(); 6897 6898 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6899 isa<ConstantSDNode>(N2)) { 6900 unsigned Opc; 6901 if (VT == MVT::v8i16) 6902 Opc = X86ISD::PINSRW; 6903 else if (VT == MVT::v16i8) 6904 Opc = X86ISD::PINSRB; 6905 else 6906 Opc = X86ISD::PINSRB; 6907 6908 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6909 // argument. 6910 if (N1.getValueType() != MVT::i32) 6911 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6912 if (N2.getValueType() != MVT::i32) 6913 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6914 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6915 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6916 // Bits [7:6] of the constant are the source select. This will always be 6917 // zero here. The DAG Combiner may combine an extract_elt index into these 6918 // bits. For example (insert (extract, 3), 2) could be matched by putting 6919 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6920 // Bits [5:4] of the constant are the destination select. This is the 6921 // value of the incoming immediate. 6922 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6923 // combine either bitwise AND or insert of float 0.0 to set these bits. 6924 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6925 // Create this as a scalar to vector.. 6926 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6927 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6928 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6929 isa<ConstantSDNode>(N2)) { 6930 // PINSR* works with constant index. 6931 return Op; 6932 } 6933 return SDValue(); 6934} 6935 6936SDValue 6937X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6938 EVT VT = Op.getValueType(); 6939 EVT EltVT = VT.getVectorElementType(); 6940 6941 DebugLoc dl = Op.getDebugLoc(); 6942 SDValue N0 = Op.getOperand(0); 6943 SDValue N1 = Op.getOperand(1); 6944 SDValue N2 = Op.getOperand(2); 6945 6946 // If this is a 256-bit vector result, first extract the 128-bit vector, 6947 // insert the element into the extracted half and then place it back. 6948 if (VT.getSizeInBits() == 256) { 6949 if (!isa<ConstantSDNode>(N2)) 6950 return SDValue(); 6951 6952 // Get the desired 128-bit vector half. 6953 unsigned NumElems = VT.getVectorNumElements(); 6954 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6955 bool Upper = IdxVal >= NumElems/2; 6956 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6957 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6958 6959 // Insert the element into the desired half. 6960 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6961 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6962 6963 // Insert the changed part back to the 256-bit vector 6964 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6965 } 6966 6967 if (Subtarget->hasSSE41()) 6968 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6969 6970 if (EltVT == MVT::i8) 6971 return SDValue(); 6972 6973 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6974 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6975 // as its second argument. 6976 if (N1.getValueType() != MVT::i32) 6977 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6978 if (N2.getValueType() != MVT::i32) 6979 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6980 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6981 } 6982 return SDValue(); 6983} 6984 6985SDValue 6986X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6987 LLVMContext *Context = DAG.getContext(); 6988 DebugLoc dl = Op.getDebugLoc(); 6989 EVT OpVT = Op.getValueType(); 6990 6991 // If this is a 256-bit vector result, first insert into a 128-bit 6992 // vector and then insert into the 256-bit vector. 6993 if (OpVT.getSizeInBits() > 128) { 6994 // Insert into a 128-bit vector. 6995 EVT VT128 = EVT::getVectorVT(*Context, 6996 OpVT.getVectorElementType(), 6997 OpVT.getVectorNumElements() / 2); 6998 6999 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7000 7001 // Insert the 128-bit vector. 7002 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7003 DAG.getConstant(0, MVT::i32), 7004 DAG, dl); 7005 } 7006 7007 if (Op.getValueType() == MVT::v1i64 && 7008 Op.getOperand(0).getValueType() == MVT::i64) 7009 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7010 7011 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7012 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7013 "Expected an SSE type!"); 7014 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7015 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7016} 7017 7018// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7019// a simple subregister reference or explicit instructions to grab 7020// upper bits of a vector. 7021SDValue 7022X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7023 if (Subtarget->hasAVX()) { 7024 DebugLoc dl = Op.getNode()->getDebugLoc(); 7025 SDValue Vec = Op.getNode()->getOperand(0); 7026 SDValue Idx = Op.getNode()->getOperand(1); 7027 7028 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7029 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7030 return Extract128BitVector(Vec, Idx, DAG, dl); 7031 } 7032 } 7033 return SDValue(); 7034} 7035 7036// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7037// simple superregister reference or explicit instructions to insert 7038// the upper bits of a vector. 7039SDValue 7040X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7041 if (Subtarget->hasAVX()) { 7042 DebugLoc dl = Op.getNode()->getDebugLoc(); 7043 SDValue Vec = Op.getNode()->getOperand(0); 7044 SDValue SubVec = Op.getNode()->getOperand(1); 7045 SDValue Idx = Op.getNode()->getOperand(2); 7046 7047 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7048 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7049 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7050 } 7051 } 7052 return SDValue(); 7053} 7054 7055// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7056// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7057// one of the above mentioned nodes. It has to be wrapped because otherwise 7058// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7059// be used to form addressing mode. These wrapped nodes will be selected 7060// into MOV32ri. 7061SDValue 7062X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7063 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7064 7065 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7066 // global base reg. 7067 unsigned char OpFlag = 0; 7068 unsigned WrapperKind = X86ISD::Wrapper; 7069 CodeModel::Model M = getTargetMachine().getCodeModel(); 7070 7071 if (Subtarget->isPICStyleRIPRel() && 7072 (M == CodeModel::Small || M == CodeModel::Kernel)) 7073 WrapperKind = X86ISD::WrapperRIP; 7074 else if (Subtarget->isPICStyleGOT()) 7075 OpFlag = X86II::MO_GOTOFF; 7076 else if (Subtarget->isPICStyleStubPIC()) 7077 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7078 7079 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7080 CP->getAlignment(), 7081 CP->getOffset(), OpFlag); 7082 DebugLoc DL = CP->getDebugLoc(); 7083 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7084 // With PIC, the address is actually $g + Offset. 7085 if (OpFlag) { 7086 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7087 DAG.getNode(X86ISD::GlobalBaseReg, 7088 DebugLoc(), getPointerTy()), 7089 Result); 7090 } 7091 7092 return Result; 7093} 7094 7095SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7096 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7097 7098 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7099 // global base reg. 7100 unsigned char OpFlag = 0; 7101 unsigned WrapperKind = X86ISD::Wrapper; 7102 CodeModel::Model M = getTargetMachine().getCodeModel(); 7103 7104 if (Subtarget->isPICStyleRIPRel() && 7105 (M == CodeModel::Small || M == CodeModel::Kernel)) 7106 WrapperKind = X86ISD::WrapperRIP; 7107 else if (Subtarget->isPICStyleGOT()) 7108 OpFlag = X86II::MO_GOTOFF; 7109 else if (Subtarget->isPICStyleStubPIC()) 7110 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7111 7112 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7113 OpFlag); 7114 DebugLoc DL = JT->getDebugLoc(); 7115 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7116 7117 // With PIC, the address is actually $g + Offset. 7118 if (OpFlag) 7119 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7120 DAG.getNode(X86ISD::GlobalBaseReg, 7121 DebugLoc(), getPointerTy()), 7122 Result); 7123 7124 return Result; 7125} 7126 7127SDValue 7128X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7129 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7130 7131 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7132 // global base reg. 7133 unsigned char OpFlag = 0; 7134 unsigned WrapperKind = X86ISD::Wrapper; 7135 CodeModel::Model M = getTargetMachine().getCodeModel(); 7136 7137 if (Subtarget->isPICStyleRIPRel() && 7138 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7139 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7140 OpFlag = X86II::MO_GOTPCREL; 7141 WrapperKind = X86ISD::WrapperRIP; 7142 } else if (Subtarget->isPICStyleGOT()) { 7143 OpFlag = X86II::MO_GOT; 7144 } else if (Subtarget->isPICStyleStubPIC()) { 7145 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7146 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7147 OpFlag = X86II::MO_DARWIN_NONLAZY; 7148 } 7149 7150 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7151 7152 DebugLoc DL = Op.getDebugLoc(); 7153 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7154 7155 7156 // With PIC, the address is actually $g + Offset. 7157 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7158 !Subtarget->is64Bit()) { 7159 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7160 DAG.getNode(X86ISD::GlobalBaseReg, 7161 DebugLoc(), getPointerTy()), 7162 Result); 7163 } 7164 7165 // For symbols that require a load from a stub to get the address, emit the 7166 // load. 7167 if (isGlobalStubReference(OpFlag)) 7168 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7169 MachinePointerInfo::getGOT(), false, false, false, 0); 7170 7171 return Result; 7172} 7173 7174SDValue 7175X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7176 // Create the TargetBlockAddressAddress node. 7177 unsigned char OpFlags = 7178 Subtarget->ClassifyBlockAddressReference(); 7179 CodeModel::Model M = getTargetMachine().getCodeModel(); 7180 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7181 DebugLoc dl = Op.getDebugLoc(); 7182 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7183 /*isTarget=*/true, OpFlags); 7184 7185 if (Subtarget->isPICStyleRIPRel() && 7186 (M == CodeModel::Small || M == CodeModel::Kernel)) 7187 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7188 else 7189 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7190 7191 // With PIC, the address is actually $g + Offset. 7192 if (isGlobalRelativeToPICBase(OpFlags)) { 7193 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7194 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7195 Result); 7196 } 7197 7198 return Result; 7199} 7200 7201SDValue 7202X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7203 int64_t Offset, 7204 SelectionDAG &DAG) const { 7205 // Create the TargetGlobalAddress node, folding in the constant 7206 // offset if it is legal. 7207 unsigned char OpFlags = 7208 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7209 CodeModel::Model M = getTargetMachine().getCodeModel(); 7210 SDValue Result; 7211 if (OpFlags == X86II::MO_NO_FLAG && 7212 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7213 // A direct static reference to a global. 7214 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7215 Offset = 0; 7216 } else { 7217 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7218 } 7219 7220 if (Subtarget->isPICStyleRIPRel() && 7221 (M == CodeModel::Small || M == CodeModel::Kernel)) 7222 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7223 else 7224 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7225 7226 // With PIC, the address is actually $g + Offset. 7227 if (isGlobalRelativeToPICBase(OpFlags)) { 7228 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7229 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7230 Result); 7231 } 7232 7233 // For globals that require a load from a stub to get the address, emit the 7234 // load. 7235 if (isGlobalStubReference(OpFlags)) 7236 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7237 MachinePointerInfo::getGOT(), false, false, false, 0); 7238 7239 // If there was a non-zero offset that we didn't fold, create an explicit 7240 // addition for it. 7241 if (Offset != 0) 7242 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7243 DAG.getConstant(Offset, getPointerTy())); 7244 7245 return Result; 7246} 7247 7248SDValue 7249X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7250 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7251 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7252 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7253} 7254 7255static SDValue 7256GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7257 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7258 unsigned char OperandFlags) { 7259 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7260 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7261 DebugLoc dl = GA->getDebugLoc(); 7262 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7263 GA->getValueType(0), 7264 GA->getOffset(), 7265 OperandFlags); 7266 if (InFlag) { 7267 SDValue Ops[] = { Chain, TGA, *InFlag }; 7268 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7269 } else { 7270 SDValue Ops[] = { Chain, TGA }; 7271 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7272 } 7273 7274 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7275 MFI->setAdjustsStack(true); 7276 7277 SDValue Flag = Chain.getValue(1); 7278 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7279} 7280 7281// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7282static SDValue 7283LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7284 const EVT PtrVT) { 7285 SDValue InFlag; 7286 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7287 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7288 DAG.getNode(X86ISD::GlobalBaseReg, 7289 DebugLoc(), PtrVT), InFlag); 7290 InFlag = Chain.getValue(1); 7291 7292 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7293} 7294 7295// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7296static SDValue 7297LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7298 const EVT PtrVT) { 7299 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7300 X86::RAX, X86II::MO_TLSGD); 7301} 7302 7303// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7304// "local exec" model. 7305static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7306 const EVT PtrVT, TLSModel::Model model, 7307 bool is64Bit) { 7308 DebugLoc dl = GA->getDebugLoc(); 7309 7310 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7311 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7312 is64Bit ? 257 : 256)); 7313 7314 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7315 DAG.getIntPtrConstant(0), 7316 MachinePointerInfo(Ptr), 7317 false, false, false, 0); 7318 7319 unsigned char OperandFlags = 0; 7320 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7321 // initialexec. 7322 unsigned WrapperKind = X86ISD::Wrapper; 7323 if (model == TLSModel::LocalExec) { 7324 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7325 } else if (is64Bit) { 7326 assert(model == TLSModel::InitialExec); 7327 OperandFlags = X86II::MO_GOTTPOFF; 7328 WrapperKind = X86ISD::WrapperRIP; 7329 } else { 7330 assert(model == TLSModel::InitialExec); 7331 OperandFlags = X86II::MO_INDNTPOFF; 7332 } 7333 7334 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7335 // exec) 7336 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7337 GA->getValueType(0), 7338 GA->getOffset(), OperandFlags); 7339 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7340 7341 if (model == TLSModel::InitialExec) 7342 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7343 MachinePointerInfo::getGOT(), false, false, false, 0); 7344 7345 // The address of the thread local variable is the add of the thread 7346 // pointer with the offset of the variable. 7347 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7348} 7349 7350SDValue 7351X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7352 7353 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7354 const GlobalValue *GV = GA->getGlobal(); 7355 7356 if (Subtarget->isTargetELF()) { 7357 // TODO: implement the "local dynamic" model 7358 // TODO: implement the "initial exec"model for pic executables 7359 7360 // If GV is an alias then use the aliasee for determining 7361 // thread-localness. 7362 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7363 GV = GA->resolveAliasedGlobal(false); 7364 7365 TLSModel::Model model 7366 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7367 7368 switch (model) { 7369 case TLSModel::GeneralDynamic: 7370 case TLSModel::LocalDynamic: // not implemented 7371 if (Subtarget->is64Bit()) 7372 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7373 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7374 7375 case TLSModel::InitialExec: 7376 case TLSModel::LocalExec: 7377 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7378 Subtarget->is64Bit()); 7379 } 7380 } else if (Subtarget->isTargetDarwin()) { 7381 // Darwin only has one model of TLS. Lower to that. 7382 unsigned char OpFlag = 0; 7383 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7384 X86ISD::WrapperRIP : X86ISD::Wrapper; 7385 7386 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7387 // global base reg. 7388 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7389 !Subtarget->is64Bit(); 7390 if (PIC32) 7391 OpFlag = X86II::MO_TLVP_PIC_BASE; 7392 else 7393 OpFlag = X86II::MO_TLVP; 7394 DebugLoc DL = Op.getDebugLoc(); 7395 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7396 GA->getValueType(0), 7397 GA->getOffset(), OpFlag); 7398 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7399 7400 // With PIC32, the address is actually $g + Offset. 7401 if (PIC32) 7402 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7403 DAG.getNode(X86ISD::GlobalBaseReg, 7404 DebugLoc(), getPointerTy()), 7405 Offset); 7406 7407 // Lowering the machine isd will make sure everything is in the right 7408 // location. 7409 SDValue Chain = DAG.getEntryNode(); 7410 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7411 SDValue Args[] = { Chain, Offset }; 7412 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7413 7414 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7415 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7416 MFI->setAdjustsStack(true); 7417 7418 // And our return value (tls address) is in the standard call return value 7419 // location. 7420 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7421 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7422 Chain.getValue(1)); 7423 } 7424 7425 assert(false && 7426 "TLS not implemented for this target."); 7427 7428 llvm_unreachable("Unreachable"); 7429 return SDValue(); 7430} 7431 7432 7433/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7434/// and take a 2 x i32 value to shift plus a shift amount. 7435SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7436 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7437 EVT VT = Op.getValueType(); 7438 unsigned VTBits = VT.getSizeInBits(); 7439 DebugLoc dl = Op.getDebugLoc(); 7440 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7441 SDValue ShOpLo = Op.getOperand(0); 7442 SDValue ShOpHi = Op.getOperand(1); 7443 SDValue ShAmt = Op.getOperand(2); 7444 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7445 DAG.getConstant(VTBits - 1, MVT::i8)) 7446 : DAG.getConstant(0, VT); 7447 7448 SDValue Tmp2, Tmp3; 7449 if (Op.getOpcode() == ISD::SHL_PARTS) { 7450 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7451 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7452 } else { 7453 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7454 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7455 } 7456 7457 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7458 DAG.getConstant(VTBits, MVT::i8)); 7459 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7460 AndNode, DAG.getConstant(0, MVT::i8)); 7461 7462 SDValue Hi, Lo; 7463 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7464 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7465 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7466 7467 if (Op.getOpcode() == ISD::SHL_PARTS) { 7468 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7469 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7470 } else { 7471 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7472 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7473 } 7474 7475 SDValue Ops[2] = { Lo, Hi }; 7476 return DAG.getMergeValues(Ops, 2, dl); 7477} 7478 7479SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7480 SelectionDAG &DAG) const { 7481 EVT SrcVT = Op.getOperand(0).getValueType(); 7482 7483 if (SrcVT.isVector()) 7484 return SDValue(); 7485 7486 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7487 "Unknown SINT_TO_FP to lower!"); 7488 7489 // These are really Legal; return the operand so the caller accepts it as 7490 // Legal. 7491 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7492 return Op; 7493 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7494 Subtarget->is64Bit()) { 7495 return Op; 7496 } 7497 7498 DebugLoc dl = Op.getDebugLoc(); 7499 unsigned Size = SrcVT.getSizeInBits()/8; 7500 MachineFunction &MF = DAG.getMachineFunction(); 7501 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7502 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7503 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7504 StackSlot, 7505 MachinePointerInfo::getFixedStack(SSFI), 7506 false, false, 0); 7507 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7508} 7509 7510SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7511 SDValue StackSlot, 7512 SelectionDAG &DAG) const { 7513 // Build the FILD 7514 DebugLoc DL = Op.getDebugLoc(); 7515 SDVTList Tys; 7516 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7517 if (useSSE) 7518 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7519 else 7520 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7521 7522 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7523 7524 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7525 MachineMemOperand *MMO; 7526 if (FI) { 7527 int SSFI = FI->getIndex(); 7528 MMO = 7529 DAG.getMachineFunction() 7530 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7531 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7532 } else { 7533 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7534 StackSlot = StackSlot.getOperand(1); 7535 } 7536 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7537 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7538 X86ISD::FILD, DL, 7539 Tys, Ops, array_lengthof(Ops), 7540 SrcVT, MMO); 7541 7542 if (useSSE) { 7543 Chain = Result.getValue(1); 7544 SDValue InFlag = Result.getValue(2); 7545 7546 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7547 // shouldn't be necessary except that RFP cannot be live across 7548 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7549 MachineFunction &MF = DAG.getMachineFunction(); 7550 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7551 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7552 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7553 Tys = DAG.getVTList(MVT::Other); 7554 SDValue Ops[] = { 7555 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7556 }; 7557 MachineMemOperand *MMO = 7558 DAG.getMachineFunction() 7559 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7560 MachineMemOperand::MOStore, SSFISize, SSFISize); 7561 7562 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7563 Ops, array_lengthof(Ops), 7564 Op.getValueType(), MMO); 7565 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7566 MachinePointerInfo::getFixedStack(SSFI), 7567 false, false, false, 0); 7568 } 7569 7570 return Result; 7571} 7572 7573// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7574SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7575 SelectionDAG &DAG) const { 7576 // This algorithm is not obvious. Here it is what we're trying to output: 7577 /* 7578 movq %rax, %xmm0 7579 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7580 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7581 #ifdef __SSE3__ 7582 haddpd %xmm0, %xmm0 7583 #else 7584 pshufd $0x4e, %xmm0, %xmm1 7585 addpd %xmm1, %xmm0 7586 #endif 7587 */ 7588 7589 DebugLoc dl = Op.getDebugLoc(); 7590 LLVMContext *Context = DAG.getContext(); 7591 7592 // Build some magic constants. 7593 SmallVector<Constant*,4> CV0; 7594 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7595 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7596 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7597 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7598 Constant *C0 = ConstantVector::get(CV0); 7599 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7600 7601 SmallVector<Constant*,2> CV1; 7602 CV1.push_back( 7603 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7604 CV1.push_back( 7605 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7606 Constant *C1 = ConstantVector::get(CV1); 7607 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7608 7609 // Load the 64-bit value into an XMM register. 7610 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7611 Op.getOperand(0)); 7612 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7613 MachinePointerInfo::getConstantPool(), 7614 false, false, false, 16); 7615 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7616 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7617 CLod0); 7618 7619 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7620 MachinePointerInfo::getConstantPool(), 7621 false, false, false, 16); 7622 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7623 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7624 SDValue Result; 7625 7626 if (Subtarget->hasSSE3()) { 7627 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7628 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7629 } else { 7630 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7631 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7632 S2F, 0x4E, DAG); 7633 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7634 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7635 Sub); 7636 } 7637 7638 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7639 DAG.getIntPtrConstant(0)); 7640} 7641 7642// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7643SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7644 SelectionDAG &DAG) const { 7645 DebugLoc dl = Op.getDebugLoc(); 7646 // FP constant to bias correct the final result. 7647 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7648 MVT::f64); 7649 7650 // Load the 32-bit value into an XMM register. 7651 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7652 Op.getOperand(0)); 7653 7654 // Zero out the upper parts of the register. 7655 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7656 7657 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7658 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7659 DAG.getIntPtrConstant(0)); 7660 7661 // Or the load with the bias. 7662 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7663 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7664 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7665 MVT::v2f64, Load)), 7666 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7667 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7668 MVT::v2f64, Bias))); 7669 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7670 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7671 DAG.getIntPtrConstant(0)); 7672 7673 // Subtract the bias. 7674 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7675 7676 // Handle final rounding. 7677 EVT DestVT = Op.getValueType(); 7678 7679 if (DestVT.bitsLT(MVT::f64)) { 7680 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7681 DAG.getIntPtrConstant(0)); 7682 } else if (DestVT.bitsGT(MVT::f64)) { 7683 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7684 } 7685 7686 // Handle final rounding. 7687 return Sub; 7688} 7689 7690SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7691 SelectionDAG &DAG) const { 7692 SDValue N0 = Op.getOperand(0); 7693 DebugLoc dl = Op.getDebugLoc(); 7694 7695 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7696 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7697 // the optimization here. 7698 if (DAG.SignBitIsZero(N0)) 7699 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7700 7701 EVT SrcVT = N0.getValueType(); 7702 EVT DstVT = Op.getValueType(); 7703 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7704 return LowerUINT_TO_FP_i64(Op, DAG); 7705 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7706 return LowerUINT_TO_FP_i32(Op, DAG); 7707 else if (Subtarget->is64Bit() && 7708 SrcVT == MVT::i64 && DstVT == MVT::f32) 7709 return SDValue(); 7710 7711 // Make a 64-bit buffer, and use it to build an FILD. 7712 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7713 if (SrcVT == MVT::i32) { 7714 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7715 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7716 getPointerTy(), StackSlot, WordOff); 7717 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7718 StackSlot, MachinePointerInfo(), 7719 false, false, 0); 7720 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7721 OffsetSlot, MachinePointerInfo(), 7722 false, false, 0); 7723 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7724 return Fild; 7725 } 7726 7727 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7728 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7729 StackSlot, MachinePointerInfo(), 7730 false, false, 0); 7731 // For i64 source, we need to add the appropriate power of 2 if the input 7732 // was negative. This is the same as the optimization in 7733 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7734 // we must be careful to do the computation in x87 extended precision, not 7735 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7736 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7737 MachineMemOperand *MMO = 7738 DAG.getMachineFunction() 7739 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7740 MachineMemOperand::MOLoad, 8, 8); 7741 7742 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7743 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7744 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7745 MVT::i64, MMO); 7746 7747 APInt FF(32, 0x5F800000ULL); 7748 7749 // Check whether the sign bit is set. 7750 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7751 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7752 ISD::SETLT); 7753 7754 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7755 SDValue FudgePtr = DAG.getConstantPool( 7756 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7757 getPointerTy()); 7758 7759 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7760 SDValue Zero = DAG.getIntPtrConstant(0); 7761 SDValue Four = DAG.getIntPtrConstant(4); 7762 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7763 Zero, Four); 7764 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7765 7766 // Load the value out, extending it from f32 to f80. 7767 // FIXME: Avoid the extend by constructing the right constant pool? 7768 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7769 FudgePtr, MachinePointerInfo::getConstantPool(), 7770 MVT::f32, false, false, 4); 7771 // Extend everything to 80 bits to force it to be done on x87. 7772 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7773 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7774} 7775 7776std::pair<SDValue,SDValue> X86TargetLowering:: 7777FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7778 DebugLoc DL = Op.getDebugLoc(); 7779 7780 EVT DstTy = Op.getValueType(); 7781 7782 if (!IsSigned) { 7783 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7784 DstTy = MVT::i64; 7785 } 7786 7787 assert(DstTy.getSimpleVT() <= MVT::i64 && 7788 DstTy.getSimpleVT() >= MVT::i16 && 7789 "Unknown FP_TO_SINT to lower!"); 7790 7791 // These are really Legal. 7792 if (DstTy == MVT::i32 && 7793 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7794 return std::make_pair(SDValue(), SDValue()); 7795 if (Subtarget->is64Bit() && 7796 DstTy == MVT::i64 && 7797 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7798 return std::make_pair(SDValue(), SDValue()); 7799 7800 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7801 // stack slot. 7802 MachineFunction &MF = DAG.getMachineFunction(); 7803 unsigned MemSize = DstTy.getSizeInBits()/8; 7804 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7805 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7806 7807 7808 7809 unsigned Opc; 7810 switch (DstTy.getSimpleVT().SimpleTy) { 7811 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7812 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7813 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7814 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7815 } 7816 7817 SDValue Chain = DAG.getEntryNode(); 7818 SDValue Value = Op.getOperand(0); 7819 EVT TheVT = Op.getOperand(0).getValueType(); 7820 if (isScalarFPTypeInSSEReg(TheVT)) { 7821 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7822 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7823 MachinePointerInfo::getFixedStack(SSFI), 7824 false, false, 0); 7825 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7826 SDValue Ops[] = { 7827 Chain, StackSlot, DAG.getValueType(TheVT) 7828 }; 7829 7830 MachineMemOperand *MMO = 7831 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7832 MachineMemOperand::MOLoad, MemSize, MemSize); 7833 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7834 DstTy, MMO); 7835 Chain = Value.getValue(1); 7836 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7837 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7838 } 7839 7840 MachineMemOperand *MMO = 7841 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7842 MachineMemOperand::MOStore, MemSize, MemSize); 7843 7844 // Build the FP_TO_INT*_IN_MEM 7845 SDValue Ops[] = { Chain, Value, StackSlot }; 7846 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7847 Ops, 3, DstTy, MMO); 7848 7849 return std::make_pair(FIST, StackSlot); 7850} 7851 7852SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7853 SelectionDAG &DAG) const { 7854 if (Op.getValueType().isVector()) 7855 return SDValue(); 7856 7857 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7858 SDValue FIST = Vals.first, StackSlot = Vals.second; 7859 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7860 if (FIST.getNode() == 0) return Op; 7861 7862 // Load the result. 7863 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7864 FIST, StackSlot, MachinePointerInfo(), 7865 false, false, false, 0); 7866} 7867 7868SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7869 SelectionDAG &DAG) const { 7870 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7871 SDValue FIST = Vals.first, StackSlot = Vals.second; 7872 assert(FIST.getNode() && "Unexpected failure"); 7873 7874 // Load the result. 7875 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7876 FIST, StackSlot, MachinePointerInfo(), 7877 false, false, false, 0); 7878} 7879 7880SDValue X86TargetLowering::LowerFABS(SDValue Op, 7881 SelectionDAG &DAG) const { 7882 LLVMContext *Context = DAG.getContext(); 7883 DebugLoc dl = Op.getDebugLoc(); 7884 EVT VT = Op.getValueType(); 7885 EVT EltVT = VT; 7886 if (VT.isVector()) 7887 EltVT = VT.getVectorElementType(); 7888 SmallVector<Constant*,4> CV; 7889 if (EltVT == MVT::f64) { 7890 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7891 CV.assign(2, C); 7892 } else { 7893 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7894 CV.assign(4, C); 7895 } 7896 Constant *C = ConstantVector::get(CV); 7897 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7898 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7899 MachinePointerInfo::getConstantPool(), 7900 false, false, false, 16); 7901 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7902} 7903 7904SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7905 LLVMContext *Context = DAG.getContext(); 7906 DebugLoc dl = Op.getDebugLoc(); 7907 EVT VT = Op.getValueType(); 7908 EVT EltVT = VT; 7909 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7910 if (VT.isVector()) { 7911 EltVT = VT.getVectorElementType(); 7912 NumElts = VT.getVectorNumElements(); 7913 } 7914 SmallVector<Constant*,8> CV; 7915 if (EltVT == MVT::f64) { 7916 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7917 CV.assign(NumElts, C); 7918 } else { 7919 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7920 CV.assign(NumElts, C); 7921 } 7922 Constant *C = ConstantVector::get(CV); 7923 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7924 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7925 MachinePointerInfo::getConstantPool(), 7926 false, false, false, 16); 7927 if (VT.isVector()) { 7928 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7929 return DAG.getNode(ISD::BITCAST, dl, VT, 7930 DAG.getNode(ISD::XOR, dl, XORVT, 7931 DAG.getNode(ISD::BITCAST, dl, XORVT, 7932 Op.getOperand(0)), 7933 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7934 } else { 7935 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7936 } 7937} 7938 7939SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7940 LLVMContext *Context = DAG.getContext(); 7941 SDValue Op0 = Op.getOperand(0); 7942 SDValue Op1 = Op.getOperand(1); 7943 DebugLoc dl = Op.getDebugLoc(); 7944 EVT VT = Op.getValueType(); 7945 EVT SrcVT = Op1.getValueType(); 7946 7947 // If second operand is smaller, extend it first. 7948 if (SrcVT.bitsLT(VT)) { 7949 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7950 SrcVT = VT; 7951 } 7952 // And if it is bigger, shrink it first. 7953 if (SrcVT.bitsGT(VT)) { 7954 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7955 SrcVT = VT; 7956 } 7957 7958 // At this point the operands and the result should have the same 7959 // type, and that won't be f80 since that is not custom lowered. 7960 7961 // First get the sign bit of second operand. 7962 SmallVector<Constant*,4> CV; 7963 if (SrcVT == MVT::f64) { 7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7966 } else { 7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7971 } 7972 Constant *C = ConstantVector::get(CV); 7973 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7974 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7975 MachinePointerInfo::getConstantPool(), 7976 false, false, false, 16); 7977 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7978 7979 // Shift sign bit right or left if the two operands have different types. 7980 if (SrcVT.bitsGT(VT)) { 7981 // Op0 is MVT::f32, Op1 is MVT::f64. 7982 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7983 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7984 DAG.getConstant(32, MVT::i32)); 7985 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7986 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7987 DAG.getIntPtrConstant(0)); 7988 } 7989 7990 // Clear first operand sign bit. 7991 CV.clear(); 7992 if (VT == MVT::f64) { 7993 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7994 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7995 } else { 7996 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8000 } 8001 C = ConstantVector::get(CV); 8002 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8003 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8004 MachinePointerInfo::getConstantPool(), 8005 false, false, false, 16); 8006 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8007 8008 // Or the value with the sign bit. 8009 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8010} 8011 8012SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8013 SDValue N0 = Op.getOperand(0); 8014 DebugLoc dl = Op.getDebugLoc(); 8015 EVT VT = Op.getValueType(); 8016 8017 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8018 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8019 DAG.getConstant(1, VT)); 8020 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8021} 8022 8023/// Emit nodes that will be selected as "test Op0,Op0", or something 8024/// equivalent. 8025SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8026 SelectionDAG &DAG) const { 8027 DebugLoc dl = Op.getDebugLoc(); 8028 8029 // CF and OF aren't always set the way we want. Determine which 8030 // of these we need. 8031 bool NeedCF = false; 8032 bool NeedOF = false; 8033 switch (X86CC) { 8034 default: break; 8035 case X86::COND_A: case X86::COND_AE: 8036 case X86::COND_B: case X86::COND_BE: 8037 NeedCF = true; 8038 break; 8039 case X86::COND_G: case X86::COND_GE: 8040 case X86::COND_L: case X86::COND_LE: 8041 case X86::COND_O: case X86::COND_NO: 8042 NeedOF = true; 8043 break; 8044 } 8045 8046 // See if we can use the EFLAGS value from the operand instead of 8047 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8048 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8049 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8050 // Emit a CMP with 0, which is the TEST pattern. 8051 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8052 DAG.getConstant(0, Op.getValueType())); 8053 8054 unsigned Opcode = 0; 8055 unsigned NumOperands = 0; 8056 switch (Op.getNode()->getOpcode()) { 8057 case ISD::ADD: 8058 // Due to an isel shortcoming, be conservative if this add is likely to be 8059 // selected as part of a load-modify-store instruction. When the root node 8060 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8061 // uses of other nodes in the match, such as the ADD in this case. This 8062 // leads to the ADD being left around and reselected, with the result being 8063 // two adds in the output. Alas, even if none our users are stores, that 8064 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8065 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8066 // climbing the DAG back to the root, and it doesn't seem to be worth the 8067 // effort. 8068 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8069 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8070 if (UI->getOpcode() != ISD::CopyToReg && 8071 UI->getOpcode() != ISD::SETCC && 8072 UI->getOpcode() != ISD::STORE) 8073 goto default_case; 8074 8075 if (ConstantSDNode *C = 8076 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8077 // An add of one will be selected as an INC. 8078 if (C->getAPIntValue() == 1) { 8079 Opcode = X86ISD::INC; 8080 NumOperands = 1; 8081 break; 8082 } 8083 8084 // An add of negative one (subtract of one) will be selected as a DEC. 8085 if (C->getAPIntValue().isAllOnesValue()) { 8086 Opcode = X86ISD::DEC; 8087 NumOperands = 1; 8088 break; 8089 } 8090 } 8091 8092 // Otherwise use a regular EFLAGS-setting add. 8093 Opcode = X86ISD::ADD; 8094 NumOperands = 2; 8095 break; 8096 case ISD::AND: { 8097 // If the primary and result isn't used, don't bother using X86ISD::AND, 8098 // because a TEST instruction will be better. 8099 bool NonFlagUse = false; 8100 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8101 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8102 SDNode *User = *UI; 8103 unsigned UOpNo = UI.getOperandNo(); 8104 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8105 // Look pass truncate. 8106 UOpNo = User->use_begin().getOperandNo(); 8107 User = *User->use_begin(); 8108 } 8109 8110 if (User->getOpcode() != ISD::BRCOND && 8111 User->getOpcode() != ISD::SETCC && 8112 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8113 NonFlagUse = true; 8114 break; 8115 } 8116 } 8117 8118 if (!NonFlagUse) 8119 break; 8120 } 8121 // FALL THROUGH 8122 case ISD::SUB: 8123 case ISD::OR: 8124 case ISD::XOR: 8125 // Due to the ISEL shortcoming noted above, be conservative if this op is 8126 // likely to be selected as part of a load-modify-store instruction. 8127 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8128 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8129 if (UI->getOpcode() == ISD::STORE) 8130 goto default_case; 8131 8132 // Otherwise use a regular EFLAGS-setting instruction. 8133 switch (Op.getNode()->getOpcode()) { 8134 default: llvm_unreachable("unexpected operator!"); 8135 case ISD::SUB: Opcode = X86ISD::SUB; break; 8136 case ISD::OR: Opcode = X86ISD::OR; break; 8137 case ISD::XOR: Opcode = X86ISD::XOR; break; 8138 case ISD::AND: Opcode = X86ISD::AND; break; 8139 } 8140 8141 NumOperands = 2; 8142 break; 8143 case X86ISD::ADD: 8144 case X86ISD::SUB: 8145 case X86ISD::INC: 8146 case X86ISD::DEC: 8147 case X86ISD::OR: 8148 case X86ISD::XOR: 8149 case X86ISD::AND: 8150 return SDValue(Op.getNode(), 1); 8151 default: 8152 default_case: 8153 break; 8154 } 8155 8156 if (Opcode == 0) 8157 // Emit a CMP with 0, which is the TEST pattern. 8158 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8159 DAG.getConstant(0, Op.getValueType())); 8160 8161 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8162 SmallVector<SDValue, 4> Ops; 8163 for (unsigned i = 0; i != NumOperands; ++i) 8164 Ops.push_back(Op.getOperand(i)); 8165 8166 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8167 DAG.ReplaceAllUsesWith(Op, New); 8168 return SDValue(New.getNode(), 1); 8169} 8170 8171/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8172/// equivalent. 8173SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8174 SelectionDAG &DAG) const { 8175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8176 if (C->getAPIntValue() == 0) 8177 return EmitTest(Op0, X86CC, DAG); 8178 8179 DebugLoc dl = Op0.getDebugLoc(); 8180 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8181} 8182 8183/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8184/// if it's possible. 8185SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8186 DebugLoc dl, SelectionDAG &DAG) const { 8187 SDValue Op0 = And.getOperand(0); 8188 SDValue Op1 = And.getOperand(1); 8189 if (Op0.getOpcode() == ISD::TRUNCATE) 8190 Op0 = Op0.getOperand(0); 8191 if (Op1.getOpcode() == ISD::TRUNCATE) 8192 Op1 = Op1.getOperand(0); 8193 8194 SDValue LHS, RHS; 8195 if (Op1.getOpcode() == ISD::SHL) 8196 std::swap(Op0, Op1); 8197 if (Op0.getOpcode() == ISD::SHL) { 8198 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8199 if (And00C->getZExtValue() == 1) { 8200 // If we looked past a truncate, check that it's only truncating away 8201 // known zeros. 8202 unsigned BitWidth = Op0.getValueSizeInBits(); 8203 unsigned AndBitWidth = And.getValueSizeInBits(); 8204 if (BitWidth > AndBitWidth) { 8205 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8206 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8207 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8208 return SDValue(); 8209 } 8210 LHS = Op1; 8211 RHS = Op0.getOperand(1); 8212 } 8213 } else if (Op1.getOpcode() == ISD::Constant) { 8214 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8215 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8216 SDValue AndLHS = Op0; 8217 8218 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8219 LHS = AndLHS.getOperand(0); 8220 RHS = AndLHS.getOperand(1); 8221 } 8222 8223 // Use BT if the immediate can't be encoded in a TEST instruction. 8224 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8225 LHS = AndLHS; 8226 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8227 } 8228 } 8229 8230 if (LHS.getNode()) { 8231 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8232 // instruction. Since the shift amount is in-range-or-undefined, we know 8233 // that doing a bittest on the i32 value is ok. We extend to i32 because 8234 // the encoding for the i16 version is larger than the i32 version. 8235 // Also promote i16 to i32 for performance / code size reason. 8236 if (LHS.getValueType() == MVT::i8 || 8237 LHS.getValueType() == MVT::i16) 8238 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8239 8240 // If the operand types disagree, extend the shift amount to match. Since 8241 // BT ignores high bits (like shifts) we can use anyextend. 8242 if (LHS.getValueType() != RHS.getValueType()) 8243 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8244 8245 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8246 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8247 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8248 DAG.getConstant(Cond, MVT::i8), BT); 8249 } 8250 8251 return SDValue(); 8252} 8253 8254SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8255 8256 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8257 8258 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8259 SDValue Op0 = Op.getOperand(0); 8260 SDValue Op1 = Op.getOperand(1); 8261 DebugLoc dl = Op.getDebugLoc(); 8262 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8263 8264 // Optimize to BT if possible. 8265 // Lower (X & (1 << N)) == 0 to BT(X, N). 8266 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8267 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8268 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8269 Op1.getOpcode() == ISD::Constant && 8270 cast<ConstantSDNode>(Op1)->isNullValue() && 8271 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8272 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8273 if (NewSetCC.getNode()) 8274 return NewSetCC; 8275 } 8276 8277 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8278 // these. 8279 if (Op1.getOpcode() == ISD::Constant && 8280 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8281 cast<ConstantSDNode>(Op1)->isNullValue()) && 8282 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8283 8284 // If the input is a setcc, then reuse the input setcc or use a new one with 8285 // the inverted condition. 8286 if (Op0.getOpcode() == X86ISD::SETCC) { 8287 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8288 bool Invert = (CC == ISD::SETNE) ^ 8289 cast<ConstantSDNode>(Op1)->isNullValue(); 8290 if (!Invert) return Op0; 8291 8292 CCode = X86::GetOppositeBranchCondition(CCode); 8293 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8294 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8295 } 8296 } 8297 8298 bool isFP = Op1.getValueType().isFloatingPoint(); 8299 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8300 if (X86CC == X86::COND_INVALID) 8301 return SDValue(); 8302 8303 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8304 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8305 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8306} 8307 8308// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8309// ones, and then concatenate the result back. 8310static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8311 EVT VT = Op.getValueType(); 8312 8313 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8314 "Unsupported value type for operation"); 8315 8316 int NumElems = VT.getVectorNumElements(); 8317 DebugLoc dl = Op.getDebugLoc(); 8318 SDValue CC = Op.getOperand(2); 8319 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8320 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8321 8322 // Extract the LHS vectors 8323 SDValue LHS = Op.getOperand(0); 8324 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8325 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8326 8327 // Extract the RHS vectors 8328 SDValue RHS = Op.getOperand(1); 8329 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8330 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8331 8332 // Issue the operation on the smaller types and concatenate the result back 8333 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8334 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8335 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8336 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8337 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8338} 8339 8340 8341SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8342 SDValue Cond; 8343 SDValue Op0 = Op.getOperand(0); 8344 SDValue Op1 = Op.getOperand(1); 8345 SDValue CC = Op.getOperand(2); 8346 EVT VT = Op.getValueType(); 8347 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8348 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8349 DebugLoc dl = Op.getDebugLoc(); 8350 8351 if (isFP) { 8352 unsigned SSECC = 8; 8353 EVT EltVT = Op0.getValueType().getVectorElementType(); 8354 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8355 8356 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8357 bool Swap = false; 8358 8359 // SSE Condition code mapping: 8360 // 0 - EQ 8361 // 1 - LT 8362 // 2 - LE 8363 // 3 - UNORD 8364 // 4 - NEQ 8365 // 5 - NLT 8366 // 6 - NLE 8367 // 7 - ORD 8368 switch (SetCCOpcode) { 8369 default: break; 8370 case ISD::SETOEQ: 8371 case ISD::SETEQ: SSECC = 0; break; 8372 case ISD::SETOGT: 8373 case ISD::SETGT: Swap = true; // Fallthrough 8374 case ISD::SETLT: 8375 case ISD::SETOLT: SSECC = 1; break; 8376 case ISD::SETOGE: 8377 case ISD::SETGE: Swap = true; // Fallthrough 8378 case ISD::SETLE: 8379 case ISD::SETOLE: SSECC = 2; break; 8380 case ISD::SETUO: SSECC = 3; break; 8381 case ISD::SETUNE: 8382 case ISD::SETNE: SSECC = 4; break; 8383 case ISD::SETULE: Swap = true; 8384 case ISD::SETUGE: SSECC = 5; break; 8385 case ISD::SETULT: Swap = true; 8386 case ISD::SETUGT: SSECC = 6; break; 8387 case ISD::SETO: SSECC = 7; break; 8388 } 8389 if (Swap) 8390 std::swap(Op0, Op1); 8391 8392 // In the two special cases we can't handle, emit two comparisons. 8393 if (SSECC == 8) { 8394 if (SetCCOpcode == ISD::SETUEQ) { 8395 SDValue UNORD, EQ; 8396 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8397 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8398 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8399 } else if (SetCCOpcode == ISD::SETONE) { 8400 SDValue ORD, NEQ; 8401 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8402 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8403 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8404 } 8405 llvm_unreachable("Illegal FP comparison"); 8406 } 8407 // Handle all other FP comparisons here. 8408 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8409 } 8410 8411 // Break 256-bit integer vector compare into smaller ones. 8412 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8413 return Lower256IntVSETCC(Op, DAG); 8414 8415 // We are handling one of the integer comparisons here. Since SSE only has 8416 // GT and EQ comparisons for integer, swapping operands and multiple 8417 // operations may be required for some comparisons. 8418 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8419 bool Swap = false, Invert = false, FlipSigns = false; 8420 8421 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 8422 default: break; 8423 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8424 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8425 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8426 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8427 } 8428 8429 switch (SetCCOpcode) { 8430 default: break; 8431 case ISD::SETNE: Invert = true; 8432 case ISD::SETEQ: Opc = EQOpc; break; 8433 case ISD::SETLT: Swap = true; 8434 case ISD::SETGT: Opc = GTOpc; break; 8435 case ISD::SETGE: Swap = true; 8436 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8437 case ISD::SETULT: Swap = true; 8438 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8439 case ISD::SETUGE: Swap = true; 8440 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8441 } 8442 if (Swap) 8443 std::swap(Op0, Op1); 8444 8445 // Check that the operation in question is available (most are plain SSE2, 8446 // but PCMPGTQ and PCMPEQQ have different requirements). 8447 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42()) 8448 return SDValue(); 8449 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41()) 8450 return SDValue(); 8451 8452 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8453 // bits of the inputs before performing those operations. 8454 if (FlipSigns) { 8455 EVT EltVT = VT.getVectorElementType(); 8456 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8457 EltVT); 8458 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8459 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8460 SignBits.size()); 8461 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8462 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8463 } 8464 8465 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8466 8467 // If the logical-not of the result is required, perform that now. 8468 if (Invert) 8469 Result = DAG.getNOT(dl, Result, VT); 8470 8471 return Result; 8472} 8473 8474// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8475static bool isX86LogicalCmp(SDValue Op) { 8476 unsigned Opc = Op.getNode()->getOpcode(); 8477 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8478 return true; 8479 if (Op.getResNo() == 1 && 8480 (Opc == X86ISD::ADD || 8481 Opc == X86ISD::SUB || 8482 Opc == X86ISD::ADC || 8483 Opc == X86ISD::SBB || 8484 Opc == X86ISD::SMUL || 8485 Opc == X86ISD::UMUL || 8486 Opc == X86ISD::INC || 8487 Opc == X86ISD::DEC || 8488 Opc == X86ISD::OR || 8489 Opc == X86ISD::XOR || 8490 Opc == X86ISD::AND)) 8491 return true; 8492 8493 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8494 return true; 8495 8496 return false; 8497} 8498 8499static bool isZero(SDValue V) { 8500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8501 return C && C->isNullValue(); 8502} 8503 8504static bool isAllOnes(SDValue V) { 8505 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8506 return C && C->isAllOnesValue(); 8507} 8508 8509SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8510 bool addTest = true; 8511 SDValue Cond = Op.getOperand(0); 8512 SDValue Op1 = Op.getOperand(1); 8513 SDValue Op2 = Op.getOperand(2); 8514 DebugLoc DL = Op.getDebugLoc(); 8515 SDValue CC; 8516 8517 if (Cond.getOpcode() == ISD::SETCC) { 8518 SDValue NewCond = LowerSETCC(Cond, DAG); 8519 if (NewCond.getNode()) 8520 Cond = NewCond; 8521 } 8522 8523 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8524 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8525 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8526 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8527 if (Cond.getOpcode() == X86ISD::SETCC && 8528 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8529 isZero(Cond.getOperand(1).getOperand(1))) { 8530 SDValue Cmp = Cond.getOperand(1); 8531 8532 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8533 8534 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8535 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8536 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8537 8538 SDValue CmpOp0 = Cmp.getOperand(0); 8539 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8540 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8541 8542 SDValue Res = // Res = 0 or -1. 8543 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8544 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8545 8546 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8547 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8548 8549 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8550 if (N2C == 0 || !N2C->isNullValue()) 8551 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8552 return Res; 8553 } 8554 } 8555 8556 // Look past (and (setcc_carry (cmp ...)), 1). 8557 if (Cond.getOpcode() == ISD::AND && 8558 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8559 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8560 if (C && C->getAPIntValue() == 1) 8561 Cond = Cond.getOperand(0); 8562 } 8563 8564 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8565 // setting operand in place of the X86ISD::SETCC. 8566 unsigned CondOpcode = Cond.getOpcode(); 8567 if (CondOpcode == X86ISD::SETCC || 8568 CondOpcode == X86ISD::SETCC_CARRY) { 8569 CC = Cond.getOperand(0); 8570 8571 SDValue Cmp = Cond.getOperand(1); 8572 unsigned Opc = Cmp.getOpcode(); 8573 EVT VT = Op.getValueType(); 8574 8575 bool IllegalFPCMov = false; 8576 if (VT.isFloatingPoint() && !VT.isVector() && 8577 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8578 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8579 8580 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8581 Opc == X86ISD::BT) { // FIXME 8582 Cond = Cmp; 8583 addTest = false; 8584 } 8585 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8586 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8587 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8588 Cond.getOperand(0).getValueType() != MVT::i8)) { 8589 SDValue LHS = Cond.getOperand(0); 8590 SDValue RHS = Cond.getOperand(1); 8591 unsigned X86Opcode; 8592 unsigned X86Cond; 8593 SDVTList VTs; 8594 switch (CondOpcode) { 8595 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8596 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8597 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8598 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8599 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8600 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8601 default: llvm_unreachable("unexpected overflowing operator"); 8602 } 8603 if (CondOpcode == ISD::UMULO) 8604 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8605 MVT::i32); 8606 else 8607 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8608 8609 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8610 8611 if (CondOpcode == ISD::UMULO) 8612 Cond = X86Op.getValue(2); 8613 else 8614 Cond = X86Op.getValue(1); 8615 8616 CC = DAG.getConstant(X86Cond, MVT::i8); 8617 addTest = false; 8618 } 8619 8620 if (addTest) { 8621 // Look pass the truncate. 8622 if (Cond.getOpcode() == ISD::TRUNCATE) 8623 Cond = Cond.getOperand(0); 8624 8625 // We know the result of AND is compared against zero. Try to match 8626 // it to BT. 8627 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8628 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8629 if (NewSetCC.getNode()) { 8630 CC = NewSetCC.getOperand(0); 8631 Cond = NewSetCC.getOperand(1); 8632 addTest = false; 8633 } 8634 } 8635 } 8636 8637 if (addTest) { 8638 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8639 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8640 } 8641 8642 // a < b ? -1 : 0 -> RES = ~setcc_carry 8643 // a < b ? 0 : -1 -> RES = setcc_carry 8644 // a >= b ? -1 : 0 -> RES = setcc_carry 8645 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8646 if (Cond.getOpcode() == X86ISD::CMP) { 8647 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8648 8649 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8650 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8651 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8652 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8653 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8654 return DAG.getNOT(DL, Res, Res.getValueType()); 8655 return Res; 8656 } 8657 } 8658 8659 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8660 // condition is true. 8661 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8662 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8663 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8664} 8665 8666// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8667// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8668// from the AND / OR. 8669static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8670 Opc = Op.getOpcode(); 8671 if (Opc != ISD::OR && Opc != ISD::AND) 8672 return false; 8673 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8674 Op.getOperand(0).hasOneUse() && 8675 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8676 Op.getOperand(1).hasOneUse()); 8677} 8678 8679// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8680// 1 and that the SETCC node has a single use. 8681static bool isXor1OfSetCC(SDValue Op) { 8682 if (Op.getOpcode() != ISD::XOR) 8683 return false; 8684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8685 if (N1C && N1C->getAPIntValue() == 1) { 8686 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8687 Op.getOperand(0).hasOneUse(); 8688 } 8689 return false; 8690} 8691 8692SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8693 bool addTest = true; 8694 SDValue Chain = Op.getOperand(0); 8695 SDValue Cond = Op.getOperand(1); 8696 SDValue Dest = Op.getOperand(2); 8697 DebugLoc dl = Op.getDebugLoc(); 8698 SDValue CC; 8699 bool Inverted = false; 8700 8701 if (Cond.getOpcode() == ISD::SETCC) { 8702 // Check for setcc([su]{add,sub,mul}o == 0). 8703 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8704 isa<ConstantSDNode>(Cond.getOperand(1)) && 8705 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8706 Cond.getOperand(0).getResNo() == 1 && 8707 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8708 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8709 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8710 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8711 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8712 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8713 Inverted = true; 8714 Cond = Cond.getOperand(0); 8715 } else { 8716 SDValue NewCond = LowerSETCC(Cond, DAG); 8717 if (NewCond.getNode()) 8718 Cond = NewCond; 8719 } 8720 } 8721#if 0 8722 // FIXME: LowerXALUO doesn't handle these!! 8723 else if (Cond.getOpcode() == X86ISD::ADD || 8724 Cond.getOpcode() == X86ISD::SUB || 8725 Cond.getOpcode() == X86ISD::SMUL || 8726 Cond.getOpcode() == X86ISD::UMUL) 8727 Cond = LowerXALUO(Cond, DAG); 8728#endif 8729 8730 // Look pass (and (setcc_carry (cmp ...)), 1). 8731 if (Cond.getOpcode() == ISD::AND && 8732 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8734 if (C && C->getAPIntValue() == 1) 8735 Cond = Cond.getOperand(0); 8736 } 8737 8738 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8739 // setting operand in place of the X86ISD::SETCC. 8740 unsigned CondOpcode = Cond.getOpcode(); 8741 if (CondOpcode == X86ISD::SETCC || 8742 CondOpcode == X86ISD::SETCC_CARRY) { 8743 CC = Cond.getOperand(0); 8744 8745 SDValue Cmp = Cond.getOperand(1); 8746 unsigned Opc = Cmp.getOpcode(); 8747 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8748 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8749 Cond = Cmp; 8750 addTest = false; 8751 } else { 8752 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8753 default: break; 8754 case X86::COND_O: 8755 case X86::COND_B: 8756 // These can only come from an arithmetic instruction with overflow, 8757 // e.g. SADDO, UADDO. 8758 Cond = Cond.getNode()->getOperand(1); 8759 addTest = false; 8760 break; 8761 } 8762 } 8763 } 8764 CondOpcode = Cond.getOpcode(); 8765 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8766 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8767 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8768 Cond.getOperand(0).getValueType() != MVT::i8)) { 8769 SDValue LHS = Cond.getOperand(0); 8770 SDValue RHS = Cond.getOperand(1); 8771 unsigned X86Opcode; 8772 unsigned X86Cond; 8773 SDVTList VTs; 8774 switch (CondOpcode) { 8775 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8776 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8777 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8778 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8779 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8780 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8781 default: llvm_unreachable("unexpected overflowing operator"); 8782 } 8783 if (Inverted) 8784 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8785 if (CondOpcode == ISD::UMULO) 8786 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8787 MVT::i32); 8788 else 8789 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8790 8791 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8792 8793 if (CondOpcode == ISD::UMULO) 8794 Cond = X86Op.getValue(2); 8795 else 8796 Cond = X86Op.getValue(1); 8797 8798 CC = DAG.getConstant(X86Cond, MVT::i8); 8799 addTest = false; 8800 } else { 8801 unsigned CondOpc; 8802 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8803 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8804 if (CondOpc == ISD::OR) { 8805 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8806 // two branches instead of an explicit OR instruction with a 8807 // separate test. 8808 if (Cmp == Cond.getOperand(1).getOperand(1) && 8809 isX86LogicalCmp(Cmp)) { 8810 CC = Cond.getOperand(0).getOperand(0); 8811 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8812 Chain, Dest, CC, Cmp); 8813 CC = Cond.getOperand(1).getOperand(0); 8814 Cond = Cmp; 8815 addTest = false; 8816 } 8817 } else { // ISD::AND 8818 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8819 // two branches instead of an explicit AND instruction with a 8820 // separate test. However, we only do this if this block doesn't 8821 // have a fall-through edge, because this requires an explicit 8822 // jmp when the condition is false. 8823 if (Cmp == Cond.getOperand(1).getOperand(1) && 8824 isX86LogicalCmp(Cmp) && 8825 Op.getNode()->hasOneUse()) { 8826 X86::CondCode CCode = 8827 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8828 CCode = X86::GetOppositeBranchCondition(CCode); 8829 CC = DAG.getConstant(CCode, MVT::i8); 8830 SDNode *User = *Op.getNode()->use_begin(); 8831 // Look for an unconditional branch following this conditional branch. 8832 // We need this because we need to reverse the successors in order 8833 // to implement FCMP_OEQ. 8834 if (User->getOpcode() == ISD::BR) { 8835 SDValue FalseBB = User->getOperand(1); 8836 SDNode *NewBR = 8837 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8838 assert(NewBR == User); 8839 (void)NewBR; 8840 Dest = FalseBB; 8841 8842 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8843 Chain, Dest, CC, Cmp); 8844 X86::CondCode CCode = 8845 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8846 CCode = X86::GetOppositeBranchCondition(CCode); 8847 CC = DAG.getConstant(CCode, MVT::i8); 8848 Cond = Cmp; 8849 addTest = false; 8850 } 8851 } 8852 } 8853 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8854 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8855 // It should be transformed during dag combiner except when the condition 8856 // is set by a arithmetics with overflow node. 8857 X86::CondCode CCode = 8858 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8859 CCode = X86::GetOppositeBranchCondition(CCode); 8860 CC = DAG.getConstant(CCode, MVT::i8); 8861 Cond = Cond.getOperand(0).getOperand(1); 8862 addTest = false; 8863 } else if (Cond.getOpcode() == ISD::SETCC && 8864 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8865 // For FCMP_OEQ, we can emit 8866 // two branches instead of an explicit AND instruction with a 8867 // separate test. However, we only do this if this block doesn't 8868 // have a fall-through edge, because this requires an explicit 8869 // jmp when the condition is false. 8870 if (Op.getNode()->hasOneUse()) { 8871 SDNode *User = *Op.getNode()->use_begin(); 8872 // Look for an unconditional branch following this conditional branch. 8873 // We need this because we need to reverse the successors in order 8874 // to implement FCMP_OEQ. 8875 if (User->getOpcode() == ISD::BR) { 8876 SDValue FalseBB = User->getOperand(1); 8877 SDNode *NewBR = 8878 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8879 assert(NewBR == User); 8880 (void)NewBR; 8881 Dest = FalseBB; 8882 8883 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8884 Cond.getOperand(0), Cond.getOperand(1)); 8885 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8886 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8887 Chain, Dest, CC, Cmp); 8888 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8889 Cond = Cmp; 8890 addTest = false; 8891 } 8892 } 8893 } else if (Cond.getOpcode() == ISD::SETCC && 8894 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8895 // For FCMP_UNE, we can emit 8896 // two branches instead of an explicit AND instruction with a 8897 // separate test. However, we only do this if this block doesn't 8898 // have a fall-through edge, because this requires an explicit 8899 // jmp when the condition is false. 8900 if (Op.getNode()->hasOneUse()) { 8901 SDNode *User = *Op.getNode()->use_begin(); 8902 // Look for an unconditional branch following this conditional branch. 8903 // We need this because we need to reverse the successors in order 8904 // to implement FCMP_UNE. 8905 if (User->getOpcode() == ISD::BR) { 8906 SDValue FalseBB = User->getOperand(1); 8907 SDNode *NewBR = 8908 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8909 assert(NewBR == User); 8910 (void)NewBR; 8911 8912 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8913 Cond.getOperand(0), Cond.getOperand(1)); 8914 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8915 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8916 Chain, Dest, CC, Cmp); 8917 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8918 Cond = Cmp; 8919 addTest = false; 8920 Dest = FalseBB; 8921 } 8922 } 8923 } 8924 } 8925 8926 if (addTest) { 8927 // Look pass the truncate. 8928 if (Cond.getOpcode() == ISD::TRUNCATE) 8929 Cond = Cond.getOperand(0); 8930 8931 // We know the result of AND is compared against zero. Try to match 8932 // it to BT. 8933 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8934 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8935 if (NewSetCC.getNode()) { 8936 CC = NewSetCC.getOperand(0); 8937 Cond = NewSetCC.getOperand(1); 8938 addTest = false; 8939 } 8940 } 8941 } 8942 8943 if (addTest) { 8944 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8945 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8946 } 8947 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8948 Chain, Dest, CC, Cond); 8949} 8950 8951 8952// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8953// Calls to _alloca is needed to probe the stack when allocating more than 4k 8954// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8955// that the guard pages used by the OS virtual memory manager are allocated in 8956// correct sequence. 8957SDValue 8958X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8959 SelectionDAG &DAG) const { 8960 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8961 getTargetMachine().Options.EnableSegmentedStacks) && 8962 "This should be used only on Windows targets or when segmented stacks " 8963 "are being used"); 8964 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8965 DebugLoc dl = Op.getDebugLoc(); 8966 8967 // Get the inputs. 8968 SDValue Chain = Op.getOperand(0); 8969 SDValue Size = Op.getOperand(1); 8970 // FIXME: Ensure alignment here 8971 8972 bool Is64Bit = Subtarget->is64Bit(); 8973 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8974 8975 if (getTargetMachine().Options.EnableSegmentedStacks) { 8976 MachineFunction &MF = DAG.getMachineFunction(); 8977 MachineRegisterInfo &MRI = MF.getRegInfo(); 8978 8979 if (Is64Bit) { 8980 // The 64 bit implementation of segmented stacks needs to clobber both r10 8981 // r11. This makes it impossible to use it along with nested parameters. 8982 const Function *F = MF.getFunction(); 8983 8984 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8985 I != E; I++) 8986 if (I->hasNestAttr()) 8987 report_fatal_error("Cannot use segmented stacks with functions that " 8988 "have nested arguments."); 8989 } 8990 8991 const TargetRegisterClass *AddrRegClass = 8992 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8993 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8994 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8995 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8996 DAG.getRegister(Vreg, SPTy)); 8997 SDValue Ops1[2] = { Value, Chain }; 8998 return DAG.getMergeValues(Ops1, 2, dl); 8999 } else { 9000 SDValue Flag; 9001 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9002 9003 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9004 Flag = Chain.getValue(1); 9005 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9006 9007 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9008 Flag = Chain.getValue(1); 9009 9010 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9011 9012 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9013 return DAG.getMergeValues(Ops1, 2, dl); 9014 } 9015} 9016 9017SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9018 MachineFunction &MF = DAG.getMachineFunction(); 9019 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9020 9021 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9022 DebugLoc DL = Op.getDebugLoc(); 9023 9024 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9025 // vastart just stores the address of the VarArgsFrameIndex slot into the 9026 // memory location argument. 9027 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9028 getPointerTy()); 9029 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9030 MachinePointerInfo(SV), false, false, 0); 9031 } 9032 9033 // __va_list_tag: 9034 // gp_offset (0 - 6 * 8) 9035 // fp_offset (48 - 48 + 8 * 16) 9036 // overflow_arg_area (point to parameters coming in memory). 9037 // reg_save_area 9038 SmallVector<SDValue, 8> MemOps; 9039 SDValue FIN = Op.getOperand(1); 9040 // Store gp_offset 9041 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9042 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9043 MVT::i32), 9044 FIN, MachinePointerInfo(SV), false, false, 0); 9045 MemOps.push_back(Store); 9046 9047 // Store fp_offset 9048 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9049 FIN, DAG.getIntPtrConstant(4)); 9050 Store = DAG.getStore(Op.getOperand(0), DL, 9051 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9052 MVT::i32), 9053 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9054 MemOps.push_back(Store); 9055 9056 // Store ptr to overflow_arg_area 9057 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9058 FIN, DAG.getIntPtrConstant(4)); 9059 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9060 getPointerTy()); 9061 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9062 MachinePointerInfo(SV, 8), 9063 false, false, 0); 9064 MemOps.push_back(Store); 9065 9066 // Store ptr to reg_save_area. 9067 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9068 FIN, DAG.getIntPtrConstant(8)); 9069 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9070 getPointerTy()); 9071 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9072 MachinePointerInfo(SV, 16), false, false, 0); 9073 MemOps.push_back(Store); 9074 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9075 &MemOps[0], MemOps.size()); 9076} 9077 9078SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9079 assert(Subtarget->is64Bit() && 9080 "LowerVAARG only handles 64-bit va_arg!"); 9081 assert((Subtarget->isTargetLinux() || 9082 Subtarget->isTargetDarwin()) && 9083 "Unhandled target in LowerVAARG"); 9084 assert(Op.getNode()->getNumOperands() == 4); 9085 SDValue Chain = Op.getOperand(0); 9086 SDValue SrcPtr = Op.getOperand(1); 9087 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9088 unsigned Align = Op.getConstantOperandVal(3); 9089 DebugLoc dl = Op.getDebugLoc(); 9090 9091 EVT ArgVT = Op.getNode()->getValueType(0); 9092 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9093 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9094 uint8_t ArgMode; 9095 9096 // Decide which area this value should be read from. 9097 // TODO: Implement the AMD64 ABI in its entirety. This simple 9098 // selection mechanism works only for the basic types. 9099 if (ArgVT == MVT::f80) { 9100 llvm_unreachable("va_arg for f80 not yet implemented"); 9101 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9102 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9103 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9104 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9105 } else { 9106 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9107 } 9108 9109 if (ArgMode == 2) { 9110 // Sanity Check: Make sure using fp_offset makes sense. 9111 assert(!getTargetMachine().Options.UseSoftFloat && 9112 !(DAG.getMachineFunction() 9113 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9114 Subtarget->hasSSE1()); 9115 } 9116 9117 // Insert VAARG_64 node into the DAG 9118 // VAARG_64 returns two values: Variable Argument Address, Chain 9119 SmallVector<SDValue, 11> InstOps; 9120 InstOps.push_back(Chain); 9121 InstOps.push_back(SrcPtr); 9122 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9123 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9124 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9125 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9126 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9127 VTs, &InstOps[0], InstOps.size(), 9128 MVT::i64, 9129 MachinePointerInfo(SV), 9130 /*Align=*/0, 9131 /*Volatile=*/false, 9132 /*ReadMem=*/true, 9133 /*WriteMem=*/true); 9134 Chain = VAARG.getValue(1); 9135 9136 // Load the next argument and return it 9137 return DAG.getLoad(ArgVT, dl, 9138 Chain, 9139 VAARG, 9140 MachinePointerInfo(), 9141 false, false, false, 0); 9142} 9143 9144SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9145 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9146 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9147 SDValue Chain = Op.getOperand(0); 9148 SDValue DstPtr = Op.getOperand(1); 9149 SDValue SrcPtr = Op.getOperand(2); 9150 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9151 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9152 DebugLoc DL = Op.getDebugLoc(); 9153 9154 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9155 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9156 false, 9157 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9158} 9159 9160SDValue 9161X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9162 DebugLoc dl = Op.getDebugLoc(); 9163 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9164 switch (IntNo) { 9165 default: return SDValue(); // Don't custom lower most intrinsics. 9166 // Comparison intrinsics. 9167 case Intrinsic::x86_sse_comieq_ss: 9168 case Intrinsic::x86_sse_comilt_ss: 9169 case Intrinsic::x86_sse_comile_ss: 9170 case Intrinsic::x86_sse_comigt_ss: 9171 case Intrinsic::x86_sse_comige_ss: 9172 case Intrinsic::x86_sse_comineq_ss: 9173 case Intrinsic::x86_sse_ucomieq_ss: 9174 case Intrinsic::x86_sse_ucomilt_ss: 9175 case Intrinsic::x86_sse_ucomile_ss: 9176 case Intrinsic::x86_sse_ucomigt_ss: 9177 case Intrinsic::x86_sse_ucomige_ss: 9178 case Intrinsic::x86_sse_ucomineq_ss: 9179 case Intrinsic::x86_sse2_comieq_sd: 9180 case Intrinsic::x86_sse2_comilt_sd: 9181 case Intrinsic::x86_sse2_comile_sd: 9182 case Intrinsic::x86_sse2_comigt_sd: 9183 case Intrinsic::x86_sse2_comige_sd: 9184 case Intrinsic::x86_sse2_comineq_sd: 9185 case Intrinsic::x86_sse2_ucomieq_sd: 9186 case Intrinsic::x86_sse2_ucomilt_sd: 9187 case Intrinsic::x86_sse2_ucomile_sd: 9188 case Intrinsic::x86_sse2_ucomigt_sd: 9189 case Intrinsic::x86_sse2_ucomige_sd: 9190 case Intrinsic::x86_sse2_ucomineq_sd: { 9191 unsigned Opc = 0; 9192 ISD::CondCode CC = ISD::SETCC_INVALID; 9193 switch (IntNo) { 9194 default: break; 9195 case Intrinsic::x86_sse_comieq_ss: 9196 case Intrinsic::x86_sse2_comieq_sd: 9197 Opc = X86ISD::COMI; 9198 CC = ISD::SETEQ; 9199 break; 9200 case Intrinsic::x86_sse_comilt_ss: 9201 case Intrinsic::x86_sse2_comilt_sd: 9202 Opc = X86ISD::COMI; 9203 CC = ISD::SETLT; 9204 break; 9205 case Intrinsic::x86_sse_comile_ss: 9206 case Intrinsic::x86_sse2_comile_sd: 9207 Opc = X86ISD::COMI; 9208 CC = ISD::SETLE; 9209 break; 9210 case Intrinsic::x86_sse_comigt_ss: 9211 case Intrinsic::x86_sse2_comigt_sd: 9212 Opc = X86ISD::COMI; 9213 CC = ISD::SETGT; 9214 break; 9215 case Intrinsic::x86_sse_comige_ss: 9216 case Intrinsic::x86_sse2_comige_sd: 9217 Opc = X86ISD::COMI; 9218 CC = ISD::SETGE; 9219 break; 9220 case Intrinsic::x86_sse_comineq_ss: 9221 case Intrinsic::x86_sse2_comineq_sd: 9222 Opc = X86ISD::COMI; 9223 CC = ISD::SETNE; 9224 break; 9225 case Intrinsic::x86_sse_ucomieq_ss: 9226 case Intrinsic::x86_sse2_ucomieq_sd: 9227 Opc = X86ISD::UCOMI; 9228 CC = ISD::SETEQ; 9229 break; 9230 case Intrinsic::x86_sse_ucomilt_ss: 9231 case Intrinsic::x86_sse2_ucomilt_sd: 9232 Opc = X86ISD::UCOMI; 9233 CC = ISD::SETLT; 9234 break; 9235 case Intrinsic::x86_sse_ucomile_ss: 9236 case Intrinsic::x86_sse2_ucomile_sd: 9237 Opc = X86ISD::UCOMI; 9238 CC = ISD::SETLE; 9239 break; 9240 case Intrinsic::x86_sse_ucomigt_ss: 9241 case Intrinsic::x86_sse2_ucomigt_sd: 9242 Opc = X86ISD::UCOMI; 9243 CC = ISD::SETGT; 9244 break; 9245 case Intrinsic::x86_sse_ucomige_ss: 9246 case Intrinsic::x86_sse2_ucomige_sd: 9247 Opc = X86ISD::UCOMI; 9248 CC = ISD::SETGE; 9249 break; 9250 case Intrinsic::x86_sse_ucomineq_ss: 9251 case Intrinsic::x86_sse2_ucomineq_sd: 9252 Opc = X86ISD::UCOMI; 9253 CC = ISD::SETNE; 9254 break; 9255 } 9256 9257 SDValue LHS = Op.getOperand(1); 9258 SDValue RHS = Op.getOperand(2); 9259 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9260 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9261 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9262 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9263 DAG.getConstant(X86CC, MVT::i8), Cond); 9264 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9265 } 9266 // Arithmetic intrinsics. 9267 case Intrinsic::x86_sse3_hadd_ps: 9268 case Intrinsic::x86_sse3_hadd_pd: 9269 case Intrinsic::x86_avx_hadd_ps_256: 9270 case Intrinsic::x86_avx_hadd_pd_256: 9271 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9272 Op.getOperand(1), Op.getOperand(2)); 9273 case Intrinsic::x86_sse3_hsub_ps: 9274 case Intrinsic::x86_sse3_hsub_pd: 9275 case Intrinsic::x86_avx_hsub_ps_256: 9276 case Intrinsic::x86_avx_hsub_pd_256: 9277 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9278 Op.getOperand(1), Op.getOperand(2)); 9279 case Intrinsic::x86_avx2_psllv_d: 9280 case Intrinsic::x86_avx2_psllv_q: 9281 case Intrinsic::x86_avx2_psllv_d_256: 9282 case Intrinsic::x86_avx2_psllv_q_256: 9283 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9284 Op.getOperand(1), Op.getOperand(2)); 9285 case Intrinsic::x86_avx2_psrlv_d: 9286 case Intrinsic::x86_avx2_psrlv_q: 9287 case Intrinsic::x86_avx2_psrlv_d_256: 9288 case Intrinsic::x86_avx2_psrlv_q_256: 9289 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9290 Op.getOperand(1), Op.getOperand(2)); 9291 case Intrinsic::x86_avx2_psrav_d: 9292 case Intrinsic::x86_avx2_psrav_d_256: 9293 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9294 Op.getOperand(1), Op.getOperand(2)); 9295 9296 // ptest and testp intrinsics. The intrinsic these come from are designed to 9297 // return an integer value, not just an instruction so lower it to the ptest 9298 // or testp pattern and a setcc for the result. 9299 case Intrinsic::x86_sse41_ptestz: 9300 case Intrinsic::x86_sse41_ptestc: 9301 case Intrinsic::x86_sse41_ptestnzc: 9302 case Intrinsic::x86_avx_ptestz_256: 9303 case Intrinsic::x86_avx_ptestc_256: 9304 case Intrinsic::x86_avx_ptestnzc_256: 9305 case Intrinsic::x86_avx_vtestz_ps: 9306 case Intrinsic::x86_avx_vtestc_ps: 9307 case Intrinsic::x86_avx_vtestnzc_ps: 9308 case Intrinsic::x86_avx_vtestz_pd: 9309 case Intrinsic::x86_avx_vtestc_pd: 9310 case Intrinsic::x86_avx_vtestnzc_pd: 9311 case Intrinsic::x86_avx_vtestz_ps_256: 9312 case Intrinsic::x86_avx_vtestc_ps_256: 9313 case Intrinsic::x86_avx_vtestnzc_ps_256: 9314 case Intrinsic::x86_avx_vtestz_pd_256: 9315 case Intrinsic::x86_avx_vtestc_pd_256: 9316 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9317 bool IsTestPacked = false; 9318 unsigned X86CC = 0; 9319 switch (IntNo) { 9320 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9321 case Intrinsic::x86_avx_vtestz_ps: 9322 case Intrinsic::x86_avx_vtestz_pd: 9323 case Intrinsic::x86_avx_vtestz_ps_256: 9324 case Intrinsic::x86_avx_vtestz_pd_256: 9325 IsTestPacked = true; // Fallthrough 9326 case Intrinsic::x86_sse41_ptestz: 9327 case Intrinsic::x86_avx_ptestz_256: 9328 // ZF = 1 9329 X86CC = X86::COND_E; 9330 break; 9331 case Intrinsic::x86_avx_vtestc_ps: 9332 case Intrinsic::x86_avx_vtestc_pd: 9333 case Intrinsic::x86_avx_vtestc_ps_256: 9334 case Intrinsic::x86_avx_vtestc_pd_256: 9335 IsTestPacked = true; // Fallthrough 9336 case Intrinsic::x86_sse41_ptestc: 9337 case Intrinsic::x86_avx_ptestc_256: 9338 // CF = 1 9339 X86CC = X86::COND_B; 9340 break; 9341 case Intrinsic::x86_avx_vtestnzc_ps: 9342 case Intrinsic::x86_avx_vtestnzc_pd: 9343 case Intrinsic::x86_avx_vtestnzc_ps_256: 9344 case Intrinsic::x86_avx_vtestnzc_pd_256: 9345 IsTestPacked = true; // Fallthrough 9346 case Intrinsic::x86_sse41_ptestnzc: 9347 case Intrinsic::x86_avx_ptestnzc_256: 9348 // ZF and CF = 0 9349 X86CC = X86::COND_A; 9350 break; 9351 } 9352 9353 SDValue LHS = Op.getOperand(1); 9354 SDValue RHS = Op.getOperand(2); 9355 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9356 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9357 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9358 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9359 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9360 } 9361 9362 // Fix vector shift instructions where the last operand is a non-immediate 9363 // i32 value. 9364 case Intrinsic::x86_avx2_pslli_w: 9365 case Intrinsic::x86_avx2_pslli_d: 9366 case Intrinsic::x86_avx2_pslli_q: 9367 case Intrinsic::x86_avx2_psrli_w: 9368 case Intrinsic::x86_avx2_psrli_d: 9369 case Intrinsic::x86_avx2_psrli_q: 9370 case Intrinsic::x86_avx2_psrai_w: 9371 case Intrinsic::x86_avx2_psrai_d: 9372 case Intrinsic::x86_sse2_pslli_w: 9373 case Intrinsic::x86_sse2_pslli_d: 9374 case Intrinsic::x86_sse2_pslli_q: 9375 case Intrinsic::x86_sse2_psrli_w: 9376 case Intrinsic::x86_sse2_psrli_d: 9377 case Intrinsic::x86_sse2_psrli_q: 9378 case Intrinsic::x86_sse2_psrai_w: 9379 case Intrinsic::x86_sse2_psrai_d: 9380 case Intrinsic::x86_mmx_pslli_w: 9381 case Intrinsic::x86_mmx_pslli_d: 9382 case Intrinsic::x86_mmx_pslli_q: 9383 case Intrinsic::x86_mmx_psrli_w: 9384 case Intrinsic::x86_mmx_psrli_d: 9385 case Intrinsic::x86_mmx_psrli_q: 9386 case Intrinsic::x86_mmx_psrai_w: 9387 case Intrinsic::x86_mmx_psrai_d: { 9388 SDValue ShAmt = Op.getOperand(2); 9389 if (isa<ConstantSDNode>(ShAmt)) 9390 return SDValue(); 9391 9392 unsigned NewIntNo = 0; 9393 EVT ShAmtVT = MVT::v4i32; 9394 switch (IntNo) { 9395 case Intrinsic::x86_sse2_pslli_w: 9396 NewIntNo = Intrinsic::x86_sse2_psll_w; 9397 break; 9398 case Intrinsic::x86_sse2_pslli_d: 9399 NewIntNo = Intrinsic::x86_sse2_psll_d; 9400 break; 9401 case Intrinsic::x86_sse2_pslli_q: 9402 NewIntNo = Intrinsic::x86_sse2_psll_q; 9403 break; 9404 case Intrinsic::x86_sse2_psrli_w: 9405 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9406 break; 9407 case Intrinsic::x86_sse2_psrli_d: 9408 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9409 break; 9410 case Intrinsic::x86_sse2_psrli_q: 9411 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9412 break; 9413 case Intrinsic::x86_sse2_psrai_w: 9414 NewIntNo = Intrinsic::x86_sse2_psra_w; 9415 break; 9416 case Intrinsic::x86_sse2_psrai_d: 9417 NewIntNo = Intrinsic::x86_sse2_psra_d; 9418 break; 9419 case Intrinsic::x86_avx2_pslli_w: 9420 NewIntNo = Intrinsic::x86_avx2_psll_w; 9421 break; 9422 case Intrinsic::x86_avx2_pslli_d: 9423 NewIntNo = Intrinsic::x86_avx2_psll_d; 9424 break; 9425 case Intrinsic::x86_avx2_pslli_q: 9426 NewIntNo = Intrinsic::x86_avx2_psll_q; 9427 break; 9428 case Intrinsic::x86_avx2_psrli_w: 9429 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9430 break; 9431 case Intrinsic::x86_avx2_psrli_d: 9432 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9433 break; 9434 case Intrinsic::x86_avx2_psrli_q: 9435 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9436 break; 9437 case Intrinsic::x86_avx2_psrai_w: 9438 NewIntNo = Intrinsic::x86_avx2_psra_w; 9439 break; 9440 case Intrinsic::x86_avx2_psrai_d: 9441 NewIntNo = Intrinsic::x86_avx2_psra_d; 9442 break; 9443 default: { 9444 ShAmtVT = MVT::v2i32; 9445 switch (IntNo) { 9446 case Intrinsic::x86_mmx_pslli_w: 9447 NewIntNo = Intrinsic::x86_mmx_psll_w; 9448 break; 9449 case Intrinsic::x86_mmx_pslli_d: 9450 NewIntNo = Intrinsic::x86_mmx_psll_d; 9451 break; 9452 case Intrinsic::x86_mmx_pslli_q: 9453 NewIntNo = Intrinsic::x86_mmx_psll_q; 9454 break; 9455 case Intrinsic::x86_mmx_psrli_w: 9456 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9457 break; 9458 case Intrinsic::x86_mmx_psrli_d: 9459 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9460 break; 9461 case Intrinsic::x86_mmx_psrli_q: 9462 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9463 break; 9464 case Intrinsic::x86_mmx_psrai_w: 9465 NewIntNo = Intrinsic::x86_mmx_psra_w; 9466 break; 9467 case Intrinsic::x86_mmx_psrai_d: 9468 NewIntNo = Intrinsic::x86_mmx_psra_d; 9469 break; 9470 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9471 } 9472 break; 9473 } 9474 } 9475 9476 // The vector shift intrinsics with scalars uses 32b shift amounts but 9477 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9478 // to be zero. 9479 SDValue ShOps[4]; 9480 ShOps[0] = ShAmt; 9481 ShOps[1] = DAG.getConstant(0, MVT::i32); 9482 if (ShAmtVT == MVT::v4i32) { 9483 ShOps[2] = DAG.getUNDEF(MVT::i32); 9484 ShOps[3] = DAG.getUNDEF(MVT::i32); 9485 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9486 } else { 9487 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9488// FIXME this must be lowered to get rid of the invalid type. 9489 } 9490 9491 EVT VT = Op.getValueType(); 9492 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9493 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9494 DAG.getConstant(NewIntNo, MVT::i32), 9495 Op.getOperand(1), ShAmt); 9496 } 9497 } 9498} 9499 9500SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9501 SelectionDAG &DAG) const { 9502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9503 MFI->setReturnAddressIsTaken(true); 9504 9505 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9506 DebugLoc dl = Op.getDebugLoc(); 9507 9508 if (Depth > 0) { 9509 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9510 SDValue Offset = 9511 DAG.getConstant(TD->getPointerSize(), 9512 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9513 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9514 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9515 FrameAddr, Offset), 9516 MachinePointerInfo(), false, false, false, 0); 9517 } 9518 9519 // Just load the return address. 9520 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9521 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9522 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9523} 9524 9525SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9526 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9527 MFI->setFrameAddressIsTaken(true); 9528 9529 EVT VT = Op.getValueType(); 9530 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9531 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9532 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9533 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9534 while (Depth--) 9535 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9536 MachinePointerInfo(), 9537 false, false, false, 0); 9538 return FrameAddr; 9539} 9540 9541SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9542 SelectionDAG &DAG) const { 9543 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9544} 9545 9546SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9547 MachineFunction &MF = DAG.getMachineFunction(); 9548 SDValue Chain = Op.getOperand(0); 9549 SDValue Offset = Op.getOperand(1); 9550 SDValue Handler = Op.getOperand(2); 9551 DebugLoc dl = Op.getDebugLoc(); 9552 9553 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9554 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9555 getPointerTy()); 9556 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9557 9558 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9559 DAG.getIntPtrConstant(TD->getPointerSize())); 9560 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9561 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9562 false, false, 0); 9563 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9564 MF.getRegInfo().addLiveOut(StoreAddrReg); 9565 9566 return DAG.getNode(X86ISD::EH_RETURN, dl, 9567 MVT::Other, 9568 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9569} 9570 9571SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9572 SelectionDAG &DAG) const { 9573 return Op.getOperand(0); 9574} 9575 9576SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9577 SelectionDAG &DAG) const { 9578 SDValue Root = Op.getOperand(0); 9579 SDValue Trmp = Op.getOperand(1); // trampoline 9580 SDValue FPtr = Op.getOperand(2); // nested function 9581 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9582 DebugLoc dl = Op.getDebugLoc(); 9583 9584 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9585 9586 if (Subtarget->is64Bit()) { 9587 SDValue OutChains[6]; 9588 9589 // Large code-model. 9590 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9591 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9592 9593 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9594 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9595 9596 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9597 9598 // Load the pointer to the nested function into R11. 9599 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9600 SDValue Addr = Trmp; 9601 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9602 Addr, MachinePointerInfo(TrmpAddr), 9603 false, false, 0); 9604 9605 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9606 DAG.getConstant(2, MVT::i64)); 9607 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9608 MachinePointerInfo(TrmpAddr, 2), 9609 false, false, 2); 9610 9611 // Load the 'nest' parameter value into R10. 9612 // R10 is specified in X86CallingConv.td 9613 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9614 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9615 DAG.getConstant(10, MVT::i64)); 9616 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9617 Addr, MachinePointerInfo(TrmpAddr, 10), 9618 false, false, 0); 9619 9620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9621 DAG.getConstant(12, MVT::i64)); 9622 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9623 MachinePointerInfo(TrmpAddr, 12), 9624 false, false, 2); 9625 9626 // Jump to the nested function. 9627 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9629 DAG.getConstant(20, MVT::i64)); 9630 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9631 Addr, MachinePointerInfo(TrmpAddr, 20), 9632 false, false, 0); 9633 9634 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9635 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9636 DAG.getConstant(22, MVT::i64)); 9637 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9638 MachinePointerInfo(TrmpAddr, 22), 9639 false, false, 0); 9640 9641 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9642 } else { 9643 const Function *Func = 9644 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9645 CallingConv::ID CC = Func->getCallingConv(); 9646 unsigned NestReg; 9647 9648 switch (CC) { 9649 default: 9650 llvm_unreachable("Unsupported calling convention"); 9651 case CallingConv::C: 9652 case CallingConv::X86_StdCall: { 9653 // Pass 'nest' parameter in ECX. 9654 // Must be kept in sync with X86CallingConv.td 9655 NestReg = X86::ECX; 9656 9657 // Check that ECX wasn't needed by an 'inreg' parameter. 9658 FunctionType *FTy = Func->getFunctionType(); 9659 const AttrListPtr &Attrs = Func->getAttributes(); 9660 9661 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9662 unsigned InRegCount = 0; 9663 unsigned Idx = 1; 9664 9665 for (FunctionType::param_iterator I = FTy->param_begin(), 9666 E = FTy->param_end(); I != E; ++I, ++Idx) 9667 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9668 // FIXME: should only count parameters that are lowered to integers. 9669 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9670 9671 if (InRegCount > 2) { 9672 report_fatal_error("Nest register in use - reduce number of inreg" 9673 " parameters!"); 9674 } 9675 } 9676 break; 9677 } 9678 case CallingConv::X86_FastCall: 9679 case CallingConv::X86_ThisCall: 9680 case CallingConv::Fast: 9681 // Pass 'nest' parameter in EAX. 9682 // Must be kept in sync with X86CallingConv.td 9683 NestReg = X86::EAX; 9684 break; 9685 } 9686 9687 SDValue OutChains[4]; 9688 SDValue Addr, Disp; 9689 9690 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9691 DAG.getConstant(10, MVT::i32)); 9692 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9693 9694 // This is storing the opcode for MOV32ri. 9695 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9696 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9697 OutChains[0] = DAG.getStore(Root, dl, 9698 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9699 Trmp, MachinePointerInfo(TrmpAddr), 9700 false, false, 0); 9701 9702 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9703 DAG.getConstant(1, MVT::i32)); 9704 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9705 MachinePointerInfo(TrmpAddr, 1), 9706 false, false, 1); 9707 9708 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9709 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9710 DAG.getConstant(5, MVT::i32)); 9711 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9712 MachinePointerInfo(TrmpAddr, 5), 9713 false, false, 1); 9714 9715 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9716 DAG.getConstant(6, MVT::i32)); 9717 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9718 MachinePointerInfo(TrmpAddr, 6), 9719 false, false, 1); 9720 9721 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9722 } 9723} 9724 9725SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9726 SelectionDAG &DAG) const { 9727 /* 9728 The rounding mode is in bits 11:10 of FPSR, and has the following 9729 settings: 9730 00 Round to nearest 9731 01 Round to -inf 9732 10 Round to +inf 9733 11 Round to 0 9734 9735 FLT_ROUNDS, on the other hand, expects the following: 9736 -1 Undefined 9737 0 Round to 0 9738 1 Round to nearest 9739 2 Round to +inf 9740 3 Round to -inf 9741 9742 To perform the conversion, we do: 9743 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9744 */ 9745 9746 MachineFunction &MF = DAG.getMachineFunction(); 9747 const TargetMachine &TM = MF.getTarget(); 9748 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9749 unsigned StackAlignment = TFI.getStackAlignment(); 9750 EVT VT = Op.getValueType(); 9751 DebugLoc DL = Op.getDebugLoc(); 9752 9753 // Save FP Control Word to stack slot 9754 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9755 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9756 9757 9758 MachineMemOperand *MMO = 9759 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9760 MachineMemOperand::MOStore, 2, 2); 9761 9762 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9763 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9764 DAG.getVTList(MVT::Other), 9765 Ops, 2, MVT::i16, MMO); 9766 9767 // Load FP Control Word from stack slot 9768 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9769 MachinePointerInfo(), false, false, false, 0); 9770 9771 // Transform as necessary 9772 SDValue CWD1 = 9773 DAG.getNode(ISD::SRL, DL, MVT::i16, 9774 DAG.getNode(ISD::AND, DL, MVT::i16, 9775 CWD, DAG.getConstant(0x800, MVT::i16)), 9776 DAG.getConstant(11, MVT::i8)); 9777 SDValue CWD2 = 9778 DAG.getNode(ISD::SRL, DL, MVT::i16, 9779 DAG.getNode(ISD::AND, DL, MVT::i16, 9780 CWD, DAG.getConstant(0x400, MVT::i16)), 9781 DAG.getConstant(9, MVT::i8)); 9782 9783 SDValue RetVal = 9784 DAG.getNode(ISD::AND, DL, MVT::i16, 9785 DAG.getNode(ISD::ADD, DL, MVT::i16, 9786 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9787 DAG.getConstant(1, MVT::i16)), 9788 DAG.getConstant(3, MVT::i16)); 9789 9790 9791 return DAG.getNode((VT.getSizeInBits() < 16 ? 9792 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9793} 9794 9795SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9796 EVT VT = Op.getValueType(); 9797 EVT OpVT = VT; 9798 unsigned NumBits = VT.getSizeInBits(); 9799 DebugLoc dl = Op.getDebugLoc(); 9800 9801 Op = Op.getOperand(0); 9802 if (VT == MVT::i8) { 9803 // Zero extend to i32 since there is not an i8 bsr. 9804 OpVT = MVT::i32; 9805 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9806 } 9807 9808 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9809 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9810 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9811 9812 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9813 SDValue Ops[] = { 9814 Op, 9815 DAG.getConstant(NumBits+NumBits-1, OpVT), 9816 DAG.getConstant(X86::COND_E, MVT::i8), 9817 Op.getValue(1) 9818 }; 9819 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9820 9821 // Finally xor with NumBits-1. 9822 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9823 9824 if (VT == MVT::i8) 9825 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9826 return Op; 9827} 9828 9829SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9830 SelectionDAG &DAG) const { 9831 EVT VT = Op.getValueType(); 9832 EVT OpVT = VT; 9833 unsigned NumBits = VT.getSizeInBits(); 9834 DebugLoc dl = Op.getDebugLoc(); 9835 9836 Op = Op.getOperand(0); 9837 if (VT == MVT::i8) { 9838 // Zero extend to i32 since there is not an i8 bsr. 9839 OpVT = MVT::i32; 9840 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9841 } 9842 9843 // Issue a bsr (scan bits in reverse). 9844 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9845 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9846 9847 // And xor with NumBits-1. 9848 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9849 9850 if (VT == MVT::i8) 9851 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9852 return Op; 9853} 9854 9855SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9856 EVT VT = Op.getValueType(); 9857 unsigned NumBits = VT.getSizeInBits(); 9858 DebugLoc dl = Op.getDebugLoc(); 9859 Op = Op.getOperand(0); 9860 9861 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9862 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9863 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9864 9865 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9866 SDValue Ops[] = { 9867 Op, 9868 DAG.getConstant(NumBits, VT), 9869 DAG.getConstant(X86::COND_E, MVT::i8), 9870 Op.getValue(1) 9871 }; 9872 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 9873} 9874 9875// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9876// ones, and then concatenate the result back. 9877static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9878 EVT VT = Op.getValueType(); 9879 9880 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9881 "Unsupported value type for operation"); 9882 9883 int NumElems = VT.getVectorNumElements(); 9884 DebugLoc dl = Op.getDebugLoc(); 9885 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9886 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9887 9888 // Extract the LHS vectors 9889 SDValue LHS = Op.getOperand(0); 9890 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9891 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9892 9893 // Extract the RHS vectors 9894 SDValue RHS = Op.getOperand(1); 9895 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9896 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9897 9898 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9899 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9900 9901 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9902 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9903 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9904} 9905 9906SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9907 assert(Op.getValueType().getSizeInBits() == 256 && 9908 Op.getValueType().isInteger() && 9909 "Only handle AVX 256-bit vector integer operation"); 9910 return Lower256IntArith(Op, DAG); 9911} 9912 9913SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9914 assert(Op.getValueType().getSizeInBits() == 256 && 9915 Op.getValueType().isInteger() && 9916 "Only handle AVX 256-bit vector integer operation"); 9917 return Lower256IntArith(Op, DAG); 9918} 9919 9920SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9921 EVT VT = Op.getValueType(); 9922 9923 // Decompose 256-bit ops into smaller 128-bit ops. 9924 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 9925 return Lower256IntArith(Op, DAG); 9926 9927 DebugLoc dl = Op.getDebugLoc(); 9928 9929 SDValue A = Op.getOperand(0); 9930 SDValue B = Op.getOperand(1); 9931 9932 if (VT == MVT::v4i64) { 9933 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 9934 9935 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 9936 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 9937 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 9938 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 9939 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 9940 // 9941 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 9942 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 9943 // return AloBlo + AloBhi + AhiBlo; 9944 9945 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9946 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9947 A, DAG.getConstant(32, MVT::i32)); 9948 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9949 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9950 B, DAG.getConstant(32, MVT::i32)); 9951 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9952 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9953 A, B); 9954 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9955 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9956 A, Bhi); 9957 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9958 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9959 Ahi, B); 9960 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9961 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9962 AloBhi, DAG.getConstant(32, MVT::i32)); 9963 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9964 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9965 AhiBlo, DAG.getConstant(32, MVT::i32)); 9966 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9967 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9968 return Res; 9969 } 9970 9971 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9972 9973 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9974 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9975 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9976 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9977 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9978 // 9979 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9980 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9981 // return AloBlo + AloBhi + AhiBlo; 9982 9983 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9984 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9985 A, DAG.getConstant(32, MVT::i32)); 9986 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9987 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9988 B, DAG.getConstant(32, MVT::i32)); 9989 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9990 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9991 A, B); 9992 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9993 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9994 A, Bhi); 9995 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9996 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9997 Ahi, B); 9998 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9999 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10000 AloBhi, DAG.getConstant(32, MVT::i32)); 10001 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10002 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10003 AhiBlo, DAG.getConstant(32, MVT::i32)); 10004 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10005 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10006 return Res; 10007} 10008 10009SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10010 10011 EVT VT = Op.getValueType(); 10012 DebugLoc dl = Op.getDebugLoc(); 10013 SDValue R = Op.getOperand(0); 10014 SDValue Amt = Op.getOperand(1); 10015 LLVMContext *Context = DAG.getContext(); 10016 10017 if (!Subtarget->hasSSE2()) 10018 return SDValue(); 10019 10020 // Optimize shl/srl/sra with constant shift amount. 10021 if (isSplatVector(Amt.getNode())) { 10022 SDValue SclrAmt = Amt->getOperand(0); 10023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10024 uint64_t ShiftAmt = C->getZExtValue(); 10025 10026 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) { 10027 // Make a large shift. 10028 SDValue SHL = 10029 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10030 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10031 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10032 // Zero out the rightmost bits. 10033 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10034 MVT::i8)); 10035 return DAG.getNode(ISD::AND, dl, VT, SHL, 10036 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10037 } 10038 10039 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 10040 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10041 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10042 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10043 10044 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 10045 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10046 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10047 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10048 10049 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 10050 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10051 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10052 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10053 10054 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) { 10055 // Make a large shift. 10056 SDValue SRL = 10057 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10058 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10059 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10060 // Zero out the leftmost bits. 10061 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10062 MVT::i8)); 10063 return DAG.getNode(ISD::AND, dl, VT, SRL, 10064 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10065 } 10066 10067 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 10068 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10069 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10070 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10071 10072 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 10073 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10074 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10075 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10076 10077 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 10078 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10079 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10080 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10081 10082 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 10083 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10084 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10085 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10086 10087 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 10088 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10089 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10090 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10091 10092 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) { 10093 if (ShiftAmt == 7) { 10094 // R s>> 7 === R s< 0 10095 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true, 10096 /* HasAVX2 */false, DAG, dl); 10097 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10098 } 10099 10100 // R s>> a === ((R u>> a) ^ m) - m 10101 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10102 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10103 MVT::i8)); 10104 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10105 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10106 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10107 return Res; 10108 } 10109 10110 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10111 if (Op.getOpcode() == ISD::SHL) { 10112 // Make a large shift. 10113 SDValue SHL = 10114 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10115 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 10116 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10117 // Zero out the rightmost bits. 10118 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10119 MVT::i8)); 10120 return DAG.getNode(ISD::AND, dl, VT, SHL, 10121 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10122 } 10123 if (Op.getOpcode() == ISD::SRL) { 10124 // Make a large shift. 10125 SDValue SRL = 10126 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10127 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 10128 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10129 // Zero out the leftmost bits. 10130 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10131 MVT::i8)); 10132 return DAG.getNode(ISD::AND, dl, VT, SRL, 10133 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10134 } 10135 if (Op.getOpcode() == ISD::SRA) { 10136 if (ShiftAmt == 7) { 10137 // R s>> 7 === R s< 0 10138 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, 10139 true /* HasAVX2 */, DAG, dl); 10140 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10141 } 10142 10143 // R s>> a === ((R u>> a) ^ m) - m 10144 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10145 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10146 MVT::i8)); 10147 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10148 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10149 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10150 return Res; 10151 } 10152 } 10153 } 10154 } 10155 10156 // Lower SHL with variable shift amount. 10157 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10158 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10159 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10160 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 10161 10162 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10163 10164 std::vector<Constant*> CV(4, CI); 10165 Constant *C = ConstantVector::get(CV); 10166 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10167 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10168 MachinePointerInfo::getConstantPool(), 10169 false, false, false, 16); 10170 10171 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10172 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10173 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10174 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10175 } 10176 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10177 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10178 10179 // a = a << 5; 10180 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10181 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10182 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 10183 10184 // Turn 'a' into a mask suitable for VSELECT 10185 SDValue VSelM = DAG.getConstant(0x80, VT); 10186 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10187 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10188 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10189 OpVSel, VSelM); 10190 10191 SDValue CM1 = DAG.getConstant(0x0f, VT); 10192 SDValue CM2 = DAG.getConstant(0x3f, VT); 10193 10194 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10195 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10196 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10197 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10198 DAG.getConstant(4, MVT::i32)); 10199 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10200 10201 // a += a 10202 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10203 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10204 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10205 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10206 OpVSel, VSelM); 10207 10208 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10209 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10210 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10211 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10212 DAG.getConstant(2, MVT::i32)); 10213 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10214 10215 // a += a 10216 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10217 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10218 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10219 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10220 OpVSel, VSelM); 10221 10222 // return VSELECT(r, r+r, a); 10223 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10224 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10225 return R; 10226 } 10227 10228 // Decompose 256-bit shifts into smaller 128-bit shifts. 10229 if (VT.getSizeInBits() == 256) { 10230 int NumElems = VT.getVectorNumElements(); 10231 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10232 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10233 10234 // Extract the two vectors 10235 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10236 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10237 DAG, dl); 10238 10239 // Recreate the shift amount vectors 10240 SDValue Amt1, Amt2; 10241 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10242 // Constant shift amount 10243 SmallVector<SDValue, 4> Amt1Csts; 10244 SmallVector<SDValue, 4> Amt2Csts; 10245 for (int i = 0; i < NumElems/2; ++i) 10246 Amt1Csts.push_back(Amt->getOperand(i)); 10247 for (int i = NumElems/2; i < NumElems; ++i) 10248 Amt2Csts.push_back(Amt->getOperand(i)); 10249 10250 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10251 &Amt1Csts[0], NumElems/2); 10252 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10253 &Amt2Csts[0], NumElems/2); 10254 } else { 10255 // Variable shift amount 10256 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10257 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10258 DAG, dl); 10259 } 10260 10261 // Issue new vector shifts for the smaller types 10262 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10263 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10264 10265 // Concatenate the result back 10266 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10267 } 10268 10269 return SDValue(); 10270} 10271 10272SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10273 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10274 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10275 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10276 // has only one use. 10277 SDNode *N = Op.getNode(); 10278 SDValue LHS = N->getOperand(0); 10279 SDValue RHS = N->getOperand(1); 10280 unsigned BaseOp = 0; 10281 unsigned Cond = 0; 10282 DebugLoc DL = Op.getDebugLoc(); 10283 switch (Op.getOpcode()) { 10284 default: llvm_unreachable("Unknown ovf instruction!"); 10285 case ISD::SADDO: 10286 // A subtract of one will be selected as a INC. Note that INC doesn't 10287 // set CF, so we can't do this for UADDO. 10288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10289 if (C->isOne()) { 10290 BaseOp = X86ISD::INC; 10291 Cond = X86::COND_O; 10292 break; 10293 } 10294 BaseOp = X86ISD::ADD; 10295 Cond = X86::COND_O; 10296 break; 10297 case ISD::UADDO: 10298 BaseOp = X86ISD::ADD; 10299 Cond = X86::COND_B; 10300 break; 10301 case ISD::SSUBO: 10302 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10303 // set CF, so we can't do this for USUBO. 10304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10305 if (C->isOne()) { 10306 BaseOp = X86ISD::DEC; 10307 Cond = X86::COND_O; 10308 break; 10309 } 10310 BaseOp = X86ISD::SUB; 10311 Cond = X86::COND_O; 10312 break; 10313 case ISD::USUBO: 10314 BaseOp = X86ISD::SUB; 10315 Cond = X86::COND_B; 10316 break; 10317 case ISD::SMULO: 10318 BaseOp = X86ISD::SMUL; 10319 Cond = X86::COND_O; 10320 break; 10321 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10322 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10323 MVT::i32); 10324 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10325 10326 SDValue SetCC = 10327 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10328 DAG.getConstant(X86::COND_O, MVT::i32), 10329 SDValue(Sum.getNode(), 2)); 10330 10331 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10332 } 10333 } 10334 10335 // Also sets EFLAGS. 10336 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10337 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10338 10339 SDValue SetCC = 10340 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10341 DAG.getConstant(Cond, MVT::i32), 10342 SDValue(Sum.getNode(), 1)); 10343 10344 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10345} 10346 10347SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10348 SelectionDAG &DAG) const { 10349 DebugLoc dl = Op.getDebugLoc(); 10350 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10351 EVT VT = Op.getValueType(); 10352 10353 if (Subtarget->hasSSE2() && VT.isVector()) { 10354 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10355 ExtraVT.getScalarType().getSizeInBits(); 10356 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10357 10358 unsigned SHLIntrinsicsID = 0; 10359 unsigned SRAIntrinsicsID = 0; 10360 switch (VT.getSimpleVT().SimpleTy) { 10361 default: 10362 return SDValue(); 10363 case MVT::v4i32: 10364 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10365 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10366 break; 10367 case MVT::v8i16: 10368 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10369 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10370 break; 10371 case MVT::v8i32: 10372 case MVT::v16i16: 10373 if (!Subtarget->hasAVX()) 10374 return SDValue(); 10375 if (!Subtarget->hasAVX2()) { 10376 // needs to be split 10377 int NumElems = VT.getVectorNumElements(); 10378 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10379 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10380 10381 // Extract the LHS vectors 10382 SDValue LHS = Op.getOperand(0); 10383 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10384 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10385 10386 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10387 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10388 10389 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10390 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10391 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10392 ExtraNumElems/2); 10393 SDValue Extra = DAG.getValueType(ExtraVT); 10394 10395 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10396 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10397 10398 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10399 } 10400 if (VT == MVT::v8i32) { 10401 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d; 10402 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d; 10403 } else { 10404 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w; 10405 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w; 10406 } 10407 } 10408 10409 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10410 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10411 Op.getOperand(0), ShAmt); 10412 10413 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10414 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10415 Tmp1, ShAmt); 10416 } 10417 10418 return SDValue(); 10419} 10420 10421 10422SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10423 DebugLoc dl = Op.getDebugLoc(); 10424 10425 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10426 // There isn't any reason to disable it if the target processor supports it. 10427 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10428 SDValue Chain = Op.getOperand(0); 10429 SDValue Zero = DAG.getConstant(0, MVT::i32); 10430 SDValue Ops[] = { 10431 DAG.getRegister(X86::ESP, MVT::i32), // Base 10432 DAG.getTargetConstant(1, MVT::i8), // Scale 10433 DAG.getRegister(0, MVT::i32), // Index 10434 DAG.getTargetConstant(0, MVT::i32), // Disp 10435 DAG.getRegister(0, MVT::i32), // Segment. 10436 Zero, 10437 Chain 10438 }; 10439 SDNode *Res = 10440 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10441 array_lengthof(Ops)); 10442 return SDValue(Res, 0); 10443 } 10444 10445 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10446 if (!isDev) 10447 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10448 10449 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10450 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10451 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10452 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10453 10454 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10455 if (!Op1 && !Op2 && !Op3 && Op4) 10456 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10457 10458 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10459 if (Op1 && !Op2 && !Op3 && !Op4) 10460 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10461 10462 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10463 // (MFENCE)>; 10464 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10465} 10466 10467SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10468 SelectionDAG &DAG) const { 10469 DebugLoc dl = Op.getDebugLoc(); 10470 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10471 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10472 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10473 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10474 10475 // The only fence that needs an instruction is a sequentially-consistent 10476 // cross-thread fence. 10477 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10478 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10479 // no-sse2). There isn't any reason to disable it if the target processor 10480 // supports it. 10481 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10482 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10483 10484 SDValue Chain = Op.getOperand(0); 10485 SDValue Zero = DAG.getConstant(0, MVT::i32); 10486 SDValue Ops[] = { 10487 DAG.getRegister(X86::ESP, MVT::i32), // Base 10488 DAG.getTargetConstant(1, MVT::i8), // Scale 10489 DAG.getRegister(0, MVT::i32), // Index 10490 DAG.getTargetConstant(0, MVT::i32), // Disp 10491 DAG.getRegister(0, MVT::i32), // Segment. 10492 Zero, 10493 Chain 10494 }; 10495 SDNode *Res = 10496 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10497 array_lengthof(Ops)); 10498 return SDValue(Res, 0); 10499 } 10500 10501 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10502 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10503} 10504 10505 10506SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10507 EVT T = Op.getValueType(); 10508 DebugLoc DL = Op.getDebugLoc(); 10509 unsigned Reg = 0; 10510 unsigned size = 0; 10511 switch(T.getSimpleVT().SimpleTy) { 10512 default: 10513 assert(false && "Invalid value type!"); 10514 case MVT::i8: Reg = X86::AL; size = 1; break; 10515 case MVT::i16: Reg = X86::AX; size = 2; break; 10516 case MVT::i32: Reg = X86::EAX; size = 4; break; 10517 case MVT::i64: 10518 assert(Subtarget->is64Bit() && "Node not type legal!"); 10519 Reg = X86::RAX; size = 8; 10520 break; 10521 } 10522 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10523 Op.getOperand(2), SDValue()); 10524 SDValue Ops[] = { cpIn.getValue(0), 10525 Op.getOperand(1), 10526 Op.getOperand(3), 10527 DAG.getTargetConstant(size, MVT::i8), 10528 cpIn.getValue(1) }; 10529 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10530 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10531 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10532 Ops, 5, T, MMO); 10533 SDValue cpOut = 10534 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10535 return cpOut; 10536} 10537 10538SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10539 SelectionDAG &DAG) const { 10540 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10541 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10542 SDValue TheChain = Op.getOperand(0); 10543 DebugLoc dl = Op.getDebugLoc(); 10544 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10545 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10546 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10547 rax.getValue(2)); 10548 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10549 DAG.getConstant(32, MVT::i8)); 10550 SDValue Ops[] = { 10551 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10552 rdx.getValue(1) 10553 }; 10554 return DAG.getMergeValues(Ops, 2, dl); 10555} 10556 10557SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10558 SelectionDAG &DAG) const { 10559 EVT SrcVT = Op.getOperand(0).getValueType(); 10560 EVT DstVT = Op.getValueType(); 10561 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10562 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10563 assert((DstVT == MVT::i64 || 10564 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10565 "Unexpected custom BITCAST"); 10566 // i64 <=> MMX conversions are Legal. 10567 if (SrcVT==MVT::i64 && DstVT.isVector()) 10568 return Op; 10569 if (DstVT==MVT::i64 && SrcVT.isVector()) 10570 return Op; 10571 // MMX <=> MMX conversions are Legal. 10572 if (SrcVT.isVector() && DstVT.isVector()) 10573 return Op; 10574 // All other conversions need to be expanded. 10575 return SDValue(); 10576} 10577 10578SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10579 SDNode *Node = Op.getNode(); 10580 DebugLoc dl = Node->getDebugLoc(); 10581 EVT T = Node->getValueType(0); 10582 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10583 DAG.getConstant(0, T), Node->getOperand(2)); 10584 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10585 cast<AtomicSDNode>(Node)->getMemoryVT(), 10586 Node->getOperand(0), 10587 Node->getOperand(1), negOp, 10588 cast<AtomicSDNode>(Node)->getSrcValue(), 10589 cast<AtomicSDNode>(Node)->getAlignment(), 10590 cast<AtomicSDNode>(Node)->getOrdering(), 10591 cast<AtomicSDNode>(Node)->getSynchScope()); 10592} 10593 10594static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10595 SDNode *Node = Op.getNode(); 10596 DebugLoc dl = Node->getDebugLoc(); 10597 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10598 10599 // Convert seq_cst store -> xchg 10600 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10601 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10602 // (The only way to get a 16-byte store is cmpxchg16b) 10603 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10604 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10605 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10606 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10607 cast<AtomicSDNode>(Node)->getMemoryVT(), 10608 Node->getOperand(0), 10609 Node->getOperand(1), Node->getOperand(2), 10610 cast<AtomicSDNode>(Node)->getMemOperand(), 10611 cast<AtomicSDNode>(Node)->getOrdering(), 10612 cast<AtomicSDNode>(Node)->getSynchScope()); 10613 return Swap.getValue(1); 10614 } 10615 // Other atomic stores have a simple pattern. 10616 return Op; 10617} 10618 10619static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10620 EVT VT = Op.getNode()->getValueType(0); 10621 10622 // Let legalize expand this if it isn't a legal type yet. 10623 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10624 return SDValue(); 10625 10626 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10627 10628 unsigned Opc; 10629 bool ExtraOp = false; 10630 switch (Op.getOpcode()) { 10631 default: assert(0 && "Invalid code"); 10632 case ISD::ADDC: Opc = X86ISD::ADD; break; 10633 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10634 case ISD::SUBC: Opc = X86ISD::SUB; break; 10635 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10636 } 10637 10638 if (!ExtraOp) 10639 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10640 Op.getOperand(1)); 10641 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10642 Op.getOperand(1), Op.getOperand(2)); 10643} 10644 10645/// LowerOperation - Provide custom lowering hooks for some operations. 10646/// 10647SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10648 switch (Op.getOpcode()) { 10649 default: llvm_unreachable("Should not custom lower this!"); 10650 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10651 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10652 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10653 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10654 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10655 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10656 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10657 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10658 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10659 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10660 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10661 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10662 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10663 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10664 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10665 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10666 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10667 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10668 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10669 case ISD::SHL_PARTS: 10670 case ISD::SRA_PARTS: 10671 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10672 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10673 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10674 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10675 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10676 case ISD::FABS: return LowerFABS(Op, DAG); 10677 case ISD::FNEG: return LowerFNEG(Op, DAG); 10678 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10679 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10680 case ISD::SETCC: return LowerSETCC(Op, DAG); 10681 case ISD::SELECT: return LowerSELECT(Op, DAG); 10682 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10683 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10684 case ISD::VASTART: return LowerVASTART(Op, DAG); 10685 case ISD::VAARG: return LowerVAARG(Op, DAG); 10686 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10687 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10688 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10689 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10690 case ISD::FRAME_TO_ARGS_OFFSET: 10691 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10692 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10693 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10694 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10695 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10696 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10697 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10698 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10699 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10700 case ISD::MUL: return LowerMUL(Op, DAG); 10701 case ISD::SRA: 10702 case ISD::SRL: 10703 case ISD::SHL: return LowerShift(Op, DAG); 10704 case ISD::SADDO: 10705 case ISD::UADDO: 10706 case ISD::SSUBO: 10707 case ISD::USUBO: 10708 case ISD::SMULO: 10709 case ISD::UMULO: return LowerXALUO(Op, DAG); 10710 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10711 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10712 case ISD::ADDC: 10713 case ISD::ADDE: 10714 case ISD::SUBC: 10715 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10716 case ISD::ADD: return LowerADD(Op, DAG); 10717 case ISD::SUB: return LowerSUB(Op, DAG); 10718 } 10719} 10720 10721static void ReplaceATOMIC_LOAD(SDNode *Node, 10722 SmallVectorImpl<SDValue> &Results, 10723 SelectionDAG &DAG) { 10724 DebugLoc dl = Node->getDebugLoc(); 10725 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10726 10727 // Convert wide load -> cmpxchg8b/cmpxchg16b 10728 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10729 // (The only way to get a 16-byte load is cmpxchg16b) 10730 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10731 SDValue Zero = DAG.getConstant(0, VT); 10732 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10733 Node->getOperand(0), 10734 Node->getOperand(1), Zero, Zero, 10735 cast<AtomicSDNode>(Node)->getMemOperand(), 10736 cast<AtomicSDNode>(Node)->getOrdering(), 10737 cast<AtomicSDNode>(Node)->getSynchScope()); 10738 Results.push_back(Swap.getValue(0)); 10739 Results.push_back(Swap.getValue(1)); 10740} 10741 10742void X86TargetLowering:: 10743ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10744 SelectionDAG &DAG, unsigned NewOp) const { 10745 DebugLoc dl = Node->getDebugLoc(); 10746 assert (Node->getValueType(0) == MVT::i64 && 10747 "Only know how to expand i64 atomics"); 10748 10749 SDValue Chain = Node->getOperand(0); 10750 SDValue In1 = Node->getOperand(1); 10751 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10752 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10753 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10754 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10755 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10756 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10757 SDValue Result = 10758 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10759 cast<MemSDNode>(Node)->getMemOperand()); 10760 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10761 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10762 Results.push_back(Result.getValue(2)); 10763} 10764 10765/// ReplaceNodeResults - Replace a node with an illegal result type 10766/// with a new node built out of custom code. 10767void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10768 SmallVectorImpl<SDValue>&Results, 10769 SelectionDAG &DAG) const { 10770 DebugLoc dl = N->getDebugLoc(); 10771 switch (N->getOpcode()) { 10772 default: 10773 assert(false && "Do not know how to custom type legalize this operation!"); 10774 return; 10775 case ISD::SIGN_EXTEND_INREG: 10776 case ISD::ADDC: 10777 case ISD::ADDE: 10778 case ISD::SUBC: 10779 case ISD::SUBE: 10780 // We don't want to expand or promote these. 10781 return; 10782 case ISD::FP_TO_SINT: { 10783 std::pair<SDValue,SDValue> Vals = 10784 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10785 SDValue FIST = Vals.first, StackSlot = Vals.second; 10786 if (FIST.getNode() != 0) { 10787 EVT VT = N->getValueType(0); 10788 // Return a load from the stack slot. 10789 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10790 MachinePointerInfo(), 10791 false, false, false, 0)); 10792 } 10793 return; 10794 } 10795 case ISD::READCYCLECOUNTER: { 10796 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10797 SDValue TheChain = N->getOperand(0); 10798 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10799 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10800 rd.getValue(1)); 10801 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10802 eax.getValue(2)); 10803 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10804 SDValue Ops[] = { eax, edx }; 10805 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10806 Results.push_back(edx.getValue(1)); 10807 return; 10808 } 10809 case ISD::ATOMIC_CMP_SWAP: { 10810 EVT T = N->getValueType(0); 10811 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10812 bool Regs64bit = T == MVT::i128; 10813 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10814 SDValue cpInL, cpInH; 10815 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10816 DAG.getConstant(0, HalfT)); 10817 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10818 DAG.getConstant(1, HalfT)); 10819 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10820 Regs64bit ? X86::RAX : X86::EAX, 10821 cpInL, SDValue()); 10822 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10823 Regs64bit ? X86::RDX : X86::EDX, 10824 cpInH, cpInL.getValue(1)); 10825 SDValue swapInL, swapInH; 10826 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10827 DAG.getConstant(0, HalfT)); 10828 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10829 DAG.getConstant(1, HalfT)); 10830 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10831 Regs64bit ? X86::RBX : X86::EBX, 10832 swapInL, cpInH.getValue(1)); 10833 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10834 Regs64bit ? X86::RCX : X86::ECX, 10835 swapInH, swapInL.getValue(1)); 10836 SDValue Ops[] = { swapInH.getValue(0), 10837 N->getOperand(1), 10838 swapInH.getValue(1) }; 10839 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10840 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10841 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10842 X86ISD::LCMPXCHG8_DAG; 10843 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10844 Ops, 3, T, MMO); 10845 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10846 Regs64bit ? X86::RAX : X86::EAX, 10847 HalfT, Result.getValue(1)); 10848 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10849 Regs64bit ? X86::RDX : X86::EDX, 10850 HalfT, cpOutL.getValue(2)); 10851 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10852 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10853 Results.push_back(cpOutH.getValue(1)); 10854 return; 10855 } 10856 case ISD::ATOMIC_LOAD_ADD: 10857 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10858 return; 10859 case ISD::ATOMIC_LOAD_AND: 10860 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10861 return; 10862 case ISD::ATOMIC_LOAD_NAND: 10863 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10864 return; 10865 case ISD::ATOMIC_LOAD_OR: 10866 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10867 return; 10868 case ISD::ATOMIC_LOAD_SUB: 10869 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10870 return; 10871 case ISD::ATOMIC_LOAD_XOR: 10872 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10873 return; 10874 case ISD::ATOMIC_SWAP: 10875 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10876 return; 10877 case ISD::ATOMIC_LOAD: 10878 ReplaceATOMIC_LOAD(N, Results, DAG); 10879 } 10880} 10881 10882const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10883 switch (Opcode) { 10884 default: return NULL; 10885 case X86ISD::BSF: return "X86ISD::BSF"; 10886 case X86ISD::BSR: return "X86ISD::BSR"; 10887 case X86ISD::SHLD: return "X86ISD::SHLD"; 10888 case X86ISD::SHRD: return "X86ISD::SHRD"; 10889 case X86ISD::FAND: return "X86ISD::FAND"; 10890 case X86ISD::FOR: return "X86ISD::FOR"; 10891 case X86ISD::FXOR: return "X86ISD::FXOR"; 10892 case X86ISD::FSRL: return "X86ISD::FSRL"; 10893 case X86ISD::FILD: return "X86ISD::FILD"; 10894 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10895 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10896 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10897 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10898 case X86ISD::FLD: return "X86ISD::FLD"; 10899 case X86ISD::FST: return "X86ISD::FST"; 10900 case X86ISD::CALL: return "X86ISD::CALL"; 10901 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10902 case X86ISD::BT: return "X86ISD::BT"; 10903 case X86ISD::CMP: return "X86ISD::CMP"; 10904 case X86ISD::COMI: return "X86ISD::COMI"; 10905 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10906 case X86ISD::SETCC: return "X86ISD::SETCC"; 10907 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10908 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10909 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10910 case X86ISD::CMOV: return "X86ISD::CMOV"; 10911 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10912 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10913 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10914 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10915 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10916 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10917 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10918 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10919 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10920 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10921 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10922 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10923 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10924 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10925 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10926 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10927 case X86ISD::HADD: return "X86ISD::HADD"; 10928 case X86ISD::HSUB: return "X86ISD::HSUB"; 10929 case X86ISD::FHADD: return "X86ISD::FHADD"; 10930 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10931 case X86ISD::FMAX: return "X86ISD::FMAX"; 10932 case X86ISD::FMIN: return "X86ISD::FMIN"; 10933 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10934 case X86ISD::FRCP: return "X86ISD::FRCP"; 10935 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10936 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10937 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10938 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10939 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10940 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10941 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10942 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10943 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10944 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10945 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10946 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10947 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10948 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10949 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10950 case X86ISD::VSHL: return "X86ISD::VSHL"; 10951 case X86ISD::VSRL: return "X86ISD::VSRL"; 10952 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10953 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10954 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10955 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10956 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10957 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10958 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10959 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10960 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10961 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10962 case X86ISD::ADD: return "X86ISD::ADD"; 10963 case X86ISD::SUB: return "X86ISD::SUB"; 10964 case X86ISD::ADC: return "X86ISD::ADC"; 10965 case X86ISD::SBB: return "X86ISD::SBB"; 10966 case X86ISD::SMUL: return "X86ISD::SMUL"; 10967 case X86ISD::UMUL: return "X86ISD::UMUL"; 10968 case X86ISD::INC: return "X86ISD::INC"; 10969 case X86ISD::DEC: return "X86ISD::DEC"; 10970 case X86ISD::OR: return "X86ISD::OR"; 10971 case X86ISD::XOR: return "X86ISD::XOR"; 10972 case X86ISD::AND: return "X86ISD::AND"; 10973 case X86ISD::ANDN: return "X86ISD::ANDN"; 10974 case X86ISD::BLSI: return "X86ISD::BLSI"; 10975 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 10976 case X86ISD::BLSR: return "X86ISD::BLSR"; 10977 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10978 case X86ISD::PTEST: return "X86ISD::PTEST"; 10979 case X86ISD::TESTP: return "X86ISD::TESTP"; 10980 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10981 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10982 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10983 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10984 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10985 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10986 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 10987 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10988 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10989 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10990 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10991 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10992 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10993 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10994 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10995 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10996 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10997 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10998 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10999 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11000 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11001 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11002 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11003 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11004 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11005 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11006 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11007 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11008 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11009 } 11010} 11011 11012// isLegalAddressingMode - Return true if the addressing mode represented 11013// by AM is legal for this target, for a load/store of the specified type. 11014bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11015 Type *Ty) const { 11016 // X86 supports extremely general addressing modes. 11017 CodeModel::Model M = getTargetMachine().getCodeModel(); 11018 Reloc::Model R = getTargetMachine().getRelocationModel(); 11019 11020 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11021 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11022 return false; 11023 11024 if (AM.BaseGV) { 11025 unsigned GVFlags = 11026 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11027 11028 // If a reference to this global requires an extra load, we can't fold it. 11029 if (isGlobalStubReference(GVFlags)) 11030 return false; 11031 11032 // If BaseGV requires a register for the PIC base, we cannot also have a 11033 // BaseReg specified. 11034 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11035 return false; 11036 11037 // If lower 4G is not available, then we must use rip-relative addressing. 11038 if ((M != CodeModel::Small || R != Reloc::Static) && 11039 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11040 return false; 11041 } 11042 11043 switch (AM.Scale) { 11044 case 0: 11045 case 1: 11046 case 2: 11047 case 4: 11048 case 8: 11049 // These scales always work. 11050 break; 11051 case 3: 11052 case 5: 11053 case 9: 11054 // These scales are formed with basereg+scalereg. Only accept if there is 11055 // no basereg yet. 11056 if (AM.HasBaseReg) 11057 return false; 11058 break; 11059 default: // Other stuff never works. 11060 return false; 11061 } 11062 11063 return true; 11064} 11065 11066 11067bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11068 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11069 return false; 11070 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11071 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11072 if (NumBits1 <= NumBits2) 11073 return false; 11074 return true; 11075} 11076 11077bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11078 if (!VT1.isInteger() || !VT2.isInteger()) 11079 return false; 11080 unsigned NumBits1 = VT1.getSizeInBits(); 11081 unsigned NumBits2 = VT2.getSizeInBits(); 11082 if (NumBits1 <= NumBits2) 11083 return false; 11084 return true; 11085} 11086 11087bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11088 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11089 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11090} 11091 11092bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11093 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11094 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11095} 11096 11097bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11098 // i16 instructions are longer (0x66 prefix) and potentially slower. 11099 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11100} 11101 11102/// isShuffleMaskLegal - Targets can use this to indicate that they only 11103/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11104/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11105/// are assumed to be legal. 11106bool 11107X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11108 EVT VT) const { 11109 // Very little shuffling can be done for 64-bit vectors right now. 11110 if (VT.getSizeInBits() == 64) 11111 return false; 11112 11113 // FIXME: pshufb, blends, shifts. 11114 return (VT.getVectorNumElements() == 2 || 11115 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11116 isMOVLMask(M, VT) || 11117 isSHUFPMask(M, VT) || 11118 isPSHUFDMask(M, VT) || 11119 isPSHUFHWMask(M, VT) || 11120 isPSHUFLWMask(M, VT) || 11121 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 11122 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11123 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11124 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11125 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11126} 11127 11128bool 11129X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11130 EVT VT) const { 11131 unsigned NumElts = VT.getVectorNumElements(); 11132 // FIXME: This collection of masks seems suspect. 11133 if (NumElts == 2) 11134 return true; 11135 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11136 return (isMOVLMask(Mask, VT) || 11137 isCommutedMOVLMask(Mask, VT, true) || 11138 isSHUFPMask(Mask, VT) || 11139 isSHUFPMask(Mask, VT, /* Commuted */ true)); 11140 } 11141 return false; 11142} 11143 11144//===----------------------------------------------------------------------===// 11145// X86 Scheduler Hooks 11146//===----------------------------------------------------------------------===// 11147 11148// private utility function 11149MachineBasicBlock * 11150X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11151 MachineBasicBlock *MBB, 11152 unsigned regOpc, 11153 unsigned immOpc, 11154 unsigned LoadOpc, 11155 unsigned CXchgOpc, 11156 unsigned notOpc, 11157 unsigned EAXreg, 11158 TargetRegisterClass *RC, 11159 bool invSrc) const { 11160 // For the atomic bitwise operator, we generate 11161 // thisMBB: 11162 // newMBB: 11163 // ld t1 = [bitinstr.addr] 11164 // op t2 = t1, [bitinstr.val] 11165 // mov EAX = t1 11166 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11167 // bz newMBB 11168 // fallthrough -->nextMBB 11169 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11170 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11171 MachineFunction::iterator MBBIter = MBB; 11172 ++MBBIter; 11173 11174 /// First build the CFG 11175 MachineFunction *F = MBB->getParent(); 11176 MachineBasicBlock *thisMBB = MBB; 11177 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11178 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11179 F->insert(MBBIter, newMBB); 11180 F->insert(MBBIter, nextMBB); 11181 11182 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11183 nextMBB->splice(nextMBB->begin(), thisMBB, 11184 llvm::next(MachineBasicBlock::iterator(bInstr)), 11185 thisMBB->end()); 11186 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11187 11188 // Update thisMBB to fall through to newMBB 11189 thisMBB->addSuccessor(newMBB); 11190 11191 // newMBB jumps to itself and fall through to nextMBB 11192 newMBB->addSuccessor(nextMBB); 11193 newMBB->addSuccessor(newMBB); 11194 11195 // Insert instructions into newMBB based on incoming instruction 11196 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11197 "unexpected number of operands"); 11198 DebugLoc dl = bInstr->getDebugLoc(); 11199 MachineOperand& destOper = bInstr->getOperand(0); 11200 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11201 int numArgs = bInstr->getNumOperands() - 1; 11202 for (int i=0; i < numArgs; ++i) 11203 argOpers[i] = &bInstr->getOperand(i+1); 11204 11205 // x86 address has 4 operands: base, index, scale, and displacement 11206 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11207 int valArgIndx = lastAddrIndx + 1; 11208 11209 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11210 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11211 for (int i=0; i <= lastAddrIndx; ++i) 11212 (*MIB).addOperand(*argOpers[i]); 11213 11214 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11215 if (invSrc) { 11216 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11217 } 11218 else 11219 tt = t1; 11220 11221 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11222 assert((argOpers[valArgIndx]->isReg() || 11223 argOpers[valArgIndx]->isImm()) && 11224 "invalid operand"); 11225 if (argOpers[valArgIndx]->isReg()) 11226 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11227 else 11228 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11229 MIB.addReg(tt); 11230 (*MIB).addOperand(*argOpers[valArgIndx]); 11231 11232 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11233 MIB.addReg(t1); 11234 11235 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11236 for (int i=0; i <= lastAddrIndx; ++i) 11237 (*MIB).addOperand(*argOpers[i]); 11238 MIB.addReg(t2); 11239 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11240 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11241 bInstr->memoperands_end()); 11242 11243 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11244 MIB.addReg(EAXreg); 11245 11246 // insert branch 11247 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11248 11249 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11250 return nextMBB; 11251} 11252 11253// private utility function: 64 bit atomics on 32 bit host. 11254MachineBasicBlock * 11255X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11256 MachineBasicBlock *MBB, 11257 unsigned regOpcL, 11258 unsigned regOpcH, 11259 unsigned immOpcL, 11260 unsigned immOpcH, 11261 bool invSrc) const { 11262 // For the atomic bitwise operator, we generate 11263 // thisMBB (instructions are in pairs, except cmpxchg8b) 11264 // ld t1,t2 = [bitinstr.addr] 11265 // newMBB: 11266 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11267 // op t5, t6 <- out1, out2, [bitinstr.val] 11268 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11269 // mov ECX, EBX <- t5, t6 11270 // mov EAX, EDX <- t1, t2 11271 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11272 // mov t3, t4 <- EAX, EDX 11273 // bz newMBB 11274 // result in out1, out2 11275 // fallthrough -->nextMBB 11276 11277 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11278 const unsigned LoadOpc = X86::MOV32rm; 11279 const unsigned NotOpc = X86::NOT32r; 11280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11281 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11282 MachineFunction::iterator MBBIter = MBB; 11283 ++MBBIter; 11284 11285 /// First build the CFG 11286 MachineFunction *F = MBB->getParent(); 11287 MachineBasicBlock *thisMBB = MBB; 11288 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11289 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11290 F->insert(MBBIter, newMBB); 11291 F->insert(MBBIter, nextMBB); 11292 11293 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11294 nextMBB->splice(nextMBB->begin(), thisMBB, 11295 llvm::next(MachineBasicBlock::iterator(bInstr)), 11296 thisMBB->end()); 11297 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11298 11299 // Update thisMBB to fall through to newMBB 11300 thisMBB->addSuccessor(newMBB); 11301 11302 // newMBB jumps to itself and fall through to nextMBB 11303 newMBB->addSuccessor(nextMBB); 11304 newMBB->addSuccessor(newMBB); 11305 11306 DebugLoc dl = bInstr->getDebugLoc(); 11307 // Insert instructions into newMBB based on incoming instruction 11308 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11309 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11310 "unexpected number of operands"); 11311 MachineOperand& dest1Oper = bInstr->getOperand(0); 11312 MachineOperand& dest2Oper = bInstr->getOperand(1); 11313 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11314 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11315 argOpers[i] = &bInstr->getOperand(i+2); 11316 11317 // We use some of the operands multiple times, so conservatively just 11318 // clear any kill flags that might be present. 11319 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11320 argOpers[i]->setIsKill(false); 11321 } 11322 11323 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11324 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11325 11326 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11327 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11328 for (int i=0; i <= lastAddrIndx; ++i) 11329 (*MIB).addOperand(*argOpers[i]); 11330 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11331 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11332 // add 4 to displacement. 11333 for (int i=0; i <= lastAddrIndx-2; ++i) 11334 (*MIB).addOperand(*argOpers[i]); 11335 MachineOperand newOp3 = *(argOpers[3]); 11336 if (newOp3.isImm()) 11337 newOp3.setImm(newOp3.getImm()+4); 11338 else 11339 newOp3.setOffset(newOp3.getOffset()+4); 11340 (*MIB).addOperand(newOp3); 11341 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11342 11343 // t3/4 are defined later, at the bottom of the loop 11344 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11345 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11346 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11347 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11348 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11349 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11350 11351 // The subsequent operations should be using the destination registers of 11352 //the PHI instructions. 11353 if (invSrc) { 11354 t1 = F->getRegInfo().createVirtualRegister(RC); 11355 t2 = F->getRegInfo().createVirtualRegister(RC); 11356 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11357 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11358 } else { 11359 t1 = dest1Oper.getReg(); 11360 t2 = dest2Oper.getReg(); 11361 } 11362 11363 int valArgIndx = lastAddrIndx + 1; 11364 assert((argOpers[valArgIndx]->isReg() || 11365 argOpers[valArgIndx]->isImm()) && 11366 "invalid operand"); 11367 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11368 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11369 if (argOpers[valArgIndx]->isReg()) 11370 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11371 else 11372 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11373 if (regOpcL != X86::MOV32rr) 11374 MIB.addReg(t1); 11375 (*MIB).addOperand(*argOpers[valArgIndx]); 11376 assert(argOpers[valArgIndx + 1]->isReg() == 11377 argOpers[valArgIndx]->isReg()); 11378 assert(argOpers[valArgIndx + 1]->isImm() == 11379 argOpers[valArgIndx]->isImm()); 11380 if (argOpers[valArgIndx + 1]->isReg()) 11381 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11382 else 11383 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11384 if (regOpcH != X86::MOV32rr) 11385 MIB.addReg(t2); 11386 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11387 11388 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11389 MIB.addReg(t1); 11390 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11391 MIB.addReg(t2); 11392 11393 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11394 MIB.addReg(t5); 11395 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11396 MIB.addReg(t6); 11397 11398 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11399 for (int i=0; i <= lastAddrIndx; ++i) 11400 (*MIB).addOperand(*argOpers[i]); 11401 11402 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11403 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11404 bInstr->memoperands_end()); 11405 11406 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11407 MIB.addReg(X86::EAX); 11408 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11409 MIB.addReg(X86::EDX); 11410 11411 // insert branch 11412 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11413 11414 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11415 return nextMBB; 11416} 11417 11418// private utility function 11419MachineBasicBlock * 11420X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11421 MachineBasicBlock *MBB, 11422 unsigned cmovOpc) const { 11423 // For the atomic min/max operator, we generate 11424 // thisMBB: 11425 // newMBB: 11426 // ld t1 = [min/max.addr] 11427 // mov t2 = [min/max.val] 11428 // cmp t1, t2 11429 // cmov[cond] t2 = t1 11430 // mov EAX = t1 11431 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11432 // bz newMBB 11433 // fallthrough -->nextMBB 11434 // 11435 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11436 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11437 MachineFunction::iterator MBBIter = MBB; 11438 ++MBBIter; 11439 11440 /// First build the CFG 11441 MachineFunction *F = MBB->getParent(); 11442 MachineBasicBlock *thisMBB = MBB; 11443 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11444 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11445 F->insert(MBBIter, newMBB); 11446 F->insert(MBBIter, nextMBB); 11447 11448 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11449 nextMBB->splice(nextMBB->begin(), thisMBB, 11450 llvm::next(MachineBasicBlock::iterator(mInstr)), 11451 thisMBB->end()); 11452 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11453 11454 // Update thisMBB to fall through to newMBB 11455 thisMBB->addSuccessor(newMBB); 11456 11457 // newMBB jumps to newMBB and fall through to nextMBB 11458 newMBB->addSuccessor(nextMBB); 11459 newMBB->addSuccessor(newMBB); 11460 11461 DebugLoc dl = mInstr->getDebugLoc(); 11462 // Insert instructions into newMBB based on incoming instruction 11463 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11464 "unexpected number of operands"); 11465 MachineOperand& destOper = mInstr->getOperand(0); 11466 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11467 int numArgs = mInstr->getNumOperands() - 1; 11468 for (int i=0; i < numArgs; ++i) 11469 argOpers[i] = &mInstr->getOperand(i+1); 11470 11471 // x86 address has 4 operands: base, index, scale, and displacement 11472 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11473 int valArgIndx = lastAddrIndx + 1; 11474 11475 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11476 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11477 for (int i=0; i <= lastAddrIndx; ++i) 11478 (*MIB).addOperand(*argOpers[i]); 11479 11480 // We only support register and immediate values 11481 assert((argOpers[valArgIndx]->isReg() || 11482 argOpers[valArgIndx]->isImm()) && 11483 "invalid operand"); 11484 11485 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11486 if (argOpers[valArgIndx]->isReg()) 11487 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11488 else 11489 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11490 (*MIB).addOperand(*argOpers[valArgIndx]); 11491 11492 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11493 MIB.addReg(t1); 11494 11495 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11496 MIB.addReg(t1); 11497 MIB.addReg(t2); 11498 11499 // Generate movc 11500 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11501 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11502 MIB.addReg(t2); 11503 MIB.addReg(t1); 11504 11505 // Cmp and exchange if none has modified the memory location 11506 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11507 for (int i=0; i <= lastAddrIndx; ++i) 11508 (*MIB).addOperand(*argOpers[i]); 11509 MIB.addReg(t3); 11510 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11511 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11512 mInstr->memoperands_end()); 11513 11514 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11515 MIB.addReg(X86::EAX); 11516 11517 // insert branch 11518 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11519 11520 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11521 return nextMBB; 11522} 11523 11524// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11525// or XMM0_V32I8 in AVX all of this code can be replaced with that 11526// in the .td file. 11527MachineBasicBlock * 11528X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11529 unsigned numArgs, bool memArg) const { 11530 assert(Subtarget->hasSSE42() && 11531 "Target must have SSE4.2 or AVX features enabled"); 11532 11533 DebugLoc dl = MI->getDebugLoc(); 11534 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11535 unsigned Opc; 11536 if (!Subtarget->hasAVX()) { 11537 if (memArg) 11538 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11539 else 11540 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11541 } else { 11542 if (memArg) 11543 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11544 else 11545 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11546 } 11547 11548 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11549 for (unsigned i = 0; i < numArgs; ++i) { 11550 MachineOperand &Op = MI->getOperand(i+1); 11551 if (!(Op.isReg() && Op.isImplicit())) 11552 MIB.addOperand(Op); 11553 } 11554 BuildMI(*BB, MI, dl, 11555 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11556 MI->getOperand(0).getReg()) 11557 .addReg(X86::XMM0); 11558 11559 MI->eraseFromParent(); 11560 return BB; 11561} 11562 11563MachineBasicBlock * 11564X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11565 DebugLoc dl = MI->getDebugLoc(); 11566 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11567 11568 // Address into RAX/EAX, other two args into ECX, EDX. 11569 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11570 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11571 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11572 for (int i = 0; i < X86::AddrNumOperands; ++i) 11573 MIB.addOperand(MI->getOperand(i)); 11574 11575 unsigned ValOps = X86::AddrNumOperands; 11576 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11577 .addReg(MI->getOperand(ValOps).getReg()); 11578 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11579 .addReg(MI->getOperand(ValOps+1).getReg()); 11580 11581 // The instruction doesn't actually take any operands though. 11582 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11583 11584 MI->eraseFromParent(); // The pseudo is gone now. 11585 return BB; 11586} 11587 11588MachineBasicBlock * 11589X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11590 DebugLoc dl = MI->getDebugLoc(); 11591 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11592 11593 // First arg in ECX, the second in EAX. 11594 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11595 .addReg(MI->getOperand(0).getReg()); 11596 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11597 .addReg(MI->getOperand(1).getReg()); 11598 11599 // The instruction doesn't actually take any operands though. 11600 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11601 11602 MI->eraseFromParent(); // The pseudo is gone now. 11603 return BB; 11604} 11605 11606MachineBasicBlock * 11607X86TargetLowering::EmitVAARG64WithCustomInserter( 11608 MachineInstr *MI, 11609 MachineBasicBlock *MBB) const { 11610 // Emit va_arg instruction on X86-64. 11611 11612 // Operands to this pseudo-instruction: 11613 // 0 ) Output : destination address (reg) 11614 // 1-5) Input : va_list address (addr, i64mem) 11615 // 6 ) ArgSize : Size (in bytes) of vararg type 11616 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11617 // 8 ) Align : Alignment of type 11618 // 9 ) EFLAGS (implicit-def) 11619 11620 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11621 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11622 11623 unsigned DestReg = MI->getOperand(0).getReg(); 11624 MachineOperand &Base = MI->getOperand(1); 11625 MachineOperand &Scale = MI->getOperand(2); 11626 MachineOperand &Index = MI->getOperand(3); 11627 MachineOperand &Disp = MI->getOperand(4); 11628 MachineOperand &Segment = MI->getOperand(5); 11629 unsigned ArgSize = MI->getOperand(6).getImm(); 11630 unsigned ArgMode = MI->getOperand(7).getImm(); 11631 unsigned Align = MI->getOperand(8).getImm(); 11632 11633 // Memory Reference 11634 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11635 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11636 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11637 11638 // Machine Information 11639 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11640 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11641 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11642 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11643 DebugLoc DL = MI->getDebugLoc(); 11644 11645 // struct va_list { 11646 // i32 gp_offset 11647 // i32 fp_offset 11648 // i64 overflow_area (address) 11649 // i64 reg_save_area (address) 11650 // } 11651 // sizeof(va_list) = 24 11652 // alignment(va_list) = 8 11653 11654 unsigned TotalNumIntRegs = 6; 11655 unsigned TotalNumXMMRegs = 8; 11656 bool UseGPOffset = (ArgMode == 1); 11657 bool UseFPOffset = (ArgMode == 2); 11658 unsigned MaxOffset = TotalNumIntRegs * 8 + 11659 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11660 11661 /* Align ArgSize to a multiple of 8 */ 11662 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11663 bool NeedsAlign = (Align > 8); 11664 11665 MachineBasicBlock *thisMBB = MBB; 11666 MachineBasicBlock *overflowMBB; 11667 MachineBasicBlock *offsetMBB; 11668 MachineBasicBlock *endMBB; 11669 11670 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11671 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11672 unsigned OffsetReg = 0; 11673 11674 if (!UseGPOffset && !UseFPOffset) { 11675 // If we only pull from the overflow region, we don't create a branch. 11676 // We don't need to alter control flow. 11677 OffsetDestReg = 0; // unused 11678 OverflowDestReg = DestReg; 11679 11680 offsetMBB = NULL; 11681 overflowMBB = thisMBB; 11682 endMBB = thisMBB; 11683 } else { 11684 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11685 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11686 // If not, pull from overflow_area. (branch to overflowMBB) 11687 // 11688 // thisMBB 11689 // | . 11690 // | . 11691 // offsetMBB overflowMBB 11692 // | . 11693 // | . 11694 // endMBB 11695 11696 // Registers for the PHI in endMBB 11697 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11698 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11699 11700 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11701 MachineFunction *MF = MBB->getParent(); 11702 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11703 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11704 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11705 11706 MachineFunction::iterator MBBIter = MBB; 11707 ++MBBIter; 11708 11709 // Insert the new basic blocks 11710 MF->insert(MBBIter, offsetMBB); 11711 MF->insert(MBBIter, overflowMBB); 11712 MF->insert(MBBIter, endMBB); 11713 11714 // Transfer the remainder of MBB and its successor edges to endMBB. 11715 endMBB->splice(endMBB->begin(), thisMBB, 11716 llvm::next(MachineBasicBlock::iterator(MI)), 11717 thisMBB->end()); 11718 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11719 11720 // Make offsetMBB and overflowMBB successors of thisMBB 11721 thisMBB->addSuccessor(offsetMBB); 11722 thisMBB->addSuccessor(overflowMBB); 11723 11724 // endMBB is a successor of both offsetMBB and overflowMBB 11725 offsetMBB->addSuccessor(endMBB); 11726 overflowMBB->addSuccessor(endMBB); 11727 11728 // Load the offset value into a register 11729 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11730 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11731 .addOperand(Base) 11732 .addOperand(Scale) 11733 .addOperand(Index) 11734 .addDisp(Disp, UseFPOffset ? 4 : 0) 11735 .addOperand(Segment) 11736 .setMemRefs(MMOBegin, MMOEnd); 11737 11738 // Check if there is enough room left to pull this argument. 11739 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11740 .addReg(OffsetReg) 11741 .addImm(MaxOffset + 8 - ArgSizeA8); 11742 11743 // Branch to "overflowMBB" if offset >= max 11744 // Fall through to "offsetMBB" otherwise 11745 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11746 .addMBB(overflowMBB); 11747 } 11748 11749 // In offsetMBB, emit code to use the reg_save_area. 11750 if (offsetMBB) { 11751 assert(OffsetReg != 0); 11752 11753 // Read the reg_save_area address. 11754 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11755 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11756 .addOperand(Base) 11757 .addOperand(Scale) 11758 .addOperand(Index) 11759 .addDisp(Disp, 16) 11760 .addOperand(Segment) 11761 .setMemRefs(MMOBegin, MMOEnd); 11762 11763 // Zero-extend the offset 11764 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11765 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11766 .addImm(0) 11767 .addReg(OffsetReg) 11768 .addImm(X86::sub_32bit); 11769 11770 // Add the offset to the reg_save_area to get the final address. 11771 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11772 .addReg(OffsetReg64) 11773 .addReg(RegSaveReg); 11774 11775 // Compute the offset for the next argument 11776 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11777 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11778 .addReg(OffsetReg) 11779 .addImm(UseFPOffset ? 16 : 8); 11780 11781 // Store it back into the va_list. 11782 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11783 .addOperand(Base) 11784 .addOperand(Scale) 11785 .addOperand(Index) 11786 .addDisp(Disp, UseFPOffset ? 4 : 0) 11787 .addOperand(Segment) 11788 .addReg(NextOffsetReg) 11789 .setMemRefs(MMOBegin, MMOEnd); 11790 11791 // Jump to endMBB 11792 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11793 .addMBB(endMBB); 11794 } 11795 11796 // 11797 // Emit code to use overflow area 11798 // 11799 11800 // Load the overflow_area address into a register. 11801 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11802 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11803 .addOperand(Base) 11804 .addOperand(Scale) 11805 .addOperand(Index) 11806 .addDisp(Disp, 8) 11807 .addOperand(Segment) 11808 .setMemRefs(MMOBegin, MMOEnd); 11809 11810 // If we need to align it, do so. Otherwise, just copy the address 11811 // to OverflowDestReg. 11812 if (NeedsAlign) { 11813 // Align the overflow address 11814 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11815 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11816 11817 // aligned_addr = (addr + (align-1)) & ~(align-1) 11818 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11819 .addReg(OverflowAddrReg) 11820 .addImm(Align-1); 11821 11822 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11823 .addReg(TmpReg) 11824 .addImm(~(uint64_t)(Align-1)); 11825 } else { 11826 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11827 .addReg(OverflowAddrReg); 11828 } 11829 11830 // Compute the next overflow address after this argument. 11831 // (the overflow address should be kept 8-byte aligned) 11832 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11833 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11834 .addReg(OverflowDestReg) 11835 .addImm(ArgSizeA8); 11836 11837 // Store the new overflow address. 11838 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11839 .addOperand(Base) 11840 .addOperand(Scale) 11841 .addOperand(Index) 11842 .addDisp(Disp, 8) 11843 .addOperand(Segment) 11844 .addReg(NextAddrReg) 11845 .setMemRefs(MMOBegin, MMOEnd); 11846 11847 // If we branched, emit the PHI to the front of endMBB. 11848 if (offsetMBB) { 11849 BuildMI(*endMBB, endMBB->begin(), DL, 11850 TII->get(X86::PHI), DestReg) 11851 .addReg(OffsetDestReg).addMBB(offsetMBB) 11852 .addReg(OverflowDestReg).addMBB(overflowMBB); 11853 } 11854 11855 // Erase the pseudo instruction 11856 MI->eraseFromParent(); 11857 11858 return endMBB; 11859} 11860 11861MachineBasicBlock * 11862X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11863 MachineInstr *MI, 11864 MachineBasicBlock *MBB) const { 11865 // Emit code to save XMM registers to the stack. The ABI says that the 11866 // number of registers to save is given in %al, so it's theoretically 11867 // possible to do an indirect jump trick to avoid saving all of them, 11868 // however this code takes a simpler approach and just executes all 11869 // of the stores if %al is non-zero. It's less code, and it's probably 11870 // easier on the hardware branch predictor, and stores aren't all that 11871 // expensive anyway. 11872 11873 // Create the new basic blocks. One block contains all the XMM stores, 11874 // and one block is the final destination regardless of whether any 11875 // stores were performed. 11876 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11877 MachineFunction *F = MBB->getParent(); 11878 MachineFunction::iterator MBBIter = MBB; 11879 ++MBBIter; 11880 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11881 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11882 F->insert(MBBIter, XMMSaveMBB); 11883 F->insert(MBBIter, EndMBB); 11884 11885 // Transfer the remainder of MBB and its successor edges to EndMBB. 11886 EndMBB->splice(EndMBB->begin(), MBB, 11887 llvm::next(MachineBasicBlock::iterator(MI)), 11888 MBB->end()); 11889 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11890 11891 // The original block will now fall through to the XMM save block. 11892 MBB->addSuccessor(XMMSaveMBB); 11893 // The XMMSaveMBB will fall through to the end block. 11894 XMMSaveMBB->addSuccessor(EndMBB); 11895 11896 // Now add the instructions. 11897 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11898 DebugLoc DL = MI->getDebugLoc(); 11899 11900 unsigned CountReg = MI->getOperand(0).getReg(); 11901 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11902 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11903 11904 if (!Subtarget->isTargetWin64()) { 11905 // If %al is 0, branch around the XMM save block. 11906 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11907 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11908 MBB->addSuccessor(EndMBB); 11909 } 11910 11911 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11912 // In the XMM save block, save all the XMM argument registers. 11913 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11914 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11915 MachineMemOperand *MMO = 11916 F->getMachineMemOperand( 11917 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11918 MachineMemOperand::MOStore, 11919 /*Size=*/16, /*Align=*/16); 11920 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11921 .addFrameIndex(RegSaveFrameIndex) 11922 .addImm(/*Scale=*/1) 11923 .addReg(/*IndexReg=*/0) 11924 .addImm(/*Disp=*/Offset) 11925 .addReg(/*Segment=*/0) 11926 .addReg(MI->getOperand(i).getReg()) 11927 .addMemOperand(MMO); 11928 } 11929 11930 MI->eraseFromParent(); // The pseudo instruction is gone now. 11931 11932 return EndMBB; 11933} 11934 11935MachineBasicBlock * 11936X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11937 MachineBasicBlock *BB) const { 11938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11939 DebugLoc DL = MI->getDebugLoc(); 11940 11941 // To "insert" a SELECT_CC instruction, we actually have to insert the 11942 // diamond control-flow pattern. The incoming instruction knows the 11943 // destination vreg to set, the condition code register to branch on, the 11944 // true/false values to select between, and a branch opcode to use. 11945 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11946 MachineFunction::iterator It = BB; 11947 ++It; 11948 11949 // thisMBB: 11950 // ... 11951 // TrueVal = ... 11952 // cmpTY ccX, r1, r2 11953 // bCC copy1MBB 11954 // fallthrough --> copy0MBB 11955 MachineBasicBlock *thisMBB = BB; 11956 MachineFunction *F = BB->getParent(); 11957 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11958 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11959 F->insert(It, copy0MBB); 11960 F->insert(It, sinkMBB); 11961 11962 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11963 // live into the sink and copy blocks. 11964 if (!MI->killsRegister(X86::EFLAGS)) { 11965 copy0MBB->addLiveIn(X86::EFLAGS); 11966 sinkMBB->addLiveIn(X86::EFLAGS); 11967 } 11968 11969 // Transfer the remainder of BB and its successor edges to sinkMBB. 11970 sinkMBB->splice(sinkMBB->begin(), BB, 11971 llvm::next(MachineBasicBlock::iterator(MI)), 11972 BB->end()); 11973 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11974 11975 // Add the true and fallthrough blocks as its successors. 11976 BB->addSuccessor(copy0MBB); 11977 BB->addSuccessor(sinkMBB); 11978 11979 // Create the conditional branch instruction. 11980 unsigned Opc = 11981 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11982 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11983 11984 // copy0MBB: 11985 // %FalseValue = ... 11986 // # fallthrough to sinkMBB 11987 copy0MBB->addSuccessor(sinkMBB); 11988 11989 // sinkMBB: 11990 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11991 // ... 11992 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11993 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11994 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11995 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11996 11997 MI->eraseFromParent(); // The pseudo instruction is gone now. 11998 return sinkMBB; 11999} 12000 12001MachineBasicBlock * 12002X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12003 bool Is64Bit) const { 12004 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12005 DebugLoc DL = MI->getDebugLoc(); 12006 MachineFunction *MF = BB->getParent(); 12007 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12008 12009 assert(getTargetMachine().Options.EnableSegmentedStacks); 12010 12011 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12012 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12013 12014 // BB: 12015 // ... [Till the alloca] 12016 // If stacklet is not large enough, jump to mallocMBB 12017 // 12018 // bumpMBB: 12019 // Allocate by subtracting from RSP 12020 // Jump to continueMBB 12021 // 12022 // mallocMBB: 12023 // Allocate by call to runtime 12024 // 12025 // continueMBB: 12026 // ... 12027 // [rest of original BB] 12028 // 12029 12030 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12031 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12032 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12033 12034 MachineRegisterInfo &MRI = MF->getRegInfo(); 12035 const TargetRegisterClass *AddrRegClass = 12036 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12037 12038 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12039 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12040 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12041 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12042 sizeVReg = MI->getOperand(1).getReg(), 12043 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12044 12045 MachineFunction::iterator MBBIter = BB; 12046 ++MBBIter; 12047 12048 MF->insert(MBBIter, bumpMBB); 12049 MF->insert(MBBIter, mallocMBB); 12050 MF->insert(MBBIter, continueMBB); 12051 12052 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12053 (MachineBasicBlock::iterator(MI)), BB->end()); 12054 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12055 12056 // Add code to the main basic block to check if the stack limit has been hit, 12057 // and if so, jump to mallocMBB otherwise to bumpMBB. 12058 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12059 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12060 .addReg(tmpSPVReg).addReg(sizeVReg); 12061 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12062 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12063 .addReg(SPLimitVReg); 12064 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12065 12066 // bumpMBB simply decreases the stack pointer, since we know the current 12067 // stacklet has enough space. 12068 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12069 .addReg(SPLimitVReg); 12070 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12071 .addReg(SPLimitVReg); 12072 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12073 12074 // Calls into a routine in libgcc to allocate more space from the heap. 12075 if (Is64Bit) { 12076 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12077 .addReg(sizeVReg); 12078 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12079 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12080 } else { 12081 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12082 .addImm(12); 12083 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12084 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12085 .addExternalSymbol("__morestack_allocate_stack_space"); 12086 } 12087 12088 if (!Is64Bit) 12089 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12090 .addImm(16); 12091 12092 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12093 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12094 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12095 12096 // Set up the CFG correctly. 12097 BB->addSuccessor(bumpMBB); 12098 BB->addSuccessor(mallocMBB); 12099 mallocMBB->addSuccessor(continueMBB); 12100 bumpMBB->addSuccessor(continueMBB); 12101 12102 // Take care of the PHI nodes. 12103 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12104 MI->getOperand(0).getReg()) 12105 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12106 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12107 12108 // Delete the original pseudo instruction. 12109 MI->eraseFromParent(); 12110 12111 // And we're done. 12112 return continueMBB; 12113} 12114 12115MachineBasicBlock * 12116X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12117 MachineBasicBlock *BB) const { 12118 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12119 DebugLoc DL = MI->getDebugLoc(); 12120 12121 assert(!Subtarget->isTargetEnvMacho()); 12122 12123 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12124 // non-trivial part is impdef of ESP. 12125 12126 if (Subtarget->isTargetWin64()) { 12127 if (Subtarget->isTargetCygMing()) { 12128 // ___chkstk(Mingw64): 12129 // Clobbers R10, R11, RAX and EFLAGS. 12130 // Updates RSP. 12131 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12132 .addExternalSymbol("___chkstk") 12133 .addReg(X86::RAX, RegState::Implicit) 12134 .addReg(X86::RSP, RegState::Implicit) 12135 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12136 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12137 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12138 } else { 12139 // __chkstk(MSVCRT): does not update stack pointer. 12140 // Clobbers R10, R11 and EFLAGS. 12141 // FIXME: RAX(allocated size) might be reused and not killed. 12142 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12143 .addExternalSymbol("__chkstk") 12144 .addReg(X86::RAX, RegState::Implicit) 12145 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12146 // RAX has the offset to subtracted from RSP. 12147 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12148 .addReg(X86::RSP) 12149 .addReg(X86::RAX); 12150 } 12151 } else { 12152 const char *StackProbeSymbol = 12153 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12154 12155 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12156 .addExternalSymbol(StackProbeSymbol) 12157 .addReg(X86::EAX, RegState::Implicit) 12158 .addReg(X86::ESP, RegState::Implicit) 12159 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12160 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12161 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12162 } 12163 12164 MI->eraseFromParent(); // The pseudo instruction is gone now. 12165 return BB; 12166} 12167 12168MachineBasicBlock * 12169X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12170 MachineBasicBlock *BB) const { 12171 // This is pretty easy. We're taking the value that we received from 12172 // our load from the relocation, sticking it in either RDI (x86-64) 12173 // or EAX and doing an indirect call. The return value will then 12174 // be in the normal return register. 12175 const X86InstrInfo *TII 12176 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12177 DebugLoc DL = MI->getDebugLoc(); 12178 MachineFunction *F = BB->getParent(); 12179 12180 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12181 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12182 12183 if (Subtarget->is64Bit()) { 12184 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12185 TII->get(X86::MOV64rm), X86::RDI) 12186 .addReg(X86::RIP) 12187 .addImm(0).addReg(0) 12188 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12189 MI->getOperand(3).getTargetFlags()) 12190 .addReg(0); 12191 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12192 addDirectMem(MIB, X86::RDI); 12193 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12194 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12195 TII->get(X86::MOV32rm), X86::EAX) 12196 .addReg(0) 12197 .addImm(0).addReg(0) 12198 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12199 MI->getOperand(3).getTargetFlags()) 12200 .addReg(0); 12201 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12202 addDirectMem(MIB, X86::EAX); 12203 } else { 12204 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12205 TII->get(X86::MOV32rm), X86::EAX) 12206 .addReg(TII->getGlobalBaseReg(F)) 12207 .addImm(0).addReg(0) 12208 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12209 MI->getOperand(3).getTargetFlags()) 12210 .addReg(0); 12211 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12212 addDirectMem(MIB, X86::EAX); 12213 } 12214 12215 MI->eraseFromParent(); // The pseudo instruction is gone now. 12216 return BB; 12217} 12218 12219MachineBasicBlock * 12220X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12221 MachineBasicBlock *BB) const { 12222 switch (MI->getOpcode()) { 12223 default: assert(0 && "Unexpected instr type to insert"); 12224 case X86::TAILJMPd64: 12225 case X86::TAILJMPr64: 12226 case X86::TAILJMPm64: 12227 assert(0 && "TAILJMP64 would not be touched here."); 12228 case X86::TCRETURNdi64: 12229 case X86::TCRETURNri64: 12230 case X86::TCRETURNmi64: 12231 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12232 // On AMD64, additional defs should be added before register allocation. 12233 if (!Subtarget->isTargetWin64()) { 12234 MI->addRegisterDefined(X86::RSI); 12235 MI->addRegisterDefined(X86::RDI); 12236 MI->addRegisterDefined(X86::XMM6); 12237 MI->addRegisterDefined(X86::XMM7); 12238 MI->addRegisterDefined(X86::XMM8); 12239 MI->addRegisterDefined(X86::XMM9); 12240 MI->addRegisterDefined(X86::XMM10); 12241 MI->addRegisterDefined(X86::XMM11); 12242 MI->addRegisterDefined(X86::XMM12); 12243 MI->addRegisterDefined(X86::XMM13); 12244 MI->addRegisterDefined(X86::XMM14); 12245 MI->addRegisterDefined(X86::XMM15); 12246 } 12247 return BB; 12248 case X86::WIN_ALLOCA: 12249 return EmitLoweredWinAlloca(MI, BB); 12250 case X86::SEG_ALLOCA_32: 12251 return EmitLoweredSegAlloca(MI, BB, false); 12252 case X86::SEG_ALLOCA_64: 12253 return EmitLoweredSegAlloca(MI, BB, true); 12254 case X86::TLSCall_32: 12255 case X86::TLSCall_64: 12256 return EmitLoweredTLSCall(MI, BB); 12257 case X86::CMOV_GR8: 12258 case X86::CMOV_FR32: 12259 case X86::CMOV_FR64: 12260 case X86::CMOV_V4F32: 12261 case X86::CMOV_V2F64: 12262 case X86::CMOV_V2I64: 12263 case X86::CMOV_V8F32: 12264 case X86::CMOV_V4F64: 12265 case X86::CMOV_V4I64: 12266 case X86::CMOV_GR16: 12267 case X86::CMOV_GR32: 12268 case X86::CMOV_RFP32: 12269 case X86::CMOV_RFP64: 12270 case X86::CMOV_RFP80: 12271 return EmitLoweredSelect(MI, BB); 12272 12273 case X86::FP32_TO_INT16_IN_MEM: 12274 case X86::FP32_TO_INT32_IN_MEM: 12275 case X86::FP32_TO_INT64_IN_MEM: 12276 case X86::FP64_TO_INT16_IN_MEM: 12277 case X86::FP64_TO_INT32_IN_MEM: 12278 case X86::FP64_TO_INT64_IN_MEM: 12279 case X86::FP80_TO_INT16_IN_MEM: 12280 case X86::FP80_TO_INT32_IN_MEM: 12281 case X86::FP80_TO_INT64_IN_MEM: { 12282 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12283 DebugLoc DL = MI->getDebugLoc(); 12284 12285 // Change the floating point control register to use "round towards zero" 12286 // mode when truncating to an integer value. 12287 MachineFunction *F = BB->getParent(); 12288 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12289 addFrameReference(BuildMI(*BB, MI, DL, 12290 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12291 12292 // Load the old value of the high byte of the control word... 12293 unsigned OldCW = 12294 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12295 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12296 CWFrameIdx); 12297 12298 // Set the high part to be round to zero... 12299 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12300 .addImm(0xC7F); 12301 12302 // Reload the modified control word now... 12303 addFrameReference(BuildMI(*BB, MI, DL, 12304 TII->get(X86::FLDCW16m)), CWFrameIdx); 12305 12306 // Restore the memory image of control word to original value 12307 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12308 .addReg(OldCW); 12309 12310 // Get the X86 opcode to use. 12311 unsigned Opc; 12312 switch (MI->getOpcode()) { 12313 default: llvm_unreachable("illegal opcode!"); 12314 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12315 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12316 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12317 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12318 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12319 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12320 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12321 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12322 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12323 } 12324 12325 X86AddressMode AM; 12326 MachineOperand &Op = MI->getOperand(0); 12327 if (Op.isReg()) { 12328 AM.BaseType = X86AddressMode::RegBase; 12329 AM.Base.Reg = Op.getReg(); 12330 } else { 12331 AM.BaseType = X86AddressMode::FrameIndexBase; 12332 AM.Base.FrameIndex = Op.getIndex(); 12333 } 12334 Op = MI->getOperand(1); 12335 if (Op.isImm()) 12336 AM.Scale = Op.getImm(); 12337 Op = MI->getOperand(2); 12338 if (Op.isImm()) 12339 AM.IndexReg = Op.getImm(); 12340 Op = MI->getOperand(3); 12341 if (Op.isGlobal()) { 12342 AM.GV = Op.getGlobal(); 12343 } else { 12344 AM.Disp = Op.getImm(); 12345 } 12346 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12347 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12348 12349 // Reload the original control word now. 12350 addFrameReference(BuildMI(*BB, MI, DL, 12351 TII->get(X86::FLDCW16m)), CWFrameIdx); 12352 12353 MI->eraseFromParent(); // The pseudo instruction is gone now. 12354 return BB; 12355 } 12356 // String/text processing lowering. 12357 case X86::PCMPISTRM128REG: 12358 case X86::VPCMPISTRM128REG: 12359 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12360 case X86::PCMPISTRM128MEM: 12361 case X86::VPCMPISTRM128MEM: 12362 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12363 case X86::PCMPESTRM128REG: 12364 case X86::VPCMPESTRM128REG: 12365 return EmitPCMP(MI, BB, 5, false /* in mem */); 12366 case X86::PCMPESTRM128MEM: 12367 case X86::VPCMPESTRM128MEM: 12368 return EmitPCMP(MI, BB, 5, true /* in mem */); 12369 12370 // Thread synchronization. 12371 case X86::MONITOR: 12372 return EmitMonitor(MI, BB); 12373 case X86::MWAIT: 12374 return EmitMwait(MI, BB); 12375 12376 // Atomic Lowering. 12377 case X86::ATOMAND32: 12378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12379 X86::AND32ri, X86::MOV32rm, 12380 X86::LCMPXCHG32, 12381 X86::NOT32r, X86::EAX, 12382 X86::GR32RegisterClass); 12383 case X86::ATOMOR32: 12384 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12385 X86::OR32ri, X86::MOV32rm, 12386 X86::LCMPXCHG32, 12387 X86::NOT32r, X86::EAX, 12388 X86::GR32RegisterClass); 12389 case X86::ATOMXOR32: 12390 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12391 X86::XOR32ri, X86::MOV32rm, 12392 X86::LCMPXCHG32, 12393 X86::NOT32r, X86::EAX, 12394 X86::GR32RegisterClass); 12395 case X86::ATOMNAND32: 12396 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12397 X86::AND32ri, X86::MOV32rm, 12398 X86::LCMPXCHG32, 12399 X86::NOT32r, X86::EAX, 12400 X86::GR32RegisterClass, true); 12401 case X86::ATOMMIN32: 12402 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12403 case X86::ATOMMAX32: 12404 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12405 case X86::ATOMUMIN32: 12406 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12407 case X86::ATOMUMAX32: 12408 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12409 12410 case X86::ATOMAND16: 12411 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12412 X86::AND16ri, X86::MOV16rm, 12413 X86::LCMPXCHG16, 12414 X86::NOT16r, X86::AX, 12415 X86::GR16RegisterClass); 12416 case X86::ATOMOR16: 12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12418 X86::OR16ri, X86::MOV16rm, 12419 X86::LCMPXCHG16, 12420 X86::NOT16r, X86::AX, 12421 X86::GR16RegisterClass); 12422 case X86::ATOMXOR16: 12423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12424 X86::XOR16ri, X86::MOV16rm, 12425 X86::LCMPXCHG16, 12426 X86::NOT16r, X86::AX, 12427 X86::GR16RegisterClass); 12428 case X86::ATOMNAND16: 12429 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12430 X86::AND16ri, X86::MOV16rm, 12431 X86::LCMPXCHG16, 12432 X86::NOT16r, X86::AX, 12433 X86::GR16RegisterClass, true); 12434 case X86::ATOMMIN16: 12435 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12436 case X86::ATOMMAX16: 12437 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12438 case X86::ATOMUMIN16: 12439 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12440 case X86::ATOMUMAX16: 12441 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12442 12443 case X86::ATOMAND8: 12444 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12445 X86::AND8ri, X86::MOV8rm, 12446 X86::LCMPXCHG8, 12447 X86::NOT8r, X86::AL, 12448 X86::GR8RegisterClass); 12449 case X86::ATOMOR8: 12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12451 X86::OR8ri, X86::MOV8rm, 12452 X86::LCMPXCHG8, 12453 X86::NOT8r, X86::AL, 12454 X86::GR8RegisterClass); 12455 case X86::ATOMXOR8: 12456 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12457 X86::XOR8ri, X86::MOV8rm, 12458 X86::LCMPXCHG8, 12459 X86::NOT8r, X86::AL, 12460 X86::GR8RegisterClass); 12461 case X86::ATOMNAND8: 12462 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12463 X86::AND8ri, X86::MOV8rm, 12464 X86::LCMPXCHG8, 12465 X86::NOT8r, X86::AL, 12466 X86::GR8RegisterClass, true); 12467 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12468 // This group is for 64-bit host. 12469 case X86::ATOMAND64: 12470 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12471 X86::AND64ri32, X86::MOV64rm, 12472 X86::LCMPXCHG64, 12473 X86::NOT64r, X86::RAX, 12474 X86::GR64RegisterClass); 12475 case X86::ATOMOR64: 12476 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12477 X86::OR64ri32, X86::MOV64rm, 12478 X86::LCMPXCHG64, 12479 X86::NOT64r, X86::RAX, 12480 X86::GR64RegisterClass); 12481 case X86::ATOMXOR64: 12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12483 X86::XOR64ri32, X86::MOV64rm, 12484 X86::LCMPXCHG64, 12485 X86::NOT64r, X86::RAX, 12486 X86::GR64RegisterClass); 12487 case X86::ATOMNAND64: 12488 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12489 X86::AND64ri32, X86::MOV64rm, 12490 X86::LCMPXCHG64, 12491 X86::NOT64r, X86::RAX, 12492 X86::GR64RegisterClass, true); 12493 case X86::ATOMMIN64: 12494 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12495 case X86::ATOMMAX64: 12496 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12497 case X86::ATOMUMIN64: 12498 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12499 case X86::ATOMUMAX64: 12500 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12501 12502 // This group does 64-bit operations on a 32-bit host. 12503 case X86::ATOMAND6432: 12504 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12505 X86::AND32rr, X86::AND32rr, 12506 X86::AND32ri, X86::AND32ri, 12507 false); 12508 case X86::ATOMOR6432: 12509 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12510 X86::OR32rr, X86::OR32rr, 12511 X86::OR32ri, X86::OR32ri, 12512 false); 12513 case X86::ATOMXOR6432: 12514 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12515 X86::XOR32rr, X86::XOR32rr, 12516 X86::XOR32ri, X86::XOR32ri, 12517 false); 12518 case X86::ATOMNAND6432: 12519 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12520 X86::AND32rr, X86::AND32rr, 12521 X86::AND32ri, X86::AND32ri, 12522 true); 12523 case X86::ATOMADD6432: 12524 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12525 X86::ADD32rr, X86::ADC32rr, 12526 X86::ADD32ri, X86::ADC32ri, 12527 false); 12528 case X86::ATOMSUB6432: 12529 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12530 X86::SUB32rr, X86::SBB32rr, 12531 X86::SUB32ri, X86::SBB32ri, 12532 false); 12533 case X86::ATOMSWAP6432: 12534 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12535 X86::MOV32rr, X86::MOV32rr, 12536 X86::MOV32ri, X86::MOV32ri, 12537 false); 12538 case X86::VASTART_SAVE_XMM_REGS: 12539 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12540 12541 case X86::VAARG_64: 12542 return EmitVAARG64WithCustomInserter(MI, BB); 12543 } 12544} 12545 12546//===----------------------------------------------------------------------===// 12547// X86 Optimization Hooks 12548//===----------------------------------------------------------------------===// 12549 12550void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12551 const APInt &Mask, 12552 APInt &KnownZero, 12553 APInt &KnownOne, 12554 const SelectionDAG &DAG, 12555 unsigned Depth) const { 12556 unsigned Opc = Op.getOpcode(); 12557 assert((Opc >= ISD::BUILTIN_OP_END || 12558 Opc == ISD::INTRINSIC_WO_CHAIN || 12559 Opc == ISD::INTRINSIC_W_CHAIN || 12560 Opc == ISD::INTRINSIC_VOID) && 12561 "Should use MaskedValueIsZero if you don't know whether Op" 12562 " is a target node!"); 12563 12564 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12565 switch (Opc) { 12566 default: break; 12567 case X86ISD::ADD: 12568 case X86ISD::SUB: 12569 case X86ISD::ADC: 12570 case X86ISD::SBB: 12571 case X86ISD::SMUL: 12572 case X86ISD::UMUL: 12573 case X86ISD::INC: 12574 case X86ISD::DEC: 12575 case X86ISD::OR: 12576 case X86ISD::XOR: 12577 case X86ISD::AND: 12578 // These nodes' second result is a boolean. 12579 if (Op.getResNo() == 0) 12580 break; 12581 // Fallthrough 12582 case X86ISD::SETCC: 12583 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12584 Mask.getBitWidth() - 1); 12585 break; 12586 case ISD::INTRINSIC_WO_CHAIN: { 12587 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12588 unsigned NumLoBits = 0; 12589 switch (IntId) { 12590 default: break; 12591 case Intrinsic::x86_sse_movmsk_ps: 12592 case Intrinsic::x86_avx_movmsk_ps_256: 12593 case Intrinsic::x86_sse2_movmsk_pd: 12594 case Intrinsic::x86_avx_movmsk_pd_256: 12595 case Intrinsic::x86_mmx_pmovmskb: 12596 case Intrinsic::x86_sse2_pmovmskb_128: 12597 case Intrinsic::x86_avx2_pmovmskb: { 12598 // High bits of movmskp{s|d}, pmovmskb are known zero. 12599 switch (IntId) { 12600 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12601 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12602 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12603 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12604 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12605 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12606 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12607 } 12608 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12609 Mask.getBitWidth() - NumLoBits); 12610 break; 12611 } 12612 } 12613 break; 12614 } 12615 } 12616} 12617 12618unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12619 unsigned Depth) const { 12620 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12621 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12622 return Op.getValueType().getScalarType().getSizeInBits(); 12623 12624 // Fallback case. 12625 return 1; 12626} 12627 12628/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12629/// node is a GlobalAddress + offset. 12630bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12631 const GlobalValue* &GA, 12632 int64_t &Offset) const { 12633 if (N->getOpcode() == X86ISD::Wrapper) { 12634 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12635 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12636 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12637 return true; 12638 } 12639 } 12640 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12641} 12642 12643/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12644/// same as extracting the high 128-bit part of 256-bit vector and then 12645/// inserting the result into the low part of a new 256-bit vector 12646static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12647 EVT VT = SVOp->getValueType(0); 12648 int NumElems = VT.getVectorNumElements(); 12649 12650 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12651 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12652 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12653 SVOp->getMaskElt(j) >= 0) 12654 return false; 12655 12656 return true; 12657} 12658 12659/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12660/// same as extracting the low 128-bit part of 256-bit vector and then 12661/// inserting the result into the high part of a new 256-bit vector 12662static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12663 EVT VT = SVOp->getValueType(0); 12664 int NumElems = VT.getVectorNumElements(); 12665 12666 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12667 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12668 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12669 SVOp->getMaskElt(j) >= 0) 12670 return false; 12671 12672 return true; 12673} 12674 12675/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12676static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12677 TargetLowering::DAGCombinerInfo &DCI, 12678 bool HasAVX2) { 12679 DebugLoc dl = N->getDebugLoc(); 12680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12681 SDValue V1 = SVOp->getOperand(0); 12682 SDValue V2 = SVOp->getOperand(1); 12683 EVT VT = SVOp->getValueType(0); 12684 int NumElems = VT.getVectorNumElements(); 12685 12686 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12687 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12688 // 12689 // 0,0,0,... 12690 // | 12691 // V UNDEF BUILD_VECTOR UNDEF 12692 // \ / \ / 12693 // CONCAT_VECTOR CONCAT_VECTOR 12694 // \ / 12695 // \ / 12696 // RESULT: V + zero extended 12697 // 12698 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12699 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12700 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12701 return SDValue(); 12702 12703 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12704 return SDValue(); 12705 12706 // To match the shuffle mask, the first half of the mask should 12707 // be exactly the first vector, and all the rest a splat with the 12708 // first element of the second one. 12709 for (int i = 0; i < NumElems/2; ++i) 12710 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12711 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12712 return SDValue(); 12713 12714 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12715 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12716 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12717 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12718 SDValue ResNode = 12719 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12720 Ld->getMemoryVT(), 12721 Ld->getPointerInfo(), 12722 Ld->getAlignment(), 12723 false/*isVolatile*/, true/*ReadMem*/, 12724 false/*WriteMem*/); 12725 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12726 } 12727 12728 // Emit a zeroed vector and insert the desired subvector on its 12729 // first half. 12730 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl); 12731 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12732 DAG.getConstant(0, MVT::i32), DAG, dl); 12733 return DCI.CombineTo(N, InsV); 12734 } 12735 12736 //===--------------------------------------------------------------------===// 12737 // Combine some shuffles into subvector extracts and inserts: 12738 // 12739 12740 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12741 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12742 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12743 DAG, dl); 12744 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12745 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12746 return DCI.CombineTo(N, InsV); 12747 } 12748 12749 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12750 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12751 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12752 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12753 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12754 return DCI.CombineTo(N, InsV); 12755 } 12756 12757 return SDValue(); 12758} 12759 12760/// PerformShuffleCombine - Performs several different shuffle combines. 12761static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12762 TargetLowering::DAGCombinerInfo &DCI, 12763 const X86Subtarget *Subtarget) { 12764 DebugLoc dl = N->getDebugLoc(); 12765 EVT VT = N->getValueType(0); 12766 12767 // Don't create instructions with illegal types after legalize types has run. 12768 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12769 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12770 return SDValue(); 12771 12772 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12773 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12774 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12775 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2()); 12776 12777 // Only handle 128 wide vector from here on. 12778 if (VT.getSizeInBits() != 128) 12779 return SDValue(); 12780 12781 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12782 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12783 // consecutive, non-overlapping, and in the right order. 12784 SmallVector<SDValue, 16> Elts; 12785 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12786 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12787 12788 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12789} 12790 12791/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12792/// generation and convert it from being a bunch of shuffles and extracts 12793/// to a simple store and scalar loads to extract the elements. 12794static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12795 const TargetLowering &TLI) { 12796 SDValue InputVector = N->getOperand(0); 12797 12798 // Only operate on vectors of 4 elements, where the alternative shuffling 12799 // gets to be more expensive. 12800 if (InputVector.getValueType() != MVT::v4i32) 12801 return SDValue(); 12802 12803 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12804 // single use which is a sign-extend or zero-extend, and all elements are 12805 // used. 12806 SmallVector<SDNode *, 4> Uses; 12807 unsigned ExtractedElements = 0; 12808 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12809 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12810 if (UI.getUse().getResNo() != InputVector.getResNo()) 12811 return SDValue(); 12812 12813 SDNode *Extract = *UI; 12814 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12815 return SDValue(); 12816 12817 if (Extract->getValueType(0) != MVT::i32) 12818 return SDValue(); 12819 if (!Extract->hasOneUse()) 12820 return SDValue(); 12821 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12822 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12823 return SDValue(); 12824 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12825 return SDValue(); 12826 12827 // Record which element was extracted. 12828 ExtractedElements |= 12829 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12830 12831 Uses.push_back(Extract); 12832 } 12833 12834 // If not all the elements were used, this may not be worthwhile. 12835 if (ExtractedElements != 15) 12836 return SDValue(); 12837 12838 // Ok, we've now decided to do the transformation. 12839 DebugLoc dl = InputVector.getDebugLoc(); 12840 12841 // Store the value to a temporary stack slot. 12842 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12843 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12844 MachinePointerInfo(), false, false, 0); 12845 12846 // Replace each use (extract) with a load of the appropriate element. 12847 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12848 UE = Uses.end(); UI != UE; ++UI) { 12849 SDNode *Extract = *UI; 12850 12851 // cOMpute the element's address. 12852 SDValue Idx = Extract->getOperand(1); 12853 unsigned EltSize = 12854 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12855 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12856 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12857 12858 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12859 StackPtr, OffsetVal); 12860 12861 // Load the scalar. 12862 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12863 ScalarAddr, MachinePointerInfo(), 12864 false, false, false, 0); 12865 12866 // Replace the exact with the load. 12867 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12868 } 12869 12870 // The replacement was made in place; don't return anything. 12871 return SDValue(); 12872} 12873 12874/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12875/// nodes. 12876static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12877 TargetLowering::DAGCombinerInfo &DCI, 12878 const X86Subtarget *Subtarget) { 12879 DebugLoc DL = N->getDebugLoc(); 12880 SDValue Cond = N->getOperand(0); 12881 // Get the LHS/RHS of the select. 12882 SDValue LHS = N->getOperand(1); 12883 SDValue RHS = N->getOperand(2); 12884 EVT VT = LHS.getValueType(); 12885 12886 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12887 // instructions match the semantics of the common C idiom x<y?x:y but not 12888 // x<=y?x:y, because of how they handle negative zero (which can be 12889 // ignored in unsafe-math mode). 12890 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12891 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12892 (Subtarget->hasSSE2() || 12893 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12894 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12895 12896 unsigned Opcode = 0; 12897 // Check for x CC y ? x : y. 12898 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12899 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12900 switch (CC) { 12901 default: break; 12902 case ISD::SETULT: 12903 // Converting this to a min would handle NaNs incorrectly, and swapping 12904 // the operands would cause it to handle comparisons between positive 12905 // and negative zero incorrectly. 12906 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12907 if (!DAG.getTarget().Options.UnsafeFPMath && 12908 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12909 break; 12910 std::swap(LHS, RHS); 12911 } 12912 Opcode = X86ISD::FMIN; 12913 break; 12914 case ISD::SETOLE: 12915 // Converting this to a min would handle comparisons between positive 12916 // and negative zero incorrectly. 12917 if (!DAG.getTarget().Options.UnsafeFPMath && 12918 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12919 break; 12920 Opcode = X86ISD::FMIN; 12921 break; 12922 case ISD::SETULE: 12923 // Converting this to a min would handle both negative zeros and NaNs 12924 // incorrectly, but we can swap the operands to fix both. 12925 std::swap(LHS, RHS); 12926 case ISD::SETOLT: 12927 case ISD::SETLT: 12928 case ISD::SETLE: 12929 Opcode = X86ISD::FMIN; 12930 break; 12931 12932 case ISD::SETOGE: 12933 // Converting this to a max would handle comparisons between positive 12934 // and negative zero incorrectly. 12935 if (!DAG.getTarget().Options.UnsafeFPMath && 12936 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12937 break; 12938 Opcode = X86ISD::FMAX; 12939 break; 12940 case ISD::SETUGT: 12941 // Converting this to a max would handle NaNs incorrectly, and swapping 12942 // the operands would cause it to handle comparisons between positive 12943 // and negative zero incorrectly. 12944 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12945 if (!DAG.getTarget().Options.UnsafeFPMath && 12946 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12947 break; 12948 std::swap(LHS, RHS); 12949 } 12950 Opcode = X86ISD::FMAX; 12951 break; 12952 case ISD::SETUGE: 12953 // Converting this to a max would handle both negative zeros and NaNs 12954 // incorrectly, but we can swap the operands to fix both. 12955 std::swap(LHS, RHS); 12956 case ISD::SETOGT: 12957 case ISD::SETGT: 12958 case ISD::SETGE: 12959 Opcode = X86ISD::FMAX; 12960 break; 12961 } 12962 // Check for x CC y ? y : x -- a min/max with reversed arms. 12963 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12964 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12965 switch (CC) { 12966 default: break; 12967 case ISD::SETOGE: 12968 // Converting this to a min would handle comparisons between positive 12969 // and negative zero incorrectly, and swapping the operands would 12970 // cause it to handle NaNs incorrectly. 12971 if (!DAG.getTarget().Options.UnsafeFPMath && 12972 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12973 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12974 break; 12975 std::swap(LHS, RHS); 12976 } 12977 Opcode = X86ISD::FMIN; 12978 break; 12979 case ISD::SETUGT: 12980 // Converting this to a min would handle NaNs incorrectly. 12981 if (!DAG.getTarget().Options.UnsafeFPMath && 12982 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12983 break; 12984 Opcode = X86ISD::FMIN; 12985 break; 12986 case ISD::SETUGE: 12987 // Converting this to a min would handle both negative zeros and NaNs 12988 // incorrectly, but we can swap the operands to fix both. 12989 std::swap(LHS, RHS); 12990 case ISD::SETOGT: 12991 case ISD::SETGT: 12992 case ISD::SETGE: 12993 Opcode = X86ISD::FMIN; 12994 break; 12995 12996 case ISD::SETULT: 12997 // Converting this to a max would handle NaNs incorrectly. 12998 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12999 break; 13000 Opcode = X86ISD::FMAX; 13001 break; 13002 case ISD::SETOLE: 13003 // Converting this to a max would handle comparisons between positive 13004 // and negative zero incorrectly, and swapping the operands would 13005 // cause it to handle NaNs incorrectly. 13006 if (!DAG.getTarget().Options.UnsafeFPMath && 13007 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13008 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13009 break; 13010 std::swap(LHS, RHS); 13011 } 13012 Opcode = X86ISD::FMAX; 13013 break; 13014 case ISD::SETULE: 13015 // Converting this to a max would handle both negative zeros and NaNs 13016 // incorrectly, but we can swap the operands to fix both. 13017 std::swap(LHS, RHS); 13018 case ISD::SETOLT: 13019 case ISD::SETLT: 13020 case ISD::SETLE: 13021 Opcode = X86ISD::FMAX; 13022 break; 13023 } 13024 } 13025 13026 if (Opcode) 13027 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13028 } 13029 13030 // If this is a select between two integer constants, try to do some 13031 // optimizations. 13032 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13033 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13034 // Don't do this for crazy integer types. 13035 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13036 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13037 // so that TrueC (the true value) is larger than FalseC. 13038 bool NeedsCondInvert = false; 13039 13040 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13041 // Efficiently invertible. 13042 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13043 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13044 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13045 NeedsCondInvert = true; 13046 std::swap(TrueC, FalseC); 13047 } 13048 13049 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13050 if (FalseC->getAPIntValue() == 0 && 13051 TrueC->getAPIntValue().isPowerOf2()) { 13052 if (NeedsCondInvert) // Invert the condition if needed. 13053 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13054 DAG.getConstant(1, Cond.getValueType())); 13055 13056 // Zero extend the condition if needed. 13057 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13058 13059 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13060 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13061 DAG.getConstant(ShAmt, MVT::i8)); 13062 } 13063 13064 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13065 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13066 if (NeedsCondInvert) // Invert the condition if needed. 13067 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13068 DAG.getConstant(1, Cond.getValueType())); 13069 13070 // Zero extend the condition if needed. 13071 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13072 FalseC->getValueType(0), Cond); 13073 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13074 SDValue(FalseC, 0)); 13075 } 13076 13077 // Optimize cases that will turn into an LEA instruction. This requires 13078 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13079 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13080 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13081 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13082 13083 bool isFastMultiplier = false; 13084 if (Diff < 10) { 13085 switch ((unsigned char)Diff) { 13086 default: break; 13087 case 1: // result = add base, cond 13088 case 2: // result = lea base( , cond*2) 13089 case 3: // result = lea base(cond, cond*2) 13090 case 4: // result = lea base( , cond*4) 13091 case 5: // result = lea base(cond, cond*4) 13092 case 8: // result = lea base( , cond*8) 13093 case 9: // result = lea base(cond, cond*8) 13094 isFastMultiplier = true; 13095 break; 13096 } 13097 } 13098 13099 if (isFastMultiplier) { 13100 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13101 if (NeedsCondInvert) // Invert the condition if needed. 13102 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13103 DAG.getConstant(1, Cond.getValueType())); 13104 13105 // Zero extend the condition if needed. 13106 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13107 Cond); 13108 // Scale the condition by the difference. 13109 if (Diff != 1) 13110 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13111 DAG.getConstant(Diff, Cond.getValueType())); 13112 13113 // Add the base if non-zero. 13114 if (FalseC->getAPIntValue() != 0) 13115 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13116 SDValue(FalseC, 0)); 13117 return Cond; 13118 } 13119 } 13120 } 13121 } 13122 13123 // Canonicalize max and min: 13124 // (x > y) ? x : y -> (x >= y) ? x : y 13125 // (x < y) ? x : y -> (x <= y) ? x : y 13126 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13127 // the need for an extra compare 13128 // against zero. e.g. 13129 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13130 // subl %esi, %edi 13131 // testl %edi, %edi 13132 // movl $0, %eax 13133 // cmovgl %edi, %eax 13134 // => 13135 // xorl %eax, %eax 13136 // subl %esi, $edi 13137 // cmovsl %eax, %edi 13138 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13139 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13140 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13141 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13142 switch (CC) { 13143 default: break; 13144 case ISD::SETLT: 13145 case ISD::SETGT: { 13146 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13147 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13148 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13149 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13150 } 13151 } 13152 } 13153 13154 // If we know that this node is legal then we know that it is going to be 13155 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13156 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13157 // to simplify previous instructions. 13158 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13159 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13160 !DCI.isBeforeLegalize() && 13161 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13162 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13163 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13164 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13165 13166 APInt KnownZero, KnownOne; 13167 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13168 DCI.isBeforeLegalizeOps()); 13169 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13170 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13171 DCI.CommitTargetLoweringOpt(TLO); 13172 } 13173 13174 return SDValue(); 13175} 13176 13177/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13178static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13179 TargetLowering::DAGCombinerInfo &DCI) { 13180 DebugLoc DL = N->getDebugLoc(); 13181 13182 // If the flag operand isn't dead, don't touch this CMOV. 13183 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13184 return SDValue(); 13185 13186 SDValue FalseOp = N->getOperand(0); 13187 SDValue TrueOp = N->getOperand(1); 13188 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13189 SDValue Cond = N->getOperand(3); 13190 if (CC == X86::COND_E || CC == X86::COND_NE) { 13191 switch (Cond.getOpcode()) { 13192 default: break; 13193 case X86ISD::BSR: 13194 case X86ISD::BSF: 13195 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13196 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13197 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13198 } 13199 } 13200 13201 // If this is a select between two integer constants, try to do some 13202 // optimizations. Note that the operands are ordered the opposite of SELECT 13203 // operands. 13204 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13205 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13206 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13207 // larger than FalseC (the false value). 13208 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13209 CC = X86::GetOppositeBranchCondition(CC); 13210 std::swap(TrueC, FalseC); 13211 } 13212 13213 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13214 // This is efficient for any integer data type (including i8/i16) and 13215 // shift amount. 13216 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13217 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13218 DAG.getConstant(CC, MVT::i8), Cond); 13219 13220 // Zero extend the condition if needed. 13221 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13222 13223 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13224 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13225 DAG.getConstant(ShAmt, MVT::i8)); 13226 if (N->getNumValues() == 2) // Dead flag value? 13227 return DCI.CombineTo(N, Cond, SDValue()); 13228 return Cond; 13229 } 13230 13231 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13232 // for any integer data type, including i8/i16. 13233 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13234 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13235 DAG.getConstant(CC, MVT::i8), Cond); 13236 13237 // Zero extend the condition if needed. 13238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13239 FalseC->getValueType(0), Cond); 13240 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13241 SDValue(FalseC, 0)); 13242 13243 if (N->getNumValues() == 2) // Dead flag value? 13244 return DCI.CombineTo(N, Cond, SDValue()); 13245 return Cond; 13246 } 13247 13248 // Optimize cases that will turn into an LEA instruction. This requires 13249 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13250 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13251 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13252 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13253 13254 bool isFastMultiplier = false; 13255 if (Diff < 10) { 13256 switch ((unsigned char)Diff) { 13257 default: break; 13258 case 1: // result = add base, cond 13259 case 2: // result = lea base( , cond*2) 13260 case 3: // result = lea base(cond, cond*2) 13261 case 4: // result = lea base( , cond*4) 13262 case 5: // result = lea base(cond, cond*4) 13263 case 8: // result = lea base( , cond*8) 13264 case 9: // result = lea base(cond, cond*8) 13265 isFastMultiplier = true; 13266 break; 13267 } 13268 } 13269 13270 if (isFastMultiplier) { 13271 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13272 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13273 DAG.getConstant(CC, MVT::i8), Cond); 13274 // Zero extend the condition if needed. 13275 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13276 Cond); 13277 // Scale the condition by the difference. 13278 if (Diff != 1) 13279 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13280 DAG.getConstant(Diff, Cond.getValueType())); 13281 13282 // Add the base if non-zero. 13283 if (FalseC->getAPIntValue() != 0) 13284 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13285 SDValue(FalseC, 0)); 13286 if (N->getNumValues() == 2) // Dead flag value? 13287 return DCI.CombineTo(N, Cond, SDValue()); 13288 return Cond; 13289 } 13290 } 13291 } 13292 } 13293 return SDValue(); 13294} 13295 13296 13297/// PerformMulCombine - Optimize a single multiply with constant into two 13298/// in order to implement it with two cheaper instructions, e.g. 13299/// LEA + SHL, LEA + LEA. 13300static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13301 TargetLowering::DAGCombinerInfo &DCI) { 13302 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13303 return SDValue(); 13304 13305 EVT VT = N->getValueType(0); 13306 if (VT != MVT::i64) 13307 return SDValue(); 13308 13309 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13310 if (!C) 13311 return SDValue(); 13312 uint64_t MulAmt = C->getZExtValue(); 13313 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13314 return SDValue(); 13315 13316 uint64_t MulAmt1 = 0; 13317 uint64_t MulAmt2 = 0; 13318 if ((MulAmt % 9) == 0) { 13319 MulAmt1 = 9; 13320 MulAmt2 = MulAmt / 9; 13321 } else if ((MulAmt % 5) == 0) { 13322 MulAmt1 = 5; 13323 MulAmt2 = MulAmt / 5; 13324 } else if ((MulAmt % 3) == 0) { 13325 MulAmt1 = 3; 13326 MulAmt2 = MulAmt / 3; 13327 } 13328 if (MulAmt2 && 13329 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13330 DebugLoc DL = N->getDebugLoc(); 13331 13332 if (isPowerOf2_64(MulAmt2) && 13333 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13334 // If second multiplifer is pow2, issue it first. We want the multiply by 13335 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13336 // is an add. 13337 std::swap(MulAmt1, MulAmt2); 13338 13339 SDValue NewMul; 13340 if (isPowerOf2_64(MulAmt1)) 13341 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13342 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13343 else 13344 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13345 DAG.getConstant(MulAmt1, VT)); 13346 13347 if (isPowerOf2_64(MulAmt2)) 13348 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13349 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13350 else 13351 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13352 DAG.getConstant(MulAmt2, VT)); 13353 13354 // Do not add new nodes to DAG combiner worklist. 13355 DCI.CombineTo(N, NewMul, false); 13356 } 13357 return SDValue(); 13358} 13359 13360static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13361 SDValue N0 = N->getOperand(0); 13362 SDValue N1 = N->getOperand(1); 13363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13364 EVT VT = N0.getValueType(); 13365 13366 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13367 // since the result of setcc_c is all zero's or all ones. 13368 if (VT.isInteger() && !VT.isVector() && 13369 N1C && N0.getOpcode() == ISD::AND && 13370 N0.getOperand(1).getOpcode() == ISD::Constant) { 13371 SDValue N00 = N0.getOperand(0); 13372 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13373 ((N00.getOpcode() == ISD::ANY_EXTEND || 13374 N00.getOpcode() == ISD::ZERO_EXTEND) && 13375 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13376 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13377 APInt ShAmt = N1C->getAPIntValue(); 13378 Mask = Mask.shl(ShAmt); 13379 if (Mask != 0) 13380 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13381 N00, DAG.getConstant(Mask, VT)); 13382 } 13383 } 13384 13385 13386 // Hardware support for vector shifts is sparse which makes us scalarize the 13387 // vector operations in many cases. Also, on sandybridge ADD is faster than 13388 // shl. 13389 // (shl V, 1) -> add V,V 13390 if (isSplatVector(N1.getNode())) { 13391 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13392 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13393 // We shift all of the values by one. In many cases we do not have 13394 // hardware support for this operation. This is better expressed as an ADD 13395 // of two values. 13396 if (N1C && (1 == N1C->getZExtValue())) { 13397 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13398 } 13399 } 13400 13401 return SDValue(); 13402} 13403 13404/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13405/// when possible. 13406static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13407 const X86Subtarget *Subtarget) { 13408 EVT VT = N->getValueType(0); 13409 if (N->getOpcode() == ISD::SHL) { 13410 SDValue V = PerformSHLCombine(N, DAG); 13411 if (V.getNode()) return V; 13412 } 13413 13414 // On X86 with SSE2 support, we can transform this to a vector shift if 13415 // all elements are shifted by the same amount. We can't do this in legalize 13416 // because the a constant vector is typically transformed to a constant pool 13417 // so we have no knowledge of the shift amount. 13418 if (!Subtarget->hasSSE2()) 13419 return SDValue(); 13420 13421 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13422 (!Subtarget->hasAVX2() || 13423 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13424 return SDValue(); 13425 13426 SDValue ShAmtOp = N->getOperand(1); 13427 EVT EltVT = VT.getVectorElementType(); 13428 DebugLoc DL = N->getDebugLoc(); 13429 SDValue BaseShAmt = SDValue(); 13430 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13431 unsigned NumElts = VT.getVectorNumElements(); 13432 unsigned i = 0; 13433 for (; i != NumElts; ++i) { 13434 SDValue Arg = ShAmtOp.getOperand(i); 13435 if (Arg.getOpcode() == ISD::UNDEF) continue; 13436 BaseShAmt = Arg; 13437 break; 13438 } 13439 // Handle the case where the build_vector is all undef 13440 // FIXME: Should DAG allow this? 13441 if (i == NumElts) 13442 return SDValue(); 13443 13444 for (; i != NumElts; ++i) { 13445 SDValue Arg = ShAmtOp.getOperand(i); 13446 if (Arg.getOpcode() == ISD::UNDEF) continue; 13447 if (Arg != BaseShAmt) { 13448 return SDValue(); 13449 } 13450 } 13451 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13452 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13453 SDValue InVec = ShAmtOp.getOperand(0); 13454 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13455 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13456 unsigned i = 0; 13457 for (; i != NumElts; ++i) { 13458 SDValue Arg = InVec.getOperand(i); 13459 if (Arg.getOpcode() == ISD::UNDEF) continue; 13460 BaseShAmt = Arg; 13461 break; 13462 } 13463 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13465 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13466 if (C->getZExtValue() == SplatIdx) 13467 BaseShAmt = InVec.getOperand(1); 13468 } 13469 } 13470 if (BaseShAmt.getNode() == 0) 13471 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13472 DAG.getIntPtrConstant(0)); 13473 } else 13474 return SDValue(); 13475 13476 // The shift amount is an i32. 13477 if (EltVT.bitsGT(MVT::i32)) 13478 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13479 else if (EltVT.bitsLT(MVT::i32)) 13480 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13481 13482 // The shift amount is identical so we can do a vector shift. 13483 SDValue ValOp = N->getOperand(0); 13484 switch (N->getOpcode()) { 13485 default: 13486 llvm_unreachable("Unknown shift opcode!"); 13487 break; 13488 case ISD::SHL: 13489 if (VT == MVT::v2i64) 13490 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13491 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13492 ValOp, BaseShAmt); 13493 if (VT == MVT::v4i32) 13494 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13495 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13496 ValOp, BaseShAmt); 13497 if (VT == MVT::v8i16) 13498 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13499 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13500 ValOp, BaseShAmt); 13501 if (VT == MVT::v4i64) 13502 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13503 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 13504 ValOp, BaseShAmt); 13505 if (VT == MVT::v8i32) 13506 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13507 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 13508 ValOp, BaseShAmt); 13509 if (VT == MVT::v16i16) 13510 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13511 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 13512 ValOp, BaseShAmt); 13513 break; 13514 case ISD::SRA: 13515 if (VT == MVT::v4i32) 13516 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13517 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13518 ValOp, BaseShAmt); 13519 if (VT == MVT::v8i16) 13520 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13521 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13522 ValOp, BaseShAmt); 13523 if (VT == MVT::v8i32) 13524 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13525 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 13526 ValOp, BaseShAmt); 13527 if (VT == MVT::v16i16) 13528 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13529 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 13530 ValOp, BaseShAmt); 13531 break; 13532 case ISD::SRL: 13533 if (VT == MVT::v2i64) 13534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13535 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13536 ValOp, BaseShAmt); 13537 if (VT == MVT::v4i32) 13538 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13539 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13540 ValOp, BaseShAmt); 13541 if (VT == MVT::v8i16) 13542 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13543 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13544 ValOp, BaseShAmt); 13545 if (VT == MVT::v4i64) 13546 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13547 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 13548 ValOp, BaseShAmt); 13549 if (VT == MVT::v8i32) 13550 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13551 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 13552 ValOp, BaseShAmt); 13553 if (VT == MVT::v16i16) 13554 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13555 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 13556 ValOp, BaseShAmt); 13557 break; 13558 } 13559 return SDValue(); 13560} 13561 13562 13563// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13564// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13565// and friends. Likewise for OR -> CMPNEQSS. 13566static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13567 TargetLowering::DAGCombinerInfo &DCI, 13568 const X86Subtarget *Subtarget) { 13569 unsigned opcode; 13570 13571 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13572 // we're requiring SSE2 for both. 13573 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13574 SDValue N0 = N->getOperand(0); 13575 SDValue N1 = N->getOperand(1); 13576 SDValue CMP0 = N0->getOperand(1); 13577 SDValue CMP1 = N1->getOperand(1); 13578 DebugLoc DL = N->getDebugLoc(); 13579 13580 // The SETCCs should both refer to the same CMP. 13581 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13582 return SDValue(); 13583 13584 SDValue CMP00 = CMP0->getOperand(0); 13585 SDValue CMP01 = CMP0->getOperand(1); 13586 EVT VT = CMP00.getValueType(); 13587 13588 if (VT == MVT::f32 || VT == MVT::f64) { 13589 bool ExpectingFlags = false; 13590 // Check for any users that want flags: 13591 for (SDNode::use_iterator UI = N->use_begin(), 13592 UE = N->use_end(); 13593 !ExpectingFlags && UI != UE; ++UI) 13594 switch (UI->getOpcode()) { 13595 default: 13596 case ISD::BR_CC: 13597 case ISD::BRCOND: 13598 case ISD::SELECT: 13599 ExpectingFlags = true; 13600 break; 13601 case ISD::CopyToReg: 13602 case ISD::SIGN_EXTEND: 13603 case ISD::ZERO_EXTEND: 13604 case ISD::ANY_EXTEND: 13605 break; 13606 } 13607 13608 if (!ExpectingFlags) { 13609 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13610 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13611 13612 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13613 X86::CondCode tmp = cc0; 13614 cc0 = cc1; 13615 cc1 = tmp; 13616 } 13617 13618 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13619 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13620 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13621 X86ISD::NodeType NTOperator = is64BitFP ? 13622 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13623 // FIXME: need symbolic constants for these magic numbers. 13624 // See X86ATTInstPrinter.cpp:printSSECC(). 13625 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13626 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13627 DAG.getConstant(x86cc, MVT::i8)); 13628 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13629 OnesOrZeroesF); 13630 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13631 DAG.getConstant(1, MVT::i32)); 13632 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13633 return OneBitOfTruth; 13634 } 13635 } 13636 } 13637 } 13638 return SDValue(); 13639} 13640 13641/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13642/// so it can be folded inside ANDNP. 13643static bool CanFoldXORWithAllOnes(const SDNode *N) { 13644 EVT VT = N->getValueType(0); 13645 13646 // Match direct AllOnes for 128 and 256-bit vectors 13647 if (ISD::isBuildVectorAllOnes(N)) 13648 return true; 13649 13650 // Look through a bit convert. 13651 if (N->getOpcode() == ISD::BITCAST) 13652 N = N->getOperand(0).getNode(); 13653 13654 // Sometimes the operand may come from a insert_subvector building a 256-bit 13655 // allones vector 13656 if (VT.getSizeInBits() == 256 && 13657 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13658 SDValue V1 = N->getOperand(0); 13659 SDValue V2 = N->getOperand(1); 13660 13661 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13662 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13663 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13664 ISD::isBuildVectorAllOnes(V2.getNode())) 13665 return true; 13666 } 13667 13668 return false; 13669} 13670 13671static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13672 TargetLowering::DAGCombinerInfo &DCI, 13673 const X86Subtarget *Subtarget) { 13674 if (DCI.isBeforeLegalizeOps()) 13675 return SDValue(); 13676 13677 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13678 if (R.getNode()) 13679 return R; 13680 13681 EVT VT = N->getValueType(0); 13682 13683 // Create ANDN, BLSI, and BLSR instructions 13684 // BLSI is X & (-X) 13685 // BLSR is X & (X-1) 13686 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13687 SDValue N0 = N->getOperand(0); 13688 SDValue N1 = N->getOperand(1); 13689 DebugLoc DL = N->getDebugLoc(); 13690 13691 // Check LHS for not 13692 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13693 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13694 // Check RHS for not 13695 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13696 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13697 13698 // Check LHS for neg 13699 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13700 isZero(N0.getOperand(0))) 13701 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13702 13703 // Check RHS for neg 13704 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13705 isZero(N1.getOperand(0))) 13706 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13707 13708 // Check LHS for X-1 13709 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13710 isAllOnes(N0.getOperand(1))) 13711 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13712 13713 // Check RHS for X-1 13714 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13715 isAllOnes(N1.getOperand(1))) 13716 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13717 13718 return SDValue(); 13719 } 13720 13721 // Want to form ANDNP nodes: 13722 // 1) In the hopes of then easily combining them with OR and AND nodes 13723 // to form PBLEND/PSIGN. 13724 // 2) To match ANDN packed intrinsics 13725 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13726 return SDValue(); 13727 13728 SDValue N0 = N->getOperand(0); 13729 SDValue N1 = N->getOperand(1); 13730 DebugLoc DL = N->getDebugLoc(); 13731 13732 // Check LHS for vnot 13733 if (N0.getOpcode() == ISD::XOR && 13734 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13735 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13736 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13737 13738 // Check RHS for vnot 13739 if (N1.getOpcode() == ISD::XOR && 13740 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13741 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13742 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13743 13744 return SDValue(); 13745} 13746 13747static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13748 TargetLowering::DAGCombinerInfo &DCI, 13749 const X86Subtarget *Subtarget) { 13750 if (DCI.isBeforeLegalizeOps()) 13751 return SDValue(); 13752 13753 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13754 if (R.getNode()) 13755 return R; 13756 13757 EVT VT = N->getValueType(0); 13758 13759 SDValue N0 = N->getOperand(0); 13760 SDValue N1 = N->getOperand(1); 13761 13762 // look for psign/blend 13763 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13764 if (!Subtarget->hasSSSE3() || 13765 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13766 return SDValue(); 13767 13768 // Canonicalize pandn to RHS 13769 if (N0.getOpcode() == X86ISD::ANDNP) 13770 std::swap(N0, N1); 13771 // or (and (m, y), (pandn m, x)) 13772 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13773 SDValue Mask = N1.getOperand(0); 13774 SDValue X = N1.getOperand(1); 13775 SDValue Y; 13776 if (N0.getOperand(0) == Mask) 13777 Y = N0.getOperand(1); 13778 if (N0.getOperand(1) == Mask) 13779 Y = N0.getOperand(0); 13780 13781 // Check to see if the mask appeared in both the AND and ANDNP and 13782 if (!Y.getNode()) 13783 return SDValue(); 13784 13785 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13786 if (Mask.getOpcode() != ISD::BITCAST || 13787 X.getOpcode() != ISD::BITCAST || 13788 Y.getOpcode() != ISD::BITCAST) 13789 return SDValue(); 13790 13791 // Look through mask bitcast. 13792 Mask = Mask.getOperand(0); 13793 EVT MaskVT = Mask.getValueType(); 13794 13795 // Validate that the Mask operand is a vector sra node. The sra node 13796 // will be an intrinsic. 13797 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13798 return SDValue(); 13799 13800 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13801 // there is no psrai.b 13802 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13803 case Intrinsic::x86_sse2_psrai_w: 13804 case Intrinsic::x86_sse2_psrai_d: 13805 case Intrinsic::x86_avx2_psrai_w: 13806 case Intrinsic::x86_avx2_psrai_d: 13807 break; 13808 default: return SDValue(); 13809 } 13810 13811 // Check that the SRA is all signbits. 13812 SDValue SraC = Mask.getOperand(2); 13813 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13814 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13815 if ((SraAmt + 1) != EltBits) 13816 return SDValue(); 13817 13818 DebugLoc DL = N->getDebugLoc(); 13819 13820 // Now we know we at least have a plendvb with the mask val. See if 13821 // we can form a psignb/w/d. 13822 // psign = x.type == y.type == mask.type && y = sub(0, x); 13823 X = X.getOperand(0); 13824 Y = Y.getOperand(0); 13825 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13826 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13827 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() && 13828 (EltBits == 8 || EltBits == 16 || EltBits == 32)) { 13829 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, 13830 Mask.getOperand(1)); 13831 return DAG.getNode(ISD::BITCAST, DL, VT, Sign); 13832 } 13833 // PBLENDVB only available on SSE 4.1 13834 if (!Subtarget->hasSSE41()) 13835 return SDValue(); 13836 13837 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13838 13839 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13840 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13841 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13842 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13843 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13844 } 13845 } 13846 13847 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13848 return SDValue(); 13849 13850 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13851 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13852 std::swap(N0, N1); 13853 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13854 return SDValue(); 13855 if (!N0.hasOneUse() || !N1.hasOneUse()) 13856 return SDValue(); 13857 13858 SDValue ShAmt0 = N0.getOperand(1); 13859 if (ShAmt0.getValueType() != MVT::i8) 13860 return SDValue(); 13861 SDValue ShAmt1 = N1.getOperand(1); 13862 if (ShAmt1.getValueType() != MVT::i8) 13863 return SDValue(); 13864 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13865 ShAmt0 = ShAmt0.getOperand(0); 13866 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13867 ShAmt1 = ShAmt1.getOperand(0); 13868 13869 DebugLoc DL = N->getDebugLoc(); 13870 unsigned Opc = X86ISD::SHLD; 13871 SDValue Op0 = N0.getOperand(0); 13872 SDValue Op1 = N1.getOperand(0); 13873 if (ShAmt0.getOpcode() == ISD::SUB) { 13874 Opc = X86ISD::SHRD; 13875 std::swap(Op0, Op1); 13876 std::swap(ShAmt0, ShAmt1); 13877 } 13878 13879 unsigned Bits = VT.getSizeInBits(); 13880 if (ShAmt1.getOpcode() == ISD::SUB) { 13881 SDValue Sum = ShAmt1.getOperand(0); 13882 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13883 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13884 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13885 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13886 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13887 return DAG.getNode(Opc, DL, VT, 13888 Op0, Op1, 13889 DAG.getNode(ISD::TRUNCATE, DL, 13890 MVT::i8, ShAmt0)); 13891 } 13892 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13893 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13894 if (ShAmt0C && 13895 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13896 return DAG.getNode(Opc, DL, VT, 13897 N0.getOperand(0), N1.getOperand(0), 13898 DAG.getNode(ISD::TRUNCATE, DL, 13899 MVT::i8, ShAmt0)); 13900 } 13901 13902 return SDValue(); 13903} 13904 13905// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 13906static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 13907 TargetLowering::DAGCombinerInfo &DCI, 13908 const X86Subtarget *Subtarget) { 13909 if (DCI.isBeforeLegalizeOps()) 13910 return SDValue(); 13911 13912 EVT VT = N->getValueType(0); 13913 13914 if (VT != MVT::i32 && VT != MVT::i64) 13915 return SDValue(); 13916 13917 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 13918 13919 // Create BLSMSK instructions by finding X ^ (X-1) 13920 SDValue N0 = N->getOperand(0); 13921 SDValue N1 = N->getOperand(1); 13922 DebugLoc DL = N->getDebugLoc(); 13923 13924 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13925 isAllOnes(N0.getOperand(1))) 13926 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 13927 13928 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13929 isAllOnes(N1.getOperand(1))) 13930 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 13931 13932 return SDValue(); 13933} 13934 13935/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13936static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13937 const X86Subtarget *Subtarget) { 13938 LoadSDNode *Ld = cast<LoadSDNode>(N); 13939 EVT RegVT = Ld->getValueType(0); 13940 EVT MemVT = Ld->getMemoryVT(); 13941 DebugLoc dl = Ld->getDebugLoc(); 13942 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13943 13944 ISD::LoadExtType Ext = Ld->getExtensionType(); 13945 13946 // If this is a vector EXT Load then attempt to optimize it using a 13947 // shuffle. We need SSE4 for the shuffles. 13948 // TODO: It is possible to support ZExt by zeroing the undef values 13949 // during the shuffle phase or after the shuffle. 13950 if (RegVT.isVector() && RegVT.isInteger() && 13951 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13952 assert(MemVT != RegVT && "Cannot extend to the same type"); 13953 assert(MemVT.isVector() && "Must load a vector from memory"); 13954 13955 unsigned NumElems = RegVT.getVectorNumElements(); 13956 unsigned RegSz = RegVT.getSizeInBits(); 13957 unsigned MemSz = MemVT.getSizeInBits(); 13958 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13959 // All sizes must be a power of two 13960 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13961 13962 // Attempt to load the original value using a single load op. 13963 // Find a scalar type which is equal to the loaded word size. 13964 MVT SclrLoadTy = MVT::i8; 13965 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13966 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13967 MVT Tp = (MVT::SimpleValueType)tp; 13968 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13969 SclrLoadTy = Tp; 13970 break; 13971 } 13972 } 13973 13974 // Proceed if a load word is found. 13975 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13976 13977 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13978 RegSz/SclrLoadTy.getSizeInBits()); 13979 13980 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13981 RegSz/MemVT.getScalarType().getSizeInBits()); 13982 // Can't shuffle using an illegal type. 13983 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13984 13985 // Perform a single load. 13986 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13987 Ld->getBasePtr(), 13988 Ld->getPointerInfo(), Ld->isVolatile(), 13989 Ld->isNonTemporal(), Ld->isInvariant(), 13990 Ld->getAlignment()); 13991 13992 // Insert the word loaded into a vector. 13993 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13994 LoadUnitVecVT, ScalarLoad); 13995 13996 // Bitcast the loaded value to a vector of the original element type, in 13997 // the size of the target vector type. 13998 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 13999 ScalarInVector); 14000 unsigned SizeRatio = RegSz/MemSz; 14001 14002 // Redistribute the loaded elements into the different locations. 14003 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14004 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14005 14006 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14007 DAG.getUNDEF(SlicedVec.getValueType()), 14008 ShuffleVec.data()); 14009 14010 // Bitcast to the requested type. 14011 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14012 // Replace the original load with the new sequence 14013 // and return the new chain. 14014 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14015 return SDValue(ScalarLoad.getNode(), 1); 14016 } 14017 14018 return SDValue(); 14019} 14020 14021/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14022static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14023 const X86Subtarget *Subtarget) { 14024 StoreSDNode *St = cast<StoreSDNode>(N); 14025 EVT VT = St->getValue().getValueType(); 14026 EVT StVT = St->getMemoryVT(); 14027 DebugLoc dl = St->getDebugLoc(); 14028 SDValue StoredVal = St->getOperand(1); 14029 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14030 14031 // If we are saving a concatenation of two XMM registers, perform two stores. 14032 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14033 // 128-bit ones. If in the future the cost becomes only one memory access the 14034 // first version would be better. 14035 if (VT.getSizeInBits() == 256 && 14036 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14037 StoredVal.getNumOperands() == 2) { 14038 14039 SDValue Value0 = StoredVal.getOperand(0); 14040 SDValue Value1 = StoredVal.getOperand(1); 14041 14042 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14043 SDValue Ptr0 = St->getBasePtr(); 14044 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14045 14046 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14047 St->getPointerInfo(), St->isVolatile(), 14048 St->isNonTemporal(), St->getAlignment()); 14049 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14050 St->getPointerInfo(), St->isVolatile(), 14051 St->isNonTemporal(), St->getAlignment()); 14052 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14053 } 14054 14055 // Optimize trunc store (of multiple scalars) to shuffle and store. 14056 // First, pack all of the elements in one place. Next, store to memory 14057 // in fewer chunks. 14058 if (St->isTruncatingStore() && VT.isVector()) { 14059 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14060 unsigned NumElems = VT.getVectorNumElements(); 14061 assert(StVT != VT && "Cannot truncate to the same type"); 14062 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14063 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14064 14065 // From, To sizes and ElemCount must be pow of two 14066 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14067 // We are going to use the original vector elt for storing. 14068 // Accumulated smaller vector elements must be a multiple of the store size. 14069 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14070 14071 unsigned SizeRatio = FromSz / ToSz; 14072 14073 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14074 14075 // Create a type on which we perform the shuffle 14076 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14077 StVT.getScalarType(), NumElems*SizeRatio); 14078 14079 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14080 14081 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14082 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14083 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14084 14085 // Can't shuffle using an illegal type 14086 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14087 14088 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14089 DAG.getUNDEF(WideVec.getValueType()), 14090 ShuffleVec.data()); 14091 // At this point all of the data is stored at the bottom of the 14092 // register. We now need to save it to mem. 14093 14094 // Find the largest store unit 14095 MVT StoreType = MVT::i8; 14096 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14097 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14098 MVT Tp = (MVT::SimpleValueType)tp; 14099 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14100 StoreType = Tp; 14101 } 14102 14103 // Bitcast the original vector into a vector of store-size units 14104 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14105 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14106 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14107 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14108 SmallVector<SDValue, 8> Chains; 14109 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14110 TLI.getPointerTy()); 14111 SDValue Ptr = St->getBasePtr(); 14112 14113 // Perform one or more big stores into memory. 14114 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14115 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14116 StoreType, ShuffWide, 14117 DAG.getIntPtrConstant(i)); 14118 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14119 St->getPointerInfo(), St->isVolatile(), 14120 St->isNonTemporal(), St->getAlignment()); 14121 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14122 Chains.push_back(Ch); 14123 } 14124 14125 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14126 Chains.size()); 14127 } 14128 14129 14130 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14131 // the FP state in cases where an emms may be missing. 14132 // A preferable solution to the general problem is to figure out the right 14133 // places to insert EMMS. This qualifies as a quick hack. 14134 14135 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14136 if (VT.getSizeInBits() != 64) 14137 return SDValue(); 14138 14139 const Function *F = DAG.getMachineFunction().getFunction(); 14140 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14141 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14142 && Subtarget->hasSSE2(); 14143 if ((VT.isVector() || 14144 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14145 isa<LoadSDNode>(St->getValue()) && 14146 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14147 St->getChain().hasOneUse() && !St->isVolatile()) { 14148 SDNode* LdVal = St->getValue().getNode(); 14149 LoadSDNode *Ld = 0; 14150 int TokenFactorIndex = -1; 14151 SmallVector<SDValue, 8> Ops; 14152 SDNode* ChainVal = St->getChain().getNode(); 14153 // Must be a store of a load. We currently handle two cases: the load 14154 // is a direct child, and it's under an intervening TokenFactor. It is 14155 // possible to dig deeper under nested TokenFactors. 14156 if (ChainVal == LdVal) 14157 Ld = cast<LoadSDNode>(St->getChain()); 14158 else if (St->getValue().hasOneUse() && 14159 ChainVal->getOpcode() == ISD::TokenFactor) { 14160 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14161 if (ChainVal->getOperand(i).getNode() == LdVal) { 14162 TokenFactorIndex = i; 14163 Ld = cast<LoadSDNode>(St->getValue()); 14164 } else 14165 Ops.push_back(ChainVal->getOperand(i)); 14166 } 14167 } 14168 14169 if (!Ld || !ISD::isNormalLoad(Ld)) 14170 return SDValue(); 14171 14172 // If this is not the MMX case, i.e. we are just turning i64 load/store 14173 // into f64 load/store, avoid the transformation if there are multiple 14174 // uses of the loaded value. 14175 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14176 return SDValue(); 14177 14178 DebugLoc LdDL = Ld->getDebugLoc(); 14179 DebugLoc StDL = N->getDebugLoc(); 14180 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14181 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14182 // pair instead. 14183 if (Subtarget->is64Bit() || F64IsLegal) { 14184 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14185 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14186 Ld->getPointerInfo(), Ld->isVolatile(), 14187 Ld->isNonTemporal(), Ld->isInvariant(), 14188 Ld->getAlignment()); 14189 SDValue NewChain = NewLd.getValue(1); 14190 if (TokenFactorIndex != -1) { 14191 Ops.push_back(NewChain); 14192 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14193 Ops.size()); 14194 } 14195 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14196 St->getPointerInfo(), 14197 St->isVolatile(), St->isNonTemporal(), 14198 St->getAlignment()); 14199 } 14200 14201 // Otherwise, lower to two pairs of 32-bit loads / stores. 14202 SDValue LoAddr = Ld->getBasePtr(); 14203 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14204 DAG.getConstant(4, MVT::i32)); 14205 14206 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14207 Ld->getPointerInfo(), 14208 Ld->isVolatile(), Ld->isNonTemporal(), 14209 Ld->isInvariant(), Ld->getAlignment()); 14210 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14211 Ld->getPointerInfo().getWithOffset(4), 14212 Ld->isVolatile(), Ld->isNonTemporal(), 14213 Ld->isInvariant(), 14214 MinAlign(Ld->getAlignment(), 4)); 14215 14216 SDValue NewChain = LoLd.getValue(1); 14217 if (TokenFactorIndex != -1) { 14218 Ops.push_back(LoLd); 14219 Ops.push_back(HiLd); 14220 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14221 Ops.size()); 14222 } 14223 14224 LoAddr = St->getBasePtr(); 14225 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14226 DAG.getConstant(4, MVT::i32)); 14227 14228 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14229 St->getPointerInfo(), 14230 St->isVolatile(), St->isNonTemporal(), 14231 St->getAlignment()); 14232 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14233 St->getPointerInfo().getWithOffset(4), 14234 St->isVolatile(), 14235 St->isNonTemporal(), 14236 MinAlign(St->getAlignment(), 4)); 14237 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14238 } 14239 return SDValue(); 14240} 14241 14242/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14243/// and return the operands for the horizontal operation in LHS and RHS. A 14244/// horizontal operation performs the binary operation on successive elements 14245/// of its first operand, then on successive elements of its second operand, 14246/// returning the resulting values in a vector. For example, if 14247/// A = < float a0, float a1, float a2, float a3 > 14248/// and 14249/// B = < float b0, float b1, float b2, float b3 > 14250/// then the result of doing a horizontal operation on A and B is 14251/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14252/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14253/// A horizontal-op B, for some already available A and B, and if so then LHS is 14254/// set to A, RHS to B, and the routine returns 'true'. 14255/// Note that the binary operation should have the property that if one of the 14256/// operands is UNDEF then the result is UNDEF. 14257static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14258 // Look for the following pattern: if 14259 // A = < float a0, float a1, float a2, float a3 > 14260 // B = < float b0, float b1, float b2, float b3 > 14261 // and 14262 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14263 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14264 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14265 // which is A horizontal-op B. 14266 14267 // At least one of the operands should be a vector shuffle. 14268 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14269 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14270 return false; 14271 14272 EVT VT = LHS.getValueType(); 14273 14274 assert((VT.is128BitVector() || VT.is256BitVector()) && 14275 "Unsupported vector type for horizontal add/sub"); 14276 14277 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14278 // operate independently on 128-bit lanes. 14279 unsigned NumElts = VT.getVectorNumElements(); 14280 unsigned NumLanes = VT.getSizeInBits()/128; 14281 unsigned NumLaneElts = NumElts / NumLanes; 14282 assert((NumLaneElts % 2 == 0) && 14283 "Vector type should have an even number of elements in each lane"); 14284 unsigned HalfLaneElts = NumLaneElts/2; 14285 14286 // View LHS in the form 14287 // LHS = VECTOR_SHUFFLE A, B, LMask 14288 // If LHS is not a shuffle then pretend it is the shuffle 14289 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14290 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14291 // type VT. 14292 SDValue A, B; 14293 SmallVector<int, 16> LMask(NumElts); 14294 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14295 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14296 A = LHS.getOperand(0); 14297 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14298 B = LHS.getOperand(1); 14299 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14300 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14301 } else { 14302 if (LHS.getOpcode() != ISD::UNDEF) 14303 A = LHS; 14304 for (unsigned i = 0; i != NumElts; ++i) 14305 LMask[i] = i; 14306 } 14307 14308 // Likewise, view RHS in the form 14309 // RHS = VECTOR_SHUFFLE C, D, RMask 14310 SDValue C, D; 14311 SmallVector<int, 16> RMask(NumElts); 14312 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14313 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14314 C = RHS.getOperand(0); 14315 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14316 D = RHS.getOperand(1); 14317 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14318 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14319 } else { 14320 if (RHS.getOpcode() != ISD::UNDEF) 14321 C = RHS; 14322 for (unsigned i = 0; i != NumElts; ++i) 14323 RMask[i] = i; 14324 } 14325 14326 // Check that the shuffles are both shuffling the same vectors. 14327 if (!(A == C && B == D) && !(A == D && B == C)) 14328 return false; 14329 14330 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14331 if (!A.getNode() && !B.getNode()) 14332 return false; 14333 14334 // If A and B occur in reverse order in RHS, then "swap" them (which means 14335 // rewriting the mask). 14336 if (A != C) 14337 CommuteVectorShuffleMask(RMask, NumElts); 14338 14339 // At this point LHS and RHS are equivalent to 14340 // LHS = VECTOR_SHUFFLE A, B, LMask 14341 // RHS = VECTOR_SHUFFLE A, B, RMask 14342 // Check that the masks correspond to performing a horizontal operation. 14343 for (unsigned i = 0; i != NumElts; ++i) { 14344 int LIdx = LMask[i], RIdx = RMask[i]; 14345 14346 // Ignore any UNDEF components. 14347 if (LIdx < 0 || RIdx < 0 || 14348 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14349 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14350 continue; 14351 14352 // Check that successive elements are being operated on. If not, this is 14353 // not a horizontal operation. 14354 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14355 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14356 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14357 if (!(LIdx == Index && RIdx == Index + 1) && 14358 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14359 return false; 14360 } 14361 14362 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14363 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14364 return true; 14365} 14366 14367/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14368static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14369 const X86Subtarget *Subtarget) { 14370 EVT VT = N->getValueType(0); 14371 SDValue LHS = N->getOperand(0); 14372 SDValue RHS = N->getOperand(1); 14373 14374 // Try to synthesize horizontal adds from adds of shuffles. 14375 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14376 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14377 isHorizontalBinOp(LHS, RHS, true)) 14378 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14379 return SDValue(); 14380} 14381 14382/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14383static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14384 const X86Subtarget *Subtarget) { 14385 EVT VT = N->getValueType(0); 14386 SDValue LHS = N->getOperand(0); 14387 SDValue RHS = N->getOperand(1); 14388 14389 // Try to synthesize horizontal subs from subs of shuffles. 14390 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14391 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14392 isHorizontalBinOp(LHS, RHS, false)) 14393 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14394 return SDValue(); 14395} 14396 14397/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14398/// X86ISD::FXOR nodes. 14399static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14400 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14401 // F[X]OR(0.0, x) -> x 14402 // F[X]OR(x, 0.0) -> x 14403 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14404 if (C->getValueAPF().isPosZero()) 14405 return N->getOperand(1); 14406 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14407 if (C->getValueAPF().isPosZero()) 14408 return N->getOperand(0); 14409 return SDValue(); 14410} 14411 14412/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14413static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14414 // FAND(0.0, x) -> 0.0 14415 // FAND(x, 0.0) -> 0.0 14416 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14417 if (C->getValueAPF().isPosZero()) 14418 return N->getOperand(0); 14419 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14420 if (C->getValueAPF().isPosZero()) 14421 return N->getOperand(1); 14422 return SDValue(); 14423} 14424 14425static SDValue PerformBTCombine(SDNode *N, 14426 SelectionDAG &DAG, 14427 TargetLowering::DAGCombinerInfo &DCI) { 14428 // BT ignores high bits in the bit index operand. 14429 SDValue Op1 = N->getOperand(1); 14430 if (Op1.hasOneUse()) { 14431 unsigned BitWidth = Op1.getValueSizeInBits(); 14432 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14433 APInt KnownZero, KnownOne; 14434 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14435 !DCI.isBeforeLegalizeOps()); 14436 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14437 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14438 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14439 DCI.CommitTargetLoweringOpt(TLO); 14440 } 14441 return SDValue(); 14442} 14443 14444static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14445 SDValue Op = N->getOperand(0); 14446 if (Op.getOpcode() == ISD::BITCAST) 14447 Op = Op.getOperand(0); 14448 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14449 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14450 VT.getVectorElementType().getSizeInBits() == 14451 OpVT.getVectorElementType().getSizeInBits()) { 14452 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14453 } 14454 return SDValue(); 14455} 14456 14457static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14458 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14459 // (and (i32 x86isd::setcc_carry), 1) 14460 // This eliminates the zext. This transformation is necessary because 14461 // ISD::SETCC is always legalized to i8. 14462 DebugLoc dl = N->getDebugLoc(); 14463 SDValue N0 = N->getOperand(0); 14464 EVT VT = N->getValueType(0); 14465 if (N0.getOpcode() == ISD::AND && 14466 N0.hasOneUse() && 14467 N0.getOperand(0).hasOneUse()) { 14468 SDValue N00 = N0.getOperand(0); 14469 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14470 return SDValue(); 14471 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14472 if (!C || C->getZExtValue() != 1) 14473 return SDValue(); 14474 return DAG.getNode(ISD::AND, dl, VT, 14475 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14476 N00.getOperand(0), N00.getOperand(1)), 14477 DAG.getConstant(1, VT)); 14478 } 14479 14480 return SDValue(); 14481} 14482 14483// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14484static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14485 unsigned X86CC = N->getConstantOperandVal(0); 14486 SDValue EFLAG = N->getOperand(1); 14487 DebugLoc DL = N->getDebugLoc(); 14488 14489 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14490 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14491 // cases. 14492 if (X86CC == X86::COND_B) 14493 return DAG.getNode(ISD::AND, DL, MVT::i8, 14494 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14495 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14496 DAG.getConstant(1, MVT::i8)); 14497 14498 return SDValue(); 14499} 14500 14501static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14502 const X86TargetLowering *XTLI) { 14503 SDValue Op0 = N->getOperand(0); 14504 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14505 // a 32-bit target where SSE doesn't support i64->FP operations. 14506 if (Op0.getOpcode() == ISD::LOAD) { 14507 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14508 EVT VT = Ld->getValueType(0); 14509 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14510 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14511 !XTLI->getSubtarget()->is64Bit() && 14512 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14513 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14514 Ld->getChain(), Op0, DAG); 14515 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14516 return FILDChain; 14517 } 14518 } 14519 return SDValue(); 14520} 14521 14522// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14523static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14524 X86TargetLowering::DAGCombinerInfo &DCI) { 14525 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14526 // the result is either zero or one (depending on the input carry bit). 14527 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14528 if (X86::isZeroNode(N->getOperand(0)) && 14529 X86::isZeroNode(N->getOperand(1)) && 14530 // We don't have a good way to replace an EFLAGS use, so only do this when 14531 // dead right now. 14532 SDValue(N, 1).use_empty()) { 14533 DebugLoc DL = N->getDebugLoc(); 14534 EVT VT = N->getValueType(0); 14535 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14536 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14537 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14538 DAG.getConstant(X86::COND_B,MVT::i8), 14539 N->getOperand(2)), 14540 DAG.getConstant(1, VT)); 14541 return DCI.CombineTo(N, Res1, CarryOut); 14542 } 14543 14544 return SDValue(); 14545} 14546 14547// fold (add Y, (sete X, 0)) -> adc 0, Y 14548// (add Y, (setne X, 0)) -> sbb -1, Y 14549// (sub (sete X, 0), Y) -> sbb 0, Y 14550// (sub (setne X, 0), Y) -> adc -1, Y 14551static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14552 DebugLoc DL = N->getDebugLoc(); 14553 14554 // Look through ZExts. 14555 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14556 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14557 return SDValue(); 14558 14559 SDValue SetCC = Ext.getOperand(0); 14560 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14561 return SDValue(); 14562 14563 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14564 if (CC != X86::COND_E && CC != X86::COND_NE) 14565 return SDValue(); 14566 14567 SDValue Cmp = SetCC.getOperand(1); 14568 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14569 !X86::isZeroNode(Cmp.getOperand(1)) || 14570 !Cmp.getOperand(0).getValueType().isInteger()) 14571 return SDValue(); 14572 14573 SDValue CmpOp0 = Cmp.getOperand(0); 14574 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14575 DAG.getConstant(1, CmpOp0.getValueType())); 14576 14577 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14578 if (CC == X86::COND_NE) 14579 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14580 DL, OtherVal.getValueType(), OtherVal, 14581 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14582 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14583 DL, OtherVal.getValueType(), OtherVal, 14584 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14585} 14586 14587/// PerformADDCombine - Do target-specific dag combines on integer adds. 14588static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14589 const X86Subtarget *Subtarget) { 14590 EVT VT = N->getValueType(0); 14591 SDValue Op0 = N->getOperand(0); 14592 SDValue Op1 = N->getOperand(1); 14593 14594 // Try to synthesize horizontal adds from adds of shuffles. 14595 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14596 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14597 isHorizontalBinOp(Op0, Op1, true)) 14598 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14599 14600 return OptimizeConditionalInDecrement(N, DAG); 14601} 14602 14603static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14604 const X86Subtarget *Subtarget) { 14605 SDValue Op0 = N->getOperand(0); 14606 SDValue Op1 = N->getOperand(1); 14607 14608 // X86 can't encode an immediate LHS of a sub. See if we can push the 14609 // negation into a preceding instruction. 14610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14611 // If the RHS of the sub is a XOR with one use and a constant, invert the 14612 // immediate. Then add one to the LHS of the sub so we can turn 14613 // X-Y -> X+~Y+1, saving one register. 14614 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14615 isa<ConstantSDNode>(Op1.getOperand(1))) { 14616 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14617 EVT VT = Op0.getValueType(); 14618 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14619 Op1.getOperand(0), 14620 DAG.getConstant(~XorC, VT)); 14621 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14622 DAG.getConstant(C->getAPIntValue()+1, VT)); 14623 } 14624 } 14625 14626 // Try to synthesize horizontal adds from adds of shuffles. 14627 EVT VT = N->getValueType(0); 14628 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14629 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14630 isHorizontalBinOp(Op0, Op1, true)) 14631 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14632 14633 return OptimizeConditionalInDecrement(N, DAG); 14634} 14635 14636SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14637 DAGCombinerInfo &DCI) const { 14638 SelectionDAG &DAG = DCI.DAG; 14639 switch (N->getOpcode()) { 14640 default: break; 14641 case ISD::EXTRACT_VECTOR_ELT: 14642 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14643 case ISD::VSELECT: 14644 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 14645 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14646 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14647 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14648 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14649 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14650 case ISD::SHL: 14651 case ISD::SRA: 14652 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14653 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14654 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14655 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14656 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14657 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14658 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14659 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14660 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14661 case X86ISD::FXOR: 14662 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14663 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14664 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14665 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14666 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14667 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14668 case X86ISD::SHUFP: // Handle all target specific shuffles 14669 case X86ISD::PALIGN: 14670 case X86ISD::UNPCKH: 14671 case X86ISD::UNPCKL: 14672 case X86ISD::MOVHLPS: 14673 case X86ISD::MOVLHPS: 14674 case X86ISD::PSHUFD: 14675 case X86ISD::PSHUFHW: 14676 case X86ISD::PSHUFLW: 14677 case X86ISD::MOVSS: 14678 case X86ISD::MOVSD: 14679 case X86ISD::VPERMILP: 14680 case X86ISD::VPERM2X128: 14681 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14682 } 14683 14684 return SDValue(); 14685} 14686 14687/// isTypeDesirableForOp - Return true if the target has native support for 14688/// the specified value type and it is 'desirable' to use the type for the 14689/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14690/// instruction encodings are longer and some i16 instructions are slow. 14691bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14692 if (!isTypeLegal(VT)) 14693 return false; 14694 if (VT != MVT::i16) 14695 return true; 14696 14697 switch (Opc) { 14698 default: 14699 return true; 14700 case ISD::LOAD: 14701 case ISD::SIGN_EXTEND: 14702 case ISD::ZERO_EXTEND: 14703 case ISD::ANY_EXTEND: 14704 case ISD::SHL: 14705 case ISD::SRL: 14706 case ISD::SUB: 14707 case ISD::ADD: 14708 case ISD::MUL: 14709 case ISD::AND: 14710 case ISD::OR: 14711 case ISD::XOR: 14712 return false; 14713 } 14714} 14715 14716/// IsDesirableToPromoteOp - This method query the target whether it is 14717/// beneficial for dag combiner to promote the specified node. If true, it 14718/// should return the desired promotion type by reference. 14719bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14720 EVT VT = Op.getValueType(); 14721 if (VT != MVT::i16) 14722 return false; 14723 14724 bool Promote = false; 14725 bool Commute = false; 14726 switch (Op.getOpcode()) { 14727 default: break; 14728 case ISD::LOAD: { 14729 LoadSDNode *LD = cast<LoadSDNode>(Op); 14730 // If the non-extending load has a single use and it's not live out, then it 14731 // might be folded. 14732 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14733 Op.hasOneUse()*/) { 14734 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14735 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14736 // The only case where we'd want to promote LOAD (rather then it being 14737 // promoted as an operand is when it's only use is liveout. 14738 if (UI->getOpcode() != ISD::CopyToReg) 14739 return false; 14740 } 14741 } 14742 Promote = true; 14743 break; 14744 } 14745 case ISD::SIGN_EXTEND: 14746 case ISD::ZERO_EXTEND: 14747 case ISD::ANY_EXTEND: 14748 Promote = true; 14749 break; 14750 case ISD::SHL: 14751 case ISD::SRL: { 14752 SDValue N0 = Op.getOperand(0); 14753 // Look out for (store (shl (load), x)). 14754 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14755 return false; 14756 Promote = true; 14757 break; 14758 } 14759 case ISD::ADD: 14760 case ISD::MUL: 14761 case ISD::AND: 14762 case ISD::OR: 14763 case ISD::XOR: 14764 Commute = true; 14765 // fallthrough 14766 case ISD::SUB: { 14767 SDValue N0 = Op.getOperand(0); 14768 SDValue N1 = Op.getOperand(1); 14769 if (!Commute && MayFoldLoad(N1)) 14770 return false; 14771 // Avoid disabling potential load folding opportunities. 14772 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14773 return false; 14774 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14775 return false; 14776 Promote = true; 14777 } 14778 } 14779 14780 PVT = MVT::i32; 14781 return Promote; 14782} 14783 14784//===----------------------------------------------------------------------===// 14785// X86 Inline Assembly Support 14786//===----------------------------------------------------------------------===// 14787 14788namespace { 14789 // Helper to match a string separated by whitespace. 14790 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 14791 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 14792 14793 for (unsigned i = 0, e = args.size(); i != e; ++i) { 14794 StringRef piece(*args[i]); 14795 if (!s.startswith(piece)) // Check if the piece matches. 14796 return false; 14797 14798 s = s.substr(piece.size()); 14799 StringRef::size_type pos = s.find_first_not_of(" \t"); 14800 if (pos == 0) // We matched a prefix. 14801 return false; 14802 14803 s = s.substr(pos); 14804 } 14805 14806 return s.empty(); 14807 } 14808 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 14809} 14810 14811bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14812 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14813 14814 std::string AsmStr = IA->getAsmString(); 14815 14816 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14817 if (!Ty || Ty->getBitWidth() % 16 != 0) 14818 return false; 14819 14820 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14821 SmallVector<StringRef, 4> AsmPieces; 14822 SplitString(AsmStr, AsmPieces, ";\n"); 14823 14824 switch (AsmPieces.size()) { 14825 default: return false; 14826 case 1: 14827 // FIXME: this should verify that we are targeting a 486 or better. If not, 14828 // we will turn this bswap into something that will be lowered to logical 14829 // ops instead of emitting the bswap asm. For now, we don't support 486 or 14830 // lower so don't worry about this. 14831 // bswap $0 14832 if (matchAsm(AsmPieces[0], "bswap", "$0") || 14833 matchAsm(AsmPieces[0], "bswapl", "$0") || 14834 matchAsm(AsmPieces[0], "bswapq", "$0") || 14835 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 14836 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 14837 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 14838 // No need to check constraints, nothing other than the equivalent of 14839 // "=r,0" would be valid here. 14840 return IntrinsicLowering::LowerToByteSwap(CI); 14841 } 14842 14843 // rorw $$8, ${0:w} --> llvm.bswap.i16 14844 if (CI->getType()->isIntegerTy(16) && 14845 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14846 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 14847 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 14848 AsmPieces.clear(); 14849 const std::string &ConstraintsStr = IA->getConstraintString(); 14850 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14851 std::sort(AsmPieces.begin(), AsmPieces.end()); 14852 if (AsmPieces.size() == 4 && 14853 AsmPieces[0] == "~{cc}" && 14854 AsmPieces[1] == "~{dirflag}" && 14855 AsmPieces[2] == "~{flags}" && 14856 AsmPieces[3] == "~{fpsr}") 14857 return IntrinsicLowering::LowerToByteSwap(CI); 14858 } 14859 break; 14860 case 3: 14861 if (CI->getType()->isIntegerTy(32) && 14862 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14863 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 14864 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 14865 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 14866 AsmPieces.clear(); 14867 const std::string &ConstraintsStr = IA->getConstraintString(); 14868 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14869 std::sort(AsmPieces.begin(), AsmPieces.end()); 14870 if (AsmPieces.size() == 4 && 14871 AsmPieces[0] == "~{cc}" && 14872 AsmPieces[1] == "~{dirflag}" && 14873 AsmPieces[2] == "~{flags}" && 14874 AsmPieces[3] == "~{fpsr}") 14875 return IntrinsicLowering::LowerToByteSwap(CI); 14876 } 14877 14878 if (CI->getType()->isIntegerTy(64)) { 14879 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14880 if (Constraints.size() >= 2 && 14881 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14882 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14883 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14884 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 14885 matchAsm(AsmPieces[1], "bswap", "%edx") && 14886 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 14887 return IntrinsicLowering::LowerToByteSwap(CI); 14888 } 14889 } 14890 break; 14891 } 14892 return false; 14893} 14894 14895 14896 14897/// getConstraintType - Given a constraint letter, return the type of 14898/// constraint it is for this target. 14899X86TargetLowering::ConstraintType 14900X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14901 if (Constraint.size() == 1) { 14902 switch (Constraint[0]) { 14903 case 'R': 14904 case 'q': 14905 case 'Q': 14906 case 'f': 14907 case 't': 14908 case 'u': 14909 case 'y': 14910 case 'x': 14911 case 'Y': 14912 case 'l': 14913 return C_RegisterClass; 14914 case 'a': 14915 case 'b': 14916 case 'c': 14917 case 'd': 14918 case 'S': 14919 case 'D': 14920 case 'A': 14921 return C_Register; 14922 case 'I': 14923 case 'J': 14924 case 'K': 14925 case 'L': 14926 case 'M': 14927 case 'N': 14928 case 'G': 14929 case 'C': 14930 case 'e': 14931 case 'Z': 14932 return C_Other; 14933 default: 14934 break; 14935 } 14936 } 14937 return TargetLowering::getConstraintType(Constraint); 14938} 14939 14940/// Examine constraint type and operand type and determine a weight value. 14941/// This object must already have been set up with the operand type 14942/// and the current alternative constraint selected. 14943TargetLowering::ConstraintWeight 14944 X86TargetLowering::getSingleConstraintMatchWeight( 14945 AsmOperandInfo &info, const char *constraint) const { 14946 ConstraintWeight weight = CW_Invalid; 14947 Value *CallOperandVal = info.CallOperandVal; 14948 // If we don't have a value, we can't do a match, 14949 // but allow it at the lowest weight. 14950 if (CallOperandVal == NULL) 14951 return CW_Default; 14952 Type *type = CallOperandVal->getType(); 14953 // Look at the constraint type. 14954 switch (*constraint) { 14955 default: 14956 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14957 case 'R': 14958 case 'q': 14959 case 'Q': 14960 case 'a': 14961 case 'b': 14962 case 'c': 14963 case 'd': 14964 case 'S': 14965 case 'D': 14966 case 'A': 14967 if (CallOperandVal->getType()->isIntegerTy()) 14968 weight = CW_SpecificReg; 14969 break; 14970 case 'f': 14971 case 't': 14972 case 'u': 14973 if (type->isFloatingPointTy()) 14974 weight = CW_SpecificReg; 14975 break; 14976 case 'y': 14977 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14978 weight = CW_SpecificReg; 14979 break; 14980 case 'x': 14981 case 'Y': 14982 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 14983 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 14984 weight = CW_Register; 14985 break; 14986 case 'I': 14987 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14988 if (C->getZExtValue() <= 31) 14989 weight = CW_Constant; 14990 } 14991 break; 14992 case 'J': 14993 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14994 if (C->getZExtValue() <= 63) 14995 weight = CW_Constant; 14996 } 14997 break; 14998 case 'K': 14999 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15000 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15001 weight = CW_Constant; 15002 } 15003 break; 15004 case 'L': 15005 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15006 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15007 weight = CW_Constant; 15008 } 15009 break; 15010 case 'M': 15011 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15012 if (C->getZExtValue() <= 3) 15013 weight = CW_Constant; 15014 } 15015 break; 15016 case 'N': 15017 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15018 if (C->getZExtValue() <= 0xff) 15019 weight = CW_Constant; 15020 } 15021 break; 15022 case 'G': 15023 case 'C': 15024 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15025 weight = CW_Constant; 15026 } 15027 break; 15028 case 'e': 15029 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15030 if ((C->getSExtValue() >= -0x80000000LL) && 15031 (C->getSExtValue() <= 0x7fffffffLL)) 15032 weight = CW_Constant; 15033 } 15034 break; 15035 case 'Z': 15036 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15037 if (C->getZExtValue() <= 0xffffffff) 15038 weight = CW_Constant; 15039 } 15040 break; 15041 } 15042 return weight; 15043} 15044 15045/// LowerXConstraint - try to replace an X constraint, which matches anything, 15046/// with another that has more specific requirements based on the type of the 15047/// corresponding operand. 15048const char *X86TargetLowering:: 15049LowerXConstraint(EVT ConstraintVT) const { 15050 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15051 // 'f' like normal targets. 15052 if (ConstraintVT.isFloatingPoint()) { 15053 if (Subtarget->hasSSE2()) 15054 return "Y"; 15055 if (Subtarget->hasSSE1()) 15056 return "x"; 15057 } 15058 15059 return TargetLowering::LowerXConstraint(ConstraintVT); 15060} 15061 15062/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15063/// vector. If it is invalid, don't add anything to Ops. 15064void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15065 std::string &Constraint, 15066 std::vector<SDValue>&Ops, 15067 SelectionDAG &DAG) const { 15068 SDValue Result(0, 0); 15069 15070 // Only support length 1 constraints for now. 15071 if (Constraint.length() > 1) return; 15072 15073 char ConstraintLetter = Constraint[0]; 15074 switch (ConstraintLetter) { 15075 default: break; 15076 case 'I': 15077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15078 if (C->getZExtValue() <= 31) { 15079 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15080 break; 15081 } 15082 } 15083 return; 15084 case 'J': 15085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15086 if (C->getZExtValue() <= 63) { 15087 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15088 break; 15089 } 15090 } 15091 return; 15092 case 'K': 15093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15094 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15095 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15096 break; 15097 } 15098 } 15099 return; 15100 case 'N': 15101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15102 if (C->getZExtValue() <= 255) { 15103 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15104 break; 15105 } 15106 } 15107 return; 15108 case 'e': { 15109 // 32-bit signed value 15110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15111 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15112 C->getSExtValue())) { 15113 // Widen to 64 bits here to get it sign extended. 15114 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15115 break; 15116 } 15117 // FIXME gcc accepts some relocatable values here too, but only in certain 15118 // memory models; it's complicated. 15119 } 15120 return; 15121 } 15122 case 'Z': { 15123 // 32-bit unsigned value 15124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15125 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15126 C->getZExtValue())) { 15127 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15128 break; 15129 } 15130 } 15131 // FIXME gcc accepts some relocatable values here too, but only in certain 15132 // memory models; it's complicated. 15133 return; 15134 } 15135 case 'i': { 15136 // Literal immediates are always ok. 15137 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15138 // Widen to 64 bits here to get it sign extended. 15139 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15140 break; 15141 } 15142 15143 // In any sort of PIC mode addresses need to be computed at runtime by 15144 // adding in a register or some sort of table lookup. These can't 15145 // be used as immediates. 15146 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15147 return; 15148 15149 // If we are in non-pic codegen mode, we allow the address of a global (with 15150 // an optional displacement) to be used with 'i'. 15151 GlobalAddressSDNode *GA = 0; 15152 int64_t Offset = 0; 15153 15154 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15155 while (1) { 15156 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15157 Offset += GA->getOffset(); 15158 break; 15159 } else if (Op.getOpcode() == ISD::ADD) { 15160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15161 Offset += C->getZExtValue(); 15162 Op = Op.getOperand(0); 15163 continue; 15164 } 15165 } else if (Op.getOpcode() == ISD::SUB) { 15166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15167 Offset += -C->getZExtValue(); 15168 Op = Op.getOperand(0); 15169 continue; 15170 } 15171 } 15172 15173 // Otherwise, this isn't something we can handle, reject it. 15174 return; 15175 } 15176 15177 const GlobalValue *GV = GA->getGlobal(); 15178 // If we require an extra load to get this address, as in PIC mode, we 15179 // can't accept it. 15180 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15181 getTargetMachine()))) 15182 return; 15183 15184 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15185 GA->getValueType(0), Offset); 15186 break; 15187 } 15188 } 15189 15190 if (Result.getNode()) { 15191 Ops.push_back(Result); 15192 return; 15193 } 15194 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15195} 15196 15197std::pair<unsigned, const TargetRegisterClass*> 15198X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15199 EVT VT) const { 15200 // First, see if this is a constraint that directly corresponds to an LLVM 15201 // register class. 15202 if (Constraint.size() == 1) { 15203 // GCC Constraint Letters 15204 switch (Constraint[0]) { 15205 default: break; 15206 // TODO: Slight differences here in allocation order and leaving 15207 // RIP in the class. Do they matter any more here than they do 15208 // in the normal allocation? 15209 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15210 if (Subtarget->is64Bit()) { 15211 if (VT == MVT::i32 || VT == MVT::f32) 15212 return std::make_pair(0U, X86::GR32RegisterClass); 15213 else if (VT == MVT::i16) 15214 return std::make_pair(0U, X86::GR16RegisterClass); 15215 else if (VT == MVT::i8 || VT == MVT::i1) 15216 return std::make_pair(0U, X86::GR8RegisterClass); 15217 else if (VT == MVT::i64 || VT == MVT::f64) 15218 return std::make_pair(0U, X86::GR64RegisterClass); 15219 break; 15220 } 15221 // 32-bit fallthrough 15222 case 'Q': // Q_REGS 15223 if (VT == MVT::i32 || VT == MVT::f32) 15224 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15225 else if (VT == MVT::i16) 15226 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15227 else if (VT == MVT::i8 || VT == MVT::i1) 15228 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15229 else if (VT == MVT::i64) 15230 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15231 break; 15232 case 'r': // GENERAL_REGS 15233 case 'l': // INDEX_REGS 15234 if (VT == MVT::i8 || VT == MVT::i1) 15235 return std::make_pair(0U, X86::GR8RegisterClass); 15236 if (VT == MVT::i16) 15237 return std::make_pair(0U, X86::GR16RegisterClass); 15238 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15239 return std::make_pair(0U, X86::GR32RegisterClass); 15240 return std::make_pair(0U, X86::GR64RegisterClass); 15241 case 'R': // LEGACY_REGS 15242 if (VT == MVT::i8 || VT == MVT::i1) 15243 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15244 if (VT == MVT::i16) 15245 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15246 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15247 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15248 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15249 case 'f': // FP Stack registers. 15250 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15251 // value to the correct fpstack register class. 15252 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15253 return std::make_pair(0U, X86::RFP32RegisterClass); 15254 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15255 return std::make_pair(0U, X86::RFP64RegisterClass); 15256 return std::make_pair(0U, X86::RFP80RegisterClass); 15257 case 'y': // MMX_REGS if MMX allowed. 15258 if (!Subtarget->hasMMX()) break; 15259 return std::make_pair(0U, X86::VR64RegisterClass); 15260 case 'Y': // SSE_REGS if SSE2 allowed 15261 if (!Subtarget->hasSSE2()) break; 15262 // FALL THROUGH. 15263 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15264 if (!Subtarget->hasSSE1()) break; 15265 15266 switch (VT.getSimpleVT().SimpleTy) { 15267 default: break; 15268 // Scalar SSE types. 15269 case MVT::f32: 15270 case MVT::i32: 15271 return std::make_pair(0U, X86::FR32RegisterClass); 15272 case MVT::f64: 15273 case MVT::i64: 15274 return std::make_pair(0U, X86::FR64RegisterClass); 15275 // Vector types. 15276 case MVT::v16i8: 15277 case MVT::v8i16: 15278 case MVT::v4i32: 15279 case MVT::v2i64: 15280 case MVT::v4f32: 15281 case MVT::v2f64: 15282 return std::make_pair(0U, X86::VR128RegisterClass); 15283 // AVX types. 15284 case MVT::v32i8: 15285 case MVT::v16i16: 15286 case MVT::v8i32: 15287 case MVT::v4i64: 15288 case MVT::v8f32: 15289 case MVT::v4f64: 15290 return std::make_pair(0U, X86::VR256RegisterClass); 15291 15292 } 15293 break; 15294 } 15295 } 15296 15297 // Use the default implementation in TargetLowering to convert the register 15298 // constraint into a member of a register class. 15299 std::pair<unsigned, const TargetRegisterClass*> Res; 15300 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15301 15302 // Not found as a standard register? 15303 if (Res.second == 0) { 15304 // Map st(0) -> st(7) -> ST0 15305 if (Constraint.size() == 7 && Constraint[0] == '{' && 15306 tolower(Constraint[1]) == 's' && 15307 tolower(Constraint[2]) == 't' && 15308 Constraint[3] == '(' && 15309 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15310 Constraint[5] == ')' && 15311 Constraint[6] == '}') { 15312 15313 Res.first = X86::ST0+Constraint[4]-'0'; 15314 Res.second = X86::RFP80RegisterClass; 15315 return Res; 15316 } 15317 15318 // GCC allows "st(0)" to be called just plain "st". 15319 if (StringRef("{st}").equals_lower(Constraint)) { 15320 Res.first = X86::ST0; 15321 Res.second = X86::RFP80RegisterClass; 15322 return Res; 15323 } 15324 15325 // flags -> EFLAGS 15326 if (StringRef("{flags}").equals_lower(Constraint)) { 15327 Res.first = X86::EFLAGS; 15328 Res.second = X86::CCRRegisterClass; 15329 return Res; 15330 } 15331 15332 // 'A' means EAX + EDX. 15333 if (Constraint == "A") { 15334 Res.first = X86::EAX; 15335 Res.second = X86::GR32_ADRegisterClass; 15336 return Res; 15337 } 15338 return Res; 15339 } 15340 15341 // Otherwise, check to see if this is a register class of the wrong value 15342 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15343 // turn into {ax},{dx}. 15344 if (Res.second->hasType(VT)) 15345 return Res; // Correct type already, nothing to do. 15346 15347 // All of the single-register GCC register classes map their values onto 15348 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15349 // really want an 8-bit or 32-bit register, map to the appropriate register 15350 // class and return the appropriate register. 15351 if (Res.second == X86::GR16RegisterClass) { 15352 if (VT == MVT::i8) { 15353 unsigned DestReg = 0; 15354 switch (Res.first) { 15355 default: break; 15356 case X86::AX: DestReg = X86::AL; break; 15357 case X86::DX: DestReg = X86::DL; break; 15358 case X86::CX: DestReg = X86::CL; break; 15359 case X86::BX: DestReg = X86::BL; break; 15360 } 15361 if (DestReg) { 15362 Res.first = DestReg; 15363 Res.second = X86::GR8RegisterClass; 15364 } 15365 } else if (VT == MVT::i32) { 15366 unsigned DestReg = 0; 15367 switch (Res.first) { 15368 default: break; 15369 case X86::AX: DestReg = X86::EAX; break; 15370 case X86::DX: DestReg = X86::EDX; break; 15371 case X86::CX: DestReg = X86::ECX; break; 15372 case X86::BX: DestReg = X86::EBX; break; 15373 case X86::SI: DestReg = X86::ESI; break; 15374 case X86::DI: DestReg = X86::EDI; break; 15375 case X86::BP: DestReg = X86::EBP; break; 15376 case X86::SP: DestReg = X86::ESP; break; 15377 } 15378 if (DestReg) { 15379 Res.first = DestReg; 15380 Res.second = X86::GR32RegisterClass; 15381 } 15382 } else if (VT == MVT::i64) { 15383 unsigned DestReg = 0; 15384 switch (Res.first) { 15385 default: break; 15386 case X86::AX: DestReg = X86::RAX; break; 15387 case X86::DX: DestReg = X86::RDX; break; 15388 case X86::CX: DestReg = X86::RCX; break; 15389 case X86::BX: DestReg = X86::RBX; break; 15390 case X86::SI: DestReg = X86::RSI; break; 15391 case X86::DI: DestReg = X86::RDI; break; 15392 case X86::BP: DestReg = X86::RBP; break; 15393 case X86::SP: DestReg = X86::RSP; break; 15394 } 15395 if (DestReg) { 15396 Res.first = DestReg; 15397 Res.second = X86::GR64RegisterClass; 15398 } 15399 } 15400 } else if (Res.second == X86::FR32RegisterClass || 15401 Res.second == X86::FR64RegisterClass || 15402 Res.second == X86::VR128RegisterClass) { 15403 // Handle references to XMM physical registers that got mapped into the 15404 // wrong class. This can happen with constraints like {xmm0} where the 15405 // target independent register mapper will just pick the first match it can 15406 // find, ignoring the required type. 15407 if (VT == MVT::f32) 15408 Res.second = X86::FR32RegisterClass; 15409 else if (VT == MVT::f64) 15410 Res.second = X86::FR64RegisterClass; 15411 else if (X86::VR128RegisterClass->hasType(VT)) 15412 Res.second = X86::VR128RegisterClass; 15413 } 15414 15415 return Res; 15416} 15417