X86ISelLowering.cpp revision a6269ee5fbb6e1237648a47d31f96ba3b4a1bb54
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "Utils/X86ShuffleDecode.h" 18#include "X86.h" 19#include "X86InstrBuilder.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/ADT/SmallSet.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/VariadicFunction.h" 26#include "llvm/CodeGen/IntrinsicLowering.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/IR/CallingConv.h" 34#include "llvm/IR/Constants.h" 35#include "llvm/IR/DerivedTypes.h" 36#include "llvm/IR/Function.h" 37#include "llvm/IR/GlobalAlias.h" 38#include "llvm/IR/GlobalVariable.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/Intrinsics.h" 41#include "llvm/IR/LLVMContext.h" 42#include "llvm/MC/MCAsmInfo.h" 43#include "llvm/MC/MCContext.h" 44#include "llvm/MC/MCExpr.h" 45#include "llvm/MC/MCSymbol.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52#include <cctype> 53using namespace llvm; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57// Forward declarations. 58static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, 59 SDValue V2); 60 61static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal, 62 SelectionDAG &DAG, SDLoc dl, 63 unsigned vectorWidth) { 64 assert((vectorWidth == 128 || vectorWidth == 256) && 65 "Unsupported vector width"); 66 EVT VT = Vec.getValueType(); 67 EVT ElVT = VT.getVectorElementType(); 68 unsigned Factor = VT.getSizeInBits()/vectorWidth; 69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 70 VT.getVectorNumElements()/Factor); 71 72 // Extract from UNDEF is UNDEF. 73 if (Vec.getOpcode() == ISD::UNDEF) 74 return DAG.getUNDEF(ResultVT); 75 76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR 77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits(); 78 79 // This is the index of the first element of the vectorWidth-bit chunk 80 // we want. 81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth) 82 * ElemsPerChunk); 83 84 // If the input is a buildvector just emit a smaller one. 85 if (Vec.getOpcode() == ISD::BUILD_VECTOR) 86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, 87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk); 88 89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 91 VecIdx); 92 93 return Result; 94 95} 96/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 97/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128 98/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4 99/// instructions or a simple subregister reference. Idx is an index in the 100/// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes 101/// lowering EXTRACT_VECTOR_ELT operations easier. 102static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 103 SelectionDAG &DAG, SDLoc dl) { 104 assert((Vec.getValueType().is256BitVector() || 105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!"); 106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128); 107} 108 109/// Generate a DAG to grab 256-bits from a 512-bit vector. 110static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal, 111 SelectionDAG &DAG, SDLoc dl) { 112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!"); 113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256); 114} 115 116static SDValue InsertSubVector(SDValue Result, SDValue Vec, 117 unsigned IdxVal, SelectionDAG &DAG, 118 SDLoc dl, unsigned vectorWidth) { 119 assert((vectorWidth == 128 || vectorWidth == 256) && 120 "Unsupported vector width"); 121 // Inserting UNDEF is Result 122 if (Vec.getOpcode() == ISD::UNDEF) 123 return Result; 124 EVT VT = Vec.getValueType(); 125 EVT ElVT = VT.getVectorElementType(); 126 EVT ResultVT = Result.getValueType(); 127 128 // Insert the relevant vectorWidth bits. 129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits(); 130 131 // This is the index of the first element of the vectorWidth-bit chunk 132 // we want. 133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth) 134 * ElemsPerChunk); 135 136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 138 VecIdx); 139} 140/// Generate a DAG to put 128-bits into a vector > 128 bits. This 141/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or 142/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a 143/// simple superregister reference. Idx is an index in the 128 bits 144/// we want. It need not be aligned to a 128-bit bounday. That makes 145/// lowering INSERT_VECTOR_ELT operations easier. 146static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 147 unsigned IdxVal, SelectionDAG &DAG, 148 SDLoc dl) { 149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!"); 150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128); 151} 152 153static SDValue Insert256BitVector(SDValue Result, SDValue Vec, 154 unsigned IdxVal, SelectionDAG &DAG, 155 SDLoc dl) { 156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!"); 157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256); 158} 159 160/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 161/// instructions. This is used because creating CONCAT_VECTOR nodes of 162/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 163/// large BUILD_VECTORS. 164static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 165 unsigned NumElems, SelectionDAG &DAG, 166 SDLoc dl) { 167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 169} 170 171static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, 172 unsigned NumElems, SelectionDAG &DAG, 173 SDLoc dl) { 174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl); 176} 177 178static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 180 bool is64Bit = Subtarget->is64Bit(); 181 182 if (Subtarget->isTargetEnvMacho()) { 183 if (is64Bit) 184 return new X86_64MachoTargetObjectFile(); 185 return new TargetLoweringObjectFileMachO(); 186 } 187 188 if (Subtarget->isTargetLinux()) 189 return new X86LinuxTargetObjectFile(); 190 if (Subtarget->isTargetELF()) 191 return new TargetLoweringObjectFileELF(); 192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 193 return new TargetLoweringObjectFileCOFF(); 194 llvm_unreachable("unknown subtarget type"); 195} 196 197X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 198 : TargetLowering(TM, createTLOF(TM)) { 199 Subtarget = &TM.getSubtarget<X86Subtarget>(); 200 X86ScalarSSEf64 = Subtarget->hasSSE2(); 201 X86ScalarSSEf32 = Subtarget->hasSSE1(); 202 TD = getDataLayout(); 203 204 resetOperationActions(); 205} 206 207void X86TargetLowering::resetOperationActions() { 208 const TargetMachine &TM = getTargetMachine(); 209 static bool FirstTimeThrough = true; 210 211 // If none of the target options have changed, then we don't need to reset the 212 // operation actions. 213 if (!FirstTimeThrough && TO == TM.Options) return; 214 215 if (!FirstTimeThrough) { 216 // Reinitialize the actions. 217 initActions(); 218 FirstTimeThrough = false; 219 } 220 221 TO = TM.Options; 222 223 // Set up the TargetLowering object. 224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 225 226 // X86 is weird, it always uses i8 for shift amounts and setcc results. 227 setBooleanContents(ZeroOrOneBooleanContent); 228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 230 231 // For 64-bit since we have so many registers use the ILP scheduler, for 232 // 32-bit code use the register pressure specific scheduling. 233 // For Atom, always use ILP scheduling. 234 if (Subtarget->isAtom()) 235 setSchedulingPreference(Sched::ILP); 236 else if (Subtarget->is64Bit()) 237 setSchedulingPreference(Sched::ILP); 238 else 239 setSchedulingPreference(Sched::RegPressure); 240 const X86RegisterInfo *RegInfo = 241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); 242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister()); 243 244 // Bypass expensive divides on Atom when compiling with O2 245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) { 246 addBypassSlowDiv(32, 8); 247 if (Subtarget->is64Bit()) 248 addBypassSlowDiv(64, 16); 249 } 250 251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 252 // Setup Windows compiler runtime calls. 253 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 255 setLibcallName(RTLIB::SREM_I64, "_allrem"); 256 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 257 setLibcallName(RTLIB::MUL_I64, "_allmul"); 258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 263 264 // The _ftol2 runtime function has an unusual calling conv, which 265 // is modeled by a special pseudo-instruction. 266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 270 } 271 272 if (Subtarget->isTargetDarwin()) { 273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 274 setUseUnderscoreSetJmp(false); 275 setUseUnderscoreLongJmp(false); 276 } else if (Subtarget->isTargetMingw()) { 277 // MS runtime is weird: it exports _setjmp, but longjmp! 278 setUseUnderscoreSetJmp(true); 279 setUseUnderscoreLongJmp(false); 280 } else { 281 setUseUnderscoreSetJmp(true); 282 setUseUnderscoreLongJmp(true); 283 } 284 285 // Set up the register classes. 286 addRegisterClass(MVT::i8, &X86::GR8RegClass); 287 addRegisterClass(MVT::i16, &X86::GR16RegClass); 288 addRegisterClass(MVT::i32, &X86::GR32RegClass); 289 if (Subtarget->is64Bit()) 290 addRegisterClass(MVT::i64, &X86::GR64RegClass); 291 292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 293 294 // We don't accept any truncstore of integer registers. 295 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 296 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 298 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 300 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 301 302 // SETOEQ and SETUNE require checking two conditions. 303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 309 310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 311 // operation. 312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 315 316 if (Subtarget->is64Bit()) { 317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 319 } else if (!TM.Options.UseSoftFloat) { 320 // We have an algorithm for SSE2->double, and we turn this into a 321 // 64-bit FILD followed by conditional FADD for other targets. 322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 323 // We have an algorithm for SSE2, and we turn this into a 64-bit 324 // FILD for other targets. 325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 326 } 327 328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 329 // this operation. 330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 332 333 if (!TM.Options.UseSoftFloat) { 334 // SSE has no i16 to fp conversion, only i32 335 if (X86ScalarSSEf32) { 336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 337 // f32 and f64 cases are Legal, f80 case is not 338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 339 } else { 340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 342 } 343 } else { 344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 346 } 347 348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 349 // are Legal, f80 is custom lowered. 350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 352 353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 354 // this operation. 355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 357 358 if (X86ScalarSSEf32) { 359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 360 // f32 and f64 cases are Legal, f80 case is not 361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 362 } else { 363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 365 } 366 367 // Handle FP_TO_UINT by promoting the destination to a larger signed 368 // conversion. 369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 372 373 if (Subtarget->is64Bit()) { 374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 376 } else if (!TM.Options.UseSoftFloat) { 377 // Since AVX is a superset of SSE3, only check for SSE here. 378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 379 // Expand FP_TO_UINT into a select. 380 // FIXME: We would like to use a Custom expander here eventually to do 381 // the optimal thing for SSE vs. the default expansion in the legalizer. 382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 383 else 384 // With SSE3 we can use fisttpll to convert to a signed i64; without 385 // SSE, we're stuck with a fistpll. 386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 387 } 388 389 if (isTargetFTOL()) { 390 // Use the _ftol2 runtime function, which has a pseudo-instruction 391 // to handle its weird calling convention. 392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 393 } 394 395 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 396 if (!X86ScalarSSEf64) { 397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 399 if (Subtarget->is64Bit()) { 400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 401 // Without SSE, i64->f64 goes through memory. 402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 403 } 404 } 405 406 // Scalar integer divide and remainder are lowered to use operations that 407 // produce two results, to match the available instructions. This exposes 408 // the two-result form to trivial CSE, which is able to combine x/y and x%y 409 // into a single instruction. 410 // 411 // Scalar integer multiply-high is also lowered to use two-result 412 // operations, to match the available instructions. However, plain multiply 413 // (low) operations are left as Legal, as there are single-result 414 // instructions for this in x86. Using the two-result multiply instructions 415 // when both high and low results are needed must be arranged by dagcombine. 416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 417 MVT VT = IntVTs[i]; 418 setOperationAction(ISD::MULHS, VT, Expand); 419 setOperationAction(ISD::MULHU, VT, Expand); 420 setOperationAction(ISD::SDIV, VT, Expand); 421 setOperationAction(ISD::UDIV, VT, Expand); 422 setOperationAction(ISD::SREM, VT, Expand); 423 setOperationAction(ISD::UREM, VT, Expand); 424 425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 426 setOperationAction(ISD::ADDC, VT, Custom); 427 setOperationAction(ISD::ADDE, VT, Custom); 428 setOperationAction(ISD::SUBC, VT, Custom); 429 setOperationAction(ISD::SUBE, VT, Custom); 430 } 431 432 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 433 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 434 setOperationAction(ISD::BR_CC , MVT::f32, Expand); 435 setOperationAction(ISD::BR_CC , MVT::f64, Expand); 436 setOperationAction(ISD::BR_CC , MVT::f80, Expand); 437 setOperationAction(ISD::BR_CC , MVT::i8, Expand); 438 setOperationAction(ISD::BR_CC , MVT::i16, Expand); 439 setOperationAction(ISD::BR_CC , MVT::i32, Expand); 440 setOperationAction(ISD::BR_CC , MVT::i64, Expand); 441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 442 if (Subtarget->is64Bit()) 443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 448 setOperationAction(ISD::FREM , MVT::f32 , Expand); 449 setOperationAction(ISD::FREM , MVT::f64 , Expand); 450 setOperationAction(ISD::FREM , MVT::f80 , Expand); 451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 452 453 // Promote the i8 variants and force them on up to i32 which has a shorter 454 // encoding. 455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 459 if (Subtarget->hasBMI()) { 460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 462 if (Subtarget->is64Bit()) 463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 464 } else { 465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 467 if (Subtarget->is64Bit()) 468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 469 } 470 471 if (Subtarget->hasLZCNT()) { 472 // When promoting the i8 variants, force them to i32 for a shorter 473 // encoding. 474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 480 if (Subtarget->is64Bit()) 481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 482 } else { 483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 489 if (Subtarget->is64Bit()) { 490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 492 } 493 } 494 495 if (Subtarget->hasPOPCNT()) { 496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 497 } else { 498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 501 if (Subtarget->is64Bit()) 502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 503 } 504 505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 507 508 // These should be promoted to a larger select which is supported. 509 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 510 // X86 wants to expand cmov itself. 511 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 512 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 513 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 514 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 515 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 516 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 517 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 518 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 519 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 520 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 521 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 522 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 523 if (Subtarget->is64Bit()) { 524 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 525 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 526 } 527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support 529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to 530 // support continuation, user-level threading, and etc.. As a result, no 531 // other SjLj exception interfaces are implemented and please don't build 532 // your own exception handling based on them. 533 // LLVM/Clang supports zero-cost DWARF exception handling. 534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 536 537 // Darwin ABI issue. 538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 542 if (Subtarget->is64Bit()) 543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 546 if (Subtarget->is64Bit()) { 547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 552 } 553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 557 if (Subtarget->is64Bit()) { 558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 561 } 562 563 if (Subtarget->hasSSE1()) 564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 565 566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 567 568 // Expand certain atomics 569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 570 MVT VT = IntVTs[i]; 571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 574 } 575 576 if (!Subtarget->is64Bit()) { 577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom); 586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom); 587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom); 588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom); 589 } 590 591 if (Subtarget->hasCmpxchg16b()) { 592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 593 } 594 595 // FIXME - use subtarget debug flags 596 if (!Subtarget->isTargetDarwin() && 597 !Subtarget->isTargetELF() && 598 !Subtarget->isTargetCygMing()) { 599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 600 } 601 602 if (Subtarget->is64Bit()) { 603 setExceptionPointerRegister(X86::RAX); 604 setExceptionSelectorRegister(X86::RDX); 605 } else { 606 setExceptionPointerRegister(X86::EAX); 607 setExceptionSelectorRegister(X86::EDX); 608 } 609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 611 612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 614 615 setOperationAction(ISD::TRAP, MVT::Other, Legal); 616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); 617 618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 619 setOperationAction(ISD::VASTART , MVT::Other, Custom); 620 setOperationAction(ISD::VAEND , MVT::Other, Expand); 621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) { 622 // TargetInfo::X86_64ABIBuiltinVaList 623 setOperationAction(ISD::VAARG , MVT::Other, Custom); 624 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 625 } else { 626 // TargetInfo::CharPtrBuiltinVaList 627 setOperationAction(ISD::VAARG , MVT::Other, Expand); 628 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 629 } 630 631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 633 634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 636 MVT::i64 : MVT::i32, Custom); 637 else if (TM.Options.EnableSegmentedStacks) 638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 639 MVT::i64 : MVT::i32, Custom); 640 else 641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 642 MVT::i64 : MVT::i32, Expand); 643 644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 645 // f32 and f64 use SSE. 646 // Set up the FP register classes. 647 addRegisterClass(MVT::f32, &X86::FR32RegClass); 648 addRegisterClass(MVT::f64, &X86::FR64RegClass); 649 650 // Use ANDPD to simulate FABS. 651 setOperationAction(ISD::FABS , MVT::f64, Custom); 652 setOperationAction(ISD::FABS , MVT::f32, Custom); 653 654 // Use XORP to simulate FNEG. 655 setOperationAction(ISD::FNEG , MVT::f64, Custom); 656 setOperationAction(ISD::FNEG , MVT::f32, Custom); 657 658 // Use ANDPD and ORPD to simulate FCOPYSIGN. 659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 661 662 // Lower this to FGETSIGNx86 plus an AND. 663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 665 666 // We don't support sin/cos/fmod 667 setOperationAction(ISD::FSIN , MVT::f64, Expand); 668 setOperationAction(ISD::FCOS , MVT::f64, Expand); 669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 670 setOperationAction(ISD::FSIN , MVT::f32, Expand); 671 setOperationAction(ISD::FCOS , MVT::f32, Expand); 672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 673 674 // Expand FP immediates into loads from the stack, except for the special 675 // cases we handle. 676 addLegalFPImmediate(APFloat(+0.0)); // xorpd 677 addLegalFPImmediate(APFloat(+0.0f)); // xorps 678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 679 // Use SSE for f32, x87 for f64. 680 // Set up the FP register classes. 681 addRegisterClass(MVT::f32, &X86::FR32RegClass); 682 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 683 684 // Use ANDPS to simulate FABS. 685 setOperationAction(ISD::FABS , MVT::f32, Custom); 686 687 // Use XORP to simulate FNEG. 688 setOperationAction(ISD::FNEG , MVT::f32, Custom); 689 690 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 691 692 // Use ANDPS and ORPS to simulate FCOPYSIGN. 693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 695 696 // We don't support sin/cos/fmod 697 setOperationAction(ISD::FSIN , MVT::f32, Expand); 698 setOperationAction(ISD::FCOS , MVT::f32, Expand); 699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 700 701 // Special cases we handle for FP constants. 702 addLegalFPImmediate(APFloat(+0.0f)); // xorps 703 addLegalFPImmediate(APFloat(+0.0)); // FLD0 704 addLegalFPImmediate(APFloat(+1.0)); // FLD1 705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 707 708 if (!TM.Options.UnsafeFPMath) { 709 setOperationAction(ISD::FSIN , MVT::f64, Expand); 710 setOperationAction(ISD::FCOS , MVT::f64, Expand); 711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 712 } 713 } else if (!TM.Options.UseSoftFloat) { 714 // f32 and f64 in x87. 715 // Set up the FP register classes. 716 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 717 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 718 719 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 720 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 723 724 if (!TM.Options.UnsafeFPMath) { 725 setOperationAction(ISD::FSIN , MVT::f64, Expand); 726 setOperationAction(ISD::FSIN , MVT::f32, Expand); 727 setOperationAction(ISD::FCOS , MVT::f64, Expand); 728 setOperationAction(ISD::FCOS , MVT::f32, Expand); 729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 731 } 732 addLegalFPImmediate(APFloat(+0.0)); // FLD0 733 addLegalFPImmediate(APFloat(+1.0)); // FLD1 734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 740 } 741 742 // We don't support FMA. 743 setOperationAction(ISD::FMA, MVT::f64, Expand); 744 setOperationAction(ISD::FMA, MVT::f32, Expand); 745 746 // Long double always uses X87. 747 if (!TM.Options.UseSoftFloat) { 748 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 749 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 751 { 752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 753 addLegalFPImmediate(TmpFlt); // FLD0 754 TmpFlt.changeSign(); 755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 756 757 bool ignored; 758 APFloat TmpFlt2(+1.0); 759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 760 &ignored); 761 addLegalFPImmediate(TmpFlt2); // FLD1 762 TmpFlt2.changeSign(); 763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 764 } 765 766 if (!TM.Options.UnsafeFPMath) { 767 setOperationAction(ISD::FSIN , MVT::f80, Expand); 768 setOperationAction(ISD::FCOS , MVT::f80, Expand); 769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); 770 } 771 772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 773 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 775 setOperationAction(ISD::FRINT, MVT::f80, Expand); 776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 777 setOperationAction(ISD::FMA, MVT::f80, Expand); 778 } 779 780 // Always use a library call for pow. 781 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 782 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 783 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 784 785 setOperationAction(ISD::FLOG, MVT::f80, Expand); 786 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 787 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 788 setOperationAction(ISD::FEXP, MVT::f80, Expand); 789 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 790 791 // First set operation action for all vector types to either promote 792 // (for widening) or expand (for scalarization). Then we will selectively 793 // turn on ones that can be effectively codegen'd. 794 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 796 MVT VT = (MVT::SimpleValueType)i; 797 setOperationAction(ISD::ADD , VT, Expand); 798 setOperationAction(ISD::SUB , VT, Expand); 799 setOperationAction(ISD::FADD, VT, Expand); 800 setOperationAction(ISD::FNEG, VT, Expand); 801 setOperationAction(ISD::FSUB, VT, Expand); 802 setOperationAction(ISD::MUL , VT, Expand); 803 setOperationAction(ISD::FMUL, VT, Expand); 804 setOperationAction(ISD::SDIV, VT, Expand); 805 setOperationAction(ISD::UDIV, VT, Expand); 806 setOperationAction(ISD::FDIV, VT, Expand); 807 setOperationAction(ISD::SREM, VT, Expand); 808 setOperationAction(ISD::UREM, VT, Expand); 809 setOperationAction(ISD::LOAD, VT, Expand); 810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); 811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); 812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); 814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); 815 setOperationAction(ISD::FABS, VT, Expand); 816 setOperationAction(ISD::FSIN, VT, Expand); 817 setOperationAction(ISD::FSINCOS, VT, Expand); 818 setOperationAction(ISD::FCOS, VT, Expand); 819 setOperationAction(ISD::FSINCOS, VT, Expand); 820 setOperationAction(ISD::FREM, VT, Expand); 821 setOperationAction(ISD::FMA, VT, Expand); 822 setOperationAction(ISD::FPOWI, VT, Expand); 823 setOperationAction(ISD::FSQRT, VT, Expand); 824 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 825 setOperationAction(ISD::FFLOOR, VT, Expand); 826 setOperationAction(ISD::FCEIL, VT, Expand); 827 setOperationAction(ISD::FTRUNC, VT, Expand); 828 setOperationAction(ISD::FRINT, VT, Expand); 829 setOperationAction(ISD::FNEARBYINT, VT, Expand); 830 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 831 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 832 setOperationAction(ISD::SDIVREM, VT, Expand); 833 setOperationAction(ISD::UDIVREM, VT, Expand); 834 setOperationAction(ISD::FPOW, VT, Expand); 835 setOperationAction(ISD::CTPOP, VT, Expand); 836 setOperationAction(ISD::CTTZ, VT, Expand); 837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 838 setOperationAction(ISD::CTLZ, VT, Expand); 839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 840 setOperationAction(ISD::SHL, VT, Expand); 841 setOperationAction(ISD::SRA, VT, Expand); 842 setOperationAction(ISD::SRL, VT, Expand); 843 setOperationAction(ISD::ROTL, VT, Expand); 844 setOperationAction(ISD::ROTR, VT, Expand); 845 setOperationAction(ISD::BSWAP, VT, Expand); 846 setOperationAction(ISD::SETCC, VT, Expand); 847 setOperationAction(ISD::FLOG, VT, Expand); 848 setOperationAction(ISD::FLOG2, VT, Expand); 849 setOperationAction(ISD::FLOG10, VT, Expand); 850 setOperationAction(ISD::FEXP, VT, Expand); 851 setOperationAction(ISD::FEXP2, VT, Expand); 852 setOperationAction(ISD::FP_TO_UINT, VT, Expand); 853 setOperationAction(ISD::FP_TO_SINT, VT, Expand); 854 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 855 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand); 857 setOperationAction(ISD::TRUNCATE, VT, Expand); 858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); 859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); 860 setOperationAction(ISD::ANY_EXTEND, VT, Expand); 861 setOperationAction(ISD::VSELECT, VT, Expand); 862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 864 setTruncStoreAction(VT, 865 (MVT::SimpleValueType)InnerVT, Expand); 866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 868 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 869 } 870 871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 872 // with -msoft-float, disable use of MMX as well. 873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 875 // No operations on x86mmx supported, everything uses intrinsics. 876 } 877 878 // MMX-sized vectors (other than x86mmx) are expected to be expanded 879 // into smaller operations. 880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 884 setOperationAction(ISD::AND, MVT::v8i8, Expand); 885 setOperationAction(ISD::AND, MVT::v4i16, Expand); 886 setOperationAction(ISD::AND, MVT::v2i32, Expand); 887 setOperationAction(ISD::AND, MVT::v1i64, Expand); 888 setOperationAction(ISD::OR, MVT::v8i8, Expand); 889 setOperationAction(ISD::OR, MVT::v4i16, Expand); 890 setOperationAction(ISD::OR, MVT::v2i32, Expand); 891 setOperationAction(ISD::OR, MVT::v1i64, Expand); 892 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 893 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 894 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 895 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 909 910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 912 913 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 919 setOperationAction(ISD::FABS, MVT::v4f32, Custom); 920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 925 } 926 927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 929 930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 931 // registers cannot be used even for integer operations. 932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 936 937 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 938 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 939 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 940 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 941 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 942 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 943 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 944 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 945 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 946 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 947 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 948 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 954 setOperationAction(ISD::FABS, MVT::v2f64, Custom); 955 956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 960 961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 966 967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 969 MVT VT = (MVT::SimpleValueType)i; 970 // Do not attempt to custom lower non-power-of-2 vectors 971 if (!isPowerOf2_32(VT.getVectorNumElements())) 972 continue; 973 // Do not attempt to custom lower non-128-bit vectors 974 if (!VT.is128BitVector()) 975 continue; 976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 979 } 980 981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 987 988 if (Subtarget->is64Bit()) { 989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 991 } 992 993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 995 MVT VT = (MVT::SimpleValueType)i; 996 997 // Do not attempt to promote non-128-bit vectors 998 if (!VT.is128BitVector()) 999 continue; 1000 1001 setOperationAction(ISD::AND, VT, Promote); 1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64); 1003 setOperationAction(ISD::OR, VT, Promote); 1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64); 1005 setOperationAction(ISD::XOR, VT, Promote); 1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64); 1007 setOperationAction(ISD::LOAD, VT, Promote); 1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); 1009 setOperationAction(ISD::SELECT, VT, Promote); 1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); 1011 } 1012 1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1014 1015 // Custom lower v2i64 and v2f64 selects. 1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 1020 1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 1023 1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); 1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 1026 // As there is no 64-bit GPR available, we need build a special custom 1027 // sequence to convert from v2i32 to v2f32. 1028 if (!Subtarget->is64Bit()) 1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom); 1030 1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); 1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom); 1033 1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal); 1035 } 1036 1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) { 1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 1041 setOperationAction(ISD::FRINT, MVT::f32, Legal); 1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 1046 setOperationAction(ISD::FRINT, MVT::f64, Legal); 1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 1048 1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); 1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); 1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); 1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); 1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); 1059 1060 // FIXME: Do we need to handle scalar-to-vector here? 1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 1062 1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 1068 1069 // i8 and i16 vectors are custom , because the source register and source 1070 // source memory operand types are not the same width. f32 vectors are 1071 // custom since the immediate controlling the insert encodes additional 1072 // information. 1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 1077 1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 1082 1083 // FIXME: these should be Legal but thats only for the case where 1084 // the index is constant. For now custom expand to deal with that. 1085 if (Subtarget->is64Bit()) { 1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 1088 } 1089 } 1090 1091 if (Subtarget->hasSSE2()) { 1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 1094 1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 1097 1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 1100 1101 // In the customized shift lowering, the legal cases in AVX2 will be 1102 // recognized. 1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1105 1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1108 1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1110 1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom); 1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom); 1113 } 1114 1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) { 1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1122 1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1126 1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); 1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); 1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal); 1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal); 1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal); 1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom); 1139 1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); 1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); 1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); 1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal); 1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal); 1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom); 1152 1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); 1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom); 1155 1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); 1157 1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); 1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1162 1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); 1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); 1166 1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal); 1168 1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1171 1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1174 1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1177 1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom); 1179 1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1184 1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1188 1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1193 1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); 1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); 1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); 1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom); 1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); 1200 1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) { 1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal); 1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal); 1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1206 setOperationAction(ISD::FMA, MVT::f32, Legal); 1207 setOperationAction(ISD::FMA, MVT::f64, Legal); 1208 } 1209 1210 if (Subtarget->hasInt256()) { 1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1215 1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1220 1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1224 // Don't lower v32i8 because there is no 128-bit byte mul 1225 1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1227 1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom); 1229 } else { 1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1234 1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1239 1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1243 // Don't lower v32i8 because there is no 128-bit byte mul 1244 } 1245 1246 // In the customized shift lowering, the legal cases in AVX2 will be 1247 // recognized. 1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1250 1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1253 1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1255 1256 // Custom lower several nodes for 256-bit types. 1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1259 MVT VT = (MVT::SimpleValueType)i; 1260 1261 // Extract subvector is special because the value type 1262 // (result) is 128-bit but the source is 256-bit wide. 1263 if (VT.is128BitVector()) 1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1265 1266 // Do not attempt to custom lower other non-256-bit vectors 1267 if (!VT.is256BitVector()) 1268 continue; 1269 1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1277 } 1278 1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1281 MVT VT = (MVT::SimpleValueType)i; 1282 1283 // Do not attempt to promote non-256-bit vectors 1284 if (!VT.is256BitVector()) 1285 continue; 1286 1287 setOperationAction(ISD::AND, VT, Promote); 1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 1289 setOperationAction(ISD::OR, VT, Promote); 1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 1291 setOperationAction(ISD::XOR, VT, Promote); 1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 1293 setOperationAction(ISD::LOAD, VT, Promote); 1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 1295 setOperationAction(ISD::SELECT, VT, Promote); 1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 1297 } 1298 } 1299 1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) { 1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); 1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass); 1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass); 1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass); 1305 1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass); 1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass); 1308 1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal); 1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal); 1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal); 1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal); 1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal); 1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal); 1315 1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal); 1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal); 1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal); 1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal); 1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal); 1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom); 1322 1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal); 1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal); 1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal); 1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal); 1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal); 1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom); 1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal); 1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal); 1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom); 1332 1333 1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); 1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal); 1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal); 1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal); 1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); 1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal); 1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal); 1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal); 1342 1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal); 1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); 1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom); 1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom); 1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); 1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); 1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); 1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); 1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); 1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom); 1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom); 1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); 1355 1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); 1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); 1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); 1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); 1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom); 1361 1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); 1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom); 1364 1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom); 1366 1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom); 1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom); 1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom); 1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom); 1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom); 1372 1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal); 1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal); 1375 1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal); 1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal); 1378 1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal); 1380 1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom); 1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom); 1383 1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom); 1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom); 1386 1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom); 1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom); 1389 1390 setOperationAction(ISD::AND, MVT::v8i64, Legal); 1391 setOperationAction(ISD::OR, MVT::v8i64, Legal); 1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal); 1393 setOperationAction(ISD::AND, MVT::v16i32, Legal); 1394 setOperationAction(ISD::OR, MVT::v16i32, Legal); 1395 setOperationAction(ISD::XOR, MVT::v16i32, Legal); 1396 1397 // Custom lower several nodes. 1398 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1399 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1400 MVT VT = (MVT::SimpleValueType)i; 1401 1402 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 1403 // Extract subvector is special because the value type 1404 // (result) is 256/128-bit but the source is 512-bit wide. 1405 if (VT.is128BitVector() || VT.is256BitVector()) 1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1407 1408 if (VT.getVectorElementType() == MVT::i1) 1409 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); 1410 1411 // Do not attempt to custom lower other non-512-bit vectors 1412 if (!VT.is512BitVector()) 1413 continue; 1414 1415 if ( EltSize >= 32) { 1416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1417 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1418 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 1419 setOperationAction(ISD::VSELECT, VT, Legal); 1420 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1421 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 1422 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1423 } 1424 } 1425 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) { 1426 MVT VT = (MVT::SimpleValueType)i; 1427 1428 // Do not attempt to promote non-256-bit vectors 1429 if (!VT.is512BitVector()) 1430 continue; 1431 1432 setOperationAction(ISD::SELECT, VT, Promote); 1433 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64); 1434 } 1435 }// has AVX-512 1436 1437 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1438 // of this type with custom code. 1439 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1440 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1441 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1442 Custom); 1443 } 1444 1445 // We want to custom lower some of our intrinsics. 1446 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1447 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 1448 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 1449 1450 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1451 // handle type legalization for these operations here. 1452 // 1453 // FIXME: We really should do custom legalization for addition and 1454 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1455 // than generic legalization for 64-bit multiplication-with-overflow, though. 1456 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1457 // Add/Sub/Mul with overflow operations are custom lowered. 1458 MVT VT = IntVTs[i]; 1459 setOperationAction(ISD::SADDO, VT, Custom); 1460 setOperationAction(ISD::UADDO, VT, Custom); 1461 setOperationAction(ISD::SSUBO, VT, Custom); 1462 setOperationAction(ISD::USUBO, VT, Custom); 1463 setOperationAction(ISD::SMULO, VT, Custom); 1464 setOperationAction(ISD::UMULO, VT, Custom); 1465 } 1466 1467 // There are no 8-bit 3-address imul/mul instructions 1468 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1469 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1470 1471 if (!Subtarget->is64Bit()) { 1472 // These libcalls are not available in 32-bit. 1473 setLibcallName(RTLIB::SHL_I128, 0); 1474 setLibcallName(RTLIB::SRL_I128, 0); 1475 setLibcallName(RTLIB::SRA_I128, 0); 1476 } 1477 1478 // Combine sin / cos into one node or libcall if possible. 1479 if (Subtarget->hasSinCos()) { 1480 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 1481 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 1482 if (Subtarget->isTargetDarwin()) { 1483 // For MacOSX, we don't want to the normal expansion of a libcall to 1484 // sincos. We want to issue a libcall to __sincos_stret to avoid memory 1485 // traffic. 1486 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); 1487 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); 1488 } 1489 } 1490 1491 // We have target-specific dag combine patterns for the following nodes: 1492 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1493 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1494 setTargetDAGCombine(ISD::VSELECT); 1495 setTargetDAGCombine(ISD::SELECT); 1496 setTargetDAGCombine(ISD::SHL); 1497 setTargetDAGCombine(ISD::SRA); 1498 setTargetDAGCombine(ISD::SRL); 1499 setTargetDAGCombine(ISD::OR); 1500 setTargetDAGCombine(ISD::AND); 1501 setTargetDAGCombine(ISD::ADD); 1502 setTargetDAGCombine(ISD::FADD); 1503 setTargetDAGCombine(ISD::FSUB); 1504 setTargetDAGCombine(ISD::FMA); 1505 setTargetDAGCombine(ISD::SUB); 1506 setTargetDAGCombine(ISD::LOAD); 1507 setTargetDAGCombine(ISD::STORE); 1508 setTargetDAGCombine(ISD::ZERO_EXTEND); 1509 setTargetDAGCombine(ISD::ANY_EXTEND); 1510 setTargetDAGCombine(ISD::SIGN_EXTEND); 1511 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); 1512 setTargetDAGCombine(ISD::TRUNCATE); 1513 setTargetDAGCombine(ISD::SINT_TO_FP); 1514 setTargetDAGCombine(ISD::SETCC); 1515 if (Subtarget->is64Bit()) 1516 setTargetDAGCombine(ISD::MUL); 1517 setTargetDAGCombine(ISD::XOR); 1518 1519 computeRegisterProperties(); 1520 1521 // On Darwin, -Os means optimize for size without hurting performance, 1522 // do not reduce the limit. 1523 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1524 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1525 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1526 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1527 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1528 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1529 setPrefLoopAlignment(4); // 2^4 bytes. 1530 1531 // Predictable cmov don't hurt on atom because it's in-order. 1532 PredictableSelectIsExpensive = !Subtarget->isAtom(); 1533 1534 setPrefFunctionAlignment(4); // 2^4 bytes. 1535} 1536 1537EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 1538 if (!VT.isVector()) return MVT::i8; 1539 return VT.changeVectorElementTypeToInteger(); 1540} 1541 1542/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1543/// the desired ByVal argument alignment. 1544static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1545 if (MaxAlign == 16) 1546 return; 1547 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1548 if (VTy->getBitWidth() == 128) 1549 MaxAlign = 16; 1550 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1551 unsigned EltAlign = 0; 1552 getMaxByValAlign(ATy->getElementType(), EltAlign); 1553 if (EltAlign > MaxAlign) 1554 MaxAlign = EltAlign; 1555 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1556 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1557 unsigned EltAlign = 0; 1558 getMaxByValAlign(STy->getElementType(i), EltAlign); 1559 if (EltAlign > MaxAlign) 1560 MaxAlign = EltAlign; 1561 if (MaxAlign == 16) 1562 break; 1563 } 1564 } 1565} 1566 1567/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1568/// function arguments in the caller parameter area. For X86, aggregates 1569/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1570/// are at 4-byte boundaries. 1571unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1572 if (Subtarget->is64Bit()) { 1573 // Max of 8 and alignment of type. 1574 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1575 if (TyAlign > 8) 1576 return TyAlign; 1577 return 8; 1578 } 1579 1580 unsigned Align = 4; 1581 if (Subtarget->hasSSE1()) 1582 getMaxByValAlign(Ty, Align); 1583 return Align; 1584} 1585 1586/// getOptimalMemOpType - Returns the target specific optimal type for load 1587/// and store operations as a result of memset, memcpy, and memmove 1588/// lowering. If DstAlign is zero that means it's safe to destination 1589/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1590/// means there isn't a need to check it against alignment requirement, 1591/// probably because the source does not need to be loaded. If 'IsMemset' is 1592/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 1593/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 1594/// source is constant so it does not need to be loaded. 1595/// It returns EVT::Other if the type should be determined using generic 1596/// target-independent logic. 1597EVT 1598X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1599 unsigned DstAlign, unsigned SrcAlign, 1600 bool IsMemset, bool ZeroMemset, 1601 bool MemcpyStrSrc, 1602 MachineFunction &MF) const { 1603 const Function *F = MF.getFunction(); 1604 if ((!IsMemset || ZeroMemset) && 1605 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 1606 Attribute::NoImplicitFloat)) { 1607 if (Size >= 16 && 1608 (Subtarget->isUnalignedMemAccessFast() || 1609 ((DstAlign == 0 || DstAlign >= 16) && 1610 (SrcAlign == 0 || SrcAlign >= 16)))) { 1611 if (Size >= 32) { 1612 if (Subtarget->hasInt256()) 1613 return MVT::v8i32; 1614 if (Subtarget->hasFp256()) 1615 return MVT::v8f32; 1616 } 1617 if (Subtarget->hasSSE2()) 1618 return MVT::v4i32; 1619 if (Subtarget->hasSSE1()) 1620 return MVT::v4f32; 1621 } else if (!MemcpyStrSrc && Size >= 8 && 1622 !Subtarget->is64Bit() && 1623 Subtarget->hasSSE2()) { 1624 // Do not use f64 to lower memcpy if source is string constant. It's 1625 // better to use i32 to avoid the loads. 1626 return MVT::f64; 1627 } 1628 } 1629 if (Subtarget->is64Bit() && Size >= 8) 1630 return MVT::i64; 1631 return MVT::i32; 1632} 1633 1634bool X86TargetLowering::isSafeMemOpType(MVT VT) const { 1635 if (VT == MVT::f32) 1636 return X86ScalarSSEf32; 1637 else if (VT == MVT::f64) 1638 return X86ScalarSSEf64; 1639 return true; 1640} 1641 1642bool 1643X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 1644 if (Fast) 1645 *Fast = Subtarget->isUnalignedMemAccessFast(); 1646 return true; 1647} 1648 1649/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1650/// current function. The returned value is a member of the 1651/// MachineJumpTableInfo::JTEntryKind enum. 1652unsigned X86TargetLowering::getJumpTableEncoding() const { 1653 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1654 // symbol. 1655 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1656 Subtarget->isPICStyleGOT()) 1657 return MachineJumpTableInfo::EK_Custom32; 1658 1659 // Otherwise, use the normal jump table encoding heuristics. 1660 return TargetLowering::getJumpTableEncoding(); 1661} 1662 1663const MCExpr * 1664X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1665 const MachineBasicBlock *MBB, 1666 unsigned uid,MCContext &Ctx) const{ 1667 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1668 Subtarget->isPICStyleGOT()); 1669 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1670 // entries. 1671 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1672 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1673} 1674 1675/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1676/// jumptable. 1677SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1678 SelectionDAG &DAG) const { 1679 if (!Subtarget->is64Bit()) 1680 // This doesn't have SDLoc associated with it, but is not really the 1681 // same as a Register. 1682 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy()); 1683 return Table; 1684} 1685 1686/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1687/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1688/// MCExpr. 1689const MCExpr *X86TargetLowering:: 1690getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1691 MCContext &Ctx) const { 1692 // X86-64 uses RIP relative addressing based on the jump table label. 1693 if (Subtarget->isPICStyleRIPRel()) 1694 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1695 1696 // Otherwise, the reference is relative to the PIC base. 1697 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1698} 1699 1700// FIXME: Why this routine is here? Move to RegInfo! 1701std::pair<const TargetRegisterClass*, uint8_t> 1702X86TargetLowering::findRepresentativeClass(MVT VT) const{ 1703 const TargetRegisterClass *RRC = 0; 1704 uint8_t Cost = 1; 1705 switch (VT.SimpleTy) { 1706 default: 1707 return TargetLowering::findRepresentativeClass(VT); 1708 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1709 RRC = Subtarget->is64Bit() ? 1710 (const TargetRegisterClass*)&X86::GR64RegClass : 1711 (const TargetRegisterClass*)&X86::GR32RegClass; 1712 break; 1713 case MVT::x86mmx: 1714 RRC = &X86::VR64RegClass; 1715 break; 1716 case MVT::f32: case MVT::f64: 1717 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1718 case MVT::v4f32: case MVT::v2f64: 1719 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1720 case MVT::v4f64: 1721 RRC = &X86::VR128RegClass; 1722 break; 1723 } 1724 return std::make_pair(RRC, Cost); 1725} 1726 1727bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1728 unsigned &Offset) const { 1729 if (!Subtarget->isTargetLinux()) 1730 return false; 1731 1732 if (Subtarget->is64Bit()) { 1733 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1734 Offset = 0x28; 1735 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1736 AddressSpace = 256; 1737 else 1738 AddressSpace = 257; 1739 } else { 1740 // %gs:0x14 on i386 1741 Offset = 0x14; 1742 AddressSpace = 256; 1743 } 1744 return true; 1745} 1746 1747//===----------------------------------------------------------------------===// 1748// Return Value Calling Convention Implementation 1749//===----------------------------------------------------------------------===// 1750 1751#include "X86GenCallingConv.inc" 1752 1753bool 1754X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1755 MachineFunction &MF, bool isVarArg, 1756 const SmallVectorImpl<ISD::OutputArg> &Outs, 1757 LLVMContext &Context) const { 1758 SmallVector<CCValAssign, 16> RVLocs; 1759 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1760 RVLocs, Context); 1761 return CCInfo.CheckReturn(Outs, RetCC_X86); 1762} 1763 1764SDValue 1765X86TargetLowering::LowerReturn(SDValue Chain, 1766 CallingConv::ID CallConv, bool isVarArg, 1767 const SmallVectorImpl<ISD::OutputArg> &Outs, 1768 const SmallVectorImpl<SDValue> &OutVals, 1769 SDLoc dl, SelectionDAG &DAG) const { 1770 MachineFunction &MF = DAG.getMachineFunction(); 1771 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1772 1773 SmallVector<CCValAssign, 16> RVLocs; 1774 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1775 RVLocs, *DAG.getContext()); 1776 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1777 1778 SDValue Flag; 1779 SmallVector<SDValue, 6> RetOps; 1780 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1781 // Operand #1 = Bytes To Pop 1782 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1783 MVT::i16)); 1784 1785 // Copy the result values into the output registers. 1786 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1787 CCValAssign &VA = RVLocs[i]; 1788 assert(VA.isRegLoc() && "Can only return in registers!"); 1789 SDValue ValToCopy = OutVals[i]; 1790 EVT ValVT = ValToCopy.getValueType(); 1791 1792 // Promote values to the appropriate types 1793 if (VA.getLocInfo() == CCValAssign::SExt) 1794 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1795 else if (VA.getLocInfo() == CCValAssign::ZExt) 1796 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1797 else if (VA.getLocInfo() == CCValAssign::AExt) 1798 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1799 else if (VA.getLocInfo() == CCValAssign::BCvt) 1800 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); 1801 1802 // If this is x86-64, and we disabled SSE, we can't return FP values, 1803 // or SSE or MMX vectors. 1804 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1805 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1806 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1807 report_fatal_error("SSE register return with SSE disabled"); 1808 } 1809 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1810 // llvm-gcc has never done it right and no one has noticed, so this 1811 // should be OK for now. 1812 if (ValVT == MVT::f64 && 1813 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1814 report_fatal_error("SSE2 register return with SSE2 disabled"); 1815 1816 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1817 // the RET instruction and handled by the FP Stackifier. 1818 if (VA.getLocReg() == X86::ST0 || 1819 VA.getLocReg() == X86::ST1) { 1820 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1821 // change the value to the FP stack register class. 1822 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1823 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1824 RetOps.push_back(ValToCopy); 1825 // Don't emit a copytoreg. 1826 continue; 1827 } 1828 1829 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1830 // which is returned in RAX / RDX. 1831 if (Subtarget->is64Bit()) { 1832 if (ValVT == MVT::x86mmx) { 1833 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1834 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1835 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1836 ValToCopy); 1837 // If we don't have SSE2 available, convert to v4f32 so the generated 1838 // register is legal. 1839 if (!Subtarget->hasSSE2()) 1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1841 } 1842 } 1843 } 1844 1845 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1846 Flag = Chain.getValue(1); 1847 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1848 } 1849 1850 // The x86-64 ABIs require that for returning structs by value we copy 1851 // the sret argument into %rax/%eax (depending on ABI) for the return. 1852 // Win32 requires us to put the sret argument to %eax as well. 1853 // We saved the argument into a virtual register in the entry block, 1854 // so now we copy the value out and into %rax/%eax. 1855 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() && 1856 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) { 1857 MachineFunction &MF = DAG.getMachineFunction(); 1858 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1859 unsigned Reg = FuncInfo->getSRetReturnReg(); 1860 assert(Reg && 1861 "SRetReturnReg should have been set in LowerFormalArguments()."); 1862 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1863 1864 unsigned RetValReg 1865 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ? 1866 X86::RAX : X86::EAX; 1867 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag); 1868 Flag = Chain.getValue(1); 1869 1870 // RAX/EAX now acts like a return value. 1871 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy())); 1872 } 1873 1874 RetOps[0] = Chain; // Update chain. 1875 1876 // Add the flag if we have it. 1877 if (Flag.getNode()) 1878 RetOps.push_back(Flag); 1879 1880 return DAG.getNode(X86ISD::RET_FLAG, dl, 1881 MVT::Other, &RetOps[0], RetOps.size()); 1882} 1883 1884bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1885 if (N->getNumValues() != 1) 1886 return false; 1887 if (!N->hasNUsesOfValue(1, 0)) 1888 return false; 1889 1890 SDValue TCChain = Chain; 1891 SDNode *Copy = *N->use_begin(); 1892 if (Copy->getOpcode() == ISD::CopyToReg) { 1893 // If the copy has a glue operand, we conservatively assume it isn't safe to 1894 // perform a tail call. 1895 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1896 return false; 1897 TCChain = Copy->getOperand(0); 1898 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1899 return false; 1900 1901 bool HasRet = false; 1902 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1903 UI != UE; ++UI) { 1904 if (UI->getOpcode() != X86ISD::RET_FLAG) 1905 return false; 1906 HasRet = true; 1907 } 1908 1909 if (!HasRet) 1910 return false; 1911 1912 Chain = TCChain; 1913 return true; 1914} 1915 1916MVT 1917X86TargetLowering::getTypeForExtArgOrReturn(MVT VT, 1918 ISD::NodeType ExtendKind) const { 1919 MVT ReturnMVT; 1920 // TODO: Is this also valid on 32-bit? 1921 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1922 ReturnMVT = MVT::i8; 1923 else 1924 ReturnMVT = MVT::i32; 1925 1926 MVT MinVT = getRegisterType(ReturnMVT); 1927 return VT.bitsLT(MinVT) ? MinVT : VT; 1928} 1929 1930/// LowerCallResult - Lower the result values of a call into the 1931/// appropriate copies out of appropriate physical registers. 1932/// 1933SDValue 1934X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1935 CallingConv::ID CallConv, bool isVarArg, 1936 const SmallVectorImpl<ISD::InputArg> &Ins, 1937 SDLoc dl, SelectionDAG &DAG, 1938 SmallVectorImpl<SDValue> &InVals) const { 1939 1940 // Assign locations to each value returned by this call. 1941 SmallVector<CCValAssign, 16> RVLocs; 1942 bool Is64Bit = Subtarget->is64Bit(); 1943 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1944 getTargetMachine(), RVLocs, *DAG.getContext()); 1945 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1946 1947 // Copy all of the result registers out of their specified physreg. 1948 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1949 CCValAssign &VA = RVLocs[i]; 1950 EVT CopyVT = VA.getValVT(); 1951 1952 // If this is x86-64, and we disabled SSE, we can't return FP values 1953 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1954 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1955 report_fatal_error("SSE register return with SSE disabled"); 1956 } 1957 1958 SDValue Val; 1959 1960 // If this is a call to a function that returns an fp value on the floating 1961 // point stack, we must guarantee the value is popped from the stack, so 1962 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1963 // if the return value is not used. We use the FpPOP_RETVAL instruction 1964 // instead. 1965 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1966 // If we prefer to use the value in xmm registers, copy it out as f80 and 1967 // use a truncate to move it from fp stack reg to xmm reg. 1968 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1969 SDValue Ops[] = { Chain, InFlag }; 1970 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1971 MVT::Other, MVT::Glue, Ops), 1); 1972 Val = Chain.getValue(0); 1973 1974 // Round the f80 to the right size, which also moves it to the appropriate 1975 // xmm register. 1976 if (CopyVT != VA.getValVT()) 1977 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1978 // This truncation won't change the value. 1979 DAG.getIntPtrConstant(1)); 1980 } else { 1981 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1982 CopyVT, InFlag).getValue(1); 1983 Val = Chain.getValue(0); 1984 } 1985 InFlag = Chain.getValue(2); 1986 InVals.push_back(Val); 1987 } 1988 1989 return Chain; 1990} 1991 1992//===----------------------------------------------------------------------===// 1993// C & StdCall & Fast Calling Convention implementation 1994//===----------------------------------------------------------------------===// 1995// StdCall calling convention seems to be standard for many Windows' API 1996// routines and around. It differs from C calling convention just a little: 1997// callee should clean up the stack, not caller. Symbols should be also 1998// decorated in some fancy way :) It doesn't support any vector arguments. 1999// For info on fast calling convention see Fast Calling Convention (tail call) 2000// implementation LowerX86_32FastCCCallTo. 2001 2002/// CallIsStructReturn - Determines whether a call uses struct return 2003/// semantics. 2004enum StructReturnType { 2005 NotStructReturn, 2006 RegStructReturn, 2007 StackStructReturn 2008}; 2009static StructReturnType 2010callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 2011 if (Outs.empty()) 2012 return NotStructReturn; 2013 2014 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 2015 if (!Flags.isSRet()) 2016 return NotStructReturn; 2017 if (Flags.isInReg()) 2018 return RegStructReturn; 2019 return StackStructReturn; 2020} 2021 2022/// ArgsAreStructReturn - Determines whether a function uses struct 2023/// return semantics. 2024static StructReturnType 2025argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 2026 if (Ins.empty()) 2027 return NotStructReturn; 2028 2029 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; 2030 if (!Flags.isSRet()) 2031 return NotStructReturn; 2032 if (Flags.isInReg()) 2033 return RegStructReturn; 2034 return StackStructReturn; 2035} 2036 2037/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2038/// by "Src" to address "Dst" with size and alignment information specified by 2039/// the specific parameter attribute. The copy will be passed as a byval 2040/// function parameter. 2041static SDValue 2042CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2043 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2044 SDLoc dl) { 2045 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2046 2047 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2048 /*isVolatile*/false, /*AlwaysInline=*/true, 2049 MachinePointerInfo(), MachinePointerInfo()); 2050} 2051 2052/// IsTailCallConvention - Return true if the calling convention is one that 2053/// supports tail call optimization. 2054static bool IsTailCallConvention(CallingConv::ID CC) { 2055 return (CC == CallingConv::Fast || CC == CallingConv::GHC || 2056 CC == CallingConv::HiPE); 2057} 2058 2059/// \brief Return true if the calling convention is a C calling convention. 2060static bool IsCCallConvention(CallingConv::ID CC) { 2061 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 || 2062 CC == CallingConv::X86_64_SysV); 2063} 2064 2065bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 2066 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 2067 return false; 2068 2069 CallSite CS(CI); 2070 CallingConv::ID CalleeCC = CS.getCallingConv(); 2071 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC)) 2072 return false; 2073 2074 return true; 2075} 2076 2077/// FuncIsMadeTailCallSafe - Return true if the function is being made into 2078/// a tailcall target by changing its ABI. 2079static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 2080 bool GuaranteedTailCallOpt) { 2081 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 2082} 2083 2084SDValue 2085X86TargetLowering::LowerMemArgument(SDValue Chain, 2086 CallingConv::ID CallConv, 2087 const SmallVectorImpl<ISD::InputArg> &Ins, 2088 SDLoc dl, SelectionDAG &DAG, 2089 const CCValAssign &VA, 2090 MachineFrameInfo *MFI, 2091 unsigned i) const { 2092 // Create the nodes corresponding to a load from this parameter slot. 2093 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2094 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 2095 getTargetMachine().Options.GuaranteedTailCallOpt); 2096 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 2097 EVT ValVT; 2098 2099 // If value is passed by pointer we have address passed instead of the value 2100 // itself. 2101 if (VA.getLocInfo() == CCValAssign::Indirect) 2102 ValVT = VA.getLocVT(); 2103 else 2104 ValVT = VA.getValVT(); 2105 2106 // FIXME: For now, all byval parameter objects are marked mutable. This can be 2107 // changed with more analysis. 2108 // In case of tail call optimization mark all arguments mutable. Since they 2109 // could be overwritten by lowering of arguments in case of a tail call. 2110 if (Flags.isByVal()) { 2111 unsigned Bytes = Flags.getByValSize(); 2112 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2113 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 2114 return DAG.getFrameIndex(FI, getPointerTy()); 2115 } else { 2116 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2117 VA.getLocMemOffset(), isImmutable); 2118 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2119 return DAG.getLoad(ValVT, dl, Chain, FIN, 2120 MachinePointerInfo::getFixedStack(FI), 2121 false, false, false, 0); 2122 } 2123} 2124 2125SDValue 2126X86TargetLowering::LowerFormalArguments(SDValue Chain, 2127 CallingConv::ID CallConv, 2128 bool isVarArg, 2129 const SmallVectorImpl<ISD::InputArg> &Ins, 2130 SDLoc dl, 2131 SelectionDAG &DAG, 2132 SmallVectorImpl<SDValue> &InVals) 2133 const { 2134 MachineFunction &MF = DAG.getMachineFunction(); 2135 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2136 2137 const Function* Fn = MF.getFunction(); 2138 if (Fn->hasExternalLinkage() && 2139 Subtarget->isTargetCygMing() && 2140 Fn->getName() == "main") 2141 FuncInfo->setForceFramePointer(true); 2142 2143 MachineFrameInfo *MFI = MF.getFrameInfo(); 2144 bool Is64Bit = Subtarget->is64Bit(); 2145 bool IsWindows = Subtarget->isTargetWindows(); 2146 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv); 2147 2148 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2149 "Var args not supported with calling convention fastcc, ghc or hipe"); 2150 2151 // Assign locations to all of the incoming arguments. 2152 SmallVector<CCValAssign, 16> ArgLocs; 2153 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2154 ArgLocs, *DAG.getContext()); 2155 2156 // Allocate shadow area for Win64 2157 if (IsWin64) 2158 CCInfo.AllocateStack(32, 8); 2159 2160 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 2161 2162 unsigned LastVal = ~0U; 2163 SDValue ArgValue; 2164 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2165 CCValAssign &VA = ArgLocs[i]; 2166 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 2167 // places. 2168 assert(VA.getValNo() != LastVal && 2169 "Don't support value assigned to multiple locs yet"); 2170 (void)LastVal; 2171 LastVal = VA.getValNo(); 2172 2173 if (VA.isRegLoc()) { 2174 EVT RegVT = VA.getLocVT(); 2175 const TargetRegisterClass *RC; 2176 if (RegVT == MVT::i32) 2177 RC = &X86::GR32RegClass; 2178 else if (Is64Bit && RegVT == MVT::i64) 2179 RC = &X86::GR64RegClass; 2180 else if (RegVT == MVT::f32) 2181 RC = &X86::FR32RegClass; 2182 else if (RegVT == MVT::f64) 2183 RC = &X86::FR64RegClass; 2184 else if (RegVT.is512BitVector()) 2185 RC = &X86::VR512RegClass; 2186 else if (RegVT.is256BitVector()) 2187 RC = &X86::VR256RegClass; 2188 else if (RegVT.is128BitVector()) 2189 RC = &X86::VR128RegClass; 2190 else if (RegVT == MVT::x86mmx) 2191 RC = &X86::VR64RegClass; 2192 else if (RegVT == MVT::v8i1) 2193 RC = &X86::VK8RegClass; 2194 else if (RegVT == MVT::v16i1) 2195 RC = &X86::VK16RegClass; 2196 else 2197 llvm_unreachable("Unknown argument type!"); 2198 2199 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2200 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2201 2202 // If this is an 8 or 16-bit value, it is really passed promoted to 32 2203 // bits. Insert an assert[sz]ext to capture this, then truncate to the 2204 // right size. 2205 if (VA.getLocInfo() == CCValAssign::SExt) 2206 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2207 DAG.getValueType(VA.getValVT())); 2208 else if (VA.getLocInfo() == CCValAssign::ZExt) 2209 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2210 DAG.getValueType(VA.getValVT())); 2211 else if (VA.getLocInfo() == CCValAssign::BCvt) 2212 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2213 2214 if (VA.isExtInLoc()) { 2215 // Handle MMX values passed in XMM regs. 2216 if (RegVT.isVector()) 2217 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue); 2218 else 2219 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2220 } 2221 } else { 2222 assert(VA.isMemLoc()); 2223 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 2224 } 2225 2226 // If value is passed via pointer - do a load. 2227 if (VA.getLocInfo() == CCValAssign::Indirect) 2228 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 2229 MachinePointerInfo(), false, false, false, 0); 2230 2231 InVals.push_back(ArgValue); 2232 } 2233 2234 // The x86-64 ABIs require that for returning structs by value we copy 2235 // the sret argument into %rax/%eax (depending on ABI) for the return. 2236 // Win32 requires us to put the sret argument to %eax as well. 2237 // Save the argument into a virtual register so that we can access it 2238 // from the return points. 2239 if (MF.getFunction()->hasStructRetAttr() && 2240 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) { 2241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2242 unsigned Reg = FuncInfo->getSRetReturnReg(); 2243 if (!Reg) { 2244 MVT PtrTy = getPointerTy(); 2245 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); 2246 FuncInfo->setSRetReturnReg(Reg); 2247 } 2248 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2249 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2250 } 2251 2252 unsigned StackSize = CCInfo.getNextStackOffset(); 2253 // Align stack specially for tail calls. 2254 if (FuncIsMadeTailCallSafe(CallConv, 2255 MF.getTarget().Options.GuaranteedTailCallOpt)) 2256 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 2257 2258 // If the function takes variable number of arguments, make a frame index for 2259 // the start of the first vararg value... for expansion of llvm.va_start. 2260 if (isVarArg) { 2261 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 2262 CallConv != CallingConv::X86_ThisCall)) { 2263 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 2264 } 2265 if (Is64Bit) { 2266 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 2267 2268 // FIXME: We should really autogenerate these arrays 2269 static const uint16_t GPR64ArgRegsWin64[] = { 2270 X86::RCX, X86::RDX, X86::R8, X86::R9 2271 }; 2272 static const uint16_t GPR64ArgRegs64Bit[] = { 2273 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 2274 }; 2275 static const uint16_t XMMArgRegs64Bit[] = { 2276 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2277 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2278 }; 2279 const uint16_t *GPR64ArgRegs; 2280 unsigned NumXMMRegs = 0; 2281 2282 if (IsWin64) { 2283 // The XMM registers which might contain var arg parameters are shadowed 2284 // in their paired GPR. So we only need to save the GPR to their home 2285 // slots. 2286 TotalNumIntRegs = 4; 2287 GPR64ArgRegs = GPR64ArgRegsWin64; 2288 } else { 2289 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 2290 GPR64ArgRegs = GPR64ArgRegs64Bit; 2291 2292 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 2293 TotalNumXMMRegs); 2294 } 2295 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 2296 TotalNumIntRegs); 2297 2298 bool NoImplicitFloatOps = Fn->getAttributes(). 2299 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 2300 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 2301 "SSE register cannot be used when SSE is disabled!"); 2302 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 2303 NoImplicitFloatOps) && 2304 "SSE register cannot be used when SSE is disabled!"); 2305 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 2306 !Subtarget->hasSSE1()) 2307 // Kernel mode asks for SSE to be disabled, so don't push them 2308 // on the stack. 2309 TotalNumXMMRegs = 0; 2310 2311 if (IsWin64) { 2312 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 2313 // Get to the caller-allocated home save location. Add 8 to account 2314 // for the return address. 2315 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 2316 FuncInfo->setRegSaveFrameIndex( 2317 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 2318 // Fixup to set vararg frame on shadow area (4 x i64). 2319 if (NumIntRegs < 4) 2320 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 2321 } else { 2322 // For X86-64, if there are vararg parameters that are passed via 2323 // registers, then we must store them to their spots on the stack so 2324 // they may be loaded by deferencing the result of va_next. 2325 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 2326 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 2327 FuncInfo->setRegSaveFrameIndex( 2328 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 2329 false)); 2330 } 2331 2332 // Store the integer parameter registers. 2333 SmallVector<SDValue, 8> MemOps; 2334 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2335 getPointerTy()); 2336 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2337 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2338 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2339 DAG.getIntPtrConstant(Offset)); 2340 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2341 &X86::GR64RegClass); 2342 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2343 SDValue Store = 2344 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2345 MachinePointerInfo::getFixedStack( 2346 FuncInfo->getRegSaveFrameIndex(), Offset), 2347 false, false, 0); 2348 MemOps.push_back(Store); 2349 Offset += 8; 2350 } 2351 2352 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2353 // Now store the XMM (fp + vector) parameter registers. 2354 SmallVector<SDValue, 11> SaveXMMOps; 2355 SaveXMMOps.push_back(Chain); 2356 2357 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2358 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2359 SaveXMMOps.push_back(ALVal); 2360 2361 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2362 FuncInfo->getRegSaveFrameIndex())); 2363 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2364 FuncInfo->getVarArgsFPOffset())); 2365 2366 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2367 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2368 &X86::VR128RegClass); 2369 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2370 SaveXMMOps.push_back(Val); 2371 } 2372 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2373 MVT::Other, 2374 &SaveXMMOps[0], SaveXMMOps.size())); 2375 } 2376 2377 if (!MemOps.empty()) 2378 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2379 &MemOps[0], MemOps.size()); 2380 } 2381 } 2382 2383 // Some CCs need callee pop. 2384 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2385 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2386 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2387 } else { 2388 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2389 // If this is an sret function, the return should pop the hidden pointer. 2390 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2391 argsAreStructReturn(Ins) == StackStructReturn) 2392 FuncInfo->setBytesToPopOnReturn(4); 2393 } 2394 2395 if (!Is64Bit) { 2396 // RegSaveFrameIndex is X86-64 only. 2397 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2398 if (CallConv == CallingConv::X86_FastCall || 2399 CallConv == CallingConv::X86_ThisCall) 2400 // fastcc functions can't have varargs. 2401 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2402 } 2403 2404 FuncInfo->setArgumentStackSize(StackSize); 2405 2406 return Chain; 2407} 2408 2409SDValue 2410X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2411 SDValue StackPtr, SDValue Arg, 2412 SDLoc dl, SelectionDAG &DAG, 2413 const CCValAssign &VA, 2414 ISD::ArgFlagsTy Flags) const { 2415 unsigned LocMemOffset = VA.getLocMemOffset(); 2416 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2417 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2418 if (Flags.isByVal()) 2419 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2420 2421 return DAG.getStore(Chain, dl, Arg, PtrOff, 2422 MachinePointerInfo::getStack(LocMemOffset), 2423 false, false, 0); 2424} 2425 2426/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2427/// optimization is performed and it is required. 2428SDValue 2429X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2430 SDValue &OutRetAddr, SDValue Chain, 2431 bool IsTailCall, bool Is64Bit, 2432 int FPDiff, SDLoc dl) const { 2433 // Adjust the Return address stack slot. 2434 EVT VT = getPointerTy(); 2435 OutRetAddr = getReturnAddressFrameIndex(DAG); 2436 2437 // Load the "old" Return address. 2438 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2439 false, false, false, 0); 2440 return SDValue(OutRetAddr.getNode(), 1); 2441} 2442 2443/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2444/// optimization is performed and it is required (FPDiff!=0). 2445static SDValue 2446EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2447 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, 2448 unsigned SlotSize, int FPDiff, SDLoc dl) { 2449 // Store the return address to the appropriate stack slot. 2450 if (!FPDiff) return Chain; 2451 // Calculate the new stack slot for the return address. 2452 int NewReturnAddrFI = 2453 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize, 2454 false); 2455 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT); 2456 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2457 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2458 false, false, 0); 2459 return Chain; 2460} 2461 2462SDValue 2463X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2464 SmallVectorImpl<SDValue> &InVals) const { 2465 SelectionDAG &DAG = CLI.DAG; 2466 SDLoc &dl = CLI.DL; 2467 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2468 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2469 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2470 SDValue Chain = CLI.Chain; 2471 SDValue Callee = CLI.Callee; 2472 CallingConv::ID CallConv = CLI.CallConv; 2473 bool &isTailCall = CLI.IsTailCall; 2474 bool isVarArg = CLI.IsVarArg; 2475 2476 MachineFunction &MF = DAG.getMachineFunction(); 2477 bool Is64Bit = Subtarget->is64Bit(); 2478 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv); 2479 bool IsWindows = Subtarget->isTargetWindows(); 2480 StructReturnType SR = callIsStructReturn(Outs); 2481 bool IsSibcall = false; 2482 2483 if (MF.getTarget().Options.DisableTailCalls) 2484 isTailCall = false; 2485 2486 if (isTailCall) { 2487 // Check if it's really possible to do a tail call. 2488 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2489 isVarArg, SR != NotStructReturn, 2490 MF.getFunction()->hasStructRetAttr(), CLI.RetTy, 2491 Outs, OutVals, Ins, DAG); 2492 2493 // Sibcalls are automatically detected tailcalls which do not require 2494 // ABI changes. 2495 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2496 IsSibcall = true; 2497 2498 if (isTailCall) 2499 ++NumTailCalls; 2500 } 2501 2502 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2503 "Var args not supported with calling convention fastcc, ghc or hipe"); 2504 2505 // Analyze operands of the call, assigning locations to each operand. 2506 SmallVector<CCValAssign, 16> ArgLocs; 2507 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2508 ArgLocs, *DAG.getContext()); 2509 2510 // Allocate shadow area for Win64 2511 if (IsWin64) 2512 CCInfo.AllocateStack(32, 8); 2513 2514 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2515 2516 // Get a count of how many bytes are to be pushed on the stack. 2517 unsigned NumBytes = CCInfo.getNextStackOffset(); 2518 if (IsSibcall) 2519 // This is a sibcall. The memory operands are available in caller's 2520 // own caller's stack. 2521 NumBytes = 0; 2522 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2523 IsTailCallConvention(CallConv)) 2524 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2525 2526 int FPDiff = 0; 2527 if (isTailCall && !IsSibcall) { 2528 // Lower arguments at fp - stackoffset + fpdiff. 2529 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>(); 2530 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn(); 2531 2532 FPDiff = NumBytesCallerPushed - NumBytes; 2533 2534 // Set the delta of movement of the returnaddr stackslot. 2535 // But only set if delta is greater than previous delta. 2536 if (FPDiff < X86Info->getTCReturnAddrDelta()) 2537 X86Info->setTCReturnAddrDelta(FPDiff); 2538 } 2539 2540 if (!IsSibcall) 2541 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), 2542 dl); 2543 2544 SDValue RetAddrFrIdx; 2545 // Load return address for tail calls. 2546 if (isTailCall && FPDiff) 2547 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2548 Is64Bit, FPDiff, dl); 2549 2550 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2551 SmallVector<SDValue, 8> MemOpChains; 2552 SDValue StackPtr; 2553 2554 // Walk the register/memloc assignments, inserting copies/loads. In the case 2555 // of tail call optimization arguments are handle later. 2556 const X86RegisterInfo *RegInfo = 2557 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 2558 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2559 CCValAssign &VA = ArgLocs[i]; 2560 EVT RegVT = VA.getLocVT(); 2561 SDValue Arg = OutVals[i]; 2562 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2563 bool isByVal = Flags.isByVal(); 2564 2565 // Promote the value if needed. 2566 switch (VA.getLocInfo()) { 2567 default: llvm_unreachable("Unknown loc info!"); 2568 case CCValAssign::Full: break; 2569 case CCValAssign::SExt: 2570 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2571 break; 2572 case CCValAssign::ZExt: 2573 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2574 break; 2575 case CCValAssign::AExt: 2576 if (RegVT.is128BitVector()) { 2577 // Special case: passing MMX values in XMM registers. 2578 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2579 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2580 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2581 } else 2582 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2583 break; 2584 case CCValAssign::BCvt: 2585 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2586 break; 2587 case CCValAssign::Indirect: { 2588 // Store the argument. 2589 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2590 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2591 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2592 MachinePointerInfo::getFixedStack(FI), 2593 false, false, 0); 2594 Arg = SpillSlot; 2595 break; 2596 } 2597 } 2598 2599 if (VA.isRegLoc()) { 2600 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2601 if (isVarArg && IsWin64) { 2602 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2603 // shadow reg if callee is a varargs function. 2604 unsigned ShadowReg = 0; 2605 switch (VA.getLocReg()) { 2606 case X86::XMM0: ShadowReg = X86::RCX; break; 2607 case X86::XMM1: ShadowReg = X86::RDX; break; 2608 case X86::XMM2: ShadowReg = X86::R8; break; 2609 case X86::XMM3: ShadowReg = X86::R9; break; 2610 } 2611 if (ShadowReg) 2612 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2613 } 2614 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2615 assert(VA.isMemLoc()); 2616 if (StackPtr.getNode() == 0) 2617 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 2618 getPointerTy()); 2619 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2620 dl, DAG, VA, Flags)); 2621 } 2622 } 2623 2624 if (!MemOpChains.empty()) 2625 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2626 &MemOpChains[0], MemOpChains.size()); 2627 2628 if (Subtarget->isPICStyleGOT()) { 2629 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2630 // GOT pointer. 2631 if (!isTailCall) { 2632 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX), 2633 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy()))); 2634 } else { 2635 // If we are tail calling and generating PIC/GOT style code load the 2636 // address of the callee into ECX. The value in ecx is used as target of 2637 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2638 // for tail calls on PIC/GOT architectures. Normally we would just put the 2639 // address of GOT into ebx and then call target@PLT. But for tail calls 2640 // ebx would be restored (since ebx is callee saved) before jumping to the 2641 // target@PLT. 2642 2643 // Note: The actual moving to ECX is done further down. 2644 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2645 if (G && !G->getGlobal()->hasHiddenVisibility() && 2646 !G->getGlobal()->hasProtectedVisibility()) 2647 Callee = LowerGlobalAddress(Callee, DAG); 2648 else if (isa<ExternalSymbolSDNode>(Callee)) 2649 Callee = LowerExternalSymbol(Callee, DAG); 2650 } 2651 } 2652 2653 if (Is64Bit && isVarArg && !IsWin64) { 2654 // From AMD64 ABI document: 2655 // For calls that may call functions that use varargs or stdargs 2656 // (prototype-less calls or calls to functions containing ellipsis (...) in 2657 // the declaration) %al is used as hidden argument to specify the number 2658 // of SSE registers used. The contents of %al do not need to match exactly 2659 // the number of registers, but must be an ubound on the number of SSE 2660 // registers used and is in the range 0 - 8 inclusive. 2661 2662 // Count the number of XMM registers allocated. 2663 static const uint16_t XMMArgRegs[] = { 2664 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2665 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2666 }; 2667 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2668 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2669 && "SSE registers cannot be used when SSE is disabled"); 2670 2671 RegsToPass.push_back(std::make_pair(unsigned(X86::AL), 2672 DAG.getConstant(NumXMMRegs, MVT::i8))); 2673 } 2674 2675 // For tail calls lower the arguments to the 'real' stack slot. 2676 if (isTailCall) { 2677 // Force all the incoming stack arguments to be loaded from the stack 2678 // before any new outgoing arguments are stored to the stack, because the 2679 // outgoing stack slots may alias the incoming argument stack slots, and 2680 // the alias isn't otherwise explicit. This is slightly more conservative 2681 // than necessary, because it means that each store effectively depends 2682 // on every argument instead of just those arguments it would clobber. 2683 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2684 2685 SmallVector<SDValue, 8> MemOpChains2; 2686 SDValue FIN; 2687 int FI = 0; 2688 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2689 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2690 CCValAssign &VA = ArgLocs[i]; 2691 if (VA.isRegLoc()) 2692 continue; 2693 assert(VA.isMemLoc()); 2694 SDValue Arg = OutVals[i]; 2695 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2696 // Create frame index. 2697 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2698 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2699 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2700 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2701 2702 if (Flags.isByVal()) { 2703 // Copy relative to framepointer. 2704 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2705 if (StackPtr.getNode() == 0) 2706 StackPtr = DAG.getCopyFromReg(Chain, dl, 2707 RegInfo->getStackRegister(), 2708 getPointerTy()); 2709 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2710 2711 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2712 ArgChain, 2713 Flags, DAG, dl)); 2714 } else { 2715 // Store relative to framepointer. 2716 MemOpChains2.push_back( 2717 DAG.getStore(ArgChain, dl, Arg, FIN, 2718 MachinePointerInfo::getFixedStack(FI), 2719 false, false, 0)); 2720 } 2721 } 2722 } 2723 2724 if (!MemOpChains2.empty()) 2725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2726 &MemOpChains2[0], MemOpChains2.size()); 2727 2728 // Store the return address to the appropriate stack slot. 2729 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, 2730 getPointerTy(), RegInfo->getSlotSize(), 2731 FPDiff, dl); 2732 } 2733 2734 // Build a sequence of copy-to-reg nodes chained together with token chain 2735 // and flag operands which copy the outgoing args into registers. 2736 SDValue InFlag; 2737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2739 RegsToPass[i].second, InFlag); 2740 InFlag = Chain.getValue(1); 2741 } 2742 2743 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2744 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2745 // In the 64-bit large code model, we have to make all calls 2746 // through a register, since the call instruction's 32-bit 2747 // pc-relative offset may not be large enough to hold the whole 2748 // address. 2749 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2750 // If the callee is a GlobalAddress node (quite common, every direct call 2751 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2752 // it. 2753 2754 // We should use extra load for direct calls to dllimported functions in 2755 // non-JIT mode. 2756 const GlobalValue *GV = G->getGlobal(); 2757 if (!GV->hasDLLImportLinkage()) { 2758 unsigned char OpFlags = 0; 2759 bool ExtraLoad = false; 2760 unsigned WrapperKind = ISD::DELETED_NODE; 2761 2762 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2763 // external symbols most go through the PLT in PIC mode. If the symbol 2764 // has hidden or protected visibility, or if it is static or local, then 2765 // we don't need to use the PLT - we can directly call it. 2766 if (Subtarget->isTargetELF() && 2767 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2768 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2769 OpFlags = X86II::MO_PLT; 2770 } else if (Subtarget->isPICStyleStubAny() && 2771 (GV->isDeclaration() || GV->isWeakForLinker()) && 2772 (!Subtarget->getTargetTriple().isMacOSX() || 2773 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2774 // PC-relative references to external symbols should go through $stub, 2775 // unless we're building with the leopard linker or later, which 2776 // automatically synthesizes these stubs. 2777 OpFlags = X86II::MO_DARWIN_STUB; 2778 } else if (Subtarget->isPICStyleRIPRel() && 2779 isa<Function>(GV) && 2780 cast<Function>(GV)->getAttributes(). 2781 hasAttribute(AttributeSet::FunctionIndex, 2782 Attribute::NonLazyBind)) { 2783 // If the function is marked as non-lazy, generate an indirect call 2784 // which loads from the GOT directly. This avoids runtime overhead 2785 // at the cost of eager binding (and one extra byte of encoding). 2786 OpFlags = X86II::MO_GOTPCREL; 2787 WrapperKind = X86ISD::WrapperRIP; 2788 ExtraLoad = true; 2789 } 2790 2791 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2792 G->getOffset(), OpFlags); 2793 2794 // Add a wrapper if needed. 2795 if (WrapperKind != ISD::DELETED_NODE) 2796 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2797 // Add extra indirection if needed. 2798 if (ExtraLoad) 2799 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2800 MachinePointerInfo::getGOT(), 2801 false, false, false, 0); 2802 } 2803 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2804 unsigned char OpFlags = 0; 2805 2806 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2807 // external symbols should go through the PLT. 2808 if (Subtarget->isTargetELF() && 2809 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2810 OpFlags = X86II::MO_PLT; 2811 } else if (Subtarget->isPICStyleStubAny() && 2812 (!Subtarget->getTargetTriple().isMacOSX() || 2813 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2814 // PC-relative references to external symbols should go through $stub, 2815 // unless we're building with the leopard linker or later, which 2816 // automatically synthesizes these stubs. 2817 OpFlags = X86II::MO_DARWIN_STUB; 2818 } 2819 2820 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2821 OpFlags); 2822 } 2823 2824 // Returns a chain & a flag for retval copy to use. 2825 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2826 SmallVector<SDValue, 8> Ops; 2827 2828 if (!IsSibcall && isTailCall) { 2829 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2830 DAG.getIntPtrConstant(0, true), InFlag, dl); 2831 InFlag = Chain.getValue(1); 2832 } 2833 2834 Ops.push_back(Chain); 2835 Ops.push_back(Callee); 2836 2837 if (isTailCall) 2838 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2839 2840 // Add argument registers to the end of the list so that they are known live 2841 // into the call. 2842 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2843 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2844 RegsToPass[i].second.getValueType())); 2845 2846 // Add a register mask operand representing the call-preserved registers. 2847 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2848 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2849 assert(Mask && "Missing call preserved mask for calling convention"); 2850 Ops.push_back(DAG.getRegisterMask(Mask)); 2851 2852 if (InFlag.getNode()) 2853 Ops.push_back(InFlag); 2854 2855 if (isTailCall) { 2856 // We used to do: 2857 //// If this is the first return lowered for this function, add the regs 2858 //// to the liveout set for the function. 2859 // This isn't right, although it's probably harmless on x86; liveouts 2860 // should be computed from returns not tail calls. Consider a void 2861 // function making a tail call to a function returning int. 2862 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 2863 } 2864 2865 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2866 InFlag = Chain.getValue(1); 2867 2868 // Create the CALLSEQ_END node. 2869 unsigned NumBytesForCalleeToPush; 2870 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2871 getTargetMachine().Options.GuaranteedTailCallOpt)) 2872 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2873 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2874 SR == StackStructReturn) 2875 // If this is a call to a struct-return function, the callee 2876 // pops the hidden struct pointer, so we have to push it back. 2877 // This is common for Darwin/X86, Linux & Mingw32 targets. 2878 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2879 NumBytesForCalleeToPush = 4; 2880 else 2881 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2882 2883 // Returns a flag for retval copy to use. 2884 if (!IsSibcall) { 2885 Chain = DAG.getCALLSEQ_END(Chain, 2886 DAG.getIntPtrConstant(NumBytes, true), 2887 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2888 true), 2889 InFlag, dl); 2890 InFlag = Chain.getValue(1); 2891 } 2892 2893 // Handle result values, copying them out of physregs into vregs that we 2894 // return. 2895 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2896 Ins, dl, DAG, InVals); 2897} 2898 2899//===----------------------------------------------------------------------===// 2900// Fast Calling Convention (tail call) implementation 2901//===----------------------------------------------------------------------===// 2902 2903// Like std call, callee cleans arguments, convention except that ECX is 2904// reserved for storing the tail called function address. Only 2 registers are 2905// free for argument passing (inreg). Tail call optimization is performed 2906// provided: 2907// * tailcallopt is enabled 2908// * caller/callee are fastcc 2909// On X86_64 architecture with GOT-style position independent code only local 2910// (within module) calls are supported at the moment. 2911// To keep the stack aligned according to platform abi the function 2912// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2913// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2914// If a tail called function callee has more arguments than the caller the 2915// caller needs to make sure that there is room to move the RETADDR to. This is 2916// achieved by reserving an area the size of the argument delta right after the 2917// original REtADDR, but before the saved framepointer or the spilled registers 2918// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2919// stack layout: 2920// arg1 2921// arg2 2922// RETADDR 2923// [ new RETADDR 2924// move area ] 2925// (possible EBP) 2926// ESI 2927// EDI 2928// local1 .. 2929 2930/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2931/// for a 16 byte align requirement. 2932unsigned 2933X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2934 SelectionDAG& DAG) const { 2935 MachineFunction &MF = DAG.getMachineFunction(); 2936 const TargetMachine &TM = MF.getTarget(); 2937 const X86RegisterInfo *RegInfo = 2938 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); 2939 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2940 unsigned StackAlignment = TFI.getStackAlignment(); 2941 uint64_t AlignMask = StackAlignment - 1; 2942 int64_t Offset = StackSize; 2943 unsigned SlotSize = RegInfo->getSlotSize(); 2944 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2945 // Number smaller than 12 so just add the difference. 2946 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2947 } else { 2948 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2949 Offset = ((~AlignMask) & Offset) + StackAlignment + 2950 (StackAlignment-SlotSize); 2951 } 2952 return Offset; 2953} 2954 2955/// MatchingStackOffset - Return true if the given stack call argument is 2956/// already available in the same position (relatively) of the caller's 2957/// incoming argument stack. 2958static 2959bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2960 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2961 const X86InstrInfo *TII) { 2962 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2963 int FI = INT_MAX; 2964 if (Arg.getOpcode() == ISD::CopyFromReg) { 2965 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2966 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2967 return false; 2968 MachineInstr *Def = MRI->getVRegDef(VR); 2969 if (!Def) 2970 return false; 2971 if (!Flags.isByVal()) { 2972 if (!TII->isLoadFromStackSlot(Def, FI)) 2973 return false; 2974 } else { 2975 unsigned Opcode = Def->getOpcode(); 2976 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2977 Def->getOperand(1).isFI()) { 2978 FI = Def->getOperand(1).getIndex(); 2979 Bytes = Flags.getByValSize(); 2980 } else 2981 return false; 2982 } 2983 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2984 if (Flags.isByVal()) 2985 // ByVal argument is passed in as a pointer but it's now being 2986 // dereferenced. e.g. 2987 // define @foo(%struct.X* %A) { 2988 // tail call @bar(%struct.X* byval %A) 2989 // } 2990 return false; 2991 SDValue Ptr = Ld->getBasePtr(); 2992 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2993 if (!FINode) 2994 return false; 2995 FI = FINode->getIndex(); 2996 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2997 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2998 FI = FINode->getIndex(); 2999 Bytes = Flags.getByValSize(); 3000 } else 3001 return false; 3002 3003 assert(FI != INT_MAX); 3004 if (!MFI->isFixedObjectIndex(FI)) 3005 return false; 3006 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 3007} 3008 3009/// IsEligibleForTailCallOptimization - Check whether the call is eligible 3010/// for tail call optimization. Targets which want to do tail call 3011/// optimization should implement this function. 3012bool 3013X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 3014 CallingConv::ID CalleeCC, 3015 bool isVarArg, 3016 bool isCalleeStructRet, 3017 bool isCallerStructRet, 3018 Type *RetTy, 3019 const SmallVectorImpl<ISD::OutputArg> &Outs, 3020 const SmallVectorImpl<SDValue> &OutVals, 3021 const SmallVectorImpl<ISD::InputArg> &Ins, 3022 SelectionDAG &DAG) const { 3023 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC)) 3024 return false; 3025 3026 // If -tailcallopt is specified, make fastcc functions tail-callable. 3027 const MachineFunction &MF = DAG.getMachineFunction(); 3028 const Function *CallerF = MF.getFunction(); 3029 3030 // If the function return type is x86_fp80 and the callee return type is not, 3031 // then the FP_EXTEND of the call result is not a nop. It's not safe to 3032 // perform a tailcall optimization here. 3033 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty()) 3034 return false; 3035 3036 CallingConv::ID CallerCC = CallerF->getCallingConv(); 3037 bool CCMatch = CallerCC == CalleeCC; 3038 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC); 3039 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC); 3040 3041 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 3042 if (IsTailCallConvention(CalleeCC) && CCMatch) 3043 return true; 3044 return false; 3045 } 3046 3047 // Look for obvious safe cases to perform tail call optimization that do not 3048 // require ABI changes. This is what gcc calls sibcall. 3049 3050 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 3051 // emit a special epilogue. 3052 const X86RegisterInfo *RegInfo = 3053 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 3054 if (RegInfo->needsStackRealignment(MF)) 3055 return false; 3056 3057 // Also avoid sibcall optimization if either caller or callee uses struct 3058 // return semantics. 3059 if (isCalleeStructRet || isCallerStructRet) 3060 return false; 3061 3062 // An stdcall caller is expected to clean up its arguments; the callee 3063 // isn't going to do that. 3064 if (!CCMatch && CallerCC == CallingConv::X86_StdCall) 3065 return false; 3066 3067 // Do not sibcall optimize vararg calls unless all arguments are passed via 3068 // registers. 3069 if (isVarArg && !Outs.empty()) { 3070 3071 // Optimizing for varargs on Win64 is unlikely to be safe without 3072 // additional testing. 3073 if (IsCalleeWin64 || IsCallerWin64) 3074 return false; 3075 3076 SmallVector<CCValAssign, 16> ArgLocs; 3077 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 3078 getTargetMachine(), ArgLocs, *DAG.getContext()); 3079 3080 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 3081 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 3082 if (!ArgLocs[i].isRegLoc()) 3083 return false; 3084 } 3085 3086 // If the call result is in ST0 / ST1, it needs to be popped off the x87 3087 // stack. Therefore, if it's not used by the call it is not safe to optimize 3088 // this into a sibcall. 3089 bool Unused = false; 3090 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 3091 if (!Ins[i].Used) { 3092 Unused = true; 3093 break; 3094 } 3095 } 3096 if (Unused) { 3097 SmallVector<CCValAssign, 16> RVLocs; 3098 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 3099 getTargetMachine(), RVLocs, *DAG.getContext()); 3100 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 3101 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3102 CCValAssign &VA = RVLocs[i]; 3103 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 3104 return false; 3105 } 3106 } 3107 3108 // If the calling conventions do not match, then we'd better make sure the 3109 // results are returned in the same way as what the caller expects. 3110 if (!CCMatch) { 3111 SmallVector<CCValAssign, 16> RVLocs1; 3112 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 3113 getTargetMachine(), RVLocs1, *DAG.getContext()); 3114 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 3115 3116 SmallVector<CCValAssign, 16> RVLocs2; 3117 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 3118 getTargetMachine(), RVLocs2, *DAG.getContext()); 3119 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 3120 3121 if (RVLocs1.size() != RVLocs2.size()) 3122 return false; 3123 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 3124 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 3125 return false; 3126 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 3127 return false; 3128 if (RVLocs1[i].isRegLoc()) { 3129 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 3130 return false; 3131 } else { 3132 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 3133 return false; 3134 } 3135 } 3136 } 3137 3138 // If the callee takes no arguments then go on to check the results of the 3139 // call. 3140 if (!Outs.empty()) { 3141 // Check if stack adjustment is needed. For now, do not do this if any 3142 // argument is passed on the stack. 3143 SmallVector<CCValAssign, 16> ArgLocs; 3144 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 3145 getTargetMachine(), ArgLocs, *DAG.getContext()); 3146 3147 // Allocate shadow area for Win64 3148 if (IsCalleeWin64) 3149 CCInfo.AllocateStack(32, 8); 3150 3151 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 3152 if (CCInfo.getNextStackOffset()) { 3153 MachineFunction &MF = DAG.getMachineFunction(); 3154 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 3155 return false; 3156 3157 // Check if the arguments are already laid out in the right way as 3158 // the caller's fixed stack objects. 3159 MachineFrameInfo *MFI = MF.getFrameInfo(); 3160 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 3161 const X86InstrInfo *TII = 3162 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo(); 3163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3164 CCValAssign &VA = ArgLocs[i]; 3165 SDValue Arg = OutVals[i]; 3166 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3167 if (VA.getLocInfo() == CCValAssign::Indirect) 3168 return false; 3169 if (!VA.isRegLoc()) { 3170 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 3171 MFI, MRI, TII)) 3172 return false; 3173 } 3174 } 3175 } 3176 3177 // If the tailcall address may be in a register, then make sure it's 3178 // possible to register allocate for it. In 32-bit, the call address can 3179 // only target EAX, EDX, or ECX since the tail call must be scheduled after 3180 // callee-saved registers are restored. These happen to be the same 3181 // registers used to pass 'inreg' arguments so watch out for those. 3182 if (!Subtarget->is64Bit() && 3183 ((!isa<GlobalAddressSDNode>(Callee) && 3184 !isa<ExternalSymbolSDNode>(Callee)) || 3185 getTargetMachine().getRelocationModel() == Reloc::PIC_)) { 3186 unsigned NumInRegs = 0; 3187 // In PIC we need an extra register to formulate the address computation 3188 // for the callee. 3189 unsigned MaxInRegs = 3190 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3; 3191 3192 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3193 CCValAssign &VA = ArgLocs[i]; 3194 if (!VA.isRegLoc()) 3195 continue; 3196 unsigned Reg = VA.getLocReg(); 3197 switch (Reg) { 3198 default: break; 3199 case X86::EAX: case X86::EDX: case X86::ECX: 3200 if (++NumInRegs == MaxInRegs) 3201 return false; 3202 break; 3203 } 3204 } 3205 } 3206 } 3207 3208 return true; 3209} 3210 3211FastISel * 3212X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 3213 const TargetLibraryInfo *libInfo) const { 3214 return X86::createFastISel(funcInfo, libInfo); 3215} 3216 3217//===----------------------------------------------------------------------===// 3218// Other Lowering Hooks 3219//===----------------------------------------------------------------------===// 3220 3221static bool MayFoldLoad(SDValue Op) { 3222 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 3223} 3224 3225static bool MayFoldIntoStore(SDValue Op) { 3226 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 3227} 3228 3229static bool isTargetShuffle(unsigned Opcode) { 3230 switch(Opcode) { 3231 default: return false; 3232 case X86ISD::PSHUFD: 3233 case X86ISD::PSHUFHW: 3234 case X86ISD::PSHUFLW: 3235 case X86ISD::SHUFP: 3236 case X86ISD::PALIGNR: 3237 case X86ISD::MOVLHPS: 3238 case X86ISD::MOVLHPD: 3239 case X86ISD::MOVHLPS: 3240 case X86ISD::MOVLPS: 3241 case X86ISD::MOVLPD: 3242 case X86ISD::MOVSHDUP: 3243 case X86ISD::MOVSLDUP: 3244 case X86ISD::MOVDDUP: 3245 case X86ISD::MOVSS: 3246 case X86ISD::MOVSD: 3247 case X86ISD::UNPCKL: 3248 case X86ISD::UNPCKH: 3249 case X86ISD::VPERMILP: 3250 case X86ISD::VPERM2X128: 3251 case X86ISD::VPERMI: 3252 return true; 3253 } 3254} 3255 3256static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, 3257 SDValue V1, SelectionDAG &DAG) { 3258 switch(Opc) { 3259 default: llvm_unreachable("Unknown x86 shuffle node"); 3260 case X86ISD::MOVSHDUP: 3261 case X86ISD::MOVSLDUP: 3262 case X86ISD::MOVDDUP: 3263 return DAG.getNode(Opc, dl, VT, V1); 3264 } 3265} 3266 3267static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, 3268 SDValue V1, unsigned TargetMask, 3269 SelectionDAG &DAG) { 3270 switch(Opc) { 3271 default: llvm_unreachable("Unknown x86 shuffle node"); 3272 case X86ISD::PSHUFD: 3273 case X86ISD::PSHUFHW: 3274 case X86ISD::PSHUFLW: 3275 case X86ISD::VPERMILP: 3276 case X86ISD::VPERMI: 3277 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 3278 } 3279} 3280 3281static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, 3282 SDValue V1, SDValue V2, unsigned TargetMask, 3283 SelectionDAG &DAG) { 3284 switch(Opc) { 3285 default: llvm_unreachable("Unknown x86 shuffle node"); 3286 case X86ISD::PALIGNR: 3287 case X86ISD::SHUFP: 3288 case X86ISD::VPERM2X128: 3289 return DAG.getNode(Opc, dl, VT, V1, V2, 3290 DAG.getConstant(TargetMask, MVT::i8)); 3291 } 3292} 3293 3294static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, 3295 SDValue V1, SDValue V2, SelectionDAG &DAG) { 3296 switch(Opc) { 3297 default: llvm_unreachable("Unknown x86 shuffle node"); 3298 case X86ISD::MOVLHPS: 3299 case X86ISD::MOVLHPD: 3300 case X86ISD::MOVHLPS: 3301 case X86ISD::MOVLPS: 3302 case X86ISD::MOVLPD: 3303 case X86ISD::MOVSS: 3304 case X86ISD::MOVSD: 3305 case X86ISD::UNPCKL: 3306 case X86ISD::UNPCKH: 3307 return DAG.getNode(Opc, dl, VT, V1, V2); 3308 } 3309} 3310 3311SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 3312 MachineFunction &MF = DAG.getMachineFunction(); 3313 const X86RegisterInfo *RegInfo = 3314 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 3315 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 3316 int ReturnAddrIndex = FuncInfo->getRAIndex(); 3317 3318 if (ReturnAddrIndex == 0) { 3319 // Set up a frame object for the return address. 3320 unsigned SlotSize = RegInfo->getSlotSize(); 3321 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, 3322 -(int64_t)SlotSize, 3323 false); 3324 FuncInfo->setRAIndex(ReturnAddrIndex); 3325 } 3326 3327 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 3328} 3329 3330bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 3331 bool hasSymbolicDisplacement) { 3332 // Offset should fit into 32 bit immediate field. 3333 if (!isInt<32>(Offset)) 3334 return false; 3335 3336 // If we don't have a symbolic displacement - we don't have any extra 3337 // restrictions. 3338 if (!hasSymbolicDisplacement) 3339 return true; 3340 3341 // FIXME: Some tweaks might be needed for medium code model. 3342 if (M != CodeModel::Small && M != CodeModel::Kernel) 3343 return false; 3344 3345 // For small code model we assume that latest object is 16MB before end of 31 3346 // bits boundary. We may also accept pretty large negative constants knowing 3347 // that all objects are in the positive half of address space. 3348 if (M == CodeModel::Small && Offset < 16*1024*1024) 3349 return true; 3350 3351 // For kernel code model we know that all object resist in the negative half 3352 // of 32bits address space. We may not accept negative offsets, since they may 3353 // be just off and we may accept pretty large positive ones. 3354 if (M == CodeModel::Kernel && Offset > 0) 3355 return true; 3356 3357 return false; 3358} 3359 3360/// isCalleePop - Determines whether the callee is required to pop its 3361/// own arguments. Callee pop is necessary to support tail calls. 3362bool X86::isCalleePop(CallingConv::ID CallingConv, 3363 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3364 if (IsVarArg) 3365 return false; 3366 3367 switch (CallingConv) { 3368 default: 3369 return false; 3370 case CallingConv::X86_StdCall: 3371 return !is64Bit; 3372 case CallingConv::X86_FastCall: 3373 return !is64Bit; 3374 case CallingConv::X86_ThisCall: 3375 return !is64Bit; 3376 case CallingConv::Fast: 3377 return TailCallOpt; 3378 case CallingConv::GHC: 3379 return TailCallOpt; 3380 case CallingConv::HiPE: 3381 return TailCallOpt; 3382 } 3383} 3384 3385/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3386/// specific condition code, returning the condition code and the LHS/RHS of the 3387/// comparison to make. 3388static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3389 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3390 if (!isFP) { 3391 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3392 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3393 // X > -1 -> X == 0, jump !sign. 3394 RHS = DAG.getConstant(0, RHS.getValueType()); 3395 return X86::COND_NS; 3396 } 3397 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3398 // X < 0 -> X == 0, jump on sign. 3399 return X86::COND_S; 3400 } 3401 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3402 // X < 1 -> X <= 0 3403 RHS = DAG.getConstant(0, RHS.getValueType()); 3404 return X86::COND_LE; 3405 } 3406 } 3407 3408 switch (SetCCOpcode) { 3409 default: llvm_unreachable("Invalid integer condition!"); 3410 case ISD::SETEQ: return X86::COND_E; 3411 case ISD::SETGT: return X86::COND_G; 3412 case ISD::SETGE: return X86::COND_GE; 3413 case ISD::SETLT: return X86::COND_L; 3414 case ISD::SETLE: return X86::COND_LE; 3415 case ISD::SETNE: return X86::COND_NE; 3416 case ISD::SETULT: return X86::COND_B; 3417 case ISD::SETUGT: return X86::COND_A; 3418 case ISD::SETULE: return X86::COND_BE; 3419 case ISD::SETUGE: return X86::COND_AE; 3420 } 3421 } 3422 3423 // First determine if it is required or is profitable to flip the operands. 3424 3425 // If LHS is a foldable load, but RHS is not, flip the condition. 3426 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3427 !ISD::isNON_EXTLoad(RHS.getNode())) { 3428 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3429 std::swap(LHS, RHS); 3430 } 3431 3432 switch (SetCCOpcode) { 3433 default: break; 3434 case ISD::SETOLT: 3435 case ISD::SETOLE: 3436 case ISD::SETUGT: 3437 case ISD::SETUGE: 3438 std::swap(LHS, RHS); 3439 break; 3440 } 3441 3442 // On a floating point condition, the flags are set as follows: 3443 // ZF PF CF op 3444 // 0 | 0 | 0 | X > Y 3445 // 0 | 0 | 1 | X < Y 3446 // 1 | 0 | 0 | X == Y 3447 // 1 | 1 | 1 | unordered 3448 switch (SetCCOpcode) { 3449 default: llvm_unreachable("Condcode should be pre-legalized away"); 3450 case ISD::SETUEQ: 3451 case ISD::SETEQ: return X86::COND_E; 3452 case ISD::SETOLT: // flipped 3453 case ISD::SETOGT: 3454 case ISD::SETGT: return X86::COND_A; 3455 case ISD::SETOLE: // flipped 3456 case ISD::SETOGE: 3457 case ISD::SETGE: return X86::COND_AE; 3458 case ISD::SETUGT: // flipped 3459 case ISD::SETULT: 3460 case ISD::SETLT: return X86::COND_B; 3461 case ISD::SETUGE: // flipped 3462 case ISD::SETULE: 3463 case ISD::SETLE: return X86::COND_BE; 3464 case ISD::SETONE: 3465 case ISD::SETNE: return X86::COND_NE; 3466 case ISD::SETUO: return X86::COND_P; 3467 case ISD::SETO: return X86::COND_NP; 3468 case ISD::SETOEQ: 3469 case ISD::SETUNE: return X86::COND_INVALID; 3470 } 3471} 3472 3473/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3474/// code. Current x86 isa includes the following FP cmov instructions: 3475/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3476static bool hasFPCMov(unsigned X86CC) { 3477 switch (X86CC) { 3478 default: 3479 return false; 3480 case X86::COND_B: 3481 case X86::COND_BE: 3482 case X86::COND_E: 3483 case X86::COND_P: 3484 case X86::COND_A: 3485 case X86::COND_AE: 3486 case X86::COND_NE: 3487 case X86::COND_NP: 3488 return true; 3489 } 3490} 3491 3492/// isFPImmLegal - Returns true if the target can instruction select the 3493/// specified FP immediate natively. If false, the legalizer will 3494/// materialize the FP immediate as a load from a constant pool. 3495bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3496 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3497 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3498 return true; 3499 } 3500 return false; 3501} 3502 3503/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3504/// the specified range (L, H]. 3505static bool isUndefOrInRange(int Val, int Low, int Hi) { 3506 return (Val < 0) || (Val >= Low && Val < Hi); 3507} 3508 3509/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3510/// specified value. 3511static bool isUndefOrEqual(int Val, int CmpVal) { 3512 return (Val < 0 || Val == CmpVal); 3513} 3514 3515/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning 3516/// from position Pos and ending in Pos+Size, falls within the specified 3517/// sequential range (L, L+Pos]. or is undef. 3518static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3519 unsigned Pos, unsigned Size, int Low) { 3520 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3521 if (!isUndefOrEqual(Mask[i], Low)) 3522 return false; 3523 return true; 3524} 3525 3526/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3527/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3528/// the second operand. 3529static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) { 3530 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3531 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3532 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3533 return (Mask[0] < 2 && Mask[1] < 2); 3534 return false; 3535} 3536 3537/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3538/// is suitable for input to PSHUFHW. 3539static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) { 3540 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3541 return false; 3542 3543 // Lower quadword copied in order or undef. 3544 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3545 return false; 3546 3547 // Upper quadword shuffled. 3548 for (unsigned i = 4; i != 8; ++i) 3549 if (!isUndefOrInRange(Mask[i], 4, 8)) 3550 return false; 3551 3552 if (VT == MVT::v16i16) { 3553 // Lower quadword copied in order or undef. 3554 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3555 return false; 3556 3557 // Upper quadword shuffled. 3558 for (unsigned i = 12; i != 16; ++i) 3559 if (!isUndefOrInRange(Mask[i], 12, 16)) 3560 return false; 3561 } 3562 3563 return true; 3564} 3565 3566/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3567/// is suitable for input to PSHUFLW. 3568static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) { 3569 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3570 return false; 3571 3572 // Upper quadword copied in order. 3573 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3574 return false; 3575 3576 // Lower quadword shuffled. 3577 for (unsigned i = 0; i != 4; ++i) 3578 if (!isUndefOrInRange(Mask[i], 0, 4)) 3579 return false; 3580 3581 if (VT == MVT::v16i16) { 3582 // Upper quadword copied in order. 3583 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3584 return false; 3585 3586 // Lower quadword shuffled. 3587 for (unsigned i = 8; i != 12; ++i) 3588 if (!isUndefOrInRange(Mask[i], 8, 12)) 3589 return false; 3590 } 3591 3592 return true; 3593} 3594 3595/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3596/// is suitable for input to PALIGNR. 3597static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT, 3598 const X86Subtarget *Subtarget) { 3599 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) || 3600 (VT.is256BitVector() && !Subtarget->hasInt256())) 3601 return false; 3602 3603 unsigned NumElts = VT.getVectorNumElements(); 3604 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128; 3605 unsigned NumLaneElts = NumElts/NumLanes; 3606 3607 // Do not handle 64-bit element shuffles with palignr. 3608 if (NumLaneElts == 2) 3609 return false; 3610 3611 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3612 unsigned i; 3613 for (i = 0; i != NumLaneElts; ++i) { 3614 if (Mask[i+l] >= 0) 3615 break; 3616 } 3617 3618 // Lane is all undef, go to next lane 3619 if (i == NumLaneElts) 3620 continue; 3621 3622 int Start = Mask[i+l]; 3623 3624 // Make sure its in this lane in one of the sources 3625 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3626 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3627 return false; 3628 3629 // If not lane 0, then we must match lane 0 3630 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3631 return false; 3632 3633 // Correct second source to be contiguous with first source 3634 if (Start >= (int)NumElts) 3635 Start -= NumElts - NumLaneElts; 3636 3637 // Make sure we're shifting in the right direction. 3638 if (Start <= (int)(i+l)) 3639 return false; 3640 3641 Start -= i; 3642 3643 // Check the rest of the elements to see if they are consecutive. 3644 for (++i; i != NumLaneElts; ++i) { 3645 int Idx = Mask[i+l]; 3646 3647 // Make sure its in this lane 3648 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3649 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3650 return false; 3651 3652 // If not lane 0, then we must match lane 0 3653 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3654 return false; 3655 3656 if (Idx >= (int)NumElts) 3657 Idx -= NumElts - NumLaneElts; 3658 3659 if (!isUndefOrEqual(Idx, Start+i)) 3660 return false; 3661 3662 } 3663 } 3664 3665 return true; 3666} 3667 3668/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3669/// the two vector operands have swapped position. 3670static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3671 unsigned NumElems) { 3672 for (unsigned i = 0; i != NumElems; ++i) { 3673 int idx = Mask[i]; 3674 if (idx < 0) 3675 continue; 3676 else if (idx < (int)NumElems) 3677 Mask[i] = idx + NumElems; 3678 else 3679 Mask[i] = idx - NumElems; 3680 } 3681} 3682 3683/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3684/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3685/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3686/// reverse of what x86 shuffles want. 3687static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) { 3688 3689 unsigned NumElems = VT.getVectorNumElements(); 3690 unsigned NumLanes = VT.getSizeInBits()/128; 3691 unsigned NumLaneElems = NumElems/NumLanes; 3692 3693 if (NumLaneElems != 2 && NumLaneElems != 4) 3694 return false; 3695 3696 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3697 bool symetricMaskRequired = 3698 (VT.getSizeInBits() >= 256) && (EltSize == 32); 3699 3700 // VSHUFPSY divides the resulting vector into 4 chunks. 3701 // The sources are also splitted into 4 chunks, and each destination 3702 // chunk must come from a different source chunk. 3703 // 3704 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3705 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3706 // 3707 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3708 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3709 // 3710 // VSHUFPDY divides the resulting vector into 4 chunks. 3711 // The sources are also splitted into 4 chunks, and each destination 3712 // chunk must come from a different source chunk. 3713 // 3714 // SRC1 => X3 X2 X1 X0 3715 // SRC2 => Y3 Y2 Y1 Y0 3716 // 3717 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3718 // 3719 SmallVector<int, 4> MaskVal(NumLaneElems, -1); 3720 unsigned HalfLaneElems = NumLaneElems/2; 3721 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3722 for (unsigned i = 0; i != NumLaneElems; ++i) { 3723 int Idx = Mask[i+l]; 3724 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3725 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3726 return false; 3727 // For VSHUFPSY, the mask of the second half must be the same as the 3728 // first but with the appropriate offsets. This works in the same way as 3729 // VPERMILPS works with masks. 3730 if (!symetricMaskRequired || Idx < 0) 3731 continue; 3732 if (MaskVal[i] < 0) { 3733 MaskVal[i] = Idx - l; 3734 continue; 3735 } 3736 if ((signed)(Idx - l) != MaskVal[i]) 3737 return false; 3738 } 3739 } 3740 3741 return true; 3742} 3743 3744/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3745/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3746static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) { 3747 if (!VT.is128BitVector()) 3748 return false; 3749 3750 unsigned NumElems = VT.getVectorNumElements(); 3751 3752 if (NumElems != 4) 3753 return false; 3754 3755 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3756 return isUndefOrEqual(Mask[0], 6) && 3757 isUndefOrEqual(Mask[1], 7) && 3758 isUndefOrEqual(Mask[2], 2) && 3759 isUndefOrEqual(Mask[3], 3); 3760} 3761 3762/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3763/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3764/// <2, 3, 2, 3> 3765static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) { 3766 if (!VT.is128BitVector()) 3767 return false; 3768 3769 unsigned NumElems = VT.getVectorNumElements(); 3770 3771 if (NumElems != 4) 3772 return false; 3773 3774 return isUndefOrEqual(Mask[0], 2) && 3775 isUndefOrEqual(Mask[1], 3) && 3776 isUndefOrEqual(Mask[2], 2) && 3777 isUndefOrEqual(Mask[3], 3); 3778} 3779 3780/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3781/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3782static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) { 3783 if (!VT.is128BitVector()) 3784 return false; 3785 3786 unsigned NumElems = VT.getVectorNumElements(); 3787 3788 if (NumElems != 2 && NumElems != 4) 3789 return false; 3790 3791 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3792 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3793 return false; 3794 3795 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3796 if (!isUndefOrEqual(Mask[i], i)) 3797 return false; 3798 3799 return true; 3800} 3801 3802/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3803/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3804static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) { 3805 if (!VT.is128BitVector()) 3806 return false; 3807 3808 unsigned NumElems = VT.getVectorNumElements(); 3809 3810 if (NumElems != 2 && NumElems != 4) 3811 return false; 3812 3813 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3814 if (!isUndefOrEqual(Mask[i], i)) 3815 return false; 3816 3817 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3818 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3819 return false; 3820 3821 return true; 3822} 3823 3824// 3825// Some special combinations that can be optimized. 3826// 3827static 3828SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, 3829 SelectionDAG &DAG) { 3830 MVT VT = SVOp->getSimpleValueType(0); 3831 SDLoc dl(SVOp); 3832 3833 if (VT != MVT::v8i32 && VT != MVT::v8f32) 3834 return SDValue(); 3835 3836 ArrayRef<int> Mask = SVOp->getMask(); 3837 3838 // These are the special masks that may be optimized. 3839 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14}; 3840 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15}; 3841 bool MatchEvenMask = true; 3842 bool MatchOddMask = true; 3843 for (int i=0; i<8; ++i) { 3844 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) 3845 MatchEvenMask = false; 3846 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) 3847 MatchOddMask = false; 3848 } 3849 3850 if (!MatchEvenMask && !MatchOddMask) 3851 return SDValue(); 3852 3853 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT); 3854 3855 SDValue Op0 = SVOp->getOperand(0); 3856 SDValue Op1 = SVOp->getOperand(1); 3857 3858 if (MatchEvenMask) { 3859 // Shift the second operand right to 32 bits. 3860 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 }; 3861 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask); 3862 } else { 3863 // Shift the first operand left to 32 bits. 3864 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 }; 3865 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask); 3866 } 3867 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15}; 3868 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask); 3869} 3870 3871/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3872/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3873static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT, 3874 bool HasInt256, bool V2IsSplat = false) { 3875 3876 assert(VT.getSizeInBits() >= 128 && 3877 "Unsupported vector type for unpckl"); 3878 3879 // AVX defines UNPCK* to operate independently on 128-bit lanes. 3880 unsigned NumLanes; 3881 unsigned NumOf256BitLanes; 3882 unsigned NumElts = VT.getVectorNumElements(); 3883 if (VT.is256BitVector()) { 3884 if (NumElts != 4 && NumElts != 8 && 3885 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3886 return false; 3887 NumLanes = 2; 3888 NumOf256BitLanes = 1; 3889 } else if (VT.is512BitVector()) { 3890 assert(VT.getScalarType().getSizeInBits() >= 32 && 3891 "Unsupported vector type for unpckh"); 3892 NumLanes = 2; 3893 NumOf256BitLanes = 2; 3894 } else { 3895 NumLanes = 1; 3896 NumOf256BitLanes = 1; 3897 } 3898 3899 unsigned NumEltsInStride = NumElts/NumOf256BitLanes; 3900 unsigned NumLaneElts = NumEltsInStride/NumLanes; 3901 3902 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) { 3903 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) { 3904 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) { 3905 int BitI = Mask[l256*NumEltsInStride+l+i]; 3906 int BitI1 = Mask[l256*NumEltsInStride+l+i+1]; 3907 if (!isUndefOrEqual(BitI, j+l256*NumElts)) 3908 return false; 3909 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts)) 3910 return false; 3911 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride)) 3912 return false; 3913 } 3914 } 3915 } 3916 return true; 3917} 3918 3919/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3920/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3921static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT, 3922 bool HasInt256, bool V2IsSplat = false) { 3923 assert(VT.getSizeInBits() >= 128 && 3924 "Unsupported vector type for unpckh"); 3925 3926 // AVX defines UNPCK* to operate independently on 128-bit lanes. 3927 unsigned NumLanes; 3928 unsigned NumOf256BitLanes; 3929 unsigned NumElts = VT.getVectorNumElements(); 3930 if (VT.is256BitVector()) { 3931 if (NumElts != 4 && NumElts != 8 && 3932 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3933 return false; 3934 NumLanes = 2; 3935 NumOf256BitLanes = 1; 3936 } else if (VT.is512BitVector()) { 3937 assert(VT.getScalarType().getSizeInBits() >= 32 && 3938 "Unsupported vector type for unpckh"); 3939 NumLanes = 2; 3940 NumOf256BitLanes = 2; 3941 } else { 3942 NumLanes = 1; 3943 NumOf256BitLanes = 1; 3944 } 3945 3946 unsigned NumEltsInStride = NumElts/NumOf256BitLanes; 3947 unsigned NumLaneElts = NumEltsInStride/NumLanes; 3948 3949 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) { 3950 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) { 3951 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) { 3952 int BitI = Mask[l256*NumEltsInStride+l+i]; 3953 int BitI1 = Mask[l256*NumEltsInStride+l+i+1]; 3954 if (!isUndefOrEqual(BitI, j+l256*NumElts)) 3955 return false; 3956 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts)) 3957 return false; 3958 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride)) 3959 return false; 3960 } 3961 } 3962 } 3963 return true; 3964} 3965 3966/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3967/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3968/// <0, 0, 1, 1> 3969static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) { 3970 unsigned NumElts = VT.getVectorNumElements(); 3971 bool Is256BitVec = VT.is256BitVector(); 3972 3973 if (VT.is512BitVector()) 3974 return false; 3975 assert((VT.is128BitVector() || VT.is256BitVector()) && 3976 "Unsupported vector type for unpckh"); 3977 3978 if (Is256BitVec && NumElts != 4 && NumElts != 8 && 3979 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3980 return false; 3981 3982 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3983 // FIXME: Need a better way to get rid of this, there's no latency difference 3984 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3985 // the former later. We should also remove the "_undef" special mask. 3986 if (NumElts == 4 && Is256BitVec) 3987 return false; 3988 3989 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3990 // independently on 128-bit lanes. 3991 unsigned NumLanes = VT.getSizeInBits()/128; 3992 unsigned NumLaneElts = NumElts/NumLanes; 3993 3994 for (unsigned l = 0; l != NumElts; l += NumLaneElts) { 3995 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) { 3996 int BitI = Mask[l+i]; 3997 int BitI1 = Mask[l+i+1]; 3998 3999 if (!isUndefOrEqual(BitI, j)) 4000 return false; 4001 if (!isUndefOrEqual(BitI1, j)) 4002 return false; 4003 } 4004 } 4005 4006 return true; 4007} 4008 4009/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 4010/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 4011/// <2, 2, 3, 3> 4012static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) { 4013 unsigned NumElts = VT.getVectorNumElements(); 4014 4015 if (VT.is512BitVector()) 4016 return false; 4017 4018 assert((VT.is128BitVector() || VT.is256BitVector()) && 4019 "Unsupported vector type for unpckh"); 4020 4021 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 4022 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 4023 return false; 4024 4025 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 4026 // independently on 128-bit lanes. 4027 unsigned NumLanes = VT.getSizeInBits()/128; 4028 unsigned NumLaneElts = NumElts/NumLanes; 4029 4030 for (unsigned l = 0; l != NumElts; l += NumLaneElts) { 4031 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) { 4032 int BitI = Mask[l+i]; 4033 int BitI1 = Mask[l+i+1]; 4034 if (!isUndefOrEqual(BitI, j)) 4035 return false; 4036 if (!isUndefOrEqual(BitI1, j)) 4037 return false; 4038 } 4039 } 4040 return true; 4041} 4042 4043/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 4044/// specifies a shuffle of elements that is suitable for input to MOVSS, 4045/// MOVSD, and MOVD, i.e. setting the lowest element. 4046static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 4047 if (VT.getVectorElementType().getSizeInBits() < 32) 4048 return false; 4049 if (!VT.is128BitVector()) 4050 return false; 4051 4052 unsigned NumElts = VT.getVectorNumElements(); 4053 4054 if (!isUndefOrEqual(Mask[0], NumElts)) 4055 return false; 4056 4057 for (unsigned i = 1; i != NumElts; ++i) 4058 if (!isUndefOrEqual(Mask[i], i)) 4059 return false; 4060 4061 return true; 4062} 4063 4064/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 4065/// as permutations between 128-bit chunks or halves. As an example: this 4066/// shuffle bellow: 4067/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 4068/// The first half comes from the second half of V1 and the second half from the 4069/// the second half of V2. 4070static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) { 4071 if (!HasFp256 || !VT.is256BitVector()) 4072 return false; 4073 4074 // The shuffle result is divided into half A and half B. In total the two 4075 // sources have 4 halves, namely: C, D, E, F. The final values of A and 4076 // B must come from C, D, E or F. 4077 unsigned HalfSize = VT.getVectorNumElements()/2; 4078 bool MatchA = false, MatchB = false; 4079 4080 // Check if A comes from one of C, D, E, F. 4081 for (unsigned Half = 0; Half != 4; ++Half) { 4082 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 4083 MatchA = true; 4084 break; 4085 } 4086 } 4087 4088 // Check if B comes from one of C, D, E, F. 4089 for (unsigned Half = 0; Half != 4; ++Half) { 4090 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 4091 MatchB = true; 4092 break; 4093 } 4094 } 4095 4096 return MatchA && MatchB; 4097} 4098 4099/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 4100/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 4101static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 4102 MVT VT = SVOp->getSimpleValueType(0); 4103 4104 unsigned HalfSize = VT.getVectorNumElements()/2; 4105 4106 unsigned FstHalf = 0, SndHalf = 0; 4107 for (unsigned i = 0; i < HalfSize; ++i) { 4108 if (SVOp->getMaskElt(i) > 0) { 4109 FstHalf = SVOp->getMaskElt(i)/HalfSize; 4110 break; 4111 } 4112 } 4113 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 4114 if (SVOp->getMaskElt(i) > 0) { 4115 SndHalf = SVOp->getMaskElt(i)/HalfSize; 4116 break; 4117 } 4118 } 4119 4120 return (FstHalf | (SndHalf << 4)); 4121} 4122 4123// Symetric in-lane mask. Each lane has 4 elements (for imm8) 4124static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) { 4125 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4126 if (EltSize < 32) 4127 return false; 4128 4129 unsigned NumElts = VT.getVectorNumElements(); 4130 Imm8 = 0; 4131 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) { 4132 for (unsigned i = 0; i != NumElts; ++i) { 4133 if (Mask[i] < 0) 4134 continue; 4135 Imm8 |= Mask[i] << (i*2); 4136 } 4137 return true; 4138 } 4139 4140 unsigned LaneSize = 4; 4141 SmallVector<int, 4> MaskVal(LaneSize, -1); 4142 4143 for (unsigned l = 0; l != NumElts; l += LaneSize) { 4144 for (unsigned i = 0; i != LaneSize; ++i) { 4145 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 4146 return false; 4147 if (Mask[i+l] < 0) 4148 continue; 4149 if (MaskVal[i] < 0) { 4150 MaskVal[i] = Mask[i+l] - l; 4151 Imm8 |= MaskVal[i] << (i*2); 4152 continue; 4153 } 4154 if (Mask[i+l] != (signed)(MaskVal[i]+l)) 4155 return false; 4156 } 4157 } 4158 return true; 4159} 4160 4161/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 4162/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 4163/// Note that VPERMIL mask matching is different depending whether theunderlying 4164/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 4165/// to the same elements of the low, but to the higher half of the source. 4166/// In VPERMILPD the two lanes could be shuffled independently of each other 4167/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 4168static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) { 4169 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4170 if (VT.getSizeInBits() < 256 || EltSize < 32) 4171 return false; 4172 bool symetricMaskRequired = (EltSize == 32); 4173 unsigned NumElts = VT.getVectorNumElements(); 4174 4175 unsigned NumLanes = VT.getSizeInBits()/128; 4176 unsigned LaneSize = NumElts/NumLanes; 4177 // 2 or 4 elements in one lane 4178 4179 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1); 4180 for (unsigned l = 0; l != NumElts; l += LaneSize) { 4181 for (unsigned i = 0; i != LaneSize; ++i) { 4182 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 4183 return false; 4184 if (symetricMaskRequired) { 4185 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) { 4186 ExpectedMaskVal[i] = Mask[i+l] - l; 4187 continue; 4188 } 4189 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l)) 4190 return false; 4191 } 4192 } 4193 } 4194 return true; 4195} 4196 4197/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 4198/// of what x86 movss want. X86 movs requires the lowest element to be lowest 4199/// element of vector 2 and the other elements to come from vector 1 in order. 4200static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT, 4201 bool V2IsSplat = false, bool V2IsUndef = false) { 4202 if (!VT.is128BitVector()) 4203 return false; 4204 4205 unsigned NumOps = VT.getVectorNumElements(); 4206 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 4207 return false; 4208 4209 if (!isUndefOrEqual(Mask[0], 0)) 4210 return false; 4211 4212 for (unsigned i = 1; i != NumOps; ++i) 4213 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 4214 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 4215 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 4216 return false; 4217 4218 return true; 4219} 4220 4221/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4222/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 4223/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 4224static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT, 4225 const X86Subtarget *Subtarget) { 4226 if (!Subtarget->hasSSE3()) 4227 return false; 4228 4229 unsigned NumElems = VT.getVectorNumElements(); 4230 4231 if ((VT.is128BitVector() && NumElems != 4) || 4232 (VT.is256BitVector() && NumElems != 8) || 4233 (VT.is512BitVector() && NumElems != 16)) 4234 return false; 4235 4236 // "i+1" is the value the indexed mask element must have 4237 for (unsigned i = 0; i != NumElems; i += 2) 4238 if (!isUndefOrEqual(Mask[i], i+1) || 4239 !isUndefOrEqual(Mask[i+1], i+1)) 4240 return false; 4241 4242 return true; 4243} 4244 4245/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4246/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 4247/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 4248static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT, 4249 const X86Subtarget *Subtarget) { 4250 if (!Subtarget->hasSSE3()) 4251 return false; 4252 4253 unsigned NumElems = VT.getVectorNumElements(); 4254 4255 if ((VT.is128BitVector() && NumElems != 4) || 4256 (VT.is256BitVector() && NumElems != 8) || 4257 (VT.is512BitVector() && NumElems != 16)) 4258 return false; 4259 4260 // "i" is the value the indexed mask element must have 4261 for (unsigned i = 0; i != NumElems; i += 2) 4262 if (!isUndefOrEqual(Mask[i], i) || 4263 !isUndefOrEqual(Mask[i+1], i)) 4264 return false; 4265 4266 return true; 4267} 4268 4269/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 4270/// specifies a shuffle of elements that is suitable for input to 256-bit 4271/// version of MOVDDUP. 4272static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) { 4273 if (!HasFp256 || !VT.is256BitVector()) 4274 return false; 4275 4276 unsigned NumElts = VT.getVectorNumElements(); 4277 if (NumElts != 4) 4278 return false; 4279 4280 for (unsigned i = 0; i != NumElts/2; ++i) 4281 if (!isUndefOrEqual(Mask[i], 0)) 4282 return false; 4283 for (unsigned i = NumElts/2; i != NumElts; ++i) 4284 if (!isUndefOrEqual(Mask[i], NumElts/2)) 4285 return false; 4286 return true; 4287} 4288 4289/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4290/// specifies a shuffle of elements that is suitable for input to 128-bit 4291/// version of MOVDDUP. 4292static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) { 4293 if (!VT.is128BitVector()) 4294 return false; 4295 4296 unsigned e = VT.getVectorNumElements() / 2; 4297 for (unsigned i = 0; i != e; ++i) 4298 if (!isUndefOrEqual(Mask[i], i)) 4299 return false; 4300 for (unsigned i = 0; i != e; ++i) 4301 if (!isUndefOrEqual(Mask[e+i], i)) 4302 return false; 4303 return true; 4304} 4305 4306/// isVEXTRACTIndex - Return true if the specified 4307/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4308/// suitable for instruction that extract 128 or 256 bit vectors 4309static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) { 4310 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width"); 4311 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4312 return false; 4313 4314 // The index should be aligned on a vecWidth-bit boundary. 4315 uint64_t Index = 4316 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4317 4318 MVT VT = N->getSimpleValueType(0); 4319 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4320 bool Result = (Index * ElSize) % vecWidth == 0; 4321 4322 return Result; 4323} 4324 4325/// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR 4326/// operand specifies a subvector insert that is suitable for input to 4327/// insertion of 128 or 256-bit subvectors 4328static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) { 4329 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width"); 4330 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4331 return false; 4332 // The index should be aligned on a vecWidth-bit boundary. 4333 uint64_t Index = 4334 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4335 4336 MVT VT = N->getSimpleValueType(0); 4337 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4338 bool Result = (Index * ElSize) % vecWidth == 0; 4339 4340 return Result; 4341} 4342 4343bool X86::isVINSERT128Index(SDNode *N) { 4344 return isVINSERTIndex(N, 128); 4345} 4346 4347bool X86::isVINSERT256Index(SDNode *N) { 4348 return isVINSERTIndex(N, 256); 4349} 4350 4351bool X86::isVEXTRACT128Index(SDNode *N) { 4352 return isVEXTRACTIndex(N, 128); 4353} 4354 4355bool X86::isVEXTRACT256Index(SDNode *N) { 4356 return isVEXTRACTIndex(N, 256); 4357} 4358 4359/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4360/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4361/// Handles 128-bit and 256-bit. 4362static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 4363 MVT VT = N->getSimpleValueType(0); 4364 4365 assert((VT.getSizeInBits() >= 128) && 4366 "Unsupported vector type for PSHUF/SHUFP"); 4367 4368 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 4369 // independently on 128-bit lanes. 4370 unsigned NumElts = VT.getVectorNumElements(); 4371 unsigned NumLanes = VT.getSizeInBits()/128; 4372 unsigned NumLaneElts = NumElts/NumLanes; 4373 4374 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) && 4375 "Only supports 2, 4 or 8 elements per lane"); 4376 4377 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0; 4378 unsigned Mask = 0; 4379 for (unsigned i = 0; i != NumElts; ++i) { 4380 int Elt = N->getMaskElt(i); 4381 if (Elt < 0) continue; 4382 Elt &= NumLaneElts - 1; 4383 unsigned ShAmt = (i << Shift) % 8; 4384 Mask |= Elt << ShAmt; 4385 } 4386 4387 return Mask; 4388} 4389 4390/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4391/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4392static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 4393 MVT VT = N->getSimpleValueType(0); 4394 4395 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4396 "Unsupported vector type for PSHUFHW"); 4397 4398 unsigned NumElts = VT.getVectorNumElements(); 4399 4400 unsigned Mask = 0; 4401 for (unsigned l = 0; l != NumElts; l += 8) { 4402 // 8 nodes per lane, but we only care about the last 4. 4403 for (unsigned i = 0; i < 4; ++i) { 4404 int Elt = N->getMaskElt(l+i+4); 4405 if (Elt < 0) continue; 4406 Elt &= 0x3; // only 2-bits. 4407 Mask |= Elt << (i * 2); 4408 } 4409 } 4410 4411 return Mask; 4412} 4413 4414/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4415/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4416static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 4417 MVT VT = N->getSimpleValueType(0); 4418 4419 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4420 "Unsupported vector type for PSHUFHW"); 4421 4422 unsigned NumElts = VT.getVectorNumElements(); 4423 4424 unsigned Mask = 0; 4425 for (unsigned l = 0; l != NumElts; l += 8) { 4426 // 8 nodes per lane, but we only care about the first 4. 4427 for (unsigned i = 0; i < 4; ++i) { 4428 int Elt = N->getMaskElt(l+i); 4429 if (Elt < 0) continue; 4430 Elt &= 0x3; // only 2-bits 4431 Mask |= Elt << (i * 2); 4432 } 4433 } 4434 4435 return Mask; 4436} 4437 4438/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4439/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4440static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4441 MVT VT = SVOp->getSimpleValueType(0); 4442 unsigned EltSize = VT.is512BitVector() ? 1 : 4443 VT.getVectorElementType().getSizeInBits() >> 3; 4444 4445 unsigned NumElts = VT.getVectorNumElements(); 4446 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128; 4447 unsigned NumLaneElts = NumElts/NumLanes; 4448 4449 int Val = 0; 4450 unsigned i; 4451 for (i = 0; i != NumElts; ++i) { 4452 Val = SVOp->getMaskElt(i); 4453 if (Val >= 0) 4454 break; 4455 } 4456 if (Val >= (int)NumElts) 4457 Val -= NumElts - NumLaneElts; 4458 4459 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4460 return (Val - i) * EltSize; 4461} 4462 4463static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) { 4464 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width"); 4465 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4466 llvm_unreachable("Illegal extract subvector for VEXTRACT"); 4467 4468 uint64_t Index = 4469 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4470 4471 MVT VecVT = N->getOperand(0).getSimpleValueType(); 4472 MVT ElVT = VecVT.getVectorElementType(); 4473 4474 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); 4475 return Index / NumElemsPerChunk; 4476} 4477 4478static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) { 4479 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width"); 4480 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4481 llvm_unreachable("Illegal insert subvector for VINSERT"); 4482 4483 uint64_t Index = 4484 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4485 4486 MVT VecVT = N->getSimpleValueType(0); 4487 MVT ElVT = VecVT.getVectorElementType(); 4488 4489 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); 4490 return Index / NumElemsPerChunk; 4491} 4492 4493/// getExtractVEXTRACT128Immediate - Return the appropriate immediate 4494/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4495/// and VINSERTI128 instructions. 4496unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) { 4497 return getExtractVEXTRACTImmediate(N, 128); 4498} 4499 4500/// getExtractVEXTRACT256Immediate - Return the appropriate immediate 4501/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4 4502/// and VINSERTI64x4 instructions. 4503unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) { 4504 return getExtractVEXTRACTImmediate(N, 256); 4505} 4506 4507/// getInsertVINSERT128Immediate - Return the appropriate immediate 4508/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4509/// and VINSERTI128 instructions. 4510unsigned X86::getInsertVINSERT128Immediate(SDNode *N) { 4511 return getInsertVINSERTImmediate(N, 128); 4512} 4513 4514/// getInsertVINSERT256Immediate - Return the appropriate immediate 4515/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4 4516/// and VINSERTI64x4 instructions. 4517unsigned X86::getInsertVINSERT256Immediate(SDNode *N) { 4518 return getInsertVINSERTImmediate(N, 256); 4519} 4520 4521/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4522/// constant +0.0. 4523bool X86::isZeroNode(SDValue Elt) { 4524 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt)) 4525 return CN->isNullValue(); 4526 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt)) 4527 return CFP->getValueAPF().isPosZero(); 4528 return false; 4529} 4530 4531/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4532/// their permute mask. 4533static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4534 SelectionDAG &DAG) { 4535 MVT VT = SVOp->getSimpleValueType(0); 4536 unsigned NumElems = VT.getVectorNumElements(); 4537 SmallVector<int, 8> MaskVec; 4538 4539 for (unsigned i = 0; i != NumElems; ++i) { 4540 int Idx = SVOp->getMaskElt(i); 4541 if (Idx >= 0) { 4542 if (Idx < (int)NumElems) 4543 Idx += NumElems; 4544 else 4545 Idx -= NumElems; 4546 } 4547 MaskVec.push_back(Idx); 4548 } 4549 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1), 4550 SVOp->getOperand(0), &MaskVec[0]); 4551} 4552 4553/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4554/// match movhlps. The lower half elements should come from upper half of 4555/// V1 (and in order), and the upper half elements should come from the upper 4556/// half of V2 (and in order). 4557static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) { 4558 if (!VT.is128BitVector()) 4559 return false; 4560 if (VT.getVectorNumElements() != 4) 4561 return false; 4562 for (unsigned i = 0, e = 2; i != e; ++i) 4563 if (!isUndefOrEqual(Mask[i], i+2)) 4564 return false; 4565 for (unsigned i = 2; i != 4; ++i) 4566 if (!isUndefOrEqual(Mask[i], i+4)) 4567 return false; 4568 return true; 4569} 4570 4571/// isScalarLoadToVector - Returns true if the node is a scalar load that 4572/// is promoted to a vector. It also returns the LoadSDNode by reference if 4573/// required. 4574static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4575 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4576 return false; 4577 N = N->getOperand(0).getNode(); 4578 if (!ISD::isNON_EXTLoad(N)) 4579 return false; 4580 if (LD) 4581 *LD = cast<LoadSDNode>(N); 4582 return true; 4583} 4584 4585// Test whether the given value is a vector value which will be legalized 4586// into a load. 4587static bool WillBeConstantPoolLoad(SDNode *N) { 4588 if (N->getOpcode() != ISD::BUILD_VECTOR) 4589 return false; 4590 4591 // Check for any non-constant elements. 4592 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4593 switch (N->getOperand(i).getNode()->getOpcode()) { 4594 case ISD::UNDEF: 4595 case ISD::ConstantFP: 4596 case ISD::Constant: 4597 break; 4598 default: 4599 return false; 4600 } 4601 4602 // Vectors of all-zeros and all-ones are materialized with special 4603 // instructions rather than being loaded. 4604 return !ISD::isBuildVectorAllZeros(N) && 4605 !ISD::isBuildVectorAllOnes(N); 4606} 4607 4608/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4609/// match movlp{s|d}. The lower half elements should come from lower half of 4610/// V1 (and in order), and the upper half elements should come from the upper 4611/// half of V2 (and in order). And since V1 will become the source of the 4612/// MOVLP, it must be either a vector load or a scalar load to vector. 4613static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4614 ArrayRef<int> Mask, MVT VT) { 4615 if (!VT.is128BitVector()) 4616 return false; 4617 4618 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4619 return false; 4620 // Is V2 is a vector load, don't do this transformation. We will try to use 4621 // load folding shufps op. 4622 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4623 return false; 4624 4625 unsigned NumElems = VT.getVectorNumElements(); 4626 4627 if (NumElems != 2 && NumElems != 4) 4628 return false; 4629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4630 if (!isUndefOrEqual(Mask[i], i)) 4631 return false; 4632 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4633 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4634 return false; 4635 return true; 4636} 4637 4638/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4639/// all the same. 4640static bool isSplatVector(SDNode *N) { 4641 if (N->getOpcode() != ISD::BUILD_VECTOR) 4642 return false; 4643 4644 SDValue SplatValue = N->getOperand(0); 4645 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4646 if (N->getOperand(i) != SplatValue) 4647 return false; 4648 return true; 4649} 4650 4651/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4652/// to an zero vector. 4653/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4654static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4655 SDValue V1 = N->getOperand(0); 4656 SDValue V2 = N->getOperand(1); 4657 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4658 for (unsigned i = 0; i != NumElems; ++i) { 4659 int Idx = N->getMaskElt(i); 4660 if (Idx >= (int)NumElems) { 4661 unsigned Opc = V2.getOpcode(); 4662 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4663 continue; 4664 if (Opc != ISD::BUILD_VECTOR || 4665 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4666 return false; 4667 } else if (Idx >= 0) { 4668 unsigned Opc = V1.getOpcode(); 4669 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4670 continue; 4671 if (Opc != ISD::BUILD_VECTOR || 4672 !X86::isZeroNode(V1.getOperand(Idx))) 4673 return false; 4674 } 4675 } 4676 return true; 4677} 4678 4679/// getZeroVector - Returns a vector of specified type with all zero elements. 4680/// 4681static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4682 SelectionDAG &DAG, SDLoc dl) { 4683 assert(VT.isVector() && "Expected a vector type"); 4684 4685 // Always build SSE zero vectors as <4 x i32> bitcasted 4686 // to their dest type. This ensures they get CSE'd. 4687 SDValue Vec; 4688 if (VT.is128BitVector()) { // SSE 4689 if (Subtarget->hasSSE2()) { // SSE2 4690 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4691 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4692 } else { // SSE1 4693 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4694 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4695 } 4696 } else if (VT.is256BitVector()) { // AVX 4697 if (Subtarget->hasInt256()) { // AVX2 4698 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4699 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4700 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 4701 array_lengthof(Ops)); 4702 } else { 4703 // 256-bit logic and arithmetic instructions in AVX are all 4704 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4705 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4706 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4707 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 4708 array_lengthof(Ops)); 4709 } 4710 } else if (VT.is512BitVector()) { // AVX-512 4711 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4712 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst, 4713 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4714 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16); 4715 } else 4716 llvm_unreachable("Unexpected vector type"); 4717 4718 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4719} 4720 4721/// getOnesVector - Returns a vector of specified type with all bits set. 4722/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4723/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4724/// Then bitcast to their original type, ensuring they get CSE'd. 4725static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, 4726 SDLoc dl) { 4727 assert(VT.isVector() && "Expected a vector type"); 4728 4729 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4730 SDValue Vec; 4731 if (VT.is256BitVector()) { 4732 if (HasInt256) { // AVX2 4733 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4734 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 4735 array_lengthof(Ops)); 4736 } else { // AVX 4737 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4738 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4739 } 4740 } else if (VT.is128BitVector()) { 4741 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4742 } else 4743 llvm_unreachable("Unexpected vector type"); 4744 4745 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4746} 4747 4748/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4749/// that point to V2 points to its first element. 4750static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4751 for (unsigned i = 0; i != NumElems; ++i) { 4752 if (Mask[i] > (int)NumElems) { 4753 Mask[i] = NumElems; 4754 } 4755 } 4756} 4757 4758/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4759/// operation of specified width. 4760static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, 4761 SDValue V2) { 4762 unsigned NumElems = VT.getVectorNumElements(); 4763 SmallVector<int, 8> Mask; 4764 Mask.push_back(NumElems); 4765 for (unsigned i = 1; i != NumElems; ++i) 4766 Mask.push_back(i); 4767 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4768} 4769 4770/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4771static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, 4772 SDValue V2) { 4773 unsigned NumElems = VT.getVectorNumElements(); 4774 SmallVector<int, 8> Mask; 4775 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4776 Mask.push_back(i); 4777 Mask.push_back(i + NumElems); 4778 } 4779 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4780} 4781 4782/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4783static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, 4784 SDValue V2) { 4785 unsigned NumElems = VT.getVectorNumElements(); 4786 SmallVector<int, 8> Mask; 4787 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4788 Mask.push_back(i + Half); 4789 Mask.push_back(i + NumElems + Half); 4790 } 4791 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4792} 4793 4794// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4795// a generic shuffle instruction because the target has no such instructions. 4796// Generate shuffles which repeat i16 and i8 several times until they can be 4797// represented by v4f32 and then be manipulated by target suported shuffles. 4798static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4799 MVT VT = V.getSimpleValueType(); 4800 int NumElems = VT.getVectorNumElements(); 4801 SDLoc dl(V); 4802 4803 while (NumElems > 4) { 4804 if (EltNo < NumElems/2) { 4805 V = getUnpackl(DAG, dl, VT, V, V); 4806 } else { 4807 V = getUnpackh(DAG, dl, VT, V, V); 4808 EltNo -= NumElems/2; 4809 } 4810 NumElems >>= 1; 4811 } 4812 return V; 4813} 4814 4815/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4816static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4817 MVT VT = V.getSimpleValueType(); 4818 SDLoc dl(V); 4819 4820 if (VT.is128BitVector()) { 4821 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4822 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4823 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4824 &SplatMask[0]); 4825 } else if (VT.is256BitVector()) { 4826 // To use VPERMILPS to splat scalars, the second half of indicies must 4827 // refer to the higher part, which is a duplication of the lower one, 4828 // because VPERMILPS can only handle in-lane permutations. 4829 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4830 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4831 4832 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4833 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4834 &SplatMask[0]); 4835 } else 4836 llvm_unreachable("Vector size not supported"); 4837 4838 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4839} 4840 4841/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4842static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4843 MVT SrcVT = SV->getSimpleValueType(0); 4844 SDValue V1 = SV->getOperand(0); 4845 SDLoc dl(SV); 4846 4847 int EltNo = SV->getSplatIndex(); 4848 int NumElems = SrcVT.getVectorNumElements(); 4849 bool Is256BitVec = SrcVT.is256BitVector(); 4850 4851 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) && 4852 "Unknown how to promote splat for type"); 4853 4854 // Extract the 128-bit part containing the splat element and update 4855 // the splat element index when it refers to the higher register. 4856 if (Is256BitVec) { 4857 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4858 if (EltNo >= NumElems/2) 4859 EltNo -= NumElems/2; 4860 } 4861 4862 // All i16 and i8 vector types can't be used directly by a generic shuffle 4863 // instruction because the target has no such instruction. Generate shuffles 4864 // which repeat i16 and i8 several times until they fit in i32, and then can 4865 // be manipulated by target suported shuffles. 4866 MVT EltVT = SrcVT.getVectorElementType(); 4867 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4868 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4869 4870 // Recreate the 256-bit vector and place the same 128-bit vector 4871 // into the low and high part. This is necessary because we want 4872 // to use VPERM* to shuffle the vectors 4873 if (Is256BitVec) { 4874 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4875 } 4876 4877 return getLegalSplat(DAG, V1, EltNo); 4878} 4879 4880/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4881/// vector of zero or undef vector. This produces a shuffle where the low 4882/// element of V2 is swizzled into the zero/undef vector, landing at element 4883/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4884static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4885 bool IsZero, 4886 const X86Subtarget *Subtarget, 4887 SelectionDAG &DAG) { 4888 MVT VT = V2.getSimpleValueType(); 4889 SDValue V1 = IsZero 4890 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT); 4891 unsigned NumElems = VT.getVectorNumElements(); 4892 SmallVector<int, 16> MaskVec; 4893 for (unsigned i = 0; i != NumElems; ++i) 4894 // If this is the insertion idx, put the low elt of V2 here. 4895 MaskVec.push_back(i == Idx ? NumElems : i); 4896 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]); 4897} 4898 4899/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4900/// target specific opcode. Returns true if the Mask could be calculated. 4901/// Sets IsUnary to true if only uses one source. 4902static bool getTargetShuffleMask(SDNode *N, MVT VT, 4903 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4904 unsigned NumElems = VT.getVectorNumElements(); 4905 SDValue ImmN; 4906 4907 IsUnary = false; 4908 switch(N->getOpcode()) { 4909 case X86ISD::SHUFP: 4910 ImmN = N->getOperand(N->getNumOperands()-1); 4911 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4912 break; 4913 case X86ISD::UNPCKH: 4914 DecodeUNPCKHMask(VT, Mask); 4915 break; 4916 case X86ISD::UNPCKL: 4917 DecodeUNPCKLMask(VT, Mask); 4918 break; 4919 case X86ISD::MOVHLPS: 4920 DecodeMOVHLPSMask(NumElems, Mask); 4921 break; 4922 case X86ISD::MOVLHPS: 4923 DecodeMOVLHPSMask(NumElems, Mask); 4924 break; 4925 case X86ISD::PALIGNR: 4926 ImmN = N->getOperand(N->getNumOperands()-1); 4927 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4928 break; 4929 case X86ISD::PSHUFD: 4930 case X86ISD::VPERMILP: 4931 ImmN = N->getOperand(N->getNumOperands()-1); 4932 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4933 IsUnary = true; 4934 break; 4935 case X86ISD::PSHUFHW: 4936 ImmN = N->getOperand(N->getNumOperands()-1); 4937 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4938 IsUnary = true; 4939 break; 4940 case X86ISD::PSHUFLW: 4941 ImmN = N->getOperand(N->getNumOperands()-1); 4942 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4943 IsUnary = true; 4944 break; 4945 case X86ISD::VPERMI: 4946 ImmN = N->getOperand(N->getNumOperands()-1); 4947 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4948 IsUnary = true; 4949 break; 4950 case X86ISD::MOVSS: 4951 case X86ISD::MOVSD: { 4952 // The index 0 always comes from the first element of the second source, 4953 // this is why MOVSS and MOVSD are used in the first place. The other 4954 // elements come from the other positions of the first source vector 4955 Mask.push_back(NumElems); 4956 for (unsigned i = 1; i != NumElems; ++i) { 4957 Mask.push_back(i); 4958 } 4959 break; 4960 } 4961 case X86ISD::VPERM2X128: 4962 ImmN = N->getOperand(N->getNumOperands()-1); 4963 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4964 if (Mask.empty()) return false; 4965 break; 4966 case X86ISD::MOVDDUP: 4967 case X86ISD::MOVLHPD: 4968 case X86ISD::MOVLPD: 4969 case X86ISD::MOVLPS: 4970 case X86ISD::MOVSHDUP: 4971 case X86ISD::MOVSLDUP: 4972 // Not yet implemented 4973 return false; 4974 default: llvm_unreachable("unknown target shuffle node"); 4975 } 4976 4977 return true; 4978} 4979 4980/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4981/// element of the result of the vector shuffle. 4982static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4983 unsigned Depth) { 4984 if (Depth == 6) 4985 return SDValue(); // Limit search depth. 4986 4987 SDValue V = SDValue(N, 0); 4988 EVT VT = V.getValueType(); 4989 unsigned Opcode = V.getOpcode(); 4990 4991 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4992 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4993 int Elt = SV->getMaskElt(Index); 4994 4995 if (Elt < 0) 4996 return DAG.getUNDEF(VT.getVectorElementType()); 4997 4998 unsigned NumElems = VT.getVectorNumElements(); 4999 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 5000 : SV->getOperand(1); 5001 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 5002 } 5003 5004 // Recurse into target specific vector shuffles to find scalars. 5005 if (isTargetShuffle(Opcode)) { 5006 MVT ShufVT = V.getSimpleValueType(); 5007 unsigned NumElems = ShufVT.getVectorNumElements(); 5008 SmallVector<int, 16> ShuffleMask; 5009 bool IsUnary; 5010 5011 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 5012 return SDValue(); 5013 5014 int Elt = ShuffleMask[Index]; 5015 if (Elt < 0) 5016 return DAG.getUNDEF(ShufVT.getVectorElementType()); 5017 5018 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 5019 : N->getOperand(1); 5020 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 5021 Depth+1); 5022 } 5023 5024 // Actual nodes that may contain scalar elements 5025 if (Opcode == ISD::BITCAST) { 5026 V = V.getOperand(0); 5027 EVT SrcVT = V.getValueType(); 5028 unsigned NumElems = VT.getVectorNumElements(); 5029 5030 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 5031 return SDValue(); 5032 } 5033 5034 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5035 return (Index == 0) ? V.getOperand(0) 5036 : DAG.getUNDEF(VT.getVectorElementType()); 5037 5038 if (V.getOpcode() == ISD::BUILD_VECTOR) 5039 return V.getOperand(Index); 5040 5041 return SDValue(); 5042} 5043 5044/// getNumOfConsecutiveZeros - Return the number of elements of a vector 5045/// shuffle operation which come from a consecutively from a zero. The 5046/// search can start in two different directions, from left or right. 5047/// We count undefs as zeros until PreferredNum is reached. 5048static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, 5049 unsigned NumElems, bool ZerosFromLeft, 5050 SelectionDAG &DAG, 5051 unsigned PreferredNum = -1U) { 5052 unsigned NumZeros = 0; 5053 for (unsigned i = 0; i != NumElems; ++i) { 5054 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1; 5055 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 5056 if (!Elt.getNode()) 5057 break; 5058 5059 if (X86::isZeroNode(Elt)) 5060 ++NumZeros; 5061 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum. 5062 NumZeros = std::min(NumZeros + 1, PreferredNum); 5063 else 5064 break; 5065 } 5066 5067 return NumZeros; 5068} 5069 5070/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 5071/// correspond consecutively to elements from one of the vector operands, 5072/// starting from its index OpIdx. Also tell OpNum which source vector operand. 5073static 5074bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 5075 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 5076 unsigned NumElems, unsigned &OpNum) { 5077 bool SeenV1 = false; 5078 bool SeenV2 = false; 5079 5080 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 5081 int Idx = SVOp->getMaskElt(i); 5082 // Ignore undef indicies 5083 if (Idx < 0) 5084 continue; 5085 5086 if (Idx < (int)NumElems) 5087 SeenV1 = true; 5088 else 5089 SeenV2 = true; 5090 5091 // Only accept consecutive elements from the same vector 5092 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 5093 return false; 5094 } 5095 5096 OpNum = SeenV1 ? 0 : 1; 5097 return true; 5098} 5099 5100/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 5101/// logical left shift of a vector. 5102static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 5103 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 5104 unsigned NumElems = 5105 SVOp->getSimpleValueType(0).getVectorNumElements(); 5106 unsigned NumZeros = getNumOfConsecutiveZeros( 5107 SVOp, NumElems, false /* check zeros from right */, DAG, 5108 SVOp->getMaskElt(0)); 5109 unsigned OpSrc; 5110 5111 if (!NumZeros) 5112 return false; 5113 5114 // Considering the elements in the mask that are not consecutive zeros, 5115 // check if they consecutively come from only one of the source vectors. 5116 // 5117 // V1 = {X, A, B, C} 0 5118 // \ \ \ / 5119 // vector_shuffle V1, V2 <1, 2, 3, X> 5120 // 5121 if (!isShuffleMaskConsecutive(SVOp, 5122 0, // Mask Start Index 5123 NumElems-NumZeros, // Mask End Index(exclusive) 5124 NumZeros, // Where to start looking in the src vector 5125 NumElems, // Number of elements in vector 5126 OpSrc)) // Which source operand ? 5127 return false; 5128 5129 isLeft = false; 5130 ShAmt = NumZeros; 5131 ShVal = SVOp->getOperand(OpSrc); 5132 return true; 5133} 5134 5135/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 5136/// logical left shift of a vector. 5137static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 5138 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 5139 unsigned NumElems = 5140 SVOp->getSimpleValueType(0).getVectorNumElements(); 5141 unsigned NumZeros = getNumOfConsecutiveZeros( 5142 SVOp, NumElems, true /* check zeros from left */, DAG, 5143 NumElems - SVOp->getMaskElt(NumElems - 1) - 1); 5144 unsigned OpSrc; 5145 5146 if (!NumZeros) 5147 return false; 5148 5149 // Considering the elements in the mask that are not consecutive zeros, 5150 // check if they consecutively come from only one of the source vectors. 5151 // 5152 // 0 { A, B, X, X } = V2 5153 // / \ / / 5154 // vector_shuffle V1, V2 <X, X, 4, 5> 5155 // 5156 if (!isShuffleMaskConsecutive(SVOp, 5157 NumZeros, // Mask Start Index 5158 NumElems, // Mask End Index(exclusive) 5159 0, // Where to start looking in the src vector 5160 NumElems, // Number of elements in vector 5161 OpSrc)) // Which source operand ? 5162 return false; 5163 5164 isLeft = true; 5165 ShAmt = NumZeros; 5166 ShVal = SVOp->getOperand(OpSrc); 5167 return true; 5168} 5169 5170/// isVectorShift - Returns true if the shuffle can be implemented as a 5171/// logical left or right shift of a vector. 5172static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 5173 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 5174 // Although the logic below support any bitwidth size, there are no 5175 // shift instructions which handle more than 128-bit vectors. 5176 if (!SVOp->getSimpleValueType(0).is128BitVector()) 5177 return false; 5178 5179 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 5180 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 5181 return true; 5182 5183 return false; 5184} 5185 5186/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 5187/// 5188static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 5189 unsigned NumNonZero, unsigned NumZero, 5190 SelectionDAG &DAG, 5191 const X86Subtarget* Subtarget, 5192 const TargetLowering &TLI) { 5193 if (NumNonZero > 8) 5194 return SDValue(); 5195 5196 SDLoc dl(Op); 5197 SDValue V(0, 0); 5198 bool First = true; 5199 for (unsigned i = 0; i < 16; ++i) { 5200 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 5201 if (ThisIsNonZero && First) { 5202 if (NumZero) 5203 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 5204 else 5205 V = DAG.getUNDEF(MVT::v8i16); 5206 First = false; 5207 } 5208 5209 if ((i & 1) != 0) { 5210 SDValue ThisElt(0, 0), LastElt(0, 0); 5211 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 5212 if (LastIsNonZero) { 5213 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 5214 MVT::i16, Op.getOperand(i-1)); 5215 } 5216 if (ThisIsNonZero) { 5217 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 5218 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 5219 ThisElt, DAG.getConstant(8, MVT::i8)); 5220 if (LastIsNonZero) 5221 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 5222 } else 5223 ThisElt = LastElt; 5224 5225 if (ThisElt.getNode()) 5226 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 5227 DAG.getIntPtrConstant(i/2)); 5228 } 5229 } 5230 5231 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 5232} 5233 5234/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 5235/// 5236static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 5237 unsigned NumNonZero, unsigned NumZero, 5238 SelectionDAG &DAG, 5239 const X86Subtarget* Subtarget, 5240 const TargetLowering &TLI) { 5241 if (NumNonZero > 4) 5242 return SDValue(); 5243 5244 SDLoc dl(Op); 5245 SDValue V(0, 0); 5246 bool First = true; 5247 for (unsigned i = 0; i < 8; ++i) { 5248 bool isNonZero = (NonZeros & (1 << i)) != 0; 5249 if (isNonZero) { 5250 if (First) { 5251 if (NumZero) 5252 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 5253 else 5254 V = DAG.getUNDEF(MVT::v8i16); 5255 First = false; 5256 } 5257 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 5258 MVT::v8i16, V, Op.getOperand(i), 5259 DAG.getIntPtrConstant(i)); 5260 } 5261 } 5262 5263 return V; 5264} 5265 5266/// getVShift - Return a vector logical shift node. 5267/// 5268static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 5269 unsigned NumBits, SelectionDAG &DAG, 5270 const TargetLowering &TLI, SDLoc dl) { 5271 assert(VT.is128BitVector() && "Unknown type for VShift"); 5272 EVT ShVT = MVT::v2i64; 5273 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 5274 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 5275 return DAG.getNode(ISD::BITCAST, dl, VT, 5276 DAG.getNode(Opc, dl, ShVT, SrcOp, 5277 DAG.getConstant(NumBits, 5278 TLI.getScalarShiftAmountTy(SrcOp.getValueType())))); 5279} 5280 5281static SDValue 5282LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) { 5283 5284 // Check if the scalar load can be widened into a vector load. And if 5285 // the address is "base + cst" see if the cst can be "absorbed" into 5286 // the shuffle mask. 5287 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 5288 SDValue Ptr = LD->getBasePtr(); 5289 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 5290 return SDValue(); 5291 EVT PVT = LD->getValueType(0); 5292 if (PVT != MVT::i32 && PVT != MVT::f32) 5293 return SDValue(); 5294 5295 int FI = -1; 5296 int64_t Offset = 0; 5297 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 5298 FI = FINode->getIndex(); 5299 Offset = 0; 5300 } else if (DAG.isBaseWithConstantOffset(Ptr) && 5301 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 5302 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 5303 Offset = Ptr.getConstantOperandVal(1); 5304 Ptr = Ptr.getOperand(0); 5305 } else { 5306 return SDValue(); 5307 } 5308 5309 // FIXME: 256-bit vector instructions don't require a strict alignment, 5310 // improve this code to support it better. 5311 unsigned RequiredAlign = VT.getSizeInBits()/8; 5312 SDValue Chain = LD->getChain(); 5313 // Make sure the stack object alignment is at least 16 or 32. 5314 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5315 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 5316 if (MFI->isFixedObjectIndex(FI)) { 5317 // Can't change the alignment. FIXME: It's possible to compute 5318 // the exact stack offset and reference FI + adjust offset instead. 5319 // If someone *really* cares about this. That's the way to implement it. 5320 return SDValue(); 5321 } else { 5322 MFI->setObjectAlignment(FI, RequiredAlign); 5323 } 5324 } 5325 5326 // (Offset % 16 or 32) must be multiple of 4. Then address is then 5327 // Ptr + (Offset & ~15). 5328 if (Offset < 0) 5329 return SDValue(); 5330 if ((Offset % RequiredAlign) & 3) 5331 return SDValue(); 5332 int64_t StartOffset = Offset & ~(RequiredAlign-1); 5333 if (StartOffset) 5334 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(), 5335 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 5336 5337 int EltNo = (Offset - StartOffset) >> 2; 5338 unsigned NumElems = VT.getVectorNumElements(); 5339 5340 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 5341 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 5342 LD->getPointerInfo().getWithOffset(StartOffset), 5343 false, false, false, 0); 5344 5345 SmallVector<int, 8> Mask; 5346 for (unsigned i = 0; i != NumElems; ++i) 5347 Mask.push_back(EltNo); 5348 5349 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 5350 } 5351 5352 return SDValue(); 5353} 5354 5355/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 5356/// vector of type 'VT', see if the elements can be replaced by a single large 5357/// load which has the same value as a build_vector whose operands are 'elts'. 5358/// 5359/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 5360/// 5361/// FIXME: we'd also like to handle the case where the last elements are zero 5362/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 5363/// There's even a handy isZeroNode for that purpose. 5364static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 5365 SDLoc &DL, SelectionDAG &DAG) { 5366 EVT EltVT = VT.getVectorElementType(); 5367 unsigned NumElems = Elts.size(); 5368 5369 LoadSDNode *LDBase = NULL; 5370 unsigned LastLoadedElt = -1U; 5371 5372 // For each element in the initializer, see if we've found a load or an undef. 5373 // If we don't find an initial load element, or later load elements are 5374 // non-consecutive, bail out. 5375 for (unsigned i = 0; i < NumElems; ++i) { 5376 SDValue Elt = Elts[i]; 5377 5378 if (!Elt.getNode() || 5379 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5380 return SDValue(); 5381 if (!LDBase) { 5382 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5383 return SDValue(); 5384 LDBase = cast<LoadSDNode>(Elt.getNode()); 5385 LastLoadedElt = i; 5386 continue; 5387 } 5388 if (Elt.getOpcode() == ISD::UNDEF) 5389 continue; 5390 5391 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5392 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5393 return SDValue(); 5394 LastLoadedElt = i; 5395 } 5396 5397 // If we have found an entire vector of loads and undefs, then return a large 5398 // load of the entire vector width starting at the base pointer. If we found 5399 // consecutive loads for the low half, generate a vzext_load node. 5400 if (LastLoadedElt == NumElems - 1) { 5401 SDValue NewLd = SDValue(); 5402 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5403 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5404 LDBase->getPointerInfo(), 5405 LDBase->isVolatile(), LDBase->isNonTemporal(), 5406 LDBase->isInvariant(), 0); 5407 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5408 LDBase->getPointerInfo(), 5409 LDBase->isVolatile(), LDBase->isNonTemporal(), 5410 LDBase->isInvariant(), LDBase->getAlignment()); 5411 5412 if (LDBase->hasAnyUseOfValue(1)) { 5413 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 5414 SDValue(LDBase, 1), 5415 SDValue(NewLd.getNode(), 1)); 5416 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain); 5417 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1), 5418 SDValue(NewLd.getNode(), 1)); 5419 } 5420 5421 return NewLd; 5422 } 5423 if (NumElems == 4 && LastLoadedElt == 1 && 5424 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5425 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5426 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5427 SDValue ResNode = 5428 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 5429 array_lengthof(Ops), MVT::i64, 5430 LDBase->getPointerInfo(), 5431 LDBase->getAlignment(), 5432 false/*isVolatile*/, true/*ReadMem*/, 5433 false/*WriteMem*/); 5434 5435 // Make sure the newly-created LOAD is in the same position as LDBase in 5436 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and 5437 // update uses of LDBase's output chain to use the TokenFactor. 5438 if (LDBase->hasAnyUseOfValue(1)) { 5439 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 5440 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1)); 5441 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain); 5442 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1), 5443 SDValue(ResNode.getNode(), 1)); 5444 } 5445 5446 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5447 } 5448 return SDValue(); 5449} 5450 5451/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 5452/// to generate a splat value for the following cases: 5453/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 5454/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5455/// a scalar load, or a constant. 5456/// The VBROADCAST node is returned when a pattern is found, 5457/// or SDValue() otherwise. 5458static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget, 5459 SelectionDAG &DAG) { 5460 if (!Subtarget->hasFp256()) 5461 return SDValue(); 5462 5463 MVT VT = Op.getSimpleValueType(); 5464 SDLoc dl(Op); 5465 5466 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && 5467 "Unsupported vector type for broadcast."); 5468 5469 SDValue Ld; 5470 bool ConstSplatVal; 5471 5472 switch (Op.getOpcode()) { 5473 default: 5474 // Unknown pattern found. 5475 return SDValue(); 5476 5477 case ISD::BUILD_VECTOR: { 5478 // The BUILD_VECTOR node must be a splat. 5479 if (!isSplatVector(Op.getNode())) 5480 return SDValue(); 5481 5482 Ld = Op.getOperand(0); 5483 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5484 Ld.getOpcode() == ISD::ConstantFP); 5485 5486 // The suspected load node has several users. Make sure that all 5487 // of its users are from the BUILD_VECTOR node. 5488 // Constants may have multiple users. 5489 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5490 return SDValue(); 5491 break; 5492 } 5493 5494 case ISD::VECTOR_SHUFFLE: { 5495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5496 5497 // Shuffles must have a splat mask where the first element is 5498 // broadcasted. 5499 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5500 return SDValue(); 5501 5502 SDValue Sc = Op.getOperand(0); 5503 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 5504 Sc.getOpcode() != ISD::BUILD_VECTOR) { 5505 5506 if (!Subtarget->hasInt256()) 5507 return SDValue(); 5508 5509 // Use the register form of the broadcast instruction available on AVX2. 5510 if (VT.getSizeInBits() >= 256) 5511 Sc = Extract128BitVector(Sc, 0, DAG, dl); 5512 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc); 5513 } 5514 5515 Ld = Sc.getOperand(0); 5516 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5517 Ld.getOpcode() == ISD::ConstantFP); 5518 5519 // The scalar_to_vector node and the suspected 5520 // load node must have exactly one user. 5521 // Constants may have multiple users. 5522 5523 // AVX-512 has register version of the broadcast 5524 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() && 5525 Ld.getValueType().getSizeInBits() >= 32; 5526 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) && 5527 !hasRegVer)) 5528 return SDValue(); 5529 break; 5530 } 5531 } 5532 5533 bool IsGE256 = (VT.getSizeInBits() >= 256); 5534 5535 // Handle the broadcasting a single constant scalar from the constant pool 5536 // into a vector. On Sandybridge it is still better to load a constant vector 5537 // from the constant pool and not to broadcast it from a scalar. 5538 if (ConstSplatVal && Subtarget->hasInt256()) { 5539 EVT CVT = Ld.getValueType(); 5540 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5541 unsigned ScalarSize = CVT.getSizeInBits(); 5542 5543 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) { 5544 const Constant *C = 0; 5545 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5546 C = CI->getConstantIntValue(); 5547 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5548 C = CF->getConstantFPValue(); 5549 5550 assert(C && "Invalid constant type"); 5551 5552 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5553 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy()); 5554 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5555 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5556 MachinePointerInfo::getConstantPool(), 5557 false, false, false, Alignment); 5558 5559 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5560 } 5561 } 5562 5563 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); 5564 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5565 5566 // Handle AVX2 in-register broadcasts. 5567 if (!IsLoad && Subtarget->hasInt256() && 5568 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))) 5569 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5570 5571 // The scalar source must be a normal load. 5572 if (!IsLoad) 5573 return SDValue(); 5574 5575 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) 5576 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5577 5578 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5579 // double since there is no vbroadcastsd xmm 5580 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) { 5581 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5582 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5583 } 5584 5585 // Unsupported broadcast. 5586 return SDValue(); 5587} 5588 5589static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) { 5590 MVT VT = Op.getSimpleValueType(); 5591 5592 // Skip if insert_vec_elt is not supported. 5593 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5594 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) 5595 return SDValue(); 5596 5597 SDLoc DL(Op); 5598 unsigned NumElems = Op.getNumOperands(); 5599 5600 SDValue VecIn1; 5601 SDValue VecIn2; 5602 SmallVector<unsigned, 4> InsertIndices; 5603 SmallVector<int, 8> Mask(NumElems, -1); 5604 5605 for (unsigned i = 0; i != NumElems; ++i) { 5606 unsigned Opc = Op.getOperand(i).getOpcode(); 5607 5608 if (Opc == ISD::UNDEF) 5609 continue; 5610 5611 if (Opc != ISD::EXTRACT_VECTOR_ELT) { 5612 // Quit if more than 1 elements need inserting. 5613 if (InsertIndices.size() > 1) 5614 return SDValue(); 5615 5616 InsertIndices.push_back(i); 5617 continue; 5618 } 5619 5620 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0); 5621 SDValue ExtIdx = Op.getOperand(i).getOperand(1); 5622 5623 // Quit if extracted from vector of different type. 5624 if (ExtractedFromVec.getValueType() != VT) 5625 return SDValue(); 5626 5627 // Quit if non-constant index. 5628 if (!isa<ConstantSDNode>(ExtIdx)) 5629 return SDValue(); 5630 5631 if (VecIn1.getNode() == 0) 5632 VecIn1 = ExtractedFromVec; 5633 else if (VecIn1 != ExtractedFromVec) { 5634 if (VecIn2.getNode() == 0) 5635 VecIn2 = ExtractedFromVec; 5636 else if (VecIn2 != ExtractedFromVec) 5637 // Quit if more than 2 vectors to shuffle 5638 return SDValue(); 5639 } 5640 5641 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue(); 5642 5643 if (ExtractedFromVec == VecIn1) 5644 Mask[i] = Idx; 5645 else if (ExtractedFromVec == VecIn2) 5646 Mask[i] = Idx + NumElems; 5647 } 5648 5649 if (VecIn1.getNode() == 0) 5650 return SDValue(); 5651 5652 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5653 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]); 5654 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) { 5655 unsigned Idx = InsertIndices[i]; 5656 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx), 5657 DAG.getIntPtrConstant(Idx)); 5658 } 5659 5660 return NV; 5661} 5662 5663// Lower BUILD_VECTOR operation for v8i1 and v16i1 types. 5664SDValue 5665X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const { 5666 5667 MVT VT = Op.getSimpleValueType(); 5668 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) && 5669 "Unexpected type in LowerBUILD_VECTORvXi1!"); 5670 5671 SDLoc dl(Op); 5672 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5673 SDValue Cst = DAG.getTargetConstant(0, MVT::i1); 5674 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst, 5675 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 5676 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, 5677 Ops, VT.getVectorNumElements()); 5678 } 5679 5680 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5681 SDValue Cst = DAG.getTargetConstant(1, MVT::i1); 5682 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst, 5683 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 5684 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, 5685 Ops, VT.getVectorNumElements()); 5686 } 5687 5688 bool AllContants = true; 5689 uint64_t Immediate = 0; 5690 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) { 5691 SDValue In = Op.getOperand(idx); 5692 if (In.getOpcode() == ISD::UNDEF) 5693 continue; 5694 if (!isa<ConstantSDNode>(In)) { 5695 AllContants = false; 5696 break; 5697 } 5698 if (cast<ConstantSDNode>(In)->getZExtValue()) 5699 Immediate |= (1ULL << idx); 5700 } 5701 5702 if (AllContants) { 5703 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, 5704 DAG.getConstant(Immediate, MVT::i16)); 5705 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask, 5706 DAG.getIntPtrConstant(0)); 5707 } 5708 5709 // Splat vector (with undefs) 5710 SDValue In = Op.getOperand(0); 5711 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) { 5712 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF) 5713 llvm_unreachable("Unsupported predicate operation"); 5714 } 5715 5716 SDValue EFLAGS, X86CC; 5717 if (In.getOpcode() == ISD::SETCC) { 5718 SDValue Op0 = In.getOperand(0); 5719 SDValue Op1 = In.getOperand(1); 5720 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get(); 5721 bool isFP = Op1.getValueType().isFloatingPoint(); 5722 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5723 5724 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation"); 5725 5726 X86CC = DAG.getConstant(X86CCVal, MVT::i8); 5727 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG); 5728 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 5729 } else if (In.getOpcode() == X86ISD::SETCC) { 5730 X86CC = In.getOperand(0); 5731 EFLAGS = In.getOperand(1); 5732 } else { 5733 // The algorithm: 5734 // Bit1 = In & 0x1 5735 // if (Bit1 != 0) 5736 // ZF = 0 5737 // else 5738 // ZF = 1 5739 // if (ZF == 0) 5740 // res = allOnes ### CMOVNE -1, %res 5741 // else 5742 // res = allZero 5743 MVT InVT = In.getSimpleValueType(); 5744 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT)); 5745 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG); 5746 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5747 } 5748 5749 if (VT == MVT::v16i1) { 5750 SDValue Cst1 = DAG.getConstant(-1, MVT::i16); 5751 SDValue Cst0 = DAG.getConstant(0, MVT::i16); 5752 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16, 5753 Cst0, Cst1, X86CC, EFLAGS); 5754 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp); 5755 } 5756 5757 if (VT == MVT::v8i1) { 5758 SDValue Cst1 = DAG.getConstant(-1, MVT::i32); 5759 SDValue Cst0 = DAG.getConstant(0, MVT::i32); 5760 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32, 5761 Cst0, Cst1, X86CC, EFLAGS); 5762 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp); 5763 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp); 5764 } 5765 llvm_unreachable("Unsupported predicate operation"); 5766} 5767 5768SDValue 5769X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5770 SDLoc dl(Op); 5771 5772 MVT VT = Op.getSimpleValueType(); 5773 MVT ExtVT = VT.getVectorElementType(); 5774 unsigned NumElems = Op.getNumOperands(); 5775 5776 // Generate vectors for predicate vectors. 5777 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512()) 5778 return LowerBUILD_VECTORvXi1(Op, DAG); 5779 5780 // Vectors containing all zeros can be matched by pxor and xorps later 5781 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5782 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5783 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5784 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) 5785 return Op; 5786 5787 return getZeroVector(VT, Subtarget, DAG, dl); 5788 } 5789 5790 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5791 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5792 // vpcmpeqd on 256-bit vectors. 5793 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) { 5794 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256())) 5795 return Op; 5796 5797 if (!VT.is512BitVector()) 5798 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl); 5799 } 5800 5801 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG); 5802 if (Broadcast.getNode()) 5803 return Broadcast; 5804 5805 unsigned EVTBits = ExtVT.getSizeInBits(); 5806 5807 unsigned NumZero = 0; 5808 unsigned NumNonZero = 0; 5809 unsigned NonZeros = 0; 5810 bool IsAllConstants = true; 5811 SmallSet<SDValue, 8> Values; 5812 for (unsigned i = 0; i < NumElems; ++i) { 5813 SDValue Elt = Op.getOperand(i); 5814 if (Elt.getOpcode() == ISD::UNDEF) 5815 continue; 5816 Values.insert(Elt); 5817 if (Elt.getOpcode() != ISD::Constant && 5818 Elt.getOpcode() != ISD::ConstantFP) 5819 IsAllConstants = false; 5820 if (X86::isZeroNode(Elt)) 5821 NumZero++; 5822 else { 5823 NonZeros |= (1 << i); 5824 NumNonZero++; 5825 } 5826 } 5827 5828 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5829 if (NumNonZero == 0) 5830 return DAG.getUNDEF(VT); 5831 5832 // Special case for single non-zero, non-undef, element. 5833 if (NumNonZero == 1) { 5834 unsigned Idx = countTrailingZeros(NonZeros); 5835 SDValue Item = Op.getOperand(Idx); 5836 5837 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5838 // the value are obviously zero, truncate the value to i32 and do the 5839 // insertion that way. Only do this if the value is non-constant or if the 5840 // value is a constant being inserted into element 0. It is cheaper to do 5841 // a constant pool load than it is to do a movd + shuffle. 5842 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5843 (!IsAllConstants || Idx == 0)) { 5844 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5845 // Handle SSE only. 5846 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5847 EVT VecVT = MVT::v4i32; 5848 unsigned VecElts = 4; 5849 5850 // Truncate the value (which may itself be a constant) to i32, and 5851 // convert it to a vector with movd (S2V+shuffle to zero extend). 5852 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5853 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5854 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5855 5856 // Now we have our 32-bit value zero extended in the low element of 5857 // a vector. If Idx != 0, swizzle it into place. 5858 if (Idx != 0) { 5859 SmallVector<int, 4> Mask; 5860 Mask.push_back(Idx); 5861 for (unsigned i = 1; i != VecElts; ++i) 5862 Mask.push_back(i); 5863 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5864 &Mask[0]); 5865 } 5866 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5867 } 5868 } 5869 5870 // If we have a constant or non-constant insertion into the low element of 5871 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5872 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5873 // depending on what the source datatype is. 5874 if (Idx == 0) { 5875 if (NumZero == 0) 5876 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5877 5878 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5879 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5880 if (VT.is256BitVector() || VT.is512BitVector()) { 5881 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5882 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5883 Item, DAG.getIntPtrConstant(0)); 5884 } 5885 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5886 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5887 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5888 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5889 } 5890 5891 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5892 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5893 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5894 if (VT.is256BitVector()) { 5895 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5896 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5897 } else { 5898 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5899 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5900 } 5901 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5902 } 5903 } 5904 5905 // Is it a vector logical left shift? 5906 if (NumElems == 2 && Idx == 1 && 5907 X86::isZeroNode(Op.getOperand(0)) && 5908 !X86::isZeroNode(Op.getOperand(1))) { 5909 unsigned NumBits = VT.getSizeInBits(); 5910 return getVShift(true, VT, 5911 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5912 VT, Op.getOperand(1)), 5913 NumBits/2, DAG, *this, dl); 5914 } 5915 5916 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5917 return SDValue(); 5918 5919 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5920 // is a non-constant being inserted into an element other than the low one, 5921 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5922 // movd/movss) to move this into the low element, then shuffle it into 5923 // place. 5924 if (EVTBits == 32) { 5925 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5926 5927 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5928 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5929 SmallVector<int, 8> MaskVec; 5930 for (unsigned i = 0; i != NumElems; ++i) 5931 MaskVec.push_back(i == Idx ? 0 : 1); 5932 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5933 } 5934 } 5935 5936 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5937 if (Values.size() == 1) { 5938 if (EVTBits == 32) { 5939 // Instead of a shuffle like this: 5940 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5941 // Check if it's possible to issue this instead. 5942 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5943 unsigned Idx = countTrailingZeros(NonZeros); 5944 SDValue Item = Op.getOperand(Idx); 5945 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5946 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5947 } 5948 return SDValue(); 5949 } 5950 5951 // A vector full of immediates; various special cases are already 5952 // handled, so this is best done with a single constant-pool load. 5953 if (IsAllConstants) 5954 return SDValue(); 5955 5956 // For AVX-length vectors, build the individual 128-bit pieces and use 5957 // shuffles to put them in place. 5958 if (VT.is256BitVector()) { 5959 SmallVector<SDValue, 32> V; 5960 for (unsigned i = 0; i != NumElems; ++i) 5961 V.push_back(Op.getOperand(i)); 5962 5963 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5964 5965 // Build both the lower and upper subvector. 5966 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5967 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5968 NumElems/2); 5969 5970 // Recreate the wider vector with the lower and upper part. 5971 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5972 } 5973 5974 // Let legalizer expand 2-wide build_vectors. 5975 if (EVTBits == 64) { 5976 if (NumNonZero == 1) { 5977 // One half is zero or undef. 5978 unsigned Idx = countTrailingZeros(NonZeros); 5979 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5980 Op.getOperand(Idx)); 5981 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5982 } 5983 return SDValue(); 5984 } 5985 5986 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5987 if (EVTBits == 8 && NumElems == 16) { 5988 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5989 Subtarget, *this); 5990 if (V.getNode()) return V; 5991 } 5992 5993 if (EVTBits == 16 && NumElems == 8) { 5994 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5995 Subtarget, *this); 5996 if (V.getNode()) return V; 5997 } 5998 5999 // If element VT is == 32 bits, turn it into a number of shuffles. 6000 SmallVector<SDValue, 8> V(NumElems); 6001 if (NumElems == 4 && NumZero > 0) { 6002 for (unsigned i = 0; i < 4; ++i) { 6003 bool isZero = !(NonZeros & (1 << i)); 6004 if (isZero) 6005 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 6006 else 6007 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 6008 } 6009 6010 for (unsigned i = 0; i < 2; ++i) { 6011 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 6012 default: break; 6013 case 0: 6014 V[i] = V[i*2]; // Must be a zero vector. 6015 break; 6016 case 1: 6017 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 6018 break; 6019 case 2: 6020 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 6021 break; 6022 case 3: 6023 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 6024 break; 6025 } 6026 } 6027 6028 bool Reverse1 = (NonZeros & 0x3) == 2; 6029 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 6030 int MaskVec[] = { 6031 Reverse1 ? 1 : 0, 6032 Reverse1 ? 0 : 1, 6033 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 6034 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 6035 }; 6036 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 6037 } 6038 6039 if (Values.size() > 1 && VT.is128BitVector()) { 6040 // Check for a build vector of consecutive loads. 6041 for (unsigned i = 0; i < NumElems; ++i) 6042 V[i] = Op.getOperand(i); 6043 6044 // Check for elements which are consecutive loads. 6045 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 6046 if (LD.getNode()) 6047 return LD; 6048 6049 // Check for a build vector from mostly shuffle plus few inserting. 6050 SDValue Sh = buildFromShuffleMostly(Op, DAG); 6051 if (Sh.getNode()) 6052 return Sh; 6053 6054 // For SSE 4.1, use insertps to put the high elements into the low element. 6055 if (getSubtarget()->hasSSE41()) { 6056 SDValue Result; 6057 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 6058 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 6059 else 6060 Result = DAG.getUNDEF(VT); 6061 6062 for (unsigned i = 1; i < NumElems; ++i) { 6063 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 6064 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 6065 Op.getOperand(i), DAG.getIntPtrConstant(i)); 6066 } 6067 return Result; 6068 } 6069 6070 // Otherwise, expand into a number of unpckl*, start by extending each of 6071 // our (non-undef) elements to the full vector width with the element in the 6072 // bottom slot of the vector (which generates no code for SSE). 6073 for (unsigned i = 0; i < NumElems; ++i) { 6074 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 6075 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 6076 else 6077 V[i] = DAG.getUNDEF(VT); 6078 } 6079 6080 // Next, we iteratively mix elements, e.g. for v4f32: 6081 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 6082 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 6083 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 6084 unsigned EltStride = NumElems >> 1; 6085 while (EltStride != 0) { 6086 for (unsigned i = 0; i < EltStride; ++i) { 6087 // If V[i+EltStride] is undef and this is the first round of mixing, 6088 // then it is safe to just drop this shuffle: V[i] is already in the 6089 // right place, the one element (since it's the first round) being 6090 // inserted as undef can be dropped. This isn't safe for successive 6091 // rounds because they will permute elements within both vectors. 6092 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 6093 EltStride == NumElems/2) 6094 continue; 6095 6096 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 6097 } 6098 EltStride >>= 1; 6099 } 6100 return V[0]; 6101 } 6102 return SDValue(); 6103} 6104 6105// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 6106// to create 256-bit vectors from two other 128-bit ones. 6107static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 6108 SDLoc dl(Op); 6109 MVT ResVT = Op.getSimpleValueType(); 6110 6111 assert((ResVT.is256BitVector() || 6112 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); 6113 6114 SDValue V1 = Op.getOperand(0); 6115 SDValue V2 = Op.getOperand(1); 6116 unsigned NumElems = ResVT.getVectorNumElements(); 6117 if(ResVT.is256BitVector()) 6118 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 6119 6120 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 6121} 6122 6123static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 6124 assert(Op.getNumOperands() == 2); 6125 6126 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors 6127 // from two other 128-bit ones. 6128 return LowerAVXCONCAT_VECTORS(Op, DAG); 6129} 6130 6131// Try to lower a shuffle node into a simple blend instruction. 6132static SDValue 6133LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 6134 const X86Subtarget *Subtarget, SelectionDAG &DAG) { 6135 SDValue V1 = SVOp->getOperand(0); 6136 SDValue V2 = SVOp->getOperand(1); 6137 SDLoc dl(SVOp); 6138 MVT VT = SVOp->getSimpleValueType(0); 6139 MVT EltVT = VT.getVectorElementType(); 6140 unsigned NumElems = VT.getVectorNumElements(); 6141 6142 // There is no blend with immediate in AVX-512. 6143 if (VT.is512BitVector()) 6144 return SDValue(); 6145 6146 if (!Subtarget->hasSSE41() || EltVT == MVT::i8) 6147 return SDValue(); 6148 if (!Subtarget->hasInt256() && VT == MVT::v16i16) 6149 return SDValue(); 6150 6151 // Check the mask for BLEND and build the value. 6152 unsigned MaskValue = 0; 6153 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise. 6154 unsigned NumLanes = (NumElems-1)/8 + 1; 6155 unsigned NumElemsInLane = NumElems / NumLanes; 6156 6157 // Blend for v16i16 should be symetric for the both lanes. 6158 for (unsigned i = 0; i < NumElemsInLane; ++i) { 6159 6160 int SndLaneEltIdx = (NumLanes == 2) ? 6161 SVOp->getMaskElt(i + NumElemsInLane) : -1; 6162 int EltIdx = SVOp->getMaskElt(i); 6163 6164 if ((EltIdx < 0 || EltIdx == (int)i) && 6165 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane))) 6166 continue; 6167 6168 if (((unsigned)EltIdx == (i + NumElems)) && 6169 (SndLaneEltIdx < 0 || 6170 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane)) 6171 MaskValue |= (1<<i); 6172 else 6173 return SDValue(); 6174 } 6175 6176 // Convert i32 vectors to floating point if it is not AVX2. 6177 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors. 6178 MVT BlendVT = VT; 6179 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) { 6180 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()), 6181 NumElems); 6182 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1); 6183 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2); 6184 } 6185 6186 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2, 6187 DAG.getConstant(MaskValue, MVT::i32)); 6188 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 6189} 6190 6191// v8i16 shuffles - Prefer shuffles in the following order: 6192// 1. [all] pshuflw, pshufhw, optional move 6193// 2. [ssse3] 1 x pshufb 6194// 3. [ssse3] 2 x pshufb + 1 x por 6195// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 6196static SDValue 6197LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, 6198 SelectionDAG &DAG) { 6199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6200 SDValue V1 = SVOp->getOperand(0); 6201 SDValue V2 = SVOp->getOperand(1); 6202 SDLoc dl(SVOp); 6203 SmallVector<int, 8> MaskVals; 6204 6205 // Determine if more than 1 of the words in each of the low and high quadwords 6206 // of the result come from the same quadword of one of the two inputs. Undef 6207 // mask values count as coming from any quadword, for better codegen. 6208 unsigned LoQuad[] = { 0, 0, 0, 0 }; 6209 unsigned HiQuad[] = { 0, 0, 0, 0 }; 6210 std::bitset<4> InputQuads; 6211 for (unsigned i = 0; i < 8; ++i) { 6212 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 6213 int EltIdx = SVOp->getMaskElt(i); 6214 MaskVals.push_back(EltIdx); 6215 if (EltIdx < 0) { 6216 ++Quad[0]; 6217 ++Quad[1]; 6218 ++Quad[2]; 6219 ++Quad[3]; 6220 continue; 6221 } 6222 ++Quad[EltIdx / 4]; 6223 InputQuads.set(EltIdx / 4); 6224 } 6225 6226 int BestLoQuad = -1; 6227 unsigned MaxQuad = 1; 6228 for (unsigned i = 0; i < 4; ++i) { 6229 if (LoQuad[i] > MaxQuad) { 6230 BestLoQuad = i; 6231 MaxQuad = LoQuad[i]; 6232 } 6233 } 6234 6235 int BestHiQuad = -1; 6236 MaxQuad = 1; 6237 for (unsigned i = 0; i < 4; ++i) { 6238 if (HiQuad[i] > MaxQuad) { 6239 BestHiQuad = i; 6240 MaxQuad = HiQuad[i]; 6241 } 6242 } 6243 6244 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 6245 // of the two input vectors, shuffle them into one input vector so only a 6246 // single pshufb instruction is necessary. If There are more than 2 input 6247 // quads, disable the next transformation since it does not help SSSE3. 6248 bool V1Used = InputQuads[0] || InputQuads[1]; 6249 bool V2Used = InputQuads[2] || InputQuads[3]; 6250 if (Subtarget->hasSSSE3()) { 6251 if (InputQuads.count() == 2 && V1Used && V2Used) { 6252 BestLoQuad = InputQuads[0] ? 0 : 1; 6253 BestHiQuad = InputQuads[2] ? 2 : 3; 6254 } 6255 if (InputQuads.count() > 2) { 6256 BestLoQuad = -1; 6257 BestHiQuad = -1; 6258 } 6259 } 6260 6261 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 6262 // the shuffle mask. If a quad is scored as -1, that means that it contains 6263 // words from all 4 input quadwords. 6264 SDValue NewV; 6265 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 6266 int MaskV[] = { 6267 BestLoQuad < 0 ? 0 : BestLoQuad, 6268 BestHiQuad < 0 ? 1 : BestHiQuad 6269 }; 6270 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 6271 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 6272 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 6273 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 6274 6275 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 6276 // source words for the shuffle, to aid later transformations. 6277 bool AllWordsInNewV = true; 6278 bool InOrder[2] = { true, true }; 6279 for (unsigned i = 0; i != 8; ++i) { 6280 int idx = MaskVals[i]; 6281 if (idx != (int)i) 6282 InOrder[i/4] = false; 6283 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 6284 continue; 6285 AllWordsInNewV = false; 6286 break; 6287 } 6288 6289 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 6290 if (AllWordsInNewV) { 6291 for (int i = 0; i != 8; ++i) { 6292 int idx = MaskVals[i]; 6293 if (idx < 0) 6294 continue; 6295 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 6296 if ((idx != i) && idx < 4) 6297 pshufhw = false; 6298 if ((idx != i) && idx > 3) 6299 pshuflw = false; 6300 } 6301 V1 = NewV; 6302 V2Used = false; 6303 BestLoQuad = 0; 6304 BestHiQuad = 1; 6305 } 6306 6307 // If we've eliminated the use of V2, and the new mask is a pshuflw or 6308 // pshufhw, that's as cheap as it gets. Return the new shuffle. 6309 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 6310 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 6311 unsigned TargetMask = 0; 6312 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 6313 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 6314 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 6315 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 6316 getShufflePSHUFLWImmediate(SVOp); 6317 V1 = NewV.getOperand(0); 6318 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 6319 } 6320 } 6321 6322 // Promote splats to a larger type which usually leads to more efficient code. 6323 // FIXME: Is this true if pshufb is available? 6324 if (SVOp->isSplat()) 6325 return PromoteSplat(SVOp, DAG); 6326 6327 // If we have SSSE3, and all words of the result are from 1 input vector, 6328 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 6329 // is present, fall back to case 4. 6330 if (Subtarget->hasSSSE3()) { 6331 SmallVector<SDValue,16> pshufbMask; 6332 6333 // If we have elements from both input vectors, set the high bit of the 6334 // shuffle mask element to zero out elements that come from V2 in the V1 6335 // mask, and elements that come from V1 in the V2 mask, so that the two 6336 // results can be OR'd together. 6337 bool TwoInputs = V1Used && V2Used; 6338 for (unsigned i = 0; i != 8; ++i) { 6339 int EltIdx = MaskVals[i] * 2; 6340 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx; 6341 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1; 6342 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 6343 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 6344 } 6345 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 6346 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 6347 DAG.getNode(ISD::BUILD_VECTOR, dl, 6348 MVT::v16i8, &pshufbMask[0], 16)); 6349 if (!TwoInputs) 6350 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 6351 6352 // Calculate the shuffle mask for the second input, shuffle it, and 6353 // OR it with the first shuffled input. 6354 pshufbMask.clear(); 6355 for (unsigned i = 0; i != 8; ++i) { 6356 int EltIdx = MaskVals[i] * 2; 6357 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16; 6358 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15; 6359 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 6360 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 6361 } 6362 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 6363 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 6364 DAG.getNode(ISD::BUILD_VECTOR, dl, 6365 MVT::v16i8, &pshufbMask[0], 16)); 6366 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 6367 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 6368 } 6369 6370 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 6371 // and update MaskVals with new element order. 6372 std::bitset<8> InOrder; 6373 if (BestLoQuad >= 0) { 6374 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 6375 for (int i = 0; i != 4; ++i) { 6376 int idx = MaskVals[i]; 6377 if (idx < 0) { 6378 InOrder.set(i); 6379 } else if ((idx / 4) == BestLoQuad) { 6380 MaskV[i] = idx & 3; 6381 InOrder.set(i); 6382 } 6383 } 6384 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 6385 &MaskV[0]); 6386 6387 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 6388 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 6389 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 6390 NewV.getOperand(0), 6391 getShufflePSHUFLWImmediate(SVOp), DAG); 6392 } 6393 } 6394 6395 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 6396 // and update MaskVals with the new element order. 6397 if (BestHiQuad >= 0) { 6398 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 6399 for (unsigned i = 4; i != 8; ++i) { 6400 int idx = MaskVals[i]; 6401 if (idx < 0) { 6402 InOrder.set(i); 6403 } else if ((idx / 4) == BestHiQuad) { 6404 MaskV[i] = (idx & 3) + 4; 6405 InOrder.set(i); 6406 } 6407 } 6408 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 6409 &MaskV[0]); 6410 6411 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 6412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 6413 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 6414 NewV.getOperand(0), 6415 getShufflePSHUFHWImmediate(SVOp), DAG); 6416 } 6417 } 6418 6419 // In case BestHi & BestLo were both -1, which means each quadword has a word 6420 // from each of the four input quadwords, calculate the InOrder bitvector now 6421 // before falling through to the insert/extract cleanup. 6422 if (BestLoQuad == -1 && BestHiQuad == -1) { 6423 NewV = V1; 6424 for (int i = 0; i != 8; ++i) 6425 if (MaskVals[i] < 0 || MaskVals[i] == i) 6426 InOrder.set(i); 6427 } 6428 6429 // The other elements are put in the right place using pextrw and pinsrw. 6430 for (unsigned i = 0; i != 8; ++i) { 6431 if (InOrder[i]) 6432 continue; 6433 int EltIdx = MaskVals[i]; 6434 if (EltIdx < 0) 6435 continue; 6436 SDValue ExtOp = (EltIdx < 8) ? 6437 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 6438 DAG.getIntPtrConstant(EltIdx)) : 6439 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 6440 DAG.getIntPtrConstant(EltIdx - 8)); 6441 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 6442 DAG.getIntPtrConstant(i)); 6443 } 6444 return NewV; 6445} 6446 6447// v16i8 shuffles - Prefer shuffles in the following order: 6448// 1. [ssse3] 1 x pshufb 6449// 2. [ssse3] 2 x pshufb + 1 x por 6450// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 6451static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 6452 const X86Subtarget* Subtarget, 6453 SelectionDAG &DAG) { 6454 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6455 SDValue V1 = SVOp->getOperand(0); 6456 SDValue V2 = SVOp->getOperand(1); 6457 SDLoc dl(SVOp); 6458 ArrayRef<int> MaskVals = SVOp->getMask(); 6459 6460 // Promote splats to a larger type which usually leads to more efficient code. 6461 // FIXME: Is this true if pshufb is available? 6462 if (SVOp->isSplat()) 6463 return PromoteSplat(SVOp, DAG); 6464 6465 // If we have SSSE3, case 1 is generated when all result bytes come from 6466 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 6467 // present, fall back to case 3. 6468 6469 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 6470 if (Subtarget->hasSSSE3()) { 6471 SmallVector<SDValue,16> pshufbMask; 6472 6473 // If all result elements are from one input vector, then only translate 6474 // undef mask values to 0x80 (zero out result) in the pshufb mask. 6475 // 6476 // Otherwise, we have elements from both input vectors, and must zero out 6477 // elements that come from V2 in the first mask, and V1 in the second mask 6478 // so that we can OR them together. 6479 for (unsigned i = 0; i != 16; ++i) { 6480 int EltIdx = MaskVals[i]; 6481 if (EltIdx < 0 || EltIdx >= 16) 6482 EltIdx = 0x80; 6483 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6484 } 6485 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 6486 DAG.getNode(ISD::BUILD_VECTOR, dl, 6487 MVT::v16i8, &pshufbMask[0], 16)); 6488 6489 // As PSHUFB will zero elements with negative indices, it's safe to ignore 6490 // the 2nd operand if it's undefined or zero. 6491 if (V2.getOpcode() == ISD::UNDEF || 6492 ISD::isBuildVectorAllZeros(V2.getNode())) 6493 return V1; 6494 6495 // Calculate the shuffle mask for the second input, shuffle it, and 6496 // OR it with the first shuffled input. 6497 pshufbMask.clear(); 6498 for (unsigned i = 0; i != 16; ++i) { 6499 int EltIdx = MaskVals[i]; 6500 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16; 6501 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6502 } 6503 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 6504 DAG.getNode(ISD::BUILD_VECTOR, dl, 6505 MVT::v16i8, &pshufbMask[0], 16)); 6506 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 6507 } 6508 6509 // No SSSE3 - Calculate in place words and then fix all out of place words 6510 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 6511 // the 16 different words that comprise the two doublequadword input vectors. 6512 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 6513 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 6514 SDValue NewV = V1; 6515 for (int i = 0; i != 8; ++i) { 6516 int Elt0 = MaskVals[i*2]; 6517 int Elt1 = MaskVals[i*2+1]; 6518 6519 // This word of the result is all undef, skip it. 6520 if (Elt0 < 0 && Elt1 < 0) 6521 continue; 6522 6523 // This word of the result is already in the correct place, skip it. 6524 if ((Elt0 == i*2) && (Elt1 == i*2+1)) 6525 continue; 6526 6527 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 6528 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 6529 SDValue InsElt; 6530 6531 // If Elt0 and Elt1 are defined, are consecutive, and can be load 6532 // using a single extract together, load it and store it. 6533 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 6534 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6535 DAG.getIntPtrConstant(Elt1 / 2)); 6536 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6537 DAG.getIntPtrConstant(i)); 6538 continue; 6539 } 6540 6541 // If Elt1 is defined, extract it from the appropriate source. If the 6542 // source byte is not also odd, shift the extracted word left 8 bits 6543 // otherwise clear the bottom 8 bits if we need to do an or. 6544 if (Elt1 >= 0) { 6545 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6546 DAG.getIntPtrConstant(Elt1 / 2)); 6547 if ((Elt1 & 1) == 0) 6548 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 6549 DAG.getConstant(8, 6550 TLI.getShiftAmountTy(InsElt.getValueType()))); 6551 else if (Elt0 >= 0) 6552 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 6553 DAG.getConstant(0xFF00, MVT::i16)); 6554 } 6555 // If Elt0 is defined, extract it from the appropriate source. If the 6556 // source byte is not also even, shift the extracted word right 8 bits. If 6557 // Elt1 was also defined, OR the extracted values together before 6558 // inserting them in the result. 6559 if (Elt0 >= 0) { 6560 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 6561 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 6562 if ((Elt0 & 1) != 0) 6563 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 6564 DAG.getConstant(8, 6565 TLI.getShiftAmountTy(InsElt0.getValueType()))); 6566 else if (Elt1 >= 0) 6567 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 6568 DAG.getConstant(0x00FF, MVT::i16)); 6569 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 6570 : InsElt0; 6571 } 6572 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6573 DAG.getIntPtrConstant(i)); 6574 } 6575 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 6576} 6577 6578// v32i8 shuffles - Translate to VPSHUFB if possible. 6579static 6580SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, 6581 const X86Subtarget *Subtarget, 6582 SelectionDAG &DAG) { 6583 MVT VT = SVOp->getSimpleValueType(0); 6584 SDValue V1 = SVOp->getOperand(0); 6585 SDValue V2 = SVOp->getOperand(1); 6586 SDLoc dl(SVOp); 6587 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end()); 6588 6589 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6590 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode()); 6591 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode()); 6592 6593 // VPSHUFB may be generated if 6594 // (1) one of input vector is undefined or zeroinitializer. 6595 // The mask value 0x80 puts 0 in the corresponding slot of the vector. 6596 // And (2) the mask indexes don't cross the 128-bit lane. 6597 if (VT != MVT::v32i8 || !Subtarget->hasInt256() || 6598 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero)) 6599 return SDValue(); 6600 6601 if (V1IsAllZero && !V2IsAllZero) { 6602 CommuteVectorShuffleMask(MaskVals, 32); 6603 V1 = V2; 6604 } 6605 SmallVector<SDValue, 32> pshufbMask; 6606 for (unsigned i = 0; i != 32; i++) { 6607 int EltIdx = MaskVals[i]; 6608 if (EltIdx < 0 || EltIdx >= 32) 6609 EltIdx = 0x80; 6610 else { 6611 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16)) 6612 // Cross lane is not allowed. 6613 return SDValue(); 6614 EltIdx &= 0xf; 6615 } 6616 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6617 } 6618 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1, 6619 DAG.getNode(ISD::BUILD_VECTOR, dl, 6620 MVT::v32i8, &pshufbMask[0], 32)); 6621} 6622 6623/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 6624/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 6625/// done when every pair / quad of shuffle mask elements point to elements in 6626/// the right sequence. e.g. 6627/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 6628static 6629SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 6630 SelectionDAG &DAG) { 6631 MVT VT = SVOp->getSimpleValueType(0); 6632 SDLoc dl(SVOp); 6633 unsigned NumElems = VT.getVectorNumElements(); 6634 MVT NewVT; 6635 unsigned Scale; 6636 switch (VT.SimpleTy) { 6637 default: llvm_unreachable("Unexpected!"); 6638 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 6639 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 6640 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 6641 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 6642 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 6643 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 6644 } 6645 6646 SmallVector<int, 8> MaskVec; 6647 for (unsigned i = 0; i != NumElems; i += Scale) { 6648 int StartIdx = -1; 6649 for (unsigned j = 0; j != Scale; ++j) { 6650 int EltIdx = SVOp->getMaskElt(i+j); 6651 if (EltIdx < 0) 6652 continue; 6653 if (StartIdx < 0) 6654 StartIdx = (EltIdx / Scale); 6655 if (EltIdx != (int)(StartIdx*Scale + j)) 6656 return SDValue(); 6657 } 6658 MaskVec.push_back(StartIdx); 6659 } 6660 6661 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 6662 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 6663 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6664} 6665 6666/// getVZextMovL - Return a zero-extending vector move low node. 6667/// 6668static SDValue getVZextMovL(MVT VT, MVT OpVT, 6669 SDValue SrcOp, SelectionDAG &DAG, 6670 const X86Subtarget *Subtarget, SDLoc dl) { 6671 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6672 LoadSDNode *LD = NULL; 6673 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6674 LD = dyn_cast<LoadSDNode>(SrcOp); 6675 if (!LD) { 6676 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6677 // instead. 6678 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6679 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6680 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6681 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6682 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6683 // PR2108 6684 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6685 return DAG.getNode(ISD::BITCAST, dl, VT, 6686 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6687 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6688 OpVT, 6689 SrcOp.getOperand(0) 6690 .getOperand(0)))); 6691 } 6692 } 6693 } 6694 6695 return DAG.getNode(ISD::BITCAST, dl, VT, 6696 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6697 DAG.getNode(ISD::BITCAST, dl, 6698 OpVT, SrcOp))); 6699} 6700 6701/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6702/// which could not be matched by any known target speficic shuffle 6703static SDValue 6704LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6705 6706 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); 6707 if (NewOp.getNode()) 6708 return NewOp; 6709 6710 MVT VT = SVOp->getSimpleValueType(0); 6711 6712 unsigned NumElems = VT.getVectorNumElements(); 6713 unsigned NumLaneElems = NumElems / 2; 6714 6715 SDLoc dl(SVOp); 6716 MVT EltVT = VT.getVectorElementType(); 6717 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 6718 SDValue Output[2]; 6719 6720 SmallVector<int, 16> Mask; 6721 for (unsigned l = 0; l < 2; ++l) { 6722 // Build a shuffle mask for the output, discovering on the fly which 6723 // input vectors to use as shuffle operands (recorded in InputUsed). 6724 // If building a suitable shuffle vector proves too hard, then bail 6725 // out with UseBuildVector set. 6726 bool UseBuildVector = false; 6727 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6728 unsigned LaneStart = l * NumLaneElems; 6729 for (unsigned i = 0; i != NumLaneElems; ++i) { 6730 // The mask element. This indexes into the input. 6731 int Idx = SVOp->getMaskElt(i+LaneStart); 6732 if (Idx < 0) { 6733 // the mask element does not index into any input vector. 6734 Mask.push_back(-1); 6735 continue; 6736 } 6737 6738 // The input vector this mask element indexes into. 6739 int Input = Idx / NumLaneElems; 6740 6741 // Turn the index into an offset from the start of the input vector. 6742 Idx -= Input * NumLaneElems; 6743 6744 // Find or create a shuffle vector operand to hold this input. 6745 unsigned OpNo; 6746 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6747 if (InputUsed[OpNo] == Input) 6748 // This input vector is already an operand. 6749 break; 6750 if (InputUsed[OpNo] < 0) { 6751 // Create a new operand for this input vector. 6752 InputUsed[OpNo] = Input; 6753 break; 6754 } 6755 } 6756 6757 if (OpNo >= array_lengthof(InputUsed)) { 6758 // More than two input vectors used! Give up on trying to create a 6759 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 6760 UseBuildVector = true; 6761 break; 6762 } 6763 6764 // Add the mask index for the new shuffle vector. 6765 Mask.push_back(Idx + OpNo * NumLaneElems); 6766 } 6767 6768 if (UseBuildVector) { 6769 SmallVector<SDValue, 16> SVOps; 6770 for (unsigned i = 0; i != NumLaneElems; ++i) { 6771 // The mask element. This indexes into the input. 6772 int Idx = SVOp->getMaskElt(i+LaneStart); 6773 if (Idx < 0) { 6774 SVOps.push_back(DAG.getUNDEF(EltVT)); 6775 continue; 6776 } 6777 6778 // The input vector this mask element indexes into. 6779 int Input = Idx / NumElems; 6780 6781 // Turn the index into an offset from the start of the input vector. 6782 Idx -= Input * NumElems; 6783 6784 // Extract the vector element by hand. 6785 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 6786 SVOp->getOperand(Input), 6787 DAG.getIntPtrConstant(Idx))); 6788 } 6789 6790 // Construct the output using a BUILD_VECTOR. 6791 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0], 6792 SVOps.size()); 6793 } else if (InputUsed[0] < 0) { 6794 // No input vectors were used! The result is undefined. 6795 Output[l] = DAG.getUNDEF(NVT); 6796 } else { 6797 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6798 (InputUsed[0] % 2) * NumLaneElems, 6799 DAG, dl); 6800 // If only one input was used, use an undefined vector for the other. 6801 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6802 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6803 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6804 // At least one input vector was used. Create a new shuffle vector. 6805 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6806 } 6807 6808 Mask.clear(); 6809 } 6810 6811 // Concatenate the result back 6812 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); 6813} 6814 6815/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6816/// 4 elements, and match them with several different shuffle types. 6817static SDValue 6818LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6819 SDValue V1 = SVOp->getOperand(0); 6820 SDValue V2 = SVOp->getOperand(1); 6821 SDLoc dl(SVOp); 6822 MVT VT = SVOp->getSimpleValueType(0); 6823 6824 assert(VT.is128BitVector() && "Unsupported vector size"); 6825 6826 std::pair<int, int> Locs[4]; 6827 int Mask1[] = { -1, -1, -1, -1 }; 6828 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6829 6830 unsigned NumHi = 0; 6831 unsigned NumLo = 0; 6832 for (unsigned i = 0; i != 4; ++i) { 6833 int Idx = PermMask[i]; 6834 if (Idx < 0) { 6835 Locs[i] = std::make_pair(-1, -1); 6836 } else { 6837 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6838 if (Idx < 4) { 6839 Locs[i] = std::make_pair(0, NumLo); 6840 Mask1[NumLo] = Idx; 6841 NumLo++; 6842 } else { 6843 Locs[i] = std::make_pair(1, NumHi); 6844 if (2+NumHi < 4) 6845 Mask1[2+NumHi] = Idx; 6846 NumHi++; 6847 } 6848 } 6849 } 6850 6851 if (NumLo <= 2 && NumHi <= 2) { 6852 // If no more than two elements come from either vector. This can be 6853 // implemented with two shuffles. First shuffle gather the elements. 6854 // The second shuffle, which takes the first shuffle as both of its 6855 // vector operands, put the elements into the right order. 6856 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6857 6858 int Mask2[] = { -1, -1, -1, -1 }; 6859 6860 for (unsigned i = 0; i != 4; ++i) 6861 if (Locs[i].first != -1) { 6862 unsigned Idx = (i < 2) ? 0 : 4; 6863 Idx += Locs[i].first * 2 + Locs[i].second; 6864 Mask2[i] = Idx; 6865 } 6866 6867 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6868 } 6869 6870 if (NumLo == 3 || NumHi == 3) { 6871 // Otherwise, we must have three elements from one vector, call it X, and 6872 // one element from the other, call it Y. First, use a shufps to build an 6873 // intermediate vector with the one element from Y and the element from X 6874 // that will be in the same half in the final destination (the indexes don't 6875 // matter). Then, use a shufps to build the final vector, taking the half 6876 // containing the element from Y from the intermediate, and the other half 6877 // from X. 6878 if (NumHi == 3) { 6879 // Normalize it so the 3 elements come from V1. 6880 CommuteVectorShuffleMask(PermMask, 4); 6881 std::swap(V1, V2); 6882 } 6883 6884 // Find the element from V2. 6885 unsigned HiIndex; 6886 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6887 int Val = PermMask[HiIndex]; 6888 if (Val < 0) 6889 continue; 6890 if (Val >= 4) 6891 break; 6892 } 6893 6894 Mask1[0] = PermMask[HiIndex]; 6895 Mask1[1] = -1; 6896 Mask1[2] = PermMask[HiIndex^1]; 6897 Mask1[3] = -1; 6898 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6899 6900 if (HiIndex >= 2) { 6901 Mask1[0] = PermMask[0]; 6902 Mask1[1] = PermMask[1]; 6903 Mask1[2] = HiIndex & 1 ? 6 : 4; 6904 Mask1[3] = HiIndex & 1 ? 4 : 6; 6905 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6906 } 6907 6908 Mask1[0] = HiIndex & 1 ? 2 : 0; 6909 Mask1[1] = HiIndex & 1 ? 0 : 2; 6910 Mask1[2] = PermMask[2]; 6911 Mask1[3] = PermMask[3]; 6912 if (Mask1[2] >= 0) 6913 Mask1[2] += 4; 6914 if (Mask1[3] >= 0) 6915 Mask1[3] += 4; 6916 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6917 } 6918 6919 // Break it into (shuffle shuffle_hi, shuffle_lo). 6920 int LoMask[] = { -1, -1, -1, -1 }; 6921 int HiMask[] = { -1, -1, -1, -1 }; 6922 6923 int *MaskPtr = LoMask; 6924 unsigned MaskIdx = 0; 6925 unsigned LoIdx = 0; 6926 unsigned HiIdx = 2; 6927 for (unsigned i = 0; i != 4; ++i) { 6928 if (i == 2) { 6929 MaskPtr = HiMask; 6930 MaskIdx = 1; 6931 LoIdx = 0; 6932 HiIdx = 2; 6933 } 6934 int Idx = PermMask[i]; 6935 if (Idx < 0) { 6936 Locs[i] = std::make_pair(-1, -1); 6937 } else if (Idx < 4) { 6938 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6939 MaskPtr[LoIdx] = Idx; 6940 LoIdx++; 6941 } else { 6942 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6943 MaskPtr[HiIdx] = Idx; 6944 HiIdx++; 6945 } 6946 } 6947 6948 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6949 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6950 int MaskOps[] = { -1, -1, -1, -1 }; 6951 for (unsigned i = 0; i != 4; ++i) 6952 if (Locs[i].first != -1) 6953 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6954 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6955} 6956 6957static bool MayFoldVectorLoad(SDValue V) { 6958 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6959 V = V.getOperand(0); 6960 6961 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6962 V = V.getOperand(0); 6963 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6964 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6965 // BUILD_VECTOR (load), undef 6966 V = V.getOperand(0); 6967 6968 return MayFoldLoad(V); 6969} 6970 6971static 6972SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) { 6973 MVT VT = Op.getSimpleValueType(); 6974 6975 // Canonizalize to v2f64. 6976 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6977 return DAG.getNode(ISD::BITCAST, dl, VT, 6978 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6979 V1, DAG)); 6980} 6981 6982static 6983SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, 6984 bool HasSSE2) { 6985 SDValue V1 = Op.getOperand(0); 6986 SDValue V2 = Op.getOperand(1); 6987 MVT VT = Op.getSimpleValueType(); 6988 6989 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6990 6991 if (HasSSE2 && VT == MVT::v2f64) 6992 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6993 6994 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6995 return DAG.getNode(ISD::BITCAST, dl, VT, 6996 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6997 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6998 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6999} 7000 7001static 7002SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) { 7003 SDValue V1 = Op.getOperand(0); 7004 SDValue V2 = Op.getOperand(1); 7005 MVT VT = Op.getSimpleValueType(); 7006 7007 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 7008 "unsupported shuffle type"); 7009 7010 if (V2.getOpcode() == ISD::UNDEF) 7011 V2 = V1; 7012 7013 // v4i32 or v4f32 7014 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 7015} 7016 7017static 7018SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 7019 SDValue V1 = Op.getOperand(0); 7020 SDValue V2 = Op.getOperand(1); 7021 MVT VT = Op.getSimpleValueType(); 7022 unsigned NumElems = VT.getVectorNumElements(); 7023 7024 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 7025 // operand of these instructions is only memory, so check if there's a 7026 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 7027 // same masks. 7028 bool CanFoldLoad = false; 7029 7030 // Trivial case, when V2 comes from a load. 7031 if (MayFoldVectorLoad(V2)) 7032 CanFoldLoad = true; 7033 7034 // When V1 is a load, it can be folded later into a store in isel, example: 7035 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 7036 // turns into: 7037 // (MOVLPSmr addr:$src1, VR128:$src2) 7038 // So, recognize this potential and also use MOVLPS or MOVLPD 7039 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 7040 CanFoldLoad = true; 7041 7042 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 7043 if (CanFoldLoad) { 7044 if (HasSSE2 && NumElems == 2) 7045 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 7046 7047 if (NumElems == 4) 7048 // If we don't care about the second element, proceed to use movss. 7049 if (SVOp->getMaskElt(1) != -1) 7050 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 7051 } 7052 7053 // movl and movlp will both match v2i64, but v2i64 is never matched by 7054 // movl earlier because we make it strict to avoid messing with the movlp load 7055 // folding logic (see the code above getMOVLP call). Match it here then, 7056 // this is horrible, but will stay like this until we move all shuffle 7057 // matching to x86 specific nodes. Note that for the 1st condition all 7058 // types are matched with movsd. 7059 if (HasSSE2) { 7060 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 7061 // as to remove this logic from here, as much as possible 7062 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 7063 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 7064 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 7065 } 7066 7067 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 7068 7069 // Invert the operand order and use SHUFPS to match it. 7070 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 7071 getShuffleSHUFImmediate(SVOp), DAG); 7072} 7073 7074// Reduce a vector shuffle to zext. 7075static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget, 7076 SelectionDAG &DAG) { 7077 // PMOVZX is only available from SSE41. 7078 if (!Subtarget->hasSSE41()) 7079 return SDValue(); 7080 7081 MVT VT = Op.getSimpleValueType(); 7082 7083 // Only AVX2 support 256-bit vector integer extending. 7084 if (!Subtarget->hasInt256() && VT.is256BitVector()) 7085 return SDValue(); 7086 7087 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 7088 SDLoc DL(Op); 7089 SDValue V1 = Op.getOperand(0); 7090 SDValue V2 = Op.getOperand(1); 7091 unsigned NumElems = VT.getVectorNumElements(); 7092 7093 // Extending is an unary operation and the element type of the source vector 7094 // won't be equal to or larger than i64. 7095 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() || 7096 VT.getVectorElementType() == MVT::i64) 7097 return SDValue(); 7098 7099 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4. 7100 unsigned Shift = 1; // Start from 2, i.e. 1 << 1. 7101 while ((1U << Shift) < NumElems) { 7102 if (SVOp->getMaskElt(1U << Shift) == 1) 7103 break; 7104 Shift += 1; 7105 // The maximal ratio is 8, i.e. from i8 to i64. 7106 if (Shift > 3) 7107 return SDValue(); 7108 } 7109 7110 // Check the shuffle mask. 7111 unsigned Mask = (1U << Shift) - 1; 7112 for (unsigned i = 0; i != NumElems; ++i) { 7113 int EltIdx = SVOp->getMaskElt(i); 7114 if ((i & Mask) != 0 && EltIdx != -1) 7115 return SDValue(); 7116 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift)) 7117 return SDValue(); 7118 } 7119 7120 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift; 7121 MVT NeVT = MVT::getIntegerVT(NBits); 7122 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift); 7123 7124 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT)) 7125 return SDValue(); 7126 7127 // Simplify the operand as it's prepared to be fed into shuffle. 7128 unsigned SignificantBits = NVT.getSizeInBits() >> Shift; 7129 if (V1.getOpcode() == ISD::BITCAST && 7130 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 7131 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && 7132 V1.getOperand(0).getOperand(0) 7133 .getSimpleValueType().getSizeInBits() == SignificantBits) { 7134 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x) 7135 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0); 7136 ConstantSDNode *CIdx = 7137 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1)); 7138 // If it's foldable, i.e. normal load with single use, we will let code 7139 // selection to fold it. Otherwise, we will short the conversion sequence. 7140 if (CIdx && CIdx->getZExtValue() == 0 && 7141 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) { 7142 MVT FullVT = V.getSimpleValueType(); 7143 MVT V1VT = V1.getSimpleValueType(); 7144 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) { 7145 // The "ext_vec_elt" node is wider than the result node. 7146 // In this case we should extract subvector from V. 7147 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)). 7148 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits(); 7149 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(), 7150 FullVT.getVectorNumElements()/Ratio); 7151 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V, 7152 DAG.getIntPtrConstant(0)); 7153 } 7154 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V); 7155 } 7156 } 7157 7158 return DAG.getNode(ISD::BITCAST, DL, VT, 7159 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1)); 7160} 7161 7162static SDValue 7163NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget, 7164 SelectionDAG &DAG) { 7165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 7166 MVT VT = Op.getSimpleValueType(); 7167 SDLoc dl(Op); 7168 SDValue V1 = Op.getOperand(0); 7169 SDValue V2 = Op.getOperand(1); 7170 7171 if (isZeroShuffle(SVOp)) 7172 return getZeroVector(VT, Subtarget, DAG, dl); 7173 7174 // Handle splat operations 7175 if (SVOp->isSplat()) { 7176 // Use vbroadcast whenever the splat comes from a foldable load 7177 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG); 7178 if (Broadcast.getNode()) 7179 return Broadcast; 7180 } 7181 7182 // Check integer expanding shuffles. 7183 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG); 7184 if (NewOp.getNode()) 7185 return NewOp; 7186 7187 // If the shuffle can be profitably rewritten as a narrower shuffle, then 7188 // do it! 7189 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 7190 VT == MVT::v16i16 || VT == MVT::v32i8) { 7191 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 7192 if (NewOp.getNode()) 7193 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 7194 } else if ((VT == MVT::v4i32 || 7195 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 7196 // FIXME: Figure out a cleaner way to do this. 7197 // Try to make use of movq to zero out the top part. 7198 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 7199 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 7200 if (NewOp.getNode()) { 7201 MVT NewVT = NewOp.getSimpleValueType(); 7202 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 7203 NewVT, true, false)) 7204 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 7205 DAG, Subtarget, dl); 7206 } 7207 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 7208 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 7209 if (NewOp.getNode()) { 7210 MVT NewVT = NewOp.getSimpleValueType(); 7211 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 7212 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 7213 DAG, Subtarget, dl); 7214 } 7215 } 7216 } 7217 return SDValue(); 7218} 7219 7220SDValue 7221X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 7222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 7223 SDValue V1 = Op.getOperand(0); 7224 SDValue V2 = Op.getOperand(1); 7225 MVT VT = Op.getSimpleValueType(); 7226 SDLoc dl(Op); 7227 unsigned NumElems = VT.getVectorNumElements(); 7228 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 7229 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 7230 bool V1IsSplat = false; 7231 bool V2IsSplat = false; 7232 bool HasSSE2 = Subtarget->hasSSE2(); 7233 bool HasFp256 = Subtarget->hasFp256(); 7234 bool HasInt256 = Subtarget->hasInt256(); 7235 MachineFunction &MF = DAG.getMachineFunction(); 7236 bool OptForSize = MF.getFunction()->getAttributes(). 7237 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); 7238 7239 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 7240 7241 if (V1IsUndef && V2IsUndef) 7242 return DAG.getUNDEF(VT); 7243 7244 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 7245 7246 // Vector shuffle lowering takes 3 steps: 7247 // 7248 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 7249 // narrowing and commutation of operands should be handled. 7250 // 2) Matching of shuffles with known shuffle masks to x86 target specific 7251 // shuffle nodes. 7252 // 3) Rewriting of unmatched masks into new generic shuffle operations, 7253 // so the shuffle can be broken into other shuffles and the legalizer can 7254 // try the lowering again. 7255 // 7256 // The general idea is that no vector_shuffle operation should be left to 7257 // be matched during isel, all of them must be converted to a target specific 7258 // node here. 7259 7260 // Normalize the input vectors. Here splats, zeroed vectors, profitable 7261 // narrowing and commutation of operands should be handled. The actual code 7262 // doesn't include all of those, work in progress... 7263 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG); 7264 if (NewOp.getNode()) 7265 return NewOp; 7266 7267 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 7268 7269 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 7270 // unpckh_undef). Only use pshufd if speed is more important than size. 7271 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 7272 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 7273 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 7274 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 7275 7276 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 7277 V2IsUndef && MayFoldVectorLoad(V1)) 7278 return getMOVDDup(Op, dl, V1, DAG); 7279 7280 if (isMOVHLPS_v_undef_Mask(M, VT)) 7281 return getMOVHighToLow(Op, dl, DAG); 7282 7283 // Use to match splats 7284 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef && 7285 (VT == MVT::v2f64 || VT == MVT::v2i64)) 7286 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 7287 7288 if (isPSHUFDMask(M, VT)) { 7289 // The actual implementation will match the mask in the if above and then 7290 // during isel it can match several different instructions, not only pshufd 7291 // as its name says, sad but true, emulate the behavior for now... 7292 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 7293 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 7294 7295 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 7296 7297 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 7298 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 7299 7300 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64)) 7301 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, 7302 DAG); 7303 7304 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 7305 TargetMask, DAG); 7306 } 7307 7308 if (isPALIGNRMask(M, VT, Subtarget)) 7309 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2, 7310 getShufflePALIGNRImmediate(SVOp), 7311 DAG); 7312 7313 // Check if this can be converted into a logical shift. 7314 bool isLeft = false; 7315 unsigned ShAmt = 0; 7316 SDValue ShVal; 7317 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 7318 if (isShift && ShVal.hasOneUse()) { 7319 // If the shifted value has multiple uses, it may be cheaper to use 7320 // v_set0 + movlhps or movhlps, etc. 7321 MVT EltVT = VT.getVectorElementType(); 7322 ShAmt *= EltVT.getSizeInBits(); 7323 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 7324 } 7325 7326 if (isMOVLMask(M, VT)) { 7327 if (ISD::isBuildVectorAllZeros(V1.getNode())) 7328 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 7329 if (!isMOVLPMask(M, VT)) { 7330 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 7331 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 7332 7333 if (VT == MVT::v4i32 || VT == MVT::v4f32) 7334 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 7335 } 7336 } 7337 7338 // FIXME: fold these into legal mask. 7339 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256)) 7340 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 7341 7342 if (isMOVHLPSMask(M, VT)) 7343 return getMOVHighToLow(Op, dl, DAG); 7344 7345 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 7346 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 7347 7348 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 7349 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 7350 7351 if (isMOVLPMask(M, VT)) 7352 return getMOVLP(Op, dl, DAG, HasSSE2); 7353 7354 if (ShouldXformToMOVHLPS(M, VT) || 7355 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 7356 return CommuteVectorShuffle(SVOp, DAG); 7357 7358 if (isShift) { 7359 // No better options. Use a vshldq / vsrldq. 7360 MVT EltVT = VT.getVectorElementType(); 7361 ShAmt *= EltVT.getSizeInBits(); 7362 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 7363 } 7364 7365 bool Commuted = false; 7366 // FIXME: This should also accept a bitcast of a splat? Be careful, not 7367 // 1,1,1,1 -> v8i16 though. 7368 V1IsSplat = isSplatVector(V1.getNode()); 7369 V2IsSplat = isSplatVector(V2.getNode()); 7370 7371 // Canonicalize the splat or undef, if present, to be on the RHS. 7372 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 7373 CommuteVectorShuffleMask(M, NumElems); 7374 std::swap(V1, V2); 7375 std::swap(V1IsSplat, V2IsSplat); 7376 Commuted = true; 7377 } 7378 7379 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 7380 // Shuffling low element of v1 into undef, just return v1. 7381 if (V2IsUndef) 7382 return V1; 7383 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 7384 // the instruction selector will not match, so get a canonical MOVL with 7385 // swapped operands to undo the commute. 7386 return getMOVL(DAG, dl, VT, V2, V1); 7387 } 7388 7389 if (isUNPCKLMask(M, VT, HasInt256)) 7390 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 7391 7392 if (isUNPCKHMask(M, VT, HasInt256)) 7393 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 7394 7395 if (V2IsSplat) { 7396 // Normalize mask so all entries that point to V2 points to its first 7397 // element then try to match unpck{h|l} again. If match, return a 7398 // new vector_shuffle with the corrected mask.p 7399 SmallVector<int, 8> NewMask(M.begin(), M.end()); 7400 NormalizeMask(NewMask, NumElems); 7401 if (isUNPCKLMask(NewMask, VT, HasInt256, true)) 7402 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 7403 if (isUNPCKHMask(NewMask, VT, HasInt256, true)) 7404 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 7405 } 7406 7407 if (Commuted) { 7408 // Commute is back and try unpck* again. 7409 // FIXME: this seems wrong. 7410 CommuteVectorShuffleMask(M, NumElems); 7411 std::swap(V1, V2); 7412 std::swap(V1IsSplat, V2IsSplat); 7413 Commuted = false; 7414 7415 if (isUNPCKLMask(M, VT, HasInt256)) 7416 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 7417 7418 if (isUNPCKHMask(M, VT, HasInt256)) 7419 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 7420 } 7421 7422 // Normalize the node to match x86 shuffle ops if needed 7423 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true))) 7424 return CommuteVectorShuffle(SVOp, DAG); 7425 7426 // The checks below are all present in isShuffleMaskLegal, but they are 7427 // inlined here right now to enable us to directly emit target specific 7428 // nodes, and remove one by one until they don't return Op anymore. 7429 7430 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 7431 SVOp->getSplatIndex() == 0 && V2IsUndef) { 7432 if (VT == MVT::v2f64 || VT == MVT::v2i64) 7433 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 7434 } 7435 7436 if (isPSHUFHWMask(M, VT, HasInt256)) 7437 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 7438 getShufflePSHUFHWImmediate(SVOp), 7439 DAG); 7440 7441 if (isPSHUFLWMask(M, VT, HasInt256)) 7442 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 7443 getShufflePSHUFLWImmediate(SVOp), 7444 DAG); 7445 7446 if (isSHUFPMask(M, VT)) 7447 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 7448 getShuffleSHUFImmediate(SVOp), DAG); 7449 7450 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 7451 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 7452 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 7453 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 7454 7455 //===--------------------------------------------------------------------===// 7456 // Generate target specific nodes for 128 or 256-bit shuffles only 7457 // supported in the AVX instruction set. 7458 // 7459 7460 // Handle VMOVDDUPY permutations 7461 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256)) 7462 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 7463 7464 // Handle VPERMILPS/D* permutations 7465 if (isVPERMILPMask(M, VT)) { 7466 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32) 7467 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 7468 getShuffleSHUFImmediate(SVOp), DAG); 7469 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 7470 getShuffleSHUFImmediate(SVOp), DAG); 7471 } 7472 7473 // Handle VPERM2F128/VPERM2I128 permutations 7474 if (isVPERM2X128Mask(M, VT, HasFp256)) 7475 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 7476 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 7477 7478 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 7479 if (BlendOp.getNode()) 7480 return BlendOp; 7481 7482 unsigned Imm8; 7483 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8)) 7484 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG); 7485 7486 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) || 7487 VT.is512BitVector()) { 7488 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits()); 7489 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems); 7490 SmallVector<SDValue, 16> permclMask; 7491 for (unsigned i = 0; i != NumElems; ++i) { 7492 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT)); 7493 } 7494 7495 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, 7496 &permclMask[0], NumElems); 7497 if (V2IsUndef) 7498 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 7499 return DAG.getNode(X86ISD::VPERMV, dl, VT, 7500 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 7501 return DAG.getNode(X86ISD::VPERMV3, dl, VT, 7502 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2); 7503 } 7504 7505 //===--------------------------------------------------------------------===// 7506 // Since no target specific shuffle was selected for this generic one, 7507 // lower it into other known shuffles. FIXME: this isn't true yet, but 7508 // this is the plan. 7509 // 7510 7511 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 7512 if (VT == MVT::v8i16) { 7513 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG); 7514 if (NewOp.getNode()) 7515 return NewOp; 7516 } 7517 7518 if (VT == MVT::v16i8) { 7519 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG); 7520 if (NewOp.getNode()) 7521 return NewOp; 7522 } 7523 7524 if (VT == MVT::v32i8) { 7525 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG); 7526 if (NewOp.getNode()) 7527 return NewOp; 7528 } 7529 7530 // Handle all 128-bit wide vectors with 4 elements, and match them with 7531 // several different shuffle types. 7532 if (NumElems == 4 && VT.is128BitVector()) 7533 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 7534 7535 // Handle general 256-bit shuffles 7536 if (VT.is256BitVector()) 7537 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 7538 7539 return SDValue(); 7540} 7541 7542static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7543 MVT VT = Op.getSimpleValueType(); 7544 SDLoc dl(Op); 7545 7546 if (!Op.getOperand(0).getSimpleValueType().is128BitVector()) 7547 return SDValue(); 7548 7549 if (VT.getSizeInBits() == 8) { 7550 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 7551 Op.getOperand(0), Op.getOperand(1)); 7552 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7553 DAG.getValueType(VT)); 7554 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7555 } 7556 7557 if (VT.getSizeInBits() == 16) { 7558 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7559 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 7560 if (Idx == 0) 7561 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7562 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7563 DAG.getNode(ISD::BITCAST, dl, 7564 MVT::v4i32, 7565 Op.getOperand(0)), 7566 Op.getOperand(1))); 7567 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 7568 Op.getOperand(0), Op.getOperand(1)); 7569 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7570 DAG.getValueType(VT)); 7571 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7572 } 7573 7574 if (VT == MVT::f32) { 7575 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 7576 // the result back to FR32 register. It's only worth matching if the 7577 // result has a single use which is a store or a bitcast to i32. And in 7578 // the case of a store, it's not worth it if the index is a constant 0, 7579 // because a MOVSSmr can be used instead, which is smaller and faster. 7580 if (!Op.hasOneUse()) 7581 return SDValue(); 7582 SDNode *User = *Op.getNode()->use_begin(); 7583 if ((User->getOpcode() != ISD::STORE || 7584 (isa<ConstantSDNode>(Op.getOperand(1)) && 7585 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 7586 (User->getOpcode() != ISD::BITCAST || 7587 User->getValueType(0) != MVT::i32)) 7588 return SDValue(); 7589 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7590 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 7591 Op.getOperand(0)), 7592 Op.getOperand(1)); 7593 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 7594 } 7595 7596 if (VT == MVT::i32 || VT == MVT::i64) { 7597 // ExtractPS/pextrq works with constant index. 7598 if (isa<ConstantSDNode>(Op.getOperand(1))) 7599 return Op; 7600 } 7601 return SDValue(); 7602} 7603 7604SDValue 7605X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 7606 SelectionDAG &DAG) const { 7607 SDLoc dl(Op); 7608 SDValue Vec = Op.getOperand(0); 7609 MVT VecVT = Vec.getSimpleValueType(); 7610 SDValue Idx = Op.getOperand(1); 7611 if (!isa<ConstantSDNode>(Idx)) { 7612 if (VecVT.is512BitVector() || 7613 (VecVT.is256BitVector() && Subtarget->hasInt256() && 7614 VecVT.getVectorElementType().getSizeInBits() == 32)) { 7615 7616 MVT MaskEltVT = 7617 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits()); 7618 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() / 7619 MaskEltVT.getSizeInBits()); 7620 7621 if (Idx.getSimpleValueType() != MaskEltVT) 7622 if (Idx.getOpcode() == ISD::ZERO_EXTEND || 7623 Idx.getOpcode() == ISD::SIGN_EXTEND) 7624 Idx = Idx.getOperand(0); 7625 assert(Idx.getSimpleValueType() == MaskEltVT && 7626 "Unexpected index in insertelement"); 7627 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT, 7628 getZeroVector(MaskVT, Subtarget, DAG, dl), 7629 Idx, DAG.getConstant(0, getPointerTy())); 7630 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec); 7631 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), 7632 Perm, DAG.getConstant(0, getPointerTy())); 7633 } 7634 return SDValue(); 7635 } 7636 7637 // If this is a 256-bit vector result, first extract the 128-bit vector and 7638 // then extract the element from the 128-bit vector. 7639 if (VecVT.is256BitVector() || VecVT.is512BitVector()) { 7640 7641 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7642 // Get the 128-bit vector. 7643 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 7644 MVT EltVT = VecVT.getVectorElementType(); 7645 7646 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits(); 7647 7648 //if (IdxVal >= NumElems/2) 7649 // IdxVal -= NumElems/2; 7650 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk; 7651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 7652 DAG.getConstant(IdxVal, MVT::i32)); 7653 } 7654 7655 assert(VecVT.is128BitVector() && "Unexpected vector length"); 7656 7657 if (Subtarget->hasSSE41()) { 7658 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7659 if (Res.getNode()) 7660 return Res; 7661 } 7662 7663 MVT VT = Op.getSimpleValueType(); 7664 // TODO: handle v16i8. 7665 if (VT.getSizeInBits() == 16) { 7666 SDValue Vec = Op.getOperand(0); 7667 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7668 if (Idx == 0) 7669 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7670 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7671 DAG.getNode(ISD::BITCAST, dl, 7672 MVT::v4i32, Vec), 7673 Op.getOperand(1))); 7674 // Transform it so it match pextrw which produces a 32-bit result. 7675 MVT EltVT = MVT::i32; 7676 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7677 Op.getOperand(0), Op.getOperand(1)); 7678 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7679 DAG.getValueType(VT)); 7680 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7681 } 7682 7683 if (VT.getSizeInBits() == 32) { 7684 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7685 if (Idx == 0) 7686 return Op; 7687 7688 // SHUFPS the element to the lowest double word, then movss. 7689 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7690 MVT VVT = Op.getOperand(0).getSimpleValueType(); 7691 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7692 DAG.getUNDEF(VVT), Mask); 7693 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7694 DAG.getIntPtrConstant(0)); 7695 } 7696 7697 if (VT.getSizeInBits() == 64) { 7698 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7699 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7700 // to match extract_elt for f64. 7701 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7702 if (Idx == 0) 7703 return Op; 7704 7705 // UNPCKHPD the element to the lowest double word, then movsd. 7706 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7707 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7708 int Mask[2] = { 1, -1 }; 7709 MVT VVT = Op.getOperand(0).getSimpleValueType(); 7710 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7711 DAG.getUNDEF(VVT), Mask); 7712 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7713 DAG.getIntPtrConstant(0)); 7714 } 7715 7716 return SDValue(); 7717} 7718 7719static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7720 MVT VT = Op.getSimpleValueType(); 7721 MVT EltVT = VT.getVectorElementType(); 7722 SDLoc dl(Op); 7723 7724 SDValue N0 = Op.getOperand(0); 7725 SDValue N1 = Op.getOperand(1); 7726 SDValue N2 = Op.getOperand(2); 7727 7728 if (!VT.is128BitVector()) 7729 return SDValue(); 7730 7731 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7732 isa<ConstantSDNode>(N2)) { 7733 unsigned Opc; 7734 if (VT == MVT::v8i16) 7735 Opc = X86ISD::PINSRW; 7736 else if (VT == MVT::v16i8) 7737 Opc = X86ISD::PINSRB; 7738 else 7739 Opc = X86ISD::PINSRB; 7740 7741 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7742 // argument. 7743 if (N1.getValueType() != MVT::i32) 7744 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7745 if (N2.getValueType() != MVT::i32) 7746 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7747 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7748 } 7749 7750 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7751 // Bits [7:6] of the constant are the source select. This will always be 7752 // zero here. The DAG Combiner may combine an extract_elt index into these 7753 // bits. For example (insert (extract, 3), 2) could be matched by putting 7754 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7755 // Bits [5:4] of the constant are the destination select. This is the 7756 // value of the incoming immediate. 7757 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7758 // combine either bitwise AND or insert of float 0.0 to set these bits. 7759 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7760 // Create this as a scalar to vector.. 7761 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7762 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7763 } 7764 7765 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 7766 // PINSR* works with constant index. 7767 return Op; 7768 } 7769 return SDValue(); 7770} 7771 7772SDValue 7773X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7774 MVT VT = Op.getSimpleValueType(); 7775 MVT EltVT = VT.getVectorElementType(); 7776 7777 SDLoc dl(Op); 7778 SDValue N0 = Op.getOperand(0); 7779 SDValue N1 = Op.getOperand(1); 7780 SDValue N2 = Op.getOperand(2); 7781 7782 // If this is a 256-bit vector result, first extract the 128-bit vector, 7783 // insert the element into the extracted half and then place it back. 7784 if (VT.is256BitVector() || VT.is512BitVector()) { 7785 if (!isa<ConstantSDNode>(N2)) 7786 return SDValue(); 7787 7788 // Get the desired 128-bit vector half. 7789 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7790 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 7791 7792 // Insert the element into the desired half. 7793 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits(); 7794 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128; 7795 7796 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 7797 DAG.getConstant(IdxIn128, MVT::i32)); 7798 7799 // Insert the changed part back to the 256-bit vector 7800 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 7801 } 7802 7803 if (Subtarget->hasSSE41()) 7804 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7805 7806 if (EltVT == MVT::i8) 7807 return SDValue(); 7808 7809 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7810 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7811 // as its second argument. 7812 if (N1.getValueType() != MVT::i32) 7813 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7814 if (N2.getValueType() != MVT::i32) 7815 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7816 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7817 } 7818 return SDValue(); 7819} 7820 7821static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 7822 SDLoc dl(Op); 7823 MVT OpVT = Op.getSimpleValueType(); 7824 7825 // If this is a 256-bit vector result, first insert into a 128-bit 7826 // vector and then insert into the 256-bit vector. 7827 if (!OpVT.is128BitVector()) { 7828 // Insert into a 128-bit vector. 7829 unsigned SizeFactor = OpVT.getSizeInBits()/128; 7830 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(), 7831 OpVT.getVectorNumElements() / SizeFactor); 7832 7833 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7834 7835 // Insert the 128-bit vector. 7836 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 7837 } 7838 7839 if (OpVT == MVT::v1i64 && 7840 Op.getOperand(0).getValueType() == MVT::i64) 7841 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7842 7843 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7844 assert(OpVT.is128BitVector() && "Expected an SSE type!"); 7845 return DAG.getNode(ISD::BITCAST, dl, OpVT, 7846 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7847} 7848 7849// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7850// a simple subregister reference or explicit instructions to grab 7851// upper bits of a vector. 7852static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7853 SelectionDAG &DAG) { 7854 SDLoc dl(Op); 7855 SDValue In = Op.getOperand(0); 7856 SDValue Idx = Op.getOperand(1); 7857 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7858 MVT ResVT = Op.getSimpleValueType(); 7859 MVT InVT = In.getSimpleValueType(); 7860 7861 if (Subtarget->hasFp256()) { 7862 if (ResVT.is128BitVector() && 7863 (InVT.is256BitVector() || InVT.is512BitVector()) && 7864 isa<ConstantSDNode>(Idx)) { 7865 return Extract128BitVector(In, IdxVal, DAG, dl); 7866 } 7867 if (ResVT.is256BitVector() && InVT.is512BitVector() && 7868 isa<ConstantSDNode>(Idx)) { 7869 return Extract256BitVector(In, IdxVal, DAG, dl); 7870 } 7871 } 7872 return SDValue(); 7873} 7874 7875// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7876// simple superregister reference or explicit instructions to insert 7877// the upper bits of a vector. 7878static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7879 SelectionDAG &DAG) { 7880 if (Subtarget->hasFp256()) { 7881 SDLoc dl(Op.getNode()); 7882 SDValue Vec = Op.getNode()->getOperand(0); 7883 SDValue SubVec = Op.getNode()->getOperand(1); 7884 SDValue Idx = Op.getNode()->getOperand(2); 7885 7886 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() || 7887 Op.getNode()->getSimpleValueType(0).is512BitVector()) && 7888 SubVec.getNode()->getSimpleValueType(0).is128BitVector() && 7889 isa<ConstantSDNode>(Idx)) { 7890 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7891 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7892 } 7893 7894 if (Op.getNode()->getSimpleValueType(0).is512BitVector() && 7895 SubVec.getNode()->getSimpleValueType(0).is256BitVector() && 7896 isa<ConstantSDNode>(Idx)) { 7897 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7898 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl); 7899 } 7900 } 7901 return SDValue(); 7902} 7903 7904// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7905// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7906// one of the above mentioned nodes. It has to be wrapped because otherwise 7907// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7908// be used to form addressing mode. These wrapped nodes will be selected 7909// into MOV32ri. 7910SDValue 7911X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7912 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7913 7914 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7915 // global base reg. 7916 unsigned char OpFlag = 0; 7917 unsigned WrapperKind = X86ISD::Wrapper; 7918 CodeModel::Model M = getTargetMachine().getCodeModel(); 7919 7920 if (Subtarget->isPICStyleRIPRel() && 7921 (M == CodeModel::Small || M == CodeModel::Kernel)) 7922 WrapperKind = X86ISD::WrapperRIP; 7923 else if (Subtarget->isPICStyleGOT()) 7924 OpFlag = X86II::MO_GOTOFF; 7925 else if (Subtarget->isPICStyleStubPIC()) 7926 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7927 7928 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7929 CP->getAlignment(), 7930 CP->getOffset(), OpFlag); 7931 SDLoc DL(CP); 7932 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7933 // With PIC, the address is actually $g + Offset. 7934 if (OpFlag) { 7935 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7936 DAG.getNode(X86ISD::GlobalBaseReg, 7937 SDLoc(), getPointerTy()), 7938 Result); 7939 } 7940 7941 return Result; 7942} 7943 7944SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7945 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7946 7947 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7948 // global base reg. 7949 unsigned char OpFlag = 0; 7950 unsigned WrapperKind = X86ISD::Wrapper; 7951 CodeModel::Model M = getTargetMachine().getCodeModel(); 7952 7953 if (Subtarget->isPICStyleRIPRel() && 7954 (M == CodeModel::Small || M == CodeModel::Kernel)) 7955 WrapperKind = X86ISD::WrapperRIP; 7956 else if (Subtarget->isPICStyleGOT()) 7957 OpFlag = X86II::MO_GOTOFF; 7958 else if (Subtarget->isPICStyleStubPIC()) 7959 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7960 7961 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7962 OpFlag); 7963 SDLoc DL(JT); 7964 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7965 7966 // With PIC, the address is actually $g + Offset. 7967 if (OpFlag) 7968 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7969 DAG.getNode(X86ISD::GlobalBaseReg, 7970 SDLoc(), getPointerTy()), 7971 Result); 7972 7973 return Result; 7974} 7975 7976SDValue 7977X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7978 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7979 7980 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7981 // global base reg. 7982 unsigned char OpFlag = 0; 7983 unsigned WrapperKind = X86ISD::Wrapper; 7984 CodeModel::Model M = getTargetMachine().getCodeModel(); 7985 7986 if (Subtarget->isPICStyleRIPRel() && 7987 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7988 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7989 OpFlag = X86II::MO_GOTPCREL; 7990 WrapperKind = X86ISD::WrapperRIP; 7991 } else if (Subtarget->isPICStyleGOT()) { 7992 OpFlag = X86II::MO_GOT; 7993 } else if (Subtarget->isPICStyleStubPIC()) { 7994 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7995 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7996 OpFlag = X86II::MO_DARWIN_NONLAZY; 7997 } 7998 7999 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 8000 8001 SDLoc DL(Op); 8002 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 8003 8004 // With PIC, the address is actually $g + Offset. 8005 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 8006 !Subtarget->is64Bit()) { 8007 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8008 DAG.getNode(X86ISD::GlobalBaseReg, 8009 SDLoc(), getPointerTy()), 8010 Result); 8011 } 8012 8013 // For symbols that require a load from a stub to get the address, emit the 8014 // load. 8015 if (isGlobalStubReference(OpFlag)) 8016 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 8017 MachinePointerInfo::getGOT(), false, false, false, 0); 8018 8019 return Result; 8020} 8021 8022SDValue 8023X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 8024 // Create the TargetBlockAddressAddress node. 8025 unsigned char OpFlags = 8026 Subtarget->ClassifyBlockAddressReference(); 8027 CodeModel::Model M = getTargetMachine().getCodeModel(); 8028 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 8029 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset(); 8030 SDLoc dl(Op); 8031 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset, 8032 OpFlags); 8033 8034 if (Subtarget->isPICStyleRIPRel() && 8035 (M == CodeModel::Small || M == CodeModel::Kernel)) 8036 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 8037 else 8038 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 8039 8040 // With PIC, the address is actually $g + Offset. 8041 if (isGlobalRelativeToPICBase(OpFlags)) { 8042 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 8043 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 8044 Result); 8045 } 8046 8047 return Result; 8048} 8049 8050SDValue 8051X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, 8052 int64_t Offset, SelectionDAG &DAG) const { 8053 // Create the TargetGlobalAddress node, folding in the constant 8054 // offset if it is legal. 8055 unsigned char OpFlags = 8056 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 8057 CodeModel::Model M = getTargetMachine().getCodeModel(); 8058 SDValue Result; 8059 if (OpFlags == X86II::MO_NO_FLAG && 8060 X86::isOffsetSuitableForCodeModel(Offset, M)) { 8061 // A direct static reference to a global. 8062 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 8063 Offset = 0; 8064 } else { 8065 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 8066 } 8067 8068 if (Subtarget->isPICStyleRIPRel() && 8069 (M == CodeModel::Small || M == CodeModel::Kernel)) 8070 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 8071 else 8072 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 8073 8074 // With PIC, the address is actually $g + Offset. 8075 if (isGlobalRelativeToPICBase(OpFlags)) { 8076 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 8077 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 8078 Result); 8079 } 8080 8081 // For globals that require a load from a stub to get the address, emit the 8082 // load. 8083 if (isGlobalStubReference(OpFlags)) 8084 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 8085 MachinePointerInfo::getGOT(), false, false, false, 0); 8086 8087 // If there was a non-zero offset that we didn't fold, create an explicit 8088 // addition for it. 8089 if (Offset != 0) 8090 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 8091 DAG.getConstant(Offset, getPointerTy())); 8092 8093 return Result; 8094} 8095 8096SDValue 8097X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 8098 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 8099 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 8100 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG); 8101} 8102 8103static SDValue 8104GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 8105 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 8106 unsigned char OperandFlags, bool LocalDynamic = false) { 8107 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8108 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8109 SDLoc dl(GA); 8110 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 8111 GA->getValueType(0), 8112 GA->getOffset(), 8113 OperandFlags); 8114 8115 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR 8116 : X86ISD::TLSADDR; 8117 8118 if (InFlag) { 8119 SDValue Ops[] = { Chain, TGA, *InFlag }; 8120 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops)); 8121 } else { 8122 SDValue Ops[] = { Chain, TGA }; 8123 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops)); 8124 } 8125 8126 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 8127 MFI->setAdjustsStack(true); 8128 8129 SDValue Flag = Chain.getValue(1); 8130 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 8131} 8132 8133// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 8134static SDValue 8135LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 8136 const EVT PtrVT) { 8137 SDValue InFlag; 8138 SDLoc dl(GA); // ? function entry point might be better 8139 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 8140 DAG.getNode(X86ISD::GlobalBaseReg, 8141 SDLoc(), PtrVT), InFlag); 8142 InFlag = Chain.getValue(1); 8143 8144 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 8145} 8146 8147// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 8148static SDValue 8149LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 8150 const EVT PtrVT) { 8151 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 8152 X86::RAX, X86II::MO_TLSGD); 8153} 8154 8155static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, 8156 SelectionDAG &DAG, 8157 const EVT PtrVT, 8158 bool is64Bit) { 8159 SDLoc dl(GA); 8160 8161 // Get the start address of the TLS block for this module. 8162 X86MachineFunctionInfo* MFI = DAG.getMachineFunction() 8163 .getInfo<X86MachineFunctionInfo>(); 8164 MFI->incNumLocalDynamicTLSAccesses(); 8165 8166 SDValue Base; 8167 if (is64Bit) { 8168 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, 8169 X86II::MO_TLSLD, /*LocalDynamic=*/true); 8170 } else { 8171 SDValue InFlag; 8172 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 8173 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag); 8174 InFlag = Chain.getValue(1); 8175 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, 8176 X86II::MO_TLSLDM, /*LocalDynamic=*/true); 8177 } 8178 8179 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations 8180 // of Base. 8181 8182 // Build x@dtpoff. 8183 unsigned char OperandFlags = X86II::MO_DTPOFF; 8184 unsigned WrapperKind = X86ISD::Wrapper; 8185 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 8186 GA->getValueType(0), 8187 GA->getOffset(), OperandFlags); 8188 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 8189 8190 // Add x@dtpoff with the base. 8191 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base); 8192} 8193 8194// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 8195static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 8196 const EVT PtrVT, TLSModel::Model model, 8197 bool is64Bit, bool isPIC) { 8198 SDLoc dl(GA); 8199 8200 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 8201 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 8202 is64Bit ? 257 : 256)); 8203 8204 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 8205 DAG.getIntPtrConstant(0), 8206 MachinePointerInfo(Ptr), 8207 false, false, false, 0); 8208 8209 unsigned char OperandFlags = 0; 8210 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 8211 // initialexec. 8212 unsigned WrapperKind = X86ISD::Wrapper; 8213 if (model == TLSModel::LocalExec) { 8214 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 8215 } else if (model == TLSModel::InitialExec) { 8216 if (is64Bit) { 8217 OperandFlags = X86II::MO_GOTTPOFF; 8218 WrapperKind = X86ISD::WrapperRIP; 8219 } else { 8220 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 8221 } 8222 } else { 8223 llvm_unreachable("Unexpected model"); 8224 } 8225 8226 // emit "addl x@ntpoff,%eax" (local exec) 8227 // or "addl x@indntpoff,%eax" (initial exec) 8228 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 8229 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 8230 GA->getValueType(0), 8231 GA->getOffset(), OperandFlags); 8232 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 8233 8234 if (model == TLSModel::InitialExec) { 8235 if (isPIC && !is64Bit) { 8236 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 8237 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), 8238 Offset); 8239 } 8240 8241 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 8242 MachinePointerInfo::getGOT(), false, false, false, 8243 0); 8244 } 8245 8246 // The address of the thread local variable is the add of the thread 8247 // pointer with the offset of the variable. 8248 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 8249} 8250 8251SDValue 8252X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 8253 8254 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 8255 const GlobalValue *GV = GA->getGlobal(); 8256 8257 if (Subtarget->isTargetELF()) { 8258 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 8259 8260 switch (model) { 8261 case TLSModel::GeneralDynamic: 8262 if (Subtarget->is64Bit()) 8263 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 8264 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 8265 case TLSModel::LocalDynamic: 8266 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(), 8267 Subtarget->is64Bit()); 8268 case TLSModel::InitialExec: 8269 case TLSModel::LocalExec: 8270 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 8271 Subtarget->is64Bit(), 8272 getTargetMachine().getRelocationModel() == Reloc::PIC_); 8273 } 8274 llvm_unreachable("Unknown TLS model."); 8275 } 8276 8277 if (Subtarget->isTargetDarwin()) { 8278 // Darwin only has one model of TLS. Lower to that. 8279 unsigned char OpFlag = 0; 8280 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 8281 X86ISD::WrapperRIP : X86ISD::Wrapper; 8282 8283 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 8284 // global base reg. 8285 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 8286 !Subtarget->is64Bit(); 8287 if (PIC32) 8288 OpFlag = X86II::MO_TLVP_PIC_BASE; 8289 else 8290 OpFlag = X86II::MO_TLVP; 8291 SDLoc DL(Op); 8292 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 8293 GA->getValueType(0), 8294 GA->getOffset(), OpFlag); 8295 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 8296 8297 // With PIC32, the address is actually $g + Offset. 8298 if (PIC32) 8299 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8300 DAG.getNode(X86ISD::GlobalBaseReg, 8301 SDLoc(), getPointerTy()), 8302 Offset); 8303 8304 // Lowering the machine isd will make sure everything is in the right 8305 // location. 8306 SDValue Chain = DAG.getEntryNode(); 8307 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8308 SDValue Args[] = { Chain, Offset }; 8309 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 8310 8311 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 8312 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8313 MFI->setAdjustsStack(true); 8314 8315 // And our return value (tls address) is in the standard call return value 8316 // location. 8317 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 8318 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 8319 Chain.getValue(1)); 8320 } 8321 8322 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) { 8323 // Just use the implicit TLS architecture 8324 // Need to generate someting similar to: 8325 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 8326 // ; from TEB 8327 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 8328 // mov rcx, qword [rdx+rcx*8] 8329 // mov eax, .tls$:tlsvar 8330 // [rax+rcx] contains the address 8331 // Windows 64bit: gs:0x58 8332 // Windows 32bit: fs:__tls_array 8333 8334 // If GV is an alias then use the aliasee for determining 8335 // thread-localness. 8336 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 8337 GV = GA->resolveAliasedGlobal(false); 8338 SDLoc dl(GA); 8339 SDValue Chain = DAG.getEntryNode(); 8340 8341 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 8342 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly 8343 // use its literal value of 0x2C. 8344 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 8345 ? Type::getInt8PtrTy(*DAG.getContext(), 8346 256) 8347 : Type::getInt32PtrTy(*DAG.getContext(), 8348 257)); 8349 8350 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) : 8351 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) : 8352 DAG.getExternalSymbol("_tls_array", getPointerTy())); 8353 8354 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray, 8355 MachinePointerInfo(Ptr), 8356 false, false, false, 0); 8357 8358 // Load the _tls_index variable 8359 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 8360 if (Subtarget->is64Bit()) 8361 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 8362 IDX, MachinePointerInfo(), MVT::i32, 8363 false, false, 0); 8364 else 8365 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 8366 false, false, false, 0); 8367 8368 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 8369 getPointerTy()); 8370 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 8371 8372 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 8373 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 8374 false, false, false, 0); 8375 8376 // Get the offset of start of .tls section 8377 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 8378 GA->getValueType(0), 8379 GA->getOffset(), X86II::MO_SECREL); 8380 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 8381 8382 // The address of the thread local variable is the add of the thread 8383 // pointer with the offset of the variable. 8384 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 8385 } 8386 8387 llvm_unreachable("TLS not implemented for this target."); 8388} 8389 8390/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 8391/// and take a 2 x i32 value to shift plus a shift amount. 8392SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 8393 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 8394 EVT VT = Op.getValueType(); 8395 unsigned VTBits = VT.getSizeInBits(); 8396 SDLoc dl(Op); 8397 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 8398 SDValue ShOpLo = Op.getOperand(0); 8399 SDValue ShOpHi = Op.getOperand(1); 8400 SDValue ShAmt = Op.getOperand(2); 8401 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 8402 DAG.getConstant(VTBits - 1, MVT::i8)) 8403 : DAG.getConstant(0, VT); 8404 8405 SDValue Tmp2, Tmp3; 8406 if (Op.getOpcode() == ISD::SHL_PARTS) { 8407 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 8408 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 8409 } else { 8410 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 8411 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 8412 } 8413 8414 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 8415 DAG.getConstant(VTBits, MVT::i8)); 8416 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8417 AndNode, DAG.getConstant(0, MVT::i8)); 8418 8419 SDValue Hi, Lo; 8420 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8421 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 8422 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 8423 8424 if (Op.getOpcode() == ISD::SHL_PARTS) { 8425 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 8426 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 8427 } else { 8428 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 8429 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 8430 } 8431 8432 SDValue Ops[2] = { Lo, Hi }; 8433 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl); 8434} 8435 8436SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 8437 SelectionDAG &DAG) const { 8438 EVT SrcVT = Op.getOperand(0).getValueType(); 8439 8440 if (SrcVT.isVector()) 8441 return SDValue(); 8442 8443 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 8444 "Unknown SINT_TO_FP to lower!"); 8445 8446 // These are really Legal; return the operand so the caller accepts it as 8447 // Legal. 8448 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 8449 return Op; 8450 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 8451 Subtarget->is64Bit()) { 8452 return Op; 8453 } 8454 8455 SDLoc dl(Op); 8456 unsigned Size = SrcVT.getSizeInBits()/8; 8457 MachineFunction &MF = DAG.getMachineFunction(); 8458 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 8459 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8460 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8461 StackSlot, 8462 MachinePointerInfo::getFixedStack(SSFI), 8463 false, false, 0); 8464 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 8465} 8466 8467SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 8468 SDValue StackSlot, 8469 SelectionDAG &DAG) const { 8470 // Build the FILD 8471 SDLoc DL(Op); 8472 SDVTList Tys; 8473 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 8474 if (useSSE) 8475 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 8476 else 8477 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 8478 8479 unsigned ByteSize = SrcVT.getSizeInBits()/8; 8480 8481 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 8482 MachineMemOperand *MMO; 8483 if (FI) { 8484 int SSFI = FI->getIndex(); 8485 MMO = 8486 DAG.getMachineFunction() 8487 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8488 MachineMemOperand::MOLoad, ByteSize, ByteSize); 8489 } else { 8490 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 8491 StackSlot = StackSlot.getOperand(1); 8492 } 8493 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 8494 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 8495 X86ISD::FILD, DL, 8496 Tys, Ops, array_lengthof(Ops), 8497 SrcVT, MMO); 8498 8499 if (useSSE) { 8500 Chain = Result.getValue(1); 8501 SDValue InFlag = Result.getValue(2); 8502 8503 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 8504 // shouldn't be necessary except that RFP cannot be live across 8505 // multiple blocks. When stackifier is fixed, they can be uncoupled. 8506 MachineFunction &MF = DAG.getMachineFunction(); 8507 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 8508 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 8509 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8510 Tys = DAG.getVTList(MVT::Other); 8511 SDValue Ops[] = { 8512 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 8513 }; 8514 MachineMemOperand *MMO = 8515 DAG.getMachineFunction() 8516 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8517 MachineMemOperand::MOStore, SSFISize, SSFISize); 8518 8519 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 8520 Ops, array_lengthof(Ops), 8521 Op.getValueType(), MMO); 8522 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 8523 MachinePointerInfo::getFixedStack(SSFI), 8524 false, false, false, 0); 8525 } 8526 8527 return Result; 8528} 8529 8530// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 8531SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 8532 SelectionDAG &DAG) const { 8533 // This algorithm is not obvious. Here it is what we're trying to output: 8534 /* 8535 movq %rax, %xmm0 8536 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 8537 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 8538 #ifdef __SSE3__ 8539 haddpd %xmm0, %xmm0 8540 #else 8541 pshufd $0x4e, %xmm0, %xmm1 8542 addpd %xmm1, %xmm0 8543 #endif 8544 */ 8545 8546 SDLoc dl(Op); 8547 LLVMContext *Context = DAG.getContext(); 8548 8549 // Build some magic constants. 8550 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 8551 Constant *C0 = ConstantDataVector::get(*Context, CV0); 8552 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 8553 8554 SmallVector<Constant*,2> CV1; 8555 CV1.push_back( 8556 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8557 APInt(64, 0x4330000000000000ULL)))); 8558 CV1.push_back( 8559 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8560 APInt(64, 0x4530000000000000ULL)))); 8561 Constant *C1 = ConstantVector::get(CV1); 8562 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 8563 8564 // Load the 64-bit value into an XMM register. 8565 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 8566 Op.getOperand(0)); 8567 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 8568 MachinePointerInfo::getConstantPool(), 8569 false, false, false, 16); 8570 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 8571 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 8572 CLod0); 8573 8574 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 8575 MachinePointerInfo::getConstantPool(), 8576 false, false, false, 16); 8577 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 8578 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 8579 SDValue Result; 8580 8581 if (Subtarget->hasSSE3()) { 8582 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 8583 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 8584 } else { 8585 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 8586 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 8587 S2F, 0x4E, DAG); 8588 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 8589 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 8590 Sub); 8591 } 8592 8593 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 8594 DAG.getIntPtrConstant(0)); 8595} 8596 8597// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 8598SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 8599 SelectionDAG &DAG) const { 8600 SDLoc dl(Op); 8601 // FP constant to bias correct the final result. 8602 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 8603 MVT::f64); 8604 8605 // Load the 32-bit value into an XMM register. 8606 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 8607 Op.getOperand(0)); 8608 8609 // Zero out the upper parts of the register. 8610 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 8611 8612 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8613 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 8614 DAG.getIntPtrConstant(0)); 8615 8616 // Or the load with the bias. 8617 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 8618 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8619 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8620 MVT::v2f64, Load)), 8621 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8623 MVT::v2f64, Bias))); 8624 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8625 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 8626 DAG.getIntPtrConstant(0)); 8627 8628 // Subtract the bias. 8629 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 8630 8631 // Handle final rounding. 8632 EVT DestVT = Op.getValueType(); 8633 8634 if (DestVT.bitsLT(MVT::f64)) 8635 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 8636 DAG.getIntPtrConstant(0)); 8637 if (DestVT.bitsGT(MVT::f64)) 8638 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 8639 8640 // Handle final rounding. 8641 return Sub; 8642} 8643 8644SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op, 8645 SelectionDAG &DAG) const { 8646 SDValue N0 = Op.getOperand(0); 8647 EVT SVT = N0.getValueType(); 8648 SDLoc dl(Op); 8649 8650 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 || 8651 SVT == MVT::v8i8 || SVT == MVT::v8i16) && 8652 "Custom UINT_TO_FP is not supported!"); 8653 8654 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, 8655 SVT.getVectorNumElements()); 8656 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), 8657 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); 8658} 8659 8660SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 8661 SelectionDAG &DAG) const { 8662 SDValue N0 = Op.getOperand(0); 8663 SDLoc dl(Op); 8664 8665 if (Op.getValueType().isVector()) 8666 return lowerUINT_TO_FP_vec(Op, DAG); 8667 8668 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 8669 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 8670 // the optimization here. 8671 if (DAG.SignBitIsZero(N0)) 8672 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 8673 8674 EVT SrcVT = N0.getValueType(); 8675 EVT DstVT = Op.getValueType(); 8676 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 8677 return LowerUINT_TO_FP_i64(Op, DAG); 8678 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 8679 return LowerUINT_TO_FP_i32(Op, DAG); 8680 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 8681 return SDValue(); 8682 8683 // Make a 64-bit buffer, and use it to build an FILD. 8684 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 8685 if (SrcVT == MVT::i32) { 8686 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 8687 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 8688 getPointerTy(), StackSlot, WordOff); 8689 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8690 StackSlot, MachinePointerInfo(), 8691 false, false, 0); 8692 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 8693 OffsetSlot, MachinePointerInfo(), 8694 false, false, 0); 8695 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 8696 return Fild; 8697 } 8698 8699 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 8700 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8701 StackSlot, MachinePointerInfo(), 8702 false, false, 0); 8703 // For i64 source, we need to add the appropriate power of 2 if the input 8704 // was negative. This is the same as the optimization in 8705 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 8706 // we must be careful to do the computation in x87 extended precision, not 8707 // in SSE. (The generic code can't know it's OK to do this, or how to.) 8708 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 8709 MachineMemOperand *MMO = 8710 DAG.getMachineFunction() 8711 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8712 MachineMemOperand::MOLoad, 8, 8); 8713 8714 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 8715 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 8716 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 8717 array_lengthof(Ops), MVT::i64, MMO); 8718 8719 APInt FF(32, 0x5F800000ULL); 8720 8721 // Check whether the sign bit is set. 8722 SDValue SignSet = DAG.getSetCC(dl, 8723 getSetCCResultType(*DAG.getContext(), MVT::i64), 8724 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 8725 ISD::SETLT); 8726 8727 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 8728 SDValue FudgePtr = DAG.getConstantPool( 8729 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 8730 getPointerTy()); 8731 8732 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 8733 SDValue Zero = DAG.getIntPtrConstant(0); 8734 SDValue Four = DAG.getIntPtrConstant(4); 8735 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 8736 Zero, Four); 8737 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 8738 8739 // Load the value out, extending it from f32 to f80. 8740 // FIXME: Avoid the extend by constructing the right constant pool? 8741 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 8742 FudgePtr, MachinePointerInfo::getConstantPool(), 8743 MVT::f32, false, false, 4); 8744 // Extend everything to 80 bits to force it to be done on x87. 8745 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 8746 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 8747} 8748 8749std::pair<SDValue,SDValue> 8750X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 8751 bool IsSigned, bool IsReplace) const { 8752 SDLoc DL(Op); 8753 8754 EVT DstTy = Op.getValueType(); 8755 8756 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 8757 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 8758 DstTy = MVT::i64; 8759 } 8760 8761 assert(DstTy.getSimpleVT() <= MVT::i64 && 8762 DstTy.getSimpleVT() >= MVT::i16 && 8763 "Unknown FP_TO_INT to lower!"); 8764 8765 // These are really Legal. 8766 if (DstTy == MVT::i32 && 8767 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8768 return std::make_pair(SDValue(), SDValue()); 8769 if (Subtarget->is64Bit() && 8770 DstTy == MVT::i64 && 8771 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8772 return std::make_pair(SDValue(), SDValue()); 8773 8774 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 8775 // stack slot, or into the FTOL runtime function. 8776 MachineFunction &MF = DAG.getMachineFunction(); 8777 unsigned MemSize = DstTy.getSizeInBits()/8; 8778 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8779 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8780 8781 unsigned Opc; 8782 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 8783 Opc = X86ISD::WIN_FTOL; 8784 else 8785 switch (DstTy.getSimpleVT().SimpleTy) { 8786 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8787 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8788 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8789 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8790 } 8791 8792 SDValue Chain = DAG.getEntryNode(); 8793 SDValue Value = Op.getOperand(0); 8794 EVT TheVT = Op.getOperand(0).getValueType(); 8795 // FIXME This causes a redundant load/store if the SSE-class value is already 8796 // in memory, such as if it is on the callstack. 8797 if (isScalarFPTypeInSSEReg(TheVT)) { 8798 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8799 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8800 MachinePointerInfo::getFixedStack(SSFI), 8801 false, false, 0); 8802 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8803 SDValue Ops[] = { 8804 Chain, StackSlot, DAG.getValueType(TheVT) 8805 }; 8806 8807 MachineMemOperand *MMO = 8808 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8809 MachineMemOperand::MOLoad, MemSize, MemSize); 8810 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 8811 array_lengthof(Ops), DstTy, MMO); 8812 Chain = Value.getValue(1); 8813 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8814 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8815 } 8816 8817 MachineMemOperand *MMO = 8818 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8819 MachineMemOperand::MOStore, MemSize, MemSize); 8820 8821 if (Opc != X86ISD::WIN_FTOL) { 8822 // Build the FP_TO_INT*_IN_MEM 8823 SDValue Ops[] = { Chain, Value, StackSlot }; 8824 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8825 Ops, array_lengthof(Ops), DstTy, 8826 MMO); 8827 return std::make_pair(FIST, StackSlot); 8828 } else { 8829 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 8830 DAG.getVTList(MVT::Other, MVT::Glue), 8831 Chain, Value); 8832 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 8833 MVT::i32, ftol.getValue(1)); 8834 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 8835 MVT::i32, eax.getValue(2)); 8836 SDValue Ops[] = { eax, edx }; 8837 SDValue pair = IsReplace 8838 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops)) 8839 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL); 8840 return std::make_pair(pair, SDValue()); 8841 } 8842} 8843 8844static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG, 8845 const X86Subtarget *Subtarget) { 8846 MVT VT = Op->getSimpleValueType(0); 8847 SDValue In = Op->getOperand(0); 8848 MVT InVT = In.getSimpleValueType(); 8849 SDLoc dl(Op); 8850 8851 // Optimize vectors in AVX mode: 8852 // 8853 // v8i16 -> v8i32 8854 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 8855 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 8856 // Concat upper and lower parts. 8857 // 8858 // v4i32 -> v4i64 8859 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 8860 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 8861 // Concat upper and lower parts. 8862 // 8863 8864 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) && 8865 ((VT != MVT::v4i64) || (InVT != MVT::v4i32))) 8866 return SDValue(); 8867 8868 if (Subtarget->hasInt256()) 8869 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In); 8870 8871 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl); 8872 SDValue Undef = DAG.getUNDEF(InVT); 8873 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND; 8874 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8875 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8876 8877 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(), 8878 VT.getVectorNumElements()/2); 8879 8880 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 8881 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 8882 8883 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 8884} 8885 8886static SDValue LowerZERO_EXTEND_AVX512(SDValue Op, 8887 SelectionDAG &DAG) { 8888 MVT VT = Op->getValueType(0).getSimpleVT(); 8889 SDValue In = Op->getOperand(0); 8890 MVT InVT = In.getValueType().getSimpleVT(); 8891 SDLoc DL(Op); 8892 unsigned int NumElts = VT.getVectorNumElements(); 8893 if (NumElts != 8 && NumElts != 16) 8894 return SDValue(); 8895 8896 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) 8897 return DAG.getNode(X86ISD::VZEXT, DL, VT, In); 8898 8899 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32; 8900 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8901 // Now we have only mask extension 8902 assert(InVT.getVectorElementType() == MVT::i1); 8903 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType()); 8904 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue(); 8905 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy()); 8906 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 8907 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP, 8908 MachinePointerInfo::getConstantPool(), 8909 false, false, false, Alignment); 8910 8911 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld); 8912 if (VT.is512BitVector()) 8913 return Brcst; 8914 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst); 8915} 8916 8917static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget, 8918 SelectionDAG &DAG) { 8919 if (Subtarget->hasFp256()) { 8920 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8921 if (Res.getNode()) 8922 return Res; 8923 } 8924 8925 return SDValue(); 8926} 8927 8928static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget, 8929 SelectionDAG &DAG) { 8930 SDLoc DL(Op); 8931 MVT VT = Op.getSimpleValueType(); 8932 SDValue In = Op.getOperand(0); 8933 MVT SVT = In.getSimpleValueType(); 8934 8935 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1) 8936 return LowerZERO_EXTEND_AVX512(Op, DAG); 8937 8938 if (Subtarget->hasFp256()) { 8939 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8940 if (Res.getNode()) 8941 return Res; 8942 } 8943 8944 if (!VT.is256BitVector() || !SVT.is128BitVector() || 8945 VT.getVectorNumElements() != SVT.getVectorNumElements()) 8946 return SDValue(); 8947 8948 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!"); 8949 8950 // AVX2 has better support of integer extending. 8951 if (Subtarget->hasInt256()) 8952 return DAG.getNode(X86ISD::VZEXT, DL, VT, In); 8953 8954 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In); 8955 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1}; 8956 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, 8957 DAG.getVectorShuffle(MVT::v8i16, DL, In, 8958 DAG.getUNDEF(MVT::v8i16), 8959 &Mask[0])); 8960 8961 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi); 8962} 8963 8964SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { 8965 SDLoc DL(Op); 8966 MVT VT = Op.getSimpleValueType(); 8967 SDValue In = Op.getOperand(0); 8968 MVT InVT = In.getSimpleValueType(); 8969 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() && 8970 "Invalid TRUNCATE operation"); 8971 8972 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) { 8973 if (VT.getVectorElementType().getSizeInBits() >=8) 8974 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In); 8975 8976 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type"); 8977 unsigned NumElts = InVT.getVectorNumElements(); 8978 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type"); 8979 if (InVT.getSizeInBits() < 512) { 8980 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64; 8981 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); 8982 InVT = ExtVT; 8983 } 8984 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType()); 8985 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue(); 8986 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 8987 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 8988 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP, 8989 MachinePointerInfo::getConstantPool(), 8990 false, false, false, Alignment); 8991 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld); 8992 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In); 8993 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And); 8994 } 8995 8996 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) { 8997 // On AVX2, v4i64 -> v4i32 becomes VPERMD. 8998 if (Subtarget->hasInt256()) { 8999 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 9000 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In); 9001 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32), 9002 ShufMask); 9003 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In, 9004 DAG.getIntPtrConstant(0)); 9005 } 9006 9007 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS. 9008 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 9009 DAG.getIntPtrConstant(0)); 9010 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 9011 DAG.getIntPtrConstant(2)); 9012 9013 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 9014 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 9015 9016 // The PSHUFD mask: 9017 static const int ShufMask1[] = {0, 2, 0, 0}; 9018 SDValue Undef = DAG.getUNDEF(VT); 9019 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1); 9020 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1); 9021 9022 // The MOVLHPS mask: 9023 static const int ShufMask2[] = {0, 1, 4, 5}; 9024 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2); 9025 } 9026 9027 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) { 9028 // On AVX2, v8i32 -> v8i16 becomed PSHUFB. 9029 if (Subtarget->hasInt256()) { 9030 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In); 9031 9032 SmallVector<SDValue,32> pshufbMask; 9033 for (unsigned i = 0; i < 2; ++i) { 9034 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 9035 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 9036 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 9037 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 9038 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 9039 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 9040 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 9041 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 9042 for (unsigned j = 0; j < 8; ++j) 9043 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 9044 } 9045 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, 9046 &pshufbMask[0], 32); 9047 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV); 9048 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In); 9049 9050 static const int ShufMask[] = {0, 2, -1, -1}; 9051 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64), 9052 &ShufMask[0]); 9053 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 9054 DAG.getIntPtrConstant(0)); 9055 return DAG.getNode(ISD::BITCAST, DL, VT, In); 9056 } 9057 9058 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 9059 DAG.getIntPtrConstant(0)); 9060 9061 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 9062 DAG.getIntPtrConstant(4)); 9063 9064 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo); 9065 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi); 9066 9067 // The PSHUFB mask: 9068 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 9069 -1, -1, -1, -1, -1, -1, -1, -1}; 9070 9071 SDValue Undef = DAG.getUNDEF(MVT::v16i8); 9072 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1); 9073 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1); 9074 9075 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 9076 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 9077 9078 // The MOVLHPS Mask: 9079 static const int ShufMask2[] = {0, 1, 4, 5}; 9080 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2); 9081 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res); 9082 } 9083 9084 // Handle truncation of V256 to V128 using shuffles. 9085 if (!VT.is128BitVector() || !InVT.is256BitVector()) 9086 return SDValue(); 9087 9088 assert(Subtarget->hasFp256() && "256-bit vector without AVX!"); 9089 9090 unsigned NumElems = VT.getVectorNumElements(); 9091 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 9092 NumElems * 2); 9093 9094 SmallVector<int, 16> MaskVec(NumElems * 2, -1); 9095 // Prepare truncation shuffle mask 9096 for (unsigned i = 0; i != NumElems; ++i) 9097 MaskVec[i] = i * 2; 9098 SDValue V = DAG.getVectorShuffle(NVT, DL, 9099 DAG.getNode(ISD::BITCAST, DL, NVT, In), 9100 DAG.getUNDEF(NVT), &MaskVec[0]); 9101 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, 9102 DAG.getIntPtrConstant(0)); 9103} 9104 9105SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 9106 SelectionDAG &DAG) const { 9107 MVT VT = Op.getSimpleValueType(); 9108 if (VT.isVector()) { 9109 if (VT == MVT::v8i16) 9110 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, 9111 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op), 9112 MVT::v8i32, Op.getOperand(0))); 9113 return SDValue(); 9114 } 9115 9116 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 9117 /*IsSigned=*/ true, /*IsReplace=*/ false); 9118 SDValue FIST = Vals.first, StackSlot = Vals.second; 9119 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 9120 if (FIST.getNode() == 0) return Op; 9121 9122 if (StackSlot.getNode()) 9123 // Load the result. 9124 return DAG.getLoad(Op.getValueType(), SDLoc(Op), 9125 FIST, StackSlot, MachinePointerInfo(), 9126 false, false, false, 0); 9127 9128 // The node is the result. 9129 return FIST; 9130} 9131 9132SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 9133 SelectionDAG &DAG) const { 9134 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 9135 /*IsSigned=*/ false, /*IsReplace=*/ false); 9136 SDValue FIST = Vals.first, StackSlot = Vals.second; 9137 assert(FIST.getNode() && "Unexpected failure"); 9138 9139 if (StackSlot.getNode()) 9140 // Load the result. 9141 return DAG.getLoad(Op.getValueType(), SDLoc(Op), 9142 FIST, StackSlot, MachinePointerInfo(), 9143 false, false, false, 0); 9144 9145 // The node is the result. 9146 return FIST; 9147} 9148 9149static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) { 9150 SDLoc DL(Op); 9151 MVT VT = Op.getSimpleValueType(); 9152 SDValue In = Op.getOperand(0); 9153 MVT SVT = In.getSimpleValueType(); 9154 9155 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!"); 9156 9157 return DAG.getNode(X86ISD::VFPEXT, DL, VT, 9158 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32, 9159 In, DAG.getUNDEF(SVT))); 9160} 9161 9162SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 9163 LLVMContext *Context = DAG.getContext(); 9164 SDLoc dl(Op); 9165 MVT VT = Op.getSimpleValueType(); 9166 MVT EltVT = VT; 9167 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 9168 if (VT.isVector()) { 9169 EltVT = VT.getVectorElementType(); 9170 NumElts = VT.getVectorNumElements(); 9171 } 9172 Constant *C; 9173 if (EltVT == MVT::f64) 9174 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 9175 APInt(64, ~(1ULL << 63)))); 9176 else 9177 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle, 9178 APInt(32, ~(1U << 31)))); 9179 C = ConstantVector::getSplat(NumElts, C); 9180 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 9181 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9182 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9183 MachinePointerInfo::getConstantPool(), 9184 false, false, false, Alignment); 9185 if (VT.isVector()) { 9186 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 9187 return DAG.getNode(ISD::BITCAST, dl, VT, 9188 DAG.getNode(ISD::AND, dl, ANDVT, 9189 DAG.getNode(ISD::BITCAST, dl, ANDVT, 9190 Op.getOperand(0)), 9191 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask))); 9192 } 9193 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 9194} 9195 9196SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 9197 LLVMContext *Context = DAG.getContext(); 9198 SDLoc dl(Op); 9199 MVT VT = Op.getSimpleValueType(); 9200 MVT EltVT = VT; 9201 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 9202 if (VT.isVector()) { 9203 EltVT = VT.getVectorElementType(); 9204 NumElts = VT.getVectorNumElements(); 9205 } 9206 Constant *C; 9207 if (EltVT == MVT::f64) 9208 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 9209 APInt(64, 1ULL << 63))); 9210 else 9211 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle, 9212 APInt(32, 1U << 31))); 9213 C = ConstantVector::getSplat(NumElts, C); 9214 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 9215 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9216 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9217 MachinePointerInfo::getConstantPool(), 9218 false, false, false, Alignment); 9219 if (VT.isVector()) { 9220 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64); 9221 return DAG.getNode(ISD::BITCAST, dl, VT, 9222 DAG.getNode(ISD::XOR, dl, XORVT, 9223 DAG.getNode(ISD::BITCAST, dl, XORVT, 9224 Op.getOperand(0)), 9225 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 9226 } 9227 9228 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 9229} 9230 9231SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 9232 LLVMContext *Context = DAG.getContext(); 9233 SDValue Op0 = Op.getOperand(0); 9234 SDValue Op1 = Op.getOperand(1); 9235 SDLoc dl(Op); 9236 MVT VT = Op.getSimpleValueType(); 9237 MVT SrcVT = Op1.getSimpleValueType(); 9238 9239 // If second operand is smaller, extend it first. 9240 if (SrcVT.bitsLT(VT)) { 9241 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 9242 SrcVT = VT; 9243 } 9244 // And if it is bigger, shrink it first. 9245 if (SrcVT.bitsGT(VT)) { 9246 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 9247 SrcVT = VT; 9248 } 9249 9250 // At this point the operands and the result should have the same 9251 // type, and that won't be f80 since that is not custom lowered. 9252 9253 // First get the sign bit of second operand. 9254 SmallVector<Constant*,4> CV; 9255 if (SrcVT == MVT::f64) { 9256 const fltSemantics &Sem = APFloat::IEEEdouble; 9257 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63)))); 9258 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0)))); 9259 } else { 9260 const fltSemantics &Sem = APFloat::IEEEsingle; 9261 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31)))); 9262 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9263 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9264 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9265 } 9266 Constant *C = ConstantVector::get(CV); 9267 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9268 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 9269 MachinePointerInfo::getConstantPool(), 9270 false, false, false, 16); 9271 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 9272 9273 // Shift sign bit right or left if the two operands have different types. 9274 if (SrcVT.bitsGT(VT)) { 9275 // Op0 is MVT::f32, Op1 is MVT::f64. 9276 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 9277 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 9278 DAG.getConstant(32, MVT::i32)); 9279 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 9280 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 9281 DAG.getIntPtrConstant(0)); 9282 } 9283 9284 // Clear first operand sign bit. 9285 CV.clear(); 9286 if (VT == MVT::f64) { 9287 const fltSemantics &Sem = APFloat::IEEEdouble; 9288 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, 9289 APInt(64, ~(1ULL << 63))))); 9290 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0)))); 9291 } else { 9292 const fltSemantics &Sem = APFloat::IEEEsingle; 9293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, 9294 APInt(32, ~(1U << 31))))); 9295 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9296 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9297 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 9298 } 9299 C = ConstantVector::get(CV); 9300 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9301 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9302 MachinePointerInfo::getConstantPool(), 9303 false, false, false, 16); 9304 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 9305 9306 // Or the value with the sign bit. 9307 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 9308} 9309 9310static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) { 9311 SDValue N0 = Op.getOperand(0); 9312 SDLoc dl(Op); 9313 MVT VT = Op.getSimpleValueType(); 9314 9315 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 9316 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 9317 DAG.getConstant(1, VT)); 9318 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 9319} 9320 9321// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able. 9322// 9323static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget, 9324 SelectionDAG &DAG) { 9325 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree."); 9326 9327 if (!Subtarget->hasSSE41()) 9328 return SDValue(); 9329 9330 if (!Op->hasOneUse()) 9331 return SDValue(); 9332 9333 SDNode *N = Op.getNode(); 9334 SDLoc DL(N); 9335 9336 SmallVector<SDValue, 8> Opnds; 9337 DenseMap<SDValue, unsigned> VecInMap; 9338 EVT VT = MVT::Other; 9339 9340 // Recognize a special case where a vector is casted into wide integer to 9341 // test all 0s. 9342 Opnds.push_back(N->getOperand(0)); 9343 Opnds.push_back(N->getOperand(1)); 9344 9345 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) { 9346 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot; 9347 // BFS traverse all OR'd operands. 9348 if (I->getOpcode() == ISD::OR) { 9349 Opnds.push_back(I->getOperand(0)); 9350 Opnds.push_back(I->getOperand(1)); 9351 // Re-evaluate the number of nodes to be traversed. 9352 e += 2; // 2 more nodes (LHS and RHS) are pushed. 9353 continue; 9354 } 9355 9356 // Quit if a non-EXTRACT_VECTOR_ELT 9357 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 9358 return SDValue(); 9359 9360 // Quit if without a constant index. 9361 SDValue Idx = I->getOperand(1); 9362 if (!isa<ConstantSDNode>(Idx)) 9363 return SDValue(); 9364 9365 SDValue ExtractedFromVec = I->getOperand(0); 9366 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec); 9367 if (M == VecInMap.end()) { 9368 VT = ExtractedFromVec.getValueType(); 9369 // Quit if not 128/256-bit vector. 9370 if (!VT.is128BitVector() && !VT.is256BitVector()) 9371 return SDValue(); 9372 // Quit if not the same type. 9373 if (VecInMap.begin() != VecInMap.end() && 9374 VT != VecInMap.begin()->first.getValueType()) 9375 return SDValue(); 9376 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first; 9377 } 9378 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue(); 9379 } 9380 9381 assert((VT.is128BitVector() || VT.is256BitVector()) && 9382 "Not extracted from 128-/256-bit vector."); 9383 9384 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U; 9385 SmallVector<SDValue, 8> VecIns; 9386 9387 for (DenseMap<SDValue, unsigned>::const_iterator 9388 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) { 9389 // Quit if not all elements are used. 9390 if (I->second != FullMask) 9391 return SDValue(); 9392 VecIns.push_back(I->first); 9393 } 9394 9395 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 9396 9397 // Cast all vectors into TestVT for PTEST. 9398 for (unsigned i = 0, e = VecIns.size(); i < e; ++i) 9399 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]); 9400 9401 // If more than one full vectors are evaluated, OR them first before PTEST. 9402 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) { 9403 // Each iteration will OR 2 nodes and append the result until there is only 9404 // 1 node left, i.e. the final OR'd value of all vectors. 9405 SDValue LHS = VecIns[Slot]; 9406 SDValue RHS = VecIns[Slot + 1]; 9407 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS)); 9408 } 9409 9410 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, 9411 VecIns.back(), VecIns.back()); 9412} 9413 9414/// Emit nodes that will be selected as "test Op0,Op0", or something 9415/// equivalent. 9416SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 9417 SelectionDAG &DAG) const { 9418 SDLoc dl(Op); 9419 9420 // CF and OF aren't always set the way we want. Determine which 9421 // of these we need. 9422 bool NeedCF = false; 9423 bool NeedOF = false; 9424 switch (X86CC) { 9425 default: break; 9426 case X86::COND_A: case X86::COND_AE: 9427 case X86::COND_B: case X86::COND_BE: 9428 NeedCF = true; 9429 break; 9430 case X86::COND_G: case X86::COND_GE: 9431 case X86::COND_L: case X86::COND_LE: 9432 case X86::COND_O: case X86::COND_NO: 9433 NeedOF = true; 9434 break; 9435 } 9436 9437 // See if we can use the EFLAGS value from the operand instead of 9438 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 9439 // we prove that the arithmetic won't overflow, we can't use OF or CF. 9440 if (Op.getResNo() != 0 || NeedOF || NeedCF) 9441 // Emit a CMP with 0, which is the TEST pattern. 9442 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 9443 DAG.getConstant(0, Op.getValueType())); 9444 9445 unsigned Opcode = 0; 9446 unsigned NumOperands = 0; 9447 9448 // Truncate operations may prevent the merge of the SETCC instruction 9449 // and the arithmetic instruction before it. Attempt to truncate the operands 9450 // of the arithmetic instruction and use a reduced bit-width instruction. 9451 bool NeedTruncation = false; 9452 SDValue ArithOp = Op; 9453 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { 9454 SDValue Arith = Op->getOperand(0); 9455 // Both the trunc and the arithmetic op need to have one user each. 9456 if (Arith->hasOneUse()) 9457 switch (Arith.getOpcode()) { 9458 default: break; 9459 case ISD::ADD: 9460 case ISD::SUB: 9461 case ISD::AND: 9462 case ISD::OR: 9463 case ISD::XOR: { 9464 NeedTruncation = true; 9465 ArithOp = Arith; 9466 } 9467 } 9468 } 9469 9470 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation 9471 // which may be the result of a CAST. We use the variable 'Op', which is the 9472 // non-casted variable when we check for possible users. 9473 switch (ArithOp.getOpcode()) { 9474 case ISD::ADD: 9475 // Due to an isel shortcoming, be conservative if this add is likely to be 9476 // selected as part of a load-modify-store instruction. When the root node 9477 // in a match is a store, isel doesn't know how to remap non-chain non-flag 9478 // uses of other nodes in the match, such as the ADD in this case. This 9479 // leads to the ADD being left around and reselected, with the result being 9480 // two adds in the output. Alas, even if none our users are stores, that 9481 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 9482 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 9483 // climbing the DAG back to the root, and it doesn't seem to be worth the 9484 // effort. 9485 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 9486 UE = Op.getNode()->use_end(); UI != UE; ++UI) 9487 if (UI->getOpcode() != ISD::CopyToReg && 9488 UI->getOpcode() != ISD::SETCC && 9489 UI->getOpcode() != ISD::STORE) 9490 goto default_case; 9491 9492 if (ConstantSDNode *C = 9493 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) { 9494 // An add of one will be selected as an INC. 9495 if (C->getAPIntValue() == 1) { 9496 Opcode = X86ISD::INC; 9497 NumOperands = 1; 9498 break; 9499 } 9500 9501 // An add of negative one (subtract of one) will be selected as a DEC. 9502 if (C->getAPIntValue().isAllOnesValue()) { 9503 Opcode = X86ISD::DEC; 9504 NumOperands = 1; 9505 break; 9506 } 9507 } 9508 9509 // Otherwise use a regular EFLAGS-setting add. 9510 Opcode = X86ISD::ADD; 9511 NumOperands = 2; 9512 break; 9513 case ISD::AND: { 9514 // If the primary and result isn't used, don't bother using X86ISD::AND, 9515 // because a TEST instruction will be better. 9516 bool NonFlagUse = false; 9517 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 9518 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 9519 SDNode *User = *UI; 9520 unsigned UOpNo = UI.getOperandNo(); 9521 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 9522 // Look pass truncate. 9523 UOpNo = User->use_begin().getOperandNo(); 9524 User = *User->use_begin(); 9525 } 9526 9527 if (User->getOpcode() != ISD::BRCOND && 9528 User->getOpcode() != ISD::SETCC && 9529 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) { 9530 NonFlagUse = true; 9531 break; 9532 } 9533 } 9534 9535 if (!NonFlagUse) 9536 break; 9537 } 9538 // FALL THROUGH 9539 case ISD::SUB: 9540 case ISD::OR: 9541 case ISD::XOR: 9542 // Due to the ISEL shortcoming noted above, be conservative if this op is 9543 // likely to be selected as part of a load-modify-store instruction. 9544 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 9545 UE = Op.getNode()->use_end(); UI != UE; ++UI) 9546 if (UI->getOpcode() == ISD::STORE) 9547 goto default_case; 9548 9549 // Otherwise use a regular EFLAGS-setting instruction. 9550 switch (ArithOp.getOpcode()) { 9551 default: llvm_unreachable("unexpected operator!"); 9552 case ISD::SUB: Opcode = X86ISD::SUB; break; 9553 case ISD::XOR: Opcode = X86ISD::XOR; break; 9554 case ISD::AND: Opcode = X86ISD::AND; break; 9555 case ISD::OR: { 9556 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) { 9557 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG); 9558 if (EFLAGS.getNode()) 9559 return EFLAGS; 9560 } 9561 Opcode = X86ISD::OR; 9562 break; 9563 } 9564 } 9565 9566 NumOperands = 2; 9567 break; 9568 case X86ISD::ADD: 9569 case X86ISD::SUB: 9570 case X86ISD::INC: 9571 case X86ISD::DEC: 9572 case X86ISD::OR: 9573 case X86ISD::XOR: 9574 case X86ISD::AND: 9575 return SDValue(Op.getNode(), 1); 9576 default: 9577 default_case: 9578 break; 9579 } 9580 9581 // If we found that truncation is beneficial, perform the truncation and 9582 // update 'Op'. 9583 if (NeedTruncation) { 9584 EVT VT = Op.getValueType(); 9585 SDValue WideVal = Op->getOperand(0); 9586 EVT WideVT = WideVal.getValueType(); 9587 unsigned ConvertedOp = 0; 9588 // Use a target machine opcode to prevent further DAGCombine 9589 // optimizations that may separate the arithmetic operations 9590 // from the setcc node. 9591 switch (WideVal.getOpcode()) { 9592 default: break; 9593 case ISD::ADD: ConvertedOp = X86ISD::ADD; break; 9594 case ISD::SUB: ConvertedOp = X86ISD::SUB; break; 9595 case ISD::AND: ConvertedOp = X86ISD::AND; break; 9596 case ISD::OR: ConvertedOp = X86ISD::OR; break; 9597 case ISD::XOR: ConvertedOp = X86ISD::XOR; break; 9598 } 9599 9600 if (ConvertedOp) { 9601 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9602 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { 9603 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0)); 9604 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1)); 9605 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1); 9606 } 9607 } 9608 } 9609 9610 if (Opcode == 0) 9611 // Emit a CMP with 0, which is the TEST pattern. 9612 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 9613 DAG.getConstant(0, Op.getValueType())); 9614 9615 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 9616 SmallVector<SDValue, 4> Ops; 9617 for (unsigned i = 0; i != NumOperands; ++i) 9618 Ops.push_back(Op.getOperand(i)); 9619 9620 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 9621 DAG.ReplaceAllUsesWith(Op, New); 9622 return SDValue(New.getNode(), 1); 9623} 9624 9625/// Emit nodes that will be selected as "cmp Op0,Op1", or something 9626/// equivalent. 9627SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 9628 SelectionDAG &DAG) const { 9629 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 9630 if (C->getAPIntValue() == 0) 9631 return EmitTest(Op0, X86CC, DAG); 9632 9633 SDLoc dl(Op0); 9634 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || 9635 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { 9636 // Use SUB instead of CMP to enable CSE between SUB and CMP. 9637 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); 9638 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, 9639 Op0, Op1); 9640 return SDValue(Sub.getNode(), 1); 9641 } 9642 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 9643} 9644 9645/// Convert a comparison if required by the subtarget. 9646SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 9647 SelectionDAG &DAG) const { 9648 // If the subtarget does not support the FUCOMI instruction, floating-point 9649 // comparisons have to be converted. 9650 if (Subtarget->hasCMov() || 9651 Cmp.getOpcode() != X86ISD::CMP || 9652 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 9653 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 9654 return Cmp; 9655 9656 // The instruction selector will select an FUCOM instruction instead of 9657 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 9658 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 9659 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 9660 SDLoc dl(Cmp); 9661 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 9662 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 9663 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 9664 DAG.getConstant(8, MVT::i8)); 9665 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 9666 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 9667} 9668 9669static bool isAllOnes(SDValue V) { 9670 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9671 return C && C->isAllOnesValue(); 9672} 9673 9674/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 9675/// if it's possible. 9676SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 9677 SDLoc dl, SelectionDAG &DAG) const { 9678 SDValue Op0 = And.getOperand(0); 9679 SDValue Op1 = And.getOperand(1); 9680 if (Op0.getOpcode() == ISD::TRUNCATE) 9681 Op0 = Op0.getOperand(0); 9682 if (Op1.getOpcode() == ISD::TRUNCATE) 9683 Op1 = Op1.getOperand(0); 9684 9685 SDValue LHS, RHS; 9686 if (Op1.getOpcode() == ISD::SHL) 9687 std::swap(Op0, Op1); 9688 if (Op0.getOpcode() == ISD::SHL) { 9689 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 9690 if (And00C->getZExtValue() == 1) { 9691 // If we looked past a truncate, check that it's only truncating away 9692 // known zeros. 9693 unsigned BitWidth = Op0.getValueSizeInBits(); 9694 unsigned AndBitWidth = And.getValueSizeInBits(); 9695 if (BitWidth > AndBitWidth) { 9696 APInt Zeros, Ones; 9697 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 9698 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 9699 return SDValue(); 9700 } 9701 LHS = Op1; 9702 RHS = Op0.getOperand(1); 9703 } 9704 } else if (Op1.getOpcode() == ISD::Constant) { 9705 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 9706 uint64_t AndRHSVal = AndRHS->getZExtValue(); 9707 SDValue AndLHS = Op0; 9708 9709 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 9710 LHS = AndLHS.getOperand(0); 9711 RHS = AndLHS.getOperand(1); 9712 } 9713 9714 // Use BT if the immediate can't be encoded in a TEST instruction. 9715 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 9716 LHS = AndLHS; 9717 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 9718 } 9719 } 9720 9721 if (LHS.getNode()) { 9722 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 9723 // instruction. Since the shift amount is in-range-or-undefined, we know 9724 // that doing a bittest on the i32 value is ok. We extend to i32 because 9725 // the encoding for the i16 version is larger than the i32 version. 9726 // Also promote i16 to i32 for performance / code size reason. 9727 if (LHS.getValueType() == MVT::i8 || 9728 LHS.getValueType() == MVT::i16) 9729 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 9730 9731 // If the operand types disagree, extend the shift amount to match. Since 9732 // BT ignores high bits (like shifts) we can use anyextend. 9733 if (LHS.getValueType() != RHS.getValueType()) 9734 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 9735 9736 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 9737 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 9738 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9739 DAG.getConstant(Cond, MVT::i8), BT); 9740 } 9741 9742 return SDValue(); 9743} 9744 9745/// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point 9746/// mask CMPs. 9747static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0, 9748 SDValue &Op1) { 9749 unsigned SSECC; 9750 bool Swap = false; 9751 9752 // SSE Condition code mapping: 9753 // 0 - EQ 9754 // 1 - LT 9755 // 2 - LE 9756 // 3 - UNORD 9757 // 4 - NEQ 9758 // 5 - NLT 9759 // 6 - NLE 9760 // 7 - ORD 9761 switch (SetCCOpcode) { 9762 default: llvm_unreachable("Unexpected SETCC condition"); 9763 case ISD::SETOEQ: 9764 case ISD::SETEQ: SSECC = 0; break; 9765 case ISD::SETOGT: 9766 case ISD::SETGT: Swap = true; // Fallthrough 9767 case ISD::SETLT: 9768 case ISD::SETOLT: SSECC = 1; break; 9769 case ISD::SETOGE: 9770 case ISD::SETGE: Swap = true; // Fallthrough 9771 case ISD::SETLE: 9772 case ISD::SETOLE: SSECC = 2; break; 9773 case ISD::SETUO: SSECC = 3; break; 9774 case ISD::SETUNE: 9775 case ISD::SETNE: SSECC = 4; break; 9776 case ISD::SETULE: Swap = true; // Fallthrough 9777 case ISD::SETUGE: SSECC = 5; break; 9778 case ISD::SETULT: Swap = true; // Fallthrough 9779 case ISD::SETUGT: SSECC = 6; break; 9780 case ISD::SETO: SSECC = 7; break; 9781 case ISD::SETUEQ: 9782 case ISD::SETONE: SSECC = 8; break; 9783 } 9784 if (Swap) 9785 std::swap(Op0, Op1); 9786 9787 return SSECC; 9788} 9789 9790// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 9791// ones, and then concatenate the result back. 9792static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 9793 MVT VT = Op.getSimpleValueType(); 9794 9795 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && 9796 "Unsupported value type for operation"); 9797 9798 unsigned NumElems = VT.getVectorNumElements(); 9799 SDLoc dl(Op); 9800 SDValue CC = Op.getOperand(2); 9801 9802 // Extract the LHS vectors 9803 SDValue LHS = Op.getOperand(0); 9804 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 9805 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 9806 9807 // Extract the RHS vectors 9808 SDValue RHS = Op.getOperand(1); 9809 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 9810 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 9811 9812 // Issue the operation on the smaller types and concatenate the result back 9813 MVT EltVT = VT.getVectorElementType(); 9814 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9815 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9816 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 9817 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 9818} 9819 9820static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) { 9821 SDValue Op0 = Op.getOperand(0); 9822 SDValue Op1 = Op.getOperand(1); 9823 SDValue CC = Op.getOperand(2); 9824 MVT VT = Op.getSimpleValueType(); 9825 9826 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 && 9827 Op.getValueType().getScalarType() == MVT::i1 && 9828 "Cannot set masked compare for this operation"); 9829 9830 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 9831 SDLoc dl(Op); 9832 9833 bool Unsigned = false; 9834 unsigned SSECC; 9835 switch (SetCCOpcode) { 9836 default: llvm_unreachable("Unexpected SETCC condition"); 9837 case ISD::SETNE: SSECC = 4; break; 9838 case ISD::SETEQ: SSECC = 0; break; 9839 case ISD::SETUGT: Unsigned = true; 9840 case ISD::SETGT: SSECC = 6; break; // NLE 9841 case ISD::SETULT: Unsigned = true; 9842 case ISD::SETLT: SSECC = 1; break; 9843 case ISD::SETUGE: Unsigned = true; 9844 case ISD::SETGE: SSECC = 5; break; // NLT 9845 case ISD::SETULE: Unsigned = true; 9846 case ISD::SETLE: SSECC = 2; break; 9847 } 9848 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM; 9849 return DAG.getNode(Opc, dl, VT, Op0, Op1, 9850 DAG.getConstant(SSECC, MVT::i8)); 9851 9852} 9853 9854static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, 9855 SelectionDAG &DAG) { 9856 SDValue Op0 = Op.getOperand(0); 9857 SDValue Op1 = Op.getOperand(1); 9858 SDValue CC = Op.getOperand(2); 9859 MVT VT = Op.getSimpleValueType(); 9860 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 9861 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint(); 9862 SDLoc dl(Op); 9863 9864 if (isFP) { 9865#ifndef NDEBUG 9866 MVT EltVT = Op0.getSimpleValueType().getVectorElementType(); 9867 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 9868#endif 9869 9870 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1); 9871 unsigned Opc = X86ISD::CMPP; 9872 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) { 9873 assert(VT.getVectorNumElements() <= 16); 9874 Opc = X86ISD::CMPM; 9875 } 9876 // In the two special cases we can't handle, emit two comparisons. 9877 if (SSECC == 8) { 9878 unsigned CC0, CC1; 9879 unsigned CombineOpc; 9880 if (SetCCOpcode == ISD::SETUEQ) { 9881 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR; 9882 } else { 9883 assert(SetCCOpcode == ISD::SETONE); 9884 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND; 9885 } 9886 9887 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1, 9888 DAG.getConstant(CC0, MVT::i8)); 9889 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1, 9890 DAG.getConstant(CC1, MVT::i8)); 9891 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); 9892 } 9893 // Handle all other FP comparisons here. 9894 return DAG.getNode(Opc, dl, VT, Op0, Op1, 9895 DAG.getConstant(SSECC, MVT::i8)); 9896 } 9897 9898 // Break 256-bit integer vector compare into smaller ones. 9899 if (VT.is256BitVector() && !Subtarget->hasInt256()) 9900 return Lower256IntVSETCC(Op, DAG); 9901 9902 bool MaskResult = (VT.getVectorElementType() == MVT::i1); 9903 EVT OpVT = Op1.getValueType(); 9904 if (Subtarget->hasAVX512()) { 9905 if (Op1.getValueType().is512BitVector() || 9906 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32)) 9907 return LowerIntVSETCC_AVX512(Op, DAG); 9908 9909 // In AVX-512 architecture setcc returns mask with i1 elements, 9910 // But there is no compare instruction for i8 and i16 elements. 9911 // We are not talking about 512-bit operands in this case, these 9912 // types are illegal. 9913 if (MaskResult && 9914 (OpVT.getVectorElementType().getSizeInBits() < 32 && 9915 OpVT.getVectorElementType().getSizeInBits() >= 8)) 9916 return DAG.getNode(ISD::TRUNCATE, dl, VT, 9917 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC)); 9918 } 9919 9920 // We are handling one of the integer comparisons here. Since SSE only has 9921 // GT and EQ comparisons for integer, swapping operands and multiple 9922 // operations may be required for some comparisons. 9923 unsigned Opc; 9924 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false; 9925 9926 switch (SetCCOpcode) { 9927 default: llvm_unreachable("Unexpected SETCC condition"); 9928 case ISD::SETNE: Invert = true; 9929 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break; 9930 case ISD::SETLT: Swap = true; 9931 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break; 9932 case ISD::SETGE: Swap = true; 9933 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; 9934 Invert = true; break; 9935 case ISD::SETULT: Swap = true; 9936 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; 9937 FlipSigns = true; break; 9938 case ISD::SETUGE: Swap = true; 9939 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; 9940 FlipSigns = true; Invert = true; break; 9941 } 9942 9943 // Special case: Use min/max operations for SETULE/SETUGE 9944 MVT VET = VT.getVectorElementType(); 9945 bool hasMinMax = 9946 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32)) 9947 || (Subtarget->hasSSE2() && (VET == MVT::i8)); 9948 9949 if (hasMinMax) { 9950 switch (SetCCOpcode) { 9951 default: break; 9952 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break; 9953 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break; 9954 } 9955 9956 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; } 9957 } 9958 9959 if (Swap) 9960 std::swap(Op0, Op1); 9961 9962 // Check that the operation in question is available (most are plain SSE2, 9963 // but PCMPGTQ and PCMPEQQ have different requirements). 9964 if (VT == MVT::v2i64) { 9965 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) { 9966 assert(Subtarget->hasSSE2() && "Don't know how to lower!"); 9967 9968 // First cast everything to the right type. 9969 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); 9970 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); 9971 9972 // Since SSE has no unsigned integer comparisons, we need to flip the sign 9973 // bits of the inputs before performing those operations. The lower 9974 // compare is always unsigned. 9975 SDValue SB; 9976 if (FlipSigns) { 9977 SB = DAG.getConstant(0x80000000U, MVT::v4i32); 9978 } else { 9979 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32); 9980 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32); 9981 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 9982 Sign, Zero, Sign, Zero); 9983 } 9984 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); 9985 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); 9986 9987 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) 9988 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); 9989 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1); 9990 9991 // Create masks for only the low parts/high parts of the 64 bit integers. 9992 static const int MaskHi[] = { 1, 1, 3, 3 }; 9993 static const int MaskLo[] = { 0, 0, 2, 2 }; 9994 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi); 9995 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); 9996 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); 9997 9998 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo); 9999 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi); 10000 10001 if (Invert) 10002 Result = DAG.getNOT(dl, Result, MVT::v4i32); 10003 10004 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 10005 } 10006 10007 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) { 10008 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with 10009 // pcmpeqd + pshufd + pand. 10010 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!"); 10011 10012 // First cast everything to the right type. 10013 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); 10014 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); 10015 10016 // Do the compare. 10017 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1); 10018 10019 // Make sure the lower and upper halves are both all-ones. 10020 static const int Mask[] = { 1, 0, 3, 2 }; 10021 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask); 10022 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf); 10023 10024 if (Invert) 10025 Result = DAG.getNOT(dl, Result, MVT::v4i32); 10026 10027 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 10028 } 10029 } 10030 10031 // Since SSE has no unsigned integer comparisons, we need to flip the sign 10032 // bits of the inputs before performing those operations. 10033 if (FlipSigns) { 10034 EVT EltVT = VT.getVectorElementType(); 10035 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT); 10036 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB); 10037 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB); 10038 } 10039 10040 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 10041 10042 // If the logical-not of the result is required, perform that now. 10043 if (Invert) 10044 Result = DAG.getNOT(dl, Result, VT); 10045 10046 if (MinMax) 10047 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result); 10048 10049 return Result; 10050} 10051 10052SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 10053 10054 MVT VT = Op.getSimpleValueType(); 10055 10056 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG); 10057 10058 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer"); 10059 SDValue Op0 = Op.getOperand(0); 10060 SDValue Op1 = Op.getOperand(1); 10061 SDLoc dl(Op); 10062 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 10063 10064 // Optimize to BT if possible. 10065 // Lower (X & (1 << N)) == 0 to BT(X, N). 10066 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 10067 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 10068 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 10069 Op1.getOpcode() == ISD::Constant && 10070 cast<ConstantSDNode>(Op1)->isNullValue() && 10071 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 10072 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 10073 if (NewSetCC.getNode()) 10074 return NewSetCC; 10075 } 10076 10077 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 10078 // these. 10079 if (Op1.getOpcode() == ISD::Constant && 10080 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 10081 cast<ConstantSDNode>(Op1)->isNullValue()) && 10082 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 10083 10084 // If the input is a setcc, then reuse the input setcc or use a new one with 10085 // the inverted condition. 10086 if (Op0.getOpcode() == X86ISD::SETCC) { 10087 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 10088 bool Invert = (CC == ISD::SETNE) ^ 10089 cast<ConstantSDNode>(Op1)->isNullValue(); 10090 if (!Invert) return Op0; 10091 10092 CCode = X86::GetOppositeBranchCondition(CCode); 10093 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10094 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 10095 } 10096 } 10097 10098 bool isFP = Op1.getSimpleValueType().isFloatingPoint(); 10099 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 10100 if (X86CC == X86::COND_INVALID) 10101 return SDValue(); 10102 10103 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 10104 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 10105 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10106 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 10107} 10108 10109// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 10110static bool isX86LogicalCmp(SDValue Op) { 10111 unsigned Opc = Op.getNode()->getOpcode(); 10112 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 10113 Opc == X86ISD::SAHF) 10114 return true; 10115 if (Op.getResNo() == 1 && 10116 (Opc == X86ISD::ADD || 10117 Opc == X86ISD::SUB || 10118 Opc == X86ISD::ADC || 10119 Opc == X86ISD::SBB || 10120 Opc == X86ISD::SMUL || 10121 Opc == X86ISD::UMUL || 10122 Opc == X86ISD::INC || 10123 Opc == X86ISD::DEC || 10124 Opc == X86ISD::OR || 10125 Opc == X86ISD::XOR || 10126 Opc == X86ISD::AND)) 10127 return true; 10128 10129 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 10130 return true; 10131 10132 return false; 10133} 10134 10135static bool isZero(SDValue V) { 10136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 10137 return C && C->isNullValue(); 10138} 10139 10140static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) { 10141 if (V.getOpcode() != ISD::TRUNCATE) 10142 return false; 10143 10144 SDValue VOp0 = V.getOperand(0); 10145 unsigned InBits = VOp0.getValueSizeInBits(); 10146 unsigned Bits = V.getValueSizeInBits(); 10147 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits)); 10148} 10149 10150SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 10151 bool addTest = true; 10152 SDValue Cond = Op.getOperand(0); 10153 SDValue Op1 = Op.getOperand(1); 10154 SDValue Op2 = Op.getOperand(2); 10155 SDLoc DL(Op); 10156 EVT VT = Op1.getValueType(); 10157 SDValue CC; 10158 10159 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops 10160 // are available. Otherwise fp cmovs get lowered into a less efficient branch 10161 // sequence later on. 10162 if (Cond.getOpcode() == ISD::SETCC && 10163 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) || 10164 (Subtarget->hasSSE1() && VT == MVT::f32)) && 10165 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) { 10166 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1); 10167 int SSECC = translateX86FSETCC( 10168 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1); 10169 10170 if (SSECC != 8) { 10171 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd; 10172 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1, 10173 DAG.getConstant(SSECC, MVT::i8)); 10174 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2); 10175 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1); 10176 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And); 10177 } 10178 } 10179 10180 if (Cond.getOpcode() == ISD::SETCC) { 10181 SDValue NewCond = LowerSETCC(Cond, DAG); 10182 if (NewCond.getNode()) 10183 Cond = NewCond; 10184 } 10185 10186 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 10187 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 10188 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 10189 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 10190 if (Cond.getOpcode() == X86ISD::SETCC && 10191 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 10192 isZero(Cond.getOperand(1).getOperand(1))) { 10193 SDValue Cmp = Cond.getOperand(1); 10194 10195 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 10196 10197 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 10198 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 10199 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 10200 10201 SDValue CmpOp0 = Cmp.getOperand(0); 10202 // Apply further optimizations for special cases 10203 // (select (x != 0), -1, 0) -> neg & sbb 10204 // (select (x == 0), 0, -1) -> neg & sbb 10205 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 10206 if (YC->isNullValue() && 10207 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 10208 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 10209 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 10210 DAG.getConstant(0, CmpOp0.getValueType()), 10211 CmpOp0); 10212 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 10213 DAG.getConstant(X86::COND_B, MVT::i8), 10214 SDValue(Neg.getNode(), 1)); 10215 return Res; 10216 } 10217 10218 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 10219 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 10220 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 10221 10222 SDValue Res = // Res = 0 or -1. 10223 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 10224 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 10225 10226 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 10227 Res = DAG.getNOT(DL, Res, Res.getValueType()); 10228 10229 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 10230 if (N2C == 0 || !N2C->isNullValue()) 10231 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 10232 return Res; 10233 } 10234 } 10235 10236 // Look past (and (setcc_carry (cmp ...)), 1). 10237 if (Cond.getOpcode() == ISD::AND && 10238 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 10239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 10240 if (C && C->getAPIntValue() == 1) 10241 Cond = Cond.getOperand(0); 10242 } 10243 10244 // If condition flag is set by a X86ISD::CMP, then use it as the condition 10245 // setting operand in place of the X86ISD::SETCC. 10246 unsigned CondOpcode = Cond.getOpcode(); 10247 if (CondOpcode == X86ISD::SETCC || 10248 CondOpcode == X86ISD::SETCC_CARRY) { 10249 CC = Cond.getOperand(0); 10250 10251 SDValue Cmp = Cond.getOperand(1); 10252 unsigned Opc = Cmp.getOpcode(); 10253 MVT VT = Op.getSimpleValueType(); 10254 10255 bool IllegalFPCMov = false; 10256 if (VT.isFloatingPoint() && !VT.isVector() && 10257 !isScalarFPTypeInSSEReg(VT)) // FPStack? 10258 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 10259 10260 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 10261 Opc == X86ISD::BT) { // FIXME 10262 Cond = Cmp; 10263 addTest = false; 10264 } 10265 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 10266 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 10267 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 10268 Cond.getOperand(0).getValueType() != MVT::i8)) { 10269 SDValue LHS = Cond.getOperand(0); 10270 SDValue RHS = Cond.getOperand(1); 10271 unsigned X86Opcode; 10272 unsigned X86Cond; 10273 SDVTList VTs; 10274 switch (CondOpcode) { 10275 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 10276 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 10277 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 10278 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 10279 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 10280 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 10281 default: llvm_unreachable("unexpected overflowing operator"); 10282 } 10283 if (CondOpcode == ISD::UMULO) 10284 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 10285 MVT::i32); 10286 else 10287 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 10288 10289 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 10290 10291 if (CondOpcode == ISD::UMULO) 10292 Cond = X86Op.getValue(2); 10293 else 10294 Cond = X86Op.getValue(1); 10295 10296 CC = DAG.getConstant(X86Cond, MVT::i8); 10297 addTest = false; 10298 } 10299 10300 if (addTest) { 10301 // Look pass the truncate if the high bits are known zero. 10302 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 10303 Cond = Cond.getOperand(0); 10304 10305 // We know the result of AND is compared against zero. Try to match 10306 // it to BT. 10307 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 10308 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 10309 if (NewSetCC.getNode()) { 10310 CC = NewSetCC.getOperand(0); 10311 Cond = NewSetCC.getOperand(1); 10312 addTest = false; 10313 } 10314 } 10315 } 10316 10317 if (addTest) { 10318 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 10319 Cond = EmitTest(Cond, X86::COND_NE, DAG); 10320 } 10321 10322 // a < b ? -1 : 0 -> RES = ~setcc_carry 10323 // a < b ? 0 : -1 -> RES = setcc_carry 10324 // a >= b ? -1 : 0 -> RES = setcc_carry 10325 // a >= b ? 0 : -1 -> RES = ~setcc_carry 10326 if (Cond.getOpcode() == X86ISD::SUB) { 10327 Cond = ConvertCmpIfNecessary(Cond, DAG); 10328 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 10329 10330 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 10331 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 10332 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 10333 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 10334 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 10335 return DAG.getNOT(DL, Res, Res.getValueType()); 10336 return Res; 10337 } 10338 } 10339 10340 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate 10341 // widen the cmov and push the truncate through. This avoids introducing a new 10342 // branch during isel and doesn't add any extensions. 10343 if (Op.getValueType() == MVT::i8 && 10344 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) { 10345 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0); 10346 if (T1.getValueType() == T2.getValueType() && 10347 // Blacklist CopyFromReg to avoid partial register stalls. 10348 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ 10349 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue); 10350 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond); 10351 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); 10352 } 10353 } 10354 10355 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 10356 // condition is true. 10357 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 10358 SDValue Ops[] = { Op2, Op1, CC, Cond }; 10359 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 10360} 10361 10362static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) { 10363 MVT VT = Op->getSimpleValueType(0); 10364 SDValue In = Op->getOperand(0); 10365 MVT InVT = In.getSimpleValueType(); 10366 SDLoc dl(Op); 10367 10368 unsigned int NumElts = VT.getVectorNumElements(); 10369 if (NumElts != 8 && NumElts != 16) 10370 return SDValue(); 10371 10372 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) 10373 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); 10374 10375 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10376 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type"); 10377 10378 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32; 10379 Constant *C = ConstantInt::get(*DAG.getContext(), 10380 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits())); 10381 10382 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy()); 10383 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 10384 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP, 10385 MachinePointerInfo::getConstantPool(), 10386 false, false, false, Alignment); 10387 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld); 10388 if (VT.is512BitVector()) 10389 return Brcst; 10390 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst); 10391} 10392 10393static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget, 10394 SelectionDAG &DAG) { 10395 MVT VT = Op->getSimpleValueType(0); 10396 SDValue In = Op->getOperand(0); 10397 MVT InVT = In.getSimpleValueType(); 10398 SDLoc dl(Op); 10399 10400 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1) 10401 return LowerSIGN_EXTEND_AVX512(Op, DAG); 10402 10403 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) && 10404 (VT != MVT::v8i32 || InVT != MVT::v8i16)) 10405 return SDValue(); 10406 10407 if (Subtarget->hasInt256()) 10408 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In); 10409 10410 // Optimize vectors in AVX mode 10411 // Sign extend v8i16 to v8i32 and 10412 // v4i32 to v4i64 10413 // 10414 // Divide input vector into two parts 10415 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 10416 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 10417 // concat the vectors to original VT 10418 10419 unsigned NumElems = InVT.getVectorNumElements(); 10420 SDValue Undef = DAG.getUNDEF(InVT); 10421 10422 SmallVector<int,8> ShufMask1(NumElems, -1); 10423 for (unsigned i = 0; i != NumElems/2; ++i) 10424 ShufMask1[i] = i; 10425 10426 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]); 10427 10428 SmallVector<int,8> ShufMask2(NumElems, -1); 10429 for (unsigned i = 0; i != NumElems/2; ++i) 10430 ShufMask2[i] = i + NumElems/2; 10431 10432 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]); 10433 10434 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(), 10435 VT.getVectorNumElements()/2); 10436 10437 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 10438 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 10439 10440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 10441} 10442 10443// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 10444// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 10445// from the AND / OR. 10446static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 10447 Opc = Op.getOpcode(); 10448 if (Opc != ISD::OR && Opc != ISD::AND) 10449 return false; 10450 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 10451 Op.getOperand(0).hasOneUse() && 10452 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 10453 Op.getOperand(1).hasOneUse()); 10454} 10455 10456// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 10457// 1 and that the SETCC node has a single use. 10458static bool isXor1OfSetCC(SDValue Op) { 10459 if (Op.getOpcode() != ISD::XOR) 10460 return false; 10461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 10462 if (N1C && N1C->getAPIntValue() == 1) { 10463 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 10464 Op.getOperand(0).hasOneUse(); 10465 } 10466 return false; 10467} 10468 10469SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 10470 bool addTest = true; 10471 SDValue Chain = Op.getOperand(0); 10472 SDValue Cond = Op.getOperand(1); 10473 SDValue Dest = Op.getOperand(2); 10474 SDLoc dl(Op); 10475 SDValue CC; 10476 bool Inverted = false; 10477 10478 if (Cond.getOpcode() == ISD::SETCC) { 10479 // Check for setcc([su]{add,sub,mul}o == 0). 10480 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 10481 isa<ConstantSDNode>(Cond.getOperand(1)) && 10482 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 10483 Cond.getOperand(0).getResNo() == 1 && 10484 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 10485 Cond.getOperand(0).getOpcode() == ISD::UADDO || 10486 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 10487 Cond.getOperand(0).getOpcode() == ISD::USUBO || 10488 Cond.getOperand(0).getOpcode() == ISD::SMULO || 10489 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 10490 Inverted = true; 10491 Cond = Cond.getOperand(0); 10492 } else { 10493 SDValue NewCond = LowerSETCC(Cond, DAG); 10494 if (NewCond.getNode()) 10495 Cond = NewCond; 10496 } 10497 } 10498#if 0 10499 // FIXME: LowerXALUO doesn't handle these!! 10500 else if (Cond.getOpcode() == X86ISD::ADD || 10501 Cond.getOpcode() == X86ISD::SUB || 10502 Cond.getOpcode() == X86ISD::SMUL || 10503 Cond.getOpcode() == X86ISD::UMUL) 10504 Cond = LowerXALUO(Cond, DAG); 10505#endif 10506 10507 // Look pass (and (setcc_carry (cmp ...)), 1). 10508 if (Cond.getOpcode() == ISD::AND && 10509 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 10510 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 10511 if (C && C->getAPIntValue() == 1) 10512 Cond = Cond.getOperand(0); 10513 } 10514 10515 // If condition flag is set by a X86ISD::CMP, then use it as the condition 10516 // setting operand in place of the X86ISD::SETCC. 10517 unsigned CondOpcode = Cond.getOpcode(); 10518 if (CondOpcode == X86ISD::SETCC || 10519 CondOpcode == X86ISD::SETCC_CARRY) { 10520 CC = Cond.getOperand(0); 10521 10522 SDValue Cmp = Cond.getOperand(1); 10523 unsigned Opc = Cmp.getOpcode(); 10524 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 10525 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 10526 Cond = Cmp; 10527 addTest = false; 10528 } else { 10529 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 10530 default: break; 10531 case X86::COND_O: 10532 case X86::COND_B: 10533 // These can only come from an arithmetic instruction with overflow, 10534 // e.g. SADDO, UADDO. 10535 Cond = Cond.getNode()->getOperand(1); 10536 addTest = false; 10537 break; 10538 } 10539 } 10540 } 10541 CondOpcode = Cond.getOpcode(); 10542 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 10543 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 10544 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 10545 Cond.getOperand(0).getValueType() != MVT::i8)) { 10546 SDValue LHS = Cond.getOperand(0); 10547 SDValue RHS = Cond.getOperand(1); 10548 unsigned X86Opcode; 10549 unsigned X86Cond; 10550 SDVTList VTs; 10551 switch (CondOpcode) { 10552 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 10553 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 10554 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 10555 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 10556 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 10557 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 10558 default: llvm_unreachable("unexpected overflowing operator"); 10559 } 10560 if (Inverted) 10561 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 10562 if (CondOpcode == ISD::UMULO) 10563 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 10564 MVT::i32); 10565 else 10566 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 10567 10568 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 10569 10570 if (CondOpcode == ISD::UMULO) 10571 Cond = X86Op.getValue(2); 10572 else 10573 Cond = X86Op.getValue(1); 10574 10575 CC = DAG.getConstant(X86Cond, MVT::i8); 10576 addTest = false; 10577 } else { 10578 unsigned CondOpc; 10579 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 10580 SDValue Cmp = Cond.getOperand(0).getOperand(1); 10581 if (CondOpc == ISD::OR) { 10582 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 10583 // two branches instead of an explicit OR instruction with a 10584 // separate test. 10585 if (Cmp == Cond.getOperand(1).getOperand(1) && 10586 isX86LogicalCmp(Cmp)) { 10587 CC = Cond.getOperand(0).getOperand(0); 10588 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10589 Chain, Dest, CC, Cmp); 10590 CC = Cond.getOperand(1).getOperand(0); 10591 Cond = Cmp; 10592 addTest = false; 10593 } 10594 } else { // ISD::AND 10595 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 10596 // two branches instead of an explicit AND instruction with a 10597 // separate test. However, we only do this if this block doesn't 10598 // have a fall-through edge, because this requires an explicit 10599 // jmp when the condition is false. 10600 if (Cmp == Cond.getOperand(1).getOperand(1) && 10601 isX86LogicalCmp(Cmp) && 10602 Op.getNode()->hasOneUse()) { 10603 X86::CondCode CCode = 10604 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 10605 CCode = X86::GetOppositeBranchCondition(CCode); 10606 CC = DAG.getConstant(CCode, MVT::i8); 10607 SDNode *User = *Op.getNode()->use_begin(); 10608 // Look for an unconditional branch following this conditional branch. 10609 // We need this because we need to reverse the successors in order 10610 // to implement FCMP_OEQ. 10611 if (User->getOpcode() == ISD::BR) { 10612 SDValue FalseBB = User->getOperand(1); 10613 SDNode *NewBR = 10614 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 10615 assert(NewBR == User); 10616 (void)NewBR; 10617 Dest = FalseBB; 10618 10619 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10620 Chain, Dest, CC, Cmp); 10621 X86::CondCode CCode = 10622 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 10623 CCode = X86::GetOppositeBranchCondition(CCode); 10624 CC = DAG.getConstant(CCode, MVT::i8); 10625 Cond = Cmp; 10626 addTest = false; 10627 } 10628 } 10629 } 10630 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 10631 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 10632 // It should be transformed during dag combiner except when the condition 10633 // is set by a arithmetics with overflow node. 10634 X86::CondCode CCode = 10635 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 10636 CCode = X86::GetOppositeBranchCondition(CCode); 10637 CC = DAG.getConstant(CCode, MVT::i8); 10638 Cond = Cond.getOperand(0).getOperand(1); 10639 addTest = false; 10640 } else if (Cond.getOpcode() == ISD::SETCC && 10641 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 10642 // For FCMP_OEQ, we can emit 10643 // two branches instead of an explicit AND instruction with a 10644 // separate test. However, we only do this if this block doesn't 10645 // have a fall-through edge, because this requires an explicit 10646 // jmp when the condition is false. 10647 if (Op.getNode()->hasOneUse()) { 10648 SDNode *User = *Op.getNode()->use_begin(); 10649 // Look for an unconditional branch following this conditional branch. 10650 // We need this because we need to reverse the successors in order 10651 // to implement FCMP_OEQ. 10652 if (User->getOpcode() == ISD::BR) { 10653 SDValue FalseBB = User->getOperand(1); 10654 SDNode *NewBR = 10655 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 10656 assert(NewBR == User); 10657 (void)NewBR; 10658 Dest = FalseBB; 10659 10660 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 10661 Cond.getOperand(0), Cond.getOperand(1)); 10662 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 10663 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 10664 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10665 Chain, Dest, CC, Cmp); 10666 CC = DAG.getConstant(X86::COND_P, MVT::i8); 10667 Cond = Cmp; 10668 addTest = false; 10669 } 10670 } 10671 } else if (Cond.getOpcode() == ISD::SETCC && 10672 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 10673 // For FCMP_UNE, we can emit 10674 // two branches instead of an explicit AND instruction with a 10675 // separate test. However, we only do this if this block doesn't 10676 // have a fall-through edge, because this requires an explicit 10677 // jmp when the condition is false. 10678 if (Op.getNode()->hasOneUse()) { 10679 SDNode *User = *Op.getNode()->use_begin(); 10680 // Look for an unconditional branch following this conditional branch. 10681 // We need this because we need to reverse the successors in order 10682 // to implement FCMP_UNE. 10683 if (User->getOpcode() == ISD::BR) { 10684 SDValue FalseBB = User->getOperand(1); 10685 SDNode *NewBR = 10686 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 10687 assert(NewBR == User); 10688 (void)NewBR; 10689 10690 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 10691 Cond.getOperand(0), Cond.getOperand(1)); 10692 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 10693 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 10694 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10695 Chain, Dest, CC, Cmp); 10696 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 10697 Cond = Cmp; 10698 addTest = false; 10699 Dest = FalseBB; 10700 } 10701 } 10702 } 10703 } 10704 10705 if (addTest) { 10706 // Look pass the truncate if the high bits are known zero. 10707 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 10708 Cond = Cond.getOperand(0); 10709 10710 // We know the result of AND is compared against zero. Try to match 10711 // it to BT. 10712 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 10713 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 10714 if (NewSetCC.getNode()) { 10715 CC = NewSetCC.getOperand(0); 10716 Cond = NewSetCC.getOperand(1); 10717 addTest = false; 10718 } 10719 } 10720 } 10721 10722 if (addTest) { 10723 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 10724 Cond = EmitTest(Cond, X86::COND_NE, DAG); 10725 } 10726 Cond = ConvertCmpIfNecessary(Cond, DAG); 10727 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10728 Chain, Dest, CC, Cond); 10729} 10730 10731// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 10732// Calls to _alloca is needed to probe the stack when allocating more than 4k 10733// bytes in one go. Touching the stack at 4K increments is necessary to ensure 10734// that the guard pages used by the OS virtual memory manager are allocated in 10735// correct sequence. 10736SDValue 10737X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 10738 SelectionDAG &DAG) const { 10739 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 10740 getTargetMachine().Options.EnableSegmentedStacks) && 10741 "This should be used only on Windows targets or when segmented stacks " 10742 "are being used"); 10743 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 10744 SDLoc dl(Op); 10745 10746 // Get the inputs. 10747 SDValue Chain = Op.getOperand(0); 10748 SDValue Size = Op.getOperand(1); 10749 // FIXME: Ensure alignment here 10750 10751 bool Is64Bit = Subtarget->is64Bit(); 10752 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 10753 10754 if (getTargetMachine().Options.EnableSegmentedStacks) { 10755 MachineFunction &MF = DAG.getMachineFunction(); 10756 MachineRegisterInfo &MRI = MF.getRegInfo(); 10757 10758 if (Is64Bit) { 10759 // The 64 bit implementation of segmented stacks needs to clobber both r10 10760 // r11. This makes it impossible to use it along with nested parameters. 10761 const Function *F = MF.getFunction(); 10762 10763 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 10764 I != E; ++I) 10765 if (I->hasNestAttr()) 10766 report_fatal_error("Cannot use segmented stacks with functions that " 10767 "have nested arguments."); 10768 } 10769 10770 const TargetRegisterClass *AddrRegClass = 10771 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 10772 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 10773 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 10774 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 10775 DAG.getRegister(Vreg, SPTy)); 10776 SDValue Ops1[2] = { Value, Chain }; 10777 return DAG.getMergeValues(Ops1, 2, dl); 10778 } else { 10779 SDValue Flag; 10780 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 10781 10782 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 10783 Flag = Chain.getValue(1); 10784 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 10785 10786 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 10787 Flag = Chain.getValue(1); 10788 10789 const X86RegisterInfo *RegInfo = 10790 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 10791 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 10792 SPTy).getValue(1); 10793 10794 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 10795 return DAG.getMergeValues(Ops1, 2, dl); 10796 } 10797} 10798 10799SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 10800 MachineFunction &MF = DAG.getMachineFunction(); 10801 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 10802 10803 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10804 SDLoc DL(Op); 10805 10806 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 10807 // vastart just stores the address of the VarArgsFrameIndex slot into the 10808 // memory location argument. 10809 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10810 getPointerTy()); 10811 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 10812 MachinePointerInfo(SV), false, false, 0); 10813 } 10814 10815 // __va_list_tag: 10816 // gp_offset (0 - 6 * 8) 10817 // fp_offset (48 - 48 + 8 * 16) 10818 // overflow_arg_area (point to parameters coming in memory). 10819 // reg_save_area 10820 SmallVector<SDValue, 8> MemOps; 10821 SDValue FIN = Op.getOperand(1); 10822 // Store gp_offset 10823 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 10824 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 10825 MVT::i32), 10826 FIN, MachinePointerInfo(SV), false, false, 0); 10827 MemOps.push_back(Store); 10828 10829 // Store fp_offset 10830 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10831 FIN, DAG.getIntPtrConstant(4)); 10832 Store = DAG.getStore(Op.getOperand(0), DL, 10833 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 10834 MVT::i32), 10835 FIN, MachinePointerInfo(SV, 4), false, false, 0); 10836 MemOps.push_back(Store); 10837 10838 // Store ptr to overflow_arg_area 10839 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10840 FIN, DAG.getIntPtrConstant(4)); 10841 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10842 getPointerTy()); 10843 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 10844 MachinePointerInfo(SV, 8), 10845 false, false, 0); 10846 MemOps.push_back(Store); 10847 10848 // Store ptr to reg_save_area. 10849 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10850 FIN, DAG.getIntPtrConstant(8)); 10851 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 10852 getPointerTy()); 10853 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 10854 MachinePointerInfo(SV, 16), false, false, 0); 10855 MemOps.push_back(Store); 10856 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 10857 &MemOps[0], MemOps.size()); 10858} 10859 10860SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 10861 assert(Subtarget->is64Bit() && 10862 "LowerVAARG only handles 64-bit va_arg!"); 10863 assert((Subtarget->isTargetLinux() || 10864 Subtarget->isTargetDarwin()) && 10865 "Unhandled target in LowerVAARG"); 10866 assert(Op.getNode()->getNumOperands() == 4); 10867 SDValue Chain = Op.getOperand(0); 10868 SDValue SrcPtr = Op.getOperand(1); 10869 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10870 unsigned Align = Op.getConstantOperandVal(3); 10871 SDLoc dl(Op); 10872 10873 EVT ArgVT = Op.getNode()->getValueType(0); 10874 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 10875 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy); 10876 uint8_t ArgMode; 10877 10878 // Decide which area this value should be read from. 10879 // TODO: Implement the AMD64 ABI in its entirety. This simple 10880 // selection mechanism works only for the basic types. 10881 if (ArgVT == MVT::f80) { 10882 llvm_unreachable("va_arg for f80 not yet implemented"); 10883 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 10884 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 10885 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 10886 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 10887 } else { 10888 llvm_unreachable("Unhandled argument type in LowerVAARG"); 10889 } 10890 10891 if (ArgMode == 2) { 10892 // Sanity Check: Make sure using fp_offset makes sense. 10893 assert(!getTargetMachine().Options.UseSoftFloat && 10894 !(DAG.getMachineFunction() 10895 .getFunction()->getAttributes() 10896 .hasAttribute(AttributeSet::FunctionIndex, 10897 Attribute::NoImplicitFloat)) && 10898 Subtarget->hasSSE1()); 10899 } 10900 10901 // Insert VAARG_64 node into the DAG 10902 // VAARG_64 returns two values: Variable Argument Address, Chain 10903 SmallVector<SDValue, 11> InstOps; 10904 InstOps.push_back(Chain); 10905 InstOps.push_back(SrcPtr); 10906 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 10907 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 10908 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 10909 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 10910 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 10911 VTs, &InstOps[0], InstOps.size(), 10912 MVT::i64, 10913 MachinePointerInfo(SV), 10914 /*Align=*/0, 10915 /*Volatile=*/false, 10916 /*ReadMem=*/true, 10917 /*WriteMem=*/true); 10918 Chain = VAARG.getValue(1); 10919 10920 // Load the next argument and return it 10921 return DAG.getLoad(ArgVT, dl, 10922 Chain, 10923 VAARG, 10924 MachinePointerInfo(), 10925 false, false, false, 0); 10926} 10927 10928static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, 10929 SelectionDAG &DAG) { 10930 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 10931 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 10932 SDValue Chain = Op.getOperand(0); 10933 SDValue DstPtr = Op.getOperand(1); 10934 SDValue SrcPtr = Op.getOperand(2); 10935 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 10936 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 10937 SDLoc DL(Op); 10938 10939 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 10940 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 10941 false, 10942 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 10943} 10944 10945// getTargetVShiftNode - Handle vector element shifts where the shift amount 10946// may or may not be a constant. Takes immediate version of shift as input. 10947static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT, 10948 SDValue SrcOp, SDValue ShAmt, 10949 SelectionDAG &DAG) { 10950 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 10951 10952 if (isa<ConstantSDNode>(ShAmt)) { 10953 // Constant may be a TargetConstant. Use a regular constant. 10954 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 10955 switch (Opc) { 10956 default: llvm_unreachable("Unknown target vector shift node"); 10957 case X86ISD::VSHLI: 10958 case X86ISD::VSRLI: 10959 case X86ISD::VSRAI: 10960 return DAG.getNode(Opc, dl, VT, SrcOp, 10961 DAG.getConstant(ShiftAmt, MVT::i32)); 10962 } 10963 } 10964 10965 // Change opcode to non-immediate version 10966 switch (Opc) { 10967 default: llvm_unreachable("Unknown target vector shift node"); 10968 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 10969 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 10970 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 10971 } 10972 10973 // Need to build a vector containing shift amount 10974 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 10975 SDValue ShOps[4]; 10976 ShOps[0] = ShAmt; 10977 ShOps[1] = DAG.getConstant(0, MVT::i32); 10978 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32); 10979 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 10980 10981 // The return type has to be a 128-bit type with the same element 10982 // type as the input type. 10983 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10984 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); 10985 10986 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt); 10987 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 10988} 10989 10990static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 10991 SDLoc dl(Op); 10992 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10993 switch (IntNo) { 10994 default: return SDValue(); // Don't custom lower most intrinsics. 10995 // Comparison intrinsics. 10996 case Intrinsic::x86_sse_comieq_ss: 10997 case Intrinsic::x86_sse_comilt_ss: 10998 case Intrinsic::x86_sse_comile_ss: 10999 case Intrinsic::x86_sse_comigt_ss: 11000 case Intrinsic::x86_sse_comige_ss: 11001 case Intrinsic::x86_sse_comineq_ss: 11002 case Intrinsic::x86_sse_ucomieq_ss: 11003 case Intrinsic::x86_sse_ucomilt_ss: 11004 case Intrinsic::x86_sse_ucomile_ss: 11005 case Intrinsic::x86_sse_ucomigt_ss: 11006 case Intrinsic::x86_sse_ucomige_ss: 11007 case Intrinsic::x86_sse_ucomineq_ss: 11008 case Intrinsic::x86_sse2_comieq_sd: 11009 case Intrinsic::x86_sse2_comilt_sd: 11010 case Intrinsic::x86_sse2_comile_sd: 11011 case Intrinsic::x86_sse2_comigt_sd: 11012 case Intrinsic::x86_sse2_comige_sd: 11013 case Intrinsic::x86_sse2_comineq_sd: 11014 case Intrinsic::x86_sse2_ucomieq_sd: 11015 case Intrinsic::x86_sse2_ucomilt_sd: 11016 case Intrinsic::x86_sse2_ucomile_sd: 11017 case Intrinsic::x86_sse2_ucomigt_sd: 11018 case Intrinsic::x86_sse2_ucomige_sd: 11019 case Intrinsic::x86_sse2_ucomineq_sd: { 11020 unsigned Opc; 11021 ISD::CondCode CC; 11022 switch (IntNo) { 11023 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11024 case Intrinsic::x86_sse_comieq_ss: 11025 case Intrinsic::x86_sse2_comieq_sd: 11026 Opc = X86ISD::COMI; 11027 CC = ISD::SETEQ; 11028 break; 11029 case Intrinsic::x86_sse_comilt_ss: 11030 case Intrinsic::x86_sse2_comilt_sd: 11031 Opc = X86ISD::COMI; 11032 CC = ISD::SETLT; 11033 break; 11034 case Intrinsic::x86_sse_comile_ss: 11035 case Intrinsic::x86_sse2_comile_sd: 11036 Opc = X86ISD::COMI; 11037 CC = ISD::SETLE; 11038 break; 11039 case Intrinsic::x86_sse_comigt_ss: 11040 case Intrinsic::x86_sse2_comigt_sd: 11041 Opc = X86ISD::COMI; 11042 CC = ISD::SETGT; 11043 break; 11044 case Intrinsic::x86_sse_comige_ss: 11045 case Intrinsic::x86_sse2_comige_sd: 11046 Opc = X86ISD::COMI; 11047 CC = ISD::SETGE; 11048 break; 11049 case Intrinsic::x86_sse_comineq_ss: 11050 case Intrinsic::x86_sse2_comineq_sd: 11051 Opc = X86ISD::COMI; 11052 CC = ISD::SETNE; 11053 break; 11054 case Intrinsic::x86_sse_ucomieq_ss: 11055 case Intrinsic::x86_sse2_ucomieq_sd: 11056 Opc = X86ISD::UCOMI; 11057 CC = ISD::SETEQ; 11058 break; 11059 case Intrinsic::x86_sse_ucomilt_ss: 11060 case Intrinsic::x86_sse2_ucomilt_sd: 11061 Opc = X86ISD::UCOMI; 11062 CC = ISD::SETLT; 11063 break; 11064 case Intrinsic::x86_sse_ucomile_ss: 11065 case Intrinsic::x86_sse2_ucomile_sd: 11066 Opc = X86ISD::UCOMI; 11067 CC = ISD::SETLE; 11068 break; 11069 case Intrinsic::x86_sse_ucomigt_ss: 11070 case Intrinsic::x86_sse2_ucomigt_sd: 11071 Opc = X86ISD::UCOMI; 11072 CC = ISD::SETGT; 11073 break; 11074 case Intrinsic::x86_sse_ucomige_ss: 11075 case Intrinsic::x86_sse2_ucomige_sd: 11076 Opc = X86ISD::UCOMI; 11077 CC = ISD::SETGE; 11078 break; 11079 case Intrinsic::x86_sse_ucomineq_ss: 11080 case Intrinsic::x86_sse2_ucomineq_sd: 11081 Opc = X86ISD::UCOMI; 11082 CC = ISD::SETNE; 11083 break; 11084 } 11085 11086 SDValue LHS = Op.getOperand(1); 11087 SDValue RHS = Op.getOperand(2); 11088 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 11089 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 11090 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 11091 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 11092 DAG.getConstant(X86CC, MVT::i8), Cond); 11093 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 11094 } 11095 11096 // Arithmetic intrinsics. 11097 case Intrinsic::x86_sse2_pmulu_dq: 11098 case Intrinsic::x86_avx2_pmulu_dq: 11099 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 11100 Op.getOperand(1), Op.getOperand(2)); 11101 11102 // SSE2/AVX2 sub with unsigned saturation intrinsics 11103 case Intrinsic::x86_sse2_psubus_b: 11104 case Intrinsic::x86_sse2_psubus_w: 11105 case Intrinsic::x86_avx2_psubus_b: 11106 case Intrinsic::x86_avx2_psubus_w: 11107 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(), 11108 Op.getOperand(1), Op.getOperand(2)); 11109 11110 // SSE3/AVX horizontal add/sub intrinsics 11111 case Intrinsic::x86_sse3_hadd_ps: 11112 case Intrinsic::x86_sse3_hadd_pd: 11113 case Intrinsic::x86_avx_hadd_ps_256: 11114 case Intrinsic::x86_avx_hadd_pd_256: 11115 case Intrinsic::x86_sse3_hsub_ps: 11116 case Intrinsic::x86_sse3_hsub_pd: 11117 case Intrinsic::x86_avx_hsub_ps_256: 11118 case Intrinsic::x86_avx_hsub_pd_256: 11119 case Intrinsic::x86_ssse3_phadd_w_128: 11120 case Intrinsic::x86_ssse3_phadd_d_128: 11121 case Intrinsic::x86_avx2_phadd_w: 11122 case Intrinsic::x86_avx2_phadd_d: 11123 case Intrinsic::x86_ssse3_phsub_w_128: 11124 case Intrinsic::x86_ssse3_phsub_d_128: 11125 case Intrinsic::x86_avx2_phsub_w: 11126 case Intrinsic::x86_avx2_phsub_d: { 11127 unsigned Opcode; 11128 switch (IntNo) { 11129 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11130 case Intrinsic::x86_sse3_hadd_ps: 11131 case Intrinsic::x86_sse3_hadd_pd: 11132 case Intrinsic::x86_avx_hadd_ps_256: 11133 case Intrinsic::x86_avx_hadd_pd_256: 11134 Opcode = X86ISD::FHADD; 11135 break; 11136 case Intrinsic::x86_sse3_hsub_ps: 11137 case Intrinsic::x86_sse3_hsub_pd: 11138 case Intrinsic::x86_avx_hsub_ps_256: 11139 case Intrinsic::x86_avx_hsub_pd_256: 11140 Opcode = X86ISD::FHSUB; 11141 break; 11142 case Intrinsic::x86_ssse3_phadd_w_128: 11143 case Intrinsic::x86_ssse3_phadd_d_128: 11144 case Intrinsic::x86_avx2_phadd_w: 11145 case Intrinsic::x86_avx2_phadd_d: 11146 Opcode = X86ISD::HADD; 11147 break; 11148 case Intrinsic::x86_ssse3_phsub_w_128: 11149 case Intrinsic::x86_ssse3_phsub_d_128: 11150 case Intrinsic::x86_avx2_phsub_w: 11151 case Intrinsic::x86_avx2_phsub_d: 11152 Opcode = X86ISD::HSUB; 11153 break; 11154 } 11155 return DAG.getNode(Opcode, dl, Op.getValueType(), 11156 Op.getOperand(1), Op.getOperand(2)); 11157 } 11158 11159 // SSE2/SSE41/AVX2 integer max/min intrinsics. 11160 case Intrinsic::x86_sse2_pmaxu_b: 11161 case Intrinsic::x86_sse41_pmaxuw: 11162 case Intrinsic::x86_sse41_pmaxud: 11163 case Intrinsic::x86_avx2_pmaxu_b: 11164 case Intrinsic::x86_avx2_pmaxu_w: 11165 case Intrinsic::x86_avx2_pmaxu_d: 11166 case Intrinsic::x86_sse2_pminu_b: 11167 case Intrinsic::x86_sse41_pminuw: 11168 case Intrinsic::x86_sse41_pminud: 11169 case Intrinsic::x86_avx2_pminu_b: 11170 case Intrinsic::x86_avx2_pminu_w: 11171 case Intrinsic::x86_avx2_pminu_d: 11172 case Intrinsic::x86_sse41_pmaxsb: 11173 case Intrinsic::x86_sse2_pmaxs_w: 11174 case Intrinsic::x86_sse41_pmaxsd: 11175 case Intrinsic::x86_avx2_pmaxs_b: 11176 case Intrinsic::x86_avx2_pmaxs_w: 11177 case Intrinsic::x86_avx2_pmaxs_d: 11178 case Intrinsic::x86_sse41_pminsb: 11179 case Intrinsic::x86_sse2_pmins_w: 11180 case Intrinsic::x86_sse41_pminsd: 11181 case Intrinsic::x86_avx2_pmins_b: 11182 case Intrinsic::x86_avx2_pmins_w: 11183 case Intrinsic::x86_avx2_pmins_d: { 11184 unsigned Opcode; 11185 switch (IntNo) { 11186 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11187 case Intrinsic::x86_sse2_pmaxu_b: 11188 case Intrinsic::x86_sse41_pmaxuw: 11189 case Intrinsic::x86_sse41_pmaxud: 11190 case Intrinsic::x86_avx2_pmaxu_b: 11191 case Intrinsic::x86_avx2_pmaxu_w: 11192 case Intrinsic::x86_avx2_pmaxu_d: 11193 Opcode = X86ISD::UMAX; 11194 break; 11195 case Intrinsic::x86_sse2_pminu_b: 11196 case Intrinsic::x86_sse41_pminuw: 11197 case Intrinsic::x86_sse41_pminud: 11198 case Intrinsic::x86_avx2_pminu_b: 11199 case Intrinsic::x86_avx2_pminu_w: 11200 case Intrinsic::x86_avx2_pminu_d: 11201 Opcode = X86ISD::UMIN; 11202 break; 11203 case Intrinsic::x86_sse41_pmaxsb: 11204 case Intrinsic::x86_sse2_pmaxs_w: 11205 case Intrinsic::x86_sse41_pmaxsd: 11206 case Intrinsic::x86_avx2_pmaxs_b: 11207 case Intrinsic::x86_avx2_pmaxs_w: 11208 case Intrinsic::x86_avx2_pmaxs_d: 11209 Opcode = X86ISD::SMAX; 11210 break; 11211 case Intrinsic::x86_sse41_pminsb: 11212 case Intrinsic::x86_sse2_pmins_w: 11213 case Intrinsic::x86_sse41_pminsd: 11214 case Intrinsic::x86_avx2_pmins_b: 11215 case Intrinsic::x86_avx2_pmins_w: 11216 case Intrinsic::x86_avx2_pmins_d: 11217 Opcode = X86ISD::SMIN; 11218 break; 11219 } 11220 return DAG.getNode(Opcode, dl, Op.getValueType(), 11221 Op.getOperand(1), Op.getOperand(2)); 11222 } 11223 11224 // SSE/SSE2/AVX floating point max/min intrinsics. 11225 case Intrinsic::x86_sse_max_ps: 11226 case Intrinsic::x86_sse2_max_pd: 11227 case Intrinsic::x86_avx_max_ps_256: 11228 case Intrinsic::x86_avx_max_pd_256: 11229 case Intrinsic::x86_avx512_max_ps_512: 11230 case Intrinsic::x86_avx512_max_pd_512: 11231 case Intrinsic::x86_sse_min_ps: 11232 case Intrinsic::x86_sse2_min_pd: 11233 case Intrinsic::x86_avx_min_ps_256: 11234 case Intrinsic::x86_avx_min_pd_256: 11235 case Intrinsic::x86_avx512_min_ps_512: 11236 case Intrinsic::x86_avx512_min_pd_512: { 11237 unsigned Opcode; 11238 switch (IntNo) { 11239 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11240 case Intrinsic::x86_sse_max_ps: 11241 case Intrinsic::x86_sse2_max_pd: 11242 case Intrinsic::x86_avx_max_ps_256: 11243 case Intrinsic::x86_avx_max_pd_256: 11244 case Intrinsic::x86_avx512_max_ps_512: 11245 case Intrinsic::x86_avx512_max_pd_512: 11246 Opcode = X86ISD::FMAX; 11247 break; 11248 case Intrinsic::x86_sse_min_ps: 11249 case Intrinsic::x86_sse2_min_pd: 11250 case Intrinsic::x86_avx_min_ps_256: 11251 case Intrinsic::x86_avx_min_pd_256: 11252 case Intrinsic::x86_avx512_min_ps_512: 11253 case Intrinsic::x86_avx512_min_pd_512: 11254 Opcode = X86ISD::FMIN; 11255 break; 11256 } 11257 return DAG.getNode(Opcode, dl, Op.getValueType(), 11258 Op.getOperand(1), Op.getOperand(2)); 11259 } 11260 11261 // AVX2 variable shift intrinsics 11262 case Intrinsic::x86_avx2_psllv_d: 11263 case Intrinsic::x86_avx2_psllv_q: 11264 case Intrinsic::x86_avx2_psllv_d_256: 11265 case Intrinsic::x86_avx2_psllv_q_256: 11266 case Intrinsic::x86_avx2_psrlv_d: 11267 case Intrinsic::x86_avx2_psrlv_q: 11268 case Intrinsic::x86_avx2_psrlv_d_256: 11269 case Intrinsic::x86_avx2_psrlv_q_256: 11270 case Intrinsic::x86_avx2_psrav_d: 11271 case Intrinsic::x86_avx2_psrav_d_256: { 11272 unsigned Opcode; 11273 switch (IntNo) { 11274 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11275 case Intrinsic::x86_avx2_psllv_d: 11276 case Intrinsic::x86_avx2_psllv_q: 11277 case Intrinsic::x86_avx2_psllv_d_256: 11278 case Intrinsic::x86_avx2_psllv_q_256: 11279 Opcode = ISD::SHL; 11280 break; 11281 case Intrinsic::x86_avx2_psrlv_d: 11282 case Intrinsic::x86_avx2_psrlv_q: 11283 case Intrinsic::x86_avx2_psrlv_d_256: 11284 case Intrinsic::x86_avx2_psrlv_q_256: 11285 Opcode = ISD::SRL; 11286 break; 11287 case Intrinsic::x86_avx2_psrav_d: 11288 case Intrinsic::x86_avx2_psrav_d_256: 11289 Opcode = ISD::SRA; 11290 break; 11291 } 11292 return DAG.getNode(Opcode, dl, Op.getValueType(), 11293 Op.getOperand(1), Op.getOperand(2)); 11294 } 11295 11296 case Intrinsic::x86_ssse3_pshuf_b_128: 11297 case Intrinsic::x86_avx2_pshuf_b: 11298 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 11299 Op.getOperand(1), Op.getOperand(2)); 11300 11301 case Intrinsic::x86_ssse3_psign_b_128: 11302 case Intrinsic::x86_ssse3_psign_w_128: 11303 case Intrinsic::x86_ssse3_psign_d_128: 11304 case Intrinsic::x86_avx2_psign_b: 11305 case Intrinsic::x86_avx2_psign_w: 11306 case Intrinsic::x86_avx2_psign_d: 11307 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 11308 Op.getOperand(1), Op.getOperand(2)); 11309 11310 case Intrinsic::x86_sse41_insertps: 11311 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 11312 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 11313 11314 case Intrinsic::x86_avx_vperm2f128_ps_256: 11315 case Intrinsic::x86_avx_vperm2f128_pd_256: 11316 case Intrinsic::x86_avx_vperm2f128_si_256: 11317 case Intrinsic::x86_avx2_vperm2i128: 11318 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 11319 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 11320 11321 case Intrinsic::x86_avx2_permd: 11322 case Intrinsic::x86_avx2_permps: 11323 // Operands intentionally swapped. Mask is last operand to intrinsic, 11324 // but second operand for node/instruction. 11325 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 11326 Op.getOperand(2), Op.getOperand(1)); 11327 11328 case Intrinsic::x86_sse_sqrt_ps: 11329 case Intrinsic::x86_sse2_sqrt_pd: 11330 case Intrinsic::x86_avx_sqrt_ps_256: 11331 case Intrinsic::x86_avx_sqrt_pd_256: 11332 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1)); 11333 11334 // ptest and testp intrinsics. The intrinsic these come from are designed to 11335 // return an integer value, not just an instruction so lower it to the ptest 11336 // or testp pattern and a setcc for the result. 11337 case Intrinsic::x86_sse41_ptestz: 11338 case Intrinsic::x86_sse41_ptestc: 11339 case Intrinsic::x86_sse41_ptestnzc: 11340 case Intrinsic::x86_avx_ptestz_256: 11341 case Intrinsic::x86_avx_ptestc_256: 11342 case Intrinsic::x86_avx_ptestnzc_256: 11343 case Intrinsic::x86_avx_vtestz_ps: 11344 case Intrinsic::x86_avx_vtestc_ps: 11345 case Intrinsic::x86_avx_vtestnzc_ps: 11346 case Intrinsic::x86_avx_vtestz_pd: 11347 case Intrinsic::x86_avx_vtestc_pd: 11348 case Intrinsic::x86_avx_vtestnzc_pd: 11349 case Intrinsic::x86_avx_vtestz_ps_256: 11350 case Intrinsic::x86_avx_vtestc_ps_256: 11351 case Intrinsic::x86_avx_vtestnzc_ps_256: 11352 case Intrinsic::x86_avx_vtestz_pd_256: 11353 case Intrinsic::x86_avx_vtestc_pd_256: 11354 case Intrinsic::x86_avx_vtestnzc_pd_256: { 11355 bool IsTestPacked = false; 11356 unsigned X86CC; 11357 switch (IntNo) { 11358 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 11359 case Intrinsic::x86_avx_vtestz_ps: 11360 case Intrinsic::x86_avx_vtestz_pd: 11361 case Intrinsic::x86_avx_vtestz_ps_256: 11362 case Intrinsic::x86_avx_vtestz_pd_256: 11363 IsTestPacked = true; // Fallthrough 11364 case Intrinsic::x86_sse41_ptestz: 11365 case Intrinsic::x86_avx_ptestz_256: 11366 // ZF = 1 11367 X86CC = X86::COND_E; 11368 break; 11369 case Intrinsic::x86_avx_vtestc_ps: 11370 case Intrinsic::x86_avx_vtestc_pd: 11371 case Intrinsic::x86_avx_vtestc_ps_256: 11372 case Intrinsic::x86_avx_vtestc_pd_256: 11373 IsTestPacked = true; // Fallthrough 11374 case Intrinsic::x86_sse41_ptestc: 11375 case Intrinsic::x86_avx_ptestc_256: 11376 // CF = 1 11377 X86CC = X86::COND_B; 11378 break; 11379 case Intrinsic::x86_avx_vtestnzc_ps: 11380 case Intrinsic::x86_avx_vtestnzc_pd: 11381 case Intrinsic::x86_avx_vtestnzc_ps_256: 11382 case Intrinsic::x86_avx_vtestnzc_pd_256: 11383 IsTestPacked = true; // Fallthrough 11384 case Intrinsic::x86_sse41_ptestnzc: 11385 case Intrinsic::x86_avx_ptestnzc_256: 11386 // ZF and CF = 0 11387 X86CC = X86::COND_A; 11388 break; 11389 } 11390 11391 SDValue LHS = Op.getOperand(1); 11392 SDValue RHS = Op.getOperand(2); 11393 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 11394 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 11395 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 11396 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 11397 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 11398 } 11399 case Intrinsic::x86_avx512_kortestz: 11400 case Intrinsic::x86_avx512_kortestc: { 11401 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B; 11402 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1)); 11403 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2)); 11404 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 11405 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS); 11406 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 11407 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 11408 } 11409 11410 // SSE/AVX shift intrinsics 11411 case Intrinsic::x86_sse2_psll_w: 11412 case Intrinsic::x86_sse2_psll_d: 11413 case Intrinsic::x86_sse2_psll_q: 11414 case Intrinsic::x86_avx2_psll_w: 11415 case Intrinsic::x86_avx2_psll_d: 11416 case Intrinsic::x86_avx2_psll_q: 11417 case Intrinsic::x86_sse2_psrl_w: 11418 case Intrinsic::x86_sse2_psrl_d: 11419 case Intrinsic::x86_sse2_psrl_q: 11420 case Intrinsic::x86_avx2_psrl_w: 11421 case Intrinsic::x86_avx2_psrl_d: 11422 case Intrinsic::x86_avx2_psrl_q: 11423 case Intrinsic::x86_sse2_psra_w: 11424 case Intrinsic::x86_sse2_psra_d: 11425 case Intrinsic::x86_avx2_psra_w: 11426 case Intrinsic::x86_avx2_psra_d: { 11427 unsigned Opcode; 11428 switch (IntNo) { 11429 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11430 case Intrinsic::x86_sse2_psll_w: 11431 case Intrinsic::x86_sse2_psll_d: 11432 case Intrinsic::x86_sse2_psll_q: 11433 case Intrinsic::x86_avx2_psll_w: 11434 case Intrinsic::x86_avx2_psll_d: 11435 case Intrinsic::x86_avx2_psll_q: 11436 Opcode = X86ISD::VSHL; 11437 break; 11438 case Intrinsic::x86_sse2_psrl_w: 11439 case Intrinsic::x86_sse2_psrl_d: 11440 case Intrinsic::x86_sse2_psrl_q: 11441 case Intrinsic::x86_avx2_psrl_w: 11442 case Intrinsic::x86_avx2_psrl_d: 11443 case Intrinsic::x86_avx2_psrl_q: 11444 Opcode = X86ISD::VSRL; 11445 break; 11446 case Intrinsic::x86_sse2_psra_w: 11447 case Intrinsic::x86_sse2_psra_d: 11448 case Intrinsic::x86_avx2_psra_w: 11449 case Intrinsic::x86_avx2_psra_d: 11450 Opcode = X86ISD::VSRA; 11451 break; 11452 } 11453 return DAG.getNode(Opcode, dl, Op.getValueType(), 11454 Op.getOperand(1), Op.getOperand(2)); 11455 } 11456 11457 // SSE/AVX immediate shift intrinsics 11458 case Intrinsic::x86_sse2_pslli_w: 11459 case Intrinsic::x86_sse2_pslli_d: 11460 case Intrinsic::x86_sse2_pslli_q: 11461 case Intrinsic::x86_avx2_pslli_w: 11462 case Intrinsic::x86_avx2_pslli_d: 11463 case Intrinsic::x86_avx2_pslli_q: 11464 case Intrinsic::x86_sse2_psrli_w: 11465 case Intrinsic::x86_sse2_psrli_d: 11466 case Intrinsic::x86_sse2_psrli_q: 11467 case Intrinsic::x86_avx2_psrli_w: 11468 case Intrinsic::x86_avx2_psrli_d: 11469 case Intrinsic::x86_avx2_psrli_q: 11470 case Intrinsic::x86_sse2_psrai_w: 11471 case Intrinsic::x86_sse2_psrai_d: 11472 case Intrinsic::x86_avx2_psrai_w: 11473 case Intrinsic::x86_avx2_psrai_d: { 11474 unsigned Opcode; 11475 switch (IntNo) { 11476 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11477 case Intrinsic::x86_sse2_pslli_w: 11478 case Intrinsic::x86_sse2_pslli_d: 11479 case Intrinsic::x86_sse2_pslli_q: 11480 case Intrinsic::x86_avx2_pslli_w: 11481 case Intrinsic::x86_avx2_pslli_d: 11482 case Intrinsic::x86_avx2_pslli_q: 11483 Opcode = X86ISD::VSHLI; 11484 break; 11485 case Intrinsic::x86_sse2_psrli_w: 11486 case Intrinsic::x86_sse2_psrli_d: 11487 case Intrinsic::x86_sse2_psrli_q: 11488 case Intrinsic::x86_avx2_psrli_w: 11489 case Intrinsic::x86_avx2_psrli_d: 11490 case Intrinsic::x86_avx2_psrli_q: 11491 Opcode = X86ISD::VSRLI; 11492 break; 11493 case Intrinsic::x86_sse2_psrai_w: 11494 case Intrinsic::x86_sse2_psrai_d: 11495 case Intrinsic::x86_avx2_psrai_w: 11496 case Intrinsic::x86_avx2_psrai_d: 11497 Opcode = X86ISD::VSRAI; 11498 break; 11499 } 11500 return getTargetVShiftNode(Opcode, dl, Op.getValueType(), 11501 Op.getOperand(1), Op.getOperand(2), DAG); 11502 } 11503 11504 case Intrinsic::x86_sse42_pcmpistria128: 11505 case Intrinsic::x86_sse42_pcmpestria128: 11506 case Intrinsic::x86_sse42_pcmpistric128: 11507 case Intrinsic::x86_sse42_pcmpestric128: 11508 case Intrinsic::x86_sse42_pcmpistrio128: 11509 case Intrinsic::x86_sse42_pcmpestrio128: 11510 case Intrinsic::x86_sse42_pcmpistris128: 11511 case Intrinsic::x86_sse42_pcmpestris128: 11512 case Intrinsic::x86_sse42_pcmpistriz128: 11513 case Intrinsic::x86_sse42_pcmpestriz128: { 11514 unsigned Opcode; 11515 unsigned X86CC; 11516 switch (IntNo) { 11517 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11518 case Intrinsic::x86_sse42_pcmpistria128: 11519 Opcode = X86ISD::PCMPISTRI; 11520 X86CC = X86::COND_A; 11521 break; 11522 case Intrinsic::x86_sse42_pcmpestria128: 11523 Opcode = X86ISD::PCMPESTRI; 11524 X86CC = X86::COND_A; 11525 break; 11526 case Intrinsic::x86_sse42_pcmpistric128: 11527 Opcode = X86ISD::PCMPISTRI; 11528 X86CC = X86::COND_B; 11529 break; 11530 case Intrinsic::x86_sse42_pcmpestric128: 11531 Opcode = X86ISD::PCMPESTRI; 11532 X86CC = X86::COND_B; 11533 break; 11534 case Intrinsic::x86_sse42_pcmpistrio128: 11535 Opcode = X86ISD::PCMPISTRI; 11536 X86CC = X86::COND_O; 11537 break; 11538 case Intrinsic::x86_sse42_pcmpestrio128: 11539 Opcode = X86ISD::PCMPESTRI; 11540 X86CC = X86::COND_O; 11541 break; 11542 case Intrinsic::x86_sse42_pcmpistris128: 11543 Opcode = X86ISD::PCMPISTRI; 11544 X86CC = X86::COND_S; 11545 break; 11546 case Intrinsic::x86_sse42_pcmpestris128: 11547 Opcode = X86ISD::PCMPESTRI; 11548 X86CC = X86::COND_S; 11549 break; 11550 case Intrinsic::x86_sse42_pcmpistriz128: 11551 Opcode = X86ISD::PCMPISTRI; 11552 X86CC = X86::COND_E; 11553 break; 11554 case Intrinsic::x86_sse42_pcmpestriz128: 11555 Opcode = X86ISD::PCMPESTRI; 11556 X86CC = X86::COND_E; 11557 break; 11558 } 11559 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end()); 11560 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 11561 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 11562 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 11563 DAG.getConstant(X86CC, MVT::i8), 11564 SDValue(PCMP.getNode(), 1)); 11565 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 11566 } 11567 11568 case Intrinsic::x86_sse42_pcmpistri128: 11569 case Intrinsic::x86_sse42_pcmpestri128: { 11570 unsigned Opcode; 11571 if (IntNo == Intrinsic::x86_sse42_pcmpistri128) 11572 Opcode = X86ISD::PCMPISTRI; 11573 else 11574 Opcode = X86ISD::PCMPESTRI; 11575 11576 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end()); 11577 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 11578 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 11579 } 11580 case Intrinsic::x86_fma_vfmadd_ps: 11581 case Intrinsic::x86_fma_vfmadd_pd: 11582 case Intrinsic::x86_fma_vfmsub_ps: 11583 case Intrinsic::x86_fma_vfmsub_pd: 11584 case Intrinsic::x86_fma_vfnmadd_ps: 11585 case Intrinsic::x86_fma_vfnmadd_pd: 11586 case Intrinsic::x86_fma_vfnmsub_ps: 11587 case Intrinsic::x86_fma_vfnmsub_pd: 11588 case Intrinsic::x86_fma_vfmaddsub_ps: 11589 case Intrinsic::x86_fma_vfmaddsub_pd: 11590 case Intrinsic::x86_fma_vfmsubadd_ps: 11591 case Intrinsic::x86_fma_vfmsubadd_pd: 11592 case Intrinsic::x86_fma_vfmadd_ps_256: 11593 case Intrinsic::x86_fma_vfmadd_pd_256: 11594 case Intrinsic::x86_fma_vfmsub_ps_256: 11595 case Intrinsic::x86_fma_vfmsub_pd_256: 11596 case Intrinsic::x86_fma_vfnmadd_ps_256: 11597 case Intrinsic::x86_fma_vfnmadd_pd_256: 11598 case Intrinsic::x86_fma_vfnmsub_ps_256: 11599 case Intrinsic::x86_fma_vfnmsub_pd_256: 11600 case Intrinsic::x86_fma_vfmaddsub_ps_256: 11601 case Intrinsic::x86_fma_vfmaddsub_pd_256: 11602 case Intrinsic::x86_fma_vfmsubadd_ps_256: 11603 case Intrinsic::x86_fma_vfmsubadd_pd_256: { 11604 unsigned Opc; 11605 switch (IntNo) { 11606 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 11607 case Intrinsic::x86_fma_vfmadd_ps: 11608 case Intrinsic::x86_fma_vfmadd_pd: 11609 case Intrinsic::x86_fma_vfmadd_ps_256: 11610 case Intrinsic::x86_fma_vfmadd_pd_256: 11611 Opc = X86ISD::FMADD; 11612 break; 11613 case Intrinsic::x86_fma_vfmsub_ps: 11614 case Intrinsic::x86_fma_vfmsub_pd: 11615 case Intrinsic::x86_fma_vfmsub_ps_256: 11616 case Intrinsic::x86_fma_vfmsub_pd_256: 11617 Opc = X86ISD::FMSUB; 11618 break; 11619 case Intrinsic::x86_fma_vfnmadd_ps: 11620 case Intrinsic::x86_fma_vfnmadd_pd: 11621 case Intrinsic::x86_fma_vfnmadd_ps_256: 11622 case Intrinsic::x86_fma_vfnmadd_pd_256: 11623 Opc = X86ISD::FNMADD; 11624 break; 11625 case Intrinsic::x86_fma_vfnmsub_ps: 11626 case Intrinsic::x86_fma_vfnmsub_pd: 11627 case Intrinsic::x86_fma_vfnmsub_ps_256: 11628 case Intrinsic::x86_fma_vfnmsub_pd_256: 11629 Opc = X86ISD::FNMSUB; 11630 break; 11631 case Intrinsic::x86_fma_vfmaddsub_ps: 11632 case Intrinsic::x86_fma_vfmaddsub_pd: 11633 case Intrinsic::x86_fma_vfmaddsub_ps_256: 11634 case Intrinsic::x86_fma_vfmaddsub_pd_256: 11635 Opc = X86ISD::FMADDSUB; 11636 break; 11637 case Intrinsic::x86_fma_vfmsubadd_ps: 11638 case Intrinsic::x86_fma_vfmsubadd_pd: 11639 case Intrinsic::x86_fma_vfmsubadd_ps_256: 11640 case Intrinsic::x86_fma_vfmsubadd_pd_256: 11641 Opc = X86ISD::FMSUBADD; 11642 break; 11643 } 11644 11645 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1), 11646 Op.getOperand(2), Op.getOperand(3)); 11647 } 11648 } 11649} 11650 11651static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG, 11652 SDValue Base, SDValue Index, 11653 SDValue ScaleOp, SDValue Chain, 11654 const X86Subtarget * Subtarget) { 11655 SDLoc dl(Op); 11656 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp); 11657 assert(C && "Invalid scale type"); 11658 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8); 11659 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl); 11660 EVT MaskVT = MVT::getVectorVT(MVT::i1, 11661 Index.getValueType().getVectorNumElements()); 11662 SDValue MaskInReg = DAG.getConstant(~0, MaskVT); 11663 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other); 11664 SDValue Disp = DAG.getTargetConstant(0, MVT::i32); 11665 SDValue Segment = DAG.getRegister(0, MVT::i32); 11666 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain}; 11667 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops); 11668 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) }; 11669 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl); 11670} 11671 11672static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG, 11673 SDValue Src, SDValue Mask, SDValue Base, 11674 SDValue Index, SDValue ScaleOp, SDValue Chain, 11675 const X86Subtarget * Subtarget) { 11676 SDLoc dl(Op); 11677 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp); 11678 assert(C && "Invalid scale type"); 11679 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8); 11680 EVT MaskVT = MVT::getVectorVT(MVT::i1, 11681 Index.getValueType().getVectorNumElements()); 11682 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask); 11683 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other); 11684 SDValue Disp = DAG.getTargetConstant(0, MVT::i32); 11685 SDValue Segment = DAG.getRegister(0, MVT::i32); 11686 if (Src.getOpcode() == ISD::UNDEF) 11687 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl); 11688 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain}; 11689 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops); 11690 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) }; 11691 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl); 11692} 11693 11694static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG, 11695 SDValue Src, SDValue Base, SDValue Index, 11696 SDValue ScaleOp, SDValue Chain) { 11697 SDLoc dl(Op); 11698 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp); 11699 assert(C && "Invalid scale type"); 11700 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8); 11701 SDValue Disp = DAG.getTargetConstant(0, MVT::i32); 11702 SDValue Segment = DAG.getRegister(0, MVT::i32); 11703 EVT MaskVT = MVT::getVectorVT(MVT::i1, 11704 Index.getValueType().getVectorNumElements()); 11705 SDValue MaskInReg = DAG.getConstant(~0, MaskVT); 11706 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other); 11707 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain}; 11708 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops); 11709 return SDValue(Res, 1); 11710} 11711 11712static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG, 11713 SDValue Src, SDValue Mask, SDValue Base, 11714 SDValue Index, SDValue ScaleOp, SDValue Chain) { 11715 SDLoc dl(Op); 11716 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp); 11717 assert(C && "Invalid scale type"); 11718 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8); 11719 SDValue Disp = DAG.getTargetConstant(0, MVT::i32); 11720 SDValue Segment = DAG.getRegister(0, MVT::i32); 11721 EVT MaskVT = MVT::getVectorVT(MVT::i1, 11722 Index.getValueType().getVectorNumElements()); 11723 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask); 11724 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other); 11725 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain}; 11726 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops); 11727 return SDValue(Res, 1); 11728} 11729 11730static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget, 11731 SelectionDAG &DAG) { 11732 SDLoc dl(Op); 11733 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 11734 switch (IntNo) { 11735 default: return SDValue(); // Don't custom lower most intrinsics. 11736 11737 // RDRAND/RDSEED intrinsics. 11738 case Intrinsic::x86_rdrand_16: 11739 case Intrinsic::x86_rdrand_32: 11740 case Intrinsic::x86_rdrand_64: 11741 case Intrinsic::x86_rdseed_16: 11742 case Intrinsic::x86_rdseed_32: 11743 case Intrinsic::x86_rdseed_64: { 11744 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 || 11745 IntNo == Intrinsic::x86_rdseed_32 || 11746 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED : 11747 X86ISD::RDRAND; 11748 // Emit the node with the right value type. 11749 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other); 11750 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0)); 11751 11752 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1. 11753 // Otherwise return the value from Rand, which is always 0, casted to i32. 11754 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)), 11755 DAG.getConstant(1, Op->getValueType(1)), 11756 DAG.getConstant(X86::COND_B, MVT::i32), 11757 SDValue(Result.getNode(), 1) }; 11758 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, 11759 DAG.getVTList(Op->getValueType(1), MVT::Glue), 11760 Ops, array_lengthof(Ops)); 11761 11762 // Return { result, isValid, chain }. 11763 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 11764 SDValue(Result.getNode(), 2)); 11765 } 11766 //int_gather(index, base, scale); 11767 case Intrinsic::x86_avx512_gather_qpd_512: 11768 case Intrinsic::x86_avx512_gather_qps_512: 11769 case Intrinsic::x86_avx512_gather_dpd_512: 11770 case Intrinsic::x86_avx512_gather_qpi_512: 11771 case Intrinsic::x86_avx512_gather_qpq_512: 11772 case Intrinsic::x86_avx512_gather_dpq_512: 11773 case Intrinsic::x86_avx512_gather_dps_512: 11774 case Intrinsic::x86_avx512_gather_dpi_512: { 11775 unsigned Opc; 11776 switch (IntNo) { 11777 default: llvm_unreachable("Unexpected intrinsic!"); 11778 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break; 11779 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break; 11780 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break; 11781 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break; 11782 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break; 11783 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break; 11784 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break; 11785 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break; 11786 } 11787 SDValue Chain = Op.getOperand(0); 11788 SDValue Index = Op.getOperand(2); 11789 SDValue Base = Op.getOperand(3); 11790 SDValue Scale = Op.getOperand(4); 11791 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget); 11792 } 11793 //int_gather_mask(v1, mask, index, base, scale); 11794 case Intrinsic::x86_avx512_gather_qps_mask_512: 11795 case Intrinsic::x86_avx512_gather_qpd_mask_512: 11796 case Intrinsic::x86_avx512_gather_dpd_mask_512: 11797 case Intrinsic::x86_avx512_gather_dps_mask_512: 11798 case Intrinsic::x86_avx512_gather_qpi_mask_512: 11799 case Intrinsic::x86_avx512_gather_qpq_mask_512: 11800 case Intrinsic::x86_avx512_gather_dpi_mask_512: 11801 case Intrinsic::x86_avx512_gather_dpq_mask_512: { 11802 unsigned Opc; 11803 switch (IntNo) { 11804 default: llvm_unreachable("Unexpected intrinsic!"); 11805 case Intrinsic::x86_avx512_gather_qps_mask_512: 11806 Opc = X86::VGATHERQPSZrm; break; 11807 case Intrinsic::x86_avx512_gather_qpd_mask_512: 11808 Opc = X86::VGATHERQPDZrm; break; 11809 case Intrinsic::x86_avx512_gather_dpd_mask_512: 11810 Opc = X86::VGATHERDPDZrm; break; 11811 case Intrinsic::x86_avx512_gather_dps_mask_512: 11812 Opc = X86::VGATHERDPSZrm; break; 11813 case Intrinsic::x86_avx512_gather_qpi_mask_512: 11814 Opc = X86::VPGATHERQDZrm; break; 11815 case Intrinsic::x86_avx512_gather_qpq_mask_512: 11816 Opc = X86::VPGATHERQQZrm; break; 11817 case Intrinsic::x86_avx512_gather_dpi_mask_512: 11818 Opc = X86::VPGATHERDDZrm; break; 11819 case Intrinsic::x86_avx512_gather_dpq_mask_512: 11820 Opc = X86::VPGATHERDQZrm; break; 11821 } 11822 SDValue Chain = Op.getOperand(0); 11823 SDValue Src = Op.getOperand(2); 11824 SDValue Mask = Op.getOperand(3); 11825 SDValue Index = Op.getOperand(4); 11826 SDValue Base = Op.getOperand(5); 11827 SDValue Scale = Op.getOperand(6); 11828 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain, 11829 Subtarget); 11830 } 11831 //int_scatter(base, index, v1, scale); 11832 case Intrinsic::x86_avx512_scatter_qpd_512: 11833 case Intrinsic::x86_avx512_scatter_qps_512: 11834 case Intrinsic::x86_avx512_scatter_dpd_512: 11835 case Intrinsic::x86_avx512_scatter_qpi_512: 11836 case Intrinsic::x86_avx512_scatter_qpq_512: 11837 case Intrinsic::x86_avx512_scatter_dpq_512: 11838 case Intrinsic::x86_avx512_scatter_dps_512: 11839 case Intrinsic::x86_avx512_scatter_dpi_512: { 11840 unsigned Opc; 11841 switch (IntNo) { 11842 default: llvm_unreachable("Unexpected intrinsic!"); 11843 case Intrinsic::x86_avx512_scatter_qpd_512: 11844 Opc = X86::VSCATTERQPDZmr; break; 11845 case Intrinsic::x86_avx512_scatter_qps_512: 11846 Opc = X86::VSCATTERQPSZmr; break; 11847 case Intrinsic::x86_avx512_scatter_dpd_512: 11848 Opc = X86::VSCATTERDPDZmr; break; 11849 case Intrinsic::x86_avx512_scatter_dps_512: 11850 Opc = X86::VSCATTERDPSZmr; break; 11851 case Intrinsic::x86_avx512_scatter_qpi_512: 11852 Opc = X86::VPSCATTERQDZmr; break; 11853 case Intrinsic::x86_avx512_scatter_qpq_512: 11854 Opc = X86::VPSCATTERQQZmr; break; 11855 case Intrinsic::x86_avx512_scatter_dpq_512: 11856 Opc = X86::VPSCATTERDQZmr; break; 11857 case Intrinsic::x86_avx512_scatter_dpi_512: 11858 Opc = X86::VPSCATTERDDZmr; break; 11859 } 11860 SDValue Chain = Op.getOperand(0); 11861 SDValue Base = Op.getOperand(2); 11862 SDValue Index = Op.getOperand(3); 11863 SDValue Src = Op.getOperand(4); 11864 SDValue Scale = Op.getOperand(5); 11865 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain); 11866 } 11867 //int_scatter_mask(base, mask, index, v1, scale); 11868 case Intrinsic::x86_avx512_scatter_qps_mask_512: 11869 case Intrinsic::x86_avx512_scatter_qpd_mask_512: 11870 case Intrinsic::x86_avx512_scatter_dpd_mask_512: 11871 case Intrinsic::x86_avx512_scatter_dps_mask_512: 11872 case Intrinsic::x86_avx512_scatter_qpi_mask_512: 11873 case Intrinsic::x86_avx512_scatter_qpq_mask_512: 11874 case Intrinsic::x86_avx512_scatter_dpi_mask_512: 11875 case Intrinsic::x86_avx512_scatter_dpq_mask_512: { 11876 unsigned Opc; 11877 switch (IntNo) { 11878 default: llvm_unreachable("Unexpected intrinsic!"); 11879 case Intrinsic::x86_avx512_scatter_qpd_mask_512: 11880 Opc = X86::VSCATTERQPDZmr; break; 11881 case Intrinsic::x86_avx512_scatter_qps_mask_512: 11882 Opc = X86::VSCATTERQPSZmr; break; 11883 case Intrinsic::x86_avx512_scatter_dpd_mask_512: 11884 Opc = X86::VSCATTERDPDZmr; break; 11885 case Intrinsic::x86_avx512_scatter_dps_mask_512: 11886 Opc = X86::VSCATTERDPSZmr; break; 11887 case Intrinsic::x86_avx512_scatter_qpi_mask_512: 11888 Opc = X86::VPSCATTERQDZmr; break; 11889 case Intrinsic::x86_avx512_scatter_qpq_mask_512: 11890 Opc = X86::VPSCATTERQQZmr; break; 11891 case Intrinsic::x86_avx512_scatter_dpq_mask_512: 11892 Opc = X86::VPSCATTERDQZmr; break; 11893 case Intrinsic::x86_avx512_scatter_dpi_mask_512: 11894 Opc = X86::VPSCATTERDDZmr; break; 11895 } 11896 SDValue Chain = Op.getOperand(0); 11897 SDValue Base = Op.getOperand(2); 11898 SDValue Mask = Op.getOperand(3); 11899 SDValue Index = Op.getOperand(4); 11900 SDValue Src = Op.getOperand(5); 11901 SDValue Scale = Op.getOperand(6); 11902 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain); 11903 } 11904 // XTEST intrinsics. 11905 case Intrinsic::x86_xtest: { 11906 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other); 11907 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0)); 11908 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 11909 DAG.getConstant(X86::COND_NE, MVT::i8), 11910 InTrans); 11911 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC); 11912 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), 11913 Ret, SDValue(InTrans.getNode(), 1)); 11914 } 11915 } 11916} 11917 11918SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 11919 SelectionDAG &DAG) const { 11920 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 11921 MFI->setReturnAddressIsTaken(true); 11922 11923 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 11924 SDLoc dl(Op); 11925 EVT PtrVT = getPointerTy(); 11926 11927 if (Depth > 0) { 11928 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 11929 const X86RegisterInfo *RegInfo = 11930 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 11931 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT); 11932 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 11933 DAG.getNode(ISD::ADD, dl, PtrVT, 11934 FrameAddr, Offset), 11935 MachinePointerInfo(), false, false, false, 0); 11936 } 11937 11938 // Just load the return address. 11939 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 11940 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 11941 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 11942} 11943 11944SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 11945 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 11946 MFI->setFrameAddressIsTaken(true); 11947 11948 EVT VT = Op.getValueType(); 11949 SDLoc dl(Op); // FIXME probably not meaningful 11950 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 11951 const X86RegisterInfo *RegInfo = 11952 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 11953 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); 11954 assert(((FrameReg == X86::RBP && VT == MVT::i64) || 11955 (FrameReg == X86::EBP && VT == MVT::i32)) && 11956 "Invalid Frame Register!"); 11957 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 11958 while (Depth--) 11959 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 11960 MachinePointerInfo(), 11961 false, false, false, 0); 11962 return FrameAddr; 11963} 11964 11965SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 11966 SelectionDAG &DAG) const { 11967 const X86RegisterInfo *RegInfo = 11968 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 11969 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize()); 11970} 11971 11972SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 11973 SDValue Chain = Op.getOperand(0); 11974 SDValue Offset = Op.getOperand(1); 11975 SDValue Handler = Op.getOperand(2); 11976 SDLoc dl (Op); 11977 11978 EVT PtrVT = getPointerTy(); 11979 const X86RegisterInfo *RegInfo = 11980 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 11981 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); 11982 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) || 11983 (FrameReg == X86::EBP && PtrVT == MVT::i32)) && 11984 "Invalid Frame Register!"); 11985 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT); 11986 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX; 11987 11988 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame, 11989 DAG.getIntPtrConstant(RegInfo->getSlotSize())); 11990 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset); 11991 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 11992 false, false, 0); 11993 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 11994 11995 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain, 11996 DAG.getRegister(StoreAddrReg, PtrVT)); 11997} 11998 11999SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op, 12000 SelectionDAG &DAG) const { 12001 SDLoc DL(Op); 12002 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL, 12003 DAG.getVTList(MVT::i32, MVT::Other), 12004 Op.getOperand(0), Op.getOperand(1)); 12005} 12006 12007SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, 12008 SelectionDAG &DAG) const { 12009 SDLoc DL(Op); 12010 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other, 12011 Op.getOperand(0), Op.getOperand(1)); 12012} 12013 12014static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 12015 return Op.getOperand(0); 12016} 12017 12018SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 12019 SelectionDAG &DAG) const { 12020 SDValue Root = Op.getOperand(0); 12021 SDValue Trmp = Op.getOperand(1); // trampoline 12022 SDValue FPtr = Op.getOperand(2); // nested function 12023 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 12024 SDLoc dl (Op); 12025 12026 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 12027 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12028 12029 if (Subtarget->is64Bit()) { 12030 SDValue OutChains[6]; 12031 12032 // Large code-model. 12033 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 12034 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 12035 12036 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7; 12037 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7; 12038 12039 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 12040 12041 // Load the pointer to the nested function into R11. 12042 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 12043 SDValue Addr = Trmp; 12044 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 12045 Addr, MachinePointerInfo(TrmpAddr), 12046 false, false, 0); 12047 12048 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 12049 DAG.getConstant(2, MVT::i64)); 12050 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 12051 MachinePointerInfo(TrmpAddr, 2), 12052 false, false, 2); 12053 12054 // Load the 'nest' parameter value into R10. 12055 // R10 is specified in X86CallingConv.td 12056 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 12057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 12058 DAG.getConstant(10, MVT::i64)); 12059 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 12060 Addr, MachinePointerInfo(TrmpAddr, 10), 12061 false, false, 0); 12062 12063 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 12064 DAG.getConstant(12, MVT::i64)); 12065 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 12066 MachinePointerInfo(TrmpAddr, 12), 12067 false, false, 2); 12068 12069 // Jump to the nested function. 12070 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 12071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 12072 DAG.getConstant(20, MVT::i64)); 12073 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 12074 Addr, MachinePointerInfo(TrmpAddr, 20), 12075 false, false, 0); 12076 12077 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 12078 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 12079 DAG.getConstant(22, MVT::i64)); 12080 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 12081 MachinePointerInfo(TrmpAddr, 22), 12082 false, false, 0); 12083 12084 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 12085 } else { 12086 const Function *Func = 12087 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 12088 CallingConv::ID CC = Func->getCallingConv(); 12089 unsigned NestReg; 12090 12091 switch (CC) { 12092 default: 12093 llvm_unreachable("Unsupported calling convention"); 12094 case CallingConv::C: 12095 case CallingConv::X86_StdCall: { 12096 // Pass 'nest' parameter in ECX. 12097 // Must be kept in sync with X86CallingConv.td 12098 NestReg = X86::ECX; 12099 12100 // Check that ECX wasn't needed by an 'inreg' parameter. 12101 FunctionType *FTy = Func->getFunctionType(); 12102 const AttributeSet &Attrs = Func->getAttributes(); 12103 12104 if (!Attrs.isEmpty() && !Func->isVarArg()) { 12105 unsigned InRegCount = 0; 12106 unsigned Idx = 1; 12107 12108 for (FunctionType::param_iterator I = FTy->param_begin(), 12109 E = FTy->param_end(); I != E; ++I, ++Idx) 12110 if (Attrs.hasAttribute(Idx, Attribute::InReg)) 12111 // FIXME: should only count parameters that are lowered to integers. 12112 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 12113 12114 if (InRegCount > 2) { 12115 report_fatal_error("Nest register in use - reduce number of inreg" 12116 " parameters!"); 12117 } 12118 } 12119 break; 12120 } 12121 case CallingConv::X86_FastCall: 12122 case CallingConv::X86_ThisCall: 12123 case CallingConv::Fast: 12124 // Pass 'nest' parameter in EAX. 12125 // Must be kept in sync with X86CallingConv.td 12126 NestReg = X86::EAX; 12127 break; 12128 } 12129 12130 SDValue OutChains[4]; 12131 SDValue Addr, Disp; 12132 12133 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 12134 DAG.getConstant(10, MVT::i32)); 12135 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 12136 12137 // This is storing the opcode for MOV32ri. 12138 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 12139 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7; 12140 OutChains[0] = DAG.getStore(Root, dl, 12141 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 12142 Trmp, MachinePointerInfo(TrmpAddr), 12143 false, false, 0); 12144 12145 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 12146 DAG.getConstant(1, MVT::i32)); 12147 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 12148 MachinePointerInfo(TrmpAddr, 1), 12149 false, false, 1); 12150 12151 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 12152 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 12153 DAG.getConstant(5, MVT::i32)); 12154 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 12155 MachinePointerInfo(TrmpAddr, 5), 12156 false, false, 1); 12157 12158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 12159 DAG.getConstant(6, MVT::i32)); 12160 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 12161 MachinePointerInfo(TrmpAddr, 6), 12162 false, false, 1); 12163 12164 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 12165 } 12166} 12167 12168SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 12169 SelectionDAG &DAG) const { 12170 /* 12171 The rounding mode is in bits 11:10 of FPSR, and has the following 12172 settings: 12173 00 Round to nearest 12174 01 Round to -inf 12175 10 Round to +inf 12176 11 Round to 0 12177 12178 FLT_ROUNDS, on the other hand, expects the following: 12179 -1 Undefined 12180 0 Round to 0 12181 1 Round to nearest 12182 2 Round to +inf 12183 3 Round to -inf 12184 12185 To perform the conversion, we do: 12186 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 12187 */ 12188 12189 MachineFunction &MF = DAG.getMachineFunction(); 12190 const TargetMachine &TM = MF.getTarget(); 12191 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 12192 unsigned StackAlignment = TFI.getStackAlignment(); 12193 EVT VT = Op.getValueType(); 12194 SDLoc DL(Op); 12195 12196 // Save FP Control Word to stack slot 12197 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 12198 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 12199 12200 MachineMemOperand *MMO = 12201 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 12202 MachineMemOperand::MOStore, 2, 2); 12203 12204 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 12205 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 12206 DAG.getVTList(MVT::Other), 12207 Ops, array_lengthof(Ops), MVT::i16, 12208 MMO); 12209 12210 // Load FP Control Word from stack slot 12211 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 12212 MachinePointerInfo(), false, false, false, 0); 12213 12214 // Transform as necessary 12215 SDValue CWD1 = 12216 DAG.getNode(ISD::SRL, DL, MVT::i16, 12217 DAG.getNode(ISD::AND, DL, MVT::i16, 12218 CWD, DAG.getConstant(0x800, MVT::i16)), 12219 DAG.getConstant(11, MVT::i8)); 12220 SDValue CWD2 = 12221 DAG.getNode(ISD::SRL, DL, MVT::i16, 12222 DAG.getNode(ISD::AND, DL, MVT::i16, 12223 CWD, DAG.getConstant(0x400, MVT::i16)), 12224 DAG.getConstant(9, MVT::i8)); 12225 12226 SDValue RetVal = 12227 DAG.getNode(ISD::AND, DL, MVT::i16, 12228 DAG.getNode(ISD::ADD, DL, MVT::i16, 12229 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 12230 DAG.getConstant(1, MVT::i16)), 12231 DAG.getConstant(3, MVT::i16)); 12232 12233 return DAG.getNode((VT.getSizeInBits() < 16 ? 12234 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 12235} 12236 12237static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 12238 EVT VT = Op.getValueType(); 12239 EVT OpVT = VT; 12240 unsigned NumBits = VT.getSizeInBits(); 12241 SDLoc dl(Op); 12242 12243 Op = Op.getOperand(0); 12244 if (VT == MVT::i8) { 12245 // Zero extend to i32 since there is not an i8 bsr. 12246 OpVT = MVT::i32; 12247 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 12248 } 12249 12250 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 12251 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 12252 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 12253 12254 // If src is zero (i.e. bsr sets ZF), returns NumBits. 12255 SDValue Ops[] = { 12256 Op, 12257 DAG.getConstant(NumBits+NumBits-1, OpVT), 12258 DAG.getConstant(X86::COND_E, MVT::i8), 12259 Op.getValue(1) 12260 }; 12261 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 12262 12263 // Finally xor with NumBits-1. 12264 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 12265 12266 if (VT == MVT::i8) 12267 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 12268 return Op; 12269} 12270 12271static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) { 12272 EVT VT = Op.getValueType(); 12273 EVT OpVT = VT; 12274 unsigned NumBits = VT.getSizeInBits(); 12275 SDLoc dl(Op); 12276 12277 Op = Op.getOperand(0); 12278 if (VT == MVT::i8) { 12279 // Zero extend to i32 since there is not an i8 bsr. 12280 OpVT = MVT::i32; 12281 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 12282 } 12283 12284 // Issue a bsr (scan bits in reverse). 12285 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 12286 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 12287 12288 // And xor with NumBits-1. 12289 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 12290 12291 if (VT == MVT::i8) 12292 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 12293 return Op; 12294} 12295 12296static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 12297 EVT VT = Op.getValueType(); 12298 unsigned NumBits = VT.getSizeInBits(); 12299 SDLoc dl(Op); 12300 Op = Op.getOperand(0); 12301 12302 // Issue a bsf (scan bits forward) which also sets EFLAGS. 12303 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 12304 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 12305 12306 // If src is zero (i.e. bsf sets ZF), returns NumBits. 12307 SDValue Ops[] = { 12308 Op, 12309 DAG.getConstant(NumBits, VT), 12310 DAG.getConstant(X86::COND_E, MVT::i8), 12311 Op.getValue(1) 12312 }; 12313 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 12314} 12315 12316// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 12317// ones, and then concatenate the result back. 12318static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 12319 EVT VT = Op.getValueType(); 12320 12321 assert(VT.is256BitVector() && VT.isInteger() && 12322 "Unsupported value type for operation"); 12323 12324 unsigned NumElems = VT.getVectorNumElements(); 12325 SDLoc dl(Op); 12326 12327 // Extract the LHS vectors 12328 SDValue LHS = Op.getOperand(0); 12329 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 12330 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 12331 12332 // Extract the RHS vectors 12333 SDValue RHS = Op.getOperand(1); 12334 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 12335 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 12336 12337 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 12338 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 12339 12340 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 12341 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 12342 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 12343} 12344 12345static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) { 12346 assert(Op.getValueType().is256BitVector() && 12347 Op.getValueType().isInteger() && 12348 "Only handle AVX 256-bit vector integer operation"); 12349 return Lower256IntArith(Op, DAG); 12350} 12351 12352static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) { 12353 assert(Op.getValueType().is256BitVector() && 12354 Op.getValueType().isInteger() && 12355 "Only handle AVX 256-bit vector integer operation"); 12356 return Lower256IntArith(Op, DAG); 12357} 12358 12359static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget, 12360 SelectionDAG &DAG) { 12361 SDLoc dl(Op); 12362 EVT VT = Op.getValueType(); 12363 12364 // Decompose 256-bit ops into smaller 128-bit ops. 12365 if (VT.is256BitVector() && !Subtarget->hasInt256()) 12366 return Lower256IntArith(Op, DAG); 12367 12368 SDValue A = Op.getOperand(0); 12369 SDValue B = Op.getOperand(1); 12370 12371 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle. 12372 if (VT == MVT::v4i32) { 12373 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() && 12374 "Should not custom lower when pmuldq is available!"); 12375 12376 // Extract the odd parts. 12377 static const int UnpackMask[] = { 1, -1, 3, -1 }; 12378 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask); 12379 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask); 12380 12381 // Multiply the even parts. 12382 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B); 12383 // Now multiply odd parts. 12384 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds); 12385 12386 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens); 12387 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds); 12388 12389 // Merge the two vectors back together with a shuffle. This expands into 2 12390 // shuffles. 12391 static const int ShufMask[] = { 0, 4, 2, 6 }; 12392 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask); 12393 } 12394 12395 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 12396 "Only know how to lower V2I64/V4I64 multiply"); 12397 12398 // Ahi = psrlqi(a, 32); 12399 // Bhi = psrlqi(b, 32); 12400 // 12401 // AloBlo = pmuludq(a, b); 12402 // AloBhi = pmuludq(a, Bhi); 12403 // AhiBlo = pmuludq(Ahi, b); 12404 12405 // AloBhi = psllqi(AloBhi, 32); 12406 // AhiBlo = psllqi(AhiBlo, 32); 12407 // return AloBlo + AloBhi + AhiBlo; 12408 12409 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 12410 12411 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 12412 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 12413 12414 // Bit cast to 32-bit vectors for MULUDQ 12415 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 12416 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 12417 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 12418 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 12419 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 12420 12421 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 12422 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 12423 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 12424 12425 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 12426 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 12427 12428 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 12429 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 12430} 12431 12432static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 12433 EVT VT = Op.getValueType(); 12434 EVT EltTy = VT.getVectorElementType(); 12435 unsigned NumElts = VT.getVectorNumElements(); 12436 SDValue N0 = Op.getOperand(0); 12437 SDLoc dl(Op); 12438 12439 // Lower sdiv X, pow2-const. 12440 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1)); 12441 if (!C) 12442 return SDValue(); 12443 12444 APInt SplatValue, SplatUndef; 12445 unsigned SplatBitSize; 12446 bool HasAnyUndefs; 12447 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 12448 HasAnyUndefs) || 12449 EltTy.getSizeInBits() < SplatBitSize) 12450 return SDValue(); 12451 12452 if ((SplatValue != 0) && 12453 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) { 12454 unsigned lg2 = SplatValue.countTrailingZeros(); 12455 // Splat the sign bit. 12456 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32); 12457 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG); 12458 // Add (N0 < 0) ? abs2 - 1 : 0; 12459 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32); 12460 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG); 12461 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL); 12462 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32); 12463 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG); 12464 12465 // If we're dividing by a positive value, we're done. Otherwise, we must 12466 // negate the result. 12467 if (SplatValue.isNonNegative()) 12468 return SRA; 12469 12470 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy)); 12471 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts); 12472 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA); 12473 } 12474 return SDValue(); 12475} 12476 12477static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG, 12478 const X86Subtarget *Subtarget) { 12479 EVT VT = Op.getValueType(); 12480 SDLoc dl(Op); 12481 SDValue R = Op.getOperand(0); 12482 SDValue Amt = Op.getOperand(1); 12483 12484 // Optimize shl/srl/sra with constant shift amount. 12485 if (isSplatVector(Amt.getNode())) { 12486 SDValue SclrAmt = Amt->getOperand(0); 12487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 12488 uint64_t ShiftAmt = C->getZExtValue(); 12489 12490 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 12491 (Subtarget->hasInt256() && 12492 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) || 12493 (Subtarget->hasAVX512() && 12494 (VT == MVT::v8i64 || VT == MVT::v16i32))) { 12495 if (Op.getOpcode() == ISD::SHL) 12496 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 12497 DAG.getConstant(ShiftAmt, MVT::i32)); 12498 if (Op.getOpcode() == ISD::SRL) 12499 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 12500 DAG.getConstant(ShiftAmt, MVT::i32)); 12501 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 12502 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 12503 DAG.getConstant(ShiftAmt, MVT::i32)); 12504 } 12505 12506 if (VT == MVT::v16i8) { 12507 if (Op.getOpcode() == ISD::SHL) { 12508 // Make a large shift. 12509 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 12510 DAG.getConstant(ShiftAmt, MVT::i32)); 12511 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 12512 // Zero out the rightmost bits. 12513 SmallVector<SDValue, 16> V(16, 12514 DAG.getConstant(uint8_t(-1U << ShiftAmt), 12515 MVT::i8)); 12516 return DAG.getNode(ISD::AND, dl, VT, SHL, 12517 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 12518 } 12519 if (Op.getOpcode() == ISD::SRL) { 12520 // Make a large shift. 12521 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 12522 DAG.getConstant(ShiftAmt, MVT::i32)); 12523 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 12524 // Zero out the leftmost bits. 12525 SmallVector<SDValue, 16> V(16, 12526 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 12527 MVT::i8)); 12528 return DAG.getNode(ISD::AND, dl, VT, SRL, 12529 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 12530 } 12531 if (Op.getOpcode() == ISD::SRA) { 12532 if (ShiftAmt == 7) { 12533 // R s>> 7 === R s< 0 12534 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12535 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 12536 } 12537 12538 // R s>> a === ((R u>> a) ^ m) - m 12539 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 12540 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 12541 MVT::i8)); 12542 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 12543 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 12544 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 12545 return Res; 12546 } 12547 llvm_unreachable("Unknown shift opcode."); 12548 } 12549 12550 if (Subtarget->hasInt256() && VT == MVT::v32i8) { 12551 if (Op.getOpcode() == ISD::SHL) { 12552 // Make a large shift. 12553 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 12554 DAG.getConstant(ShiftAmt, MVT::i32)); 12555 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 12556 // Zero out the rightmost bits. 12557 SmallVector<SDValue, 32> V(32, 12558 DAG.getConstant(uint8_t(-1U << ShiftAmt), 12559 MVT::i8)); 12560 return DAG.getNode(ISD::AND, dl, VT, SHL, 12561 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 12562 } 12563 if (Op.getOpcode() == ISD::SRL) { 12564 // Make a large shift. 12565 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 12566 DAG.getConstant(ShiftAmt, MVT::i32)); 12567 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 12568 // Zero out the leftmost bits. 12569 SmallVector<SDValue, 32> V(32, 12570 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 12571 MVT::i8)); 12572 return DAG.getNode(ISD::AND, dl, VT, SRL, 12573 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 12574 } 12575 if (Op.getOpcode() == ISD::SRA) { 12576 if (ShiftAmt == 7) { 12577 // R s>> 7 === R s< 0 12578 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12579 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 12580 } 12581 12582 // R s>> a === ((R u>> a) ^ m) - m 12583 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 12584 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 12585 MVT::i8)); 12586 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 12587 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 12588 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 12589 return Res; 12590 } 12591 llvm_unreachable("Unknown shift opcode."); 12592 } 12593 } 12594 } 12595 12596 // Special case in 32-bit mode, where i64 is expanded into high and low parts. 12597 if (!Subtarget->is64Bit() && 12598 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) && 12599 Amt.getOpcode() == ISD::BITCAST && 12600 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { 12601 Amt = Amt.getOperand(0); 12602 unsigned Ratio = Amt.getValueType().getVectorNumElements() / 12603 VT.getVectorNumElements(); 12604 unsigned RatioInLog2 = Log2_32_Ceil(Ratio); 12605 uint64_t ShiftAmt = 0; 12606 for (unsigned i = 0; i != Ratio; ++i) { 12607 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i)); 12608 if (C == 0) 12609 return SDValue(); 12610 // 6 == Log2(64) 12611 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2))); 12612 } 12613 // Check remaining shift amounts. 12614 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) { 12615 uint64_t ShAmt = 0; 12616 for (unsigned j = 0; j != Ratio; ++j) { 12617 ConstantSDNode *C = 12618 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j)); 12619 if (C == 0) 12620 return SDValue(); 12621 // 6 == Log2(64) 12622 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2))); 12623 } 12624 if (ShAmt != ShiftAmt) 12625 return SDValue(); 12626 } 12627 switch (Op.getOpcode()) { 12628 default: 12629 llvm_unreachable("Unknown shift opcode!"); 12630 case ISD::SHL: 12631 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 12632 DAG.getConstant(ShiftAmt, MVT::i32)); 12633 case ISD::SRL: 12634 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 12635 DAG.getConstant(ShiftAmt, MVT::i32)); 12636 case ISD::SRA: 12637 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 12638 DAG.getConstant(ShiftAmt, MVT::i32)); 12639 } 12640 } 12641 12642 return SDValue(); 12643} 12644 12645static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG, 12646 const X86Subtarget* Subtarget) { 12647 EVT VT = Op.getValueType(); 12648 SDLoc dl(Op); 12649 SDValue R = Op.getOperand(0); 12650 SDValue Amt = Op.getOperand(1); 12651 12652 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) || 12653 VT == MVT::v4i32 || VT == MVT::v8i16 || 12654 (Subtarget->hasInt256() && 12655 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) || 12656 VT == MVT::v8i32 || VT == MVT::v16i16)) || 12657 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) { 12658 SDValue BaseShAmt; 12659 EVT EltVT = VT.getVectorElementType(); 12660 12661 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 12662 unsigned NumElts = VT.getVectorNumElements(); 12663 unsigned i, j; 12664 for (i = 0; i != NumElts; ++i) { 12665 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF) 12666 continue; 12667 break; 12668 } 12669 for (j = i; j != NumElts; ++j) { 12670 SDValue Arg = Amt.getOperand(j); 12671 if (Arg.getOpcode() == ISD::UNDEF) continue; 12672 if (Arg != Amt.getOperand(i)) 12673 break; 12674 } 12675 if (i != NumElts && j == NumElts) 12676 BaseShAmt = Amt.getOperand(i); 12677 } else { 12678 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR) 12679 Amt = Amt.getOperand(0); 12680 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE && 12681 cast<ShuffleVectorSDNode>(Amt)->isSplat()) { 12682 SDValue InVec = Amt.getOperand(0); 12683 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 12684 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 12685 unsigned i = 0; 12686 for (; i != NumElts; ++i) { 12687 SDValue Arg = InVec.getOperand(i); 12688 if (Arg.getOpcode() == ISD::UNDEF) continue; 12689 BaseShAmt = Arg; 12690 break; 12691 } 12692 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 12693 if (ConstantSDNode *C = 12694 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 12695 unsigned SplatIdx = 12696 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex(); 12697 if (C->getZExtValue() == SplatIdx) 12698 BaseShAmt = InVec.getOperand(1); 12699 } 12700 } 12701 if (BaseShAmt.getNode() == 0) 12702 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt, 12703 DAG.getIntPtrConstant(0)); 12704 } 12705 } 12706 12707 if (BaseShAmt.getNode()) { 12708 if (EltVT.bitsGT(MVT::i32)) 12709 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt); 12710 else if (EltVT.bitsLT(MVT::i32)) 12711 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt); 12712 12713 switch (Op.getOpcode()) { 12714 default: 12715 llvm_unreachable("Unknown shift opcode!"); 12716 case ISD::SHL: 12717 switch (VT.getSimpleVT().SimpleTy) { 12718 default: return SDValue(); 12719 case MVT::v2i64: 12720 case MVT::v4i32: 12721 case MVT::v8i16: 12722 case MVT::v4i64: 12723 case MVT::v8i32: 12724 case MVT::v16i16: 12725 case MVT::v16i32: 12726 case MVT::v8i64: 12727 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG); 12728 } 12729 case ISD::SRA: 12730 switch (VT.getSimpleVT().SimpleTy) { 12731 default: return SDValue(); 12732 case MVT::v4i32: 12733 case MVT::v8i16: 12734 case MVT::v8i32: 12735 case MVT::v16i16: 12736 case MVT::v16i32: 12737 case MVT::v8i64: 12738 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG); 12739 } 12740 case ISD::SRL: 12741 switch (VT.getSimpleVT().SimpleTy) { 12742 default: return SDValue(); 12743 case MVT::v2i64: 12744 case MVT::v4i32: 12745 case MVT::v8i16: 12746 case MVT::v4i64: 12747 case MVT::v8i32: 12748 case MVT::v16i16: 12749 case MVT::v16i32: 12750 case MVT::v8i64: 12751 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG); 12752 } 12753 } 12754 } 12755 } 12756 12757 // Special case in 32-bit mode, where i64 is expanded into high and low parts. 12758 if (!Subtarget->is64Bit() && 12759 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) || 12760 (Subtarget->hasAVX512() && VT == MVT::v8i64)) && 12761 Amt.getOpcode() == ISD::BITCAST && 12762 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { 12763 Amt = Amt.getOperand(0); 12764 unsigned Ratio = Amt.getValueType().getVectorNumElements() / 12765 VT.getVectorNumElements(); 12766 std::vector<SDValue> Vals(Ratio); 12767 for (unsigned i = 0; i != Ratio; ++i) 12768 Vals[i] = Amt.getOperand(i); 12769 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) { 12770 for (unsigned j = 0; j != Ratio; ++j) 12771 if (Vals[j] != Amt.getOperand(i + j)) 12772 return SDValue(); 12773 } 12774 switch (Op.getOpcode()) { 12775 default: 12776 llvm_unreachable("Unknown shift opcode!"); 12777 case ISD::SHL: 12778 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1)); 12779 case ISD::SRL: 12780 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1)); 12781 case ISD::SRA: 12782 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1)); 12783 } 12784 } 12785 12786 return SDValue(); 12787} 12788 12789static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget, 12790 SelectionDAG &DAG) { 12791 12792 EVT VT = Op.getValueType(); 12793 SDLoc dl(Op); 12794 SDValue R = Op.getOperand(0); 12795 SDValue Amt = Op.getOperand(1); 12796 SDValue V; 12797 12798 if (!Subtarget->hasSSE2()) 12799 return SDValue(); 12800 12801 V = LowerScalarImmediateShift(Op, DAG, Subtarget); 12802 if (V.getNode()) 12803 return V; 12804 12805 V = LowerScalarVariableShift(Op, DAG, Subtarget); 12806 if (V.getNode()) 12807 return V; 12808 12809 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64)) 12810 return Op; 12811 // AVX2 has VPSLLV/VPSRAV/VPSRLV. 12812 if (Subtarget->hasInt256()) { 12813 if (Op.getOpcode() == ISD::SRL && 12814 (VT == MVT::v2i64 || VT == MVT::v4i32 || 12815 VT == MVT::v4i64 || VT == MVT::v8i32)) 12816 return Op; 12817 if (Op.getOpcode() == ISD::SHL && 12818 (VT == MVT::v2i64 || VT == MVT::v4i32 || 12819 VT == MVT::v4i64 || VT == MVT::v8i32)) 12820 return Op; 12821 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32)) 12822 return Op; 12823 } 12824 12825 // Lower SHL with variable shift amount. 12826 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 12827 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT)); 12828 12829 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT)); 12830 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 12831 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 12832 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 12833 } 12834 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 12835 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 12836 12837 // a = a << 5; 12838 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT)); 12839 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 12840 12841 // Turn 'a' into a mask suitable for VSELECT 12842 SDValue VSelM = DAG.getConstant(0x80, VT); 12843 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 12844 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 12845 12846 SDValue CM1 = DAG.getConstant(0x0f, VT); 12847 SDValue CM2 = DAG.getConstant(0x3f, VT); 12848 12849 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 12850 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 12851 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 12852 DAG.getConstant(4, MVT::i32), DAG); 12853 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 12854 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 12855 12856 // a += a 12857 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 12858 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 12859 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 12860 12861 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 12862 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 12863 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 12864 DAG.getConstant(2, MVT::i32), DAG); 12865 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 12866 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 12867 12868 // a += a 12869 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 12870 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 12871 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 12872 12873 // return VSELECT(r, r+r, a); 12874 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 12875 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 12876 return R; 12877 } 12878 12879 // Decompose 256-bit shifts into smaller 128-bit shifts. 12880 if (VT.is256BitVector()) { 12881 unsigned NumElems = VT.getVectorNumElements(); 12882 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 12883 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 12884 12885 // Extract the two vectors 12886 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 12887 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 12888 12889 // Recreate the shift amount vectors 12890 SDValue Amt1, Amt2; 12891 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 12892 // Constant shift amount 12893 SmallVector<SDValue, 4> Amt1Csts; 12894 SmallVector<SDValue, 4> Amt2Csts; 12895 for (unsigned i = 0; i != NumElems/2; ++i) 12896 Amt1Csts.push_back(Amt->getOperand(i)); 12897 for (unsigned i = NumElems/2; i != NumElems; ++i) 12898 Amt2Csts.push_back(Amt->getOperand(i)); 12899 12900 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 12901 &Amt1Csts[0], NumElems/2); 12902 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 12903 &Amt2Csts[0], NumElems/2); 12904 } else { 12905 // Variable shift amount 12906 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 12907 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 12908 } 12909 12910 // Issue new vector shifts for the smaller types 12911 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 12912 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 12913 12914 // Concatenate the result back 12915 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 12916 } 12917 12918 return SDValue(); 12919} 12920 12921static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 12922 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 12923 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 12924 // looks for this combo and may remove the "setcc" instruction if the "setcc" 12925 // has only one use. 12926 SDNode *N = Op.getNode(); 12927 SDValue LHS = N->getOperand(0); 12928 SDValue RHS = N->getOperand(1); 12929 unsigned BaseOp = 0; 12930 unsigned Cond = 0; 12931 SDLoc DL(Op); 12932 switch (Op.getOpcode()) { 12933 default: llvm_unreachable("Unknown ovf instruction!"); 12934 case ISD::SADDO: 12935 // A subtract of one will be selected as a INC. Note that INC doesn't 12936 // set CF, so we can't do this for UADDO. 12937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 12938 if (C->isOne()) { 12939 BaseOp = X86ISD::INC; 12940 Cond = X86::COND_O; 12941 break; 12942 } 12943 BaseOp = X86ISD::ADD; 12944 Cond = X86::COND_O; 12945 break; 12946 case ISD::UADDO: 12947 BaseOp = X86ISD::ADD; 12948 Cond = X86::COND_B; 12949 break; 12950 case ISD::SSUBO: 12951 // A subtract of one will be selected as a DEC. Note that DEC doesn't 12952 // set CF, so we can't do this for USUBO. 12953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 12954 if (C->isOne()) { 12955 BaseOp = X86ISD::DEC; 12956 Cond = X86::COND_O; 12957 break; 12958 } 12959 BaseOp = X86ISD::SUB; 12960 Cond = X86::COND_O; 12961 break; 12962 case ISD::USUBO: 12963 BaseOp = X86ISD::SUB; 12964 Cond = X86::COND_B; 12965 break; 12966 case ISD::SMULO: 12967 BaseOp = X86ISD::SMUL; 12968 Cond = X86::COND_O; 12969 break; 12970 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 12971 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 12972 MVT::i32); 12973 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 12974 12975 SDValue SetCC = 12976 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12977 DAG.getConstant(X86::COND_O, MVT::i32), 12978 SDValue(Sum.getNode(), 2)); 12979 12980 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 12981 } 12982 } 12983 12984 // Also sets EFLAGS. 12985 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 12986 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 12987 12988 SDValue SetCC = 12989 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 12990 DAG.getConstant(Cond, MVT::i32), 12991 SDValue(Sum.getNode(), 1)); 12992 12993 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 12994} 12995 12996SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 12997 SelectionDAG &DAG) const { 12998 SDLoc dl(Op); 12999 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 13000 EVT VT = Op.getValueType(); 13001 13002 if (!Subtarget->hasSSE2() || !VT.isVector()) 13003 return SDValue(); 13004 13005 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 13006 ExtraVT.getScalarType().getSizeInBits(); 13007 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 13008 13009 switch (VT.getSimpleVT().SimpleTy) { 13010 default: return SDValue(); 13011 case MVT::v8i32: 13012 case MVT::v16i16: 13013 if (!Subtarget->hasFp256()) 13014 return SDValue(); 13015 if (!Subtarget->hasInt256()) { 13016 // needs to be split 13017 unsigned NumElems = VT.getVectorNumElements(); 13018 13019 // Extract the LHS vectors 13020 SDValue LHS = Op.getOperand(0); 13021 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 13022 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 13023 13024 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 13025 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 13026 13027 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 13028 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 13029 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 13030 ExtraNumElems/2); 13031 SDValue Extra = DAG.getValueType(ExtraVT); 13032 13033 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 13034 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 13035 13036 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2); 13037 } 13038 // fall through 13039 case MVT::v4i32: 13040 case MVT::v8i16: { 13041 // (sext (vzext x)) -> (vsext x) 13042 SDValue Op0 = Op.getOperand(0); 13043 SDValue Op00 = Op0.getOperand(0); 13044 SDValue Tmp1; 13045 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT. 13046 if (Op0.getOpcode() == ISD::BITCAST && 13047 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) 13048 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG); 13049 if (Tmp1.getNode()) { 13050 SDValue Tmp1Op0 = Tmp1.getOperand(0); 13051 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT && 13052 "This optimization is invalid without a VZEXT."); 13053 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0)); 13054 } 13055 13056 // If the above didn't work, then just use Shift-Left + Shift-Right. 13057 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG); 13058 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 13059 } 13060 } 13061} 13062 13063static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, 13064 SelectionDAG &DAG) { 13065 SDLoc dl(Op); 13066 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 13067 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 13068 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 13069 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 13070 13071 // The only fence that needs an instruction is a sequentially-consistent 13072 // cross-thread fence. 13073 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 13074 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 13075 // no-sse2). There isn't any reason to disable it if the target processor 13076 // supports it. 13077 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 13078 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 13079 13080 SDValue Chain = Op.getOperand(0); 13081 SDValue Zero = DAG.getConstant(0, MVT::i32); 13082 SDValue Ops[] = { 13083 DAG.getRegister(X86::ESP, MVT::i32), // Base 13084 DAG.getTargetConstant(1, MVT::i8), // Scale 13085 DAG.getRegister(0, MVT::i32), // Index 13086 DAG.getTargetConstant(0, MVT::i32), // Disp 13087 DAG.getRegister(0, MVT::i32), // Segment. 13088 Zero, 13089 Chain 13090 }; 13091 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops); 13092 return SDValue(Res, 0); 13093 } 13094 13095 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 13096 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 13097} 13098 13099static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, 13100 SelectionDAG &DAG) { 13101 EVT T = Op.getValueType(); 13102 SDLoc DL(Op); 13103 unsigned Reg = 0; 13104 unsigned size = 0; 13105 switch(T.getSimpleVT().SimpleTy) { 13106 default: llvm_unreachable("Invalid value type!"); 13107 case MVT::i8: Reg = X86::AL; size = 1; break; 13108 case MVT::i16: Reg = X86::AX; size = 2; break; 13109 case MVT::i32: Reg = X86::EAX; size = 4; break; 13110 case MVT::i64: 13111 assert(Subtarget->is64Bit() && "Node not type legal!"); 13112 Reg = X86::RAX; size = 8; 13113 break; 13114 } 13115 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 13116 Op.getOperand(2), SDValue()); 13117 SDValue Ops[] = { cpIn.getValue(0), 13118 Op.getOperand(1), 13119 Op.getOperand(3), 13120 DAG.getTargetConstant(size, MVT::i8), 13121 cpIn.getValue(1) }; 13122 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 13123 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 13124 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 13125 Ops, array_lengthof(Ops), T, MMO); 13126 SDValue cpOut = 13127 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 13128 return cpOut; 13129} 13130 13131static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, 13132 SelectionDAG &DAG) { 13133 assert(Subtarget->is64Bit() && "Result not type legalized?"); 13134 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 13135 SDValue TheChain = Op.getOperand(0); 13136 SDLoc dl(Op); 13137 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 13138 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 13139 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 13140 rax.getValue(2)); 13141 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 13142 DAG.getConstant(32, MVT::i8)); 13143 SDValue Ops[] = { 13144 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 13145 rdx.getValue(1) 13146 }; 13147 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl); 13148} 13149 13150static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget, 13151 SelectionDAG &DAG) { 13152 MVT SrcVT = Op.getOperand(0).getSimpleValueType(); 13153 MVT DstVT = Op.getSimpleValueType(); 13154 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 13155 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 13156 assert((DstVT == MVT::i64 || 13157 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 13158 "Unexpected custom BITCAST"); 13159 // i64 <=> MMX conversions are Legal. 13160 if (SrcVT==MVT::i64 && DstVT.isVector()) 13161 return Op; 13162 if (DstVT==MVT::i64 && SrcVT.isVector()) 13163 return Op; 13164 // MMX <=> MMX conversions are Legal. 13165 if (SrcVT.isVector() && DstVT.isVector()) 13166 return Op; 13167 // All other conversions need to be expanded. 13168 return SDValue(); 13169} 13170 13171static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 13172 SDNode *Node = Op.getNode(); 13173 SDLoc dl(Node); 13174 EVT T = Node->getValueType(0); 13175 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 13176 DAG.getConstant(0, T), Node->getOperand(2)); 13177 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 13178 cast<AtomicSDNode>(Node)->getMemoryVT(), 13179 Node->getOperand(0), 13180 Node->getOperand(1), negOp, 13181 cast<AtomicSDNode>(Node)->getSrcValue(), 13182 cast<AtomicSDNode>(Node)->getAlignment(), 13183 cast<AtomicSDNode>(Node)->getOrdering(), 13184 cast<AtomicSDNode>(Node)->getSynchScope()); 13185} 13186 13187static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 13188 SDNode *Node = Op.getNode(); 13189 SDLoc dl(Node); 13190 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 13191 13192 // Convert seq_cst store -> xchg 13193 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 13194 // FIXME: On 32-bit, store -> fist or movq would be more efficient 13195 // (The only way to get a 16-byte store is cmpxchg16b) 13196 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 13197 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 13198 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 13199 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 13200 cast<AtomicSDNode>(Node)->getMemoryVT(), 13201 Node->getOperand(0), 13202 Node->getOperand(1), Node->getOperand(2), 13203 cast<AtomicSDNode>(Node)->getMemOperand(), 13204 cast<AtomicSDNode>(Node)->getOrdering(), 13205 cast<AtomicSDNode>(Node)->getSynchScope()); 13206 return Swap.getValue(1); 13207 } 13208 // Other atomic stores have a simple pattern. 13209 return Op; 13210} 13211 13212static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 13213 EVT VT = Op.getNode()->getValueType(0); 13214 13215 // Let legalize expand this if it isn't a legal type yet. 13216 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 13217 return SDValue(); 13218 13219 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 13220 13221 unsigned Opc; 13222 bool ExtraOp = false; 13223 switch (Op.getOpcode()) { 13224 default: llvm_unreachable("Invalid code"); 13225 case ISD::ADDC: Opc = X86ISD::ADD; break; 13226 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 13227 case ISD::SUBC: Opc = X86ISD::SUB; break; 13228 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 13229 } 13230 13231 if (!ExtraOp) 13232 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), 13233 Op.getOperand(1)); 13234 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), 13235 Op.getOperand(1), Op.getOperand(2)); 13236} 13237 13238static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget, 13239 SelectionDAG &DAG) { 13240 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit()); 13241 13242 // For MacOSX, we want to call an alternative entry point: __sincos_stret, 13243 // which returns the values as { float, float } (in XMM0) or 13244 // { double, double } (which is returned in XMM0, XMM1). 13245 SDLoc dl(Op); 13246 SDValue Arg = Op.getOperand(0); 13247 EVT ArgVT = Arg.getValueType(); 13248 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 13249 13250 TargetLowering::ArgListTy Args; 13251 TargetLowering::ArgListEntry Entry; 13252 13253 Entry.Node = Arg; 13254 Entry.Ty = ArgTy; 13255 Entry.isSExt = false; 13256 Entry.isZExt = false; 13257 Args.push_back(Entry); 13258 13259 bool isF64 = ArgVT == MVT::f64; 13260 // Only optimize x86_64 for now. i386 is a bit messy. For f32, 13261 // the small struct {f32, f32} is returned in (eax, edx). For f64, 13262 // the results are returned via SRet in memory. 13263 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret"; 13264 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13265 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy()); 13266 13267 Type *RetTy = isF64 13268 ? (Type*)StructType::get(ArgTy, ArgTy, NULL) 13269 : (Type*)VectorType::get(ArgTy, 4); 13270 TargetLowering:: 13271 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, 13272 false, false, false, false, 0, 13273 CallingConv::C, /*isTaillCall=*/false, 13274 /*doesNotRet=*/false, /*isReturnValueUsed*/true, 13275 Callee, Args, DAG, dl); 13276 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 13277 13278 if (isF64) 13279 // Returned in xmm0 and xmm1. 13280 return CallResult.first; 13281 13282 // Returned in bits 0:31 and 32:64 xmm0. 13283 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT, 13284 CallResult.first, DAG.getIntPtrConstant(0)); 13285 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT, 13286 CallResult.first, DAG.getIntPtrConstant(1)); 13287 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT); 13288 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal); 13289} 13290 13291/// LowerOperation - Provide custom lowering hooks for some operations. 13292/// 13293SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 13294 switch (Op.getOpcode()) { 13295 default: llvm_unreachable("Should not custom lower this!"); 13296 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 13297 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG); 13298 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG); 13299 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 13300 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 13301 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 13302 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 13303 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 13304 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 13305 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 13306 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG); 13307 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); 13308 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 13309 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 13310 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 13311 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 13312 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 13313 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 13314 case ISD::SHL_PARTS: 13315 case ISD::SRA_PARTS: 13316 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 13317 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 13318 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 13319 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG); 13320 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG); 13321 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG); 13322 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG); 13323 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 13324 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 13325 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); 13326 case ISD::FABS: return LowerFABS(Op, DAG); 13327 case ISD::FNEG: return LowerFNEG(Op, DAG); 13328 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 13329 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 13330 case ISD::SETCC: return LowerSETCC(Op, DAG); 13331 case ISD::SELECT: return LowerSELECT(Op, DAG); 13332 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 13333 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 13334 case ISD::VASTART: return LowerVASTART(Op, DAG); 13335 case ISD::VAARG: return LowerVAARG(Op, DAG); 13336 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG); 13337 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 13338 case ISD::INTRINSIC_VOID: 13339 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG); 13340 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 13341 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 13342 case ISD::FRAME_TO_ARGS_OFFSET: 13343 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 13344 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 13345 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 13346 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); 13347 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); 13348 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 13349 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 13350 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 13351 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 13352 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 13353 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 13354 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG); 13355 case ISD::SRA: 13356 case ISD::SRL: 13357 case ISD::SHL: return LowerShift(Op, Subtarget, DAG); 13358 case ISD::SADDO: 13359 case ISD::UADDO: 13360 case ISD::SSUBO: 13361 case ISD::USUBO: 13362 case ISD::SMULO: 13363 case ISD::UMULO: return LowerXALUO(Op, DAG); 13364 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG); 13365 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG); 13366 case ISD::ADDC: 13367 case ISD::ADDE: 13368 case ISD::SUBC: 13369 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 13370 case ISD::ADD: return LowerADD(Op, DAG); 13371 case ISD::SUB: return LowerSUB(Op, DAG); 13372 case ISD::SDIV: return LowerSDIV(Op, DAG); 13373 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG); 13374 } 13375} 13376 13377static void ReplaceATOMIC_LOAD(SDNode *Node, 13378 SmallVectorImpl<SDValue> &Results, 13379 SelectionDAG &DAG) { 13380 SDLoc dl(Node); 13381 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 13382 13383 // Convert wide load -> cmpxchg8b/cmpxchg16b 13384 // FIXME: On 32-bit, load -> fild or movq would be more efficient 13385 // (The only way to get a 16-byte load is cmpxchg16b) 13386 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 13387 SDValue Zero = DAG.getConstant(0, VT); 13388 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 13389 Node->getOperand(0), 13390 Node->getOperand(1), Zero, Zero, 13391 cast<AtomicSDNode>(Node)->getMemOperand(), 13392 cast<AtomicSDNode>(Node)->getOrdering(), 13393 cast<AtomicSDNode>(Node)->getSynchScope()); 13394 Results.push_back(Swap.getValue(0)); 13395 Results.push_back(Swap.getValue(1)); 13396} 13397 13398static void 13399ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 13400 SelectionDAG &DAG, unsigned NewOp) { 13401 SDLoc dl(Node); 13402 assert (Node->getValueType(0) == MVT::i64 && 13403 "Only know how to expand i64 atomics"); 13404 13405 SDValue Chain = Node->getOperand(0); 13406 SDValue In1 = Node->getOperand(1); 13407 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 13408 Node->getOperand(2), DAG.getIntPtrConstant(0)); 13409 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 13410 Node->getOperand(2), DAG.getIntPtrConstant(1)); 13411 SDValue Ops[] = { Chain, In1, In2L, In2H }; 13412 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 13413 SDValue Result = 13414 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64, 13415 cast<MemSDNode>(Node)->getMemOperand()); 13416 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 13417 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 13418 Results.push_back(Result.getValue(2)); 13419} 13420 13421/// ReplaceNodeResults - Replace a node with an illegal result type 13422/// with a new node built out of custom code. 13423void X86TargetLowering::ReplaceNodeResults(SDNode *N, 13424 SmallVectorImpl<SDValue>&Results, 13425 SelectionDAG &DAG) const { 13426 SDLoc dl(N); 13427 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13428 switch (N->getOpcode()) { 13429 default: 13430 llvm_unreachable("Do not know how to custom type legalize this operation!"); 13431 case ISD::SIGN_EXTEND_INREG: 13432 case ISD::ADDC: 13433 case ISD::ADDE: 13434 case ISD::SUBC: 13435 case ISD::SUBE: 13436 // We don't want to expand or promote these. 13437 return; 13438 case ISD::FP_TO_SINT: 13439 case ISD::FP_TO_UINT: { 13440 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 13441 13442 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 13443 return; 13444 13445 std::pair<SDValue,SDValue> Vals = 13446 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 13447 SDValue FIST = Vals.first, StackSlot = Vals.second; 13448 if (FIST.getNode() != 0) { 13449 EVT VT = N->getValueType(0); 13450 // Return a load from the stack slot. 13451 if (StackSlot.getNode() != 0) 13452 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 13453 MachinePointerInfo(), 13454 false, false, false, 0)); 13455 else 13456 Results.push_back(FIST); 13457 } 13458 return; 13459 } 13460 case ISD::UINT_TO_FP: { 13461 assert(Subtarget->hasSSE2() && "Requires at least SSE2!"); 13462 if (N->getOperand(0).getValueType() != MVT::v2i32 || 13463 N->getValueType(0) != MVT::v2f32) 13464 return; 13465 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, 13466 N->getOperand(0)); 13467 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 13468 MVT::f64); 13469 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); 13470 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, 13471 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias)); 13472 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or); 13473 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias); 13474 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub)); 13475 return; 13476 } 13477 case ISD::FP_ROUND: { 13478 if (!TLI.isTypeLegal(N->getOperand(0).getValueType())) 13479 return; 13480 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0)); 13481 Results.push_back(V); 13482 return; 13483 } 13484 case ISD::READCYCLECOUNTER: { 13485 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 13486 SDValue TheChain = N->getOperand(0); 13487 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 13488 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 13489 rd.getValue(1)); 13490 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 13491 eax.getValue(2)); 13492 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 13493 SDValue Ops[] = { eax, edx }; 13494 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 13495 array_lengthof(Ops))); 13496 Results.push_back(edx.getValue(1)); 13497 return; 13498 } 13499 case ISD::ATOMIC_CMP_SWAP: { 13500 EVT T = N->getValueType(0); 13501 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 13502 bool Regs64bit = T == MVT::i128; 13503 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 13504 SDValue cpInL, cpInH; 13505 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 13506 DAG.getConstant(0, HalfT)); 13507 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 13508 DAG.getConstant(1, HalfT)); 13509 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 13510 Regs64bit ? X86::RAX : X86::EAX, 13511 cpInL, SDValue()); 13512 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 13513 Regs64bit ? X86::RDX : X86::EDX, 13514 cpInH, cpInL.getValue(1)); 13515 SDValue swapInL, swapInH; 13516 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 13517 DAG.getConstant(0, HalfT)); 13518 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 13519 DAG.getConstant(1, HalfT)); 13520 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 13521 Regs64bit ? X86::RBX : X86::EBX, 13522 swapInL, cpInH.getValue(1)); 13523 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 13524 Regs64bit ? X86::RCX : X86::ECX, 13525 swapInH, swapInL.getValue(1)); 13526 SDValue Ops[] = { swapInH.getValue(0), 13527 N->getOperand(1), 13528 swapInH.getValue(1) }; 13529 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 13530 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 13531 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 13532 X86ISD::LCMPXCHG8_DAG; 13533 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 13534 Ops, array_lengthof(Ops), T, MMO); 13535 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 13536 Regs64bit ? X86::RAX : X86::EAX, 13537 HalfT, Result.getValue(1)); 13538 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 13539 Regs64bit ? X86::RDX : X86::EDX, 13540 HalfT, cpOutL.getValue(2)); 13541 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 13542 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 13543 Results.push_back(cpOutH.getValue(1)); 13544 return; 13545 } 13546 case ISD::ATOMIC_LOAD_ADD: 13547 case ISD::ATOMIC_LOAD_AND: 13548 case ISD::ATOMIC_LOAD_NAND: 13549 case ISD::ATOMIC_LOAD_OR: 13550 case ISD::ATOMIC_LOAD_SUB: 13551 case ISD::ATOMIC_LOAD_XOR: 13552 case ISD::ATOMIC_LOAD_MAX: 13553 case ISD::ATOMIC_LOAD_MIN: 13554 case ISD::ATOMIC_LOAD_UMAX: 13555 case ISD::ATOMIC_LOAD_UMIN: 13556 case ISD::ATOMIC_SWAP: { 13557 unsigned Opc; 13558 switch (N->getOpcode()) { 13559 default: llvm_unreachable("Unexpected opcode"); 13560 case ISD::ATOMIC_LOAD_ADD: 13561 Opc = X86ISD::ATOMADD64_DAG; 13562 break; 13563 case ISD::ATOMIC_LOAD_AND: 13564 Opc = X86ISD::ATOMAND64_DAG; 13565 break; 13566 case ISD::ATOMIC_LOAD_NAND: 13567 Opc = X86ISD::ATOMNAND64_DAG; 13568 break; 13569 case ISD::ATOMIC_LOAD_OR: 13570 Opc = X86ISD::ATOMOR64_DAG; 13571 break; 13572 case ISD::ATOMIC_LOAD_SUB: 13573 Opc = X86ISD::ATOMSUB64_DAG; 13574 break; 13575 case ISD::ATOMIC_LOAD_XOR: 13576 Opc = X86ISD::ATOMXOR64_DAG; 13577 break; 13578 case ISD::ATOMIC_LOAD_MAX: 13579 Opc = X86ISD::ATOMMAX64_DAG; 13580 break; 13581 case ISD::ATOMIC_LOAD_MIN: 13582 Opc = X86ISD::ATOMMIN64_DAG; 13583 break; 13584 case ISD::ATOMIC_LOAD_UMAX: 13585 Opc = X86ISD::ATOMUMAX64_DAG; 13586 break; 13587 case ISD::ATOMIC_LOAD_UMIN: 13588 Opc = X86ISD::ATOMUMIN64_DAG; 13589 break; 13590 case ISD::ATOMIC_SWAP: 13591 Opc = X86ISD::ATOMSWAP64_DAG; 13592 break; 13593 } 13594 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc); 13595 return; 13596 } 13597 case ISD::ATOMIC_LOAD: 13598 ReplaceATOMIC_LOAD(N, Results, DAG); 13599 } 13600} 13601 13602const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 13603 switch (Opcode) { 13604 default: return NULL; 13605 case X86ISD::BSF: return "X86ISD::BSF"; 13606 case X86ISD::BSR: return "X86ISD::BSR"; 13607 case X86ISD::SHLD: return "X86ISD::SHLD"; 13608 case X86ISD::SHRD: return "X86ISD::SHRD"; 13609 case X86ISD::FAND: return "X86ISD::FAND"; 13610 case X86ISD::FANDN: return "X86ISD::FANDN"; 13611 case X86ISD::FOR: return "X86ISD::FOR"; 13612 case X86ISD::FXOR: return "X86ISD::FXOR"; 13613 case X86ISD::FSRL: return "X86ISD::FSRL"; 13614 case X86ISD::FILD: return "X86ISD::FILD"; 13615 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 13616 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 13617 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 13618 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 13619 case X86ISD::FLD: return "X86ISD::FLD"; 13620 case X86ISD::FST: return "X86ISD::FST"; 13621 case X86ISD::CALL: return "X86ISD::CALL"; 13622 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 13623 case X86ISD::BT: return "X86ISD::BT"; 13624 case X86ISD::CMP: return "X86ISD::CMP"; 13625 case X86ISD::COMI: return "X86ISD::COMI"; 13626 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 13627 case X86ISD::CMPM: return "X86ISD::CMPM"; 13628 case X86ISD::CMPMU: return "X86ISD::CMPMU"; 13629 case X86ISD::SETCC: return "X86ISD::SETCC"; 13630 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 13631 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 13632 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 13633 case X86ISD::CMOV: return "X86ISD::CMOV"; 13634 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 13635 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 13636 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 13637 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 13638 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 13639 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 13640 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 13641 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 13642 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 13643 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 13644 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 13645 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 13646 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 13647 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 13648 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 13649 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 13650 case X86ISD::BLENDI: return "X86ISD::BLENDI"; 13651 case X86ISD::SUBUS: return "X86ISD::SUBUS"; 13652 case X86ISD::HADD: return "X86ISD::HADD"; 13653 case X86ISD::HSUB: return "X86ISD::HSUB"; 13654 case X86ISD::FHADD: return "X86ISD::FHADD"; 13655 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 13656 case X86ISD::UMAX: return "X86ISD::UMAX"; 13657 case X86ISD::UMIN: return "X86ISD::UMIN"; 13658 case X86ISD::SMAX: return "X86ISD::SMAX"; 13659 case X86ISD::SMIN: return "X86ISD::SMIN"; 13660 case X86ISD::FMAX: return "X86ISD::FMAX"; 13661 case X86ISD::FMIN: return "X86ISD::FMIN"; 13662 case X86ISD::FMAXC: return "X86ISD::FMAXC"; 13663 case X86ISD::FMINC: return "X86ISD::FMINC"; 13664 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 13665 case X86ISD::FRCP: return "X86ISD::FRCP"; 13666 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 13667 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR"; 13668 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 13669 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP"; 13670 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP"; 13671 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 13672 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 13673 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 13674 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 13675 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 13676 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 13677 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 13678 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 13679 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 13680 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 13681 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 13682 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 13683 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 13684 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL"; 13685 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 13686 case X86ISD::VZEXT: return "X86ISD::VZEXT"; 13687 case X86ISD::VSEXT: return "X86ISD::VSEXT"; 13688 case X86ISD::VTRUNC: return "X86ISD::VTRUNC"; 13689 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM"; 13690 case X86ISD::VINSERT: return "X86ISD::VINSERT"; 13691 case X86ISD::VFPEXT: return "X86ISD::VFPEXT"; 13692 case X86ISD::VFPROUND: return "X86ISD::VFPROUND"; 13693 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 13694 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 13695 case X86ISD::VSHL: return "X86ISD::VSHL"; 13696 case X86ISD::VSRL: return "X86ISD::VSRL"; 13697 case X86ISD::VSRA: return "X86ISD::VSRA"; 13698 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 13699 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 13700 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 13701 case X86ISD::CMPP: return "X86ISD::CMPP"; 13702 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 13703 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 13704 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM"; 13705 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM"; 13706 case X86ISD::ADD: return "X86ISD::ADD"; 13707 case X86ISD::SUB: return "X86ISD::SUB"; 13708 case X86ISD::ADC: return "X86ISD::ADC"; 13709 case X86ISD::SBB: return "X86ISD::SBB"; 13710 case X86ISD::SMUL: return "X86ISD::SMUL"; 13711 case X86ISD::UMUL: return "X86ISD::UMUL"; 13712 case X86ISD::INC: return "X86ISD::INC"; 13713 case X86ISD::DEC: return "X86ISD::DEC"; 13714 case X86ISD::OR: return "X86ISD::OR"; 13715 case X86ISD::XOR: return "X86ISD::XOR"; 13716 case X86ISD::AND: return "X86ISD::AND"; 13717 case X86ISD::BLSI: return "X86ISD::BLSI"; 13718 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 13719 case X86ISD::BLSR: return "X86ISD::BLSR"; 13720 case X86ISD::BZHI: return "X86ISD::BZHI"; 13721 case X86ISD::BEXTR: return "X86ISD::BEXTR"; 13722 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 13723 case X86ISD::PTEST: return "X86ISD::PTEST"; 13724 case X86ISD::TESTP: return "X86ISD::TESTP"; 13725 case X86ISD::TESTM: return "X86ISD::TESTM"; 13726 case X86ISD::KORTEST: return "X86ISD::KORTEST"; 13727 case X86ISD::KTEST: return "X86ISD::KTEST"; 13728 case X86ISD::PALIGNR: return "X86ISD::PALIGNR"; 13729 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 13730 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 13731 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 13732 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 13733 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 13734 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 13735 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 13736 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 13737 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 13738 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 13739 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 13740 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 13741 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 13742 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 13743 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 13744 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 13745 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 13746 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM"; 13747 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 13748 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 13749 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 13750 case X86ISD::VPERMV3: return "X86ISD::VPERMV3"; 13751 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 13752 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 13753 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 13754 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 13755 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 13756 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 13757 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 13758 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 13759 case X86ISD::SAHF: return "X86ISD::SAHF"; 13760 case X86ISD::RDRAND: return "X86ISD::RDRAND"; 13761 case X86ISD::RDSEED: return "X86ISD::RDSEED"; 13762 case X86ISD::FMADD: return "X86ISD::FMADD"; 13763 case X86ISD::FMSUB: return "X86ISD::FMSUB"; 13764 case X86ISD::FNMADD: return "X86ISD::FNMADD"; 13765 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; 13766 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB"; 13767 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD"; 13768 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI"; 13769 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI"; 13770 case X86ISD::XTEST: return "X86ISD::XTEST"; 13771 } 13772} 13773 13774// isLegalAddressingMode - Return true if the addressing mode represented 13775// by AM is legal for this target, for a load/store of the specified type. 13776bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 13777 Type *Ty) const { 13778 // X86 supports extremely general addressing modes. 13779 CodeModel::Model M = getTargetMachine().getCodeModel(); 13780 Reloc::Model R = getTargetMachine().getRelocationModel(); 13781 13782 // X86 allows a sign-extended 32-bit immediate field as a displacement. 13783 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 13784 return false; 13785 13786 if (AM.BaseGV) { 13787 unsigned GVFlags = 13788 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 13789 13790 // If a reference to this global requires an extra load, we can't fold it. 13791 if (isGlobalStubReference(GVFlags)) 13792 return false; 13793 13794 // If BaseGV requires a register for the PIC base, we cannot also have a 13795 // BaseReg specified. 13796 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 13797 return false; 13798 13799 // If lower 4G is not available, then we must use rip-relative addressing. 13800 if ((M != CodeModel::Small || R != Reloc::Static) && 13801 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 13802 return false; 13803 } 13804 13805 switch (AM.Scale) { 13806 case 0: 13807 case 1: 13808 case 2: 13809 case 4: 13810 case 8: 13811 // These scales always work. 13812 break; 13813 case 3: 13814 case 5: 13815 case 9: 13816 // These scales are formed with basereg+scalereg. Only accept if there is 13817 // no basereg yet. 13818 if (AM.HasBaseReg) 13819 return false; 13820 break; 13821 default: // Other stuff never works. 13822 return false; 13823 } 13824 13825 return true; 13826} 13827 13828bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 13829 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 13830 return false; 13831 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 13832 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 13833 return NumBits1 > NumBits2; 13834} 13835 13836bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const { 13837 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 13838 return false; 13839 13840 if (!isTypeLegal(EVT::getEVT(Ty1))) 13841 return false; 13842 13843 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop"); 13844 13845 // Assuming the caller doesn't have a zeroext or signext return parameter, 13846 // truncation all the way down to i1 is valid. 13847 return true; 13848} 13849 13850bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { 13851 return isInt<32>(Imm); 13852} 13853 13854bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { 13855 // Can also use sub to handle negated immediates. 13856 return isInt<32>(Imm); 13857} 13858 13859bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 13860 if (!VT1.isInteger() || !VT2.isInteger()) 13861 return false; 13862 unsigned NumBits1 = VT1.getSizeInBits(); 13863 unsigned NumBits2 = VT2.getSizeInBits(); 13864 return NumBits1 > NumBits2; 13865} 13866 13867bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 13868 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 13869 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 13870} 13871 13872bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 13873 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 13874 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 13875} 13876 13877bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 13878 EVT VT1 = Val.getValueType(); 13879 if (isZExtFree(VT1, VT2)) 13880 return true; 13881 13882 if (Val.getOpcode() != ISD::LOAD) 13883 return false; 13884 13885 if (!VT1.isSimple() || !VT1.isInteger() || 13886 !VT2.isSimple() || !VT2.isInteger()) 13887 return false; 13888 13889 switch (VT1.getSimpleVT().SimpleTy) { 13890 default: break; 13891 case MVT::i8: 13892 case MVT::i16: 13893 case MVT::i32: 13894 // X86 has 8, 16, and 32-bit zero-extending loads. 13895 return true; 13896 } 13897 13898 return false; 13899} 13900 13901bool 13902X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { 13903 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4())) 13904 return false; 13905 13906 VT = VT.getScalarType(); 13907 13908 if (!VT.isSimple()) 13909 return false; 13910 13911 switch (VT.getSimpleVT().SimpleTy) { 13912 case MVT::f32: 13913 case MVT::f64: 13914 return true; 13915 default: 13916 break; 13917 } 13918 13919 return false; 13920} 13921 13922bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 13923 // i16 instructions are longer (0x66 prefix) and potentially slower. 13924 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 13925} 13926 13927/// isShuffleMaskLegal - Targets can use this to indicate that they only 13928/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 13929/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 13930/// are assumed to be legal. 13931bool 13932X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 13933 EVT VT) const { 13934 if (!VT.isSimple()) 13935 return false; 13936 13937 MVT SVT = VT.getSimpleVT(); 13938 13939 // Very little shuffling can be done for 64-bit vectors right now. 13940 if (VT.getSizeInBits() == 64) 13941 return false; 13942 13943 // FIXME: pshufb, blends, shifts. 13944 return (SVT.getVectorNumElements() == 2 || 13945 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 13946 isMOVLMask(M, SVT) || 13947 isSHUFPMask(M, SVT) || 13948 isPSHUFDMask(M, SVT) || 13949 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) || 13950 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) || 13951 isPALIGNRMask(M, SVT, Subtarget) || 13952 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) || 13953 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) || 13954 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) || 13955 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256())); 13956} 13957 13958bool 13959X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 13960 EVT VT) const { 13961 if (!VT.isSimple()) 13962 return false; 13963 13964 MVT SVT = VT.getSimpleVT(); 13965 unsigned NumElts = SVT.getVectorNumElements(); 13966 // FIXME: This collection of masks seems suspect. 13967 if (NumElts == 2) 13968 return true; 13969 if (NumElts == 4 && SVT.is128BitVector()) { 13970 return (isMOVLMask(Mask, SVT) || 13971 isCommutedMOVLMask(Mask, SVT, true) || 13972 isSHUFPMask(Mask, SVT) || 13973 isSHUFPMask(Mask, SVT, /* Commuted */ true)); 13974 } 13975 return false; 13976} 13977 13978//===----------------------------------------------------------------------===// 13979// X86 Scheduler Hooks 13980//===----------------------------------------------------------------------===// 13981 13982/// Utility function to emit xbegin specifying the start of an RTM region. 13983static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, 13984 const TargetInstrInfo *TII) { 13985 DebugLoc DL = MI->getDebugLoc(); 13986 13987 const BasicBlock *BB = MBB->getBasicBlock(); 13988 MachineFunction::iterator I = MBB; 13989 ++I; 13990 13991 // For the v = xbegin(), we generate 13992 // 13993 // thisMBB: 13994 // xbegin sinkMBB 13995 // 13996 // mainMBB: 13997 // eax = -1 13998 // 13999 // sinkMBB: 14000 // v = eax 14001 14002 MachineBasicBlock *thisMBB = MBB; 14003 MachineFunction *MF = MBB->getParent(); 14004 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 14005 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 14006 MF->insert(I, mainMBB); 14007 MF->insert(I, sinkMBB); 14008 14009 // Transfer the remainder of BB and its successor edges to sinkMBB. 14010 sinkMBB->splice(sinkMBB->begin(), MBB, 14011 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 14012 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 14013 14014 // thisMBB: 14015 // xbegin sinkMBB 14016 // # fallthrough to mainMBB 14017 // # abortion to sinkMBB 14018 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB); 14019 thisMBB->addSuccessor(mainMBB); 14020 thisMBB->addSuccessor(sinkMBB); 14021 14022 // mainMBB: 14023 // EAX = -1 14024 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1); 14025 mainMBB->addSuccessor(sinkMBB); 14026 14027 // sinkMBB: 14028 // EAX is live into the sinkMBB 14029 sinkMBB->addLiveIn(X86::EAX); 14030 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14031 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 14032 .addReg(X86::EAX); 14033 14034 MI->eraseFromParent(); 14035 return sinkMBB; 14036} 14037 14038// Get CMPXCHG opcode for the specified data type. 14039static unsigned getCmpXChgOpcode(EVT VT) { 14040 switch (VT.getSimpleVT().SimpleTy) { 14041 case MVT::i8: return X86::LCMPXCHG8; 14042 case MVT::i16: return X86::LCMPXCHG16; 14043 case MVT::i32: return X86::LCMPXCHG32; 14044 case MVT::i64: return X86::LCMPXCHG64; 14045 default: 14046 break; 14047 } 14048 llvm_unreachable("Invalid operand size!"); 14049} 14050 14051// Get LOAD opcode for the specified data type. 14052static unsigned getLoadOpcode(EVT VT) { 14053 switch (VT.getSimpleVT().SimpleTy) { 14054 case MVT::i8: return X86::MOV8rm; 14055 case MVT::i16: return X86::MOV16rm; 14056 case MVT::i32: return X86::MOV32rm; 14057 case MVT::i64: return X86::MOV64rm; 14058 default: 14059 break; 14060 } 14061 llvm_unreachable("Invalid operand size!"); 14062} 14063 14064// Get opcode of the non-atomic one from the specified atomic instruction. 14065static unsigned getNonAtomicOpcode(unsigned Opc) { 14066 switch (Opc) { 14067 case X86::ATOMAND8: return X86::AND8rr; 14068 case X86::ATOMAND16: return X86::AND16rr; 14069 case X86::ATOMAND32: return X86::AND32rr; 14070 case X86::ATOMAND64: return X86::AND64rr; 14071 case X86::ATOMOR8: return X86::OR8rr; 14072 case X86::ATOMOR16: return X86::OR16rr; 14073 case X86::ATOMOR32: return X86::OR32rr; 14074 case X86::ATOMOR64: return X86::OR64rr; 14075 case X86::ATOMXOR8: return X86::XOR8rr; 14076 case X86::ATOMXOR16: return X86::XOR16rr; 14077 case X86::ATOMXOR32: return X86::XOR32rr; 14078 case X86::ATOMXOR64: return X86::XOR64rr; 14079 } 14080 llvm_unreachable("Unhandled atomic-load-op opcode!"); 14081} 14082 14083// Get opcode of the non-atomic one from the specified atomic instruction with 14084// extra opcode. 14085static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc, 14086 unsigned &ExtraOpc) { 14087 switch (Opc) { 14088 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr; 14089 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr; 14090 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr; 14091 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr; 14092 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr; 14093 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr; 14094 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr; 14095 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr; 14096 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr; 14097 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr; 14098 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr; 14099 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr; 14100 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr; 14101 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr; 14102 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr; 14103 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr; 14104 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr; 14105 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr; 14106 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr; 14107 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr; 14108 } 14109 llvm_unreachable("Unhandled atomic-load-op opcode!"); 14110} 14111 14112// Get opcode of the non-atomic one from the specified atomic instruction for 14113// 64-bit data type on 32-bit target. 14114static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) { 14115 switch (Opc) { 14116 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr; 14117 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr; 14118 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr; 14119 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr; 14120 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr; 14121 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr; 14122 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr; 14123 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr; 14124 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr; 14125 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr; 14126 } 14127 llvm_unreachable("Unhandled atomic-load-op opcode!"); 14128} 14129 14130// Get opcode of the non-atomic one from the specified atomic instruction for 14131// 64-bit data type on 32-bit target with extra opcode. 14132static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc, 14133 unsigned &HiOpc, 14134 unsigned &ExtraOpc) { 14135 switch (Opc) { 14136 case X86::ATOMNAND6432: 14137 ExtraOpc = X86::NOT32r; 14138 HiOpc = X86::AND32rr; 14139 return X86::AND32rr; 14140 } 14141 llvm_unreachable("Unhandled atomic-load-op opcode!"); 14142} 14143 14144// Get pseudo CMOV opcode from the specified data type. 14145static unsigned getPseudoCMOVOpc(EVT VT) { 14146 switch (VT.getSimpleVT().SimpleTy) { 14147 case MVT::i8: return X86::CMOV_GR8; 14148 case MVT::i16: return X86::CMOV_GR16; 14149 case MVT::i32: return X86::CMOV_GR32; 14150 default: 14151 break; 14152 } 14153 llvm_unreachable("Unknown CMOV opcode!"); 14154} 14155 14156// EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions. 14157// They will be translated into a spin-loop or compare-exchange loop from 14158// 14159// ... 14160// dst = atomic-fetch-op MI.addr, MI.val 14161// ... 14162// 14163// to 14164// 14165// ... 14166// t1 = LOAD MI.addr 14167// loop: 14168// t4 = phi(t1, t3 / loop) 14169// t2 = OP MI.val, t4 14170// EAX = t4 14171// LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined] 14172// t3 = EAX 14173// JNE loop 14174// sink: 14175// dst = t3 14176// ... 14177MachineBasicBlock * 14178X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI, 14179 MachineBasicBlock *MBB) const { 14180 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14181 DebugLoc DL = MI->getDebugLoc(); 14182 14183 MachineFunction *MF = MBB->getParent(); 14184 MachineRegisterInfo &MRI = MF->getRegInfo(); 14185 14186 const BasicBlock *BB = MBB->getBasicBlock(); 14187 MachineFunction::iterator I = MBB; 14188 ++I; 14189 14190 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 && 14191 "Unexpected number of operands"); 14192 14193 assert(MI->hasOneMemOperand() && 14194 "Expected atomic-load-op to have one memoperand"); 14195 14196 // Memory Reference 14197 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14198 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14199 14200 unsigned DstReg, SrcReg; 14201 unsigned MemOpndSlot; 14202 14203 unsigned CurOp = 0; 14204 14205 DstReg = MI->getOperand(CurOp++).getReg(); 14206 MemOpndSlot = CurOp; 14207 CurOp += X86::AddrNumOperands; 14208 SrcReg = MI->getOperand(CurOp++).getReg(); 14209 14210 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 14211 MVT::SimpleValueType VT = *RC->vt_begin(); 14212 unsigned t1 = MRI.createVirtualRegister(RC); 14213 unsigned t2 = MRI.createVirtualRegister(RC); 14214 unsigned t3 = MRI.createVirtualRegister(RC); 14215 unsigned t4 = MRI.createVirtualRegister(RC); 14216 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT); 14217 14218 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT); 14219 unsigned LOADOpc = getLoadOpcode(VT); 14220 14221 // For the atomic load-arith operator, we generate 14222 // 14223 // thisMBB: 14224 // t1 = LOAD [MI.addr] 14225 // mainMBB: 14226 // t4 = phi(t1 / thisMBB, t3 / mainMBB) 14227 // t1 = OP MI.val, EAX 14228 // EAX = t4 14229 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 14230 // t3 = EAX 14231 // JNE mainMBB 14232 // sinkMBB: 14233 // dst = t3 14234 14235 MachineBasicBlock *thisMBB = MBB; 14236 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 14237 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 14238 MF->insert(I, mainMBB); 14239 MF->insert(I, sinkMBB); 14240 14241 MachineInstrBuilder MIB; 14242 14243 // Transfer the remainder of BB and its successor edges to sinkMBB. 14244 sinkMBB->splice(sinkMBB->begin(), MBB, 14245 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 14246 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 14247 14248 // thisMBB: 14249 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1); 14250 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14251 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 14252 if (NewMO.isReg()) 14253 NewMO.setIsKill(false); 14254 MIB.addOperand(NewMO); 14255 } 14256 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) { 14257 unsigned flags = (*MMOI)->getFlags(); 14258 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad; 14259 MachineMemOperand *MMO = 14260 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags, 14261 (*MMOI)->getSize(), 14262 (*MMOI)->getBaseAlignment(), 14263 (*MMOI)->getTBAAInfo(), 14264 (*MMOI)->getRanges()); 14265 MIB.addMemOperand(MMO); 14266 } 14267 14268 thisMBB->addSuccessor(mainMBB); 14269 14270 // mainMBB: 14271 MachineBasicBlock *origMainMBB = mainMBB; 14272 14273 // Add a PHI. 14274 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4) 14275 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB); 14276 14277 unsigned Opc = MI->getOpcode(); 14278 switch (Opc) { 14279 default: 14280 llvm_unreachable("Unhandled atomic-load-op opcode!"); 14281 case X86::ATOMAND8: 14282 case X86::ATOMAND16: 14283 case X86::ATOMAND32: 14284 case X86::ATOMAND64: 14285 case X86::ATOMOR8: 14286 case X86::ATOMOR16: 14287 case X86::ATOMOR32: 14288 case X86::ATOMOR64: 14289 case X86::ATOMXOR8: 14290 case X86::ATOMXOR16: 14291 case X86::ATOMXOR32: 14292 case X86::ATOMXOR64: { 14293 unsigned ARITHOpc = getNonAtomicOpcode(Opc); 14294 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg) 14295 .addReg(t4); 14296 break; 14297 } 14298 case X86::ATOMNAND8: 14299 case X86::ATOMNAND16: 14300 case X86::ATOMNAND32: 14301 case X86::ATOMNAND64: { 14302 unsigned Tmp = MRI.createVirtualRegister(RC); 14303 unsigned NOTOpc; 14304 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc); 14305 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg) 14306 .addReg(t4); 14307 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp); 14308 break; 14309 } 14310 case X86::ATOMMAX8: 14311 case X86::ATOMMAX16: 14312 case X86::ATOMMAX32: 14313 case X86::ATOMMAX64: 14314 case X86::ATOMMIN8: 14315 case X86::ATOMMIN16: 14316 case X86::ATOMMIN32: 14317 case X86::ATOMMIN64: 14318 case X86::ATOMUMAX8: 14319 case X86::ATOMUMAX16: 14320 case X86::ATOMUMAX32: 14321 case X86::ATOMUMAX64: 14322 case X86::ATOMUMIN8: 14323 case X86::ATOMUMIN16: 14324 case X86::ATOMUMIN32: 14325 case X86::ATOMUMIN64: { 14326 unsigned CMPOpc; 14327 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc); 14328 14329 BuildMI(mainMBB, DL, TII->get(CMPOpc)) 14330 .addReg(SrcReg) 14331 .addReg(t4); 14332 14333 if (Subtarget->hasCMov()) { 14334 if (VT != MVT::i8) { 14335 // Native support 14336 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2) 14337 .addReg(SrcReg) 14338 .addReg(t4); 14339 } else { 14340 // Promote i8 to i32 to use CMOV32 14341 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 14342 const TargetRegisterClass *RC32 = 14343 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit); 14344 unsigned SrcReg32 = MRI.createVirtualRegister(RC32); 14345 unsigned AccReg32 = MRI.createVirtualRegister(RC32); 14346 unsigned Tmp = MRI.createVirtualRegister(RC32); 14347 14348 unsigned Undef = MRI.createVirtualRegister(RC32); 14349 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef); 14350 14351 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32) 14352 .addReg(Undef) 14353 .addReg(SrcReg) 14354 .addImm(X86::sub_8bit); 14355 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32) 14356 .addReg(Undef) 14357 .addReg(t4) 14358 .addImm(X86::sub_8bit); 14359 14360 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp) 14361 .addReg(SrcReg32) 14362 .addReg(AccReg32); 14363 14364 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2) 14365 .addReg(Tmp, 0, X86::sub_8bit); 14366 } 14367 } else { 14368 // Use pseudo select and lower them. 14369 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && 14370 "Invalid atomic-load-op transformation!"); 14371 unsigned SelOpc = getPseudoCMOVOpc(VT); 14372 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc); 14373 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!"); 14374 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2) 14375 .addReg(SrcReg).addReg(t4) 14376 .addImm(CC); 14377 mainMBB = EmitLoweredSelect(MIB, mainMBB); 14378 // Replace the original PHI node as mainMBB is changed after CMOV 14379 // lowering. 14380 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4) 14381 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB); 14382 Phi->eraseFromParent(); 14383 } 14384 break; 14385 } 14386 } 14387 14388 // Copy PhyReg back from virtual register. 14389 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg) 14390 .addReg(t4); 14391 14392 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 14393 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14394 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 14395 if (NewMO.isReg()) 14396 NewMO.setIsKill(false); 14397 MIB.addOperand(NewMO); 14398 } 14399 MIB.addReg(t2); 14400 MIB.setMemRefs(MMOBegin, MMOEnd); 14401 14402 // Copy PhyReg back to virtual register. 14403 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3) 14404 .addReg(PhyReg); 14405 14406 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 14407 14408 mainMBB->addSuccessor(origMainMBB); 14409 mainMBB->addSuccessor(sinkMBB); 14410 14411 // sinkMBB: 14412 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14413 TII->get(TargetOpcode::COPY), DstReg) 14414 .addReg(t3); 14415 14416 MI->eraseFromParent(); 14417 return sinkMBB; 14418} 14419 14420// EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic 14421// instructions. They will be translated into a spin-loop or compare-exchange 14422// loop from 14423// 14424// ... 14425// dst = atomic-fetch-op MI.addr, MI.val 14426// ... 14427// 14428// to 14429// 14430// ... 14431// t1L = LOAD [MI.addr + 0] 14432// t1H = LOAD [MI.addr + 4] 14433// loop: 14434// t4L = phi(t1L, t3L / loop) 14435// t4H = phi(t1H, t3H / loop) 14436// t2L = OP MI.val.lo, t4L 14437// t2H = OP MI.val.hi, t4H 14438// EAX = t4L 14439// EDX = t4H 14440// EBX = t2L 14441// ECX = t2H 14442// LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 14443// t3L = EAX 14444// t3H = EDX 14445// JNE loop 14446// sink: 14447// dstL = t3L 14448// dstH = t3H 14449// ... 14450MachineBasicBlock * 14451X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, 14452 MachineBasicBlock *MBB) const { 14453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14454 DebugLoc DL = MI->getDebugLoc(); 14455 14456 MachineFunction *MF = MBB->getParent(); 14457 MachineRegisterInfo &MRI = MF->getRegInfo(); 14458 14459 const BasicBlock *BB = MBB->getBasicBlock(); 14460 MachineFunction::iterator I = MBB; 14461 ++I; 14462 14463 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 && 14464 "Unexpected number of operands"); 14465 14466 assert(MI->hasOneMemOperand() && 14467 "Expected atomic-load-op32 to have one memoperand"); 14468 14469 // Memory Reference 14470 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14471 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14472 14473 unsigned DstLoReg, DstHiReg; 14474 unsigned SrcLoReg, SrcHiReg; 14475 unsigned MemOpndSlot; 14476 14477 unsigned CurOp = 0; 14478 14479 DstLoReg = MI->getOperand(CurOp++).getReg(); 14480 DstHiReg = MI->getOperand(CurOp++).getReg(); 14481 MemOpndSlot = CurOp; 14482 CurOp += X86::AddrNumOperands; 14483 SrcLoReg = MI->getOperand(CurOp++).getReg(); 14484 SrcHiReg = MI->getOperand(CurOp++).getReg(); 14485 14486 const TargetRegisterClass *RC = &X86::GR32RegClass; 14487 const TargetRegisterClass *RC8 = &X86::GR8RegClass; 14488 14489 unsigned t1L = MRI.createVirtualRegister(RC); 14490 unsigned t1H = MRI.createVirtualRegister(RC); 14491 unsigned t2L = MRI.createVirtualRegister(RC); 14492 unsigned t2H = MRI.createVirtualRegister(RC); 14493 unsigned t3L = MRI.createVirtualRegister(RC); 14494 unsigned t3H = MRI.createVirtualRegister(RC); 14495 unsigned t4L = MRI.createVirtualRegister(RC); 14496 unsigned t4H = MRI.createVirtualRegister(RC); 14497 14498 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B; 14499 unsigned LOADOpc = X86::MOV32rm; 14500 14501 // For the atomic load-arith operator, we generate 14502 // 14503 // thisMBB: 14504 // t1L = LOAD [MI.addr + 0] 14505 // t1H = LOAD [MI.addr + 4] 14506 // mainMBB: 14507 // t4L = phi(t1L / thisMBB, t3L / mainMBB) 14508 // t4H = phi(t1H / thisMBB, t3H / mainMBB) 14509 // t2L = OP MI.val.lo, t4L 14510 // t2H = OP MI.val.hi, t4H 14511 // EBX = t2L 14512 // ECX = t2H 14513 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 14514 // t3L = EAX 14515 // t3H = EDX 14516 // JNE loop 14517 // sinkMBB: 14518 // dstL = t3L 14519 // dstH = t3H 14520 14521 MachineBasicBlock *thisMBB = MBB; 14522 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 14523 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 14524 MF->insert(I, mainMBB); 14525 MF->insert(I, sinkMBB); 14526 14527 MachineInstrBuilder MIB; 14528 14529 // Transfer the remainder of BB and its successor edges to sinkMBB. 14530 sinkMBB->splice(sinkMBB->begin(), MBB, 14531 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 14532 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 14533 14534 // thisMBB: 14535 // Lo 14536 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L); 14537 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14538 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 14539 if (NewMO.isReg()) 14540 NewMO.setIsKill(false); 14541 MIB.addOperand(NewMO); 14542 } 14543 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) { 14544 unsigned flags = (*MMOI)->getFlags(); 14545 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad; 14546 MachineMemOperand *MMO = 14547 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags, 14548 (*MMOI)->getSize(), 14549 (*MMOI)->getBaseAlignment(), 14550 (*MMOI)->getTBAAInfo(), 14551 (*MMOI)->getRanges()); 14552 MIB.addMemOperand(MMO); 14553 }; 14554 MachineInstr *LowMI = MIB; 14555 14556 // Hi 14557 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H); 14558 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14559 if (i == X86::AddrDisp) { 14560 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32) 14561 } else { 14562 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 14563 if (NewMO.isReg()) 14564 NewMO.setIsKill(false); 14565 MIB.addOperand(NewMO); 14566 } 14567 } 14568 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end()); 14569 14570 thisMBB->addSuccessor(mainMBB); 14571 14572 // mainMBB: 14573 MachineBasicBlock *origMainMBB = mainMBB; 14574 14575 // Add PHIs. 14576 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L) 14577 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB); 14578 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H) 14579 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB); 14580 14581 unsigned Opc = MI->getOpcode(); 14582 switch (Opc) { 14583 default: 14584 llvm_unreachable("Unhandled atomic-load-op6432 opcode!"); 14585 case X86::ATOMAND6432: 14586 case X86::ATOMOR6432: 14587 case X86::ATOMXOR6432: 14588 case X86::ATOMADD6432: 14589 case X86::ATOMSUB6432: { 14590 unsigned HiOpc; 14591 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 14592 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L) 14593 .addReg(SrcLoReg); 14594 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H) 14595 .addReg(SrcHiReg); 14596 break; 14597 } 14598 case X86::ATOMNAND6432: { 14599 unsigned HiOpc, NOTOpc; 14600 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc); 14601 unsigned TmpL = MRI.createVirtualRegister(RC); 14602 unsigned TmpH = MRI.createVirtualRegister(RC); 14603 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg) 14604 .addReg(t4L); 14605 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg) 14606 .addReg(t4H); 14607 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL); 14608 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH); 14609 break; 14610 } 14611 case X86::ATOMMAX6432: 14612 case X86::ATOMMIN6432: 14613 case X86::ATOMUMAX6432: 14614 case X86::ATOMUMIN6432: { 14615 unsigned HiOpc; 14616 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 14617 unsigned cL = MRI.createVirtualRegister(RC8); 14618 unsigned cH = MRI.createVirtualRegister(RC8); 14619 unsigned cL32 = MRI.createVirtualRegister(RC); 14620 unsigned cH32 = MRI.createVirtualRegister(RC); 14621 unsigned cc = MRI.createVirtualRegister(RC); 14622 // cl := cmp src_lo, lo 14623 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 14624 .addReg(SrcLoReg).addReg(t4L); 14625 BuildMI(mainMBB, DL, TII->get(LoOpc), cL); 14626 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL); 14627 // ch := cmp src_hi, hi 14628 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 14629 .addReg(SrcHiReg).addReg(t4H); 14630 BuildMI(mainMBB, DL, TII->get(HiOpc), cH); 14631 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH); 14632 // cc := if (src_hi == hi) ? cl : ch; 14633 if (Subtarget->hasCMov()) { 14634 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc) 14635 .addReg(cH32).addReg(cL32); 14636 } else { 14637 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc) 14638 .addReg(cH32).addReg(cL32) 14639 .addImm(X86::COND_E); 14640 mainMBB = EmitLoweredSelect(MIB, mainMBB); 14641 } 14642 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc); 14643 if (Subtarget->hasCMov()) { 14644 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L) 14645 .addReg(SrcLoReg).addReg(t4L); 14646 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H) 14647 .addReg(SrcHiReg).addReg(t4H); 14648 } else { 14649 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L) 14650 .addReg(SrcLoReg).addReg(t4L) 14651 .addImm(X86::COND_NE); 14652 mainMBB = EmitLoweredSelect(MIB, mainMBB); 14653 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the 14654 // 2nd CMOV lowering. 14655 mainMBB->addLiveIn(X86::EFLAGS); 14656 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H) 14657 .addReg(SrcHiReg).addReg(t4H) 14658 .addImm(X86::COND_NE); 14659 mainMBB = EmitLoweredSelect(MIB, mainMBB); 14660 // Replace the original PHI node as mainMBB is changed after CMOV 14661 // lowering. 14662 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L) 14663 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB); 14664 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H) 14665 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB); 14666 PhiL->eraseFromParent(); 14667 PhiH->eraseFromParent(); 14668 } 14669 break; 14670 } 14671 case X86::ATOMSWAP6432: { 14672 unsigned HiOpc; 14673 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 14674 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg); 14675 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg); 14676 break; 14677 } 14678 } 14679 14680 // Copy EDX:EAX back from HiReg:LoReg 14681 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L); 14682 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H); 14683 // Copy ECX:EBX from t1H:t1L 14684 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L); 14685 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H); 14686 14687 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 14688 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14689 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 14690 if (NewMO.isReg()) 14691 NewMO.setIsKill(false); 14692 MIB.addOperand(NewMO); 14693 } 14694 MIB.setMemRefs(MMOBegin, MMOEnd); 14695 14696 // Copy EDX:EAX back to t3H:t3L 14697 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX); 14698 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX); 14699 14700 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 14701 14702 mainMBB->addSuccessor(origMainMBB); 14703 mainMBB->addSuccessor(sinkMBB); 14704 14705 // sinkMBB: 14706 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14707 TII->get(TargetOpcode::COPY), DstLoReg) 14708 .addReg(t3L); 14709 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14710 TII->get(TargetOpcode::COPY), DstHiReg) 14711 .addReg(t3H); 14712 14713 MI->eraseFromParent(); 14714 return sinkMBB; 14715} 14716 14717// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 14718// or XMM0_V32I8 in AVX all of this code can be replaced with that 14719// in the .td file. 14720static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, 14721 const TargetInstrInfo *TII) { 14722 unsigned Opc; 14723 switch (MI->getOpcode()) { 14724 default: llvm_unreachable("illegal opcode!"); 14725 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break; 14726 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break; 14727 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break; 14728 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break; 14729 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break; 14730 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break; 14731 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break; 14732 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break; 14733 } 14734 14735 DebugLoc dl = MI->getDebugLoc(); 14736 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 14737 14738 unsigned NumArgs = MI->getNumOperands(); 14739 for (unsigned i = 1; i < NumArgs; ++i) { 14740 MachineOperand &Op = MI->getOperand(i); 14741 if (!(Op.isReg() && Op.isImplicit())) 14742 MIB.addOperand(Op); 14743 } 14744 if (MI->hasOneMemOperand()) 14745 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 14746 14747 BuildMI(*BB, MI, dl, 14748 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 14749 .addReg(X86::XMM0); 14750 14751 MI->eraseFromParent(); 14752 return BB; 14753} 14754 14755// FIXME: Custom handling because TableGen doesn't support multiple implicit 14756// defs in an instruction pattern 14757static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, 14758 const TargetInstrInfo *TII) { 14759 unsigned Opc; 14760 switch (MI->getOpcode()) { 14761 default: llvm_unreachable("illegal opcode!"); 14762 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break; 14763 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break; 14764 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break; 14765 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break; 14766 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break; 14767 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break; 14768 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break; 14769 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break; 14770 } 14771 14772 DebugLoc dl = MI->getDebugLoc(); 14773 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 14774 14775 unsigned NumArgs = MI->getNumOperands(); // remove the results 14776 for (unsigned i = 1; i < NumArgs; ++i) { 14777 MachineOperand &Op = MI->getOperand(i); 14778 if (!(Op.isReg() && Op.isImplicit())) 14779 MIB.addOperand(Op); 14780 } 14781 if (MI->hasOneMemOperand()) 14782 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 14783 14784 BuildMI(*BB, MI, dl, 14785 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 14786 .addReg(X86::ECX); 14787 14788 MI->eraseFromParent(); 14789 return BB; 14790} 14791 14792static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, 14793 const TargetInstrInfo *TII, 14794 const X86Subtarget* Subtarget) { 14795 DebugLoc dl = MI->getDebugLoc(); 14796 14797 // Address into RAX/EAX, other two args into ECX, EDX. 14798 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 14799 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 14800 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 14801 for (int i = 0; i < X86::AddrNumOperands; ++i) 14802 MIB.addOperand(MI->getOperand(i)); 14803 14804 unsigned ValOps = X86::AddrNumOperands; 14805 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 14806 .addReg(MI->getOperand(ValOps).getReg()); 14807 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 14808 .addReg(MI->getOperand(ValOps+1).getReg()); 14809 14810 // The instruction doesn't actually take any operands though. 14811 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 14812 14813 MI->eraseFromParent(); // The pseudo is gone now. 14814 return BB; 14815} 14816 14817MachineBasicBlock * 14818X86TargetLowering::EmitVAARG64WithCustomInserter( 14819 MachineInstr *MI, 14820 MachineBasicBlock *MBB) const { 14821 // Emit va_arg instruction on X86-64. 14822 14823 // Operands to this pseudo-instruction: 14824 // 0 ) Output : destination address (reg) 14825 // 1-5) Input : va_list address (addr, i64mem) 14826 // 6 ) ArgSize : Size (in bytes) of vararg type 14827 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 14828 // 8 ) Align : Alignment of type 14829 // 9 ) EFLAGS (implicit-def) 14830 14831 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 14832 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 14833 14834 unsigned DestReg = MI->getOperand(0).getReg(); 14835 MachineOperand &Base = MI->getOperand(1); 14836 MachineOperand &Scale = MI->getOperand(2); 14837 MachineOperand &Index = MI->getOperand(3); 14838 MachineOperand &Disp = MI->getOperand(4); 14839 MachineOperand &Segment = MI->getOperand(5); 14840 unsigned ArgSize = MI->getOperand(6).getImm(); 14841 unsigned ArgMode = MI->getOperand(7).getImm(); 14842 unsigned Align = MI->getOperand(8).getImm(); 14843 14844 // Memory Reference 14845 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 14846 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14847 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14848 14849 // Machine Information 14850 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14851 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 14852 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 14853 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 14854 DebugLoc DL = MI->getDebugLoc(); 14855 14856 // struct va_list { 14857 // i32 gp_offset 14858 // i32 fp_offset 14859 // i64 overflow_area (address) 14860 // i64 reg_save_area (address) 14861 // } 14862 // sizeof(va_list) = 24 14863 // alignment(va_list) = 8 14864 14865 unsigned TotalNumIntRegs = 6; 14866 unsigned TotalNumXMMRegs = 8; 14867 bool UseGPOffset = (ArgMode == 1); 14868 bool UseFPOffset = (ArgMode == 2); 14869 unsigned MaxOffset = TotalNumIntRegs * 8 + 14870 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 14871 14872 /* Align ArgSize to a multiple of 8 */ 14873 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 14874 bool NeedsAlign = (Align > 8); 14875 14876 MachineBasicBlock *thisMBB = MBB; 14877 MachineBasicBlock *overflowMBB; 14878 MachineBasicBlock *offsetMBB; 14879 MachineBasicBlock *endMBB; 14880 14881 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 14882 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 14883 unsigned OffsetReg = 0; 14884 14885 if (!UseGPOffset && !UseFPOffset) { 14886 // If we only pull from the overflow region, we don't create a branch. 14887 // We don't need to alter control flow. 14888 OffsetDestReg = 0; // unused 14889 OverflowDestReg = DestReg; 14890 14891 offsetMBB = NULL; 14892 overflowMBB = thisMBB; 14893 endMBB = thisMBB; 14894 } else { 14895 // First emit code to check if gp_offset (or fp_offset) is below the bound. 14896 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 14897 // If not, pull from overflow_area. (branch to overflowMBB) 14898 // 14899 // thisMBB 14900 // | . 14901 // | . 14902 // offsetMBB overflowMBB 14903 // | . 14904 // | . 14905 // endMBB 14906 14907 // Registers for the PHI in endMBB 14908 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 14909 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 14910 14911 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 14912 MachineFunction *MF = MBB->getParent(); 14913 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14914 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14915 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14916 14917 MachineFunction::iterator MBBIter = MBB; 14918 ++MBBIter; 14919 14920 // Insert the new basic blocks 14921 MF->insert(MBBIter, offsetMBB); 14922 MF->insert(MBBIter, overflowMBB); 14923 MF->insert(MBBIter, endMBB); 14924 14925 // Transfer the remainder of MBB and its successor edges to endMBB. 14926 endMBB->splice(endMBB->begin(), thisMBB, 14927 llvm::next(MachineBasicBlock::iterator(MI)), 14928 thisMBB->end()); 14929 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 14930 14931 // Make offsetMBB and overflowMBB successors of thisMBB 14932 thisMBB->addSuccessor(offsetMBB); 14933 thisMBB->addSuccessor(overflowMBB); 14934 14935 // endMBB is a successor of both offsetMBB and overflowMBB 14936 offsetMBB->addSuccessor(endMBB); 14937 overflowMBB->addSuccessor(endMBB); 14938 14939 // Load the offset value into a register 14940 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 14941 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 14942 .addOperand(Base) 14943 .addOperand(Scale) 14944 .addOperand(Index) 14945 .addDisp(Disp, UseFPOffset ? 4 : 0) 14946 .addOperand(Segment) 14947 .setMemRefs(MMOBegin, MMOEnd); 14948 14949 // Check if there is enough room left to pull this argument. 14950 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 14951 .addReg(OffsetReg) 14952 .addImm(MaxOffset + 8 - ArgSizeA8); 14953 14954 // Branch to "overflowMBB" if offset >= max 14955 // Fall through to "offsetMBB" otherwise 14956 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 14957 .addMBB(overflowMBB); 14958 } 14959 14960 // In offsetMBB, emit code to use the reg_save_area. 14961 if (offsetMBB) { 14962 assert(OffsetReg != 0); 14963 14964 // Read the reg_save_area address. 14965 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 14966 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 14967 .addOperand(Base) 14968 .addOperand(Scale) 14969 .addOperand(Index) 14970 .addDisp(Disp, 16) 14971 .addOperand(Segment) 14972 .setMemRefs(MMOBegin, MMOEnd); 14973 14974 // Zero-extend the offset 14975 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 14976 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 14977 .addImm(0) 14978 .addReg(OffsetReg) 14979 .addImm(X86::sub_32bit); 14980 14981 // Add the offset to the reg_save_area to get the final address. 14982 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 14983 .addReg(OffsetReg64) 14984 .addReg(RegSaveReg); 14985 14986 // Compute the offset for the next argument 14987 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 14988 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 14989 .addReg(OffsetReg) 14990 .addImm(UseFPOffset ? 16 : 8); 14991 14992 // Store it back into the va_list. 14993 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 14994 .addOperand(Base) 14995 .addOperand(Scale) 14996 .addOperand(Index) 14997 .addDisp(Disp, UseFPOffset ? 4 : 0) 14998 .addOperand(Segment) 14999 .addReg(NextOffsetReg) 15000 .setMemRefs(MMOBegin, MMOEnd); 15001 15002 // Jump to endMBB 15003 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 15004 .addMBB(endMBB); 15005 } 15006 15007 // 15008 // Emit code to use overflow area 15009 // 15010 15011 // Load the overflow_area address into a register. 15012 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 15013 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 15014 .addOperand(Base) 15015 .addOperand(Scale) 15016 .addOperand(Index) 15017 .addDisp(Disp, 8) 15018 .addOperand(Segment) 15019 .setMemRefs(MMOBegin, MMOEnd); 15020 15021 // If we need to align it, do so. Otherwise, just copy the address 15022 // to OverflowDestReg. 15023 if (NeedsAlign) { 15024 // Align the overflow address 15025 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 15026 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 15027 15028 // aligned_addr = (addr + (align-1)) & ~(align-1) 15029 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 15030 .addReg(OverflowAddrReg) 15031 .addImm(Align-1); 15032 15033 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 15034 .addReg(TmpReg) 15035 .addImm(~(uint64_t)(Align-1)); 15036 } else { 15037 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 15038 .addReg(OverflowAddrReg); 15039 } 15040 15041 // Compute the next overflow address after this argument. 15042 // (the overflow address should be kept 8-byte aligned) 15043 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 15044 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 15045 .addReg(OverflowDestReg) 15046 .addImm(ArgSizeA8); 15047 15048 // Store the new overflow address. 15049 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 15050 .addOperand(Base) 15051 .addOperand(Scale) 15052 .addOperand(Index) 15053 .addDisp(Disp, 8) 15054 .addOperand(Segment) 15055 .addReg(NextAddrReg) 15056 .setMemRefs(MMOBegin, MMOEnd); 15057 15058 // If we branched, emit the PHI to the front of endMBB. 15059 if (offsetMBB) { 15060 BuildMI(*endMBB, endMBB->begin(), DL, 15061 TII->get(X86::PHI), DestReg) 15062 .addReg(OffsetDestReg).addMBB(offsetMBB) 15063 .addReg(OverflowDestReg).addMBB(overflowMBB); 15064 } 15065 15066 // Erase the pseudo instruction 15067 MI->eraseFromParent(); 15068 15069 return endMBB; 15070} 15071 15072MachineBasicBlock * 15073X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 15074 MachineInstr *MI, 15075 MachineBasicBlock *MBB) const { 15076 // Emit code to save XMM registers to the stack. The ABI says that the 15077 // number of registers to save is given in %al, so it's theoretically 15078 // possible to do an indirect jump trick to avoid saving all of them, 15079 // however this code takes a simpler approach and just executes all 15080 // of the stores if %al is non-zero. It's less code, and it's probably 15081 // easier on the hardware branch predictor, and stores aren't all that 15082 // expensive anyway. 15083 15084 // Create the new basic blocks. One block contains all the XMM stores, 15085 // and one block is the final destination regardless of whether any 15086 // stores were performed. 15087 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 15088 MachineFunction *F = MBB->getParent(); 15089 MachineFunction::iterator MBBIter = MBB; 15090 ++MBBIter; 15091 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 15092 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 15093 F->insert(MBBIter, XMMSaveMBB); 15094 F->insert(MBBIter, EndMBB); 15095 15096 // Transfer the remainder of MBB and its successor edges to EndMBB. 15097 EndMBB->splice(EndMBB->begin(), MBB, 15098 llvm::next(MachineBasicBlock::iterator(MI)), 15099 MBB->end()); 15100 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 15101 15102 // The original block will now fall through to the XMM save block. 15103 MBB->addSuccessor(XMMSaveMBB); 15104 // The XMMSaveMBB will fall through to the end block. 15105 XMMSaveMBB->addSuccessor(EndMBB); 15106 15107 // Now add the instructions. 15108 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15109 DebugLoc DL = MI->getDebugLoc(); 15110 15111 unsigned CountReg = MI->getOperand(0).getReg(); 15112 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 15113 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 15114 15115 if (!Subtarget->isTargetWin64()) { 15116 // If %al is 0, branch around the XMM save block. 15117 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 15118 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 15119 MBB->addSuccessor(EndMBB); 15120 } 15121 15122 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr; 15123 // In the XMM save block, save all the XMM argument registers. 15124 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 15125 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 15126 MachineMemOperand *MMO = 15127 F->getMachineMemOperand( 15128 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 15129 MachineMemOperand::MOStore, 15130 /*Size=*/16, /*Align=*/16); 15131 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 15132 .addFrameIndex(RegSaveFrameIndex) 15133 .addImm(/*Scale=*/1) 15134 .addReg(/*IndexReg=*/0) 15135 .addImm(/*Disp=*/Offset) 15136 .addReg(/*Segment=*/0) 15137 .addReg(MI->getOperand(i).getReg()) 15138 .addMemOperand(MMO); 15139 } 15140 15141 MI->eraseFromParent(); // The pseudo instruction is gone now. 15142 15143 return EndMBB; 15144} 15145 15146// The EFLAGS operand of SelectItr might be missing a kill marker 15147// because there were multiple uses of EFLAGS, and ISel didn't know 15148// which to mark. Figure out whether SelectItr should have had a 15149// kill marker, and set it if it should. Returns the correct kill 15150// marker value. 15151static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 15152 MachineBasicBlock* BB, 15153 const TargetRegisterInfo* TRI) { 15154 // Scan forward through BB for a use/def of EFLAGS. 15155 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 15156 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 15157 const MachineInstr& mi = *miI; 15158 if (mi.readsRegister(X86::EFLAGS)) 15159 return false; 15160 if (mi.definesRegister(X86::EFLAGS)) 15161 break; // Should have kill-flag - update below. 15162 } 15163 15164 // If we hit the end of the block, check whether EFLAGS is live into a 15165 // successor. 15166 if (miI == BB->end()) { 15167 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 15168 sEnd = BB->succ_end(); 15169 sItr != sEnd; ++sItr) { 15170 MachineBasicBlock* succ = *sItr; 15171 if (succ->isLiveIn(X86::EFLAGS)) 15172 return false; 15173 } 15174 } 15175 15176 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 15177 // out. SelectMI should have a kill flag on EFLAGS. 15178 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 15179 return true; 15180} 15181 15182MachineBasicBlock * 15183X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 15184 MachineBasicBlock *BB) const { 15185 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15186 DebugLoc DL = MI->getDebugLoc(); 15187 15188 // To "insert" a SELECT_CC instruction, we actually have to insert the 15189 // diamond control-flow pattern. The incoming instruction knows the 15190 // destination vreg to set, the condition code register to branch on, the 15191 // true/false values to select between, and a branch opcode to use. 15192 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 15193 MachineFunction::iterator It = BB; 15194 ++It; 15195 15196 // thisMBB: 15197 // ... 15198 // TrueVal = ... 15199 // cmpTY ccX, r1, r2 15200 // bCC copy1MBB 15201 // fallthrough --> copy0MBB 15202 MachineBasicBlock *thisMBB = BB; 15203 MachineFunction *F = BB->getParent(); 15204 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 15205 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 15206 F->insert(It, copy0MBB); 15207 F->insert(It, sinkMBB); 15208 15209 // If the EFLAGS register isn't dead in the terminator, then claim that it's 15210 // live into the sink and copy blocks. 15211 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 15212 if (!MI->killsRegister(X86::EFLAGS) && 15213 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 15214 copy0MBB->addLiveIn(X86::EFLAGS); 15215 sinkMBB->addLiveIn(X86::EFLAGS); 15216 } 15217 15218 // Transfer the remainder of BB and its successor edges to sinkMBB. 15219 sinkMBB->splice(sinkMBB->begin(), BB, 15220 llvm::next(MachineBasicBlock::iterator(MI)), 15221 BB->end()); 15222 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 15223 15224 // Add the true and fallthrough blocks as its successors. 15225 BB->addSuccessor(copy0MBB); 15226 BB->addSuccessor(sinkMBB); 15227 15228 // Create the conditional branch instruction. 15229 unsigned Opc = 15230 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 15231 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 15232 15233 // copy0MBB: 15234 // %FalseValue = ... 15235 // # fallthrough to sinkMBB 15236 copy0MBB->addSuccessor(sinkMBB); 15237 15238 // sinkMBB: 15239 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 15240 // ... 15241 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 15242 TII->get(X86::PHI), MI->getOperand(0).getReg()) 15243 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 15244 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 15245 15246 MI->eraseFromParent(); // The pseudo instruction is gone now. 15247 return sinkMBB; 15248} 15249 15250MachineBasicBlock * 15251X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 15252 bool Is64Bit) const { 15253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15254 DebugLoc DL = MI->getDebugLoc(); 15255 MachineFunction *MF = BB->getParent(); 15256 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 15257 15258 assert(getTargetMachine().Options.EnableSegmentedStacks); 15259 15260 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 15261 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 15262 15263 // BB: 15264 // ... [Till the alloca] 15265 // If stacklet is not large enough, jump to mallocMBB 15266 // 15267 // bumpMBB: 15268 // Allocate by subtracting from RSP 15269 // Jump to continueMBB 15270 // 15271 // mallocMBB: 15272 // Allocate by call to runtime 15273 // 15274 // continueMBB: 15275 // ... 15276 // [rest of original BB] 15277 // 15278 15279 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 15280 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 15281 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 15282 15283 MachineRegisterInfo &MRI = MF->getRegInfo(); 15284 const TargetRegisterClass *AddrRegClass = 15285 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 15286 15287 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 15288 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 15289 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 15290 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 15291 sizeVReg = MI->getOperand(1).getReg(), 15292 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 15293 15294 MachineFunction::iterator MBBIter = BB; 15295 ++MBBIter; 15296 15297 MF->insert(MBBIter, bumpMBB); 15298 MF->insert(MBBIter, mallocMBB); 15299 MF->insert(MBBIter, continueMBB); 15300 15301 continueMBB->splice(continueMBB->begin(), BB, llvm::next 15302 (MachineBasicBlock::iterator(MI)), BB->end()); 15303 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 15304 15305 // Add code to the main basic block to check if the stack limit has been hit, 15306 // and if so, jump to mallocMBB otherwise to bumpMBB. 15307 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 15308 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 15309 .addReg(tmpSPVReg).addReg(sizeVReg); 15310 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 15311 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 15312 .addReg(SPLimitVReg); 15313 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 15314 15315 // bumpMBB simply decreases the stack pointer, since we know the current 15316 // stacklet has enough space. 15317 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 15318 .addReg(SPLimitVReg); 15319 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 15320 .addReg(SPLimitVReg); 15321 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 15322 15323 // Calls into a routine in libgcc to allocate more space from the heap. 15324 const uint32_t *RegMask = 15325 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 15326 if (Is64Bit) { 15327 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 15328 .addReg(sizeVReg); 15329 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 15330 .addExternalSymbol("__morestack_allocate_stack_space") 15331 .addRegMask(RegMask) 15332 .addReg(X86::RDI, RegState::Implicit) 15333 .addReg(X86::RAX, RegState::ImplicitDefine); 15334 } else { 15335 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 15336 .addImm(12); 15337 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 15338 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 15339 .addExternalSymbol("__morestack_allocate_stack_space") 15340 .addRegMask(RegMask) 15341 .addReg(X86::EAX, RegState::ImplicitDefine); 15342 } 15343 15344 if (!Is64Bit) 15345 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 15346 .addImm(16); 15347 15348 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 15349 .addReg(Is64Bit ? X86::RAX : X86::EAX); 15350 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 15351 15352 // Set up the CFG correctly. 15353 BB->addSuccessor(bumpMBB); 15354 BB->addSuccessor(mallocMBB); 15355 mallocMBB->addSuccessor(continueMBB); 15356 bumpMBB->addSuccessor(continueMBB); 15357 15358 // Take care of the PHI nodes. 15359 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 15360 MI->getOperand(0).getReg()) 15361 .addReg(mallocPtrVReg).addMBB(mallocMBB) 15362 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 15363 15364 // Delete the original pseudo instruction. 15365 MI->eraseFromParent(); 15366 15367 // And we're done. 15368 return continueMBB; 15369} 15370 15371MachineBasicBlock * 15372X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 15373 MachineBasicBlock *BB) const { 15374 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15375 DebugLoc DL = MI->getDebugLoc(); 15376 15377 assert(!Subtarget->isTargetEnvMacho()); 15378 15379 // The lowering is pretty easy: we're just emitting the call to _alloca. The 15380 // non-trivial part is impdef of ESP. 15381 15382 if (Subtarget->isTargetWin64()) { 15383 if (Subtarget->isTargetCygMing()) { 15384 // ___chkstk(Mingw64): 15385 // Clobbers R10, R11, RAX and EFLAGS. 15386 // Updates RSP. 15387 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 15388 .addExternalSymbol("___chkstk") 15389 .addReg(X86::RAX, RegState::Implicit) 15390 .addReg(X86::RSP, RegState::Implicit) 15391 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 15392 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 15393 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 15394 } else { 15395 // __chkstk(MSVCRT): does not update stack pointer. 15396 // Clobbers R10, R11 and EFLAGS. 15397 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 15398 .addExternalSymbol("__chkstk") 15399 .addReg(X86::RAX, RegState::Implicit) 15400 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 15401 // RAX has the offset to be subtracted from RSP. 15402 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 15403 .addReg(X86::RSP) 15404 .addReg(X86::RAX); 15405 } 15406 } else { 15407 const char *StackProbeSymbol = 15408 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 15409 15410 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 15411 .addExternalSymbol(StackProbeSymbol) 15412 .addReg(X86::EAX, RegState::Implicit) 15413 .addReg(X86::ESP, RegState::Implicit) 15414 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 15415 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 15416 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 15417 } 15418 15419 MI->eraseFromParent(); // The pseudo instruction is gone now. 15420 return BB; 15421} 15422 15423MachineBasicBlock * 15424X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 15425 MachineBasicBlock *BB) const { 15426 // This is pretty easy. We're taking the value that we received from 15427 // our load from the relocation, sticking it in either RDI (x86-64) 15428 // or EAX and doing an indirect call. The return value will then 15429 // be in the normal return register. 15430 const X86InstrInfo *TII 15431 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 15432 DebugLoc DL = MI->getDebugLoc(); 15433 MachineFunction *F = BB->getParent(); 15434 15435 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 15436 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 15437 15438 // Get a register mask for the lowered call. 15439 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 15440 // proper register mask. 15441 const uint32_t *RegMask = 15442 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 15443 if (Subtarget->is64Bit()) { 15444 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 15445 TII->get(X86::MOV64rm), X86::RDI) 15446 .addReg(X86::RIP) 15447 .addImm(0).addReg(0) 15448 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 15449 MI->getOperand(3).getTargetFlags()) 15450 .addReg(0); 15451 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 15452 addDirectMem(MIB, X86::RDI); 15453 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 15454 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 15455 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 15456 TII->get(X86::MOV32rm), X86::EAX) 15457 .addReg(0) 15458 .addImm(0).addReg(0) 15459 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 15460 MI->getOperand(3).getTargetFlags()) 15461 .addReg(0); 15462 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 15463 addDirectMem(MIB, X86::EAX); 15464 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 15465 } else { 15466 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 15467 TII->get(X86::MOV32rm), X86::EAX) 15468 .addReg(TII->getGlobalBaseReg(F)) 15469 .addImm(0).addReg(0) 15470 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 15471 MI->getOperand(3).getTargetFlags()) 15472 .addReg(0); 15473 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 15474 addDirectMem(MIB, X86::EAX); 15475 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 15476 } 15477 15478 MI->eraseFromParent(); // The pseudo instruction is gone now. 15479 return BB; 15480} 15481 15482MachineBasicBlock * 15483X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, 15484 MachineBasicBlock *MBB) const { 15485 DebugLoc DL = MI->getDebugLoc(); 15486 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15487 15488 MachineFunction *MF = MBB->getParent(); 15489 MachineRegisterInfo &MRI = MF->getRegInfo(); 15490 15491 const BasicBlock *BB = MBB->getBasicBlock(); 15492 MachineFunction::iterator I = MBB; 15493 ++I; 15494 15495 // Memory Reference 15496 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 15497 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 15498 15499 unsigned DstReg; 15500 unsigned MemOpndSlot = 0; 15501 15502 unsigned CurOp = 0; 15503 15504 DstReg = MI->getOperand(CurOp++).getReg(); 15505 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 15506 assert(RC->hasType(MVT::i32) && "Invalid destination!"); 15507 unsigned mainDstReg = MRI.createVirtualRegister(RC); 15508 unsigned restoreDstReg = MRI.createVirtualRegister(RC); 15509 15510 MemOpndSlot = CurOp; 15511 15512 MVT PVT = getPointerTy(); 15513 assert((PVT == MVT::i64 || PVT == MVT::i32) && 15514 "Invalid Pointer Size!"); 15515 15516 // For v = setjmp(buf), we generate 15517 // 15518 // thisMBB: 15519 // buf[LabelOffset] = restoreMBB 15520 // SjLjSetup restoreMBB 15521 // 15522 // mainMBB: 15523 // v_main = 0 15524 // 15525 // sinkMBB: 15526 // v = phi(main, restore) 15527 // 15528 // restoreMBB: 15529 // v_restore = 1 15530 15531 MachineBasicBlock *thisMBB = MBB; 15532 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 15533 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 15534 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB); 15535 MF->insert(I, mainMBB); 15536 MF->insert(I, sinkMBB); 15537 MF->push_back(restoreMBB); 15538 15539 MachineInstrBuilder MIB; 15540 15541 // Transfer the remainder of BB and its successor edges to sinkMBB. 15542 sinkMBB->splice(sinkMBB->begin(), MBB, 15543 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 15544 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 15545 15546 // thisMBB: 15547 unsigned PtrStoreOpc = 0; 15548 unsigned LabelReg = 0; 15549 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 15550 Reloc::Model RM = getTargetMachine().getRelocationModel(); 15551 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) && 15552 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC); 15553 15554 // Prepare IP either in reg or imm. 15555 if (!UseImmLabel) { 15556 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr; 15557 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); 15558 LabelReg = MRI.createVirtualRegister(PtrRC); 15559 if (Subtarget->is64Bit()) { 15560 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg) 15561 .addReg(X86::RIP) 15562 .addImm(0) 15563 .addReg(0) 15564 .addMBB(restoreMBB) 15565 .addReg(0); 15566 } else { 15567 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII); 15568 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg) 15569 .addReg(XII->getGlobalBaseReg(MF)) 15570 .addImm(0) 15571 .addReg(0) 15572 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference()) 15573 .addReg(0); 15574 } 15575 } else 15576 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi; 15577 // Store IP 15578 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc)); 15579 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 15580 if (i == X86::AddrDisp) 15581 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset); 15582 else 15583 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 15584 } 15585 if (!UseImmLabel) 15586 MIB.addReg(LabelReg); 15587 else 15588 MIB.addMBB(restoreMBB); 15589 MIB.setMemRefs(MMOBegin, MMOEnd); 15590 // Setup 15591 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup)) 15592 .addMBB(restoreMBB); 15593 15594 const X86RegisterInfo *RegInfo = 15595 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 15596 MIB.addRegMask(RegInfo->getNoPreservedMask()); 15597 thisMBB->addSuccessor(mainMBB); 15598 thisMBB->addSuccessor(restoreMBB); 15599 15600 // mainMBB: 15601 // EAX = 0 15602 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg); 15603 mainMBB->addSuccessor(sinkMBB); 15604 15605 // sinkMBB: 15606 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 15607 TII->get(X86::PHI), DstReg) 15608 .addReg(mainDstReg).addMBB(mainMBB) 15609 .addReg(restoreDstReg).addMBB(restoreMBB); 15610 15611 // restoreMBB: 15612 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1); 15613 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB); 15614 restoreMBB->addSuccessor(sinkMBB); 15615 15616 MI->eraseFromParent(); 15617 return sinkMBB; 15618} 15619 15620MachineBasicBlock * 15621X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, 15622 MachineBasicBlock *MBB) const { 15623 DebugLoc DL = MI->getDebugLoc(); 15624 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15625 15626 MachineFunction *MF = MBB->getParent(); 15627 MachineRegisterInfo &MRI = MF->getRegInfo(); 15628 15629 // Memory Reference 15630 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 15631 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 15632 15633 MVT PVT = getPointerTy(); 15634 assert((PVT == MVT::i64 || PVT == MVT::i32) && 15635 "Invalid Pointer Size!"); 15636 15637 const TargetRegisterClass *RC = 15638 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass; 15639 unsigned Tmp = MRI.createVirtualRegister(RC); 15640 // Since FP is only updated here but NOT referenced, it's treated as GPR. 15641 const X86RegisterInfo *RegInfo = 15642 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); 15643 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; 15644 unsigned SP = RegInfo->getStackRegister(); 15645 15646 MachineInstrBuilder MIB; 15647 15648 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 15649 const int64_t SPOffset = 2 * PVT.getStoreSize(); 15650 15651 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm; 15652 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r; 15653 15654 // Reload FP 15655 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP); 15656 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 15657 MIB.addOperand(MI->getOperand(i)); 15658 MIB.setMemRefs(MMOBegin, MMOEnd); 15659 // Reload IP 15660 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp); 15661 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 15662 if (i == X86::AddrDisp) 15663 MIB.addDisp(MI->getOperand(i), LabelOffset); 15664 else 15665 MIB.addOperand(MI->getOperand(i)); 15666 } 15667 MIB.setMemRefs(MMOBegin, MMOEnd); 15668 // Reload SP 15669 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP); 15670 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 15671 if (i == X86::AddrDisp) 15672 MIB.addDisp(MI->getOperand(i), SPOffset); 15673 else 15674 MIB.addOperand(MI->getOperand(i)); 15675 } 15676 MIB.setMemRefs(MMOBegin, MMOEnd); 15677 // Jump 15678 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp); 15679 15680 MI->eraseFromParent(); 15681 return MBB; 15682} 15683 15684MachineBasicBlock * 15685X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 15686 MachineBasicBlock *BB) const { 15687 switch (MI->getOpcode()) { 15688 default: llvm_unreachable("Unexpected instr type to insert"); 15689 case X86::TAILJMPd64: 15690 case X86::TAILJMPr64: 15691 case X86::TAILJMPm64: 15692 llvm_unreachable("TAILJMP64 would not be touched here."); 15693 case X86::TCRETURNdi64: 15694 case X86::TCRETURNri64: 15695 case X86::TCRETURNmi64: 15696 return BB; 15697 case X86::WIN_ALLOCA: 15698 return EmitLoweredWinAlloca(MI, BB); 15699 case X86::SEG_ALLOCA_32: 15700 return EmitLoweredSegAlloca(MI, BB, false); 15701 case X86::SEG_ALLOCA_64: 15702 return EmitLoweredSegAlloca(MI, BB, true); 15703 case X86::TLSCall_32: 15704 case X86::TLSCall_64: 15705 return EmitLoweredTLSCall(MI, BB); 15706 case X86::CMOV_GR8: 15707 case X86::CMOV_FR32: 15708 case X86::CMOV_FR64: 15709 case X86::CMOV_V4F32: 15710 case X86::CMOV_V2F64: 15711 case X86::CMOV_V2I64: 15712 case X86::CMOV_V8F32: 15713 case X86::CMOV_V4F64: 15714 case X86::CMOV_V4I64: 15715 case X86::CMOV_GR16: 15716 case X86::CMOV_GR32: 15717 case X86::CMOV_RFP32: 15718 case X86::CMOV_RFP64: 15719 case X86::CMOV_RFP80: 15720 return EmitLoweredSelect(MI, BB); 15721 15722 case X86::FP32_TO_INT16_IN_MEM: 15723 case X86::FP32_TO_INT32_IN_MEM: 15724 case X86::FP32_TO_INT64_IN_MEM: 15725 case X86::FP64_TO_INT16_IN_MEM: 15726 case X86::FP64_TO_INT32_IN_MEM: 15727 case X86::FP64_TO_INT64_IN_MEM: 15728 case X86::FP80_TO_INT16_IN_MEM: 15729 case X86::FP80_TO_INT32_IN_MEM: 15730 case X86::FP80_TO_INT64_IN_MEM: { 15731 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 15732 DebugLoc DL = MI->getDebugLoc(); 15733 15734 // Change the floating point control register to use "round towards zero" 15735 // mode when truncating to an integer value. 15736 MachineFunction *F = BB->getParent(); 15737 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 15738 addFrameReference(BuildMI(*BB, MI, DL, 15739 TII->get(X86::FNSTCW16m)), CWFrameIdx); 15740 15741 // Load the old value of the high byte of the control word... 15742 unsigned OldCW = 15743 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 15744 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 15745 CWFrameIdx); 15746 15747 // Set the high part to be round to zero... 15748 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 15749 .addImm(0xC7F); 15750 15751 // Reload the modified control word now... 15752 addFrameReference(BuildMI(*BB, MI, DL, 15753 TII->get(X86::FLDCW16m)), CWFrameIdx); 15754 15755 // Restore the memory image of control word to original value 15756 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 15757 .addReg(OldCW); 15758 15759 // Get the X86 opcode to use. 15760 unsigned Opc; 15761 switch (MI->getOpcode()) { 15762 default: llvm_unreachable("illegal opcode!"); 15763 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 15764 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 15765 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 15766 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 15767 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 15768 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 15769 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 15770 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 15771 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 15772 } 15773 15774 X86AddressMode AM; 15775 MachineOperand &Op = MI->getOperand(0); 15776 if (Op.isReg()) { 15777 AM.BaseType = X86AddressMode::RegBase; 15778 AM.Base.Reg = Op.getReg(); 15779 } else { 15780 AM.BaseType = X86AddressMode::FrameIndexBase; 15781 AM.Base.FrameIndex = Op.getIndex(); 15782 } 15783 Op = MI->getOperand(1); 15784 if (Op.isImm()) 15785 AM.Scale = Op.getImm(); 15786 Op = MI->getOperand(2); 15787 if (Op.isImm()) 15788 AM.IndexReg = Op.getImm(); 15789 Op = MI->getOperand(3); 15790 if (Op.isGlobal()) { 15791 AM.GV = Op.getGlobal(); 15792 } else { 15793 AM.Disp = Op.getImm(); 15794 } 15795 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 15796 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 15797 15798 // Reload the original control word now. 15799 addFrameReference(BuildMI(*BB, MI, DL, 15800 TII->get(X86::FLDCW16m)), CWFrameIdx); 15801 15802 MI->eraseFromParent(); // The pseudo instruction is gone now. 15803 return BB; 15804 } 15805 // String/text processing lowering. 15806 case X86::PCMPISTRM128REG: 15807 case X86::VPCMPISTRM128REG: 15808 case X86::PCMPISTRM128MEM: 15809 case X86::VPCMPISTRM128MEM: 15810 case X86::PCMPESTRM128REG: 15811 case X86::VPCMPESTRM128REG: 15812 case X86::PCMPESTRM128MEM: 15813 case X86::VPCMPESTRM128MEM: 15814 assert(Subtarget->hasSSE42() && 15815 "Target must have SSE4.2 or AVX features enabled"); 15816 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo()); 15817 15818 // String/text processing lowering. 15819 case X86::PCMPISTRIREG: 15820 case X86::VPCMPISTRIREG: 15821 case X86::PCMPISTRIMEM: 15822 case X86::VPCMPISTRIMEM: 15823 case X86::PCMPESTRIREG: 15824 case X86::VPCMPESTRIREG: 15825 case X86::PCMPESTRIMEM: 15826 case X86::VPCMPESTRIMEM: 15827 assert(Subtarget->hasSSE42() && 15828 "Target must have SSE4.2 or AVX features enabled"); 15829 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo()); 15830 15831 // Thread synchronization. 15832 case X86::MONITOR: 15833 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget); 15834 15835 // xbegin 15836 case X86::XBEGIN: 15837 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo()); 15838 15839 // Atomic Lowering. 15840 case X86::ATOMAND8: 15841 case X86::ATOMAND16: 15842 case X86::ATOMAND32: 15843 case X86::ATOMAND64: 15844 // Fall through 15845 case X86::ATOMOR8: 15846 case X86::ATOMOR16: 15847 case X86::ATOMOR32: 15848 case X86::ATOMOR64: 15849 // Fall through 15850 case X86::ATOMXOR16: 15851 case X86::ATOMXOR8: 15852 case X86::ATOMXOR32: 15853 case X86::ATOMXOR64: 15854 // Fall through 15855 case X86::ATOMNAND8: 15856 case X86::ATOMNAND16: 15857 case X86::ATOMNAND32: 15858 case X86::ATOMNAND64: 15859 // Fall through 15860 case X86::ATOMMAX8: 15861 case X86::ATOMMAX16: 15862 case X86::ATOMMAX32: 15863 case X86::ATOMMAX64: 15864 // Fall through 15865 case X86::ATOMMIN8: 15866 case X86::ATOMMIN16: 15867 case X86::ATOMMIN32: 15868 case X86::ATOMMIN64: 15869 // Fall through 15870 case X86::ATOMUMAX8: 15871 case X86::ATOMUMAX16: 15872 case X86::ATOMUMAX32: 15873 case X86::ATOMUMAX64: 15874 // Fall through 15875 case X86::ATOMUMIN8: 15876 case X86::ATOMUMIN16: 15877 case X86::ATOMUMIN32: 15878 case X86::ATOMUMIN64: 15879 return EmitAtomicLoadArith(MI, BB); 15880 15881 // This group does 64-bit operations on a 32-bit host. 15882 case X86::ATOMAND6432: 15883 case X86::ATOMOR6432: 15884 case X86::ATOMXOR6432: 15885 case X86::ATOMNAND6432: 15886 case X86::ATOMADD6432: 15887 case X86::ATOMSUB6432: 15888 case X86::ATOMMAX6432: 15889 case X86::ATOMMIN6432: 15890 case X86::ATOMUMAX6432: 15891 case X86::ATOMUMIN6432: 15892 case X86::ATOMSWAP6432: 15893 return EmitAtomicLoadArith6432(MI, BB); 15894 15895 case X86::VASTART_SAVE_XMM_REGS: 15896 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 15897 15898 case X86::VAARG_64: 15899 return EmitVAARG64WithCustomInserter(MI, BB); 15900 15901 case X86::EH_SjLj_SetJmp32: 15902 case X86::EH_SjLj_SetJmp64: 15903 return emitEHSjLjSetJmp(MI, BB); 15904 15905 case X86::EH_SjLj_LongJmp32: 15906 case X86::EH_SjLj_LongJmp64: 15907 return emitEHSjLjLongJmp(MI, BB); 15908 } 15909} 15910 15911//===----------------------------------------------------------------------===// 15912// X86 Optimization Hooks 15913//===----------------------------------------------------------------------===// 15914 15915void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 15916 APInt &KnownZero, 15917 APInt &KnownOne, 15918 const SelectionDAG &DAG, 15919 unsigned Depth) const { 15920 unsigned BitWidth = KnownZero.getBitWidth(); 15921 unsigned Opc = Op.getOpcode(); 15922 assert((Opc >= ISD::BUILTIN_OP_END || 15923 Opc == ISD::INTRINSIC_WO_CHAIN || 15924 Opc == ISD::INTRINSIC_W_CHAIN || 15925 Opc == ISD::INTRINSIC_VOID) && 15926 "Should use MaskedValueIsZero if you don't know whether Op" 15927 " is a target node!"); 15928 15929 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 15930 switch (Opc) { 15931 default: break; 15932 case X86ISD::ADD: 15933 case X86ISD::SUB: 15934 case X86ISD::ADC: 15935 case X86ISD::SBB: 15936 case X86ISD::SMUL: 15937 case X86ISD::UMUL: 15938 case X86ISD::INC: 15939 case X86ISD::DEC: 15940 case X86ISD::OR: 15941 case X86ISD::XOR: 15942 case X86ISD::AND: 15943 // These nodes' second result is a boolean. 15944 if (Op.getResNo() == 0) 15945 break; 15946 // Fallthrough 15947 case X86ISD::SETCC: 15948 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 15949 break; 15950 case ISD::INTRINSIC_WO_CHAIN: { 15951 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 15952 unsigned NumLoBits = 0; 15953 switch (IntId) { 15954 default: break; 15955 case Intrinsic::x86_sse_movmsk_ps: 15956 case Intrinsic::x86_avx_movmsk_ps_256: 15957 case Intrinsic::x86_sse2_movmsk_pd: 15958 case Intrinsic::x86_avx_movmsk_pd_256: 15959 case Intrinsic::x86_mmx_pmovmskb: 15960 case Intrinsic::x86_sse2_pmovmskb_128: 15961 case Intrinsic::x86_avx2_pmovmskb: { 15962 // High bits of movmskp{s|d}, pmovmskb are known zero. 15963 switch (IntId) { 15964 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 15965 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 15966 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 15967 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 15968 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 15969 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 15970 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 15971 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 15972 } 15973 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 15974 break; 15975 } 15976 } 15977 break; 15978 } 15979 } 15980} 15981 15982unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 15983 unsigned Depth) const { 15984 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 15985 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 15986 return Op.getValueType().getScalarType().getSizeInBits(); 15987 15988 // Fallback case. 15989 return 1; 15990} 15991 15992/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 15993/// node is a GlobalAddress + offset. 15994bool X86TargetLowering::isGAPlusOffset(SDNode *N, 15995 const GlobalValue* &GA, 15996 int64_t &Offset) const { 15997 if (N->getOpcode() == X86ISD::Wrapper) { 15998 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 15999 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 16000 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 16001 return true; 16002 } 16003 } 16004 return TargetLowering::isGAPlusOffset(N, GA, Offset); 16005} 16006 16007/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 16008/// same as extracting the high 128-bit part of 256-bit vector and then 16009/// inserting the result into the low part of a new 256-bit vector 16010static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 16011 EVT VT = SVOp->getValueType(0); 16012 unsigned NumElems = VT.getVectorNumElements(); 16013 16014 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 16015 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 16016 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 16017 SVOp->getMaskElt(j) >= 0) 16018 return false; 16019 16020 return true; 16021} 16022 16023/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 16024/// same as extracting the low 128-bit part of 256-bit vector and then 16025/// inserting the result into the high part of a new 256-bit vector 16026static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 16027 EVT VT = SVOp->getValueType(0); 16028 unsigned NumElems = VT.getVectorNumElements(); 16029 16030 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 16031 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 16032 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 16033 SVOp->getMaskElt(j) >= 0) 16034 return false; 16035 16036 return true; 16037} 16038 16039/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 16040static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 16041 TargetLowering::DAGCombinerInfo &DCI, 16042 const X86Subtarget* Subtarget) { 16043 SDLoc dl(N); 16044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 16045 SDValue V1 = SVOp->getOperand(0); 16046 SDValue V2 = SVOp->getOperand(1); 16047 EVT VT = SVOp->getValueType(0); 16048 unsigned NumElems = VT.getVectorNumElements(); 16049 16050 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 16051 V2.getOpcode() == ISD::CONCAT_VECTORS) { 16052 // 16053 // 0,0,0,... 16054 // | 16055 // V UNDEF BUILD_VECTOR UNDEF 16056 // \ / \ / 16057 // CONCAT_VECTOR CONCAT_VECTOR 16058 // \ / 16059 // \ / 16060 // RESULT: V + zero extended 16061 // 16062 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 16063 V2.getOperand(1).getOpcode() != ISD::UNDEF || 16064 V1.getOperand(1).getOpcode() != ISD::UNDEF) 16065 return SDValue(); 16066 16067 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 16068 return SDValue(); 16069 16070 // To match the shuffle mask, the first half of the mask should 16071 // be exactly the first vector, and all the rest a splat with the 16072 // first element of the second one. 16073 for (unsigned i = 0; i != NumElems/2; ++i) 16074 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 16075 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 16076 return SDValue(); 16077 16078 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 16079 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 16080 if (Ld->hasNUsesOfValue(1, 0)) { 16081 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 16082 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 16083 SDValue ResNode = 16084 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 16085 array_lengthof(Ops), 16086 Ld->getMemoryVT(), 16087 Ld->getPointerInfo(), 16088 Ld->getAlignment(), 16089 false/*isVolatile*/, true/*ReadMem*/, 16090 false/*WriteMem*/); 16091 16092 // Make sure the newly-created LOAD is in the same position as Ld in 16093 // terms of dependency. We create a TokenFactor for Ld and ResNode, 16094 // and update uses of Ld's output chain to use the TokenFactor. 16095 if (Ld->hasAnyUseOfValue(1)) { 16096 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 16097 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1)); 16098 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain); 16099 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1), 16100 SDValue(ResNode.getNode(), 1)); 16101 } 16102 16103 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 16104 } 16105 } 16106 16107 // Emit a zeroed vector and insert the desired subvector on its 16108 // first half. 16109 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 16110 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 16111 return DCI.CombineTo(N, InsV); 16112 } 16113 16114 //===--------------------------------------------------------------------===// 16115 // Combine some shuffles into subvector extracts and inserts: 16116 // 16117 16118 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 16119 if (isShuffleHigh128VectorInsertLow(SVOp)) { 16120 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 16121 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 16122 return DCI.CombineTo(N, InsV); 16123 } 16124 16125 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 16126 if (isShuffleLow128VectorInsertHigh(SVOp)) { 16127 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 16128 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 16129 return DCI.CombineTo(N, InsV); 16130 } 16131 16132 return SDValue(); 16133} 16134 16135/// PerformShuffleCombine - Performs several different shuffle combines. 16136static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 16137 TargetLowering::DAGCombinerInfo &DCI, 16138 const X86Subtarget *Subtarget) { 16139 SDLoc dl(N); 16140 EVT VT = N->getValueType(0); 16141 16142 // Don't create instructions with illegal types after legalize types has run. 16143 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16144 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 16145 return SDValue(); 16146 16147 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 16148 if (Subtarget->hasFp256() && VT.is256BitVector() && 16149 N->getOpcode() == ISD::VECTOR_SHUFFLE) 16150 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 16151 16152 // Only handle 128 wide vector from here on. 16153 if (!VT.is128BitVector()) 16154 return SDValue(); 16155 16156 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 16157 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 16158 // consecutive, non-overlapping, and in the right order. 16159 SmallVector<SDValue, 16> Elts; 16160 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 16161 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 16162 16163 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 16164} 16165 16166/// PerformTruncateCombine - Converts truncate operation to 16167/// a sequence of vector shuffle operations. 16168/// It is possible when we truncate 256-bit vector to 128-bit vector 16169static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 16170 TargetLowering::DAGCombinerInfo &DCI, 16171 const X86Subtarget *Subtarget) { 16172 return SDValue(); 16173} 16174 16175/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 16176/// specific shuffle of a load can be folded into a single element load. 16177/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 16178/// shuffles have been customed lowered so we need to handle those here. 16179static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 16180 TargetLowering::DAGCombinerInfo &DCI) { 16181 if (DCI.isBeforeLegalizeOps()) 16182 return SDValue(); 16183 16184 SDValue InVec = N->getOperand(0); 16185 SDValue EltNo = N->getOperand(1); 16186 16187 if (!isa<ConstantSDNode>(EltNo)) 16188 return SDValue(); 16189 16190 EVT VT = InVec.getValueType(); 16191 16192 bool HasShuffleIntoBitcast = false; 16193 if (InVec.getOpcode() == ISD::BITCAST) { 16194 // Don't duplicate a load with other uses. 16195 if (!InVec.hasOneUse()) 16196 return SDValue(); 16197 EVT BCVT = InVec.getOperand(0).getValueType(); 16198 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 16199 return SDValue(); 16200 InVec = InVec.getOperand(0); 16201 HasShuffleIntoBitcast = true; 16202 } 16203 16204 if (!isTargetShuffle(InVec.getOpcode())) 16205 return SDValue(); 16206 16207 // Don't duplicate a load with other uses. 16208 if (!InVec.hasOneUse()) 16209 return SDValue(); 16210 16211 SmallVector<int, 16> ShuffleMask; 16212 bool UnaryShuffle; 16213 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 16214 UnaryShuffle)) 16215 return SDValue(); 16216 16217 // Select the input vector, guarding against out of range extract vector. 16218 unsigned NumElems = VT.getVectorNumElements(); 16219 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 16220 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 16221 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 16222 : InVec.getOperand(1); 16223 16224 // If inputs to shuffle are the same for both ops, then allow 2 uses 16225 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 16226 16227 if (LdNode.getOpcode() == ISD::BITCAST) { 16228 // Don't duplicate a load with other uses. 16229 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 16230 return SDValue(); 16231 16232 AllowedUses = 1; // only allow 1 load use if we have a bitcast 16233 LdNode = LdNode.getOperand(0); 16234 } 16235 16236 if (!ISD::isNormalLoad(LdNode.getNode())) 16237 return SDValue(); 16238 16239 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 16240 16241 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 16242 return SDValue(); 16243 16244 if (HasShuffleIntoBitcast) { 16245 // If there's a bitcast before the shuffle, check if the load type and 16246 // alignment is valid. 16247 unsigned Align = LN0->getAlignment(); 16248 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16249 unsigned NewAlign = TLI.getDataLayout()-> 16250 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 16251 16252 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 16253 return SDValue(); 16254 } 16255 16256 // All checks match so transform back to vector_shuffle so that DAG combiner 16257 // can finish the job 16258 SDLoc dl(N); 16259 16260 // Create shuffle node taking into account the case that its a unary shuffle 16261 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 16262 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 16263 InVec.getOperand(0), Shuffle, 16264 &ShuffleMask[0]); 16265 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 16266 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 16267 EltNo); 16268} 16269 16270/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 16271/// generation and convert it from being a bunch of shuffles and extracts 16272/// to a simple store and scalar loads to extract the elements. 16273static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 16274 TargetLowering::DAGCombinerInfo &DCI) { 16275 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 16276 if (NewOp.getNode()) 16277 return NewOp; 16278 16279 SDValue InputVector = N->getOperand(0); 16280 // Detect whether we are trying to convert from mmx to i32 and the bitcast 16281 // from mmx to v2i32 has a single usage. 16282 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST && 16283 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx && 16284 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32) 16285 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector), 16286 N->getValueType(0), 16287 InputVector.getNode()->getOperand(0)); 16288 16289 // Only operate on vectors of 4 elements, where the alternative shuffling 16290 // gets to be more expensive. 16291 if (InputVector.getValueType() != MVT::v4i32) 16292 return SDValue(); 16293 16294 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 16295 // single use which is a sign-extend or zero-extend, and all elements are 16296 // used. 16297 SmallVector<SDNode *, 4> Uses; 16298 unsigned ExtractedElements = 0; 16299 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 16300 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 16301 if (UI.getUse().getResNo() != InputVector.getResNo()) 16302 return SDValue(); 16303 16304 SDNode *Extract = *UI; 16305 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 16306 return SDValue(); 16307 16308 if (Extract->getValueType(0) != MVT::i32) 16309 return SDValue(); 16310 if (!Extract->hasOneUse()) 16311 return SDValue(); 16312 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 16313 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 16314 return SDValue(); 16315 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 16316 return SDValue(); 16317 16318 // Record which element was extracted. 16319 ExtractedElements |= 16320 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 16321 16322 Uses.push_back(Extract); 16323 } 16324 16325 // If not all the elements were used, this may not be worthwhile. 16326 if (ExtractedElements != 15) 16327 return SDValue(); 16328 16329 // Ok, we've now decided to do the transformation. 16330 SDLoc dl(InputVector); 16331 16332 // Store the value to a temporary stack slot. 16333 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 16334 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 16335 MachinePointerInfo(), false, false, 0); 16336 16337 // Replace each use (extract) with a load of the appropriate element. 16338 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 16339 UE = Uses.end(); UI != UE; ++UI) { 16340 SDNode *Extract = *UI; 16341 16342 // cOMpute the element's address. 16343 SDValue Idx = Extract->getOperand(1); 16344 unsigned EltSize = 16345 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 16346 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 16347 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16348 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 16349 16350 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 16351 StackPtr, OffsetVal); 16352 16353 // Load the scalar. 16354 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 16355 ScalarAddr, MachinePointerInfo(), 16356 false, false, false, 0); 16357 16358 // Replace the exact with the load. 16359 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 16360 } 16361 16362 // The replacement was made in place; don't return anything. 16363 return SDValue(); 16364} 16365 16366/// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match. 16367static std::pair<unsigned, bool> 16368matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS, 16369 SelectionDAG &DAG, const X86Subtarget *Subtarget) { 16370 if (!VT.isVector()) 16371 return std::make_pair(0, false); 16372 16373 bool NeedSplit = false; 16374 switch (VT.getSimpleVT().SimpleTy) { 16375 default: return std::make_pair(0, false); 16376 case MVT::v32i8: 16377 case MVT::v16i16: 16378 case MVT::v8i32: 16379 if (!Subtarget->hasAVX2()) 16380 NeedSplit = true; 16381 if (!Subtarget->hasAVX()) 16382 return std::make_pair(0, false); 16383 break; 16384 case MVT::v16i8: 16385 case MVT::v8i16: 16386 case MVT::v4i32: 16387 if (!Subtarget->hasSSE2()) 16388 return std::make_pair(0, false); 16389 } 16390 16391 // SSE2 has only a small subset of the operations. 16392 bool hasUnsigned = Subtarget->hasSSE41() || 16393 (Subtarget->hasSSE2() && VT == MVT::v16i8); 16394 bool hasSigned = Subtarget->hasSSE41() || 16395 (Subtarget->hasSSE2() && VT == MVT::v8i16); 16396 16397 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 16398 16399 unsigned Opc = 0; 16400 // Check for x CC y ? x : y. 16401 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 16402 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 16403 switch (CC) { 16404 default: break; 16405 case ISD::SETULT: 16406 case ISD::SETULE: 16407 Opc = hasUnsigned ? X86ISD::UMIN : 0; break; 16408 case ISD::SETUGT: 16409 case ISD::SETUGE: 16410 Opc = hasUnsigned ? X86ISD::UMAX : 0; break; 16411 case ISD::SETLT: 16412 case ISD::SETLE: 16413 Opc = hasSigned ? X86ISD::SMIN : 0; break; 16414 case ISD::SETGT: 16415 case ISD::SETGE: 16416 Opc = hasSigned ? X86ISD::SMAX : 0; break; 16417 } 16418 // Check for x CC y ? y : x -- a min/max with reversed arms. 16419 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 16420 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 16421 switch (CC) { 16422 default: break; 16423 case ISD::SETULT: 16424 case ISD::SETULE: 16425 Opc = hasUnsigned ? X86ISD::UMAX : 0; break; 16426 case ISD::SETUGT: 16427 case ISD::SETUGE: 16428 Opc = hasUnsigned ? X86ISD::UMIN : 0; break; 16429 case ISD::SETLT: 16430 case ISD::SETLE: 16431 Opc = hasSigned ? X86ISD::SMAX : 0; break; 16432 case ISD::SETGT: 16433 case ISD::SETGE: 16434 Opc = hasSigned ? X86ISD::SMIN : 0; break; 16435 } 16436 } 16437 16438 return std::make_pair(Opc, NeedSplit); 16439} 16440 16441/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 16442/// nodes. 16443static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 16444 TargetLowering::DAGCombinerInfo &DCI, 16445 const X86Subtarget *Subtarget) { 16446 SDLoc DL(N); 16447 SDValue Cond = N->getOperand(0); 16448 // Get the LHS/RHS of the select. 16449 SDValue LHS = N->getOperand(1); 16450 SDValue RHS = N->getOperand(2); 16451 EVT VT = LHS.getValueType(); 16452 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16453 16454 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 16455 // instructions match the semantics of the common C idiom x<y?x:y but not 16456 // x<=y?x:y, because of how they handle negative zero (which can be 16457 // ignored in unsafe-math mode). 16458 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 16459 VT != MVT::f80 && TLI.isTypeLegal(VT) && 16460 (Subtarget->hasSSE2() || 16461 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 16462 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 16463 16464 unsigned Opcode = 0; 16465 // Check for x CC y ? x : y. 16466 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 16467 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 16468 switch (CC) { 16469 default: break; 16470 case ISD::SETULT: 16471 // Converting this to a min would handle NaNs incorrectly, and swapping 16472 // the operands would cause it to handle comparisons between positive 16473 // and negative zero incorrectly. 16474 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 16475 if (!DAG.getTarget().Options.UnsafeFPMath && 16476 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 16477 break; 16478 std::swap(LHS, RHS); 16479 } 16480 Opcode = X86ISD::FMIN; 16481 break; 16482 case ISD::SETOLE: 16483 // Converting this to a min would handle comparisons between positive 16484 // and negative zero incorrectly. 16485 if (!DAG.getTarget().Options.UnsafeFPMath && 16486 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 16487 break; 16488 Opcode = X86ISD::FMIN; 16489 break; 16490 case ISD::SETULE: 16491 // Converting this to a min would handle both negative zeros and NaNs 16492 // incorrectly, but we can swap the operands to fix both. 16493 std::swap(LHS, RHS); 16494 case ISD::SETOLT: 16495 case ISD::SETLT: 16496 case ISD::SETLE: 16497 Opcode = X86ISD::FMIN; 16498 break; 16499 16500 case ISD::SETOGE: 16501 // Converting this to a max would handle comparisons between positive 16502 // and negative zero incorrectly. 16503 if (!DAG.getTarget().Options.UnsafeFPMath && 16504 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 16505 break; 16506 Opcode = X86ISD::FMAX; 16507 break; 16508 case ISD::SETUGT: 16509 // Converting this to a max would handle NaNs incorrectly, and swapping 16510 // the operands would cause it to handle comparisons between positive 16511 // and negative zero incorrectly. 16512 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 16513 if (!DAG.getTarget().Options.UnsafeFPMath && 16514 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 16515 break; 16516 std::swap(LHS, RHS); 16517 } 16518 Opcode = X86ISD::FMAX; 16519 break; 16520 case ISD::SETUGE: 16521 // Converting this to a max would handle both negative zeros and NaNs 16522 // incorrectly, but we can swap the operands to fix both. 16523 std::swap(LHS, RHS); 16524 case ISD::SETOGT: 16525 case ISD::SETGT: 16526 case ISD::SETGE: 16527 Opcode = X86ISD::FMAX; 16528 break; 16529 } 16530 // Check for x CC y ? y : x -- a min/max with reversed arms. 16531 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 16532 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 16533 switch (CC) { 16534 default: break; 16535 case ISD::SETOGE: 16536 // Converting this to a min would handle comparisons between positive 16537 // and negative zero incorrectly, and swapping the operands would 16538 // cause it to handle NaNs incorrectly. 16539 if (!DAG.getTarget().Options.UnsafeFPMath && 16540 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 16541 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 16542 break; 16543 std::swap(LHS, RHS); 16544 } 16545 Opcode = X86ISD::FMIN; 16546 break; 16547 case ISD::SETUGT: 16548 // Converting this to a min would handle NaNs incorrectly. 16549 if (!DAG.getTarget().Options.UnsafeFPMath && 16550 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 16551 break; 16552 Opcode = X86ISD::FMIN; 16553 break; 16554 case ISD::SETUGE: 16555 // Converting this to a min would handle both negative zeros and NaNs 16556 // incorrectly, but we can swap the operands to fix both. 16557 std::swap(LHS, RHS); 16558 case ISD::SETOGT: 16559 case ISD::SETGT: 16560 case ISD::SETGE: 16561 Opcode = X86ISD::FMIN; 16562 break; 16563 16564 case ISD::SETULT: 16565 // Converting this to a max would handle NaNs incorrectly. 16566 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 16567 break; 16568 Opcode = X86ISD::FMAX; 16569 break; 16570 case ISD::SETOLE: 16571 // Converting this to a max would handle comparisons between positive 16572 // and negative zero incorrectly, and swapping the operands would 16573 // cause it to handle NaNs incorrectly. 16574 if (!DAG.getTarget().Options.UnsafeFPMath && 16575 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 16576 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 16577 break; 16578 std::swap(LHS, RHS); 16579 } 16580 Opcode = X86ISD::FMAX; 16581 break; 16582 case ISD::SETULE: 16583 // Converting this to a max would handle both negative zeros and NaNs 16584 // incorrectly, but we can swap the operands to fix both. 16585 std::swap(LHS, RHS); 16586 case ISD::SETOLT: 16587 case ISD::SETLT: 16588 case ISD::SETLE: 16589 Opcode = X86ISD::FMAX; 16590 break; 16591 } 16592 } 16593 16594 if (Opcode) 16595 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 16596 } 16597 16598 if (Subtarget->hasAVX512() && VT.isVector() && 16599 Cond.getValueType().getVectorElementType() == MVT::i1) { 16600 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper 16601 // lowering on AVX-512. In this case we convert it to 16602 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction. 16603 // The same situation for all 128 and 256-bit vectors of i8 and i16 16604 EVT OpVT = LHS.getValueType(); 16605 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) && 16606 (OpVT.getVectorElementType() == MVT::i8 || 16607 OpVT.getVectorElementType() == MVT::i16)) { 16608 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond); 16609 DCI.AddToWorklist(Cond.getNode()); 16610 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS); 16611 } 16612 } 16613 // If this is a select between two integer constants, try to do some 16614 // optimizations. 16615 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 16616 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 16617 // Don't do this for crazy integer types. 16618 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 16619 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 16620 // so that TrueC (the true value) is larger than FalseC. 16621 bool NeedsCondInvert = false; 16622 16623 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 16624 // Efficiently invertible. 16625 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 16626 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 16627 isa<ConstantSDNode>(Cond.getOperand(1))))) { 16628 NeedsCondInvert = true; 16629 std::swap(TrueC, FalseC); 16630 } 16631 16632 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 16633 if (FalseC->getAPIntValue() == 0 && 16634 TrueC->getAPIntValue().isPowerOf2()) { 16635 if (NeedsCondInvert) // Invert the condition if needed. 16636 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 16637 DAG.getConstant(1, Cond.getValueType())); 16638 16639 // Zero extend the condition if needed. 16640 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 16641 16642 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 16643 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 16644 DAG.getConstant(ShAmt, MVT::i8)); 16645 } 16646 16647 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 16648 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 16649 if (NeedsCondInvert) // Invert the condition if needed. 16650 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 16651 DAG.getConstant(1, Cond.getValueType())); 16652 16653 // Zero extend the condition if needed. 16654 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 16655 FalseC->getValueType(0), Cond); 16656 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 16657 SDValue(FalseC, 0)); 16658 } 16659 16660 // Optimize cases that will turn into an LEA instruction. This requires 16661 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 16662 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 16663 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 16664 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 16665 16666 bool isFastMultiplier = false; 16667 if (Diff < 10) { 16668 switch ((unsigned char)Diff) { 16669 default: break; 16670 case 1: // result = add base, cond 16671 case 2: // result = lea base( , cond*2) 16672 case 3: // result = lea base(cond, cond*2) 16673 case 4: // result = lea base( , cond*4) 16674 case 5: // result = lea base(cond, cond*4) 16675 case 8: // result = lea base( , cond*8) 16676 case 9: // result = lea base(cond, cond*8) 16677 isFastMultiplier = true; 16678 break; 16679 } 16680 } 16681 16682 if (isFastMultiplier) { 16683 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 16684 if (NeedsCondInvert) // Invert the condition if needed. 16685 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 16686 DAG.getConstant(1, Cond.getValueType())); 16687 16688 // Zero extend the condition if needed. 16689 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 16690 Cond); 16691 // Scale the condition by the difference. 16692 if (Diff != 1) 16693 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 16694 DAG.getConstant(Diff, Cond.getValueType())); 16695 16696 // Add the base if non-zero. 16697 if (FalseC->getAPIntValue() != 0) 16698 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 16699 SDValue(FalseC, 0)); 16700 return Cond; 16701 } 16702 } 16703 } 16704 } 16705 16706 // Canonicalize max and min: 16707 // (x > y) ? x : y -> (x >= y) ? x : y 16708 // (x < y) ? x : y -> (x <= y) ? x : y 16709 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 16710 // the need for an extra compare 16711 // against zero. e.g. 16712 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 16713 // subl %esi, %edi 16714 // testl %edi, %edi 16715 // movl $0, %eax 16716 // cmovgl %edi, %eax 16717 // => 16718 // xorl %eax, %eax 16719 // subl %esi, $edi 16720 // cmovsl %eax, %edi 16721 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 16722 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 16723 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 16724 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 16725 switch (CC) { 16726 default: break; 16727 case ISD::SETLT: 16728 case ISD::SETGT: { 16729 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 16730 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(), 16731 Cond.getOperand(0), Cond.getOperand(1), NewCC); 16732 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 16733 } 16734 } 16735 } 16736 16737 // Early exit check 16738 if (!TLI.isTypeLegal(VT)) 16739 return SDValue(); 16740 16741 // Match VSELECTs into subs with unsigned saturation. 16742 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && 16743 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors. 16744 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) || 16745 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) { 16746 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 16747 16748 // Check if one of the arms of the VSELECT is a zero vector. If it's on the 16749 // left side invert the predicate to simplify logic below. 16750 SDValue Other; 16751 if (ISD::isBuildVectorAllZeros(LHS.getNode())) { 16752 Other = RHS; 16753 CC = ISD::getSetCCInverse(CC, true); 16754 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) { 16755 Other = LHS; 16756 } 16757 16758 if (Other.getNode() && Other->getNumOperands() == 2 && 16759 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) { 16760 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1); 16761 SDValue CondRHS = Cond->getOperand(1); 16762 16763 // Look for a general sub with unsigned saturation first. 16764 // x >= y ? x-y : 0 --> subus x, y 16765 // x > y ? x-y : 0 --> subus x, y 16766 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) && 16767 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS)) 16768 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 16769 16770 // If the RHS is a constant we have to reverse the const canonicalization. 16771 // x > C-1 ? x+-C : 0 --> subus x, C 16772 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD && 16773 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) { 16774 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 16775 if (CondRHS.getConstantOperandVal(0) == -A-1) 16776 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, 16777 DAG.getConstant(-A, VT)); 16778 } 16779 16780 // Another special case: If C was a sign bit, the sub has been 16781 // canonicalized into a xor. 16782 // FIXME: Would it be better to use ComputeMaskedBits to determine whether 16783 // it's safe to decanonicalize the xor? 16784 // x s< 0 ? x^C : 0 --> subus x, C 16785 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR && 16786 ISD::isBuildVectorAllZeros(CondRHS.getNode()) && 16787 isSplatVector(OpRHS.getNode())) { 16788 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 16789 if (A.isSignBit()) 16790 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 16791 } 16792 } 16793 } 16794 16795 // Try to match a min/max vector operation. 16796 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) { 16797 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget); 16798 unsigned Opc = ret.first; 16799 bool NeedSplit = ret.second; 16800 16801 if (Opc && NeedSplit) { 16802 unsigned NumElems = VT.getVectorNumElements(); 16803 // Extract the LHS vectors 16804 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL); 16805 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL); 16806 16807 // Extract the RHS vectors 16808 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL); 16809 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL); 16810 16811 // Create min/max for each subvector 16812 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1); 16813 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2); 16814 16815 // Merge the result 16816 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS); 16817 } else if (Opc) 16818 return DAG.getNode(Opc, DL, VT, LHS, RHS); 16819 } 16820 16821 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*. 16822 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && 16823 // Check if SETCC has already been promoted 16824 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) { 16825 16826 assert(Cond.getValueType().isVector() && 16827 "vector select expects a vector selector!"); 16828 16829 EVT IntVT = Cond.getValueType(); 16830 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode()); 16831 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); 16832 16833 if (!TValIsAllOnes && !FValIsAllZeros) { 16834 // Try invert the condition if true value is not all 1s and false value 16835 // is not all 0s. 16836 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode()); 16837 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode()); 16838 16839 if (TValIsAllZeros || FValIsAllOnes) { 16840 SDValue CC = Cond.getOperand(2); 16841 ISD::CondCode NewCC = 16842 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 16843 Cond.getOperand(0).getValueType().isInteger()); 16844 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC); 16845 std::swap(LHS, RHS); 16846 TValIsAllOnes = FValIsAllOnes; 16847 FValIsAllZeros = TValIsAllZeros; 16848 } 16849 } 16850 16851 if (TValIsAllOnes || FValIsAllZeros) { 16852 SDValue Ret; 16853 16854 if (TValIsAllOnes && FValIsAllZeros) 16855 Ret = Cond; 16856 else if (TValIsAllOnes) 16857 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond, 16858 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS)); 16859 else if (FValIsAllZeros) 16860 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond, 16861 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS)); 16862 16863 return DAG.getNode(ISD::BITCAST, DL, VT, Ret); 16864 } 16865 } 16866 16867 // If we know that this node is legal then we know that it is going to be 16868 // matched by one of the SSE/AVX BLEND instructions. These instructions only 16869 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 16870 // to simplify previous instructions. 16871 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 16872 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) { 16873 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 16874 16875 // Don't optimize vector selects that map to mask-registers. 16876 if (BitWidth == 1) 16877 return SDValue(); 16878 16879 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 16880 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 16881 16882 APInt KnownZero, KnownOne; 16883 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 16884 DCI.isBeforeLegalizeOps()); 16885 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 16886 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 16887 DCI.CommitTargetLoweringOpt(TLO); 16888 } 16889 16890 return SDValue(); 16891} 16892 16893// Check whether a boolean test is testing a boolean value generated by 16894// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition 16895// code. 16896// 16897// Simplify the following patterns: 16898// (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or 16899// (Op (CMP (SETCC Cond EFLAGS) 0) NEQ) 16900// to (Op EFLAGS Cond) 16901// 16902// (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or 16903// (Op (CMP (SETCC Cond EFLAGS) 1) NEQ) 16904// to (Op EFLAGS !Cond) 16905// 16906// where Op could be BRCOND or CMOV. 16907// 16908static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) { 16909 // Quit if not CMP and SUB with its value result used. 16910 if (Cmp.getOpcode() != X86ISD::CMP && 16911 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0))) 16912 return SDValue(); 16913 16914 // Quit if not used as a boolean value. 16915 if (CC != X86::COND_E && CC != X86::COND_NE) 16916 return SDValue(); 16917 16918 // Check CMP operands. One of them should be 0 or 1 and the other should be 16919 // an SetCC or extended from it. 16920 SDValue Op1 = Cmp.getOperand(0); 16921 SDValue Op2 = Cmp.getOperand(1); 16922 16923 SDValue SetCC; 16924 const ConstantSDNode* C = 0; 16925 bool needOppositeCond = (CC == X86::COND_E); 16926 bool checkAgainstTrue = false; // Is it a comparison against 1? 16927 16928 if ((C = dyn_cast<ConstantSDNode>(Op1))) 16929 SetCC = Op2; 16930 else if ((C = dyn_cast<ConstantSDNode>(Op2))) 16931 SetCC = Op1; 16932 else // Quit if all operands are not constants. 16933 return SDValue(); 16934 16935 if (C->getZExtValue() == 1) { 16936 needOppositeCond = !needOppositeCond; 16937 checkAgainstTrue = true; 16938 } else if (C->getZExtValue() != 0) 16939 // Quit if the constant is neither 0 or 1. 16940 return SDValue(); 16941 16942 bool truncatedToBoolWithAnd = false; 16943 // Skip (zext $x), (trunc $x), or (and $x, 1) node. 16944 while (SetCC.getOpcode() == ISD::ZERO_EXTEND || 16945 SetCC.getOpcode() == ISD::TRUNCATE || 16946 SetCC.getOpcode() == ISD::AND) { 16947 if (SetCC.getOpcode() == ISD::AND) { 16948 int OpIdx = -1; 16949 ConstantSDNode *CS; 16950 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) && 16951 CS->getZExtValue() == 1) 16952 OpIdx = 1; 16953 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) && 16954 CS->getZExtValue() == 1) 16955 OpIdx = 0; 16956 if (OpIdx == -1) 16957 break; 16958 SetCC = SetCC.getOperand(OpIdx); 16959 truncatedToBoolWithAnd = true; 16960 } else 16961 SetCC = SetCC.getOperand(0); 16962 } 16963 16964 switch (SetCC.getOpcode()) { 16965 case X86ISD::SETCC_CARRY: 16966 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to 16967 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1, 16968 // i.e. it's a comparison against true but the result of SETCC_CARRY is not 16969 // truncated to i1 using 'and'. 16970 if (checkAgainstTrue && !truncatedToBoolWithAnd) 16971 break; 16972 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B && 16973 "Invalid use of SETCC_CARRY!"); 16974 // FALL THROUGH 16975 case X86ISD::SETCC: 16976 // Set the condition code or opposite one if necessary. 16977 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); 16978 if (needOppositeCond) 16979 CC = X86::GetOppositeBranchCondition(CC); 16980 return SetCC.getOperand(1); 16981 case X86ISD::CMOV: { 16982 // Check whether false/true value has canonical one, i.e. 0 or 1. 16983 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0)); 16984 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1)); 16985 // Quit if true value is not a constant. 16986 if (!TVal) 16987 return SDValue(); 16988 // Quit if false value is not a constant. 16989 if (!FVal) { 16990 SDValue Op = SetCC.getOperand(0); 16991 // Skip 'zext' or 'trunc' node. 16992 if (Op.getOpcode() == ISD::ZERO_EXTEND || 16993 Op.getOpcode() == ISD::TRUNCATE) 16994 Op = Op.getOperand(0); 16995 // A special case for rdrand/rdseed, where 0 is set if false cond is 16996 // found. 16997 if ((Op.getOpcode() != X86ISD::RDRAND && 16998 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0) 16999 return SDValue(); 17000 } 17001 // Quit if false value is not the constant 0 or 1. 17002 bool FValIsFalse = true; 17003 if (FVal && FVal->getZExtValue() != 0) { 17004 if (FVal->getZExtValue() != 1) 17005 return SDValue(); 17006 // If FVal is 1, opposite cond is needed. 17007 needOppositeCond = !needOppositeCond; 17008 FValIsFalse = false; 17009 } 17010 // Quit if TVal is not the constant opposite of FVal. 17011 if (FValIsFalse && TVal->getZExtValue() != 1) 17012 return SDValue(); 17013 if (!FValIsFalse && TVal->getZExtValue() != 0) 17014 return SDValue(); 17015 CC = X86::CondCode(SetCC.getConstantOperandVal(2)); 17016 if (needOppositeCond) 17017 CC = X86::GetOppositeBranchCondition(CC); 17018 return SetCC.getOperand(3); 17019 } 17020 } 17021 17022 return SDValue(); 17023} 17024 17025/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 17026static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 17027 TargetLowering::DAGCombinerInfo &DCI, 17028 const X86Subtarget *Subtarget) { 17029 SDLoc DL(N); 17030 17031 // If the flag operand isn't dead, don't touch this CMOV. 17032 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 17033 return SDValue(); 17034 17035 SDValue FalseOp = N->getOperand(0); 17036 SDValue TrueOp = N->getOperand(1); 17037 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 17038 SDValue Cond = N->getOperand(3); 17039 17040 if (CC == X86::COND_E || CC == X86::COND_NE) { 17041 switch (Cond.getOpcode()) { 17042 default: break; 17043 case X86ISD::BSR: 17044 case X86ISD::BSF: 17045 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 17046 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 17047 return (CC == X86::COND_E) ? FalseOp : TrueOp; 17048 } 17049 } 17050 17051 SDValue Flags; 17052 17053 Flags = checkBoolTestSetCCCombine(Cond, CC); 17054 if (Flags.getNode() && 17055 // Extra check as FCMOV only supports a subset of X86 cond. 17056 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) { 17057 SDValue Ops[] = { FalseOp, TrueOp, 17058 DAG.getConstant(CC, MVT::i8), Flags }; 17059 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), 17060 Ops, array_lengthof(Ops)); 17061 } 17062 17063 // If this is a select between two integer constants, try to do some 17064 // optimizations. Note that the operands are ordered the opposite of SELECT 17065 // operands. 17066 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 17067 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 17068 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 17069 // larger than FalseC (the false value). 17070 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 17071 CC = X86::GetOppositeBranchCondition(CC); 17072 std::swap(TrueC, FalseC); 17073 std::swap(TrueOp, FalseOp); 17074 } 17075 17076 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 17077 // This is efficient for any integer data type (including i8/i16) and 17078 // shift amount. 17079 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 17080 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 17081 DAG.getConstant(CC, MVT::i8), Cond); 17082 17083 // Zero extend the condition if needed. 17084 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 17085 17086 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 17087 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 17088 DAG.getConstant(ShAmt, MVT::i8)); 17089 if (N->getNumValues() == 2) // Dead flag value? 17090 return DCI.CombineTo(N, Cond, SDValue()); 17091 return Cond; 17092 } 17093 17094 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 17095 // for any integer data type, including i8/i16. 17096 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 17097 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 17098 DAG.getConstant(CC, MVT::i8), Cond); 17099 17100 // Zero extend the condition if needed. 17101 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 17102 FalseC->getValueType(0), Cond); 17103 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 17104 SDValue(FalseC, 0)); 17105 17106 if (N->getNumValues() == 2) // Dead flag value? 17107 return DCI.CombineTo(N, Cond, SDValue()); 17108 return Cond; 17109 } 17110 17111 // Optimize cases that will turn into an LEA instruction. This requires 17112 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 17113 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 17114 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 17115 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 17116 17117 bool isFastMultiplier = false; 17118 if (Diff < 10) { 17119 switch ((unsigned char)Diff) { 17120 default: break; 17121 case 1: // result = add base, cond 17122 case 2: // result = lea base( , cond*2) 17123 case 3: // result = lea base(cond, cond*2) 17124 case 4: // result = lea base( , cond*4) 17125 case 5: // result = lea base(cond, cond*4) 17126 case 8: // result = lea base( , cond*8) 17127 case 9: // result = lea base(cond, cond*8) 17128 isFastMultiplier = true; 17129 break; 17130 } 17131 } 17132 17133 if (isFastMultiplier) { 17134 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 17135 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 17136 DAG.getConstant(CC, MVT::i8), Cond); 17137 // Zero extend the condition if needed. 17138 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 17139 Cond); 17140 // Scale the condition by the difference. 17141 if (Diff != 1) 17142 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 17143 DAG.getConstant(Diff, Cond.getValueType())); 17144 17145 // Add the base if non-zero. 17146 if (FalseC->getAPIntValue() != 0) 17147 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 17148 SDValue(FalseC, 0)); 17149 if (N->getNumValues() == 2) // Dead flag value? 17150 return DCI.CombineTo(N, Cond, SDValue()); 17151 return Cond; 17152 } 17153 } 17154 } 17155 } 17156 17157 // Handle these cases: 17158 // (select (x != c), e, c) -> select (x != c), e, x), 17159 // (select (x == c), c, e) -> select (x == c), x, e) 17160 // where the c is an integer constant, and the "select" is the combination 17161 // of CMOV and CMP. 17162 // 17163 // The rationale for this change is that the conditional-move from a constant 17164 // needs two instructions, however, conditional-move from a register needs 17165 // only one instruction. 17166 // 17167 // CAVEAT: By replacing a constant with a symbolic value, it may obscure 17168 // some instruction-combining opportunities. This opt needs to be 17169 // postponed as late as possible. 17170 // 17171 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { 17172 // the DCI.xxxx conditions are provided to postpone the optimization as 17173 // late as possible. 17174 17175 ConstantSDNode *CmpAgainst = 0; 17176 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) && 17177 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) && 17178 !isa<ConstantSDNode>(Cond.getOperand(0))) { 17179 17180 if (CC == X86::COND_NE && 17181 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) { 17182 CC = X86::GetOppositeBranchCondition(CC); 17183 std::swap(TrueOp, FalseOp); 17184 } 17185 17186 if (CC == X86::COND_E && 17187 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) { 17188 SDValue Ops[] = { FalseOp, Cond.getOperand(0), 17189 DAG.getConstant(CC, MVT::i8), Cond }; 17190 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops, 17191 array_lengthof(Ops)); 17192 } 17193 } 17194 } 17195 17196 return SDValue(); 17197} 17198 17199/// PerformMulCombine - Optimize a single multiply with constant into two 17200/// in order to implement it with two cheaper instructions, e.g. 17201/// LEA + SHL, LEA + LEA. 17202static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 17203 TargetLowering::DAGCombinerInfo &DCI) { 17204 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 17205 return SDValue(); 17206 17207 EVT VT = N->getValueType(0); 17208 if (VT != MVT::i64) 17209 return SDValue(); 17210 17211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 17212 if (!C) 17213 return SDValue(); 17214 uint64_t MulAmt = C->getZExtValue(); 17215 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 17216 return SDValue(); 17217 17218 uint64_t MulAmt1 = 0; 17219 uint64_t MulAmt2 = 0; 17220 if ((MulAmt % 9) == 0) { 17221 MulAmt1 = 9; 17222 MulAmt2 = MulAmt / 9; 17223 } else if ((MulAmt % 5) == 0) { 17224 MulAmt1 = 5; 17225 MulAmt2 = MulAmt / 5; 17226 } else if ((MulAmt % 3) == 0) { 17227 MulAmt1 = 3; 17228 MulAmt2 = MulAmt / 3; 17229 } 17230 if (MulAmt2 && 17231 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 17232 SDLoc DL(N); 17233 17234 if (isPowerOf2_64(MulAmt2) && 17235 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 17236 // If second multiplifer is pow2, issue it first. We want the multiply by 17237 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 17238 // is an add. 17239 std::swap(MulAmt1, MulAmt2); 17240 17241 SDValue NewMul; 17242 if (isPowerOf2_64(MulAmt1)) 17243 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 17244 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 17245 else 17246 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 17247 DAG.getConstant(MulAmt1, VT)); 17248 17249 if (isPowerOf2_64(MulAmt2)) 17250 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 17251 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 17252 else 17253 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 17254 DAG.getConstant(MulAmt2, VT)); 17255 17256 // Do not add new nodes to DAG combiner worklist. 17257 DCI.CombineTo(N, NewMul, false); 17258 } 17259 return SDValue(); 17260} 17261 17262static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 17263 SDValue N0 = N->getOperand(0); 17264 SDValue N1 = N->getOperand(1); 17265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 17266 EVT VT = N0.getValueType(); 17267 17268 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 17269 // since the result of setcc_c is all zero's or all ones. 17270 if (VT.isInteger() && !VT.isVector() && 17271 N1C && N0.getOpcode() == ISD::AND && 17272 N0.getOperand(1).getOpcode() == ISD::Constant) { 17273 SDValue N00 = N0.getOperand(0); 17274 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 17275 ((N00.getOpcode() == ISD::ANY_EXTEND || 17276 N00.getOpcode() == ISD::ZERO_EXTEND) && 17277 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 17278 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 17279 APInt ShAmt = N1C->getAPIntValue(); 17280 Mask = Mask.shl(ShAmt); 17281 if (Mask != 0) 17282 return DAG.getNode(ISD::AND, SDLoc(N), VT, 17283 N00, DAG.getConstant(Mask, VT)); 17284 } 17285 } 17286 17287 // Hardware support for vector shifts is sparse which makes us scalarize the 17288 // vector operations in many cases. Also, on sandybridge ADD is faster than 17289 // shl. 17290 // (shl V, 1) -> add V,V 17291 if (isSplatVector(N1.getNode())) { 17292 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 17293 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 17294 // We shift all of the values by one. In many cases we do not have 17295 // hardware support for this operation. This is better expressed as an ADD 17296 // of two values. 17297 if (N1C && (1 == N1C->getZExtValue())) { 17298 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0); 17299 } 17300 } 17301 17302 return SDValue(); 17303} 17304 17305/// \brief Returns a vector of 0s if the node in input is a vector logical 17306/// shift by a constant amount which is known to be bigger than or equal 17307/// to the vector element size in bits. 17308static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG, 17309 const X86Subtarget *Subtarget) { 17310 EVT VT = N->getValueType(0); 17311 17312 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 17313 (!Subtarget->hasInt256() || 17314 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 17315 return SDValue(); 17316 17317 SDValue Amt = N->getOperand(1); 17318 SDLoc DL(N); 17319 if (isSplatVector(Amt.getNode())) { 17320 SDValue SclrAmt = Amt->getOperand(0); 17321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 17322 APInt ShiftAmt = C->getAPIntValue(); 17323 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits(); 17324 17325 // SSE2/AVX2 logical shifts always return a vector of 0s 17326 // if the shift amount is bigger than or equal to 17327 // the element size. The constant shift amount will be 17328 // encoded as a 8-bit immediate. 17329 if (ShiftAmt.trunc(8).uge(MaxAmount)) 17330 return getZeroVector(VT, Subtarget, DAG, DL); 17331 } 17332 } 17333 17334 return SDValue(); 17335} 17336 17337/// PerformShiftCombine - Combine shifts. 17338static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 17339 TargetLowering::DAGCombinerInfo &DCI, 17340 const X86Subtarget *Subtarget) { 17341 if (N->getOpcode() == ISD::SHL) { 17342 SDValue V = PerformSHLCombine(N, DAG); 17343 if (V.getNode()) return V; 17344 } 17345 17346 if (N->getOpcode() != ISD::SRA) { 17347 // Try to fold this logical shift into a zero vector. 17348 SDValue V = performShiftToAllZeros(N, DAG, Subtarget); 17349 if (V.getNode()) return V; 17350 } 17351 17352 return SDValue(); 17353} 17354 17355// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 17356// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 17357// and friends. Likewise for OR -> CMPNEQSS. 17358static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 17359 TargetLowering::DAGCombinerInfo &DCI, 17360 const X86Subtarget *Subtarget) { 17361 unsigned opcode; 17362 17363 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 17364 // we're requiring SSE2 for both. 17365 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 17366 SDValue N0 = N->getOperand(0); 17367 SDValue N1 = N->getOperand(1); 17368 SDValue CMP0 = N0->getOperand(1); 17369 SDValue CMP1 = N1->getOperand(1); 17370 SDLoc DL(N); 17371 17372 // The SETCCs should both refer to the same CMP. 17373 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 17374 return SDValue(); 17375 17376 SDValue CMP00 = CMP0->getOperand(0); 17377 SDValue CMP01 = CMP0->getOperand(1); 17378 EVT VT = CMP00.getValueType(); 17379 17380 if (VT == MVT::f32 || VT == MVT::f64) { 17381 bool ExpectingFlags = false; 17382 // Check for any users that want flags: 17383 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 17384 !ExpectingFlags && UI != UE; ++UI) 17385 switch (UI->getOpcode()) { 17386 default: 17387 case ISD::BR_CC: 17388 case ISD::BRCOND: 17389 case ISD::SELECT: 17390 ExpectingFlags = true; 17391 break; 17392 case ISD::CopyToReg: 17393 case ISD::SIGN_EXTEND: 17394 case ISD::ZERO_EXTEND: 17395 case ISD::ANY_EXTEND: 17396 break; 17397 } 17398 17399 if (!ExpectingFlags) { 17400 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 17401 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 17402 17403 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 17404 X86::CondCode tmp = cc0; 17405 cc0 = cc1; 17406 cc1 = tmp; 17407 } 17408 17409 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 17410 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 17411 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 17412 X86ISD::NodeType NTOperator = is64BitFP ? 17413 X86ISD::FSETCCsd : X86ISD::FSETCCss; 17414 // FIXME: need symbolic constants for these magic numbers. 17415 // See X86ATTInstPrinter.cpp:printSSECC(). 17416 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 17417 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 17418 DAG.getConstant(x86cc, MVT::i8)); 17419 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 17420 OnesOrZeroesF); 17421 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 17422 DAG.getConstant(1, MVT::i32)); 17423 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 17424 return OneBitOfTruth; 17425 } 17426 } 17427 } 17428 } 17429 return SDValue(); 17430} 17431 17432/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 17433/// so it can be folded inside ANDNP. 17434static bool CanFoldXORWithAllOnes(const SDNode *N) { 17435 EVT VT = N->getValueType(0); 17436 17437 // Match direct AllOnes for 128 and 256-bit vectors 17438 if (ISD::isBuildVectorAllOnes(N)) 17439 return true; 17440 17441 // Look through a bit convert. 17442 if (N->getOpcode() == ISD::BITCAST) 17443 N = N->getOperand(0).getNode(); 17444 17445 // Sometimes the operand may come from a insert_subvector building a 256-bit 17446 // allones vector 17447 if (VT.is256BitVector() && 17448 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 17449 SDValue V1 = N->getOperand(0); 17450 SDValue V2 = N->getOperand(1); 17451 17452 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 17453 V1.getOperand(0).getOpcode() == ISD::UNDEF && 17454 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 17455 ISD::isBuildVectorAllOnes(V2.getNode())) 17456 return true; 17457 } 17458 17459 return false; 17460} 17461 17462// On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 17463// register. In most cases we actually compare or select YMM-sized registers 17464// and mixing the two types creates horrible code. This method optimizes 17465// some of the transition sequences. 17466static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG, 17467 TargetLowering::DAGCombinerInfo &DCI, 17468 const X86Subtarget *Subtarget) { 17469 EVT VT = N->getValueType(0); 17470 if (!VT.is256BitVector()) 17471 return SDValue(); 17472 17473 assert((N->getOpcode() == ISD::ANY_EXTEND || 17474 N->getOpcode() == ISD::ZERO_EXTEND || 17475 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node"); 17476 17477 SDValue Narrow = N->getOperand(0); 17478 EVT NarrowVT = Narrow->getValueType(0); 17479 if (!NarrowVT.is128BitVector()) 17480 return SDValue(); 17481 17482 if (Narrow->getOpcode() != ISD::XOR && 17483 Narrow->getOpcode() != ISD::AND && 17484 Narrow->getOpcode() != ISD::OR) 17485 return SDValue(); 17486 17487 SDValue N0 = Narrow->getOperand(0); 17488 SDValue N1 = Narrow->getOperand(1); 17489 SDLoc DL(Narrow); 17490 17491 // The Left side has to be a trunc. 17492 if (N0.getOpcode() != ISD::TRUNCATE) 17493 return SDValue(); 17494 17495 // The type of the truncated inputs. 17496 EVT WideVT = N0->getOperand(0)->getValueType(0); 17497 if (WideVT != VT) 17498 return SDValue(); 17499 17500 // The right side has to be a 'trunc' or a constant vector. 17501 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE; 17502 bool RHSConst = (isSplatVector(N1.getNode()) && 17503 isa<ConstantSDNode>(N1->getOperand(0))); 17504 if (!RHSTrunc && !RHSConst) 17505 return SDValue(); 17506 17507 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 17508 17509 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) 17510 return SDValue(); 17511 17512 // Set N0 and N1 to hold the inputs to the new wide operation. 17513 N0 = N0->getOperand(0); 17514 if (RHSConst) { 17515 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(), 17516 N1->getOperand(0)); 17517 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1); 17518 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size()); 17519 } else if (RHSTrunc) { 17520 N1 = N1->getOperand(0); 17521 } 17522 17523 // Generate the wide operation. 17524 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); 17525 unsigned Opcode = N->getOpcode(); 17526 switch (Opcode) { 17527 case ISD::ANY_EXTEND: 17528 return Op; 17529 case ISD::ZERO_EXTEND: { 17530 unsigned InBits = NarrowVT.getScalarType().getSizeInBits(); 17531 APInt Mask = APInt::getAllOnesValue(InBits); 17532 Mask = Mask.zext(VT.getScalarType().getSizeInBits()); 17533 return DAG.getNode(ISD::AND, DL, VT, 17534 Op, DAG.getConstant(Mask, VT)); 17535 } 17536 case ISD::SIGN_EXTEND: 17537 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, 17538 Op, DAG.getValueType(NarrowVT)); 17539 default: 17540 llvm_unreachable("Unexpected opcode"); 17541 } 17542} 17543 17544static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 17545 TargetLowering::DAGCombinerInfo &DCI, 17546 const X86Subtarget *Subtarget) { 17547 EVT VT = N->getValueType(0); 17548 if (DCI.isBeforeLegalizeOps()) 17549 return SDValue(); 17550 17551 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 17552 if (R.getNode()) 17553 return R; 17554 17555 // Create BLSI, BLSR, and BZHI instructions 17556 // BLSI is X & (-X) 17557 // BLSR is X & (X-1) 17558 // BZHI is X & ((1 << Y) - 1) 17559 // BEXTR is ((X >> imm) & (2**size-1)) 17560 if (VT == MVT::i32 || VT == MVT::i64) { 17561 SDValue N0 = N->getOperand(0); 17562 SDValue N1 = N->getOperand(1); 17563 SDLoc DL(N); 17564 17565 if (Subtarget->hasBMI()) { 17566 // Check LHS for neg 17567 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 17568 isZero(N0.getOperand(0))) 17569 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 17570 17571 // Check RHS for neg 17572 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 17573 isZero(N1.getOperand(0))) 17574 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 17575 17576 // Check LHS for X-1 17577 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 17578 isAllOnes(N0.getOperand(1))) 17579 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 17580 17581 // Check RHS for X-1 17582 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 17583 isAllOnes(N1.getOperand(1))) 17584 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 17585 } 17586 17587 if (Subtarget->hasBMI2()) { 17588 // Check for (and (add (shl 1, Y), -1), X) 17589 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) { 17590 SDValue N00 = N0.getOperand(0); 17591 if (N00.getOpcode() == ISD::SHL) { 17592 SDValue N001 = N00.getOperand(1); 17593 assert(N001.getValueType() == MVT::i8 && "unexpected type"); 17594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0)); 17595 if (C && C->getZExtValue() == 1) 17596 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001); 17597 } 17598 } 17599 17600 // Check for (and X, (add (shl 1, Y), -1)) 17601 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) { 17602 SDValue N10 = N1.getOperand(0); 17603 if (N10.getOpcode() == ISD::SHL) { 17604 SDValue N101 = N10.getOperand(1); 17605 assert(N101.getValueType() == MVT::i8 && "unexpected type"); 17606 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0)); 17607 if (C && C->getZExtValue() == 1) 17608 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101); 17609 } 17610 } 17611 } 17612 17613 // Check for BEXTR. 17614 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) && 17615 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) { 17616 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1); 17617 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 17618 if (MaskNode && ShiftNode) { 17619 uint64_t Mask = MaskNode->getZExtValue(); 17620 uint64_t Shift = ShiftNode->getZExtValue(); 17621 if (isMask_64(Mask)) { 17622 uint64_t MaskSize = CountPopulation_64(Mask); 17623 if (Shift + MaskSize <= VT.getSizeInBits()) 17624 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0), 17625 DAG.getConstant(Shift | (MaskSize << 8), VT)); 17626 } 17627 } 17628 } // BEXTR 17629 17630 return SDValue(); 17631 } 17632 17633 // Want to form ANDNP nodes: 17634 // 1) In the hopes of then easily combining them with OR and AND nodes 17635 // to form PBLEND/PSIGN. 17636 // 2) To match ANDN packed intrinsics 17637 if (VT != MVT::v2i64 && VT != MVT::v4i64) 17638 return SDValue(); 17639 17640 SDValue N0 = N->getOperand(0); 17641 SDValue N1 = N->getOperand(1); 17642 SDLoc DL(N); 17643 17644 // Check LHS for vnot 17645 if (N0.getOpcode() == ISD::XOR && 17646 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 17647 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 17648 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 17649 17650 // Check RHS for vnot 17651 if (N1.getOpcode() == ISD::XOR && 17652 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 17653 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 17654 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 17655 17656 return SDValue(); 17657} 17658 17659static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 17660 TargetLowering::DAGCombinerInfo &DCI, 17661 const X86Subtarget *Subtarget) { 17662 EVT VT = N->getValueType(0); 17663 if (DCI.isBeforeLegalizeOps()) 17664 return SDValue(); 17665 17666 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 17667 if (R.getNode()) 17668 return R; 17669 17670 SDValue N0 = N->getOperand(0); 17671 SDValue N1 = N->getOperand(1); 17672 17673 // look for psign/blend 17674 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 17675 if (!Subtarget->hasSSSE3() || 17676 (VT == MVT::v4i64 && !Subtarget->hasInt256())) 17677 return SDValue(); 17678 17679 // Canonicalize pandn to RHS 17680 if (N0.getOpcode() == X86ISD::ANDNP) 17681 std::swap(N0, N1); 17682 // or (and (m, y), (pandn m, x)) 17683 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 17684 SDValue Mask = N1.getOperand(0); 17685 SDValue X = N1.getOperand(1); 17686 SDValue Y; 17687 if (N0.getOperand(0) == Mask) 17688 Y = N0.getOperand(1); 17689 if (N0.getOperand(1) == Mask) 17690 Y = N0.getOperand(0); 17691 17692 // Check to see if the mask appeared in both the AND and ANDNP and 17693 if (!Y.getNode()) 17694 return SDValue(); 17695 17696 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 17697 // Look through mask bitcast. 17698 if (Mask.getOpcode() == ISD::BITCAST) 17699 Mask = Mask.getOperand(0); 17700 if (X.getOpcode() == ISD::BITCAST) 17701 X = X.getOperand(0); 17702 if (Y.getOpcode() == ISD::BITCAST) 17703 Y = Y.getOperand(0); 17704 17705 EVT MaskVT = Mask.getValueType(); 17706 17707 // Validate that the Mask operand is a vector sra node. 17708 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 17709 // there is no psrai.b 17710 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 17711 unsigned SraAmt = ~0; 17712 if (Mask.getOpcode() == ISD::SRA) { 17713 SDValue Amt = Mask.getOperand(1); 17714 if (isSplatVector(Amt.getNode())) { 17715 SDValue SclrAmt = Amt->getOperand(0); 17716 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) 17717 SraAmt = C->getZExtValue(); 17718 } 17719 } else if (Mask.getOpcode() == X86ISD::VSRAI) { 17720 SDValue SraC = Mask.getOperand(1); 17721 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 17722 } 17723 if ((SraAmt + 1) != EltBits) 17724 return SDValue(); 17725 17726 SDLoc DL(N); 17727 17728 // Now we know we at least have a plendvb with the mask val. See if 17729 // we can form a psignb/w/d. 17730 // psign = x.type == y.type == mask.type && y = sub(0, x); 17731 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 17732 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 17733 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 17734 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 17735 "Unsupported VT for PSIGN"); 17736 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 17737 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 17738 } 17739 // PBLENDVB only available on SSE 4.1 17740 if (!Subtarget->hasSSE41()) 17741 return SDValue(); 17742 17743 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 17744 17745 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 17746 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 17747 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 17748 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 17749 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 17750 } 17751 } 17752 17753 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 17754 return SDValue(); 17755 17756 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 17757 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 17758 std::swap(N0, N1); 17759 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 17760 return SDValue(); 17761 if (!N0.hasOneUse() || !N1.hasOneUse()) 17762 return SDValue(); 17763 17764 SDValue ShAmt0 = N0.getOperand(1); 17765 if (ShAmt0.getValueType() != MVT::i8) 17766 return SDValue(); 17767 SDValue ShAmt1 = N1.getOperand(1); 17768 if (ShAmt1.getValueType() != MVT::i8) 17769 return SDValue(); 17770 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 17771 ShAmt0 = ShAmt0.getOperand(0); 17772 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 17773 ShAmt1 = ShAmt1.getOperand(0); 17774 17775 SDLoc DL(N); 17776 unsigned Opc = X86ISD::SHLD; 17777 SDValue Op0 = N0.getOperand(0); 17778 SDValue Op1 = N1.getOperand(0); 17779 if (ShAmt0.getOpcode() == ISD::SUB) { 17780 Opc = X86ISD::SHRD; 17781 std::swap(Op0, Op1); 17782 std::swap(ShAmt0, ShAmt1); 17783 } 17784 17785 unsigned Bits = VT.getSizeInBits(); 17786 if (ShAmt1.getOpcode() == ISD::SUB) { 17787 SDValue Sum = ShAmt1.getOperand(0); 17788 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 17789 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 17790 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 17791 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 17792 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 17793 return DAG.getNode(Opc, DL, VT, 17794 Op0, Op1, 17795 DAG.getNode(ISD::TRUNCATE, DL, 17796 MVT::i8, ShAmt0)); 17797 } 17798 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 17799 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 17800 if (ShAmt0C && 17801 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 17802 return DAG.getNode(Opc, DL, VT, 17803 N0.getOperand(0), N1.getOperand(0), 17804 DAG.getNode(ISD::TRUNCATE, DL, 17805 MVT::i8, ShAmt0)); 17806 } 17807 17808 return SDValue(); 17809} 17810 17811// Generate NEG and CMOV for integer abs. 17812static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 17813 EVT VT = N->getValueType(0); 17814 17815 // Since X86 does not have CMOV for 8-bit integer, we don't convert 17816 // 8-bit integer abs to NEG and CMOV. 17817 if (VT.isInteger() && VT.getSizeInBits() == 8) 17818 return SDValue(); 17819 17820 SDValue N0 = N->getOperand(0); 17821 SDValue N1 = N->getOperand(1); 17822 SDLoc DL(N); 17823 17824 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 17825 // and change it to SUB and CMOV. 17826 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 17827 N0.getOpcode() == ISD::ADD && 17828 N0.getOperand(1) == N1 && 17829 N1.getOpcode() == ISD::SRA && 17830 N1.getOperand(0) == N0.getOperand(0)) 17831 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 17832 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { 17833 // Generate SUB & CMOV. 17834 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32), 17835 DAG.getConstant(0, VT), N0.getOperand(0)); 17836 17837 SDValue Ops[] = { N0.getOperand(0), Neg, 17838 DAG.getConstant(X86::COND_GE, MVT::i8), 17839 SDValue(Neg.getNode(), 1) }; 17840 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), 17841 Ops, array_lengthof(Ops)); 17842 } 17843 return SDValue(); 17844} 17845 17846// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 17847static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 17848 TargetLowering::DAGCombinerInfo &DCI, 17849 const X86Subtarget *Subtarget) { 17850 EVT VT = N->getValueType(0); 17851 if (DCI.isBeforeLegalizeOps()) 17852 return SDValue(); 17853 17854 if (Subtarget->hasCMov()) { 17855 SDValue RV = performIntegerAbsCombine(N, DAG); 17856 if (RV.getNode()) 17857 return RV; 17858 } 17859 17860 // Try forming BMI if it is available. 17861 if (!Subtarget->hasBMI()) 17862 return SDValue(); 17863 17864 if (VT != MVT::i32 && VT != MVT::i64) 17865 return SDValue(); 17866 17867 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 17868 17869 // Create BLSMSK instructions by finding X ^ (X-1) 17870 SDValue N0 = N->getOperand(0); 17871 SDValue N1 = N->getOperand(1); 17872 SDLoc DL(N); 17873 17874 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 17875 isAllOnes(N0.getOperand(1))) 17876 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 17877 17878 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 17879 isAllOnes(N1.getOperand(1))) 17880 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 17881 17882 return SDValue(); 17883} 17884 17885/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 17886static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 17887 TargetLowering::DAGCombinerInfo &DCI, 17888 const X86Subtarget *Subtarget) { 17889 LoadSDNode *Ld = cast<LoadSDNode>(N); 17890 EVT RegVT = Ld->getValueType(0); 17891 EVT MemVT = Ld->getMemoryVT(); 17892 SDLoc dl(Ld); 17893 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 17894 unsigned RegSz = RegVT.getSizeInBits(); 17895 17896 // On Sandybridge unaligned 256bit loads are inefficient. 17897 ISD::LoadExtType Ext = Ld->getExtensionType(); 17898 unsigned Alignment = Ld->getAlignment(); 17899 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8; 17900 if (RegVT.is256BitVector() && !Subtarget->hasInt256() && 17901 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) { 17902 unsigned NumElems = RegVT.getVectorNumElements(); 17903 if (NumElems < 2) 17904 return SDValue(); 17905 17906 SDValue Ptr = Ld->getBasePtr(); 17907 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy()); 17908 17909 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 17910 NumElems/2); 17911 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 17912 Ld->getPointerInfo(), Ld->isVolatile(), 17913 Ld->isNonTemporal(), Ld->isInvariant(), 17914 Alignment); 17915 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 17916 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 17917 Ld->getPointerInfo(), Ld->isVolatile(), 17918 Ld->isNonTemporal(), Ld->isInvariant(), 17919 std::min(16U, Alignment)); 17920 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 17921 Load1.getValue(1), 17922 Load2.getValue(1)); 17923 17924 SDValue NewVec = DAG.getUNDEF(RegVT); 17925 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl); 17926 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl); 17927 return DCI.CombineTo(N, NewVec, TF, true); 17928 } 17929 17930 // If this is a vector EXT Load then attempt to optimize it using a 17931 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the 17932 // expansion is still better than scalar code. 17933 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll 17934 // emit a shuffle and a arithmetic shift. 17935 // TODO: It is possible to support ZExt by zeroing the undef values 17936 // during the shuffle phase or after the shuffle. 17937 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() && 17938 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) { 17939 assert(MemVT != RegVT && "Cannot extend to the same type"); 17940 assert(MemVT.isVector() && "Must load a vector from memory"); 17941 17942 unsigned NumElems = RegVT.getVectorNumElements(); 17943 unsigned MemSz = MemVT.getSizeInBits(); 17944 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 17945 17946 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) 17947 return SDValue(); 17948 17949 // All sizes must be a power of two. 17950 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) 17951 return SDValue(); 17952 17953 // Attempt to load the original value using scalar loads. 17954 // Find the largest scalar type that divides the total loaded size. 17955 MVT SclrLoadTy = MVT::i8; 17956 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 17957 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 17958 MVT Tp = (MVT::SimpleValueType)tp; 17959 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { 17960 SclrLoadTy = Tp; 17961 } 17962 } 17963 17964 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 17965 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && 17966 (64 <= MemSz)) 17967 SclrLoadTy = MVT::f64; 17968 17969 // Calculate the number of scalar loads that we need to perform 17970 // in order to load our vector from memory. 17971 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); 17972 if (Ext == ISD::SEXTLOAD && NumLoads > 1) 17973 return SDValue(); 17974 17975 unsigned loadRegZize = RegSz; 17976 if (Ext == ISD::SEXTLOAD && RegSz == 256) 17977 loadRegZize /= 2; 17978 17979 // Represent our vector as a sequence of elements which are the 17980 // largest scalar that we can load. 17981 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 17982 loadRegZize/SclrLoadTy.getSizeInBits()); 17983 17984 // Represent the data using the same element type that is stored in 17985 // memory. In practice, we ''widen'' MemVT. 17986 EVT WideVecVT = 17987 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 17988 loadRegZize/MemVT.getScalarType().getSizeInBits()); 17989 17990 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && 17991 "Invalid vector type"); 17992 17993 // We can't shuffle using an illegal type. 17994 if (!TLI.isTypeLegal(WideVecVT)) 17995 return SDValue(); 17996 17997 SmallVector<SDValue, 8> Chains; 17998 SDValue Ptr = Ld->getBasePtr(); 17999 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8, 18000 TLI.getPointerTy()); 18001 SDValue Res = DAG.getUNDEF(LoadUnitVecVT); 18002 18003 for (unsigned i = 0; i < NumLoads; ++i) { 18004 // Perform a single load. 18005 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 18006 Ptr, Ld->getPointerInfo(), 18007 Ld->isVolatile(), Ld->isNonTemporal(), 18008 Ld->isInvariant(), Ld->getAlignment()); 18009 Chains.push_back(ScalarLoad.getValue(1)); 18010 // Create the first element type using SCALAR_TO_VECTOR in order to avoid 18011 // another round of DAGCombining. 18012 if (i == 0) 18013 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad); 18014 else 18015 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res, 18016 ScalarLoad, DAG.getIntPtrConstant(i)); 18017 18018 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 18019 } 18020 18021 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 18022 Chains.size()); 18023 18024 // Bitcast the loaded value to a vector of the original element type, in 18025 // the size of the target vector type. 18026 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res); 18027 unsigned SizeRatio = RegSz/MemSz; 18028 18029 if (Ext == ISD::SEXTLOAD) { 18030 // If we have SSE4.1 we can directly emit a VSEXT node. 18031 if (Subtarget->hasSSE41()) { 18032 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec); 18033 return DCI.CombineTo(N, Sext, TF, true); 18034 } 18035 18036 // Otherwise we'll shuffle the small elements in the high bits of the 18037 // larger type and perform an arithmetic shift. If the shift is not legal 18038 // it's better to scalarize. 18039 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT)) 18040 return SDValue(); 18041 18042 // Redistribute the loaded elements into the different locations. 18043 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 18044 for (unsigned i = 0; i != NumElems; ++i) 18045 ShuffleVec[i*SizeRatio + SizeRatio-1] = i; 18046 18047 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 18048 DAG.getUNDEF(WideVecVT), 18049 &ShuffleVec[0]); 18050 18051 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 18052 18053 // Build the arithmetic shift. 18054 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() - 18055 MemVT.getVectorElementType().getSizeInBits(); 18056 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, 18057 DAG.getConstant(Amt, RegVT)); 18058 18059 return DCI.CombineTo(N, Shuff, TF, true); 18060 } 18061 18062 // Redistribute the loaded elements into the different locations. 18063 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 18064 for (unsigned i = 0; i != NumElems; ++i) 18065 ShuffleVec[i*SizeRatio] = i; 18066 18067 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 18068 DAG.getUNDEF(WideVecVT), 18069 &ShuffleVec[0]); 18070 18071 // Bitcast to the requested type. 18072 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 18073 // Replace the original load with the new sequence 18074 // and return the new chain. 18075 return DCI.CombineTo(N, Shuff, TF, true); 18076 } 18077 18078 return SDValue(); 18079} 18080 18081/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 18082static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 18083 const X86Subtarget *Subtarget) { 18084 StoreSDNode *St = cast<StoreSDNode>(N); 18085 EVT VT = St->getValue().getValueType(); 18086 EVT StVT = St->getMemoryVT(); 18087 SDLoc dl(St); 18088 SDValue StoredVal = St->getOperand(1); 18089 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 18090 18091 // If we are saving a concatenation of two XMM registers, perform two stores. 18092 // On Sandy Bridge, 256-bit memory operations are executed by two 18093 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit 18094 // memory operation. 18095 unsigned Alignment = St->getAlignment(); 18096 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8; 18097 if (VT.is256BitVector() && !Subtarget->hasInt256() && 18098 StVT == VT && !IsAligned) { 18099 unsigned NumElems = VT.getVectorNumElements(); 18100 if (NumElems < 2) 18101 return SDValue(); 18102 18103 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl); 18104 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl); 18105 18106 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 18107 SDValue Ptr0 = St->getBasePtr(); 18108 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 18109 18110 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 18111 St->getPointerInfo(), St->isVolatile(), 18112 St->isNonTemporal(), Alignment); 18113 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 18114 St->getPointerInfo(), St->isVolatile(), 18115 St->isNonTemporal(), 18116 std::min(16U, Alignment)); 18117 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 18118 } 18119 18120 // Optimize trunc store (of multiple scalars) to shuffle and store. 18121 // First, pack all of the elements in one place. Next, store to memory 18122 // in fewer chunks. 18123 if (St->isTruncatingStore() && VT.isVector()) { 18124 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 18125 unsigned NumElems = VT.getVectorNumElements(); 18126 assert(StVT != VT && "Cannot truncate to the same type"); 18127 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 18128 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 18129 18130 // From, To sizes and ElemCount must be pow of two 18131 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 18132 // We are going to use the original vector elt for storing. 18133 // Accumulated smaller vector elements must be a multiple of the store size. 18134 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 18135 18136 unsigned SizeRatio = FromSz / ToSz; 18137 18138 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 18139 18140 // Create a type on which we perform the shuffle 18141 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 18142 StVT.getScalarType(), NumElems*SizeRatio); 18143 18144 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 18145 18146 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 18147 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 18148 for (unsigned i = 0; i != NumElems; ++i) 18149 ShuffleVec[i] = i * SizeRatio; 18150 18151 // Can't shuffle using an illegal type. 18152 if (!TLI.isTypeLegal(WideVecVT)) 18153 return SDValue(); 18154 18155 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 18156 DAG.getUNDEF(WideVecVT), 18157 &ShuffleVec[0]); 18158 // At this point all of the data is stored at the bottom of the 18159 // register. We now need to save it to mem. 18160 18161 // Find the largest store unit 18162 MVT StoreType = MVT::i8; 18163 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 18164 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 18165 MVT Tp = (MVT::SimpleValueType)tp; 18166 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) 18167 StoreType = Tp; 18168 } 18169 18170 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 18171 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && 18172 (64 <= NumElems * ToSz)) 18173 StoreType = MVT::f64; 18174 18175 // Bitcast the original vector into a vector of store-size units 18176 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 18177 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); 18178 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 18179 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 18180 SmallVector<SDValue, 8> Chains; 18181 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 18182 TLI.getPointerTy()); 18183 SDValue Ptr = St->getBasePtr(); 18184 18185 // Perform one or more big stores into memory. 18186 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 18187 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 18188 StoreType, ShuffWide, 18189 DAG.getIntPtrConstant(i)); 18190 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 18191 St->getPointerInfo(), St->isVolatile(), 18192 St->isNonTemporal(), St->getAlignment()); 18193 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 18194 Chains.push_back(Ch); 18195 } 18196 18197 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 18198 Chains.size()); 18199 } 18200 18201 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 18202 // the FP state in cases where an emms may be missing. 18203 // A preferable solution to the general problem is to figure out the right 18204 // places to insert EMMS. This qualifies as a quick hack. 18205 18206 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 18207 if (VT.getSizeInBits() != 64) 18208 return SDValue(); 18209 18210 const Function *F = DAG.getMachineFunction().getFunction(); 18211 bool NoImplicitFloatOps = F->getAttributes(). 18212 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 18213 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 18214 && Subtarget->hasSSE2(); 18215 if ((VT.isVector() || 18216 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 18217 isa<LoadSDNode>(St->getValue()) && 18218 !cast<LoadSDNode>(St->getValue())->isVolatile() && 18219 St->getChain().hasOneUse() && !St->isVolatile()) { 18220 SDNode* LdVal = St->getValue().getNode(); 18221 LoadSDNode *Ld = 0; 18222 int TokenFactorIndex = -1; 18223 SmallVector<SDValue, 8> Ops; 18224 SDNode* ChainVal = St->getChain().getNode(); 18225 // Must be a store of a load. We currently handle two cases: the load 18226 // is a direct child, and it's under an intervening TokenFactor. It is 18227 // possible to dig deeper under nested TokenFactors. 18228 if (ChainVal == LdVal) 18229 Ld = cast<LoadSDNode>(St->getChain()); 18230 else if (St->getValue().hasOneUse() && 18231 ChainVal->getOpcode() == ISD::TokenFactor) { 18232 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 18233 if (ChainVal->getOperand(i).getNode() == LdVal) { 18234 TokenFactorIndex = i; 18235 Ld = cast<LoadSDNode>(St->getValue()); 18236 } else 18237 Ops.push_back(ChainVal->getOperand(i)); 18238 } 18239 } 18240 18241 if (!Ld || !ISD::isNormalLoad(Ld)) 18242 return SDValue(); 18243 18244 // If this is not the MMX case, i.e. we are just turning i64 load/store 18245 // into f64 load/store, avoid the transformation if there are multiple 18246 // uses of the loaded value. 18247 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 18248 return SDValue(); 18249 18250 SDLoc LdDL(Ld); 18251 SDLoc StDL(N); 18252 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 18253 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 18254 // pair instead. 18255 if (Subtarget->is64Bit() || F64IsLegal) { 18256 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 18257 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 18258 Ld->getPointerInfo(), Ld->isVolatile(), 18259 Ld->isNonTemporal(), Ld->isInvariant(), 18260 Ld->getAlignment()); 18261 SDValue NewChain = NewLd.getValue(1); 18262 if (TokenFactorIndex != -1) { 18263 Ops.push_back(NewChain); 18264 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 18265 Ops.size()); 18266 } 18267 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 18268 St->getPointerInfo(), 18269 St->isVolatile(), St->isNonTemporal(), 18270 St->getAlignment()); 18271 } 18272 18273 // Otherwise, lower to two pairs of 32-bit loads / stores. 18274 SDValue LoAddr = Ld->getBasePtr(); 18275 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 18276 DAG.getConstant(4, MVT::i32)); 18277 18278 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 18279 Ld->getPointerInfo(), 18280 Ld->isVolatile(), Ld->isNonTemporal(), 18281 Ld->isInvariant(), Ld->getAlignment()); 18282 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 18283 Ld->getPointerInfo().getWithOffset(4), 18284 Ld->isVolatile(), Ld->isNonTemporal(), 18285 Ld->isInvariant(), 18286 MinAlign(Ld->getAlignment(), 4)); 18287 18288 SDValue NewChain = LoLd.getValue(1); 18289 if (TokenFactorIndex != -1) { 18290 Ops.push_back(LoLd); 18291 Ops.push_back(HiLd); 18292 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 18293 Ops.size()); 18294 } 18295 18296 LoAddr = St->getBasePtr(); 18297 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 18298 DAG.getConstant(4, MVT::i32)); 18299 18300 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 18301 St->getPointerInfo(), 18302 St->isVolatile(), St->isNonTemporal(), 18303 St->getAlignment()); 18304 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 18305 St->getPointerInfo().getWithOffset(4), 18306 St->isVolatile(), 18307 St->isNonTemporal(), 18308 MinAlign(St->getAlignment(), 4)); 18309 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 18310 } 18311 return SDValue(); 18312} 18313 18314/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 18315/// and return the operands for the horizontal operation in LHS and RHS. A 18316/// horizontal operation performs the binary operation on successive elements 18317/// of its first operand, then on successive elements of its second operand, 18318/// returning the resulting values in a vector. For example, if 18319/// A = < float a0, float a1, float a2, float a3 > 18320/// and 18321/// B = < float b0, float b1, float b2, float b3 > 18322/// then the result of doing a horizontal operation on A and B is 18323/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 18324/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 18325/// A horizontal-op B, for some already available A and B, and if so then LHS is 18326/// set to A, RHS to B, and the routine returns 'true'. 18327/// Note that the binary operation should have the property that if one of the 18328/// operands is UNDEF then the result is UNDEF. 18329static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 18330 // Look for the following pattern: if 18331 // A = < float a0, float a1, float a2, float a3 > 18332 // B = < float b0, float b1, float b2, float b3 > 18333 // and 18334 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 18335 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 18336 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 18337 // which is A horizontal-op B. 18338 18339 // At least one of the operands should be a vector shuffle. 18340 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 18341 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 18342 return false; 18343 18344 MVT VT = LHS.getSimpleValueType(); 18345 18346 assert((VT.is128BitVector() || VT.is256BitVector()) && 18347 "Unsupported vector type for horizontal add/sub"); 18348 18349 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 18350 // operate independently on 128-bit lanes. 18351 unsigned NumElts = VT.getVectorNumElements(); 18352 unsigned NumLanes = VT.getSizeInBits()/128; 18353 unsigned NumLaneElts = NumElts / NumLanes; 18354 assert((NumLaneElts % 2 == 0) && 18355 "Vector type should have an even number of elements in each lane"); 18356 unsigned HalfLaneElts = NumLaneElts/2; 18357 18358 // View LHS in the form 18359 // LHS = VECTOR_SHUFFLE A, B, LMask 18360 // If LHS is not a shuffle then pretend it is the shuffle 18361 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 18362 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 18363 // type VT. 18364 SDValue A, B; 18365 SmallVector<int, 16> LMask(NumElts); 18366 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 18367 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 18368 A = LHS.getOperand(0); 18369 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 18370 B = LHS.getOperand(1); 18371 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 18372 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 18373 } else { 18374 if (LHS.getOpcode() != ISD::UNDEF) 18375 A = LHS; 18376 for (unsigned i = 0; i != NumElts; ++i) 18377 LMask[i] = i; 18378 } 18379 18380 // Likewise, view RHS in the form 18381 // RHS = VECTOR_SHUFFLE C, D, RMask 18382 SDValue C, D; 18383 SmallVector<int, 16> RMask(NumElts); 18384 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 18385 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 18386 C = RHS.getOperand(0); 18387 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 18388 D = RHS.getOperand(1); 18389 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 18390 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 18391 } else { 18392 if (RHS.getOpcode() != ISD::UNDEF) 18393 C = RHS; 18394 for (unsigned i = 0; i != NumElts; ++i) 18395 RMask[i] = i; 18396 } 18397 18398 // Check that the shuffles are both shuffling the same vectors. 18399 if (!(A == C && B == D) && !(A == D && B == C)) 18400 return false; 18401 18402 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 18403 if (!A.getNode() && !B.getNode()) 18404 return false; 18405 18406 // If A and B occur in reverse order in RHS, then "swap" them (which means 18407 // rewriting the mask). 18408 if (A != C) 18409 CommuteVectorShuffleMask(RMask, NumElts); 18410 18411 // At this point LHS and RHS are equivalent to 18412 // LHS = VECTOR_SHUFFLE A, B, LMask 18413 // RHS = VECTOR_SHUFFLE A, B, RMask 18414 // Check that the masks correspond to performing a horizontal operation. 18415 for (unsigned l = 0; l != NumElts; l += NumLaneElts) { 18416 for (unsigned i = 0; i != NumLaneElts; ++i) { 18417 int LIdx = LMask[i+l], RIdx = RMask[i+l]; 18418 18419 // Ignore any UNDEF components. 18420 if (LIdx < 0 || RIdx < 0 || 18421 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 18422 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 18423 continue; 18424 18425 // Check that successive elements are being operated on. If not, this is 18426 // not a horizontal operation. 18427 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs 18428 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l; 18429 if (!(LIdx == Index && RIdx == Index + 1) && 18430 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 18431 return false; 18432 } 18433 } 18434 18435 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 18436 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 18437 return true; 18438} 18439 18440/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 18441static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 18442 const X86Subtarget *Subtarget) { 18443 EVT VT = N->getValueType(0); 18444 SDValue LHS = N->getOperand(0); 18445 SDValue RHS = N->getOperand(1); 18446 18447 // Try to synthesize horizontal adds from adds of shuffles. 18448 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 18449 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 18450 isHorizontalBinOp(LHS, RHS, true)) 18451 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS); 18452 return SDValue(); 18453} 18454 18455/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 18456static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 18457 const X86Subtarget *Subtarget) { 18458 EVT VT = N->getValueType(0); 18459 SDValue LHS = N->getOperand(0); 18460 SDValue RHS = N->getOperand(1); 18461 18462 // Try to synthesize horizontal subs from subs of shuffles. 18463 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 18464 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 18465 isHorizontalBinOp(LHS, RHS, false)) 18466 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS); 18467 return SDValue(); 18468} 18469 18470/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 18471/// X86ISD::FXOR nodes. 18472static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 18473 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 18474 // F[X]OR(0.0, x) -> x 18475 // F[X]OR(x, 0.0) -> x 18476 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 18477 if (C->getValueAPF().isPosZero()) 18478 return N->getOperand(1); 18479 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 18480 if (C->getValueAPF().isPosZero()) 18481 return N->getOperand(0); 18482 return SDValue(); 18483} 18484 18485/// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and 18486/// X86ISD::FMAX nodes. 18487static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) { 18488 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); 18489 18490 // Only perform optimizations if UnsafeMath is used. 18491 if (!DAG.getTarget().Options.UnsafeFPMath) 18492 return SDValue(); 18493 18494 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes 18495 // into FMINC and FMAXC, which are Commutative operations. 18496 unsigned NewOp = 0; 18497 switch (N->getOpcode()) { 18498 default: llvm_unreachable("unknown opcode"); 18499 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; 18500 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break; 18501 } 18502 18503 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0), 18504 N->getOperand(0), N->getOperand(1)); 18505} 18506 18507/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 18508static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 18509 // FAND(0.0, x) -> 0.0 18510 // FAND(x, 0.0) -> 0.0 18511 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 18512 if (C->getValueAPF().isPosZero()) 18513 return N->getOperand(0); 18514 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 18515 if (C->getValueAPF().isPosZero()) 18516 return N->getOperand(1); 18517 return SDValue(); 18518} 18519 18520/// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes 18521static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) { 18522 // FANDN(x, 0.0) -> 0.0 18523 // FANDN(0.0, x) -> x 18524 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 18525 if (C->getValueAPF().isPosZero()) 18526 return N->getOperand(1); 18527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 18528 if (C->getValueAPF().isPosZero()) 18529 return N->getOperand(1); 18530 return SDValue(); 18531} 18532 18533static SDValue PerformBTCombine(SDNode *N, 18534 SelectionDAG &DAG, 18535 TargetLowering::DAGCombinerInfo &DCI) { 18536 // BT ignores high bits in the bit index operand. 18537 SDValue Op1 = N->getOperand(1); 18538 if (Op1.hasOneUse()) { 18539 unsigned BitWidth = Op1.getValueSizeInBits(); 18540 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 18541 APInt KnownZero, KnownOne; 18542 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 18543 !DCI.isBeforeLegalizeOps()); 18544 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 18545 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 18546 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 18547 DCI.CommitTargetLoweringOpt(TLO); 18548 } 18549 return SDValue(); 18550} 18551 18552static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 18553 SDValue Op = N->getOperand(0); 18554 if (Op.getOpcode() == ISD::BITCAST) 18555 Op = Op.getOperand(0); 18556 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 18557 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 18558 VT.getVectorElementType().getSizeInBits() == 18559 OpVT.getVectorElementType().getSizeInBits()) { 18560 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); 18561 } 18562 return SDValue(); 18563} 18564 18565static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG, 18566 const X86Subtarget *Subtarget) { 18567 EVT VT = N->getValueType(0); 18568 if (!VT.isVector()) 18569 return SDValue(); 18570 18571 SDValue N0 = N->getOperand(0); 18572 SDValue N1 = N->getOperand(1); 18573 EVT ExtraVT = cast<VTSDNode>(N1)->getVT(); 18574 SDLoc dl(N); 18575 18576 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the 18577 // both SSE and AVX2 since there is no sign-extended shift right 18578 // operation on a vector with 64-bit elements. 18579 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> 18580 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) 18581 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND || 18582 N0.getOpcode() == ISD::SIGN_EXTEND)) { 18583 SDValue N00 = N0.getOperand(0); 18584 18585 // EXTLOAD has a better solution on AVX2, 18586 // it may be replaced with X86ISD::VSEXT node. 18587 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256()) 18588 if (!ISD::isNormalLoad(N00.getNode())) 18589 return SDValue(); 18590 18591 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) { 18592 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, 18593 N00, N1); 18594 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp); 18595 } 18596 } 18597 return SDValue(); 18598} 18599 18600static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 18601 TargetLowering::DAGCombinerInfo &DCI, 18602 const X86Subtarget *Subtarget) { 18603 if (!DCI.isBeforeLegalizeOps()) 18604 return SDValue(); 18605 18606 if (!Subtarget->hasFp256()) 18607 return SDValue(); 18608 18609 EVT VT = N->getValueType(0); 18610 if (VT.isVector() && VT.getSizeInBits() == 256) { 18611 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 18612 if (R.getNode()) 18613 return R; 18614 } 18615 18616 return SDValue(); 18617} 18618 18619static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, 18620 const X86Subtarget* Subtarget) { 18621 SDLoc dl(N); 18622 EVT VT = N->getValueType(0); 18623 18624 // Let legalize expand this if it isn't a legal type yet. 18625 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 18626 return SDValue(); 18627 18628 EVT ScalarVT = VT.getScalarType(); 18629 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || 18630 (!Subtarget->hasFMA() && !Subtarget->hasFMA4())) 18631 return SDValue(); 18632 18633 SDValue A = N->getOperand(0); 18634 SDValue B = N->getOperand(1); 18635 SDValue C = N->getOperand(2); 18636 18637 bool NegA = (A.getOpcode() == ISD::FNEG); 18638 bool NegB = (B.getOpcode() == ISD::FNEG); 18639 bool NegC = (C.getOpcode() == ISD::FNEG); 18640 18641 // Negative multiplication when NegA xor NegB 18642 bool NegMul = (NegA != NegB); 18643 if (NegA) 18644 A = A.getOperand(0); 18645 if (NegB) 18646 B = B.getOperand(0); 18647 if (NegC) 18648 C = C.getOperand(0); 18649 18650 unsigned Opcode; 18651 if (!NegMul) 18652 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; 18653 else 18654 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; 18655 18656 return DAG.getNode(Opcode, dl, VT, A, B, C); 18657} 18658 18659static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 18660 TargetLowering::DAGCombinerInfo &DCI, 18661 const X86Subtarget *Subtarget) { 18662 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 18663 // (and (i32 x86isd::setcc_carry), 1) 18664 // This eliminates the zext. This transformation is necessary because 18665 // ISD::SETCC is always legalized to i8. 18666 SDLoc dl(N); 18667 SDValue N0 = N->getOperand(0); 18668 EVT VT = N->getValueType(0); 18669 18670 if (N0.getOpcode() == ISD::AND && 18671 N0.hasOneUse() && 18672 N0.getOperand(0).hasOneUse()) { 18673 SDValue N00 = N0.getOperand(0); 18674 if (N00.getOpcode() == X86ISD::SETCC_CARRY) { 18675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 18676 if (!C || C->getZExtValue() != 1) 18677 return SDValue(); 18678 return DAG.getNode(ISD::AND, dl, VT, 18679 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 18680 N00.getOperand(0), N00.getOperand(1)), 18681 DAG.getConstant(1, VT)); 18682 } 18683 } 18684 18685 if (VT.is256BitVector()) { 18686 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 18687 if (R.getNode()) 18688 return R; 18689 } 18690 18691 return SDValue(); 18692} 18693 18694// Optimize x == -y --> x+y == 0 18695// x != -y --> x+y != 0 18696static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 18697 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 18698 SDValue LHS = N->getOperand(0); 18699 SDValue RHS = N->getOperand(1); 18700 18701 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 18702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 18703 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 18704 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), 18705 LHS.getValueType(), RHS, LHS.getOperand(1)); 18706 return DAG.getSetCC(SDLoc(N), N->getValueType(0), 18707 addV, DAG.getConstant(0, addV.getValueType()), CC); 18708 } 18709 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 18710 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 18711 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 18712 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), 18713 RHS.getValueType(), LHS, RHS.getOperand(1)); 18714 return DAG.getSetCC(SDLoc(N), N->getValueType(0), 18715 addV, DAG.getConstant(0, addV.getValueType()), CC); 18716 } 18717 return SDValue(); 18718} 18719 18720// Helper function of PerformSETCCCombine. It is to materialize "setb reg" 18721// as "sbb reg,reg", since it can be extended without zext and produces 18722// an all-ones bit which is more useful than 0/1 in some cases. 18723static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) { 18724 return DAG.getNode(ISD::AND, DL, MVT::i8, 18725 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 18726 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS), 18727 DAG.getConstant(1, MVT::i8)); 18728} 18729 18730// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 18731static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, 18732 TargetLowering::DAGCombinerInfo &DCI, 18733 const X86Subtarget *Subtarget) { 18734 SDLoc DL(N); 18735 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0)); 18736 SDValue EFLAGS = N->getOperand(1); 18737 18738 if (CC == X86::COND_A) { 18739 // Try to convert COND_A into COND_B in an attempt to facilitate 18740 // materializing "setb reg". 18741 // 18742 // Do not flip "e > c", where "c" is a constant, because Cmp instruction 18743 // cannot take an immediate as its first operand. 18744 // 18745 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() && 18746 EFLAGS.getValueType().isInteger() && 18747 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) { 18748 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS), 18749 EFLAGS.getNode()->getVTList(), 18750 EFLAGS.getOperand(1), EFLAGS.getOperand(0)); 18751 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo()); 18752 return MaterializeSETB(DL, NewEFLAGS, DAG); 18753 } 18754 } 18755 18756 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 18757 // a zext and produces an all-ones bit which is more useful than 0/1 in some 18758 // cases. 18759 if (CC == X86::COND_B) 18760 return MaterializeSETB(DL, EFLAGS, DAG); 18761 18762 SDValue Flags; 18763 18764 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 18765 if (Flags.getNode()) { 18766 SDValue Cond = DAG.getConstant(CC, MVT::i8); 18767 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); 18768 } 18769 18770 return SDValue(); 18771} 18772 18773// Optimize branch condition evaluation. 18774// 18775static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, 18776 TargetLowering::DAGCombinerInfo &DCI, 18777 const X86Subtarget *Subtarget) { 18778 SDLoc DL(N); 18779 SDValue Chain = N->getOperand(0); 18780 SDValue Dest = N->getOperand(1); 18781 SDValue EFLAGS = N->getOperand(3); 18782 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2)); 18783 18784 SDValue Flags; 18785 18786 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 18787 if (Flags.getNode()) { 18788 SDValue Cond = DAG.getConstant(CC, MVT::i8); 18789 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond, 18790 Flags); 18791 } 18792 18793 return SDValue(); 18794} 18795 18796static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 18797 const X86TargetLowering *XTLI) { 18798 SDValue Op0 = N->getOperand(0); 18799 EVT InVT = Op0->getValueType(0); 18800 18801 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 18802 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 18803 SDLoc dl(N); 18804 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 18805 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 18806 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 18807 } 18808 18809 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 18810 // a 32-bit target where SSE doesn't support i64->FP operations. 18811 if (Op0.getOpcode() == ISD::LOAD) { 18812 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 18813 EVT VT = Ld->getValueType(0); 18814 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 18815 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 18816 !XTLI->getSubtarget()->is64Bit() && 18817 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 18818 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 18819 Ld->getChain(), Op0, DAG); 18820 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 18821 return FILDChain; 18822 } 18823 } 18824 return SDValue(); 18825} 18826 18827// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 18828static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 18829 X86TargetLowering::DAGCombinerInfo &DCI) { 18830 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 18831 // the result is either zero or one (depending on the input carry bit). 18832 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 18833 if (X86::isZeroNode(N->getOperand(0)) && 18834 X86::isZeroNode(N->getOperand(1)) && 18835 // We don't have a good way to replace an EFLAGS use, so only do this when 18836 // dead right now. 18837 SDValue(N, 1).use_empty()) { 18838 SDLoc DL(N); 18839 EVT VT = N->getValueType(0); 18840 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 18841 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 18842 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 18843 DAG.getConstant(X86::COND_B,MVT::i8), 18844 N->getOperand(2)), 18845 DAG.getConstant(1, VT)); 18846 return DCI.CombineTo(N, Res1, CarryOut); 18847 } 18848 18849 return SDValue(); 18850} 18851 18852// fold (add Y, (sete X, 0)) -> adc 0, Y 18853// (add Y, (setne X, 0)) -> sbb -1, Y 18854// (sub (sete X, 0), Y) -> sbb 0, Y 18855// (sub (setne X, 0), Y) -> adc -1, Y 18856static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 18857 SDLoc DL(N); 18858 18859 // Look through ZExts. 18860 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 18861 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 18862 return SDValue(); 18863 18864 SDValue SetCC = Ext.getOperand(0); 18865 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 18866 return SDValue(); 18867 18868 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 18869 if (CC != X86::COND_E && CC != X86::COND_NE) 18870 return SDValue(); 18871 18872 SDValue Cmp = SetCC.getOperand(1); 18873 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 18874 !X86::isZeroNode(Cmp.getOperand(1)) || 18875 !Cmp.getOperand(0).getValueType().isInteger()) 18876 return SDValue(); 18877 18878 SDValue CmpOp0 = Cmp.getOperand(0); 18879 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 18880 DAG.getConstant(1, CmpOp0.getValueType())); 18881 18882 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 18883 if (CC == X86::COND_NE) 18884 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 18885 DL, OtherVal.getValueType(), OtherVal, 18886 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 18887 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 18888 DL, OtherVal.getValueType(), OtherVal, 18889 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 18890} 18891 18892/// PerformADDCombine - Do target-specific dag combines on integer adds. 18893static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 18894 const X86Subtarget *Subtarget) { 18895 EVT VT = N->getValueType(0); 18896 SDValue Op0 = N->getOperand(0); 18897 SDValue Op1 = N->getOperand(1); 18898 18899 // Try to synthesize horizontal adds from adds of shuffles. 18900 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 18901 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 18902 isHorizontalBinOp(Op0, Op1, true)) 18903 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1); 18904 18905 return OptimizeConditionalInDecrement(N, DAG); 18906} 18907 18908static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 18909 const X86Subtarget *Subtarget) { 18910 SDValue Op0 = N->getOperand(0); 18911 SDValue Op1 = N->getOperand(1); 18912 18913 // X86 can't encode an immediate LHS of a sub. See if we can push the 18914 // negation into a preceding instruction. 18915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 18916 // If the RHS of the sub is a XOR with one use and a constant, invert the 18917 // immediate. Then add one to the LHS of the sub so we can turn 18918 // X-Y -> X+~Y+1, saving one register. 18919 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 18920 isa<ConstantSDNode>(Op1.getOperand(1))) { 18921 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 18922 EVT VT = Op0.getValueType(); 18923 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT, 18924 Op1.getOperand(0), 18925 DAG.getConstant(~XorC, VT)); 18926 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor, 18927 DAG.getConstant(C->getAPIntValue()+1, VT)); 18928 } 18929 } 18930 18931 // Try to synthesize horizontal adds from adds of shuffles. 18932 EVT VT = N->getValueType(0); 18933 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 18934 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 18935 isHorizontalBinOp(Op0, Op1, true)) 18936 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1); 18937 18938 return OptimizeConditionalInDecrement(N, DAG); 18939} 18940 18941/// performVZEXTCombine - Performs build vector combines 18942static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG, 18943 TargetLowering::DAGCombinerInfo &DCI, 18944 const X86Subtarget *Subtarget) { 18945 // (vzext (bitcast (vzext (x)) -> (vzext x) 18946 SDValue In = N->getOperand(0); 18947 while (In.getOpcode() == ISD::BITCAST) 18948 In = In.getOperand(0); 18949 18950 if (In.getOpcode() != X86ISD::VZEXT) 18951 return SDValue(); 18952 18953 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0), 18954 In.getOperand(0)); 18955} 18956 18957SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 18958 DAGCombinerInfo &DCI) const { 18959 SelectionDAG &DAG = DCI.DAG; 18960 switch (N->getOpcode()) { 18961 default: break; 18962 case ISD::EXTRACT_VECTOR_ELT: 18963 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 18964 case ISD::VSELECT: 18965 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 18966 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); 18967 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 18968 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 18969 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 18970 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 18971 case ISD::SHL: 18972 case ISD::SRA: 18973 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 18974 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 18975 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 18976 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 18977 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); 18978 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 18979 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 18980 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 18981 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 18982 case X86ISD::FXOR: 18983 case X86ISD::FOR: return PerformFORCombine(N, DAG); 18984 case X86ISD::FMIN: 18985 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG); 18986 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 18987 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG); 18988 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 18989 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 18990 case ISD::ANY_EXTEND: 18991 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 18992 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 18993 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget); 18994 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget); 18995 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 18996 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); 18997 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); 18998 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget); 18999 case X86ISD::SHUFP: // Handle all target specific shuffles 19000 case X86ISD::PALIGNR: 19001 case X86ISD::UNPCKH: 19002 case X86ISD::UNPCKL: 19003 case X86ISD::MOVHLPS: 19004 case X86ISD::MOVLHPS: 19005 case X86ISD::PSHUFD: 19006 case X86ISD::PSHUFHW: 19007 case X86ISD::PSHUFLW: 19008 case X86ISD::MOVSS: 19009 case X86ISD::MOVSD: 19010 case X86ISD::VPERMILP: 19011 case X86ISD::VPERM2X128: 19012 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 19013 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget); 19014 } 19015 19016 return SDValue(); 19017} 19018 19019/// isTypeDesirableForOp - Return true if the target has native support for 19020/// the specified value type and it is 'desirable' to use the type for the 19021/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 19022/// instruction encodings are longer and some i16 instructions are slow. 19023bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 19024 if (!isTypeLegal(VT)) 19025 return false; 19026 if (VT != MVT::i16) 19027 return true; 19028 19029 switch (Opc) { 19030 default: 19031 return true; 19032 case ISD::LOAD: 19033 case ISD::SIGN_EXTEND: 19034 case ISD::ZERO_EXTEND: 19035 case ISD::ANY_EXTEND: 19036 case ISD::SHL: 19037 case ISD::SRL: 19038 case ISD::SUB: 19039 case ISD::ADD: 19040 case ISD::MUL: 19041 case ISD::AND: 19042 case ISD::OR: 19043 case ISD::XOR: 19044 return false; 19045 } 19046} 19047 19048/// IsDesirableToPromoteOp - This method query the target whether it is 19049/// beneficial for dag combiner to promote the specified node. If true, it 19050/// should return the desired promotion type by reference. 19051bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 19052 EVT VT = Op.getValueType(); 19053 if (VT != MVT::i16) 19054 return false; 19055 19056 bool Promote = false; 19057 bool Commute = false; 19058 switch (Op.getOpcode()) { 19059 default: break; 19060 case ISD::LOAD: { 19061 LoadSDNode *LD = cast<LoadSDNode>(Op); 19062 // If the non-extending load has a single use and it's not live out, then it 19063 // might be folded. 19064 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 19065 Op.hasOneUse()*/) { 19066 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 19067 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 19068 // The only case where we'd want to promote LOAD (rather then it being 19069 // promoted as an operand is when it's only use is liveout. 19070 if (UI->getOpcode() != ISD::CopyToReg) 19071 return false; 19072 } 19073 } 19074 Promote = true; 19075 break; 19076 } 19077 case ISD::SIGN_EXTEND: 19078 case ISD::ZERO_EXTEND: 19079 case ISD::ANY_EXTEND: 19080 Promote = true; 19081 break; 19082 case ISD::SHL: 19083 case ISD::SRL: { 19084 SDValue N0 = Op.getOperand(0); 19085 // Look out for (store (shl (load), x)). 19086 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 19087 return false; 19088 Promote = true; 19089 break; 19090 } 19091 case ISD::ADD: 19092 case ISD::MUL: 19093 case ISD::AND: 19094 case ISD::OR: 19095 case ISD::XOR: 19096 Commute = true; 19097 // fallthrough 19098 case ISD::SUB: { 19099 SDValue N0 = Op.getOperand(0); 19100 SDValue N1 = Op.getOperand(1); 19101 if (!Commute && MayFoldLoad(N1)) 19102 return false; 19103 // Avoid disabling potential load folding opportunities. 19104 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 19105 return false; 19106 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 19107 return false; 19108 Promote = true; 19109 } 19110 } 19111 19112 PVT = MVT::i32; 19113 return Promote; 19114} 19115 19116//===----------------------------------------------------------------------===// 19117// X86 Inline Assembly Support 19118//===----------------------------------------------------------------------===// 19119 19120namespace { 19121 // Helper to match a string separated by whitespace. 19122 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 19123 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 19124 19125 for (unsigned i = 0, e = args.size(); i != e; ++i) { 19126 StringRef piece(*args[i]); 19127 if (!s.startswith(piece)) // Check if the piece matches. 19128 return false; 19129 19130 s = s.substr(piece.size()); 19131 StringRef::size_type pos = s.find_first_not_of(" \t"); 19132 if (pos == 0) // We matched a prefix. 19133 return false; 19134 19135 s = s.substr(pos); 19136 } 19137 19138 return s.empty(); 19139 } 19140 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 19141} 19142 19143bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 19144 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 19145 19146 std::string AsmStr = IA->getAsmString(); 19147 19148 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 19149 if (!Ty || Ty->getBitWidth() % 16 != 0) 19150 return false; 19151 19152 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 19153 SmallVector<StringRef, 4> AsmPieces; 19154 SplitString(AsmStr, AsmPieces, ";\n"); 19155 19156 switch (AsmPieces.size()) { 19157 default: return false; 19158 case 1: 19159 // FIXME: this should verify that we are targeting a 486 or better. If not, 19160 // we will turn this bswap into something that will be lowered to logical 19161 // ops instead of emitting the bswap asm. For now, we don't support 486 or 19162 // lower so don't worry about this. 19163 // bswap $0 19164 if (matchAsm(AsmPieces[0], "bswap", "$0") || 19165 matchAsm(AsmPieces[0], "bswapl", "$0") || 19166 matchAsm(AsmPieces[0], "bswapq", "$0") || 19167 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 19168 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 19169 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 19170 // No need to check constraints, nothing other than the equivalent of 19171 // "=r,0" would be valid here. 19172 return IntrinsicLowering::LowerToByteSwap(CI); 19173 } 19174 19175 // rorw $$8, ${0:w} --> llvm.bswap.i16 19176 if (CI->getType()->isIntegerTy(16) && 19177 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 19178 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 19179 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 19180 AsmPieces.clear(); 19181 const std::string &ConstraintsStr = IA->getConstraintString(); 19182 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 19183 array_pod_sort(AsmPieces.begin(), AsmPieces.end()); 19184 if (AsmPieces.size() == 4 && 19185 AsmPieces[0] == "~{cc}" && 19186 AsmPieces[1] == "~{dirflag}" && 19187 AsmPieces[2] == "~{flags}" && 19188 AsmPieces[3] == "~{fpsr}") 19189 return IntrinsicLowering::LowerToByteSwap(CI); 19190 } 19191 break; 19192 case 3: 19193 if (CI->getType()->isIntegerTy(32) && 19194 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 19195 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 19196 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 19197 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 19198 AsmPieces.clear(); 19199 const std::string &ConstraintsStr = IA->getConstraintString(); 19200 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 19201 array_pod_sort(AsmPieces.begin(), AsmPieces.end()); 19202 if (AsmPieces.size() == 4 && 19203 AsmPieces[0] == "~{cc}" && 19204 AsmPieces[1] == "~{dirflag}" && 19205 AsmPieces[2] == "~{flags}" && 19206 AsmPieces[3] == "~{fpsr}") 19207 return IntrinsicLowering::LowerToByteSwap(CI); 19208 } 19209 19210 if (CI->getType()->isIntegerTy(64)) { 19211 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 19212 if (Constraints.size() >= 2 && 19213 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 19214 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 19215 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 19216 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 19217 matchAsm(AsmPieces[1], "bswap", "%edx") && 19218 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 19219 return IntrinsicLowering::LowerToByteSwap(CI); 19220 } 19221 } 19222 break; 19223 } 19224 return false; 19225} 19226 19227/// getConstraintType - Given a constraint letter, return the type of 19228/// constraint it is for this target. 19229X86TargetLowering::ConstraintType 19230X86TargetLowering::getConstraintType(const std::string &Constraint) const { 19231 if (Constraint.size() == 1) { 19232 switch (Constraint[0]) { 19233 case 'R': 19234 case 'q': 19235 case 'Q': 19236 case 'f': 19237 case 't': 19238 case 'u': 19239 case 'y': 19240 case 'x': 19241 case 'Y': 19242 case 'l': 19243 return C_RegisterClass; 19244 case 'a': 19245 case 'b': 19246 case 'c': 19247 case 'd': 19248 case 'S': 19249 case 'D': 19250 case 'A': 19251 return C_Register; 19252 case 'I': 19253 case 'J': 19254 case 'K': 19255 case 'L': 19256 case 'M': 19257 case 'N': 19258 case 'G': 19259 case 'C': 19260 case 'e': 19261 case 'Z': 19262 return C_Other; 19263 default: 19264 break; 19265 } 19266 } 19267 return TargetLowering::getConstraintType(Constraint); 19268} 19269 19270/// Examine constraint type and operand type and determine a weight value. 19271/// This object must already have been set up with the operand type 19272/// and the current alternative constraint selected. 19273TargetLowering::ConstraintWeight 19274 X86TargetLowering::getSingleConstraintMatchWeight( 19275 AsmOperandInfo &info, const char *constraint) const { 19276 ConstraintWeight weight = CW_Invalid; 19277 Value *CallOperandVal = info.CallOperandVal; 19278 // If we don't have a value, we can't do a match, 19279 // but allow it at the lowest weight. 19280 if (CallOperandVal == NULL) 19281 return CW_Default; 19282 Type *type = CallOperandVal->getType(); 19283 // Look at the constraint type. 19284 switch (*constraint) { 19285 default: 19286 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 19287 case 'R': 19288 case 'q': 19289 case 'Q': 19290 case 'a': 19291 case 'b': 19292 case 'c': 19293 case 'd': 19294 case 'S': 19295 case 'D': 19296 case 'A': 19297 if (CallOperandVal->getType()->isIntegerTy()) 19298 weight = CW_SpecificReg; 19299 break; 19300 case 'f': 19301 case 't': 19302 case 'u': 19303 if (type->isFloatingPointTy()) 19304 weight = CW_SpecificReg; 19305 break; 19306 case 'y': 19307 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 19308 weight = CW_SpecificReg; 19309 break; 19310 case 'x': 19311 case 'Y': 19312 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 19313 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256())) 19314 weight = CW_Register; 19315 break; 19316 case 'I': 19317 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 19318 if (C->getZExtValue() <= 31) 19319 weight = CW_Constant; 19320 } 19321 break; 19322 case 'J': 19323 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19324 if (C->getZExtValue() <= 63) 19325 weight = CW_Constant; 19326 } 19327 break; 19328 case 'K': 19329 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19330 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 19331 weight = CW_Constant; 19332 } 19333 break; 19334 case 'L': 19335 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19336 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 19337 weight = CW_Constant; 19338 } 19339 break; 19340 case 'M': 19341 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19342 if (C->getZExtValue() <= 3) 19343 weight = CW_Constant; 19344 } 19345 break; 19346 case 'N': 19347 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19348 if (C->getZExtValue() <= 0xff) 19349 weight = CW_Constant; 19350 } 19351 break; 19352 case 'G': 19353 case 'C': 19354 if (dyn_cast<ConstantFP>(CallOperandVal)) { 19355 weight = CW_Constant; 19356 } 19357 break; 19358 case 'e': 19359 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19360 if ((C->getSExtValue() >= -0x80000000LL) && 19361 (C->getSExtValue() <= 0x7fffffffLL)) 19362 weight = CW_Constant; 19363 } 19364 break; 19365 case 'Z': 19366 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 19367 if (C->getZExtValue() <= 0xffffffff) 19368 weight = CW_Constant; 19369 } 19370 break; 19371 } 19372 return weight; 19373} 19374 19375/// LowerXConstraint - try to replace an X constraint, which matches anything, 19376/// with another that has more specific requirements based on the type of the 19377/// corresponding operand. 19378const char *X86TargetLowering:: 19379LowerXConstraint(EVT ConstraintVT) const { 19380 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 19381 // 'f' like normal targets. 19382 if (ConstraintVT.isFloatingPoint()) { 19383 if (Subtarget->hasSSE2()) 19384 return "Y"; 19385 if (Subtarget->hasSSE1()) 19386 return "x"; 19387 } 19388 19389 return TargetLowering::LowerXConstraint(ConstraintVT); 19390} 19391 19392/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 19393/// vector. If it is invalid, don't add anything to Ops. 19394void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 19395 std::string &Constraint, 19396 std::vector<SDValue>&Ops, 19397 SelectionDAG &DAG) const { 19398 SDValue Result(0, 0); 19399 19400 // Only support length 1 constraints for now. 19401 if (Constraint.length() > 1) return; 19402 19403 char ConstraintLetter = Constraint[0]; 19404 switch (ConstraintLetter) { 19405 default: break; 19406 case 'I': 19407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19408 if (C->getZExtValue() <= 31) { 19409 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 19410 break; 19411 } 19412 } 19413 return; 19414 case 'J': 19415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19416 if (C->getZExtValue() <= 63) { 19417 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 19418 break; 19419 } 19420 } 19421 return; 19422 case 'K': 19423 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19424 if (isInt<8>(C->getSExtValue())) { 19425 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 19426 break; 19427 } 19428 } 19429 return; 19430 case 'N': 19431 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19432 if (C->getZExtValue() <= 255) { 19433 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 19434 break; 19435 } 19436 } 19437 return; 19438 case 'e': { 19439 // 32-bit signed value 19440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19441 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 19442 C->getSExtValue())) { 19443 // Widen to 64 bits here to get it sign extended. 19444 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 19445 break; 19446 } 19447 // FIXME gcc accepts some relocatable values here too, but only in certain 19448 // memory models; it's complicated. 19449 } 19450 return; 19451 } 19452 case 'Z': { 19453 // 32-bit unsigned value 19454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 19455 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 19456 C->getZExtValue())) { 19457 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 19458 break; 19459 } 19460 } 19461 // FIXME gcc accepts some relocatable values here too, but only in certain 19462 // memory models; it's complicated. 19463 return; 19464 } 19465 case 'i': { 19466 // Literal immediates are always ok. 19467 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 19468 // Widen to 64 bits here to get it sign extended. 19469 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 19470 break; 19471 } 19472 19473 // In any sort of PIC mode addresses need to be computed at runtime by 19474 // adding in a register or some sort of table lookup. These can't 19475 // be used as immediates. 19476 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 19477 return; 19478 19479 // If we are in non-pic codegen mode, we allow the address of a global (with 19480 // an optional displacement) to be used with 'i'. 19481 GlobalAddressSDNode *GA = 0; 19482 int64_t Offset = 0; 19483 19484 // Match either (GA), (GA+C), (GA+C1+C2), etc. 19485 while (1) { 19486 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 19487 Offset += GA->getOffset(); 19488 break; 19489 } else if (Op.getOpcode() == ISD::ADD) { 19490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 19491 Offset += C->getZExtValue(); 19492 Op = Op.getOperand(0); 19493 continue; 19494 } 19495 } else if (Op.getOpcode() == ISD::SUB) { 19496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 19497 Offset += -C->getZExtValue(); 19498 Op = Op.getOperand(0); 19499 continue; 19500 } 19501 } 19502 19503 // Otherwise, this isn't something we can handle, reject it. 19504 return; 19505 } 19506 19507 const GlobalValue *GV = GA->getGlobal(); 19508 // If we require an extra load to get this address, as in PIC mode, we 19509 // can't accept it. 19510 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 19511 getTargetMachine()))) 19512 return; 19513 19514 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), 19515 GA->getValueType(0), Offset); 19516 break; 19517 } 19518 } 19519 19520 if (Result.getNode()) { 19521 Ops.push_back(Result); 19522 return; 19523 } 19524 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 19525} 19526 19527std::pair<unsigned, const TargetRegisterClass*> 19528X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 19529 MVT VT) const { 19530 // First, see if this is a constraint that directly corresponds to an LLVM 19531 // register class. 19532 if (Constraint.size() == 1) { 19533 // GCC Constraint Letters 19534 switch (Constraint[0]) { 19535 default: break; 19536 // TODO: Slight differences here in allocation order and leaving 19537 // RIP in the class. Do they matter any more here than they do 19538 // in the normal allocation? 19539 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 19540 if (Subtarget->is64Bit()) { 19541 if (VT == MVT::i32 || VT == MVT::f32) 19542 return std::make_pair(0U, &X86::GR32RegClass); 19543 if (VT == MVT::i16) 19544 return std::make_pair(0U, &X86::GR16RegClass); 19545 if (VT == MVT::i8 || VT == MVT::i1) 19546 return std::make_pair(0U, &X86::GR8RegClass); 19547 if (VT == MVT::i64 || VT == MVT::f64) 19548 return std::make_pair(0U, &X86::GR64RegClass); 19549 break; 19550 } 19551 // 32-bit fallthrough 19552 case 'Q': // Q_REGS 19553 if (VT == MVT::i32 || VT == MVT::f32) 19554 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 19555 if (VT == MVT::i16) 19556 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 19557 if (VT == MVT::i8 || VT == MVT::i1) 19558 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 19559 if (VT == MVT::i64) 19560 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 19561 break; 19562 case 'r': // GENERAL_REGS 19563 case 'l': // INDEX_REGS 19564 if (VT == MVT::i8 || VT == MVT::i1) 19565 return std::make_pair(0U, &X86::GR8RegClass); 19566 if (VT == MVT::i16) 19567 return std::make_pair(0U, &X86::GR16RegClass); 19568 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 19569 return std::make_pair(0U, &X86::GR32RegClass); 19570 return std::make_pair(0U, &X86::GR64RegClass); 19571 case 'R': // LEGACY_REGS 19572 if (VT == MVT::i8 || VT == MVT::i1) 19573 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 19574 if (VT == MVT::i16) 19575 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 19576 if (VT == MVT::i32 || !Subtarget->is64Bit()) 19577 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 19578 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 19579 case 'f': // FP Stack registers. 19580 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 19581 // value to the correct fpstack register class. 19582 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 19583 return std::make_pair(0U, &X86::RFP32RegClass); 19584 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 19585 return std::make_pair(0U, &X86::RFP64RegClass); 19586 return std::make_pair(0U, &X86::RFP80RegClass); 19587 case 'y': // MMX_REGS if MMX allowed. 19588 if (!Subtarget->hasMMX()) break; 19589 return std::make_pair(0U, &X86::VR64RegClass); 19590 case 'Y': // SSE_REGS if SSE2 allowed 19591 if (!Subtarget->hasSSE2()) break; 19592 // FALL THROUGH. 19593 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 19594 if (!Subtarget->hasSSE1()) break; 19595 19596 switch (VT.SimpleTy) { 19597 default: break; 19598 // Scalar SSE types. 19599 case MVT::f32: 19600 case MVT::i32: 19601 return std::make_pair(0U, &X86::FR32RegClass); 19602 case MVT::f64: 19603 case MVT::i64: 19604 return std::make_pair(0U, &X86::FR64RegClass); 19605 // Vector types. 19606 case MVT::v16i8: 19607 case MVT::v8i16: 19608 case MVT::v4i32: 19609 case MVT::v2i64: 19610 case MVT::v4f32: 19611 case MVT::v2f64: 19612 return std::make_pair(0U, &X86::VR128RegClass); 19613 // AVX types. 19614 case MVT::v32i8: 19615 case MVT::v16i16: 19616 case MVT::v8i32: 19617 case MVT::v4i64: 19618 case MVT::v8f32: 19619 case MVT::v4f64: 19620 return std::make_pair(0U, &X86::VR256RegClass); 19621 case MVT::v8f64: 19622 case MVT::v16f32: 19623 case MVT::v16i32: 19624 case MVT::v8i64: 19625 return std::make_pair(0U, &X86::VR512RegClass); 19626 } 19627 break; 19628 } 19629 } 19630 19631 // Use the default implementation in TargetLowering to convert the register 19632 // constraint into a member of a register class. 19633 std::pair<unsigned, const TargetRegisterClass*> Res; 19634 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 19635 19636 // Not found as a standard register? 19637 if (Res.second == 0) { 19638 // Map st(0) -> st(7) -> ST0 19639 if (Constraint.size() == 7 && Constraint[0] == '{' && 19640 tolower(Constraint[1]) == 's' && 19641 tolower(Constraint[2]) == 't' && 19642 Constraint[3] == '(' && 19643 (Constraint[4] >= '0' && Constraint[4] <= '7') && 19644 Constraint[5] == ')' && 19645 Constraint[6] == '}') { 19646 19647 Res.first = X86::ST0+Constraint[4]-'0'; 19648 Res.second = &X86::RFP80RegClass; 19649 return Res; 19650 } 19651 19652 // GCC allows "st(0)" to be called just plain "st". 19653 if (StringRef("{st}").equals_lower(Constraint)) { 19654 Res.first = X86::ST0; 19655 Res.second = &X86::RFP80RegClass; 19656 return Res; 19657 } 19658 19659 // flags -> EFLAGS 19660 if (StringRef("{flags}").equals_lower(Constraint)) { 19661 Res.first = X86::EFLAGS; 19662 Res.second = &X86::CCRRegClass; 19663 return Res; 19664 } 19665 19666 // 'A' means EAX + EDX. 19667 if (Constraint == "A") { 19668 Res.first = X86::EAX; 19669 Res.second = &X86::GR32_ADRegClass; 19670 return Res; 19671 } 19672 return Res; 19673 } 19674 19675 // Otherwise, check to see if this is a register class of the wrong value 19676 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 19677 // turn into {ax},{dx}. 19678 if (Res.second->hasType(VT)) 19679 return Res; // Correct type already, nothing to do. 19680 19681 // All of the single-register GCC register classes map their values onto 19682 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 19683 // really want an 8-bit or 32-bit register, map to the appropriate register 19684 // class and return the appropriate register. 19685 if (Res.second == &X86::GR16RegClass) { 19686 if (VT == MVT::i8 || VT == MVT::i1) { 19687 unsigned DestReg = 0; 19688 switch (Res.first) { 19689 default: break; 19690 case X86::AX: DestReg = X86::AL; break; 19691 case X86::DX: DestReg = X86::DL; break; 19692 case X86::CX: DestReg = X86::CL; break; 19693 case X86::BX: DestReg = X86::BL; break; 19694 } 19695 if (DestReg) { 19696 Res.first = DestReg; 19697 Res.second = &X86::GR8RegClass; 19698 } 19699 } else if (VT == MVT::i32 || VT == MVT::f32) { 19700 unsigned DestReg = 0; 19701 switch (Res.first) { 19702 default: break; 19703 case X86::AX: DestReg = X86::EAX; break; 19704 case X86::DX: DestReg = X86::EDX; break; 19705 case X86::CX: DestReg = X86::ECX; break; 19706 case X86::BX: DestReg = X86::EBX; break; 19707 case X86::SI: DestReg = X86::ESI; break; 19708 case X86::DI: DestReg = X86::EDI; break; 19709 case X86::BP: DestReg = X86::EBP; break; 19710 case X86::SP: DestReg = X86::ESP; break; 19711 } 19712 if (DestReg) { 19713 Res.first = DestReg; 19714 Res.second = &X86::GR32RegClass; 19715 } 19716 } else if (VT == MVT::i64 || VT == MVT::f64) { 19717 unsigned DestReg = 0; 19718 switch (Res.first) { 19719 default: break; 19720 case X86::AX: DestReg = X86::RAX; break; 19721 case X86::DX: DestReg = X86::RDX; break; 19722 case X86::CX: DestReg = X86::RCX; break; 19723 case X86::BX: DestReg = X86::RBX; break; 19724 case X86::SI: DestReg = X86::RSI; break; 19725 case X86::DI: DestReg = X86::RDI; break; 19726 case X86::BP: DestReg = X86::RBP; break; 19727 case X86::SP: DestReg = X86::RSP; break; 19728 } 19729 if (DestReg) { 19730 Res.first = DestReg; 19731 Res.second = &X86::GR64RegClass; 19732 } 19733 } 19734 } else if (Res.second == &X86::FR32RegClass || 19735 Res.second == &X86::FR64RegClass || 19736 Res.second == &X86::VR128RegClass || 19737 Res.second == &X86::VR256RegClass || 19738 Res.second == &X86::FR32XRegClass || 19739 Res.second == &X86::FR64XRegClass || 19740 Res.second == &X86::VR128XRegClass || 19741 Res.second == &X86::VR256XRegClass || 19742 Res.second == &X86::VR512RegClass) { 19743 // Handle references to XMM physical registers that got mapped into the 19744 // wrong class. This can happen with constraints like {xmm0} where the 19745 // target independent register mapper will just pick the first match it can 19746 // find, ignoring the required type. 19747 19748 if (VT == MVT::f32 || VT == MVT::i32) 19749 Res.second = &X86::FR32RegClass; 19750 else if (VT == MVT::f64 || VT == MVT::i64) 19751 Res.second = &X86::FR64RegClass; 19752 else if (X86::VR128RegClass.hasType(VT)) 19753 Res.second = &X86::VR128RegClass; 19754 else if (X86::VR256RegClass.hasType(VT)) 19755 Res.second = &X86::VR256RegClass; 19756 else if (X86::VR512RegClass.hasType(VT)) 19757 Res.second = &X86::VR512RegClass; 19758 } 19759 19760 return Res; 19761} 19762