X86ISelLowering.cpp revision a9a568a79dbaf7315db863b4808d31ad9f5f91dc
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 66 SelectionDAG &DAG, DebugLoc dl) { 67 EVT VT = Vec.getValueType(); 68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 69 EVT ElVT = VT.getVectorElementType(); 70 unsigned Factor = VT.getSizeInBits()/128; 71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 72 VT.getVectorNumElements()/Factor); 73 74 // Extract from UNDEF is UNDEF. 75 if (Vec.getOpcode() == ISD::UNDEF) 76 return DAG.getUNDEF(ResultVT); 77 78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 79 // we can match to VEXTRACTF128. 80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 81 82 // This is the index of the first element of the 128-bit chunk 83 // we want. 84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 85 * ElemsPerChunk); 86 87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 89 VecIdx); 90 91 return Result; 92} 93 94/// Generate a DAG to put 128-bits into a vector > 128 bits. This 95/// sets things up to match to an AVX VINSERTF128 instruction or a 96/// simple superregister reference. Idx is an index in the 128 bits 97/// we want. It need not be aligned to a 128-bit bounday. That makes 98/// lowering INSERT_VECTOR_ELT operations easier. 99static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 100 unsigned IdxVal, SelectionDAG &DAG, 101 DebugLoc dl) { 102 EVT VT = Vec.getValueType(); 103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 104 105 EVT ElVT = VT.getVectorElementType(); 106 EVT ResultVT = Result.getValueType(); 107 108 // Insert the relevant 128 bits. 109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 110 111 // This is the index of the first element of the 128-bit chunk 112 // we want. 113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 114 * ElemsPerChunk); 115 116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 118 VecIdx); 119 return Result; 120} 121 122/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 123/// instructions. This is used because creating CONCAT_VECTOR nodes of 124/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 125/// large BUILD_VECTORS. 126static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 127 unsigned NumElems, SelectionDAG &DAG, 128 DebugLoc dl) { 129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 131} 132 133static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 135 bool is64Bit = Subtarget->is64Bit(); 136 137 if (Subtarget->isTargetEnvMacho()) { 138 if (is64Bit) 139 return new X8664_MachoTargetObjectFile(); 140 return new TargetLoweringObjectFileMachO(); 141 } 142 143 if (Subtarget->isTargetELF()) 144 return new TargetLoweringObjectFileELF(); 145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 146 return new TargetLoweringObjectFileCOFF(); 147 llvm_unreachable("unknown subtarget type"); 148} 149 150X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 151 : TargetLowering(TM, createTLOF(TM)) { 152 Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 X86ScalarSSEf64 = Subtarget->hasSSE2(); 154 X86ScalarSSEf32 = Subtarget->hasSSE1(); 155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 156 157 RegInfo = TM.getRegisterInfo(); 158 TD = getTargetData(); 159 160 // Set up the TargetLowering object. 161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 162 163 // X86 is weird, it always uses i8 for shift amounts and setcc results. 164 setBooleanContents(ZeroOrOneBooleanContent); 165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 167 168 // For 64-bit since we have so many registers use the ILP scheduler, for 169 // 32-bit code use the register pressure specific scheduling. 170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 171 if (Subtarget->is64Bit()) 172 setSchedulingPreference(Sched::ILP); 173 else if (Subtarget->isAtom()) 174 setSchedulingPreference(Sched::Hybrid); 175 else 176 setSchedulingPreference(Sched::RegPressure); 177 setStackPointerRegisterToSaveRestore(X86StackPtr); 178 179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 180 // Setup Windows compiler runtime calls. 181 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 183 setLibcallName(RTLIB::SREM_I64, "_allrem"); 184 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 185 setLibcallName(RTLIB::MUL_I64, "_allmul"); 186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 191 192 // The _ftol2 runtime function has an unusual calling conv, which 193 // is modeled by a special pseudo-instruction. 194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 198 } 199 200 if (Subtarget->isTargetDarwin()) { 201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 202 setUseUnderscoreSetJmp(false); 203 setUseUnderscoreLongJmp(false); 204 } else if (Subtarget->isTargetMingw()) { 205 // MS runtime is weird: it exports _setjmp, but longjmp! 206 setUseUnderscoreSetJmp(true); 207 setUseUnderscoreLongJmp(false); 208 } else { 209 setUseUnderscoreSetJmp(true); 210 setUseUnderscoreLongJmp(true); 211 } 212 213 // Set up the register classes. 214 addRegisterClass(MVT::i8, &X86::GR8RegClass); 215 addRegisterClass(MVT::i16, &X86::GR16RegClass); 216 addRegisterClass(MVT::i32, &X86::GR32RegClass); 217 if (Subtarget->is64Bit()) 218 addRegisterClass(MVT::i64, &X86::GR64RegClass); 219 220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 221 222 // We don't accept any truncstore of integer registers. 223 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 224 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 226 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 228 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 229 230 // SETOEQ and SETUNE require checking two conditions. 231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 237 238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 239 // operation. 240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 243 244 if (Subtarget->is64Bit()) { 245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 247 } else if (!TM.Options.UseSoftFloat) { 248 // We have an algorithm for SSE2->double, and we turn this into a 249 // 64-bit FILD followed by conditional FADD for other targets. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 // We have an algorithm for SSE2, and we turn this into a 64-bit 252 // FILD for other targets. 253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 254 } 255 256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 257 // this operation. 258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 260 261 if (!TM.Options.UseSoftFloat) { 262 // SSE has no i16 to fp conversion, only i32 263 if (X86ScalarSSEf32) { 264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 265 // f32 and f64 cases are Legal, f80 case is not 266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 267 } else { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 270 } 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 274 } 275 276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 277 // are Legal, f80 is custom lowered. 278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 280 281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 282 // this operation. 283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 285 286 if (X86ScalarSSEf32) { 287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 288 // f32 and f64 cases are Legal, f80 case is not 289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 290 } else { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 293 } 294 295 // Handle FP_TO_UINT by promoting the destination to a larger signed 296 // conversion. 297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 300 301 if (Subtarget->is64Bit()) { 302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 304 } else if (!TM.Options.UseSoftFloat) { 305 // Since AVX is a superset of SSE3, only check for SSE here. 306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 307 // Expand FP_TO_UINT into a select. 308 // FIXME: We would like to use a Custom expander here eventually to do 309 // the optimal thing for SSE vs. the default expansion in the legalizer. 310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 311 else 312 // With SSE3 we can use fisttpll to convert to a signed i64; without 313 // SSE, we're stuck with a fistpll. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 315 } 316 317 if (isTargetFTOL()) { 318 // Use the _ftol2 runtime function, which has a pseudo-instruction 319 // to handle its weird calling convention. 320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 321 } 322 323 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 324 if (!X86ScalarSSEf64) { 325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 327 if (Subtarget->is64Bit()) { 328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 329 // Without SSE, i64->f64 goes through memory. 330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 331 } 332 } 333 334 // Scalar integer divide and remainder are lowered to use operations that 335 // produce two results, to match the available instructions. This exposes 336 // the two-result form to trivial CSE, which is able to combine x/y and x%y 337 // into a single instruction. 338 // 339 // Scalar integer multiply-high is also lowered to use two-result 340 // operations, to match the available instructions. However, plain multiply 341 // (low) operations are left as Legal, as there are single-result 342 // instructions for this in x86. Using the two-result multiply instructions 343 // when both high and low results are needed must be arranged by dagcombine. 344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 345 MVT VT = IntVTs[i]; 346 setOperationAction(ISD::MULHS, VT, Expand); 347 setOperationAction(ISD::MULHU, VT, Expand); 348 setOperationAction(ISD::SDIV, VT, Expand); 349 setOperationAction(ISD::UDIV, VT, Expand); 350 setOperationAction(ISD::SREM, VT, Expand); 351 setOperationAction(ISD::UREM, VT, Expand); 352 353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 354 setOperationAction(ISD::ADDC, VT, Custom); 355 setOperationAction(ISD::ADDE, VT, Custom); 356 setOperationAction(ISD::SUBC, VT, Custom); 357 setOperationAction(ISD::SUBE, VT, Custom); 358 } 359 360 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 361 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 362 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 364 if (Subtarget->is64Bit()) 365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 370 setOperationAction(ISD::FREM , MVT::f32 , Expand); 371 setOperationAction(ISD::FREM , MVT::f64 , Expand); 372 setOperationAction(ISD::FREM , MVT::f80 , Expand); 373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 374 375 // Promote the i8 variants and force them on up to i32 which has a shorter 376 // encoding. 377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 381 if (Subtarget->hasBMI()) { 382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 384 if (Subtarget->is64Bit()) 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 386 } else { 387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 389 if (Subtarget->is64Bit()) 390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 391 } 392 393 if (Subtarget->hasLZCNT()) { 394 // When promoting the i8 variants, force them to i32 for a shorter 395 // encoding. 396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 402 if (Subtarget->is64Bit()) 403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 404 } else { 405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 411 if (Subtarget->is64Bit()) { 412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 414 } 415 } 416 417 if (Subtarget->hasPOPCNT()) { 418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 419 } else { 420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 423 if (Subtarget->is64Bit()) 424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 425 } 426 427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 429 430 // These should be promoted to a larger select which is supported. 431 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 432 // X86 wants to expand cmov itself. 433 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 434 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 435 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 436 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 437 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 438 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 439 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 440 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 441 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 442 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 443 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 444 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 445 if (Subtarget->is64Bit()) { 446 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 448 } 449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 450 451 // Darwin ABI issue. 452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 456 if (Subtarget->is64Bit()) 457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) { 461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 466 } 467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 471 if (Subtarget->is64Bit()) { 472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 475 } 476 477 if (Subtarget->hasSSE1()) 478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 479 480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 482 483 // On X86 and X86-64, atomic operations are lowered to locked instructions. 484 // Locked instructions, in turn, have implicit fence semantics (all memory 485 // operations are flushed before issuing the locked instruction, and they 486 // are not buffered), so we can fold away the common pattern of 487 // fence-atomic-fence. 488 setShouldFoldAtomicFences(true); 489 490 // Expand certain atomics 491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 492 MVT VT = IntVTs[i]; 493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 496 } 497 498 if (!Subtarget->is64Bit()) { 499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 507 } 508 509 if (Subtarget->hasCmpxchg16b()) { 510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 511 } 512 513 // FIXME - use subtarget debug flags 514 if (!Subtarget->isTargetDarwin() && 515 !Subtarget->isTargetELF() && 516 !Subtarget->isTargetCygMing()) { 517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 518 } 519 520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 524 if (Subtarget->is64Bit()) { 525 setExceptionPointerRegister(X86::RAX); 526 setExceptionSelectorRegister(X86::RDX); 527 } else { 528 setExceptionPointerRegister(X86::EAX); 529 setExceptionSelectorRegister(X86::EDX); 530 } 531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 533 534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 536 537 setOperationAction(ISD::TRAP, MVT::Other, Legal); 538 539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 540 setOperationAction(ISD::VASTART , MVT::Other, Custom); 541 setOperationAction(ISD::VAEND , MVT::Other, Expand); 542 if (Subtarget->is64Bit()) { 543 setOperationAction(ISD::VAARG , MVT::Other, Custom); 544 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 545 } else { 546 setOperationAction(ISD::VAARG , MVT::Other, Expand); 547 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 548 } 549 550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 552 553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 555 MVT::i64 : MVT::i32, Custom); 556 else if (TM.Options.EnableSegmentedStacks) 557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 558 MVT::i64 : MVT::i32, Custom); 559 else 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Expand); 562 563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 564 // f32 and f64 use SSE. 565 // Set up the FP register classes. 566 addRegisterClass(MVT::f32, &X86::FR32RegClass); 567 addRegisterClass(MVT::f64, &X86::FR64RegClass); 568 569 // Use ANDPD to simulate FABS. 570 setOperationAction(ISD::FABS , MVT::f64, Custom); 571 setOperationAction(ISD::FABS , MVT::f32, Custom); 572 573 // Use XORP to simulate FNEG. 574 setOperationAction(ISD::FNEG , MVT::f64, Custom); 575 setOperationAction(ISD::FNEG , MVT::f32, Custom); 576 577 // Use ANDPD and ORPD to simulate FCOPYSIGN. 578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 580 581 // Lower this to FGETSIGNx86 plus an AND. 582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 584 585 // We don't support sin/cos/fmod 586 setOperationAction(ISD::FSIN , MVT::f64, Expand); 587 setOperationAction(ISD::FCOS , MVT::f64, Expand); 588 setOperationAction(ISD::FSIN , MVT::f32, Expand); 589 setOperationAction(ISD::FCOS , MVT::f32, Expand); 590 591 // Expand FP immediates into loads from the stack, except for the special 592 // cases we handle. 593 addLegalFPImmediate(APFloat(+0.0)); // xorpd 594 addLegalFPImmediate(APFloat(+0.0f)); // xorps 595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 596 // Use SSE for f32, x87 for f64. 597 // Set up the FP register classes. 598 addRegisterClass(MVT::f32, &X86::FR32RegClass); 599 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 600 601 // Use ANDPS to simulate FABS. 602 setOperationAction(ISD::FABS , MVT::f32, Custom); 603 604 // Use XORP to simulate FNEG. 605 setOperationAction(ISD::FNEG , MVT::f32, Custom); 606 607 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 608 609 // Use ANDPS and ORPS to simulate FCOPYSIGN. 610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 612 613 // We don't support sin/cos/fmod 614 setOperationAction(ISD::FSIN , MVT::f32, Expand); 615 setOperationAction(ISD::FCOS , MVT::f32, Expand); 616 617 // Special cases we handle for FP constants. 618 addLegalFPImmediate(APFloat(+0.0f)); // xorps 619 addLegalFPImmediate(APFloat(+0.0)); // FLD0 620 addLegalFPImmediate(APFloat(+1.0)); // FLD1 621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 623 624 if (!TM.Options.UnsafeFPMath) { 625 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 626 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 627 } 628 } else if (!TM.Options.UseSoftFloat) { 629 // f32 and f64 in x87. 630 // Set up the FP register classes. 631 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 632 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 633 634 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 635 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 638 639 if (!TM.Options.UnsafeFPMath) { 640 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 641 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 642 } 643 addLegalFPImmediate(APFloat(+0.0)); // FLD0 644 addLegalFPImmediate(APFloat(+1.0)); // FLD1 645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 651 } 652 653 // We don't support FMA. 654 setOperationAction(ISD::FMA, MVT::f64, Expand); 655 setOperationAction(ISD::FMA, MVT::f32, Expand); 656 657 // Long double always uses X87. 658 if (!TM.Options.UseSoftFloat) { 659 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 660 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 662 { 663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 664 addLegalFPImmediate(TmpFlt); // FLD0 665 TmpFlt.changeSign(); 666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 667 668 bool ignored; 669 APFloat TmpFlt2(+1.0); 670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 671 &ignored); 672 addLegalFPImmediate(TmpFlt2); // FLD1 673 TmpFlt2.changeSign(); 674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 675 } 676 677 if (!TM.Options.UnsafeFPMath) { 678 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 679 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 680 } 681 682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 683 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 685 setOperationAction(ISD::FRINT, MVT::f80, Expand); 686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 687 setOperationAction(ISD::FMA, MVT::f80, Expand); 688 } 689 690 // Always use a library call for pow. 691 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 692 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 693 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 694 695 setOperationAction(ISD::FLOG, MVT::f80, Expand); 696 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 697 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 698 setOperationAction(ISD::FEXP, MVT::f80, Expand); 699 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 700 701 // First set operation action for all vector types to either promote 702 // (for widening) or expand (for scalarization). Then we will selectively 703 // turn on ones that can be effectively codegen'd. 704 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 705 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) { 706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 763 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 764 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 765 setTruncStoreAction((MVT::SimpleValueType)VT, 766 (MVT::SimpleValueType)InnerVT, Expand); 767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 770 } 771 772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 773 // with -msoft-float, disable use of MMX as well. 774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 776 // No operations on x86mmx supported, everything uses intrinsics. 777 } 778 779 // MMX-sized vectors (other than x86mmx) are expected to be expanded 780 // into smaller operations. 781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 785 setOperationAction(ISD::AND, MVT::v8i8, Expand); 786 setOperationAction(ISD::AND, MVT::v4i16, Expand); 787 setOperationAction(ISD::AND, MVT::v2i32, Expand); 788 setOperationAction(ISD::AND, MVT::v1i64, Expand); 789 setOperationAction(ISD::OR, MVT::v8i8, Expand); 790 setOperationAction(ISD::OR, MVT::v4i16, Expand); 791 setOperationAction(ISD::OR, MVT::v2i32, Expand); 792 setOperationAction(ISD::OR, MVT::v1i64, Expand); 793 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 794 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 795 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 796 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 810 811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 813 814 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 826 } 827 828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 830 831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 832 // registers cannot be used even for integer operations. 833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 837 838 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 839 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 840 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 841 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 842 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 843 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 844 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 845 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 846 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 847 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 848 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 854 855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 859 860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 865 866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 871 872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 874 EVT VT = (MVT::SimpleValueType)i; 875 // Do not attempt to custom lower non-power-of-2 vectors 876 if (!isPowerOf2_32(VT.getVectorNumElements())) 877 continue; 878 // Do not attempt to custom lower non-128-bit vectors 879 if (!VT.is128BitVector()) 880 continue; 881 setOperationAction(ISD::BUILD_VECTOR, 882 VT.getSimpleVT().SimpleTy, Custom); 883 setOperationAction(ISD::VECTOR_SHUFFLE, 884 VT.getSimpleVT().SimpleTy, Custom); 885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 886 VT.getSimpleVT().SimpleTy, Custom); 887 } 888 889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 895 896 if (Subtarget->is64Bit()) { 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 899 } 900 901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 902 for (int i = MVT::v16i8; i != MVT::v2i64; i++) { 903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 904 EVT VT = SVT; 905 906 // Do not attempt to promote non-128-bit vectors 907 if (!VT.is128BitVector()) 908 continue; 909 910 setOperationAction(ISD::AND, SVT, Promote); 911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 912 setOperationAction(ISD::OR, SVT, Promote); 913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 914 setOperationAction(ISD::XOR, SVT, Promote); 915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 916 setOperationAction(ISD::LOAD, SVT, Promote); 917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 918 setOperationAction(ISD::SELECT, SVT, Promote); 919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 920 } 921 922 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 923 924 // Custom lower v2i64 and v2f64 selects. 925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 929 930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 932 } 933 934 if (Subtarget->hasSSE41()) { 935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 936 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 938 setOperationAction(ISD::FRINT, MVT::f32, Legal); 939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 941 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 943 setOperationAction(ISD::FRINT, MVT::f64, Legal); 944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 945 946 // FIXME: Do we need to handle scalar-to-vector here? 947 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 948 949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 954 955 // i8 and i16 vectors are custom , because the source register and source 956 // source memory operand types are not the same width. f32 vectors are 957 // custom since the immediate controlling the insert encodes additional 958 // information. 959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 963 964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 968 969 // FIXME: these should be Legal but thats only for the case where 970 // the index is constant. For now custom expand to deal with that. 971 if (Subtarget->is64Bit()) { 972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 974 } 975 } 976 977 if (Subtarget->hasSSE2()) { 978 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 979 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 980 981 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 982 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 983 984 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 986 987 if (Subtarget->hasAVX2()) { 988 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 989 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 990 991 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 992 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 993 994 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 995 } else { 996 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 997 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 998 999 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1001 1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1003 } 1004 } 1005 1006 if (Subtarget->hasSSE42()) 1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1008 1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1016 1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1020 1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1027 1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1034 1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1038 1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1045 1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1048 1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1051 1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1059 1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1063 1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1068 1069 if (Subtarget->hasAVX2()) { 1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1074 1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1079 1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1083 // Don't lower v32i8 because there is no 128-bit byte mul 1084 1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1086 1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1089 1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1092 1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1094 } else { 1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1099 1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1104 1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1108 // Don't lower v32i8 because there is no 128-bit byte mul 1109 1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1112 1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1115 1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1117 } 1118 1119 // Custom lower several nodes for 256-bit types. 1120 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1121 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1123 EVT VT = SVT; 1124 1125 // Extract subvector is special because the value type 1126 // (result) is 128-bit but the source is 256-bit wide. 1127 if (VT.is128BitVector()) 1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1129 1130 // Do not attempt to custom lower other non-256-bit vectors 1131 if (!VT.is256BitVector()) 1132 continue; 1133 1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1140 } 1141 1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1143 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1145 EVT VT = SVT; 1146 1147 // Do not attempt to promote non-256-bit vectors 1148 if (!VT.is256BitVector()) 1149 continue; 1150 1151 setOperationAction(ISD::AND, SVT, Promote); 1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1153 setOperationAction(ISD::OR, SVT, Promote); 1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1155 setOperationAction(ISD::XOR, SVT, Promote); 1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1157 setOperationAction(ISD::LOAD, SVT, Promote); 1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1159 setOperationAction(ISD::SELECT, SVT, Promote); 1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1161 } 1162 } 1163 1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1165 // of this type with custom code. 1166 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1167 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1169 Custom); 1170 } 1171 1172 // We want to custom lower some of our intrinsics. 1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1174 1175 1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1177 // handle type legalization for these operations here. 1178 // 1179 // FIXME: We really should do custom legalization for addition and 1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1181 // than generic legalization for 64-bit multiplication-with-overflow, though. 1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1183 // Add/Sub/Mul with overflow operations are custom lowered. 1184 MVT VT = IntVTs[i]; 1185 setOperationAction(ISD::SADDO, VT, Custom); 1186 setOperationAction(ISD::UADDO, VT, Custom); 1187 setOperationAction(ISD::SSUBO, VT, Custom); 1188 setOperationAction(ISD::USUBO, VT, Custom); 1189 setOperationAction(ISD::SMULO, VT, Custom); 1190 setOperationAction(ISD::UMULO, VT, Custom); 1191 } 1192 1193 // There are no 8-bit 3-address imul/mul instructions 1194 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1195 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1196 1197 if (!Subtarget->is64Bit()) { 1198 // These libcalls are not available in 32-bit. 1199 setLibcallName(RTLIB::SHL_I128, 0); 1200 setLibcallName(RTLIB::SRL_I128, 0); 1201 setLibcallName(RTLIB::SRA_I128, 0); 1202 } 1203 1204 // We have target-specific dag combine patterns for the following nodes: 1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1207 setTargetDAGCombine(ISD::VSELECT); 1208 setTargetDAGCombine(ISD::SELECT); 1209 setTargetDAGCombine(ISD::SHL); 1210 setTargetDAGCombine(ISD::SRA); 1211 setTargetDAGCombine(ISD::SRL); 1212 setTargetDAGCombine(ISD::OR); 1213 setTargetDAGCombine(ISD::AND); 1214 setTargetDAGCombine(ISD::ADD); 1215 setTargetDAGCombine(ISD::FADD); 1216 setTargetDAGCombine(ISD::FSUB); 1217 setTargetDAGCombine(ISD::SUB); 1218 setTargetDAGCombine(ISD::LOAD); 1219 setTargetDAGCombine(ISD::STORE); 1220 setTargetDAGCombine(ISD::ZERO_EXTEND); 1221 setTargetDAGCombine(ISD::ANY_EXTEND); 1222 setTargetDAGCombine(ISD::SIGN_EXTEND); 1223 setTargetDAGCombine(ISD::TRUNCATE); 1224 setTargetDAGCombine(ISD::UINT_TO_FP); 1225 setTargetDAGCombine(ISD::SINT_TO_FP); 1226 setTargetDAGCombine(ISD::SETCC); 1227 setTargetDAGCombine(ISD::FP_TO_SINT); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279} 1280 1281/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1282/// function arguments in the caller parameter area. For X86, aggregates 1283/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1284/// are at 4-byte boundaries. 1285unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1286 if (Subtarget->is64Bit()) { 1287 // Max of 8 and alignment of type. 1288 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1289 if (TyAlign > 8) 1290 return TyAlign; 1291 return 8; 1292 } 1293 1294 unsigned Align = 4; 1295 if (Subtarget->hasSSE1()) 1296 getMaxByValAlign(Ty, Align); 1297 return Align; 1298} 1299 1300/// getOptimalMemOpType - Returns the target specific optimal type for load 1301/// and store operations as a result of memset, memcpy, and memmove 1302/// lowering. If DstAlign is zero that means it's safe to destination 1303/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1304/// means there isn't a need to check it against alignment requirement, 1305/// probably because the source does not need to be loaded. If 1306/// 'IsZeroVal' is true, that means it's safe to return a 1307/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1308/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1309/// constant so it does not need to be loaded. 1310/// It returns EVT::Other if the type should be determined using generic 1311/// target-independent logic. 1312EVT 1313X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1314 unsigned DstAlign, unsigned SrcAlign, 1315 bool IsZeroVal, 1316 bool MemcpyStrSrc, 1317 MachineFunction &MF) const { 1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1319 // linux. This is because the stack realignment code can't handle certain 1320 // cases like PR2962. This should be removed when PR2962 is fixed. 1321 const Function *F = MF.getFunction(); 1322 if (IsZeroVal && 1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1324 if (Size >= 16 && 1325 (Subtarget->isUnalignedMemAccessFast() || 1326 ((DstAlign == 0 || DstAlign >= 16) && 1327 (SrcAlign == 0 || SrcAlign >= 16))) && 1328 Subtarget->getStackAlignment() >= 16) { 1329 if (Subtarget->getStackAlignment() >= 32) { 1330 if (Subtarget->hasAVX2()) 1331 return MVT::v8i32; 1332 if (Subtarget->hasAVX()) 1333 return MVT::v8f32; 1334 } 1335 if (Subtarget->hasSSE2()) 1336 return MVT::v4i32; 1337 if (Subtarget->hasSSE1()) 1338 return MVT::v4f32; 1339 } else if (!MemcpyStrSrc && Size >= 8 && 1340 !Subtarget->is64Bit() && 1341 Subtarget->getStackAlignment() >= 8 && 1342 Subtarget->hasSSE2()) { 1343 // Do not use f64 to lower memcpy if source is string constant. It's 1344 // better to use i32 to avoid the loads. 1345 return MVT::f64; 1346 } 1347 } 1348 if (Subtarget->is64Bit() && Size >= 8) 1349 return MVT::i64; 1350 return MVT::i32; 1351} 1352 1353/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1354/// current function. The returned value is a member of the 1355/// MachineJumpTableInfo::JTEntryKind enum. 1356unsigned X86TargetLowering::getJumpTableEncoding() const { 1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1358 // symbol. 1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1360 Subtarget->isPICStyleGOT()) 1361 return MachineJumpTableInfo::EK_Custom32; 1362 1363 // Otherwise, use the normal jump table encoding heuristics. 1364 return TargetLowering::getJumpTableEncoding(); 1365} 1366 1367const MCExpr * 1368X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1369 const MachineBasicBlock *MBB, 1370 unsigned uid,MCContext &Ctx) const{ 1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1372 Subtarget->isPICStyleGOT()); 1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1374 // entries. 1375 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1376 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1377} 1378 1379/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1380/// jumptable. 1381SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1382 SelectionDAG &DAG) const { 1383 if (!Subtarget->is64Bit()) 1384 // This doesn't have DebugLoc associated with it, but is not really the 1385 // same as a Register. 1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1387 return Table; 1388} 1389 1390/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1391/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1392/// MCExpr. 1393const MCExpr *X86TargetLowering:: 1394getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1395 MCContext &Ctx) const { 1396 // X86-64 uses RIP relative addressing based on the jump table label. 1397 if (Subtarget->isPICStyleRIPRel()) 1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1399 1400 // Otherwise, the reference is relative to the PIC base. 1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1402} 1403 1404// FIXME: Why this routine is here? Move to RegInfo! 1405std::pair<const TargetRegisterClass*, uint8_t> 1406X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1407 const TargetRegisterClass *RRC = 0; 1408 uint8_t Cost = 1; 1409 switch (VT.getSimpleVT().SimpleTy) { 1410 default: 1411 return TargetLowering::findRepresentativeClass(VT); 1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1413 RRC = Subtarget->is64Bit() ? 1414 (const TargetRegisterClass*)&X86::GR64RegClass : 1415 (const TargetRegisterClass*)&X86::GR32RegClass; 1416 break; 1417 case MVT::x86mmx: 1418 RRC = &X86::VR64RegClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = &X86::VR128RegClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDValue TCChain = Chain; 1588 SDNode *Copy = *N->use_begin(); 1589 if (Copy->getOpcode() == ISD::CopyToReg) { 1590 // If the copy has a glue operand, we conservatively assume it isn't safe to 1591 // perform a tail call. 1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1593 return false; 1594 TCChain = Copy->getOperand(0); 1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1596 return false; 1597 1598 bool HasRet = false; 1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1600 UI != UE; ++UI) { 1601 if (UI->getOpcode() != X86ISD::RET_FLAG) 1602 return false; 1603 HasRet = true; 1604 } 1605 1606 if (!HasRet) 1607 return false; 1608 1609 Chain = TCChain; 1610 return true; 1611} 1612 1613EVT 1614X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1615 ISD::NodeType ExtendKind) const { 1616 MVT ReturnMVT; 1617 // TODO: Is this also valid on 32-bit? 1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1619 ReturnMVT = MVT::i8; 1620 else 1621 ReturnMVT = MVT::i32; 1622 1623 EVT MinVT = getRegisterType(Context, ReturnMVT); 1624 return VT.bitsLT(MinVT) ? MinVT : VT; 1625} 1626 1627/// LowerCallResult - Lower the result values of a call into the 1628/// appropriate copies out of appropriate physical registers. 1629/// 1630SDValue 1631X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1632 CallingConv::ID CallConv, bool isVarArg, 1633 const SmallVectorImpl<ISD::InputArg> &Ins, 1634 DebugLoc dl, SelectionDAG &DAG, 1635 SmallVectorImpl<SDValue> &InVals) const { 1636 1637 // Assign locations to each value returned by this call. 1638 SmallVector<CCValAssign, 16> RVLocs; 1639 bool Is64Bit = Subtarget->is64Bit(); 1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1641 getTargetMachine(), RVLocs, *DAG.getContext()); 1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1643 1644 // Copy all of the result registers out of their specified physreg. 1645 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1646 CCValAssign &VA = RVLocs[i]; 1647 EVT CopyVT = VA.getValVT(); 1648 1649 // If this is x86-64, and we disabled SSE, we can't return FP values 1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1652 report_fatal_error("SSE register return with SSE disabled"); 1653 } 1654 1655 SDValue Val; 1656 1657 // If this is a call to a function that returns an fp value on the floating 1658 // point stack, we must guarantee the the value is popped from the stack, so 1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1660 // if the return value is not used. We use the FpPOP_RETVAL instruction 1661 // instead. 1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1663 // If we prefer to use the value in xmm registers, copy it out as f80 and 1664 // use a truncate to move it from fp stack reg to xmm reg. 1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1666 SDValue Ops[] = { Chain, InFlag }; 1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1668 MVT::Other, MVT::Glue, Ops, 2), 1); 1669 Val = Chain.getValue(0); 1670 1671 // Round the f80 to the right size, which also moves it to the appropriate 1672 // xmm register. 1673 if (CopyVT != VA.getValVT()) 1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1675 // This truncation won't change the value. 1676 DAG.getIntPtrConstant(1)); 1677 } else { 1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1679 CopyVT, InFlag).getValue(1); 1680 Val = Chain.getValue(0); 1681 } 1682 InFlag = Chain.getValue(2); 1683 InVals.push_back(Val); 1684 } 1685 1686 return Chain; 1687} 1688 1689 1690//===----------------------------------------------------------------------===// 1691// C & StdCall & Fast Calling Convention implementation 1692//===----------------------------------------------------------------------===// 1693// StdCall calling convention seems to be standard for many Windows' API 1694// routines and around. It differs from C calling convention just a little: 1695// callee should clean up the stack, not caller. Symbols should be also 1696// decorated in some fancy way :) It doesn't support any vector arguments. 1697// For info on fast calling convention see Fast Calling Convention (tail call) 1698// implementation LowerX86_32FastCCCallTo. 1699 1700/// CallIsStructReturn - Determines whether a call uses struct return 1701/// semantics. 1702static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1703 if (Outs.empty()) 1704 return false; 1705 1706 return Outs[0].Flags.isSRet(); 1707} 1708 1709/// ArgsAreStructReturn - Determines whether a function uses struct 1710/// return semantics. 1711static bool 1712ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1713 if (Ins.empty()) 1714 return false; 1715 1716 return Ins[0].Flags.isSRet(); 1717} 1718 1719/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1720/// by "Src" to address "Dst" with size and alignment information specified by 1721/// the specific parameter attribute. The copy will be passed as a byval 1722/// function parameter. 1723static SDValue 1724CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1726 DebugLoc dl) { 1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1728 1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1730 /*isVolatile*/false, /*AlwaysInline=*/true, 1731 MachinePointerInfo(), MachinePointerInfo()); 1732} 1733 1734/// IsTailCallConvention - Return true if the calling convention is one that 1735/// supports tail call optimization. 1736static bool IsTailCallConvention(CallingConv::ID CC) { 1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1738} 1739 1740bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1742 return false; 1743 1744 CallSite CS(CI); 1745 CallingConv::ID CalleeCC = CS.getCallingConv(); 1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1747 return false; 1748 1749 return true; 1750} 1751 1752/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1753/// a tailcall target by changing its ABI. 1754static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1755 bool GuaranteedTailCallOpt) { 1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1757} 1758 1759SDValue 1760X86TargetLowering::LowerMemArgument(SDValue Chain, 1761 CallingConv::ID CallConv, 1762 const SmallVectorImpl<ISD::InputArg> &Ins, 1763 DebugLoc dl, SelectionDAG &DAG, 1764 const CCValAssign &VA, 1765 MachineFrameInfo *MFI, 1766 unsigned i) const { 1767 // Create the nodes corresponding to a load from this parameter slot. 1768 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1770 getTargetMachine().Options.GuaranteedTailCallOpt); 1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1772 EVT ValVT; 1773 1774 // If value is passed by pointer we have address passed instead of the value 1775 // itself. 1776 if (VA.getLocInfo() == CCValAssign::Indirect) 1777 ValVT = VA.getLocVT(); 1778 else 1779 ValVT = VA.getValVT(); 1780 1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1782 // changed with more analysis. 1783 // In case of tail call optimization mark all arguments mutable. Since they 1784 // could be overwritten by lowering of arguments in case of a tail call. 1785 if (Flags.isByVal()) { 1786 unsigned Bytes = Flags.getByValSize(); 1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1789 return DAG.getFrameIndex(FI, getPointerTy()); 1790 } else { 1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1792 VA.getLocMemOffset(), isImmutable); 1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1794 return DAG.getLoad(ValVT, dl, Chain, FIN, 1795 MachinePointerInfo::getFixedStack(FI), 1796 false, false, false, 0); 1797 } 1798} 1799 1800SDValue 1801X86TargetLowering::LowerFormalArguments(SDValue Chain, 1802 CallingConv::ID CallConv, 1803 bool isVarArg, 1804 const SmallVectorImpl<ISD::InputArg> &Ins, 1805 DebugLoc dl, 1806 SelectionDAG &DAG, 1807 SmallVectorImpl<SDValue> &InVals) 1808 const { 1809 MachineFunction &MF = DAG.getMachineFunction(); 1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1811 1812 const Function* Fn = MF.getFunction(); 1813 if (Fn->hasExternalLinkage() && 1814 Subtarget->isTargetCygMing() && 1815 Fn->getName() == "main") 1816 FuncInfo->setForceFramePointer(true); 1817 1818 MachineFrameInfo *MFI = MF.getFrameInfo(); 1819 bool Is64Bit = Subtarget->is64Bit(); 1820 bool IsWindows = Subtarget->isTargetWindows(); 1821 bool IsWin64 = Subtarget->isTargetWin64(); 1822 1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1824 "Var args not supported with calling convention fastcc or ghc"); 1825 1826 // Assign locations to all of the incoming arguments. 1827 SmallVector<CCValAssign, 16> ArgLocs; 1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1829 ArgLocs, *DAG.getContext()); 1830 1831 // Allocate shadow area for Win64 1832 if (IsWin64) { 1833 CCInfo.AllocateStack(32, 8); 1834 } 1835 1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1837 1838 unsigned LastVal = ~0U; 1839 SDValue ArgValue; 1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1841 CCValAssign &VA = ArgLocs[i]; 1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1843 // places. 1844 assert(VA.getValNo() != LastVal && 1845 "Don't support value assigned to multiple locs yet"); 1846 (void)LastVal; 1847 LastVal = VA.getValNo(); 1848 1849 if (VA.isRegLoc()) { 1850 EVT RegVT = VA.getLocVT(); 1851 const TargetRegisterClass *RC; 1852 if (RegVT == MVT::i32) 1853 RC = &X86::GR32RegClass; 1854 else if (Is64Bit && RegVT == MVT::i64) 1855 RC = &X86::GR64RegClass; 1856 else if (RegVT == MVT::f32) 1857 RC = &X86::FR32RegClass; 1858 else if (RegVT == MVT::f64) 1859 RC = &X86::FR64RegClass; 1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1861 RC = &X86::VR256RegClass; 1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1863 RC = &X86::VR128RegClass; 1864 else if (RegVT == MVT::x86mmx) 1865 RC = &X86::VR64RegClass; 1866 else 1867 llvm_unreachable("Unknown argument type!"); 1868 1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1871 1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1874 // right size. 1875 if (VA.getLocInfo() == CCValAssign::SExt) 1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1877 DAG.getValueType(VA.getValVT())); 1878 else if (VA.getLocInfo() == CCValAssign::ZExt) 1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1880 DAG.getValueType(VA.getValVT())); 1881 else if (VA.getLocInfo() == CCValAssign::BCvt) 1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1883 1884 if (VA.isExtInLoc()) { 1885 // Handle MMX values passed in XMM regs. 1886 if (RegVT.isVector()) { 1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1888 ArgValue); 1889 } else 1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1891 } 1892 } else { 1893 assert(VA.isMemLoc()); 1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1895 } 1896 1897 // If value is passed via pointer - do a load. 1898 if (VA.getLocInfo() == CCValAssign::Indirect) 1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1900 MachinePointerInfo(), false, false, false, 0); 1901 1902 InVals.push_back(ArgValue); 1903 } 1904 1905 // The x86-64 ABI for returning structs by value requires that we copy 1906 // the sret argument into %rax for the return. Save the argument into 1907 // a virtual register so that we can access it from the return points. 1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1910 unsigned Reg = FuncInfo->getSRetReturnReg(); 1911 if (!Reg) { 1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1913 FuncInfo->setSRetReturnReg(Reg); 1914 } 1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1917 } 1918 1919 unsigned StackSize = CCInfo.getNextStackOffset(); 1920 // Align stack specially for tail calls. 1921 if (FuncIsMadeTailCallSafe(CallConv, 1922 MF.getTarget().Options.GuaranteedTailCallOpt)) 1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1924 1925 // If the function takes variable number of arguments, make a frame index for 1926 // the start of the first vararg value... for expansion of llvm.va_start. 1927 if (isVarArg) { 1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1929 CallConv != CallingConv::X86_ThisCall)) { 1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1931 } 1932 if (Is64Bit) { 1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1934 1935 // FIXME: We should really autogenerate these arrays 1936 static const uint16_t GPR64ArgRegsWin64[] = { 1937 X86::RCX, X86::RDX, X86::R8, X86::R9 1938 }; 1939 static const uint16_t GPR64ArgRegs64Bit[] = { 1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1941 }; 1942 static const uint16_t XMMArgRegs64Bit[] = { 1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1945 }; 1946 const uint16_t *GPR64ArgRegs; 1947 unsigned NumXMMRegs = 0; 1948 1949 if (IsWin64) { 1950 // The XMM registers which might contain var arg parameters are shadowed 1951 // in their paired GPR. So we only need to save the GPR to their home 1952 // slots. 1953 TotalNumIntRegs = 4; 1954 GPR64ArgRegs = GPR64ArgRegsWin64; 1955 } else { 1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1957 GPR64ArgRegs = GPR64ArgRegs64Bit; 1958 1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1960 TotalNumXMMRegs); 1961 } 1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1963 TotalNumIntRegs); 1964 1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1967 "SSE register cannot be used when SSE is disabled!"); 1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1969 NoImplicitFloatOps) && 1970 "SSE register cannot be used when SSE is disabled!"); 1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1972 !Subtarget->hasSSE1()) 1973 // Kernel mode asks for SSE to be disabled, so don't push them 1974 // on the stack. 1975 TotalNumXMMRegs = 0; 1976 1977 if (IsWin64) { 1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1979 // Get to the caller-allocated home save location. Add 8 to account 1980 // for the return address. 1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1984 // Fixup to set vararg frame on shadow area (4 x i64). 1985 if (NumIntRegs < 4) 1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1987 } else { 1988 // For X86-64, if there are vararg parameters that are passed via 1989 // registers, then we must store them to their spots on the stack so 1990 // they may be loaded by deferencing the result of va_next. 1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1993 FuncInfo->setRegSaveFrameIndex( 1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1995 false)); 1996 } 1997 1998 // Store the integer parameter registers. 1999 SmallVector<SDValue, 8> MemOps; 2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2001 getPointerTy()); 2002 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2005 DAG.getIntPtrConstant(Offset)); 2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2007 &X86::GR64RegClass); 2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2009 SDValue Store = 2010 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2011 MachinePointerInfo::getFixedStack( 2012 FuncInfo->getRegSaveFrameIndex(), Offset), 2013 false, false, 0); 2014 MemOps.push_back(Store); 2015 Offset += 8; 2016 } 2017 2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2019 // Now store the XMM (fp + vector) parameter registers. 2020 SmallVector<SDValue, 11> SaveXMMOps; 2021 SaveXMMOps.push_back(Chain); 2022 2023 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2025 SaveXMMOps.push_back(ALVal); 2026 2027 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2028 FuncInfo->getRegSaveFrameIndex())); 2029 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2030 FuncInfo->getVarArgsFPOffset())); 2031 2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2034 &X86::VR128RegClass); 2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2036 SaveXMMOps.push_back(Val); 2037 } 2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2039 MVT::Other, 2040 &SaveXMMOps[0], SaveXMMOps.size())); 2041 } 2042 2043 if (!MemOps.empty()) 2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2045 &MemOps[0], MemOps.size()); 2046 } 2047 } 2048 2049 // Some CCs need callee pop. 2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2051 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2053 } else { 2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2055 // If this is an sret function, the return should pop the hidden pointer. 2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2057 ArgsAreStructReturn(Ins)) 2058 FuncInfo->setBytesToPopOnReturn(4); 2059 } 2060 2061 if (!Is64Bit) { 2062 // RegSaveFrameIndex is X86-64 only. 2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2064 if (CallConv == CallingConv::X86_FastCall || 2065 CallConv == CallingConv::X86_ThisCall) 2066 // fastcc functions can't have varargs. 2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2068 } 2069 2070 FuncInfo->setArgumentStackSize(StackSize); 2071 2072 return Chain; 2073} 2074 2075SDValue 2076X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2077 SDValue StackPtr, SDValue Arg, 2078 DebugLoc dl, SelectionDAG &DAG, 2079 const CCValAssign &VA, 2080 ISD::ArgFlagsTy Flags) const { 2081 unsigned LocMemOffset = VA.getLocMemOffset(); 2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2084 if (Flags.isByVal()) 2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2086 2087 return DAG.getStore(Chain, dl, Arg, PtrOff, 2088 MachinePointerInfo::getStack(LocMemOffset), 2089 false, false, 0); 2090} 2091 2092/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2093/// optimization is performed and it is required. 2094SDValue 2095X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2096 SDValue &OutRetAddr, SDValue Chain, 2097 bool IsTailCall, bool Is64Bit, 2098 int FPDiff, DebugLoc dl) const { 2099 // Adjust the Return address stack slot. 2100 EVT VT = getPointerTy(); 2101 OutRetAddr = getReturnAddressFrameIndex(DAG); 2102 2103 // Load the "old" Return address. 2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2105 false, false, false, 0); 2106 return SDValue(OutRetAddr.getNode(), 1); 2107} 2108 2109/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2110/// optimization is performed and it is required (FPDiff!=0). 2111static SDValue 2112EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2113 SDValue Chain, SDValue RetAddrFrIdx, 2114 bool Is64Bit, int FPDiff, DebugLoc dl) { 2115 // Store the return address to the appropriate stack slot. 2116 if (!FPDiff) return Chain; 2117 // Calculate the new stack slot for the return address. 2118 int SlotSize = Is64Bit ? 8 : 4; 2119 int NewReturnAddrFI = 2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2125 false, false, 0); 2126 return Chain; 2127} 2128 2129SDValue 2130X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2131 CallingConv::ID CallConv, bool isVarArg, 2132 bool doesNotRet, bool &isTailCall, 2133 const SmallVectorImpl<ISD::OutputArg> &Outs, 2134 const SmallVectorImpl<SDValue> &OutVals, 2135 const SmallVectorImpl<ISD::InputArg> &Ins, 2136 DebugLoc dl, SelectionDAG &DAG, 2137 SmallVectorImpl<SDValue> &InVals) const { 2138 MachineFunction &MF = DAG.getMachineFunction(); 2139 bool Is64Bit = Subtarget->is64Bit(); 2140 bool IsWin64 = Subtarget->isTargetWin64(); 2141 bool IsWindows = Subtarget->isTargetWindows(); 2142 bool IsStructRet = CallIsStructReturn(Outs); 2143 bool IsSibcall = false; 2144 2145 if (MF.getTarget().Options.DisableTailCalls) 2146 isTailCall = false; 2147 2148 if (isTailCall) { 2149 // Check if it's really possible to do a tail call. 2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2152 Outs, OutVals, Ins, DAG); 2153 2154 // Sibcalls are automatically detected tailcalls which do not require 2155 // ABI changes. 2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2157 IsSibcall = true; 2158 2159 if (isTailCall) 2160 ++NumTailCalls; 2161 } 2162 2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2164 "Var args not supported with calling convention fastcc or ghc"); 2165 2166 // Analyze operands of the call, assigning locations to each operand. 2167 SmallVector<CCValAssign, 16> ArgLocs; 2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2169 ArgLocs, *DAG.getContext()); 2170 2171 // Allocate shadow area for Win64 2172 if (IsWin64) { 2173 CCInfo.AllocateStack(32, 8); 2174 } 2175 2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2177 2178 // Get a count of how many bytes are to be pushed on the stack. 2179 unsigned NumBytes = CCInfo.getNextStackOffset(); 2180 if (IsSibcall) 2181 // This is a sibcall. The memory operands are available in caller's 2182 // own caller's stack. 2183 NumBytes = 0; 2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2185 IsTailCallConvention(CallConv)) 2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2187 2188 int FPDiff = 0; 2189 if (isTailCall && !IsSibcall) { 2190 // Lower arguments at fp - stackoffset + fpdiff. 2191 unsigned NumBytesCallerPushed = 2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2193 FPDiff = NumBytesCallerPushed - NumBytes; 2194 2195 // Set the delta of movement of the returnaddr stackslot. 2196 // But only set if delta is greater than previous delta. 2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2199 } 2200 2201 if (!IsSibcall) 2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2203 2204 SDValue RetAddrFrIdx; 2205 // Load return address for tail calls. 2206 if (isTailCall && FPDiff) 2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2208 Is64Bit, FPDiff, dl); 2209 2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2211 SmallVector<SDValue, 8> MemOpChains; 2212 SDValue StackPtr; 2213 2214 // Walk the register/memloc assignments, inserting copies/loads. In the case 2215 // of tail call optimization arguments are handle later. 2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2217 CCValAssign &VA = ArgLocs[i]; 2218 EVT RegVT = VA.getLocVT(); 2219 SDValue Arg = OutVals[i]; 2220 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2221 bool isByVal = Flags.isByVal(); 2222 2223 // Promote the value if needed. 2224 switch (VA.getLocInfo()) { 2225 default: llvm_unreachable("Unknown loc info!"); 2226 case CCValAssign::Full: break; 2227 case CCValAssign::SExt: 2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2229 break; 2230 case CCValAssign::ZExt: 2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2232 break; 2233 case CCValAssign::AExt: 2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2235 // Special case: passing MMX values in XMM registers. 2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2239 } else 2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2241 break; 2242 case CCValAssign::BCvt: 2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2244 break; 2245 case CCValAssign::Indirect: { 2246 // Store the argument. 2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2250 MachinePointerInfo::getFixedStack(FI), 2251 false, false, 0); 2252 Arg = SpillSlot; 2253 break; 2254 } 2255 } 2256 2257 if (VA.isRegLoc()) { 2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2259 if (isVarArg && IsWin64) { 2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2261 // shadow reg if callee is a varargs function. 2262 unsigned ShadowReg = 0; 2263 switch (VA.getLocReg()) { 2264 case X86::XMM0: ShadowReg = X86::RCX; break; 2265 case X86::XMM1: ShadowReg = X86::RDX; break; 2266 case X86::XMM2: ShadowReg = X86::R8; break; 2267 case X86::XMM3: ShadowReg = X86::R9; break; 2268 } 2269 if (ShadowReg) 2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2271 } 2272 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2273 assert(VA.isMemLoc()); 2274 if (StackPtr.getNode() == 0) 2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2277 dl, DAG, VA, Flags)); 2278 } 2279 } 2280 2281 if (!MemOpChains.empty()) 2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2283 &MemOpChains[0], MemOpChains.size()); 2284 2285 // Build a sequence of copy-to-reg nodes chained together with token chain 2286 // and flag operands which copy the outgoing args into registers. 2287 SDValue InFlag; 2288 // Tail call byval lowering might overwrite argument registers so in case of 2289 // tail call optimization the copies to registers are lowered later. 2290 if (!isTailCall) 2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2293 RegsToPass[i].second, InFlag); 2294 InFlag = Chain.getValue(1); 2295 } 2296 2297 if (Subtarget->isPICStyleGOT()) { 2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2299 // GOT pointer. 2300 if (!isTailCall) { 2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2302 DAG.getNode(X86ISD::GlobalBaseReg, 2303 DebugLoc(), getPointerTy()), 2304 InFlag); 2305 InFlag = Chain.getValue(1); 2306 } else { 2307 // If we are tail calling and generating PIC/GOT style code load the 2308 // address of the callee into ECX. The value in ecx is used as target of 2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2310 // for tail calls on PIC/GOT architectures. Normally we would just put the 2311 // address of GOT into ebx and then call target@PLT. But for tail calls 2312 // ebx would be restored (since ebx is callee saved) before jumping to the 2313 // target@PLT. 2314 2315 // Note: The actual moving to ECX is done further down. 2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2317 if (G && !G->getGlobal()->hasHiddenVisibility() && 2318 !G->getGlobal()->hasProtectedVisibility()) 2319 Callee = LowerGlobalAddress(Callee, DAG); 2320 else if (isa<ExternalSymbolSDNode>(Callee)) 2321 Callee = LowerExternalSymbol(Callee, DAG); 2322 } 2323 } 2324 2325 if (Is64Bit && isVarArg && !IsWin64) { 2326 // From AMD64 ABI document: 2327 // For calls that may call functions that use varargs or stdargs 2328 // (prototype-less calls or calls to functions containing ellipsis (...) in 2329 // the declaration) %al is used as hidden argument to specify the number 2330 // of SSE registers used. The contents of %al do not need to match exactly 2331 // the number of registers, but must be an ubound on the number of SSE 2332 // registers used and is in the range 0 - 8 inclusive. 2333 2334 // Count the number of XMM registers allocated. 2335 static const uint16_t XMMArgRegs[] = { 2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2338 }; 2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2340 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2341 && "SSE registers cannot be used when SSE is disabled"); 2342 2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2345 InFlag = Chain.getValue(1); 2346 } 2347 2348 2349 // For tail calls lower the arguments to the 'real' stack slot. 2350 if (isTailCall) { 2351 // Force all the incoming stack arguments to be loaded from the stack 2352 // before any new outgoing arguments are stored to the stack, because the 2353 // outgoing stack slots may alias the incoming argument stack slots, and 2354 // the alias isn't otherwise explicit. This is slightly more conservative 2355 // than necessary, because it means that each store effectively depends 2356 // on every argument instead of just those arguments it would clobber. 2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2358 2359 SmallVector<SDValue, 8> MemOpChains2; 2360 SDValue FIN; 2361 int FI = 0; 2362 // Do not flag preceding copytoreg stuff together with the following stuff. 2363 InFlag = SDValue(); 2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2366 CCValAssign &VA = ArgLocs[i]; 2367 if (VA.isRegLoc()) 2368 continue; 2369 assert(VA.isMemLoc()); 2370 SDValue Arg = OutVals[i]; 2371 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2372 // Create frame index. 2373 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2376 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2377 2378 if (Flags.isByVal()) { 2379 // Copy relative to framepointer. 2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2381 if (StackPtr.getNode() == 0) 2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2383 getPointerTy()); 2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2385 2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2387 ArgChain, 2388 Flags, DAG, dl)); 2389 } else { 2390 // Store relative to framepointer. 2391 MemOpChains2.push_back( 2392 DAG.getStore(ArgChain, dl, Arg, FIN, 2393 MachinePointerInfo::getFixedStack(FI), 2394 false, false, 0)); 2395 } 2396 } 2397 } 2398 2399 if (!MemOpChains2.empty()) 2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2401 &MemOpChains2[0], MemOpChains2.size()); 2402 2403 // Copy arguments to their registers. 2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2406 RegsToPass[i].second, InFlag); 2407 InFlag = Chain.getValue(1); 2408 } 2409 InFlag =SDValue(); 2410 2411 // Store the return address to the appropriate stack slot. 2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2413 FPDiff, dl); 2414 } 2415 2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2418 // In the 64-bit large code model, we have to make all calls 2419 // through a register, since the call instruction's 32-bit 2420 // pc-relative offset may not be large enough to hold the whole 2421 // address. 2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2423 // If the callee is a GlobalAddress node (quite common, every direct call 2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2425 // it. 2426 2427 // We should use extra load for direct calls to dllimported functions in 2428 // non-JIT mode. 2429 const GlobalValue *GV = G->getGlobal(); 2430 if (!GV->hasDLLImportLinkage()) { 2431 unsigned char OpFlags = 0; 2432 bool ExtraLoad = false; 2433 unsigned WrapperKind = ISD::DELETED_NODE; 2434 2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2436 // external symbols most go through the PLT in PIC mode. If the symbol 2437 // has hidden or protected visibility, or if it is static or local, then 2438 // we don't need to use the PLT - we can directly call it. 2439 if (Subtarget->isTargetELF() && 2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2442 OpFlags = X86II::MO_PLT; 2443 } else if (Subtarget->isPICStyleStubAny() && 2444 (GV->isDeclaration() || GV->isWeakForLinker()) && 2445 (!Subtarget->getTargetTriple().isMacOSX() || 2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2447 // PC-relative references to external symbols should go through $stub, 2448 // unless we're building with the leopard linker or later, which 2449 // automatically synthesizes these stubs. 2450 OpFlags = X86II::MO_DARWIN_STUB; 2451 } else if (Subtarget->isPICStyleRIPRel() && 2452 isa<Function>(GV) && 2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2454 // If the function is marked as non-lazy, generate an indirect call 2455 // which loads from the GOT directly. This avoids runtime overhead 2456 // at the cost of eager binding (and one extra byte of encoding). 2457 OpFlags = X86II::MO_GOTPCREL; 2458 WrapperKind = X86ISD::WrapperRIP; 2459 ExtraLoad = true; 2460 } 2461 2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2463 G->getOffset(), OpFlags); 2464 2465 // Add a wrapper if needed. 2466 if (WrapperKind != ISD::DELETED_NODE) 2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2468 // Add extra indirection if needed. 2469 if (ExtraLoad) 2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2471 MachinePointerInfo::getGOT(), 2472 false, false, false, 0); 2473 } 2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2475 unsigned char OpFlags = 0; 2476 2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2478 // external symbols should go through the PLT. 2479 if (Subtarget->isTargetELF() && 2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2481 OpFlags = X86II::MO_PLT; 2482 } else if (Subtarget->isPICStyleStubAny() && 2483 (!Subtarget->getTargetTriple().isMacOSX() || 2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2485 // PC-relative references to external symbols should go through $stub, 2486 // unless we're building with the leopard linker or later, which 2487 // automatically synthesizes these stubs. 2488 OpFlags = X86II::MO_DARWIN_STUB; 2489 } 2490 2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2492 OpFlags); 2493 } 2494 2495 // Returns a chain & a flag for retval copy to use. 2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2497 SmallVector<SDValue, 8> Ops; 2498 2499 if (!IsSibcall && isTailCall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2501 DAG.getIntPtrConstant(0, true), InFlag); 2502 InFlag = Chain.getValue(1); 2503 } 2504 2505 Ops.push_back(Chain); 2506 Ops.push_back(Callee); 2507 2508 if (isTailCall) 2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2510 2511 // Add argument registers to the end of the list so that they are known live 2512 // into the call. 2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2515 RegsToPass[i].second.getValueType())); 2516 2517 // Add an implicit use GOT pointer in EBX. 2518 if (!isTailCall && Subtarget->isPICStyleGOT()) 2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2520 2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2522 if (Is64Bit && isVarArg && !IsWin64) 2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2524 2525 // Add a register mask operand representing the call-preserved registers. 2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2528 assert(Mask && "Missing call preserved mask for calling convention"); 2529 Ops.push_back(DAG.getRegisterMask(Mask)); 2530 2531 if (InFlag.getNode()) 2532 Ops.push_back(InFlag); 2533 2534 if (isTailCall) { 2535 // We used to do: 2536 //// If this is the first return lowered for this function, add the regs 2537 //// to the liveout set for the function. 2538 // This isn't right, although it's probably harmless on x86; liveouts 2539 // should be computed from returns not tail calls. Consider a void 2540 // function making a tail call to a function returning int. 2541 return DAG.getNode(X86ISD::TC_RETURN, dl, 2542 NodeTys, &Ops[0], Ops.size()); 2543 } 2544 2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2546 InFlag = Chain.getValue(1); 2547 2548 // Create the CALLSEQ_END node. 2549 unsigned NumBytesForCalleeToPush; 2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2551 getTargetMachine().Options.GuaranteedTailCallOpt)) 2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2554 IsStructRet) 2555 // If this is a call to a struct-return function, the callee 2556 // pops the hidden struct pointer, so we have to push it back. 2557 // This is common for Darwin/X86, Linux & Mingw32 targets. 2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2559 NumBytesForCalleeToPush = 4; 2560 else 2561 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2562 2563 // Returns a flag for retval copy to use. 2564 if (!IsSibcall) { 2565 Chain = DAG.getCALLSEQ_END(Chain, 2566 DAG.getIntPtrConstant(NumBytes, true), 2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2568 true), 2569 InFlag); 2570 InFlag = Chain.getValue(1); 2571 } 2572 2573 // Handle result values, copying them out of physregs into vregs that we 2574 // return. 2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2576 Ins, dl, DAG, InVals); 2577} 2578 2579 2580//===----------------------------------------------------------------------===// 2581// Fast Calling Convention (tail call) implementation 2582//===----------------------------------------------------------------------===// 2583 2584// Like std call, callee cleans arguments, convention except that ECX is 2585// reserved for storing the tail called function address. Only 2 registers are 2586// free for argument passing (inreg). Tail call optimization is performed 2587// provided: 2588// * tailcallopt is enabled 2589// * caller/callee are fastcc 2590// On X86_64 architecture with GOT-style position independent code only local 2591// (within module) calls are supported at the moment. 2592// To keep the stack aligned according to platform abi the function 2593// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2594// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2595// If a tail called function callee has more arguments than the caller the 2596// caller needs to make sure that there is room to move the RETADDR to. This is 2597// achieved by reserving an area the size of the argument delta right after the 2598// original REtADDR, but before the saved framepointer or the spilled registers 2599// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2600// stack layout: 2601// arg1 2602// arg2 2603// RETADDR 2604// [ new RETADDR 2605// move area ] 2606// (possible EBP) 2607// ESI 2608// EDI 2609// local1 .. 2610 2611/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2612/// for a 16 byte align requirement. 2613unsigned 2614X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2615 SelectionDAG& DAG) const { 2616 MachineFunction &MF = DAG.getMachineFunction(); 2617 const TargetMachine &TM = MF.getTarget(); 2618 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2619 unsigned StackAlignment = TFI.getStackAlignment(); 2620 uint64_t AlignMask = StackAlignment - 1; 2621 int64_t Offset = StackSize; 2622 uint64_t SlotSize = TD->getPointerSize(); 2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2624 // Number smaller than 12 so just add the difference. 2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2626 } else { 2627 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2628 Offset = ((~AlignMask) & Offset) + StackAlignment + 2629 (StackAlignment-SlotSize); 2630 } 2631 return Offset; 2632} 2633 2634/// MatchingStackOffset - Return true if the given stack call argument is 2635/// already available in the same position (relatively) of the caller's 2636/// incoming argument stack. 2637static 2638bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2640 const X86InstrInfo *TII) { 2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2642 int FI = INT_MAX; 2643 if (Arg.getOpcode() == ISD::CopyFromReg) { 2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2645 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2646 return false; 2647 MachineInstr *Def = MRI->getVRegDef(VR); 2648 if (!Def) 2649 return false; 2650 if (!Flags.isByVal()) { 2651 if (!TII->isLoadFromStackSlot(Def, FI)) 2652 return false; 2653 } else { 2654 unsigned Opcode = Def->getOpcode(); 2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2656 Def->getOperand(1).isFI()) { 2657 FI = Def->getOperand(1).getIndex(); 2658 Bytes = Flags.getByValSize(); 2659 } else 2660 return false; 2661 } 2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2663 if (Flags.isByVal()) 2664 // ByVal argument is passed in as a pointer but it's now being 2665 // dereferenced. e.g. 2666 // define @foo(%struct.X* %A) { 2667 // tail call @bar(%struct.X* byval %A) 2668 // } 2669 return false; 2670 SDValue Ptr = Ld->getBasePtr(); 2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2672 if (!FINode) 2673 return false; 2674 FI = FINode->getIndex(); 2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2677 FI = FINode->getIndex(); 2678 Bytes = Flags.getByValSize(); 2679 } else 2680 return false; 2681 2682 assert(FI != INT_MAX); 2683 if (!MFI->isFixedObjectIndex(FI)) 2684 return false; 2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2686} 2687 2688/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2689/// for tail call optimization. Targets which want to do tail call 2690/// optimization should implement this function. 2691bool 2692X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2693 CallingConv::ID CalleeCC, 2694 bool isVarArg, 2695 bool isCalleeStructRet, 2696 bool isCallerStructRet, 2697 const SmallVectorImpl<ISD::OutputArg> &Outs, 2698 const SmallVectorImpl<SDValue> &OutVals, 2699 const SmallVectorImpl<ISD::InputArg> &Ins, 2700 SelectionDAG& DAG) const { 2701 if (!IsTailCallConvention(CalleeCC) && 2702 CalleeCC != CallingConv::C) 2703 return false; 2704 2705 // If -tailcallopt is specified, make fastcc functions tail-callable. 2706 const MachineFunction &MF = DAG.getMachineFunction(); 2707 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2708 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2709 bool CCMatch = CallerCC == CalleeCC; 2710 2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2712 if (IsTailCallConvention(CalleeCC) && CCMatch) 2713 return true; 2714 return false; 2715 } 2716 2717 // Look for obvious safe cases to perform tail call optimization that do not 2718 // require ABI changes. This is what gcc calls sibcall. 2719 2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2721 // emit a special epilogue. 2722 if (RegInfo->needsStackRealignment(MF)) 2723 return false; 2724 2725 // Also avoid sibcall optimization if either caller or callee uses struct 2726 // return semantics. 2727 if (isCalleeStructRet || isCallerStructRet) 2728 return false; 2729 2730 // An stdcall caller is expected to clean up its arguments; the callee 2731 // isn't going to do that. 2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2733 return false; 2734 2735 // Do not sibcall optimize vararg calls unless all arguments are passed via 2736 // registers. 2737 if (isVarArg && !Outs.empty()) { 2738 2739 // Optimizing for varargs on Win64 is unlikely to be safe without 2740 // additional testing. 2741 if (Subtarget->isTargetWin64()) 2742 return false; 2743 2744 SmallVector<CCValAssign, 16> ArgLocs; 2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2746 getTargetMachine(), ArgLocs, *DAG.getContext()); 2747 2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2750 if (!ArgLocs[i].isRegLoc()) 2751 return false; 2752 } 2753 2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2755 // stack. Therefore, if it's not used by the call it is not safe to optimize 2756 // this into a sibcall. 2757 bool Unused = false; 2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2759 if (!Ins[i].Used) { 2760 Unused = true; 2761 break; 2762 } 2763 } 2764 if (Unused) { 2765 SmallVector<CCValAssign, 16> RVLocs; 2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2767 getTargetMachine(), RVLocs, *DAG.getContext()); 2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2770 CCValAssign &VA = RVLocs[i]; 2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2772 return false; 2773 } 2774 } 2775 2776 // If the calling conventions do not match, then we'd better make sure the 2777 // results are returned in the same way as what the caller expects. 2778 if (!CCMatch) { 2779 SmallVector<CCValAssign, 16> RVLocs1; 2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2781 getTargetMachine(), RVLocs1, *DAG.getContext()); 2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2783 2784 SmallVector<CCValAssign, 16> RVLocs2; 2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2786 getTargetMachine(), RVLocs2, *DAG.getContext()); 2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2788 2789 if (RVLocs1.size() != RVLocs2.size()) 2790 return false; 2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2793 return false; 2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2795 return false; 2796 if (RVLocs1[i].isRegLoc()) { 2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2798 return false; 2799 } else { 2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2801 return false; 2802 } 2803 } 2804 } 2805 2806 // If the callee takes no arguments then go on to check the results of the 2807 // call. 2808 if (!Outs.empty()) { 2809 // Check if stack adjustment is needed. For now, do not do this if any 2810 // argument is passed on the stack. 2811 SmallVector<CCValAssign, 16> ArgLocs; 2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2813 getTargetMachine(), ArgLocs, *DAG.getContext()); 2814 2815 // Allocate shadow area for Win64 2816 if (Subtarget->isTargetWin64()) { 2817 CCInfo.AllocateStack(32, 8); 2818 } 2819 2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2821 if (CCInfo.getNextStackOffset()) { 2822 MachineFunction &MF = DAG.getMachineFunction(); 2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2824 return false; 2825 2826 // Check if the arguments are already laid out in the right way as 2827 // the caller's fixed stack objects. 2828 MachineFrameInfo *MFI = MF.getFrameInfo(); 2829 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2830 const X86InstrInfo *TII = 2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2833 CCValAssign &VA = ArgLocs[i]; 2834 SDValue Arg = OutVals[i]; 2835 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2836 if (VA.getLocInfo() == CCValAssign::Indirect) 2837 return false; 2838 if (!VA.isRegLoc()) { 2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2840 MFI, MRI, TII)) 2841 return false; 2842 } 2843 } 2844 } 2845 2846 // If the tailcall address may be in a register, then make sure it's 2847 // possible to register allocate for it. In 32-bit, the call address can 2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2849 // callee-saved registers are restored. These happen to be the same 2850 // registers used to pass 'inreg' arguments so watch out for those. 2851 if (!Subtarget->is64Bit() && 2852 !isa<GlobalAddressSDNode>(Callee) && 2853 !isa<ExternalSymbolSDNode>(Callee)) { 2854 unsigned NumInRegs = 0; 2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2856 CCValAssign &VA = ArgLocs[i]; 2857 if (!VA.isRegLoc()) 2858 continue; 2859 unsigned Reg = VA.getLocReg(); 2860 switch (Reg) { 2861 default: break; 2862 case X86::EAX: case X86::EDX: case X86::ECX: 2863 if (++NumInRegs == 3) 2864 return false; 2865 break; 2866 } 2867 } 2868 } 2869 } 2870 2871 return true; 2872} 2873 2874FastISel * 2875X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2876 return X86::createFastISel(funcInfo); 2877} 2878 2879 2880//===----------------------------------------------------------------------===// 2881// Other Lowering Hooks 2882//===----------------------------------------------------------------------===// 2883 2884static bool MayFoldLoad(SDValue Op) { 2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2886} 2887 2888static bool MayFoldIntoStore(SDValue Op) { 2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2890} 2891 2892static bool isTargetShuffle(unsigned Opcode) { 2893 switch(Opcode) { 2894 default: return false; 2895 case X86ISD::PSHUFD: 2896 case X86ISD::PSHUFHW: 2897 case X86ISD::PSHUFLW: 2898 case X86ISD::SHUFP: 2899 case X86ISD::PALIGN: 2900 case X86ISD::MOVLHPS: 2901 case X86ISD::MOVLHPD: 2902 case X86ISD::MOVHLPS: 2903 case X86ISD::MOVLPS: 2904 case X86ISD::MOVLPD: 2905 case X86ISD::MOVSHDUP: 2906 case X86ISD::MOVSLDUP: 2907 case X86ISD::MOVDDUP: 2908 case X86ISD::MOVSS: 2909 case X86ISD::MOVSD: 2910 case X86ISD::UNPCKL: 2911 case X86ISD::UNPCKH: 2912 case X86ISD::VPERMILP: 2913 case X86ISD::VPERM2X128: 2914 return true; 2915 } 2916} 2917 2918static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2919 SDValue V1, SelectionDAG &DAG) { 2920 switch(Opc) { 2921 default: llvm_unreachable("Unknown x86 shuffle node"); 2922 case X86ISD::MOVSHDUP: 2923 case X86ISD::MOVSLDUP: 2924 case X86ISD::MOVDDUP: 2925 return DAG.getNode(Opc, dl, VT, V1); 2926 } 2927} 2928 2929static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2930 SDValue V1, unsigned TargetMask, 2931 SelectionDAG &DAG) { 2932 switch(Opc) { 2933 default: llvm_unreachable("Unknown x86 shuffle node"); 2934 case X86ISD::PSHUFD: 2935 case X86ISD::PSHUFHW: 2936 case X86ISD::PSHUFLW: 2937 case X86ISD::VPERMILP: 2938 case X86ISD::VPERMI: 2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2940 } 2941} 2942 2943static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2944 SDValue V1, SDValue V2, unsigned TargetMask, 2945 SelectionDAG &DAG) { 2946 switch(Opc) { 2947 default: llvm_unreachable("Unknown x86 shuffle node"); 2948 case X86ISD::PALIGN: 2949 case X86ISD::SHUFP: 2950 case X86ISD::VPERM2X128: 2951 return DAG.getNode(Opc, dl, VT, V1, V2, 2952 DAG.getConstant(TargetMask, MVT::i8)); 2953 } 2954} 2955 2956static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2957 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2958 switch(Opc) { 2959 default: llvm_unreachable("Unknown x86 shuffle node"); 2960 case X86ISD::MOVLHPS: 2961 case X86ISD::MOVLHPD: 2962 case X86ISD::MOVHLPS: 2963 case X86ISD::MOVLPS: 2964 case X86ISD::MOVLPD: 2965 case X86ISD::MOVSS: 2966 case X86ISD::MOVSD: 2967 case X86ISD::UNPCKL: 2968 case X86ISD::UNPCKH: 2969 return DAG.getNode(Opc, dl, VT, V1, V2); 2970 } 2971} 2972 2973SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2974 MachineFunction &MF = DAG.getMachineFunction(); 2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2976 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2977 2978 if (ReturnAddrIndex == 0) { 2979 // Set up a frame object for the return address. 2980 uint64_t SlotSize = TD->getPointerSize(); 2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2982 false); 2983 FuncInfo->setRAIndex(ReturnAddrIndex); 2984 } 2985 2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2987} 2988 2989 2990bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2991 bool hasSymbolicDisplacement) { 2992 // Offset should fit into 32 bit immediate field. 2993 if (!isInt<32>(Offset)) 2994 return false; 2995 2996 // If we don't have a symbolic displacement - we don't have any extra 2997 // restrictions. 2998 if (!hasSymbolicDisplacement) 2999 return true; 3000 3001 // FIXME: Some tweaks might be needed for medium code model. 3002 if (M != CodeModel::Small && M != CodeModel::Kernel) 3003 return false; 3004 3005 // For small code model we assume that latest object is 16MB before end of 31 3006 // bits boundary. We may also accept pretty large negative constants knowing 3007 // that all objects are in the positive half of address space. 3008 if (M == CodeModel::Small && Offset < 16*1024*1024) 3009 return true; 3010 3011 // For kernel code model we know that all object resist in the negative half 3012 // of 32bits address space. We may not accept negative offsets, since they may 3013 // be just off and we may accept pretty large positive ones. 3014 if (M == CodeModel::Kernel && Offset > 0) 3015 return true; 3016 3017 return false; 3018} 3019 3020/// isCalleePop - Determines whether the callee is required to pop its 3021/// own arguments. Callee pop is necessary to support tail calls. 3022bool X86::isCalleePop(CallingConv::ID CallingConv, 3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3024 if (IsVarArg) 3025 return false; 3026 3027 switch (CallingConv) { 3028 default: 3029 return false; 3030 case CallingConv::X86_StdCall: 3031 return !is64Bit; 3032 case CallingConv::X86_FastCall: 3033 return !is64Bit; 3034 case CallingConv::X86_ThisCall: 3035 return !is64Bit; 3036 case CallingConv::Fast: 3037 return TailCallOpt; 3038 case CallingConv::GHC: 3039 return TailCallOpt; 3040 } 3041} 3042 3043/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3044/// specific condition code, returning the condition code and the LHS/RHS of the 3045/// comparison to make. 3046static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3048 if (!isFP) { 3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3051 // X > -1 -> X == 0, jump !sign. 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_NS; 3054 } 3055 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3056 // X < 0 -> X == 0, jump on sign. 3057 return X86::COND_S; 3058 } 3059 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3060 // X < 1 -> X <= 0 3061 RHS = DAG.getConstant(0, RHS.getValueType()); 3062 return X86::COND_LE; 3063 } 3064 } 3065 3066 switch (SetCCOpcode) { 3067 default: llvm_unreachable("Invalid integer condition!"); 3068 case ISD::SETEQ: return X86::COND_E; 3069 case ISD::SETGT: return X86::COND_G; 3070 case ISD::SETGE: return X86::COND_GE; 3071 case ISD::SETLT: return X86::COND_L; 3072 case ISD::SETLE: return X86::COND_LE; 3073 case ISD::SETNE: return X86::COND_NE; 3074 case ISD::SETULT: return X86::COND_B; 3075 case ISD::SETUGT: return X86::COND_A; 3076 case ISD::SETULE: return X86::COND_BE; 3077 case ISD::SETUGE: return X86::COND_AE; 3078 } 3079 } 3080 3081 // First determine if it is required or is profitable to flip the operands. 3082 3083 // If LHS is a foldable load, but RHS is not, flip the condition. 3084 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3085 !ISD::isNON_EXTLoad(RHS.getNode())) { 3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3087 std::swap(LHS, RHS); 3088 } 3089 3090 switch (SetCCOpcode) { 3091 default: break; 3092 case ISD::SETOLT: 3093 case ISD::SETOLE: 3094 case ISD::SETUGT: 3095 case ISD::SETUGE: 3096 std::swap(LHS, RHS); 3097 break; 3098 } 3099 3100 // On a floating point condition, the flags are set as follows: 3101 // ZF PF CF op 3102 // 0 | 0 | 0 | X > Y 3103 // 0 | 0 | 1 | X < Y 3104 // 1 | 0 | 0 | X == Y 3105 // 1 | 1 | 1 | unordered 3106 switch (SetCCOpcode) { 3107 default: llvm_unreachable("Condcode should be pre-legalized away"); 3108 case ISD::SETUEQ: 3109 case ISD::SETEQ: return X86::COND_E; 3110 case ISD::SETOLT: // flipped 3111 case ISD::SETOGT: 3112 case ISD::SETGT: return X86::COND_A; 3113 case ISD::SETOLE: // flipped 3114 case ISD::SETOGE: 3115 case ISD::SETGE: return X86::COND_AE; 3116 case ISD::SETUGT: // flipped 3117 case ISD::SETULT: 3118 case ISD::SETLT: return X86::COND_B; 3119 case ISD::SETUGE: // flipped 3120 case ISD::SETULE: 3121 case ISD::SETLE: return X86::COND_BE; 3122 case ISD::SETONE: 3123 case ISD::SETNE: return X86::COND_NE; 3124 case ISD::SETUO: return X86::COND_P; 3125 case ISD::SETO: return X86::COND_NP; 3126 case ISD::SETOEQ: 3127 case ISD::SETUNE: return X86::COND_INVALID; 3128 } 3129} 3130 3131/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3132/// code. Current x86 isa includes the following FP cmov instructions: 3133/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3134static bool hasFPCMov(unsigned X86CC) { 3135 switch (X86CC) { 3136 default: 3137 return false; 3138 case X86::COND_B: 3139 case X86::COND_BE: 3140 case X86::COND_E: 3141 case X86::COND_P: 3142 case X86::COND_A: 3143 case X86::COND_AE: 3144 case X86::COND_NE: 3145 case X86::COND_NP: 3146 return true; 3147 } 3148} 3149 3150/// isFPImmLegal - Returns true if the target can instruction select the 3151/// specified FP immediate natively. If false, the legalizer will 3152/// materialize the FP immediate as a load from a constant pool. 3153bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3156 return true; 3157 } 3158 return false; 3159} 3160 3161/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3162/// the specified range (L, H]. 3163static bool isUndefOrInRange(int Val, int Low, int Hi) { 3164 return (Val < 0) || (Val >= Low && Val < Hi); 3165} 3166 3167/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3168/// specified value. 3169static bool isUndefOrEqual(int Val, int CmpVal) { 3170 if (Val < 0 || Val == CmpVal) 3171 return true; 3172 return false; 3173} 3174 3175/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3176/// from position Pos and ending in Pos+Size, falls within the specified 3177/// sequential range (L, L+Pos]. or is undef. 3178static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3179 int Pos, int Size, int Low) { 3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3181 if (!isUndefOrEqual(Mask[i], Low)) 3182 return false; 3183 return true; 3184} 3185 3186/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3187/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3188/// the second operand. 3189static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3192 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3193 return (Mask[0] < 2 && Mask[1] < 2); 3194 return false; 3195} 3196 3197/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3198/// is suitable for input to PSHUFHW. 3199static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3200 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3201 return false; 3202 3203 // Lower quadword copied in order or undef. 3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3205 return false; 3206 3207 // Upper quadword shuffled. 3208 for (unsigned i = 4; i != 8; ++i) 3209 if (!isUndefOrInRange(Mask[i], 4, 8)) 3210 return false; 3211 3212 if (VT == MVT::v16i16) { 3213 // Lower quadword copied in order or undef. 3214 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3215 return false; 3216 3217 // Upper quadword shuffled. 3218 for (unsigned i = 12; i != 16; ++i) 3219 if (!isUndefOrInRange(Mask[i], 12, 16)) 3220 return false; 3221 } 3222 3223 return true; 3224} 3225 3226/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3227/// is suitable for input to PSHUFLW. 3228static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3229 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3230 return false; 3231 3232 // Upper quadword copied in order. 3233 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3234 return false; 3235 3236 // Lower quadword shuffled. 3237 for (unsigned i = 0; i != 4; ++i) 3238 if (!isUndefOrInRange(Mask[i], 0, 4)) 3239 return false; 3240 3241 if (VT == MVT::v16i16) { 3242 // Upper quadword copied in order. 3243 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3244 return false; 3245 3246 // Lower quadword shuffled. 3247 for (unsigned i = 8; i != 12; ++i) 3248 if (!isUndefOrInRange(Mask[i], 8, 12)) 3249 return false; 3250 } 3251 3252 return true; 3253} 3254 3255/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3256/// is suitable for input to PALIGNR. 3257static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3258 const X86Subtarget *Subtarget) { 3259 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3260 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3261 return false; 3262 3263 unsigned NumElts = VT.getVectorNumElements(); 3264 unsigned NumLanes = VT.getSizeInBits()/128; 3265 unsigned NumLaneElts = NumElts/NumLanes; 3266 3267 // Do not handle 64-bit element shuffles with palignr. 3268 if (NumLaneElts == 2) 3269 return false; 3270 3271 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3272 unsigned i; 3273 for (i = 0; i != NumLaneElts; ++i) { 3274 if (Mask[i+l] >= 0) 3275 break; 3276 } 3277 3278 // Lane is all undef, go to next lane 3279 if (i == NumLaneElts) 3280 continue; 3281 3282 int Start = Mask[i+l]; 3283 3284 // Make sure its in this lane in one of the sources 3285 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3286 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3287 return false; 3288 3289 // If not lane 0, then we must match lane 0 3290 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3291 return false; 3292 3293 // Correct second source to be contiguous with first source 3294 if (Start >= (int)NumElts) 3295 Start -= NumElts - NumLaneElts; 3296 3297 // Make sure we're shifting in the right direction. 3298 if (Start <= (int)(i+l)) 3299 return false; 3300 3301 Start -= i; 3302 3303 // Check the rest of the elements to see if they are consecutive. 3304 for (++i; i != NumLaneElts; ++i) { 3305 int Idx = Mask[i+l]; 3306 3307 // Make sure its in this lane 3308 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3309 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3310 return false; 3311 3312 // If not lane 0, then we must match lane 0 3313 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3314 return false; 3315 3316 if (Idx >= (int)NumElts) 3317 Idx -= NumElts - NumLaneElts; 3318 3319 if (!isUndefOrEqual(Idx, Start+i)) 3320 return false; 3321 3322 } 3323 } 3324 3325 return true; 3326} 3327 3328/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3329/// the two vector operands have swapped position. 3330static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3331 unsigned NumElems) { 3332 for (unsigned i = 0; i != NumElems; ++i) { 3333 int idx = Mask[i]; 3334 if (idx < 0) 3335 continue; 3336 else if (idx < (int)NumElems) 3337 Mask[i] = idx + NumElems; 3338 else 3339 Mask[i] = idx - NumElems; 3340 } 3341} 3342 3343/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3344/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3345/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3346/// reverse of what x86 shuffles want. 3347static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3348 bool Commuted = false) { 3349 if (!HasAVX && VT.getSizeInBits() == 256) 3350 return false; 3351 3352 unsigned NumElems = VT.getVectorNumElements(); 3353 unsigned NumLanes = VT.getSizeInBits()/128; 3354 unsigned NumLaneElems = NumElems/NumLanes; 3355 3356 if (NumLaneElems != 2 && NumLaneElems != 4) 3357 return false; 3358 3359 // VSHUFPSY divides the resulting vector into 4 chunks. 3360 // The sources are also splitted into 4 chunks, and each destination 3361 // chunk must come from a different source chunk. 3362 // 3363 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3364 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3365 // 3366 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3367 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3368 // 3369 // VSHUFPDY divides the resulting vector into 4 chunks. 3370 // The sources are also splitted into 4 chunks, and each destination 3371 // chunk must come from a different source chunk. 3372 // 3373 // SRC1 => X3 X2 X1 X0 3374 // SRC2 => Y3 Y2 Y1 Y0 3375 // 3376 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3377 // 3378 unsigned HalfLaneElems = NumLaneElems/2; 3379 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3380 for (unsigned i = 0; i != NumLaneElems; ++i) { 3381 int Idx = Mask[i+l]; 3382 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3383 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3384 return false; 3385 // For VSHUFPSY, the mask of the second half must be the same as the 3386 // first but with the appropriate offsets. This works in the same way as 3387 // VPERMILPS works with masks. 3388 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3389 continue; 3390 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3391 return false; 3392 } 3393 } 3394 3395 return true; 3396} 3397 3398/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3399/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3400static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3401 unsigned NumElems = VT.getVectorNumElements(); 3402 3403 if (VT.getSizeInBits() != 128) 3404 return false; 3405 3406 if (NumElems != 4) 3407 return false; 3408 3409 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3410 return isUndefOrEqual(Mask[0], 6) && 3411 isUndefOrEqual(Mask[1], 7) && 3412 isUndefOrEqual(Mask[2], 2) && 3413 isUndefOrEqual(Mask[3], 3); 3414} 3415 3416/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3417/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3418/// <2, 3, 2, 3> 3419static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3420 unsigned NumElems = VT.getVectorNumElements(); 3421 3422 if (VT.getSizeInBits() != 128) 3423 return false; 3424 3425 if (NumElems != 4) 3426 return false; 3427 3428 return isUndefOrEqual(Mask[0], 2) && 3429 isUndefOrEqual(Mask[1], 3) && 3430 isUndefOrEqual(Mask[2], 2) && 3431 isUndefOrEqual(Mask[3], 3); 3432} 3433 3434/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3435/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3436static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3437 if (VT.getSizeInBits() != 128) 3438 return false; 3439 3440 unsigned NumElems = VT.getVectorNumElements(); 3441 3442 if (NumElems != 2 && NumElems != 4) 3443 return false; 3444 3445 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3446 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3447 return false; 3448 3449 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3450 if (!isUndefOrEqual(Mask[i], i)) 3451 return false; 3452 3453 return true; 3454} 3455 3456/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3457/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3458static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3459 unsigned NumElems = VT.getVectorNumElements(); 3460 3461 if ((NumElems != 2 && NumElems != 4) 3462 || VT.getSizeInBits() > 128) 3463 return false; 3464 3465 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3466 if (!isUndefOrEqual(Mask[i], i)) 3467 return false; 3468 3469 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3470 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3471 return false; 3472 3473 return true; 3474} 3475 3476/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3477/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3478static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3479 bool HasAVX2, bool V2IsSplat = false) { 3480 unsigned NumElts = VT.getVectorNumElements(); 3481 3482 assert((VT.is128BitVector() || VT.is256BitVector()) && 3483 "Unsupported vector type for unpckh"); 3484 3485 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3486 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3487 return false; 3488 3489 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3490 // independently on 128-bit lanes. 3491 unsigned NumLanes = VT.getSizeInBits()/128; 3492 unsigned NumLaneElts = NumElts/NumLanes; 3493 3494 for (unsigned l = 0; l != NumLanes; ++l) { 3495 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3496 i != (l+1)*NumLaneElts; 3497 i += 2, ++j) { 3498 int BitI = Mask[i]; 3499 int BitI1 = Mask[i+1]; 3500 if (!isUndefOrEqual(BitI, j)) 3501 return false; 3502 if (V2IsSplat) { 3503 if (!isUndefOrEqual(BitI1, NumElts)) 3504 return false; 3505 } else { 3506 if (!isUndefOrEqual(BitI1, j + NumElts)) 3507 return false; 3508 } 3509 } 3510 } 3511 3512 return true; 3513} 3514 3515/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3516/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3517static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3518 bool HasAVX2, bool V2IsSplat = false) { 3519 unsigned NumElts = VT.getVectorNumElements(); 3520 3521 assert((VT.is128BitVector() || VT.is256BitVector()) && 3522 "Unsupported vector type for unpckh"); 3523 3524 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3525 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3526 return false; 3527 3528 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3529 // independently on 128-bit lanes. 3530 unsigned NumLanes = VT.getSizeInBits()/128; 3531 unsigned NumLaneElts = NumElts/NumLanes; 3532 3533 for (unsigned l = 0; l != NumLanes; ++l) { 3534 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3535 i != (l+1)*NumLaneElts; i += 2, ++j) { 3536 int BitI = Mask[i]; 3537 int BitI1 = Mask[i+1]; 3538 if (!isUndefOrEqual(BitI, j)) 3539 return false; 3540 if (V2IsSplat) { 3541 if (isUndefOrEqual(BitI1, NumElts)) 3542 return false; 3543 } else { 3544 if (!isUndefOrEqual(BitI1, j+NumElts)) 3545 return false; 3546 } 3547 } 3548 } 3549 return true; 3550} 3551 3552/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3553/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3554/// <0, 0, 1, 1> 3555static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3556 bool HasAVX2) { 3557 unsigned NumElts = VT.getVectorNumElements(); 3558 3559 assert((VT.is128BitVector() || VT.is256BitVector()) && 3560 "Unsupported vector type for unpckh"); 3561 3562 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3563 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3564 return false; 3565 3566 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3567 // FIXME: Need a better way to get rid of this, there's no latency difference 3568 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3569 // the former later. We should also remove the "_undef" special mask. 3570 if (NumElts == 4 && VT.getSizeInBits() == 256) 3571 return false; 3572 3573 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3574 // independently on 128-bit lanes. 3575 unsigned NumLanes = VT.getSizeInBits()/128; 3576 unsigned NumLaneElts = NumElts/NumLanes; 3577 3578 for (unsigned l = 0; l != NumLanes; ++l) { 3579 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3580 i != (l+1)*NumLaneElts; 3581 i += 2, ++j) { 3582 int BitI = Mask[i]; 3583 int BitI1 = Mask[i+1]; 3584 3585 if (!isUndefOrEqual(BitI, j)) 3586 return false; 3587 if (!isUndefOrEqual(BitI1, j)) 3588 return false; 3589 } 3590 } 3591 3592 return true; 3593} 3594 3595/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3596/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3597/// <2, 2, 3, 3> 3598static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3599 unsigned NumElts = VT.getVectorNumElements(); 3600 3601 assert((VT.is128BitVector() || VT.is256BitVector()) && 3602 "Unsupported vector type for unpckh"); 3603 3604 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3605 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3606 return false; 3607 3608 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3609 // independently on 128-bit lanes. 3610 unsigned NumLanes = VT.getSizeInBits()/128; 3611 unsigned NumLaneElts = NumElts/NumLanes; 3612 3613 for (unsigned l = 0; l != NumLanes; ++l) { 3614 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3615 i != (l+1)*NumLaneElts; i += 2, ++j) { 3616 int BitI = Mask[i]; 3617 int BitI1 = Mask[i+1]; 3618 if (!isUndefOrEqual(BitI, j)) 3619 return false; 3620 if (!isUndefOrEqual(BitI1, j)) 3621 return false; 3622 } 3623 } 3624 return true; 3625} 3626 3627/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3628/// specifies a shuffle of elements that is suitable for input to MOVSS, 3629/// MOVSD, and MOVD, i.e. setting the lowest element. 3630static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3631 if (VT.getVectorElementType().getSizeInBits() < 32) 3632 return false; 3633 if (VT.getSizeInBits() == 256) 3634 return false; 3635 3636 unsigned NumElts = VT.getVectorNumElements(); 3637 3638 if (!isUndefOrEqual(Mask[0], NumElts)) 3639 return false; 3640 3641 for (unsigned i = 1; i != NumElts; ++i) 3642 if (!isUndefOrEqual(Mask[i], i)) 3643 return false; 3644 3645 return true; 3646} 3647 3648/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3649/// as permutations between 128-bit chunks or halves. As an example: this 3650/// shuffle bellow: 3651/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3652/// The first half comes from the second half of V1 and the second half from the 3653/// the second half of V2. 3654static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3655 if (!HasAVX || VT.getSizeInBits() != 256) 3656 return false; 3657 3658 // The shuffle result is divided into half A and half B. In total the two 3659 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3660 // B must come from C, D, E or F. 3661 unsigned HalfSize = VT.getVectorNumElements()/2; 3662 bool MatchA = false, MatchB = false; 3663 3664 // Check if A comes from one of C, D, E, F. 3665 for (unsigned Half = 0; Half != 4; ++Half) { 3666 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3667 MatchA = true; 3668 break; 3669 } 3670 } 3671 3672 // Check if B comes from one of C, D, E, F. 3673 for (unsigned Half = 0; Half != 4; ++Half) { 3674 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3675 MatchB = true; 3676 break; 3677 } 3678 } 3679 3680 return MatchA && MatchB; 3681} 3682 3683/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3684/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3685static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3686 EVT VT = SVOp->getValueType(0); 3687 3688 unsigned HalfSize = VT.getVectorNumElements()/2; 3689 3690 unsigned FstHalf = 0, SndHalf = 0; 3691 for (unsigned i = 0; i < HalfSize; ++i) { 3692 if (SVOp->getMaskElt(i) > 0) { 3693 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3694 break; 3695 } 3696 } 3697 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3698 if (SVOp->getMaskElt(i) > 0) { 3699 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3700 break; 3701 } 3702 } 3703 3704 return (FstHalf | (SndHalf << 4)); 3705} 3706 3707/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3708/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3709/// Note that VPERMIL mask matching is different depending whether theunderlying 3710/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3711/// to the same elements of the low, but to the higher half of the source. 3712/// In VPERMILPD the two lanes could be shuffled independently of each other 3713/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3714static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3715 if (!HasAVX) 3716 return false; 3717 3718 unsigned NumElts = VT.getVectorNumElements(); 3719 // Only match 256-bit with 32/64-bit types 3720 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3721 return false; 3722 3723 unsigned NumLanes = VT.getSizeInBits()/128; 3724 unsigned LaneSize = NumElts/NumLanes; 3725 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3726 for (unsigned i = 0; i != LaneSize; ++i) { 3727 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3728 return false; 3729 if (NumElts != 8 || l == 0) 3730 continue; 3731 // VPERMILPS handling 3732 if (Mask[i] < 0) 3733 continue; 3734 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3735 return false; 3736 } 3737 } 3738 3739 return true; 3740} 3741 3742/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3743/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3744/// element of vector 2 and the other elements to come from vector 1 in order. 3745static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3746 bool V2IsSplat = false, bool V2IsUndef = false) { 3747 unsigned NumOps = VT.getVectorNumElements(); 3748 if (VT.getSizeInBits() == 256) 3749 return false; 3750 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3751 return false; 3752 3753 if (!isUndefOrEqual(Mask[0], 0)) 3754 return false; 3755 3756 for (unsigned i = 1; i != NumOps; ++i) 3757 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3758 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3759 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3760 return false; 3761 3762 return true; 3763} 3764 3765/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3766/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3767/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3768static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3769 const X86Subtarget *Subtarget) { 3770 if (!Subtarget->hasSSE3()) 3771 return false; 3772 3773 unsigned NumElems = VT.getVectorNumElements(); 3774 3775 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3776 (VT.getSizeInBits() == 256 && NumElems != 8)) 3777 return false; 3778 3779 // "i+1" is the value the indexed mask element must have 3780 for (unsigned i = 0; i != NumElems; i += 2) 3781 if (!isUndefOrEqual(Mask[i], i+1) || 3782 !isUndefOrEqual(Mask[i+1], i+1)) 3783 return false; 3784 3785 return true; 3786} 3787 3788/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3789/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3790/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3791static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3792 const X86Subtarget *Subtarget) { 3793 if (!Subtarget->hasSSE3()) 3794 return false; 3795 3796 unsigned NumElems = VT.getVectorNumElements(); 3797 3798 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3799 (VT.getSizeInBits() == 256 && NumElems != 8)) 3800 return false; 3801 3802 // "i" is the value the indexed mask element must have 3803 for (unsigned i = 0; i != NumElems; i += 2) 3804 if (!isUndefOrEqual(Mask[i], i) || 3805 !isUndefOrEqual(Mask[i+1], i)) 3806 return false; 3807 3808 return true; 3809} 3810 3811/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3812/// specifies a shuffle of elements that is suitable for input to 256-bit 3813/// version of MOVDDUP. 3814static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3815 unsigned NumElts = VT.getVectorNumElements(); 3816 3817 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3818 return false; 3819 3820 for (unsigned i = 0; i != NumElts/2; ++i) 3821 if (!isUndefOrEqual(Mask[i], 0)) 3822 return false; 3823 for (unsigned i = NumElts/2; i != NumElts; ++i) 3824 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3825 return false; 3826 return true; 3827} 3828 3829/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3830/// specifies a shuffle of elements that is suitable for input to 128-bit 3831/// version of MOVDDUP. 3832static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3833 if (VT.getSizeInBits() != 128) 3834 return false; 3835 3836 unsigned e = VT.getVectorNumElements() / 2; 3837 for (unsigned i = 0; i != e; ++i) 3838 if (!isUndefOrEqual(Mask[i], i)) 3839 return false; 3840 for (unsigned i = 0; i != e; ++i) 3841 if (!isUndefOrEqual(Mask[e+i], i)) 3842 return false; 3843 return true; 3844} 3845 3846/// isVEXTRACTF128Index - Return true if the specified 3847/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3848/// suitable for input to VEXTRACTF128. 3849bool X86::isVEXTRACTF128Index(SDNode *N) { 3850 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3851 return false; 3852 3853 // The index should be aligned on a 128-bit boundary. 3854 uint64_t Index = 3855 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3856 3857 unsigned VL = N->getValueType(0).getVectorNumElements(); 3858 unsigned VBits = N->getValueType(0).getSizeInBits(); 3859 unsigned ElSize = VBits / VL; 3860 bool Result = (Index * ElSize) % 128 == 0; 3861 3862 return Result; 3863} 3864 3865/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3866/// operand specifies a subvector insert that is suitable for input to 3867/// VINSERTF128. 3868bool X86::isVINSERTF128Index(SDNode *N) { 3869 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3870 return false; 3871 3872 // The index should be aligned on a 128-bit boundary. 3873 uint64_t Index = 3874 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3875 3876 unsigned VL = N->getValueType(0).getVectorNumElements(); 3877 unsigned VBits = N->getValueType(0).getSizeInBits(); 3878 unsigned ElSize = VBits / VL; 3879 bool Result = (Index * ElSize) % 128 == 0; 3880 3881 return Result; 3882} 3883 3884/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3885/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3886/// Handles 128-bit and 256-bit. 3887static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3888 EVT VT = N->getValueType(0); 3889 3890 assert((VT.is128BitVector() || VT.is256BitVector()) && 3891 "Unsupported vector type for PSHUF/SHUFP"); 3892 3893 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3894 // independently on 128-bit lanes. 3895 unsigned NumElts = VT.getVectorNumElements(); 3896 unsigned NumLanes = VT.getSizeInBits()/128; 3897 unsigned NumLaneElts = NumElts/NumLanes; 3898 3899 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3900 "Only supports 2 or 4 elements per lane"); 3901 3902 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3903 unsigned Mask = 0; 3904 for (unsigned i = 0; i != NumElts; ++i) { 3905 int Elt = N->getMaskElt(i); 3906 if (Elt < 0) continue; 3907 Elt %= NumLaneElts; 3908 unsigned ShAmt = i << Shift; 3909 if (ShAmt >= 8) ShAmt -= 8; 3910 Mask |= Elt << ShAmt; 3911 } 3912 3913 return Mask; 3914} 3915 3916/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3917/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3918static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3919 unsigned Mask = 0; 3920 // 8 nodes, but we only care about the last 4. 3921 for (unsigned i = 7; i >= 4; --i) { 3922 int Val = N->getMaskElt(i); 3923 if (Val >= 0) 3924 Mask |= (Val - 4); 3925 if (i != 4) 3926 Mask <<= 2; 3927 } 3928 return Mask; 3929} 3930 3931/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3932/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3933static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3934 unsigned Mask = 0; 3935 // 8 nodes, but we only care about the first 4. 3936 for (int i = 3; i >= 0; --i) { 3937 int Val = N->getMaskElt(i); 3938 if (Val >= 0) 3939 Mask |= Val; 3940 if (i != 0) 3941 Mask <<= 2; 3942 } 3943 return Mask; 3944} 3945 3946/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3947/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3948static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3949 EVT VT = SVOp->getValueType(0); 3950 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3951 3952 unsigned NumElts = VT.getVectorNumElements(); 3953 unsigned NumLanes = VT.getSizeInBits()/128; 3954 unsigned NumLaneElts = NumElts/NumLanes; 3955 3956 int Val = 0; 3957 unsigned i; 3958 for (i = 0; i != NumElts; ++i) { 3959 Val = SVOp->getMaskElt(i); 3960 if (Val >= 0) 3961 break; 3962 } 3963 if (Val >= (int)NumElts) 3964 Val -= NumElts - NumLaneElts; 3965 3966 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3967 return (Val - i) * EltSize; 3968} 3969 3970/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3971/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3972/// instructions. 3973unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3974 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3975 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3976 3977 uint64_t Index = 3978 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3979 3980 EVT VecVT = N->getOperand(0).getValueType(); 3981 EVT ElVT = VecVT.getVectorElementType(); 3982 3983 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3984 return Index / NumElemsPerChunk; 3985} 3986 3987/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3988/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3989/// instructions. 3990unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3991 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3992 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3993 3994 uint64_t Index = 3995 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3996 3997 EVT VecVT = N->getValueType(0); 3998 EVT ElVT = VecVT.getVectorElementType(); 3999 4000 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4001 return Index / NumElemsPerChunk; 4002} 4003 4004/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4005/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4006/// Handles 256-bit. 4007static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4008 EVT VT = N->getValueType(0); 4009 4010 unsigned NumElts = VT.getVectorNumElements(); 4011 4012 assert((VT.is256BitVector() && NumElts == 4) && 4013 "Unsupported vector type for VPERMQ/VPERMPD"); 4014 4015 unsigned Mask = 0; 4016 for (unsigned i = 0; i != NumElts; ++i) { 4017 int Elt = N->getMaskElt(i); 4018 if (Elt < 0) 4019 continue; 4020 Mask |= Elt << (i*2); 4021 } 4022 4023 return Mask; 4024} 4025/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4026/// constant +0.0. 4027bool X86::isZeroNode(SDValue Elt) { 4028 return ((isa<ConstantSDNode>(Elt) && 4029 cast<ConstantSDNode>(Elt)->isNullValue()) || 4030 (isa<ConstantFPSDNode>(Elt) && 4031 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4032} 4033 4034/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4035/// their permute mask. 4036static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4037 SelectionDAG &DAG) { 4038 EVT VT = SVOp->getValueType(0); 4039 unsigned NumElems = VT.getVectorNumElements(); 4040 SmallVector<int, 8> MaskVec; 4041 4042 for (unsigned i = 0; i != NumElems; ++i) { 4043 int idx = SVOp->getMaskElt(i); 4044 if (idx < 0) 4045 MaskVec.push_back(idx); 4046 else if (idx < (int)NumElems) 4047 MaskVec.push_back(idx + NumElems); 4048 else 4049 MaskVec.push_back(idx - NumElems); 4050 } 4051 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4052 SVOp->getOperand(0), &MaskVec[0]); 4053} 4054 4055/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4056/// match movhlps. The lower half elements should come from upper half of 4057/// V1 (and in order), and the upper half elements should come from the upper 4058/// half of V2 (and in order). 4059static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4060 if (VT.getSizeInBits() != 128) 4061 return false; 4062 if (VT.getVectorNumElements() != 4) 4063 return false; 4064 for (unsigned i = 0, e = 2; i != e; ++i) 4065 if (!isUndefOrEqual(Mask[i], i+2)) 4066 return false; 4067 for (unsigned i = 2; i != 4; ++i) 4068 if (!isUndefOrEqual(Mask[i], i+4)) 4069 return false; 4070 return true; 4071} 4072 4073/// isScalarLoadToVector - Returns true if the node is a scalar load that 4074/// is promoted to a vector. It also returns the LoadSDNode by reference if 4075/// required. 4076static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4077 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4078 return false; 4079 N = N->getOperand(0).getNode(); 4080 if (!ISD::isNON_EXTLoad(N)) 4081 return false; 4082 if (LD) 4083 *LD = cast<LoadSDNode>(N); 4084 return true; 4085} 4086 4087// Test whether the given value is a vector value which will be legalized 4088// into a load. 4089static bool WillBeConstantPoolLoad(SDNode *N) { 4090 if (N->getOpcode() != ISD::BUILD_VECTOR) 4091 return false; 4092 4093 // Check for any non-constant elements. 4094 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4095 switch (N->getOperand(i).getNode()->getOpcode()) { 4096 case ISD::UNDEF: 4097 case ISD::ConstantFP: 4098 case ISD::Constant: 4099 break; 4100 default: 4101 return false; 4102 } 4103 4104 // Vectors of all-zeros and all-ones are materialized with special 4105 // instructions rather than being loaded. 4106 return !ISD::isBuildVectorAllZeros(N) && 4107 !ISD::isBuildVectorAllOnes(N); 4108} 4109 4110/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4111/// match movlp{s|d}. The lower half elements should come from lower half of 4112/// V1 (and in order), and the upper half elements should come from the upper 4113/// half of V2 (and in order). And since V1 will become the source of the 4114/// MOVLP, it must be either a vector load or a scalar load to vector. 4115static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4116 ArrayRef<int> Mask, EVT VT) { 4117 if (VT.getSizeInBits() != 128) 4118 return false; 4119 4120 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4121 return false; 4122 // Is V2 is a vector load, don't do this transformation. We will try to use 4123 // load folding shufps op. 4124 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4125 return false; 4126 4127 unsigned NumElems = VT.getVectorNumElements(); 4128 4129 if (NumElems != 2 && NumElems != 4) 4130 return false; 4131 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4132 if (!isUndefOrEqual(Mask[i], i)) 4133 return false; 4134 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4135 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4136 return false; 4137 return true; 4138} 4139 4140/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4141/// all the same. 4142static bool isSplatVector(SDNode *N) { 4143 if (N->getOpcode() != ISD::BUILD_VECTOR) 4144 return false; 4145 4146 SDValue SplatValue = N->getOperand(0); 4147 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4148 if (N->getOperand(i) != SplatValue) 4149 return false; 4150 return true; 4151} 4152 4153/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4154/// to an zero vector. 4155/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4156static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4157 SDValue V1 = N->getOperand(0); 4158 SDValue V2 = N->getOperand(1); 4159 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4160 for (unsigned i = 0; i != NumElems; ++i) { 4161 int Idx = N->getMaskElt(i); 4162 if (Idx >= (int)NumElems) { 4163 unsigned Opc = V2.getOpcode(); 4164 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4165 continue; 4166 if (Opc != ISD::BUILD_VECTOR || 4167 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4168 return false; 4169 } else if (Idx >= 0) { 4170 unsigned Opc = V1.getOpcode(); 4171 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4172 continue; 4173 if (Opc != ISD::BUILD_VECTOR || 4174 !X86::isZeroNode(V1.getOperand(Idx))) 4175 return false; 4176 } 4177 } 4178 return true; 4179} 4180 4181/// getZeroVector - Returns a vector of specified type with all zero elements. 4182/// 4183static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4184 SelectionDAG &DAG, DebugLoc dl) { 4185 assert(VT.isVector() && "Expected a vector type"); 4186 unsigned Size = VT.getSizeInBits(); 4187 4188 // Always build SSE zero vectors as <4 x i32> bitcasted 4189 // to their dest type. This ensures they get CSE'd. 4190 SDValue Vec; 4191 if (Size == 128) { // SSE 4192 if (Subtarget->hasSSE2()) { // SSE2 4193 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4194 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4195 } else { // SSE1 4196 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4197 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4198 } 4199 } else if (Size == 256) { // AVX 4200 if (Subtarget->hasAVX2()) { // AVX2 4201 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4202 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4203 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4204 } else { 4205 // 256-bit logic and arithmetic instructions in AVX are all 4206 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4207 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4208 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4210 } 4211 } else 4212 llvm_unreachable("Unexpected vector type"); 4213 4214 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4215} 4216 4217/// getOnesVector - Returns a vector of specified type with all bits set. 4218/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4219/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4220/// Then bitcast to their original type, ensuring they get CSE'd. 4221static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4222 DebugLoc dl) { 4223 assert(VT.isVector() && "Expected a vector type"); 4224 unsigned Size = VT.getSizeInBits(); 4225 4226 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4227 SDValue Vec; 4228 if (Size == 256) { 4229 if (HasAVX2) { // AVX2 4230 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4231 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4232 } else { // AVX 4233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4234 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4235 } 4236 } else if (Size == 128) { 4237 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4238 } else 4239 llvm_unreachable("Unexpected vector type"); 4240 4241 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4242} 4243 4244/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4245/// that point to V2 points to its first element. 4246static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4247 for (unsigned i = 0; i != NumElems; ++i) { 4248 if (Mask[i] > (int)NumElems) { 4249 Mask[i] = NumElems; 4250 } 4251 } 4252} 4253 4254/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4255/// operation of specified width. 4256static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4257 SDValue V2) { 4258 unsigned NumElems = VT.getVectorNumElements(); 4259 SmallVector<int, 8> Mask; 4260 Mask.push_back(NumElems); 4261 for (unsigned i = 1; i != NumElems; ++i) 4262 Mask.push_back(i); 4263 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4264} 4265 4266/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4267static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4268 SDValue V2) { 4269 unsigned NumElems = VT.getVectorNumElements(); 4270 SmallVector<int, 8> Mask; 4271 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4272 Mask.push_back(i); 4273 Mask.push_back(i + NumElems); 4274 } 4275 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4276} 4277 4278/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4279static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4280 SDValue V2) { 4281 unsigned NumElems = VT.getVectorNumElements(); 4282 SmallVector<int, 8> Mask; 4283 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4284 Mask.push_back(i + Half); 4285 Mask.push_back(i + NumElems + Half); 4286 } 4287 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4288} 4289 4290// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4291// a generic shuffle instruction because the target has no such instructions. 4292// Generate shuffles which repeat i16 and i8 several times until they can be 4293// represented by v4f32 and then be manipulated by target suported shuffles. 4294static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4295 EVT VT = V.getValueType(); 4296 int NumElems = VT.getVectorNumElements(); 4297 DebugLoc dl = V.getDebugLoc(); 4298 4299 while (NumElems > 4) { 4300 if (EltNo < NumElems/2) { 4301 V = getUnpackl(DAG, dl, VT, V, V); 4302 } else { 4303 V = getUnpackh(DAG, dl, VT, V, V); 4304 EltNo -= NumElems/2; 4305 } 4306 NumElems >>= 1; 4307 } 4308 return V; 4309} 4310 4311/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4312static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4313 EVT VT = V.getValueType(); 4314 DebugLoc dl = V.getDebugLoc(); 4315 unsigned Size = VT.getSizeInBits(); 4316 4317 if (Size == 128) { 4318 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4319 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4320 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4321 &SplatMask[0]); 4322 } else if (Size == 256) { 4323 // To use VPERMILPS to splat scalars, the second half of indicies must 4324 // refer to the higher part, which is a duplication of the lower one, 4325 // because VPERMILPS can only handle in-lane permutations. 4326 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4327 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4328 4329 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4330 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4331 &SplatMask[0]); 4332 } else 4333 llvm_unreachable("Vector size not supported"); 4334 4335 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4336} 4337 4338/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4339static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4340 EVT SrcVT = SV->getValueType(0); 4341 SDValue V1 = SV->getOperand(0); 4342 DebugLoc dl = SV->getDebugLoc(); 4343 4344 int EltNo = SV->getSplatIndex(); 4345 int NumElems = SrcVT.getVectorNumElements(); 4346 unsigned Size = SrcVT.getSizeInBits(); 4347 4348 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4349 "Unknown how to promote splat for type"); 4350 4351 // Extract the 128-bit part containing the splat element and update 4352 // the splat element index when it refers to the higher register. 4353 if (Size == 256) { 4354 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4355 if (EltNo >= NumElems/2) 4356 EltNo -= NumElems/2; 4357 } 4358 4359 // All i16 and i8 vector types can't be used directly by a generic shuffle 4360 // instruction because the target has no such instruction. Generate shuffles 4361 // which repeat i16 and i8 several times until they fit in i32, and then can 4362 // be manipulated by target suported shuffles. 4363 EVT EltVT = SrcVT.getVectorElementType(); 4364 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4365 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4366 4367 // Recreate the 256-bit vector and place the same 128-bit vector 4368 // into the low and high part. This is necessary because we want 4369 // to use VPERM* to shuffle the vectors 4370 if (Size == 256) { 4371 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4372 } 4373 4374 return getLegalSplat(DAG, V1, EltNo); 4375} 4376 4377/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4378/// vector of zero or undef vector. This produces a shuffle where the low 4379/// element of V2 is swizzled into the zero/undef vector, landing at element 4380/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4381static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4382 bool IsZero, 4383 const X86Subtarget *Subtarget, 4384 SelectionDAG &DAG) { 4385 EVT VT = V2.getValueType(); 4386 SDValue V1 = IsZero 4387 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4388 unsigned NumElems = VT.getVectorNumElements(); 4389 SmallVector<int, 16> MaskVec; 4390 for (unsigned i = 0; i != NumElems; ++i) 4391 // If this is the insertion idx, put the low elt of V2 here. 4392 MaskVec.push_back(i == Idx ? NumElems : i); 4393 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4394} 4395 4396/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4397/// target specific opcode. Returns true if the Mask could be calculated. 4398/// Sets IsUnary to true if only uses one source. 4399static bool getTargetShuffleMask(SDNode *N, EVT VT, 4400 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4401 unsigned NumElems = VT.getVectorNumElements(); 4402 SDValue ImmN; 4403 4404 IsUnary = false; 4405 switch(N->getOpcode()) { 4406 case X86ISD::SHUFP: 4407 ImmN = N->getOperand(N->getNumOperands()-1); 4408 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4409 break; 4410 case X86ISD::UNPCKH: 4411 DecodeUNPCKHMask(VT, Mask); 4412 break; 4413 case X86ISD::UNPCKL: 4414 DecodeUNPCKLMask(VT, Mask); 4415 break; 4416 case X86ISD::MOVHLPS: 4417 DecodeMOVHLPSMask(NumElems, Mask); 4418 break; 4419 case X86ISD::MOVLHPS: 4420 DecodeMOVLHPSMask(NumElems, Mask); 4421 break; 4422 case X86ISD::PSHUFD: 4423 case X86ISD::VPERMILP: 4424 ImmN = N->getOperand(N->getNumOperands()-1); 4425 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4426 IsUnary = true; 4427 break; 4428 case X86ISD::PSHUFHW: 4429 ImmN = N->getOperand(N->getNumOperands()-1); 4430 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4431 IsUnary = true; 4432 break; 4433 case X86ISD::PSHUFLW: 4434 ImmN = N->getOperand(N->getNumOperands()-1); 4435 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4436 IsUnary = true; 4437 break; 4438 case X86ISD::MOVSS: 4439 case X86ISD::MOVSD: { 4440 // The index 0 always comes from the first element of the second source, 4441 // this is why MOVSS and MOVSD are used in the first place. The other 4442 // elements come from the other positions of the first source vector 4443 Mask.push_back(NumElems); 4444 for (unsigned i = 1; i != NumElems; ++i) { 4445 Mask.push_back(i); 4446 } 4447 break; 4448 } 4449 case X86ISD::VPERM2X128: 4450 ImmN = N->getOperand(N->getNumOperands()-1); 4451 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4452 if (Mask.empty()) return false; 4453 break; 4454 case X86ISD::MOVDDUP: 4455 case X86ISD::MOVLHPD: 4456 case X86ISD::MOVLPD: 4457 case X86ISD::MOVLPS: 4458 case X86ISD::MOVSHDUP: 4459 case X86ISD::MOVSLDUP: 4460 case X86ISD::PALIGN: 4461 // Not yet implemented 4462 return false; 4463 default: llvm_unreachable("unknown target shuffle node"); 4464 } 4465 4466 return true; 4467} 4468 4469/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4470/// element of the result of the vector shuffle. 4471static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4472 unsigned Depth) { 4473 if (Depth == 6) 4474 return SDValue(); // Limit search depth. 4475 4476 SDValue V = SDValue(N, 0); 4477 EVT VT = V.getValueType(); 4478 unsigned Opcode = V.getOpcode(); 4479 4480 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4481 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4482 int Elt = SV->getMaskElt(Index); 4483 4484 if (Elt < 0) 4485 return DAG.getUNDEF(VT.getVectorElementType()); 4486 4487 unsigned NumElems = VT.getVectorNumElements(); 4488 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4489 : SV->getOperand(1); 4490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4491 } 4492 4493 // Recurse into target specific vector shuffles to find scalars. 4494 if (isTargetShuffle(Opcode)) { 4495 unsigned NumElems = VT.getVectorNumElements(); 4496 SmallVector<int, 16> ShuffleMask; 4497 SDValue ImmN; 4498 bool IsUnary; 4499 4500 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4501 return SDValue(); 4502 4503 int Elt = ShuffleMask[Index]; 4504 if (Elt < 0) 4505 return DAG.getUNDEF(VT.getVectorElementType()); 4506 4507 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4508 : N->getOperand(1); 4509 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4510 Depth+1); 4511 } 4512 4513 // Actual nodes that may contain scalar elements 4514 if (Opcode == ISD::BITCAST) { 4515 V = V.getOperand(0); 4516 EVT SrcVT = V.getValueType(); 4517 unsigned NumElems = VT.getVectorNumElements(); 4518 4519 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4520 return SDValue(); 4521 } 4522 4523 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4524 return (Index == 0) ? V.getOperand(0) 4525 : DAG.getUNDEF(VT.getVectorElementType()); 4526 4527 if (V.getOpcode() == ISD::BUILD_VECTOR) 4528 return V.getOperand(Index); 4529 4530 return SDValue(); 4531} 4532 4533/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4534/// shuffle operation which come from a consecutively from a zero. The 4535/// search can start in two different directions, from left or right. 4536static 4537unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4538 bool ZerosFromLeft, SelectionDAG &DAG) { 4539 unsigned i; 4540 for (i = 0; i != NumElems; ++i) { 4541 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4542 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4543 if (!(Elt.getNode() && 4544 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4545 break; 4546 } 4547 4548 return i; 4549} 4550 4551/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4552/// correspond consecutively to elements from one of the vector operands, 4553/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4554static 4555bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4556 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4557 unsigned NumElems, unsigned &OpNum) { 4558 bool SeenV1 = false; 4559 bool SeenV2 = false; 4560 4561 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4562 int Idx = SVOp->getMaskElt(i); 4563 // Ignore undef indicies 4564 if (Idx < 0) 4565 continue; 4566 4567 if (Idx < (int)NumElems) 4568 SeenV1 = true; 4569 else 4570 SeenV2 = true; 4571 4572 // Only accept consecutive elements from the same vector 4573 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4574 return false; 4575 } 4576 4577 OpNum = SeenV1 ? 0 : 1; 4578 return true; 4579} 4580 4581/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4582/// logical left shift of a vector. 4583static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4584 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4585 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4586 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4587 false /* check zeros from right */, DAG); 4588 unsigned OpSrc; 4589 4590 if (!NumZeros) 4591 return false; 4592 4593 // Considering the elements in the mask that are not consecutive zeros, 4594 // check if they consecutively come from only one of the source vectors. 4595 // 4596 // V1 = {X, A, B, C} 0 4597 // \ \ \ / 4598 // vector_shuffle V1, V2 <1, 2, 3, X> 4599 // 4600 if (!isShuffleMaskConsecutive(SVOp, 4601 0, // Mask Start Index 4602 NumElems-NumZeros, // Mask End Index(exclusive) 4603 NumZeros, // Where to start looking in the src vector 4604 NumElems, // Number of elements in vector 4605 OpSrc)) // Which source operand ? 4606 return false; 4607 4608 isLeft = false; 4609 ShAmt = NumZeros; 4610 ShVal = SVOp->getOperand(OpSrc); 4611 return true; 4612} 4613 4614/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4615/// logical left shift of a vector. 4616static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4617 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4618 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4619 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4620 true /* check zeros from left */, DAG); 4621 unsigned OpSrc; 4622 4623 if (!NumZeros) 4624 return false; 4625 4626 // Considering the elements in the mask that are not consecutive zeros, 4627 // check if they consecutively come from only one of the source vectors. 4628 // 4629 // 0 { A, B, X, X } = V2 4630 // / \ / / 4631 // vector_shuffle V1, V2 <X, X, 4, 5> 4632 // 4633 if (!isShuffleMaskConsecutive(SVOp, 4634 NumZeros, // Mask Start Index 4635 NumElems, // Mask End Index(exclusive) 4636 0, // Where to start looking in the src vector 4637 NumElems, // Number of elements in vector 4638 OpSrc)) // Which source operand ? 4639 return false; 4640 4641 isLeft = true; 4642 ShAmt = NumZeros; 4643 ShVal = SVOp->getOperand(OpSrc); 4644 return true; 4645} 4646 4647/// isVectorShift - Returns true if the shuffle can be implemented as a 4648/// logical left or right shift of a vector. 4649static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4651 // Although the logic below support any bitwidth size, there are no 4652 // shift instructions which handle more than 128-bit vectors. 4653 if (SVOp->getValueType(0).getSizeInBits() > 128) 4654 return false; 4655 4656 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4657 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4658 return true; 4659 4660 return false; 4661} 4662 4663/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4664/// 4665static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4666 unsigned NumNonZero, unsigned NumZero, 4667 SelectionDAG &DAG, 4668 const X86Subtarget* Subtarget, 4669 const TargetLowering &TLI) { 4670 if (NumNonZero > 8) 4671 return SDValue(); 4672 4673 DebugLoc dl = Op.getDebugLoc(); 4674 SDValue V(0, 0); 4675 bool First = true; 4676 for (unsigned i = 0; i < 16; ++i) { 4677 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4678 if (ThisIsNonZero && First) { 4679 if (NumZero) 4680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4681 else 4682 V = DAG.getUNDEF(MVT::v8i16); 4683 First = false; 4684 } 4685 4686 if ((i & 1) != 0) { 4687 SDValue ThisElt(0, 0), LastElt(0, 0); 4688 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4689 if (LastIsNonZero) { 4690 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4691 MVT::i16, Op.getOperand(i-1)); 4692 } 4693 if (ThisIsNonZero) { 4694 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4695 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4696 ThisElt, DAG.getConstant(8, MVT::i8)); 4697 if (LastIsNonZero) 4698 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4699 } else 4700 ThisElt = LastElt; 4701 4702 if (ThisElt.getNode()) 4703 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4704 DAG.getIntPtrConstant(i/2)); 4705 } 4706 } 4707 4708 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4709} 4710 4711/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4712/// 4713static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4714 unsigned NumNonZero, unsigned NumZero, 4715 SelectionDAG &DAG, 4716 const X86Subtarget* Subtarget, 4717 const TargetLowering &TLI) { 4718 if (NumNonZero > 4) 4719 return SDValue(); 4720 4721 DebugLoc dl = Op.getDebugLoc(); 4722 SDValue V(0, 0); 4723 bool First = true; 4724 for (unsigned i = 0; i < 8; ++i) { 4725 bool isNonZero = (NonZeros & (1 << i)) != 0; 4726 if (isNonZero) { 4727 if (First) { 4728 if (NumZero) 4729 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4730 else 4731 V = DAG.getUNDEF(MVT::v8i16); 4732 First = false; 4733 } 4734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4735 MVT::v8i16, V, Op.getOperand(i), 4736 DAG.getIntPtrConstant(i)); 4737 } 4738 } 4739 4740 return V; 4741} 4742 4743/// getVShift - Return a vector logical shift node. 4744/// 4745static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4746 unsigned NumBits, SelectionDAG &DAG, 4747 const TargetLowering &TLI, DebugLoc dl) { 4748 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4749 EVT ShVT = MVT::v2i64; 4750 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4751 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4752 return DAG.getNode(ISD::BITCAST, dl, VT, 4753 DAG.getNode(Opc, dl, ShVT, SrcOp, 4754 DAG.getConstant(NumBits, 4755 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4756} 4757 4758SDValue 4759X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4760 SelectionDAG &DAG) const { 4761 4762 // Check if the scalar load can be widened into a vector load. And if 4763 // the address is "base + cst" see if the cst can be "absorbed" into 4764 // the shuffle mask. 4765 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4766 SDValue Ptr = LD->getBasePtr(); 4767 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4768 return SDValue(); 4769 EVT PVT = LD->getValueType(0); 4770 if (PVT != MVT::i32 && PVT != MVT::f32) 4771 return SDValue(); 4772 4773 int FI = -1; 4774 int64_t Offset = 0; 4775 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4776 FI = FINode->getIndex(); 4777 Offset = 0; 4778 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4779 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4780 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4781 Offset = Ptr.getConstantOperandVal(1); 4782 Ptr = Ptr.getOperand(0); 4783 } else { 4784 return SDValue(); 4785 } 4786 4787 // FIXME: 256-bit vector instructions don't require a strict alignment, 4788 // improve this code to support it better. 4789 unsigned RequiredAlign = VT.getSizeInBits()/8; 4790 SDValue Chain = LD->getChain(); 4791 // Make sure the stack object alignment is at least 16 or 32. 4792 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4793 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4794 if (MFI->isFixedObjectIndex(FI)) { 4795 // Can't change the alignment. FIXME: It's possible to compute 4796 // the exact stack offset and reference FI + adjust offset instead. 4797 // If someone *really* cares about this. That's the way to implement it. 4798 return SDValue(); 4799 } else { 4800 MFI->setObjectAlignment(FI, RequiredAlign); 4801 } 4802 } 4803 4804 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4805 // Ptr + (Offset & ~15). 4806 if (Offset < 0) 4807 return SDValue(); 4808 if ((Offset % RequiredAlign) & 3) 4809 return SDValue(); 4810 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4811 if (StartOffset) 4812 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4813 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4814 4815 int EltNo = (Offset - StartOffset) >> 2; 4816 unsigned NumElems = VT.getVectorNumElements(); 4817 4818 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4819 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4820 LD->getPointerInfo().getWithOffset(StartOffset), 4821 false, false, false, 0); 4822 4823 SmallVector<int, 8> Mask; 4824 for (unsigned i = 0; i != NumElems; ++i) 4825 Mask.push_back(EltNo); 4826 4827 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4828 } 4829 4830 return SDValue(); 4831} 4832 4833/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4834/// vector of type 'VT', see if the elements can be replaced by a single large 4835/// load which has the same value as a build_vector whose operands are 'elts'. 4836/// 4837/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4838/// 4839/// FIXME: we'd also like to handle the case where the last elements are zero 4840/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4841/// There's even a handy isZeroNode for that purpose. 4842static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4843 DebugLoc &DL, SelectionDAG &DAG) { 4844 EVT EltVT = VT.getVectorElementType(); 4845 unsigned NumElems = Elts.size(); 4846 4847 LoadSDNode *LDBase = NULL; 4848 unsigned LastLoadedElt = -1U; 4849 4850 // For each element in the initializer, see if we've found a load or an undef. 4851 // If we don't find an initial load element, or later load elements are 4852 // non-consecutive, bail out. 4853 for (unsigned i = 0; i < NumElems; ++i) { 4854 SDValue Elt = Elts[i]; 4855 4856 if (!Elt.getNode() || 4857 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4858 return SDValue(); 4859 if (!LDBase) { 4860 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4861 return SDValue(); 4862 LDBase = cast<LoadSDNode>(Elt.getNode()); 4863 LastLoadedElt = i; 4864 continue; 4865 } 4866 if (Elt.getOpcode() == ISD::UNDEF) 4867 continue; 4868 4869 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4870 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4871 return SDValue(); 4872 LastLoadedElt = i; 4873 } 4874 4875 // If we have found an entire vector of loads and undefs, then return a large 4876 // load of the entire vector width starting at the base pointer. If we found 4877 // consecutive loads for the low half, generate a vzext_load node. 4878 if (LastLoadedElt == NumElems - 1) { 4879 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4880 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4881 LDBase->getPointerInfo(), 4882 LDBase->isVolatile(), LDBase->isNonTemporal(), 4883 LDBase->isInvariant(), 0); 4884 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4885 LDBase->getPointerInfo(), 4886 LDBase->isVolatile(), LDBase->isNonTemporal(), 4887 LDBase->isInvariant(), LDBase->getAlignment()); 4888 } 4889 if (NumElems == 4 && LastLoadedElt == 1 && 4890 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4891 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4892 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4893 SDValue ResNode = 4894 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4895 LDBase->getPointerInfo(), 4896 LDBase->getAlignment(), 4897 false/*isVolatile*/, true/*ReadMem*/, 4898 false/*WriteMem*/); 4899 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4900 } 4901 return SDValue(); 4902} 4903 4904/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4905/// to generate a splat value for the following cases: 4906/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4907/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4908/// a scalar load, or a constant. 4909/// The VBROADCAST node is returned when a pattern is found, 4910/// or SDValue() otherwise. 4911SDValue 4912X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4913 if (!Subtarget->hasAVX()) 4914 return SDValue(); 4915 4916 EVT VT = Op.getValueType(); 4917 DebugLoc dl = Op.getDebugLoc(); 4918 4919 SDValue Ld; 4920 bool ConstSplatVal; 4921 4922 switch (Op.getOpcode()) { 4923 default: 4924 // Unknown pattern found. 4925 return SDValue(); 4926 4927 case ISD::BUILD_VECTOR: { 4928 // The BUILD_VECTOR node must be a splat. 4929 if (!isSplatVector(Op.getNode())) 4930 return SDValue(); 4931 4932 Ld = Op.getOperand(0); 4933 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4934 Ld.getOpcode() == ISD::ConstantFP); 4935 4936 // The suspected load node has several users. Make sure that all 4937 // of its users are from the BUILD_VECTOR node. 4938 // Constants may have multiple users. 4939 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4940 return SDValue(); 4941 break; 4942 } 4943 4944 case ISD::VECTOR_SHUFFLE: { 4945 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4946 4947 // Shuffles must have a splat mask where the first element is 4948 // broadcasted. 4949 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4950 return SDValue(); 4951 4952 SDValue Sc = Op.getOperand(0); 4953 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4954 return SDValue(); 4955 4956 Ld = Sc.getOperand(0); 4957 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4958 Ld.getOpcode() == ISD::ConstantFP); 4959 4960 // The scalar_to_vector node and the suspected 4961 // load node must have exactly one user. 4962 // Constants may have multiple users. 4963 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4964 return SDValue(); 4965 break; 4966 } 4967 } 4968 4969 bool Is256 = VT.getSizeInBits() == 256; 4970 bool Is128 = VT.getSizeInBits() == 128; 4971 4972 // Handle the broadcasting a single constant scalar from the constant pool 4973 // into a vector. On Sandybridge it is still better to load a constant vector 4974 // from the constant pool and not to broadcast it from a scalar. 4975 if (ConstSplatVal && Subtarget->hasAVX2()) { 4976 EVT CVT = Ld.getValueType(); 4977 assert(!CVT.isVector() && "Must not broadcast a vector type"); 4978 unsigned ScalarSize = CVT.getSizeInBits(); 4979 4980 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) || 4981 (Is128 && (ScalarSize == 32))) { 4982 4983 const Constant *C = 0; 4984 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 4985 C = CI->getConstantIntValue(); 4986 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 4987 C = CF->getConstantFPValue(); 4988 4989 assert(C && "Invalid constant type"); 4990 4991 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 4992 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 4993 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 4994 MachinePointerInfo::getConstantPool(), 4995 false, false, false, Alignment); 4996 4997 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4998 } 4999 } 5000 5001 // The scalar source must be a normal load. 5002 if (!ISD::isNormalLoad(Ld.getNode())) 5003 return SDValue(); 5004 5005 // Reject loads that have uses of the chain result 5006 if (Ld->hasAnyUseOfValue(1)) 5007 return SDValue(); 5008 5009 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5010 5011 // VBroadcast to YMM 5012 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5013 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5014 5015 // VBroadcast to XMM 5016 if (Is128 && (ScalarSize == 32)) 5017 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5018 5019 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5020 // double since there is vbroadcastsd xmm 5021 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5022 // VBroadcast to YMM 5023 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5024 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5025 5026 // VBroadcast to XMM 5027 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5028 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5029 } 5030 5031 // Unsupported broadcast. 5032 return SDValue(); 5033} 5034 5035SDValue 5036X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5037 DebugLoc dl = Op.getDebugLoc(); 5038 5039 EVT VT = Op.getValueType(); 5040 EVT ExtVT = VT.getVectorElementType(); 5041 unsigned NumElems = Op.getNumOperands(); 5042 5043 // Vectors containing all zeros can be matched by pxor and xorps later 5044 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5045 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5046 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5047 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5048 return Op; 5049 5050 return getZeroVector(VT, Subtarget, DAG, dl); 5051 } 5052 5053 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5054 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5055 // vpcmpeqd on 256-bit vectors. 5056 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5057 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5058 return Op; 5059 5060 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5061 } 5062 5063 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5064 if (Broadcast.getNode()) 5065 return Broadcast; 5066 5067 unsigned EVTBits = ExtVT.getSizeInBits(); 5068 5069 unsigned NumZero = 0; 5070 unsigned NumNonZero = 0; 5071 unsigned NonZeros = 0; 5072 bool IsAllConstants = true; 5073 SmallSet<SDValue, 8> Values; 5074 for (unsigned i = 0; i < NumElems; ++i) { 5075 SDValue Elt = Op.getOperand(i); 5076 if (Elt.getOpcode() == ISD::UNDEF) 5077 continue; 5078 Values.insert(Elt); 5079 if (Elt.getOpcode() != ISD::Constant && 5080 Elt.getOpcode() != ISD::ConstantFP) 5081 IsAllConstants = false; 5082 if (X86::isZeroNode(Elt)) 5083 NumZero++; 5084 else { 5085 NonZeros |= (1 << i); 5086 NumNonZero++; 5087 } 5088 } 5089 5090 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5091 if (NumNonZero == 0) 5092 return DAG.getUNDEF(VT); 5093 5094 // Special case for single non-zero, non-undef, element. 5095 if (NumNonZero == 1) { 5096 unsigned Idx = CountTrailingZeros_32(NonZeros); 5097 SDValue Item = Op.getOperand(Idx); 5098 5099 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5100 // the value are obviously zero, truncate the value to i32 and do the 5101 // insertion that way. Only do this if the value is non-constant or if the 5102 // value is a constant being inserted into element 0. It is cheaper to do 5103 // a constant pool load than it is to do a movd + shuffle. 5104 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5105 (!IsAllConstants || Idx == 0)) { 5106 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5107 // Handle SSE only. 5108 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5109 EVT VecVT = MVT::v4i32; 5110 unsigned VecElts = 4; 5111 5112 // Truncate the value (which may itself be a constant) to i32, and 5113 // convert it to a vector with movd (S2V+shuffle to zero extend). 5114 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5115 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5116 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5117 5118 // Now we have our 32-bit value zero extended in the low element of 5119 // a vector. If Idx != 0, swizzle it into place. 5120 if (Idx != 0) { 5121 SmallVector<int, 4> Mask; 5122 Mask.push_back(Idx); 5123 for (unsigned i = 1; i != VecElts; ++i) 5124 Mask.push_back(i); 5125 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5126 &Mask[0]); 5127 } 5128 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5129 } 5130 } 5131 5132 // If we have a constant or non-constant insertion into the low element of 5133 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5134 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5135 // depending on what the source datatype is. 5136 if (Idx == 0) { 5137 if (NumZero == 0) 5138 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5139 5140 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5141 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5142 if (VT.getSizeInBits() == 256) { 5143 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5144 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5145 Item, DAG.getIntPtrConstant(0)); 5146 } 5147 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5149 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5150 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5151 } 5152 5153 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5154 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5156 if (VT.getSizeInBits() == 256) { 5157 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5158 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5159 } else { 5160 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5161 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5162 } 5163 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5164 } 5165 } 5166 5167 // Is it a vector logical left shift? 5168 if (NumElems == 2 && Idx == 1 && 5169 X86::isZeroNode(Op.getOperand(0)) && 5170 !X86::isZeroNode(Op.getOperand(1))) { 5171 unsigned NumBits = VT.getSizeInBits(); 5172 return getVShift(true, VT, 5173 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5174 VT, Op.getOperand(1)), 5175 NumBits/2, DAG, *this, dl); 5176 } 5177 5178 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5179 return SDValue(); 5180 5181 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5182 // is a non-constant being inserted into an element other than the low one, 5183 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5184 // movd/movss) to move this into the low element, then shuffle it into 5185 // place. 5186 if (EVTBits == 32) { 5187 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5188 5189 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5190 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5191 SmallVector<int, 8> MaskVec; 5192 for (unsigned i = 0; i < NumElems; i++) 5193 MaskVec.push_back(i == Idx ? 0 : 1); 5194 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5195 } 5196 } 5197 5198 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5199 if (Values.size() == 1) { 5200 if (EVTBits == 32) { 5201 // Instead of a shuffle like this: 5202 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5203 // Check if it's possible to issue this instead. 5204 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5205 unsigned Idx = CountTrailingZeros_32(NonZeros); 5206 SDValue Item = Op.getOperand(Idx); 5207 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5208 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5209 } 5210 return SDValue(); 5211 } 5212 5213 // A vector full of immediates; various special cases are already 5214 // handled, so this is best done with a single constant-pool load. 5215 if (IsAllConstants) 5216 return SDValue(); 5217 5218 // For AVX-length vectors, build the individual 128-bit pieces and use 5219 // shuffles to put them in place. 5220 if (VT.getSizeInBits() == 256) { 5221 SmallVector<SDValue, 32> V; 5222 for (unsigned i = 0; i != NumElems; ++i) 5223 V.push_back(Op.getOperand(i)); 5224 5225 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5226 5227 // Build both the lower and upper subvector. 5228 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5229 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5230 NumElems/2); 5231 5232 // Recreate the wider vector with the lower and upper part. 5233 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5234 } 5235 5236 // Let legalizer expand 2-wide build_vectors. 5237 if (EVTBits == 64) { 5238 if (NumNonZero == 1) { 5239 // One half is zero or undef. 5240 unsigned Idx = CountTrailingZeros_32(NonZeros); 5241 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5242 Op.getOperand(Idx)); 5243 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5244 } 5245 return SDValue(); 5246 } 5247 5248 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5249 if (EVTBits == 8 && NumElems == 16) { 5250 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5251 Subtarget, *this); 5252 if (V.getNode()) return V; 5253 } 5254 5255 if (EVTBits == 16 && NumElems == 8) { 5256 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5257 Subtarget, *this); 5258 if (V.getNode()) return V; 5259 } 5260 5261 // If element VT is == 32 bits, turn it into a number of shuffles. 5262 SmallVector<SDValue, 8> V(NumElems); 5263 if (NumElems == 4 && NumZero > 0) { 5264 for (unsigned i = 0; i < 4; ++i) { 5265 bool isZero = !(NonZeros & (1 << i)); 5266 if (isZero) 5267 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5268 else 5269 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5270 } 5271 5272 for (unsigned i = 0; i < 2; ++i) { 5273 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5274 default: break; 5275 case 0: 5276 V[i] = V[i*2]; // Must be a zero vector. 5277 break; 5278 case 1: 5279 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5280 break; 5281 case 2: 5282 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5283 break; 5284 case 3: 5285 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5286 break; 5287 } 5288 } 5289 5290 bool Reverse1 = (NonZeros & 0x3) == 2; 5291 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5292 int MaskVec[] = { 5293 Reverse1 ? 1 : 0, 5294 Reverse1 ? 0 : 1, 5295 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5296 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5297 }; 5298 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5299 } 5300 5301 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5302 // Check for a build vector of consecutive loads. 5303 for (unsigned i = 0; i < NumElems; ++i) 5304 V[i] = Op.getOperand(i); 5305 5306 // Check for elements which are consecutive loads. 5307 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5308 if (LD.getNode()) 5309 return LD; 5310 5311 // For SSE 4.1, use insertps to put the high elements into the low element. 5312 if (getSubtarget()->hasSSE41()) { 5313 SDValue Result; 5314 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5315 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5316 else 5317 Result = DAG.getUNDEF(VT); 5318 5319 for (unsigned i = 1; i < NumElems; ++i) { 5320 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5321 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5322 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5323 } 5324 return Result; 5325 } 5326 5327 // Otherwise, expand into a number of unpckl*, start by extending each of 5328 // our (non-undef) elements to the full vector width with the element in the 5329 // bottom slot of the vector (which generates no code for SSE). 5330 for (unsigned i = 0; i < NumElems; ++i) { 5331 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5332 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5333 else 5334 V[i] = DAG.getUNDEF(VT); 5335 } 5336 5337 // Next, we iteratively mix elements, e.g. for v4f32: 5338 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5339 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5340 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5341 unsigned EltStride = NumElems >> 1; 5342 while (EltStride != 0) { 5343 for (unsigned i = 0; i < EltStride; ++i) { 5344 // If V[i+EltStride] is undef and this is the first round of mixing, 5345 // then it is safe to just drop this shuffle: V[i] is already in the 5346 // right place, the one element (since it's the first round) being 5347 // inserted as undef can be dropped. This isn't safe for successive 5348 // rounds because they will permute elements within both vectors. 5349 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5350 EltStride == NumElems/2) 5351 continue; 5352 5353 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5354 } 5355 EltStride >>= 1; 5356 } 5357 return V[0]; 5358 } 5359 return SDValue(); 5360} 5361 5362// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5363// them in a MMX register. This is better than doing a stack convert. 5364static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5365 DebugLoc dl = Op.getDebugLoc(); 5366 EVT ResVT = Op.getValueType(); 5367 5368 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5369 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5370 int Mask[2]; 5371 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5372 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5373 InVec = Op.getOperand(1); 5374 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5375 unsigned NumElts = ResVT.getVectorNumElements(); 5376 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5377 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5378 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5379 } else { 5380 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5381 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5382 Mask[0] = 0; Mask[1] = 2; 5383 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5384 } 5385 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5386} 5387 5388// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5389// to create 256-bit vectors from two other 128-bit ones. 5390static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5391 DebugLoc dl = Op.getDebugLoc(); 5392 EVT ResVT = Op.getValueType(); 5393 5394 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5395 5396 SDValue V1 = Op.getOperand(0); 5397 SDValue V2 = Op.getOperand(1); 5398 unsigned NumElems = ResVT.getVectorNumElements(); 5399 5400 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5401} 5402 5403SDValue 5404X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5405 EVT ResVT = Op.getValueType(); 5406 5407 assert(Op.getNumOperands() == 2); 5408 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5409 "Unsupported CONCAT_VECTORS for value type"); 5410 5411 // We support concatenate two MMX registers and place them in a MMX register. 5412 // This is better than doing a stack convert. 5413 if (ResVT.is128BitVector()) 5414 return LowerMMXCONCAT_VECTORS(Op, DAG); 5415 5416 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5417 // from two other 128-bit ones. 5418 return LowerAVXCONCAT_VECTORS(Op, DAG); 5419} 5420 5421// Try to lower a shuffle node into a simple blend instruction. 5422static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5423 const X86Subtarget *Subtarget, 5424 SelectionDAG &DAG) { 5425 SDValue V1 = SVOp->getOperand(0); 5426 SDValue V2 = SVOp->getOperand(1); 5427 DebugLoc dl = SVOp->getDebugLoc(); 5428 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5429 unsigned NumElems = VT.getVectorNumElements(); 5430 5431 if (!Subtarget->hasSSE41()) 5432 return SDValue(); 5433 5434 unsigned ISDNo = 0; 5435 MVT OpTy; 5436 5437 switch (VT.SimpleTy) { 5438 default: return SDValue(); 5439 case MVT::v8i16: 5440 ISDNo = X86ISD::BLENDPW; 5441 OpTy = MVT::v8i16; 5442 break; 5443 case MVT::v4i32: 5444 case MVT::v4f32: 5445 ISDNo = X86ISD::BLENDPS; 5446 OpTy = MVT::v4f32; 5447 break; 5448 case MVT::v2i64: 5449 case MVT::v2f64: 5450 ISDNo = X86ISD::BLENDPD; 5451 OpTy = MVT::v2f64; 5452 break; 5453 case MVT::v8i32: 5454 case MVT::v8f32: 5455 if (!Subtarget->hasAVX()) 5456 return SDValue(); 5457 ISDNo = X86ISD::BLENDPS; 5458 OpTy = MVT::v8f32; 5459 break; 5460 case MVT::v4i64: 5461 case MVT::v4f64: 5462 if (!Subtarget->hasAVX()) 5463 return SDValue(); 5464 ISDNo = X86ISD::BLENDPD; 5465 OpTy = MVT::v4f64; 5466 break; 5467 } 5468 assert(ISDNo && "Invalid Op Number"); 5469 5470 unsigned MaskVals = 0; 5471 5472 for (unsigned i = 0; i != NumElems; ++i) { 5473 int EltIdx = SVOp->getMaskElt(i); 5474 if (EltIdx == (int)i || EltIdx < 0) 5475 MaskVals |= (1<<i); 5476 else if (EltIdx == (int)(i + NumElems)) 5477 continue; // Bit is set to zero; 5478 else 5479 return SDValue(); 5480 } 5481 5482 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5483 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5484 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5485 DAG.getConstant(MaskVals, MVT::i32)); 5486 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5487} 5488 5489// v8i16 shuffles - Prefer shuffles in the following order: 5490// 1. [all] pshuflw, pshufhw, optional move 5491// 2. [ssse3] 1 x pshufb 5492// 3. [ssse3] 2 x pshufb + 1 x por 5493// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5494SDValue 5495X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5496 SelectionDAG &DAG) const { 5497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5498 SDValue V1 = SVOp->getOperand(0); 5499 SDValue V2 = SVOp->getOperand(1); 5500 DebugLoc dl = SVOp->getDebugLoc(); 5501 SmallVector<int, 8> MaskVals; 5502 5503 // Determine if more than 1 of the words in each of the low and high quadwords 5504 // of the result come from the same quadword of one of the two inputs. Undef 5505 // mask values count as coming from any quadword, for better codegen. 5506 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5507 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5508 std::bitset<4> InputQuads; 5509 for (unsigned i = 0; i < 8; ++i) { 5510 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5511 int EltIdx = SVOp->getMaskElt(i); 5512 MaskVals.push_back(EltIdx); 5513 if (EltIdx < 0) { 5514 ++Quad[0]; 5515 ++Quad[1]; 5516 ++Quad[2]; 5517 ++Quad[3]; 5518 continue; 5519 } 5520 ++Quad[EltIdx / 4]; 5521 InputQuads.set(EltIdx / 4); 5522 } 5523 5524 int BestLoQuad = -1; 5525 unsigned MaxQuad = 1; 5526 for (unsigned i = 0; i < 4; ++i) { 5527 if (LoQuad[i] > MaxQuad) { 5528 BestLoQuad = i; 5529 MaxQuad = LoQuad[i]; 5530 } 5531 } 5532 5533 int BestHiQuad = -1; 5534 MaxQuad = 1; 5535 for (unsigned i = 0; i < 4; ++i) { 5536 if (HiQuad[i] > MaxQuad) { 5537 BestHiQuad = i; 5538 MaxQuad = HiQuad[i]; 5539 } 5540 } 5541 5542 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5543 // of the two input vectors, shuffle them into one input vector so only a 5544 // single pshufb instruction is necessary. If There are more than 2 input 5545 // quads, disable the next transformation since it does not help SSSE3. 5546 bool V1Used = InputQuads[0] || InputQuads[1]; 5547 bool V2Used = InputQuads[2] || InputQuads[3]; 5548 if (Subtarget->hasSSSE3()) { 5549 if (InputQuads.count() == 2 && V1Used && V2Used) { 5550 BestLoQuad = InputQuads[0] ? 0 : 1; 5551 BestHiQuad = InputQuads[2] ? 2 : 3; 5552 } 5553 if (InputQuads.count() > 2) { 5554 BestLoQuad = -1; 5555 BestHiQuad = -1; 5556 } 5557 } 5558 5559 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5560 // the shuffle mask. If a quad is scored as -1, that means that it contains 5561 // words from all 4 input quadwords. 5562 SDValue NewV; 5563 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5564 int MaskV[] = { 5565 BestLoQuad < 0 ? 0 : BestLoQuad, 5566 BestHiQuad < 0 ? 1 : BestHiQuad 5567 }; 5568 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5569 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5571 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5572 5573 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5574 // source words for the shuffle, to aid later transformations. 5575 bool AllWordsInNewV = true; 5576 bool InOrder[2] = { true, true }; 5577 for (unsigned i = 0; i != 8; ++i) { 5578 int idx = MaskVals[i]; 5579 if (idx != (int)i) 5580 InOrder[i/4] = false; 5581 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5582 continue; 5583 AllWordsInNewV = false; 5584 break; 5585 } 5586 5587 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5588 if (AllWordsInNewV) { 5589 for (int i = 0; i != 8; ++i) { 5590 int idx = MaskVals[i]; 5591 if (idx < 0) 5592 continue; 5593 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5594 if ((idx != i) && idx < 4) 5595 pshufhw = false; 5596 if ((idx != i) && idx > 3) 5597 pshuflw = false; 5598 } 5599 V1 = NewV; 5600 V2Used = false; 5601 BestLoQuad = 0; 5602 BestHiQuad = 1; 5603 } 5604 5605 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5606 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5607 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5608 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5609 unsigned TargetMask = 0; 5610 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5611 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5612 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5613 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5614 getShufflePSHUFLWImmediate(SVOp); 5615 V1 = NewV.getOperand(0); 5616 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5617 } 5618 } 5619 5620 // If we have SSSE3, and all words of the result are from 1 input vector, 5621 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5622 // is present, fall back to case 4. 5623 if (Subtarget->hasSSSE3()) { 5624 SmallVector<SDValue,16> pshufbMask; 5625 5626 // If we have elements from both input vectors, set the high bit of the 5627 // shuffle mask element to zero out elements that come from V2 in the V1 5628 // mask, and elements that come from V1 in the V2 mask, so that the two 5629 // results can be OR'd together. 5630 bool TwoInputs = V1Used && V2Used; 5631 for (unsigned i = 0; i != 8; ++i) { 5632 int EltIdx = MaskVals[i] * 2; 5633 if (TwoInputs && (EltIdx >= 16)) { 5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5636 continue; 5637 } 5638 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5639 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5640 } 5641 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5642 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5643 DAG.getNode(ISD::BUILD_VECTOR, dl, 5644 MVT::v16i8, &pshufbMask[0], 16)); 5645 if (!TwoInputs) 5646 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5647 5648 // Calculate the shuffle mask for the second input, shuffle it, and 5649 // OR it with the first shuffled input. 5650 pshufbMask.clear(); 5651 for (unsigned i = 0; i != 8; ++i) { 5652 int EltIdx = MaskVals[i] * 2; 5653 if (EltIdx < 16) { 5654 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5655 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5656 continue; 5657 } 5658 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5659 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5660 } 5661 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5662 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5663 DAG.getNode(ISD::BUILD_VECTOR, dl, 5664 MVT::v16i8, &pshufbMask[0], 16)); 5665 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5666 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5667 } 5668 5669 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5670 // and update MaskVals with new element order. 5671 std::bitset<8> InOrder; 5672 if (BestLoQuad >= 0) { 5673 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5674 for (int i = 0; i != 4; ++i) { 5675 int idx = MaskVals[i]; 5676 if (idx < 0) { 5677 InOrder.set(i); 5678 } else if ((idx / 4) == BestLoQuad) { 5679 MaskV[i] = idx & 3; 5680 InOrder.set(i); 5681 } 5682 } 5683 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5684 &MaskV[0]); 5685 5686 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5688 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5689 NewV.getOperand(0), 5690 getShufflePSHUFLWImmediate(SVOp), DAG); 5691 } 5692 } 5693 5694 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5695 // and update MaskVals with the new element order. 5696 if (BestHiQuad >= 0) { 5697 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5698 for (unsigned i = 4; i != 8; ++i) { 5699 int idx = MaskVals[i]; 5700 if (idx < 0) { 5701 InOrder.set(i); 5702 } else if ((idx / 4) == BestHiQuad) { 5703 MaskV[i] = (idx & 3) + 4; 5704 InOrder.set(i); 5705 } 5706 } 5707 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5708 &MaskV[0]); 5709 5710 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5712 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5713 NewV.getOperand(0), 5714 getShufflePSHUFHWImmediate(SVOp), DAG); 5715 } 5716 } 5717 5718 // In case BestHi & BestLo were both -1, which means each quadword has a word 5719 // from each of the four input quadwords, calculate the InOrder bitvector now 5720 // before falling through to the insert/extract cleanup. 5721 if (BestLoQuad == -1 && BestHiQuad == -1) { 5722 NewV = V1; 5723 for (int i = 0; i != 8; ++i) 5724 if (MaskVals[i] < 0 || MaskVals[i] == i) 5725 InOrder.set(i); 5726 } 5727 5728 // The other elements are put in the right place using pextrw and pinsrw. 5729 for (unsigned i = 0; i != 8; ++i) { 5730 if (InOrder[i]) 5731 continue; 5732 int EltIdx = MaskVals[i]; 5733 if (EltIdx < 0) 5734 continue; 5735 SDValue ExtOp = (EltIdx < 8) 5736 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5737 DAG.getIntPtrConstant(EltIdx)) 5738 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5739 DAG.getIntPtrConstant(EltIdx - 8)); 5740 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5741 DAG.getIntPtrConstant(i)); 5742 } 5743 return NewV; 5744} 5745 5746// v16i8 shuffles - Prefer shuffles in the following order: 5747// 1. [ssse3] 1 x pshufb 5748// 2. [ssse3] 2 x pshufb + 1 x por 5749// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5750static 5751SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5752 SelectionDAG &DAG, 5753 const X86TargetLowering &TLI) { 5754 SDValue V1 = SVOp->getOperand(0); 5755 SDValue V2 = SVOp->getOperand(1); 5756 DebugLoc dl = SVOp->getDebugLoc(); 5757 ArrayRef<int> MaskVals = SVOp->getMask(); 5758 5759 // If we have SSSE3, case 1 is generated when all result bytes come from 5760 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5761 // present, fall back to case 3. 5762 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5763 bool V1Only = true; 5764 bool V2Only = true; 5765 for (unsigned i = 0; i < 16; ++i) { 5766 int EltIdx = MaskVals[i]; 5767 if (EltIdx < 0) 5768 continue; 5769 if (EltIdx < 16) 5770 V2Only = false; 5771 else 5772 V1Only = false; 5773 } 5774 5775 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5776 if (TLI.getSubtarget()->hasSSSE3()) { 5777 SmallVector<SDValue,16> pshufbMask; 5778 5779 // If all result elements are from one input vector, then only translate 5780 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5781 // 5782 // Otherwise, we have elements from both input vectors, and must zero out 5783 // elements that come from V2 in the first mask, and V1 in the second mask 5784 // so that we can OR them together. 5785 bool TwoInputs = !(V1Only || V2Only); 5786 for (unsigned i = 0; i != 16; ++i) { 5787 int EltIdx = MaskVals[i]; 5788 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5789 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5790 continue; 5791 } 5792 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5793 } 5794 // If all the elements are from V2, assign it to V1 and return after 5795 // building the first pshufb. 5796 if (V2Only) 5797 V1 = V2; 5798 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5799 DAG.getNode(ISD::BUILD_VECTOR, dl, 5800 MVT::v16i8, &pshufbMask[0], 16)); 5801 if (!TwoInputs) 5802 return V1; 5803 5804 // Calculate the shuffle mask for the second input, shuffle it, and 5805 // OR it with the first shuffled input. 5806 pshufbMask.clear(); 5807 for (unsigned i = 0; i != 16; ++i) { 5808 int EltIdx = MaskVals[i]; 5809 if (EltIdx < 16) { 5810 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5811 continue; 5812 } 5813 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5814 } 5815 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5816 DAG.getNode(ISD::BUILD_VECTOR, dl, 5817 MVT::v16i8, &pshufbMask[0], 16)); 5818 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5819 } 5820 5821 // No SSSE3 - Calculate in place words and then fix all out of place words 5822 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5823 // the 16 different words that comprise the two doublequadword input vectors. 5824 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5825 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5826 SDValue NewV = V2Only ? V2 : V1; 5827 for (int i = 0; i != 8; ++i) { 5828 int Elt0 = MaskVals[i*2]; 5829 int Elt1 = MaskVals[i*2+1]; 5830 5831 // This word of the result is all undef, skip it. 5832 if (Elt0 < 0 && Elt1 < 0) 5833 continue; 5834 5835 // This word of the result is already in the correct place, skip it. 5836 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5837 continue; 5838 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5839 continue; 5840 5841 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5842 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5843 SDValue InsElt; 5844 5845 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5846 // using a single extract together, load it and store it. 5847 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5848 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5849 DAG.getIntPtrConstant(Elt1 / 2)); 5850 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5851 DAG.getIntPtrConstant(i)); 5852 continue; 5853 } 5854 5855 // If Elt1 is defined, extract it from the appropriate source. If the 5856 // source byte is not also odd, shift the extracted word left 8 bits 5857 // otherwise clear the bottom 8 bits if we need to do an or. 5858 if (Elt1 >= 0) { 5859 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5860 DAG.getIntPtrConstant(Elt1 / 2)); 5861 if ((Elt1 & 1) == 0) 5862 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5863 DAG.getConstant(8, 5864 TLI.getShiftAmountTy(InsElt.getValueType()))); 5865 else if (Elt0 >= 0) 5866 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5867 DAG.getConstant(0xFF00, MVT::i16)); 5868 } 5869 // If Elt0 is defined, extract it from the appropriate source. If the 5870 // source byte is not also even, shift the extracted word right 8 bits. If 5871 // Elt1 was also defined, OR the extracted values together before 5872 // inserting them in the result. 5873 if (Elt0 >= 0) { 5874 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5875 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5876 if ((Elt0 & 1) != 0) 5877 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5878 DAG.getConstant(8, 5879 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5880 else if (Elt1 >= 0) 5881 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5882 DAG.getConstant(0x00FF, MVT::i16)); 5883 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5884 : InsElt0; 5885 } 5886 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5887 DAG.getIntPtrConstant(i)); 5888 } 5889 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5890} 5891 5892/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5893/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5894/// done when every pair / quad of shuffle mask elements point to elements in 5895/// the right sequence. e.g. 5896/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5897static 5898SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5899 SelectionDAG &DAG, DebugLoc dl) { 5900 EVT VT = SVOp->getValueType(0); 5901 SDValue V1 = SVOp->getOperand(0); 5902 SDValue V2 = SVOp->getOperand(1); 5903 unsigned NumElems = VT.getVectorNumElements(); 5904 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5905 EVT NewVT; 5906 switch (VT.getSimpleVT().SimpleTy) { 5907 default: llvm_unreachable("Unexpected!"); 5908 case MVT::v4f32: NewVT = MVT::v2f64; break; 5909 case MVT::v4i32: NewVT = MVT::v2i64; break; 5910 case MVT::v8i16: NewVT = MVT::v4i32; break; 5911 case MVT::v16i8: NewVT = MVT::v4i32; break; 5912 } 5913 5914 int Scale = NumElems / NewWidth; 5915 SmallVector<int, 8> MaskVec; 5916 for (unsigned i = 0; i < NumElems; i += Scale) { 5917 int StartIdx = -1; 5918 for (int j = 0; j < Scale; ++j) { 5919 int EltIdx = SVOp->getMaskElt(i+j); 5920 if (EltIdx < 0) 5921 continue; 5922 if (StartIdx == -1) 5923 StartIdx = EltIdx - (EltIdx % Scale); 5924 if (EltIdx != StartIdx + j) 5925 return SDValue(); 5926 } 5927 if (StartIdx == -1) 5928 MaskVec.push_back(-1); 5929 else 5930 MaskVec.push_back(StartIdx / Scale); 5931 } 5932 5933 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5934 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5935 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5936} 5937 5938/// getVZextMovL - Return a zero-extending vector move low node. 5939/// 5940static SDValue getVZextMovL(EVT VT, EVT OpVT, 5941 SDValue SrcOp, SelectionDAG &DAG, 5942 const X86Subtarget *Subtarget, DebugLoc dl) { 5943 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5944 LoadSDNode *LD = NULL; 5945 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5946 LD = dyn_cast<LoadSDNode>(SrcOp); 5947 if (!LD) { 5948 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5949 // instead. 5950 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5951 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5952 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5953 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5954 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5955 // PR2108 5956 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5957 return DAG.getNode(ISD::BITCAST, dl, VT, 5958 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5959 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5960 OpVT, 5961 SrcOp.getOperand(0) 5962 .getOperand(0)))); 5963 } 5964 } 5965 } 5966 5967 return DAG.getNode(ISD::BITCAST, dl, VT, 5968 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5969 DAG.getNode(ISD::BITCAST, dl, 5970 OpVT, SrcOp))); 5971} 5972 5973/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5974/// which could not be matched by any known target speficic shuffle 5975static SDValue 5976LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5977 EVT VT = SVOp->getValueType(0); 5978 5979 unsigned NumElems = VT.getVectorNumElements(); 5980 unsigned NumLaneElems = NumElems / 2; 5981 5982 DebugLoc dl = SVOp->getDebugLoc(); 5983 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5984 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5985 SDValue Shufs[2]; 5986 5987 SmallVector<int, 16> Mask; 5988 for (unsigned l = 0; l < 2; ++l) { 5989 // Build a shuffle mask for the output, discovering on the fly which 5990 // input vectors to use as shuffle operands (recorded in InputUsed). 5991 // If building a suitable shuffle vector proves too hard, then bail 5992 // out with useBuildVector set. 5993 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 5994 unsigned LaneStart = l * NumLaneElems; 5995 for (unsigned i = 0; i != NumLaneElems; ++i) { 5996 // The mask element. This indexes into the input. 5997 int Idx = SVOp->getMaskElt(i+LaneStart); 5998 if (Idx < 0) { 5999 // the mask element does not index into any input vector. 6000 Mask.push_back(-1); 6001 continue; 6002 } 6003 6004 // The input vector this mask element indexes into. 6005 int Input = Idx / NumLaneElems; 6006 6007 // Turn the index into an offset from the start of the input vector. 6008 Idx -= Input * NumLaneElems; 6009 6010 // Find or create a shuffle vector operand to hold this input. 6011 unsigned OpNo; 6012 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6013 if (InputUsed[OpNo] == Input) 6014 // This input vector is already an operand. 6015 break; 6016 if (InputUsed[OpNo] < 0) { 6017 // Create a new operand for this input vector. 6018 InputUsed[OpNo] = Input; 6019 break; 6020 } 6021 } 6022 6023 if (OpNo >= array_lengthof(InputUsed)) { 6024 // More than two input vectors used! Give up. 6025 return SDValue(); 6026 } 6027 6028 // Add the mask index for the new shuffle vector. 6029 Mask.push_back(Idx + OpNo * NumLaneElems); 6030 } 6031 6032 if (InputUsed[0] < 0) { 6033 // No input vectors were used! The result is undefined. 6034 Shufs[l] = DAG.getUNDEF(NVT); 6035 } else { 6036 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6037 (InputUsed[0] % 2) * NumLaneElems, 6038 DAG, dl); 6039 // If only one input was used, use an undefined vector for the other. 6040 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6041 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6042 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6043 // At least one input vector was used. Create a new shuffle vector. 6044 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6045 } 6046 6047 Mask.clear(); 6048 } 6049 6050 // Concatenate the result back 6051 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]); 6052} 6053 6054/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6055/// 4 elements, and match them with several different shuffle types. 6056static SDValue 6057LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6058 SDValue V1 = SVOp->getOperand(0); 6059 SDValue V2 = SVOp->getOperand(1); 6060 DebugLoc dl = SVOp->getDebugLoc(); 6061 EVT VT = SVOp->getValueType(0); 6062 6063 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6064 6065 std::pair<int, int> Locs[4]; 6066 int Mask1[] = { -1, -1, -1, -1 }; 6067 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6068 6069 unsigned NumHi = 0; 6070 unsigned NumLo = 0; 6071 for (unsigned i = 0; i != 4; ++i) { 6072 int Idx = PermMask[i]; 6073 if (Idx < 0) { 6074 Locs[i] = std::make_pair(-1, -1); 6075 } else { 6076 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6077 if (Idx < 4) { 6078 Locs[i] = std::make_pair(0, NumLo); 6079 Mask1[NumLo] = Idx; 6080 NumLo++; 6081 } else { 6082 Locs[i] = std::make_pair(1, NumHi); 6083 if (2+NumHi < 4) 6084 Mask1[2+NumHi] = Idx; 6085 NumHi++; 6086 } 6087 } 6088 } 6089 6090 if (NumLo <= 2 && NumHi <= 2) { 6091 // If no more than two elements come from either vector. This can be 6092 // implemented with two shuffles. First shuffle gather the elements. 6093 // The second shuffle, which takes the first shuffle as both of its 6094 // vector operands, put the elements into the right order. 6095 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6096 6097 int Mask2[] = { -1, -1, -1, -1 }; 6098 6099 for (unsigned i = 0; i != 4; ++i) 6100 if (Locs[i].first != -1) { 6101 unsigned Idx = (i < 2) ? 0 : 4; 6102 Idx += Locs[i].first * 2 + Locs[i].second; 6103 Mask2[i] = Idx; 6104 } 6105 6106 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6107 } 6108 6109 if (NumLo == 3 || NumHi == 3) { 6110 // Otherwise, we must have three elements from one vector, call it X, and 6111 // one element from the other, call it Y. First, use a shufps to build an 6112 // intermediate vector with the one element from Y and the element from X 6113 // that will be in the same half in the final destination (the indexes don't 6114 // matter). Then, use a shufps to build the final vector, taking the half 6115 // containing the element from Y from the intermediate, and the other half 6116 // from X. 6117 if (NumHi == 3) { 6118 // Normalize it so the 3 elements come from V1. 6119 CommuteVectorShuffleMask(PermMask, 4); 6120 std::swap(V1, V2); 6121 } 6122 6123 // Find the element from V2. 6124 unsigned HiIndex; 6125 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6126 int Val = PermMask[HiIndex]; 6127 if (Val < 0) 6128 continue; 6129 if (Val >= 4) 6130 break; 6131 } 6132 6133 Mask1[0] = PermMask[HiIndex]; 6134 Mask1[1] = -1; 6135 Mask1[2] = PermMask[HiIndex^1]; 6136 Mask1[3] = -1; 6137 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6138 6139 if (HiIndex >= 2) { 6140 Mask1[0] = PermMask[0]; 6141 Mask1[1] = PermMask[1]; 6142 Mask1[2] = HiIndex & 1 ? 6 : 4; 6143 Mask1[3] = HiIndex & 1 ? 4 : 6; 6144 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6145 } 6146 6147 Mask1[0] = HiIndex & 1 ? 2 : 0; 6148 Mask1[1] = HiIndex & 1 ? 0 : 2; 6149 Mask1[2] = PermMask[2]; 6150 Mask1[3] = PermMask[3]; 6151 if (Mask1[2] >= 0) 6152 Mask1[2] += 4; 6153 if (Mask1[3] >= 0) 6154 Mask1[3] += 4; 6155 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6156 } 6157 6158 // Break it into (shuffle shuffle_hi, shuffle_lo). 6159 int LoMask[] = { -1, -1, -1, -1 }; 6160 int HiMask[] = { -1, -1, -1, -1 }; 6161 6162 int *MaskPtr = LoMask; 6163 unsigned MaskIdx = 0; 6164 unsigned LoIdx = 0; 6165 unsigned HiIdx = 2; 6166 for (unsigned i = 0; i != 4; ++i) { 6167 if (i == 2) { 6168 MaskPtr = HiMask; 6169 MaskIdx = 1; 6170 LoIdx = 0; 6171 HiIdx = 2; 6172 } 6173 int Idx = PermMask[i]; 6174 if (Idx < 0) { 6175 Locs[i] = std::make_pair(-1, -1); 6176 } else if (Idx < 4) { 6177 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6178 MaskPtr[LoIdx] = Idx; 6179 LoIdx++; 6180 } else { 6181 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6182 MaskPtr[HiIdx] = Idx; 6183 HiIdx++; 6184 } 6185 } 6186 6187 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6188 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6189 int MaskOps[] = { -1, -1, -1, -1 }; 6190 for (unsigned i = 0; i != 4; ++i) 6191 if (Locs[i].first != -1) 6192 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6193 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6194} 6195 6196static bool MayFoldVectorLoad(SDValue V) { 6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6198 V = V.getOperand(0); 6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6200 V = V.getOperand(0); 6201 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6202 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6203 // BUILD_VECTOR (load), undef 6204 V = V.getOperand(0); 6205 if (MayFoldLoad(V)) 6206 return true; 6207 return false; 6208} 6209 6210// FIXME: the version above should always be used. Since there's 6211// a bug where several vector shuffles can't be folded because the 6212// DAG is not updated during lowering and a node claims to have two 6213// uses while it only has one, use this version, and let isel match 6214// another instruction if the load really happens to have more than 6215// one use. Remove this version after this bug get fixed. 6216// rdar://8434668, PR8156 6217static bool RelaxedMayFoldVectorLoad(SDValue V) { 6218 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6219 V = V.getOperand(0); 6220 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6221 V = V.getOperand(0); 6222 if (ISD::isNormalLoad(V.getNode())) 6223 return true; 6224 return false; 6225} 6226 6227static 6228SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6229 EVT VT = Op.getValueType(); 6230 6231 // Canonizalize to v2f64. 6232 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6233 return DAG.getNode(ISD::BITCAST, dl, VT, 6234 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6235 V1, DAG)); 6236} 6237 6238static 6239SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6240 bool HasSSE2) { 6241 SDValue V1 = Op.getOperand(0); 6242 SDValue V2 = Op.getOperand(1); 6243 EVT VT = Op.getValueType(); 6244 6245 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6246 6247 if (HasSSE2 && VT == MVT::v2f64) 6248 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6249 6250 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6251 return DAG.getNode(ISD::BITCAST, dl, VT, 6252 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6253 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6254 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6255} 6256 6257static 6258SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6259 SDValue V1 = Op.getOperand(0); 6260 SDValue V2 = Op.getOperand(1); 6261 EVT VT = Op.getValueType(); 6262 6263 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6264 "unsupported shuffle type"); 6265 6266 if (V2.getOpcode() == ISD::UNDEF) 6267 V2 = V1; 6268 6269 // v4i32 or v4f32 6270 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6271} 6272 6273static 6274SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6275 SDValue V1 = Op.getOperand(0); 6276 SDValue V2 = Op.getOperand(1); 6277 EVT VT = Op.getValueType(); 6278 unsigned NumElems = VT.getVectorNumElements(); 6279 6280 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6281 // operand of these instructions is only memory, so check if there's a 6282 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6283 // same masks. 6284 bool CanFoldLoad = false; 6285 6286 // Trivial case, when V2 comes from a load. 6287 if (MayFoldVectorLoad(V2)) 6288 CanFoldLoad = true; 6289 6290 // When V1 is a load, it can be folded later into a store in isel, example: 6291 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6292 // turns into: 6293 // (MOVLPSmr addr:$src1, VR128:$src2) 6294 // So, recognize this potential and also use MOVLPS or MOVLPD 6295 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6296 CanFoldLoad = true; 6297 6298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6299 if (CanFoldLoad) { 6300 if (HasSSE2 && NumElems == 2) 6301 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6302 6303 if (NumElems == 4) 6304 // If we don't care about the second element, procede to use movss. 6305 if (SVOp->getMaskElt(1) != -1) 6306 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6307 } 6308 6309 // movl and movlp will both match v2i64, but v2i64 is never matched by 6310 // movl earlier because we make it strict to avoid messing with the movlp load 6311 // folding logic (see the code above getMOVLP call). Match it here then, 6312 // this is horrible, but will stay like this until we move all shuffle 6313 // matching to x86 specific nodes. Note that for the 1st condition all 6314 // types are matched with movsd. 6315 if (HasSSE2) { 6316 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6317 // as to remove this logic from here, as much as possible 6318 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6319 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6321 } 6322 6323 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6324 6325 // Invert the operand order and use SHUFPS to match it. 6326 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6327 getShuffleSHUFImmediate(SVOp), DAG); 6328} 6329 6330SDValue 6331X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6333 EVT VT = Op.getValueType(); 6334 DebugLoc dl = Op.getDebugLoc(); 6335 SDValue V1 = Op.getOperand(0); 6336 SDValue V2 = Op.getOperand(1); 6337 6338 if (isZeroShuffle(SVOp)) 6339 return getZeroVector(VT, Subtarget, DAG, dl); 6340 6341 // Handle splat operations 6342 if (SVOp->isSplat()) { 6343 unsigned NumElem = VT.getVectorNumElements(); 6344 int Size = VT.getSizeInBits(); 6345 6346 // Use vbroadcast whenever the splat comes from a foldable load 6347 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6348 if (Broadcast.getNode()) 6349 return Broadcast; 6350 6351 // Handle splats by matching through known shuffle masks 6352 if ((Size == 128 && NumElem <= 4) || 6353 (Size == 256 && NumElem < 8)) 6354 return SDValue(); 6355 6356 // All remaning splats are promoted to target supported vector shuffles. 6357 return PromoteSplat(SVOp, DAG); 6358 } 6359 6360 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6361 // do it! 6362 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6363 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6364 if (NewOp.getNode()) 6365 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6366 } else if ((VT == MVT::v4i32 || 6367 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6368 // FIXME: Figure out a cleaner way to do this. 6369 // Try to make use of movq to zero out the top part. 6370 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6371 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6372 if (NewOp.getNode()) { 6373 EVT NewVT = NewOp.getValueType(); 6374 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6375 NewVT, true, false)) 6376 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6377 DAG, Subtarget, dl); 6378 } 6379 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6380 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6381 if (NewOp.getNode()) { 6382 EVT NewVT = NewOp.getValueType(); 6383 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6384 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6385 DAG, Subtarget, dl); 6386 } 6387 } 6388 } 6389 return SDValue(); 6390} 6391 6392SDValue 6393X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6395 SDValue V1 = Op.getOperand(0); 6396 SDValue V2 = Op.getOperand(1); 6397 EVT VT = Op.getValueType(); 6398 DebugLoc dl = Op.getDebugLoc(); 6399 unsigned NumElems = VT.getVectorNumElements(); 6400 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6401 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6402 bool V1IsSplat = false; 6403 bool V2IsSplat = false; 6404 bool HasSSE2 = Subtarget->hasSSE2(); 6405 bool HasAVX = Subtarget->hasAVX(); 6406 bool HasAVX2 = Subtarget->hasAVX2(); 6407 MachineFunction &MF = DAG.getMachineFunction(); 6408 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6409 6410 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6411 6412 if (V1IsUndef && V2IsUndef) 6413 return DAG.getUNDEF(VT); 6414 6415 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6416 6417 // Vector shuffle lowering takes 3 steps: 6418 // 6419 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6420 // narrowing and commutation of operands should be handled. 6421 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6422 // shuffle nodes. 6423 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6424 // so the shuffle can be broken into other shuffles and the legalizer can 6425 // try the lowering again. 6426 // 6427 // The general idea is that no vector_shuffle operation should be left to 6428 // be matched during isel, all of them must be converted to a target specific 6429 // node here. 6430 6431 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6432 // narrowing and commutation of operands should be handled. The actual code 6433 // doesn't include all of those, work in progress... 6434 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6435 if (NewOp.getNode()) 6436 return NewOp; 6437 6438 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6439 6440 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6441 // unpckh_undef). Only use pshufd if speed is more important than size. 6442 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6443 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6444 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6445 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6446 6447 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6448 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6449 return getMOVDDup(Op, dl, V1, DAG); 6450 6451 if (isMOVHLPS_v_undef_Mask(M, VT)) 6452 return getMOVHighToLow(Op, dl, DAG); 6453 6454 // Use to match splats 6455 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6456 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6457 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6458 6459 if (isPSHUFDMask(M, VT)) { 6460 // The actual implementation will match the mask in the if above and then 6461 // during isel it can match several different instructions, not only pshufd 6462 // as its name says, sad but true, emulate the behavior for now... 6463 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6464 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6465 6466 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6467 6468 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6469 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6470 6471 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6472 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6473 6474 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6475 TargetMask, DAG); 6476 } 6477 6478 // Check if this can be converted into a logical shift. 6479 bool isLeft = false; 6480 unsigned ShAmt = 0; 6481 SDValue ShVal; 6482 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6483 if (isShift && ShVal.hasOneUse()) { 6484 // If the shifted value has multiple uses, it may be cheaper to use 6485 // v_set0 + movlhps or movhlps, etc. 6486 EVT EltVT = VT.getVectorElementType(); 6487 ShAmt *= EltVT.getSizeInBits(); 6488 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6489 } 6490 6491 if (isMOVLMask(M, VT)) { 6492 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6493 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6494 if (!isMOVLPMask(M, VT)) { 6495 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6496 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6497 6498 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6499 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6500 } 6501 } 6502 6503 // FIXME: fold these into legal mask. 6504 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6505 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6506 6507 if (isMOVHLPSMask(M, VT)) 6508 return getMOVHighToLow(Op, dl, DAG); 6509 6510 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6511 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6512 6513 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6514 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6515 6516 if (isMOVLPMask(M, VT)) 6517 return getMOVLP(Op, dl, DAG, HasSSE2); 6518 6519 if (ShouldXformToMOVHLPS(M, VT) || 6520 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6521 return CommuteVectorShuffle(SVOp, DAG); 6522 6523 if (isShift) { 6524 // No better options. Use a vshldq / vsrldq. 6525 EVT EltVT = VT.getVectorElementType(); 6526 ShAmt *= EltVT.getSizeInBits(); 6527 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6528 } 6529 6530 bool Commuted = false; 6531 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6532 // 1,1,1,1 -> v8i16 though. 6533 V1IsSplat = isSplatVector(V1.getNode()); 6534 V2IsSplat = isSplatVector(V2.getNode()); 6535 6536 // Canonicalize the splat or undef, if present, to be on the RHS. 6537 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6538 CommuteVectorShuffleMask(M, NumElems); 6539 std::swap(V1, V2); 6540 std::swap(V1IsSplat, V2IsSplat); 6541 Commuted = true; 6542 } 6543 6544 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6545 // Shuffling low element of v1 into undef, just return v1. 6546 if (V2IsUndef) 6547 return V1; 6548 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6549 // the instruction selector will not match, so get a canonical MOVL with 6550 // swapped operands to undo the commute. 6551 return getMOVL(DAG, dl, VT, V2, V1); 6552 } 6553 6554 if (isUNPCKLMask(M, VT, HasAVX2)) 6555 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6556 6557 if (isUNPCKHMask(M, VT, HasAVX2)) 6558 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6559 6560 if (V2IsSplat) { 6561 // Normalize mask so all entries that point to V2 points to its first 6562 // element then try to match unpck{h|l} again. If match, return a 6563 // new vector_shuffle with the corrected mask.p 6564 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6565 NormalizeMask(NewMask, NumElems); 6566 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) 6567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6568 if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) 6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6570 } 6571 6572 if (Commuted) { 6573 // Commute is back and try unpck* again. 6574 // FIXME: this seems wrong. 6575 CommuteVectorShuffleMask(M, NumElems); 6576 std::swap(V1, V2); 6577 std::swap(V1IsSplat, V2IsSplat); 6578 Commuted = false; 6579 6580 if (isUNPCKLMask(M, VT, HasAVX2)) 6581 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6582 6583 if (isUNPCKHMask(M, VT, HasAVX2)) 6584 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6585 } 6586 6587 // Normalize the node to match x86 shuffle ops if needed 6588 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6589 return CommuteVectorShuffle(SVOp, DAG); 6590 6591 // The checks below are all present in isShuffleMaskLegal, but they are 6592 // inlined here right now to enable us to directly emit target specific 6593 // nodes, and remove one by one until they don't return Op anymore. 6594 6595 if (isPALIGNRMask(M, VT, Subtarget)) 6596 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6597 getShufflePALIGNRImmediate(SVOp), 6598 DAG); 6599 6600 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6601 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6602 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6603 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6604 } 6605 6606 if (isPSHUFHWMask(M, VT, HasAVX2)) 6607 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6608 getShufflePSHUFHWImmediate(SVOp), 6609 DAG); 6610 6611 if (isPSHUFLWMask(M, VT, HasAVX2)) 6612 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6613 getShufflePSHUFLWImmediate(SVOp), 6614 DAG); 6615 6616 if (isSHUFPMask(M, VT, HasAVX)) 6617 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6618 getShuffleSHUFImmediate(SVOp), DAG); 6619 6620 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6621 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6622 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6623 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6624 6625 //===--------------------------------------------------------------------===// 6626 // Generate target specific nodes for 128 or 256-bit shuffles only 6627 // supported in the AVX instruction set. 6628 // 6629 6630 // Handle VMOVDDUPY permutations 6631 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6632 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6633 6634 // Handle VPERMILPS/D* permutations 6635 if (isVPERMILPMask(M, VT, HasAVX)) { 6636 if (HasAVX2 && VT == MVT::v8i32) 6637 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6638 getShuffleSHUFImmediate(SVOp), DAG); 6639 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6640 getShuffleSHUFImmediate(SVOp), DAG); 6641 } 6642 6643 // Handle VPERM2F128/VPERM2I128 permutations 6644 if (isVPERM2X128Mask(M, VT, HasAVX)) 6645 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6646 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6647 6648 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6649 if (BlendOp.getNode()) 6650 return BlendOp; 6651 6652 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6653 SmallVector<SDValue, 8> permclMask; 6654 for (unsigned i = 0; i != 8; ++i) { 6655 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6656 } 6657 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6658 &permclMask[0], 8); 6659 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6660 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6661 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6662 } 6663 6664 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6665 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6666 getShuffleCLImmediate(SVOp), DAG); 6667 6668 6669 //===--------------------------------------------------------------------===// 6670 // Since no target specific shuffle was selected for this generic one, 6671 // lower it into other known shuffles. FIXME: this isn't true yet, but 6672 // this is the plan. 6673 // 6674 6675 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6676 if (VT == MVT::v8i16) { 6677 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6678 if (NewOp.getNode()) 6679 return NewOp; 6680 } 6681 6682 if (VT == MVT::v16i8) { 6683 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6684 if (NewOp.getNode()) 6685 return NewOp; 6686 } 6687 6688 // Handle all 128-bit wide vectors with 4 elements, and match them with 6689 // several different shuffle types. 6690 if (NumElems == 4 && VT.getSizeInBits() == 128) 6691 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6692 6693 // Handle general 256-bit shuffles 6694 if (VT.is256BitVector()) 6695 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6696 6697 return SDValue(); 6698} 6699 6700SDValue 6701X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6702 SelectionDAG &DAG) const { 6703 EVT VT = Op.getValueType(); 6704 DebugLoc dl = Op.getDebugLoc(); 6705 6706 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6707 return SDValue(); 6708 6709 if (VT.getSizeInBits() == 8) { 6710 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6711 Op.getOperand(0), Op.getOperand(1)); 6712 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6713 DAG.getValueType(VT)); 6714 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6715 } 6716 6717 if (VT.getSizeInBits() == 16) { 6718 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6719 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6720 if (Idx == 0) 6721 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6723 DAG.getNode(ISD::BITCAST, dl, 6724 MVT::v4i32, 6725 Op.getOperand(0)), 6726 Op.getOperand(1))); 6727 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6728 Op.getOperand(0), Op.getOperand(1)); 6729 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6730 DAG.getValueType(VT)); 6731 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6732 } 6733 6734 if (VT == MVT::f32) { 6735 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6736 // the result back to FR32 register. It's only worth matching if the 6737 // result has a single use which is a store or a bitcast to i32. And in 6738 // the case of a store, it's not worth it if the index is a constant 0, 6739 // because a MOVSSmr can be used instead, which is smaller and faster. 6740 if (!Op.hasOneUse()) 6741 return SDValue(); 6742 SDNode *User = *Op.getNode()->use_begin(); 6743 if ((User->getOpcode() != ISD::STORE || 6744 (isa<ConstantSDNode>(Op.getOperand(1)) && 6745 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6746 (User->getOpcode() != ISD::BITCAST || 6747 User->getValueType(0) != MVT::i32)) 6748 return SDValue(); 6749 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6750 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6751 Op.getOperand(0)), 6752 Op.getOperand(1)); 6753 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6754 } 6755 6756 if (VT == MVT::i32 || VT == MVT::i64) { 6757 // ExtractPS/pextrq works with constant index. 6758 if (isa<ConstantSDNode>(Op.getOperand(1))) 6759 return Op; 6760 } 6761 return SDValue(); 6762} 6763 6764 6765SDValue 6766X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6767 SelectionDAG &DAG) const { 6768 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6769 return SDValue(); 6770 6771 SDValue Vec = Op.getOperand(0); 6772 EVT VecVT = Vec.getValueType(); 6773 6774 // If this is a 256-bit vector result, first extract the 128-bit vector and 6775 // then extract the element from the 128-bit vector. 6776 if (VecVT.getSizeInBits() == 256) { 6777 DebugLoc dl = Op.getNode()->getDebugLoc(); 6778 unsigned NumElems = VecVT.getVectorNumElements(); 6779 SDValue Idx = Op.getOperand(1); 6780 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6781 6782 // Get the 128-bit vector. 6783 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 6784 6785 if (IdxVal >= NumElems/2) 6786 IdxVal -= NumElems/2; 6787 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6788 DAG.getConstant(IdxVal, MVT::i32)); 6789 } 6790 6791 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6792 6793 if (Subtarget->hasSSE41()) { 6794 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6795 if (Res.getNode()) 6796 return Res; 6797 } 6798 6799 EVT VT = Op.getValueType(); 6800 DebugLoc dl = Op.getDebugLoc(); 6801 // TODO: handle v16i8. 6802 if (VT.getSizeInBits() == 16) { 6803 SDValue Vec = Op.getOperand(0); 6804 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6805 if (Idx == 0) 6806 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6807 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6808 DAG.getNode(ISD::BITCAST, dl, 6809 MVT::v4i32, Vec), 6810 Op.getOperand(1))); 6811 // Transform it so it match pextrw which produces a 32-bit result. 6812 EVT EltVT = MVT::i32; 6813 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6814 Op.getOperand(0), Op.getOperand(1)); 6815 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6816 DAG.getValueType(VT)); 6817 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6818 } 6819 6820 if (VT.getSizeInBits() == 32) { 6821 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6822 if (Idx == 0) 6823 return Op; 6824 6825 // SHUFPS the element to the lowest double word, then movss. 6826 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6827 EVT VVT = Op.getOperand(0).getValueType(); 6828 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6829 DAG.getUNDEF(VVT), Mask); 6830 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6831 DAG.getIntPtrConstant(0)); 6832 } 6833 6834 if (VT.getSizeInBits() == 64) { 6835 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6836 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6837 // to match extract_elt for f64. 6838 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6839 if (Idx == 0) 6840 return Op; 6841 6842 // UNPCKHPD the element to the lowest double word, then movsd. 6843 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6844 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6845 int Mask[2] = { 1, -1 }; 6846 EVT VVT = Op.getOperand(0).getValueType(); 6847 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6848 DAG.getUNDEF(VVT), Mask); 6849 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6850 DAG.getIntPtrConstant(0)); 6851 } 6852 6853 return SDValue(); 6854} 6855 6856SDValue 6857X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6858 SelectionDAG &DAG) const { 6859 EVT VT = Op.getValueType(); 6860 EVT EltVT = VT.getVectorElementType(); 6861 DebugLoc dl = Op.getDebugLoc(); 6862 6863 SDValue N0 = Op.getOperand(0); 6864 SDValue N1 = Op.getOperand(1); 6865 SDValue N2 = Op.getOperand(2); 6866 6867 if (VT.getSizeInBits() == 256) 6868 return SDValue(); 6869 6870 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6871 isa<ConstantSDNode>(N2)) { 6872 unsigned Opc; 6873 if (VT == MVT::v8i16) 6874 Opc = X86ISD::PINSRW; 6875 else if (VT == MVT::v16i8) 6876 Opc = X86ISD::PINSRB; 6877 else 6878 Opc = X86ISD::PINSRB; 6879 6880 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6881 // argument. 6882 if (N1.getValueType() != MVT::i32) 6883 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6884 if (N2.getValueType() != MVT::i32) 6885 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6886 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6887 } 6888 6889 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6890 // Bits [7:6] of the constant are the source select. This will always be 6891 // zero here. The DAG Combiner may combine an extract_elt index into these 6892 // bits. For example (insert (extract, 3), 2) could be matched by putting 6893 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6894 // Bits [5:4] of the constant are the destination select. This is the 6895 // value of the incoming immediate. 6896 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6897 // combine either bitwise AND or insert of float 0.0 to set these bits. 6898 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6899 // Create this as a scalar to vector.. 6900 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6901 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6902 } 6903 6904 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 6905 // PINSR* works with constant index. 6906 return Op; 6907 } 6908 return SDValue(); 6909} 6910 6911SDValue 6912X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6913 EVT VT = Op.getValueType(); 6914 EVT EltVT = VT.getVectorElementType(); 6915 6916 DebugLoc dl = Op.getDebugLoc(); 6917 SDValue N0 = Op.getOperand(0); 6918 SDValue N1 = Op.getOperand(1); 6919 SDValue N2 = Op.getOperand(2); 6920 6921 // If this is a 256-bit vector result, first extract the 128-bit vector, 6922 // insert the element into the extracted half and then place it back. 6923 if (VT.getSizeInBits() == 256) { 6924 if (!isa<ConstantSDNode>(N2)) 6925 return SDValue(); 6926 6927 // Get the desired 128-bit vector half. 6928 unsigned NumElems = VT.getVectorNumElements(); 6929 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6930 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 6931 6932 // Insert the element into the desired half. 6933 bool Upper = IdxVal >= NumElems/2; 6934 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 6935 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 6936 6937 // Insert the changed part back to the 256-bit vector 6938 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 6939 } 6940 6941 if (Subtarget->hasSSE41()) 6942 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6943 6944 if (EltVT == MVT::i8) 6945 return SDValue(); 6946 6947 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6948 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6949 // as its second argument. 6950 if (N1.getValueType() != MVT::i32) 6951 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6952 if (N2.getValueType() != MVT::i32) 6953 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6954 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6955 } 6956 return SDValue(); 6957} 6958 6959SDValue 6960X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6961 LLVMContext *Context = DAG.getContext(); 6962 DebugLoc dl = Op.getDebugLoc(); 6963 EVT OpVT = Op.getValueType(); 6964 6965 // If this is a 256-bit vector result, first insert into a 128-bit 6966 // vector and then insert into the 256-bit vector. 6967 if (OpVT.getSizeInBits() > 128) { 6968 // Insert into a 128-bit vector. 6969 EVT VT128 = EVT::getVectorVT(*Context, 6970 OpVT.getVectorElementType(), 6971 OpVT.getVectorNumElements() / 2); 6972 6973 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6974 6975 // Insert the 128-bit vector. 6976 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 6977 } 6978 6979 if (OpVT == MVT::v1i64 && 6980 Op.getOperand(0).getValueType() == MVT::i64) 6981 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6982 6983 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6984 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!"); 6985 return DAG.getNode(ISD::BITCAST, dl, OpVT, 6986 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6987} 6988 6989// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6990// a simple subregister reference or explicit instructions to grab 6991// upper bits of a vector. 6992SDValue 6993X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6994 if (Subtarget->hasAVX()) { 6995 DebugLoc dl = Op.getNode()->getDebugLoc(); 6996 SDValue Vec = Op.getNode()->getOperand(0); 6997 SDValue Idx = Op.getNode()->getOperand(1); 6998 6999 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 && 7000 Vec.getNode()->getValueType(0).getSizeInBits() == 256 && 7001 isa<ConstantSDNode>(Idx)) { 7002 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7003 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7004 } 7005 } 7006 return SDValue(); 7007} 7008 7009// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7010// simple superregister reference or explicit instructions to insert 7011// the upper bits of a vector. 7012SDValue 7013X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7014 if (Subtarget->hasAVX()) { 7015 DebugLoc dl = Op.getNode()->getDebugLoc(); 7016 SDValue Vec = Op.getNode()->getOperand(0); 7017 SDValue SubVec = Op.getNode()->getOperand(1); 7018 SDValue Idx = Op.getNode()->getOperand(2); 7019 7020 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 && 7021 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 && 7022 isa<ConstantSDNode>(Idx)) { 7023 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7024 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7025 } 7026 } 7027 return SDValue(); 7028} 7029 7030// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7031// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7032// one of the above mentioned nodes. It has to be wrapped because otherwise 7033// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7034// be used to form addressing mode. These wrapped nodes will be selected 7035// into MOV32ri. 7036SDValue 7037X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7038 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7039 7040 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7041 // global base reg. 7042 unsigned char OpFlag = 0; 7043 unsigned WrapperKind = X86ISD::Wrapper; 7044 CodeModel::Model M = getTargetMachine().getCodeModel(); 7045 7046 if (Subtarget->isPICStyleRIPRel() && 7047 (M == CodeModel::Small || M == CodeModel::Kernel)) 7048 WrapperKind = X86ISD::WrapperRIP; 7049 else if (Subtarget->isPICStyleGOT()) 7050 OpFlag = X86II::MO_GOTOFF; 7051 else if (Subtarget->isPICStyleStubPIC()) 7052 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7053 7054 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7055 CP->getAlignment(), 7056 CP->getOffset(), OpFlag); 7057 DebugLoc DL = CP->getDebugLoc(); 7058 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7059 // With PIC, the address is actually $g + Offset. 7060 if (OpFlag) { 7061 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7062 DAG.getNode(X86ISD::GlobalBaseReg, 7063 DebugLoc(), getPointerTy()), 7064 Result); 7065 } 7066 7067 return Result; 7068} 7069 7070SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7071 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7072 7073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7074 // global base reg. 7075 unsigned char OpFlag = 0; 7076 unsigned WrapperKind = X86ISD::Wrapper; 7077 CodeModel::Model M = getTargetMachine().getCodeModel(); 7078 7079 if (Subtarget->isPICStyleRIPRel() && 7080 (M == CodeModel::Small || M == CodeModel::Kernel)) 7081 WrapperKind = X86ISD::WrapperRIP; 7082 else if (Subtarget->isPICStyleGOT()) 7083 OpFlag = X86II::MO_GOTOFF; 7084 else if (Subtarget->isPICStyleStubPIC()) 7085 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7086 7087 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7088 OpFlag); 7089 DebugLoc DL = JT->getDebugLoc(); 7090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7091 7092 // With PIC, the address is actually $g + Offset. 7093 if (OpFlag) 7094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7095 DAG.getNode(X86ISD::GlobalBaseReg, 7096 DebugLoc(), getPointerTy()), 7097 Result); 7098 7099 return Result; 7100} 7101 7102SDValue 7103X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7104 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7105 7106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7107 // global base reg. 7108 unsigned char OpFlag = 0; 7109 unsigned WrapperKind = X86ISD::Wrapper; 7110 CodeModel::Model M = getTargetMachine().getCodeModel(); 7111 7112 if (Subtarget->isPICStyleRIPRel() && 7113 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7114 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7115 OpFlag = X86II::MO_GOTPCREL; 7116 WrapperKind = X86ISD::WrapperRIP; 7117 } else if (Subtarget->isPICStyleGOT()) { 7118 OpFlag = X86II::MO_GOT; 7119 } else if (Subtarget->isPICStyleStubPIC()) { 7120 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7121 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7122 OpFlag = X86II::MO_DARWIN_NONLAZY; 7123 } 7124 7125 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7126 7127 DebugLoc DL = Op.getDebugLoc(); 7128 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7129 7130 7131 // With PIC, the address is actually $g + Offset. 7132 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7133 !Subtarget->is64Bit()) { 7134 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7135 DAG.getNode(X86ISD::GlobalBaseReg, 7136 DebugLoc(), getPointerTy()), 7137 Result); 7138 } 7139 7140 // For symbols that require a load from a stub to get the address, emit the 7141 // load. 7142 if (isGlobalStubReference(OpFlag)) 7143 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7144 MachinePointerInfo::getGOT(), false, false, false, 0); 7145 7146 return Result; 7147} 7148 7149SDValue 7150X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7151 // Create the TargetBlockAddressAddress node. 7152 unsigned char OpFlags = 7153 Subtarget->ClassifyBlockAddressReference(); 7154 CodeModel::Model M = getTargetMachine().getCodeModel(); 7155 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7156 DebugLoc dl = Op.getDebugLoc(); 7157 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7158 /*isTarget=*/true, OpFlags); 7159 7160 if (Subtarget->isPICStyleRIPRel() && 7161 (M == CodeModel::Small || M == CodeModel::Kernel)) 7162 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7163 else 7164 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7165 7166 // With PIC, the address is actually $g + Offset. 7167 if (isGlobalRelativeToPICBase(OpFlags)) { 7168 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7169 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7170 Result); 7171 } 7172 7173 return Result; 7174} 7175 7176SDValue 7177X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7178 int64_t Offset, 7179 SelectionDAG &DAG) const { 7180 // Create the TargetGlobalAddress node, folding in the constant 7181 // offset if it is legal. 7182 unsigned char OpFlags = 7183 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7184 CodeModel::Model M = getTargetMachine().getCodeModel(); 7185 SDValue Result; 7186 if (OpFlags == X86II::MO_NO_FLAG && 7187 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7188 // A direct static reference to a global. 7189 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7190 Offset = 0; 7191 } else { 7192 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7193 } 7194 7195 if (Subtarget->isPICStyleRIPRel() && 7196 (M == CodeModel::Small || M == CodeModel::Kernel)) 7197 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7198 else 7199 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7200 7201 // With PIC, the address is actually $g + Offset. 7202 if (isGlobalRelativeToPICBase(OpFlags)) { 7203 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7204 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7205 Result); 7206 } 7207 7208 // For globals that require a load from a stub to get the address, emit the 7209 // load. 7210 if (isGlobalStubReference(OpFlags)) 7211 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7212 MachinePointerInfo::getGOT(), false, false, false, 0); 7213 7214 // If there was a non-zero offset that we didn't fold, create an explicit 7215 // addition for it. 7216 if (Offset != 0) 7217 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7218 DAG.getConstant(Offset, getPointerTy())); 7219 7220 return Result; 7221} 7222 7223SDValue 7224X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7225 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7226 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7227 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7228} 7229 7230static SDValue 7231GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7232 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7233 unsigned char OperandFlags) { 7234 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7235 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7236 DebugLoc dl = GA->getDebugLoc(); 7237 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7238 GA->getValueType(0), 7239 GA->getOffset(), 7240 OperandFlags); 7241 if (InFlag) { 7242 SDValue Ops[] = { Chain, TGA, *InFlag }; 7243 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7244 } else { 7245 SDValue Ops[] = { Chain, TGA }; 7246 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7247 } 7248 7249 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7250 MFI->setAdjustsStack(true); 7251 7252 SDValue Flag = Chain.getValue(1); 7253 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7254} 7255 7256// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7257static SDValue 7258LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7259 const EVT PtrVT) { 7260 SDValue InFlag; 7261 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7262 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7263 DAG.getNode(X86ISD::GlobalBaseReg, 7264 DebugLoc(), PtrVT), InFlag); 7265 InFlag = Chain.getValue(1); 7266 7267 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7268} 7269 7270// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7271static SDValue 7272LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7273 const EVT PtrVT) { 7274 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7275 X86::RAX, X86II::MO_TLSGD); 7276} 7277 7278// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7279// "local exec" model. 7280static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7281 const EVT PtrVT, TLSModel::Model model, 7282 bool is64Bit) { 7283 DebugLoc dl = GA->getDebugLoc(); 7284 7285 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7286 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7287 is64Bit ? 257 : 256)); 7288 7289 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7290 DAG.getIntPtrConstant(0), 7291 MachinePointerInfo(Ptr), 7292 false, false, false, 0); 7293 7294 unsigned char OperandFlags = 0; 7295 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7296 // initialexec. 7297 unsigned WrapperKind = X86ISD::Wrapper; 7298 if (model == TLSModel::LocalExec) { 7299 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7300 } else if (is64Bit) { 7301 assert(model == TLSModel::InitialExec); 7302 OperandFlags = X86II::MO_GOTTPOFF; 7303 WrapperKind = X86ISD::WrapperRIP; 7304 } else { 7305 assert(model == TLSModel::InitialExec); 7306 OperandFlags = X86II::MO_INDNTPOFF; 7307 } 7308 7309 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7310 // exec) 7311 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7312 GA->getValueType(0), 7313 GA->getOffset(), OperandFlags); 7314 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7315 7316 if (model == TLSModel::InitialExec) 7317 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7318 MachinePointerInfo::getGOT(), false, false, false, 0); 7319 7320 // The address of the thread local variable is the add of the thread 7321 // pointer with the offset of the variable. 7322 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7323} 7324 7325SDValue 7326X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7327 7328 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7329 const GlobalValue *GV = GA->getGlobal(); 7330 7331 if (Subtarget->isTargetELF()) { 7332 // TODO: implement the "local dynamic" model 7333 // TODO: implement the "initial exec"model for pic executables 7334 7335 // If GV is an alias then use the aliasee for determining 7336 // thread-localness. 7337 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7338 GV = GA->resolveAliasedGlobal(false); 7339 7340 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7341 7342 switch (model) { 7343 case TLSModel::GeneralDynamic: 7344 case TLSModel::LocalDynamic: // not implemented 7345 if (Subtarget->is64Bit()) 7346 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7347 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7348 7349 case TLSModel::InitialExec: 7350 case TLSModel::LocalExec: 7351 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7352 Subtarget->is64Bit()); 7353 } 7354 llvm_unreachable("Unknown TLS model."); 7355 } 7356 7357 if (Subtarget->isTargetDarwin()) { 7358 // Darwin only has one model of TLS. Lower to that. 7359 unsigned char OpFlag = 0; 7360 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7361 X86ISD::WrapperRIP : X86ISD::Wrapper; 7362 7363 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7364 // global base reg. 7365 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7366 !Subtarget->is64Bit(); 7367 if (PIC32) 7368 OpFlag = X86II::MO_TLVP_PIC_BASE; 7369 else 7370 OpFlag = X86II::MO_TLVP; 7371 DebugLoc DL = Op.getDebugLoc(); 7372 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7373 GA->getValueType(0), 7374 GA->getOffset(), OpFlag); 7375 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7376 7377 // With PIC32, the address is actually $g + Offset. 7378 if (PIC32) 7379 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7380 DAG.getNode(X86ISD::GlobalBaseReg, 7381 DebugLoc(), getPointerTy()), 7382 Offset); 7383 7384 // Lowering the machine isd will make sure everything is in the right 7385 // location. 7386 SDValue Chain = DAG.getEntryNode(); 7387 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7388 SDValue Args[] = { Chain, Offset }; 7389 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7390 7391 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7392 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7393 MFI->setAdjustsStack(true); 7394 7395 // And our return value (tls address) is in the standard call return value 7396 // location. 7397 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7398 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7399 Chain.getValue(1)); 7400 } 7401 7402 if (Subtarget->isTargetWindows()) { 7403 // Just use the implicit TLS architecture 7404 // Need to generate someting similar to: 7405 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7406 // ; from TEB 7407 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7408 // mov rcx, qword [rdx+rcx*8] 7409 // mov eax, .tls$:tlsvar 7410 // [rax+rcx] contains the address 7411 // Windows 64bit: gs:0x58 7412 // Windows 32bit: fs:__tls_array 7413 7414 // If GV is an alias then use the aliasee for determining 7415 // thread-localness. 7416 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7417 GV = GA->resolveAliasedGlobal(false); 7418 DebugLoc dl = GA->getDebugLoc(); 7419 SDValue Chain = DAG.getEntryNode(); 7420 7421 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7422 // %gs:0x58 (64-bit). 7423 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7424 ? Type::getInt8PtrTy(*DAG.getContext(), 7425 256) 7426 : Type::getInt32PtrTy(*DAG.getContext(), 7427 257)); 7428 7429 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7430 Subtarget->is64Bit() 7431 ? DAG.getIntPtrConstant(0x58) 7432 : DAG.getExternalSymbol("_tls_array", 7433 getPointerTy()), 7434 MachinePointerInfo(Ptr), 7435 false, false, false, 0); 7436 7437 // Load the _tls_index variable 7438 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7439 if (Subtarget->is64Bit()) 7440 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7441 IDX, MachinePointerInfo(), MVT::i32, 7442 false, false, 0); 7443 else 7444 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7445 false, false, false, 0); 7446 7447 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7448 getPointerTy()); 7449 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7450 7451 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7452 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7453 false, false, false, 0); 7454 7455 // Get the offset of start of .tls section 7456 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7457 GA->getValueType(0), 7458 GA->getOffset(), X86II::MO_SECREL); 7459 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7460 7461 // The address of the thread local variable is the add of the thread 7462 // pointer with the offset of the variable. 7463 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7464 } 7465 7466 llvm_unreachable("TLS not implemented for this target."); 7467} 7468 7469 7470/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7471/// and take a 2 x i32 value to shift plus a shift amount. 7472SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7473 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7474 EVT VT = Op.getValueType(); 7475 unsigned VTBits = VT.getSizeInBits(); 7476 DebugLoc dl = Op.getDebugLoc(); 7477 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7478 SDValue ShOpLo = Op.getOperand(0); 7479 SDValue ShOpHi = Op.getOperand(1); 7480 SDValue ShAmt = Op.getOperand(2); 7481 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7482 DAG.getConstant(VTBits - 1, MVT::i8)) 7483 : DAG.getConstant(0, VT); 7484 7485 SDValue Tmp2, Tmp3; 7486 if (Op.getOpcode() == ISD::SHL_PARTS) { 7487 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7488 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7489 } else { 7490 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7491 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7492 } 7493 7494 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7495 DAG.getConstant(VTBits, MVT::i8)); 7496 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7497 AndNode, DAG.getConstant(0, MVT::i8)); 7498 7499 SDValue Hi, Lo; 7500 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7501 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7502 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7503 7504 if (Op.getOpcode() == ISD::SHL_PARTS) { 7505 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7506 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7507 } else { 7508 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7509 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7510 } 7511 7512 SDValue Ops[2] = { Lo, Hi }; 7513 return DAG.getMergeValues(Ops, 2, dl); 7514} 7515 7516SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7517 SelectionDAG &DAG) const { 7518 EVT SrcVT = Op.getOperand(0).getValueType(); 7519 7520 if (SrcVT.isVector()) 7521 return SDValue(); 7522 7523 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7524 "Unknown SINT_TO_FP to lower!"); 7525 7526 // These are really Legal; return the operand so the caller accepts it as 7527 // Legal. 7528 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7529 return Op; 7530 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7531 Subtarget->is64Bit()) { 7532 return Op; 7533 } 7534 7535 DebugLoc dl = Op.getDebugLoc(); 7536 unsigned Size = SrcVT.getSizeInBits()/8; 7537 MachineFunction &MF = DAG.getMachineFunction(); 7538 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7539 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7540 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7541 StackSlot, 7542 MachinePointerInfo::getFixedStack(SSFI), 7543 false, false, 0); 7544 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7545} 7546 7547SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7548 SDValue StackSlot, 7549 SelectionDAG &DAG) const { 7550 // Build the FILD 7551 DebugLoc DL = Op.getDebugLoc(); 7552 SDVTList Tys; 7553 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7554 if (useSSE) 7555 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7556 else 7557 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7558 7559 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7560 7561 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7562 MachineMemOperand *MMO; 7563 if (FI) { 7564 int SSFI = FI->getIndex(); 7565 MMO = 7566 DAG.getMachineFunction() 7567 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7568 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7569 } else { 7570 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7571 StackSlot = StackSlot.getOperand(1); 7572 } 7573 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7574 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7575 X86ISD::FILD, DL, 7576 Tys, Ops, array_lengthof(Ops), 7577 SrcVT, MMO); 7578 7579 if (useSSE) { 7580 Chain = Result.getValue(1); 7581 SDValue InFlag = Result.getValue(2); 7582 7583 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7584 // shouldn't be necessary except that RFP cannot be live across 7585 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7586 MachineFunction &MF = DAG.getMachineFunction(); 7587 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7588 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7589 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7590 Tys = DAG.getVTList(MVT::Other); 7591 SDValue Ops[] = { 7592 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7593 }; 7594 MachineMemOperand *MMO = 7595 DAG.getMachineFunction() 7596 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7597 MachineMemOperand::MOStore, SSFISize, SSFISize); 7598 7599 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7600 Ops, array_lengthof(Ops), 7601 Op.getValueType(), MMO); 7602 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7603 MachinePointerInfo::getFixedStack(SSFI), 7604 false, false, false, 0); 7605 } 7606 7607 return Result; 7608} 7609 7610// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7611SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7612 SelectionDAG &DAG) const { 7613 // This algorithm is not obvious. Here it is what we're trying to output: 7614 /* 7615 movq %rax, %xmm0 7616 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7617 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7618 #ifdef __SSE3__ 7619 haddpd %xmm0, %xmm0 7620 #else 7621 pshufd $0x4e, %xmm0, %xmm1 7622 addpd %xmm1, %xmm0 7623 #endif 7624 */ 7625 7626 DebugLoc dl = Op.getDebugLoc(); 7627 LLVMContext *Context = DAG.getContext(); 7628 7629 // Build some magic constants. 7630 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7631 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7632 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7633 7634 SmallVector<Constant*,2> CV1; 7635 CV1.push_back( 7636 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7637 CV1.push_back( 7638 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7639 Constant *C1 = ConstantVector::get(CV1); 7640 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7641 7642 // Load the 64-bit value into an XMM register. 7643 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7644 Op.getOperand(0)); 7645 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7646 MachinePointerInfo::getConstantPool(), 7647 false, false, false, 16); 7648 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7649 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7650 CLod0); 7651 7652 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7653 MachinePointerInfo::getConstantPool(), 7654 false, false, false, 16); 7655 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7656 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7657 SDValue Result; 7658 7659 if (Subtarget->hasSSE3()) { 7660 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7661 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7662 } else { 7663 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7664 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7665 S2F, 0x4E, DAG); 7666 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7667 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7668 Sub); 7669 } 7670 7671 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7672 DAG.getIntPtrConstant(0)); 7673} 7674 7675// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7676SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7677 SelectionDAG &DAG) const { 7678 DebugLoc dl = Op.getDebugLoc(); 7679 // FP constant to bias correct the final result. 7680 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7681 MVT::f64); 7682 7683 // Load the 32-bit value into an XMM register. 7684 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7685 Op.getOperand(0)); 7686 7687 // Zero out the upper parts of the register. 7688 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7689 7690 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7691 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7692 DAG.getIntPtrConstant(0)); 7693 7694 // Or the load with the bias. 7695 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7696 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7697 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7698 MVT::v2f64, Load)), 7699 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7700 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7701 MVT::v2f64, Bias))); 7702 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7703 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7704 DAG.getIntPtrConstant(0)); 7705 7706 // Subtract the bias. 7707 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7708 7709 // Handle final rounding. 7710 EVT DestVT = Op.getValueType(); 7711 7712 if (DestVT.bitsLT(MVT::f64)) 7713 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7714 DAG.getIntPtrConstant(0)); 7715 if (DestVT.bitsGT(MVT::f64)) 7716 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7717 7718 // Handle final rounding. 7719 return Sub; 7720} 7721 7722SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7723 SelectionDAG &DAG) const { 7724 SDValue N0 = Op.getOperand(0); 7725 DebugLoc dl = Op.getDebugLoc(); 7726 7727 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7728 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7729 // the optimization here. 7730 if (DAG.SignBitIsZero(N0)) 7731 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7732 7733 EVT SrcVT = N0.getValueType(); 7734 EVT DstVT = Op.getValueType(); 7735 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7736 return LowerUINT_TO_FP_i64(Op, DAG); 7737 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7738 return LowerUINT_TO_FP_i32(Op, DAG); 7739 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 7740 return SDValue(); 7741 7742 // Make a 64-bit buffer, and use it to build an FILD. 7743 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7744 if (SrcVT == MVT::i32) { 7745 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7746 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7747 getPointerTy(), StackSlot, WordOff); 7748 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7749 StackSlot, MachinePointerInfo(), 7750 false, false, 0); 7751 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7752 OffsetSlot, MachinePointerInfo(), 7753 false, false, 0); 7754 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7755 return Fild; 7756 } 7757 7758 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7759 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7760 StackSlot, MachinePointerInfo(), 7761 false, false, 0); 7762 // For i64 source, we need to add the appropriate power of 2 if the input 7763 // was negative. This is the same as the optimization in 7764 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7765 // we must be careful to do the computation in x87 extended precision, not 7766 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7767 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7768 MachineMemOperand *MMO = 7769 DAG.getMachineFunction() 7770 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7771 MachineMemOperand::MOLoad, 8, 8); 7772 7773 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7774 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7775 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7776 MVT::i64, MMO); 7777 7778 APInt FF(32, 0x5F800000ULL); 7779 7780 // Check whether the sign bit is set. 7781 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7782 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7783 ISD::SETLT); 7784 7785 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7786 SDValue FudgePtr = DAG.getConstantPool( 7787 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7788 getPointerTy()); 7789 7790 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7791 SDValue Zero = DAG.getIntPtrConstant(0); 7792 SDValue Four = DAG.getIntPtrConstant(4); 7793 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7794 Zero, Four); 7795 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7796 7797 // Load the value out, extending it from f32 to f80. 7798 // FIXME: Avoid the extend by constructing the right constant pool? 7799 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7800 FudgePtr, MachinePointerInfo::getConstantPool(), 7801 MVT::f32, false, false, 4); 7802 // Extend everything to 80 bits to force it to be done on x87. 7803 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7804 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7805} 7806 7807std::pair<SDValue,SDValue> X86TargetLowering:: 7808FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7809 DebugLoc DL = Op.getDebugLoc(); 7810 7811 EVT DstTy = Op.getValueType(); 7812 7813 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7814 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7815 DstTy = MVT::i64; 7816 } 7817 7818 assert(DstTy.getSimpleVT() <= MVT::i64 && 7819 DstTy.getSimpleVT() >= MVT::i16 && 7820 "Unknown FP_TO_INT to lower!"); 7821 7822 // These are really Legal. 7823 if (DstTy == MVT::i32 && 7824 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7825 return std::make_pair(SDValue(), SDValue()); 7826 if (Subtarget->is64Bit() && 7827 DstTy == MVT::i64 && 7828 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7829 return std::make_pair(SDValue(), SDValue()); 7830 7831 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7832 // stack slot, or into the FTOL runtime function. 7833 MachineFunction &MF = DAG.getMachineFunction(); 7834 unsigned MemSize = DstTy.getSizeInBits()/8; 7835 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7836 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7837 7838 unsigned Opc; 7839 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7840 Opc = X86ISD::WIN_FTOL; 7841 else 7842 switch (DstTy.getSimpleVT().SimpleTy) { 7843 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7844 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7845 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7846 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7847 } 7848 7849 SDValue Chain = DAG.getEntryNode(); 7850 SDValue Value = Op.getOperand(0); 7851 EVT TheVT = Op.getOperand(0).getValueType(); 7852 // FIXME This causes a redundant load/store if the SSE-class value is already 7853 // in memory, such as if it is on the callstack. 7854 if (isScalarFPTypeInSSEReg(TheVT)) { 7855 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7856 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7857 MachinePointerInfo::getFixedStack(SSFI), 7858 false, false, 0); 7859 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7860 SDValue Ops[] = { 7861 Chain, StackSlot, DAG.getValueType(TheVT) 7862 }; 7863 7864 MachineMemOperand *MMO = 7865 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7866 MachineMemOperand::MOLoad, MemSize, MemSize); 7867 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7868 DstTy, MMO); 7869 Chain = Value.getValue(1); 7870 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7871 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7872 } 7873 7874 MachineMemOperand *MMO = 7875 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7876 MachineMemOperand::MOStore, MemSize, MemSize); 7877 7878 if (Opc != X86ISD::WIN_FTOL) { 7879 // Build the FP_TO_INT*_IN_MEM 7880 SDValue Ops[] = { Chain, Value, StackSlot }; 7881 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7882 Ops, 3, DstTy, MMO); 7883 return std::make_pair(FIST, StackSlot); 7884 } else { 7885 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7886 DAG.getVTList(MVT::Other, MVT::Glue), 7887 Chain, Value); 7888 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7889 MVT::i32, ftol.getValue(1)); 7890 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7891 MVT::i32, eax.getValue(2)); 7892 SDValue Ops[] = { eax, edx }; 7893 SDValue pair = IsReplace 7894 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7895 : DAG.getMergeValues(Ops, 2, DL); 7896 return std::make_pair(pair, SDValue()); 7897 } 7898} 7899 7900SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7901 SelectionDAG &DAG) const { 7902 if (Op.getValueType().isVector()) 7903 return SDValue(); 7904 7905 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7906 /*IsSigned=*/ true, /*IsReplace=*/ false); 7907 SDValue FIST = Vals.first, StackSlot = Vals.second; 7908 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7909 if (FIST.getNode() == 0) return Op; 7910 7911 if (StackSlot.getNode()) 7912 // Load the result. 7913 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7914 FIST, StackSlot, MachinePointerInfo(), 7915 false, false, false, 0); 7916 7917 // The node is the result. 7918 return FIST; 7919} 7920 7921SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7922 SelectionDAG &DAG) const { 7923 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7924 /*IsSigned=*/ false, /*IsReplace=*/ false); 7925 SDValue FIST = Vals.first, StackSlot = Vals.second; 7926 assert(FIST.getNode() && "Unexpected failure"); 7927 7928 if (StackSlot.getNode()) 7929 // Load the result. 7930 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7931 FIST, StackSlot, MachinePointerInfo(), 7932 false, false, false, 0); 7933 7934 // The node is the result. 7935 return FIST; 7936} 7937 7938SDValue X86TargetLowering::LowerFABS(SDValue Op, 7939 SelectionDAG &DAG) const { 7940 LLVMContext *Context = DAG.getContext(); 7941 DebugLoc dl = Op.getDebugLoc(); 7942 EVT VT = Op.getValueType(); 7943 EVT EltVT = VT; 7944 if (VT.isVector()) 7945 EltVT = VT.getVectorElementType(); 7946 Constant *C; 7947 if (EltVT == MVT::f64) { 7948 C = ConstantVector::getSplat(2, 7949 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7950 } else { 7951 C = ConstantVector::getSplat(4, 7952 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7953 } 7954 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7955 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7956 MachinePointerInfo::getConstantPool(), 7957 false, false, false, 16); 7958 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7959} 7960 7961SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7962 LLVMContext *Context = DAG.getContext(); 7963 DebugLoc dl = Op.getDebugLoc(); 7964 EVT VT = Op.getValueType(); 7965 EVT EltVT = VT; 7966 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7967 if (VT.isVector()) { 7968 EltVT = VT.getVectorElementType(); 7969 NumElts = VT.getVectorNumElements(); 7970 } 7971 Constant *C; 7972 if (EltVT == MVT::f64) 7973 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7974 else 7975 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7976 C = ConstantVector::getSplat(NumElts, C); 7977 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7978 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7979 MachinePointerInfo::getConstantPool(), 7980 false, false, false, 16); 7981 if (VT.isVector()) { 7982 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7983 return DAG.getNode(ISD::BITCAST, dl, VT, 7984 DAG.getNode(ISD::XOR, dl, XORVT, 7985 DAG.getNode(ISD::BITCAST, dl, XORVT, 7986 Op.getOperand(0)), 7987 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7988 } 7989 7990 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7991} 7992 7993SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7994 LLVMContext *Context = DAG.getContext(); 7995 SDValue Op0 = Op.getOperand(0); 7996 SDValue Op1 = Op.getOperand(1); 7997 DebugLoc dl = Op.getDebugLoc(); 7998 EVT VT = Op.getValueType(); 7999 EVT SrcVT = Op1.getValueType(); 8000 8001 // If second operand is smaller, extend it first. 8002 if (SrcVT.bitsLT(VT)) { 8003 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8004 SrcVT = VT; 8005 } 8006 // And if it is bigger, shrink it first. 8007 if (SrcVT.bitsGT(VT)) { 8008 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8009 SrcVT = VT; 8010 } 8011 8012 // At this point the operands and the result should have the same 8013 // type, and that won't be f80 since that is not custom lowered. 8014 8015 // First get the sign bit of second operand. 8016 SmallVector<Constant*,4> CV; 8017 if (SrcVT == MVT::f64) { 8018 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8019 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8020 } else { 8021 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8022 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8023 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8024 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8025 } 8026 Constant *C = ConstantVector::get(CV); 8027 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8028 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8029 MachinePointerInfo::getConstantPool(), 8030 false, false, false, 16); 8031 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8032 8033 // Shift sign bit right or left if the two operands have different types. 8034 if (SrcVT.bitsGT(VT)) { 8035 // Op0 is MVT::f32, Op1 is MVT::f64. 8036 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8037 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8038 DAG.getConstant(32, MVT::i32)); 8039 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8040 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8041 DAG.getIntPtrConstant(0)); 8042 } 8043 8044 // Clear first operand sign bit. 8045 CV.clear(); 8046 if (VT == MVT::f64) { 8047 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8048 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8049 } else { 8050 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8051 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8052 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8053 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8054 } 8055 C = ConstantVector::get(CV); 8056 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8057 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8058 MachinePointerInfo::getConstantPool(), 8059 false, false, false, 16); 8060 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8061 8062 // Or the value with the sign bit. 8063 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8064} 8065 8066SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8067 SDValue N0 = Op.getOperand(0); 8068 DebugLoc dl = Op.getDebugLoc(); 8069 EVT VT = Op.getValueType(); 8070 8071 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8072 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8073 DAG.getConstant(1, VT)); 8074 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8075} 8076 8077/// Emit nodes that will be selected as "test Op0,Op0", or something 8078/// equivalent. 8079SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8080 SelectionDAG &DAG) const { 8081 DebugLoc dl = Op.getDebugLoc(); 8082 8083 // CF and OF aren't always set the way we want. Determine which 8084 // of these we need. 8085 bool NeedCF = false; 8086 bool NeedOF = false; 8087 switch (X86CC) { 8088 default: break; 8089 case X86::COND_A: case X86::COND_AE: 8090 case X86::COND_B: case X86::COND_BE: 8091 NeedCF = true; 8092 break; 8093 case X86::COND_G: case X86::COND_GE: 8094 case X86::COND_L: case X86::COND_LE: 8095 case X86::COND_O: case X86::COND_NO: 8096 NeedOF = true; 8097 break; 8098 } 8099 8100 // See if we can use the EFLAGS value from the operand instead of 8101 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8102 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8103 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8104 // Emit a CMP with 0, which is the TEST pattern. 8105 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8106 DAG.getConstant(0, Op.getValueType())); 8107 8108 unsigned Opcode = 0; 8109 unsigned NumOperands = 0; 8110 switch (Op.getNode()->getOpcode()) { 8111 case ISD::ADD: 8112 // Due to an isel shortcoming, be conservative if this add is likely to be 8113 // selected as part of a load-modify-store instruction. When the root node 8114 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8115 // uses of other nodes in the match, such as the ADD in this case. This 8116 // leads to the ADD being left around and reselected, with the result being 8117 // two adds in the output. Alas, even if none our users are stores, that 8118 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8119 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8120 // climbing the DAG back to the root, and it doesn't seem to be worth the 8121 // effort. 8122 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8123 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8124 if (UI->getOpcode() != ISD::CopyToReg && 8125 UI->getOpcode() != ISD::SETCC && 8126 UI->getOpcode() != ISD::STORE) 8127 goto default_case; 8128 8129 if (ConstantSDNode *C = 8130 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8131 // An add of one will be selected as an INC. 8132 if (C->getAPIntValue() == 1) { 8133 Opcode = X86ISD::INC; 8134 NumOperands = 1; 8135 break; 8136 } 8137 8138 // An add of negative one (subtract of one) will be selected as a DEC. 8139 if (C->getAPIntValue().isAllOnesValue()) { 8140 Opcode = X86ISD::DEC; 8141 NumOperands = 1; 8142 break; 8143 } 8144 } 8145 8146 // Otherwise use a regular EFLAGS-setting add. 8147 Opcode = X86ISD::ADD; 8148 NumOperands = 2; 8149 break; 8150 case ISD::AND: { 8151 // If the primary and result isn't used, don't bother using X86ISD::AND, 8152 // because a TEST instruction will be better. 8153 bool NonFlagUse = false; 8154 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8155 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8156 SDNode *User = *UI; 8157 unsigned UOpNo = UI.getOperandNo(); 8158 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8159 // Look pass truncate. 8160 UOpNo = User->use_begin().getOperandNo(); 8161 User = *User->use_begin(); 8162 } 8163 8164 if (User->getOpcode() != ISD::BRCOND && 8165 User->getOpcode() != ISD::SETCC && 8166 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8167 NonFlagUse = true; 8168 break; 8169 } 8170 } 8171 8172 if (!NonFlagUse) 8173 break; 8174 } 8175 // FALL THROUGH 8176 case ISD::SUB: 8177 case ISD::OR: 8178 case ISD::XOR: 8179 // Due to the ISEL shortcoming noted above, be conservative if this op is 8180 // likely to be selected as part of a load-modify-store instruction. 8181 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8182 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8183 if (UI->getOpcode() == ISD::STORE) 8184 goto default_case; 8185 8186 // Otherwise use a regular EFLAGS-setting instruction. 8187 switch (Op.getNode()->getOpcode()) { 8188 default: llvm_unreachable("unexpected operator!"); 8189 case ISD::SUB: Opcode = X86ISD::SUB; break; 8190 case ISD::OR: Opcode = X86ISD::OR; break; 8191 case ISD::XOR: Opcode = X86ISD::XOR; break; 8192 case ISD::AND: Opcode = X86ISD::AND; break; 8193 } 8194 8195 NumOperands = 2; 8196 break; 8197 case X86ISD::ADD: 8198 case X86ISD::SUB: 8199 case X86ISD::INC: 8200 case X86ISD::DEC: 8201 case X86ISD::OR: 8202 case X86ISD::XOR: 8203 case X86ISD::AND: 8204 return SDValue(Op.getNode(), 1); 8205 default: 8206 default_case: 8207 break; 8208 } 8209 8210 if (Opcode == 0) 8211 // Emit a CMP with 0, which is the TEST pattern. 8212 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8213 DAG.getConstant(0, Op.getValueType())); 8214 8215 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8216 SmallVector<SDValue, 4> Ops; 8217 for (unsigned i = 0; i != NumOperands; ++i) 8218 Ops.push_back(Op.getOperand(i)); 8219 8220 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8221 DAG.ReplaceAllUsesWith(Op, New); 8222 return SDValue(New.getNode(), 1); 8223} 8224 8225/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8226/// equivalent. 8227SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8228 SelectionDAG &DAG) const { 8229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8230 if (C->getAPIntValue() == 0) 8231 return EmitTest(Op0, X86CC, DAG); 8232 8233 DebugLoc dl = Op0.getDebugLoc(); 8234 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8235} 8236 8237/// Convert a comparison if required by the subtarget. 8238SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 8239 SelectionDAG &DAG) const { 8240 // If the subtarget does not support the FUCOMI instruction, floating-point 8241 // comparisons have to be converted. 8242 if (Subtarget->hasCMov() || 8243 Cmp.getOpcode() != X86ISD::CMP || 8244 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 8245 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 8246 return Cmp; 8247 8248 // The instruction selector will select an FUCOM instruction instead of 8249 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 8250 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 8251 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 8252 DebugLoc dl = Cmp.getDebugLoc(); 8253 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 8254 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 8255 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 8256 DAG.getConstant(8, MVT::i8)); 8257 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 8258 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 8259} 8260 8261/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8262/// if it's possible. 8263SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8264 DebugLoc dl, SelectionDAG &DAG) const { 8265 SDValue Op0 = And.getOperand(0); 8266 SDValue Op1 = And.getOperand(1); 8267 if (Op0.getOpcode() == ISD::TRUNCATE) 8268 Op0 = Op0.getOperand(0); 8269 if (Op1.getOpcode() == ISD::TRUNCATE) 8270 Op1 = Op1.getOperand(0); 8271 8272 SDValue LHS, RHS; 8273 if (Op1.getOpcode() == ISD::SHL) 8274 std::swap(Op0, Op1); 8275 if (Op0.getOpcode() == ISD::SHL) { 8276 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8277 if (And00C->getZExtValue() == 1) { 8278 // If we looked past a truncate, check that it's only truncating away 8279 // known zeros. 8280 unsigned BitWidth = Op0.getValueSizeInBits(); 8281 unsigned AndBitWidth = And.getValueSizeInBits(); 8282 if (BitWidth > AndBitWidth) { 8283 APInt Zeros, Ones; 8284 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8285 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8286 return SDValue(); 8287 } 8288 LHS = Op1; 8289 RHS = Op0.getOperand(1); 8290 } 8291 } else if (Op1.getOpcode() == ISD::Constant) { 8292 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8293 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8294 SDValue AndLHS = Op0; 8295 8296 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8297 LHS = AndLHS.getOperand(0); 8298 RHS = AndLHS.getOperand(1); 8299 } 8300 8301 // Use BT if the immediate can't be encoded in a TEST instruction. 8302 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8303 LHS = AndLHS; 8304 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8305 } 8306 } 8307 8308 if (LHS.getNode()) { 8309 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8310 // instruction. Since the shift amount is in-range-or-undefined, we know 8311 // that doing a bittest on the i32 value is ok. We extend to i32 because 8312 // the encoding for the i16 version is larger than the i32 version. 8313 // Also promote i16 to i32 for performance / code size reason. 8314 if (LHS.getValueType() == MVT::i8 || 8315 LHS.getValueType() == MVT::i16) 8316 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8317 8318 // If the operand types disagree, extend the shift amount to match. Since 8319 // BT ignores high bits (like shifts) we can use anyextend. 8320 if (LHS.getValueType() != RHS.getValueType()) 8321 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8322 8323 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8324 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8325 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8326 DAG.getConstant(Cond, MVT::i8), BT); 8327 } 8328 8329 return SDValue(); 8330} 8331 8332SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8333 8334 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8335 8336 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8337 SDValue Op0 = Op.getOperand(0); 8338 SDValue Op1 = Op.getOperand(1); 8339 DebugLoc dl = Op.getDebugLoc(); 8340 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8341 8342 // Optimize to BT if possible. 8343 // Lower (X & (1 << N)) == 0 to BT(X, N). 8344 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8345 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8346 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8347 Op1.getOpcode() == ISD::Constant && 8348 cast<ConstantSDNode>(Op1)->isNullValue() && 8349 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8350 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8351 if (NewSetCC.getNode()) 8352 return NewSetCC; 8353 } 8354 8355 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8356 // these. 8357 if (Op1.getOpcode() == ISD::Constant && 8358 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8359 cast<ConstantSDNode>(Op1)->isNullValue()) && 8360 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8361 8362 // If the input is a setcc, then reuse the input setcc or use a new one with 8363 // the inverted condition. 8364 if (Op0.getOpcode() == X86ISD::SETCC) { 8365 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8366 bool Invert = (CC == ISD::SETNE) ^ 8367 cast<ConstantSDNode>(Op1)->isNullValue(); 8368 if (!Invert) return Op0; 8369 8370 CCode = X86::GetOppositeBranchCondition(CCode); 8371 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8372 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8373 } 8374 } 8375 8376 bool isFP = Op1.getValueType().isFloatingPoint(); 8377 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8378 if (X86CC == X86::COND_INVALID) 8379 return SDValue(); 8380 8381 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8382 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 8383 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8384 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8385} 8386 8387// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8388// ones, and then concatenate the result back. 8389static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8390 EVT VT = Op.getValueType(); 8391 8392 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8393 "Unsupported value type for operation"); 8394 8395 unsigned NumElems = VT.getVectorNumElements(); 8396 DebugLoc dl = Op.getDebugLoc(); 8397 SDValue CC = Op.getOperand(2); 8398 8399 // Extract the LHS vectors 8400 SDValue LHS = Op.getOperand(0); 8401 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 8402 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 8403 8404 // Extract the RHS vectors 8405 SDValue RHS = Op.getOperand(1); 8406 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 8407 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 8408 8409 // Issue the operation on the smaller types and concatenate the result back 8410 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8411 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8412 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8413 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8414 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8415} 8416 8417 8418SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8419 SDValue Cond; 8420 SDValue Op0 = Op.getOperand(0); 8421 SDValue Op1 = Op.getOperand(1); 8422 SDValue CC = Op.getOperand(2); 8423 EVT VT = Op.getValueType(); 8424 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8425 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8426 DebugLoc dl = Op.getDebugLoc(); 8427 8428 if (isFP) { 8429 unsigned SSECC = 8; 8430 EVT EltVT = Op0.getValueType().getVectorElementType(); 8431 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8432 8433 bool Swap = false; 8434 8435 // SSE Condition code mapping: 8436 // 0 - EQ 8437 // 1 - LT 8438 // 2 - LE 8439 // 3 - UNORD 8440 // 4 - NEQ 8441 // 5 - NLT 8442 // 6 - NLE 8443 // 7 - ORD 8444 switch (SetCCOpcode) { 8445 default: break; 8446 case ISD::SETOEQ: 8447 case ISD::SETEQ: SSECC = 0; break; 8448 case ISD::SETOGT: 8449 case ISD::SETGT: Swap = true; // Fallthrough 8450 case ISD::SETLT: 8451 case ISD::SETOLT: SSECC = 1; break; 8452 case ISD::SETOGE: 8453 case ISD::SETGE: Swap = true; // Fallthrough 8454 case ISD::SETLE: 8455 case ISD::SETOLE: SSECC = 2; break; 8456 case ISD::SETUO: SSECC = 3; break; 8457 case ISD::SETUNE: 8458 case ISD::SETNE: SSECC = 4; break; 8459 case ISD::SETULE: Swap = true; 8460 case ISD::SETUGE: SSECC = 5; break; 8461 case ISD::SETULT: Swap = true; 8462 case ISD::SETUGT: SSECC = 6; break; 8463 case ISD::SETO: SSECC = 7; break; 8464 } 8465 if (Swap) 8466 std::swap(Op0, Op1); 8467 8468 // In the two special cases we can't handle, emit two comparisons. 8469 if (SSECC == 8) { 8470 if (SetCCOpcode == ISD::SETUEQ) { 8471 SDValue UNORD, EQ; 8472 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8473 DAG.getConstant(3, MVT::i8)); 8474 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8475 DAG.getConstant(0, MVT::i8)); 8476 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8477 } 8478 if (SetCCOpcode == ISD::SETONE) { 8479 SDValue ORD, NEQ; 8480 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8481 DAG.getConstant(7, MVT::i8)); 8482 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8483 DAG.getConstant(4, MVT::i8)); 8484 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8485 } 8486 llvm_unreachable("Illegal FP comparison"); 8487 } 8488 // Handle all other FP comparisons here. 8489 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8490 DAG.getConstant(SSECC, MVT::i8)); 8491 } 8492 8493 // Break 256-bit integer vector compare into smaller ones. 8494 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8495 return Lower256IntVSETCC(Op, DAG); 8496 8497 // We are handling one of the integer comparisons here. Since SSE only has 8498 // GT and EQ comparisons for integer, swapping operands and multiple 8499 // operations may be required for some comparisons. 8500 unsigned Opc = 0; 8501 bool Swap = false, Invert = false, FlipSigns = false; 8502 8503 switch (SetCCOpcode) { 8504 default: break; 8505 case ISD::SETNE: Invert = true; 8506 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8507 case ISD::SETLT: Swap = true; 8508 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8509 case ISD::SETGE: Swap = true; 8510 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8511 case ISD::SETULT: Swap = true; 8512 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8513 case ISD::SETUGE: Swap = true; 8514 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8515 } 8516 if (Swap) 8517 std::swap(Op0, Op1); 8518 8519 // Check that the operation in question is available (most are plain SSE2, 8520 // but PCMPGTQ and PCMPEQQ have different requirements). 8521 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8522 return SDValue(); 8523 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8524 return SDValue(); 8525 8526 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8527 // bits of the inputs before performing those operations. 8528 if (FlipSigns) { 8529 EVT EltVT = VT.getVectorElementType(); 8530 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8531 EltVT); 8532 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8533 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8534 SignBits.size()); 8535 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8536 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8537 } 8538 8539 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8540 8541 // If the logical-not of the result is required, perform that now. 8542 if (Invert) 8543 Result = DAG.getNOT(dl, Result, VT); 8544 8545 return Result; 8546} 8547 8548// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8549static bool isX86LogicalCmp(SDValue Op) { 8550 unsigned Opc = Op.getNode()->getOpcode(); 8551 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 8552 Opc == X86ISD::SAHF) 8553 return true; 8554 if (Op.getResNo() == 1 && 8555 (Opc == X86ISD::ADD || 8556 Opc == X86ISD::SUB || 8557 Opc == X86ISD::ADC || 8558 Opc == X86ISD::SBB || 8559 Opc == X86ISD::SMUL || 8560 Opc == X86ISD::UMUL || 8561 Opc == X86ISD::INC || 8562 Opc == X86ISD::DEC || 8563 Opc == X86ISD::OR || 8564 Opc == X86ISD::XOR || 8565 Opc == X86ISD::AND)) 8566 return true; 8567 8568 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8569 return true; 8570 8571 return false; 8572} 8573 8574static bool isZero(SDValue V) { 8575 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8576 return C && C->isNullValue(); 8577} 8578 8579static bool isAllOnes(SDValue V) { 8580 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8581 return C && C->isAllOnesValue(); 8582} 8583 8584SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8585 bool addTest = true; 8586 SDValue Cond = Op.getOperand(0); 8587 SDValue Op1 = Op.getOperand(1); 8588 SDValue Op2 = Op.getOperand(2); 8589 DebugLoc DL = Op.getDebugLoc(); 8590 SDValue CC; 8591 8592 if (Cond.getOpcode() == ISD::SETCC) { 8593 SDValue NewCond = LowerSETCC(Cond, DAG); 8594 if (NewCond.getNode()) 8595 Cond = NewCond; 8596 } 8597 8598 // Handle the following cases related to max and min: 8599 // (a > b) ? (a-b) : 0 8600 // (a >= b) ? (a-b) : 0 8601 // (b < a) ? (a-b) : 0 8602 // (b <= a) ? (a-b) : 0 8603 // Comparison is removed to use EFLAGS from SUB. 8604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2)) 8605 if (Cond.getOpcode() == X86ISD::SETCC && 8606 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8607 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) && 8608 C->getAPIntValue() == 0) { 8609 SDValue Cmp = Cond.getOperand(1); 8610 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8611 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) && 8612 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) && 8613 (CC == X86::COND_G || CC == X86::COND_GE || 8614 CC == X86::COND_A || CC == X86::COND_AE)) || 8615 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) && 8616 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) && 8617 (CC == X86::COND_L || CC == X86::COND_LE || 8618 CC == X86::COND_B || CC == X86::COND_BE))) { 8619 8620 if (Op1.getOpcode() == ISD::SUB) { 8621 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32); 8622 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs, 8623 Op1.getOperand(0), Op1.getOperand(1)); 8624 DAG.ReplaceAllUsesWith(Op1, New); 8625 Op1 = New; 8626 } 8627 8628 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8629 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE || 8630 CC == X86::COND_L || 8631 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE; 8632 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8), 8633 SDValue(Op1.getNode(), 1) }; 8634 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8635 } 8636 } 8637 8638 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8639 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8640 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8641 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8642 if (Cond.getOpcode() == X86ISD::SETCC && 8643 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8644 isZero(Cond.getOperand(1).getOperand(1))) { 8645 SDValue Cmp = Cond.getOperand(1); 8646 8647 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8648 8649 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8650 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8651 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8652 8653 SDValue CmpOp0 = Cmp.getOperand(0); 8654 // further optimization for special cases 8655 // (select (x != 0), -1, 0) -> neg & sbb 8656 // (select (x == 0), 0, -1) -> neg & sbb 8657 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 8658 if (YC->isNullValue() && 8659 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 8660 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 8661 SDValue Neg = DAG.getNode(ISD::SUB, DL, VTs, 8662 DAG.getConstant(0, CmpOp0.getValueType()), 8663 CmpOp0); 8664 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8665 DAG.getConstant(X86::COND_B, MVT::i8), 8666 SDValue(Neg.getNode(), 1)); 8667 return Res; 8668 } 8669 8670 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8671 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8672 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8673 8674 SDValue Res = // Res = 0 or -1. 8675 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8676 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8677 8678 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8679 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8680 8681 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8682 if (N2C == 0 || !N2C->isNullValue()) 8683 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8684 return Res; 8685 } 8686 } 8687 8688 // Look past (and (setcc_carry (cmp ...)), 1). 8689 if (Cond.getOpcode() == ISD::AND && 8690 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8691 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8692 if (C && C->getAPIntValue() == 1) 8693 Cond = Cond.getOperand(0); 8694 } 8695 8696 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8697 // setting operand in place of the X86ISD::SETCC. 8698 unsigned CondOpcode = Cond.getOpcode(); 8699 if (CondOpcode == X86ISD::SETCC || 8700 CondOpcode == X86ISD::SETCC_CARRY) { 8701 CC = Cond.getOperand(0); 8702 8703 SDValue Cmp = Cond.getOperand(1); 8704 unsigned Opc = Cmp.getOpcode(); 8705 EVT VT = Op.getValueType(); 8706 8707 bool IllegalFPCMov = false; 8708 if (VT.isFloatingPoint() && !VT.isVector() && 8709 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8710 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8711 8712 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8713 Opc == X86ISD::BT) { // FIXME 8714 Cond = Cmp; 8715 addTest = false; 8716 } 8717 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8718 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8719 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8720 Cond.getOperand(0).getValueType() != MVT::i8)) { 8721 SDValue LHS = Cond.getOperand(0); 8722 SDValue RHS = Cond.getOperand(1); 8723 unsigned X86Opcode; 8724 unsigned X86Cond; 8725 SDVTList VTs; 8726 switch (CondOpcode) { 8727 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8728 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8729 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8730 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8731 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8732 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8733 default: llvm_unreachable("unexpected overflowing operator"); 8734 } 8735 if (CondOpcode == ISD::UMULO) 8736 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8737 MVT::i32); 8738 else 8739 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8740 8741 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8742 8743 if (CondOpcode == ISD::UMULO) 8744 Cond = X86Op.getValue(2); 8745 else 8746 Cond = X86Op.getValue(1); 8747 8748 CC = DAG.getConstant(X86Cond, MVT::i8); 8749 addTest = false; 8750 } 8751 8752 if (addTest) { 8753 // Look pass the truncate. 8754 if (Cond.getOpcode() == ISD::TRUNCATE) 8755 Cond = Cond.getOperand(0); 8756 8757 // We know the result of AND is compared against zero. Try to match 8758 // it to BT. 8759 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8760 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8761 if (NewSetCC.getNode()) { 8762 CC = NewSetCC.getOperand(0); 8763 Cond = NewSetCC.getOperand(1); 8764 addTest = false; 8765 } 8766 } 8767 } 8768 8769 if (addTest) { 8770 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8771 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8772 } 8773 8774 // a < b ? -1 : 0 -> RES = ~setcc_carry 8775 // a < b ? 0 : -1 -> RES = setcc_carry 8776 // a >= b ? -1 : 0 -> RES = setcc_carry 8777 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8778 if (Cond.getOpcode() == X86ISD::CMP) { 8779 Cond = ConvertCmpIfNecessary(Cond, DAG); 8780 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8781 8782 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8783 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8784 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8785 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8786 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8787 return DAG.getNOT(DL, Res, Res.getValueType()); 8788 return Res; 8789 } 8790 } 8791 8792 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8793 // condition is true. 8794 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8795 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8796 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8797} 8798 8799// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8800// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8801// from the AND / OR. 8802static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8803 Opc = Op.getOpcode(); 8804 if (Opc != ISD::OR && Opc != ISD::AND) 8805 return false; 8806 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8807 Op.getOperand(0).hasOneUse() && 8808 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8809 Op.getOperand(1).hasOneUse()); 8810} 8811 8812// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8813// 1 and that the SETCC node has a single use. 8814static bool isXor1OfSetCC(SDValue Op) { 8815 if (Op.getOpcode() != ISD::XOR) 8816 return false; 8817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8818 if (N1C && N1C->getAPIntValue() == 1) { 8819 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8820 Op.getOperand(0).hasOneUse(); 8821 } 8822 return false; 8823} 8824 8825SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8826 bool addTest = true; 8827 SDValue Chain = Op.getOperand(0); 8828 SDValue Cond = Op.getOperand(1); 8829 SDValue Dest = Op.getOperand(2); 8830 DebugLoc dl = Op.getDebugLoc(); 8831 SDValue CC; 8832 bool Inverted = false; 8833 8834 if (Cond.getOpcode() == ISD::SETCC) { 8835 // Check for setcc([su]{add,sub,mul}o == 0). 8836 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8837 isa<ConstantSDNode>(Cond.getOperand(1)) && 8838 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8839 Cond.getOperand(0).getResNo() == 1 && 8840 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8841 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8842 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8843 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8844 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8845 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8846 Inverted = true; 8847 Cond = Cond.getOperand(0); 8848 } else { 8849 SDValue NewCond = LowerSETCC(Cond, DAG); 8850 if (NewCond.getNode()) 8851 Cond = NewCond; 8852 } 8853 } 8854#if 0 8855 // FIXME: LowerXALUO doesn't handle these!! 8856 else if (Cond.getOpcode() == X86ISD::ADD || 8857 Cond.getOpcode() == X86ISD::SUB || 8858 Cond.getOpcode() == X86ISD::SMUL || 8859 Cond.getOpcode() == X86ISD::UMUL) 8860 Cond = LowerXALUO(Cond, DAG); 8861#endif 8862 8863 // Look pass (and (setcc_carry (cmp ...)), 1). 8864 if (Cond.getOpcode() == ISD::AND && 8865 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8867 if (C && C->getAPIntValue() == 1) 8868 Cond = Cond.getOperand(0); 8869 } 8870 8871 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8872 // setting operand in place of the X86ISD::SETCC. 8873 unsigned CondOpcode = Cond.getOpcode(); 8874 if (CondOpcode == X86ISD::SETCC || 8875 CondOpcode == X86ISD::SETCC_CARRY) { 8876 CC = Cond.getOperand(0); 8877 8878 SDValue Cmp = Cond.getOperand(1); 8879 unsigned Opc = Cmp.getOpcode(); 8880 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8881 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8882 Cond = Cmp; 8883 addTest = false; 8884 } else { 8885 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8886 default: break; 8887 case X86::COND_O: 8888 case X86::COND_B: 8889 // These can only come from an arithmetic instruction with overflow, 8890 // e.g. SADDO, UADDO. 8891 Cond = Cond.getNode()->getOperand(1); 8892 addTest = false; 8893 break; 8894 } 8895 } 8896 } 8897 CondOpcode = Cond.getOpcode(); 8898 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8899 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8900 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8901 Cond.getOperand(0).getValueType() != MVT::i8)) { 8902 SDValue LHS = Cond.getOperand(0); 8903 SDValue RHS = Cond.getOperand(1); 8904 unsigned X86Opcode; 8905 unsigned X86Cond; 8906 SDVTList VTs; 8907 switch (CondOpcode) { 8908 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8909 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8910 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8911 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8912 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8913 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8914 default: llvm_unreachable("unexpected overflowing operator"); 8915 } 8916 if (Inverted) 8917 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8918 if (CondOpcode == ISD::UMULO) 8919 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8920 MVT::i32); 8921 else 8922 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8923 8924 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8925 8926 if (CondOpcode == ISD::UMULO) 8927 Cond = X86Op.getValue(2); 8928 else 8929 Cond = X86Op.getValue(1); 8930 8931 CC = DAG.getConstant(X86Cond, MVT::i8); 8932 addTest = false; 8933 } else { 8934 unsigned CondOpc; 8935 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8936 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8937 if (CondOpc == ISD::OR) { 8938 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8939 // two branches instead of an explicit OR instruction with a 8940 // separate test. 8941 if (Cmp == Cond.getOperand(1).getOperand(1) && 8942 isX86LogicalCmp(Cmp)) { 8943 CC = Cond.getOperand(0).getOperand(0); 8944 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8945 Chain, Dest, CC, Cmp); 8946 CC = Cond.getOperand(1).getOperand(0); 8947 Cond = Cmp; 8948 addTest = false; 8949 } 8950 } else { // ISD::AND 8951 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8952 // two branches instead of an explicit AND instruction with a 8953 // separate test. However, we only do this if this block doesn't 8954 // have a fall-through edge, because this requires an explicit 8955 // jmp when the condition is false. 8956 if (Cmp == Cond.getOperand(1).getOperand(1) && 8957 isX86LogicalCmp(Cmp) && 8958 Op.getNode()->hasOneUse()) { 8959 X86::CondCode CCode = 8960 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8961 CCode = X86::GetOppositeBranchCondition(CCode); 8962 CC = DAG.getConstant(CCode, MVT::i8); 8963 SDNode *User = *Op.getNode()->use_begin(); 8964 // Look for an unconditional branch following this conditional branch. 8965 // We need this because we need to reverse the successors in order 8966 // to implement FCMP_OEQ. 8967 if (User->getOpcode() == ISD::BR) { 8968 SDValue FalseBB = User->getOperand(1); 8969 SDNode *NewBR = 8970 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8971 assert(NewBR == User); 8972 (void)NewBR; 8973 Dest = FalseBB; 8974 8975 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8976 Chain, Dest, CC, Cmp); 8977 X86::CondCode CCode = 8978 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8979 CCode = X86::GetOppositeBranchCondition(CCode); 8980 CC = DAG.getConstant(CCode, MVT::i8); 8981 Cond = Cmp; 8982 addTest = false; 8983 } 8984 } 8985 } 8986 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8987 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8988 // It should be transformed during dag combiner except when the condition 8989 // is set by a arithmetics with overflow node. 8990 X86::CondCode CCode = 8991 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8992 CCode = X86::GetOppositeBranchCondition(CCode); 8993 CC = DAG.getConstant(CCode, MVT::i8); 8994 Cond = Cond.getOperand(0).getOperand(1); 8995 addTest = false; 8996 } else if (Cond.getOpcode() == ISD::SETCC && 8997 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8998 // For FCMP_OEQ, we can emit 8999 // two branches instead of an explicit AND instruction with a 9000 // separate test. However, we only do this if this block doesn't 9001 // have a fall-through edge, because this requires an explicit 9002 // jmp when the condition is false. 9003 if (Op.getNode()->hasOneUse()) { 9004 SDNode *User = *Op.getNode()->use_begin(); 9005 // Look for an unconditional branch following this conditional branch. 9006 // We need this because we need to reverse the successors in order 9007 // to implement FCMP_OEQ. 9008 if (User->getOpcode() == ISD::BR) { 9009 SDValue FalseBB = User->getOperand(1); 9010 SDNode *NewBR = 9011 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9012 assert(NewBR == User); 9013 (void)NewBR; 9014 Dest = FalseBB; 9015 9016 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9017 Cond.getOperand(0), Cond.getOperand(1)); 9018 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9019 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9020 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9021 Chain, Dest, CC, Cmp); 9022 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9023 Cond = Cmp; 9024 addTest = false; 9025 } 9026 } 9027 } else if (Cond.getOpcode() == ISD::SETCC && 9028 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9029 // For FCMP_UNE, we can emit 9030 // two branches instead of an explicit AND instruction with a 9031 // separate test. However, we only do this if this block doesn't 9032 // have a fall-through edge, because this requires an explicit 9033 // jmp when the condition is false. 9034 if (Op.getNode()->hasOneUse()) { 9035 SDNode *User = *Op.getNode()->use_begin(); 9036 // Look for an unconditional branch following this conditional branch. 9037 // We need this because we need to reverse the successors in order 9038 // to implement FCMP_UNE. 9039 if (User->getOpcode() == ISD::BR) { 9040 SDValue FalseBB = User->getOperand(1); 9041 SDNode *NewBR = 9042 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9043 assert(NewBR == User); 9044 (void)NewBR; 9045 9046 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9047 Cond.getOperand(0), Cond.getOperand(1)); 9048 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9049 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9050 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9051 Chain, Dest, CC, Cmp); 9052 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9053 Cond = Cmp; 9054 addTest = false; 9055 Dest = FalseBB; 9056 } 9057 } 9058 } 9059 } 9060 9061 if (addTest) { 9062 // Look pass the truncate. 9063 if (Cond.getOpcode() == ISD::TRUNCATE) 9064 Cond = Cond.getOperand(0); 9065 9066 // We know the result of AND is compared against zero. Try to match 9067 // it to BT. 9068 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9069 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9070 if (NewSetCC.getNode()) { 9071 CC = NewSetCC.getOperand(0); 9072 Cond = NewSetCC.getOperand(1); 9073 addTest = false; 9074 } 9075 } 9076 } 9077 9078 if (addTest) { 9079 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9080 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9081 } 9082 Cond = ConvertCmpIfNecessary(Cond, DAG); 9083 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9084 Chain, Dest, CC, Cond); 9085} 9086 9087 9088// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9089// Calls to _alloca is needed to probe the stack when allocating more than 4k 9090// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9091// that the guard pages used by the OS virtual memory manager are allocated in 9092// correct sequence. 9093SDValue 9094X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9095 SelectionDAG &DAG) const { 9096 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9097 getTargetMachine().Options.EnableSegmentedStacks) && 9098 "This should be used only on Windows targets or when segmented stacks " 9099 "are being used"); 9100 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9101 DebugLoc dl = Op.getDebugLoc(); 9102 9103 // Get the inputs. 9104 SDValue Chain = Op.getOperand(0); 9105 SDValue Size = Op.getOperand(1); 9106 // FIXME: Ensure alignment here 9107 9108 bool Is64Bit = Subtarget->is64Bit(); 9109 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9110 9111 if (getTargetMachine().Options.EnableSegmentedStacks) { 9112 MachineFunction &MF = DAG.getMachineFunction(); 9113 MachineRegisterInfo &MRI = MF.getRegInfo(); 9114 9115 if (Is64Bit) { 9116 // The 64 bit implementation of segmented stacks needs to clobber both r10 9117 // r11. This makes it impossible to use it along with nested parameters. 9118 const Function *F = MF.getFunction(); 9119 9120 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9121 I != E; I++) 9122 if (I->hasNestAttr()) 9123 report_fatal_error("Cannot use segmented stacks with functions that " 9124 "have nested arguments."); 9125 } 9126 9127 const TargetRegisterClass *AddrRegClass = 9128 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9129 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9130 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9131 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9132 DAG.getRegister(Vreg, SPTy)); 9133 SDValue Ops1[2] = { Value, Chain }; 9134 return DAG.getMergeValues(Ops1, 2, dl); 9135 } else { 9136 SDValue Flag; 9137 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9138 9139 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9140 Flag = Chain.getValue(1); 9141 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9142 9143 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9144 Flag = Chain.getValue(1); 9145 9146 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9147 9148 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9149 return DAG.getMergeValues(Ops1, 2, dl); 9150 } 9151} 9152 9153SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9154 MachineFunction &MF = DAG.getMachineFunction(); 9155 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9156 9157 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9158 DebugLoc DL = Op.getDebugLoc(); 9159 9160 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9161 // vastart just stores the address of the VarArgsFrameIndex slot into the 9162 // memory location argument. 9163 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9164 getPointerTy()); 9165 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9166 MachinePointerInfo(SV), false, false, 0); 9167 } 9168 9169 // __va_list_tag: 9170 // gp_offset (0 - 6 * 8) 9171 // fp_offset (48 - 48 + 8 * 16) 9172 // overflow_arg_area (point to parameters coming in memory). 9173 // reg_save_area 9174 SmallVector<SDValue, 8> MemOps; 9175 SDValue FIN = Op.getOperand(1); 9176 // Store gp_offset 9177 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9178 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9179 MVT::i32), 9180 FIN, MachinePointerInfo(SV), false, false, 0); 9181 MemOps.push_back(Store); 9182 9183 // Store fp_offset 9184 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9185 FIN, DAG.getIntPtrConstant(4)); 9186 Store = DAG.getStore(Op.getOperand(0), DL, 9187 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9188 MVT::i32), 9189 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9190 MemOps.push_back(Store); 9191 9192 // Store ptr to overflow_arg_area 9193 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9194 FIN, DAG.getIntPtrConstant(4)); 9195 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9196 getPointerTy()); 9197 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9198 MachinePointerInfo(SV, 8), 9199 false, false, 0); 9200 MemOps.push_back(Store); 9201 9202 // Store ptr to reg_save_area. 9203 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9204 FIN, DAG.getIntPtrConstant(8)); 9205 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9206 getPointerTy()); 9207 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9208 MachinePointerInfo(SV, 16), false, false, 0); 9209 MemOps.push_back(Store); 9210 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9211 &MemOps[0], MemOps.size()); 9212} 9213 9214SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9215 assert(Subtarget->is64Bit() && 9216 "LowerVAARG only handles 64-bit va_arg!"); 9217 assert((Subtarget->isTargetLinux() || 9218 Subtarget->isTargetDarwin()) && 9219 "Unhandled target in LowerVAARG"); 9220 assert(Op.getNode()->getNumOperands() == 4); 9221 SDValue Chain = Op.getOperand(0); 9222 SDValue SrcPtr = Op.getOperand(1); 9223 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9224 unsigned Align = Op.getConstantOperandVal(3); 9225 DebugLoc dl = Op.getDebugLoc(); 9226 9227 EVT ArgVT = Op.getNode()->getValueType(0); 9228 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9229 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9230 uint8_t ArgMode; 9231 9232 // Decide which area this value should be read from. 9233 // TODO: Implement the AMD64 ABI in its entirety. This simple 9234 // selection mechanism works only for the basic types. 9235 if (ArgVT == MVT::f80) { 9236 llvm_unreachable("va_arg for f80 not yet implemented"); 9237 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9238 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9239 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9240 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9241 } else { 9242 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9243 } 9244 9245 if (ArgMode == 2) { 9246 // Sanity Check: Make sure using fp_offset makes sense. 9247 assert(!getTargetMachine().Options.UseSoftFloat && 9248 !(DAG.getMachineFunction() 9249 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9250 Subtarget->hasSSE1()); 9251 } 9252 9253 // Insert VAARG_64 node into the DAG 9254 // VAARG_64 returns two values: Variable Argument Address, Chain 9255 SmallVector<SDValue, 11> InstOps; 9256 InstOps.push_back(Chain); 9257 InstOps.push_back(SrcPtr); 9258 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9259 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9260 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9261 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9262 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9263 VTs, &InstOps[0], InstOps.size(), 9264 MVT::i64, 9265 MachinePointerInfo(SV), 9266 /*Align=*/0, 9267 /*Volatile=*/false, 9268 /*ReadMem=*/true, 9269 /*WriteMem=*/true); 9270 Chain = VAARG.getValue(1); 9271 9272 // Load the next argument and return it 9273 return DAG.getLoad(ArgVT, dl, 9274 Chain, 9275 VAARG, 9276 MachinePointerInfo(), 9277 false, false, false, 0); 9278} 9279 9280SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9281 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9282 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9283 SDValue Chain = Op.getOperand(0); 9284 SDValue DstPtr = Op.getOperand(1); 9285 SDValue SrcPtr = Op.getOperand(2); 9286 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9287 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9288 DebugLoc DL = Op.getDebugLoc(); 9289 9290 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9291 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9292 false, 9293 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9294} 9295 9296// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9297// may or may not be a constant. Takes immediate version of shift as input. 9298static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9299 SDValue SrcOp, SDValue ShAmt, 9300 SelectionDAG &DAG) { 9301 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9302 9303 if (isa<ConstantSDNode>(ShAmt)) { 9304 switch (Opc) { 9305 default: llvm_unreachable("Unknown target vector shift node"); 9306 case X86ISD::VSHLI: 9307 case X86ISD::VSRLI: 9308 case X86ISD::VSRAI: 9309 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9310 } 9311 } 9312 9313 // Change opcode to non-immediate version 9314 switch (Opc) { 9315 default: llvm_unreachable("Unknown target vector shift node"); 9316 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9317 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9318 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9319 } 9320 9321 // Need to build a vector containing shift amount 9322 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9323 SDValue ShOps[4]; 9324 ShOps[0] = ShAmt; 9325 ShOps[1] = DAG.getConstant(0, MVT::i32); 9326 ShOps[2] = DAG.getUNDEF(MVT::i32); 9327 ShOps[3] = DAG.getUNDEF(MVT::i32); 9328 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9329 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9330 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9331} 9332 9333SDValue 9334X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9335 DebugLoc dl = Op.getDebugLoc(); 9336 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9337 switch (IntNo) { 9338 default: return SDValue(); // Don't custom lower most intrinsics. 9339 // Comparison intrinsics. 9340 case Intrinsic::x86_sse_comieq_ss: 9341 case Intrinsic::x86_sse_comilt_ss: 9342 case Intrinsic::x86_sse_comile_ss: 9343 case Intrinsic::x86_sse_comigt_ss: 9344 case Intrinsic::x86_sse_comige_ss: 9345 case Intrinsic::x86_sse_comineq_ss: 9346 case Intrinsic::x86_sse_ucomieq_ss: 9347 case Intrinsic::x86_sse_ucomilt_ss: 9348 case Intrinsic::x86_sse_ucomile_ss: 9349 case Intrinsic::x86_sse_ucomigt_ss: 9350 case Intrinsic::x86_sse_ucomige_ss: 9351 case Intrinsic::x86_sse_ucomineq_ss: 9352 case Intrinsic::x86_sse2_comieq_sd: 9353 case Intrinsic::x86_sse2_comilt_sd: 9354 case Intrinsic::x86_sse2_comile_sd: 9355 case Intrinsic::x86_sse2_comigt_sd: 9356 case Intrinsic::x86_sse2_comige_sd: 9357 case Intrinsic::x86_sse2_comineq_sd: 9358 case Intrinsic::x86_sse2_ucomieq_sd: 9359 case Intrinsic::x86_sse2_ucomilt_sd: 9360 case Intrinsic::x86_sse2_ucomile_sd: 9361 case Intrinsic::x86_sse2_ucomigt_sd: 9362 case Intrinsic::x86_sse2_ucomige_sd: 9363 case Intrinsic::x86_sse2_ucomineq_sd: { 9364 unsigned Opc = 0; 9365 ISD::CondCode CC = ISD::SETCC_INVALID; 9366 switch (IntNo) { 9367 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9368 case Intrinsic::x86_sse_comieq_ss: 9369 case Intrinsic::x86_sse2_comieq_sd: 9370 Opc = X86ISD::COMI; 9371 CC = ISD::SETEQ; 9372 break; 9373 case Intrinsic::x86_sse_comilt_ss: 9374 case Intrinsic::x86_sse2_comilt_sd: 9375 Opc = X86ISD::COMI; 9376 CC = ISD::SETLT; 9377 break; 9378 case Intrinsic::x86_sse_comile_ss: 9379 case Intrinsic::x86_sse2_comile_sd: 9380 Opc = X86ISD::COMI; 9381 CC = ISD::SETLE; 9382 break; 9383 case Intrinsic::x86_sse_comigt_ss: 9384 case Intrinsic::x86_sse2_comigt_sd: 9385 Opc = X86ISD::COMI; 9386 CC = ISD::SETGT; 9387 break; 9388 case Intrinsic::x86_sse_comige_ss: 9389 case Intrinsic::x86_sse2_comige_sd: 9390 Opc = X86ISD::COMI; 9391 CC = ISD::SETGE; 9392 break; 9393 case Intrinsic::x86_sse_comineq_ss: 9394 case Intrinsic::x86_sse2_comineq_sd: 9395 Opc = X86ISD::COMI; 9396 CC = ISD::SETNE; 9397 break; 9398 case Intrinsic::x86_sse_ucomieq_ss: 9399 case Intrinsic::x86_sse2_ucomieq_sd: 9400 Opc = X86ISD::UCOMI; 9401 CC = ISD::SETEQ; 9402 break; 9403 case Intrinsic::x86_sse_ucomilt_ss: 9404 case Intrinsic::x86_sse2_ucomilt_sd: 9405 Opc = X86ISD::UCOMI; 9406 CC = ISD::SETLT; 9407 break; 9408 case Intrinsic::x86_sse_ucomile_ss: 9409 case Intrinsic::x86_sse2_ucomile_sd: 9410 Opc = X86ISD::UCOMI; 9411 CC = ISD::SETLE; 9412 break; 9413 case Intrinsic::x86_sse_ucomigt_ss: 9414 case Intrinsic::x86_sse2_ucomigt_sd: 9415 Opc = X86ISD::UCOMI; 9416 CC = ISD::SETGT; 9417 break; 9418 case Intrinsic::x86_sse_ucomige_ss: 9419 case Intrinsic::x86_sse2_ucomige_sd: 9420 Opc = X86ISD::UCOMI; 9421 CC = ISD::SETGE; 9422 break; 9423 case Intrinsic::x86_sse_ucomineq_ss: 9424 case Intrinsic::x86_sse2_ucomineq_sd: 9425 Opc = X86ISD::UCOMI; 9426 CC = ISD::SETNE; 9427 break; 9428 } 9429 9430 SDValue LHS = Op.getOperand(1); 9431 SDValue RHS = Op.getOperand(2); 9432 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9433 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9434 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9435 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9436 DAG.getConstant(X86CC, MVT::i8), Cond); 9437 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9438 } 9439 // XOP comparison intrinsics 9440 case Intrinsic::x86_xop_vpcomltb: 9441 case Intrinsic::x86_xop_vpcomltw: 9442 case Intrinsic::x86_xop_vpcomltd: 9443 case Intrinsic::x86_xop_vpcomltq: 9444 case Intrinsic::x86_xop_vpcomltub: 9445 case Intrinsic::x86_xop_vpcomltuw: 9446 case Intrinsic::x86_xop_vpcomltud: 9447 case Intrinsic::x86_xop_vpcomltuq: 9448 case Intrinsic::x86_xop_vpcomleb: 9449 case Intrinsic::x86_xop_vpcomlew: 9450 case Intrinsic::x86_xop_vpcomled: 9451 case Intrinsic::x86_xop_vpcomleq: 9452 case Intrinsic::x86_xop_vpcomleub: 9453 case Intrinsic::x86_xop_vpcomleuw: 9454 case Intrinsic::x86_xop_vpcomleud: 9455 case Intrinsic::x86_xop_vpcomleuq: 9456 case Intrinsic::x86_xop_vpcomgtb: 9457 case Intrinsic::x86_xop_vpcomgtw: 9458 case Intrinsic::x86_xop_vpcomgtd: 9459 case Intrinsic::x86_xop_vpcomgtq: 9460 case Intrinsic::x86_xop_vpcomgtub: 9461 case Intrinsic::x86_xop_vpcomgtuw: 9462 case Intrinsic::x86_xop_vpcomgtud: 9463 case Intrinsic::x86_xop_vpcomgtuq: 9464 case Intrinsic::x86_xop_vpcomgeb: 9465 case Intrinsic::x86_xop_vpcomgew: 9466 case Intrinsic::x86_xop_vpcomged: 9467 case Intrinsic::x86_xop_vpcomgeq: 9468 case Intrinsic::x86_xop_vpcomgeub: 9469 case Intrinsic::x86_xop_vpcomgeuw: 9470 case Intrinsic::x86_xop_vpcomgeud: 9471 case Intrinsic::x86_xop_vpcomgeuq: 9472 case Intrinsic::x86_xop_vpcomeqb: 9473 case Intrinsic::x86_xop_vpcomeqw: 9474 case Intrinsic::x86_xop_vpcomeqd: 9475 case Intrinsic::x86_xop_vpcomeqq: 9476 case Intrinsic::x86_xop_vpcomequb: 9477 case Intrinsic::x86_xop_vpcomequw: 9478 case Intrinsic::x86_xop_vpcomequd: 9479 case Intrinsic::x86_xop_vpcomequq: 9480 case Intrinsic::x86_xop_vpcomneb: 9481 case Intrinsic::x86_xop_vpcomnew: 9482 case Intrinsic::x86_xop_vpcomned: 9483 case Intrinsic::x86_xop_vpcomneq: 9484 case Intrinsic::x86_xop_vpcomneub: 9485 case Intrinsic::x86_xop_vpcomneuw: 9486 case Intrinsic::x86_xop_vpcomneud: 9487 case Intrinsic::x86_xop_vpcomneuq: 9488 case Intrinsic::x86_xop_vpcomfalseb: 9489 case Intrinsic::x86_xop_vpcomfalsew: 9490 case Intrinsic::x86_xop_vpcomfalsed: 9491 case Intrinsic::x86_xop_vpcomfalseq: 9492 case Intrinsic::x86_xop_vpcomfalseub: 9493 case Intrinsic::x86_xop_vpcomfalseuw: 9494 case Intrinsic::x86_xop_vpcomfalseud: 9495 case Intrinsic::x86_xop_vpcomfalseuq: 9496 case Intrinsic::x86_xop_vpcomtrueb: 9497 case Intrinsic::x86_xop_vpcomtruew: 9498 case Intrinsic::x86_xop_vpcomtrued: 9499 case Intrinsic::x86_xop_vpcomtrueq: 9500 case Intrinsic::x86_xop_vpcomtrueub: 9501 case Intrinsic::x86_xop_vpcomtrueuw: 9502 case Intrinsic::x86_xop_vpcomtrueud: 9503 case Intrinsic::x86_xop_vpcomtrueuq: { 9504 unsigned CC = 0; 9505 unsigned Opc = 0; 9506 9507 switch (IntNo) { 9508 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9509 case Intrinsic::x86_xop_vpcomltb: 9510 case Intrinsic::x86_xop_vpcomltw: 9511 case Intrinsic::x86_xop_vpcomltd: 9512 case Intrinsic::x86_xop_vpcomltq: 9513 CC = 0; 9514 Opc = X86ISD::VPCOM; 9515 break; 9516 case Intrinsic::x86_xop_vpcomltub: 9517 case Intrinsic::x86_xop_vpcomltuw: 9518 case Intrinsic::x86_xop_vpcomltud: 9519 case Intrinsic::x86_xop_vpcomltuq: 9520 CC = 0; 9521 Opc = X86ISD::VPCOMU; 9522 break; 9523 case Intrinsic::x86_xop_vpcomleb: 9524 case Intrinsic::x86_xop_vpcomlew: 9525 case Intrinsic::x86_xop_vpcomled: 9526 case Intrinsic::x86_xop_vpcomleq: 9527 CC = 1; 9528 Opc = X86ISD::VPCOM; 9529 break; 9530 case Intrinsic::x86_xop_vpcomleub: 9531 case Intrinsic::x86_xop_vpcomleuw: 9532 case Intrinsic::x86_xop_vpcomleud: 9533 case Intrinsic::x86_xop_vpcomleuq: 9534 CC = 1; 9535 Opc = X86ISD::VPCOMU; 9536 break; 9537 case Intrinsic::x86_xop_vpcomgtb: 9538 case Intrinsic::x86_xop_vpcomgtw: 9539 case Intrinsic::x86_xop_vpcomgtd: 9540 case Intrinsic::x86_xop_vpcomgtq: 9541 CC = 2; 9542 Opc = X86ISD::VPCOM; 9543 break; 9544 case Intrinsic::x86_xop_vpcomgtub: 9545 case Intrinsic::x86_xop_vpcomgtuw: 9546 case Intrinsic::x86_xop_vpcomgtud: 9547 case Intrinsic::x86_xop_vpcomgtuq: 9548 CC = 2; 9549 Opc = X86ISD::VPCOMU; 9550 break; 9551 case Intrinsic::x86_xop_vpcomgeb: 9552 case Intrinsic::x86_xop_vpcomgew: 9553 case Intrinsic::x86_xop_vpcomged: 9554 case Intrinsic::x86_xop_vpcomgeq: 9555 CC = 3; 9556 Opc = X86ISD::VPCOM; 9557 break; 9558 case Intrinsic::x86_xop_vpcomgeub: 9559 case Intrinsic::x86_xop_vpcomgeuw: 9560 case Intrinsic::x86_xop_vpcomgeud: 9561 case Intrinsic::x86_xop_vpcomgeuq: 9562 CC = 3; 9563 Opc = X86ISD::VPCOMU; 9564 break; 9565 case Intrinsic::x86_xop_vpcomeqb: 9566 case Intrinsic::x86_xop_vpcomeqw: 9567 case Intrinsic::x86_xop_vpcomeqd: 9568 case Intrinsic::x86_xop_vpcomeqq: 9569 CC = 4; 9570 Opc = X86ISD::VPCOM; 9571 break; 9572 case Intrinsic::x86_xop_vpcomequb: 9573 case Intrinsic::x86_xop_vpcomequw: 9574 case Intrinsic::x86_xop_vpcomequd: 9575 case Intrinsic::x86_xop_vpcomequq: 9576 CC = 4; 9577 Opc = X86ISD::VPCOMU; 9578 break; 9579 case Intrinsic::x86_xop_vpcomneb: 9580 case Intrinsic::x86_xop_vpcomnew: 9581 case Intrinsic::x86_xop_vpcomned: 9582 case Intrinsic::x86_xop_vpcomneq: 9583 CC = 5; 9584 Opc = X86ISD::VPCOM; 9585 break; 9586 case Intrinsic::x86_xop_vpcomneub: 9587 case Intrinsic::x86_xop_vpcomneuw: 9588 case Intrinsic::x86_xop_vpcomneud: 9589 case Intrinsic::x86_xop_vpcomneuq: 9590 CC = 5; 9591 Opc = X86ISD::VPCOMU; 9592 break; 9593 case Intrinsic::x86_xop_vpcomfalseb: 9594 case Intrinsic::x86_xop_vpcomfalsew: 9595 case Intrinsic::x86_xop_vpcomfalsed: 9596 case Intrinsic::x86_xop_vpcomfalseq: 9597 CC = 6; 9598 Opc = X86ISD::VPCOM; 9599 break; 9600 case Intrinsic::x86_xop_vpcomfalseub: 9601 case Intrinsic::x86_xop_vpcomfalseuw: 9602 case Intrinsic::x86_xop_vpcomfalseud: 9603 case Intrinsic::x86_xop_vpcomfalseuq: 9604 CC = 6; 9605 Opc = X86ISD::VPCOMU; 9606 break; 9607 case Intrinsic::x86_xop_vpcomtrueb: 9608 case Intrinsic::x86_xop_vpcomtruew: 9609 case Intrinsic::x86_xop_vpcomtrued: 9610 case Intrinsic::x86_xop_vpcomtrueq: 9611 CC = 7; 9612 Opc = X86ISD::VPCOM; 9613 break; 9614 case Intrinsic::x86_xop_vpcomtrueub: 9615 case Intrinsic::x86_xop_vpcomtrueuw: 9616 case Intrinsic::x86_xop_vpcomtrueud: 9617 case Intrinsic::x86_xop_vpcomtrueuq: 9618 CC = 7; 9619 Opc = X86ISD::VPCOMU; 9620 break; 9621 } 9622 9623 SDValue LHS = Op.getOperand(1); 9624 SDValue RHS = Op.getOperand(2); 9625 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9626 DAG.getConstant(CC, MVT::i8)); 9627 } 9628 9629 // Arithmetic intrinsics. 9630 case Intrinsic::x86_sse2_pmulu_dq: 9631 case Intrinsic::x86_avx2_pmulu_dq: 9632 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9633 Op.getOperand(1), Op.getOperand(2)); 9634 case Intrinsic::x86_sse3_hadd_ps: 9635 case Intrinsic::x86_sse3_hadd_pd: 9636 case Intrinsic::x86_avx_hadd_ps_256: 9637 case Intrinsic::x86_avx_hadd_pd_256: 9638 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9639 Op.getOperand(1), Op.getOperand(2)); 9640 case Intrinsic::x86_sse3_hsub_ps: 9641 case Intrinsic::x86_sse3_hsub_pd: 9642 case Intrinsic::x86_avx_hsub_ps_256: 9643 case Intrinsic::x86_avx_hsub_pd_256: 9644 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9645 Op.getOperand(1), Op.getOperand(2)); 9646 case Intrinsic::x86_ssse3_phadd_w_128: 9647 case Intrinsic::x86_ssse3_phadd_d_128: 9648 case Intrinsic::x86_avx2_phadd_w: 9649 case Intrinsic::x86_avx2_phadd_d: 9650 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9651 Op.getOperand(1), Op.getOperand(2)); 9652 case Intrinsic::x86_ssse3_phsub_w_128: 9653 case Intrinsic::x86_ssse3_phsub_d_128: 9654 case Intrinsic::x86_avx2_phsub_w: 9655 case Intrinsic::x86_avx2_phsub_d: 9656 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9657 Op.getOperand(1), Op.getOperand(2)); 9658 case Intrinsic::x86_avx2_psllv_d: 9659 case Intrinsic::x86_avx2_psllv_q: 9660 case Intrinsic::x86_avx2_psllv_d_256: 9661 case Intrinsic::x86_avx2_psllv_q_256: 9662 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9663 Op.getOperand(1), Op.getOperand(2)); 9664 case Intrinsic::x86_avx2_psrlv_d: 9665 case Intrinsic::x86_avx2_psrlv_q: 9666 case Intrinsic::x86_avx2_psrlv_d_256: 9667 case Intrinsic::x86_avx2_psrlv_q_256: 9668 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9669 Op.getOperand(1), Op.getOperand(2)); 9670 case Intrinsic::x86_avx2_psrav_d: 9671 case Intrinsic::x86_avx2_psrav_d_256: 9672 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9673 Op.getOperand(1), Op.getOperand(2)); 9674 case Intrinsic::x86_ssse3_pshuf_b_128: 9675 case Intrinsic::x86_avx2_pshuf_b: 9676 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9677 Op.getOperand(1), Op.getOperand(2)); 9678 case Intrinsic::x86_ssse3_psign_b_128: 9679 case Intrinsic::x86_ssse3_psign_w_128: 9680 case Intrinsic::x86_ssse3_psign_d_128: 9681 case Intrinsic::x86_avx2_psign_b: 9682 case Intrinsic::x86_avx2_psign_w: 9683 case Intrinsic::x86_avx2_psign_d: 9684 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9685 Op.getOperand(1), Op.getOperand(2)); 9686 case Intrinsic::x86_sse41_insertps: 9687 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9688 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9689 case Intrinsic::x86_avx_vperm2f128_ps_256: 9690 case Intrinsic::x86_avx_vperm2f128_pd_256: 9691 case Intrinsic::x86_avx_vperm2f128_si_256: 9692 case Intrinsic::x86_avx2_vperm2i128: 9693 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9694 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9695 case Intrinsic::x86_avx2_permd: 9696 case Intrinsic::x86_avx2_permps: 9697 // Operands intentionally swapped. Mask is last operand to intrinsic, 9698 // but second operand for node/intruction. 9699 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9700 Op.getOperand(2), Op.getOperand(1)); 9701 9702 // ptest and testp intrinsics. The intrinsic these come from are designed to 9703 // return an integer value, not just an instruction so lower it to the ptest 9704 // or testp pattern and a setcc for the result. 9705 case Intrinsic::x86_sse41_ptestz: 9706 case Intrinsic::x86_sse41_ptestc: 9707 case Intrinsic::x86_sse41_ptestnzc: 9708 case Intrinsic::x86_avx_ptestz_256: 9709 case Intrinsic::x86_avx_ptestc_256: 9710 case Intrinsic::x86_avx_ptestnzc_256: 9711 case Intrinsic::x86_avx_vtestz_ps: 9712 case Intrinsic::x86_avx_vtestc_ps: 9713 case Intrinsic::x86_avx_vtestnzc_ps: 9714 case Intrinsic::x86_avx_vtestz_pd: 9715 case Intrinsic::x86_avx_vtestc_pd: 9716 case Intrinsic::x86_avx_vtestnzc_pd: 9717 case Intrinsic::x86_avx_vtestz_ps_256: 9718 case Intrinsic::x86_avx_vtestc_ps_256: 9719 case Intrinsic::x86_avx_vtestnzc_ps_256: 9720 case Intrinsic::x86_avx_vtestz_pd_256: 9721 case Intrinsic::x86_avx_vtestc_pd_256: 9722 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9723 bool IsTestPacked = false; 9724 unsigned X86CC = 0; 9725 switch (IntNo) { 9726 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9727 case Intrinsic::x86_avx_vtestz_ps: 9728 case Intrinsic::x86_avx_vtestz_pd: 9729 case Intrinsic::x86_avx_vtestz_ps_256: 9730 case Intrinsic::x86_avx_vtestz_pd_256: 9731 IsTestPacked = true; // Fallthrough 9732 case Intrinsic::x86_sse41_ptestz: 9733 case Intrinsic::x86_avx_ptestz_256: 9734 // ZF = 1 9735 X86CC = X86::COND_E; 9736 break; 9737 case Intrinsic::x86_avx_vtestc_ps: 9738 case Intrinsic::x86_avx_vtestc_pd: 9739 case Intrinsic::x86_avx_vtestc_ps_256: 9740 case Intrinsic::x86_avx_vtestc_pd_256: 9741 IsTestPacked = true; // Fallthrough 9742 case Intrinsic::x86_sse41_ptestc: 9743 case Intrinsic::x86_avx_ptestc_256: 9744 // CF = 1 9745 X86CC = X86::COND_B; 9746 break; 9747 case Intrinsic::x86_avx_vtestnzc_ps: 9748 case Intrinsic::x86_avx_vtestnzc_pd: 9749 case Intrinsic::x86_avx_vtestnzc_ps_256: 9750 case Intrinsic::x86_avx_vtestnzc_pd_256: 9751 IsTestPacked = true; // Fallthrough 9752 case Intrinsic::x86_sse41_ptestnzc: 9753 case Intrinsic::x86_avx_ptestnzc_256: 9754 // ZF and CF = 0 9755 X86CC = X86::COND_A; 9756 break; 9757 } 9758 9759 SDValue LHS = Op.getOperand(1); 9760 SDValue RHS = Op.getOperand(2); 9761 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9762 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9763 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9764 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9765 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9766 } 9767 9768 // SSE/AVX shift intrinsics 9769 case Intrinsic::x86_sse2_psll_w: 9770 case Intrinsic::x86_sse2_psll_d: 9771 case Intrinsic::x86_sse2_psll_q: 9772 case Intrinsic::x86_avx2_psll_w: 9773 case Intrinsic::x86_avx2_psll_d: 9774 case Intrinsic::x86_avx2_psll_q: 9775 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9776 Op.getOperand(1), Op.getOperand(2)); 9777 case Intrinsic::x86_sse2_psrl_w: 9778 case Intrinsic::x86_sse2_psrl_d: 9779 case Intrinsic::x86_sse2_psrl_q: 9780 case Intrinsic::x86_avx2_psrl_w: 9781 case Intrinsic::x86_avx2_psrl_d: 9782 case Intrinsic::x86_avx2_psrl_q: 9783 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9784 Op.getOperand(1), Op.getOperand(2)); 9785 case Intrinsic::x86_sse2_psra_w: 9786 case Intrinsic::x86_sse2_psra_d: 9787 case Intrinsic::x86_avx2_psra_w: 9788 case Intrinsic::x86_avx2_psra_d: 9789 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9790 Op.getOperand(1), Op.getOperand(2)); 9791 case Intrinsic::x86_sse2_pslli_w: 9792 case Intrinsic::x86_sse2_pslli_d: 9793 case Intrinsic::x86_sse2_pslli_q: 9794 case Intrinsic::x86_avx2_pslli_w: 9795 case Intrinsic::x86_avx2_pslli_d: 9796 case Intrinsic::x86_avx2_pslli_q: 9797 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9798 Op.getOperand(1), Op.getOperand(2), DAG); 9799 case Intrinsic::x86_sse2_psrli_w: 9800 case Intrinsic::x86_sse2_psrli_d: 9801 case Intrinsic::x86_sse2_psrli_q: 9802 case Intrinsic::x86_avx2_psrli_w: 9803 case Intrinsic::x86_avx2_psrli_d: 9804 case Intrinsic::x86_avx2_psrli_q: 9805 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9806 Op.getOperand(1), Op.getOperand(2), DAG); 9807 case Intrinsic::x86_sse2_psrai_w: 9808 case Intrinsic::x86_sse2_psrai_d: 9809 case Intrinsic::x86_avx2_psrai_w: 9810 case Intrinsic::x86_avx2_psrai_d: 9811 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9812 Op.getOperand(1), Op.getOperand(2), DAG); 9813 // Fix vector shift instructions where the last operand is a non-immediate 9814 // i32 value. 9815 case Intrinsic::x86_mmx_pslli_w: 9816 case Intrinsic::x86_mmx_pslli_d: 9817 case Intrinsic::x86_mmx_pslli_q: 9818 case Intrinsic::x86_mmx_psrli_w: 9819 case Intrinsic::x86_mmx_psrli_d: 9820 case Intrinsic::x86_mmx_psrli_q: 9821 case Intrinsic::x86_mmx_psrai_w: 9822 case Intrinsic::x86_mmx_psrai_d: { 9823 SDValue ShAmt = Op.getOperand(2); 9824 if (isa<ConstantSDNode>(ShAmt)) 9825 return SDValue(); 9826 9827 unsigned NewIntNo = 0; 9828 switch (IntNo) { 9829 case Intrinsic::x86_mmx_pslli_w: 9830 NewIntNo = Intrinsic::x86_mmx_psll_w; 9831 break; 9832 case Intrinsic::x86_mmx_pslli_d: 9833 NewIntNo = Intrinsic::x86_mmx_psll_d; 9834 break; 9835 case Intrinsic::x86_mmx_pslli_q: 9836 NewIntNo = Intrinsic::x86_mmx_psll_q; 9837 break; 9838 case Intrinsic::x86_mmx_psrli_w: 9839 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9840 break; 9841 case Intrinsic::x86_mmx_psrli_d: 9842 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9843 break; 9844 case Intrinsic::x86_mmx_psrli_q: 9845 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9846 break; 9847 case Intrinsic::x86_mmx_psrai_w: 9848 NewIntNo = Intrinsic::x86_mmx_psra_w; 9849 break; 9850 case Intrinsic::x86_mmx_psrai_d: 9851 NewIntNo = Intrinsic::x86_mmx_psra_d; 9852 break; 9853 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9854 } 9855 9856 // The vector shift intrinsics with scalars uses 32b shift amounts but 9857 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9858 // to be zero. 9859 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9860 DAG.getConstant(0, MVT::i32)); 9861// FIXME this must be lowered to get rid of the invalid type. 9862 9863 EVT VT = Op.getValueType(); 9864 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9865 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9866 DAG.getConstant(NewIntNo, MVT::i32), 9867 Op.getOperand(1), ShAmt); 9868 } 9869 } 9870} 9871 9872SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9873 SelectionDAG &DAG) const { 9874 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9875 MFI->setReturnAddressIsTaken(true); 9876 9877 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9878 DebugLoc dl = Op.getDebugLoc(); 9879 9880 if (Depth > 0) { 9881 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9882 SDValue Offset = 9883 DAG.getConstant(TD->getPointerSize(), 9884 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9885 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9886 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9887 FrameAddr, Offset), 9888 MachinePointerInfo(), false, false, false, 0); 9889 } 9890 9891 // Just load the return address. 9892 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9893 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9894 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9895} 9896 9897SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9898 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9899 MFI->setFrameAddressIsTaken(true); 9900 9901 EVT VT = Op.getValueType(); 9902 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9903 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9904 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9905 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9906 while (Depth--) 9907 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9908 MachinePointerInfo(), 9909 false, false, false, 0); 9910 return FrameAddr; 9911} 9912 9913SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9914 SelectionDAG &DAG) const { 9915 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9916} 9917 9918SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9919 MachineFunction &MF = DAG.getMachineFunction(); 9920 SDValue Chain = Op.getOperand(0); 9921 SDValue Offset = Op.getOperand(1); 9922 SDValue Handler = Op.getOperand(2); 9923 DebugLoc dl = Op.getDebugLoc(); 9924 9925 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9926 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9927 getPointerTy()); 9928 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9929 9930 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9931 DAG.getIntPtrConstant(TD->getPointerSize())); 9932 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9933 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9934 false, false, 0); 9935 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9936 MF.getRegInfo().addLiveOut(StoreAddrReg); 9937 9938 return DAG.getNode(X86ISD::EH_RETURN, dl, 9939 MVT::Other, 9940 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9941} 9942 9943SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9944 SelectionDAG &DAG) const { 9945 return Op.getOperand(0); 9946} 9947 9948SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9949 SelectionDAG &DAG) const { 9950 SDValue Root = Op.getOperand(0); 9951 SDValue Trmp = Op.getOperand(1); // trampoline 9952 SDValue FPtr = Op.getOperand(2); // nested function 9953 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9954 DebugLoc dl = Op.getDebugLoc(); 9955 9956 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9957 9958 if (Subtarget->is64Bit()) { 9959 SDValue OutChains[6]; 9960 9961 // Large code-model. 9962 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9963 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9964 9965 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9966 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9967 9968 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9969 9970 // Load the pointer to the nested function into R11. 9971 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9972 SDValue Addr = Trmp; 9973 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9974 Addr, MachinePointerInfo(TrmpAddr), 9975 false, false, 0); 9976 9977 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9978 DAG.getConstant(2, MVT::i64)); 9979 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9980 MachinePointerInfo(TrmpAddr, 2), 9981 false, false, 2); 9982 9983 // Load the 'nest' parameter value into R10. 9984 // R10 is specified in X86CallingConv.td 9985 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9987 DAG.getConstant(10, MVT::i64)); 9988 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9989 Addr, MachinePointerInfo(TrmpAddr, 10), 9990 false, false, 0); 9991 9992 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9993 DAG.getConstant(12, MVT::i64)); 9994 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9995 MachinePointerInfo(TrmpAddr, 12), 9996 false, false, 2); 9997 9998 // Jump to the nested function. 9999 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 10000 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10001 DAG.getConstant(20, MVT::i64)); 10002 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10003 Addr, MachinePointerInfo(TrmpAddr, 20), 10004 false, false, 0); 10005 10006 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 10007 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10008 DAG.getConstant(22, MVT::i64)); 10009 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 10010 MachinePointerInfo(TrmpAddr, 22), 10011 false, false, 0); 10012 10013 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 10014 } else { 10015 const Function *Func = 10016 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 10017 CallingConv::ID CC = Func->getCallingConv(); 10018 unsigned NestReg; 10019 10020 switch (CC) { 10021 default: 10022 llvm_unreachable("Unsupported calling convention"); 10023 case CallingConv::C: 10024 case CallingConv::X86_StdCall: { 10025 // Pass 'nest' parameter in ECX. 10026 // Must be kept in sync with X86CallingConv.td 10027 NestReg = X86::ECX; 10028 10029 // Check that ECX wasn't needed by an 'inreg' parameter. 10030 FunctionType *FTy = Func->getFunctionType(); 10031 const AttrListPtr &Attrs = Func->getAttributes(); 10032 10033 if (!Attrs.isEmpty() && !Func->isVarArg()) { 10034 unsigned InRegCount = 0; 10035 unsigned Idx = 1; 10036 10037 for (FunctionType::param_iterator I = FTy->param_begin(), 10038 E = FTy->param_end(); I != E; ++I, ++Idx) 10039 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 10040 // FIXME: should only count parameters that are lowered to integers. 10041 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 10042 10043 if (InRegCount > 2) { 10044 report_fatal_error("Nest register in use - reduce number of inreg" 10045 " parameters!"); 10046 } 10047 } 10048 break; 10049 } 10050 case CallingConv::X86_FastCall: 10051 case CallingConv::X86_ThisCall: 10052 case CallingConv::Fast: 10053 // Pass 'nest' parameter in EAX. 10054 // Must be kept in sync with X86CallingConv.td 10055 NestReg = X86::EAX; 10056 break; 10057 } 10058 10059 SDValue OutChains[4]; 10060 SDValue Addr, Disp; 10061 10062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10063 DAG.getConstant(10, MVT::i32)); 10064 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 10065 10066 // This is storing the opcode for MOV32ri. 10067 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 10068 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 10069 OutChains[0] = DAG.getStore(Root, dl, 10070 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 10071 Trmp, MachinePointerInfo(TrmpAddr), 10072 false, false, 0); 10073 10074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10075 DAG.getConstant(1, MVT::i32)); 10076 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10077 MachinePointerInfo(TrmpAddr, 1), 10078 false, false, 1); 10079 10080 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10082 DAG.getConstant(5, MVT::i32)); 10083 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10084 MachinePointerInfo(TrmpAddr, 5), 10085 false, false, 1); 10086 10087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10088 DAG.getConstant(6, MVT::i32)); 10089 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10090 MachinePointerInfo(TrmpAddr, 6), 10091 false, false, 1); 10092 10093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10094 } 10095} 10096 10097SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10098 SelectionDAG &DAG) const { 10099 /* 10100 The rounding mode is in bits 11:10 of FPSR, and has the following 10101 settings: 10102 00 Round to nearest 10103 01 Round to -inf 10104 10 Round to +inf 10105 11 Round to 0 10106 10107 FLT_ROUNDS, on the other hand, expects the following: 10108 -1 Undefined 10109 0 Round to 0 10110 1 Round to nearest 10111 2 Round to +inf 10112 3 Round to -inf 10113 10114 To perform the conversion, we do: 10115 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10116 */ 10117 10118 MachineFunction &MF = DAG.getMachineFunction(); 10119 const TargetMachine &TM = MF.getTarget(); 10120 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10121 unsigned StackAlignment = TFI.getStackAlignment(); 10122 EVT VT = Op.getValueType(); 10123 DebugLoc DL = Op.getDebugLoc(); 10124 10125 // Save FP Control Word to stack slot 10126 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10127 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10128 10129 10130 MachineMemOperand *MMO = 10131 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10132 MachineMemOperand::MOStore, 2, 2); 10133 10134 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10135 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10136 DAG.getVTList(MVT::Other), 10137 Ops, 2, MVT::i16, MMO); 10138 10139 // Load FP Control Word from stack slot 10140 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10141 MachinePointerInfo(), false, false, false, 0); 10142 10143 // Transform as necessary 10144 SDValue CWD1 = 10145 DAG.getNode(ISD::SRL, DL, MVT::i16, 10146 DAG.getNode(ISD::AND, DL, MVT::i16, 10147 CWD, DAG.getConstant(0x800, MVT::i16)), 10148 DAG.getConstant(11, MVT::i8)); 10149 SDValue CWD2 = 10150 DAG.getNode(ISD::SRL, DL, MVT::i16, 10151 DAG.getNode(ISD::AND, DL, MVT::i16, 10152 CWD, DAG.getConstant(0x400, MVT::i16)), 10153 DAG.getConstant(9, MVT::i8)); 10154 10155 SDValue RetVal = 10156 DAG.getNode(ISD::AND, DL, MVT::i16, 10157 DAG.getNode(ISD::ADD, DL, MVT::i16, 10158 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10159 DAG.getConstant(1, MVT::i16)), 10160 DAG.getConstant(3, MVT::i16)); 10161 10162 10163 return DAG.getNode((VT.getSizeInBits() < 16 ? 10164 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10165} 10166 10167SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10168 EVT VT = Op.getValueType(); 10169 EVT OpVT = VT; 10170 unsigned NumBits = VT.getSizeInBits(); 10171 DebugLoc dl = Op.getDebugLoc(); 10172 10173 Op = Op.getOperand(0); 10174 if (VT == MVT::i8) { 10175 // Zero extend to i32 since there is not an i8 bsr. 10176 OpVT = MVT::i32; 10177 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10178 } 10179 10180 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10181 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10182 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10183 10184 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10185 SDValue Ops[] = { 10186 Op, 10187 DAG.getConstant(NumBits+NumBits-1, OpVT), 10188 DAG.getConstant(X86::COND_E, MVT::i8), 10189 Op.getValue(1) 10190 }; 10191 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10192 10193 // Finally xor with NumBits-1. 10194 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10195 10196 if (VT == MVT::i8) 10197 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10198 return Op; 10199} 10200 10201SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10202 SelectionDAG &DAG) const { 10203 EVT VT = Op.getValueType(); 10204 EVT OpVT = VT; 10205 unsigned NumBits = VT.getSizeInBits(); 10206 DebugLoc dl = Op.getDebugLoc(); 10207 10208 Op = Op.getOperand(0); 10209 if (VT == MVT::i8) { 10210 // Zero extend to i32 since there is not an i8 bsr. 10211 OpVT = MVT::i32; 10212 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10213 } 10214 10215 // Issue a bsr (scan bits in reverse). 10216 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10217 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10218 10219 // And xor with NumBits-1. 10220 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10221 10222 if (VT == MVT::i8) 10223 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10224 return Op; 10225} 10226 10227SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10228 EVT VT = Op.getValueType(); 10229 unsigned NumBits = VT.getSizeInBits(); 10230 DebugLoc dl = Op.getDebugLoc(); 10231 Op = Op.getOperand(0); 10232 10233 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10234 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10235 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10236 10237 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10238 SDValue Ops[] = { 10239 Op, 10240 DAG.getConstant(NumBits, VT), 10241 DAG.getConstant(X86::COND_E, MVT::i8), 10242 Op.getValue(1) 10243 }; 10244 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10245} 10246 10247// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10248// ones, and then concatenate the result back. 10249static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10250 EVT VT = Op.getValueType(); 10251 10252 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10253 "Unsupported value type for operation"); 10254 10255 unsigned NumElems = VT.getVectorNumElements(); 10256 DebugLoc dl = Op.getDebugLoc(); 10257 10258 // Extract the LHS vectors 10259 SDValue LHS = Op.getOperand(0); 10260 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10261 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10262 10263 // Extract the RHS vectors 10264 SDValue RHS = Op.getOperand(1); 10265 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 10266 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 10267 10268 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10269 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10270 10271 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10272 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10273 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10274} 10275 10276SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10277 assert(Op.getValueType().getSizeInBits() == 256 && 10278 Op.getValueType().isInteger() && 10279 "Only handle AVX 256-bit vector integer operation"); 10280 return Lower256IntArith(Op, DAG); 10281} 10282 10283SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10284 assert(Op.getValueType().getSizeInBits() == 256 && 10285 Op.getValueType().isInteger() && 10286 "Only handle AVX 256-bit vector integer operation"); 10287 return Lower256IntArith(Op, DAG); 10288} 10289 10290SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10291 EVT VT = Op.getValueType(); 10292 10293 // Decompose 256-bit ops into smaller 128-bit ops. 10294 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10295 return Lower256IntArith(Op, DAG); 10296 10297 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10298 "Only know how to lower V2I64/V4I64 multiply"); 10299 10300 DebugLoc dl = Op.getDebugLoc(); 10301 10302 // Ahi = psrlqi(a, 32); 10303 // Bhi = psrlqi(b, 32); 10304 // 10305 // AloBlo = pmuludq(a, b); 10306 // AloBhi = pmuludq(a, Bhi); 10307 // AhiBlo = pmuludq(Ahi, b); 10308 10309 // AloBhi = psllqi(AloBhi, 32); 10310 // AhiBlo = psllqi(AhiBlo, 32); 10311 // return AloBlo + AloBhi + AhiBlo; 10312 10313 SDValue A = Op.getOperand(0); 10314 SDValue B = Op.getOperand(1); 10315 10316 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10317 10318 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10319 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10320 10321 // Bit cast to 32-bit vectors for MULUDQ 10322 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10323 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10324 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10325 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10326 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10327 10328 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10329 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10330 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10331 10332 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10333 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10334 10335 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10336 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10337} 10338 10339SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10340 10341 EVT VT = Op.getValueType(); 10342 DebugLoc dl = Op.getDebugLoc(); 10343 SDValue R = Op.getOperand(0); 10344 SDValue Amt = Op.getOperand(1); 10345 LLVMContext *Context = DAG.getContext(); 10346 10347 if (!Subtarget->hasSSE2()) 10348 return SDValue(); 10349 10350 // Optimize shl/srl/sra with constant shift amount. 10351 if (isSplatVector(Amt.getNode())) { 10352 SDValue SclrAmt = Amt->getOperand(0); 10353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10354 uint64_t ShiftAmt = C->getZExtValue(); 10355 10356 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10357 (Subtarget->hasAVX2() && 10358 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10359 if (Op.getOpcode() == ISD::SHL) 10360 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10361 DAG.getConstant(ShiftAmt, MVT::i32)); 10362 if (Op.getOpcode() == ISD::SRL) 10363 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10364 DAG.getConstant(ShiftAmt, MVT::i32)); 10365 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10366 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10367 DAG.getConstant(ShiftAmt, MVT::i32)); 10368 } 10369 10370 if (VT == MVT::v16i8) { 10371 if (Op.getOpcode() == ISD::SHL) { 10372 // Make a large shift. 10373 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10374 DAG.getConstant(ShiftAmt, MVT::i32)); 10375 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10376 // Zero out the rightmost bits. 10377 SmallVector<SDValue, 16> V(16, 10378 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10379 MVT::i8)); 10380 return DAG.getNode(ISD::AND, dl, VT, SHL, 10381 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10382 } 10383 if (Op.getOpcode() == ISD::SRL) { 10384 // Make a large shift. 10385 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10386 DAG.getConstant(ShiftAmt, MVT::i32)); 10387 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10388 // Zero out the leftmost bits. 10389 SmallVector<SDValue, 16> V(16, 10390 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10391 MVT::i8)); 10392 return DAG.getNode(ISD::AND, dl, VT, SRL, 10393 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10394 } 10395 if (Op.getOpcode() == ISD::SRA) { 10396 if (ShiftAmt == 7) { 10397 // R s>> 7 === R s< 0 10398 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10399 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10400 } 10401 10402 // R s>> a === ((R u>> a) ^ m) - m 10403 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10404 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10405 MVT::i8)); 10406 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10407 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10408 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10409 return Res; 10410 } 10411 llvm_unreachable("Unknown shift opcode."); 10412 } 10413 10414 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10415 if (Op.getOpcode() == ISD::SHL) { 10416 // Make a large shift. 10417 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10418 DAG.getConstant(ShiftAmt, MVT::i32)); 10419 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10420 // Zero out the rightmost bits. 10421 SmallVector<SDValue, 32> V(32, 10422 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10423 MVT::i8)); 10424 return DAG.getNode(ISD::AND, dl, VT, SHL, 10425 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10426 } 10427 if (Op.getOpcode() == ISD::SRL) { 10428 // Make a large shift. 10429 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10430 DAG.getConstant(ShiftAmt, MVT::i32)); 10431 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10432 // Zero out the leftmost bits. 10433 SmallVector<SDValue, 32> V(32, 10434 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10435 MVT::i8)); 10436 return DAG.getNode(ISD::AND, dl, VT, SRL, 10437 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10438 } 10439 if (Op.getOpcode() == ISD::SRA) { 10440 if (ShiftAmt == 7) { 10441 // R s>> 7 === R s< 0 10442 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10443 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10444 } 10445 10446 // R s>> a === ((R u>> a) ^ m) - m 10447 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10448 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10449 MVT::i8)); 10450 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10451 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10452 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10453 return Res; 10454 } 10455 llvm_unreachable("Unknown shift opcode."); 10456 } 10457 } 10458 } 10459 10460 // Lower SHL with variable shift amount. 10461 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10462 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10463 DAG.getConstant(23, MVT::i32)); 10464 10465 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10466 Constant *C = ConstantDataVector::get(*Context, CV); 10467 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10468 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10469 MachinePointerInfo::getConstantPool(), 10470 false, false, false, 16); 10471 10472 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10473 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10474 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10475 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10476 } 10477 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10478 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10479 10480 // a = a << 5; 10481 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10482 DAG.getConstant(5, MVT::i32)); 10483 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10484 10485 // Turn 'a' into a mask suitable for VSELECT 10486 SDValue VSelM = DAG.getConstant(0x80, VT); 10487 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10488 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10489 10490 SDValue CM1 = DAG.getConstant(0x0f, VT); 10491 SDValue CM2 = DAG.getConstant(0x3f, VT); 10492 10493 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10494 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10495 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10496 DAG.getConstant(4, MVT::i32), DAG); 10497 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10498 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10499 10500 // a += a 10501 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10502 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10503 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10504 10505 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10506 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10507 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10508 DAG.getConstant(2, MVT::i32), DAG); 10509 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10510 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10511 10512 // a += a 10513 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10514 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10515 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10516 10517 // return VSELECT(r, r+r, a); 10518 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10519 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10520 return R; 10521 } 10522 10523 // Decompose 256-bit shifts into smaller 128-bit shifts. 10524 if (VT.getSizeInBits() == 256) { 10525 unsigned NumElems = VT.getVectorNumElements(); 10526 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10527 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10528 10529 // Extract the two vectors 10530 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 10531 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 10532 10533 // Recreate the shift amount vectors 10534 SDValue Amt1, Amt2; 10535 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10536 // Constant shift amount 10537 SmallVector<SDValue, 4> Amt1Csts; 10538 SmallVector<SDValue, 4> Amt2Csts; 10539 for (unsigned i = 0; i != NumElems/2; ++i) 10540 Amt1Csts.push_back(Amt->getOperand(i)); 10541 for (unsigned i = NumElems/2; i != NumElems; ++i) 10542 Amt2Csts.push_back(Amt->getOperand(i)); 10543 10544 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10545 &Amt1Csts[0], NumElems/2); 10546 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10547 &Amt2Csts[0], NumElems/2); 10548 } else { 10549 // Variable shift amount 10550 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 10551 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 10552 } 10553 10554 // Issue new vector shifts for the smaller types 10555 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10556 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10557 10558 // Concatenate the result back 10559 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10560 } 10561 10562 return SDValue(); 10563} 10564 10565SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10566 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10567 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10568 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10569 // has only one use. 10570 SDNode *N = Op.getNode(); 10571 SDValue LHS = N->getOperand(0); 10572 SDValue RHS = N->getOperand(1); 10573 unsigned BaseOp = 0; 10574 unsigned Cond = 0; 10575 DebugLoc DL = Op.getDebugLoc(); 10576 switch (Op.getOpcode()) { 10577 default: llvm_unreachable("Unknown ovf instruction!"); 10578 case ISD::SADDO: 10579 // A subtract of one will be selected as a INC. Note that INC doesn't 10580 // set CF, so we can't do this for UADDO. 10581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10582 if (C->isOne()) { 10583 BaseOp = X86ISD::INC; 10584 Cond = X86::COND_O; 10585 break; 10586 } 10587 BaseOp = X86ISD::ADD; 10588 Cond = X86::COND_O; 10589 break; 10590 case ISD::UADDO: 10591 BaseOp = X86ISD::ADD; 10592 Cond = X86::COND_B; 10593 break; 10594 case ISD::SSUBO: 10595 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10596 // set CF, so we can't do this for USUBO. 10597 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10598 if (C->isOne()) { 10599 BaseOp = X86ISD::DEC; 10600 Cond = X86::COND_O; 10601 break; 10602 } 10603 BaseOp = X86ISD::SUB; 10604 Cond = X86::COND_O; 10605 break; 10606 case ISD::USUBO: 10607 BaseOp = X86ISD::SUB; 10608 Cond = X86::COND_B; 10609 break; 10610 case ISD::SMULO: 10611 BaseOp = X86ISD::SMUL; 10612 Cond = X86::COND_O; 10613 break; 10614 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10615 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10616 MVT::i32); 10617 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10618 10619 SDValue SetCC = 10620 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10621 DAG.getConstant(X86::COND_O, MVT::i32), 10622 SDValue(Sum.getNode(), 2)); 10623 10624 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10625 } 10626 } 10627 10628 // Also sets EFLAGS. 10629 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10630 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10631 10632 SDValue SetCC = 10633 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10634 DAG.getConstant(Cond, MVT::i32), 10635 SDValue(Sum.getNode(), 1)); 10636 10637 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10638} 10639 10640SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10641 SelectionDAG &DAG) const { 10642 DebugLoc dl = Op.getDebugLoc(); 10643 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10644 EVT VT = Op.getValueType(); 10645 10646 if (!Subtarget->hasSSE2() || !VT.isVector()) 10647 return SDValue(); 10648 10649 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10650 ExtraVT.getScalarType().getSizeInBits(); 10651 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10652 10653 switch (VT.getSimpleVT().SimpleTy) { 10654 default: return SDValue(); 10655 case MVT::v8i32: 10656 case MVT::v16i16: 10657 if (!Subtarget->hasAVX()) 10658 return SDValue(); 10659 if (!Subtarget->hasAVX2()) { 10660 // needs to be split 10661 unsigned NumElems = VT.getVectorNumElements(); 10662 10663 // Extract the LHS vectors 10664 SDValue LHS = Op.getOperand(0); 10665 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10666 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10667 10668 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10669 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10670 10671 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10672 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10673 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10674 ExtraNumElems/2); 10675 SDValue Extra = DAG.getValueType(ExtraVT); 10676 10677 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10678 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10679 10680 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10681 } 10682 // fall through 10683 case MVT::v4i32: 10684 case MVT::v8i16: { 10685 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10686 Op.getOperand(0), ShAmt, DAG); 10687 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10688 } 10689 } 10690} 10691 10692 10693SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10694 DebugLoc dl = Op.getDebugLoc(); 10695 10696 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10697 // There isn't any reason to disable it if the target processor supports it. 10698 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10699 SDValue Chain = Op.getOperand(0); 10700 SDValue Zero = DAG.getConstant(0, MVT::i32); 10701 SDValue Ops[] = { 10702 DAG.getRegister(X86::ESP, MVT::i32), // Base 10703 DAG.getTargetConstant(1, MVT::i8), // Scale 10704 DAG.getRegister(0, MVT::i32), // Index 10705 DAG.getTargetConstant(0, MVT::i32), // Disp 10706 DAG.getRegister(0, MVT::i32), // Segment. 10707 Zero, 10708 Chain 10709 }; 10710 SDNode *Res = 10711 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10712 array_lengthof(Ops)); 10713 return SDValue(Res, 0); 10714 } 10715 10716 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10717 if (!isDev) 10718 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10719 10720 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10721 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10722 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10723 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10724 10725 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10726 if (!Op1 && !Op2 && !Op3 && Op4) 10727 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10728 10729 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10730 if (Op1 && !Op2 && !Op3 && !Op4) 10731 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10732 10733 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10734 // (MFENCE)>; 10735 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10736} 10737 10738SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10739 SelectionDAG &DAG) const { 10740 DebugLoc dl = Op.getDebugLoc(); 10741 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10742 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10743 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10744 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10745 10746 // The only fence that needs an instruction is a sequentially-consistent 10747 // cross-thread fence. 10748 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10749 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10750 // no-sse2). There isn't any reason to disable it if the target processor 10751 // supports it. 10752 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10753 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10754 10755 SDValue Chain = Op.getOperand(0); 10756 SDValue Zero = DAG.getConstant(0, MVT::i32); 10757 SDValue Ops[] = { 10758 DAG.getRegister(X86::ESP, MVT::i32), // Base 10759 DAG.getTargetConstant(1, MVT::i8), // Scale 10760 DAG.getRegister(0, MVT::i32), // Index 10761 DAG.getTargetConstant(0, MVT::i32), // Disp 10762 DAG.getRegister(0, MVT::i32), // Segment. 10763 Zero, 10764 Chain 10765 }; 10766 SDNode *Res = 10767 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10768 array_lengthof(Ops)); 10769 return SDValue(Res, 0); 10770 } 10771 10772 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10773 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10774} 10775 10776 10777SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10778 EVT T = Op.getValueType(); 10779 DebugLoc DL = Op.getDebugLoc(); 10780 unsigned Reg = 0; 10781 unsigned size = 0; 10782 switch(T.getSimpleVT().SimpleTy) { 10783 default: llvm_unreachable("Invalid value type!"); 10784 case MVT::i8: Reg = X86::AL; size = 1; break; 10785 case MVT::i16: Reg = X86::AX; size = 2; break; 10786 case MVT::i32: Reg = X86::EAX; size = 4; break; 10787 case MVT::i64: 10788 assert(Subtarget->is64Bit() && "Node not type legal!"); 10789 Reg = X86::RAX; size = 8; 10790 break; 10791 } 10792 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10793 Op.getOperand(2), SDValue()); 10794 SDValue Ops[] = { cpIn.getValue(0), 10795 Op.getOperand(1), 10796 Op.getOperand(3), 10797 DAG.getTargetConstant(size, MVT::i8), 10798 cpIn.getValue(1) }; 10799 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10800 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10801 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10802 Ops, 5, T, MMO); 10803 SDValue cpOut = 10804 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10805 return cpOut; 10806} 10807 10808SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10809 SelectionDAG &DAG) const { 10810 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10811 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10812 SDValue TheChain = Op.getOperand(0); 10813 DebugLoc dl = Op.getDebugLoc(); 10814 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10815 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10816 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10817 rax.getValue(2)); 10818 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10819 DAG.getConstant(32, MVT::i8)); 10820 SDValue Ops[] = { 10821 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10822 rdx.getValue(1) 10823 }; 10824 return DAG.getMergeValues(Ops, 2, dl); 10825} 10826 10827SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10828 SelectionDAG &DAG) const { 10829 EVT SrcVT = Op.getOperand(0).getValueType(); 10830 EVT DstVT = Op.getValueType(); 10831 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10832 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10833 assert((DstVT == MVT::i64 || 10834 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10835 "Unexpected custom BITCAST"); 10836 // i64 <=> MMX conversions are Legal. 10837 if (SrcVT==MVT::i64 && DstVT.isVector()) 10838 return Op; 10839 if (DstVT==MVT::i64 && SrcVT.isVector()) 10840 return Op; 10841 // MMX <=> MMX conversions are Legal. 10842 if (SrcVT.isVector() && DstVT.isVector()) 10843 return Op; 10844 // All other conversions need to be expanded. 10845 return SDValue(); 10846} 10847 10848SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10849 SDNode *Node = Op.getNode(); 10850 DebugLoc dl = Node->getDebugLoc(); 10851 EVT T = Node->getValueType(0); 10852 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10853 DAG.getConstant(0, T), Node->getOperand(2)); 10854 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10855 cast<AtomicSDNode>(Node)->getMemoryVT(), 10856 Node->getOperand(0), 10857 Node->getOperand(1), negOp, 10858 cast<AtomicSDNode>(Node)->getSrcValue(), 10859 cast<AtomicSDNode>(Node)->getAlignment(), 10860 cast<AtomicSDNode>(Node)->getOrdering(), 10861 cast<AtomicSDNode>(Node)->getSynchScope()); 10862} 10863 10864static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10865 SDNode *Node = Op.getNode(); 10866 DebugLoc dl = Node->getDebugLoc(); 10867 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10868 10869 // Convert seq_cst store -> xchg 10870 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10871 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10872 // (The only way to get a 16-byte store is cmpxchg16b) 10873 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10874 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10875 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10876 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10877 cast<AtomicSDNode>(Node)->getMemoryVT(), 10878 Node->getOperand(0), 10879 Node->getOperand(1), Node->getOperand(2), 10880 cast<AtomicSDNode>(Node)->getMemOperand(), 10881 cast<AtomicSDNode>(Node)->getOrdering(), 10882 cast<AtomicSDNode>(Node)->getSynchScope()); 10883 return Swap.getValue(1); 10884 } 10885 // Other atomic stores have a simple pattern. 10886 return Op; 10887} 10888 10889static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10890 EVT VT = Op.getNode()->getValueType(0); 10891 10892 // Let legalize expand this if it isn't a legal type yet. 10893 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10894 return SDValue(); 10895 10896 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10897 10898 unsigned Opc; 10899 bool ExtraOp = false; 10900 switch (Op.getOpcode()) { 10901 default: llvm_unreachable("Invalid code"); 10902 case ISD::ADDC: Opc = X86ISD::ADD; break; 10903 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10904 case ISD::SUBC: Opc = X86ISD::SUB; break; 10905 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10906 } 10907 10908 if (!ExtraOp) 10909 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10910 Op.getOperand(1)); 10911 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10912 Op.getOperand(1), Op.getOperand(2)); 10913} 10914 10915/// LowerOperation - Provide custom lowering hooks for some operations. 10916/// 10917SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10918 switch (Op.getOpcode()) { 10919 default: llvm_unreachable("Should not custom lower this!"); 10920 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10921 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10922 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10923 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10924 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10925 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10926 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10927 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10928 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10929 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10930 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10931 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10932 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10933 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10934 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10935 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10936 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10937 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10938 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10939 case ISD::SHL_PARTS: 10940 case ISD::SRA_PARTS: 10941 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10942 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10943 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10944 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10945 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10946 case ISD::FABS: return LowerFABS(Op, DAG); 10947 case ISD::FNEG: return LowerFNEG(Op, DAG); 10948 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10949 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10950 case ISD::SETCC: return LowerSETCC(Op, DAG); 10951 case ISD::SELECT: return LowerSELECT(Op, DAG); 10952 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10953 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10954 case ISD::VASTART: return LowerVASTART(Op, DAG); 10955 case ISD::VAARG: return LowerVAARG(Op, DAG); 10956 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10957 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10958 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10959 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10960 case ISD::FRAME_TO_ARGS_OFFSET: 10961 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10962 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10963 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10964 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10965 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10966 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10967 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10968 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10969 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10970 case ISD::MUL: return LowerMUL(Op, DAG); 10971 case ISD::SRA: 10972 case ISD::SRL: 10973 case ISD::SHL: return LowerShift(Op, DAG); 10974 case ISD::SADDO: 10975 case ISD::UADDO: 10976 case ISD::SSUBO: 10977 case ISD::USUBO: 10978 case ISD::SMULO: 10979 case ISD::UMULO: return LowerXALUO(Op, DAG); 10980 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10981 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10982 case ISD::ADDC: 10983 case ISD::ADDE: 10984 case ISD::SUBC: 10985 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10986 case ISD::ADD: return LowerADD(Op, DAG); 10987 case ISD::SUB: return LowerSUB(Op, DAG); 10988 } 10989} 10990 10991static void ReplaceATOMIC_LOAD(SDNode *Node, 10992 SmallVectorImpl<SDValue> &Results, 10993 SelectionDAG &DAG) { 10994 DebugLoc dl = Node->getDebugLoc(); 10995 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10996 10997 // Convert wide load -> cmpxchg8b/cmpxchg16b 10998 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10999 // (The only way to get a 16-byte load is cmpxchg16b) 11000 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 11001 SDValue Zero = DAG.getConstant(0, VT); 11002 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 11003 Node->getOperand(0), 11004 Node->getOperand(1), Zero, Zero, 11005 cast<AtomicSDNode>(Node)->getMemOperand(), 11006 cast<AtomicSDNode>(Node)->getOrdering(), 11007 cast<AtomicSDNode>(Node)->getSynchScope()); 11008 Results.push_back(Swap.getValue(0)); 11009 Results.push_back(Swap.getValue(1)); 11010} 11011 11012void X86TargetLowering:: 11013ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 11014 SelectionDAG &DAG, unsigned NewOp) const { 11015 DebugLoc dl = Node->getDebugLoc(); 11016 assert (Node->getValueType(0) == MVT::i64 && 11017 "Only know how to expand i64 atomics"); 11018 11019 SDValue Chain = Node->getOperand(0); 11020 SDValue In1 = Node->getOperand(1); 11021 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11022 Node->getOperand(2), DAG.getIntPtrConstant(0)); 11023 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11024 Node->getOperand(2), DAG.getIntPtrConstant(1)); 11025 SDValue Ops[] = { Chain, In1, In2L, In2H }; 11026 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 11027 SDValue Result = 11028 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 11029 cast<MemSDNode>(Node)->getMemOperand()); 11030 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 11031 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 11032 Results.push_back(Result.getValue(2)); 11033} 11034 11035/// ReplaceNodeResults - Replace a node with an illegal result type 11036/// with a new node built out of custom code. 11037void X86TargetLowering::ReplaceNodeResults(SDNode *N, 11038 SmallVectorImpl<SDValue>&Results, 11039 SelectionDAG &DAG) const { 11040 DebugLoc dl = N->getDebugLoc(); 11041 switch (N->getOpcode()) { 11042 default: 11043 llvm_unreachable("Do not know how to custom type legalize this operation!"); 11044 case ISD::SIGN_EXTEND_INREG: 11045 case ISD::ADDC: 11046 case ISD::ADDE: 11047 case ISD::SUBC: 11048 case ISD::SUBE: 11049 // We don't want to expand or promote these. 11050 return; 11051 case ISD::FP_TO_SINT: 11052 case ISD::FP_TO_UINT: { 11053 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 11054 11055 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 11056 return; 11057 11058 std::pair<SDValue,SDValue> Vals = 11059 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 11060 SDValue FIST = Vals.first, StackSlot = Vals.second; 11061 if (FIST.getNode() != 0) { 11062 EVT VT = N->getValueType(0); 11063 // Return a load from the stack slot. 11064 if (StackSlot.getNode() != 0) 11065 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 11066 MachinePointerInfo(), 11067 false, false, false, 0)); 11068 else 11069 Results.push_back(FIST); 11070 } 11071 return; 11072 } 11073 case ISD::READCYCLECOUNTER: { 11074 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11075 SDValue TheChain = N->getOperand(0); 11076 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11077 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11078 rd.getValue(1)); 11079 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11080 eax.getValue(2)); 11081 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11082 SDValue Ops[] = { eax, edx }; 11083 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11084 Results.push_back(edx.getValue(1)); 11085 return; 11086 } 11087 case ISD::ATOMIC_CMP_SWAP: { 11088 EVT T = N->getValueType(0); 11089 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11090 bool Regs64bit = T == MVT::i128; 11091 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11092 SDValue cpInL, cpInH; 11093 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11094 DAG.getConstant(0, HalfT)); 11095 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11096 DAG.getConstant(1, HalfT)); 11097 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11098 Regs64bit ? X86::RAX : X86::EAX, 11099 cpInL, SDValue()); 11100 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11101 Regs64bit ? X86::RDX : X86::EDX, 11102 cpInH, cpInL.getValue(1)); 11103 SDValue swapInL, swapInH; 11104 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11105 DAG.getConstant(0, HalfT)); 11106 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11107 DAG.getConstant(1, HalfT)); 11108 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11109 Regs64bit ? X86::RBX : X86::EBX, 11110 swapInL, cpInH.getValue(1)); 11111 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11112 Regs64bit ? X86::RCX : X86::ECX, 11113 swapInH, swapInL.getValue(1)); 11114 SDValue Ops[] = { swapInH.getValue(0), 11115 N->getOperand(1), 11116 swapInH.getValue(1) }; 11117 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11118 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11119 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11120 X86ISD::LCMPXCHG8_DAG; 11121 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11122 Ops, 3, T, MMO); 11123 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11124 Regs64bit ? X86::RAX : X86::EAX, 11125 HalfT, Result.getValue(1)); 11126 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11127 Regs64bit ? X86::RDX : X86::EDX, 11128 HalfT, cpOutL.getValue(2)); 11129 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11130 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11131 Results.push_back(cpOutH.getValue(1)); 11132 return; 11133 } 11134 case ISD::ATOMIC_LOAD_ADD: 11135 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11136 return; 11137 case ISD::ATOMIC_LOAD_AND: 11138 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11139 return; 11140 case ISD::ATOMIC_LOAD_NAND: 11141 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11142 return; 11143 case ISD::ATOMIC_LOAD_OR: 11144 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11145 return; 11146 case ISD::ATOMIC_LOAD_SUB: 11147 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11148 return; 11149 case ISD::ATOMIC_LOAD_XOR: 11150 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11151 return; 11152 case ISD::ATOMIC_SWAP: 11153 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11154 return; 11155 case ISD::ATOMIC_LOAD: 11156 ReplaceATOMIC_LOAD(N, Results, DAG); 11157 } 11158} 11159 11160const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11161 switch (Opcode) { 11162 default: return NULL; 11163 case X86ISD::BSF: return "X86ISD::BSF"; 11164 case X86ISD::BSR: return "X86ISD::BSR"; 11165 case X86ISD::SHLD: return "X86ISD::SHLD"; 11166 case X86ISD::SHRD: return "X86ISD::SHRD"; 11167 case X86ISD::FAND: return "X86ISD::FAND"; 11168 case X86ISD::FOR: return "X86ISD::FOR"; 11169 case X86ISD::FXOR: return "X86ISD::FXOR"; 11170 case X86ISD::FSRL: return "X86ISD::FSRL"; 11171 case X86ISD::FILD: return "X86ISD::FILD"; 11172 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11173 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11174 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11175 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11176 case X86ISD::FLD: return "X86ISD::FLD"; 11177 case X86ISD::FST: return "X86ISD::FST"; 11178 case X86ISD::CALL: return "X86ISD::CALL"; 11179 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11180 case X86ISD::BT: return "X86ISD::BT"; 11181 case X86ISD::CMP: return "X86ISD::CMP"; 11182 case X86ISD::COMI: return "X86ISD::COMI"; 11183 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11184 case X86ISD::SETCC: return "X86ISD::SETCC"; 11185 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11186 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11187 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11188 case X86ISD::CMOV: return "X86ISD::CMOV"; 11189 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11190 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11191 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11192 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11193 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11194 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11195 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11196 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11197 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11198 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11199 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11200 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11201 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11202 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11203 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11204 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11205 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11206 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11207 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11208 case X86ISD::HADD: return "X86ISD::HADD"; 11209 case X86ISD::HSUB: return "X86ISD::HSUB"; 11210 case X86ISD::FHADD: return "X86ISD::FHADD"; 11211 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11212 case X86ISD::FMAX: return "X86ISD::FMAX"; 11213 case X86ISD::FMIN: return "X86ISD::FMIN"; 11214 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11215 case X86ISD::FRCP: return "X86ISD::FRCP"; 11216 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11217 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11218 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11219 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11220 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11221 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 11222 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11223 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11224 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11225 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11226 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11227 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11228 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11229 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11230 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11231 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11232 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11233 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11234 case X86ISD::VSHL: return "X86ISD::VSHL"; 11235 case X86ISD::VSRL: return "X86ISD::VSRL"; 11236 case X86ISD::VSRA: return "X86ISD::VSRA"; 11237 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11238 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11239 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11240 case X86ISD::CMPP: return "X86ISD::CMPP"; 11241 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11242 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11243 case X86ISD::ADD: return "X86ISD::ADD"; 11244 case X86ISD::SUB: return "X86ISD::SUB"; 11245 case X86ISD::ADC: return "X86ISD::ADC"; 11246 case X86ISD::SBB: return "X86ISD::SBB"; 11247 case X86ISD::SMUL: return "X86ISD::SMUL"; 11248 case X86ISD::UMUL: return "X86ISD::UMUL"; 11249 case X86ISD::INC: return "X86ISD::INC"; 11250 case X86ISD::DEC: return "X86ISD::DEC"; 11251 case X86ISD::OR: return "X86ISD::OR"; 11252 case X86ISD::XOR: return "X86ISD::XOR"; 11253 case X86ISD::AND: return "X86ISD::AND"; 11254 case X86ISD::ANDN: return "X86ISD::ANDN"; 11255 case X86ISD::BLSI: return "X86ISD::BLSI"; 11256 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11257 case X86ISD::BLSR: return "X86ISD::BLSR"; 11258 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11259 case X86ISD::PTEST: return "X86ISD::PTEST"; 11260 case X86ISD::TESTP: return "X86ISD::TESTP"; 11261 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11262 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11263 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11264 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11265 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11266 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11267 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11268 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11269 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11270 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11271 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11272 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11273 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11274 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11275 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11276 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11277 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11278 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11279 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11280 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11281 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11282 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11283 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11284 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11285 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11286 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11287 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11288 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11289 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11290 case X86ISD::SAHF: return "X86ISD::SAHF"; 11291 } 11292} 11293 11294// isLegalAddressingMode - Return true if the addressing mode represented 11295// by AM is legal for this target, for a load/store of the specified type. 11296bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11297 Type *Ty) const { 11298 // X86 supports extremely general addressing modes. 11299 CodeModel::Model M = getTargetMachine().getCodeModel(); 11300 Reloc::Model R = getTargetMachine().getRelocationModel(); 11301 11302 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11303 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11304 return false; 11305 11306 if (AM.BaseGV) { 11307 unsigned GVFlags = 11308 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11309 11310 // If a reference to this global requires an extra load, we can't fold it. 11311 if (isGlobalStubReference(GVFlags)) 11312 return false; 11313 11314 // If BaseGV requires a register for the PIC base, we cannot also have a 11315 // BaseReg specified. 11316 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11317 return false; 11318 11319 // If lower 4G is not available, then we must use rip-relative addressing. 11320 if ((M != CodeModel::Small || R != Reloc::Static) && 11321 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11322 return false; 11323 } 11324 11325 switch (AM.Scale) { 11326 case 0: 11327 case 1: 11328 case 2: 11329 case 4: 11330 case 8: 11331 // These scales always work. 11332 break; 11333 case 3: 11334 case 5: 11335 case 9: 11336 // These scales are formed with basereg+scalereg. Only accept if there is 11337 // no basereg yet. 11338 if (AM.HasBaseReg) 11339 return false; 11340 break; 11341 default: // Other stuff never works. 11342 return false; 11343 } 11344 11345 return true; 11346} 11347 11348 11349bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11350 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11351 return false; 11352 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11353 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11354 if (NumBits1 <= NumBits2) 11355 return false; 11356 return true; 11357} 11358 11359bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11360 if (!VT1.isInteger() || !VT2.isInteger()) 11361 return false; 11362 unsigned NumBits1 = VT1.getSizeInBits(); 11363 unsigned NumBits2 = VT2.getSizeInBits(); 11364 if (NumBits1 <= NumBits2) 11365 return false; 11366 return true; 11367} 11368 11369bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11370 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11371 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11372} 11373 11374bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11375 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11376 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11377} 11378 11379bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11380 // i16 instructions are longer (0x66 prefix) and potentially slower. 11381 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11382} 11383 11384/// isShuffleMaskLegal - Targets can use this to indicate that they only 11385/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11386/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11387/// are assumed to be legal. 11388bool 11389X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11390 EVT VT) const { 11391 // Very little shuffling can be done for 64-bit vectors right now. 11392 if (VT.getSizeInBits() == 64) 11393 return false; 11394 11395 // FIXME: pshufb, blends, shifts. 11396 return (VT.getVectorNumElements() == 2 || 11397 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11398 isMOVLMask(M, VT) || 11399 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11400 isPSHUFDMask(M, VT) || 11401 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) || 11402 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) || 11403 isPALIGNRMask(M, VT, Subtarget) || 11404 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11405 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11406 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11407 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11408} 11409 11410bool 11411X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11412 EVT VT) const { 11413 unsigned NumElts = VT.getVectorNumElements(); 11414 // FIXME: This collection of masks seems suspect. 11415 if (NumElts == 2) 11416 return true; 11417 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11418 return (isMOVLMask(Mask, VT) || 11419 isCommutedMOVLMask(Mask, VT, true) || 11420 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11421 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11422 } 11423 return false; 11424} 11425 11426//===----------------------------------------------------------------------===// 11427// X86 Scheduler Hooks 11428//===----------------------------------------------------------------------===// 11429 11430// private utility function 11431MachineBasicBlock * 11432X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11433 MachineBasicBlock *MBB, 11434 unsigned regOpc, 11435 unsigned immOpc, 11436 unsigned LoadOpc, 11437 unsigned CXchgOpc, 11438 unsigned notOpc, 11439 unsigned EAXreg, 11440 const TargetRegisterClass *RC, 11441 bool Invert) const { 11442 // For the atomic bitwise operator, we generate 11443 // thisMBB: 11444 // newMBB: 11445 // ld t1 = [bitinstr.addr] 11446 // op t2 = t1, [bitinstr.val] 11447 // not t3 = t2 (if Invert) 11448 // mov EAX = t1 11449 // lcs dest = [bitinstr.addr], t3 [EAX is implicit] 11450 // bz newMBB 11451 // fallthrough -->nextMBB 11452 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11453 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11454 MachineFunction::iterator MBBIter = MBB; 11455 ++MBBIter; 11456 11457 /// First build the CFG 11458 MachineFunction *F = MBB->getParent(); 11459 MachineBasicBlock *thisMBB = MBB; 11460 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11461 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11462 F->insert(MBBIter, newMBB); 11463 F->insert(MBBIter, nextMBB); 11464 11465 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11466 nextMBB->splice(nextMBB->begin(), thisMBB, 11467 llvm::next(MachineBasicBlock::iterator(bInstr)), 11468 thisMBB->end()); 11469 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11470 11471 // Update thisMBB to fall through to newMBB 11472 thisMBB->addSuccessor(newMBB); 11473 11474 // newMBB jumps to itself and fall through to nextMBB 11475 newMBB->addSuccessor(nextMBB); 11476 newMBB->addSuccessor(newMBB); 11477 11478 // Insert instructions into newMBB based on incoming instruction 11479 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11480 "unexpected number of operands"); 11481 DebugLoc dl = bInstr->getDebugLoc(); 11482 MachineOperand& destOper = bInstr->getOperand(0); 11483 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11484 int numArgs = bInstr->getNumOperands() - 1; 11485 for (int i=0; i < numArgs; ++i) 11486 argOpers[i] = &bInstr->getOperand(i+1); 11487 11488 // x86 address has 4 operands: base, index, scale, and displacement 11489 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11490 int valArgIndx = lastAddrIndx + 1; 11491 11492 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11493 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11494 for (int i=0; i <= lastAddrIndx; ++i) 11495 (*MIB).addOperand(*argOpers[i]); 11496 11497 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11498 assert((argOpers[valArgIndx]->isReg() || 11499 argOpers[valArgIndx]->isImm()) && 11500 "invalid operand"); 11501 if (argOpers[valArgIndx]->isReg()) 11502 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11503 else 11504 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11505 MIB.addReg(t1); 11506 (*MIB).addOperand(*argOpers[valArgIndx]); 11507 11508 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11509 if (Invert) { 11510 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2); 11511 } 11512 else 11513 t3 = t2; 11514 11515 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11516 MIB.addReg(t1); 11517 11518 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11519 for (int i=0; i <= lastAddrIndx; ++i) 11520 (*MIB).addOperand(*argOpers[i]); 11521 MIB.addReg(t3); 11522 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11523 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11524 bInstr->memoperands_end()); 11525 11526 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11527 MIB.addReg(EAXreg); 11528 11529 // insert branch 11530 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11531 11532 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11533 return nextMBB; 11534} 11535 11536// private utility function: 64 bit atomics on 32 bit host. 11537MachineBasicBlock * 11538X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11539 MachineBasicBlock *MBB, 11540 unsigned regOpcL, 11541 unsigned regOpcH, 11542 unsigned immOpcL, 11543 unsigned immOpcH, 11544 bool Invert) const { 11545 // For the atomic bitwise operator, we generate 11546 // thisMBB (instructions are in pairs, except cmpxchg8b) 11547 // ld t1,t2 = [bitinstr.addr] 11548 // newMBB: 11549 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11550 // op t5, t6 <- out1, out2, [bitinstr.val] 11551 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11552 // neg t7, t8 < t5, t6 (if Invert) 11553 // mov ECX, EBX <- t5, t6 11554 // mov EAX, EDX <- t1, t2 11555 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11556 // mov t3, t4 <- EAX, EDX 11557 // bz newMBB 11558 // result in out1, out2 11559 // fallthrough -->nextMBB 11560 11561 const TargetRegisterClass *RC = &X86::GR32RegClass; 11562 const unsigned LoadOpc = X86::MOV32rm; 11563 const unsigned NotOpc = X86::NOT32r; 11564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11565 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11566 MachineFunction::iterator MBBIter = MBB; 11567 ++MBBIter; 11568 11569 /// First build the CFG 11570 MachineFunction *F = MBB->getParent(); 11571 MachineBasicBlock *thisMBB = MBB; 11572 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11573 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11574 F->insert(MBBIter, newMBB); 11575 F->insert(MBBIter, nextMBB); 11576 11577 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11578 nextMBB->splice(nextMBB->begin(), thisMBB, 11579 llvm::next(MachineBasicBlock::iterator(bInstr)), 11580 thisMBB->end()); 11581 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11582 11583 // Update thisMBB to fall through to newMBB 11584 thisMBB->addSuccessor(newMBB); 11585 11586 // newMBB jumps to itself and fall through to nextMBB 11587 newMBB->addSuccessor(nextMBB); 11588 newMBB->addSuccessor(newMBB); 11589 11590 DebugLoc dl = bInstr->getDebugLoc(); 11591 // Insert instructions into newMBB based on incoming instruction 11592 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11593 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11594 "unexpected number of operands"); 11595 MachineOperand& dest1Oper = bInstr->getOperand(0); 11596 MachineOperand& dest2Oper = bInstr->getOperand(1); 11597 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11598 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11599 argOpers[i] = &bInstr->getOperand(i+2); 11600 11601 // We use some of the operands multiple times, so conservatively just 11602 // clear any kill flags that might be present. 11603 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11604 argOpers[i]->setIsKill(false); 11605 } 11606 11607 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11608 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11609 11610 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11611 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11612 for (int i=0; i <= lastAddrIndx; ++i) 11613 (*MIB).addOperand(*argOpers[i]); 11614 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11615 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11616 // add 4 to displacement. 11617 for (int i=0; i <= lastAddrIndx-2; ++i) 11618 (*MIB).addOperand(*argOpers[i]); 11619 MachineOperand newOp3 = *(argOpers[3]); 11620 if (newOp3.isImm()) 11621 newOp3.setImm(newOp3.getImm()+4); 11622 else 11623 newOp3.setOffset(newOp3.getOffset()+4); 11624 (*MIB).addOperand(newOp3); 11625 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11626 11627 // t3/4 are defined later, at the bottom of the loop 11628 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11629 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11630 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11631 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11632 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11633 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11634 11635 // The subsequent operations should be using the destination registers of 11636 // the PHI instructions. 11637 t1 = dest1Oper.getReg(); 11638 t2 = dest2Oper.getReg(); 11639 11640 int valArgIndx = lastAddrIndx + 1; 11641 assert((argOpers[valArgIndx]->isReg() || 11642 argOpers[valArgIndx]->isImm()) && 11643 "invalid operand"); 11644 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11645 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11646 if (argOpers[valArgIndx]->isReg()) 11647 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11648 else 11649 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11650 if (regOpcL != X86::MOV32rr) 11651 MIB.addReg(t1); 11652 (*MIB).addOperand(*argOpers[valArgIndx]); 11653 assert(argOpers[valArgIndx + 1]->isReg() == 11654 argOpers[valArgIndx]->isReg()); 11655 assert(argOpers[valArgIndx + 1]->isImm() == 11656 argOpers[valArgIndx]->isImm()); 11657 if (argOpers[valArgIndx + 1]->isReg()) 11658 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11659 else 11660 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11661 if (regOpcH != X86::MOV32rr) 11662 MIB.addReg(t2); 11663 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11664 11665 unsigned t7, t8; 11666 if (Invert) { 11667 t7 = F->getRegInfo().createVirtualRegister(RC); 11668 t8 = F->getRegInfo().createVirtualRegister(RC); 11669 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5); 11670 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6); 11671 } else { 11672 t7 = t5; 11673 t8 = t6; 11674 } 11675 11676 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11677 MIB.addReg(t1); 11678 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11679 MIB.addReg(t2); 11680 11681 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11682 MIB.addReg(t7); 11683 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11684 MIB.addReg(t8); 11685 11686 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11687 for (int i=0; i <= lastAddrIndx; ++i) 11688 (*MIB).addOperand(*argOpers[i]); 11689 11690 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11691 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11692 bInstr->memoperands_end()); 11693 11694 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11695 MIB.addReg(X86::EAX); 11696 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11697 MIB.addReg(X86::EDX); 11698 11699 // insert branch 11700 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11701 11702 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11703 return nextMBB; 11704} 11705 11706// private utility function 11707MachineBasicBlock * 11708X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11709 MachineBasicBlock *MBB, 11710 unsigned cmovOpc) const { 11711 // For the atomic min/max operator, we generate 11712 // thisMBB: 11713 // newMBB: 11714 // ld t1 = [min/max.addr] 11715 // mov t2 = [min/max.val] 11716 // cmp t1, t2 11717 // cmov[cond] t2 = t1 11718 // mov EAX = t1 11719 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11720 // bz newMBB 11721 // fallthrough -->nextMBB 11722 // 11723 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11724 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11725 MachineFunction::iterator MBBIter = MBB; 11726 ++MBBIter; 11727 11728 /// First build the CFG 11729 MachineFunction *F = MBB->getParent(); 11730 MachineBasicBlock *thisMBB = MBB; 11731 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11732 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11733 F->insert(MBBIter, newMBB); 11734 F->insert(MBBIter, nextMBB); 11735 11736 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11737 nextMBB->splice(nextMBB->begin(), thisMBB, 11738 llvm::next(MachineBasicBlock::iterator(mInstr)), 11739 thisMBB->end()); 11740 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11741 11742 // Update thisMBB to fall through to newMBB 11743 thisMBB->addSuccessor(newMBB); 11744 11745 // newMBB jumps to newMBB and fall through to nextMBB 11746 newMBB->addSuccessor(nextMBB); 11747 newMBB->addSuccessor(newMBB); 11748 11749 DebugLoc dl = mInstr->getDebugLoc(); 11750 // Insert instructions into newMBB based on incoming instruction 11751 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11752 "unexpected number of operands"); 11753 MachineOperand& destOper = mInstr->getOperand(0); 11754 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11755 int numArgs = mInstr->getNumOperands() - 1; 11756 for (int i=0; i < numArgs; ++i) 11757 argOpers[i] = &mInstr->getOperand(i+1); 11758 11759 // x86 address has 4 operands: base, index, scale, and displacement 11760 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11761 int valArgIndx = lastAddrIndx + 1; 11762 11763 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11764 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11765 for (int i=0; i <= lastAddrIndx; ++i) 11766 (*MIB).addOperand(*argOpers[i]); 11767 11768 // We only support register and immediate values 11769 assert((argOpers[valArgIndx]->isReg() || 11770 argOpers[valArgIndx]->isImm()) && 11771 "invalid operand"); 11772 11773 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11774 if (argOpers[valArgIndx]->isReg()) 11775 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11776 else 11777 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11778 (*MIB).addOperand(*argOpers[valArgIndx]); 11779 11780 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11781 MIB.addReg(t1); 11782 11783 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11784 MIB.addReg(t1); 11785 MIB.addReg(t2); 11786 11787 // Generate movc 11788 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11789 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11790 MIB.addReg(t2); 11791 MIB.addReg(t1); 11792 11793 // Cmp and exchange if none has modified the memory location 11794 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11795 for (int i=0; i <= lastAddrIndx; ++i) 11796 (*MIB).addOperand(*argOpers[i]); 11797 MIB.addReg(t3); 11798 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11799 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11800 mInstr->memoperands_end()); 11801 11802 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11803 MIB.addReg(X86::EAX); 11804 11805 // insert branch 11806 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11807 11808 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11809 return nextMBB; 11810} 11811 11812// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11813// or XMM0_V32I8 in AVX all of this code can be replaced with that 11814// in the .td file. 11815MachineBasicBlock * 11816X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11817 unsigned numArgs, bool memArg) const { 11818 assert(Subtarget->hasSSE42() && 11819 "Target must have SSE4.2 or AVX features enabled"); 11820 11821 DebugLoc dl = MI->getDebugLoc(); 11822 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11823 unsigned Opc; 11824 if (!Subtarget->hasAVX()) { 11825 if (memArg) 11826 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11827 else 11828 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11829 } else { 11830 if (memArg) 11831 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11832 else 11833 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11834 } 11835 11836 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11837 for (unsigned i = 0; i < numArgs; ++i) { 11838 MachineOperand &Op = MI->getOperand(i+1); 11839 if (!(Op.isReg() && Op.isImplicit())) 11840 MIB.addOperand(Op); 11841 } 11842 BuildMI(*BB, MI, dl, 11843 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11844 MI->getOperand(0).getReg()) 11845 .addReg(X86::XMM0); 11846 11847 MI->eraseFromParent(); 11848 return BB; 11849} 11850 11851MachineBasicBlock * 11852X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11853 DebugLoc dl = MI->getDebugLoc(); 11854 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11855 11856 // Address into RAX/EAX, other two args into ECX, EDX. 11857 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11858 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11859 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11860 for (int i = 0; i < X86::AddrNumOperands; ++i) 11861 MIB.addOperand(MI->getOperand(i)); 11862 11863 unsigned ValOps = X86::AddrNumOperands; 11864 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11865 .addReg(MI->getOperand(ValOps).getReg()); 11866 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11867 .addReg(MI->getOperand(ValOps+1).getReg()); 11868 11869 // The instruction doesn't actually take any operands though. 11870 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11871 11872 MI->eraseFromParent(); // The pseudo is gone now. 11873 return BB; 11874} 11875 11876MachineBasicBlock * 11877X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11878 DebugLoc dl = MI->getDebugLoc(); 11879 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11880 11881 // First arg in ECX, the second in EAX. 11882 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11883 .addReg(MI->getOperand(0).getReg()); 11884 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11885 .addReg(MI->getOperand(1).getReg()); 11886 11887 // The instruction doesn't actually take any operands though. 11888 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11889 11890 MI->eraseFromParent(); // The pseudo is gone now. 11891 return BB; 11892} 11893 11894MachineBasicBlock * 11895X86TargetLowering::EmitVAARG64WithCustomInserter( 11896 MachineInstr *MI, 11897 MachineBasicBlock *MBB) const { 11898 // Emit va_arg instruction on X86-64. 11899 11900 // Operands to this pseudo-instruction: 11901 // 0 ) Output : destination address (reg) 11902 // 1-5) Input : va_list address (addr, i64mem) 11903 // 6 ) ArgSize : Size (in bytes) of vararg type 11904 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11905 // 8 ) Align : Alignment of type 11906 // 9 ) EFLAGS (implicit-def) 11907 11908 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11909 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11910 11911 unsigned DestReg = MI->getOperand(0).getReg(); 11912 MachineOperand &Base = MI->getOperand(1); 11913 MachineOperand &Scale = MI->getOperand(2); 11914 MachineOperand &Index = MI->getOperand(3); 11915 MachineOperand &Disp = MI->getOperand(4); 11916 MachineOperand &Segment = MI->getOperand(5); 11917 unsigned ArgSize = MI->getOperand(6).getImm(); 11918 unsigned ArgMode = MI->getOperand(7).getImm(); 11919 unsigned Align = MI->getOperand(8).getImm(); 11920 11921 // Memory Reference 11922 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11923 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11924 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11925 11926 // Machine Information 11927 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11928 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11929 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11930 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11931 DebugLoc DL = MI->getDebugLoc(); 11932 11933 // struct va_list { 11934 // i32 gp_offset 11935 // i32 fp_offset 11936 // i64 overflow_area (address) 11937 // i64 reg_save_area (address) 11938 // } 11939 // sizeof(va_list) = 24 11940 // alignment(va_list) = 8 11941 11942 unsigned TotalNumIntRegs = 6; 11943 unsigned TotalNumXMMRegs = 8; 11944 bool UseGPOffset = (ArgMode == 1); 11945 bool UseFPOffset = (ArgMode == 2); 11946 unsigned MaxOffset = TotalNumIntRegs * 8 + 11947 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11948 11949 /* Align ArgSize to a multiple of 8 */ 11950 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11951 bool NeedsAlign = (Align > 8); 11952 11953 MachineBasicBlock *thisMBB = MBB; 11954 MachineBasicBlock *overflowMBB; 11955 MachineBasicBlock *offsetMBB; 11956 MachineBasicBlock *endMBB; 11957 11958 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11959 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11960 unsigned OffsetReg = 0; 11961 11962 if (!UseGPOffset && !UseFPOffset) { 11963 // If we only pull from the overflow region, we don't create a branch. 11964 // We don't need to alter control flow. 11965 OffsetDestReg = 0; // unused 11966 OverflowDestReg = DestReg; 11967 11968 offsetMBB = NULL; 11969 overflowMBB = thisMBB; 11970 endMBB = thisMBB; 11971 } else { 11972 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11973 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11974 // If not, pull from overflow_area. (branch to overflowMBB) 11975 // 11976 // thisMBB 11977 // | . 11978 // | . 11979 // offsetMBB overflowMBB 11980 // | . 11981 // | . 11982 // endMBB 11983 11984 // Registers for the PHI in endMBB 11985 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11986 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11987 11988 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11989 MachineFunction *MF = MBB->getParent(); 11990 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11991 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11992 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11993 11994 MachineFunction::iterator MBBIter = MBB; 11995 ++MBBIter; 11996 11997 // Insert the new basic blocks 11998 MF->insert(MBBIter, offsetMBB); 11999 MF->insert(MBBIter, overflowMBB); 12000 MF->insert(MBBIter, endMBB); 12001 12002 // Transfer the remainder of MBB and its successor edges to endMBB. 12003 endMBB->splice(endMBB->begin(), thisMBB, 12004 llvm::next(MachineBasicBlock::iterator(MI)), 12005 thisMBB->end()); 12006 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 12007 12008 // Make offsetMBB and overflowMBB successors of thisMBB 12009 thisMBB->addSuccessor(offsetMBB); 12010 thisMBB->addSuccessor(overflowMBB); 12011 12012 // endMBB is a successor of both offsetMBB and overflowMBB 12013 offsetMBB->addSuccessor(endMBB); 12014 overflowMBB->addSuccessor(endMBB); 12015 12016 // Load the offset value into a register 12017 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12018 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 12019 .addOperand(Base) 12020 .addOperand(Scale) 12021 .addOperand(Index) 12022 .addDisp(Disp, UseFPOffset ? 4 : 0) 12023 .addOperand(Segment) 12024 .setMemRefs(MMOBegin, MMOEnd); 12025 12026 // Check if there is enough room left to pull this argument. 12027 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 12028 .addReg(OffsetReg) 12029 .addImm(MaxOffset + 8 - ArgSizeA8); 12030 12031 // Branch to "overflowMBB" if offset >= max 12032 // Fall through to "offsetMBB" otherwise 12033 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 12034 .addMBB(overflowMBB); 12035 } 12036 12037 // In offsetMBB, emit code to use the reg_save_area. 12038 if (offsetMBB) { 12039 assert(OffsetReg != 0); 12040 12041 // Read the reg_save_area address. 12042 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 12043 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 12044 .addOperand(Base) 12045 .addOperand(Scale) 12046 .addOperand(Index) 12047 .addDisp(Disp, 16) 12048 .addOperand(Segment) 12049 .setMemRefs(MMOBegin, MMOEnd); 12050 12051 // Zero-extend the offset 12052 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 12053 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 12054 .addImm(0) 12055 .addReg(OffsetReg) 12056 .addImm(X86::sub_32bit); 12057 12058 // Add the offset to the reg_save_area to get the final address. 12059 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 12060 .addReg(OffsetReg64) 12061 .addReg(RegSaveReg); 12062 12063 // Compute the offset for the next argument 12064 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12065 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 12066 .addReg(OffsetReg) 12067 .addImm(UseFPOffset ? 16 : 8); 12068 12069 // Store it back into the va_list. 12070 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 12071 .addOperand(Base) 12072 .addOperand(Scale) 12073 .addOperand(Index) 12074 .addDisp(Disp, UseFPOffset ? 4 : 0) 12075 .addOperand(Segment) 12076 .addReg(NextOffsetReg) 12077 .setMemRefs(MMOBegin, MMOEnd); 12078 12079 // Jump to endMBB 12080 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12081 .addMBB(endMBB); 12082 } 12083 12084 // 12085 // Emit code to use overflow area 12086 // 12087 12088 // Load the overflow_area address into a register. 12089 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12090 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12091 .addOperand(Base) 12092 .addOperand(Scale) 12093 .addOperand(Index) 12094 .addDisp(Disp, 8) 12095 .addOperand(Segment) 12096 .setMemRefs(MMOBegin, MMOEnd); 12097 12098 // If we need to align it, do so. Otherwise, just copy the address 12099 // to OverflowDestReg. 12100 if (NeedsAlign) { 12101 // Align the overflow address 12102 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12103 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12104 12105 // aligned_addr = (addr + (align-1)) & ~(align-1) 12106 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12107 .addReg(OverflowAddrReg) 12108 .addImm(Align-1); 12109 12110 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12111 .addReg(TmpReg) 12112 .addImm(~(uint64_t)(Align-1)); 12113 } else { 12114 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12115 .addReg(OverflowAddrReg); 12116 } 12117 12118 // Compute the next overflow address after this argument. 12119 // (the overflow address should be kept 8-byte aligned) 12120 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12121 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12122 .addReg(OverflowDestReg) 12123 .addImm(ArgSizeA8); 12124 12125 // Store the new overflow address. 12126 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12127 .addOperand(Base) 12128 .addOperand(Scale) 12129 .addOperand(Index) 12130 .addDisp(Disp, 8) 12131 .addOperand(Segment) 12132 .addReg(NextAddrReg) 12133 .setMemRefs(MMOBegin, MMOEnd); 12134 12135 // If we branched, emit the PHI to the front of endMBB. 12136 if (offsetMBB) { 12137 BuildMI(*endMBB, endMBB->begin(), DL, 12138 TII->get(X86::PHI), DestReg) 12139 .addReg(OffsetDestReg).addMBB(offsetMBB) 12140 .addReg(OverflowDestReg).addMBB(overflowMBB); 12141 } 12142 12143 // Erase the pseudo instruction 12144 MI->eraseFromParent(); 12145 12146 return endMBB; 12147} 12148 12149MachineBasicBlock * 12150X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12151 MachineInstr *MI, 12152 MachineBasicBlock *MBB) const { 12153 // Emit code to save XMM registers to the stack. The ABI says that the 12154 // number of registers to save is given in %al, so it's theoretically 12155 // possible to do an indirect jump trick to avoid saving all of them, 12156 // however this code takes a simpler approach and just executes all 12157 // of the stores if %al is non-zero. It's less code, and it's probably 12158 // easier on the hardware branch predictor, and stores aren't all that 12159 // expensive anyway. 12160 12161 // Create the new basic blocks. One block contains all the XMM stores, 12162 // and one block is the final destination regardless of whether any 12163 // stores were performed. 12164 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12165 MachineFunction *F = MBB->getParent(); 12166 MachineFunction::iterator MBBIter = MBB; 12167 ++MBBIter; 12168 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12169 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12170 F->insert(MBBIter, XMMSaveMBB); 12171 F->insert(MBBIter, EndMBB); 12172 12173 // Transfer the remainder of MBB and its successor edges to EndMBB. 12174 EndMBB->splice(EndMBB->begin(), MBB, 12175 llvm::next(MachineBasicBlock::iterator(MI)), 12176 MBB->end()); 12177 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12178 12179 // The original block will now fall through to the XMM save block. 12180 MBB->addSuccessor(XMMSaveMBB); 12181 // The XMMSaveMBB will fall through to the end block. 12182 XMMSaveMBB->addSuccessor(EndMBB); 12183 12184 // Now add the instructions. 12185 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12186 DebugLoc DL = MI->getDebugLoc(); 12187 12188 unsigned CountReg = MI->getOperand(0).getReg(); 12189 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12190 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12191 12192 if (!Subtarget->isTargetWin64()) { 12193 // If %al is 0, branch around the XMM save block. 12194 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12195 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12196 MBB->addSuccessor(EndMBB); 12197 } 12198 12199 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12200 // In the XMM save block, save all the XMM argument registers. 12201 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12202 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12203 MachineMemOperand *MMO = 12204 F->getMachineMemOperand( 12205 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12206 MachineMemOperand::MOStore, 12207 /*Size=*/16, /*Align=*/16); 12208 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12209 .addFrameIndex(RegSaveFrameIndex) 12210 .addImm(/*Scale=*/1) 12211 .addReg(/*IndexReg=*/0) 12212 .addImm(/*Disp=*/Offset) 12213 .addReg(/*Segment=*/0) 12214 .addReg(MI->getOperand(i).getReg()) 12215 .addMemOperand(MMO); 12216 } 12217 12218 MI->eraseFromParent(); // The pseudo instruction is gone now. 12219 12220 return EndMBB; 12221} 12222 12223// The EFLAGS operand of SelectItr might be missing a kill marker 12224// because there were multiple uses of EFLAGS, and ISel didn't know 12225// which to mark. Figure out whether SelectItr should have had a 12226// kill marker, and set it if it should. Returns the correct kill 12227// marker value. 12228static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12229 MachineBasicBlock* BB, 12230 const TargetRegisterInfo* TRI) { 12231 // Scan forward through BB for a use/def of EFLAGS. 12232 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12233 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12234 const MachineInstr& mi = *miI; 12235 if (mi.readsRegister(X86::EFLAGS)) 12236 return false; 12237 if (mi.definesRegister(X86::EFLAGS)) 12238 break; // Should have kill-flag - update below. 12239 } 12240 12241 // If we hit the end of the block, check whether EFLAGS is live into a 12242 // successor. 12243 if (miI == BB->end()) { 12244 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12245 sEnd = BB->succ_end(); 12246 sItr != sEnd; ++sItr) { 12247 MachineBasicBlock* succ = *sItr; 12248 if (succ->isLiveIn(X86::EFLAGS)) 12249 return false; 12250 } 12251 } 12252 12253 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12254 // out. SelectMI should have a kill flag on EFLAGS. 12255 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12256 return true; 12257} 12258 12259MachineBasicBlock * 12260X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12261 MachineBasicBlock *BB) const { 12262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12263 DebugLoc DL = MI->getDebugLoc(); 12264 12265 // To "insert" a SELECT_CC instruction, we actually have to insert the 12266 // diamond control-flow pattern. The incoming instruction knows the 12267 // destination vreg to set, the condition code register to branch on, the 12268 // true/false values to select between, and a branch opcode to use. 12269 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12270 MachineFunction::iterator It = BB; 12271 ++It; 12272 12273 // thisMBB: 12274 // ... 12275 // TrueVal = ... 12276 // cmpTY ccX, r1, r2 12277 // bCC copy1MBB 12278 // fallthrough --> copy0MBB 12279 MachineBasicBlock *thisMBB = BB; 12280 MachineFunction *F = BB->getParent(); 12281 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12282 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12283 F->insert(It, copy0MBB); 12284 F->insert(It, sinkMBB); 12285 12286 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12287 // live into the sink and copy blocks. 12288 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12289 if (!MI->killsRegister(X86::EFLAGS) && 12290 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12291 copy0MBB->addLiveIn(X86::EFLAGS); 12292 sinkMBB->addLiveIn(X86::EFLAGS); 12293 } 12294 12295 // Transfer the remainder of BB and its successor edges to sinkMBB. 12296 sinkMBB->splice(sinkMBB->begin(), BB, 12297 llvm::next(MachineBasicBlock::iterator(MI)), 12298 BB->end()); 12299 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12300 12301 // Add the true and fallthrough blocks as its successors. 12302 BB->addSuccessor(copy0MBB); 12303 BB->addSuccessor(sinkMBB); 12304 12305 // Create the conditional branch instruction. 12306 unsigned Opc = 12307 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12308 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12309 12310 // copy0MBB: 12311 // %FalseValue = ... 12312 // # fallthrough to sinkMBB 12313 copy0MBB->addSuccessor(sinkMBB); 12314 12315 // sinkMBB: 12316 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12317 // ... 12318 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12319 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12320 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12321 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12322 12323 MI->eraseFromParent(); // The pseudo instruction is gone now. 12324 return sinkMBB; 12325} 12326 12327MachineBasicBlock * 12328X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12329 bool Is64Bit) const { 12330 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12331 DebugLoc DL = MI->getDebugLoc(); 12332 MachineFunction *MF = BB->getParent(); 12333 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12334 12335 assert(getTargetMachine().Options.EnableSegmentedStacks); 12336 12337 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12338 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12339 12340 // BB: 12341 // ... [Till the alloca] 12342 // If stacklet is not large enough, jump to mallocMBB 12343 // 12344 // bumpMBB: 12345 // Allocate by subtracting from RSP 12346 // Jump to continueMBB 12347 // 12348 // mallocMBB: 12349 // Allocate by call to runtime 12350 // 12351 // continueMBB: 12352 // ... 12353 // [rest of original BB] 12354 // 12355 12356 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12357 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12358 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12359 12360 MachineRegisterInfo &MRI = MF->getRegInfo(); 12361 const TargetRegisterClass *AddrRegClass = 12362 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12363 12364 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12365 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12366 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12367 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12368 sizeVReg = MI->getOperand(1).getReg(), 12369 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12370 12371 MachineFunction::iterator MBBIter = BB; 12372 ++MBBIter; 12373 12374 MF->insert(MBBIter, bumpMBB); 12375 MF->insert(MBBIter, mallocMBB); 12376 MF->insert(MBBIter, continueMBB); 12377 12378 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12379 (MachineBasicBlock::iterator(MI)), BB->end()); 12380 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12381 12382 // Add code to the main basic block to check if the stack limit has been hit, 12383 // and if so, jump to mallocMBB otherwise to bumpMBB. 12384 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12385 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12386 .addReg(tmpSPVReg).addReg(sizeVReg); 12387 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12388 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12389 .addReg(SPLimitVReg); 12390 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12391 12392 // bumpMBB simply decreases the stack pointer, since we know the current 12393 // stacklet has enough space. 12394 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12395 .addReg(SPLimitVReg); 12396 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12397 .addReg(SPLimitVReg); 12398 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12399 12400 // Calls into a routine in libgcc to allocate more space from the heap. 12401 const uint32_t *RegMask = 12402 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12403 if (Is64Bit) { 12404 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12405 .addReg(sizeVReg); 12406 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12407 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12408 .addRegMask(RegMask) 12409 .addReg(X86::RAX, RegState::ImplicitDefine); 12410 } else { 12411 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12412 .addImm(12); 12413 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12414 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12415 .addExternalSymbol("__morestack_allocate_stack_space") 12416 .addRegMask(RegMask) 12417 .addReg(X86::EAX, RegState::ImplicitDefine); 12418 } 12419 12420 if (!Is64Bit) 12421 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12422 .addImm(16); 12423 12424 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12425 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12426 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12427 12428 // Set up the CFG correctly. 12429 BB->addSuccessor(bumpMBB); 12430 BB->addSuccessor(mallocMBB); 12431 mallocMBB->addSuccessor(continueMBB); 12432 bumpMBB->addSuccessor(continueMBB); 12433 12434 // Take care of the PHI nodes. 12435 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12436 MI->getOperand(0).getReg()) 12437 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12438 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12439 12440 // Delete the original pseudo instruction. 12441 MI->eraseFromParent(); 12442 12443 // And we're done. 12444 return continueMBB; 12445} 12446 12447MachineBasicBlock * 12448X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12449 MachineBasicBlock *BB) const { 12450 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12451 DebugLoc DL = MI->getDebugLoc(); 12452 12453 assert(!Subtarget->isTargetEnvMacho()); 12454 12455 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12456 // non-trivial part is impdef of ESP. 12457 12458 if (Subtarget->isTargetWin64()) { 12459 if (Subtarget->isTargetCygMing()) { 12460 // ___chkstk(Mingw64): 12461 // Clobbers R10, R11, RAX and EFLAGS. 12462 // Updates RSP. 12463 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12464 .addExternalSymbol("___chkstk") 12465 .addReg(X86::RAX, RegState::Implicit) 12466 .addReg(X86::RSP, RegState::Implicit) 12467 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12468 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12469 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12470 } else { 12471 // __chkstk(MSVCRT): does not update stack pointer. 12472 // Clobbers R10, R11 and EFLAGS. 12473 // FIXME: RAX(allocated size) might be reused and not killed. 12474 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12475 .addExternalSymbol("__chkstk") 12476 .addReg(X86::RAX, RegState::Implicit) 12477 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12478 // RAX has the offset to subtracted from RSP. 12479 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12480 .addReg(X86::RSP) 12481 .addReg(X86::RAX); 12482 } 12483 } else { 12484 const char *StackProbeSymbol = 12485 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12486 12487 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12488 .addExternalSymbol(StackProbeSymbol) 12489 .addReg(X86::EAX, RegState::Implicit) 12490 .addReg(X86::ESP, RegState::Implicit) 12491 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12492 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12493 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12494 } 12495 12496 MI->eraseFromParent(); // The pseudo instruction is gone now. 12497 return BB; 12498} 12499 12500MachineBasicBlock * 12501X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12502 MachineBasicBlock *BB) const { 12503 // This is pretty easy. We're taking the value that we received from 12504 // our load from the relocation, sticking it in either RDI (x86-64) 12505 // or EAX and doing an indirect call. The return value will then 12506 // be in the normal return register. 12507 const X86InstrInfo *TII 12508 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12509 DebugLoc DL = MI->getDebugLoc(); 12510 MachineFunction *F = BB->getParent(); 12511 12512 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12513 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12514 12515 // Get a register mask for the lowered call. 12516 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12517 // proper register mask. 12518 const uint32_t *RegMask = 12519 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12520 if (Subtarget->is64Bit()) { 12521 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12522 TII->get(X86::MOV64rm), X86::RDI) 12523 .addReg(X86::RIP) 12524 .addImm(0).addReg(0) 12525 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12526 MI->getOperand(3).getTargetFlags()) 12527 .addReg(0); 12528 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12529 addDirectMem(MIB, X86::RDI); 12530 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12531 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12532 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12533 TII->get(X86::MOV32rm), X86::EAX) 12534 .addReg(0) 12535 .addImm(0).addReg(0) 12536 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12537 MI->getOperand(3).getTargetFlags()) 12538 .addReg(0); 12539 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12540 addDirectMem(MIB, X86::EAX); 12541 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12542 } else { 12543 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12544 TII->get(X86::MOV32rm), X86::EAX) 12545 .addReg(TII->getGlobalBaseReg(F)) 12546 .addImm(0).addReg(0) 12547 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12548 MI->getOperand(3).getTargetFlags()) 12549 .addReg(0); 12550 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12551 addDirectMem(MIB, X86::EAX); 12552 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12553 } 12554 12555 MI->eraseFromParent(); // The pseudo instruction is gone now. 12556 return BB; 12557} 12558 12559MachineBasicBlock * 12560X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12561 MachineBasicBlock *BB) const { 12562 switch (MI->getOpcode()) { 12563 default: llvm_unreachable("Unexpected instr type to insert"); 12564 case X86::TAILJMPd64: 12565 case X86::TAILJMPr64: 12566 case X86::TAILJMPm64: 12567 llvm_unreachable("TAILJMP64 would not be touched here."); 12568 case X86::TCRETURNdi64: 12569 case X86::TCRETURNri64: 12570 case X86::TCRETURNmi64: 12571 return BB; 12572 case X86::WIN_ALLOCA: 12573 return EmitLoweredWinAlloca(MI, BB); 12574 case X86::SEG_ALLOCA_32: 12575 return EmitLoweredSegAlloca(MI, BB, false); 12576 case X86::SEG_ALLOCA_64: 12577 return EmitLoweredSegAlloca(MI, BB, true); 12578 case X86::TLSCall_32: 12579 case X86::TLSCall_64: 12580 return EmitLoweredTLSCall(MI, BB); 12581 case X86::CMOV_GR8: 12582 case X86::CMOV_FR32: 12583 case X86::CMOV_FR64: 12584 case X86::CMOV_V4F32: 12585 case X86::CMOV_V2F64: 12586 case X86::CMOV_V2I64: 12587 case X86::CMOV_V8F32: 12588 case X86::CMOV_V4F64: 12589 case X86::CMOV_V4I64: 12590 case X86::CMOV_GR16: 12591 case X86::CMOV_GR32: 12592 case X86::CMOV_RFP32: 12593 case X86::CMOV_RFP64: 12594 case X86::CMOV_RFP80: 12595 return EmitLoweredSelect(MI, BB); 12596 12597 case X86::FP32_TO_INT16_IN_MEM: 12598 case X86::FP32_TO_INT32_IN_MEM: 12599 case X86::FP32_TO_INT64_IN_MEM: 12600 case X86::FP64_TO_INT16_IN_MEM: 12601 case X86::FP64_TO_INT32_IN_MEM: 12602 case X86::FP64_TO_INT64_IN_MEM: 12603 case X86::FP80_TO_INT16_IN_MEM: 12604 case X86::FP80_TO_INT32_IN_MEM: 12605 case X86::FP80_TO_INT64_IN_MEM: { 12606 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12607 DebugLoc DL = MI->getDebugLoc(); 12608 12609 // Change the floating point control register to use "round towards zero" 12610 // mode when truncating to an integer value. 12611 MachineFunction *F = BB->getParent(); 12612 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12613 addFrameReference(BuildMI(*BB, MI, DL, 12614 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12615 12616 // Load the old value of the high byte of the control word... 12617 unsigned OldCW = 12618 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 12619 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12620 CWFrameIdx); 12621 12622 // Set the high part to be round to zero... 12623 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12624 .addImm(0xC7F); 12625 12626 // Reload the modified control word now... 12627 addFrameReference(BuildMI(*BB, MI, DL, 12628 TII->get(X86::FLDCW16m)), CWFrameIdx); 12629 12630 // Restore the memory image of control word to original value 12631 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12632 .addReg(OldCW); 12633 12634 // Get the X86 opcode to use. 12635 unsigned Opc; 12636 switch (MI->getOpcode()) { 12637 default: llvm_unreachable("illegal opcode!"); 12638 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12639 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12640 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12641 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12642 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12643 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12644 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12645 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12646 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12647 } 12648 12649 X86AddressMode AM; 12650 MachineOperand &Op = MI->getOperand(0); 12651 if (Op.isReg()) { 12652 AM.BaseType = X86AddressMode::RegBase; 12653 AM.Base.Reg = Op.getReg(); 12654 } else { 12655 AM.BaseType = X86AddressMode::FrameIndexBase; 12656 AM.Base.FrameIndex = Op.getIndex(); 12657 } 12658 Op = MI->getOperand(1); 12659 if (Op.isImm()) 12660 AM.Scale = Op.getImm(); 12661 Op = MI->getOperand(2); 12662 if (Op.isImm()) 12663 AM.IndexReg = Op.getImm(); 12664 Op = MI->getOperand(3); 12665 if (Op.isGlobal()) { 12666 AM.GV = Op.getGlobal(); 12667 } else { 12668 AM.Disp = Op.getImm(); 12669 } 12670 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12671 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12672 12673 // Reload the original control word now. 12674 addFrameReference(BuildMI(*BB, MI, DL, 12675 TII->get(X86::FLDCW16m)), CWFrameIdx); 12676 12677 MI->eraseFromParent(); // The pseudo instruction is gone now. 12678 return BB; 12679 } 12680 // String/text processing lowering. 12681 case X86::PCMPISTRM128REG: 12682 case X86::VPCMPISTRM128REG: 12683 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12684 case X86::PCMPISTRM128MEM: 12685 case X86::VPCMPISTRM128MEM: 12686 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12687 case X86::PCMPESTRM128REG: 12688 case X86::VPCMPESTRM128REG: 12689 return EmitPCMP(MI, BB, 5, false /* in mem */); 12690 case X86::PCMPESTRM128MEM: 12691 case X86::VPCMPESTRM128MEM: 12692 return EmitPCMP(MI, BB, 5, true /* in mem */); 12693 12694 // Thread synchronization. 12695 case X86::MONITOR: 12696 return EmitMonitor(MI, BB); 12697 case X86::MWAIT: 12698 return EmitMwait(MI, BB); 12699 12700 // Atomic Lowering. 12701 case X86::ATOMAND32: 12702 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12703 X86::AND32ri, X86::MOV32rm, 12704 X86::LCMPXCHG32, 12705 X86::NOT32r, X86::EAX, 12706 &X86::GR32RegClass); 12707 case X86::ATOMOR32: 12708 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12709 X86::OR32ri, X86::MOV32rm, 12710 X86::LCMPXCHG32, 12711 X86::NOT32r, X86::EAX, 12712 &X86::GR32RegClass); 12713 case X86::ATOMXOR32: 12714 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12715 X86::XOR32ri, X86::MOV32rm, 12716 X86::LCMPXCHG32, 12717 X86::NOT32r, X86::EAX, 12718 &X86::GR32RegClass); 12719 case X86::ATOMNAND32: 12720 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12721 X86::AND32ri, X86::MOV32rm, 12722 X86::LCMPXCHG32, 12723 X86::NOT32r, X86::EAX, 12724 &X86::GR32RegClass, true); 12725 case X86::ATOMMIN32: 12726 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12727 case X86::ATOMMAX32: 12728 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12729 case X86::ATOMUMIN32: 12730 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12731 case X86::ATOMUMAX32: 12732 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12733 12734 case X86::ATOMAND16: 12735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12736 X86::AND16ri, X86::MOV16rm, 12737 X86::LCMPXCHG16, 12738 X86::NOT16r, X86::AX, 12739 &X86::GR16RegClass); 12740 case X86::ATOMOR16: 12741 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12742 X86::OR16ri, X86::MOV16rm, 12743 X86::LCMPXCHG16, 12744 X86::NOT16r, X86::AX, 12745 &X86::GR16RegClass); 12746 case X86::ATOMXOR16: 12747 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12748 X86::XOR16ri, X86::MOV16rm, 12749 X86::LCMPXCHG16, 12750 X86::NOT16r, X86::AX, 12751 &X86::GR16RegClass); 12752 case X86::ATOMNAND16: 12753 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12754 X86::AND16ri, X86::MOV16rm, 12755 X86::LCMPXCHG16, 12756 X86::NOT16r, X86::AX, 12757 &X86::GR16RegClass, true); 12758 case X86::ATOMMIN16: 12759 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12760 case X86::ATOMMAX16: 12761 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12762 case X86::ATOMUMIN16: 12763 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12764 case X86::ATOMUMAX16: 12765 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12766 12767 case X86::ATOMAND8: 12768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12769 X86::AND8ri, X86::MOV8rm, 12770 X86::LCMPXCHG8, 12771 X86::NOT8r, X86::AL, 12772 &X86::GR8RegClass); 12773 case X86::ATOMOR8: 12774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12775 X86::OR8ri, X86::MOV8rm, 12776 X86::LCMPXCHG8, 12777 X86::NOT8r, X86::AL, 12778 &X86::GR8RegClass); 12779 case X86::ATOMXOR8: 12780 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12781 X86::XOR8ri, X86::MOV8rm, 12782 X86::LCMPXCHG8, 12783 X86::NOT8r, X86::AL, 12784 &X86::GR8RegClass); 12785 case X86::ATOMNAND8: 12786 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12787 X86::AND8ri, X86::MOV8rm, 12788 X86::LCMPXCHG8, 12789 X86::NOT8r, X86::AL, 12790 &X86::GR8RegClass, true); 12791 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12792 // This group is for 64-bit host. 12793 case X86::ATOMAND64: 12794 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12795 X86::AND64ri32, X86::MOV64rm, 12796 X86::LCMPXCHG64, 12797 X86::NOT64r, X86::RAX, 12798 &X86::GR64RegClass); 12799 case X86::ATOMOR64: 12800 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12801 X86::OR64ri32, X86::MOV64rm, 12802 X86::LCMPXCHG64, 12803 X86::NOT64r, X86::RAX, 12804 &X86::GR64RegClass); 12805 case X86::ATOMXOR64: 12806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12807 X86::XOR64ri32, X86::MOV64rm, 12808 X86::LCMPXCHG64, 12809 X86::NOT64r, X86::RAX, 12810 &X86::GR64RegClass); 12811 case X86::ATOMNAND64: 12812 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12813 X86::AND64ri32, X86::MOV64rm, 12814 X86::LCMPXCHG64, 12815 X86::NOT64r, X86::RAX, 12816 &X86::GR64RegClass, true); 12817 case X86::ATOMMIN64: 12818 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12819 case X86::ATOMMAX64: 12820 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12821 case X86::ATOMUMIN64: 12822 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12823 case X86::ATOMUMAX64: 12824 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12825 12826 // This group does 64-bit operations on a 32-bit host. 12827 case X86::ATOMAND6432: 12828 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12829 X86::AND32rr, X86::AND32rr, 12830 X86::AND32ri, X86::AND32ri, 12831 false); 12832 case X86::ATOMOR6432: 12833 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12834 X86::OR32rr, X86::OR32rr, 12835 X86::OR32ri, X86::OR32ri, 12836 false); 12837 case X86::ATOMXOR6432: 12838 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12839 X86::XOR32rr, X86::XOR32rr, 12840 X86::XOR32ri, X86::XOR32ri, 12841 false); 12842 case X86::ATOMNAND6432: 12843 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12844 X86::AND32rr, X86::AND32rr, 12845 X86::AND32ri, X86::AND32ri, 12846 true); 12847 case X86::ATOMADD6432: 12848 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12849 X86::ADD32rr, X86::ADC32rr, 12850 X86::ADD32ri, X86::ADC32ri, 12851 false); 12852 case X86::ATOMSUB6432: 12853 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12854 X86::SUB32rr, X86::SBB32rr, 12855 X86::SUB32ri, X86::SBB32ri, 12856 false); 12857 case X86::ATOMSWAP6432: 12858 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12859 X86::MOV32rr, X86::MOV32rr, 12860 X86::MOV32ri, X86::MOV32ri, 12861 false); 12862 case X86::VASTART_SAVE_XMM_REGS: 12863 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12864 12865 case X86::VAARG_64: 12866 return EmitVAARG64WithCustomInserter(MI, BB); 12867 } 12868} 12869 12870//===----------------------------------------------------------------------===// 12871// X86 Optimization Hooks 12872//===----------------------------------------------------------------------===// 12873 12874void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12875 APInt &KnownZero, 12876 APInt &KnownOne, 12877 const SelectionDAG &DAG, 12878 unsigned Depth) const { 12879 unsigned BitWidth = KnownZero.getBitWidth(); 12880 unsigned Opc = Op.getOpcode(); 12881 assert((Opc >= ISD::BUILTIN_OP_END || 12882 Opc == ISD::INTRINSIC_WO_CHAIN || 12883 Opc == ISD::INTRINSIC_W_CHAIN || 12884 Opc == ISD::INTRINSIC_VOID) && 12885 "Should use MaskedValueIsZero if you don't know whether Op" 12886 " is a target node!"); 12887 12888 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12889 switch (Opc) { 12890 default: break; 12891 case X86ISD::ADD: 12892 case X86ISD::SUB: 12893 case X86ISD::ADC: 12894 case X86ISD::SBB: 12895 case X86ISD::SMUL: 12896 case X86ISD::UMUL: 12897 case X86ISD::INC: 12898 case X86ISD::DEC: 12899 case X86ISD::OR: 12900 case X86ISD::XOR: 12901 case X86ISD::AND: 12902 // These nodes' second result is a boolean. 12903 if (Op.getResNo() == 0) 12904 break; 12905 // Fallthrough 12906 case X86ISD::SETCC: 12907 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12908 break; 12909 case ISD::INTRINSIC_WO_CHAIN: { 12910 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12911 unsigned NumLoBits = 0; 12912 switch (IntId) { 12913 default: break; 12914 case Intrinsic::x86_sse_movmsk_ps: 12915 case Intrinsic::x86_avx_movmsk_ps_256: 12916 case Intrinsic::x86_sse2_movmsk_pd: 12917 case Intrinsic::x86_avx_movmsk_pd_256: 12918 case Intrinsic::x86_mmx_pmovmskb: 12919 case Intrinsic::x86_sse2_pmovmskb_128: 12920 case Intrinsic::x86_avx2_pmovmskb: { 12921 // High bits of movmskp{s|d}, pmovmskb are known zero. 12922 switch (IntId) { 12923 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12924 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12925 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12926 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12927 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12928 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12929 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12930 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12931 } 12932 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12933 break; 12934 } 12935 } 12936 break; 12937 } 12938 } 12939} 12940 12941unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12942 unsigned Depth) const { 12943 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12944 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12945 return Op.getValueType().getScalarType().getSizeInBits(); 12946 12947 // Fallback case. 12948 return 1; 12949} 12950 12951/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12952/// node is a GlobalAddress + offset. 12953bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12954 const GlobalValue* &GA, 12955 int64_t &Offset) const { 12956 if (N->getOpcode() == X86ISD::Wrapper) { 12957 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12958 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12959 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12960 return true; 12961 } 12962 } 12963 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12964} 12965 12966/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12967/// same as extracting the high 128-bit part of 256-bit vector and then 12968/// inserting the result into the low part of a new 256-bit vector 12969static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12970 EVT VT = SVOp->getValueType(0); 12971 unsigned NumElems = VT.getVectorNumElements(); 12972 12973 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12974 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 12975 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12976 SVOp->getMaskElt(j) >= 0) 12977 return false; 12978 12979 return true; 12980} 12981 12982/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12983/// same as extracting the low 128-bit part of 256-bit vector and then 12984/// inserting the result into the high part of a new 256-bit vector 12985static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12986 EVT VT = SVOp->getValueType(0); 12987 unsigned NumElems = VT.getVectorNumElements(); 12988 12989 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12990 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 12991 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12992 SVOp->getMaskElt(j) >= 0) 12993 return false; 12994 12995 return true; 12996} 12997 12998/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12999static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 13000 TargetLowering::DAGCombinerInfo &DCI, 13001 const X86Subtarget* Subtarget) { 13002 DebugLoc dl = N->getDebugLoc(); 13003 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 13004 SDValue V1 = SVOp->getOperand(0); 13005 SDValue V2 = SVOp->getOperand(1); 13006 EVT VT = SVOp->getValueType(0); 13007 unsigned NumElems = VT.getVectorNumElements(); 13008 13009 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 13010 V2.getOpcode() == ISD::CONCAT_VECTORS) { 13011 // 13012 // 0,0,0,... 13013 // | 13014 // V UNDEF BUILD_VECTOR UNDEF 13015 // \ / \ / 13016 // CONCAT_VECTOR CONCAT_VECTOR 13017 // \ / 13018 // \ / 13019 // RESULT: V + zero extended 13020 // 13021 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 13022 V2.getOperand(1).getOpcode() != ISD::UNDEF || 13023 V1.getOperand(1).getOpcode() != ISD::UNDEF) 13024 return SDValue(); 13025 13026 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 13027 return SDValue(); 13028 13029 // To match the shuffle mask, the first half of the mask should 13030 // be exactly the first vector, and all the rest a splat with the 13031 // first element of the second one. 13032 for (unsigned i = 0; i != NumElems/2; ++i) 13033 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 13034 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 13035 return SDValue(); 13036 13037 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 13038 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 13039 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 13040 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 13041 SDValue ResNode = 13042 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 13043 Ld->getMemoryVT(), 13044 Ld->getPointerInfo(), 13045 Ld->getAlignment(), 13046 false/*isVolatile*/, true/*ReadMem*/, 13047 false/*WriteMem*/); 13048 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 13049 } 13050 13051 // Emit a zeroed vector and insert the desired subvector on its 13052 // first half. 13053 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 13054 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 13055 return DCI.CombineTo(N, InsV); 13056 } 13057 13058 //===--------------------------------------------------------------------===// 13059 // Combine some shuffles into subvector extracts and inserts: 13060 // 13061 13062 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13063 if (isShuffleHigh128VectorInsertLow(SVOp)) { 13064 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 13065 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 13066 return DCI.CombineTo(N, InsV); 13067 } 13068 13069 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13070 if (isShuffleLow128VectorInsertHigh(SVOp)) { 13071 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 13072 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 13073 return DCI.CombineTo(N, InsV); 13074 } 13075 13076 return SDValue(); 13077} 13078 13079/// PerformShuffleCombine - Performs several different shuffle combines. 13080static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13081 TargetLowering::DAGCombinerInfo &DCI, 13082 const X86Subtarget *Subtarget) { 13083 DebugLoc dl = N->getDebugLoc(); 13084 EVT VT = N->getValueType(0); 13085 13086 // Don't create instructions with illegal types after legalize types has run. 13087 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13088 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13089 return SDValue(); 13090 13091 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13092 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13093 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13094 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13095 13096 // Only handle 128 wide vector from here on. 13097 if (VT.getSizeInBits() != 128) 13098 return SDValue(); 13099 13100 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13101 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13102 // consecutive, non-overlapping, and in the right order. 13103 SmallVector<SDValue, 16> Elts; 13104 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13105 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13106 13107 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13108} 13109 13110 13111/// DCI, PerformTruncateCombine - Converts truncate operation to 13112/// a sequence of vector shuffle operations. 13113/// It is possible when we truncate 256-bit vector to 128-bit vector 13114 13115SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13116 DAGCombinerInfo &DCI) const { 13117 if (!DCI.isBeforeLegalizeOps()) 13118 return SDValue(); 13119 13120 if (!Subtarget->hasAVX()) 13121 return SDValue(); 13122 13123 EVT VT = N->getValueType(0); 13124 SDValue Op = N->getOperand(0); 13125 EVT OpVT = Op.getValueType(); 13126 DebugLoc dl = N->getDebugLoc(); 13127 13128 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13129 13130 if (Subtarget->hasAVX2()) { 13131 // AVX2: v4i64 -> v4i32 13132 13133 // VPERMD 13134 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 13135 13136 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op); 13137 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32), 13138 ShufMask); 13139 13140 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, 13141 DAG.getIntPtrConstant(0)); 13142 } 13143 13144 // AVX: v4i64 -> v4i32 13145 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13146 DAG.getIntPtrConstant(0)); 13147 13148 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13149 DAG.getIntPtrConstant(2)); 13150 13151 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13152 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13153 13154 // PSHUFD 13155 static const int ShufMask1[] = {0, 2, 0, 0}; 13156 13157 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1); 13158 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1); 13159 13160 // MOVLHPS 13161 static const int ShufMask2[] = {0, 1, 4, 5}; 13162 13163 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13164 } 13165 13166 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13167 13168 if (Subtarget->hasAVX2()) { 13169 // AVX2: v8i32 -> v8i16 13170 13171 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op); 13172 13173 // PSHUFB 13174 SmallVector<SDValue,32> pshufbMask; 13175 for (unsigned i = 0; i < 2; ++i) { 13176 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 13177 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 13178 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 13179 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 13180 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 13181 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 13182 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 13183 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 13184 for (unsigned j = 0; j < 8; ++j) 13185 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 13186 } 13187 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, 13188 &pshufbMask[0], 32); 13189 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV); 13190 13191 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op); 13192 13193 static const int ShufMask[] = {0, 2, -1, -1}; 13194 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64), 13195 &ShufMask[0]); 13196 13197 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13198 DAG.getIntPtrConstant(0)); 13199 13200 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 13201 } 13202 13203 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13204 DAG.getIntPtrConstant(0)); 13205 13206 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13207 DAG.getIntPtrConstant(4)); 13208 13209 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13210 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13211 13212 // PSHUFB 13213 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13214 -1, -1, -1, -1, -1, -1, -1, -1}; 13215 13216 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8), 13217 ShufMask1); 13218 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8), 13219 ShufMask1); 13220 13221 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13222 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13223 13224 // MOVLHPS 13225 static const int ShufMask2[] = {0, 1, 4, 5}; 13226 13227 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13228 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13229 } 13230 13231 return SDValue(); 13232} 13233 13234/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13235/// specific shuffle of a load can be folded into a single element load. 13236/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13237/// shuffles have been customed lowered so we need to handle those here. 13238static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13239 TargetLowering::DAGCombinerInfo &DCI) { 13240 if (DCI.isBeforeLegalizeOps()) 13241 return SDValue(); 13242 13243 SDValue InVec = N->getOperand(0); 13244 SDValue EltNo = N->getOperand(1); 13245 13246 if (!isa<ConstantSDNode>(EltNo)) 13247 return SDValue(); 13248 13249 EVT VT = InVec.getValueType(); 13250 13251 bool HasShuffleIntoBitcast = false; 13252 if (InVec.getOpcode() == ISD::BITCAST) { 13253 // Don't duplicate a load with other uses. 13254 if (!InVec.hasOneUse()) 13255 return SDValue(); 13256 EVT BCVT = InVec.getOperand(0).getValueType(); 13257 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13258 return SDValue(); 13259 InVec = InVec.getOperand(0); 13260 HasShuffleIntoBitcast = true; 13261 } 13262 13263 if (!isTargetShuffle(InVec.getOpcode())) 13264 return SDValue(); 13265 13266 // Don't duplicate a load with other uses. 13267 if (!InVec.hasOneUse()) 13268 return SDValue(); 13269 13270 SmallVector<int, 16> ShuffleMask; 13271 bool UnaryShuffle; 13272 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 13273 return SDValue(); 13274 13275 // Select the input vector, guarding against out of range extract vector. 13276 unsigned NumElems = VT.getVectorNumElements(); 13277 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13278 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13279 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13280 : InVec.getOperand(1); 13281 13282 // If inputs to shuffle are the same for both ops, then allow 2 uses 13283 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13284 13285 if (LdNode.getOpcode() == ISD::BITCAST) { 13286 // Don't duplicate a load with other uses. 13287 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13288 return SDValue(); 13289 13290 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13291 LdNode = LdNode.getOperand(0); 13292 } 13293 13294 if (!ISD::isNormalLoad(LdNode.getNode())) 13295 return SDValue(); 13296 13297 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13298 13299 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13300 return SDValue(); 13301 13302 if (HasShuffleIntoBitcast) { 13303 // If there's a bitcast before the shuffle, check if the load type and 13304 // alignment is valid. 13305 unsigned Align = LN0->getAlignment(); 13306 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13307 unsigned NewAlign = TLI.getTargetData()-> 13308 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13309 13310 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13311 return SDValue(); 13312 } 13313 13314 // All checks match so transform back to vector_shuffle so that DAG combiner 13315 // can finish the job 13316 DebugLoc dl = N->getDebugLoc(); 13317 13318 // Create shuffle node taking into account the case that its a unary shuffle 13319 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13320 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13321 InVec.getOperand(0), Shuffle, 13322 &ShuffleMask[0]); 13323 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13324 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13325 EltNo); 13326} 13327 13328/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13329/// generation and convert it from being a bunch of shuffles and extracts 13330/// to a simple store and scalar loads to extract the elements. 13331static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13332 TargetLowering::DAGCombinerInfo &DCI) { 13333 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13334 if (NewOp.getNode()) 13335 return NewOp; 13336 13337 SDValue InputVector = N->getOperand(0); 13338 13339 // Only operate on vectors of 4 elements, where the alternative shuffling 13340 // gets to be more expensive. 13341 if (InputVector.getValueType() != MVT::v4i32) 13342 return SDValue(); 13343 13344 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13345 // single use which is a sign-extend or zero-extend, and all elements are 13346 // used. 13347 SmallVector<SDNode *, 4> Uses; 13348 unsigned ExtractedElements = 0; 13349 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13350 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13351 if (UI.getUse().getResNo() != InputVector.getResNo()) 13352 return SDValue(); 13353 13354 SDNode *Extract = *UI; 13355 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13356 return SDValue(); 13357 13358 if (Extract->getValueType(0) != MVT::i32) 13359 return SDValue(); 13360 if (!Extract->hasOneUse()) 13361 return SDValue(); 13362 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13363 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13364 return SDValue(); 13365 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13366 return SDValue(); 13367 13368 // Record which element was extracted. 13369 ExtractedElements |= 13370 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13371 13372 Uses.push_back(Extract); 13373 } 13374 13375 // If not all the elements were used, this may not be worthwhile. 13376 if (ExtractedElements != 15) 13377 return SDValue(); 13378 13379 // Ok, we've now decided to do the transformation. 13380 DebugLoc dl = InputVector.getDebugLoc(); 13381 13382 // Store the value to a temporary stack slot. 13383 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13384 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13385 MachinePointerInfo(), false, false, 0); 13386 13387 // Replace each use (extract) with a load of the appropriate element. 13388 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13389 UE = Uses.end(); UI != UE; ++UI) { 13390 SDNode *Extract = *UI; 13391 13392 // cOMpute the element's address. 13393 SDValue Idx = Extract->getOperand(1); 13394 unsigned EltSize = 13395 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13396 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13397 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13398 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13399 13400 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13401 StackPtr, OffsetVal); 13402 13403 // Load the scalar. 13404 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13405 ScalarAddr, MachinePointerInfo(), 13406 false, false, false, 0); 13407 13408 // Replace the exact with the load. 13409 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13410 } 13411 13412 // The replacement was made in place; don't return anything. 13413 return SDValue(); 13414} 13415 13416/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13417/// nodes. 13418static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13419 TargetLowering::DAGCombinerInfo &DCI, 13420 const X86Subtarget *Subtarget) { 13421 13422 13423 DebugLoc DL = N->getDebugLoc(); 13424 SDValue Cond = N->getOperand(0); 13425 // Get the LHS/RHS of the select. 13426 SDValue LHS = N->getOperand(1); 13427 SDValue RHS = N->getOperand(2); 13428 EVT VT = LHS.getValueType(); 13429 13430 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13431 // instructions match the semantics of the common C idiom x<y?x:y but not 13432 // x<=y?x:y, because of how they handle negative zero (which can be 13433 // ignored in unsafe-math mode). 13434 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13435 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13436 (Subtarget->hasSSE2() || 13437 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13438 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13439 13440 unsigned Opcode = 0; 13441 // Check for x CC y ? x : y. 13442 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13443 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13444 switch (CC) { 13445 default: break; 13446 case ISD::SETULT: 13447 // Converting this to a min would handle NaNs incorrectly, and swapping 13448 // the operands would cause it to handle comparisons between positive 13449 // and negative zero incorrectly. 13450 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13451 if (!DAG.getTarget().Options.UnsafeFPMath && 13452 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13453 break; 13454 std::swap(LHS, RHS); 13455 } 13456 Opcode = X86ISD::FMIN; 13457 break; 13458 case ISD::SETOLE: 13459 // Converting this to a min would handle comparisons between positive 13460 // and negative zero incorrectly. 13461 if (!DAG.getTarget().Options.UnsafeFPMath && 13462 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13463 break; 13464 Opcode = X86ISD::FMIN; 13465 break; 13466 case ISD::SETULE: 13467 // Converting this to a min would handle both negative zeros and NaNs 13468 // incorrectly, but we can swap the operands to fix both. 13469 std::swap(LHS, RHS); 13470 case ISD::SETOLT: 13471 case ISD::SETLT: 13472 case ISD::SETLE: 13473 Opcode = X86ISD::FMIN; 13474 break; 13475 13476 case ISD::SETOGE: 13477 // Converting this to a max would handle comparisons between positive 13478 // and negative zero incorrectly. 13479 if (!DAG.getTarget().Options.UnsafeFPMath && 13480 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13481 break; 13482 Opcode = X86ISD::FMAX; 13483 break; 13484 case ISD::SETUGT: 13485 // Converting this to a max would handle NaNs incorrectly, and swapping 13486 // the operands would cause it to handle comparisons between positive 13487 // and negative zero incorrectly. 13488 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13489 if (!DAG.getTarget().Options.UnsafeFPMath && 13490 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13491 break; 13492 std::swap(LHS, RHS); 13493 } 13494 Opcode = X86ISD::FMAX; 13495 break; 13496 case ISD::SETUGE: 13497 // Converting this to a max would handle both negative zeros and NaNs 13498 // incorrectly, but we can swap the operands to fix both. 13499 std::swap(LHS, RHS); 13500 case ISD::SETOGT: 13501 case ISD::SETGT: 13502 case ISD::SETGE: 13503 Opcode = X86ISD::FMAX; 13504 break; 13505 } 13506 // Check for x CC y ? y : x -- a min/max with reversed arms. 13507 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13508 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13509 switch (CC) { 13510 default: break; 13511 case ISD::SETOGE: 13512 // Converting this to a min would handle comparisons between positive 13513 // and negative zero incorrectly, and swapping the operands would 13514 // cause it to handle NaNs incorrectly. 13515 if (!DAG.getTarget().Options.UnsafeFPMath && 13516 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13517 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13518 break; 13519 std::swap(LHS, RHS); 13520 } 13521 Opcode = X86ISD::FMIN; 13522 break; 13523 case ISD::SETUGT: 13524 // Converting this to a min would handle NaNs incorrectly. 13525 if (!DAG.getTarget().Options.UnsafeFPMath && 13526 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13527 break; 13528 Opcode = X86ISD::FMIN; 13529 break; 13530 case ISD::SETUGE: 13531 // Converting this to a min would handle both negative zeros and NaNs 13532 // incorrectly, but we can swap the operands to fix both. 13533 std::swap(LHS, RHS); 13534 case ISD::SETOGT: 13535 case ISD::SETGT: 13536 case ISD::SETGE: 13537 Opcode = X86ISD::FMIN; 13538 break; 13539 13540 case ISD::SETULT: 13541 // Converting this to a max would handle NaNs incorrectly. 13542 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13543 break; 13544 Opcode = X86ISD::FMAX; 13545 break; 13546 case ISD::SETOLE: 13547 // Converting this to a max would handle comparisons between positive 13548 // and negative zero incorrectly, and swapping the operands would 13549 // cause it to handle NaNs incorrectly. 13550 if (!DAG.getTarget().Options.UnsafeFPMath && 13551 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13552 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13553 break; 13554 std::swap(LHS, RHS); 13555 } 13556 Opcode = X86ISD::FMAX; 13557 break; 13558 case ISD::SETULE: 13559 // Converting this to a max would handle both negative zeros and NaNs 13560 // incorrectly, but we can swap the operands to fix both. 13561 std::swap(LHS, RHS); 13562 case ISD::SETOLT: 13563 case ISD::SETLT: 13564 case ISD::SETLE: 13565 Opcode = X86ISD::FMAX; 13566 break; 13567 } 13568 } 13569 13570 if (Opcode) 13571 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13572 } 13573 13574 // If this is a select between two integer constants, try to do some 13575 // optimizations. 13576 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13577 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13578 // Don't do this for crazy integer types. 13579 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13580 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13581 // so that TrueC (the true value) is larger than FalseC. 13582 bool NeedsCondInvert = false; 13583 13584 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13585 // Efficiently invertible. 13586 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13587 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13588 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13589 NeedsCondInvert = true; 13590 std::swap(TrueC, FalseC); 13591 } 13592 13593 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13594 if (FalseC->getAPIntValue() == 0 && 13595 TrueC->getAPIntValue().isPowerOf2()) { 13596 if (NeedsCondInvert) // Invert the condition if needed. 13597 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13598 DAG.getConstant(1, Cond.getValueType())); 13599 13600 // Zero extend the condition if needed. 13601 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13602 13603 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13604 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13605 DAG.getConstant(ShAmt, MVT::i8)); 13606 } 13607 13608 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13609 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13610 if (NeedsCondInvert) // Invert the condition if needed. 13611 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13612 DAG.getConstant(1, Cond.getValueType())); 13613 13614 // Zero extend the condition if needed. 13615 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13616 FalseC->getValueType(0), Cond); 13617 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13618 SDValue(FalseC, 0)); 13619 } 13620 13621 // Optimize cases that will turn into an LEA instruction. This requires 13622 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13623 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13624 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13625 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13626 13627 bool isFastMultiplier = false; 13628 if (Diff < 10) { 13629 switch ((unsigned char)Diff) { 13630 default: break; 13631 case 1: // result = add base, cond 13632 case 2: // result = lea base( , cond*2) 13633 case 3: // result = lea base(cond, cond*2) 13634 case 4: // result = lea base( , cond*4) 13635 case 5: // result = lea base(cond, cond*4) 13636 case 8: // result = lea base( , cond*8) 13637 case 9: // result = lea base(cond, cond*8) 13638 isFastMultiplier = true; 13639 break; 13640 } 13641 } 13642 13643 if (isFastMultiplier) { 13644 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13645 if (NeedsCondInvert) // Invert the condition if needed. 13646 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13647 DAG.getConstant(1, Cond.getValueType())); 13648 13649 // Zero extend the condition if needed. 13650 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13651 Cond); 13652 // Scale the condition by the difference. 13653 if (Diff != 1) 13654 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13655 DAG.getConstant(Diff, Cond.getValueType())); 13656 13657 // Add the base if non-zero. 13658 if (FalseC->getAPIntValue() != 0) 13659 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13660 SDValue(FalseC, 0)); 13661 return Cond; 13662 } 13663 } 13664 } 13665 } 13666 13667 // Canonicalize max and min: 13668 // (x > y) ? x : y -> (x >= y) ? x : y 13669 // (x < y) ? x : y -> (x <= y) ? x : y 13670 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13671 // the need for an extra compare 13672 // against zero. e.g. 13673 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13674 // subl %esi, %edi 13675 // testl %edi, %edi 13676 // movl $0, %eax 13677 // cmovgl %edi, %eax 13678 // => 13679 // xorl %eax, %eax 13680 // subl %esi, $edi 13681 // cmovsl %eax, %edi 13682 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13683 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13684 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13685 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13686 switch (CC) { 13687 default: break; 13688 case ISD::SETLT: 13689 case ISD::SETGT: { 13690 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13691 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13692 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13693 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13694 } 13695 } 13696 } 13697 13698 // If we know that this node is legal then we know that it is going to be 13699 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13700 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13701 // to simplify previous instructions. 13702 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13703 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13704 !DCI.isBeforeLegalize() && 13705 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13706 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13707 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13708 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13709 13710 APInt KnownZero, KnownOne; 13711 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13712 DCI.isBeforeLegalizeOps()); 13713 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13714 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13715 DCI.CommitTargetLoweringOpt(TLO); 13716 } 13717 13718 return SDValue(); 13719} 13720 13721/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13722static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13723 TargetLowering::DAGCombinerInfo &DCI) { 13724 DebugLoc DL = N->getDebugLoc(); 13725 13726 // If the flag operand isn't dead, don't touch this CMOV. 13727 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13728 return SDValue(); 13729 13730 SDValue FalseOp = N->getOperand(0); 13731 SDValue TrueOp = N->getOperand(1); 13732 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13733 SDValue Cond = N->getOperand(3); 13734 if (CC == X86::COND_E || CC == X86::COND_NE) { 13735 switch (Cond.getOpcode()) { 13736 default: break; 13737 case X86ISD::BSR: 13738 case X86ISD::BSF: 13739 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13740 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13741 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13742 } 13743 } 13744 13745 // If this is a select between two integer constants, try to do some 13746 // optimizations. Note that the operands are ordered the opposite of SELECT 13747 // operands. 13748 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13749 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13750 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13751 // larger than FalseC (the false value). 13752 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13753 CC = X86::GetOppositeBranchCondition(CC); 13754 std::swap(TrueC, FalseC); 13755 } 13756 13757 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13758 // This is efficient for any integer data type (including i8/i16) and 13759 // shift amount. 13760 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13761 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13762 DAG.getConstant(CC, MVT::i8), Cond); 13763 13764 // Zero extend the condition if needed. 13765 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13766 13767 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13768 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13769 DAG.getConstant(ShAmt, MVT::i8)); 13770 if (N->getNumValues() == 2) // Dead flag value? 13771 return DCI.CombineTo(N, Cond, SDValue()); 13772 return Cond; 13773 } 13774 13775 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13776 // for any integer data type, including i8/i16. 13777 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13778 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13779 DAG.getConstant(CC, MVT::i8), Cond); 13780 13781 // Zero extend the condition if needed. 13782 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13783 FalseC->getValueType(0), Cond); 13784 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13785 SDValue(FalseC, 0)); 13786 13787 if (N->getNumValues() == 2) // Dead flag value? 13788 return DCI.CombineTo(N, Cond, SDValue()); 13789 return Cond; 13790 } 13791 13792 // Optimize cases that will turn into an LEA instruction. This requires 13793 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13794 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13795 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13796 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13797 13798 bool isFastMultiplier = false; 13799 if (Diff < 10) { 13800 switch ((unsigned char)Diff) { 13801 default: break; 13802 case 1: // result = add base, cond 13803 case 2: // result = lea base( , cond*2) 13804 case 3: // result = lea base(cond, cond*2) 13805 case 4: // result = lea base( , cond*4) 13806 case 5: // result = lea base(cond, cond*4) 13807 case 8: // result = lea base( , cond*8) 13808 case 9: // result = lea base(cond, cond*8) 13809 isFastMultiplier = true; 13810 break; 13811 } 13812 } 13813 13814 if (isFastMultiplier) { 13815 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13816 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13817 DAG.getConstant(CC, MVT::i8), Cond); 13818 // Zero extend the condition if needed. 13819 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13820 Cond); 13821 // Scale the condition by the difference. 13822 if (Diff != 1) 13823 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13824 DAG.getConstant(Diff, Cond.getValueType())); 13825 13826 // Add the base if non-zero. 13827 if (FalseC->getAPIntValue() != 0) 13828 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13829 SDValue(FalseC, 0)); 13830 if (N->getNumValues() == 2) // Dead flag value? 13831 return DCI.CombineTo(N, Cond, SDValue()); 13832 return Cond; 13833 } 13834 } 13835 } 13836 } 13837 return SDValue(); 13838} 13839 13840 13841/// PerformMulCombine - Optimize a single multiply with constant into two 13842/// in order to implement it with two cheaper instructions, e.g. 13843/// LEA + SHL, LEA + LEA. 13844static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13845 TargetLowering::DAGCombinerInfo &DCI) { 13846 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13847 return SDValue(); 13848 13849 EVT VT = N->getValueType(0); 13850 if (VT != MVT::i64) 13851 return SDValue(); 13852 13853 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13854 if (!C) 13855 return SDValue(); 13856 uint64_t MulAmt = C->getZExtValue(); 13857 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13858 return SDValue(); 13859 13860 uint64_t MulAmt1 = 0; 13861 uint64_t MulAmt2 = 0; 13862 if ((MulAmt % 9) == 0) { 13863 MulAmt1 = 9; 13864 MulAmt2 = MulAmt / 9; 13865 } else if ((MulAmt % 5) == 0) { 13866 MulAmt1 = 5; 13867 MulAmt2 = MulAmt / 5; 13868 } else if ((MulAmt % 3) == 0) { 13869 MulAmt1 = 3; 13870 MulAmt2 = MulAmt / 3; 13871 } 13872 if (MulAmt2 && 13873 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13874 DebugLoc DL = N->getDebugLoc(); 13875 13876 if (isPowerOf2_64(MulAmt2) && 13877 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13878 // If second multiplifer is pow2, issue it first. We want the multiply by 13879 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13880 // is an add. 13881 std::swap(MulAmt1, MulAmt2); 13882 13883 SDValue NewMul; 13884 if (isPowerOf2_64(MulAmt1)) 13885 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13886 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13887 else 13888 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13889 DAG.getConstant(MulAmt1, VT)); 13890 13891 if (isPowerOf2_64(MulAmt2)) 13892 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13893 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13894 else 13895 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13896 DAG.getConstant(MulAmt2, VT)); 13897 13898 // Do not add new nodes to DAG combiner worklist. 13899 DCI.CombineTo(N, NewMul, false); 13900 } 13901 return SDValue(); 13902} 13903 13904static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13905 SDValue N0 = N->getOperand(0); 13906 SDValue N1 = N->getOperand(1); 13907 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13908 EVT VT = N0.getValueType(); 13909 13910 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13911 // since the result of setcc_c is all zero's or all ones. 13912 if (VT.isInteger() && !VT.isVector() && 13913 N1C && N0.getOpcode() == ISD::AND && 13914 N0.getOperand(1).getOpcode() == ISD::Constant) { 13915 SDValue N00 = N0.getOperand(0); 13916 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13917 ((N00.getOpcode() == ISD::ANY_EXTEND || 13918 N00.getOpcode() == ISD::ZERO_EXTEND) && 13919 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13920 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13921 APInt ShAmt = N1C->getAPIntValue(); 13922 Mask = Mask.shl(ShAmt); 13923 if (Mask != 0) 13924 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13925 N00, DAG.getConstant(Mask, VT)); 13926 } 13927 } 13928 13929 13930 // Hardware support for vector shifts is sparse which makes us scalarize the 13931 // vector operations in many cases. Also, on sandybridge ADD is faster than 13932 // shl. 13933 // (shl V, 1) -> add V,V 13934 if (isSplatVector(N1.getNode())) { 13935 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13936 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13937 // We shift all of the values by one. In many cases we do not have 13938 // hardware support for this operation. This is better expressed as an ADD 13939 // of two values. 13940 if (N1C && (1 == N1C->getZExtValue())) { 13941 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13942 } 13943 } 13944 13945 return SDValue(); 13946} 13947 13948/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13949/// when possible. 13950static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13951 TargetLowering::DAGCombinerInfo &DCI, 13952 const X86Subtarget *Subtarget) { 13953 EVT VT = N->getValueType(0); 13954 if (N->getOpcode() == ISD::SHL) { 13955 SDValue V = PerformSHLCombine(N, DAG); 13956 if (V.getNode()) return V; 13957 } 13958 13959 // On X86 with SSE2 support, we can transform this to a vector shift if 13960 // all elements are shifted by the same amount. We can't do this in legalize 13961 // because the a constant vector is typically transformed to a constant pool 13962 // so we have no knowledge of the shift amount. 13963 if (!Subtarget->hasSSE2()) 13964 return SDValue(); 13965 13966 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13967 (!Subtarget->hasAVX2() || 13968 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13969 return SDValue(); 13970 13971 SDValue ShAmtOp = N->getOperand(1); 13972 EVT EltVT = VT.getVectorElementType(); 13973 DebugLoc DL = N->getDebugLoc(); 13974 SDValue BaseShAmt = SDValue(); 13975 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13976 unsigned NumElts = VT.getVectorNumElements(); 13977 unsigned i = 0; 13978 for (; i != NumElts; ++i) { 13979 SDValue Arg = ShAmtOp.getOperand(i); 13980 if (Arg.getOpcode() == ISD::UNDEF) continue; 13981 BaseShAmt = Arg; 13982 break; 13983 } 13984 // Handle the case where the build_vector is all undef 13985 // FIXME: Should DAG allow this? 13986 if (i == NumElts) 13987 return SDValue(); 13988 13989 for (; i != NumElts; ++i) { 13990 SDValue Arg = ShAmtOp.getOperand(i); 13991 if (Arg.getOpcode() == ISD::UNDEF) continue; 13992 if (Arg != BaseShAmt) { 13993 return SDValue(); 13994 } 13995 } 13996 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13997 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13998 SDValue InVec = ShAmtOp.getOperand(0); 13999 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 14000 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 14001 unsigned i = 0; 14002 for (; i != NumElts; ++i) { 14003 SDValue Arg = InVec.getOperand(i); 14004 if (Arg.getOpcode() == ISD::UNDEF) continue; 14005 BaseShAmt = Arg; 14006 break; 14007 } 14008 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 14009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 14010 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 14011 if (C->getZExtValue() == SplatIdx) 14012 BaseShAmt = InVec.getOperand(1); 14013 } 14014 } 14015 if (BaseShAmt.getNode() == 0) { 14016 // Don't create instructions with illegal types after legalize 14017 // types has run. 14018 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 14019 !DCI.isBeforeLegalize()) 14020 return SDValue(); 14021 14022 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 14023 DAG.getIntPtrConstant(0)); 14024 } 14025 } else 14026 return SDValue(); 14027 14028 // The shift amount is an i32. 14029 if (EltVT.bitsGT(MVT::i32)) 14030 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 14031 else if (EltVT.bitsLT(MVT::i32)) 14032 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 14033 14034 // The shift amount is identical so we can do a vector shift. 14035 SDValue ValOp = N->getOperand(0); 14036 switch (N->getOpcode()) { 14037 default: 14038 llvm_unreachable("Unknown shift opcode!"); 14039 case ISD::SHL: 14040 switch (VT.getSimpleVT().SimpleTy) { 14041 default: return SDValue(); 14042 case MVT::v2i64: 14043 case MVT::v4i32: 14044 case MVT::v8i16: 14045 case MVT::v4i64: 14046 case MVT::v8i32: 14047 case MVT::v16i16: 14048 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 14049 } 14050 case ISD::SRA: 14051 switch (VT.getSimpleVT().SimpleTy) { 14052 default: return SDValue(); 14053 case MVT::v4i32: 14054 case MVT::v8i16: 14055 case MVT::v8i32: 14056 case MVT::v16i16: 14057 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 14058 } 14059 case ISD::SRL: 14060 switch (VT.getSimpleVT().SimpleTy) { 14061 default: return SDValue(); 14062 case MVT::v2i64: 14063 case MVT::v4i32: 14064 case MVT::v8i16: 14065 case MVT::v4i64: 14066 case MVT::v8i32: 14067 case MVT::v16i16: 14068 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 14069 } 14070 } 14071} 14072 14073 14074// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 14075// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 14076// and friends. Likewise for OR -> CMPNEQSS. 14077static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 14078 TargetLowering::DAGCombinerInfo &DCI, 14079 const X86Subtarget *Subtarget) { 14080 unsigned opcode; 14081 14082 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 14083 // we're requiring SSE2 for both. 14084 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 14085 SDValue N0 = N->getOperand(0); 14086 SDValue N1 = N->getOperand(1); 14087 SDValue CMP0 = N0->getOperand(1); 14088 SDValue CMP1 = N1->getOperand(1); 14089 DebugLoc DL = N->getDebugLoc(); 14090 14091 // The SETCCs should both refer to the same CMP. 14092 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 14093 return SDValue(); 14094 14095 SDValue CMP00 = CMP0->getOperand(0); 14096 SDValue CMP01 = CMP0->getOperand(1); 14097 EVT VT = CMP00.getValueType(); 14098 14099 if (VT == MVT::f32 || VT == MVT::f64) { 14100 bool ExpectingFlags = false; 14101 // Check for any users that want flags: 14102 for (SDNode::use_iterator UI = N->use_begin(), 14103 UE = N->use_end(); 14104 !ExpectingFlags && UI != UE; ++UI) 14105 switch (UI->getOpcode()) { 14106 default: 14107 case ISD::BR_CC: 14108 case ISD::BRCOND: 14109 case ISD::SELECT: 14110 ExpectingFlags = true; 14111 break; 14112 case ISD::CopyToReg: 14113 case ISD::SIGN_EXTEND: 14114 case ISD::ZERO_EXTEND: 14115 case ISD::ANY_EXTEND: 14116 break; 14117 } 14118 14119 if (!ExpectingFlags) { 14120 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 14121 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 14122 14123 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 14124 X86::CondCode tmp = cc0; 14125 cc0 = cc1; 14126 cc1 = tmp; 14127 } 14128 14129 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 14130 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 14131 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 14132 X86ISD::NodeType NTOperator = is64BitFP ? 14133 X86ISD::FSETCCsd : X86ISD::FSETCCss; 14134 // FIXME: need symbolic constants for these magic numbers. 14135 // See X86ATTInstPrinter.cpp:printSSECC(). 14136 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14137 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14138 DAG.getConstant(x86cc, MVT::i8)); 14139 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14140 OnesOrZeroesF); 14141 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14142 DAG.getConstant(1, MVT::i32)); 14143 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14144 return OneBitOfTruth; 14145 } 14146 } 14147 } 14148 } 14149 return SDValue(); 14150} 14151 14152/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14153/// so it can be folded inside ANDNP. 14154static bool CanFoldXORWithAllOnes(const SDNode *N) { 14155 EVT VT = N->getValueType(0); 14156 14157 // Match direct AllOnes for 128 and 256-bit vectors 14158 if (ISD::isBuildVectorAllOnes(N)) 14159 return true; 14160 14161 // Look through a bit convert. 14162 if (N->getOpcode() == ISD::BITCAST) 14163 N = N->getOperand(0).getNode(); 14164 14165 // Sometimes the operand may come from a insert_subvector building a 256-bit 14166 // allones vector 14167 if (VT.getSizeInBits() == 256 && 14168 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14169 SDValue V1 = N->getOperand(0); 14170 SDValue V2 = N->getOperand(1); 14171 14172 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14173 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14174 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14175 ISD::isBuildVectorAllOnes(V2.getNode())) 14176 return true; 14177 } 14178 14179 return false; 14180} 14181 14182static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14183 TargetLowering::DAGCombinerInfo &DCI, 14184 const X86Subtarget *Subtarget) { 14185 if (DCI.isBeforeLegalizeOps()) 14186 return SDValue(); 14187 14188 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14189 if (R.getNode()) 14190 return R; 14191 14192 EVT VT = N->getValueType(0); 14193 14194 // Create ANDN, BLSI, and BLSR instructions 14195 // BLSI is X & (-X) 14196 // BLSR is X & (X-1) 14197 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14198 SDValue N0 = N->getOperand(0); 14199 SDValue N1 = N->getOperand(1); 14200 DebugLoc DL = N->getDebugLoc(); 14201 14202 // Check LHS for not 14203 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14204 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14205 // Check RHS for not 14206 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14207 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14208 14209 // Check LHS for neg 14210 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14211 isZero(N0.getOperand(0))) 14212 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14213 14214 // Check RHS for neg 14215 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14216 isZero(N1.getOperand(0))) 14217 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14218 14219 // Check LHS for X-1 14220 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14221 isAllOnes(N0.getOperand(1))) 14222 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14223 14224 // Check RHS for X-1 14225 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14226 isAllOnes(N1.getOperand(1))) 14227 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14228 14229 return SDValue(); 14230 } 14231 14232 // Want to form ANDNP nodes: 14233 // 1) In the hopes of then easily combining them with OR and AND nodes 14234 // to form PBLEND/PSIGN. 14235 // 2) To match ANDN packed intrinsics 14236 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14237 return SDValue(); 14238 14239 SDValue N0 = N->getOperand(0); 14240 SDValue N1 = N->getOperand(1); 14241 DebugLoc DL = N->getDebugLoc(); 14242 14243 // Check LHS for vnot 14244 if (N0.getOpcode() == ISD::XOR && 14245 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14246 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14247 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14248 14249 // Check RHS for vnot 14250 if (N1.getOpcode() == ISD::XOR && 14251 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14252 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14253 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14254 14255 return SDValue(); 14256} 14257 14258static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14259 TargetLowering::DAGCombinerInfo &DCI, 14260 const X86Subtarget *Subtarget) { 14261 if (DCI.isBeforeLegalizeOps()) 14262 return SDValue(); 14263 14264 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14265 if (R.getNode()) 14266 return R; 14267 14268 EVT VT = N->getValueType(0); 14269 14270 SDValue N0 = N->getOperand(0); 14271 SDValue N1 = N->getOperand(1); 14272 14273 // look for psign/blend 14274 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14275 if (!Subtarget->hasSSSE3() || 14276 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14277 return SDValue(); 14278 14279 // Canonicalize pandn to RHS 14280 if (N0.getOpcode() == X86ISD::ANDNP) 14281 std::swap(N0, N1); 14282 // or (and (m, y), (pandn m, x)) 14283 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14284 SDValue Mask = N1.getOperand(0); 14285 SDValue X = N1.getOperand(1); 14286 SDValue Y; 14287 if (N0.getOperand(0) == Mask) 14288 Y = N0.getOperand(1); 14289 if (N0.getOperand(1) == Mask) 14290 Y = N0.getOperand(0); 14291 14292 // Check to see if the mask appeared in both the AND and ANDNP and 14293 if (!Y.getNode()) 14294 return SDValue(); 14295 14296 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14297 // Look through mask bitcast. 14298 if (Mask.getOpcode() == ISD::BITCAST) 14299 Mask = Mask.getOperand(0); 14300 if (X.getOpcode() == ISD::BITCAST) 14301 X = X.getOperand(0); 14302 if (Y.getOpcode() == ISD::BITCAST) 14303 Y = Y.getOperand(0); 14304 14305 EVT MaskVT = Mask.getValueType(); 14306 14307 // Validate that the Mask operand is a vector sra node. 14308 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14309 // there is no psrai.b 14310 if (Mask.getOpcode() != X86ISD::VSRAI) 14311 return SDValue(); 14312 14313 // Check that the SRA is all signbits. 14314 SDValue SraC = Mask.getOperand(1); 14315 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14316 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14317 if ((SraAmt + 1) != EltBits) 14318 return SDValue(); 14319 14320 DebugLoc DL = N->getDebugLoc(); 14321 14322 // Now we know we at least have a plendvb with the mask val. See if 14323 // we can form a psignb/w/d. 14324 // psign = x.type == y.type == mask.type && y = sub(0, x); 14325 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14326 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14327 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14328 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14329 "Unsupported VT for PSIGN"); 14330 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14331 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14332 } 14333 // PBLENDVB only available on SSE 4.1 14334 if (!Subtarget->hasSSE41()) 14335 return SDValue(); 14336 14337 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14338 14339 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14340 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14341 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14342 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14343 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14344 } 14345 } 14346 14347 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14348 return SDValue(); 14349 14350 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14351 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14352 std::swap(N0, N1); 14353 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14354 return SDValue(); 14355 if (!N0.hasOneUse() || !N1.hasOneUse()) 14356 return SDValue(); 14357 14358 SDValue ShAmt0 = N0.getOperand(1); 14359 if (ShAmt0.getValueType() != MVT::i8) 14360 return SDValue(); 14361 SDValue ShAmt1 = N1.getOperand(1); 14362 if (ShAmt1.getValueType() != MVT::i8) 14363 return SDValue(); 14364 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14365 ShAmt0 = ShAmt0.getOperand(0); 14366 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14367 ShAmt1 = ShAmt1.getOperand(0); 14368 14369 DebugLoc DL = N->getDebugLoc(); 14370 unsigned Opc = X86ISD::SHLD; 14371 SDValue Op0 = N0.getOperand(0); 14372 SDValue Op1 = N1.getOperand(0); 14373 if (ShAmt0.getOpcode() == ISD::SUB) { 14374 Opc = X86ISD::SHRD; 14375 std::swap(Op0, Op1); 14376 std::swap(ShAmt0, ShAmt1); 14377 } 14378 14379 unsigned Bits = VT.getSizeInBits(); 14380 if (ShAmt1.getOpcode() == ISD::SUB) { 14381 SDValue Sum = ShAmt1.getOperand(0); 14382 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14383 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14384 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14385 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14386 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14387 return DAG.getNode(Opc, DL, VT, 14388 Op0, Op1, 14389 DAG.getNode(ISD::TRUNCATE, DL, 14390 MVT::i8, ShAmt0)); 14391 } 14392 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14393 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14394 if (ShAmt0C && 14395 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14396 return DAG.getNode(Opc, DL, VT, 14397 N0.getOperand(0), N1.getOperand(0), 14398 DAG.getNode(ISD::TRUNCATE, DL, 14399 MVT::i8, ShAmt0)); 14400 } 14401 14402 return SDValue(); 14403} 14404 14405// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14406static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14407 TargetLowering::DAGCombinerInfo &DCI, 14408 const X86Subtarget *Subtarget) { 14409 if (DCI.isBeforeLegalizeOps()) 14410 return SDValue(); 14411 14412 EVT VT = N->getValueType(0); 14413 14414 if (VT != MVT::i32 && VT != MVT::i64) 14415 return SDValue(); 14416 14417 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14418 14419 // Create BLSMSK instructions by finding X ^ (X-1) 14420 SDValue N0 = N->getOperand(0); 14421 SDValue N1 = N->getOperand(1); 14422 DebugLoc DL = N->getDebugLoc(); 14423 14424 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14425 isAllOnes(N0.getOperand(1))) 14426 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14427 14428 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14429 isAllOnes(N1.getOperand(1))) 14430 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14431 14432 return SDValue(); 14433} 14434 14435/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14436static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14437 const X86Subtarget *Subtarget) { 14438 LoadSDNode *Ld = cast<LoadSDNode>(N); 14439 EVT RegVT = Ld->getValueType(0); 14440 EVT MemVT = Ld->getMemoryVT(); 14441 DebugLoc dl = Ld->getDebugLoc(); 14442 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14443 14444 ISD::LoadExtType Ext = Ld->getExtensionType(); 14445 14446 // If this is a vector EXT Load then attempt to optimize it using a 14447 // shuffle. We need SSE4 for the shuffles. 14448 // TODO: It is possible to support ZExt by zeroing the undef values 14449 // during the shuffle phase or after the shuffle. 14450 if (RegVT.isVector() && RegVT.isInteger() && 14451 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14452 assert(MemVT != RegVT && "Cannot extend to the same type"); 14453 assert(MemVT.isVector() && "Must load a vector from memory"); 14454 14455 unsigned NumElems = RegVT.getVectorNumElements(); 14456 unsigned RegSz = RegVT.getSizeInBits(); 14457 unsigned MemSz = MemVT.getSizeInBits(); 14458 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14459 // All sizes must be a power of two 14460 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14461 14462 // Attempt to load the original value using a single load op. 14463 // Find a scalar type which is equal to the loaded word size. 14464 MVT SclrLoadTy = MVT::i8; 14465 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14466 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14467 MVT Tp = (MVT::SimpleValueType)tp; 14468 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14469 SclrLoadTy = Tp; 14470 break; 14471 } 14472 } 14473 14474 // Proceed if a load word is found. 14475 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14476 14477 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14478 RegSz/SclrLoadTy.getSizeInBits()); 14479 14480 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14481 RegSz/MemVT.getScalarType().getSizeInBits()); 14482 // Can't shuffle using an illegal type. 14483 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14484 14485 // Perform a single load. 14486 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14487 Ld->getBasePtr(), 14488 Ld->getPointerInfo(), Ld->isVolatile(), 14489 Ld->isNonTemporal(), Ld->isInvariant(), 14490 Ld->getAlignment()); 14491 14492 // Insert the word loaded into a vector. 14493 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14494 LoadUnitVecVT, ScalarLoad); 14495 14496 // Bitcast the loaded value to a vector of the original element type, in 14497 // the size of the target vector type. 14498 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14499 ScalarInVector); 14500 unsigned SizeRatio = RegSz/MemSz; 14501 14502 // Redistribute the loaded elements into the different locations. 14503 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14504 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14505 14506 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14507 DAG.getUNDEF(WideVecVT), 14508 &ShuffleVec[0]); 14509 14510 // Bitcast to the requested type. 14511 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14512 // Replace the original load with the new sequence 14513 // and return the new chain. 14514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14515 return SDValue(ScalarLoad.getNode(), 1); 14516 } 14517 14518 return SDValue(); 14519} 14520 14521/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14522static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14523 const X86Subtarget *Subtarget) { 14524 StoreSDNode *St = cast<StoreSDNode>(N); 14525 EVT VT = St->getValue().getValueType(); 14526 EVT StVT = St->getMemoryVT(); 14527 DebugLoc dl = St->getDebugLoc(); 14528 SDValue StoredVal = St->getOperand(1); 14529 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14530 14531 // If we are saving a concatenation of two XMM registers, perform two stores. 14532 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14533 // 128-bit ones. If in the future the cost becomes only one memory access the 14534 // first version would be better. 14535 if (VT.getSizeInBits() == 256 && 14536 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14537 StoredVal.getNumOperands() == 2) { 14538 14539 SDValue Value0 = StoredVal.getOperand(0); 14540 SDValue Value1 = StoredVal.getOperand(1); 14541 14542 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14543 SDValue Ptr0 = St->getBasePtr(); 14544 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14545 14546 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14547 St->getPointerInfo(), St->isVolatile(), 14548 St->isNonTemporal(), St->getAlignment()); 14549 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14550 St->getPointerInfo(), St->isVolatile(), 14551 St->isNonTemporal(), St->getAlignment()); 14552 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14553 } 14554 14555 // Optimize trunc store (of multiple scalars) to shuffle and store. 14556 // First, pack all of the elements in one place. Next, store to memory 14557 // in fewer chunks. 14558 if (St->isTruncatingStore() && VT.isVector()) { 14559 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14560 unsigned NumElems = VT.getVectorNumElements(); 14561 assert(StVT != VT && "Cannot truncate to the same type"); 14562 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14563 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14564 14565 // From, To sizes and ElemCount must be pow of two 14566 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14567 // We are going to use the original vector elt for storing. 14568 // Accumulated smaller vector elements must be a multiple of the store size. 14569 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14570 14571 unsigned SizeRatio = FromSz / ToSz; 14572 14573 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14574 14575 // Create a type on which we perform the shuffle 14576 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14577 StVT.getScalarType(), NumElems*SizeRatio); 14578 14579 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14580 14581 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14582 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14583 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14584 14585 // Can't shuffle using an illegal type 14586 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14587 14588 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14589 DAG.getUNDEF(WideVecVT), 14590 &ShuffleVec[0]); 14591 // At this point all of the data is stored at the bottom of the 14592 // register. We now need to save it to mem. 14593 14594 // Find the largest store unit 14595 MVT StoreType = MVT::i8; 14596 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14597 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14598 MVT Tp = (MVT::SimpleValueType)tp; 14599 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14600 StoreType = Tp; 14601 } 14602 14603 // Bitcast the original vector into a vector of store-size units 14604 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14605 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14606 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14607 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14608 SmallVector<SDValue, 8> Chains; 14609 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14610 TLI.getPointerTy()); 14611 SDValue Ptr = St->getBasePtr(); 14612 14613 // Perform one or more big stores into memory. 14614 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14615 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14616 StoreType, ShuffWide, 14617 DAG.getIntPtrConstant(i)); 14618 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14619 St->getPointerInfo(), St->isVolatile(), 14620 St->isNonTemporal(), St->getAlignment()); 14621 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14622 Chains.push_back(Ch); 14623 } 14624 14625 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14626 Chains.size()); 14627 } 14628 14629 14630 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14631 // the FP state in cases where an emms may be missing. 14632 // A preferable solution to the general problem is to figure out the right 14633 // places to insert EMMS. This qualifies as a quick hack. 14634 14635 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14636 if (VT.getSizeInBits() != 64) 14637 return SDValue(); 14638 14639 const Function *F = DAG.getMachineFunction().getFunction(); 14640 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14641 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14642 && Subtarget->hasSSE2(); 14643 if ((VT.isVector() || 14644 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14645 isa<LoadSDNode>(St->getValue()) && 14646 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14647 St->getChain().hasOneUse() && !St->isVolatile()) { 14648 SDNode* LdVal = St->getValue().getNode(); 14649 LoadSDNode *Ld = 0; 14650 int TokenFactorIndex = -1; 14651 SmallVector<SDValue, 8> Ops; 14652 SDNode* ChainVal = St->getChain().getNode(); 14653 // Must be a store of a load. We currently handle two cases: the load 14654 // is a direct child, and it's under an intervening TokenFactor. It is 14655 // possible to dig deeper under nested TokenFactors. 14656 if (ChainVal == LdVal) 14657 Ld = cast<LoadSDNode>(St->getChain()); 14658 else if (St->getValue().hasOneUse() && 14659 ChainVal->getOpcode() == ISD::TokenFactor) { 14660 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14661 if (ChainVal->getOperand(i).getNode() == LdVal) { 14662 TokenFactorIndex = i; 14663 Ld = cast<LoadSDNode>(St->getValue()); 14664 } else 14665 Ops.push_back(ChainVal->getOperand(i)); 14666 } 14667 } 14668 14669 if (!Ld || !ISD::isNormalLoad(Ld)) 14670 return SDValue(); 14671 14672 // If this is not the MMX case, i.e. we are just turning i64 load/store 14673 // into f64 load/store, avoid the transformation if there are multiple 14674 // uses of the loaded value. 14675 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14676 return SDValue(); 14677 14678 DebugLoc LdDL = Ld->getDebugLoc(); 14679 DebugLoc StDL = N->getDebugLoc(); 14680 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14681 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14682 // pair instead. 14683 if (Subtarget->is64Bit() || F64IsLegal) { 14684 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14685 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14686 Ld->getPointerInfo(), Ld->isVolatile(), 14687 Ld->isNonTemporal(), Ld->isInvariant(), 14688 Ld->getAlignment()); 14689 SDValue NewChain = NewLd.getValue(1); 14690 if (TokenFactorIndex != -1) { 14691 Ops.push_back(NewChain); 14692 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14693 Ops.size()); 14694 } 14695 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14696 St->getPointerInfo(), 14697 St->isVolatile(), St->isNonTemporal(), 14698 St->getAlignment()); 14699 } 14700 14701 // Otherwise, lower to two pairs of 32-bit loads / stores. 14702 SDValue LoAddr = Ld->getBasePtr(); 14703 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14704 DAG.getConstant(4, MVT::i32)); 14705 14706 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14707 Ld->getPointerInfo(), 14708 Ld->isVolatile(), Ld->isNonTemporal(), 14709 Ld->isInvariant(), Ld->getAlignment()); 14710 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14711 Ld->getPointerInfo().getWithOffset(4), 14712 Ld->isVolatile(), Ld->isNonTemporal(), 14713 Ld->isInvariant(), 14714 MinAlign(Ld->getAlignment(), 4)); 14715 14716 SDValue NewChain = LoLd.getValue(1); 14717 if (TokenFactorIndex != -1) { 14718 Ops.push_back(LoLd); 14719 Ops.push_back(HiLd); 14720 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14721 Ops.size()); 14722 } 14723 14724 LoAddr = St->getBasePtr(); 14725 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14726 DAG.getConstant(4, MVT::i32)); 14727 14728 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14729 St->getPointerInfo(), 14730 St->isVolatile(), St->isNonTemporal(), 14731 St->getAlignment()); 14732 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14733 St->getPointerInfo().getWithOffset(4), 14734 St->isVolatile(), 14735 St->isNonTemporal(), 14736 MinAlign(St->getAlignment(), 4)); 14737 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14738 } 14739 return SDValue(); 14740} 14741 14742/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14743/// and return the operands for the horizontal operation in LHS and RHS. A 14744/// horizontal operation performs the binary operation on successive elements 14745/// of its first operand, then on successive elements of its second operand, 14746/// returning the resulting values in a vector. For example, if 14747/// A = < float a0, float a1, float a2, float a3 > 14748/// and 14749/// B = < float b0, float b1, float b2, float b3 > 14750/// then the result of doing a horizontal operation on A and B is 14751/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14752/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14753/// A horizontal-op B, for some already available A and B, and if so then LHS is 14754/// set to A, RHS to B, and the routine returns 'true'. 14755/// Note that the binary operation should have the property that if one of the 14756/// operands is UNDEF then the result is UNDEF. 14757static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14758 // Look for the following pattern: if 14759 // A = < float a0, float a1, float a2, float a3 > 14760 // B = < float b0, float b1, float b2, float b3 > 14761 // and 14762 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14763 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14764 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14765 // which is A horizontal-op B. 14766 14767 // At least one of the operands should be a vector shuffle. 14768 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14769 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14770 return false; 14771 14772 EVT VT = LHS.getValueType(); 14773 14774 assert((VT.is128BitVector() || VT.is256BitVector()) && 14775 "Unsupported vector type for horizontal add/sub"); 14776 14777 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14778 // operate independently on 128-bit lanes. 14779 unsigned NumElts = VT.getVectorNumElements(); 14780 unsigned NumLanes = VT.getSizeInBits()/128; 14781 unsigned NumLaneElts = NumElts / NumLanes; 14782 assert((NumLaneElts % 2 == 0) && 14783 "Vector type should have an even number of elements in each lane"); 14784 unsigned HalfLaneElts = NumLaneElts/2; 14785 14786 // View LHS in the form 14787 // LHS = VECTOR_SHUFFLE A, B, LMask 14788 // If LHS is not a shuffle then pretend it is the shuffle 14789 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14790 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14791 // type VT. 14792 SDValue A, B; 14793 SmallVector<int, 16> LMask(NumElts); 14794 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14795 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14796 A = LHS.getOperand(0); 14797 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14798 B = LHS.getOperand(1); 14799 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14800 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14801 } else { 14802 if (LHS.getOpcode() != ISD::UNDEF) 14803 A = LHS; 14804 for (unsigned i = 0; i != NumElts; ++i) 14805 LMask[i] = i; 14806 } 14807 14808 // Likewise, view RHS in the form 14809 // RHS = VECTOR_SHUFFLE C, D, RMask 14810 SDValue C, D; 14811 SmallVector<int, 16> RMask(NumElts); 14812 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14813 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14814 C = RHS.getOperand(0); 14815 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14816 D = RHS.getOperand(1); 14817 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14818 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14819 } else { 14820 if (RHS.getOpcode() != ISD::UNDEF) 14821 C = RHS; 14822 for (unsigned i = 0; i != NumElts; ++i) 14823 RMask[i] = i; 14824 } 14825 14826 // Check that the shuffles are both shuffling the same vectors. 14827 if (!(A == C && B == D) && !(A == D && B == C)) 14828 return false; 14829 14830 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14831 if (!A.getNode() && !B.getNode()) 14832 return false; 14833 14834 // If A and B occur in reverse order in RHS, then "swap" them (which means 14835 // rewriting the mask). 14836 if (A != C) 14837 CommuteVectorShuffleMask(RMask, NumElts); 14838 14839 // At this point LHS and RHS are equivalent to 14840 // LHS = VECTOR_SHUFFLE A, B, LMask 14841 // RHS = VECTOR_SHUFFLE A, B, RMask 14842 // Check that the masks correspond to performing a horizontal operation. 14843 for (unsigned i = 0; i != NumElts; ++i) { 14844 int LIdx = LMask[i], RIdx = RMask[i]; 14845 14846 // Ignore any UNDEF components. 14847 if (LIdx < 0 || RIdx < 0 || 14848 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14849 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14850 continue; 14851 14852 // Check that successive elements are being operated on. If not, this is 14853 // not a horizontal operation. 14854 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14855 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14856 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14857 if (!(LIdx == Index && RIdx == Index + 1) && 14858 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14859 return false; 14860 } 14861 14862 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14863 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14864 return true; 14865} 14866 14867/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14868static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14869 const X86Subtarget *Subtarget) { 14870 EVT VT = N->getValueType(0); 14871 SDValue LHS = N->getOperand(0); 14872 SDValue RHS = N->getOperand(1); 14873 14874 // Try to synthesize horizontal adds from adds of shuffles. 14875 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14876 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14877 isHorizontalBinOp(LHS, RHS, true)) 14878 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14879 return SDValue(); 14880} 14881 14882/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14883static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14884 const X86Subtarget *Subtarget) { 14885 EVT VT = N->getValueType(0); 14886 SDValue LHS = N->getOperand(0); 14887 SDValue RHS = N->getOperand(1); 14888 14889 // Try to synthesize horizontal subs from subs of shuffles. 14890 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14891 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14892 isHorizontalBinOp(LHS, RHS, false)) 14893 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14894 return SDValue(); 14895} 14896 14897/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14898/// X86ISD::FXOR nodes. 14899static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14900 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14901 // F[X]OR(0.0, x) -> x 14902 // F[X]OR(x, 0.0) -> x 14903 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14904 if (C->getValueAPF().isPosZero()) 14905 return N->getOperand(1); 14906 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14907 if (C->getValueAPF().isPosZero()) 14908 return N->getOperand(0); 14909 return SDValue(); 14910} 14911 14912/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14913static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14914 // FAND(0.0, x) -> 0.0 14915 // FAND(x, 0.0) -> 0.0 14916 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14917 if (C->getValueAPF().isPosZero()) 14918 return N->getOperand(0); 14919 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14920 if (C->getValueAPF().isPosZero()) 14921 return N->getOperand(1); 14922 return SDValue(); 14923} 14924 14925static SDValue PerformBTCombine(SDNode *N, 14926 SelectionDAG &DAG, 14927 TargetLowering::DAGCombinerInfo &DCI) { 14928 // BT ignores high bits in the bit index operand. 14929 SDValue Op1 = N->getOperand(1); 14930 if (Op1.hasOneUse()) { 14931 unsigned BitWidth = Op1.getValueSizeInBits(); 14932 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14933 APInt KnownZero, KnownOne; 14934 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14935 !DCI.isBeforeLegalizeOps()); 14936 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14937 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14938 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14939 DCI.CommitTargetLoweringOpt(TLO); 14940 } 14941 return SDValue(); 14942} 14943 14944static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14945 SDValue Op = N->getOperand(0); 14946 if (Op.getOpcode() == ISD::BITCAST) 14947 Op = Op.getOperand(0); 14948 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14949 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14950 VT.getVectorElementType().getSizeInBits() == 14951 OpVT.getVectorElementType().getSizeInBits()) { 14952 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14953 } 14954 return SDValue(); 14955} 14956 14957static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14958 TargetLowering::DAGCombinerInfo &DCI, 14959 const X86Subtarget *Subtarget) { 14960 if (!DCI.isBeforeLegalizeOps()) 14961 return SDValue(); 14962 14963 if (!Subtarget->hasAVX()) 14964 return SDValue(); 14965 14966 EVT VT = N->getValueType(0); 14967 SDValue Op = N->getOperand(0); 14968 EVT OpVT = Op.getValueType(); 14969 DebugLoc dl = N->getDebugLoc(); 14970 14971 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14972 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14973 14974 if (Subtarget->hasAVX2()) 14975 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); 14976 14977 // Optimize vectors in AVX mode 14978 // Sign extend v8i16 to v8i32 and 14979 // v4i32 to v4i64 14980 // 14981 // Divide input vector into two parts 14982 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14983 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14984 // concat the vectors to original VT 14985 14986 unsigned NumElems = OpVT.getVectorNumElements(); 14987 SmallVector<int,8> ShufMask1(NumElems, -1); 14988 for (unsigned i = 0; i != NumElems/2; ++i) 14989 ShufMask1[i] = i; 14990 14991 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14992 &ShufMask1[0]); 14993 14994 SmallVector<int,8> ShufMask2(NumElems, -1); 14995 for (unsigned i = 0; i != NumElems/2; ++i) 14996 ShufMask2[i] = i + NumElems/2; 14997 14998 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14999 &ShufMask2[0]); 15000 15001 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 15002 VT.getVectorNumElements()/2); 15003 15004 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 15005 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 15006 15007 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15008 } 15009 return SDValue(); 15010} 15011 15012static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 15013 TargetLowering::DAGCombinerInfo &DCI, 15014 const X86Subtarget *Subtarget) { 15015 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 15016 // (and (i32 x86isd::setcc_carry), 1) 15017 // This eliminates the zext. This transformation is necessary because 15018 // ISD::SETCC is always legalized to i8. 15019 DebugLoc dl = N->getDebugLoc(); 15020 SDValue N0 = N->getOperand(0); 15021 EVT VT = N->getValueType(0); 15022 EVT OpVT = N0.getValueType(); 15023 15024 if (N0.getOpcode() == ISD::AND && 15025 N0.hasOneUse() && 15026 N0.getOperand(0).hasOneUse()) { 15027 SDValue N00 = N0.getOperand(0); 15028 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 15029 return SDValue(); 15030 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 15031 if (!C || C->getZExtValue() != 1) 15032 return SDValue(); 15033 return DAG.getNode(ISD::AND, dl, VT, 15034 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 15035 N00.getOperand(0), N00.getOperand(1)), 15036 DAG.getConstant(1, VT)); 15037 } 15038 15039 // Optimize vectors in AVX mode: 15040 // 15041 // v8i16 -> v8i32 15042 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 15043 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 15044 // Concat upper and lower parts. 15045 // 15046 // v4i32 -> v4i64 15047 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 15048 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 15049 // Concat upper and lower parts. 15050 // 15051 if (!DCI.isBeforeLegalizeOps()) 15052 return SDValue(); 15053 15054 if (!Subtarget->hasAVX()) 15055 return SDValue(); 15056 15057 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 15058 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 15059 15060 if (Subtarget->hasAVX2()) 15061 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0); 15062 15063 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 15064 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec); 15065 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec); 15066 15067 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 15068 VT.getVectorNumElements()/2); 15069 15070 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 15071 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 15072 15073 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15074 } 15075 15076 return SDValue(); 15077} 15078 15079// Optimize x == -y --> x+y == 0 15080// x != -y --> x+y != 0 15081static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15082 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 15083 SDValue LHS = N->getOperand(0); 15084 SDValue RHS = N->getOperand(1); 15085 15086 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 15087 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 15088 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 15089 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15090 LHS.getValueType(), RHS, LHS.getOperand(1)); 15091 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15092 addV, DAG.getConstant(0, addV.getValueType()), CC); 15093 } 15094 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 15095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 15096 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 15097 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15098 RHS.getValueType(), LHS, RHS.getOperand(1)); 15099 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15100 addV, DAG.getConstant(0, addV.getValueType()), CC); 15101 } 15102 return SDValue(); 15103} 15104 15105// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 15106static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15107 unsigned X86CC = N->getConstantOperandVal(0); 15108 SDValue EFLAG = N->getOperand(1); 15109 DebugLoc DL = N->getDebugLoc(); 15110 15111 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 15112 // a zext and produces an all-ones bit which is more useful than 0/1 in some 15113 // cases. 15114 if (X86CC == X86::COND_B) 15115 return DAG.getNode(ISD::AND, DL, MVT::i8, 15116 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 15117 DAG.getConstant(X86CC, MVT::i8), EFLAG), 15118 DAG.getConstant(1, MVT::i8)); 15119 15120 return SDValue(); 15121} 15122 15123static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) { 15124 SDValue Op0 = N->getOperand(0); 15125 EVT InVT = Op0->getValueType(0); 15126 15127 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15128 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15129 DebugLoc dl = N->getDebugLoc(); 15130 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15131 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); 15132 // Notice that we use SINT_TO_FP because we know that the high bits 15133 // are zero and SINT_TO_FP is better supported by the hardware. 15134 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15135 } 15136 15137 return SDValue(); 15138} 15139 15140static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 15141 const X86TargetLowering *XTLI) { 15142 SDValue Op0 = N->getOperand(0); 15143 EVT InVT = Op0->getValueType(0); 15144 15145 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15146 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15147 DebugLoc dl = N->getDebugLoc(); 15148 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15149 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 15150 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15151 } 15152 15153 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 15154 // a 32-bit target where SSE doesn't support i64->FP operations. 15155 if (Op0.getOpcode() == ISD::LOAD) { 15156 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 15157 EVT VT = Ld->getValueType(0); 15158 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 15159 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 15160 !XTLI->getSubtarget()->is64Bit() && 15161 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 15162 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 15163 Ld->getChain(), Op0, DAG); 15164 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 15165 return FILDChain; 15166 } 15167 } 15168 return SDValue(); 15169} 15170 15171static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) { 15172 EVT VT = N->getValueType(0); 15173 15174 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() 15175 if (VT == MVT::v8i8 || VT == MVT::v4i8) { 15176 DebugLoc dl = N->getDebugLoc(); 15177 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15178 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); 15179 return DAG.getNode(ISD::TRUNCATE, dl, VT, I); 15180 } 15181 15182 return SDValue(); 15183} 15184 15185// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 15186static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 15187 X86TargetLowering::DAGCombinerInfo &DCI) { 15188 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 15189 // the result is either zero or one (depending on the input carry bit). 15190 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 15191 if (X86::isZeroNode(N->getOperand(0)) && 15192 X86::isZeroNode(N->getOperand(1)) && 15193 // We don't have a good way to replace an EFLAGS use, so only do this when 15194 // dead right now. 15195 SDValue(N, 1).use_empty()) { 15196 DebugLoc DL = N->getDebugLoc(); 15197 EVT VT = N->getValueType(0); 15198 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 15199 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 15200 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 15201 DAG.getConstant(X86::COND_B,MVT::i8), 15202 N->getOperand(2)), 15203 DAG.getConstant(1, VT)); 15204 return DCI.CombineTo(N, Res1, CarryOut); 15205 } 15206 15207 return SDValue(); 15208} 15209 15210// fold (add Y, (sete X, 0)) -> adc 0, Y 15211// (add Y, (setne X, 0)) -> sbb -1, Y 15212// (sub (sete X, 0), Y) -> sbb 0, Y 15213// (sub (setne X, 0), Y) -> adc -1, Y 15214static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 15215 DebugLoc DL = N->getDebugLoc(); 15216 15217 // Look through ZExts. 15218 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 15219 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 15220 return SDValue(); 15221 15222 SDValue SetCC = Ext.getOperand(0); 15223 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 15224 return SDValue(); 15225 15226 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 15227 if (CC != X86::COND_E && CC != X86::COND_NE) 15228 return SDValue(); 15229 15230 SDValue Cmp = SetCC.getOperand(1); 15231 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 15232 !X86::isZeroNode(Cmp.getOperand(1)) || 15233 !Cmp.getOperand(0).getValueType().isInteger()) 15234 return SDValue(); 15235 15236 SDValue CmpOp0 = Cmp.getOperand(0); 15237 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 15238 DAG.getConstant(1, CmpOp0.getValueType())); 15239 15240 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 15241 if (CC == X86::COND_NE) 15242 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 15243 DL, OtherVal.getValueType(), OtherVal, 15244 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 15245 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 15246 DL, OtherVal.getValueType(), OtherVal, 15247 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 15248} 15249 15250/// PerformADDCombine - Do target-specific dag combines on integer adds. 15251static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 15252 const X86Subtarget *Subtarget) { 15253 EVT VT = N->getValueType(0); 15254 SDValue Op0 = N->getOperand(0); 15255 SDValue Op1 = N->getOperand(1); 15256 15257 // Try to synthesize horizontal adds from adds of shuffles. 15258 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15259 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15260 isHorizontalBinOp(Op0, Op1, true)) 15261 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 15262 15263 return OptimizeConditionalInDecrement(N, DAG); 15264} 15265 15266static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 15267 const X86Subtarget *Subtarget) { 15268 SDValue Op0 = N->getOperand(0); 15269 SDValue Op1 = N->getOperand(1); 15270 15271 // X86 can't encode an immediate LHS of a sub. See if we can push the 15272 // negation into a preceding instruction. 15273 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 15274 // If the RHS of the sub is a XOR with one use and a constant, invert the 15275 // immediate. Then add one to the LHS of the sub so we can turn 15276 // X-Y -> X+~Y+1, saving one register. 15277 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 15278 isa<ConstantSDNode>(Op1.getOperand(1))) { 15279 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 15280 EVT VT = Op0.getValueType(); 15281 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 15282 Op1.getOperand(0), 15283 DAG.getConstant(~XorC, VT)); 15284 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 15285 DAG.getConstant(C->getAPIntValue()+1, VT)); 15286 } 15287 } 15288 15289 // Try to synthesize horizontal adds from adds of shuffles. 15290 EVT VT = N->getValueType(0); 15291 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15292 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15293 isHorizontalBinOp(Op0, Op1, true)) 15294 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15295 15296 return OptimizeConditionalInDecrement(N, DAG); 15297} 15298 15299SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15300 DAGCombinerInfo &DCI) const { 15301 SelectionDAG &DAG = DCI.DAG; 15302 switch (N->getOpcode()) { 15303 default: break; 15304 case ISD::EXTRACT_VECTOR_ELT: 15305 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15306 case ISD::VSELECT: 15307 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15308 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15309 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15310 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15311 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15312 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15313 case ISD::SHL: 15314 case ISD::SRA: 15315 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15316 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15317 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15318 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15319 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15320 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15321 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG); 15322 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15323 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG); 15324 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15325 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15326 case X86ISD::FXOR: 15327 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15328 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15329 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15330 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15331 case ISD::ANY_EXTEND: 15332 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 15333 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15334 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15335 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 15336 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15337 case X86ISD::SHUFP: // Handle all target specific shuffles 15338 case X86ISD::PALIGN: 15339 case X86ISD::UNPCKH: 15340 case X86ISD::UNPCKL: 15341 case X86ISD::MOVHLPS: 15342 case X86ISD::MOVLHPS: 15343 case X86ISD::PSHUFD: 15344 case X86ISD::PSHUFHW: 15345 case X86ISD::PSHUFLW: 15346 case X86ISD::MOVSS: 15347 case X86ISD::MOVSD: 15348 case X86ISD::VPERMILP: 15349 case X86ISD::VPERM2X128: 15350 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15351 } 15352 15353 return SDValue(); 15354} 15355 15356/// isTypeDesirableForOp - Return true if the target has native support for 15357/// the specified value type and it is 'desirable' to use the type for the 15358/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15359/// instruction encodings are longer and some i16 instructions are slow. 15360bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15361 if (!isTypeLegal(VT)) 15362 return false; 15363 if (VT != MVT::i16) 15364 return true; 15365 15366 switch (Opc) { 15367 default: 15368 return true; 15369 case ISD::LOAD: 15370 case ISD::SIGN_EXTEND: 15371 case ISD::ZERO_EXTEND: 15372 case ISD::ANY_EXTEND: 15373 case ISD::SHL: 15374 case ISD::SRL: 15375 case ISD::SUB: 15376 case ISD::ADD: 15377 case ISD::MUL: 15378 case ISD::AND: 15379 case ISD::OR: 15380 case ISD::XOR: 15381 return false; 15382 } 15383} 15384 15385/// IsDesirableToPromoteOp - This method query the target whether it is 15386/// beneficial for dag combiner to promote the specified node. If true, it 15387/// should return the desired promotion type by reference. 15388bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15389 EVT VT = Op.getValueType(); 15390 if (VT != MVT::i16) 15391 return false; 15392 15393 bool Promote = false; 15394 bool Commute = false; 15395 switch (Op.getOpcode()) { 15396 default: break; 15397 case ISD::LOAD: { 15398 LoadSDNode *LD = cast<LoadSDNode>(Op); 15399 // If the non-extending load has a single use and it's not live out, then it 15400 // might be folded. 15401 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15402 Op.hasOneUse()*/) { 15403 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15404 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15405 // The only case where we'd want to promote LOAD (rather then it being 15406 // promoted as an operand is when it's only use is liveout. 15407 if (UI->getOpcode() != ISD::CopyToReg) 15408 return false; 15409 } 15410 } 15411 Promote = true; 15412 break; 15413 } 15414 case ISD::SIGN_EXTEND: 15415 case ISD::ZERO_EXTEND: 15416 case ISD::ANY_EXTEND: 15417 Promote = true; 15418 break; 15419 case ISD::SHL: 15420 case ISD::SRL: { 15421 SDValue N0 = Op.getOperand(0); 15422 // Look out for (store (shl (load), x)). 15423 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15424 return false; 15425 Promote = true; 15426 break; 15427 } 15428 case ISD::ADD: 15429 case ISD::MUL: 15430 case ISD::AND: 15431 case ISD::OR: 15432 case ISD::XOR: 15433 Commute = true; 15434 // fallthrough 15435 case ISD::SUB: { 15436 SDValue N0 = Op.getOperand(0); 15437 SDValue N1 = Op.getOperand(1); 15438 if (!Commute && MayFoldLoad(N1)) 15439 return false; 15440 // Avoid disabling potential load folding opportunities. 15441 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15442 return false; 15443 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15444 return false; 15445 Promote = true; 15446 } 15447 } 15448 15449 PVT = MVT::i32; 15450 return Promote; 15451} 15452 15453//===----------------------------------------------------------------------===// 15454// X86 Inline Assembly Support 15455//===----------------------------------------------------------------------===// 15456 15457namespace { 15458 // Helper to match a string separated by whitespace. 15459 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15460 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15461 15462 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15463 StringRef piece(*args[i]); 15464 if (!s.startswith(piece)) // Check if the piece matches. 15465 return false; 15466 15467 s = s.substr(piece.size()); 15468 StringRef::size_type pos = s.find_first_not_of(" \t"); 15469 if (pos == 0) // We matched a prefix. 15470 return false; 15471 15472 s = s.substr(pos); 15473 } 15474 15475 return s.empty(); 15476 } 15477 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15478} 15479 15480bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15481 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15482 15483 std::string AsmStr = IA->getAsmString(); 15484 15485 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15486 if (!Ty || Ty->getBitWidth() % 16 != 0) 15487 return false; 15488 15489 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15490 SmallVector<StringRef, 4> AsmPieces; 15491 SplitString(AsmStr, AsmPieces, ";\n"); 15492 15493 switch (AsmPieces.size()) { 15494 default: return false; 15495 case 1: 15496 // FIXME: this should verify that we are targeting a 486 or better. If not, 15497 // we will turn this bswap into something that will be lowered to logical 15498 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15499 // lower so don't worry about this. 15500 // bswap $0 15501 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15502 matchAsm(AsmPieces[0], "bswapl", "$0") || 15503 matchAsm(AsmPieces[0], "bswapq", "$0") || 15504 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15505 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15506 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15507 // No need to check constraints, nothing other than the equivalent of 15508 // "=r,0" would be valid here. 15509 return IntrinsicLowering::LowerToByteSwap(CI); 15510 } 15511 15512 // rorw $$8, ${0:w} --> llvm.bswap.i16 15513 if (CI->getType()->isIntegerTy(16) && 15514 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15515 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15516 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15517 AsmPieces.clear(); 15518 const std::string &ConstraintsStr = IA->getConstraintString(); 15519 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15520 std::sort(AsmPieces.begin(), AsmPieces.end()); 15521 if (AsmPieces.size() == 4 && 15522 AsmPieces[0] == "~{cc}" && 15523 AsmPieces[1] == "~{dirflag}" && 15524 AsmPieces[2] == "~{flags}" && 15525 AsmPieces[3] == "~{fpsr}") 15526 return IntrinsicLowering::LowerToByteSwap(CI); 15527 } 15528 break; 15529 case 3: 15530 if (CI->getType()->isIntegerTy(32) && 15531 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15532 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15533 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15534 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15535 AsmPieces.clear(); 15536 const std::string &ConstraintsStr = IA->getConstraintString(); 15537 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15538 std::sort(AsmPieces.begin(), AsmPieces.end()); 15539 if (AsmPieces.size() == 4 && 15540 AsmPieces[0] == "~{cc}" && 15541 AsmPieces[1] == "~{dirflag}" && 15542 AsmPieces[2] == "~{flags}" && 15543 AsmPieces[3] == "~{fpsr}") 15544 return IntrinsicLowering::LowerToByteSwap(CI); 15545 } 15546 15547 if (CI->getType()->isIntegerTy(64)) { 15548 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15549 if (Constraints.size() >= 2 && 15550 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15551 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15552 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15553 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15554 matchAsm(AsmPieces[1], "bswap", "%edx") && 15555 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15556 return IntrinsicLowering::LowerToByteSwap(CI); 15557 } 15558 } 15559 break; 15560 } 15561 return false; 15562} 15563 15564 15565 15566/// getConstraintType - Given a constraint letter, return the type of 15567/// constraint it is for this target. 15568X86TargetLowering::ConstraintType 15569X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15570 if (Constraint.size() == 1) { 15571 switch (Constraint[0]) { 15572 case 'R': 15573 case 'q': 15574 case 'Q': 15575 case 'f': 15576 case 't': 15577 case 'u': 15578 case 'y': 15579 case 'x': 15580 case 'Y': 15581 case 'l': 15582 return C_RegisterClass; 15583 case 'a': 15584 case 'b': 15585 case 'c': 15586 case 'd': 15587 case 'S': 15588 case 'D': 15589 case 'A': 15590 return C_Register; 15591 case 'I': 15592 case 'J': 15593 case 'K': 15594 case 'L': 15595 case 'M': 15596 case 'N': 15597 case 'G': 15598 case 'C': 15599 case 'e': 15600 case 'Z': 15601 return C_Other; 15602 default: 15603 break; 15604 } 15605 } 15606 return TargetLowering::getConstraintType(Constraint); 15607} 15608 15609/// Examine constraint type and operand type and determine a weight value. 15610/// This object must already have been set up with the operand type 15611/// and the current alternative constraint selected. 15612TargetLowering::ConstraintWeight 15613 X86TargetLowering::getSingleConstraintMatchWeight( 15614 AsmOperandInfo &info, const char *constraint) const { 15615 ConstraintWeight weight = CW_Invalid; 15616 Value *CallOperandVal = info.CallOperandVal; 15617 // If we don't have a value, we can't do a match, 15618 // but allow it at the lowest weight. 15619 if (CallOperandVal == NULL) 15620 return CW_Default; 15621 Type *type = CallOperandVal->getType(); 15622 // Look at the constraint type. 15623 switch (*constraint) { 15624 default: 15625 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15626 case 'R': 15627 case 'q': 15628 case 'Q': 15629 case 'a': 15630 case 'b': 15631 case 'c': 15632 case 'd': 15633 case 'S': 15634 case 'D': 15635 case 'A': 15636 if (CallOperandVal->getType()->isIntegerTy()) 15637 weight = CW_SpecificReg; 15638 break; 15639 case 'f': 15640 case 't': 15641 case 'u': 15642 if (type->isFloatingPointTy()) 15643 weight = CW_SpecificReg; 15644 break; 15645 case 'y': 15646 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15647 weight = CW_SpecificReg; 15648 break; 15649 case 'x': 15650 case 'Y': 15651 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15652 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15653 weight = CW_Register; 15654 break; 15655 case 'I': 15656 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15657 if (C->getZExtValue() <= 31) 15658 weight = CW_Constant; 15659 } 15660 break; 15661 case 'J': 15662 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15663 if (C->getZExtValue() <= 63) 15664 weight = CW_Constant; 15665 } 15666 break; 15667 case 'K': 15668 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15669 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15670 weight = CW_Constant; 15671 } 15672 break; 15673 case 'L': 15674 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15675 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15676 weight = CW_Constant; 15677 } 15678 break; 15679 case 'M': 15680 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15681 if (C->getZExtValue() <= 3) 15682 weight = CW_Constant; 15683 } 15684 break; 15685 case 'N': 15686 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15687 if (C->getZExtValue() <= 0xff) 15688 weight = CW_Constant; 15689 } 15690 break; 15691 case 'G': 15692 case 'C': 15693 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15694 weight = CW_Constant; 15695 } 15696 break; 15697 case 'e': 15698 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15699 if ((C->getSExtValue() >= -0x80000000LL) && 15700 (C->getSExtValue() <= 0x7fffffffLL)) 15701 weight = CW_Constant; 15702 } 15703 break; 15704 case 'Z': 15705 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15706 if (C->getZExtValue() <= 0xffffffff) 15707 weight = CW_Constant; 15708 } 15709 break; 15710 } 15711 return weight; 15712} 15713 15714/// LowerXConstraint - try to replace an X constraint, which matches anything, 15715/// with another that has more specific requirements based on the type of the 15716/// corresponding operand. 15717const char *X86TargetLowering:: 15718LowerXConstraint(EVT ConstraintVT) const { 15719 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15720 // 'f' like normal targets. 15721 if (ConstraintVT.isFloatingPoint()) { 15722 if (Subtarget->hasSSE2()) 15723 return "Y"; 15724 if (Subtarget->hasSSE1()) 15725 return "x"; 15726 } 15727 15728 return TargetLowering::LowerXConstraint(ConstraintVT); 15729} 15730 15731/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15732/// vector. If it is invalid, don't add anything to Ops. 15733void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15734 std::string &Constraint, 15735 std::vector<SDValue>&Ops, 15736 SelectionDAG &DAG) const { 15737 SDValue Result(0, 0); 15738 15739 // Only support length 1 constraints for now. 15740 if (Constraint.length() > 1) return; 15741 15742 char ConstraintLetter = Constraint[0]; 15743 switch (ConstraintLetter) { 15744 default: break; 15745 case 'I': 15746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15747 if (C->getZExtValue() <= 31) { 15748 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15749 break; 15750 } 15751 } 15752 return; 15753 case 'J': 15754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15755 if (C->getZExtValue() <= 63) { 15756 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15757 break; 15758 } 15759 } 15760 return; 15761 case 'K': 15762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15763 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15764 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15765 break; 15766 } 15767 } 15768 return; 15769 case 'N': 15770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15771 if (C->getZExtValue() <= 255) { 15772 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15773 break; 15774 } 15775 } 15776 return; 15777 case 'e': { 15778 // 32-bit signed value 15779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15780 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15781 C->getSExtValue())) { 15782 // Widen to 64 bits here to get it sign extended. 15783 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15784 break; 15785 } 15786 // FIXME gcc accepts some relocatable values here too, but only in certain 15787 // memory models; it's complicated. 15788 } 15789 return; 15790 } 15791 case 'Z': { 15792 // 32-bit unsigned value 15793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15794 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15795 C->getZExtValue())) { 15796 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15797 break; 15798 } 15799 } 15800 // FIXME gcc accepts some relocatable values here too, but only in certain 15801 // memory models; it's complicated. 15802 return; 15803 } 15804 case 'i': { 15805 // Literal immediates are always ok. 15806 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15807 // Widen to 64 bits here to get it sign extended. 15808 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15809 break; 15810 } 15811 15812 // In any sort of PIC mode addresses need to be computed at runtime by 15813 // adding in a register or some sort of table lookup. These can't 15814 // be used as immediates. 15815 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15816 return; 15817 15818 // If we are in non-pic codegen mode, we allow the address of a global (with 15819 // an optional displacement) to be used with 'i'. 15820 GlobalAddressSDNode *GA = 0; 15821 int64_t Offset = 0; 15822 15823 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15824 while (1) { 15825 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15826 Offset += GA->getOffset(); 15827 break; 15828 } else if (Op.getOpcode() == ISD::ADD) { 15829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15830 Offset += C->getZExtValue(); 15831 Op = Op.getOperand(0); 15832 continue; 15833 } 15834 } else if (Op.getOpcode() == ISD::SUB) { 15835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15836 Offset += -C->getZExtValue(); 15837 Op = Op.getOperand(0); 15838 continue; 15839 } 15840 } 15841 15842 // Otherwise, this isn't something we can handle, reject it. 15843 return; 15844 } 15845 15846 const GlobalValue *GV = GA->getGlobal(); 15847 // If we require an extra load to get this address, as in PIC mode, we 15848 // can't accept it. 15849 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15850 getTargetMachine()))) 15851 return; 15852 15853 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15854 GA->getValueType(0), Offset); 15855 break; 15856 } 15857 } 15858 15859 if (Result.getNode()) { 15860 Ops.push_back(Result); 15861 return; 15862 } 15863 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15864} 15865 15866std::pair<unsigned, const TargetRegisterClass*> 15867X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15868 EVT VT) const { 15869 // First, see if this is a constraint that directly corresponds to an LLVM 15870 // register class. 15871 if (Constraint.size() == 1) { 15872 // GCC Constraint Letters 15873 switch (Constraint[0]) { 15874 default: break; 15875 // TODO: Slight differences here in allocation order and leaving 15876 // RIP in the class. Do they matter any more here than they do 15877 // in the normal allocation? 15878 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15879 if (Subtarget->is64Bit()) { 15880 if (VT == MVT::i32 || VT == MVT::f32) 15881 return std::make_pair(0U, &X86::GR32RegClass); 15882 if (VT == MVT::i16) 15883 return std::make_pair(0U, &X86::GR16RegClass); 15884 if (VT == MVT::i8 || VT == MVT::i1) 15885 return std::make_pair(0U, &X86::GR8RegClass); 15886 if (VT == MVT::i64 || VT == MVT::f64) 15887 return std::make_pair(0U, &X86::GR64RegClass); 15888 break; 15889 } 15890 // 32-bit fallthrough 15891 case 'Q': // Q_REGS 15892 if (VT == MVT::i32 || VT == MVT::f32) 15893 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 15894 if (VT == MVT::i16) 15895 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 15896 if (VT == MVT::i8 || VT == MVT::i1) 15897 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 15898 if (VT == MVT::i64) 15899 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 15900 break; 15901 case 'r': // GENERAL_REGS 15902 case 'l': // INDEX_REGS 15903 if (VT == MVT::i8 || VT == MVT::i1) 15904 return std::make_pair(0U, &X86::GR8RegClass); 15905 if (VT == MVT::i16) 15906 return std::make_pair(0U, &X86::GR16RegClass); 15907 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15908 return std::make_pair(0U, &X86::GR32RegClass); 15909 return std::make_pair(0U, &X86::GR64RegClass); 15910 case 'R': // LEGACY_REGS 15911 if (VT == MVT::i8 || VT == MVT::i1) 15912 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 15913 if (VT == MVT::i16) 15914 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 15915 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15916 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 15917 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 15918 case 'f': // FP Stack registers. 15919 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15920 // value to the correct fpstack register class. 15921 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15922 return std::make_pair(0U, &X86::RFP32RegClass); 15923 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15924 return std::make_pair(0U, &X86::RFP64RegClass); 15925 return std::make_pair(0U, &X86::RFP80RegClass); 15926 case 'y': // MMX_REGS if MMX allowed. 15927 if (!Subtarget->hasMMX()) break; 15928 return std::make_pair(0U, &X86::VR64RegClass); 15929 case 'Y': // SSE_REGS if SSE2 allowed 15930 if (!Subtarget->hasSSE2()) break; 15931 // FALL THROUGH. 15932 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15933 if (!Subtarget->hasSSE1()) break; 15934 15935 switch (VT.getSimpleVT().SimpleTy) { 15936 default: break; 15937 // Scalar SSE types. 15938 case MVT::f32: 15939 case MVT::i32: 15940 return std::make_pair(0U, &X86::FR32RegClass); 15941 case MVT::f64: 15942 case MVT::i64: 15943 return std::make_pair(0U, &X86::FR64RegClass); 15944 // Vector types. 15945 case MVT::v16i8: 15946 case MVT::v8i16: 15947 case MVT::v4i32: 15948 case MVT::v2i64: 15949 case MVT::v4f32: 15950 case MVT::v2f64: 15951 return std::make_pair(0U, &X86::VR128RegClass); 15952 // AVX types. 15953 case MVT::v32i8: 15954 case MVT::v16i16: 15955 case MVT::v8i32: 15956 case MVT::v4i64: 15957 case MVT::v8f32: 15958 case MVT::v4f64: 15959 return std::make_pair(0U, &X86::VR256RegClass); 15960 } 15961 break; 15962 } 15963 } 15964 15965 // Use the default implementation in TargetLowering to convert the register 15966 // constraint into a member of a register class. 15967 std::pair<unsigned, const TargetRegisterClass*> Res; 15968 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15969 15970 // Not found as a standard register? 15971 if (Res.second == 0) { 15972 // Map st(0) -> st(7) -> ST0 15973 if (Constraint.size() == 7 && Constraint[0] == '{' && 15974 tolower(Constraint[1]) == 's' && 15975 tolower(Constraint[2]) == 't' && 15976 Constraint[3] == '(' && 15977 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15978 Constraint[5] == ')' && 15979 Constraint[6] == '}') { 15980 15981 Res.first = X86::ST0+Constraint[4]-'0'; 15982 Res.second = &X86::RFP80RegClass; 15983 return Res; 15984 } 15985 15986 // GCC allows "st(0)" to be called just plain "st". 15987 if (StringRef("{st}").equals_lower(Constraint)) { 15988 Res.first = X86::ST0; 15989 Res.second = &X86::RFP80RegClass; 15990 return Res; 15991 } 15992 15993 // flags -> EFLAGS 15994 if (StringRef("{flags}").equals_lower(Constraint)) { 15995 Res.first = X86::EFLAGS; 15996 Res.second = &X86::CCRRegClass; 15997 return Res; 15998 } 15999 16000 // 'A' means EAX + EDX. 16001 if (Constraint == "A") { 16002 Res.first = X86::EAX; 16003 Res.second = &X86::GR32_ADRegClass; 16004 return Res; 16005 } 16006 return Res; 16007 } 16008 16009 // Otherwise, check to see if this is a register class of the wrong value 16010 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 16011 // turn into {ax},{dx}. 16012 if (Res.second->hasType(VT)) 16013 return Res; // Correct type already, nothing to do. 16014 16015 // All of the single-register GCC register classes map their values onto 16016 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 16017 // really want an 8-bit or 32-bit register, map to the appropriate register 16018 // class and return the appropriate register. 16019 if (Res.second == &X86::GR16RegClass) { 16020 if (VT == MVT::i8) { 16021 unsigned DestReg = 0; 16022 switch (Res.first) { 16023 default: break; 16024 case X86::AX: DestReg = X86::AL; break; 16025 case X86::DX: DestReg = X86::DL; break; 16026 case X86::CX: DestReg = X86::CL; break; 16027 case X86::BX: DestReg = X86::BL; break; 16028 } 16029 if (DestReg) { 16030 Res.first = DestReg; 16031 Res.second = &X86::GR8RegClass; 16032 } 16033 } else if (VT == MVT::i32) { 16034 unsigned DestReg = 0; 16035 switch (Res.first) { 16036 default: break; 16037 case X86::AX: DestReg = X86::EAX; break; 16038 case X86::DX: DestReg = X86::EDX; break; 16039 case X86::CX: DestReg = X86::ECX; break; 16040 case X86::BX: DestReg = X86::EBX; break; 16041 case X86::SI: DestReg = X86::ESI; break; 16042 case X86::DI: DestReg = X86::EDI; break; 16043 case X86::BP: DestReg = X86::EBP; break; 16044 case X86::SP: DestReg = X86::ESP; break; 16045 } 16046 if (DestReg) { 16047 Res.first = DestReg; 16048 Res.second = &X86::GR32RegClass; 16049 } 16050 } else if (VT == MVT::i64) { 16051 unsigned DestReg = 0; 16052 switch (Res.first) { 16053 default: break; 16054 case X86::AX: DestReg = X86::RAX; break; 16055 case X86::DX: DestReg = X86::RDX; break; 16056 case X86::CX: DestReg = X86::RCX; break; 16057 case X86::BX: DestReg = X86::RBX; break; 16058 case X86::SI: DestReg = X86::RSI; break; 16059 case X86::DI: DestReg = X86::RDI; break; 16060 case X86::BP: DestReg = X86::RBP; break; 16061 case X86::SP: DestReg = X86::RSP; break; 16062 } 16063 if (DestReg) { 16064 Res.first = DestReg; 16065 Res.second = &X86::GR64RegClass; 16066 } 16067 } 16068 } else if (Res.second == &X86::FR32RegClass || 16069 Res.second == &X86::FR64RegClass || 16070 Res.second == &X86::VR128RegClass) { 16071 // Handle references to XMM physical registers that got mapped into the 16072 // wrong class. This can happen with constraints like {xmm0} where the 16073 // target independent register mapper will just pick the first match it can 16074 // find, ignoring the required type. 16075 if (VT == MVT::f32) 16076 Res.second = &X86::FR32RegClass; 16077 else if (VT == MVT::f64) 16078 Res.second = &X86::FR64RegClass; 16079 else if (X86::VR128RegClass.hasType(VT)) 16080 Res.second = &X86::VR128RegClass; 16081 } 16082 16083 return Res; 16084} 16085