X86ISelLowering.cpp revision ad9c0a3d8bf625d169596547f893b9ec8b953e26 
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86ISelLowering.h"
18#include "X86TargetMachine.h"
19#include "X86TargetObjectFile.h"
20#include "llvm/CallingConv.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/GlobalAlias.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/Function.h"
26#include "llvm/Instructions.h"
27#include "llvm/Intrinsics.h"
28#include "llvm/LLVMContext.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/VectorExtras.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstrBuilder.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Target/TargetOptions.h"
41#include "llvm/ADT/SmallSet.h"
42#include "llvm/ADT/StringExtras.h"
43#include "llvm/Support/CommandLine.h"
44#include "llvm/Support/raw_ostream.h"
45using namespace llvm;
46
47static cl::opt<bool>
48DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
49
50// Disable16Bit - 16-bit operations typically have a larger encoding than
51// corresponding 32-bit instructions, and 16-bit code is slow on some
52// processors. This is an experimental flag to disable 16-bit operations
53// (which forces them to be Legalized to 32-bit operations).
54static cl::opt<bool>
55Disable16Bit("disable-16bit", cl::Hidden,
56             cl::desc("Disable use of 16-bit instructions"));
57
58// Forward declarations.
59static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60                       SDValue V2);
61
62static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63  switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64  default: llvm_unreachable("unknown subtarget type");
65  case X86Subtarget::isDarwin:
66    if (TM.getSubtarget<X86Subtarget>().is64Bit())
67      return new X8664_MachoTargetObjectFile();
68    return new X8632_MachoTargetObjectFile();
69  case X86Subtarget::isELF:
70    return new TargetLoweringObjectFileELF();
71  case X86Subtarget::isMingw:
72  case X86Subtarget::isCygwin:
73  case X86Subtarget::isWindows:
74    return new TargetLoweringObjectFileCOFF();
75  }
76
77}
78
79X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80  : TargetLowering(TM, createTLOF(TM)) {
81  Subtarget = &TM.getSubtarget<X86Subtarget>();
82  X86ScalarSSEf64 = Subtarget->hasSSE2();
83  X86ScalarSSEf32 = Subtarget->hasSSE1();
84  X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
85
86  RegInfo = TM.getRegisterInfo();
87  TD = getTargetData();
88
89  // Set up the TargetLowering object.
90
91  // X86 is weird, it always uses i8 for shift amounts and setcc results.
92  setShiftAmountType(MVT::i8);
93  setBooleanContents(ZeroOrOneBooleanContent);
94  setSchedulingPreference(SchedulingForRegPressure);
95  setStackPointerRegisterToSaveRestore(X86StackPtr);
96
97  if (Subtarget->isTargetDarwin()) {
98    // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99    setUseUnderscoreSetJmp(false);
100    setUseUnderscoreLongJmp(false);
101  } else if (Subtarget->isTargetMingw()) {
102    // MS runtime is weird: it exports _setjmp, but longjmp!
103    setUseUnderscoreSetJmp(true);
104    setUseUnderscoreLongJmp(false);
105  } else {
106    setUseUnderscoreSetJmp(true);
107    setUseUnderscoreLongJmp(true);
108  }
109
110  // Set up the register classes.
111  addRegisterClass(MVT::i8, X86::GR8RegisterClass);
112  if (!Disable16Bit)
113    addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114  addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115  if (Subtarget->is64Bit())
116    addRegisterClass(MVT::i64, X86::GR64RegisterClass);
117
118  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
119
120  // We don't accept any truncstore of integer registers.
121  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122  if (!Disable16Bit)
123    setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124  setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
125  if (!Disable16Bit)
126    setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127  setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128  setTruncStoreAction(MVT::i16, MVT::i8,  Expand);
129
130  // SETOEQ and SETUNE require checking two conditions.
131  setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132  setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133  setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134  setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135  setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136  setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
137
138  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
139  // operation.
140  setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
141  setOperationAction(ISD::UINT_TO_FP       , MVT::i8   , Promote);
142  setOperationAction(ISD::UINT_TO_FP       , MVT::i16  , Promote);
143
144  if (Subtarget->is64Bit()) {
145    setOperationAction(ISD::UINT_TO_FP     , MVT::i32  , Promote);
146    setOperationAction(ISD::UINT_TO_FP     , MVT::i64  , Expand);
147  } else if (!UseSoftFloat) {
148    if (X86ScalarSSEf64) {
149      // We have an impenetrably clever algorithm for ui64->double only.
150      setOperationAction(ISD::UINT_TO_FP   , MVT::i64  , Custom);
151    }
152    // We have an algorithm for SSE2, and we turn this into a 64-bit
153    // FILD for other targets.
154    setOperationAction(ISD::UINT_TO_FP   , MVT::i32  , Custom);
155  }
156
157  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
158  // this operation.
159  setOperationAction(ISD::SINT_TO_FP       , MVT::i1   , Promote);
160  setOperationAction(ISD::SINT_TO_FP       , MVT::i8   , Promote);
161
162  if (!UseSoftFloat) {
163    // SSE has no i16 to fp conversion, only i32
164    if (X86ScalarSSEf32) {
165      setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Promote);
166      // f32 and f64 cases are Legal, f80 case is not
167      setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
168    } else {
169      setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Custom);
170      setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
171    }
172  } else {
173    setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Promote);
174    setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Promote);
175  }
176
177  // In 32-bit mode these are custom lowered.  In 64-bit mode F32 and F64
178  // are Legal, f80 is custom lowered.
179  setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);
180  setOperationAction(ISD::SINT_TO_FP     , MVT::i64  , Custom);
181
182  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
183  // this operation.
184  setOperationAction(ISD::FP_TO_SINT       , MVT::i1   , Promote);
185  setOperationAction(ISD::FP_TO_SINT       , MVT::i8   , Promote);
186
187  if (X86ScalarSSEf32) {
188    setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Promote);
189    // f32 and f64 cases are Legal, f80 case is not
190    setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);
191  } else {
192    setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Custom);
193    setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);
194  }
195
196  // Handle FP_TO_UINT by promoting the destination to a larger signed
197  // conversion.
198  setOperationAction(ISD::FP_TO_UINT       , MVT::i1   , Promote);
199  setOperationAction(ISD::FP_TO_UINT       , MVT::i8   , Promote);
200  setOperationAction(ISD::FP_TO_UINT       , MVT::i16  , Promote);
201
202  if (Subtarget->is64Bit()) {
203    setOperationAction(ISD::FP_TO_UINT     , MVT::i64  , Expand);
204    setOperationAction(ISD::FP_TO_UINT     , MVT::i32  , Promote);
205  } else if (!UseSoftFloat) {
206    if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207      // Expand FP_TO_UINT into a select.
208      // FIXME: We would like to use a Custom expander here eventually to do
209      // the optimal thing for SSE vs. the default expansion in the legalizer.
210      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Expand);
211    else
212      // With SSE3 we can use fisttpll to convert to a signed i64; without
213      // SSE, we're stuck with a fistpll.
214      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Custom);
215  }
216
217  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218  if (!X86ScalarSSEf64) {
219    setOperationAction(ISD::BIT_CONVERT      , MVT::f32  , Expand);
220    setOperationAction(ISD::BIT_CONVERT      , MVT::i32  , Expand);
221  }
222
223  // Scalar integer divide and remainder are lowered to use operations that
224  // produce two results, to match the available instructions. This exposes
225  // the two-result form to trivial CSE, which is able to combine x/y and x%y
226  // into a single instruction.
227  //
228  // Scalar integer multiply-high is also lowered to use two-result
229  // operations, to match the available instructions. However, plain multiply
230  // (low) operations are left as Legal, as there are single-result
231  // instructions for this in x86. Using the two-result multiply instructions
232  // when both high and low results are needed must be arranged by dagcombine.
233  setOperationAction(ISD::MULHS           , MVT::i8    , Expand);
234  setOperationAction(ISD::MULHU           , MVT::i8    , Expand);
235  setOperationAction(ISD::SDIV            , MVT::i8    , Expand);
236  setOperationAction(ISD::UDIV            , MVT::i8    , Expand);
237  setOperationAction(ISD::SREM            , MVT::i8    , Expand);
238  setOperationAction(ISD::UREM            , MVT::i8    , Expand);
239  setOperationAction(ISD::MULHS           , MVT::i16   , Expand);
240  setOperationAction(ISD::MULHU           , MVT::i16   , Expand);
241  setOperationAction(ISD::SDIV            , MVT::i16   , Expand);
242  setOperationAction(ISD::UDIV            , MVT::i16   , Expand);
243  setOperationAction(ISD::SREM            , MVT::i16   , Expand);
244  setOperationAction(ISD::UREM            , MVT::i16   , Expand);
245  setOperationAction(ISD::MULHS           , MVT::i32   , Expand);
246  setOperationAction(ISD::MULHU           , MVT::i32   , Expand);
247  setOperationAction(ISD::SDIV            , MVT::i32   , Expand);
248  setOperationAction(ISD::UDIV            , MVT::i32   , Expand);
249  setOperationAction(ISD::SREM            , MVT::i32   , Expand);
250  setOperationAction(ISD::UREM            , MVT::i32   , Expand);
251  setOperationAction(ISD::MULHS           , MVT::i64   , Expand);
252  setOperationAction(ISD::MULHU           , MVT::i64   , Expand);
253  setOperationAction(ISD::SDIV            , MVT::i64   , Expand);
254  setOperationAction(ISD::UDIV            , MVT::i64   , Expand);
255  setOperationAction(ISD::SREM            , MVT::i64   , Expand);
256  setOperationAction(ISD::UREM            , MVT::i64   , Expand);
257
258  setOperationAction(ISD::BR_JT            , MVT::Other, Expand);
259  setOperationAction(ISD::BRCOND           , MVT::Other, Custom);
260  setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
261  setOperationAction(ISD::SELECT_CC        , MVT::Other, Expand);
262  if (Subtarget->is64Bit())
263    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Legal);
265  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Legal);
266  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
267  setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
268  setOperationAction(ISD::FREM             , MVT::f32  , Expand);
269  setOperationAction(ISD::FREM             , MVT::f64  , Expand);
270  setOperationAction(ISD::FREM             , MVT::f80  , Expand);
271  setOperationAction(ISD::FLT_ROUNDS_      , MVT::i32  , Custom);
272
273  setOperationAction(ISD::CTPOP            , MVT::i8   , Expand);
274  setOperationAction(ISD::CTTZ             , MVT::i8   , Custom);
275  setOperationAction(ISD::CTLZ             , MVT::i8   , Custom);
276  setOperationAction(ISD::CTPOP            , MVT::i16  , Expand);
277  if (Disable16Bit) {
278    setOperationAction(ISD::CTTZ           , MVT::i16  , Expand);
279    setOperationAction(ISD::CTLZ           , MVT::i16  , Expand);
280  } else {
281    setOperationAction(ISD::CTTZ           , MVT::i16  , Custom);
282    setOperationAction(ISD::CTLZ           , MVT::i16  , Custom);
283  }
284  setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
285  setOperationAction(ISD::CTTZ             , MVT::i32  , Custom);
286  setOperationAction(ISD::CTLZ             , MVT::i32  , Custom);
287  if (Subtarget->is64Bit()) {
288    setOperationAction(ISD::CTPOP          , MVT::i64  , Expand);
289    setOperationAction(ISD::CTTZ           , MVT::i64  , Custom);
290    setOperationAction(ISD::CTLZ           , MVT::i64  , Custom);
291  }
292
293  setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
294  setOperationAction(ISD::BSWAP            , MVT::i16  , Expand);
295
296  // These should be promoted to a larger select which is supported.
297  setOperationAction(ISD::SELECT          , MVT::i1   , Promote);
298  // X86 wants to expand cmov itself.
299  setOperationAction(ISD::SELECT          , MVT::i8   , Custom);
300  if (Disable16Bit)
301    setOperationAction(ISD::SELECT        , MVT::i16  , Expand);
302  else
303    setOperationAction(ISD::SELECT        , MVT::i16  , Custom);
304  setOperationAction(ISD::SELECT          , MVT::i32  , Custom);
305  setOperationAction(ISD::SELECT          , MVT::f32  , Custom);
306  setOperationAction(ISD::SELECT          , MVT::f64  , Custom);
307  setOperationAction(ISD::SELECT          , MVT::f80  , Custom);
308  setOperationAction(ISD::SETCC           , MVT::i8   , Custom);
309  if (Disable16Bit)
310    setOperationAction(ISD::SETCC         , MVT::i16  , Expand);
311  else
312    setOperationAction(ISD::SETCC         , MVT::i16  , Custom);
313  setOperationAction(ISD::SETCC           , MVT::i32  , Custom);
314  setOperationAction(ISD::SETCC           , MVT::f32  , Custom);
315  setOperationAction(ISD::SETCC           , MVT::f64  , Custom);
316  setOperationAction(ISD::SETCC           , MVT::f80  , Custom);
317  if (Subtarget->is64Bit()) {
318    setOperationAction(ISD::SELECT        , MVT::i64  , Custom);
319    setOperationAction(ISD::SETCC         , MVT::i64  , Custom);
320  }
321  setOperationAction(ISD::EH_RETURN       , MVT::Other, Custom);
322
323  // Darwin ABI issue.
324  setOperationAction(ISD::ConstantPool    , MVT::i32  , Custom);
325  setOperationAction(ISD::JumpTable       , MVT::i32  , Custom);
326  setOperationAction(ISD::GlobalAddress   , MVT::i32  , Custom);
327  setOperationAction(ISD::GlobalTLSAddress, MVT::i32  , Custom);
328  if (Subtarget->is64Bit())
329    setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330  setOperationAction(ISD::ExternalSymbol  , MVT::i32  , Custom);
331  setOperationAction(ISD::BlockAddress    , MVT::i32  , Custom);
332  if (Subtarget->is64Bit()) {
333    setOperationAction(ISD::ConstantPool  , MVT::i64  , Custom);
334    setOperationAction(ISD::JumpTable     , MVT::i64  , Custom);
335    setOperationAction(ISD::GlobalAddress , MVT::i64  , Custom);
336    setOperationAction(ISD::ExternalSymbol, MVT::i64  , Custom);
337    setOperationAction(ISD::BlockAddress  , MVT::i64  , Custom);
338  }
339  // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340  setOperationAction(ISD::SHL_PARTS       , MVT::i32  , Custom);
341  setOperationAction(ISD::SRA_PARTS       , MVT::i32  , Custom);
342  setOperationAction(ISD::SRL_PARTS       , MVT::i32  , Custom);
343  if (Subtarget->is64Bit()) {
344    setOperationAction(ISD::SHL_PARTS     , MVT::i64  , Custom);
345    setOperationAction(ISD::SRA_PARTS     , MVT::i64  , Custom);
346    setOperationAction(ISD::SRL_PARTS     , MVT::i64  , Custom);
347  }
348
349  if (Subtarget->hasSSE1())
350    setOperationAction(ISD::PREFETCH      , MVT::Other, Legal);
351
352  if (!Subtarget->hasSSE2())
353    setOperationAction(ISD::MEMBARRIER    , MVT::Other, Expand);
354
355  // Expand certain atomics
356  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
360
361  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
365
366  if (!Subtarget->is64Bit()) {
367    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368    setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369    setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372    setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373    setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
374  }
375
376  // FIXME - use subtarget debug flags
377  if (!Subtarget->isTargetDarwin() &&
378      !Subtarget->isTargetELF() &&
379      !Subtarget->isTargetCygMing()) {
380    setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
381  }
382
383  setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384  setOperationAction(ISD::EHSELECTION,   MVT::i64, Expand);
385  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386  setOperationAction(ISD::EHSELECTION,   MVT::i32, Expand);
387  if (Subtarget->is64Bit()) {
388    setExceptionPointerRegister(X86::RAX);
389    setExceptionSelectorRegister(X86::RDX);
390  } else {
391    setExceptionPointerRegister(X86::EAX);
392    setExceptionSelectorRegister(X86::EDX);
393  }
394  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
396
397  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
398
399  setOperationAction(ISD::TRAP, MVT::Other, Legal);
400
401  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
403  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
404  if (Subtarget->is64Bit()) {
405    setOperationAction(ISD::VAARG           , MVT::Other, Custom);
406    setOperationAction(ISD::VACOPY          , MVT::Other, Custom);
407  } else {
408    setOperationAction(ISD::VAARG           , MVT::Other, Expand);
409    setOperationAction(ISD::VACOPY          , MVT::Other, Expand);
410  }
411
412  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
413  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
414  if (Subtarget->is64Bit())
415    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416  if (Subtarget->isTargetCygMing())
417    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
418  else
419    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
420
421  if (!UseSoftFloat && X86ScalarSSEf64) {
422    // f32 and f64 use SSE.
423    // Set up the FP register classes.
424    addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425    addRegisterClass(MVT::f64, X86::FR64RegisterClass);
426
427    // Use ANDPD to simulate FABS.
428    setOperationAction(ISD::FABS , MVT::f64, Custom);
429    setOperationAction(ISD::FABS , MVT::f32, Custom);
430
431    // Use XORP to simulate FNEG.
432    setOperationAction(ISD::FNEG , MVT::f64, Custom);
433    setOperationAction(ISD::FNEG , MVT::f32, Custom);
434
435    // Use ANDPD and ORPD to simulate FCOPYSIGN.
436    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
438
439    // We don't support sin/cos/fmod
440    setOperationAction(ISD::FSIN , MVT::f64, Expand);
441    setOperationAction(ISD::FCOS , MVT::f64, Expand);
442    setOperationAction(ISD::FSIN , MVT::f32, Expand);
443    setOperationAction(ISD::FCOS , MVT::f32, Expand);
444
445    // Expand FP immediates into loads from the stack, except for the special
446    // cases we handle.
447    addLegalFPImmediate(APFloat(+0.0)); // xorpd
448    addLegalFPImmediate(APFloat(+0.0f)); // xorps
449  } else if (!UseSoftFloat && X86ScalarSSEf32) {
450    // Use SSE for f32, x87 for f64.
451    // Set up the FP register classes.
452    addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453    addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
454
455    // Use ANDPS to simulate FABS.
456    setOperationAction(ISD::FABS , MVT::f32, Custom);
457
458    // Use XORP to simulate FNEG.
459    setOperationAction(ISD::FNEG , MVT::f32, Custom);
460
461    setOperationAction(ISD::UNDEF,     MVT::f64, Expand);
462
463    // Use ANDPS and ORPS to simulate FCOPYSIGN.
464    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
466
467    // We don't support sin/cos/fmod
468    setOperationAction(ISD::FSIN , MVT::f32, Expand);
469    setOperationAction(ISD::FCOS , MVT::f32, Expand);
470
471    // Special cases we handle for FP constants.
472    addLegalFPImmediate(APFloat(+0.0f)); // xorps
473    addLegalFPImmediate(APFloat(+0.0)); // FLD0
474    addLegalFPImmediate(APFloat(+1.0)); // FLD1
475    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
477
478    if (!UnsafeFPMath) {
479      setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
480      setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
481    }
482  } else if (!UseSoftFloat) {
483    // f32 and f64 in x87.
484    // Set up the FP register classes.
485    addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486    addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
487
488    setOperationAction(ISD::UNDEF,     MVT::f64, Expand);
489    setOperationAction(ISD::UNDEF,     MVT::f32, Expand);
490    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
492
493    if (!UnsafeFPMath) {
494      setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
495      setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
496    }
497    addLegalFPImmediate(APFloat(+0.0)); // FLD0
498    addLegalFPImmediate(APFloat(+1.0)); // FLD1
499    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501    addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502    addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503    addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504    addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
505  }
506
507  // Long double always uses X87.
508  if (!UseSoftFloat) {
509    addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510    setOperationAction(ISD::UNDEF,     MVT::f80, Expand);
511    setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
512    {
513      bool ignored;
514      APFloat TmpFlt(+0.0);
515      TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
516                     &ignored);
517      addLegalFPImmediate(TmpFlt);  // FLD0
518      TmpFlt.changeSign();
519      addLegalFPImmediate(TmpFlt);  // FLD0/FCHS
520      APFloat TmpFlt2(+1.0);
521      TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
522                      &ignored);
523      addLegalFPImmediate(TmpFlt2);  // FLD1
524      TmpFlt2.changeSign();
525      addLegalFPImmediate(TmpFlt2);  // FLD1/FCHS
526    }
527
528    if (!UnsafeFPMath) {
529      setOperationAction(ISD::FSIN           , MVT::f80  , Expand);
530      setOperationAction(ISD::FCOS           , MVT::f80  , Expand);
531    }
532  }
533
534  // Always use a library call for pow.
535  setOperationAction(ISD::FPOW             , MVT::f32  , Expand);
536  setOperationAction(ISD::FPOW             , MVT::f64  , Expand);
537  setOperationAction(ISD::FPOW             , MVT::f80  , Expand);
538
539  setOperationAction(ISD::FLOG, MVT::f80, Expand);
540  setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541  setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542  setOperationAction(ISD::FEXP, MVT::f80, Expand);
543  setOperationAction(ISD::FEXP2, MVT::f80, Expand);
544
545  // First set operation action for all vector types to either promote
546  // (for widening) or expand (for scalarization). Then we will selectively
547  // turn on ones that can be effectively codegen'd.
548  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549       VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550    setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551    setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552    setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553    setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554    setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555    setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556    setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557    setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558    setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559    setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560    setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561    setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562    setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564    setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565    setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566    setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567    setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568    setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569    setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570    setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571    setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572    setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573    setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574    setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575    setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576    setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577    setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578    setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579    setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580    setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581    setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582    setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583    setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584    setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585    setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586    setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587    setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588    setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589    setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590    setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591    setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592    setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593    setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594    setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595    setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596    setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597    setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598    setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599    setOperationAction(ISD::TRUNCATE,  (MVT::SimpleValueType)VT, Expand);
600    setOperationAction(ISD::SIGN_EXTEND,  (MVT::SimpleValueType)VT, Expand);
601    setOperationAction(ISD::ZERO_EXTEND,  (MVT::SimpleValueType)VT, Expand);
602    setOperationAction(ISD::ANY_EXTEND,  (MVT::SimpleValueType)VT, Expand);
603    for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604         InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605      setTruncStoreAction((MVT::SimpleValueType)VT,
606                          (MVT::SimpleValueType)InnerVT, Expand);
607    setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608    setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609    setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
610  }
611
612  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613  // with -msoft-float, disable use of MMX as well.
614  if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615    addRegisterClass(MVT::v8i8,  X86::VR64RegisterClass);
616    addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
617    addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
618    addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
619    addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
620
621    setOperationAction(ISD::ADD,                MVT::v8i8,  Legal);
622    setOperationAction(ISD::ADD,                MVT::v4i16, Legal);
623    setOperationAction(ISD::ADD,                MVT::v2i32, Legal);
624    setOperationAction(ISD::ADD,                MVT::v1i64, Legal);
625
626    setOperationAction(ISD::SUB,                MVT::v8i8,  Legal);
627    setOperationAction(ISD::SUB,                MVT::v4i16, Legal);
628    setOperationAction(ISD::SUB,                MVT::v2i32, Legal);
629    setOperationAction(ISD::SUB,                MVT::v1i64, Legal);
630
631    setOperationAction(ISD::MULHS,              MVT::v4i16, Legal);
632    setOperationAction(ISD::MUL,                MVT::v4i16, Legal);
633
634    setOperationAction(ISD::AND,                MVT::v8i8,  Promote);
635    AddPromotedToType (ISD::AND,                MVT::v8i8,  MVT::v1i64);
636    setOperationAction(ISD::AND,                MVT::v4i16, Promote);
637    AddPromotedToType (ISD::AND,                MVT::v4i16, MVT::v1i64);
638    setOperationAction(ISD::AND,                MVT::v2i32, Promote);
639    AddPromotedToType (ISD::AND,                MVT::v2i32, MVT::v1i64);
640    setOperationAction(ISD::AND,                MVT::v1i64, Legal);
641
642    setOperationAction(ISD::OR,                 MVT::v8i8,  Promote);
643    AddPromotedToType (ISD::OR,                 MVT::v8i8,  MVT::v1i64);
644    setOperationAction(ISD::OR,                 MVT::v4i16, Promote);
645    AddPromotedToType (ISD::OR,                 MVT::v4i16, MVT::v1i64);
646    setOperationAction(ISD::OR,                 MVT::v2i32, Promote);
647    AddPromotedToType (ISD::OR,                 MVT::v2i32, MVT::v1i64);
648    setOperationAction(ISD::OR,                 MVT::v1i64, Legal);
649
650    setOperationAction(ISD::XOR,                MVT::v8i8,  Promote);
651    AddPromotedToType (ISD::XOR,                MVT::v8i8,  MVT::v1i64);
652    setOperationAction(ISD::XOR,                MVT::v4i16, Promote);
653    AddPromotedToType (ISD::XOR,                MVT::v4i16, MVT::v1i64);
654    setOperationAction(ISD::XOR,                MVT::v2i32, Promote);
655    AddPromotedToType (ISD::XOR,                MVT::v2i32, MVT::v1i64);
656    setOperationAction(ISD::XOR,                MVT::v1i64, Legal);
657
658    setOperationAction(ISD::LOAD,               MVT::v8i8,  Promote);
659    AddPromotedToType (ISD::LOAD,               MVT::v8i8,  MVT::v1i64);
660    setOperationAction(ISD::LOAD,               MVT::v4i16, Promote);
661    AddPromotedToType (ISD::LOAD,               MVT::v4i16, MVT::v1i64);
662    setOperationAction(ISD::LOAD,               MVT::v2i32, Promote);
663    AddPromotedToType (ISD::LOAD,               MVT::v2i32, MVT::v1i64);
664    setOperationAction(ISD::LOAD,               MVT::v2f32, Promote);
665    AddPromotedToType (ISD::LOAD,               MVT::v2f32, MVT::v1i64);
666    setOperationAction(ISD::LOAD,               MVT::v1i64, Legal);
667
668    setOperationAction(ISD::BUILD_VECTOR,       MVT::v8i8,  Custom);
669    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i16, Custom);
670    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i32, Custom);
671    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2f32, Custom);
672    setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i64, Custom);
673
674    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i8,  Custom);
675    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4i16, Custom);
676    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i32, Custom);
677    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v1i64, Custom);
678
679    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v2f32, Custom);
680    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i8,  Custom);
681    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v4i16, Custom);
682    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v1i64, Custom);
683
684    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i16, Custom);
685
686    setOperationAction(ISD::SELECT,             MVT::v8i8, Promote);
687    setOperationAction(ISD::SELECT,             MVT::v4i16, Promote);
688    setOperationAction(ISD::SELECT,             MVT::v2i32, Promote);
689    setOperationAction(ISD::SELECT,             MVT::v1i64, Custom);
690    setOperationAction(ISD::VSETCC,             MVT::v8i8, Custom);
691    setOperationAction(ISD::VSETCC,             MVT::v4i16, Custom);
692    setOperationAction(ISD::VSETCC,             MVT::v2i32, Custom);
693  }
694
695  if (!UseSoftFloat && Subtarget->hasSSE1()) {
696    addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
697
698    setOperationAction(ISD::FADD,               MVT::v4f32, Legal);
699    setOperationAction(ISD::FSUB,               MVT::v4f32, Legal);
700    setOperationAction(ISD::FMUL,               MVT::v4f32, Legal);
701    setOperationAction(ISD::FDIV,               MVT::v4f32, Legal);
702    setOperationAction(ISD::FSQRT,              MVT::v4f32, Legal);
703    setOperationAction(ISD::FNEG,               MVT::v4f32, Custom);
704    setOperationAction(ISD::LOAD,               MVT::v4f32, Legal);
705    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4f32, Custom);
706    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f32, Custom);
707    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
708    setOperationAction(ISD::SELECT,             MVT::v4f32, Custom);
709    setOperationAction(ISD::VSETCC,             MVT::v4f32, Custom);
710  }
711
712  if (!UseSoftFloat && Subtarget->hasSSE2()) {
713    addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
714
715    // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
716    // registers cannot be used even for integer operations.
717    addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
718    addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
719    addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
720    addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
721
722    setOperationAction(ISD::ADD,                MVT::v16i8, Legal);
723    setOperationAction(ISD::ADD,                MVT::v8i16, Legal);
724    setOperationAction(ISD::ADD,                MVT::v4i32, Legal);
725    setOperationAction(ISD::ADD,                MVT::v2i64, Legal);
726    setOperationAction(ISD::MUL,                MVT::v2i64, Custom);
727    setOperationAction(ISD::SUB,                MVT::v16i8, Legal);
728    setOperationAction(ISD::SUB,                MVT::v8i16, Legal);
729    setOperationAction(ISD::SUB,                MVT::v4i32, Legal);
730    setOperationAction(ISD::SUB,                MVT::v2i64, Legal);
731    setOperationAction(ISD::MUL,                MVT::v8i16, Legal);
732    setOperationAction(ISD::FADD,               MVT::v2f64, Legal);
733    setOperationAction(ISD::FSUB,               MVT::v2f64, Legal);
734    setOperationAction(ISD::FMUL,               MVT::v2f64, Legal);
735    setOperationAction(ISD::FDIV,               MVT::v2f64, Legal);
736    setOperationAction(ISD::FSQRT,              MVT::v2f64, Legal);
737    setOperationAction(ISD::FNEG,               MVT::v2f64, Custom);
738
739    setOperationAction(ISD::VSETCC,             MVT::v2f64, Custom);
740    setOperationAction(ISD::VSETCC,             MVT::v16i8, Custom);
741    setOperationAction(ISD::VSETCC,             MVT::v8i16, Custom);
742    setOperationAction(ISD::VSETCC,             MVT::v4i32, Custom);
743
744    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i8, Custom);
745    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i16, Custom);
746    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
747    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);
748    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);
749
750    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
751    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
752      EVT VT = (MVT::SimpleValueType)i;
753      // Do not attempt to custom lower non-power-of-2 vectors
754      if (!isPowerOf2_32(VT.getVectorNumElements()))
755        continue;
756      // Do not attempt to custom lower non-128-bit vectors
757      if (!VT.is128BitVector())
758        continue;
759      setOperationAction(ISD::BUILD_VECTOR,
760                         VT.getSimpleVT().SimpleTy, Custom);
761      setOperationAction(ISD::VECTOR_SHUFFLE,
762                         VT.getSimpleVT().SimpleTy, Custom);
763      setOperationAction(ISD::EXTRACT_VECTOR_ELT,
764                         VT.getSimpleVT().SimpleTy, Custom);
765    }
766
767    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2f64, Custom);
768    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i64, Custom);
769    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2f64, Custom);
770    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i64, Custom);
771    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2f64, Custom);
772    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
773
774    if (Subtarget->is64Bit()) {
775      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);
776      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
777    }
778
779    // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
780    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
781      MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
782      EVT VT = SVT;
783
784      // Do not attempt to promote non-128-bit vectors
785      if (!VT.is128BitVector()) {
786        continue;
787      }
788      setOperationAction(ISD::AND,    SVT, Promote);
789      AddPromotedToType (ISD::AND,    SVT, MVT::v2i64);
790      setOperationAction(ISD::OR,     SVT, Promote);
791      AddPromotedToType (ISD::OR,     SVT, MVT::v2i64);
792      setOperationAction(ISD::XOR,    SVT, Promote);
793      AddPromotedToType (ISD::XOR,    SVT, MVT::v2i64);
794      setOperationAction(ISD::LOAD,   SVT, Promote);
795      AddPromotedToType (ISD::LOAD,   SVT, MVT::v2i64);
796      setOperationAction(ISD::SELECT, SVT, Promote);
797      AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
798    }
799
800    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
801
802    // Custom lower v2i64 and v2f64 selects.
803    setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
804    setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
805    setOperationAction(ISD::SELECT,             MVT::v2f64, Custom);
806    setOperationAction(ISD::SELECT,             MVT::v2i64, Custom);
807
808    setOperationAction(ISD::FP_TO_SINT,         MVT::v4i32, Legal);
809    setOperationAction(ISD::SINT_TO_FP,         MVT::v4i32, Legal);
810    if (!DisableMMX && Subtarget->hasMMX()) {
811      setOperationAction(ISD::FP_TO_SINT,         MVT::v2i32, Custom);
812      setOperationAction(ISD::SINT_TO_FP,         MVT::v2i32, Custom);
813    }
814  }
815
816  if (Subtarget->hasSSE41()) {
817    // FIXME: Do we need to handle scalar-to-vector here?
818    setOperationAction(ISD::MUL,                MVT::v4i32, Legal);
819
820    // i8 and i16 vectors are custom , because the source register and source
821    // source memory operand types are not the same width.  f32 vectors are
822    // custom since the immediate controlling the insert encodes additional
823    // information.
824    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);
825    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
826    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);
827    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);
828
829    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
830    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
831    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
832    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
833
834    if (Subtarget->is64Bit()) {
835      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Legal);
836      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
837    }
838  }
839
840  if (Subtarget->hasSSE42()) {
841    setOperationAction(ISD::VSETCC,             MVT::v2i64, Custom);
842  }
843
844  if (!UseSoftFloat && Subtarget->hasAVX()) {
845    addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
846    addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
847    addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
848    addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
849
850    setOperationAction(ISD::LOAD,               MVT::v8f32, Legal);
851    setOperationAction(ISD::LOAD,               MVT::v8i32, Legal);
852    setOperationAction(ISD::LOAD,               MVT::v4f64, Legal);
853    setOperationAction(ISD::LOAD,               MVT::v4i64, Legal);
854    setOperationAction(ISD::FADD,               MVT::v8f32, Legal);
855    setOperationAction(ISD::FSUB,               MVT::v8f32, Legal);
856    setOperationAction(ISD::FMUL,               MVT::v8f32, Legal);
857    setOperationAction(ISD::FDIV,               MVT::v8f32, Legal);
858    setOperationAction(ISD::FSQRT,              MVT::v8f32, Legal);
859    setOperationAction(ISD::FNEG,               MVT::v8f32, Custom);
860    //setOperationAction(ISD::BUILD_VECTOR,       MVT::v8f32, Custom);
861    //setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8f32, Custom);
862    //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
863    //setOperationAction(ISD::SELECT,             MVT::v8f32, Custom);
864    //setOperationAction(ISD::VSETCC,             MVT::v8f32, Custom);
865
866    // Operations to consider commented out -v16i16 v32i8
867    //setOperationAction(ISD::ADD,                MVT::v16i16, Legal);
868    setOperationAction(ISD::ADD,                MVT::v8i32, Custom);
869    setOperationAction(ISD::ADD,                MVT::v4i64, Custom);
870    //setOperationAction(ISD::SUB,                MVT::v32i8, Legal);
871    //setOperationAction(ISD::SUB,                MVT::v16i16, Legal);
872    setOperationAction(ISD::SUB,                MVT::v8i32, Custom);
873    setOperationAction(ISD::SUB,                MVT::v4i64, Custom);
874    //setOperationAction(ISD::MUL,                MVT::v16i16, Legal);
875    setOperationAction(ISD::FADD,               MVT::v4f64, Legal);
876    setOperationAction(ISD::FSUB,               MVT::v4f64, Legal);
877    setOperationAction(ISD::FMUL,               MVT::v4f64, Legal);
878    setOperationAction(ISD::FDIV,               MVT::v4f64, Legal);
879    setOperationAction(ISD::FSQRT,              MVT::v4f64, Legal);
880    setOperationAction(ISD::FNEG,               MVT::v4f64, Custom);
881
882    setOperationAction(ISD::VSETCC,             MVT::v4f64, Custom);
883    // setOperationAction(ISD::VSETCC,             MVT::v32i8, Custom);
884    // setOperationAction(ISD::VSETCC,             MVT::v16i16, Custom);
885    setOperationAction(ISD::VSETCC,             MVT::v8i32, Custom);
886
887    // setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v32i8, Custom);
888    // setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i16, Custom);
889    // setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i16, Custom);
890    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i32, Custom);
891    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8f32, Custom);
892
893    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4f64, Custom);
894    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i64, Custom);
895    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f64, Custom);
896    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4i64, Custom);
897    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f64, Custom);
898    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
899
900#if 0
901    // Not sure we want to do this since there are no 256-bit integer
902    // operations in AVX
903
904    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
905    // This includes 256-bit vectors
906    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
907      EVT VT = (MVT::SimpleValueType)i;
908
909      // Do not attempt to custom lower non-power-of-2 vectors
910      if (!isPowerOf2_32(VT.getVectorNumElements()))
911        continue;
912
913      setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
914      setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
915      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
916    }
917
918    if (Subtarget->is64Bit()) {
919      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i64, Custom);
920      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
921    }
922#endif
923
924#if 0
925    // Not sure we want to do this since there are no 256-bit integer
926    // operations in AVX
927
928    // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
929    // Including 256-bit vectors
930    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
931      EVT VT = (MVT::SimpleValueType)i;
932
933      if (!VT.is256BitVector()) {
934        continue;
935      }
936      setOperationAction(ISD::AND,    VT, Promote);
937      AddPromotedToType (ISD::AND,    VT, MVT::v4i64);
938      setOperationAction(ISD::OR,     VT, Promote);
939      AddPromotedToType (ISD::OR,     VT, MVT::v4i64);
940      setOperationAction(ISD::XOR,    VT, Promote);
941      AddPromotedToType (ISD::XOR,    VT, MVT::v4i64);
942      setOperationAction(ISD::LOAD,   VT, Promote);
943      AddPromotedToType (ISD::LOAD,   VT, MVT::v4i64);
944      setOperationAction(ISD::SELECT, VT, Promote);
945      AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
946    }
947
948    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
949#endif
950  }
951
952  // We want to custom lower some of our intrinsics.
953  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
954
955  // Add/Sub/Mul with overflow operations are custom lowered.
956  setOperationAction(ISD::SADDO, MVT::i32, Custom);
957  setOperationAction(ISD::SADDO, MVT::i64, Custom);
958  setOperationAction(ISD::UADDO, MVT::i32, Custom);
959  setOperationAction(ISD::UADDO, MVT::i64, Custom);
960  setOperationAction(ISD::SSUBO, MVT::i32, Custom);
961  setOperationAction(ISD::SSUBO, MVT::i64, Custom);
962  setOperationAction(ISD::USUBO, MVT::i32, Custom);
963  setOperationAction(ISD::USUBO, MVT::i64, Custom);
964  setOperationAction(ISD::SMULO, MVT::i32, Custom);
965  setOperationAction(ISD::SMULO, MVT::i64, Custom);
966
967  if (!Subtarget->is64Bit()) {
968    // These libcalls are not available in 32-bit.
969    setLibcallName(RTLIB::SHL_I128, 0);
970    setLibcallName(RTLIB::SRL_I128, 0);
971    setLibcallName(RTLIB::SRA_I128, 0);
972  }
973
974  // We have target-specific dag combine patterns for the following nodes:
975  setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
976  setTargetDAGCombine(ISD::BUILD_VECTOR);
977  setTargetDAGCombine(ISD::SELECT);
978  setTargetDAGCombine(ISD::SHL);
979  setTargetDAGCombine(ISD::SRA);
980  setTargetDAGCombine(ISD::SRL);
981  setTargetDAGCombine(ISD::STORE);
982  setTargetDAGCombine(ISD::MEMBARRIER);
983  if (Subtarget->is64Bit())
984    setTargetDAGCombine(ISD::MUL);
985
986  computeRegisterProperties();
987
988  // Divide and reminder operations have no vector equivalent and can
989  // trap. Do a custom widening for these operations in which we never
990  // generate more divides/remainder than the original vector width.
991  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
992       VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
993    if (!isTypeLegal((MVT::SimpleValueType)VT)) {
994      setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
995      setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
996      setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
997      setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
998    }
999  }
1000
1001  // FIXME: These should be based on subtarget info. Plus, the values should
1002  // be smaller when we are in optimizing for size mode.
1003  maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1004  maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1005  maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1006  setPrefLoopAlignment(16);
1007  benefitFromCodePlacementOpt = true;
1008}
1009
1010
1011MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1012  return MVT::i8;
1013}
1014
1015
1016/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1017/// the desired ByVal argument alignment.
1018static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1019  if (MaxAlign == 16)
1020    return;
1021  if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1022    if (VTy->getBitWidth() == 128)
1023      MaxAlign = 16;
1024  } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1025    unsigned EltAlign = 0;
1026    getMaxByValAlign(ATy->getElementType(), EltAlign);
1027    if (EltAlign > MaxAlign)
1028      MaxAlign = EltAlign;
1029  } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1030    for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1031      unsigned EltAlign = 0;
1032      getMaxByValAlign(STy->getElementType(i), EltAlign);
1033      if (EltAlign > MaxAlign)
1034        MaxAlign = EltAlign;
1035      if (MaxAlign == 16)
1036        break;
1037    }
1038  }
1039  return;
1040}
1041
1042/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1043/// function arguments in the caller parameter area. For X86, aggregates
1044/// that contain SSE vectors are placed at 16-byte boundaries while the rest
1045/// are at 4-byte boundaries.
1046unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1047  if (Subtarget->is64Bit()) {
1048    // Max of 8 and alignment of type.
1049    unsigned TyAlign = TD->getABITypeAlignment(Ty);
1050    if (TyAlign > 8)
1051      return TyAlign;
1052    return 8;
1053  }
1054
1055  unsigned Align = 4;
1056  if (Subtarget->hasSSE1())
1057    getMaxByValAlign(Ty, Align);
1058  return Align;
1059}
1060
1061/// getOptimalMemOpType - Returns the target specific optimal type for load
1062/// and store operations as a result of memset, memcpy, and memmove
1063/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1064/// determining it.
1065EVT
1066X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1067                                       bool isSrcConst, bool isSrcStr,
1068                                       SelectionDAG &DAG) const {
1069  // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1070  // linux.  This is because the stack realignment code can't handle certain
1071  // cases like PR2962.  This should be removed when PR2962 is fixed.
1072  const Function *F = DAG.getMachineFunction().getFunction();
1073  bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1074  if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1075    if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1076      return MVT::v4i32;
1077    if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1078      return MVT::v4f32;
1079  }
1080  if (Subtarget->is64Bit() && Size >= 8)
1081    return MVT::i64;
1082  return MVT::i32;
1083}
1084
1085/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1086/// jumptable.
1087SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1088                                                      SelectionDAG &DAG) const {
1089  if (usesGlobalOffsetTable())
1090    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1091  if (!Subtarget->is64Bit())
1092    // This doesn't have DebugLoc associated with it, but is not really the
1093    // same as a Register.
1094    return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1095                       getPointerTy());
1096  return Table;
1097}
1098
1099/// getFunctionAlignment - Return the Log2 alignment of this function.
1100unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1101  return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1102}
1103
1104//===----------------------------------------------------------------------===//
1105//               Return Value Calling Convention Implementation
1106//===----------------------------------------------------------------------===//
1107
1108#include "X86GenCallingConv.inc"
1109
1110bool
1111X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1112                        const SmallVectorImpl<EVT> &OutTys,
1113                        const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1114                        SelectionDAG &DAG) {
1115  SmallVector<CCValAssign, 16> RVLocs;
1116  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1117                 RVLocs, *DAG.getContext());
1118  return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1119}
1120
1121SDValue
1122X86TargetLowering::LowerReturn(SDValue Chain,
1123                               CallingConv::ID CallConv, bool isVarArg,
1124                               const SmallVectorImpl<ISD::OutputArg> &Outs,
1125                               DebugLoc dl, SelectionDAG &DAG) {
1126
1127  SmallVector<CCValAssign, 16> RVLocs;
1128  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1129                 RVLocs, *DAG.getContext());
1130  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1131
1132  // If this is the first return lowered for this function, add the regs to the
1133  // liveout set for the function.
1134  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1135    for (unsigned i = 0; i != RVLocs.size(); ++i)
1136      if (RVLocs[i].isRegLoc())
1137        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1138  }
1139
1140  SDValue Flag;
1141
1142  SmallVector<SDValue, 6> RetOps;
1143  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1144  // Operand #1 = Bytes To Pop
1145  RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1146
1147  // Copy the result values into the output registers.
1148  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1149    CCValAssign &VA = RVLocs[i];
1150    assert(VA.isRegLoc() && "Can only return in registers!");
1151    SDValue ValToCopy = Outs[i].Val;
1152
1153    // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1154    // the RET instruction and handled by the FP Stackifier.
1155    if (VA.getLocReg() == X86::ST0 ||
1156        VA.getLocReg() == X86::ST1) {
1157      // If this is a copy from an xmm register to ST(0), use an FPExtend to
1158      // change the value to the FP stack register class.
1159      if (isScalarFPTypeInSSEReg(VA.getValVT()))
1160        ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1161      RetOps.push_back(ValToCopy);
1162      // Don't emit a copytoreg.
1163      continue;
1164    }
1165
1166    // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1167    // which is returned in RAX / RDX.
1168    if (Subtarget->is64Bit()) {
1169      EVT ValVT = ValToCopy.getValueType();
1170      if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1171        ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1172        if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1173          ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1174      }
1175    }
1176
1177    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1178    Flag = Chain.getValue(1);
1179  }
1180
1181  // The x86-64 ABI for returning structs by value requires that we copy
1182  // the sret argument into %rax for the return. We saved the argument into
1183  // a virtual register in the entry block, so now we copy the value out
1184  // and into %rax.
1185  if (Subtarget->is64Bit() &&
1186      DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1187    MachineFunction &MF = DAG.getMachineFunction();
1188    X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1189    unsigned Reg = FuncInfo->getSRetReturnReg();
1190    if (!Reg) {
1191      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1192      FuncInfo->setSRetReturnReg(Reg);
1193    }
1194    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1195
1196    Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1197    Flag = Chain.getValue(1);
1198
1199    // RAX now acts like a return value.
1200    MF.getRegInfo().addLiveOut(X86::RAX);
1201  }
1202
1203  RetOps[0] = Chain;  // Update chain.
1204
1205  // Add the flag if we have it.
1206  if (Flag.getNode())
1207    RetOps.push_back(Flag);
1208
1209  return DAG.getNode(X86ISD::RET_FLAG, dl,
1210                     MVT::Other, &RetOps[0], RetOps.size());
1211}
1212
1213/// LowerCallResult - Lower the result values of a call into the
1214/// appropriate copies out of appropriate physical registers.
1215///
1216SDValue
1217X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1218                                   CallingConv::ID CallConv, bool isVarArg,
1219                                   const SmallVectorImpl<ISD::InputArg> &Ins,
1220                                   DebugLoc dl, SelectionDAG &DAG,
1221                                   SmallVectorImpl<SDValue> &InVals) {
1222
1223  // Assign locations to each value returned by this call.
1224  SmallVector<CCValAssign, 16> RVLocs;
1225  bool Is64Bit = Subtarget->is64Bit();
1226  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1227                 RVLocs, *DAG.getContext());
1228  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1229
1230  // Copy all of the result registers out of their specified physreg.
1231  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1232    CCValAssign &VA = RVLocs[i];
1233    EVT CopyVT = VA.getValVT();
1234
1235    // If this is x86-64, and we disabled SSE, we can't return FP values
1236    if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1237        ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1238      llvm_report_error("SSE register return with SSE disabled");
1239    }
1240
1241    // If this is a call to a function that returns an fp value on the floating
1242    // point stack, but where we prefer to use the value in xmm registers, copy
1243    // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1244    if ((VA.getLocReg() == X86::ST0 ||
1245         VA.getLocReg() == X86::ST1) &&
1246        isScalarFPTypeInSSEReg(VA.getValVT())) {
1247      CopyVT = MVT::f80;
1248    }
1249
1250    SDValue Val;
1251    if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1252      // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1253      if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1254        Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1255                                   MVT::v2i64, InFlag).getValue(1);
1256        Val = Chain.getValue(0);
1257        Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1258                          Val, DAG.getConstant(0, MVT::i64));
1259      } else {
1260        Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1261                                   MVT::i64, InFlag).getValue(1);
1262        Val = Chain.getValue(0);
1263      }
1264      Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1265    } else {
1266      Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1267                                 CopyVT, InFlag).getValue(1);
1268      Val = Chain.getValue(0);
1269    }
1270    InFlag = Chain.getValue(2);
1271
1272    if (CopyVT != VA.getValVT()) {
1273      // Round the F80 the right size, which also moves to the appropriate xmm
1274      // register.
1275      Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1276                        // This truncation won't change the value.
1277                        DAG.getIntPtrConstant(1));
1278    }
1279
1280    InVals.push_back(Val);
1281  }
1282
1283  return Chain;
1284}
1285
1286
1287//===----------------------------------------------------------------------===//
1288//                C & StdCall & Fast Calling Convention implementation
1289//===----------------------------------------------------------------------===//
1290//  StdCall calling convention seems to be standard for many Windows' API
1291//  routines and around. It differs from C calling convention just a little:
1292//  callee should clean up the stack, not caller. Symbols should be also
1293//  decorated in some fancy way :) It doesn't support any vector arguments.
1294//  For info on fast calling convention see Fast Calling Convention (tail call)
1295//  implementation LowerX86_32FastCCCallTo.
1296
1297/// CallIsStructReturn - Determines whether a call uses struct return
1298/// semantics.
1299static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1300  if (Outs.empty())
1301    return false;
1302
1303  return Outs[0].Flags.isSRet();
1304}
1305
1306/// ArgsAreStructReturn - Determines whether a function uses struct
1307/// return semantics.
1308static bool
1309ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1310  if (Ins.empty())
1311    return false;
1312
1313  return Ins[0].Flags.isSRet();
1314}
1315
1316/// IsCalleePop - Determines whether the callee is required to pop its
1317/// own arguments. Callee pop is necessary to support tail calls.
1318bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1319  if (IsVarArg)
1320    return false;
1321
1322  switch (CallingConv) {
1323  default:
1324    return false;
1325  case CallingConv::X86_StdCall:
1326    return !Subtarget->is64Bit();
1327  case CallingConv::X86_FastCall:
1328    return !Subtarget->is64Bit();
1329  case CallingConv::Fast:
1330    return PerformTailCallOpt;
1331  }
1332}
1333
1334/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1335/// given CallingConvention value.
1336CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1337  if (Subtarget->is64Bit()) {
1338    if (Subtarget->isTargetWin64())
1339      return CC_X86_Win64_C;
1340    else
1341      return CC_X86_64_C;
1342  }
1343
1344  if (CC == CallingConv::X86_FastCall)
1345    return CC_X86_32_FastCall;
1346  else if (CC == CallingConv::Fast)
1347    return CC_X86_32_FastCC;
1348  else
1349    return CC_X86_32_C;
1350}
1351
1352/// NameDecorationForCallConv - Selects the appropriate decoration to
1353/// apply to a MachineFunction containing a given calling convention.
1354NameDecorationStyle
1355X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1356  if (CallConv == CallingConv::X86_FastCall)
1357    return FastCall;
1358  else if (CallConv == CallingConv::X86_StdCall)
1359    return StdCall;
1360  return None;
1361}
1362
1363
1364/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1365/// by "Src" to address "Dst" with size and alignment information specified by
1366/// the specific parameter attribute. The copy will be passed as a byval
1367/// function parameter.
1368static SDValue
1369CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1370                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1371                          DebugLoc dl) {
1372  SDValue SizeNode     = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1373  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1374                       /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1375}
1376
1377SDValue
1378X86TargetLowering::LowerMemArgument(SDValue Chain,
1379                                    CallingConv::ID CallConv,
1380                                    const SmallVectorImpl<ISD::InputArg> &Ins,
1381                                    DebugLoc dl, SelectionDAG &DAG,
1382                                    const CCValAssign &VA,
1383                                    MachineFrameInfo *MFI,
1384                                    unsigned i) {
1385
1386  // Create the nodes corresponding to a load from this parameter slot.
1387  ISD::ArgFlagsTy Flags = Ins[i].Flags;
1388  bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1389  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1390  EVT ValVT;
1391
1392  // If value is passed by pointer we have address passed instead of the value
1393  // itself.
1394  if (VA.getLocInfo() == CCValAssign::Indirect)
1395    ValVT = VA.getLocVT();
1396  else
1397    ValVT = VA.getValVT();
1398
1399  // FIXME: For now, all byval parameter objects are marked mutable. This can be
1400  // changed with more analysis.
1401  // In case of tail call optimization mark all arguments mutable. Since they
1402  // could be overwritten by lowering of arguments in case of a tail call.
1403  int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1404                                  VA.getLocMemOffset(), isImmutable, false);
1405  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1406  if (Flags.isByVal())
1407    return FIN;
1408  return DAG.getLoad(ValVT, dl, Chain, FIN,
1409                     PseudoSourceValue::getFixedStack(FI), 0);
1410}
1411
1412SDValue
1413X86TargetLowering::LowerFormalArguments(SDValue Chain,
1414                                        CallingConv::ID CallConv,
1415                                        bool isVarArg,
1416                                      const SmallVectorImpl<ISD::InputArg> &Ins,
1417                                        DebugLoc dl,
1418                                        SelectionDAG &DAG,
1419                                        SmallVectorImpl<SDValue> &InVals) {
1420
1421  MachineFunction &MF = DAG.getMachineFunction();
1422  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1423
1424  const Function* Fn = MF.getFunction();
1425  if (Fn->hasExternalLinkage() &&
1426      Subtarget->isTargetCygMing() &&
1427      Fn->getName() == "main")
1428    FuncInfo->setForceFramePointer(true);
1429
1430  // Decorate the function name.
1431  FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1432
1433  MachineFrameInfo *MFI = MF.getFrameInfo();
1434  bool Is64Bit = Subtarget->is64Bit();
1435  bool IsWin64 = Subtarget->isTargetWin64();
1436
1437  assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1438         "Var args not supported with calling convention fastcc");
1439
1440  // Assign locations to all of the incoming arguments.
1441  SmallVector<CCValAssign, 16> ArgLocs;
1442  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1443                 ArgLocs, *DAG.getContext());
1444  CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1445
1446  unsigned LastVal = ~0U;
1447  SDValue ArgValue;
1448  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1449    CCValAssign &VA = ArgLocs[i];
1450    // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1451    // places.
1452    assert(VA.getValNo() != LastVal &&
1453           "Don't support value assigned to multiple locs yet");
1454    LastVal = VA.getValNo();
1455
1456    if (VA.isRegLoc()) {
1457      EVT RegVT = VA.getLocVT();
1458      TargetRegisterClass *RC = NULL;
1459      if (RegVT == MVT::i32)
1460        RC = X86::GR32RegisterClass;
1461      else if (Is64Bit && RegVT == MVT::i64)
1462        RC = X86::GR64RegisterClass;
1463      else if (RegVT == MVT::f32)
1464        RC = X86::FR32RegisterClass;
1465      else if (RegVT == MVT::f64)
1466        RC = X86::FR64RegisterClass;
1467      else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1468        RC = X86::VR128RegisterClass;
1469      else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1470        RC = X86::VR64RegisterClass;
1471      else
1472        llvm_unreachable("Unknown argument type!");
1473
1474      unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1475      ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1476
1477      // If this is an 8 or 16-bit value, it is really passed promoted to 32
1478      // bits.  Insert an assert[sz]ext to capture this, then truncate to the
1479      // right size.
1480      if (VA.getLocInfo() == CCValAssign::SExt)
1481        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1482                               DAG.getValueType(VA.getValVT()));
1483      else if (VA.getLocInfo() == CCValAssign::ZExt)
1484        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1485                               DAG.getValueType(VA.getValVT()));
1486      else if (VA.getLocInfo() == CCValAssign::BCvt)
1487        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1488
1489      if (VA.isExtInLoc()) {
1490        // Handle MMX values passed in XMM regs.
1491        if (RegVT.isVector()) {
1492          ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1493                                 ArgValue, DAG.getConstant(0, MVT::i64));
1494          ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1495        } else
1496          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1497      }
1498    } else {
1499      assert(VA.isMemLoc());
1500      ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1501    }
1502
1503    // If value is passed via pointer - do a load.
1504    if (VA.getLocInfo() == CCValAssign::Indirect)
1505      ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1506
1507    InVals.push_back(ArgValue);
1508  }
1509
1510  // The x86-64 ABI for returning structs by value requires that we copy
1511  // the sret argument into %rax for the return. Save the argument into
1512  // a virtual register so that we can access it from the return points.
1513  if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1514    X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1515    unsigned Reg = FuncInfo->getSRetReturnReg();
1516    if (!Reg) {
1517      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1518      FuncInfo->setSRetReturnReg(Reg);
1519    }
1520    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1521    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1522  }
1523
1524  unsigned StackSize = CCInfo.getNextStackOffset();
1525  // align stack specially for tail calls
1526  if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1527    StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1528
1529  // If the function takes variable number of arguments, make a frame index for
1530  // the start of the first vararg value... for expansion of llvm.va_start.
1531  if (isVarArg) {
1532    if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1533      VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1534    }
1535    if (Is64Bit) {
1536      unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1537
1538      // FIXME: We should really autogenerate these arrays
1539      static const unsigned GPR64ArgRegsWin64[] = {
1540        X86::RCX, X86::RDX, X86::R8,  X86::R9
1541      };
1542      static const unsigned XMMArgRegsWin64[] = {
1543        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1544      };
1545      static const unsigned GPR64ArgRegs64Bit[] = {
1546        X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1547      };
1548      static const unsigned XMMArgRegs64Bit[] = {
1549        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1550        X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1551      };
1552      const unsigned *GPR64ArgRegs, *XMMArgRegs;
1553
1554      if (IsWin64) {
1555        TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1556        GPR64ArgRegs = GPR64ArgRegsWin64;
1557        XMMArgRegs = XMMArgRegsWin64;
1558      } else {
1559        TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1560        GPR64ArgRegs = GPR64ArgRegs64Bit;
1561        XMMArgRegs = XMMArgRegs64Bit;
1562      }
1563      unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1564                                                       TotalNumIntRegs);
1565      unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1566                                                       TotalNumXMMRegs);
1567
1568      bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1569      assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1570             "SSE register cannot be used when SSE is disabled!");
1571      assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1572             "SSE register cannot be used when SSE is disabled!");
1573      if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1574        // Kernel mode asks for SSE to be disabled, so don't push them
1575        // on the stack.
1576        TotalNumXMMRegs = 0;
1577
1578      // For X86-64, if there are vararg parameters that are passed via
1579      // registers, then we must store them to their spots on the stack so they
1580      // may be loaded by deferencing the result of va_next.
1581      VarArgsGPOffset = NumIntRegs * 8;
1582      VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1583      RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1584                                                 TotalNumXMMRegs * 16, 16,
1585                                                 false);
1586
1587      // Store the integer parameter registers.
1588      SmallVector<SDValue, 8> MemOps;
1589      SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1590      unsigned Offset = VarArgsGPOffset;
1591      for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1592        SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1593                                  DAG.getIntPtrConstant(Offset));
1594        unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1595                                     X86::GR64RegisterClass);
1596        SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1597        SDValue Store =
1598          DAG.getStore(Val.getValue(1), dl, Val, FIN,
1599                       PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1600                       Offset);
1601        MemOps.push_back(Store);
1602        Offset += 8;
1603      }
1604
1605      if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1606        // Now store the XMM (fp + vector) parameter registers.
1607        SmallVector<SDValue, 11> SaveXMMOps;
1608        SaveXMMOps.push_back(Chain);
1609
1610        unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1611        SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1612        SaveXMMOps.push_back(ALVal);
1613
1614        SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1615        SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1616
1617        for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1618          unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1619                                       X86::VR128RegisterClass);
1620          SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1621          SaveXMMOps.push_back(Val);
1622        }
1623        MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1624                                     MVT::Other,
1625                                     &SaveXMMOps[0], SaveXMMOps.size()));
1626      }
1627
1628      if (!MemOps.empty())
1629        Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1630                            &MemOps[0], MemOps.size());
1631    }
1632  }
1633
1634  // Some CCs need callee pop.
1635  if (IsCalleePop(isVarArg, CallConv)) {
1636    BytesToPopOnReturn  = StackSize; // Callee pops everything.
1637    BytesCallerReserves = 0;
1638  } else {
1639    BytesToPopOnReturn  = 0; // Callee pops nothing.
1640    // If this is an sret function, the return should pop the hidden pointer.
1641    if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1642      BytesToPopOnReturn = 4;
1643    BytesCallerReserves = StackSize;
1644  }
1645
1646  if (!Is64Bit) {
1647    RegSaveFrameIndex = 0xAAAAAAA;   // RegSaveFrameIndex is X86-64 only.
1648    if (CallConv == CallingConv::X86_FastCall)
1649      VarArgsFrameIndex = 0xAAAAAAA;   // fastcc functions can't have varargs.
1650  }
1651
1652  FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1653
1654  return Chain;
1655}
1656
1657SDValue
1658X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1659                                    SDValue StackPtr, SDValue Arg,
1660                                    DebugLoc dl, SelectionDAG &DAG,
1661                                    const CCValAssign &VA,
1662                                    ISD::ArgFlagsTy Flags) {
1663  const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1664  unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1665  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1666  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1667  if (Flags.isByVal()) {
1668    return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1669  }
1670  return DAG.getStore(Chain, dl, Arg, PtrOff,
1671                      PseudoSourceValue::getStack(), LocMemOffset);
1672}
1673
1674/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1675/// optimization is performed and it is required.
1676SDValue
1677X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1678                                           SDValue &OutRetAddr,
1679                                           SDValue Chain,
1680                                           bool IsTailCall,
1681                                           bool Is64Bit,
1682                                           int FPDiff,
1683                                           DebugLoc dl) {
1684  if (!IsTailCall || FPDiff==0) return Chain;
1685
1686  // Adjust the Return address stack slot.
1687  EVT VT = getPointerTy();
1688  OutRetAddr = getReturnAddressFrameIndex(DAG);
1689
1690  // Load the "old" Return address.
1691  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1692  return SDValue(OutRetAddr.getNode(), 1);
1693}
1694
1695/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1696/// optimization is performed and it is required (FPDiff!=0).
1697static SDValue
1698EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1699                         SDValue Chain, SDValue RetAddrFrIdx,
1700                         bool Is64Bit, int FPDiff, DebugLoc dl) {
1701  // Store the return address to the appropriate stack slot.
1702  if (!FPDiff) return Chain;
1703  // Calculate the new stack slot for the return address.
1704  int SlotSize = Is64Bit ? 8 : 4;
1705  int NewReturnAddrFI =
1706    MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1707                                         true, false);
1708  EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1709  SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1710  Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1711                       PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1712  return Chain;
1713}
1714
1715SDValue
1716X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1717                             CallingConv::ID CallConv, bool isVarArg,
1718                             bool isTailCall,
1719                             const SmallVectorImpl<ISD::OutputArg> &Outs,
1720                             const SmallVectorImpl<ISD::InputArg> &Ins,
1721                             DebugLoc dl, SelectionDAG &DAG,
1722                             SmallVectorImpl<SDValue> &InVals) {
1723
1724  MachineFunction &MF = DAG.getMachineFunction();
1725  bool Is64Bit        = Subtarget->is64Bit();
1726  bool IsStructRet    = CallIsStructReturn(Outs);
1727
1728  assert((!isTailCall ||
1729          (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1730         "IsEligibleForTailCallOptimization missed a case!");
1731  assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1732         "Var args not supported with calling convention fastcc");
1733
1734  // Analyze operands of the call, assigning locations to each operand.
1735  SmallVector<CCValAssign, 16> ArgLocs;
1736  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1737                 ArgLocs, *DAG.getContext());
1738  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1739
1740  // Get a count of how many bytes are to be pushed on the stack.
1741  unsigned NumBytes = CCInfo.getNextStackOffset();
1742  if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1743    NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1744
1745  int FPDiff = 0;
1746  if (isTailCall) {
1747    // Lower arguments at fp - stackoffset + fpdiff.
1748    unsigned NumBytesCallerPushed =
1749      MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1750    FPDiff = NumBytesCallerPushed - NumBytes;
1751
1752    // Set the delta of movement of the returnaddr stackslot.
1753    // But only set if delta is greater than previous delta.
1754    if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1755      MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1756  }
1757
1758  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1759
1760  SDValue RetAddrFrIdx;
1761  // Load return adress for tail calls.
1762  Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1763                                  FPDiff, dl);
1764
1765  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1766  SmallVector<SDValue, 8> MemOpChains;
1767  SDValue StackPtr;
1768
1769  // Walk the register/memloc assignments, inserting copies/loads.  In the case
1770  // of tail call optimization arguments are handle later.
1771  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1772    CCValAssign &VA = ArgLocs[i];
1773    EVT RegVT = VA.getLocVT();
1774    SDValue Arg = Outs[i].Val;
1775    ISD::ArgFlagsTy Flags = Outs[i].Flags;
1776    bool isByVal = Flags.isByVal();
1777
1778    // Promote the value if needed.
1779    switch (VA.getLocInfo()) {
1780    default: llvm_unreachable("Unknown loc info!");
1781    case CCValAssign::Full: break;
1782    case CCValAssign::SExt:
1783      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1784      break;
1785    case CCValAssign::ZExt:
1786      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1787      break;
1788    case CCValAssign::AExt:
1789      if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1790        // Special case: passing MMX values in XMM registers.
1791        Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1792        Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1793        Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1794      } else
1795        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1796      break;
1797    case CCValAssign::BCvt:
1798      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1799      break;
1800    case CCValAssign::Indirect: {
1801      // Store the argument.
1802      SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1803      int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1804      Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1805                           PseudoSourceValue::getFixedStack(FI), 0);
1806      Arg = SpillSlot;
1807      break;
1808    }
1809    }
1810
1811    if (VA.isRegLoc()) {
1812      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1813    } else {
1814      if (!isTailCall || (isTailCall && isByVal)) {
1815        assert(VA.isMemLoc());
1816        if (StackPtr.getNode() == 0)
1817          StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1818
1819        MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1820                                               dl, DAG, VA, Flags));
1821      }
1822    }
1823  }
1824
1825  if (!MemOpChains.empty())
1826    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1827                        &MemOpChains[0], MemOpChains.size());
1828
1829  // Build a sequence of copy-to-reg nodes chained together with token chain
1830  // and flag operands which copy the outgoing args into registers.
1831  SDValue InFlag;
1832  // Tail call byval lowering might overwrite argument registers so in case of
1833  // tail call optimization the copies to registers are lowered later.
1834  if (!isTailCall)
1835    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1836      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1837                               RegsToPass[i].second, InFlag);
1838      InFlag = Chain.getValue(1);
1839    }
1840
1841
1842  if (Subtarget->isPICStyleGOT()) {
1843    // ELF / PIC requires GOT in the EBX register before function calls via PLT
1844    // GOT pointer.
1845    if (!isTailCall) {
1846      Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1847                               DAG.getNode(X86ISD::GlobalBaseReg,
1848                                           DebugLoc::getUnknownLoc(),
1849                                           getPointerTy()),
1850                               InFlag);
1851      InFlag = Chain.getValue(1);
1852    } else {
1853      // If we are tail calling and generating PIC/GOT style code load the
1854      // address of the callee into ECX. The value in ecx is used as target of
1855      // the tail jump. This is done to circumvent the ebx/callee-saved problem
1856      // for tail calls on PIC/GOT architectures. Normally we would just put the
1857      // address of GOT into ebx and then call target@PLT. But for tail calls
1858      // ebx would be restored (since ebx is callee saved) before jumping to the
1859      // target@PLT.
1860
1861      // Note: The actual moving to ECX is done further down.
1862      GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1863      if (G && !G->getGlobal()->hasHiddenVisibility() &&
1864          !G->getGlobal()->hasProtectedVisibility())
1865        Callee = LowerGlobalAddress(Callee, DAG);
1866      else if (isa<ExternalSymbolSDNode>(Callee))
1867        Callee = LowerExternalSymbol(Callee, DAG);
1868    }
1869  }
1870
1871  if (Is64Bit && isVarArg) {
1872    // From AMD64 ABI document:
1873    // For calls that may call functions that use varargs or stdargs
1874    // (prototype-less calls or calls to functions containing ellipsis (...) in
1875    // the declaration) %al is used as hidden argument to specify the number
1876    // of SSE registers used. The contents of %al do not need to match exactly
1877    // the number of registers, but must be an ubound on the number of SSE
1878    // registers used and is in the range 0 - 8 inclusive.
1879
1880    // FIXME: Verify this on Win64
1881    // Count the number of XMM registers allocated.
1882    static const unsigned XMMArgRegs[] = {
1883      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1884      X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1885    };
1886    unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1887    assert((Subtarget->hasSSE1() || !NumXMMRegs)
1888           && "SSE registers cannot be used when SSE is disabled");
1889
1890    Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1891                             DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1892    InFlag = Chain.getValue(1);
1893  }
1894
1895
1896  // For tail calls lower the arguments to the 'real' stack slot.
1897  if (isTailCall) {
1898    // Force all the incoming stack arguments to be loaded from the stack
1899    // before any new outgoing arguments are stored to the stack, because the
1900    // outgoing stack slots may alias the incoming argument stack slots, and
1901    // the alias isn't otherwise explicit. This is slightly more conservative
1902    // than necessary, because it means that each store effectively depends
1903    // on every argument instead of just those arguments it would clobber.
1904    SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1905
1906    SmallVector<SDValue, 8> MemOpChains2;
1907    SDValue FIN;
1908    int FI = 0;
1909    // Do not flag preceeding copytoreg stuff together with the following stuff.
1910    InFlag = SDValue();
1911    for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1912      CCValAssign &VA = ArgLocs[i];
1913      if (!VA.isRegLoc()) {
1914        assert(VA.isMemLoc());
1915        SDValue Arg = Outs[i].Val;
1916        ISD::ArgFlagsTy Flags = Outs[i].Flags;
1917        // Create frame index.
1918        int32_t Offset = VA.getLocMemOffset()+FPDiff;
1919        uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1920        FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1921        FIN = DAG.getFrameIndex(FI, getPointerTy());
1922
1923        if (Flags.isByVal()) {
1924          // Copy relative to framepointer.
1925          SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1926          if (StackPtr.getNode() == 0)
1927            StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1928                                          getPointerTy());
1929          Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1930
1931          MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1932                                                           ArgChain,
1933                                                           Flags, DAG, dl));
1934        } else {
1935          // Store relative to framepointer.
1936          MemOpChains2.push_back(
1937            DAG.getStore(ArgChain, dl, Arg, FIN,
1938                         PseudoSourceValue::getFixedStack(FI), 0));
1939        }
1940      }
1941    }
1942
1943    if (!MemOpChains2.empty())
1944      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1945                          &MemOpChains2[0], MemOpChains2.size());
1946
1947    // Copy arguments to their registers.
1948    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1949      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1950                               RegsToPass[i].second, InFlag);
1951      InFlag = Chain.getValue(1);
1952    }
1953    InFlag =SDValue();
1954
1955    // Store the return address to the appropriate stack slot.
1956    Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1957                                     FPDiff, dl);
1958  }
1959
1960  bool WasGlobalOrExternal = false;
1961  if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1962    assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1963    // In the 64-bit large code model, we have to make all calls
1964    // through a register, since the call instruction's 32-bit
1965    // pc-relative offset may not be large enough to hold the whole
1966    // address.
1967  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1968    WasGlobalOrExternal = true;
1969    // If the callee is a GlobalAddress node (quite common, every direct call
1970    // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1971    // it.
1972
1973    // We should use extra load for direct calls to dllimported functions in
1974    // non-JIT mode.
1975    GlobalValue *GV = G->getGlobal();
1976    if (!GV->hasDLLImportLinkage()) {
1977      unsigned char OpFlags = 0;
1978
1979      // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1980      // external symbols most go through the PLT in PIC mode.  If the symbol
1981      // has hidden or protected visibility, or if it is static or local, then
1982      // we don't need to use the PLT - we can directly call it.
1983      if (Subtarget->isTargetELF() &&
1984          getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1985          GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1986        OpFlags = X86II::MO_PLT;
1987      } else if (Subtarget->isPICStyleStubAny() &&
1988               (GV->isDeclaration() || GV->isWeakForLinker()) &&
1989               Subtarget->getDarwinVers() < 9) {
1990        // PC-relative references to external symbols should go through $stub,
1991        // unless we're building with the leopard linker or later, which
1992        // automatically synthesizes these stubs.
1993        OpFlags = X86II::MO_DARWIN_STUB;
1994      }
1995
1996      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1997                                          G->getOffset(), OpFlags);
1998    }
1999  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2000    WasGlobalOrExternal = true;
2001    unsigned char OpFlags = 0;
2002
2003    // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2004    // symbols should go through the PLT.
2005    if (Subtarget->isTargetELF() &&
2006        getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2007      OpFlags = X86II::MO_PLT;
2008    } else if (Subtarget->isPICStyleStubAny() &&
2009             Subtarget->getDarwinVers() < 9) {
2010      // PC-relative references to external symbols should go through $stub,
2011      // unless we're building with the leopard linker or later, which
2012      // automatically synthesizes these stubs.
2013      OpFlags = X86II::MO_DARWIN_STUB;
2014    }
2015
2016    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2017                                         OpFlags);
2018  }
2019
2020  if (isTailCall && !WasGlobalOrExternal) {
2021    unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2022
2023    Chain = DAG.getCopyToReg(Chain,  dl,
2024                             DAG.getRegister(Opc, getPointerTy()),
2025                             Callee,InFlag);
2026    Callee = DAG.getRegister(Opc, getPointerTy());
2027    // Add register as live out.
2028    MF.getRegInfo().addLiveOut(Opc);
2029  }
2030
2031  // Returns a chain & a flag for retval copy to use.
2032  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2033  SmallVector<SDValue, 8> Ops;
2034
2035  if (isTailCall) {
2036    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2037                           DAG.getIntPtrConstant(0, true), InFlag);
2038    InFlag = Chain.getValue(1);
2039  }
2040
2041  Ops.push_back(Chain);
2042  Ops.push_back(Callee);
2043
2044  if (isTailCall)
2045    Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2046
2047  // Add argument registers to the end of the list so that they are known live
2048  // into the call.
2049  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2050    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2051                                  RegsToPass[i].second.getValueType()));
2052
2053  // Add an implicit use GOT pointer in EBX.
2054  if (!isTailCall && Subtarget->isPICStyleGOT())
2055    Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2056
2057  // Add an implicit use of AL for x86 vararg functions.
2058  if (Is64Bit && isVarArg)
2059    Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2060
2061  if (InFlag.getNode())
2062    Ops.push_back(InFlag);
2063
2064  if (isTailCall) {
2065    // If this is the first return lowered for this function, add the regs
2066    // to the liveout set for the function.
2067    if (MF.getRegInfo().liveout_empty()) {
2068      SmallVector<CCValAssign, 16> RVLocs;
2069      CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2070                     *DAG.getContext());
2071      CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2072      for (unsigned i = 0; i != RVLocs.size(); ++i)
2073        if (RVLocs[i].isRegLoc())
2074          MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2075    }
2076
2077    assert(((Callee.getOpcode() == ISD::Register &&
2078               (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2079                cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2080              Callee.getOpcode() == ISD::TargetExternalSymbol ||
2081              Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2082             "Expecting an global address, external symbol, or register");
2083
2084    return DAG.getNode(X86ISD::TC_RETURN, dl,
2085                       NodeTys, &Ops[0], Ops.size());
2086  }
2087
2088  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2089  InFlag = Chain.getValue(1);
2090
2091  // Create the CALLSEQ_END node.
2092  unsigned NumBytesForCalleeToPush;
2093  if (IsCalleePop(isVarArg, CallConv))
2094    NumBytesForCalleeToPush = NumBytes;    // Callee pops everything
2095  else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2096    // If this is is a call to a struct-return function, the callee
2097    // pops the hidden struct pointer, so we have to push it back.
2098    // This is common for Darwin/X86, Linux & Mingw32 targets.
2099    NumBytesForCalleeToPush = 4;
2100  else
2101    NumBytesForCalleeToPush = 0;  // Callee pops nothing.
2102
2103  // Returns a flag for retval copy to use.
2104  Chain = DAG.getCALLSEQ_END(Chain,
2105                             DAG.getIntPtrConstant(NumBytes, true),
2106                             DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2107                                                   true),
2108                             InFlag);
2109  InFlag = Chain.getValue(1);
2110
2111  // Handle result values, copying them out of physregs into vregs that we
2112  // return.
2113  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2114                         Ins, dl, DAG, InVals);
2115}
2116
2117
2118//===----------------------------------------------------------------------===//
2119//                Fast Calling Convention (tail call) implementation
2120//===----------------------------------------------------------------------===//
2121
2122//  Like std call, callee cleans arguments, convention except that ECX is
2123//  reserved for storing the tail called function address. Only 2 registers are
2124//  free for argument passing (inreg). Tail call optimization is performed
2125//  provided:
2126//                * tailcallopt is enabled
2127//                * caller/callee are fastcc
2128//  On X86_64 architecture with GOT-style position independent code only local
2129//  (within module) calls are supported at the moment.
2130//  To keep the stack aligned according to platform abi the function
2131//  GetAlignedArgumentStackSize ensures that argument delta is always multiples
2132//  of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2133//  If a tail called function callee has more arguments than the caller the
2134//  caller needs to make sure that there is room to move the RETADDR to. This is
2135//  achieved by reserving an area the size of the argument delta right after the
2136//  original REtADDR, but before the saved framepointer or the spilled registers
2137//  e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2138//  stack layout:
2139//    arg1
2140//    arg2
2141//    RETADDR
2142//    [ new RETADDR
2143//      move area ]
2144//    (possible EBP)
2145//    ESI
2146//    EDI
2147//    local1 ..
2148
2149/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2150/// for a 16 byte align requirement.
2151unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2152                                                        SelectionDAG& DAG) {
2153  MachineFunction &MF = DAG.getMachineFunction();
2154  const TargetMachine &TM = MF.getTarget();
2155  const TargetFrameInfo &TFI = *TM.getFrameInfo();
2156  unsigned StackAlignment = TFI.getStackAlignment();
2157  uint64_t AlignMask = StackAlignment - 1;
2158  int64_t Offset = StackSize;
2159  uint64_t SlotSize = TD->getPointerSize();
2160  if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2161    // Number smaller than 12 so just add the difference.
2162    Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2163  } else {
2164    // Mask out lower bits, add stackalignment once plus the 12 bytes.
2165    Offset = ((~AlignMask) & Offset) + StackAlignment +
2166      (StackAlignment-SlotSize);
2167  }
2168  return Offset;
2169}
2170
2171/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2172/// for tail call optimization. Targets which want to do tail call
2173/// optimization should implement this function.
2174bool
2175X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2176                                                     CallingConv::ID CalleeCC,
2177                                                     bool isVarArg,
2178                                      const SmallVectorImpl<ISD::InputArg> &Ins,
2179                                                     SelectionDAG& DAG) const {
2180  MachineFunction &MF = DAG.getMachineFunction();
2181  CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2182  return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2183}
2184
2185FastISel *
2186X86TargetLowering::createFastISel(MachineFunction &mf,
2187                                  MachineModuleInfo *mmo,
2188                                  DwarfWriter *dw,
2189                                  DenseMap<const Value *, unsigned> &vm,
2190                                  DenseMap<const BasicBlock *,
2191                                           MachineBasicBlock *> &bm,
2192                                  DenseMap<const AllocaInst *, int> &am
2193#ifndef NDEBUG
2194                                  , SmallSet<Instruction*, 8> &cil
2195#endif
2196                                  ) {
2197  return X86::createFastISel(mf, mmo, dw, vm, bm, am
2198#ifndef NDEBUG
2199                             , cil
2200#endif
2201                             );
2202}
2203
2204
2205//===----------------------------------------------------------------------===//
2206//                           Other Lowering Hooks
2207//===----------------------------------------------------------------------===//
2208
2209
2210SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2211  MachineFunction &MF = DAG.getMachineFunction();
2212  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2213  int ReturnAddrIndex = FuncInfo->getRAIndex();
2214
2215  if (ReturnAddrIndex == 0) {
2216    // Set up a frame object for the return address.
2217    uint64_t SlotSize = TD->getPointerSize();
2218    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2219                                                           true, false);
2220    FuncInfo->setRAIndex(ReturnAddrIndex);
2221  }
2222
2223  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2224}
2225
2226
2227bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2228                                       bool hasSymbolicDisplacement) {
2229  // Offset should fit into 32 bit immediate field.
2230  if (!isInt32(Offset))
2231    return false;
2232
2233  // If we don't have a symbolic displacement - we don't have any extra
2234  // restrictions.
2235  if (!hasSymbolicDisplacement)
2236    return true;
2237
2238  // FIXME: Some tweaks might be needed for medium code model.
2239  if (M != CodeModel::Small && M != CodeModel::Kernel)
2240    return false;
2241
2242  // For small code model we assume that latest object is 16MB before end of 31
2243  // bits boundary. We may also accept pretty large negative constants knowing
2244  // that all objects are in the positive half of address space.
2245  if (M == CodeModel::Small && Offset < 16*1024*1024)
2246    return true;
2247
2248  // For kernel code model we know that all object resist in the negative half
2249  // of 32bits address space. We may not accept negative offsets, since they may
2250  // be just off and we may accept pretty large positive ones.
2251  if (M == CodeModel::Kernel && Offset > 0)
2252    return true;
2253
2254  return false;
2255}
2256
2257/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2258/// specific condition code, returning the condition code and the LHS/RHS of the
2259/// comparison to make.
2260static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2261                               SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2262  if (!isFP) {
2263    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2264      if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2265        // X > -1   -> X == 0, jump !sign.
2266        RHS = DAG.getConstant(0, RHS.getValueType());
2267        return X86::COND_NS;
2268      } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2269        // X < 0   -> X == 0, jump on sign.
2270        return X86::COND_S;
2271      } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2272        // X < 1   -> X <= 0
2273        RHS = DAG.getConstant(0, RHS.getValueType());
2274        return X86::COND_LE;
2275      }
2276    }
2277
2278    switch (SetCCOpcode) {
2279    default: llvm_unreachable("Invalid integer condition!");
2280    case ISD::SETEQ:  return X86::COND_E;
2281    case ISD::SETGT:  return X86::COND_G;
2282    case ISD::SETGE:  return X86::COND_GE;
2283    case ISD::SETLT:  return X86::COND_L;
2284    case ISD::SETLE:  return X86::COND_LE;
2285    case ISD::SETNE:  return X86::COND_NE;
2286    case ISD::SETULT: return X86::COND_B;
2287    case ISD::SETUGT: return X86::COND_A;
2288    case ISD::SETULE: return X86::COND_BE;
2289    case ISD::SETUGE: return X86::COND_AE;
2290    }
2291  }
2292
2293  // First determine if it is required or is profitable to flip the operands.
2294
2295  // If LHS is a foldable load, but RHS is not, flip the condition.
2296  if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2297      !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2298    SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2299    std::swap(LHS, RHS);
2300  }
2301
2302  switch (SetCCOpcode) {
2303  default: break;
2304  case ISD::SETOLT:
2305  case ISD::SETOLE:
2306  case ISD::SETUGT:
2307  case ISD::SETUGE:
2308    std::swap(LHS, RHS);
2309    break;
2310  }
2311
2312  // On a floating point condition, the flags are set as follows:
2313  // ZF  PF  CF   op
2314  //  0 | 0 | 0 | X > Y
2315  //  0 | 0 | 1 | X < Y
2316  //  1 | 0 | 0 | X == Y
2317  //  1 | 1 | 1 | unordered
2318  switch (SetCCOpcode) {
2319  default: llvm_unreachable("Condcode should be pre-legalized away");
2320  case ISD::SETUEQ:
2321  case ISD::SETEQ:   return X86::COND_E;
2322  case ISD::SETOLT:              // flipped
2323  case ISD::SETOGT:
2324  case ISD::SETGT:   return X86::COND_A;
2325  case ISD::SETOLE:              // flipped
2326  case ISD::SETOGE:
2327  case ISD::SETGE:   return X86::COND_AE;
2328  case ISD::SETUGT:              // flipped
2329  case ISD::SETULT:
2330  case ISD::SETLT:   return X86::COND_B;
2331  case ISD::SETUGE:              // flipped
2332  case ISD::SETULE:
2333  case ISD::SETLE:   return X86::COND_BE;
2334  case ISD::SETONE:
2335  case ISD::SETNE:   return X86::COND_NE;
2336  case ISD::SETUO:   return X86::COND_P;
2337  case ISD::SETO:    return X86::COND_NP;
2338  case ISD::SETOEQ:
2339  case ISD::SETUNE:  return X86::COND_INVALID;
2340  }
2341}
2342
2343/// hasFPCMov - is there a floating point cmov for the specific X86 condition
2344/// code. Current x86 isa includes the following FP cmov instructions:
2345/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2346static bool hasFPCMov(unsigned X86CC) {
2347  switch (X86CC) {
2348  default:
2349    return false;
2350  case X86::COND_B:
2351  case X86::COND_BE:
2352  case X86::COND_E:
2353  case X86::COND_P:
2354  case X86::COND_A:
2355  case X86::COND_AE:
2356  case X86::COND_NE:
2357  case X86::COND_NP:
2358    return true;
2359  }
2360}
2361
2362/// isFPImmLegal - Returns true if the target can instruction select the
2363/// specified FP immediate natively. If false, the legalizer will
2364/// materialize the FP immediate as a load from a constant pool.
2365bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2366  for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2367    if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2368      return true;
2369  }
2370  return false;
2371}
2372
2373/// isUndefOrInRange - Return true if Val is undef or if its value falls within
2374/// the specified range (L, H].
2375static bool isUndefOrInRange(int Val, int Low, int Hi) {
2376  return (Val < 0) || (Val >= Low && Val < Hi);
2377}
2378
2379/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2380/// specified value.
2381static bool isUndefOrEqual(int Val, int CmpVal) {
2382  if (Val < 0 || Val == CmpVal)
2383    return true;
2384  return false;
2385}
2386
2387/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2388/// is suitable for input to PSHUFD or PSHUFW.  That is, it doesn't reference
2389/// the second operand.
2390static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2391  if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2392    return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2393  if (VT == MVT::v2f64 || VT == MVT::v2i64)
2394    return (Mask[0] < 2 && Mask[1] < 2);
2395  return false;
2396}
2397
2398bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2399  SmallVector<int, 8> M;
2400  N->getMask(M);
2401  return ::isPSHUFDMask(M, N->getValueType(0));
2402}
2403
2404/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2405/// is suitable for input to PSHUFHW.
2406static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2407  if (VT != MVT::v8i16)
2408    return false;
2409
2410  // Lower quadword copied in order or undef.
2411  for (int i = 0; i != 4; ++i)
2412    if (Mask[i] >= 0 && Mask[i] != i)
2413      return false;
2414
2415  // Upper quadword shuffled.
2416  for (int i = 4; i != 8; ++i)
2417    if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2418      return false;
2419
2420  return true;
2421}
2422
2423bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2424  SmallVector<int, 8> M;
2425  N->getMask(M);
2426  return ::isPSHUFHWMask(M, N->getValueType(0));
2427}
2428
2429/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2430/// is suitable for input to PSHUFLW.
2431static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2432  if (VT != MVT::v8i16)
2433    return false;
2434
2435  // Upper quadword copied in order.
2436  for (int i = 4; i != 8; ++i)
2437    if (Mask[i] >= 0 && Mask[i] != i)
2438      return false;
2439
2440  // Lower quadword shuffled.
2441  for (int i = 0; i != 4; ++i)
2442    if (Mask[i] >= 4)
2443      return false;
2444
2445  return true;
2446}
2447
2448bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2449  SmallVector<int, 8> M;
2450  N->getMask(M);
2451  return ::isPSHUFLWMask(M, N->getValueType(0));
2452}
2453
2454/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2455/// is suitable for input to PALIGNR.
2456static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2457                          bool hasSSSE3) {
2458  int i, e = VT.getVectorNumElements();
2459
2460  // Do not handle v2i64 / v2f64 shuffles with palignr.
2461  if (e < 4 || !hasSSSE3)
2462    return false;
2463
2464  for (i = 0; i != e; ++i)
2465    if (Mask[i] >= 0)
2466      break;
2467
2468  // All undef, not a palignr.
2469  if (i == e)
2470    return false;
2471
2472  // Determine if it's ok to perform a palignr with only the LHS, since we
2473  // don't have access to the actual shuffle elements to see if RHS is undef.
2474  bool Unary = Mask[i] < (int)e;
2475  bool NeedsUnary = false;
2476
2477  int s = Mask[i] - i;
2478
2479  // Check the rest of the elements to see if they are consecutive.
2480  for (++i; i != e; ++i) {
2481    int m = Mask[i];
2482    if (m < 0)
2483      continue;
2484
2485    Unary = Unary && (m < (int)e);
2486    NeedsUnary = NeedsUnary || (m < s);
2487
2488    if (NeedsUnary && !Unary)
2489      return false;
2490    if (Unary && m != ((s+i) & (e-1)))
2491      return false;
2492    if (!Unary && m != (s+i))
2493      return false;
2494  }
2495  return true;
2496}
2497
2498bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2499  SmallVector<int, 8> M;
2500  N->getMask(M);
2501  return ::isPALIGNRMask(M, N->getValueType(0), true);
2502}
2503
2504/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2505/// specifies a shuffle of elements that is suitable for input to SHUFP*.
2506static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2507  int NumElems = VT.getVectorNumElements();
2508  if (NumElems != 2 && NumElems != 4)
2509    return false;
2510
2511  int Half = NumElems / 2;
2512  for (int i = 0; i < Half; ++i)
2513    if (!isUndefOrInRange(Mask[i], 0, NumElems))
2514      return false;
2515  for (int i = Half; i < NumElems; ++i)
2516    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2517      return false;
2518
2519  return true;
2520}
2521
2522bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2523  SmallVector<int, 8> M;
2524  N->getMask(M);
2525  return ::isSHUFPMask(M, N->getValueType(0));
2526}
2527
2528/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2529/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2530/// half elements to come from vector 1 (which would equal the dest.) and
2531/// the upper half to come from vector 2.
2532static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2533  int NumElems = VT.getVectorNumElements();
2534
2535  if (NumElems != 2 && NumElems != 4)
2536    return false;
2537
2538  int Half = NumElems / 2;
2539  for (int i = 0; i < Half; ++i)
2540    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2541      return false;
2542  for (int i = Half; i < NumElems; ++i)
2543    if (!isUndefOrInRange(Mask[i], 0, NumElems))
2544      return false;
2545  return true;
2546}
2547
2548static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2549  SmallVector<int, 8> M;
2550  N->getMask(M);
2551  return isCommutedSHUFPMask(M, N->getValueType(0));
2552}
2553
2554/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2555/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2556bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2557  if (N->getValueType(0).getVectorNumElements() != 4)
2558    return false;
2559
2560  // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2561  return isUndefOrEqual(N->getMaskElt(0), 6) &&
2562         isUndefOrEqual(N->getMaskElt(1), 7) &&
2563         isUndefOrEqual(N->getMaskElt(2), 2) &&
2564         isUndefOrEqual(N->getMaskElt(3), 3);
2565}
2566
2567/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2568/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2569/// <2, 3, 2, 3>
2570bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2571  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2572
2573  if (NumElems != 4)
2574    return false;
2575
2576  return isUndefOrEqual(N->getMaskElt(0), 2) &&
2577  isUndefOrEqual(N->getMaskElt(1), 3) &&
2578  isUndefOrEqual(N->getMaskElt(2), 2) &&
2579  isUndefOrEqual(N->getMaskElt(3), 3);
2580}
2581
2582/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2583/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2584bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2585  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2586
2587  if (NumElems != 2 && NumElems != 4)
2588    return false;
2589
2590  for (unsigned i = 0; i < NumElems/2; ++i)
2591    if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2592      return false;
2593
2594  for (unsigned i = NumElems/2; i < NumElems; ++i)
2595    if (!isUndefOrEqual(N->getMaskElt(i), i))
2596      return false;
2597
2598  return true;
2599}
2600
2601/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2602/// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2603bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2604  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2605
2606  if (NumElems != 2 && NumElems != 4)
2607    return false;
2608
2609  for (unsigned i = 0; i < NumElems/2; ++i)
2610    if (!isUndefOrEqual(N->getMaskElt(i), i))
2611      return false;
2612
2613  for (unsigned i = 0; i < NumElems/2; ++i)
2614    if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2615      return false;
2616
2617  return true;
2618}
2619
2620/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2621/// specifies a shuffle of elements that is suitable for input to UNPCKL.
2622static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2623                         bool V2IsSplat = false) {
2624  int NumElts = VT.getVectorNumElements();
2625  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2626    return false;
2627
2628  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2629    int BitI  = Mask[i];
2630    int BitI1 = Mask[i+1];
2631    if (!isUndefOrEqual(BitI, j))
2632      return false;
2633    if (V2IsSplat) {
2634      if (!isUndefOrEqual(BitI1, NumElts))
2635        return false;
2636    } else {
2637      if (!isUndefOrEqual(BitI1, j + NumElts))
2638        return false;
2639    }
2640  }
2641  return true;
2642}
2643
2644bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2645  SmallVector<int, 8> M;
2646  N->getMask(M);
2647  return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2648}
2649
2650/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2651/// specifies a shuffle of elements that is suitable for input to UNPCKH.
2652static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2653                         bool V2IsSplat = false) {
2654  int NumElts = VT.getVectorNumElements();
2655  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2656    return false;
2657
2658  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2659    int BitI  = Mask[i];
2660    int BitI1 = Mask[i+1];
2661    if (!isUndefOrEqual(BitI, j + NumElts/2))
2662      return false;
2663    if (V2IsSplat) {
2664      if (isUndefOrEqual(BitI1, NumElts))
2665        return false;
2666    } else {
2667      if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2668        return false;
2669    }
2670  }
2671  return true;
2672}
2673
2674bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2675  SmallVector<int, 8> M;
2676  N->getMask(M);
2677  return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2678}
2679
2680/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2681/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2682/// <0, 0, 1, 1>
2683static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2684  int NumElems = VT.getVectorNumElements();
2685  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2686    return false;
2687
2688  for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2689    int BitI  = Mask[i];
2690    int BitI1 = Mask[i+1];
2691    if (!isUndefOrEqual(BitI, j))
2692      return false;
2693    if (!isUndefOrEqual(BitI1, j))
2694      return false;
2695  }
2696  return true;
2697}
2698
2699bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2700  SmallVector<int, 8> M;
2701  N->getMask(M);
2702  return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2703}
2704
2705/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2706/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2707/// <2, 2, 3, 3>
2708static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2709  int NumElems = VT.getVectorNumElements();
2710  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2711    return false;
2712
2713  for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2714    int BitI  = Mask[i];
2715    int BitI1 = Mask[i+1];
2716    if (!isUndefOrEqual(BitI, j))
2717      return false;
2718    if (!isUndefOrEqual(BitI1, j))
2719      return false;
2720  }
2721  return true;
2722}
2723
2724bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2725  SmallVector<int, 8> M;
2726  N->getMask(M);
2727  return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2728}
2729
2730/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2731/// specifies a shuffle of elements that is suitable for input to MOVSS,
2732/// MOVSD, and MOVD, i.e. setting the lowest element.
2733static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2734  if (VT.getVectorElementType().getSizeInBits() < 32)
2735    return false;
2736
2737  int NumElts = VT.getVectorNumElements();
2738
2739  if (!isUndefOrEqual(Mask[0], NumElts))
2740    return false;
2741
2742  for (int i = 1; i < NumElts; ++i)
2743    if (!isUndefOrEqual(Mask[i], i))
2744      return false;
2745
2746  return true;
2747}
2748
2749bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2750  SmallVector<int, 8> M;
2751  N->getMask(M);
2752  return ::isMOVLMask(M, N->getValueType(0));
2753}
2754
2755/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2756/// of what x86 movss want. X86 movs requires the lowest  element to be lowest
2757/// element of vector 2 and the other elements to come from vector 1 in order.
2758static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2759                               bool V2IsSplat = false, bool V2IsUndef = false) {
2760  int NumOps = VT.getVectorNumElements();
2761  if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2762    return false;
2763
2764  if (!isUndefOrEqual(Mask[0], 0))
2765    return false;
2766
2767  for (int i = 1; i < NumOps; ++i)
2768    if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2769          (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2770          (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2771      return false;
2772
2773  return true;
2774}
2775
2776static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2777                           bool V2IsUndef = false) {
2778  SmallVector<int, 8> M;
2779  N->getMask(M);
2780  return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2781}
2782
2783/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2784/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2785bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2786  if (N->getValueType(0).getVectorNumElements() != 4)
2787    return false;
2788
2789  // Expect 1, 1, 3, 3
2790  for (unsigned i = 0; i < 2; ++i) {
2791    int Elt = N->getMaskElt(i);
2792    if (Elt >= 0 && Elt != 1)
2793      return false;
2794  }
2795
2796  bool HasHi = false;
2797  for (unsigned i = 2; i < 4; ++i) {
2798    int Elt = N->getMaskElt(i);
2799    if (Elt >= 0 && Elt != 3)
2800      return false;
2801    if (Elt == 3)
2802      HasHi = true;
2803  }
2804  // Don't use movshdup if it can be done with a shufps.
2805  // FIXME: verify that matching u, u, 3, 3 is what we want.
2806  return HasHi;
2807}
2808
2809/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2810/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2811bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2812  if (N->getValueType(0).getVectorNumElements() != 4)
2813    return false;
2814
2815  // Expect 0, 0, 2, 2
2816  for (unsigned i = 0; i < 2; ++i)
2817    if (N->getMaskElt(i) > 0)
2818      return false;
2819
2820  bool HasHi = false;
2821  for (unsigned i = 2; i < 4; ++i) {
2822    int Elt = N->getMaskElt(i);
2823    if (Elt >= 0 && Elt != 2)
2824      return false;
2825    if (Elt == 2)
2826      HasHi = true;
2827  }
2828  // Don't use movsldup if it can be done with a shufps.
2829  return HasHi;
2830}
2831
2832/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2833/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2834bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2835  int e = N->getValueType(0).getVectorNumElements() / 2;
2836
2837  for (int i = 0; i < e; ++i)
2838    if (!isUndefOrEqual(N->getMaskElt(i), i))
2839      return false;
2840  for (int i = 0; i < e; ++i)
2841    if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2842      return false;
2843  return true;
2844}
2845
2846/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2847/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2848unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2849  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2850  int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2851
2852  unsigned Shift = (NumOperands == 4) ? 2 : 1;
2853  unsigned Mask = 0;
2854  for (int i = 0; i < NumOperands; ++i) {
2855    int Val = SVOp->getMaskElt(NumOperands-i-1);
2856    if (Val < 0) Val = 0;
2857    if (Val >= NumOperands) Val -= NumOperands;
2858    Mask |= Val;
2859    if (i != NumOperands - 1)
2860      Mask <<= Shift;
2861  }
2862  return Mask;
2863}
2864
2865/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2866/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2867unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2868  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2869  unsigned Mask = 0;
2870  // 8 nodes, but we only care about the last 4.
2871  for (unsigned i = 7; i >= 4; --i) {
2872    int Val = SVOp->getMaskElt(i);
2873    if (Val >= 0)
2874      Mask |= (Val - 4);
2875    if (i != 4)
2876      Mask <<= 2;
2877  }
2878  return Mask;
2879}
2880
2881/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2882/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2883unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2884  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2885  unsigned Mask = 0;
2886  // 8 nodes, but we only care about the first 4.
2887  for (int i = 3; i >= 0; --i) {
2888    int Val = SVOp->getMaskElt(i);
2889    if (Val >= 0)
2890      Mask |= Val;
2891    if (i != 0)
2892      Mask <<= 2;
2893  }
2894  return Mask;
2895}
2896
2897/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2898/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2899unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2900  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2901  EVT VVT = N->getValueType(0);
2902  unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2903  int Val = 0;
2904
2905  unsigned i, e;
2906  for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2907    Val = SVOp->getMaskElt(i);
2908    if (Val >= 0)
2909      break;
2910  }
2911  return (Val - i) * EltSize;
2912}
2913
2914/// isZeroNode - Returns true if Elt is a constant zero or a floating point
2915/// constant +0.0.
2916bool X86::isZeroNode(SDValue Elt) {
2917  return ((isa<ConstantSDNode>(Elt) &&
2918           cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2919          (isa<ConstantFPSDNode>(Elt) &&
2920           cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2921}
2922
2923/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2924/// their permute mask.
2925static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2926                                    SelectionDAG &DAG) {
2927  EVT VT = SVOp->getValueType(0);
2928  unsigned NumElems = VT.getVectorNumElements();
2929  SmallVector<int, 8> MaskVec;
2930
2931  for (unsigned i = 0; i != NumElems; ++i) {
2932    int idx = SVOp->getMaskElt(i);
2933    if (idx < 0)
2934      MaskVec.push_back(idx);
2935    else if (idx < (int)NumElems)
2936      MaskVec.push_back(idx + NumElems);
2937    else
2938      MaskVec.push_back(idx - NumElems);
2939  }
2940  return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2941                              SVOp->getOperand(0), &MaskVec[0]);
2942}
2943
2944/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2945/// the two vector operands have swapped position.
2946static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2947  unsigned NumElems = VT.getVectorNumElements();
2948  for (unsigned i = 0; i != NumElems; ++i) {
2949    int idx = Mask[i];
2950    if (idx < 0)
2951      continue;
2952    else if (idx < (int)NumElems)
2953      Mask[i] = idx + NumElems;
2954    else
2955      Mask[i] = idx - NumElems;
2956  }
2957}
2958
2959/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2960/// match movhlps. The lower half elements should come from upper half of
2961/// V1 (and in order), and the upper half elements should come from the upper
2962/// half of V2 (and in order).
2963static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2964  if (Op->getValueType(0).getVectorNumElements() != 4)
2965    return false;
2966  for (unsigned i = 0, e = 2; i != e; ++i)
2967    if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2968      return false;
2969  for (unsigned i = 2; i != 4; ++i)
2970    if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2971      return false;
2972  return true;
2973}
2974
2975/// isScalarLoadToVector - Returns true if the node is a scalar load that
2976/// is promoted to a vector. It also returns the LoadSDNode by reference if
2977/// required.
2978static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2979  if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2980    return false;
2981  N = N->getOperand(0).getNode();
2982  if (!ISD::isNON_EXTLoad(N))
2983    return false;
2984  if (LD)
2985    *LD = cast<LoadSDNode>(N);
2986  return true;
2987}
2988
2989/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2990/// match movlp{s|d}. The lower half elements should come from lower half of
2991/// V1 (and in order), and the upper half elements should come from the upper
2992/// half of V2 (and in order). And since V1 will become the source of the
2993/// MOVLP, it must be either a vector load or a scalar load to vector.
2994static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2995                               ShuffleVectorSDNode *Op) {
2996  if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2997    return false;
2998  // Is V2 is a vector load, don't do this transformation. We will try to use
2999  // load folding shufps op.
3000  if (ISD::isNON_EXTLoad(V2))
3001    return false;
3002
3003  unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3004
3005  if (NumElems != 2 && NumElems != 4)
3006    return false;
3007  for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3008    if (!isUndefOrEqual(Op->getMaskElt(i), i))
3009      return false;
3010  for (unsigned i = NumElems/2; i != NumElems; ++i)
3011    if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3012      return false;
3013  return true;
3014}
3015
3016/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3017/// all the same.
3018static bool isSplatVector(SDNode *N) {
3019  if (N->getOpcode() != ISD::BUILD_VECTOR)
3020    return false;
3021
3022  SDValue SplatValue = N->getOperand(0);
3023  for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3024    if (N->getOperand(i) != SplatValue)
3025      return false;
3026  return true;
3027}
3028
3029/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3030/// to an zero vector.
3031/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3032static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3033  SDValue V1 = N->getOperand(0);
3034  SDValue V2 = N->getOperand(1);
3035  unsigned NumElems = N->getValueType(0).getVectorNumElements();
3036  for (unsigned i = 0; i != NumElems; ++i) {
3037    int Idx = N->getMaskElt(i);
3038    if (Idx >= (int)NumElems) {
3039      unsigned Opc = V2.getOpcode();
3040      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3041        continue;
3042      if (Opc != ISD::BUILD_VECTOR ||
3043          !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3044        return false;
3045    } else if (Idx >= 0) {
3046      unsigned Opc = V1.getOpcode();
3047      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3048        continue;
3049      if (Opc != ISD::BUILD_VECTOR ||
3050          !X86::isZeroNode(V1.getOperand(Idx)))
3051        return false;
3052    }
3053  }
3054  return true;
3055}
3056
3057/// getZeroVector - Returns a vector of specified type with all zero elements.
3058///
3059static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3060                             DebugLoc dl) {
3061  assert(VT.isVector() && "Expected a vector type");
3062
3063  // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3064  // type.  This ensures they get CSE'd.
3065  SDValue Vec;
3066  if (VT.getSizeInBits() == 64) { // MMX
3067    SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3068    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3069  } else if (HasSSE2) {  // SSE2
3070    SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3071    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3072  } else { // SSE1
3073    SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3074    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3075  }
3076  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3077}
3078
3079/// getOnesVector - Returns a vector of specified type with all bits set.
3080///
3081static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3082  assert(VT.isVector() && "Expected a vector type");
3083
3084  // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3085  // type.  This ensures they get CSE'd.
3086  SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3087  SDValue Vec;
3088  if (VT.getSizeInBits() == 64)  // MMX
3089    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3090  else                                              // SSE
3091    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3092  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3093}
3094
3095
3096/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3097/// that point to V2 points to its first element.
3098static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3099  EVT VT = SVOp->getValueType(0);
3100  unsigned NumElems = VT.getVectorNumElements();
3101
3102  bool Changed = false;
3103  SmallVector<int, 8> MaskVec;
3104  SVOp->getMask(MaskVec);
3105
3106  for (unsigned i = 0; i != NumElems; ++i) {
3107    if (MaskVec[i] > (int)NumElems) {
3108      MaskVec[i] = NumElems;
3109      Changed = true;
3110    }
3111  }
3112  if (Changed)
3113    return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3114                                SVOp->getOperand(1), &MaskVec[0]);
3115  return SDValue(SVOp, 0);
3116}
3117
3118/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3119/// operation of specified width.
3120static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3121                       SDValue V2) {
3122  unsigned NumElems = VT.getVectorNumElements();
3123  SmallVector<int, 8> Mask;
3124  Mask.push_back(NumElems);
3125  for (unsigned i = 1; i != NumElems; ++i)
3126    Mask.push_back(i);
3127  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3128}
3129
3130/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3131static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3132                          SDValue V2) {
3133  unsigned NumElems = VT.getVectorNumElements();
3134  SmallVector<int, 8> Mask;
3135  for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3136    Mask.push_back(i);
3137    Mask.push_back(i + NumElems);
3138  }
3139  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3140}
3141
3142/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3143static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3144                          SDValue V2) {
3145  unsigned NumElems = VT.getVectorNumElements();
3146  unsigned Half = NumElems/2;
3147  SmallVector<int, 8> Mask;
3148  for (unsigned i = 0; i != Half; ++i) {
3149    Mask.push_back(i + Half);
3150    Mask.push_back(i + NumElems + Half);
3151  }
3152  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3153}
3154
3155/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3156static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3157                            bool HasSSE2) {
3158  if (SV->getValueType(0).getVectorNumElements() <= 4)
3159    return SDValue(SV, 0);
3160
3161  EVT PVT = MVT::v4f32;
3162  EVT VT = SV->getValueType(0);
3163  DebugLoc dl = SV->getDebugLoc();
3164  SDValue V1 = SV->getOperand(0);
3165  int NumElems = VT.getVectorNumElements();
3166  int EltNo = SV->getSplatIndex();
3167
3168  // unpack elements to the correct location
3169  while (NumElems > 4) {
3170    if (EltNo < NumElems/2) {
3171      V1 = getUnpackl(DAG, dl, VT, V1, V1);
3172    } else {
3173      V1 = getUnpackh(DAG, dl, VT, V1, V1);
3174      EltNo -= NumElems/2;
3175    }
3176    NumElems >>= 1;
3177  }
3178
3179  // Perform the splat.
3180  int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3181  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3182  V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3183  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3184}
3185
3186/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3187/// vector of zero or undef vector.  This produces a shuffle where the low
3188/// element of V2 is swizzled into the zero/undef vector, landing at element
3189/// Idx.  This produces a shuffle mask like 4,1,2,3 (idx=0) or  0,1,2,4 (idx=3).
3190static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3191                                             bool isZero, bool HasSSE2,
3192                                             SelectionDAG &DAG) {
3193  EVT VT = V2.getValueType();
3194  SDValue V1 = isZero
3195    ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3196  unsigned NumElems = VT.getVectorNumElements();
3197  SmallVector<int, 16> MaskVec;
3198  for (unsigned i = 0; i != NumElems; ++i)
3199    // If this is the insertion idx, put the low elt of V2 here.
3200    MaskVec.push_back(i == Idx ? NumElems : i);
3201  return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3202}
3203
3204/// getNumOfConsecutiveZeros - Return the number of elements in a result of
3205/// a shuffle that is zero.
3206static
3207unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3208                                  bool Low, SelectionDAG &DAG) {
3209  unsigned NumZeros = 0;
3210  for (int i = 0; i < NumElems; ++i) {
3211    unsigned Index = Low ? i : NumElems-i-1;
3212    int Idx = SVOp->getMaskElt(Index);
3213    if (Idx < 0) {
3214      ++NumZeros;
3215      continue;
3216    }
3217    SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3218    if (Elt.getNode() && X86::isZeroNode(Elt))
3219      ++NumZeros;
3220    else
3221      break;
3222  }
3223  return NumZeros;
3224}
3225
3226/// isVectorShift - Returns true if the shuffle can be implemented as a
3227/// logical left or right shift of a vector.
3228/// FIXME: split into pslldqi, psrldqi, palignr variants.
3229static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3230                          bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3231  int NumElems = SVOp->getValueType(0).getVectorNumElements();
3232
3233  isLeft = true;
3234  unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3235  if (!NumZeros) {
3236    isLeft = false;
3237    NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3238    if (!NumZeros)
3239      return false;
3240  }
3241  bool SeenV1 = false;
3242  bool SeenV2 = false;
3243  for (int i = NumZeros; i < NumElems; ++i) {
3244    int Val = isLeft ? (i - NumZeros) : i;
3245    int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3246    if (Idx < 0)
3247      continue;
3248    if (Idx < NumElems)
3249      SeenV1 = true;
3250    else {
3251      Idx -= NumElems;
3252      SeenV2 = true;
3253    }
3254    if (Idx != Val)
3255      return false;
3256  }
3257  if (SeenV1 && SeenV2)
3258    return false;
3259
3260  ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3261  ShAmt = NumZeros;
3262  return true;
3263}
3264
3265
3266/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3267///
3268static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3269                                       unsigned NumNonZero, unsigned NumZero,
3270                                       SelectionDAG &DAG, TargetLowering &TLI) {
3271  if (NumNonZero > 8)
3272    return SDValue();
3273
3274  DebugLoc dl = Op.getDebugLoc();
3275  SDValue V(0, 0);
3276  bool First = true;
3277  for (unsigned i = 0; i < 16; ++i) {
3278    bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3279    if (ThisIsNonZero && First) {
3280      if (NumZero)
3281        V = getZeroVector(MVT::v8i16, true, DAG, dl);
3282      else
3283        V = DAG.getUNDEF(MVT::v8i16);
3284      First = false;
3285    }
3286
3287    if ((i & 1) != 0) {
3288      SDValue ThisElt(0, 0), LastElt(0, 0);
3289      bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3290      if (LastIsNonZero) {
3291        LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3292                              MVT::i16, Op.getOperand(i-1));
3293      }
3294      if (ThisIsNonZero) {
3295        ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3296        ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3297                              ThisElt, DAG.getConstant(8, MVT::i8));
3298        if (LastIsNonZero)
3299          ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3300      } else
3301        ThisElt = LastElt;
3302
3303      if (ThisElt.getNode())
3304        V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3305                        DAG.getIntPtrConstant(i/2));
3306    }
3307  }
3308
3309  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3310}
3311
3312/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3313///
3314static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3315                                       unsigned NumNonZero, unsigned NumZero,
3316                                       SelectionDAG &DAG, TargetLowering &TLI) {
3317  if (NumNonZero > 4)
3318    return SDValue();
3319
3320  DebugLoc dl = Op.getDebugLoc();
3321  SDValue V(0, 0);
3322  bool First = true;
3323  for (unsigned i = 0; i < 8; ++i) {
3324    bool isNonZero = (NonZeros & (1 << i)) != 0;
3325    if (isNonZero) {
3326      if (First) {
3327        if (NumZero)
3328          V = getZeroVector(MVT::v8i16, true, DAG, dl);
3329        else
3330          V = DAG.getUNDEF(MVT::v8i16);
3331        First = false;
3332      }
3333      V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3334                      MVT::v8i16, V, Op.getOperand(i),
3335                      DAG.getIntPtrConstant(i));
3336    }
3337  }
3338
3339  return V;
3340}
3341
3342/// getVShift - Return a vector logical shift node.
3343///
3344static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3345                         unsigned NumBits, SelectionDAG &DAG,
3346                         const TargetLowering &TLI, DebugLoc dl) {
3347  bool isMMX = VT.getSizeInBits() == 64;
3348  EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3349  unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3350  SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3351  return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3352                     DAG.getNode(Opc, dl, ShVT, SrcOp,
3353                             DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3354}
3355
3356SDValue
3357X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3358                                          SelectionDAG &DAG) {
3359
3360  // Check if the scalar load can be widened into a vector load. And if
3361  // the address is "base + cst" see if the cst can be "absorbed" into
3362  // the shuffle mask.
3363  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3364    SDValue Ptr = LD->getBasePtr();
3365    if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3366      return SDValue();
3367    EVT PVT = LD->getValueType(0);
3368    if (PVT != MVT::i32 && PVT != MVT::f32)
3369      return SDValue();
3370
3371    int FI = -1;
3372    int64_t Offset = 0;
3373    if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3374      FI = FINode->getIndex();
3375      Offset = 0;
3376    } else if (Ptr.getOpcode() == ISD::ADD &&
3377               isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3378               isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3379      FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3380      Offset = Ptr.getConstantOperandVal(1);
3381      Ptr = Ptr.getOperand(0);
3382    } else {
3383      return SDValue();
3384    }
3385
3386    SDValue Chain = LD->getChain();
3387    // Make sure the stack object alignment is at least 16.
3388    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3389    if (DAG.InferPtrAlignment(Ptr) < 16) {
3390      if (MFI->isFixedObjectIndex(FI)) {
3391        // Can't change the alignment. Reference stack + offset explicitly
3392        // if stack pointer is at least 16-byte aligned.
3393        unsigned StackAlign = Subtarget->getStackAlignment();
3394        if (StackAlign < 16)
3395          return SDValue();
3396        Offset = MFI->getObjectOffset(FI) + Offset;
3397        SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
3398                                              getPointerTy());
3399        Ptr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3400                          DAG.getConstant(Offset & ~15, getPointerTy()));
3401        Offset %= 16;
3402      } else {
3403        MFI->setObjectAlignment(FI, 16);
3404      }
3405    }
3406
3407    // (Offset % 16) must be multiple of 4. Then address is then
3408    // Ptr + (Offset & ~15).
3409    if (Offset < 0)
3410      return SDValue();
3411    if ((Offset % 16) & 3)
3412      return SDValue();
3413    int64_t StartOffset = Offset & ~15;
3414    if (StartOffset)
3415      Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3416                        Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3417
3418    int EltNo = (Offset - StartOffset) >> 2;
3419    int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3420    EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3421    SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3422    // Canonicalize it to a v4i32 shuffle.
3423    V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3424    return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3425                       DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3426                                            DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3427  }
3428
3429  return SDValue();
3430}
3431
3432SDValue
3433X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3434  DebugLoc dl = Op.getDebugLoc();
3435  // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3436  if (ISD::isBuildVectorAllZeros(Op.getNode())
3437      || ISD::isBuildVectorAllOnes(Op.getNode())) {
3438    // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3439    // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3440    // eliminated on x86-32 hosts.
3441    if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3442      return Op;
3443
3444    if (ISD::isBuildVectorAllOnes(Op.getNode()))
3445      return getOnesVector(Op.getValueType(), DAG, dl);
3446    return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3447  }
3448
3449  EVT VT = Op.getValueType();
3450  EVT ExtVT = VT.getVectorElementType();
3451  unsigned EVTBits = ExtVT.getSizeInBits();
3452
3453  unsigned NumElems = Op.getNumOperands();
3454  unsigned NumZero  = 0;
3455  unsigned NumNonZero = 0;
3456  unsigned NonZeros = 0;
3457  bool IsAllConstants = true;
3458  SmallSet<SDValue, 8> Values;
3459  for (unsigned i = 0; i < NumElems; ++i) {
3460    SDValue Elt = Op.getOperand(i);
3461    if (Elt.getOpcode() == ISD::UNDEF)
3462      continue;
3463    Values.insert(Elt);
3464    if (Elt.getOpcode() != ISD::Constant &&
3465        Elt.getOpcode() != ISD::ConstantFP)
3466      IsAllConstants = false;
3467    if (X86::isZeroNode(Elt))
3468      NumZero++;
3469    else {
3470      NonZeros |= (1 << i);
3471      NumNonZero++;
3472    }
3473  }
3474
3475  if (NumNonZero == 0) {
3476    // All undef vector. Return an UNDEF.  All zero vectors were handled above.
3477    return DAG.getUNDEF(VT);
3478  }
3479
3480  // Special case for single non-zero, non-undef, element.
3481  if (NumNonZero == 1) {
3482    unsigned Idx = CountTrailingZeros_32(NonZeros);
3483    SDValue Item = Op.getOperand(Idx);
3484
3485    // If this is an insertion of an i64 value on x86-32, and if the top bits of
3486    // the value are obviously zero, truncate the value to i32 and do the
3487    // insertion that way.  Only do this if the value is non-constant or if the
3488    // value is a constant being inserted into element 0.  It is cheaper to do
3489    // a constant pool load than it is to do a movd + shuffle.
3490    if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3491        (!IsAllConstants || Idx == 0)) {
3492      if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3493        // Handle MMX and SSE both.
3494        EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3495        unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3496
3497        // Truncate the value (which may itself be a constant) to i32, and
3498        // convert it to a vector with movd (S2V+shuffle to zero extend).
3499        Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3500        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3501        Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3502                                           Subtarget->hasSSE2(), DAG);
3503
3504        // Now we have our 32-bit value zero extended in the low element of
3505        // a vector.  If Idx != 0, swizzle it into place.
3506        if (Idx != 0) {
3507          SmallVector<int, 4> Mask;
3508          Mask.push_back(Idx);
3509          for (unsigned i = 1; i != VecElts; ++i)
3510            Mask.push_back(i);
3511          Item = DAG.getVectorShuffle(VecVT, dl, Item,
3512                                      DAG.getUNDEF(Item.getValueType()),
3513                                      &Mask[0]);
3514        }
3515        return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3516      }
3517    }
3518
3519    // If we have a constant or non-constant insertion into the low element of
3520    // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3521    // the rest of the elements.  This will be matched as movd/movq/movss/movsd
3522    // depending on what the source datatype is.
3523    if (Idx == 0) {
3524      if (NumZero == 0) {
3525        return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3526      } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3527          (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3528        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3529        // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3530        return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3531                                           DAG);
3532      } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3533        Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3534        EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3535        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3536        Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3537                                           Subtarget->hasSSE2(), DAG);
3538        return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3539      }
3540    }
3541
3542    // Is it a vector logical left shift?
3543    if (NumElems == 2 && Idx == 1 &&
3544        X86::isZeroNode(Op.getOperand(0)) &&
3545        !X86::isZeroNode(Op.getOperand(1))) {
3546      unsigned NumBits = VT.getSizeInBits();
3547      return getVShift(true, VT,
3548                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3549                                   VT, Op.getOperand(1)),
3550                       NumBits/2, DAG, *this, dl);
3551    }
3552
3553    if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3554      return SDValue();
3555
3556    // Otherwise, if this is a vector with i32 or f32 elements, and the element
3557    // is a non-constant being inserted into an element other than the low one,
3558    // we can't use a constant pool load.  Instead, use SCALAR_TO_VECTOR (aka
3559    // movd/movss) to move this into the low element, then shuffle it into
3560    // place.
3561    if (EVTBits == 32) {
3562      Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3563
3564      // Turn it into a shuffle of zero and zero-extended scalar to vector.
3565      Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3566                                         Subtarget->hasSSE2(), DAG);
3567      SmallVector<int, 8> MaskVec;
3568      for (unsigned i = 0; i < NumElems; i++)
3569        MaskVec.push_back(i == Idx ? 0 : 1);
3570      return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3571    }
3572  }
3573
3574  // Splat is obviously ok. Let legalizer expand it to a shuffle.
3575  if (Values.size() == 1) {
3576    if (EVTBits == 32) {
3577      // Instead of a shuffle like this:
3578      // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3579      // Check if it's possible to issue this instead.
3580      // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3581      unsigned Idx = CountTrailingZeros_32(NonZeros);
3582      SDValue Item = Op.getOperand(Idx);
3583      if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3584        return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3585    }
3586    return SDValue();
3587  }
3588
3589  // A vector full of immediates; various special cases are already
3590  // handled, so this is best done with a single constant-pool load.
3591  if (IsAllConstants)
3592    return SDValue();
3593
3594  // Let legalizer expand 2-wide build_vectors.
3595  if (EVTBits == 64) {
3596    if (NumNonZero == 1) {
3597      // One half is zero or undef.
3598      unsigned Idx = CountTrailingZeros_32(NonZeros);
3599      SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3600                                 Op.getOperand(Idx));
3601      return getShuffleVectorZeroOrUndef(V2, Idx, true,
3602                                         Subtarget->hasSSE2(), DAG);
3603    }
3604    return SDValue();
3605  }
3606
3607  // If element VT is < 32 bits, convert it to inserts into a zero vector.
3608  if (EVTBits == 8 && NumElems == 16) {
3609    SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3610                                        *this);
3611    if (V.getNode()) return V;
3612  }
3613
3614  if (EVTBits == 16 && NumElems == 8) {
3615    SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3616                                        *this);
3617    if (V.getNode()) return V;
3618  }
3619
3620  // If element VT is == 32 bits, turn it into a number of shuffles.
3621  SmallVector<SDValue, 8> V;
3622  V.resize(NumElems);
3623  if (NumElems == 4 && NumZero > 0) {
3624    for (unsigned i = 0; i < 4; ++i) {
3625      bool isZero = !(NonZeros & (1 << i));
3626      if (isZero)
3627        V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3628      else
3629        V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3630    }
3631
3632    for (unsigned i = 0; i < 2; ++i) {
3633      switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3634        default: break;
3635        case 0:
3636          V[i] = V[i*2];  // Must be a zero vector.
3637          break;
3638        case 1:
3639          V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3640          break;
3641        case 2:
3642          V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3643          break;
3644        case 3:
3645          V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3646          break;
3647      }
3648    }
3649
3650    SmallVector<int, 8> MaskVec;
3651    bool Reverse = (NonZeros & 0x3) == 2;
3652    for (unsigned i = 0; i < 2; ++i)
3653      MaskVec.push_back(Reverse ? 1-i : i);
3654    Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3655    for (unsigned i = 0; i < 2; ++i)
3656      MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3657    return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3658  }
3659
3660  if (Values.size() > 2) {
3661    // If we have SSE 4.1, Expand into a number of inserts unless the number of
3662    // values to be inserted is equal to the number of elements, in which case
3663    // use the unpack code below in the hopes of matching the consecutive elts
3664    // load merge pattern for shuffles.
3665    // FIXME: We could probably just check that here directly.
3666    if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3667        getSubtarget()->hasSSE41()) {
3668      V[0] = DAG.getUNDEF(VT);
3669      for (unsigned i = 0; i < NumElems; ++i)
3670        if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3671          V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3672                             Op.getOperand(i), DAG.getIntPtrConstant(i));
3673      return V[0];
3674    }
3675    // Expand into a number of unpckl*.
3676    // e.g. for v4f32
3677    //   Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3678    //         : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3679    //   Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>
3680    for (unsigned i = 0; i < NumElems; ++i)
3681      V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3682    NumElems >>= 1;
3683    while (NumElems != 0) {
3684      for (unsigned i = 0; i < NumElems; ++i)
3685        V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3686      NumElems >>= 1;
3687    }
3688    return V[0];
3689  }
3690
3691  return SDValue();
3692}
3693
3694// v8i16 shuffles - Prefer shuffles in the following order:
3695// 1. [all]   pshuflw, pshufhw, optional move
3696// 2. [ssse3] 1 x pshufb
3697// 3. [ssse3] 2 x pshufb + 1 x por
3698// 4. [all]   mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3699static
3700SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3701                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
3702  SDValue V1 = SVOp->getOperand(0);
3703  SDValue V2 = SVOp->getOperand(1);
3704  DebugLoc dl = SVOp->getDebugLoc();
3705  SmallVector<int, 8> MaskVals;
3706
3707  // Determine if more than 1 of the words in each of the low and high quadwords
3708  // of the result come from the same quadword of one of the two inputs.  Undef
3709  // mask values count as coming from any quadword, for better codegen.
3710  SmallVector<unsigned, 4> LoQuad(4);
3711  SmallVector<unsigned, 4> HiQuad(4);
3712  BitVector InputQuads(4);
3713  for (unsigned i = 0; i < 8; ++i) {
3714    SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3715    int EltIdx = SVOp->getMaskElt(i);
3716    MaskVals.push_back(EltIdx);
3717    if (EltIdx < 0) {
3718      ++Quad[0];
3719      ++Quad[1];
3720      ++Quad[2];
3721      ++Quad[3];
3722      continue;
3723    }
3724    ++Quad[EltIdx / 4];
3725    InputQuads.set(EltIdx / 4);
3726  }
3727
3728  int BestLoQuad = -1;
3729  unsigned MaxQuad = 1;
3730  for (unsigned i = 0; i < 4; ++i) {
3731    if (LoQuad[i] > MaxQuad) {
3732      BestLoQuad = i;
3733      MaxQuad = LoQuad[i];
3734    }
3735  }
3736
3737  int BestHiQuad = -1;
3738  MaxQuad = 1;
3739  for (unsigned i = 0; i < 4; ++i) {
3740    if (HiQuad[i] > MaxQuad) {
3741      BestHiQuad = i;
3742      MaxQuad = HiQuad[i];
3743    }
3744  }
3745
3746  // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3747  // of the two input vectors, shuffle them into one input vector so only a
3748  // single pshufb instruction is necessary. If There are more than 2 input
3749  // quads, disable the next transformation since it does not help SSSE3.
3750  bool V1Used = InputQuads[0] || InputQuads[1];
3751  bool V2Used = InputQuads[2] || InputQuads[3];
3752  if (TLI.getSubtarget()->hasSSSE3()) {
3753    if (InputQuads.count() == 2 && V1Used && V2Used) {
3754      BestLoQuad = InputQuads.find_first();
3755      BestHiQuad = InputQuads.find_next(BestLoQuad);
3756    }
3757    if (InputQuads.count() > 2) {
3758      BestLoQuad = -1;
3759      BestHiQuad = -1;
3760    }
3761  }
3762
3763  // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3764  // the shuffle mask.  If a quad is scored as -1, that means that it contains
3765  // words from all 4 input quadwords.
3766  SDValue NewV;
3767  if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3768    SmallVector<int, 8> MaskV;
3769    MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3770    MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3771    NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3772                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3773                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3774    NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3775
3776    // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3777    // source words for the shuffle, to aid later transformations.
3778    bool AllWordsInNewV = true;
3779    bool InOrder[2] = { true, true };
3780    for (unsigned i = 0; i != 8; ++i) {
3781      int idx = MaskVals[i];
3782      if (idx != (int)i)
3783        InOrder[i/4] = false;
3784      if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3785        continue;
3786      AllWordsInNewV = false;
3787      break;
3788    }
3789
3790    bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3791    if (AllWordsInNewV) {
3792      for (int i = 0; i != 8; ++i) {
3793        int idx = MaskVals[i];
3794        if (idx < 0)
3795          continue;
3796        idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3797        if ((idx != i) && idx < 4)
3798          pshufhw = false;
3799        if ((idx != i) && idx > 3)
3800          pshuflw = false;
3801      }
3802      V1 = NewV;
3803      V2Used = false;
3804      BestLoQuad = 0;
3805      BestHiQuad = 1;
3806    }
3807
3808    // If we've eliminated the use of V2, and the new mask is a pshuflw or
3809    // pshufhw, that's as cheap as it gets.  Return the new shuffle.
3810    if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3811      return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3812                                  DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3813    }
3814  }
3815
3816  // If we have SSSE3, and all words of the result are from 1 input vector,
3817  // case 2 is generated, otherwise case 3 is generated.  If no SSSE3
3818  // is present, fall back to case 4.
3819  if (TLI.getSubtarget()->hasSSSE3()) {
3820    SmallVector<SDValue,16> pshufbMask;
3821
3822    // If we have elements from both input vectors, set the high bit of the
3823    // shuffle mask element to zero out elements that come from V2 in the V1
3824    // mask, and elements that come from V1 in the V2 mask, so that the two
3825    // results can be OR'd together.
3826    bool TwoInputs = V1Used && V2Used;
3827    for (unsigned i = 0; i != 8; ++i) {
3828      int EltIdx = MaskVals[i] * 2;
3829      if (TwoInputs && (EltIdx >= 16)) {
3830        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3831        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3832        continue;
3833      }
3834      pshufbMask.push_back(DAG.getConstant(EltIdx,   MVT::i8));
3835      pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3836    }
3837    V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3838    V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3839                     DAG.getNode(ISD::BUILD_VECTOR, dl,
3840                                 MVT::v16i8, &pshufbMask[0], 16));
3841    if (!TwoInputs)
3842      return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3843
3844    // Calculate the shuffle mask for the second input, shuffle it, and
3845    // OR it with the first shuffled input.
3846    pshufbMask.clear();
3847    for (unsigned i = 0; i != 8; ++i) {
3848      int EltIdx = MaskVals[i] * 2;
3849      if (EltIdx < 16) {
3850        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3851        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3852        continue;
3853      }
3854      pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3855      pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3856    }
3857    V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3858    V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3859                     DAG.getNode(ISD::BUILD_VECTOR, dl,
3860                                 MVT::v16i8, &pshufbMask[0], 16));
3861    V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3862    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3863  }
3864
3865  // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3866  // and update MaskVals with new element order.
3867  BitVector InOrder(8);
3868  if (BestLoQuad >= 0) {
3869    SmallVector<int, 8> MaskV;
3870    for (int i = 0; i != 4; ++i) {
3871      int idx = MaskVals[i];
3872      if (idx < 0) {
3873        MaskV.push_back(-1);
3874        InOrder.set(i);
3875      } else if ((idx / 4) == BestLoQuad) {
3876        MaskV.push_back(idx & 3);
3877        InOrder.set(i);
3878      } else {
3879        MaskV.push_back(-1);
3880      }
3881    }
3882    for (unsigned i = 4; i != 8; ++i)
3883      MaskV.push_back(i);
3884    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3885                                &MaskV[0]);
3886  }
3887
3888  // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3889  // and update MaskVals with the new element order.
3890  if (BestHiQuad >= 0) {
3891    SmallVector<int, 8> MaskV;
3892    for (unsigned i = 0; i != 4; ++i)
3893      MaskV.push_back(i);
3894    for (unsigned i = 4; i != 8; ++i) {
3895      int idx = MaskVals[i];
3896      if (idx < 0) {
3897        MaskV.push_back(-1);
3898        InOrder.set(i);
3899      } else if ((idx / 4) == BestHiQuad) {
3900        MaskV.push_back((idx & 3) + 4);
3901        InOrder.set(i);
3902      } else {
3903        MaskV.push_back(-1);
3904      }
3905    }
3906    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3907                                &MaskV[0]);
3908  }
3909
3910  // In case BestHi & BestLo were both -1, which means each quadword has a word
3911  // from each of the four input quadwords, calculate the InOrder bitvector now
3912  // before falling through to the insert/extract cleanup.
3913  if (BestLoQuad == -1 && BestHiQuad == -1) {
3914    NewV = V1;
3915    for (int i = 0; i != 8; ++i)
3916      if (MaskVals[i] < 0 || MaskVals[i] == i)
3917        InOrder.set(i);
3918  }
3919
3920  // The other elements are put in the right place using pextrw and pinsrw.
3921  for (unsigned i = 0; i != 8; ++i) {
3922    if (InOrder[i])
3923      continue;
3924    int EltIdx = MaskVals[i];
3925    if (EltIdx < 0)
3926      continue;
3927    SDValue ExtOp = (EltIdx < 8)
3928    ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3929                  DAG.getIntPtrConstant(EltIdx))
3930    : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3931                  DAG.getIntPtrConstant(EltIdx - 8));
3932    NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3933                       DAG.getIntPtrConstant(i));
3934  }
3935  return NewV;
3936}
3937
3938// v16i8 shuffles - Prefer shuffles in the following order:
3939// 1. [ssse3] 1 x pshufb
3940// 2. [ssse3] 2 x pshufb + 1 x por
3941// 3. [all]   v8i16 shuffle + N x pextrw + rotate + pinsrw
3942static
3943SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3944                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
3945  SDValue V1 = SVOp->getOperand(0);
3946  SDValue V2 = SVOp->getOperand(1);
3947  DebugLoc dl = SVOp->getDebugLoc();
3948  SmallVector<int, 16> MaskVals;
3949  SVOp->getMask(MaskVals);
3950
3951  // If we have SSSE3, case 1 is generated when all result bytes come from
3952  // one of  the inputs.  Otherwise, case 2 is generated.  If no SSSE3 is
3953  // present, fall back to case 3.
3954  // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3955  bool V1Only = true;
3956  bool V2Only = true;
3957  for (unsigned i = 0; i < 16; ++i) {
3958    int EltIdx = MaskVals[i];
3959    if (EltIdx < 0)
3960      continue;
3961    if (EltIdx < 16)
3962      V2Only = false;
3963    else
3964      V1Only = false;
3965  }
3966
3967  // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3968  if (TLI.getSubtarget()->hasSSSE3()) {
3969    SmallVector<SDValue,16> pshufbMask;
3970
3971    // If all result elements are from one input vector, then only translate
3972    // undef mask values to 0x80 (zero out result) in the pshufb mask.
3973    //
3974    // Otherwise, we have elements from both input vectors, and must zero out
3975    // elements that come from V2 in the first mask, and V1 in the second mask
3976    // so that we can OR them together.
3977    bool TwoInputs = !(V1Only || V2Only);
3978    for (unsigned i = 0; i != 16; ++i) {
3979      int EltIdx = MaskVals[i];
3980      if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3981        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3982        continue;
3983      }
3984      pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3985    }
3986    // If all the elements are from V2, assign it to V1 and return after
3987    // building the first pshufb.
3988    if (V2Only)
3989      V1 = V2;
3990    V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3991                     DAG.getNode(ISD::BUILD_VECTOR, dl,
3992                                 MVT::v16i8, &pshufbMask[0], 16));
3993    if (!TwoInputs)
3994      return V1;
3995
3996    // Calculate the shuffle mask for the second input, shuffle it, and
3997    // OR it with the first shuffled input.
3998    pshufbMask.clear();
3999    for (unsigned i = 0; i != 16; ++i) {
4000      int EltIdx = MaskVals[i];
4001      if (EltIdx < 16) {
4002        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4003        continue;
4004      }
4005      pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4006    }
4007    V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4008                     DAG.getNode(ISD::BUILD_VECTOR, dl,
4009                                 MVT::v16i8, &pshufbMask[0], 16));
4010    return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4011  }
4012
4013  // No SSSE3 - Calculate in place words and then fix all out of place words
4014  // With 0-16 extracts & inserts.  Worst case is 16 bytes out of order from
4015  // the 16 different words that comprise the two doublequadword input vectors.
4016  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4017  V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4018  SDValue NewV = V2Only ? V2 : V1;
4019  for (int i = 0; i != 8; ++i) {
4020    int Elt0 = MaskVals[i*2];
4021    int Elt1 = MaskVals[i*2+1];
4022
4023    // This word of the result is all undef, skip it.
4024    if (Elt0 < 0 && Elt1 < 0)
4025      continue;
4026
4027    // This word of the result is already in the correct place, skip it.
4028    if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4029      continue;
4030    if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4031      continue;
4032
4033    SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4034    SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4035    SDValue InsElt;
4036
4037    // If Elt0 and Elt1 are defined, are consecutive, and can be load
4038    // using a single extract together, load it and store it.
4039    if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4040      InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4041                           DAG.getIntPtrConstant(Elt1 / 2));
4042      NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4043                        DAG.getIntPtrConstant(i));
4044      continue;
4045    }
4046
4047    // If Elt1 is defined, extract it from the appropriate source.  If the
4048    // source byte is not also odd, shift the extracted word left 8 bits
4049    // otherwise clear the bottom 8 bits if we need to do an or.
4050    if (Elt1 >= 0) {
4051      InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4052                           DAG.getIntPtrConstant(Elt1 / 2));
4053      if ((Elt1 & 1) == 0)
4054        InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4055                             DAG.getConstant(8, TLI.getShiftAmountTy()));
4056      else if (Elt0 >= 0)
4057        InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4058                             DAG.getConstant(0xFF00, MVT::i16));
4059    }
4060    // If Elt0 is defined, extract it from the appropriate source.  If the
4061    // source byte is not also even, shift the extracted word right 8 bits. If
4062    // Elt1 was also defined, OR the extracted values together before
4063    // inserting them in the result.
4064    if (Elt0 >= 0) {
4065      SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4066                                    Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4067      if ((Elt0 & 1) != 0)
4068        InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4069                              DAG.getConstant(8, TLI.getShiftAmountTy()));
4070      else if (Elt1 >= 0)
4071        InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4072                             DAG.getConstant(0x00FF, MVT::i16));
4073      InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4074                         : InsElt0;
4075    }
4076    NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4077                       DAG.getIntPtrConstant(i));
4078  }
4079  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4080}
4081
4082/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4083/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4084/// done when every pair / quad of shuffle mask elements point to elements in
4085/// the right sequence. e.g.
4086/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4087static
4088SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4089                                 SelectionDAG &DAG,
4090                                 TargetLowering &TLI, DebugLoc dl) {
4091  EVT VT = SVOp->getValueType(0);
4092  SDValue V1 = SVOp->getOperand(0);
4093  SDValue V2 = SVOp->getOperand(1);
4094  unsigned NumElems = VT.getVectorNumElements();
4095  unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4096  EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4097  EVT MaskEltVT = MaskVT.getVectorElementType();
4098  EVT NewVT = MaskVT;
4099  switch (VT.getSimpleVT().SimpleTy) {
4100  default: assert(false && "Unexpected!");
4101  case MVT::v4f32: NewVT = MVT::v2f64; break;
4102  case MVT::v4i32: NewVT = MVT::v2i64; break;
4103  case MVT::v8i16: NewVT = MVT::v4i32; break;
4104  case MVT::v16i8: NewVT = MVT::v4i32; break;
4105  }
4106
4107  if (NewWidth == 2) {
4108    if (VT.isInteger())
4109      NewVT = MVT::v2i64;
4110    else
4111      NewVT = MVT::v2f64;
4112  }
4113  int Scale = NumElems / NewWidth;
4114  SmallVector<int, 8> MaskVec;
4115  for (unsigned i = 0; i < NumElems; i += Scale) {
4116    int StartIdx = -1;
4117    for (int j = 0; j < Scale; ++j) {
4118      int EltIdx = SVOp->getMaskElt(i+j);
4119      if (EltIdx < 0)
4120        continue;
4121      if (StartIdx == -1)
4122        StartIdx = EltIdx - (EltIdx % Scale);
4123      if (EltIdx != StartIdx + j)
4124        return SDValue();
4125    }
4126    if (StartIdx == -1)
4127      MaskVec.push_back(-1);
4128    else
4129      MaskVec.push_back(StartIdx / Scale);
4130  }
4131
4132  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4133  V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4134  return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4135}
4136
4137/// getVZextMovL - Return a zero-extending vector move low node.
4138///
4139static SDValue getVZextMovL(EVT VT, EVT OpVT,
4140                            SDValue SrcOp, SelectionDAG &DAG,
4141                            const X86Subtarget *Subtarget, DebugLoc dl) {
4142  if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4143    LoadSDNode *LD = NULL;
4144    if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4145      LD = dyn_cast<LoadSDNode>(SrcOp);
4146    if (!LD) {
4147      // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4148      // instead.
4149      MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4150      if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4151          SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4152          SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4153          SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4154        // PR2108
4155        OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4156        return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4157                           DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4158                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4159                                                   OpVT,
4160                                                   SrcOp.getOperand(0)
4161                                                          .getOperand(0))));
4162      }
4163    }
4164  }
4165
4166  return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4167                     DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4168                                 DAG.getNode(ISD::BIT_CONVERT, dl,
4169                                             OpVT, SrcOp)));
4170}
4171
4172/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4173/// shuffles.
4174static SDValue
4175LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4176  SDValue V1 = SVOp->getOperand(0);
4177  SDValue V2 = SVOp->getOperand(1);
4178  DebugLoc dl = SVOp->getDebugLoc();
4179  EVT VT = SVOp->getValueType(0);
4180
4181  SmallVector<std::pair<int, int>, 8> Locs;
4182  Locs.resize(4);
4183  SmallVector<int, 8> Mask1(4U, -1);
4184  SmallVector<int, 8> PermMask;
4185  SVOp->getMask(PermMask);
4186
4187  unsigned NumHi = 0;
4188  unsigned NumLo = 0;
4189  for (unsigned i = 0; i != 4; ++i) {
4190    int Idx = PermMask[i];
4191    if (Idx < 0) {
4192      Locs[i] = std::make_pair(-1, -1);
4193    } else {
4194      assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4195      if (Idx < 4) {
4196        Locs[i] = std::make_pair(0, NumLo);
4197        Mask1[NumLo] = Idx;
4198        NumLo++;
4199      } else {
4200        Locs[i] = std::make_pair(1, NumHi);
4201        if (2+NumHi < 4)
4202          Mask1[2+NumHi] = Idx;
4203        NumHi++;
4204      }
4205    }
4206  }
4207
4208  if (NumLo <= 2 && NumHi <= 2) {
4209    // If no more than two elements come from either vector. This can be
4210    // implemented with two shuffles. First shuffle gather the elements.
4211    // The second shuffle, which takes the first shuffle as both of its
4212    // vector operands, put the elements into the right order.
4213    V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4214
4215    SmallVector<int, 8> Mask2(4U, -1);
4216
4217    for (unsigned i = 0; i != 4; ++i) {
4218      if (Locs[i].first == -1)
4219        continue;
4220      else {
4221        unsigned Idx = (i < 2) ? 0 : 4;
4222        Idx += Locs[i].first * 2 + Locs[i].second;
4223        Mask2[i] = Idx;
4224      }
4225    }
4226
4227    return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4228  } else if (NumLo == 3 || NumHi == 3) {
4229    // Otherwise, we must have three elements from one vector, call it X, and
4230    // one element from the other, call it Y.  First, use a shufps to build an
4231    // intermediate vector with the one element from Y and the element from X
4232    // that will be in the same half in the final destination (the indexes don't
4233    // matter). Then, use a shufps to build the final vector, taking the half
4234    // containing the element from Y from the intermediate, and the other half
4235    // from X.
4236    if (NumHi == 3) {
4237      // Normalize it so the 3 elements come from V1.
4238      CommuteVectorShuffleMask(PermMask, VT);
4239      std::swap(V1, V2);
4240    }
4241
4242    // Find the element from V2.
4243    unsigned HiIndex;
4244    for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4245      int Val = PermMask[HiIndex];
4246      if (Val < 0)
4247        continue;
4248      if (Val >= 4)
4249        break;
4250    }
4251
4252    Mask1[0] = PermMask[HiIndex];
4253    Mask1[1] = -1;
4254    Mask1[2] = PermMask[HiIndex^1];
4255    Mask1[3] = -1;
4256    V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4257
4258    if (HiIndex >= 2) {
4259      Mask1[0] = PermMask[0];
4260      Mask1[1] = PermMask[1];
4261      Mask1[2] = HiIndex & 1 ? 6 : 4;
4262      Mask1[3] = HiIndex & 1 ? 4 : 6;
4263      return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4264    } else {
4265      Mask1[0] = HiIndex & 1 ? 2 : 0;
4266      Mask1[1] = HiIndex & 1 ? 0 : 2;
4267      Mask1[2] = PermMask[2];
4268      Mask1[3] = PermMask[3];
4269      if (Mask1[2] >= 0)
4270        Mask1[2] += 4;
4271      if (Mask1[3] >= 0)
4272        Mask1[3] += 4;
4273      return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4274    }
4275  }
4276
4277  // Break it into (shuffle shuffle_hi, shuffle_lo).
4278  Locs.clear();
4279  SmallVector<int,8> LoMask(4U, -1);
4280  SmallVector<int,8> HiMask(4U, -1);
4281
4282  SmallVector<int,8> *MaskPtr = &LoMask;
4283  unsigned MaskIdx = 0;
4284  unsigned LoIdx = 0;
4285  unsigned HiIdx = 2;
4286  for (unsigned i = 0; i != 4; ++i) {
4287    if (i == 2) {
4288      MaskPtr = &HiMask;
4289      MaskIdx = 1;
4290      LoIdx = 0;
4291      HiIdx = 2;
4292    }
4293    int Idx = PermMask[i];
4294    if (Idx < 0) {
4295      Locs[i] = std::make_pair(-1, -1);
4296    } else if (Idx < 4) {
4297      Locs[i] = std::make_pair(MaskIdx, LoIdx);
4298      (*MaskPtr)[LoIdx] = Idx;
4299      LoIdx++;
4300    } else {
4301      Locs[i] = std::make_pair(MaskIdx, HiIdx);
4302      (*MaskPtr)[HiIdx] = Idx;
4303      HiIdx++;
4304    }
4305  }
4306
4307  SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4308  SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4309  SmallVector<int, 8> MaskOps;
4310  for (unsigned i = 0; i != 4; ++i) {
4311    if (Locs[i].first == -1) {
4312      MaskOps.push_back(-1);
4313    } else {
4314      unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4315      MaskOps.push_back(Idx);
4316    }
4317  }
4318  return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4319}
4320
4321SDValue
4322X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4323  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4324  SDValue V1 = Op.getOperand(0);
4325  SDValue V2 = Op.getOperand(1);
4326  EVT VT = Op.getValueType();
4327  DebugLoc dl = Op.getDebugLoc();
4328  unsigned NumElems = VT.getVectorNumElements();
4329  bool isMMX = VT.getSizeInBits() == 64;
4330  bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4331  bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4332  bool V1IsSplat = false;
4333  bool V2IsSplat = false;
4334
4335  if (isZeroShuffle(SVOp))
4336    return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4337
4338  // Promote splats to v4f32.
4339  if (SVOp->isSplat()) {
4340    if (isMMX || NumElems < 4)
4341      return Op;
4342    return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4343  }
4344
4345  // If the shuffle can be profitably rewritten as a narrower shuffle, then
4346  // do it!
4347  if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4348    SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4349    if (NewOp.getNode())
4350      return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4351                         LowerVECTOR_SHUFFLE(NewOp, DAG));
4352  } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4353    // FIXME: Figure out a cleaner way to do this.
4354    // Try to make use of movq to zero out the top part.
4355    if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4356      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4357      if (NewOp.getNode()) {
4358        if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4359          return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4360                              DAG, Subtarget, dl);
4361      }
4362    } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4363      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4364      if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4365        return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4366                            DAG, Subtarget, dl);
4367    }
4368  }
4369
4370  if (X86::isPSHUFDMask(SVOp))
4371    return Op;
4372
4373  // Check if this can be converted into a logical shift.
4374  bool isLeft = false;
4375  unsigned ShAmt = 0;
4376  SDValue ShVal;
4377  bool isShift = getSubtarget()->hasSSE2() &&
4378    isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4379  if (isShift && ShVal.hasOneUse()) {
4380    // If the shifted value has multiple uses, it may be cheaper to use
4381    // v_set0 + movlhps or movhlps, etc.
4382    EVT EltVT = VT.getVectorElementType();
4383    ShAmt *= EltVT.getSizeInBits();
4384    return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4385  }
4386
4387  if (X86::isMOVLMask(SVOp)) {
4388    if (V1IsUndef)
4389      return V2;
4390    if (ISD::isBuildVectorAllZeros(V1.getNode()))
4391      return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4392    if (!isMMX)
4393      return Op;
4394  }
4395
4396  // FIXME: fold these into legal mask.
4397  if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4398                 X86::isMOVSLDUPMask(SVOp) ||
4399                 X86::isMOVHLPSMask(SVOp) ||
4400                 X86::isMOVLHPSMask(SVOp) ||
4401                 X86::isMOVLPMask(SVOp)))
4402    return Op;
4403
4404  if (ShouldXformToMOVHLPS(SVOp) ||
4405      ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4406    return CommuteVectorShuffle(SVOp, DAG);
4407
4408  if (isShift) {
4409    // No better options. Use a vshl / vsrl.
4410    EVT EltVT = VT.getVectorElementType();
4411    ShAmt *= EltVT.getSizeInBits();
4412    return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4413  }
4414
4415  bool Commuted = false;
4416  // FIXME: This should also accept a bitcast of a splat?  Be careful, not
4417  // 1,1,1,1 -> v8i16 though.
4418  V1IsSplat = isSplatVector(V1.getNode());
4419  V2IsSplat = isSplatVector(V2.getNode());
4420
4421  // Canonicalize the splat or undef, if present, to be on the RHS.
4422  if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4423    Op = CommuteVectorShuffle(SVOp, DAG);
4424    SVOp = cast<ShuffleVectorSDNode>(Op);
4425    V1 = SVOp->getOperand(0);
4426    V2 = SVOp->getOperand(1);
4427    std::swap(V1IsSplat, V2IsSplat);
4428    std::swap(V1IsUndef, V2IsUndef);
4429    Commuted = true;
4430  }
4431
4432  if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4433    // Shuffling low element of v1 into undef, just return v1.
4434    if (V2IsUndef)
4435      return V1;
4436    // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4437    // the instruction selector will not match, so get a canonical MOVL with
4438    // swapped operands to undo the commute.
4439    return getMOVL(DAG, dl, VT, V2, V1);
4440  }
4441
4442  if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4443      X86::isUNPCKH_v_undef_Mask(SVOp) ||
4444      X86::isUNPCKLMask(SVOp) ||
4445      X86::isUNPCKHMask(SVOp))
4446    return Op;
4447
4448  if (V2IsSplat) {
4449    // Normalize mask so all entries that point to V2 points to its first
4450    // element then try to match unpck{h|l} again. If match, return a
4451    // new vector_shuffle with the corrected mask.
4452    SDValue NewMask = NormalizeMask(SVOp, DAG);
4453    ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4454    if (NSVOp != SVOp) {
4455      if (X86::isUNPCKLMask(NSVOp, true)) {
4456        return NewMask;
4457      } else if (X86::isUNPCKHMask(NSVOp, true)) {
4458        return NewMask;
4459      }
4460    }
4461  }
4462
4463  if (Commuted) {
4464    // Commute is back and try unpck* again.
4465    // FIXME: this seems wrong.
4466    SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4467    ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4468    if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4469        X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4470        X86::isUNPCKLMask(NewSVOp) ||
4471        X86::isUNPCKHMask(NewSVOp))
4472      return NewOp;
4473  }
4474
4475  // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4476
4477  // Normalize the node to match x86 shuffle ops if needed
4478  if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4479    return CommuteVectorShuffle(SVOp, DAG);
4480
4481  // Check for legal shuffle and return?
4482  SmallVector<int, 16> PermMask;
4483  SVOp->getMask(PermMask);
4484  if (isShuffleMaskLegal(PermMask, VT))
4485    return Op;
4486
4487  // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4488  if (VT == MVT::v8i16) {
4489    SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4490    if (NewOp.getNode())
4491      return NewOp;
4492  }
4493
4494  if (VT == MVT::v16i8) {
4495    SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4496    if (NewOp.getNode())
4497      return NewOp;
4498  }
4499
4500  // Handle all 4 wide cases with a number of shuffles except for MMX.
4501  if (NumElems == 4 && !isMMX)
4502    return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4503
4504  return SDValue();
4505}
4506
4507SDValue
4508X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4509                                                SelectionDAG &DAG) {
4510  EVT VT = Op.getValueType();
4511  DebugLoc dl = Op.getDebugLoc();
4512  if (VT.getSizeInBits() == 8) {
4513    SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4514                                    Op.getOperand(0), Op.getOperand(1));
4515    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4516                                    DAG.getValueType(VT));
4517    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4518  } else if (VT.getSizeInBits() == 16) {
4519    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4520    // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4521    if (Idx == 0)
4522      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4523                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4524                                     DAG.getNode(ISD::BIT_CONVERT, dl,
4525                                                 MVT::v4i32,
4526                                                 Op.getOperand(0)),
4527                                     Op.getOperand(1)));
4528    SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4529                                    Op.getOperand(0), Op.getOperand(1));
4530    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4531                                    DAG.getValueType(VT));
4532    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4533  } else if (VT == MVT::f32) {
4534    // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4535    // the result back to FR32 register. It's only worth matching if the
4536    // result has a single use which is a store or a bitcast to i32.  And in
4537    // the case of a store, it's not worth it if the index is a constant 0,
4538    // because a MOVSSmr can be used instead, which is smaller and faster.
4539    if (!Op.hasOneUse())
4540      return SDValue();
4541    SDNode *User = *Op.getNode()->use_begin();
4542    if ((User->getOpcode() != ISD::STORE ||
4543         (isa<ConstantSDNode>(Op.getOperand(1)) &&
4544          cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4545        (User->getOpcode() != ISD::BIT_CONVERT ||
4546         User->getValueType(0) != MVT::i32))
4547      return SDValue();
4548    SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4549                                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4550                                              Op.getOperand(0)),
4551                                              Op.getOperand(1));
4552    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4553  } else if (VT == MVT::i32) {
4554    // ExtractPS works with constant index.
4555    if (isa<ConstantSDNode>(Op.getOperand(1)))
4556      return Op;
4557  }
4558  return SDValue();
4559}
4560
4561
4562SDValue
4563X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4564  if (!isa<ConstantSDNode>(Op.getOperand(1)))
4565    return SDValue();
4566
4567  if (Subtarget->hasSSE41()) {
4568    SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4569    if (Res.getNode())
4570      return Res;
4571  }
4572
4573  EVT VT = Op.getValueType();
4574  DebugLoc dl = Op.getDebugLoc();
4575  // TODO: handle v16i8.
4576  if (VT.getSizeInBits() == 16) {
4577    SDValue Vec = Op.getOperand(0);
4578    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4579    if (Idx == 0)
4580      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4581                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4582                                     DAG.getNode(ISD::BIT_CONVERT, dl,
4583                                                 MVT::v4i32, Vec),
4584                                     Op.getOperand(1)));
4585    // Transform it so it match pextrw which produces a 32-bit result.
4586    EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4587    SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4588                                    Op.getOperand(0), Op.getOperand(1));
4589    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4590                                    DAG.getValueType(VT));
4591    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4592  } else if (VT.getSizeInBits() == 32) {
4593    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4594    if (Idx == 0)
4595      return Op;
4596
4597    // SHUFPS the element to the lowest double word, then movss.
4598    int Mask[4] = { Idx, -1, -1, -1 };
4599    EVT VVT = Op.getOperand(0).getValueType();
4600    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4601                                       DAG.getUNDEF(VVT), Mask);
4602    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4603                       DAG.getIntPtrConstant(0));
4604  } else if (VT.getSizeInBits() == 64) {
4605    // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4606    // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4607    //        to match extract_elt for f64.
4608    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4609    if (Idx == 0)
4610      return Op;
4611
4612    // UNPCKHPD the element to the lowest double word, then movsd.
4613    // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4614    // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4615    int Mask[2] = { 1, -1 };
4616    EVT VVT = Op.getOperand(0).getValueType();
4617    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4618                                       DAG.getUNDEF(VVT), Mask);
4619    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4620                       DAG.getIntPtrConstant(0));
4621  }
4622
4623  return SDValue();
4624}
4625
4626SDValue
4627X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4628  EVT VT = Op.getValueType();
4629  EVT EltVT = VT.getVectorElementType();
4630  DebugLoc dl = Op.getDebugLoc();
4631
4632  SDValue N0 = Op.getOperand(0);
4633  SDValue N1 = Op.getOperand(1);
4634  SDValue N2 = Op.getOperand(2);
4635
4636  if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4637      isa<ConstantSDNode>(N2)) {
4638    unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4639                                                : X86ISD::PINSRW;
4640    // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4641    // argument.
4642    if (N1.getValueType() != MVT::i32)
4643      N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4644    if (N2.getValueType() != MVT::i32)
4645      N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4646    return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4647  } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4648    // Bits [7:6] of the constant are the source select.  This will always be
4649    //  zero here.  The DAG Combiner may combine an extract_elt index into these
4650    //  bits.  For example (insert (extract, 3), 2) could be matched by putting
4651    //  the '3' into bits [7:6] of X86ISD::INSERTPS.
4652    // Bits [5:4] of the constant are the destination select.  This is the
4653    //  value of the incoming immediate.
4654    // Bits [3:0] of the constant are the zero mask.  The DAG Combiner may
4655    //   combine either bitwise AND or insert of float 0.0 to set these bits.
4656    N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4657    // Create this as a scalar to vector..
4658    N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4659    return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4660  } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4661    // PINSR* works with constant index.
4662    return Op;
4663  }
4664  return SDValue();
4665}
4666
4667SDValue
4668X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4669  EVT VT = Op.getValueType();
4670  EVT EltVT = VT.getVectorElementType();
4671
4672  if (Subtarget->hasSSE41())
4673    return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4674
4675  if (EltVT == MVT::i8)
4676    return SDValue();
4677
4678  DebugLoc dl = Op.getDebugLoc();
4679  SDValue N0 = Op.getOperand(0);
4680  SDValue N1 = Op.getOperand(1);
4681  SDValue N2 = Op.getOperand(2);
4682
4683  if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4684    // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4685    // as its second argument.
4686    if (N1.getValueType() != MVT::i32)
4687      N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4688    if (N2.getValueType() != MVT::i32)
4689      N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4690    return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4691  }
4692  return SDValue();
4693}
4694
4695SDValue
4696X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4697  DebugLoc dl = Op.getDebugLoc();
4698  if (Op.getValueType() == MVT::v2f32)
4699    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4700                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4701                                   DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4702                                               Op.getOperand(0))));
4703
4704  if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4705    return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4706
4707  SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4708  EVT VT = MVT::v2i32;
4709  switch (Op.getValueType().getSimpleVT().SimpleTy) {
4710  default: break;
4711  case MVT::v16i8:
4712  case MVT::v8i16:
4713    VT = MVT::v4i32;
4714    break;
4715  }
4716  return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4717                     DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4718}
4719
4720// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4721// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4722// one of the above mentioned nodes. It has to be wrapped because otherwise
4723// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4724// be used to form addressing mode. These wrapped nodes will be selected
4725// into MOV32ri.
4726SDValue
4727X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4728  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4729
4730  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4731  // global base reg.
4732  unsigned char OpFlag = 0;
4733  unsigned WrapperKind = X86ISD::Wrapper;
4734  CodeModel::Model M = getTargetMachine().getCodeModel();
4735
4736  if (Subtarget->isPICStyleRIPRel() &&
4737      (M == CodeModel::Small || M == CodeModel::Kernel))
4738    WrapperKind = X86ISD::WrapperRIP;
4739  else if (Subtarget->isPICStyleGOT())
4740    OpFlag = X86II::MO_GOTOFF;
4741  else if (Subtarget->isPICStyleStubPIC())
4742    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4743
4744  SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4745                                             CP->getAlignment(),
4746                                             CP->getOffset(), OpFlag);
4747  DebugLoc DL = CP->getDebugLoc();
4748  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4749  // With PIC, the address is actually $g + Offset.
4750  if (OpFlag) {
4751    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4752                         DAG.getNode(X86ISD::GlobalBaseReg,
4753                                     DebugLoc::getUnknownLoc(), getPointerTy()),
4754                         Result);
4755  }
4756
4757  return Result;
4758}
4759
4760SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4761  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4762
4763  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4764  // global base reg.
4765  unsigned char OpFlag = 0;
4766  unsigned WrapperKind = X86ISD::Wrapper;
4767  CodeModel::Model M = getTargetMachine().getCodeModel();
4768
4769  if (Subtarget->isPICStyleRIPRel() &&
4770      (M == CodeModel::Small || M == CodeModel::Kernel))
4771    WrapperKind = X86ISD::WrapperRIP;
4772  else if (Subtarget->isPICStyleGOT())
4773    OpFlag = X86II::MO_GOTOFF;
4774  else if (Subtarget->isPICStyleStubPIC())
4775    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4776
4777  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4778                                          OpFlag);
4779  DebugLoc DL = JT->getDebugLoc();
4780  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4781
4782  // With PIC, the address is actually $g + Offset.
4783  if (OpFlag) {
4784    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4785                         DAG.getNode(X86ISD::GlobalBaseReg,
4786                                     DebugLoc::getUnknownLoc(), getPointerTy()),
4787                         Result);
4788  }
4789
4790  return Result;
4791}
4792
4793SDValue
4794X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4795  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4796
4797  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4798  // global base reg.
4799  unsigned char OpFlag = 0;
4800  unsigned WrapperKind = X86ISD::Wrapper;
4801  CodeModel::Model M = getTargetMachine().getCodeModel();
4802
4803  if (Subtarget->isPICStyleRIPRel() &&
4804      (M == CodeModel::Small || M == CodeModel::Kernel))
4805    WrapperKind = X86ISD::WrapperRIP;
4806  else if (Subtarget->isPICStyleGOT())
4807    OpFlag = X86II::MO_GOTOFF;
4808  else if (Subtarget->isPICStyleStubPIC())
4809    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4810
4811  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4812
4813  DebugLoc DL = Op.getDebugLoc();
4814  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4815
4816
4817  // With PIC, the address is actually $g + Offset.
4818  if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4819      !Subtarget->is64Bit()) {
4820    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4821                         DAG.getNode(X86ISD::GlobalBaseReg,
4822                                     DebugLoc::getUnknownLoc(),
4823                                     getPointerTy()),
4824                         Result);
4825  }
4826
4827  return Result;
4828}
4829
4830SDValue
4831X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4832  // Create the TargetBlockAddressAddress node.
4833  unsigned char OpFlags =
4834    Subtarget->ClassifyBlockAddressReference();
4835  CodeModel::Model M = getTargetMachine().getCodeModel();
4836  BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4837  DebugLoc dl = Op.getDebugLoc();
4838  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4839                                       /*isTarget=*/true, OpFlags);
4840
4841  if (Subtarget->isPICStyleRIPRel() &&
4842      (M == CodeModel::Small || M == CodeModel::Kernel))
4843    Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4844  else
4845    Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4846
4847  // With PIC, the address is actually $g + Offset.
4848  if (isGlobalRelativeToPICBase(OpFlags)) {
4849    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4850                         DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4851                         Result);
4852  }
4853
4854  return Result;
4855}
4856
4857SDValue
4858X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4859                                      int64_t Offset,
4860                                      SelectionDAG &DAG) const {
4861  // Create the TargetGlobalAddress node, folding in the constant
4862  // offset if it is legal.
4863  unsigned char OpFlags =
4864    Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4865  CodeModel::Model M = getTargetMachine().getCodeModel();
4866  SDValue Result;
4867  if (OpFlags == X86II::MO_NO_FLAG &&
4868      X86::isOffsetSuitableForCodeModel(Offset, M)) {
4869    // A direct static reference to a global.
4870    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4871    Offset = 0;
4872  } else {
4873    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4874  }
4875
4876  if (Subtarget->isPICStyleRIPRel() &&
4877      (M == CodeModel::Small || M == CodeModel::Kernel))
4878    Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4879  else
4880    Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4881
4882  // With PIC, the address is actually $g + Offset.
4883  if (isGlobalRelativeToPICBase(OpFlags)) {
4884    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4885                         DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4886                         Result);
4887  }
4888
4889  // For globals that require a load from a stub to get the address, emit the
4890  // load.
4891  if (isGlobalStubReference(OpFlags))
4892    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4893                         PseudoSourceValue::getGOT(), 0);
4894
4895  // If there was a non-zero offset that we didn't fold, create an explicit
4896  // addition for it.
4897  if (Offset != 0)
4898    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4899                         DAG.getConstant(Offset, getPointerTy()));
4900
4901  return Result;
4902}
4903
4904SDValue
4905X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4906  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4907  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4908  return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4909}
4910
4911static SDValue
4912GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4913           SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4914           unsigned char OperandFlags) {
4915  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4916  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4917  DebugLoc dl = GA->getDebugLoc();
4918  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4919                                           GA->getValueType(0),
4920                                           GA->getOffset(),
4921                                           OperandFlags);
4922  if (InFlag) {
4923    SDValue Ops[] = { Chain,  TGA, *InFlag };
4924    Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4925  } else {
4926    SDValue Ops[]  = { Chain, TGA };
4927    Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4928  }
4929
4930  // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
4931  MFI->setHasCalls(true);
4932
4933  SDValue Flag = Chain.getValue(1);
4934  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4935}
4936
4937// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4938static SDValue
4939LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4940                                const EVT PtrVT) {
4941  SDValue InFlag;
4942  DebugLoc dl = GA->getDebugLoc();  // ? function entry point might be better
4943  SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4944                                     DAG.getNode(X86ISD::GlobalBaseReg,
4945                                                 DebugLoc::getUnknownLoc(),
4946                                                 PtrVT), InFlag);
4947  InFlag = Chain.getValue(1);
4948
4949  return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4950}
4951
4952// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4953static SDValue
4954LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4955                                const EVT PtrVT) {
4956  return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4957                    X86::RAX, X86II::MO_TLSGD);
4958}
4959
4960// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4961// "local exec" model.
4962static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4963                                   const EVT PtrVT, TLSModel::Model model,
4964                                   bool is64Bit) {
4965  DebugLoc dl = GA->getDebugLoc();
4966  // Get the Thread Pointer
4967  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4968                             DebugLoc::getUnknownLoc(), PtrVT,
4969                             DAG.getRegister(is64Bit? X86::FS : X86::GS,
4970                                             MVT::i32));
4971
4972  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4973                                      NULL, 0);
4974
4975  unsigned char OperandFlags = 0;
4976  // Most TLS accesses are not RIP relative, even on x86-64.  One exception is
4977  // initialexec.
4978  unsigned WrapperKind = X86ISD::Wrapper;
4979  if (model == TLSModel::LocalExec) {
4980    OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4981  } else if (is64Bit) {
4982    assert(model == TLSModel::InitialExec);
4983    OperandFlags = X86II::MO_GOTTPOFF;
4984    WrapperKind = X86ISD::WrapperRIP;
4985  } else {
4986    assert(model == TLSModel::InitialExec);
4987    OperandFlags = X86II::MO_INDNTPOFF;
4988  }
4989
4990  // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4991  // exec)
4992  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4993                                           GA->getOffset(), OperandFlags);
4994  SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4995
4996  if (model == TLSModel::InitialExec)
4997    Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4998                         PseudoSourceValue::getGOT(), 0);
4999
5000  // The address of the thread local variable is the add of the thread
5001  // pointer with the offset of the variable.
5002  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5003}
5004
5005SDValue
5006X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5007  // TODO: implement the "local dynamic" model
5008  // TODO: implement the "initial exec"model for pic executables
5009  assert(Subtarget->isTargetELF() &&
5010         "TLS not implemented for non-ELF targets");
5011  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5012  const GlobalValue *GV = GA->getGlobal();
5013
5014  // If GV is an alias then use the aliasee for determining
5015  // thread-localness.
5016  if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5017    GV = GA->resolveAliasedGlobal(false);
5018
5019  TLSModel::Model model = getTLSModel(GV,
5020                                      getTargetMachine().getRelocationModel());
5021
5022  switch (model) {
5023  case TLSModel::GeneralDynamic:
5024  case TLSModel::LocalDynamic: // not implemented
5025    if (Subtarget->is64Bit())
5026      return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5027    return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5028
5029  case TLSModel::InitialExec:
5030  case TLSModel::LocalExec:
5031    return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5032                               Subtarget->is64Bit());
5033  }
5034
5035  llvm_unreachable("Unreachable");
5036  return SDValue();
5037}
5038
5039
5040/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5041/// take a 2 x i32 value to shift plus a shift amount.
5042SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5043  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5044  EVT VT = Op.getValueType();
5045  unsigned VTBits = VT.getSizeInBits();
5046  DebugLoc dl = Op.getDebugLoc();
5047  bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5048  SDValue ShOpLo = Op.getOperand(0);
5049  SDValue ShOpHi = Op.getOperand(1);
5050  SDValue ShAmt  = Op.getOperand(2);
5051  SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5052                                     DAG.getConstant(VTBits - 1, MVT::i8))
5053                       : DAG.getConstant(0, VT);
5054
5055  SDValue Tmp2, Tmp3;
5056  if (Op.getOpcode() == ISD::SHL_PARTS) {
5057    Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5058    Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5059  } else {
5060    Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5061    Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5062  }
5063
5064  SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5065                                DAG.getConstant(VTBits, MVT::i8));
5066  SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5067                             AndNode, DAG.getConstant(0, MVT::i8));
5068
5069  SDValue Hi, Lo;
5070  SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5071  SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5072  SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5073
5074  if (Op.getOpcode() == ISD::SHL_PARTS) {
5075    Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5076    Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5077  } else {
5078    Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5079    Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5080  }
5081
5082  SDValue Ops[2] = { Lo, Hi };
5083  return DAG.getMergeValues(Ops, 2, dl);
5084}
5085
5086SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5087  EVT SrcVT = Op.getOperand(0).getValueType();
5088
5089  if (SrcVT.isVector()) {
5090    if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5091      return Op;
5092    }
5093    return SDValue();
5094  }
5095
5096  assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5097         "Unknown SINT_TO_FP to lower!");
5098
5099  // These are really Legal; return the operand so the caller accepts it as
5100  // Legal.
5101  if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5102    return Op;
5103  if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5104      Subtarget->is64Bit()) {
5105    return Op;
5106  }
5107
5108  DebugLoc dl = Op.getDebugLoc();
5109  unsigned Size = SrcVT.getSizeInBits()/8;
5110  MachineFunction &MF = DAG.getMachineFunction();
5111  int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5112  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5113  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5114                               StackSlot,
5115                               PseudoSourceValue::getFixedStack(SSFI), 0);
5116  return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5117}
5118
5119SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5120                                     SDValue StackSlot,
5121                                     SelectionDAG &DAG) {
5122  // Build the FILD
5123  DebugLoc dl = Op.getDebugLoc();
5124  SDVTList Tys;
5125  bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5126  if (useSSE)
5127    Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5128  else
5129    Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5130  SmallVector<SDValue, 8> Ops;
5131  Ops.push_back(Chain);
5132  Ops.push_back(StackSlot);
5133  Ops.push_back(DAG.getValueType(SrcVT));
5134  SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5135                                 Tys, &Ops[0], Ops.size());
5136
5137  if (useSSE) {
5138    Chain = Result.getValue(1);
5139    SDValue InFlag = Result.getValue(2);
5140
5141    // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5142    // shouldn't be necessary except that RFP cannot be live across
5143    // multiple blocks. When stackifier is fixed, they can be uncoupled.
5144    MachineFunction &MF = DAG.getMachineFunction();
5145    int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5146    SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5147    Tys = DAG.getVTList(MVT::Other);
5148    SmallVector<SDValue, 8> Ops;
5149    Ops.push_back(Chain);
5150    Ops.push_back(Result);
5151    Ops.push_back(StackSlot);
5152    Ops.push_back(DAG.getValueType(Op.getValueType()));
5153    Ops.push_back(InFlag);
5154    Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5155    Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5156                         PseudoSourceValue::getFixedStack(SSFI), 0);
5157  }
5158
5159  return Result;
5160}
5161
5162// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5163SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5164  // This algorithm is not obvious. Here it is in C code, more or less:
5165  /*
5166    double uint64_to_double( uint32_t hi, uint32_t lo ) {
5167      static const __m128i exp = { 0x4330000045300000ULL, 0 };
5168      static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5169
5170      // Copy ints to xmm registers.
5171      __m128i xh = _mm_cvtsi32_si128( hi );
5172      __m128i xl = _mm_cvtsi32_si128( lo );
5173
5174      // Combine into low half of a single xmm register.
5175      __m128i x = _mm_unpacklo_epi32( xh, xl );
5176      __m128d d;
5177      double sd;
5178
5179      // Merge in appropriate exponents to give the integer bits the right
5180      // magnitude.
5181      x = _mm_unpacklo_epi32( x, exp );
5182
5183      // Subtract away the biases to deal with the IEEE-754 double precision
5184      // implicit 1.
5185      d = _mm_sub_pd( (__m128d) x, bias );
5186
5187      // All conversions up to here are exact. The correctly rounded result is
5188      // calculated using the current rounding mode using the following
5189      // horizontal add.
5190      d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5191      _mm_store_sd( &sd, d );   // Because we are returning doubles in XMM, this
5192                                // store doesn't really need to be here (except
5193                                // maybe to zero the other double)
5194      return sd;
5195    }
5196  */
5197
5198  DebugLoc dl = Op.getDebugLoc();
5199  LLVMContext *Context = DAG.getContext();
5200
5201  // Build some magic constants.
5202  std::vector<Constant*> CV0;
5203  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5204  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5205  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5206  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5207  Constant *C0 = ConstantVector::get(CV0);
5208  SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5209
5210  std::vector<Constant*> CV1;
5211  CV1.push_back(
5212    ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5213  CV1.push_back(
5214    ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5215  Constant *C1 = ConstantVector::get(CV1);
5216  SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5217
5218  SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5219                            DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5220                                        Op.getOperand(0),
5221                                        DAG.getIntPtrConstant(1)));
5222  SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5223                            DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5224                                        Op.getOperand(0),
5225                                        DAG.getIntPtrConstant(0)));
5226  SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5227  SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5228                              PseudoSourceValue::getConstantPool(), 0,
5229                              false, 16);
5230  SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5231  SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5232  SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5233                              PseudoSourceValue::getConstantPool(), 0,
5234                              false, 16);
5235  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5236
5237  // Add the halves; easiest way is to swap them into another reg first.
5238  int ShufMask[2] = { 1, -1 };
5239  SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5240                                      DAG.getUNDEF(MVT::v2f64), ShufMask);
5241  SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5242  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5243                     DAG.getIntPtrConstant(0));
5244}
5245
5246// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5247SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5248  DebugLoc dl = Op.getDebugLoc();
5249  // FP constant to bias correct the final result.
5250  SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5251                                   MVT::f64);
5252
5253  // Load the 32-bit value into an XMM register.
5254  SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5255                             DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5256                                         Op.getOperand(0),
5257                                         DAG.getIntPtrConstant(0)));
5258
5259  Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5260                     DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5261                     DAG.getIntPtrConstant(0));
5262
5263  // Or the load with the bias.
5264  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5265                           DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5266                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5267                                                   MVT::v2f64, Load)),
5268                           DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5269                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5270                                                   MVT::v2f64, Bias)));
5271  Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5272                   DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5273                   DAG.getIntPtrConstant(0));
5274
5275  // Subtract the bias.
5276  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5277
5278  // Handle final rounding.
5279  EVT DestVT = Op.getValueType();
5280
5281  if (DestVT.bitsLT(MVT::f64)) {
5282    return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5283                       DAG.getIntPtrConstant(0));
5284  } else if (DestVT.bitsGT(MVT::f64)) {
5285    return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5286  }
5287
5288  // Handle final rounding.
5289  return Sub;
5290}
5291
5292SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5293  SDValue N0 = Op.getOperand(0);
5294  DebugLoc dl = Op.getDebugLoc();
5295
5296  // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5297  // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5298  // the optimization here.
5299  if (DAG.SignBitIsZero(N0))
5300    return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5301
5302  EVT SrcVT = N0.getValueType();
5303  if (SrcVT == MVT::i64) {
5304    // We only handle SSE2 f64 target here; caller can expand the rest.
5305    if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5306      return SDValue();
5307
5308    return LowerUINT_TO_FP_i64(Op, DAG);
5309  } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5310    return LowerUINT_TO_FP_i32(Op, DAG);
5311  }
5312
5313  assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5314
5315  // Make a 64-bit buffer, and use it to build an FILD.
5316  SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5317  SDValue WordOff = DAG.getConstant(4, getPointerTy());
5318  SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5319                                   getPointerTy(), StackSlot, WordOff);
5320  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5321                                StackSlot, NULL, 0);
5322  SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5323                                OffsetSlot, NULL, 0);
5324  return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5325}
5326
5327std::pair<SDValue,SDValue> X86TargetLowering::
5328FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5329  DebugLoc dl = Op.getDebugLoc();
5330
5331  EVT DstTy = Op.getValueType();
5332
5333  if (!IsSigned) {
5334    assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5335    DstTy = MVT::i64;
5336  }
5337
5338  assert(DstTy.getSimpleVT() <= MVT::i64 &&
5339         DstTy.getSimpleVT() >= MVT::i16 &&
5340         "Unknown FP_TO_SINT to lower!");
5341
5342  // These are really Legal.
5343  if (DstTy == MVT::i32 &&
5344      isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5345    return std::make_pair(SDValue(), SDValue());
5346  if (Subtarget->is64Bit() &&
5347      DstTy == MVT::i64 &&
5348      isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5349    return std::make_pair(SDValue(), SDValue());
5350
5351  // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5352  // stack slot.
5353  MachineFunction &MF = DAG.getMachineFunction();
5354  unsigned MemSize = DstTy.getSizeInBits()/8;
5355  int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5356  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5357
5358  unsigned Opc;
5359  switch (DstTy.getSimpleVT().SimpleTy) {
5360  default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5361  case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5362  case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5363  case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5364  }
5365
5366  SDValue Chain = DAG.getEntryNode();
5367  SDValue Value = Op.getOperand(0);
5368  if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5369    assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5370    Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5371                         PseudoSourceValue::getFixedStack(SSFI), 0);
5372    SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5373    SDValue Ops[] = {
5374      Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5375    };
5376    Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5377    Chain = Value.getValue(1);
5378    SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5379    StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5380  }
5381
5382  // Build the FP_TO_INT*_IN_MEM
5383  SDValue Ops[] = { Chain, Value, StackSlot };
5384  SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5385
5386  return std::make_pair(FIST, StackSlot);
5387}
5388
5389SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5390  if (Op.getValueType().isVector()) {
5391    if (Op.getValueType() == MVT::v2i32 &&
5392        Op.getOperand(0).getValueType() == MVT::v2f64) {
5393      return Op;
5394    }
5395    return SDValue();
5396  }
5397
5398  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5399  SDValue FIST = Vals.first, StackSlot = Vals.second;
5400  // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5401  if (FIST.getNode() == 0) return Op;
5402
5403  // Load the result.
5404  return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5405                     FIST, StackSlot, NULL, 0);
5406}
5407
5408SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5409  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5410  SDValue FIST = Vals.first, StackSlot = Vals.second;
5411  assert(FIST.getNode() && "Unexpected failure");
5412
5413  // Load the result.
5414  return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5415                     FIST, StackSlot, NULL, 0);
5416}
5417
5418SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5419  LLVMContext *Context = DAG.getContext();
5420  DebugLoc dl = Op.getDebugLoc();
5421  EVT VT = Op.getValueType();
5422  EVT EltVT = VT;
5423  if (VT.isVector())
5424    EltVT = VT.getVectorElementType();
5425  std::vector<Constant*> CV;
5426  if (EltVT == MVT::f64) {
5427    Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5428    CV.push_back(C);
5429    CV.push_back(C);
5430  } else {
5431    Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5432    CV.push_back(C);
5433    CV.push_back(C);
5434    CV.push_back(C);
5435    CV.push_back(C);
5436  }
5437  Constant *C = ConstantVector::get(CV);
5438  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5439  SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5440                               PseudoSourceValue::getConstantPool(), 0,
5441                               false, 16);
5442  return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5443}
5444
5445SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5446  LLVMContext *Context = DAG.getContext();
5447  DebugLoc dl = Op.getDebugLoc();
5448  EVT VT = Op.getValueType();
5449  EVT EltVT = VT;
5450  if (VT.isVector())
5451    EltVT = VT.getVectorElementType();
5452  std::vector<Constant*> CV;
5453  if (EltVT == MVT::f64) {
5454    Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5455    CV.push_back(C);
5456    CV.push_back(C);
5457  } else {
5458    Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5459    CV.push_back(C);
5460    CV.push_back(C);
5461    CV.push_back(C);
5462    CV.push_back(C);
5463  }
5464  Constant *C = ConstantVector::get(CV);
5465  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5466  SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5467                               PseudoSourceValue::getConstantPool(), 0,
5468                               false, 16);
5469  if (VT.isVector()) {
5470    return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5471                       DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5472                    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5473                                Op.getOperand(0)),
5474                    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5475  } else {
5476    return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5477  }
5478}
5479
5480SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5481  LLVMContext *Context = DAG.getContext();
5482  SDValue Op0 = Op.getOperand(0);
5483  SDValue Op1 = Op.getOperand(1);
5484  DebugLoc dl = Op.getDebugLoc();
5485  EVT VT = Op.getValueType();
5486  EVT SrcVT = Op1.getValueType();
5487
5488  // If second operand is smaller, extend it first.
5489  if (SrcVT.bitsLT(VT)) {
5490    Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5491    SrcVT = VT;
5492  }
5493  // And if it is bigger, shrink it first.
5494  if (SrcVT.bitsGT(VT)) {
5495    Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5496    SrcVT = VT;
5497  }
5498
5499  // At this point the operands and the result should have the same
5500  // type, and that won't be f80 since that is not custom lowered.
5501
5502  // First get the sign bit of second operand.
5503  std::vector<Constant*> CV;
5504  if (SrcVT == MVT::f64) {
5505    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5506    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5507  } else {
5508    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5509    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5510    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5511    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5512  }
5513  Constant *C = ConstantVector::get(CV);
5514  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5515  SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5516                                PseudoSourceValue::getConstantPool(), 0,
5517                                false, 16);
5518  SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5519
5520  // Shift sign bit right or left if the two operands have different types.
5521  if (SrcVT.bitsGT(VT)) {
5522    // Op0 is MVT::f32, Op1 is MVT::f64.
5523    SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5524    SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5525                          DAG.getConstant(32, MVT::i32));
5526    SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5527    SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5528                          DAG.getIntPtrConstant(0));
5529  }
5530
5531  // Clear first operand sign bit.
5532  CV.clear();
5533  if (VT == MVT::f64) {
5534    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5535    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5536  } else {
5537    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5538    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5539    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5540    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5541  }
5542  C = ConstantVector::get(CV);
5543  CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5544  SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5545                                PseudoSourceValue::getConstantPool(), 0,
5546                                false, 16);
5547  SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5548
5549  // Or the value with the sign bit.
5550  return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5551}
5552
5553/// Emit nodes that will be selected as "test Op0,Op0", or something
5554/// equivalent.
5555SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5556                                    SelectionDAG &DAG) {
5557  DebugLoc dl = Op.getDebugLoc();
5558
5559  // CF and OF aren't always set the way we want. Determine which
5560  // of these we need.
5561  bool NeedCF = false;
5562  bool NeedOF = false;
5563  switch (X86CC) {
5564  case X86::COND_A: case X86::COND_AE:
5565  case X86::COND_B: case X86::COND_BE:
5566    NeedCF = true;
5567    break;
5568  case X86::COND_G: case X86::COND_GE:
5569  case X86::COND_L: case X86::COND_LE:
5570  case X86::COND_O: case X86::COND_NO:
5571    NeedOF = true;
5572    break;
5573  default: break;
5574  }
5575
5576  // See if we can use the EFLAGS value from the operand instead of
5577  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5578  // we prove that the arithmetic won't overflow, we can't use OF or CF.
5579  if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5580    unsigned Opcode = 0;
5581    unsigned NumOperands = 0;
5582    switch (Op.getNode()->getOpcode()) {
5583    case ISD::ADD:
5584      // Due to an isel shortcoming, be conservative if this add is likely to
5585      // be selected as part of a load-modify-store instruction. When the root
5586      // node in a match is a store, isel doesn't know how to remap non-chain
5587      // non-flag uses of other nodes in the match, such as the ADD in this
5588      // case. This leads to the ADD being left around and reselected, with
5589      // the result being two adds in the output.
5590      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5591           UE = Op.getNode()->use_end(); UI != UE; ++UI)
5592        if (UI->getOpcode() == ISD::STORE)
5593          goto default_case;
5594      if (ConstantSDNode *C =
5595            dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5596        // An add of one will be selected as an INC.
5597        if (C->getAPIntValue() == 1) {
5598          Opcode = X86ISD::INC;
5599          NumOperands = 1;
5600          break;
5601        }
5602        // An add of negative one (subtract of one) will be selected as a DEC.
5603        if (C->getAPIntValue().isAllOnesValue()) {
5604          Opcode = X86ISD::DEC;
5605          NumOperands = 1;
5606          break;
5607        }
5608      }
5609      // Otherwise use a regular EFLAGS-setting add.
5610      Opcode = X86ISD::ADD;
5611      NumOperands = 2;
5612      break;
5613    case ISD::AND: {
5614      // If the primary and result isn't used, don't bother using X86ISD::AND,
5615      // because a TEST instruction will be better.
5616      bool NonFlagUse = false;
5617      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5618           UE = Op.getNode()->use_end(); UI != UE; ++UI)
5619        if (UI->getOpcode() != ISD::BRCOND &&
5620            UI->getOpcode() != ISD::SELECT &&
5621            UI->getOpcode() != ISD::SETCC) {
5622          NonFlagUse = true;
5623          break;
5624        }
5625      if (!NonFlagUse)
5626        break;
5627    }
5628    // FALL THROUGH
5629    case ISD::SUB:
5630    case ISD::OR:
5631    case ISD::XOR:
5632      // Due to the ISEL shortcoming noted above, be conservative if this op is
5633      // likely to be selected as part of a load-modify-store instruction.
5634      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5635           UE = Op.getNode()->use_end(); UI != UE; ++UI)
5636        if (UI->getOpcode() == ISD::STORE)
5637          goto default_case;
5638      // Otherwise use a regular EFLAGS-setting instruction.
5639      switch (Op.getNode()->getOpcode()) {
5640      case ISD::SUB: Opcode = X86ISD::SUB; break;
5641      case ISD::OR:  Opcode = X86ISD::OR;  break;
5642      case ISD::XOR: Opcode = X86ISD::XOR; break;
5643      case ISD::AND: Opcode = X86ISD::AND; break;
5644      default: llvm_unreachable("unexpected operator!");
5645      }
5646      NumOperands = 2;
5647      break;
5648    case X86ISD::ADD:
5649    case X86ISD::SUB:
5650    case X86ISD::INC:
5651    case X86ISD::DEC:
5652    case X86ISD::OR:
5653    case X86ISD::XOR:
5654    case X86ISD::AND:
5655      return SDValue(Op.getNode(), 1);
5656    default:
5657    default_case:
5658      break;
5659    }
5660    if (Opcode != 0) {
5661      SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5662      SmallVector<SDValue, 4> Ops;
5663      for (unsigned i = 0; i != NumOperands; ++i)
5664        Ops.push_back(Op.getOperand(i));
5665      SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5666      DAG.ReplaceAllUsesWith(Op, New);
5667      return SDValue(New.getNode(), 1);
5668    }
5669  }
5670
5671  // Otherwise just emit a CMP with 0, which is the TEST pattern.
5672  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5673                     DAG.getConstant(0, Op.getValueType()));
5674}
5675
5676/// Emit nodes that will be selected as "cmp Op0,Op1", or something
5677/// equivalent.
5678SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5679                                   SelectionDAG &DAG) {
5680  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5681    if (C->getAPIntValue() == 0)
5682      return EmitTest(Op0, X86CC, DAG);
5683
5684  DebugLoc dl = Op0.getDebugLoc();
5685  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5686}
5687
5688SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5689  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5690  SDValue Op0 = Op.getOperand(0);
5691  SDValue Op1 = Op.getOperand(1);
5692  DebugLoc dl = Op.getDebugLoc();
5693  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5694
5695  // Lower (X & (1 << N)) == 0 to BT(X, N).
5696  // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5697  // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5698  if (Op0.getOpcode() == ISD::AND &&
5699      Op0.hasOneUse() &&
5700      Op1.getOpcode() == ISD::Constant &&
5701      cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5702      (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5703    SDValue LHS, RHS;
5704    if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5705      if (ConstantSDNode *Op010C =
5706            dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5707        if (Op010C->getZExtValue() == 1) {
5708          LHS = Op0.getOperand(0);
5709          RHS = Op0.getOperand(1).getOperand(1);
5710        }
5711    } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5712      if (ConstantSDNode *Op000C =
5713            dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5714        if (Op000C->getZExtValue() == 1) {
5715          LHS = Op0.getOperand(1);
5716          RHS = Op0.getOperand(0).getOperand(1);
5717        }
5718    } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5719      ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5720      SDValue AndLHS = Op0.getOperand(0);
5721      if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5722        LHS = AndLHS.getOperand(0);
5723        RHS = AndLHS.getOperand(1);
5724      }
5725    }
5726
5727    if (LHS.getNode()) {
5728      // If LHS is i8, promote it to i16 with any_extend.  There is no i8 BT
5729      // instruction.  Since the shift amount is in-range-or-undefined, we know
5730      // that doing a bittest on the i16 value is ok.  We extend to i32 because
5731      // the encoding for the i16 version is larger than the i32 version.
5732      if (LHS.getValueType() == MVT::i8)
5733        LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5734
5735      // If the operand types disagree, extend the shift amount to match.  Since
5736      // BT ignores high bits (like shifts) we can use anyextend.
5737      if (LHS.getValueType() != RHS.getValueType())
5738        RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5739
5740      SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5741      unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5742      return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5743                         DAG.getConstant(Cond, MVT::i8), BT);
5744    }
5745  }
5746
5747  bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5748  unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5749  if (X86CC == X86::COND_INVALID)
5750    return SDValue();
5751
5752  SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5753
5754  // Use sbb x, x to materialize carry bit into a GPR.
5755  if (X86CC == X86::COND_B) {
5756    return DAG.getNode(ISD::AND, dl, MVT::i8,
5757                       DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5758                                   DAG.getConstant(X86CC, MVT::i8), Cond),
5759                       DAG.getConstant(1, MVT::i8));
5760  }
5761
5762  return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5763                     DAG.getConstant(X86CC, MVT::i8), Cond);
5764}
5765
5766SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5767  SDValue Cond;
5768  SDValue Op0 = Op.getOperand(0);
5769  SDValue Op1 = Op.getOperand(1);
5770  SDValue CC = Op.getOperand(2);
5771  EVT VT = Op.getValueType();
5772  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5773  bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5774  DebugLoc dl = Op.getDebugLoc();
5775
5776  if (isFP) {
5777    unsigned SSECC = 8;
5778    EVT VT0 = Op0.getValueType();
5779    assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5780    unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5781    bool Swap = false;
5782
5783    switch (SetCCOpcode) {
5784    default: break;
5785    case ISD::SETOEQ:
5786    case ISD::SETEQ:  SSECC = 0; break;
5787    case ISD::SETOGT:
5788    case ISD::SETGT: Swap = true; // Fallthrough
5789    case ISD::SETLT:
5790    case ISD::SETOLT: SSECC = 1; break;
5791    case ISD::SETOGE:
5792    case ISD::SETGE: Swap = true; // Fallthrough
5793    case ISD::SETLE:
5794    case ISD::SETOLE: SSECC = 2; break;
5795    case ISD::SETUO:  SSECC = 3; break;
5796    case ISD::SETUNE:
5797    case ISD::SETNE:  SSECC = 4; break;
5798    case ISD::SETULE: Swap = true;
5799    case ISD::SETUGE: SSECC = 5; break;
5800    case ISD::SETULT: Swap = true;
5801    case ISD::SETUGT: SSECC = 6; break;
5802    case ISD::SETO:   SSECC = 7; break;
5803    }
5804    if (Swap)
5805      std::swap(Op0, Op1);
5806
5807    // In the two special cases we can't handle, emit two comparisons.
5808    if (SSECC == 8) {
5809      if (SetCCOpcode == ISD::SETUEQ) {
5810        SDValue UNORD, EQ;
5811        UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5812        EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5813        return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5814      }
5815      else if (SetCCOpcode == ISD::SETONE) {
5816        SDValue ORD, NEQ;
5817        ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5818        NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5819        return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5820      }
5821      llvm_unreachable("Illegal FP comparison");
5822    }
5823    // Handle all other FP comparisons here.
5824    return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5825  }
5826
5827  // We are handling one of the integer comparisons here.  Since SSE only has
5828  // GT and EQ comparisons for integer, swapping operands and multiple
5829  // operations may be required for some comparisons.
5830  unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5831  bool Swap = false, Invert = false, FlipSigns = false;
5832
5833  switch (VT.getSimpleVT().SimpleTy) {
5834  default: break;
5835  case MVT::v8i8:
5836  case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5837  case MVT::v4i16:
5838  case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5839  case MVT::v2i32:
5840  case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5841  case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5842  }
5843
5844  switch (SetCCOpcode) {
5845  default: break;
5846  case ISD::SETNE:  Invert = true;
5847  case ISD::SETEQ:  Opc = EQOpc; break;
5848  case ISD::SETLT:  Swap = true;
5849  case ISD::SETGT:  Opc = GTOpc; break;
5850  case ISD::SETGE:  Swap = true;
5851  case ISD::SETLE:  Opc = GTOpc; Invert = true; break;
5852  case ISD::SETULT: Swap = true;
5853  case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5854  case ISD::SETUGE: Swap = true;
5855  case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5856  }
5857  if (Swap)
5858    std::swap(Op0, Op1);
5859
5860  // Since SSE has no unsigned integer comparisons, we need to flip  the sign
5861  // bits of the inputs before performing those operations.
5862  if (FlipSigns) {
5863    EVT EltVT = VT.getVectorElementType();
5864    SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5865                                      EltVT);
5866    std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5867    SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5868                                    SignBits.size());
5869    Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5870    Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5871  }
5872
5873  SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5874
5875  // If the logical-not of the result is required, perform that now.
5876  if (Invert)
5877    Result = DAG.getNOT(dl, Result, VT);
5878
5879  return Result;
5880}
5881
5882// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5883static bool isX86LogicalCmp(SDValue Op) {
5884  unsigned Opc = Op.getNode()->getOpcode();
5885  if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5886    return true;
5887  if (Op.getResNo() == 1 &&
5888      (Opc == X86ISD::ADD ||
5889       Opc == X86ISD::SUB ||
5890       Opc == X86ISD::SMUL ||
5891       Opc == X86ISD::UMUL ||
5892       Opc == X86ISD::INC ||
5893       Opc == X86ISD::DEC ||
5894       Opc == X86ISD::OR ||
5895       Opc == X86ISD::XOR ||
5896       Opc == X86ISD::AND))
5897    return true;
5898
5899  return false;
5900}
5901
5902SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5903  bool addTest = true;
5904  SDValue Cond  = Op.getOperand(0);
5905  DebugLoc dl = Op.getDebugLoc();
5906  SDValue CC;
5907
5908  if (Cond.getOpcode() == ISD::SETCC) {
5909    SDValue NewCond = LowerSETCC(Cond, DAG);
5910    if (NewCond.getNode())
5911      Cond = NewCond;
5912  }
5913
5914  // Look pass (and (setcc_carry (cmp ...)), 1).
5915  if (Cond.getOpcode() == ISD::AND &&
5916      Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
5917    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5918    if (C && C->getAPIntValue() == 1)
5919      Cond = Cond.getOperand(0);
5920  }
5921
5922  // If condition flag is set by a X86ISD::CMP, then use it as the condition
5923  // setting operand in place of the X86ISD::SETCC.
5924  if (Cond.getOpcode() == X86ISD::SETCC ||
5925      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
5926    CC = Cond.getOperand(0);
5927
5928    SDValue Cmp = Cond.getOperand(1);
5929    unsigned Opc = Cmp.getOpcode();
5930    EVT VT = Op.getValueType();
5931
5932    bool IllegalFPCMov = false;
5933    if (VT.isFloatingPoint() && !VT.isVector() &&
5934        !isScalarFPTypeInSSEReg(VT))  // FPStack?
5935      IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5936
5937    if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5938        Opc == X86ISD::BT) { // FIXME
5939      Cond = Cmp;
5940      addTest = false;
5941    }
5942  }
5943
5944  if (addTest) {
5945    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5946    Cond = EmitTest(Cond, X86::COND_NE, DAG);
5947  }
5948
5949  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5950  SmallVector<SDValue, 4> Ops;
5951  // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5952  // condition is true.
5953  Ops.push_back(Op.getOperand(2));
5954  Ops.push_back(Op.getOperand(1));
5955  Ops.push_back(CC);
5956  Ops.push_back(Cond);
5957  return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5958}
5959
5960// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5961// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5962// from the AND / OR.
5963static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5964  Opc = Op.getOpcode();
5965  if (Opc != ISD::OR && Opc != ISD::AND)
5966    return false;
5967  return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5968          Op.getOperand(0).hasOneUse() &&
5969          Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5970          Op.getOperand(1).hasOneUse());
5971}
5972
5973// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5974// 1 and that the SETCC node has a single use.
5975static bool isXor1OfSetCC(SDValue Op) {
5976  if (Op.getOpcode() != ISD::XOR)
5977    return false;
5978  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5979  if (N1C && N1C->getAPIntValue() == 1) {
5980    return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5981      Op.getOperand(0).hasOneUse();
5982  }
5983  return false;
5984}
5985
5986SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5987  bool addTest = true;
5988  SDValue Chain = Op.getOperand(0);
5989  SDValue Cond  = Op.getOperand(1);
5990  SDValue Dest  = Op.getOperand(2);
5991  DebugLoc dl = Op.getDebugLoc();
5992  SDValue CC;
5993
5994  if (Cond.getOpcode() == ISD::SETCC) {
5995    SDValue NewCond = LowerSETCC(Cond, DAG);
5996    if (NewCond.getNode())
5997      Cond = NewCond;
5998  }
5999#if 0
6000  // FIXME: LowerXALUO doesn't handle these!!
6001  else if (Cond.getOpcode() == X86ISD::ADD  ||
6002           Cond.getOpcode() == X86ISD::SUB  ||
6003           Cond.getOpcode() == X86ISD::SMUL ||
6004           Cond.getOpcode() == X86ISD::UMUL)
6005    Cond = LowerXALUO(Cond, DAG);
6006#endif
6007
6008  // Look pass (and (setcc_carry (cmp ...)), 1).
6009  if (Cond.getOpcode() == ISD::AND &&
6010      Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6011    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6012    if (C && C->getAPIntValue() == 1)
6013      Cond = Cond.getOperand(0);
6014  }
6015
6016  // If condition flag is set by a X86ISD::CMP, then use it as the condition
6017  // setting operand in place of the X86ISD::SETCC.
6018  if (Cond.getOpcode() == X86ISD::SETCC ||
6019      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6020    CC = Cond.getOperand(0);
6021
6022    SDValue Cmp = Cond.getOperand(1);
6023    unsigned Opc = Cmp.getOpcode();
6024    // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6025    if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6026      Cond = Cmp;
6027      addTest = false;
6028    } else {
6029      switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6030      default: break;
6031      case X86::COND_O:
6032      case X86::COND_B:
6033        // These can only come from an arithmetic instruction with overflow,
6034        // e.g. SADDO, UADDO.
6035        Cond = Cond.getNode()->getOperand(1);
6036        addTest = false;
6037        break;
6038      }
6039    }
6040  } else {
6041    unsigned CondOpc;
6042    if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6043      SDValue Cmp = Cond.getOperand(0).getOperand(1);
6044      if (CondOpc == ISD::OR) {
6045        // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6046        // two branches instead of an explicit OR instruction with a
6047        // separate test.
6048        if (Cmp == Cond.getOperand(1).getOperand(1) &&
6049            isX86LogicalCmp(Cmp)) {
6050          CC = Cond.getOperand(0).getOperand(0);
6051          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6052                              Chain, Dest, CC, Cmp);
6053          CC = Cond.getOperand(1).getOperand(0);
6054          Cond = Cmp;
6055          addTest = false;
6056        }
6057      } else { // ISD::AND
6058        // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6059        // two branches instead of an explicit AND instruction with a
6060        // separate test. However, we only do this if this block doesn't
6061        // have a fall-through edge, because this requires an explicit
6062        // jmp when the condition is false.
6063        if (Cmp == Cond.getOperand(1).getOperand(1) &&
6064            isX86LogicalCmp(Cmp) &&
6065            Op.getNode()->hasOneUse()) {
6066          X86::CondCode CCode =
6067            (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6068          CCode = X86::GetOppositeBranchCondition(CCode);
6069          CC = DAG.getConstant(CCode, MVT::i8);
6070          SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6071          // Look for an unconditional branch following this conditional branch.
6072          // We need this because we need to reverse the successors in order
6073          // to implement FCMP_OEQ.
6074          if (User.getOpcode() == ISD::BR) {
6075            SDValue FalseBB = User.getOperand(1);
6076            SDValue NewBR =
6077              DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6078            assert(NewBR == User);
6079            Dest = FalseBB;
6080
6081            Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6082                                Chain, Dest, CC, Cmp);
6083            X86::CondCode CCode =
6084              (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6085            CCode = X86::GetOppositeBranchCondition(CCode);
6086            CC = DAG.getConstant(CCode, MVT::i8);
6087            Cond = Cmp;
6088            addTest = false;
6089          }
6090        }
6091      }
6092    } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6093      // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6094      // It should be transformed during dag combiner except when the condition
6095      // is set by a arithmetics with overflow node.
6096      X86::CondCode CCode =
6097        (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6098      CCode = X86::GetOppositeBranchCondition(CCode);
6099      CC = DAG.getConstant(CCode, MVT::i8);
6100      Cond = Cond.getOperand(0).getOperand(1);
6101      addTest = false;
6102    }
6103  }
6104
6105  if (addTest) {
6106    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6107    Cond = EmitTest(Cond, X86::COND_NE, DAG);
6108  }
6109  return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6110                     Chain, Dest, CC, Cond);
6111}
6112
6113
6114// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6115// Calls to _alloca is needed to probe the stack when allocating more than 4k
6116// bytes in one go. Touching the stack at 4K increments is necessary to ensure
6117// that the guard pages used by the OS virtual memory manager are allocated in
6118// correct sequence.
6119SDValue
6120X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6121                                           SelectionDAG &DAG) {
6122  assert(Subtarget->isTargetCygMing() &&
6123         "This should be used only on Cygwin/Mingw targets");
6124  DebugLoc dl = Op.getDebugLoc();
6125
6126  // Get the inputs.
6127  SDValue Chain = Op.getOperand(0);
6128  SDValue Size  = Op.getOperand(1);
6129  // FIXME: Ensure alignment here
6130
6131  SDValue Flag;
6132
6133  EVT IntPtr = getPointerTy();
6134  EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6135
6136  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6137
6138  Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6139  Flag = Chain.getValue(1);
6140
6141  SDVTList  NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6142  SDValue Ops[] = { Chain,
6143                      DAG.getTargetExternalSymbol("_alloca", IntPtr),
6144                      DAG.getRegister(X86::EAX, IntPtr),
6145                      DAG.getRegister(X86StackPtr, SPTy),
6146                      Flag };
6147  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6148  Flag = Chain.getValue(1);
6149
6150  Chain = DAG.getCALLSEQ_END(Chain,
6151                             DAG.getIntPtrConstant(0, true),
6152                             DAG.getIntPtrConstant(0, true),
6153                             Flag);
6154
6155  Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6156
6157  SDValue Ops1[2] = { Chain.getValue(0), Chain };
6158  return DAG.getMergeValues(Ops1, 2, dl);
6159}
6160
6161SDValue
6162X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6163                                           SDValue Chain,
6164                                           SDValue Dst, SDValue Src,
6165                                           SDValue Size, unsigned Align,
6166                                           const Value *DstSV,
6167                                           uint64_t DstSVOff) {
6168  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6169
6170  // If not DWORD aligned or size is more than the threshold, call the library.
6171  // The libc version is likely to be faster for these cases. It can use the
6172  // address value and run time information about the CPU.
6173  if ((Align & 3) != 0 ||
6174      !ConstantSize ||
6175      ConstantSize->getZExtValue() >
6176        getSubtarget()->getMaxInlineSizeThreshold()) {
6177    SDValue InFlag(0, 0);
6178
6179    // Check to see if there is a specialized entry-point for memory zeroing.
6180    ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6181
6182    if (const char *bzeroEntry =  V &&
6183        V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6184      EVT IntPtr = getPointerTy();
6185      const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6186      TargetLowering::ArgListTy Args;
6187      TargetLowering::ArgListEntry Entry;
6188      Entry.Node = Dst;
6189      Entry.Ty = IntPtrTy;
6190      Args.push_back(Entry);
6191      Entry.Node = Size;
6192      Args.push_back(Entry);
6193      std::pair<SDValue,SDValue> CallResult =
6194        LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6195                    false, false, false, false,
6196                    0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6197                    DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6198      return CallResult.second;
6199    }
6200
6201    // Otherwise have the target-independent code call memset.
6202    return SDValue();
6203  }
6204
6205  uint64_t SizeVal = ConstantSize->getZExtValue();
6206  SDValue InFlag(0, 0);
6207  EVT AVT;
6208  SDValue Count;
6209  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6210  unsigned BytesLeft = 0;
6211  bool TwoRepStos = false;
6212  if (ValC) {
6213    unsigned ValReg;
6214    uint64_t Val = ValC->getZExtValue() & 255;
6215
6216    // If the value is a constant, then we can potentially use larger sets.
6217    switch (Align & 3) {
6218    case 2:   // WORD aligned
6219      AVT = MVT::i16;
6220      ValReg = X86::AX;
6221      Val = (Val << 8) | Val;
6222      break;
6223    case 0:  // DWORD aligned
6224      AVT = MVT::i32;
6225      ValReg = X86::EAX;
6226      Val = (Val << 8)  | Val;
6227      Val = (Val << 16) | Val;
6228      if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) {  // QWORD aligned
6229        AVT = MVT::i64;
6230        ValReg = X86::RAX;
6231        Val = (Val << 32) | Val;
6232      }
6233      break;
6234    default:  // Byte aligned
6235      AVT = MVT::i8;
6236      ValReg = X86::AL;
6237      Count = DAG.getIntPtrConstant(SizeVal);
6238      break;
6239    }
6240
6241    if (AVT.bitsGT(MVT::i8)) {
6242      unsigned UBytes = AVT.getSizeInBits() / 8;
6243      Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6244      BytesLeft = SizeVal % UBytes;
6245    }
6246
6247    Chain  = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6248                              InFlag);
6249    InFlag = Chain.getValue(1);
6250  } else {
6251    AVT = MVT::i8;
6252    Count  = DAG.getIntPtrConstant(SizeVal);
6253    Chain  = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6254    InFlag = Chain.getValue(1);
6255  }
6256
6257  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6258                                                              X86::ECX,
6259                            Count, InFlag);
6260  InFlag = Chain.getValue(1);
6261  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6262                                                              X86::EDI,
6263                            Dst, InFlag);
6264  InFlag = Chain.getValue(1);
6265
6266  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6267  SmallVector<SDValue, 8> Ops;
6268  Ops.push_back(Chain);
6269  Ops.push_back(DAG.getValueType(AVT));
6270  Ops.push_back(InFlag);
6271  Chain  = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6272
6273  if (TwoRepStos) {
6274    InFlag = Chain.getValue(1);
6275    Count  = Size;
6276    EVT CVT = Count.getValueType();
6277    SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6278                               DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6279    Chain  = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6280                                                             X86::ECX,
6281                              Left, InFlag);
6282    InFlag = Chain.getValue(1);
6283    Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6284    Ops.clear();
6285    Ops.push_back(Chain);
6286    Ops.push_back(DAG.getValueType(MVT::i8));
6287    Ops.push_back(InFlag);
6288    Chain  = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6289  } else if (BytesLeft) {
6290    // Handle the last 1 - 7 bytes.
6291    unsigned Offset = SizeVal - BytesLeft;
6292    EVT AddrVT = Dst.getValueType();
6293    EVT SizeVT = Size.getValueType();
6294
6295    Chain = DAG.getMemset(Chain, dl,
6296                          DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6297                                      DAG.getConstant(Offset, AddrVT)),
6298                          Src,
6299                          DAG.getConstant(BytesLeft, SizeVT),
6300                          Align, DstSV, DstSVOff + Offset);
6301  }
6302
6303  // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6304  return Chain;
6305}
6306
6307SDValue
6308X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6309                                      SDValue Chain, SDValue Dst, SDValue Src,
6310                                      SDValue Size, unsigned Align,
6311                                      bool AlwaysInline,
6312                                      const Value *DstSV, uint64_t DstSVOff,
6313                                      const Value *SrcSV, uint64_t SrcSVOff) {
6314  // This requires the copy size to be a constant, preferrably
6315  // within a subtarget-specific limit.
6316  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6317  if (!ConstantSize)
6318    return SDValue();
6319  uint64_t SizeVal = ConstantSize->getZExtValue();
6320  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6321    return SDValue();
6322
6323  /// If not DWORD aligned, call the library.
6324  if ((Align & 3) != 0)
6325    return SDValue();
6326
6327  // DWORD aligned
6328  EVT AVT = MVT::i32;
6329  if (Subtarget->is64Bit() && ((Align & 0x7) == 0))  // QWORD aligned
6330    AVT = MVT::i64;
6331
6332  unsigned UBytes = AVT.getSizeInBits() / 8;
6333  unsigned CountVal = SizeVal / UBytes;
6334  SDValue Count = DAG.getIntPtrConstant(CountVal);
6335  unsigned BytesLeft = SizeVal % UBytes;
6336
6337  SDValue InFlag(0, 0);
6338  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6339                                                              X86::ECX,
6340                            Count, InFlag);
6341  InFlag = Chain.getValue(1);
6342  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6343                                                             X86::EDI,
6344                            Dst, InFlag);
6345  InFlag = Chain.getValue(1);
6346  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6347                                                              X86::ESI,
6348                            Src, InFlag);
6349  InFlag = Chain.getValue(1);
6350
6351  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6352  SmallVector<SDValue, 8> Ops;
6353  Ops.push_back(Chain);
6354  Ops.push_back(DAG.getValueType(AVT));
6355  Ops.push_back(InFlag);
6356  SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6357
6358  SmallVector<SDValue, 4> Results;
6359  Results.push_back(RepMovs);
6360  if (BytesLeft) {
6361    // Handle the last 1 - 7 bytes.
6362    unsigned Offset = SizeVal - BytesLeft;
6363    EVT DstVT = Dst.getValueType();
6364    EVT SrcVT = Src.getValueType();
6365    EVT SizeVT = Size.getValueType();
6366    Results.push_back(DAG.getMemcpy(Chain, dl,
6367                                    DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6368                                                DAG.getConstant(Offset, DstVT)),
6369                                    DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6370                                                DAG.getConstant(Offset, SrcVT)),
6371                                    DAG.getConstant(BytesLeft, SizeVT),
6372                                    Align, AlwaysInline,
6373                                    DstSV, DstSVOff + Offset,
6374                                    SrcSV, SrcSVOff + Offset));
6375  }
6376
6377  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6378                     &Results[0], Results.size());
6379}
6380
6381SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6382  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6383  DebugLoc dl = Op.getDebugLoc();
6384
6385  if (!Subtarget->is64Bit()) {
6386    // vastart just stores the address of the VarArgsFrameIndex slot into the
6387    // memory location argument.
6388    SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6389    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6390  }
6391
6392  // __va_list_tag:
6393  //   gp_offset         (0 - 6 * 8)
6394  //   fp_offset         (48 - 48 + 8 * 16)
6395  //   overflow_arg_area (point to parameters coming in memory).
6396  //   reg_save_area
6397  SmallVector<SDValue, 8> MemOps;
6398  SDValue FIN = Op.getOperand(1);
6399  // Store gp_offset
6400  SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6401                                 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6402                                 FIN, SV, 0);
6403  MemOps.push_back(Store);
6404
6405  // Store fp_offset
6406  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6407                    FIN, DAG.getIntPtrConstant(4));
6408  Store = DAG.getStore(Op.getOperand(0), dl,
6409                       DAG.getConstant(VarArgsFPOffset, MVT::i32),
6410                       FIN, SV, 0);
6411  MemOps.push_back(Store);
6412
6413  // Store ptr to overflow_arg_area
6414  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6415                    FIN, DAG.getIntPtrConstant(4));
6416  SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6417  Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6418  MemOps.push_back(Store);
6419
6420  // Store ptr to reg_save_area.
6421  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6422                    FIN, DAG.getIntPtrConstant(8));
6423  SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6424  Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6425  MemOps.push_back(Store);
6426  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6427                     &MemOps[0], MemOps.size());
6428}
6429
6430SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6431  // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6432  assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6433  SDValue Chain = Op.getOperand(0);
6434  SDValue SrcPtr = Op.getOperand(1);
6435  SDValue SrcSV = Op.getOperand(2);
6436
6437  llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6438  return SDValue();
6439}
6440
6441SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6442  // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6443  assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6444  SDValue Chain = Op.getOperand(0);
6445  SDValue DstPtr = Op.getOperand(1);
6446  SDValue SrcPtr = Op.getOperand(2);
6447  const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6448  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6449  DebugLoc dl = Op.getDebugLoc();
6450
6451  return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6452                       DAG.getIntPtrConstant(24), 8, false,
6453                       DstSV, 0, SrcSV, 0);
6454}
6455
6456SDValue
6457X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6458  DebugLoc dl = Op.getDebugLoc();
6459  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6460  switch (IntNo) {
6461  default: return SDValue();    // Don't custom lower most intrinsics.
6462  // Comparison intrinsics.
6463  case Intrinsic::x86_sse_comieq_ss:
6464  case Intrinsic::x86_sse_comilt_ss:
6465  case Intrinsic::x86_sse_comile_ss:
6466  case Intrinsic::x86_sse_comigt_ss:
6467  case Intrinsic::x86_sse_comige_ss:
6468  case Intrinsic::x86_sse_comineq_ss:
6469  case Intrinsic::x86_sse_ucomieq_ss:
6470  case Intrinsic::x86_sse_ucomilt_ss:
6471  case Intrinsic::x86_sse_ucomile_ss:
6472  case Intrinsic::x86_sse_ucomigt_ss:
6473  case Intrinsic::x86_sse_ucomige_ss:
6474  case Intrinsic::x86_sse_ucomineq_ss:
6475  case Intrinsic::x86_sse2_comieq_sd:
6476  case Intrinsic::x86_sse2_comilt_sd:
6477  case Intrinsic::x86_sse2_comile_sd:
6478  case Intrinsic::x86_sse2_comigt_sd:
6479  case Intrinsic::x86_sse2_comige_sd:
6480  case Intrinsic::x86_sse2_comineq_sd:
6481  case Intrinsic::x86_sse2_ucomieq_sd:
6482  case Intrinsic::x86_sse2_ucomilt_sd:
6483  case Intrinsic::x86_sse2_ucomile_sd:
6484  case Intrinsic::x86_sse2_ucomigt_sd:
6485  case Intrinsic::x86_sse2_ucomige_sd:
6486  case Intrinsic::x86_sse2_ucomineq_sd: {
6487    unsigned Opc = 0;
6488    ISD::CondCode CC = ISD::SETCC_INVALID;
6489    switch (IntNo) {
6490    default: break;
6491    case Intrinsic::x86_sse_comieq_ss:
6492    case Intrinsic::x86_sse2_comieq_sd:
6493      Opc = X86ISD::COMI;
6494      CC = ISD::SETEQ;
6495      break;
6496    case Intrinsic::x86_sse_comilt_ss:
6497    case Intrinsic::x86_sse2_comilt_sd:
6498      Opc = X86ISD::COMI;
6499      CC = ISD::SETLT;
6500      break;
6501    case Intrinsic::x86_sse_comile_ss:
6502    case Intrinsic::x86_sse2_comile_sd:
6503      Opc = X86ISD::COMI;
6504      CC = ISD::SETLE;
6505      break;
6506    case Intrinsic::x86_sse_comigt_ss:
6507    case Intrinsic::x86_sse2_comigt_sd:
6508      Opc = X86ISD::COMI;
6509      CC = ISD::SETGT;
6510      break;
6511    case Intrinsic::x86_sse_comige_ss:
6512    case Intrinsic::x86_sse2_comige_sd:
6513      Opc = X86ISD::COMI;
6514      CC = ISD::SETGE;
6515      break;
6516    case Intrinsic::x86_sse_comineq_ss:
6517    case Intrinsic::x86_sse2_comineq_sd:
6518      Opc = X86ISD::COMI;
6519      CC = ISD::SETNE;
6520      break;
6521    case Intrinsic::x86_sse_ucomieq_ss:
6522    case Intrinsic::x86_sse2_ucomieq_sd:
6523      Opc = X86ISD::UCOMI;
6524      CC = ISD::SETEQ;
6525      break;
6526    case Intrinsic::x86_sse_ucomilt_ss:
6527    case Intrinsic::x86_sse2_ucomilt_sd:
6528      Opc = X86ISD::UCOMI;
6529      CC = ISD::SETLT;
6530      break;
6531    case Intrinsic::x86_sse_ucomile_ss:
6532    case Intrinsic::x86_sse2_ucomile_sd:
6533      Opc = X86ISD::UCOMI;
6534      CC = ISD::SETLE;
6535      break;
6536    case Intrinsic::x86_sse_ucomigt_ss:
6537    case Intrinsic::x86_sse2_ucomigt_sd:
6538      Opc = X86ISD::UCOMI;
6539      CC = ISD::SETGT;
6540      break;
6541    case Intrinsic::x86_sse_ucomige_ss:
6542    case Intrinsic::x86_sse2_ucomige_sd:
6543      Opc = X86ISD::UCOMI;
6544      CC = ISD::SETGE;
6545      break;
6546    case Intrinsic::x86_sse_ucomineq_ss:
6547    case Intrinsic::x86_sse2_ucomineq_sd:
6548      Opc = X86ISD::UCOMI;
6549      CC = ISD::SETNE;
6550      break;
6551    }
6552
6553    SDValue LHS = Op.getOperand(1);
6554    SDValue RHS = Op.getOperand(2);
6555    unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6556    assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6557    SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6558    SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6559                                DAG.getConstant(X86CC, MVT::i8), Cond);
6560    return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6561  }
6562  // ptest intrinsics. The intrinsic these come from are designed to return
6563  // an integer value, not just an instruction so lower it to the ptest
6564  // pattern and a setcc for the result.
6565  case Intrinsic::x86_sse41_ptestz:
6566  case Intrinsic::x86_sse41_ptestc:
6567  case Intrinsic::x86_sse41_ptestnzc:{
6568    unsigned X86CC = 0;
6569    switch (IntNo) {
6570    default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6571    case Intrinsic::x86_sse41_ptestz:
6572      // ZF = 1
6573      X86CC = X86::COND_E;
6574      break;
6575    case Intrinsic::x86_sse41_ptestc:
6576      // CF = 1
6577      X86CC = X86::COND_B;
6578      break;
6579    case Intrinsic::x86_sse41_ptestnzc:
6580      // ZF and CF = 0
6581      X86CC = X86::COND_A;
6582      break;
6583    }
6584
6585    SDValue LHS = Op.getOperand(1);
6586    SDValue RHS = Op.getOperand(2);
6587    SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6588    SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6589    SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6590    return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6591  }
6592
6593  // Fix vector shift instructions where the last operand is a non-immediate
6594  // i32 value.
6595  case Intrinsic::x86_sse2_pslli_w:
6596  case Intrinsic::x86_sse2_pslli_d:
6597  case Intrinsic::x86_sse2_pslli_q:
6598  case Intrinsic::x86_sse2_psrli_w:
6599  case Intrinsic::x86_sse2_psrli_d:
6600  case Intrinsic::x86_sse2_psrli_q:
6601  case Intrinsic::x86_sse2_psrai_w:
6602  case Intrinsic::x86_sse2_psrai_d:
6603  case Intrinsic::x86_mmx_pslli_w:
6604  case Intrinsic::x86_mmx_pslli_d:
6605  case Intrinsic::x86_mmx_pslli_q:
6606  case Intrinsic::x86_mmx_psrli_w:
6607  case Intrinsic::x86_mmx_psrli_d:
6608  case Intrinsic::x86_mmx_psrli_q:
6609  case Intrinsic::x86_mmx_psrai_w:
6610  case Intrinsic::x86_mmx_psrai_d: {
6611    SDValue ShAmt = Op.getOperand(2);
6612    if (isa<ConstantSDNode>(ShAmt))
6613      return SDValue();
6614
6615    unsigned NewIntNo = 0;
6616    EVT ShAmtVT = MVT::v4i32;
6617    switch (IntNo) {
6618    case Intrinsic::x86_sse2_pslli_w:
6619      NewIntNo = Intrinsic::x86_sse2_psll_w;
6620      break;
6621    case Intrinsic::x86_sse2_pslli_d:
6622      NewIntNo = Intrinsic::x86_sse2_psll_d;
6623      break;
6624    case Intrinsic::x86_sse2_pslli_q:
6625      NewIntNo = Intrinsic::x86_sse2_psll_q;
6626      break;
6627    case Intrinsic::x86_sse2_psrli_w:
6628      NewIntNo = Intrinsic::x86_sse2_psrl_w;
6629      break;
6630    case Intrinsic::x86_sse2_psrli_d:
6631      NewIntNo = Intrinsic::x86_sse2_psrl_d;
6632      break;
6633    case Intrinsic::x86_sse2_psrli_q:
6634      NewIntNo = Intrinsic::x86_sse2_psrl_q;
6635      break;
6636    case Intrinsic::x86_sse2_psrai_w:
6637      NewIntNo = Intrinsic::x86_sse2_psra_w;
6638      break;
6639    case Intrinsic::x86_sse2_psrai_d:
6640      NewIntNo = Intrinsic::x86_sse2_psra_d;
6641      break;
6642    default: {
6643      ShAmtVT = MVT::v2i32;
6644      switch (IntNo) {
6645      case Intrinsic::x86_mmx_pslli_w:
6646        NewIntNo = Intrinsic::x86_mmx_psll_w;
6647        break;
6648      case Intrinsic::x86_mmx_pslli_d:
6649        NewIntNo = Intrinsic::x86_mmx_psll_d;
6650        break;
6651      case Intrinsic::x86_mmx_pslli_q:
6652        NewIntNo = Intrinsic::x86_mmx_psll_q;
6653        break;
6654      case Intrinsic::x86_mmx_psrli_w:
6655        NewIntNo = Intrinsic::x86_mmx_psrl_w;
6656        break;
6657      case Intrinsic::x86_mmx_psrli_d:
6658        NewIntNo = Intrinsic::x86_mmx_psrl_d;
6659        break;
6660      case Intrinsic::x86_mmx_psrli_q:
6661        NewIntNo = Intrinsic::x86_mmx_psrl_q;
6662        break;
6663      case Intrinsic::x86_mmx_psrai_w:
6664        NewIntNo = Intrinsic::x86_mmx_psra_w;
6665        break;
6666      case Intrinsic::x86_mmx_psrai_d:
6667        NewIntNo = Intrinsic::x86_mmx_psra_d;
6668        break;
6669      default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
6670      }
6671      break;
6672    }
6673    }
6674
6675    // The vector shift intrinsics with scalars uses 32b shift amounts but
6676    // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6677    // to be zero.
6678    SDValue ShOps[4];
6679    ShOps[0] = ShAmt;
6680    ShOps[1] = DAG.getConstant(0, MVT::i32);
6681    if (ShAmtVT == MVT::v4i32) {
6682      ShOps[2] = DAG.getUNDEF(MVT::i32);
6683      ShOps[3] = DAG.getUNDEF(MVT::i32);
6684      ShAmt =  DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6685    } else {
6686      ShAmt =  DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6687    }
6688
6689    EVT VT = Op.getValueType();
6690    ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6691    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6692                       DAG.getConstant(NewIntNo, MVT::i32),
6693                       Op.getOperand(1), ShAmt);
6694  }
6695  }
6696}
6697
6698SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6699  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6700  DebugLoc dl = Op.getDebugLoc();
6701
6702  if (Depth > 0) {
6703    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6704    SDValue Offset =
6705      DAG.getConstant(TD->getPointerSize(),
6706                      Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6707    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6708                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
6709                                   FrameAddr, Offset),
6710                       NULL, 0);
6711  }
6712
6713  // Just load the return address.
6714  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6715  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6716                     RetAddrFI, NULL, 0);
6717}
6718
6719SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6720  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6721  MFI->setFrameAddressIsTaken(true);
6722  EVT VT = Op.getValueType();
6723  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
6724  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6725  unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6726  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6727  while (Depth--)
6728    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6729  return FrameAddr;
6730}
6731
6732SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6733                                                     SelectionDAG &DAG) {
6734  return DAG.getIntPtrConstant(2*TD->getPointerSize());
6735}
6736
6737SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6738{
6739  MachineFunction &MF = DAG.getMachineFunction();
6740  SDValue Chain     = Op.getOperand(0);
6741  SDValue Offset    = Op.getOperand(1);
6742  SDValue Handler   = Op.getOperand(2);
6743  DebugLoc dl       = Op.getDebugLoc();
6744
6745  SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6746                                  getPointerTy());
6747  unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6748
6749  SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6750                                  DAG.getIntPtrConstant(-TD->getPointerSize()));
6751  StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6752  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6753  Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6754  MF.getRegInfo().addLiveOut(StoreAddrReg);
6755
6756  return DAG.getNode(X86ISD::EH_RETURN, dl,
6757                     MVT::Other,
6758                     Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6759}
6760
6761SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6762                                             SelectionDAG &DAG) {
6763  SDValue Root = Op.getOperand(0);
6764  SDValue Trmp = Op.getOperand(1); // trampoline
6765  SDValue FPtr = Op.getOperand(2); // nested function
6766  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6767  DebugLoc dl  = Op.getDebugLoc();
6768
6769  const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6770
6771  const X86InstrInfo *TII =
6772    ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6773
6774  if (Subtarget->is64Bit()) {
6775    SDValue OutChains[6];
6776
6777    // Large code-model.
6778
6779    const unsigned char JMP64r  = TII->getBaseOpcodeFor(X86::JMP64r);
6780    const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6781
6782    const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6783    const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6784
6785    const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6786
6787    // Load the pointer to the nested function into R11.
6788    unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6789    SDValue Addr = Trmp;
6790    OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6791                                Addr, TrmpAddr, 0);
6792
6793    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6794                       DAG.getConstant(2, MVT::i64));
6795    OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6796
6797    // Load the 'nest' parameter value into R10.
6798    // R10 is specified in X86CallingConv.td
6799    OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6800    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6801                       DAG.getConstant(10, MVT::i64));
6802    OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6803                                Addr, TrmpAddr, 10);
6804
6805    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6806                       DAG.getConstant(12, MVT::i64));
6807    OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6808
6809    // Jump to the nested function.
6810    OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6811    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6812                       DAG.getConstant(20, MVT::i64));
6813    OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6814                                Addr, TrmpAddr, 20);
6815
6816    unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6817    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6818                       DAG.getConstant(22, MVT::i64));
6819    OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6820                                TrmpAddr, 22);
6821
6822    SDValue Ops[] =
6823      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6824    return DAG.getMergeValues(Ops, 2, dl);
6825  } else {
6826    const Function *Func =
6827      cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6828    CallingConv::ID CC = Func->getCallingConv();
6829    unsigned NestReg;
6830
6831    switch (CC) {
6832    default:
6833      llvm_unreachable("Unsupported calling convention");
6834    case CallingConv::C:
6835    case CallingConv::X86_StdCall: {
6836      // Pass 'nest' parameter in ECX.
6837      // Must be kept in sync with X86CallingConv.td
6838      NestReg = X86::ECX;
6839
6840      // Check that ECX wasn't needed by an 'inreg' parameter.
6841      const FunctionType *FTy = Func->getFunctionType();
6842      const AttrListPtr &Attrs = Func->getAttributes();
6843
6844      if (!Attrs.isEmpty() && !Func->isVarArg()) {
6845        unsigned InRegCount = 0;
6846        unsigned Idx = 1;
6847
6848        for (FunctionType::param_iterator I = FTy->param_begin(),
6849             E = FTy->param_end(); I != E; ++I, ++Idx)
6850          if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6851            // FIXME: should only count parameters that are lowered to integers.
6852            InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6853
6854        if (InRegCount > 2) {
6855          llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6856        }
6857      }
6858      break;
6859    }
6860    case CallingConv::X86_FastCall:
6861    case CallingConv::Fast:
6862      // Pass 'nest' parameter in EAX.
6863      // Must be kept in sync with X86CallingConv.td
6864      NestReg = X86::EAX;
6865      break;
6866    }
6867
6868    SDValue OutChains[4];
6869    SDValue Addr, Disp;
6870
6871    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6872                       DAG.getConstant(10, MVT::i32));
6873    Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6874
6875    const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6876    const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6877    OutChains[0] = DAG.getStore(Root, dl,
6878                                DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6879                                Trmp, TrmpAddr, 0);
6880
6881    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6882                       DAG.getConstant(1, MVT::i32));
6883    OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6884
6885    const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6886    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6887                       DAG.getConstant(5, MVT::i32));
6888    OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6889                                TrmpAddr, 5, false, 1);
6890
6891    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6892                       DAG.getConstant(6, MVT::i32));
6893    OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6894
6895    SDValue Ops[] =
6896      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6897    return DAG.getMergeValues(Ops, 2, dl);
6898  }
6899}
6900
6901SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6902  /*
6903   The rounding mode is in bits 11:10 of FPSR, and has the following
6904   settings:
6905     00 Round to nearest
6906     01 Round to -inf
6907     10 Round to +inf
6908     11 Round to 0
6909
6910  FLT_ROUNDS, on the other hand, expects the following:
6911    -1 Undefined
6912     0 Round to 0
6913     1 Round to nearest
6914     2 Round to +inf
6915     3 Round to -inf
6916
6917  To perform the conversion, we do:
6918    (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6919  */
6920
6921  MachineFunction &MF = DAG.getMachineFunction();
6922  const TargetMachine &TM = MF.getTarget();
6923  const TargetFrameInfo &TFI = *TM.getFrameInfo();
6924  unsigned StackAlignment = TFI.getStackAlignment();
6925  EVT VT = Op.getValueType();
6926  DebugLoc dl = Op.getDebugLoc();
6927
6928  // Save FP Control Word to stack slot
6929  int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6930  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6931
6932  SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6933                              DAG.getEntryNode(), StackSlot);
6934
6935  // Load FP Control Word from stack slot
6936  SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6937
6938  // Transform as necessary
6939  SDValue CWD1 =
6940    DAG.getNode(ISD::SRL, dl, MVT::i16,
6941                DAG.getNode(ISD::AND, dl, MVT::i16,
6942                            CWD, DAG.getConstant(0x800, MVT::i16)),
6943                DAG.getConstant(11, MVT::i8));
6944  SDValue CWD2 =
6945    DAG.getNode(ISD::SRL, dl, MVT::i16,
6946                DAG.getNode(ISD::AND, dl, MVT::i16,
6947                            CWD, DAG.getConstant(0x400, MVT::i16)),
6948                DAG.getConstant(9, MVT::i8));
6949
6950  SDValue RetVal =
6951    DAG.getNode(ISD::AND, dl, MVT::i16,
6952                DAG.getNode(ISD::ADD, dl, MVT::i16,
6953                            DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6954                            DAG.getConstant(1, MVT::i16)),
6955                DAG.getConstant(3, MVT::i16));
6956
6957
6958  return DAG.getNode((VT.getSizeInBits() < 16 ?
6959                      ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6960}
6961
6962SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6963  EVT VT = Op.getValueType();
6964  EVT OpVT = VT;
6965  unsigned NumBits = VT.getSizeInBits();
6966  DebugLoc dl = Op.getDebugLoc();
6967
6968  Op = Op.getOperand(0);
6969  if (VT == MVT::i8) {
6970    // Zero extend to i32 since there is not an i8 bsr.
6971    OpVT = MVT::i32;
6972    Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6973  }
6974
6975  // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6976  SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6977  Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6978
6979  // If src is zero (i.e. bsr sets ZF), returns NumBits.
6980  SmallVector<SDValue, 4> Ops;
6981  Ops.push_back(Op);
6982  Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6983  Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6984  Ops.push_back(Op.getValue(1));
6985  Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6986
6987  // Finally xor with NumBits-1.
6988  Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6989
6990  if (VT == MVT::i8)
6991    Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6992  return Op;
6993}
6994
6995SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6996  EVT VT = Op.getValueType();
6997  EVT OpVT = VT;
6998  unsigned NumBits = VT.getSizeInBits();
6999  DebugLoc dl = Op.getDebugLoc();
7000
7001  Op = Op.getOperand(0);
7002  if (VT == MVT::i8) {
7003    OpVT = MVT::i32;
7004    Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7005  }
7006
7007  // Issue a bsf (scan bits forward) which also sets EFLAGS.
7008  SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7009  Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7010
7011  // If src is zero (i.e. bsf sets ZF), returns NumBits.
7012  SmallVector<SDValue, 4> Ops;
7013  Ops.push_back(Op);
7014  Ops.push_back(DAG.getConstant(NumBits, OpVT));
7015  Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
7016  Ops.push_back(Op.getValue(1));
7017  Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
7018
7019  if (VT == MVT::i8)
7020    Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7021  return Op;
7022}
7023
7024SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7025  EVT VT = Op.getValueType();
7026  assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7027  DebugLoc dl = Op.getDebugLoc();
7028
7029  //  ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7030  //  ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7031  //  ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7032  //  ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7033  //  ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7034  //
7035  //  AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7036  //  AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7037  //  return AloBlo + AloBhi + AhiBlo;
7038
7039  SDValue A = Op.getOperand(0);
7040  SDValue B = Op.getOperand(1);
7041
7042  SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7043                       DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7044                       A, DAG.getConstant(32, MVT::i32));
7045  SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7046                       DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7047                       B, DAG.getConstant(32, MVT::i32));
7048  SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7049                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7050                       A, B);
7051  SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7052                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7053                       A, Bhi);
7054  SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7055                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7056                       Ahi, B);
7057  AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7058                       DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7059                       AloBhi, DAG.getConstant(32, MVT::i32));
7060  AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7061                       DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7062                       AhiBlo, DAG.getConstant(32, MVT::i32));
7063  SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7064  Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7065  return Res;
7066}
7067
7068
7069SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7070  // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7071  // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7072  // looks for this combo and may remove the "setcc" instruction if the "setcc"
7073  // has only one use.
7074  SDNode *N = Op.getNode();
7075  SDValue LHS = N->getOperand(0);
7076  SDValue RHS = N->getOperand(1);
7077  unsigned BaseOp = 0;
7078  unsigned Cond = 0;
7079  DebugLoc dl = Op.getDebugLoc();
7080
7081  switch (Op.getOpcode()) {
7082  default: llvm_unreachable("Unknown ovf instruction!");
7083  case ISD::SADDO:
7084    // A subtract of one will be selected as a INC. Note that INC doesn't
7085    // set CF, so we can't do this for UADDO.
7086    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7087      if (C->getAPIntValue() == 1) {
7088        BaseOp = X86ISD::INC;
7089        Cond = X86::COND_O;
7090        break;
7091      }
7092    BaseOp = X86ISD::ADD;
7093    Cond = X86::COND_O;
7094    break;
7095  case ISD::UADDO:
7096    BaseOp = X86ISD::ADD;
7097    Cond = X86::COND_B;
7098    break;
7099  case ISD::SSUBO:
7100    // A subtract of one will be selected as a DEC. Note that DEC doesn't
7101    // set CF, so we can't do this for USUBO.
7102    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7103      if (C->getAPIntValue() == 1) {
7104        BaseOp = X86ISD::DEC;
7105        Cond = X86::COND_O;
7106        break;
7107      }
7108    BaseOp = X86ISD::SUB;
7109    Cond = X86::COND_O;
7110    break;
7111  case ISD::USUBO:
7112    BaseOp = X86ISD::SUB;
7113    Cond = X86::COND_B;
7114    break;
7115  case ISD::SMULO:
7116    BaseOp = X86ISD::SMUL;
7117    Cond = X86::COND_O;
7118    break;
7119  case ISD::UMULO:
7120    BaseOp = X86ISD::UMUL;
7121    Cond = X86::COND_B;
7122    break;
7123  }
7124
7125  // Also sets EFLAGS.
7126  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7127  SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7128
7129  SDValue SetCC =
7130    DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7131                DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7132
7133  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7134  return Sum;
7135}
7136
7137SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7138  EVT T = Op.getValueType();
7139  DebugLoc dl = Op.getDebugLoc();
7140  unsigned Reg = 0;
7141  unsigned size = 0;
7142  switch(T.getSimpleVT().SimpleTy) {
7143  default:
7144    assert(false && "Invalid value type!");
7145  case MVT::i8:  Reg = X86::AL;  size = 1; break;
7146  case MVT::i16: Reg = X86::AX;  size = 2; break;
7147  case MVT::i32: Reg = X86::EAX; size = 4; break;
7148  case MVT::i64:
7149    assert(Subtarget->is64Bit() && "Node not type legal!");
7150    Reg = X86::RAX; size = 8;
7151    break;
7152  }
7153  SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7154                                    Op.getOperand(2), SDValue());
7155  SDValue Ops[] = { cpIn.getValue(0),
7156                    Op.getOperand(1),
7157                    Op.getOperand(3),
7158                    DAG.getTargetConstant(size, MVT::i8),
7159                    cpIn.getValue(1) };
7160  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7161  SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7162  SDValue cpOut =
7163    DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7164  return cpOut;
7165}
7166
7167SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7168                                                 SelectionDAG &DAG) {
7169  assert(Subtarget->is64Bit() && "Result not type legalized?");
7170  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7171  SDValue TheChain = Op.getOperand(0);
7172  DebugLoc dl = Op.getDebugLoc();
7173  SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7174  SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7175  SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7176                                   rax.getValue(2));
7177  SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7178                            DAG.getConstant(32, MVT::i8));
7179  SDValue Ops[] = {
7180    DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7181    rdx.getValue(1)
7182  };
7183  return DAG.getMergeValues(Ops, 2, dl);
7184}
7185
7186SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7187  SDNode *Node = Op.getNode();
7188  DebugLoc dl = Node->getDebugLoc();
7189  EVT T = Node->getValueType(0);
7190  SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7191                              DAG.getConstant(0, T), Node->getOperand(2));
7192  return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7193                       cast<AtomicSDNode>(Node)->getMemoryVT(),
7194                       Node->getOperand(0),
7195                       Node->getOperand(1), negOp,
7196                       cast<AtomicSDNode>(Node)->getSrcValue(),
7197                       cast<AtomicSDNode>(Node)->getAlignment());
7198}
7199
7200/// LowerOperation - Provide custom lowering hooks for some operations.
7201///
7202SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7203  switch (Op.getOpcode()) {
7204  default: llvm_unreachable("Should not custom lower this!");
7205  case ISD::ATOMIC_CMP_SWAP:    return LowerCMP_SWAP(Op,DAG);
7206  case ISD::ATOMIC_LOAD_SUB:    return LowerLOAD_SUB(Op,DAG);
7207  case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
7208  case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
7209  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7210  case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);
7211  case ISD::SCALAR_TO_VECTOR:   return LowerSCALAR_TO_VECTOR(Op, DAG);
7212  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
7213  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
7214  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
7215  case ISD::ExternalSymbol:     return LowerExternalSymbol(Op, DAG);
7216  case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
7217  case ISD::SHL_PARTS:
7218  case ISD::SRA_PARTS:
7219  case ISD::SRL_PARTS:          return LowerShift(Op, DAG);
7220  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
7221  case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG);
7222  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
7223  case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG);
7224  case ISD::FABS:               return LowerFABS(Op, DAG);
7225  case ISD::FNEG:               return LowerFNEG(Op, DAG);
7226  case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
7227  case ISD::SETCC:              return LowerSETCC(Op, DAG);
7228  case ISD::VSETCC:             return LowerVSETCC(Op, DAG);
7229  case ISD::SELECT:             return LowerSELECT(Op, DAG);
7230  case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
7231  case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
7232  case ISD::VASTART:            return LowerVASTART(Op, DAG);
7233  case ISD::VAARG:              return LowerVAARG(Op, DAG);
7234  case ISD::VACOPY:             return LowerVACOPY(Op, DAG);
7235  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7236  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
7237  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
7238  case ISD::FRAME_TO_ARGS_OFFSET:
7239                                return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7240  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7241  case ISD::EH_RETURN:          return LowerEH_RETURN(Op, DAG);
7242  case ISD::TRAMPOLINE:         return LowerTRAMPOLINE(Op, DAG);
7243  case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
7244  case ISD::CTLZ:               return LowerCTLZ(Op, DAG);
7245  case ISD::CTTZ:               return LowerCTTZ(Op, DAG);
7246  case ISD::MUL:                return LowerMUL_V2I64(Op, DAG);
7247  case ISD::SADDO:
7248  case ISD::UADDO:
7249  case ISD::SSUBO:
7250  case ISD::USUBO:
7251  case ISD::SMULO:
7252  case ISD::UMULO:              return LowerXALUO(Op, DAG);
7253  case ISD::READCYCLECOUNTER:   return LowerREADCYCLECOUNTER(Op, DAG);
7254  }
7255}
7256
7257void X86TargetLowering::
7258ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7259                        SelectionDAG &DAG, unsigned NewOp) {
7260  EVT T = Node->getValueType(0);
7261  DebugLoc dl = Node->getDebugLoc();
7262  assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7263
7264  SDValue Chain = Node->getOperand(0);
7265  SDValue In1 = Node->getOperand(1);
7266  SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7267                             Node->getOperand(2), DAG.getIntPtrConstant(0));
7268  SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7269                             Node->getOperand(2), DAG.getIntPtrConstant(1));
7270  SDValue Ops[] = { Chain, In1, In2L, In2H };
7271  SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7272  SDValue Result =
7273    DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7274                            cast<MemSDNode>(Node)->getMemOperand());
7275  SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7276  Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7277  Results.push_back(Result.getValue(2));
7278}
7279
7280/// ReplaceNodeResults - Replace a node with an illegal result type
7281/// with a new node built out of custom code.
7282void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7283                                           SmallVectorImpl<SDValue>&Results,
7284                                           SelectionDAG &DAG) {
7285  DebugLoc dl = N->getDebugLoc();
7286  switch (N->getOpcode()) {
7287  default:
7288    assert(false && "Do not know how to custom type legalize this operation!");
7289    return;
7290  case ISD::FP_TO_SINT: {
7291    std::pair<SDValue,SDValue> Vals =
7292        FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7293    SDValue FIST = Vals.first, StackSlot = Vals.second;
7294    if (FIST.getNode() != 0) {
7295      EVT VT = N->getValueType(0);
7296      // Return a load from the stack slot.
7297      Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7298    }
7299    return;
7300  }
7301  case ISD::READCYCLECOUNTER: {
7302    SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7303    SDValue TheChain = N->getOperand(0);
7304    SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7305    SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7306                                     rd.getValue(1));
7307    SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7308                                     eax.getValue(2));
7309    // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7310    SDValue Ops[] = { eax, edx };
7311    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7312    Results.push_back(edx.getValue(1));
7313    return;
7314  }
7315  case ISD::SDIV:
7316  case ISD::UDIV:
7317  case ISD::SREM:
7318  case ISD::UREM: {
7319    EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7320    Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7321    return;
7322  }
7323  case ISD::ATOMIC_CMP_SWAP: {
7324    EVT T = N->getValueType(0);
7325    assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7326    SDValue cpInL, cpInH;
7327    cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7328                        DAG.getConstant(0, MVT::i32));
7329    cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7330                        DAG.getConstant(1, MVT::i32));
7331    cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7332    cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7333                             cpInL.getValue(1));
7334    SDValue swapInL, swapInH;
7335    swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7336                          DAG.getConstant(0, MVT::i32));
7337    swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7338                          DAG.getConstant(1, MVT::i32));
7339    swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7340                               cpInH.getValue(1));
7341    swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7342                               swapInL.getValue(1));
7343    SDValue Ops[] = { swapInH.getValue(0),
7344                      N->getOperand(1),
7345                      swapInH.getValue(1) };
7346    SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7347    SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7348    SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7349                                        MVT::i32, Result.getValue(1));
7350    SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7351                                        MVT::i32, cpOutL.getValue(2));
7352    SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7353    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7354    Results.push_back(cpOutH.getValue(1));
7355    return;
7356  }
7357  case ISD::ATOMIC_LOAD_ADD:
7358    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7359    return;
7360  case ISD::ATOMIC_LOAD_AND:
7361    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7362    return;
7363  case ISD::ATOMIC_LOAD_NAND:
7364    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7365    return;
7366  case ISD::ATOMIC_LOAD_OR:
7367    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7368    return;
7369  case ISD::ATOMIC_LOAD_SUB:
7370    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7371    return;
7372  case ISD::ATOMIC_LOAD_XOR:
7373    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7374    return;
7375  case ISD::ATOMIC_SWAP:
7376    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7377    return;
7378  }
7379}
7380
7381const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7382  switch (Opcode) {
7383  default: return NULL;
7384  case X86ISD::BSF:                return "X86ISD::BSF";
7385  case X86ISD::BSR:                return "X86ISD::BSR";
7386  case X86ISD::SHLD:               return "X86ISD::SHLD";
7387  case X86ISD::SHRD:               return "X86ISD::SHRD";
7388  case X86ISD::FAND:               return "X86ISD::FAND";
7389  case X86ISD::FOR:                return "X86ISD::FOR";
7390  case X86ISD::FXOR:               return "X86ISD::FXOR";
7391  case X86ISD::FSRL:               return "X86ISD::FSRL";
7392  case X86ISD::FILD:               return "X86ISD::FILD";
7393  case X86ISD::FILD_FLAG:          return "X86ISD::FILD_FLAG";
7394  case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7395  case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7396  case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7397  case X86ISD::FLD:                return "X86ISD::FLD";
7398  case X86ISD::FST:                return "X86ISD::FST";
7399  case X86ISD::CALL:               return "X86ISD::CALL";
7400  case X86ISD::RDTSC_DAG:          return "X86ISD::RDTSC_DAG";
7401  case X86ISD::BT:                 return "X86ISD::BT";
7402  case X86ISD::CMP:                return "X86ISD::CMP";
7403  case X86ISD::COMI:               return "X86ISD::COMI";
7404  case X86ISD::UCOMI:              return "X86ISD::UCOMI";
7405  case X86ISD::SETCC:              return "X86ISD::SETCC";
7406  case X86ISD::SETCC_CARRY:        return "X86ISD::SETCC_CARRY";
7407  case X86ISD::CMOV:               return "X86ISD::CMOV";
7408  case X86ISD::BRCOND:             return "X86ISD::BRCOND";
7409  case X86ISD::RET_FLAG:           return "X86ISD::RET_FLAG";
7410  case X86ISD::REP_STOS:           return "X86ISD::REP_STOS";
7411  case X86ISD::REP_MOVS:           return "X86ISD::REP_MOVS";
7412  case X86ISD::GlobalBaseReg:      return "X86ISD::GlobalBaseReg";
7413  case X86ISD::Wrapper:            return "X86ISD::Wrapper";
7414  case X86ISD::WrapperRIP:         return "X86ISD::WrapperRIP";
7415  case X86ISD::PEXTRB:             return "X86ISD::PEXTRB";
7416  case X86ISD::PEXTRW:             return "X86ISD::PEXTRW";
7417  case X86ISD::INSERTPS:           return "X86ISD::INSERTPS";
7418  case X86ISD::PINSRB:             return "X86ISD::PINSRB";
7419  case X86ISD::PINSRW:             return "X86ISD::PINSRW";
7420  case X86ISD::PSHUFB:             return "X86ISD::PSHUFB";
7421  case X86ISD::FMAX:               return "X86ISD::FMAX";
7422  case X86ISD::FMIN:               return "X86ISD::FMIN";
7423  case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
7424  case X86ISD::FRCP:               return "X86ISD::FRCP";
7425  case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
7426  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7427  case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
7428  case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
7429  case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
7430  case X86ISD::LCMPXCHG_DAG:       return "X86ISD::LCMPXCHG_DAG";
7431  case X86ISD::LCMPXCHG8_DAG:      return "X86ISD::LCMPXCHG8_DAG";
7432  case X86ISD::ATOMADD64_DAG:      return "X86ISD::ATOMADD64_DAG";
7433  case X86ISD::ATOMSUB64_DAG:      return "X86ISD::ATOMSUB64_DAG";
7434  case X86ISD::ATOMOR64_DAG:       return "X86ISD::ATOMOR64_DAG";
7435  case X86ISD::ATOMXOR64_DAG:      return "X86ISD::ATOMXOR64_DAG";
7436  case X86ISD::ATOMAND64_DAG:      return "X86ISD::ATOMAND64_DAG";
7437  case X86ISD::ATOMNAND64_DAG:     return "X86ISD::ATOMNAND64_DAG";
7438  case X86ISD::VZEXT_MOVL:         return "X86ISD::VZEXT_MOVL";
7439  case X86ISD::VZEXT_LOAD:         return "X86ISD::VZEXT_LOAD";
7440  case X86ISD::VSHL:               return "X86ISD::VSHL";
7441  case X86ISD::VSRL:               return "X86ISD::VSRL";
7442  case X86ISD::CMPPD:              return "X86ISD::CMPPD";
7443  case X86ISD::CMPPS:              return "X86ISD::CMPPS";
7444  case X86ISD::PCMPEQB:            return "X86ISD::PCMPEQB";
7445  case X86ISD::PCMPEQW:            return "X86ISD::PCMPEQW";
7446  case X86ISD::PCMPEQD:            return "X86ISD::PCMPEQD";
7447  case X86ISD::PCMPEQQ:            return "X86ISD::PCMPEQQ";
7448  case X86ISD::PCMPGTB:            return "X86ISD::PCMPGTB";
7449  case X86ISD::PCMPGTW:            return "X86ISD::PCMPGTW";
7450  case X86ISD::PCMPGTD:            return "X86ISD::PCMPGTD";
7451  case X86ISD::PCMPGTQ:            return "X86ISD::PCMPGTQ";
7452  case X86ISD::ADD:                return "X86ISD::ADD";
7453  case X86ISD::SUB:                return "X86ISD::SUB";
7454  case X86ISD::SMUL:               return "X86ISD::SMUL";
7455  case X86ISD::UMUL:               return "X86ISD::UMUL";
7456  case X86ISD::INC:                return "X86ISD::INC";
7457  case X86ISD::DEC:                return "X86ISD::DEC";
7458  case X86ISD::OR:                 return "X86ISD::OR";
7459  case X86ISD::XOR:                return "X86ISD::XOR";
7460  case X86ISD::AND:                return "X86ISD::AND";
7461  case X86ISD::MUL_IMM:            return "X86ISD::MUL_IMM";
7462  case X86ISD::PTEST:              return "X86ISD::PTEST";
7463  case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7464  }
7465}
7466
7467// isLegalAddressingMode - Return true if the addressing mode represented
7468// by AM is legal for this target, for a load/store of the specified type.
7469bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7470                                              const Type *Ty) const {
7471  // X86 supports extremely general addressing modes.
7472  CodeModel::Model M = getTargetMachine().getCodeModel();
7473
7474  // X86 allows a sign-extended 32-bit immediate field as a displacement.
7475  if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7476    return false;
7477
7478  if (AM.BaseGV) {
7479    unsigned GVFlags =
7480      Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7481
7482    // If a reference to this global requires an extra load, we can't fold it.
7483    if (isGlobalStubReference(GVFlags))
7484      return false;
7485
7486    // If BaseGV requires a register for the PIC base, we cannot also have a
7487    // BaseReg specified.
7488    if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7489      return false;
7490
7491    // If lower 4G is not available, then we must use rip-relative addressing.
7492    if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7493      return false;
7494  }
7495
7496  switch (AM.Scale) {
7497  case 0:
7498  case 1:
7499  case 2:
7500  case 4:
7501  case 8:
7502    // These scales always work.
7503    break;
7504  case 3:
7505  case 5:
7506  case 9:
7507    // These scales are formed with basereg+scalereg.  Only accept if there is
7508    // no basereg yet.
7509    if (AM.HasBaseReg)
7510      return false;
7511    break;
7512  default:  // Other stuff never works.
7513    return false;
7514  }
7515
7516  return true;
7517}
7518
7519
7520bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7521  if (!Ty1->isInteger() || !Ty2->isInteger())
7522    return false;
7523  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7524  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7525  if (NumBits1 <= NumBits2)
7526    return false;
7527  return Subtarget->is64Bit() || NumBits1 < 64;
7528}
7529
7530bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7531  if (!VT1.isInteger() || !VT2.isInteger())
7532    return false;
7533  unsigned NumBits1 = VT1.getSizeInBits();
7534  unsigned NumBits2 = VT2.getSizeInBits();
7535  if (NumBits1 <= NumBits2)
7536    return false;
7537  return Subtarget->is64Bit() || NumBits1 < 64;
7538}
7539
7540bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7541  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7542  return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7543         Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7544}
7545
7546bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7547  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7548  return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7549}
7550
7551bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7552  // i16 instructions are longer (0x66 prefix) and potentially slower.
7553  return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7554}
7555
7556/// isShuffleMaskLegal - Targets can use this to indicate that they only
7557/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7558/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7559/// are assumed to be legal.
7560bool
7561X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7562                                      EVT VT) const {
7563  // Only do shuffles on 128-bit vector types for now.
7564  if (VT.getSizeInBits() == 64)
7565    return false;
7566
7567  // FIXME: pshufb, blends, shifts.
7568  return (VT.getVectorNumElements() == 2 ||
7569          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7570          isMOVLMask(M, VT) ||
7571          isSHUFPMask(M, VT) ||
7572          isPSHUFDMask(M, VT) ||
7573          isPSHUFHWMask(M, VT) ||
7574          isPSHUFLWMask(M, VT) ||
7575          isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7576          isUNPCKLMask(M, VT) ||
7577          isUNPCKHMask(M, VT) ||
7578          isUNPCKL_v_undef_Mask(M, VT) ||
7579          isUNPCKH_v_undef_Mask(M, VT));
7580}
7581
7582bool
7583X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7584                                          EVT VT) const {
7585  unsigned NumElts = VT.getVectorNumElements();
7586  // FIXME: This collection of masks seems suspect.
7587  if (NumElts == 2)
7588    return true;
7589  if (NumElts == 4 && VT.getSizeInBits() == 128) {
7590    return (isMOVLMask(Mask, VT)  ||
7591            isCommutedMOVLMask(Mask, VT, true) ||
7592            isSHUFPMask(Mask, VT) ||
7593            isCommutedSHUFPMask(Mask, VT));
7594  }
7595  return false;
7596}
7597
7598//===----------------------------------------------------------------------===//
7599//                           X86 Scheduler Hooks
7600//===----------------------------------------------------------------------===//
7601
7602// private utility function
7603MachineBasicBlock *
7604X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7605                                                       MachineBasicBlock *MBB,
7606                                                       unsigned regOpc,
7607                                                       unsigned immOpc,
7608                                                       unsigned LoadOpc,
7609                                                       unsigned CXchgOpc,
7610                                                       unsigned copyOpc,
7611                                                       unsigned notOpc,
7612                                                       unsigned EAXreg,
7613                                                       TargetRegisterClass *RC,
7614                                                       bool invSrc) const {
7615  // For the atomic bitwise operator, we generate
7616  //   thisMBB:
7617  //   newMBB:
7618  //     ld  t1 = [bitinstr.addr]
7619  //     op  t2 = t1, [bitinstr.val]
7620  //     mov EAX = t1
7621  //     lcs dest = [bitinstr.addr], t2  [EAX is implicit]
7622  //     bz  newMBB
7623  //     fallthrough -->nextMBB
7624  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7625  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7626  MachineFunction::iterator MBBIter = MBB;
7627  ++MBBIter;
7628
7629  /// First build the CFG
7630  MachineFunction *F = MBB->getParent();
7631  MachineBasicBlock *thisMBB = MBB;
7632  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7633  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7634  F->insert(MBBIter, newMBB);
7635  F->insert(MBBIter, nextMBB);
7636
7637  // Move all successors to thisMBB to nextMBB
7638  nextMBB->transferSuccessors(thisMBB);
7639
7640  // Update thisMBB to fall through to newMBB
7641  thisMBB->addSuccessor(newMBB);
7642
7643  // newMBB jumps to itself and fall through to nextMBB
7644  newMBB->addSuccessor(nextMBB);
7645  newMBB->addSuccessor(newMBB);
7646
7647  // Insert instructions into newMBB based on incoming instruction
7648  assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7649         "unexpected number of operands");
7650  DebugLoc dl = bInstr->getDebugLoc();
7651  MachineOperand& destOper = bInstr->getOperand(0);
7652  MachineOperand* argOpers[2 + X86AddrNumOperands];
7653  int numArgs = bInstr->getNumOperands() - 1;
7654  for (int i=0; i < numArgs; ++i)
7655    argOpers[i] = &bInstr->getOperand(i+1);
7656
7657  // x86 address has 4 operands: base, index, scale, and displacement
7658  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7659  int valArgIndx = lastAddrIndx + 1;
7660
7661  unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7662  MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7663  for (int i=0; i <= lastAddrIndx; ++i)
7664    (*MIB).addOperand(*argOpers[i]);
7665
7666  unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7667  if (invSrc) {
7668    MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7669  }
7670  else
7671    tt = t1;
7672
7673  unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7674  assert((argOpers[valArgIndx]->isReg() ||
7675          argOpers[valArgIndx]->isImm()) &&
7676         "invalid operand");
7677  if (argOpers[valArgIndx]->isReg())
7678    MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7679  else
7680    MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7681  MIB.addReg(tt);
7682  (*MIB).addOperand(*argOpers[valArgIndx]);
7683
7684  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7685  MIB.addReg(t1);
7686
7687  MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7688  for (int i=0; i <= lastAddrIndx; ++i)
7689    (*MIB).addOperand(*argOpers[i]);
7690  MIB.addReg(t2);
7691  assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7692  (*MIB).setMemRefs(bInstr->memoperands_begin(),
7693                    bInstr->memoperands_end());
7694
7695  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7696  MIB.addReg(EAXreg);
7697
7698  // insert branch
7699  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7700
7701  F->DeleteMachineInstr(bInstr);   // The pseudo instruction is gone now.
7702  return nextMBB;
7703}
7704
7705// private utility function:  64 bit atomics on 32 bit host.
7706MachineBasicBlock *
7707X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7708                                                       MachineBasicBlock *MBB,
7709                                                       unsigned regOpcL,
7710                                                       unsigned regOpcH,
7711                                                       unsigned immOpcL,
7712                                                       unsigned immOpcH,
7713                                                       bool invSrc) const {
7714  // For the atomic bitwise operator, we generate
7715  //   thisMBB (instructions are in pairs, except cmpxchg8b)
7716  //     ld t1,t2 = [bitinstr.addr]
7717  //   newMBB:
7718  //     out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7719  //     op  t5, t6 <- out1, out2, [bitinstr.val]
7720  //      (for SWAP, substitute:  mov t5, t6 <- [bitinstr.val])
7721  //     mov ECX, EBX <- t5, t6
7722  //     mov EAX, EDX <- t1, t2
7723  //     cmpxchg8b [bitinstr.addr]  [EAX, EDX, EBX, ECX implicit]
7724  //     mov t3, t4 <- EAX, EDX
7725  //     bz  newMBB
7726  //     result in out1, out2
7727  //     fallthrough -->nextMBB
7728
7729  const TargetRegisterClass *RC = X86::GR32RegisterClass;
7730  const unsigned LoadOpc = X86::MOV32rm;
7731  const unsigned copyOpc = X86::MOV32rr;
7732  const unsigned NotOpc = X86::NOT32r;
7733  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7734  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7735  MachineFunction::iterator MBBIter = MBB;
7736  ++MBBIter;
7737
7738  /// First build the CFG
7739  MachineFunction *F = MBB->getParent();
7740  MachineBasicBlock *thisMBB = MBB;
7741  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7742  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7743  F->insert(MBBIter, newMBB);
7744  F->insert(MBBIter, nextMBB);
7745
7746  // Move all successors to thisMBB to nextMBB
7747  nextMBB->transferSuccessors(thisMBB);
7748
7749  // Update thisMBB to fall through to newMBB
7750  thisMBB->addSuccessor(newMBB);
7751
7752  // newMBB jumps to itself and fall through to nextMBB
7753  newMBB->addSuccessor(nextMBB);
7754  newMBB->addSuccessor(newMBB);
7755
7756  DebugLoc dl = bInstr->getDebugLoc();
7757  // Insert instructions into newMBB based on incoming instruction
7758  // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7759  assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7760         "unexpected number of operands");
7761  MachineOperand& dest1Oper = bInstr->getOperand(0);
7762  MachineOperand& dest2Oper = bInstr->getOperand(1);
7763  MachineOperand* argOpers[2 + X86AddrNumOperands];
7764  for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7765    argOpers[i] = &bInstr->getOperand(i+2);
7766
7767  // x86 address has 4 operands: base, index, scale, and displacement
7768  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7769
7770  unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7771  MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7772  for (int i=0; i <= lastAddrIndx; ++i)
7773    (*MIB).addOperand(*argOpers[i]);
7774  unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7775  MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7776  // add 4 to displacement.
7777  for (int i=0; i <= lastAddrIndx-2; ++i)
7778    (*MIB).addOperand(*argOpers[i]);
7779  MachineOperand newOp3 = *(argOpers[3]);
7780  if (newOp3.isImm())
7781    newOp3.setImm(newOp3.getImm()+4);
7782  else
7783    newOp3.setOffset(newOp3.getOffset()+4);
7784  (*MIB).addOperand(newOp3);
7785  (*MIB).addOperand(*argOpers[lastAddrIndx]);
7786
7787  // t3/4 are defined later, at the bottom of the loop
7788  unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7789  unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7790  BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7791    .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7792  BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7793    .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7794
7795  unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7796  unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7797  if (invSrc) {
7798    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7799    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7800  } else {
7801    tt1 = t1;
7802    tt2 = t2;
7803  }
7804
7805  int valArgIndx = lastAddrIndx + 1;
7806  assert((argOpers[valArgIndx]->isReg() ||
7807          argOpers[valArgIndx]->isImm()) &&
7808         "invalid operand");
7809  unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7810  unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7811  if (argOpers[valArgIndx]->isReg())
7812    MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7813  else
7814    MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7815  if (regOpcL != X86::MOV32rr)
7816    MIB.addReg(tt1);
7817  (*MIB).addOperand(*argOpers[valArgIndx]);
7818  assert(argOpers[valArgIndx + 1]->isReg() ==
7819         argOpers[valArgIndx]->isReg());
7820  assert(argOpers[valArgIndx + 1]->isImm() ==
7821         argOpers[valArgIndx]->isImm());
7822  if (argOpers[valArgIndx + 1]->isReg())
7823    MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7824  else
7825    MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7826  if (regOpcH != X86::MOV32rr)
7827    MIB.addReg(tt2);
7828  (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7829
7830  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7831  MIB.addReg(t1);
7832  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7833  MIB.addReg(t2);
7834
7835  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7836  MIB.addReg(t5);
7837  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7838  MIB.addReg(t6);
7839
7840  MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7841  for (int i=0; i <= lastAddrIndx; ++i)
7842    (*MIB).addOperand(*argOpers[i]);
7843
7844  assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7845  (*MIB).setMemRefs(bInstr->memoperands_begin(),
7846                    bInstr->memoperands_end());
7847
7848  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7849  MIB.addReg(X86::EAX);
7850  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7851  MIB.addReg(X86::EDX);
7852
7853  // insert branch
7854  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7855
7856  F->DeleteMachineInstr(bInstr);   // The pseudo instruction is gone now.
7857  return nextMBB;
7858}
7859
7860// private utility function
7861MachineBasicBlock *
7862X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7863                                                      MachineBasicBlock *MBB,
7864                                                      unsigned cmovOpc) const {
7865  // For the atomic min/max operator, we generate
7866  //   thisMBB:
7867  //   newMBB:
7868  //     ld t1 = [min/max.addr]
7869  //     mov t2 = [min/max.val]
7870  //     cmp  t1, t2
7871  //     cmov[cond] t2 = t1
7872  //     mov EAX = t1
7873  //     lcs dest = [bitinstr.addr], t2  [EAX is implicit]
7874  //     bz   newMBB
7875  //     fallthrough -->nextMBB
7876  //
7877  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7878  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7879  MachineFunction::iterator MBBIter = MBB;
7880  ++MBBIter;
7881
7882  /// First build the CFG
7883  MachineFunction *F = MBB->getParent();
7884  MachineBasicBlock *thisMBB = MBB;
7885  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7886  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7887  F->insert(MBBIter, newMBB);
7888  F->insert(MBBIter, nextMBB);
7889
7890  // Move all successors of thisMBB to nextMBB
7891  nextMBB->transferSuccessors(thisMBB);
7892
7893  // Update thisMBB to fall through to newMBB
7894  thisMBB->addSuccessor(newMBB);
7895
7896  // newMBB jumps to newMBB and fall through to nextMBB
7897  newMBB->addSuccessor(nextMBB);
7898  newMBB->addSuccessor(newMBB);
7899
7900  DebugLoc dl = mInstr->getDebugLoc();
7901  // Insert instructions into newMBB based on incoming instruction
7902  assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7903         "unexpected number of operands");
7904  MachineOperand& destOper = mInstr->getOperand(0);
7905  MachineOperand* argOpers[2 + X86AddrNumOperands];
7906  int numArgs = mInstr->getNumOperands() - 1;
7907  for (int i=0; i < numArgs; ++i)
7908    argOpers[i] = &mInstr->getOperand(i+1);
7909
7910  // x86 address has 4 operands: base, index, scale, and displacement
7911  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7912  int valArgIndx = lastAddrIndx + 1;
7913
7914  unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7915  MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7916  for (int i=0; i <= lastAddrIndx; ++i)
7917    (*MIB).addOperand(*argOpers[i]);
7918
7919  // We only support register and immediate values
7920  assert((argOpers[valArgIndx]->isReg() ||
7921          argOpers[valArgIndx]->isImm()) &&
7922         "invalid operand");
7923
7924  unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7925  if (argOpers[valArgIndx]->isReg())
7926    MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7927  else
7928    MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7929  (*MIB).addOperand(*argOpers[valArgIndx]);
7930
7931  MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7932  MIB.addReg(t1);
7933
7934  MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7935  MIB.addReg(t1);
7936  MIB.addReg(t2);
7937
7938  // Generate movc
7939  unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7940  MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7941  MIB.addReg(t2);
7942  MIB.addReg(t1);
7943
7944  // Cmp and exchange if none has modified the memory location
7945  MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7946  for (int i=0; i <= lastAddrIndx; ++i)
7947    (*MIB).addOperand(*argOpers[i]);
7948  MIB.addReg(t3);
7949  assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7950  (*MIB).setMemRefs(mInstr->memoperands_begin(),
7951                    mInstr->memoperands_end());
7952
7953  MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7954  MIB.addReg(X86::EAX);
7955
7956  // insert branch
7957  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7958
7959  F->DeleteMachineInstr(mInstr);   // The pseudo instruction is gone now.
7960  return nextMBB;
7961}
7962
7963// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7964// all of this code can be replaced with that in the .td file.
7965MachineBasicBlock *
7966X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7967                            unsigned numArgs, bool memArg) const {
7968
7969  MachineFunction *F = BB->getParent();
7970  DebugLoc dl = MI->getDebugLoc();
7971  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7972
7973  unsigned Opc;
7974  if (memArg)
7975    Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7976  else
7977    Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7978
7979  MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7980
7981  for (unsigned i = 0; i < numArgs; ++i) {
7982    MachineOperand &Op = MI->getOperand(i+1);
7983
7984    if (!(Op.isReg() && Op.isImplicit()))
7985      MIB.addOperand(Op);
7986  }
7987
7988  BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7989    .addReg(X86::XMM0);
7990
7991  F->DeleteMachineInstr(MI);
7992
7993  return BB;
7994}
7995
7996MachineBasicBlock *
7997X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7998                                                 MachineInstr *MI,
7999                                                 MachineBasicBlock *MBB) const {
8000  // Emit code to save XMM registers to the stack. The ABI says that the
8001  // number of registers to save is given in %al, so it's theoretically
8002  // possible to do an indirect jump trick to avoid saving all of them,
8003  // however this code takes a simpler approach and just executes all
8004  // of the stores if %al is non-zero. It's less code, and it's probably
8005  // easier on the hardware branch predictor, and stores aren't all that
8006  // expensive anyway.
8007
8008  // Create the new basic blocks. One block contains all the XMM stores,
8009  // and one block is the final destination regardless of whether any
8010  // stores were performed.
8011  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8012  MachineFunction *F = MBB->getParent();
8013  MachineFunction::iterator MBBIter = MBB;
8014  ++MBBIter;
8015  MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8016  MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8017  F->insert(MBBIter, XMMSaveMBB);
8018  F->insert(MBBIter, EndMBB);
8019
8020  // Set up the CFG.
8021  // Move any original successors of MBB to the end block.
8022  EndMBB->transferSuccessors(MBB);
8023  // The original block will now fall through to the XMM save block.
8024  MBB->addSuccessor(XMMSaveMBB);
8025  // The XMMSaveMBB will fall through to the end block.
8026  XMMSaveMBB->addSuccessor(EndMBB);
8027
8028  // Now add the instructions.
8029  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8030  DebugLoc DL = MI->getDebugLoc();
8031
8032  unsigned CountReg = MI->getOperand(0).getReg();
8033  int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8034  int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8035
8036  if (!Subtarget->isTargetWin64()) {
8037    // If %al is 0, branch around the XMM save block.
8038    BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8039    BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8040    MBB->addSuccessor(EndMBB);
8041  }
8042
8043  // In the XMM save block, save all the XMM argument registers.
8044  for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8045    int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8046    MachineMemOperand *MMO =
8047      F->getMachineMemOperand(
8048        PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8049        MachineMemOperand::MOStore, Offset,
8050        /*Size=*/16, /*Align=*/16);
8051    BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8052      .addFrameIndex(RegSaveFrameIndex)
8053      .addImm(/*Scale=*/1)
8054      .addReg(/*IndexReg=*/0)
8055      .addImm(/*Disp=*/Offset)
8056      .addReg(/*Segment=*/0)
8057      .addReg(MI->getOperand(i).getReg())
8058      .addMemOperand(MMO);
8059  }
8060
8061  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8062
8063  return EndMBB;
8064}
8065
8066MachineBasicBlock *
8067X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8068                                     MachineBasicBlock *BB,
8069                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8070  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8071  DebugLoc DL = MI->getDebugLoc();
8072
8073  // To "insert" a SELECT_CC instruction, we actually have to insert the
8074  // diamond control-flow pattern.  The incoming instruction knows the
8075  // destination vreg to set, the condition code register to branch on, the
8076  // true/false values to select between, and a branch opcode to use.
8077  const BasicBlock *LLVM_BB = BB->getBasicBlock();
8078  MachineFunction::iterator It = BB;
8079  ++It;
8080
8081  //  thisMBB:
8082  //  ...
8083  //   TrueVal = ...
8084  //   cmpTY ccX, r1, r2
8085  //   bCC copy1MBB
8086  //   fallthrough --> copy0MBB
8087  MachineBasicBlock *thisMBB = BB;
8088  MachineFunction *F = BB->getParent();
8089  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8090  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8091  unsigned Opc =
8092    X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8093  BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8094  F->insert(It, copy0MBB);
8095  F->insert(It, sinkMBB);
8096  // Update machine-CFG edges by first adding all successors of the current
8097  // block to the new block which will contain the Phi node for the select.
8098  // Also inform sdisel of the edge changes.
8099  for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8100         E = BB->succ_end(); I != E; ++I) {
8101    EM->insert(std::make_pair(*I, sinkMBB));
8102    sinkMBB->addSuccessor(*I);
8103  }
8104  // Next, remove all successors of the current block, and add the true
8105  // and fallthrough blocks as its successors.
8106  while (!BB->succ_empty())
8107    BB->removeSuccessor(BB->succ_begin());
8108  // Add the true and fallthrough blocks as its successors.
8109  BB->addSuccessor(copy0MBB);
8110  BB->addSuccessor(sinkMBB);
8111
8112  //  copy0MBB:
8113  //   %FalseValue = ...
8114  //   # fallthrough to sinkMBB
8115  BB = copy0MBB;
8116
8117  // Update machine-CFG edges
8118  BB->addSuccessor(sinkMBB);
8119
8120  //  sinkMBB:
8121  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8122  //  ...
8123  BB = sinkMBB;
8124  BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8125    .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8126    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8127
8128  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8129  return BB;
8130}
8131
8132
8133MachineBasicBlock *
8134X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8135                                               MachineBasicBlock *BB,
8136                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8137  switch (MI->getOpcode()) {
8138  default: assert(false && "Unexpected instr type to insert");
8139  case X86::CMOV_GR8:
8140  case X86::CMOV_V1I64:
8141  case X86::CMOV_FR32:
8142  case X86::CMOV_FR64:
8143  case X86::CMOV_V4F32:
8144  case X86::CMOV_V2F64:
8145  case X86::CMOV_V2I64:
8146    return EmitLoweredSelect(MI, BB, EM);
8147
8148  case X86::FP32_TO_INT16_IN_MEM:
8149  case X86::FP32_TO_INT32_IN_MEM:
8150  case X86::FP32_TO_INT64_IN_MEM:
8151  case X86::FP64_TO_INT16_IN_MEM:
8152  case X86::FP64_TO_INT32_IN_MEM:
8153  case X86::FP64_TO_INT64_IN_MEM:
8154  case X86::FP80_TO_INT16_IN_MEM:
8155  case X86::FP80_TO_INT32_IN_MEM:
8156  case X86::FP80_TO_INT64_IN_MEM: {
8157    const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8158    DebugLoc DL = MI->getDebugLoc();
8159
8160    // Change the floating point control register to use "round towards zero"
8161    // mode when truncating to an integer value.
8162    MachineFunction *F = BB->getParent();
8163    int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8164    addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8165
8166    // Load the old value of the high byte of the control word...
8167    unsigned OldCW =
8168      F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8169    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8170                      CWFrameIdx);
8171
8172    // Set the high part to be round to zero...
8173    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8174      .addImm(0xC7F);
8175
8176    // Reload the modified control word now...
8177    addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8178
8179    // Restore the memory image of control word to original value
8180    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8181      .addReg(OldCW);
8182
8183    // Get the X86 opcode to use.
8184    unsigned Opc;
8185    switch (MI->getOpcode()) {
8186    default: llvm_unreachable("illegal opcode!");
8187    case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8188    case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8189    case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8190    case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8191    case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8192    case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8193    case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8194    case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8195    case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8196    }
8197
8198    X86AddressMode AM;
8199    MachineOperand &Op = MI->getOperand(0);
8200    if (Op.isReg()) {
8201      AM.BaseType = X86AddressMode::RegBase;
8202      AM.Base.Reg = Op.getReg();
8203    } else {
8204      AM.BaseType = X86AddressMode::FrameIndexBase;
8205      AM.Base.FrameIndex = Op.getIndex();
8206    }
8207    Op = MI->getOperand(1);
8208    if (Op.isImm())
8209      AM.Scale = Op.getImm();
8210    Op = MI->getOperand(2);
8211    if (Op.isImm())
8212      AM.IndexReg = Op.getImm();
8213    Op = MI->getOperand(3);
8214    if (Op.isGlobal()) {
8215      AM.GV = Op.getGlobal();
8216    } else {
8217      AM.Disp = Op.getImm();
8218    }
8219    addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8220                      .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8221
8222    // Reload the original control word now.
8223    addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8224
8225    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8226    return BB;
8227  }
8228    // String/text processing lowering.
8229  case X86::PCMPISTRM128REG:
8230    return EmitPCMP(MI, BB, 3, false /* in-mem */);
8231  case X86::PCMPISTRM128MEM:
8232    return EmitPCMP(MI, BB, 3, true /* in-mem */);
8233  case X86::PCMPESTRM128REG:
8234    return EmitPCMP(MI, BB, 5, false /* in mem */);
8235  case X86::PCMPESTRM128MEM:
8236    return EmitPCMP(MI, BB, 5, true /* in mem */);
8237
8238    // Atomic Lowering.
8239  case X86::ATOMAND32:
8240    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8241                                               X86::AND32ri, X86::MOV32rm,
8242                                               X86::LCMPXCHG32, X86::MOV32rr,
8243                                               X86::NOT32r, X86::EAX,
8244                                               X86::GR32RegisterClass);
8245  case X86::ATOMOR32:
8246    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8247                                               X86::OR32ri, X86::MOV32rm,
8248                                               X86::LCMPXCHG32, X86::MOV32rr,
8249                                               X86::NOT32r, X86::EAX,
8250                                               X86::GR32RegisterClass);
8251  case X86::ATOMXOR32:
8252    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8253                                               X86::XOR32ri, X86::MOV32rm,
8254                                               X86::LCMPXCHG32, X86::MOV32rr,
8255                                               X86::NOT32r, X86::EAX,
8256                                               X86::GR32RegisterClass);
8257  case X86::ATOMNAND32:
8258    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8259                                               X86::AND32ri, X86::MOV32rm,
8260                                               X86::LCMPXCHG32, X86::MOV32rr,
8261                                               X86::NOT32r, X86::EAX,
8262                                               X86::GR32RegisterClass, true);
8263  case X86::ATOMMIN32:
8264    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8265  case X86::ATOMMAX32:
8266    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8267  case X86::ATOMUMIN32:
8268    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8269  case X86::ATOMUMAX32:
8270    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8271
8272  case X86::ATOMAND16:
8273    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8274                                               X86::AND16ri, X86::MOV16rm,
8275                                               X86::LCMPXCHG16, X86::MOV16rr,
8276                                               X86::NOT16r, X86::AX,
8277                                               X86::GR16RegisterClass);
8278  case X86::ATOMOR16:
8279    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8280                                               X86::OR16ri, X86::MOV16rm,
8281                                               X86::LCMPXCHG16, X86::MOV16rr,
8282                                               X86::NOT16r, X86::AX,
8283                                               X86::GR16RegisterClass);
8284  case X86::ATOMXOR16:
8285    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8286                                               X86::XOR16ri, X86::MOV16rm,
8287                                               X86::LCMPXCHG16, X86::MOV16rr,
8288                                               X86::NOT16r, X86::AX,
8289                                               X86::GR16RegisterClass);
8290  case X86::ATOMNAND16:
8291    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8292                                               X86::AND16ri, X86::MOV16rm,
8293                                               X86::LCMPXCHG16, X86::MOV16rr,
8294                                               X86::NOT16r, X86::AX,
8295                                               X86::GR16RegisterClass, true);
8296  case X86::ATOMMIN16:
8297    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8298  case X86::ATOMMAX16:
8299    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8300  case X86::ATOMUMIN16:
8301    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8302  case X86::ATOMUMAX16:
8303    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8304
8305  case X86::ATOMAND8:
8306    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8307                                               X86::AND8ri, X86::MOV8rm,
8308                                               X86::LCMPXCHG8, X86::MOV8rr,
8309                                               X86::NOT8r, X86::AL,
8310                                               X86::GR8RegisterClass);
8311  case X86::ATOMOR8:
8312    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8313                                               X86::OR8ri, X86::MOV8rm,
8314                                               X86::LCMPXCHG8, X86::MOV8rr,
8315                                               X86::NOT8r, X86::AL,
8316                                               X86::GR8RegisterClass);
8317  case X86::ATOMXOR8:
8318    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8319                                               X86::XOR8ri, X86::MOV8rm,
8320                                               X86::LCMPXCHG8, X86::MOV8rr,
8321                                               X86::NOT8r, X86::AL,
8322                                               X86::GR8RegisterClass);
8323  case X86::ATOMNAND8:
8324    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8325                                               X86::AND8ri, X86::MOV8rm,
8326                                               X86::LCMPXCHG8, X86::MOV8rr,
8327                                               X86::NOT8r, X86::AL,
8328                                               X86::GR8RegisterClass, true);
8329  // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8330  // This group is for 64-bit host.
8331  case X86::ATOMAND64:
8332    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8333                                               X86::AND64ri32, X86::MOV64rm,
8334                                               X86::LCMPXCHG64, X86::MOV64rr,
8335                                               X86::NOT64r, X86::RAX,
8336                                               X86::GR64RegisterClass);
8337  case X86::ATOMOR64:
8338    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8339                                               X86::OR64ri32, X86::MOV64rm,
8340                                               X86::LCMPXCHG64, X86::MOV64rr,
8341                                               X86::NOT64r, X86::RAX,
8342                                               X86::GR64RegisterClass);
8343  case X86::ATOMXOR64:
8344    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8345                                               X86::XOR64ri32, X86::MOV64rm,
8346                                               X86::LCMPXCHG64, X86::MOV64rr,
8347                                               X86::NOT64r, X86::RAX,
8348                                               X86::GR64RegisterClass);
8349  case X86::ATOMNAND64:
8350    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8351                                               X86::AND64ri32, X86::MOV64rm,
8352                                               X86::LCMPXCHG64, X86::MOV64rr,
8353                                               X86::NOT64r, X86::RAX,
8354                                               X86::GR64RegisterClass, true);
8355  case X86::ATOMMIN64:
8356    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8357  case X86::ATOMMAX64:
8358    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8359  case X86::ATOMUMIN64:
8360    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8361  case X86::ATOMUMAX64:
8362    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8363
8364  // This group does 64-bit operations on a 32-bit host.
8365  case X86::ATOMAND6432:
8366    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8367                                               X86::AND32rr, X86::AND32rr,
8368                                               X86::AND32ri, X86::AND32ri,
8369                                               false);
8370  case X86::ATOMOR6432:
8371    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8372                                               X86::OR32rr, X86::OR32rr,
8373                                               X86::OR32ri, X86::OR32ri,
8374                                               false);
8375  case X86::ATOMXOR6432:
8376    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8377                                               X86::XOR32rr, X86::XOR32rr,
8378                                               X86::XOR32ri, X86::XOR32ri,
8379                                               false);
8380  case X86::ATOMNAND6432:
8381    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8382                                               X86::AND32rr, X86::AND32rr,
8383                                               X86::AND32ri, X86::AND32ri,
8384                                               true);
8385  case X86::ATOMADD6432:
8386    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8387                                               X86::ADD32rr, X86::ADC32rr,
8388                                               X86::ADD32ri, X86::ADC32ri,
8389                                               false);
8390  case X86::ATOMSUB6432:
8391    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8392                                               X86::SUB32rr, X86::SBB32rr,
8393                                               X86::SUB32ri, X86::SBB32ri,
8394                                               false);
8395  case X86::ATOMSWAP6432:
8396    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8397                                               X86::MOV32rr, X86::MOV32rr,
8398                                               X86::MOV32ri, X86::MOV32ri,
8399                                               false);
8400  case X86::VASTART_SAVE_XMM_REGS:
8401    return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8402  }
8403}
8404
8405//===----------------------------------------------------------------------===//
8406//                           X86 Optimization Hooks
8407//===----------------------------------------------------------------------===//
8408
8409void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8410                                                       const APInt &Mask,
8411                                                       APInt &KnownZero,
8412                                                       APInt &KnownOne,
8413                                                       const SelectionDAG &DAG,
8414                                                       unsigned Depth) const {
8415  unsigned Opc = Op.getOpcode();
8416  assert((Opc >= ISD::BUILTIN_OP_END ||
8417          Opc == ISD::INTRINSIC_WO_CHAIN ||
8418          Opc == ISD::INTRINSIC_W_CHAIN ||
8419          Opc == ISD::INTRINSIC_VOID) &&
8420         "Should use MaskedValueIsZero if you don't know whether Op"
8421         " is a target node!");
8422
8423  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
8424  switch (Opc) {
8425  default: break;
8426  case X86ISD::ADD:
8427  case X86ISD::SUB:
8428  case X86ISD::SMUL:
8429  case X86ISD::UMUL:
8430  case X86ISD::INC:
8431  case X86ISD::DEC:
8432  case X86ISD::OR:
8433  case X86ISD::XOR:
8434  case X86ISD::AND:
8435    // These nodes' second result is a boolean.
8436    if (Op.getResNo() == 0)
8437      break;
8438    // Fallthrough
8439  case X86ISD::SETCC:
8440    KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8441                                       Mask.getBitWidth() - 1);
8442    break;
8443  }
8444}
8445
8446/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8447/// node is a GlobalAddress + offset.
8448bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8449                                       GlobalValue* &GA, int64_t &Offset) const{
8450  if (N->getOpcode() == X86ISD::Wrapper) {
8451    if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8452      GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8453      Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8454      return true;
8455    }
8456  }
8457  return TargetLowering::isGAPlusOffset(N, GA, Offset);
8458}
8459
8460static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8461                                     EVT EltVT, LoadSDNode *&LDBase,
8462                                     unsigned &LastLoadedElt,
8463                                     SelectionDAG &DAG, MachineFrameInfo *MFI,
8464                                     const TargetLowering &TLI) {
8465  LDBase = NULL;
8466  LastLoadedElt = -1U;
8467  for (unsigned i = 0; i < NumElems; ++i) {
8468    if (N->getMaskElt(i) < 0) {
8469      if (!LDBase)
8470        return false;
8471      continue;
8472    }
8473
8474    SDValue Elt = DAG.getShuffleScalarElt(N, i);
8475    if (!Elt.getNode() ||
8476        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8477      return false;
8478    if (!LDBase) {
8479      if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8480        return false;
8481      LDBase = cast<LoadSDNode>(Elt.getNode());
8482      LastLoadedElt = i;
8483      continue;
8484    }
8485    if (Elt.getOpcode() == ISD::UNDEF)
8486      continue;
8487
8488    LoadSDNode *LD = cast<LoadSDNode>(Elt);
8489    if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8490      return false;
8491    LastLoadedElt = i;
8492  }
8493  return true;
8494}
8495
8496/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8497/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8498/// if the load addresses are consecutive, non-overlapping, and in the right
8499/// order.  In the case of v2i64, it will see if it can rewrite the
8500/// shuffle to be an appropriate build vector so it can take advantage of
8501// performBuildVectorCombine.
8502static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8503                                     const TargetLowering &TLI) {
8504  DebugLoc dl = N->getDebugLoc();
8505  EVT VT = N->getValueType(0);
8506  EVT EltVT = VT.getVectorElementType();
8507  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8508  unsigned NumElems = VT.getVectorNumElements();
8509
8510  if (VT.getSizeInBits() != 128)
8511    return SDValue();
8512
8513  // Try to combine a vector_shuffle into a 128-bit load.
8514  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8515  LoadSDNode *LD = NULL;
8516  unsigned LastLoadedElt;
8517  if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8518                                MFI, TLI))
8519    return SDValue();
8520
8521  if (LastLoadedElt == NumElems - 1) {
8522    if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8523      return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8524                         LD->getSrcValue(), LD->getSrcValueOffset(),
8525                         LD->isVolatile());
8526    return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8527                       LD->getSrcValue(), LD->getSrcValueOffset(),
8528                       LD->isVolatile(), LD->getAlignment());
8529  } else if (NumElems == 4 && LastLoadedElt == 1) {
8530    SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8531    SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8532    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8533    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8534  }
8535  return SDValue();
8536}
8537
8538/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8539static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8540                                    const X86Subtarget *Subtarget) {
8541  DebugLoc DL = N->getDebugLoc();
8542  SDValue Cond = N->getOperand(0);
8543  // Get the LHS/RHS of the select.
8544  SDValue LHS = N->getOperand(1);
8545  SDValue RHS = N->getOperand(2);
8546
8547  // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8548  // instructions have the peculiarity that if either operand is a NaN,
8549  // they chose what we call the RHS operand (and as such are not symmetric).
8550  // It happens that this matches the semantics of the common C idiom
8551  // x<y?x:y and related forms, so we can recognize these cases.
8552  if (Subtarget->hasSSE2() &&
8553      (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8554      Cond.getOpcode() == ISD::SETCC) {
8555    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8556
8557    unsigned Opcode = 0;
8558    // Check for x CC y ? x : y.
8559    if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8560      switch (CC) {
8561      default: break;
8562      case ISD::SETULT:
8563        // This can be a min if we can prove that at least one of the operands
8564        // is not a nan.
8565        if (!FiniteOnlyFPMath()) {
8566          if (DAG.isKnownNeverNaN(RHS)) {
8567            // Put the potential NaN in the RHS so that SSE will preserve it.
8568            std::swap(LHS, RHS);
8569          } else if (!DAG.isKnownNeverNaN(LHS))
8570            break;
8571        }
8572        Opcode = X86ISD::FMIN;
8573        break;
8574      case ISD::SETOLE:
8575        // This can be a min if we can prove that at least one of the operands
8576        // is not a nan.
8577        if (!FiniteOnlyFPMath()) {
8578          if (DAG.isKnownNeverNaN(LHS)) {
8579            // Put the potential NaN in the RHS so that SSE will preserve it.
8580            std::swap(LHS, RHS);
8581          } else if (!DAG.isKnownNeverNaN(RHS))
8582            break;
8583        }
8584        Opcode = X86ISD::FMIN;
8585        break;
8586      case ISD::SETULE:
8587        // This can be a min, but if either operand is a NaN we need it to
8588        // preserve the original LHS.
8589        std::swap(LHS, RHS);
8590      case ISD::SETOLT:
8591      case ISD::SETLT:
8592      case ISD::SETLE:
8593        Opcode = X86ISD::FMIN;
8594        break;
8595
8596      case ISD::SETOGE:
8597        // This can be a max if we can prove that at least one of the operands
8598        // is not a nan.
8599        if (!FiniteOnlyFPMath()) {
8600          if (DAG.isKnownNeverNaN(LHS)) {
8601            // Put the potential NaN in the RHS so that SSE will preserve it.
8602            std::swap(LHS, RHS);
8603          } else if (!DAG.isKnownNeverNaN(RHS))
8604            break;
8605        }
8606        Opcode = X86ISD::FMAX;
8607        break;
8608      case ISD::SETUGT:
8609        // This can be a max if we can prove that at least one of the operands
8610        // is not a nan.
8611        if (!FiniteOnlyFPMath()) {
8612          if (DAG.isKnownNeverNaN(RHS)) {
8613            // Put the potential NaN in the RHS so that SSE will preserve it.
8614            std::swap(LHS, RHS);
8615          } else if (!DAG.isKnownNeverNaN(LHS))
8616            break;
8617        }
8618        Opcode = X86ISD::FMAX;
8619        break;
8620      case ISD::SETUGE:
8621        // This can be a max, but if either operand is a NaN we need it to
8622        // preserve the original LHS.
8623        std::swap(LHS, RHS);
8624      case ISD::SETOGT:
8625      case ISD::SETGT:
8626      case ISD::SETGE:
8627        Opcode = X86ISD::FMAX;
8628        break;
8629      }
8630    // Check for x CC y ? y : x -- a min/max with reversed arms.
8631    } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8632      switch (CC) {
8633      default: break;
8634      case ISD::SETOGE:
8635        // This can be a min if we can prove that at least one of the operands
8636        // is not a nan.
8637        if (!FiniteOnlyFPMath()) {
8638          if (DAG.isKnownNeverNaN(RHS)) {
8639            // Put the potential NaN in the RHS so that SSE will preserve it.
8640            std::swap(LHS, RHS);
8641          } else if (!DAG.isKnownNeverNaN(LHS))
8642            break;
8643        }
8644        Opcode = X86ISD::FMIN;
8645        break;
8646      case ISD::SETUGT:
8647        // This can be a min if we can prove that at least one of the operands
8648        // is not a nan.
8649        if (!FiniteOnlyFPMath()) {
8650          if (DAG.isKnownNeverNaN(LHS)) {
8651            // Put the potential NaN in the RHS so that SSE will preserve it.
8652            std::swap(LHS, RHS);
8653          } else if (!DAG.isKnownNeverNaN(RHS))
8654            break;
8655        }
8656        Opcode = X86ISD::FMIN;
8657        break;
8658      case ISD::SETUGE:
8659        // This can be a min, but if either operand is a NaN we need it to
8660        // preserve the original LHS.
8661        std::swap(LHS, RHS);
8662      case ISD::SETOGT:
8663      case ISD::SETGT:
8664      case ISD::SETGE:
8665        Opcode = X86ISD::FMIN;
8666        break;
8667
8668      case ISD::SETULT:
8669        // This can be a max if we can prove that at least one of the operands
8670        // is not a nan.
8671        if (!FiniteOnlyFPMath()) {
8672          if (DAG.isKnownNeverNaN(LHS)) {
8673            // Put the potential NaN in the RHS so that SSE will preserve it.
8674            std::swap(LHS, RHS);
8675          } else if (!DAG.isKnownNeverNaN(RHS))
8676            break;
8677        }
8678        Opcode = X86ISD::FMAX;
8679        break;
8680      case ISD::SETOLE:
8681        // This can be a max if we can prove that at least one of the operands
8682        // is not a nan.
8683        if (!FiniteOnlyFPMath()) {
8684          if (DAG.isKnownNeverNaN(RHS)) {
8685            // Put the potential NaN in the RHS so that SSE will preserve it.
8686            std::swap(LHS, RHS);
8687          } else if (!DAG.isKnownNeverNaN(LHS))
8688            break;
8689        }
8690        Opcode = X86ISD::FMAX;
8691        break;
8692      case ISD::SETULE:
8693        // This can be a max, but if either operand is a NaN we need it to
8694        // preserve the original LHS.
8695        std::swap(LHS, RHS);
8696      case ISD::SETOLT:
8697      case ISD::SETLT:
8698      case ISD::SETLE:
8699        Opcode = X86ISD::FMAX;
8700        break;
8701      }
8702    }
8703
8704    if (Opcode)
8705      return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8706  }
8707
8708  // If this is a select between two integer constants, try to do some
8709  // optimizations.
8710  if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8711    if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8712      // Don't do this for crazy integer types.
8713      if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8714        // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8715        // so that TrueC (the true value) is larger than FalseC.
8716        bool NeedsCondInvert = false;
8717
8718        if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8719            // Efficiently invertible.
8720            (Cond.getOpcode() == ISD::SETCC ||  // setcc -> invertible.
8721             (Cond.getOpcode() == ISD::XOR &&   // xor(X, C) -> invertible.
8722              isa<ConstantSDNode>(Cond.getOperand(1))))) {
8723          NeedsCondInvert = true;
8724          std::swap(TrueC, FalseC);
8725        }
8726
8727        // Optimize C ? 8 : 0 -> zext(C) << 3.  Likewise for any pow2/0.
8728        if (FalseC->getAPIntValue() == 0 &&
8729            TrueC->getAPIntValue().isPowerOf2()) {
8730          if (NeedsCondInvert) // Invert the condition if needed.
8731            Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8732                               DAG.getConstant(1, Cond.getValueType()));
8733
8734          // Zero extend the condition if needed.
8735          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8736
8737          unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8738          return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8739                             DAG.getConstant(ShAmt, MVT::i8));
8740        }
8741
8742        // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8743        if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8744          if (NeedsCondInvert) // Invert the condition if needed.
8745            Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8746                               DAG.getConstant(1, Cond.getValueType()));
8747
8748          // Zero extend the condition if needed.
8749          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8750                             FalseC->getValueType(0), Cond);
8751          return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8752                             SDValue(FalseC, 0));
8753        }
8754
8755        // Optimize cases that will turn into an LEA instruction.  This requires
8756        // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8757        if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8758          uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8759          if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8760
8761          bool isFastMultiplier = false;
8762          if (Diff < 10) {
8763            switch ((unsigned char)Diff) {
8764              default: break;
8765              case 1:  // result = add base, cond
8766              case 2:  // result = lea base(    , cond*2)
8767              case 3:  // result = lea base(cond, cond*2)
8768              case 4:  // result = lea base(    , cond*4)
8769              case 5:  // result = lea base(cond, cond*4)
8770              case 8:  // result = lea base(    , cond*8)
8771              case 9:  // result = lea base(cond, cond*8)
8772                isFastMultiplier = true;
8773                break;
8774            }
8775          }
8776
8777          if (isFastMultiplier) {
8778            APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8779            if (NeedsCondInvert) // Invert the condition if needed.
8780              Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8781                                 DAG.getConstant(1, Cond.getValueType()));
8782
8783            // Zero extend the condition if needed.
8784            Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8785                               Cond);
8786            // Scale the condition by the difference.
8787            if (Diff != 1)
8788              Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8789                                 DAG.getConstant(Diff, Cond.getValueType()));
8790
8791            // Add the base if non-zero.
8792            if (FalseC->getAPIntValue() != 0)
8793              Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8794                                 SDValue(FalseC, 0));
8795            return Cond;
8796          }
8797        }
8798      }
8799  }
8800
8801  return SDValue();
8802}
8803
8804/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8805static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8806                                  TargetLowering::DAGCombinerInfo &DCI) {
8807  DebugLoc DL = N->getDebugLoc();
8808
8809  // If the flag operand isn't dead, don't touch this CMOV.
8810  if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8811    return SDValue();
8812
8813  // If this is a select between two integer constants, try to do some
8814  // optimizations.  Note that the operands are ordered the opposite of SELECT
8815  // operands.
8816  if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8817    if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8818      // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8819      // larger than FalseC (the false value).
8820      X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8821
8822      if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8823        CC = X86::GetOppositeBranchCondition(CC);
8824        std::swap(TrueC, FalseC);
8825      }
8826
8827      // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3.  Likewise for any pow2/0.
8828      // This is efficient for any integer data type (including i8/i16) and
8829      // shift amount.
8830      if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8831        SDValue Cond = N->getOperand(3);
8832        Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8833                           DAG.getConstant(CC, MVT::i8), Cond);
8834
8835        // Zero extend the condition if needed.
8836        Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8837
8838        unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8839        Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8840                           DAG.getConstant(ShAmt, MVT::i8));
8841        if (N->getNumValues() == 2)  // Dead flag value?
8842          return DCI.CombineTo(N, Cond, SDValue());
8843        return Cond;
8844      }
8845
8846      // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.  This is efficient
8847      // for any integer data type, including i8/i16.
8848      if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8849        SDValue Cond = N->getOperand(3);
8850        Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8851                           DAG.getConstant(CC, MVT::i8), Cond);
8852
8853        // Zero extend the condition if needed.
8854        Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8855                           FalseC->getValueType(0), Cond);
8856        Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8857                           SDValue(FalseC, 0));
8858
8859        if (N->getNumValues() == 2)  // Dead flag value?
8860          return DCI.CombineTo(N, Cond, SDValue());
8861        return Cond;
8862      }
8863
8864      // Optimize cases that will turn into an LEA instruction.  This requires
8865      // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8866      if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8867        uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8868        if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8869
8870        bool isFastMultiplier = false;
8871        if (Diff < 10) {
8872          switch ((unsigned char)Diff) {
8873          default: break;
8874          case 1:  // result = add base, cond
8875          case 2:  // result = lea base(    , cond*2)
8876          case 3:  // result = lea base(cond, cond*2)
8877          case 4:  // result = lea base(    , cond*4)
8878          case 5:  // result = lea base(cond, cond*4)
8879          case 8:  // result = lea base(    , cond*8)
8880          case 9:  // result = lea base(cond, cond*8)
8881            isFastMultiplier = true;
8882            break;
8883          }
8884        }
8885
8886        if (isFastMultiplier) {
8887          APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8888          SDValue Cond = N->getOperand(3);
8889          Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8890                             DAG.getConstant(CC, MVT::i8), Cond);
8891          // Zero extend the condition if needed.
8892          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8893                             Cond);
8894          // Scale the condition by the difference.
8895          if (Diff != 1)
8896            Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8897                               DAG.getConstant(Diff, Cond.getValueType()));
8898
8899          // Add the base if non-zero.
8900          if (FalseC->getAPIntValue() != 0)
8901            Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8902                               SDValue(FalseC, 0));
8903          if (N->getNumValues() == 2)  // Dead flag value?
8904            return DCI.CombineTo(N, Cond, SDValue());
8905          return Cond;
8906        }
8907      }
8908    }
8909  }
8910  return SDValue();
8911}
8912
8913
8914/// PerformMulCombine - Optimize a single multiply with constant into two
8915/// in order to implement it with two cheaper instructions, e.g.
8916/// LEA + SHL, LEA + LEA.
8917static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8918                                 TargetLowering::DAGCombinerInfo &DCI) {
8919  if (DAG.getMachineFunction().
8920      getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8921    return SDValue();
8922
8923  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8924    return SDValue();
8925
8926  EVT VT = N->getValueType(0);
8927  if (VT != MVT::i64)
8928    return SDValue();
8929
8930  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8931  if (!C)
8932    return SDValue();
8933  uint64_t MulAmt = C->getZExtValue();
8934  if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8935    return SDValue();
8936
8937  uint64_t MulAmt1 = 0;
8938  uint64_t MulAmt2 = 0;
8939  if ((MulAmt % 9) == 0) {
8940    MulAmt1 = 9;
8941    MulAmt2 = MulAmt / 9;
8942  } else if ((MulAmt % 5) == 0) {
8943    MulAmt1 = 5;
8944    MulAmt2 = MulAmt / 5;
8945  } else if ((MulAmt % 3) == 0) {
8946    MulAmt1 = 3;
8947    MulAmt2 = MulAmt / 3;
8948  }
8949  if (MulAmt2 &&
8950      (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8951    DebugLoc DL = N->getDebugLoc();
8952
8953    if (isPowerOf2_64(MulAmt2) &&
8954        !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8955      // If second multiplifer is pow2, issue it first. We want the multiply by
8956      // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8957      // is an add.
8958      std::swap(MulAmt1, MulAmt2);
8959
8960    SDValue NewMul;
8961    if (isPowerOf2_64(MulAmt1))
8962      NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8963                           DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8964    else
8965      NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8966                           DAG.getConstant(MulAmt1, VT));
8967
8968    if (isPowerOf2_64(MulAmt2))
8969      NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8970                           DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8971    else
8972      NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8973                           DAG.getConstant(MulAmt2, VT));
8974
8975    // Do not add new nodes to DAG combiner worklist.
8976    DCI.CombineTo(N, NewMul, false);
8977  }
8978  return SDValue();
8979}
8980
8981static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
8982  SDValue N0 = N->getOperand(0);
8983  SDValue N1 = N->getOperand(1);
8984  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8985  EVT VT = N0.getValueType();
8986
8987  // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
8988  // since the result of setcc_c is all zero's or all ones.
8989  if (N1C && N0.getOpcode() == ISD::AND &&
8990      N0.getOperand(1).getOpcode() == ISD::Constant) {
8991    SDValue N00 = N0.getOperand(0);
8992    if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
8993        ((N00.getOpcode() == ISD::ANY_EXTEND ||
8994          N00.getOpcode() == ISD::ZERO_EXTEND) &&
8995         N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
8996      APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
8997      APInt ShAmt = N1C->getAPIntValue();
8998      Mask = Mask.shl(ShAmt);
8999      if (Mask != 0)
9000        return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9001                           N00, DAG.getConstant(Mask, VT));
9002    }
9003  }
9004
9005  return SDValue();
9006}
9007
9008/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9009///                       when possible.
9010static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9011                                   const X86Subtarget *Subtarget) {
9012  EVT VT = N->getValueType(0);
9013  if (!VT.isVector() && VT.isInteger() &&
9014      N->getOpcode() == ISD::SHL)
9015    return PerformSHLCombine(N, DAG);
9016
9017  // On X86 with SSE2 support, we can transform this to a vector shift if
9018  // all elements are shifted by the same amount.  We can't do this in legalize
9019  // because the a constant vector is typically transformed to a constant pool
9020  // so we have no knowledge of the shift amount.
9021  if (!Subtarget->hasSSE2())
9022    return SDValue();
9023
9024  if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9025    return SDValue();
9026
9027  SDValue ShAmtOp = N->getOperand(1);
9028  EVT EltVT = VT.getVectorElementType();
9029  DebugLoc DL = N->getDebugLoc();
9030  SDValue BaseShAmt = SDValue();
9031  if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9032    unsigned NumElts = VT.getVectorNumElements();
9033    unsigned i = 0;
9034    for (; i != NumElts; ++i) {
9035      SDValue Arg = ShAmtOp.getOperand(i);
9036      if (Arg.getOpcode() == ISD::UNDEF) continue;
9037      BaseShAmt = Arg;
9038      break;
9039    }
9040    for (; i != NumElts; ++i) {
9041      SDValue Arg = ShAmtOp.getOperand(i);
9042      if (Arg.getOpcode() == ISD::UNDEF) continue;
9043      if (Arg != BaseShAmt) {
9044        return SDValue();
9045      }
9046    }
9047  } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9048             cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9049    SDValue InVec = ShAmtOp.getOperand(0);
9050    if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9051      unsigned NumElts = InVec.getValueType().getVectorNumElements();
9052      unsigned i = 0;
9053      for (; i != NumElts; ++i) {
9054        SDValue Arg = InVec.getOperand(i);
9055        if (Arg.getOpcode() == ISD::UNDEF) continue;
9056        BaseShAmt = Arg;
9057        break;
9058      }
9059    } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9060       if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9061         unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9062         if (C->getZExtValue() == SplatIdx)
9063           BaseShAmt = InVec.getOperand(1);
9064       }
9065    }
9066    if (BaseShAmt.getNode() == 0)
9067      BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9068                              DAG.getIntPtrConstant(0));
9069  } else
9070    return SDValue();
9071
9072  // The shift amount is an i32.
9073  if (EltVT.bitsGT(MVT::i32))
9074    BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9075  else if (EltVT.bitsLT(MVT::i32))
9076    BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9077
9078  // The shift amount is identical so we can do a vector shift.
9079  SDValue  ValOp = N->getOperand(0);
9080  switch (N->getOpcode()) {
9081  default:
9082    llvm_unreachable("Unknown shift opcode!");
9083    break;
9084  case ISD::SHL:
9085    if (VT == MVT::v2i64)
9086      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9087                         DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9088                         ValOp, BaseShAmt);
9089    if (VT == MVT::v4i32)
9090      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9091                         DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9092                         ValOp, BaseShAmt);
9093    if (VT == MVT::v8i16)
9094      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9095                         DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9096                         ValOp, BaseShAmt);
9097    break;
9098  case ISD::SRA:
9099    if (VT == MVT::v4i32)
9100      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9101                         DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9102                         ValOp, BaseShAmt);
9103    if (VT == MVT::v8i16)
9104      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9105                         DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9106                         ValOp, BaseShAmt);
9107    break;
9108  case ISD::SRL:
9109    if (VT == MVT::v2i64)
9110      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9111                         DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9112                         ValOp, BaseShAmt);
9113    if (VT == MVT::v4i32)
9114      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9115                         DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9116                         ValOp, BaseShAmt);
9117    if (VT ==  MVT::v8i16)
9118      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9119                         DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9120                         ValOp, BaseShAmt);
9121    break;
9122  }
9123  return SDValue();
9124}
9125
9126/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9127static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9128                                   const X86Subtarget *Subtarget) {
9129  // Turn load->store of MMX types into GPR load/stores.  This avoids clobbering
9130  // the FP state in cases where an emms may be missing.
9131  // A preferable solution to the general problem is to figure out the right
9132  // places to insert EMMS.  This qualifies as a quick hack.
9133
9134  // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9135  StoreSDNode *St = cast<StoreSDNode>(N);
9136  EVT VT = St->getValue().getValueType();
9137  if (VT.getSizeInBits() != 64)
9138    return SDValue();
9139
9140  const Function *F = DAG.getMachineFunction().getFunction();
9141  bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9142  bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9143    && Subtarget->hasSSE2();
9144  if ((VT.isVector() ||
9145       (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9146      isa<LoadSDNode>(St->getValue()) &&
9147      !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9148      St->getChain().hasOneUse() && !St->isVolatile()) {
9149    SDNode* LdVal = St->getValue().getNode();
9150    LoadSDNode *Ld = 0;
9151    int TokenFactorIndex = -1;
9152    SmallVector<SDValue, 8> Ops;
9153    SDNode* ChainVal = St->getChain().getNode();
9154    // Must be a store of a load.  We currently handle two cases:  the load
9155    // is a direct child, and it's under an intervening TokenFactor.  It is
9156    // possible to dig deeper under nested TokenFactors.
9157    if (ChainVal == LdVal)
9158      Ld = cast<LoadSDNode>(St->getChain());
9159    else if (St->getValue().hasOneUse() &&
9160             ChainVal->getOpcode() == ISD::TokenFactor) {
9161      for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9162        if (ChainVal->getOperand(i).getNode() == LdVal) {
9163          TokenFactorIndex = i;
9164          Ld = cast<LoadSDNode>(St->getValue());
9165        } else
9166          Ops.push_back(ChainVal->getOperand(i));
9167      }
9168    }
9169
9170    if (!Ld || !ISD::isNormalLoad(Ld))
9171      return SDValue();
9172
9173    // If this is not the MMX case, i.e. we are just turning i64 load/store
9174    // into f64 load/store, avoid the transformation if there are multiple
9175    // uses of the loaded value.
9176    if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9177      return SDValue();
9178
9179    DebugLoc LdDL = Ld->getDebugLoc();
9180    DebugLoc StDL = N->getDebugLoc();
9181    // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9182    // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9183    // pair instead.
9184    if (Subtarget->is64Bit() || F64IsLegal) {
9185      EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9186      SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9187                                  Ld->getBasePtr(), Ld->getSrcValue(),
9188                                  Ld->getSrcValueOffset(), Ld->isVolatile(),
9189                                  Ld->getAlignment());
9190      SDValue NewChain = NewLd.getValue(1);
9191      if (TokenFactorIndex != -1) {
9192        Ops.push_back(NewChain);
9193        NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9194                               Ops.size());
9195      }
9196      return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9197                          St->getSrcValue(), St->getSrcValueOffset(),
9198                          St->isVolatile(), St->getAlignment());
9199    }
9200
9201    // Otherwise, lower to two pairs of 32-bit loads / stores.
9202    SDValue LoAddr = Ld->getBasePtr();
9203    SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9204                                 DAG.getConstant(4, MVT::i32));
9205
9206    SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9207                               Ld->getSrcValue(), Ld->getSrcValueOffset(),
9208                               Ld->isVolatile(), Ld->getAlignment());
9209    SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9210                               Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9211                               Ld->isVolatile(),
9212                               MinAlign(Ld->getAlignment(), 4));
9213
9214    SDValue NewChain = LoLd.getValue(1);
9215    if (TokenFactorIndex != -1) {
9216      Ops.push_back(LoLd);
9217      Ops.push_back(HiLd);
9218      NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9219                             Ops.size());
9220    }
9221
9222    LoAddr = St->getBasePtr();
9223    HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9224                         DAG.getConstant(4, MVT::i32));
9225
9226    SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9227                                St->getSrcValue(), St->getSrcValueOffset(),
9228                                St->isVolatile(), St->getAlignment());
9229    SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9230                                St->getSrcValue(),
9231                                St->getSrcValueOffset() + 4,
9232                                St->isVolatile(),
9233                                MinAlign(St->getAlignment(), 4));
9234    return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9235  }
9236  return SDValue();
9237}
9238
9239/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9240/// X86ISD::FXOR nodes.
9241static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9242  assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9243  // F[X]OR(0.0, x) -> x
9244  // F[X]OR(x, 0.0) -> x
9245  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9246    if (C->getValueAPF().isPosZero())
9247      return N->getOperand(1);
9248  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9249    if (C->getValueAPF().isPosZero())
9250      return N->getOperand(0);
9251  return SDValue();
9252}
9253
9254/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9255static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9256  // FAND(0.0, x) -> 0.0
9257  // FAND(x, 0.0) -> 0.0
9258  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9259    if (C->getValueAPF().isPosZero())
9260      return N->getOperand(0);
9261  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9262    if (C->getValueAPF().isPosZero())
9263      return N->getOperand(1);
9264  return SDValue();
9265}
9266
9267static SDValue PerformBTCombine(SDNode *N,
9268                                SelectionDAG &DAG,
9269                                TargetLowering::DAGCombinerInfo &DCI) {
9270  // BT ignores high bits in the bit index operand.
9271  SDValue Op1 = N->getOperand(1);
9272  if (Op1.hasOneUse()) {
9273    unsigned BitWidth = Op1.getValueSizeInBits();
9274    APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9275    APInt KnownZero, KnownOne;
9276    TargetLowering::TargetLoweringOpt TLO(DAG);
9277    TargetLowering &TLI = DAG.getTargetLoweringInfo();
9278    if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9279        TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9280      DCI.CommitTargetLoweringOpt(TLO);
9281  }
9282  return SDValue();
9283}
9284
9285static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9286  SDValue Op = N->getOperand(0);
9287  if (Op.getOpcode() == ISD::BIT_CONVERT)
9288    Op = Op.getOperand(0);
9289  EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9290  if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9291      VT.getVectorElementType().getSizeInBits() ==
9292      OpVT.getVectorElementType().getSizeInBits()) {
9293    return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9294  }
9295  return SDValue();
9296}
9297
9298// On X86 and X86-64, atomic operations are lowered to locked instructions.
9299// Locked instructions, in turn, have implicit fence semantics (all memory
9300// operations are flushed before issuing the locked instruction, and the
9301// are not buffered), so we can fold away the common pattern of
9302// fence-atomic-fence.
9303static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9304  SDValue atomic = N->getOperand(0);
9305  switch (atomic.getOpcode()) {
9306    case ISD::ATOMIC_CMP_SWAP:
9307    case ISD::ATOMIC_SWAP:
9308    case ISD::ATOMIC_LOAD_ADD:
9309    case ISD::ATOMIC_LOAD_SUB:
9310    case ISD::ATOMIC_LOAD_AND:
9311    case ISD::ATOMIC_LOAD_OR:
9312    case ISD::ATOMIC_LOAD_XOR:
9313    case ISD::ATOMIC_LOAD_NAND:
9314    case ISD::ATOMIC_LOAD_MIN:
9315    case ISD::ATOMIC_LOAD_MAX:
9316    case ISD::ATOMIC_LOAD_UMIN:
9317    case ISD::ATOMIC_LOAD_UMAX:
9318      break;
9319    default:
9320      return SDValue();
9321  }
9322
9323  SDValue fence = atomic.getOperand(0);
9324  if (fence.getOpcode() != ISD::MEMBARRIER)
9325    return SDValue();
9326
9327  switch (atomic.getOpcode()) {
9328    case ISD::ATOMIC_CMP_SWAP:
9329      return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9330                                    atomic.getOperand(1), atomic.getOperand(2),
9331                                    atomic.getOperand(3));
9332    case ISD::ATOMIC_SWAP:
9333    case ISD::ATOMIC_LOAD_ADD:
9334    case ISD::ATOMIC_LOAD_SUB:
9335    case ISD::ATOMIC_LOAD_AND:
9336    case ISD::ATOMIC_LOAD_OR:
9337    case ISD::ATOMIC_LOAD_XOR:
9338    case ISD::ATOMIC_LOAD_NAND:
9339    case ISD::ATOMIC_LOAD_MIN:
9340    case ISD::ATOMIC_LOAD_MAX:
9341    case ISD::ATOMIC_LOAD_UMIN:
9342    case ISD::ATOMIC_LOAD_UMAX:
9343      return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9344                                    atomic.getOperand(1), atomic.getOperand(2));
9345    default:
9346      return SDValue();
9347  }
9348}
9349
9350SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9351                                             DAGCombinerInfo &DCI) const {
9352  SelectionDAG &DAG = DCI.DAG;
9353  switch (N->getOpcode()) {
9354  default: break;
9355  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9356  case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
9357  case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
9358  case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
9359  case ISD::SHL:
9360  case ISD::SRA:
9361  case ISD::SRL:            return PerformShiftCombine(N, DAG, Subtarget);
9362  case ISD::STORE:          return PerformSTORECombine(N, DAG, Subtarget);
9363  case X86ISD::FXOR:
9364  case X86ISD::FOR:         return PerformFORCombine(N, DAG);
9365  case X86ISD::FAND:        return PerformFANDCombine(N, DAG);
9366  case X86ISD::BT:          return PerformBTCombine(N, DAG, DCI);
9367  case X86ISD::VZEXT_MOVL:  return PerformVZEXT_MOVLCombine(N, DAG);
9368  case ISD::MEMBARRIER:     return PerformMEMBARRIERCombine(N, DAG);
9369  }
9370
9371  return SDValue();
9372}
9373
9374//===----------------------------------------------------------------------===//
9375//                           X86 Inline Assembly Support
9376//===----------------------------------------------------------------------===//
9377
9378static bool LowerToBSwap(CallInst *CI) {
9379  // FIXME: this should verify that we are targetting a 486 or better.  If not,
9380  // we will turn this bswap into something that will be lowered to logical ops
9381  // instead of emitting the bswap asm.  For now, we don't support 486 or lower
9382  // so don't worry about this.
9383
9384  // Verify this is a simple bswap.
9385  if (CI->getNumOperands() != 2 ||
9386      CI->getType() != CI->getOperand(1)->getType() ||
9387      !CI->getType()->isInteger())
9388    return false;
9389
9390  const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9391  if (!Ty || Ty->getBitWidth() % 16 != 0)
9392    return false;
9393
9394  // Okay, we can do this xform, do so now.
9395  const Type *Tys[] = { Ty };
9396  Module *M = CI->getParent()->getParent()->getParent();
9397  Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9398
9399  Value *Op = CI->getOperand(1);
9400  Op = CallInst::Create(Int, Op, CI->getName(), CI);
9401
9402  CI->replaceAllUsesWith(Op);
9403  CI->eraseFromParent();
9404  return true;
9405}
9406
9407bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9408  InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9409  std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9410
9411  std::string AsmStr = IA->getAsmString();
9412
9413  // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9414  std::vector<std::string> AsmPieces;
9415  SplitString(AsmStr, AsmPieces, "\n");  // ; as separator?
9416
9417  switch (AsmPieces.size()) {
9418  default: return false;
9419  case 1:
9420    AsmStr = AsmPieces[0];
9421    AsmPieces.clear();
9422    SplitString(AsmStr, AsmPieces, " \t");  // Split with whitespace.
9423
9424    // bswap $0
9425    if (AsmPieces.size() == 2 &&
9426        (AsmPieces[0] == "bswap" ||
9427         AsmPieces[0] == "bswapq" ||
9428         AsmPieces[0] == "bswapl") &&
9429        (AsmPieces[1] == "$0" ||
9430         AsmPieces[1] == "${0:q}")) {
9431      // No need to check constraints, nothing other than the equivalent of
9432      // "=r,0" would be valid here.
9433      return LowerToBSwap(CI);
9434    }
9435    // rorw $$8, ${0:w}  -->  llvm.bswap.i16
9436    if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9437        AsmPieces.size() == 3 &&
9438        AsmPieces[0] == "rorw" &&
9439        AsmPieces[1] == "$$8," &&
9440        AsmPieces[2] == "${0:w}" &&
9441        IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9442      return LowerToBSwap(CI);
9443    }
9444    break;
9445  case 3:
9446    if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9447        Constraints.size() >= 2 &&
9448        Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9449        Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9450      // bswap %eax / bswap %edx / xchgl %eax, %edx  -> llvm.bswap.i64
9451      std::vector<std::string> Words;
9452      SplitString(AsmPieces[0], Words, " \t");
9453      if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9454        Words.clear();
9455        SplitString(AsmPieces[1], Words, " \t");
9456        if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9457          Words.clear();
9458          SplitString(AsmPieces[2], Words, " \t,");
9459          if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9460              Words[2] == "%edx") {
9461            return LowerToBSwap(CI);
9462          }
9463        }
9464      }
9465    }
9466    break;
9467  }
9468  return false;
9469}
9470
9471
9472
9473/// getConstraintType - Given a constraint letter, return the type of
9474/// constraint it is for this target.
9475X86TargetLowering::ConstraintType
9476X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9477  if (Constraint.size() == 1) {
9478    switch (Constraint[0]) {
9479    case 'A':
9480      return C_Register;
9481    case 'f':
9482    case 'r':
9483    case 'R':
9484    case 'l':
9485    case 'q':
9486    case 'Q':
9487    case 'x':
9488    case 'y':
9489    case 'Y':
9490      return C_RegisterClass;
9491    case 'e':
9492    case 'Z':
9493      return C_Other;
9494    default:
9495      break;
9496    }
9497  }
9498  return TargetLowering::getConstraintType(Constraint);
9499}
9500
9501/// LowerXConstraint - try to replace an X constraint, which matches anything,
9502/// with another that has more specific requirements based on the type of the
9503/// corresponding operand.
9504const char *X86TargetLowering::
9505LowerXConstraint(EVT ConstraintVT) const {
9506  // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9507  // 'f' like normal targets.
9508  if (ConstraintVT.isFloatingPoint()) {
9509    if (Subtarget->hasSSE2())
9510      return "Y";
9511    if (Subtarget->hasSSE1())
9512      return "x";
9513  }
9514
9515  return TargetLowering::LowerXConstraint(ConstraintVT);
9516}
9517
9518/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9519/// vector.  If it is invalid, don't add anything to Ops.
9520void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9521                                                     char Constraint,
9522                                                     bool hasMemory,
9523                                                     std::vector<SDValue>&Ops,
9524                                                     SelectionDAG &DAG) const {
9525  SDValue Result(0, 0);
9526
9527  switch (Constraint) {
9528  default: break;
9529  case 'I':
9530    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9531      if (C->getZExtValue() <= 31) {
9532        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9533        break;
9534      }
9535    }
9536    return;
9537  case 'J':
9538    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9539      if (C->getZExtValue() <= 63) {
9540        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9541        break;
9542      }
9543    }
9544    return;
9545  case 'K':
9546    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9547      if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9548        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9549        break;
9550      }
9551    }
9552    return;
9553  case 'N':
9554    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9555      if (C->getZExtValue() <= 255) {
9556        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9557        break;
9558      }
9559    }
9560    return;
9561  case 'e': {
9562    // 32-bit signed value
9563    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9564      const ConstantInt *CI = C->getConstantIntValue();
9565      if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9566                                  C->getSExtValue())) {
9567        // Widen to 64 bits here to get it sign extended.
9568        Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9569        break;
9570      }
9571    // FIXME gcc accepts some relocatable values here too, but only in certain
9572    // memory models; it's complicated.
9573    }
9574    return;
9575  }
9576  case 'Z': {
9577    // 32-bit unsigned value
9578    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9579      const ConstantInt *CI = C->getConstantIntValue();
9580      if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9581                                  C->getZExtValue())) {
9582        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9583        break;
9584      }
9585    }
9586    // FIXME gcc accepts some relocatable values here too, but only in certain
9587    // memory models; it's complicated.
9588    return;
9589  }
9590  case 'i': {
9591    // Literal immediates are always ok.
9592    if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9593      // Widen to 64 bits here to get it sign extended.
9594      Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9595      break;
9596    }
9597
9598    // If we are in non-pic codegen mode, we allow the address of a global (with
9599    // an optional displacement) to be used with 'i'.
9600    GlobalAddressSDNode *GA = 0;
9601    int64_t Offset = 0;
9602
9603    // Match either (GA), (GA+C), (GA+C1+C2), etc.
9604    while (1) {
9605      if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9606        Offset += GA->getOffset();
9607        break;
9608      } else if (Op.getOpcode() == ISD::ADD) {
9609        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9610          Offset += C->getZExtValue();
9611          Op = Op.getOperand(0);
9612          continue;
9613        }
9614      } else if (Op.getOpcode() == ISD::SUB) {
9615        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9616          Offset += -C->getZExtValue();
9617          Op = Op.getOperand(0);
9618          continue;
9619        }
9620      }
9621
9622      // Otherwise, this isn't something we can handle, reject it.
9623      return;
9624    }
9625
9626    GlobalValue *GV = GA->getGlobal();
9627    // If we require an extra load to get this address, as in PIC mode, we
9628    // can't accept it.
9629    if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9630                                                        getTargetMachine())))
9631      return;
9632
9633    if (hasMemory)
9634      Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9635    else
9636      Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9637    Result = Op;
9638    break;
9639  }
9640  }
9641
9642  if (Result.getNode()) {
9643    Ops.push_back(Result);
9644    return;
9645  }
9646  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9647                                                      Ops, DAG);
9648}
9649
9650std::vector<unsigned> X86TargetLowering::
9651getRegClassForInlineAsmConstraint(const std::string &Constraint,
9652                                  EVT VT) const {
9653  if (Constraint.size() == 1) {
9654    // FIXME: not handling fp-stack yet!
9655    switch (Constraint[0]) {      // GCC X86 Constraint Letters
9656    default: break;  // Unknown constraint letter
9657    case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9658      if (Subtarget->is64Bit()) {
9659        if (VT == MVT::i32)
9660          return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9661                                       X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9662                                       X86::R10D,X86::R11D,X86::R12D,
9663                                       X86::R13D,X86::R14D,X86::R15D,
9664                                       X86::EBP, X86::ESP, 0);
9665        else if (VT == MVT::i16)
9666          return make_vector<unsigned>(X86::AX,  X86::DX,  X86::CX, X86::BX,
9667                                       X86::SI,  X86::DI,  X86::R8W,X86::R9W,
9668                                       X86::R10W,X86::R11W,X86::R12W,
9669                                       X86::R13W,X86::R14W,X86::R15W,
9670                                       X86::BP,  X86::SP, 0);
9671        else if (VT == MVT::i8)
9672          return make_vector<unsigned>(X86::AL,  X86::DL,  X86::CL, X86::BL,
9673                                       X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9674                                       X86::R10B,X86::R11B,X86::R12B,
9675                                       X86::R13B,X86::R14B,X86::R15B,
9676                                       X86::BPL, X86::SPL, 0);
9677
9678        else if (VT == MVT::i64)
9679          return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9680                                       X86::RSI, X86::RDI, X86::R8,  X86::R9,
9681                                       X86::R10, X86::R11, X86::R12,
9682                                       X86::R13, X86::R14, X86::R15,
9683                                       X86::RBP, X86::RSP, 0);
9684
9685        break;
9686      }
9687      // 32-bit fallthrough
9688    case 'Q':   // Q_REGS
9689      if (VT == MVT::i32)
9690        return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9691      else if (VT == MVT::i16)
9692        return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9693      else if (VT == MVT::i8)
9694        return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9695      else if (VT == MVT::i64)
9696        return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9697      break;
9698    }
9699  }
9700
9701  return std::vector<unsigned>();
9702}
9703
9704std::pair<unsigned, const TargetRegisterClass*>
9705X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9706                                                EVT VT) const {
9707  // First, see if this is a constraint that directly corresponds to an LLVM
9708  // register class.
9709  if (Constraint.size() == 1) {
9710    // GCC Constraint Letters
9711    switch (Constraint[0]) {
9712    default: break;
9713    case 'r':   // GENERAL_REGS
9714    case 'l':   // INDEX_REGS
9715      if (VT == MVT::i8)
9716        return std::make_pair(0U, X86::GR8RegisterClass);
9717      if (VT == MVT::i16)
9718        return std::make_pair(0U, X86::GR16RegisterClass);
9719      if (VT == MVT::i32 || !Subtarget->is64Bit())
9720        return std::make_pair(0U, X86::GR32RegisterClass);
9721      return std::make_pair(0U, X86::GR64RegisterClass);
9722    case 'R':   // LEGACY_REGS
9723      if (VT == MVT::i8)
9724        return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9725      if (VT == MVT::i16)
9726        return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9727      if (VT == MVT::i32 || !Subtarget->is64Bit())
9728        return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9729      return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9730    case 'f':  // FP Stack registers.
9731      // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9732      // value to the correct fpstack register class.
9733      if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9734        return std::make_pair(0U, X86::RFP32RegisterClass);
9735      if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9736        return std::make_pair(0U, X86::RFP64RegisterClass);
9737      return std::make_pair(0U, X86::RFP80RegisterClass);
9738    case 'y':   // MMX_REGS if MMX allowed.
9739      if (!Subtarget->hasMMX()) break;
9740      return std::make_pair(0U, X86::VR64RegisterClass);
9741    case 'Y':   // SSE_REGS if SSE2 allowed
9742      if (!Subtarget->hasSSE2()) break;
9743      // FALL THROUGH.
9744    case 'x':   // SSE_REGS if SSE1 allowed
9745      if (!Subtarget->hasSSE1()) break;
9746
9747      switch (VT.getSimpleVT().SimpleTy) {
9748      default: break;
9749      // Scalar SSE types.
9750      case MVT::f32:
9751      case MVT::i32:
9752        return std::make_pair(0U, X86::FR32RegisterClass);
9753      case MVT::f64:
9754      case MVT::i64:
9755        return std::make_pair(0U, X86::FR64RegisterClass);
9756      // Vector types.
9757      case MVT::v16i8:
9758      case MVT::v8i16:
9759      case MVT::v4i32:
9760      case MVT::v2i64:
9761      case MVT::v4f32:
9762      case MVT::v2f64:
9763        return std::make_pair(0U, X86::VR128RegisterClass);
9764      }
9765      break;
9766    }
9767  }
9768
9769  // Use the default implementation in TargetLowering to convert the register
9770  // constraint into a member of a register class.
9771  std::pair<unsigned, const TargetRegisterClass*> Res;
9772  Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9773
9774  // Not found as a standard register?
9775  if (Res.second == 0) {
9776    // Map st(0) -> st(7) -> ST0
9777    if (Constraint.size() == 7 && Constraint[0] == '{' &&
9778        tolower(Constraint[1]) == 's' &&
9779        tolower(Constraint[2]) == 't' &&
9780        Constraint[3] == '(' &&
9781        (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9782        Constraint[5] == ')' &&
9783        Constraint[6] == '}') {
9784
9785      Res.first = X86::ST0+Constraint[4]-'0';
9786      Res.second = X86::RFP80RegisterClass;
9787      return Res;
9788    }
9789
9790    // GCC allows "st(0)" to be called just plain "st".
9791    if (StringRef("{st}").equals_lower(Constraint)) {
9792      Res.first = X86::ST0;
9793      Res.second = X86::RFP80RegisterClass;
9794      return Res;
9795    }
9796
9797    // flags -> EFLAGS
9798    if (StringRef("{flags}").equals_lower(Constraint)) {
9799      Res.first = X86::EFLAGS;
9800      Res.second = X86::CCRRegisterClass;
9801      return Res;
9802    }
9803
9804    // 'A' means EAX + EDX.
9805    if (Constraint == "A") {
9806      Res.first = X86::EAX;
9807      Res.second = X86::GR32_ADRegisterClass;
9808      return Res;
9809    }
9810    return Res;
9811  }
9812
9813  // Otherwise, check to see if this is a register class of the wrong value
9814  // type.  For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9815  // turn into {ax},{dx}.
9816  if (Res.second->hasType(VT))
9817    return Res;   // Correct type already, nothing to do.
9818
9819  // All of the single-register GCC register classes map their values onto
9820  // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp".  If we
9821  // really want an 8-bit or 32-bit register, map to the appropriate register
9822  // class and return the appropriate register.
9823  if (Res.second == X86::GR16RegisterClass) {
9824    if (VT == MVT::i8) {
9825      unsigned DestReg = 0;
9826      switch (Res.first) {
9827      default: break;
9828      case X86::AX: DestReg = X86::AL; break;
9829      case X86::DX: DestReg = X86::DL; break;
9830      case X86::CX: DestReg = X86::CL; break;
9831      case X86::BX: DestReg = X86::BL; break;
9832      }
9833      if (DestReg) {
9834        Res.first = DestReg;
9835        Res.second = X86::GR8RegisterClass;
9836      }
9837    } else if (VT == MVT::i32) {
9838      unsigned DestReg = 0;
9839      switch (Res.first) {
9840      default: break;
9841      case X86::AX: DestReg = X86::EAX; break;
9842      case X86::DX: DestReg = X86::EDX; break;
9843      case X86::CX: DestReg = X86::ECX; break;
9844      case X86::BX: DestReg = X86::EBX; break;
9845      case X86::SI: DestReg = X86::ESI; break;
9846      case X86::DI: DestReg = X86::EDI; break;
9847      case X86::BP: DestReg = X86::EBP; break;
9848      case X86::SP: DestReg = X86::ESP; break;
9849      }
9850      if (DestReg) {
9851        Res.first = DestReg;
9852        Res.second = X86::GR32RegisterClass;
9853      }
9854    } else if (VT == MVT::i64) {
9855      unsigned DestReg = 0;
9856      switch (Res.first) {
9857      default: break;
9858      case X86::AX: DestReg = X86::RAX; break;
9859      case X86::DX: DestReg = X86::RDX; break;
9860      case X86::CX: DestReg = X86::RCX; break;
9861      case X86::BX: DestReg = X86::RBX; break;
9862      case X86::SI: DestReg = X86::RSI; break;
9863      case X86::DI: DestReg = X86::RDI; break;
9864      case X86::BP: DestReg = X86::RBP; break;
9865      case X86::SP: DestReg = X86::RSP; break;
9866      }
9867      if (DestReg) {
9868        Res.first = DestReg;
9869        Res.second = X86::GR64RegisterClass;
9870      }
9871    }
9872  } else if (Res.second == X86::FR32RegisterClass ||
9873             Res.second == X86::FR64RegisterClass ||
9874             Res.second == X86::VR128RegisterClass) {
9875    // Handle references to XMM physical registers that got mapped into the
9876    // wrong class.  This can happen with constraints like {xmm0} where the
9877    // target independent register mapper will just pick the first match it can
9878    // find, ignoring the required type.
9879    if (VT == MVT::f32)
9880      Res.second = X86::FR32RegisterClass;
9881    else if (VT == MVT::f64)
9882      Res.second = X86::FR64RegisterClass;
9883    else if (X86::VR128RegisterClass->hasType(VT))
9884      Res.second = X86::VR128RegisterClass;
9885  }
9886
9887  return Res;
9888}
9889
9890//===----------------------------------------------------------------------===//
9891//                           X86 Widen vector type
9892//===----------------------------------------------------------------------===//
9893
9894/// getWidenVectorType: given a vector type, returns the type to widen
9895/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9896/// If there is no vector type that we want to widen to, returns MVT::Other
9897/// When and where to widen is target dependent based on the cost of
9898/// scalarizing vs using the wider vector type.
9899
9900EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9901  assert(VT.isVector());
9902  if (isTypeLegal(VT))
9903    return VT;
9904
9905  // TODO: In computeRegisterProperty, we can compute the list of legal vector
9906  //       type based on element type.  This would speed up our search (though
9907  //       it may not be worth it since the size of the list is relatively
9908  //       small).
9909  EVT EltVT = VT.getVectorElementType();
9910  unsigned NElts = VT.getVectorNumElements();
9911
9912  // On X86, it make sense to widen any vector wider than 1
9913  if (NElts <= 1)
9914    return MVT::Other;
9915
9916  for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9917       nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9918    EVT SVT = (MVT::SimpleValueType)nVT;
9919
9920    if (isTypeLegal(SVT) &&
9921        SVT.getVectorElementType() == EltVT &&
9922        SVT.getVectorNumElements() > NElts)
9923      return SVT;
9924  }
9925  return MVT::Other;
9926}
9927