X86ISelLowering.cpp revision ae16d6b9722dd6ff4a606308e3a14d200f3a903f
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/MC/MCAsmInfo.h" 40#include "llvm/MC/MCContext.h" 41#include "llvm/MC/MCExpr.h" 42#include "llvm/MC/MCSymbol.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/Support/CallSite.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG); 75 76 77/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 78/// sets things up to match to an AVX VEXTRACTF128 instruction or a 79/// simple subregister reference. Idx is an index in the 128 bits we 80/// want. It need not be aligned to a 128-bit bounday. That makes 81/// lowering EXTRACT_VECTOR_ELT operations easier. 82static SDValue Extract128BitVector(SDValue Vec, 83 SDValue Idx, 84 SelectionDAG &DAG, 85 DebugLoc dl) { 86 EVT VT = Vec.getValueType(); 87 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 88 89 EVT ElVT = VT.getVectorElementType(); 90 91 int Factor = VT.getSizeInBits() / 128; 92 93 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), 94 ElVT, 95 VT.getVectorNumElements() / Factor); 96 97 // Extract from UNDEF is UNDEF. 98 if (Vec.getOpcode() == ISD::UNDEF) 99 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 100 101 if (isa<ConstantSDNode>(Idx)) { 102 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 103 104 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 105 // we can match to VEXTRACTF128. 106 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 107 108 // This is the index of the first element of the 128-bit chunk 109 // we want. 110 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 111 * ElemsPerChunk); 112 113 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 114 115 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 116 VecIdx); 117 118 return Result; 119 } 120 121 return SDValue(); 122} 123 124/// Generate a DAG to put 128-bits into a vector > 128 bits. This 125/// sets things up to match to an AVX VINSERTF128 instruction or a 126/// simple superregister reference. Idx is an index in the 128 bits 127/// we want. It need not be aligned to a 128-bit bounday. That makes 128/// lowering INSERT_VECTOR_ELT operations easier. 129static SDValue Insert128BitVector(SDValue Result, 130 SDValue Vec, 131 SDValue Idx, 132 SelectionDAG &DAG, 133 DebugLoc dl) { 134 if (isa<ConstantSDNode>(Idx)) { 135 EVT VT = Vec.getValueType(); 136 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 137 138 EVT ElVT = VT.getVectorElementType(); 139 140 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 141 142 EVT ResultVT = Result.getValueType(); 143 144 // Insert the relevant 128 bits. 145 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 146 147 // This is the index of the first element of the 128-bit chunk 148 // we want. 149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 150 * ElemsPerChunk); 151 152 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 153 154 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 155 VecIdx); 156 return Result; 157 } 158 159 return SDValue(); 160} 161 162/// Given two vectors, concat them. 163static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG) { 164 DebugLoc dl = Lower.getDebugLoc(); 165 166 assert(Lower.getValueType() == Upper.getValueType() && "Mismatched vectors!"); 167 168 EVT VT = EVT::getVectorVT(*DAG.getContext(), 169 Lower.getValueType().getVectorElementType(), 170 Lower.getValueType().getVectorNumElements() * 2); 171 172 // TODO: Generalize to arbitrary vector length (this assumes 256-bit vectors). 173 assert(VT.getSizeInBits() == 256 && "Unsupported vector concat!"); 174 175 // Insert the upper subvector. 176 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper, 177 DAG.getConstant( 178 // This is half the length of the result 179 // vector. Start inserting the upper 128 180 // bits here. 181 Lower.getValueType().getVectorNumElements(), 182 MVT::i32), 183 DAG, dl); 184 185 // Insert the lower subvector. 186 Vec = Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32), DAG, dl); 187 return Vec; 188} 189 190static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 191 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 192 bool is64Bit = Subtarget->is64Bit(); 193 194 if (Subtarget->isTargetEnvMacho()) { 195 if (is64Bit) 196 return new X8664_MachoTargetObjectFile(); 197 return new TargetLoweringObjectFileMachO(); 198 } 199 200 if (Subtarget->isTargetELF()) { 201 if (is64Bit) 202 return new X8664_ELFTargetObjectFile(TM); 203 return new X8632_ELFTargetObjectFile(TM); 204 } 205 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 206 return new TargetLoweringObjectFileCOFF(); 207 llvm_unreachable("unknown subtarget type"); 208} 209 210X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 211 : TargetLowering(TM, createTLOF(TM)) { 212 Subtarget = &TM.getSubtarget<X86Subtarget>(); 213 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 214 X86ScalarSSEf32 = Subtarget->hasXMM(); 215 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 216 217 RegInfo = TM.getRegisterInfo(); 218 TD = getTargetData(); 219 220 // Set up the TargetLowering object. 221 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 222 223 // X86 is weird, it always uses i8 for shift amounts and setcc results. 224 setBooleanContents(ZeroOrOneBooleanContent); 225 226 // For 64-bit since we have so many registers use the ILP scheduler, for 227 // 32-bit code use the register pressure specific scheduling. 228 if (Subtarget->is64Bit()) 229 setSchedulingPreference(Sched::ILP); 230 else 231 setSchedulingPreference(Sched::RegPressure); 232 setStackPointerRegisterToSaveRestore(X86StackPtr); 233 234 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 235 // Setup Windows compiler runtime calls. 236 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 237 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 238 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 239 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 240 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 241 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 242 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 243 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 244 } 245 246 if (Subtarget->isTargetDarwin()) { 247 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 248 setUseUnderscoreSetJmp(false); 249 setUseUnderscoreLongJmp(false); 250 } else if (Subtarget->isTargetMingw()) { 251 // MS runtime is weird: it exports _setjmp, but longjmp! 252 setUseUnderscoreSetJmp(true); 253 setUseUnderscoreLongJmp(false); 254 } else { 255 setUseUnderscoreSetJmp(true); 256 setUseUnderscoreLongJmp(true); 257 } 258 259 // Set up the register classes. 260 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 261 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 262 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 263 if (Subtarget->is64Bit()) 264 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 265 266 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 267 268 // We don't accept any truncstore of integer registers. 269 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 270 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 271 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 272 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 273 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 274 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 275 276 // SETOEQ and SETUNE require checking two conditions. 277 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 278 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 279 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 280 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 281 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 282 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 283 284 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 285 // operation. 286 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 287 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 288 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 289 290 if (Subtarget->is64Bit()) { 291 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 292 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 293 } else if (!UseSoftFloat) { 294 // We have an algorithm for SSE2->double, and we turn this into a 295 // 64-bit FILD followed by conditional FADD for other targets. 296 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 297 // We have an algorithm for SSE2, and we turn this into a 64-bit 298 // FILD for other targets. 299 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 300 } 301 302 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 303 // this operation. 304 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 305 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 306 307 if (!UseSoftFloat) { 308 // SSE has no i16 to fp conversion, only i32 309 if (X86ScalarSSEf32) { 310 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 311 // f32 and f64 cases are Legal, f80 case is not 312 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 313 } else { 314 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 315 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 316 } 317 } else { 318 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 319 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 320 } 321 322 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 323 // are Legal, f80 is custom lowered. 324 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 325 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 326 327 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 328 // this operation. 329 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 330 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 331 332 if (X86ScalarSSEf32) { 333 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 334 // f32 and f64 cases are Legal, f80 case is not 335 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 336 } else { 337 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 338 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 339 } 340 341 // Handle FP_TO_UINT by promoting the destination to a larger signed 342 // conversion. 343 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 344 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 345 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 346 347 if (Subtarget->is64Bit()) { 348 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 349 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 350 } else if (!UseSoftFloat) { 351 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 352 // Expand FP_TO_UINT into a select. 353 // FIXME: We would like to use a Custom expander here eventually to do 354 // the optimal thing for SSE vs. the default expansion in the legalizer. 355 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 356 else 357 // With SSE3 we can use fisttpll to convert to a signed i64; without 358 // SSE, we're stuck with a fistpll. 359 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 360 } 361 362 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 363 if (!X86ScalarSSEf64) { 364 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 365 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 366 if (Subtarget->is64Bit()) { 367 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 368 // Without SSE, i64->f64 goes through memory. 369 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 370 } 371 } 372 373 // Scalar integer divide and remainder are lowered to use operations that 374 // produce two results, to match the available instructions. This exposes 375 // the two-result form to trivial CSE, which is able to combine x/y and x%y 376 // into a single instruction. 377 // 378 // Scalar integer multiply-high is also lowered to use two-result 379 // operations, to match the available instructions. However, plain multiply 380 // (low) operations are left as Legal, as there are single-result 381 // instructions for this in x86. Using the two-result multiply instructions 382 // when both high and low results are needed must be arranged by dagcombine. 383 for (unsigned i = 0, e = 4; i != e; ++i) { 384 MVT VT = IntVTs[i]; 385 setOperationAction(ISD::MULHS, VT, Expand); 386 setOperationAction(ISD::MULHU, VT, Expand); 387 setOperationAction(ISD::SDIV, VT, Expand); 388 setOperationAction(ISD::UDIV, VT, Expand); 389 setOperationAction(ISD::SREM, VT, Expand); 390 setOperationAction(ISD::UREM, VT, Expand); 391 392 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 393 setOperationAction(ISD::ADDC, VT, Custom); 394 setOperationAction(ISD::ADDE, VT, Custom); 395 setOperationAction(ISD::SUBC, VT, Custom); 396 setOperationAction(ISD::SUBE, VT, Custom); 397 } 398 399 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 400 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 401 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 402 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 403 if (Subtarget->is64Bit()) 404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 408 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 409 setOperationAction(ISD::FREM , MVT::f32 , Expand); 410 setOperationAction(ISD::FREM , MVT::f64 , Expand); 411 setOperationAction(ISD::FREM , MVT::f80 , Expand); 412 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 413 414 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 416 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 417 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 418 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 419 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 420 if (Subtarget->is64Bit()) { 421 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 423 } 424 425 if (Subtarget->hasPOPCNT()) { 426 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 427 } else { 428 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 429 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 430 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 431 if (Subtarget->is64Bit()) 432 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 433 } 434 435 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 436 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 437 438 // These should be promoted to a larger select which is supported. 439 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 440 // X86 wants to expand cmov itself. 441 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 442 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 443 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 444 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 445 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 446 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 448 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 449 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 450 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 451 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 452 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 453 if (Subtarget->is64Bit()) { 454 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 455 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 456 } 457 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 458 459 // Darwin ABI issue. 460 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 461 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 462 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 463 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 464 if (Subtarget->is64Bit()) 465 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 466 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 467 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 468 if (Subtarget->is64Bit()) { 469 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 470 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 471 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 472 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 473 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 474 } 475 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 476 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 477 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 478 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 479 if (Subtarget->is64Bit()) { 480 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 481 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 482 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 483 } 484 485 if (Subtarget->hasXMM()) 486 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 487 488 // We may not have a libcall for MEMBARRIER so we should lower this. 489 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 490 491 // On X86 and X86-64, atomic operations are lowered to locked instructions. 492 // Locked instructions, in turn, have implicit fence semantics (all memory 493 // operations are flushed before issuing the locked instruction, and they 494 // are not buffered), so we can fold away the common pattern of 495 // fence-atomic-fence. 496 setShouldFoldAtomicFences(true); 497 498 // Expand certain atomics 499 for (unsigned i = 0, e = 4; i != e; ++i) { 500 MVT VT = IntVTs[i]; 501 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 502 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 503 } 504 505 if (!Subtarget->is64Bit()) { 506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 513 } 514 515 // FIXME - use subtarget debug flags 516 if (!Subtarget->isTargetDarwin() && 517 !Subtarget->isTargetELF() && 518 !Subtarget->isTargetCygMing()) { 519 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 520 } 521 522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 523 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 525 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 526 if (Subtarget->is64Bit()) { 527 setExceptionPointerRegister(X86::RAX); 528 setExceptionSelectorRegister(X86::RDX); 529 } else { 530 setExceptionPointerRegister(X86::EAX); 531 setExceptionSelectorRegister(X86::EDX); 532 } 533 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 534 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 535 536 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 537 538 setOperationAction(ISD::TRAP, MVT::Other, Legal); 539 540 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 541 setOperationAction(ISD::VASTART , MVT::Other, Custom); 542 setOperationAction(ISD::VAEND , MVT::Other, Expand); 543 if (Subtarget->is64Bit()) { 544 setOperationAction(ISD::VAARG , MVT::Other, Custom); 545 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 546 } else { 547 setOperationAction(ISD::VAARG , MVT::Other, Expand); 548 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 549 } 550 551 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 552 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 553 if (Subtarget->is64Bit()) 554 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 555 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) 556 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 557 else 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 559 560 if (!UseSoftFloat && X86ScalarSSEf64) { 561 // f32 and f64 use SSE. 562 // Set up the FP register classes. 563 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 564 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 565 566 // Use ANDPD to simulate FABS. 567 setOperationAction(ISD::FABS , MVT::f64, Custom); 568 setOperationAction(ISD::FABS , MVT::f32, Custom); 569 570 // Use XORP to simulate FNEG. 571 setOperationAction(ISD::FNEG , MVT::f64, Custom); 572 setOperationAction(ISD::FNEG , MVT::f32, Custom); 573 574 // Use ANDPD and ORPD to simulate FCOPYSIGN. 575 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 576 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 577 578 // We don't support sin/cos/fmod 579 setOperationAction(ISD::FSIN , MVT::f64, Expand); 580 setOperationAction(ISD::FCOS , MVT::f64, Expand); 581 setOperationAction(ISD::FSIN , MVT::f32, Expand); 582 setOperationAction(ISD::FCOS , MVT::f32, Expand); 583 584 // Expand FP immediates into loads from the stack, except for the special 585 // cases we handle. 586 addLegalFPImmediate(APFloat(+0.0)); // xorpd 587 addLegalFPImmediate(APFloat(+0.0f)); // xorps 588 } else if (!UseSoftFloat && X86ScalarSSEf32) { 589 // Use SSE for f32, x87 for f64. 590 // Set up the FP register classes. 591 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 592 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 593 594 // Use ANDPS to simulate FABS. 595 setOperationAction(ISD::FABS , MVT::f32, Custom); 596 597 // Use XORP to simulate FNEG. 598 setOperationAction(ISD::FNEG , MVT::f32, Custom); 599 600 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 601 602 // Use ANDPS and ORPS to simulate FCOPYSIGN. 603 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 604 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 605 606 // We don't support sin/cos/fmod 607 setOperationAction(ISD::FSIN , MVT::f32, Expand); 608 setOperationAction(ISD::FCOS , MVT::f32, Expand); 609 610 // Special cases we handle for FP constants. 611 addLegalFPImmediate(APFloat(+0.0f)); // xorps 612 addLegalFPImmediate(APFloat(+0.0)); // FLD0 613 addLegalFPImmediate(APFloat(+1.0)); // FLD1 614 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 615 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 616 617 if (!UnsafeFPMath) { 618 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 619 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 620 } 621 } else if (!UseSoftFloat) { 622 // f32 and f64 in x87. 623 // Set up the FP register classes. 624 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 625 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 626 627 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 628 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 629 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 630 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 631 632 if (!UnsafeFPMath) { 633 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 634 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 635 } 636 addLegalFPImmediate(APFloat(+0.0)); // FLD0 637 addLegalFPImmediate(APFloat(+1.0)); // FLD1 638 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 639 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 640 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 641 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 642 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 643 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 644 } 645 646 // Long double always uses X87. 647 if (!UseSoftFloat) { 648 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 649 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 650 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 651 { 652 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 653 addLegalFPImmediate(TmpFlt); // FLD0 654 TmpFlt.changeSign(); 655 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 656 657 bool ignored; 658 APFloat TmpFlt2(+1.0); 659 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 660 &ignored); 661 addLegalFPImmediate(TmpFlt2); // FLD1 662 TmpFlt2.changeSign(); 663 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 664 } 665 666 if (!UnsafeFPMath) { 667 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 668 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 669 } 670 } 671 672 // Always use a library call for pow. 673 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 674 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 675 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 676 677 setOperationAction(ISD::FLOG, MVT::f80, Expand); 678 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 679 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 680 setOperationAction(ISD::FEXP, MVT::f80, Expand); 681 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 682 683 // First set operation action for all vector types to either promote 684 // (for widening) or expand (for scalarization). Then we will selectively 685 // turn on ones that can be effectively codegen'd. 686 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 687 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 688 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 703 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 705 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 706 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 738 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 742 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 743 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 744 setTruncStoreAction((MVT::SimpleValueType)VT, 745 (MVT::SimpleValueType)InnerVT, Expand); 746 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 747 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 748 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 749 } 750 751 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 752 // with -msoft-float, disable use of MMX as well. 753 if (!UseSoftFloat && Subtarget->hasMMX()) { 754 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 755 // No operations on x86mmx supported, everything uses intrinsics. 756 } 757 758 // MMX-sized vectors (other than x86mmx) are expected to be expanded 759 // into smaller operations. 760 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 761 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 762 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 763 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 764 setOperationAction(ISD::AND, MVT::v8i8, Expand); 765 setOperationAction(ISD::AND, MVT::v4i16, Expand); 766 setOperationAction(ISD::AND, MVT::v2i32, Expand); 767 setOperationAction(ISD::AND, MVT::v1i64, Expand); 768 setOperationAction(ISD::OR, MVT::v8i8, Expand); 769 setOperationAction(ISD::OR, MVT::v4i16, Expand); 770 setOperationAction(ISD::OR, MVT::v2i32, Expand); 771 setOperationAction(ISD::OR, MVT::v1i64, Expand); 772 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 773 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 774 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 775 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 778 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 779 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 780 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 781 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 782 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 783 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 784 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 785 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 786 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 787 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 788 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 789 790 if (!UseSoftFloat && Subtarget->hasXMM()) { 791 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 792 793 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 794 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 795 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 796 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 797 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 798 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 799 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 800 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 801 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 802 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 803 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 804 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 805 } 806 807 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 808 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 809 810 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 811 // registers cannot be used even for integer operations. 812 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 813 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 814 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 815 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 816 817 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 818 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 819 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 820 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 821 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 822 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 823 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 824 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 825 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 826 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 827 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 828 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 829 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 830 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 831 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 832 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 833 834 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 835 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 836 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 837 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 838 839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 844 845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 848 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 849 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 850 851 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 852 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 853 EVT VT = (MVT::SimpleValueType)i; 854 // Do not attempt to custom lower non-power-of-2 vectors 855 if (!isPowerOf2_32(VT.getVectorNumElements())) 856 continue; 857 // Do not attempt to custom lower non-128-bit vectors 858 if (!VT.is128BitVector()) 859 continue; 860 setOperationAction(ISD::BUILD_VECTOR, 861 VT.getSimpleVT().SimpleTy, Custom); 862 setOperationAction(ISD::VECTOR_SHUFFLE, 863 VT.getSimpleVT().SimpleTy, Custom); 864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 865 VT.getSimpleVT().SimpleTy, Custom); 866 } 867 868 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 869 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 870 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 871 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 872 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 873 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 874 875 if (Subtarget->is64Bit()) { 876 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 877 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 878 } 879 880 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 881 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 882 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 883 EVT VT = SVT; 884 885 // Do not attempt to promote non-128-bit vectors 886 if (!VT.is128BitVector()) 887 continue; 888 889 setOperationAction(ISD::AND, SVT, Promote); 890 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 891 setOperationAction(ISD::OR, SVT, Promote); 892 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 893 setOperationAction(ISD::XOR, SVT, Promote); 894 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 895 setOperationAction(ISD::LOAD, SVT, Promote); 896 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 897 setOperationAction(ISD::SELECT, SVT, Promote); 898 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 899 } 900 901 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 902 903 // Custom lower v2i64 and v2f64 selects. 904 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 905 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 906 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 907 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 908 909 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 910 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 911 } 912 913 if (Subtarget->hasSSE41()) { 914 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 915 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 916 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 917 setOperationAction(ISD::FRINT, MVT::f32, Legal); 918 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 919 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 920 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 921 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 922 setOperationAction(ISD::FRINT, MVT::f64, Legal); 923 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 924 925 // FIXME: Do we need to handle scalar-to-vector here? 926 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 927 928 // Can turn SHL into an integer multiply. 929 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 930 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 931 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 932 933 // i8 and i16 vectors are custom , because the source register and source 934 // source memory operand types are not the same width. f32 vectors are 935 // custom since the immediate controlling the insert encodes additional 936 // information. 937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 938 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 939 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 941 942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 946 947 if (Subtarget->is64Bit()) { 948 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 949 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 950 } 951 } 952 953 if (Subtarget->hasSSE42()) 954 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 955 956 if (!UseSoftFloat && Subtarget->hasAVX()) { 957 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 958 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 959 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 960 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 961 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 962 963 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 964 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 965 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 966 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 967 968 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 969 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 970 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 971 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 972 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 973 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 974 975 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 976 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 977 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 978 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 979 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 980 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 981 982 // Custom lower build_vector, vector_shuffle, scalar_to_vector, 983 // insert_vector_elt extract_subvector and extract_vector_elt for 984 // 256-bit types. 985 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 986 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; 987 ++i) { 988 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 989 // Do not attempt to custom lower non-256-bit vectors 990 if (!isPowerOf2_32(MVT(VT).getVectorNumElements()) 991 || (MVT(VT).getSizeInBits() < 256)) 992 continue; 993 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 994 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 995 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 997 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 998 } 999 // Custom-lower insert_subvector and extract_subvector based on 1000 // the result type. 1001 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1002 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; 1003 ++i) { 1004 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 1005 // Do not attempt to custom lower non-256-bit vectors 1006 if (!isPowerOf2_32(MVT(VT).getVectorNumElements())) 1007 continue; 1008 1009 if (MVT(VT).getSizeInBits() == 128) { 1010 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1011 } 1012 else if (MVT(VT).getSizeInBits() == 256) { 1013 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1014 } 1015 } 1016 1017 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1018 // Don't promote loads because we need them for VPERM vector index versions. 1019 1020 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1021 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; 1022 VT++) { 1023 if (!isPowerOf2_32(MVT((MVT::SimpleValueType)VT).getVectorNumElements()) 1024 || (MVT((MVT::SimpleValueType)VT).getSizeInBits() < 256)) 1025 continue; 1026 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); 1027 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v4i64); 1028 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); 1029 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v4i64); 1030 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); 1031 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v4i64); 1032 //setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); 1033 //AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v4i64); 1034 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); 1035 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v4i64); 1036 } 1037 } 1038 1039 // We want to custom lower some of our intrinsics. 1040 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1041 1042 1043 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1044 // handle type legalization for these operations here. 1045 // 1046 // FIXME: We really should do custom legalization for addition and 1047 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1048 // than generic legalization for 64-bit multiplication-with-overflow, though. 1049 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1050 // Add/Sub/Mul with overflow operations are custom lowered. 1051 MVT VT = IntVTs[i]; 1052 setOperationAction(ISD::SADDO, VT, Custom); 1053 setOperationAction(ISD::UADDO, VT, Custom); 1054 setOperationAction(ISD::SSUBO, VT, Custom); 1055 setOperationAction(ISD::USUBO, VT, Custom); 1056 setOperationAction(ISD::SMULO, VT, Custom); 1057 setOperationAction(ISD::UMULO, VT, Custom); 1058 } 1059 1060 // There are no 8-bit 3-address imul/mul instructions 1061 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1062 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1063 1064 if (!Subtarget->is64Bit()) { 1065 // These libcalls are not available in 32-bit. 1066 setLibcallName(RTLIB::SHL_I128, 0); 1067 setLibcallName(RTLIB::SRL_I128, 0); 1068 setLibcallName(RTLIB::SRA_I128, 0); 1069 } 1070 1071 // We have target-specific dag combine patterns for the following nodes: 1072 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1073 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1074 setTargetDAGCombine(ISD::BUILD_VECTOR); 1075 setTargetDAGCombine(ISD::SELECT); 1076 setTargetDAGCombine(ISD::SHL); 1077 setTargetDAGCombine(ISD::SRA); 1078 setTargetDAGCombine(ISD::SRL); 1079 setTargetDAGCombine(ISD::OR); 1080 setTargetDAGCombine(ISD::AND); 1081 setTargetDAGCombine(ISD::ADD); 1082 setTargetDAGCombine(ISD::SUB); 1083 setTargetDAGCombine(ISD::STORE); 1084 setTargetDAGCombine(ISD::ZERO_EXTEND); 1085 if (Subtarget->is64Bit()) 1086 setTargetDAGCombine(ISD::MUL); 1087 1088 computeRegisterProperties(); 1089 1090 // On Darwin, -Os means optimize for size without hurting performance, 1091 // do not reduce the limit. 1092 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1093 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1094 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1095 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1096 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1097 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1098 setPrefLoopAlignment(16); 1099 benefitFromCodePlacementOpt = true; 1100} 1101 1102 1103MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1104 return MVT::i8; 1105} 1106 1107 1108/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1109/// the desired ByVal argument alignment. 1110static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1111 if (MaxAlign == 16) 1112 return; 1113 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1114 if (VTy->getBitWidth() == 128) 1115 MaxAlign = 16; 1116 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1117 unsigned EltAlign = 0; 1118 getMaxByValAlign(ATy->getElementType(), EltAlign); 1119 if (EltAlign > MaxAlign) 1120 MaxAlign = EltAlign; 1121 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1122 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1123 unsigned EltAlign = 0; 1124 getMaxByValAlign(STy->getElementType(i), EltAlign); 1125 if (EltAlign > MaxAlign) 1126 MaxAlign = EltAlign; 1127 if (MaxAlign == 16) 1128 break; 1129 } 1130 } 1131 return; 1132} 1133 1134/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1135/// function arguments in the caller parameter area. For X86, aggregates 1136/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1137/// are at 4-byte boundaries. 1138unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1139 if (Subtarget->is64Bit()) { 1140 // Max of 8 and alignment of type. 1141 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1142 if (TyAlign > 8) 1143 return TyAlign; 1144 return 8; 1145 } 1146 1147 unsigned Align = 4; 1148 if (Subtarget->hasXMM()) 1149 getMaxByValAlign(Ty, Align); 1150 return Align; 1151} 1152 1153/// getOptimalMemOpType - Returns the target specific optimal type for load 1154/// and store operations as a result of memset, memcpy, and memmove 1155/// lowering. If DstAlign is zero that means it's safe to destination 1156/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1157/// means there isn't a need to check it against alignment requirement, 1158/// probably because the source does not need to be loaded. If 1159/// 'NonScalarIntSafe' is true, that means it's safe to return a 1160/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1161/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1162/// constant so it does not need to be loaded. 1163/// It returns EVT::Other if the type should be determined using generic 1164/// target-independent logic. 1165EVT 1166X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1167 unsigned DstAlign, unsigned SrcAlign, 1168 bool NonScalarIntSafe, 1169 bool MemcpyStrSrc, 1170 MachineFunction &MF) const { 1171 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1172 // linux. This is because the stack realignment code can't handle certain 1173 // cases like PR2962. This should be removed when PR2962 is fixed. 1174 const Function *F = MF.getFunction(); 1175 if (NonScalarIntSafe && 1176 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1177 if (Size >= 16 && 1178 (Subtarget->isUnalignedMemAccessFast() || 1179 ((DstAlign == 0 || DstAlign >= 16) && 1180 (SrcAlign == 0 || SrcAlign >= 16))) && 1181 Subtarget->getStackAlignment() >= 16) { 1182 if (Subtarget->hasSSE2()) 1183 return MVT::v4i32; 1184 if (Subtarget->hasSSE1()) 1185 return MVT::v4f32; 1186 } else if (!MemcpyStrSrc && Size >= 8 && 1187 !Subtarget->is64Bit() && 1188 Subtarget->getStackAlignment() >= 8 && 1189 Subtarget->hasXMMInt()) { 1190 // Do not use f64 to lower memcpy if source is string constant. It's 1191 // better to use i32 to avoid the loads. 1192 return MVT::f64; 1193 } 1194 } 1195 if (Subtarget->is64Bit() && Size >= 8) 1196 return MVT::i64; 1197 return MVT::i32; 1198} 1199 1200/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1201/// current function. The returned value is a member of the 1202/// MachineJumpTableInfo::JTEntryKind enum. 1203unsigned X86TargetLowering::getJumpTableEncoding() const { 1204 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1205 // symbol. 1206 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1207 Subtarget->isPICStyleGOT()) 1208 return MachineJumpTableInfo::EK_Custom32; 1209 1210 // Otherwise, use the normal jump table encoding heuristics. 1211 return TargetLowering::getJumpTableEncoding(); 1212} 1213 1214const MCExpr * 1215X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1216 const MachineBasicBlock *MBB, 1217 unsigned uid,MCContext &Ctx) const{ 1218 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1219 Subtarget->isPICStyleGOT()); 1220 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1221 // entries. 1222 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1223 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1224} 1225 1226/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1227/// jumptable. 1228SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1229 SelectionDAG &DAG) const { 1230 if (!Subtarget->is64Bit()) 1231 // This doesn't have DebugLoc associated with it, but is not really the 1232 // same as a Register. 1233 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1234 return Table; 1235} 1236 1237/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1238/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1239/// MCExpr. 1240const MCExpr *X86TargetLowering:: 1241getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1242 MCContext &Ctx) const { 1243 // X86-64 uses RIP relative addressing based on the jump table label. 1244 if (Subtarget->isPICStyleRIPRel()) 1245 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1246 1247 // Otherwise, the reference is relative to the PIC base. 1248 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1249} 1250 1251/// getFunctionAlignment - Return the Log2 alignment of this function. 1252unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1253 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1254} 1255 1256// FIXME: Why this routine is here? Move to RegInfo! 1257std::pair<const TargetRegisterClass*, uint8_t> 1258X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1259 const TargetRegisterClass *RRC = 0; 1260 uint8_t Cost = 1; 1261 switch (VT.getSimpleVT().SimpleTy) { 1262 default: 1263 return TargetLowering::findRepresentativeClass(VT); 1264 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1265 RRC = (Subtarget->is64Bit() 1266 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1267 break; 1268 case MVT::x86mmx: 1269 RRC = X86::VR64RegisterClass; 1270 break; 1271 case MVT::f32: case MVT::f64: 1272 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1273 case MVT::v4f32: case MVT::v2f64: 1274 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1275 case MVT::v4f64: 1276 RRC = X86::VR128RegisterClass; 1277 break; 1278 } 1279 return std::make_pair(RRC, Cost); 1280} 1281 1282bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1283 unsigned &Offset) const { 1284 if (!Subtarget->isTargetLinux()) 1285 return false; 1286 1287 if (Subtarget->is64Bit()) { 1288 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1289 Offset = 0x28; 1290 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1291 AddressSpace = 256; 1292 else 1293 AddressSpace = 257; 1294 } else { 1295 // %gs:0x14 on i386 1296 Offset = 0x14; 1297 AddressSpace = 256; 1298 } 1299 return true; 1300} 1301 1302 1303//===----------------------------------------------------------------------===// 1304// Return Value Calling Convention Implementation 1305//===----------------------------------------------------------------------===// 1306 1307#include "X86GenCallingConv.inc" 1308 1309bool 1310X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1311 const SmallVectorImpl<ISD::OutputArg> &Outs, 1312 LLVMContext &Context) const { 1313 SmallVector<CCValAssign, 16> RVLocs; 1314 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1315 RVLocs, Context); 1316 return CCInfo.CheckReturn(Outs, RetCC_X86); 1317} 1318 1319SDValue 1320X86TargetLowering::LowerReturn(SDValue Chain, 1321 CallingConv::ID CallConv, bool isVarArg, 1322 const SmallVectorImpl<ISD::OutputArg> &Outs, 1323 const SmallVectorImpl<SDValue> &OutVals, 1324 DebugLoc dl, SelectionDAG &DAG) const { 1325 MachineFunction &MF = DAG.getMachineFunction(); 1326 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1327 1328 SmallVector<CCValAssign, 16> RVLocs; 1329 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1330 RVLocs, *DAG.getContext()); 1331 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1332 1333 // Add the regs to the liveout set for the function. 1334 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1335 for (unsigned i = 0; i != RVLocs.size(); ++i) 1336 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1337 MRI.addLiveOut(RVLocs[i].getLocReg()); 1338 1339 SDValue Flag; 1340 1341 SmallVector<SDValue, 6> RetOps; 1342 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1343 // Operand #1 = Bytes To Pop 1344 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1345 MVT::i16)); 1346 1347 // Copy the result values into the output registers. 1348 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1349 CCValAssign &VA = RVLocs[i]; 1350 assert(VA.isRegLoc() && "Can only return in registers!"); 1351 SDValue ValToCopy = OutVals[i]; 1352 EVT ValVT = ValToCopy.getValueType(); 1353 1354 // If this is x86-64, and we disabled SSE, we can't return FP values, 1355 // or SSE or MMX vectors. 1356 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1357 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1358 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1359 report_fatal_error("SSE register return with SSE disabled"); 1360 } 1361 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1362 // llvm-gcc has never done it right and no one has noticed, so this 1363 // should be OK for now. 1364 if (ValVT == MVT::f64 && 1365 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1366 report_fatal_error("SSE2 register return with SSE2 disabled"); 1367 1368 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1369 // the RET instruction and handled by the FP Stackifier. 1370 if (VA.getLocReg() == X86::ST0 || 1371 VA.getLocReg() == X86::ST1) { 1372 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1373 // change the value to the FP stack register class. 1374 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1375 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1376 RetOps.push_back(ValToCopy); 1377 // Don't emit a copytoreg. 1378 continue; 1379 } 1380 1381 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1382 // which is returned in RAX / RDX. 1383 if (Subtarget->is64Bit()) { 1384 if (ValVT == MVT::x86mmx) { 1385 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1386 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1387 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1388 ValToCopy); 1389 // If we don't have SSE2 available, convert to v4f32 so the generated 1390 // register is legal. 1391 if (!Subtarget->hasSSE2()) 1392 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1393 } 1394 } 1395 } 1396 1397 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1398 Flag = Chain.getValue(1); 1399 } 1400 1401 // The x86-64 ABI for returning structs by value requires that we copy 1402 // the sret argument into %rax for the return. We saved the argument into 1403 // a virtual register in the entry block, so now we copy the value out 1404 // and into %rax. 1405 if (Subtarget->is64Bit() && 1406 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1407 MachineFunction &MF = DAG.getMachineFunction(); 1408 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1409 unsigned Reg = FuncInfo->getSRetReturnReg(); 1410 assert(Reg && 1411 "SRetReturnReg should have been set in LowerFormalArguments()."); 1412 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1413 1414 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1415 Flag = Chain.getValue(1); 1416 1417 // RAX now acts like a return value. 1418 MRI.addLiveOut(X86::RAX); 1419 } 1420 1421 RetOps[0] = Chain; // Update chain. 1422 1423 // Add the flag if we have it. 1424 if (Flag.getNode()) 1425 RetOps.push_back(Flag); 1426 1427 return DAG.getNode(X86ISD::RET_FLAG, dl, 1428 MVT::Other, &RetOps[0], RetOps.size()); 1429} 1430 1431bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1432 if (N->getNumValues() != 1) 1433 return false; 1434 if (!N->hasNUsesOfValue(1, 0)) 1435 return false; 1436 1437 SDNode *Copy = *N->use_begin(); 1438 if (Copy->getOpcode() != ISD::CopyToReg && 1439 Copy->getOpcode() != ISD::FP_EXTEND) 1440 return false; 1441 1442 bool HasRet = false; 1443 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1444 UI != UE; ++UI) { 1445 if (UI->getOpcode() != X86ISD::RET_FLAG) 1446 return false; 1447 HasRet = true; 1448 } 1449 1450 return HasRet; 1451} 1452 1453EVT 1454X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1455 ISD::NodeType ExtendKind) const { 1456 MVT ReturnMVT; 1457 // TODO: Is this also valid on 32-bit? 1458 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1459 ReturnMVT = MVT::i8; 1460 else 1461 ReturnMVT = MVT::i32; 1462 1463 EVT MinVT = getRegisterType(Context, ReturnMVT); 1464 return VT.bitsLT(MinVT) ? MinVT : VT; 1465} 1466 1467/// LowerCallResult - Lower the result values of a call into the 1468/// appropriate copies out of appropriate physical registers. 1469/// 1470SDValue 1471X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1472 CallingConv::ID CallConv, bool isVarArg, 1473 const SmallVectorImpl<ISD::InputArg> &Ins, 1474 DebugLoc dl, SelectionDAG &DAG, 1475 SmallVectorImpl<SDValue> &InVals) const { 1476 1477 // Assign locations to each value returned by this call. 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 bool Is64Bit = Subtarget->is64Bit(); 1480 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1481 RVLocs, *DAG.getContext()); 1482 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1483 1484 // Copy all of the result registers out of their specified physreg. 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1486 CCValAssign &VA = RVLocs[i]; 1487 EVT CopyVT = VA.getValVT(); 1488 1489 // If this is x86-64, and we disabled SSE, we can't return FP values 1490 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1491 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1492 report_fatal_error("SSE register return with SSE disabled"); 1493 } 1494 1495 SDValue Val; 1496 1497 // If this is a call to a function that returns an fp value on the floating 1498 // point stack, we must guarantee the the value is popped from the stack, so 1499 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1500 // if the return value is not used. We use the FpGET_ST0 instructions 1501 // instead. 1502 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1503 // If we prefer to use the value in xmm registers, copy it out as f80 and 1504 // use a truncate to move it from fp stack reg to xmm reg. 1505 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1506 bool isST0 = VA.getLocReg() == X86::ST0; 1507 unsigned Opc = 0; 1508 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; 1509 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; 1510 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; 1511 SDValue Ops[] = { Chain, InFlag }; 1512 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue, 1513 Ops, 2), 1); 1514 Val = Chain.getValue(0); 1515 1516 // Round the f80 to the right size, which also moves it to the appropriate 1517 // xmm register. 1518 if (CopyVT != VA.getValVT()) 1519 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1520 // This truncation won't change the value. 1521 DAG.getIntPtrConstant(1)); 1522 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1523 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1524 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1525 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1526 MVT::v2i64, InFlag).getValue(1); 1527 Val = Chain.getValue(0); 1528 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1529 Val, DAG.getConstant(0, MVT::i64)); 1530 } else { 1531 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1532 MVT::i64, InFlag).getValue(1); 1533 Val = Chain.getValue(0); 1534 } 1535 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val); 1536 } else { 1537 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1538 CopyVT, InFlag).getValue(1); 1539 Val = Chain.getValue(0); 1540 } 1541 InFlag = Chain.getValue(2); 1542 InVals.push_back(Val); 1543 } 1544 1545 return Chain; 1546} 1547 1548 1549//===----------------------------------------------------------------------===// 1550// C & StdCall & Fast Calling Convention implementation 1551//===----------------------------------------------------------------------===// 1552// StdCall calling convention seems to be standard for many Windows' API 1553// routines and around. It differs from C calling convention just a little: 1554// callee should clean up the stack, not caller. Symbols should be also 1555// decorated in some fancy way :) It doesn't support any vector arguments. 1556// For info on fast calling convention see Fast Calling Convention (tail call) 1557// implementation LowerX86_32FastCCCallTo. 1558 1559/// CallIsStructReturn - Determines whether a call uses struct return 1560/// semantics. 1561static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1562 if (Outs.empty()) 1563 return false; 1564 1565 return Outs[0].Flags.isSRet(); 1566} 1567 1568/// ArgsAreStructReturn - Determines whether a function uses struct 1569/// return semantics. 1570static bool 1571ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1572 if (Ins.empty()) 1573 return false; 1574 1575 return Ins[0].Flags.isSRet(); 1576} 1577 1578/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1579/// by "Src" to address "Dst" with size and alignment information specified by 1580/// the specific parameter attribute. The copy will be passed as a byval 1581/// function parameter. 1582static SDValue 1583CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1584 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1585 DebugLoc dl) { 1586 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1587 1588 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1589 /*isVolatile*/false, /*AlwaysInline=*/true, 1590 MachinePointerInfo(), MachinePointerInfo()); 1591} 1592 1593/// IsTailCallConvention - Return true if the calling convention is one that 1594/// supports tail call optimization. 1595static bool IsTailCallConvention(CallingConv::ID CC) { 1596 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1597} 1598 1599bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1600 if (!CI->isTailCall()) 1601 return false; 1602 1603 CallSite CS(CI); 1604 CallingConv::ID CalleeCC = CS.getCallingConv(); 1605 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1606 return false; 1607 1608 return true; 1609} 1610 1611/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1612/// a tailcall target by changing its ABI. 1613static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1614 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1615} 1616 1617SDValue 1618X86TargetLowering::LowerMemArgument(SDValue Chain, 1619 CallingConv::ID CallConv, 1620 const SmallVectorImpl<ISD::InputArg> &Ins, 1621 DebugLoc dl, SelectionDAG &DAG, 1622 const CCValAssign &VA, 1623 MachineFrameInfo *MFI, 1624 unsigned i) const { 1625 // Create the nodes corresponding to a load from this parameter slot. 1626 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1627 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1628 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1629 EVT ValVT; 1630 1631 // If value is passed by pointer we have address passed instead of the value 1632 // itself. 1633 if (VA.getLocInfo() == CCValAssign::Indirect) 1634 ValVT = VA.getLocVT(); 1635 else 1636 ValVT = VA.getValVT(); 1637 1638 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1639 // changed with more analysis. 1640 // In case of tail call optimization mark all arguments mutable. Since they 1641 // could be overwritten by lowering of arguments in case of a tail call. 1642 if (Flags.isByVal()) { 1643 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1644 VA.getLocMemOffset(), isImmutable); 1645 return DAG.getFrameIndex(FI, getPointerTy()); 1646 } else { 1647 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1648 VA.getLocMemOffset(), isImmutable); 1649 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1650 return DAG.getLoad(ValVT, dl, Chain, FIN, 1651 MachinePointerInfo::getFixedStack(FI), 1652 false, false, 0); 1653 } 1654} 1655 1656SDValue 1657X86TargetLowering::LowerFormalArguments(SDValue Chain, 1658 CallingConv::ID CallConv, 1659 bool isVarArg, 1660 const SmallVectorImpl<ISD::InputArg> &Ins, 1661 DebugLoc dl, 1662 SelectionDAG &DAG, 1663 SmallVectorImpl<SDValue> &InVals) 1664 const { 1665 MachineFunction &MF = DAG.getMachineFunction(); 1666 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1667 1668 const Function* Fn = MF.getFunction(); 1669 if (Fn->hasExternalLinkage() && 1670 Subtarget->isTargetCygMing() && 1671 Fn->getName() == "main") 1672 FuncInfo->setForceFramePointer(true); 1673 1674 MachineFrameInfo *MFI = MF.getFrameInfo(); 1675 bool Is64Bit = Subtarget->is64Bit(); 1676 bool IsWin64 = Subtarget->isTargetWin64(); 1677 1678 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1679 "Var args not supported with calling convention fastcc or ghc"); 1680 1681 // Assign locations to all of the incoming arguments. 1682 SmallVector<CCValAssign, 16> ArgLocs; 1683 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1684 ArgLocs, *DAG.getContext()); 1685 1686 // Allocate shadow area for Win64 1687 if (IsWin64) { 1688 CCInfo.AllocateStack(32, 8); 1689 } 1690 1691 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1692 1693 unsigned LastVal = ~0U; 1694 SDValue ArgValue; 1695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1696 CCValAssign &VA = ArgLocs[i]; 1697 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1698 // places. 1699 assert(VA.getValNo() != LastVal && 1700 "Don't support value assigned to multiple locs yet"); 1701 LastVal = VA.getValNo(); 1702 1703 if (VA.isRegLoc()) { 1704 EVT RegVT = VA.getLocVT(); 1705 TargetRegisterClass *RC = NULL; 1706 if (RegVT == MVT::i32) 1707 RC = X86::GR32RegisterClass; 1708 else if (Is64Bit && RegVT == MVT::i64) 1709 RC = X86::GR64RegisterClass; 1710 else if (RegVT == MVT::f32) 1711 RC = X86::FR32RegisterClass; 1712 else if (RegVT == MVT::f64) 1713 RC = X86::FR64RegisterClass; 1714 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1715 RC = X86::VR256RegisterClass; 1716 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1717 RC = X86::VR128RegisterClass; 1718 else if (RegVT == MVT::x86mmx) 1719 RC = X86::VR64RegisterClass; 1720 else 1721 llvm_unreachable("Unknown argument type!"); 1722 1723 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1724 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1725 1726 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1727 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1728 // right size. 1729 if (VA.getLocInfo() == CCValAssign::SExt) 1730 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1731 DAG.getValueType(VA.getValVT())); 1732 else if (VA.getLocInfo() == CCValAssign::ZExt) 1733 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1734 DAG.getValueType(VA.getValVT())); 1735 else if (VA.getLocInfo() == CCValAssign::BCvt) 1736 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1737 1738 if (VA.isExtInLoc()) { 1739 // Handle MMX values passed in XMM regs. 1740 if (RegVT.isVector()) { 1741 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1742 ArgValue); 1743 } else 1744 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1745 } 1746 } else { 1747 assert(VA.isMemLoc()); 1748 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1749 } 1750 1751 // If value is passed via pointer - do a load. 1752 if (VA.getLocInfo() == CCValAssign::Indirect) 1753 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1754 MachinePointerInfo(), false, false, 0); 1755 1756 InVals.push_back(ArgValue); 1757 } 1758 1759 // The x86-64 ABI for returning structs by value requires that we copy 1760 // the sret argument into %rax for the return. Save the argument into 1761 // a virtual register so that we can access it from the return points. 1762 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1763 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1764 unsigned Reg = FuncInfo->getSRetReturnReg(); 1765 if (!Reg) { 1766 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1767 FuncInfo->setSRetReturnReg(Reg); 1768 } 1769 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1770 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1771 } 1772 1773 unsigned StackSize = CCInfo.getNextStackOffset(); 1774 // Align stack specially for tail calls. 1775 if (FuncIsMadeTailCallSafe(CallConv)) 1776 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1777 1778 // If the function takes variable number of arguments, make a frame index for 1779 // the start of the first vararg value... for expansion of llvm.va_start. 1780 if (isVarArg) { 1781 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1782 CallConv != CallingConv::X86_ThisCall)) { 1783 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1784 } 1785 if (Is64Bit) { 1786 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1787 1788 // FIXME: We should really autogenerate these arrays 1789 static const unsigned GPR64ArgRegsWin64[] = { 1790 X86::RCX, X86::RDX, X86::R8, X86::R9 1791 }; 1792 static const unsigned GPR64ArgRegs64Bit[] = { 1793 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1794 }; 1795 static const unsigned XMMArgRegs64Bit[] = { 1796 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1797 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1798 }; 1799 const unsigned *GPR64ArgRegs; 1800 unsigned NumXMMRegs = 0; 1801 1802 if (IsWin64) { 1803 // The XMM registers which might contain var arg parameters are shadowed 1804 // in their paired GPR. So we only need to save the GPR to their home 1805 // slots. 1806 TotalNumIntRegs = 4; 1807 GPR64ArgRegs = GPR64ArgRegsWin64; 1808 } else { 1809 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1810 GPR64ArgRegs = GPR64ArgRegs64Bit; 1811 1812 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1813 } 1814 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1815 TotalNumIntRegs); 1816 1817 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1818 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1819 "SSE register cannot be used when SSE is disabled!"); 1820 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1821 "SSE register cannot be used when SSE is disabled!"); 1822 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1823 // Kernel mode asks for SSE to be disabled, so don't push them 1824 // on the stack. 1825 TotalNumXMMRegs = 0; 1826 1827 if (IsWin64) { 1828 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1829 // Get to the caller-allocated home save location. Add 8 to account 1830 // for the return address. 1831 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1832 FuncInfo->setRegSaveFrameIndex( 1833 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1834 // Fixup to set vararg frame on shadow area (4 x i64). 1835 if (NumIntRegs < 4) 1836 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1837 } else { 1838 // For X86-64, if there are vararg parameters that are passed via 1839 // registers, then we must store them to their spots on the stack so they 1840 // may be loaded by deferencing the result of va_next. 1841 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1842 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1843 FuncInfo->setRegSaveFrameIndex( 1844 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1845 false)); 1846 } 1847 1848 // Store the integer parameter registers. 1849 SmallVector<SDValue, 8> MemOps; 1850 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1851 getPointerTy()); 1852 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1853 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1854 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1855 DAG.getIntPtrConstant(Offset)); 1856 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1857 X86::GR64RegisterClass); 1858 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1859 SDValue Store = 1860 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1861 MachinePointerInfo::getFixedStack( 1862 FuncInfo->getRegSaveFrameIndex(), Offset), 1863 false, false, 0); 1864 MemOps.push_back(Store); 1865 Offset += 8; 1866 } 1867 1868 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1869 // Now store the XMM (fp + vector) parameter registers. 1870 SmallVector<SDValue, 11> SaveXMMOps; 1871 SaveXMMOps.push_back(Chain); 1872 1873 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1874 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1875 SaveXMMOps.push_back(ALVal); 1876 1877 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1878 FuncInfo->getRegSaveFrameIndex())); 1879 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1880 FuncInfo->getVarArgsFPOffset())); 1881 1882 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1883 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1884 X86::VR128RegisterClass); 1885 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1886 SaveXMMOps.push_back(Val); 1887 } 1888 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1889 MVT::Other, 1890 &SaveXMMOps[0], SaveXMMOps.size())); 1891 } 1892 1893 if (!MemOps.empty()) 1894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1895 &MemOps[0], MemOps.size()); 1896 } 1897 } 1898 1899 // Some CCs need callee pop. 1900 if (Subtarget->IsCalleePop(isVarArg, CallConv)) { 1901 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1902 } else { 1903 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1904 // If this is an sret function, the return should pop the hidden pointer. 1905 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1906 FuncInfo->setBytesToPopOnReturn(4); 1907 } 1908 1909 if (!Is64Bit) { 1910 // RegSaveFrameIndex is X86-64 only. 1911 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1912 if (CallConv == CallingConv::X86_FastCall || 1913 CallConv == CallingConv::X86_ThisCall) 1914 // fastcc functions can't have varargs. 1915 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1916 } 1917 1918 return Chain; 1919} 1920 1921SDValue 1922X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1923 SDValue StackPtr, SDValue Arg, 1924 DebugLoc dl, SelectionDAG &DAG, 1925 const CCValAssign &VA, 1926 ISD::ArgFlagsTy Flags) const { 1927 unsigned LocMemOffset = VA.getLocMemOffset(); 1928 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1929 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1930 if (Flags.isByVal()) 1931 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1932 1933 return DAG.getStore(Chain, dl, Arg, PtrOff, 1934 MachinePointerInfo::getStack(LocMemOffset), 1935 false, false, 0); 1936} 1937 1938/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1939/// optimization is performed and it is required. 1940SDValue 1941X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1942 SDValue &OutRetAddr, SDValue Chain, 1943 bool IsTailCall, bool Is64Bit, 1944 int FPDiff, DebugLoc dl) const { 1945 // Adjust the Return address stack slot. 1946 EVT VT = getPointerTy(); 1947 OutRetAddr = getReturnAddressFrameIndex(DAG); 1948 1949 // Load the "old" Return address. 1950 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1951 false, false, 0); 1952 return SDValue(OutRetAddr.getNode(), 1); 1953} 1954 1955/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1956/// optimization is performed and it is required (FPDiff!=0). 1957static SDValue 1958EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1959 SDValue Chain, SDValue RetAddrFrIdx, 1960 bool Is64Bit, int FPDiff, DebugLoc dl) { 1961 // Store the return address to the appropriate stack slot. 1962 if (!FPDiff) return Chain; 1963 // Calculate the new stack slot for the return address. 1964 int SlotSize = Is64Bit ? 8 : 4; 1965 int NewReturnAddrFI = 1966 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1967 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1968 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1969 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1970 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 1971 false, false, 0); 1972 return Chain; 1973} 1974 1975SDValue 1976X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1977 CallingConv::ID CallConv, bool isVarArg, 1978 bool &isTailCall, 1979 const SmallVectorImpl<ISD::OutputArg> &Outs, 1980 const SmallVectorImpl<SDValue> &OutVals, 1981 const SmallVectorImpl<ISD::InputArg> &Ins, 1982 DebugLoc dl, SelectionDAG &DAG, 1983 SmallVectorImpl<SDValue> &InVals) const { 1984 MachineFunction &MF = DAG.getMachineFunction(); 1985 bool Is64Bit = Subtarget->is64Bit(); 1986 bool IsWin64 = Subtarget->isTargetWin64(); 1987 bool IsStructRet = CallIsStructReturn(Outs); 1988 bool IsSibcall = false; 1989 1990 if (isTailCall) { 1991 // Check if it's really possible to do a tail call. 1992 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1993 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1994 Outs, OutVals, Ins, DAG); 1995 1996 // Sibcalls are automatically detected tailcalls which do not require 1997 // ABI changes. 1998 if (!GuaranteedTailCallOpt && isTailCall) 1999 IsSibcall = true; 2000 2001 if (isTailCall) 2002 ++NumTailCalls; 2003 } 2004 2005 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2006 "Var args not supported with calling convention fastcc or ghc"); 2007 2008 // Analyze operands of the call, assigning locations to each operand. 2009 SmallVector<CCValAssign, 16> ArgLocs; 2010 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2011 ArgLocs, *DAG.getContext()); 2012 2013 // Allocate shadow area for Win64 2014 if (IsWin64) { 2015 CCInfo.AllocateStack(32, 8); 2016 } 2017 2018 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2019 2020 // Get a count of how many bytes are to be pushed on the stack. 2021 unsigned NumBytes = CCInfo.getNextStackOffset(); 2022 if (IsSibcall) 2023 // This is a sibcall. The memory operands are available in caller's 2024 // own caller's stack. 2025 NumBytes = 0; 2026 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2027 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2028 2029 int FPDiff = 0; 2030 if (isTailCall && !IsSibcall) { 2031 // Lower arguments at fp - stackoffset + fpdiff. 2032 unsigned NumBytesCallerPushed = 2033 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2034 FPDiff = NumBytesCallerPushed - NumBytes; 2035 2036 // Set the delta of movement of the returnaddr stackslot. 2037 // But only set if delta is greater than previous delta. 2038 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2039 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2040 } 2041 2042 if (!IsSibcall) 2043 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2044 2045 SDValue RetAddrFrIdx; 2046 // Load return adress for tail calls. 2047 if (isTailCall && FPDiff) 2048 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2049 Is64Bit, FPDiff, dl); 2050 2051 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2052 SmallVector<SDValue, 8> MemOpChains; 2053 SDValue StackPtr; 2054 2055 // Walk the register/memloc assignments, inserting copies/loads. In the case 2056 // of tail call optimization arguments are handle later. 2057 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2058 CCValAssign &VA = ArgLocs[i]; 2059 EVT RegVT = VA.getLocVT(); 2060 SDValue Arg = OutVals[i]; 2061 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2062 bool isByVal = Flags.isByVal(); 2063 2064 // Promote the value if needed. 2065 switch (VA.getLocInfo()) { 2066 default: llvm_unreachable("Unknown loc info!"); 2067 case CCValAssign::Full: break; 2068 case CCValAssign::SExt: 2069 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2070 break; 2071 case CCValAssign::ZExt: 2072 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2073 break; 2074 case CCValAssign::AExt: 2075 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2076 // Special case: passing MMX values in XMM registers. 2077 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2078 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2079 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2080 } else 2081 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2082 break; 2083 case CCValAssign::BCvt: 2084 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2085 break; 2086 case CCValAssign::Indirect: { 2087 // Store the argument. 2088 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2089 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2090 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2091 MachinePointerInfo::getFixedStack(FI), 2092 false, false, 0); 2093 Arg = SpillSlot; 2094 break; 2095 } 2096 } 2097 2098 if (VA.isRegLoc()) { 2099 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2100 if (isVarArg && IsWin64) { 2101 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2102 // shadow reg if callee is a varargs function. 2103 unsigned ShadowReg = 0; 2104 switch (VA.getLocReg()) { 2105 case X86::XMM0: ShadowReg = X86::RCX; break; 2106 case X86::XMM1: ShadowReg = X86::RDX; break; 2107 case X86::XMM2: ShadowReg = X86::R8; break; 2108 case X86::XMM3: ShadowReg = X86::R9; break; 2109 } 2110 if (ShadowReg) 2111 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2112 } 2113 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2114 assert(VA.isMemLoc()); 2115 if (StackPtr.getNode() == 0) 2116 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2117 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2118 dl, DAG, VA, Flags)); 2119 } 2120 } 2121 2122 if (!MemOpChains.empty()) 2123 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2124 &MemOpChains[0], MemOpChains.size()); 2125 2126 // Build a sequence of copy-to-reg nodes chained together with token chain 2127 // and flag operands which copy the outgoing args into registers. 2128 SDValue InFlag; 2129 // Tail call byval lowering might overwrite argument registers so in case of 2130 // tail call optimization the copies to registers are lowered later. 2131 if (!isTailCall) 2132 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2133 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2134 RegsToPass[i].second, InFlag); 2135 InFlag = Chain.getValue(1); 2136 } 2137 2138 if (Subtarget->isPICStyleGOT()) { 2139 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2140 // GOT pointer. 2141 if (!isTailCall) { 2142 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2143 DAG.getNode(X86ISD::GlobalBaseReg, 2144 DebugLoc(), getPointerTy()), 2145 InFlag); 2146 InFlag = Chain.getValue(1); 2147 } else { 2148 // If we are tail calling and generating PIC/GOT style code load the 2149 // address of the callee into ECX. The value in ecx is used as target of 2150 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2151 // for tail calls on PIC/GOT architectures. Normally we would just put the 2152 // address of GOT into ebx and then call target@PLT. But for tail calls 2153 // ebx would be restored (since ebx is callee saved) before jumping to the 2154 // target@PLT. 2155 2156 // Note: The actual moving to ECX is done further down. 2157 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2158 if (G && !G->getGlobal()->hasHiddenVisibility() && 2159 !G->getGlobal()->hasProtectedVisibility()) 2160 Callee = LowerGlobalAddress(Callee, DAG); 2161 else if (isa<ExternalSymbolSDNode>(Callee)) 2162 Callee = LowerExternalSymbol(Callee, DAG); 2163 } 2164 } 2165 2166 if (Is64Bit && isVarArg && !IsWin64) { 2167 // From AMD64 ABI document: 2168 // For calls that may call functions that use varargs or stdargs 2169 // (prototype-less calls or calls to functions containing ellipsis (...) in 2170 // the declaration) %al is used as hidden argument to specify the number 2171 // of SSE registers used. The contents of %al do not need to match exactly 2172 // the number of registers, but must be an ubound on the number of SSE 2173 // registers used and is in the range 0 - 8 inclusive. 2174 2175 // Count the number of XMM registers allocated. 2176 static const unsigned XMMArgRegs[] = { 2177 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2178 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2179 }; 2180 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2181 assert((Subtarget->hasXMM() || !NumXMMRegs) 2182 && "SSE registers cannot be used when SSE is disabled"); 2183 2184 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2185 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2186 InFlag = Chain.getValue(1); 2187 } 2188 2189 2190 // For tail calls lower the arguments to the 'real' stack slot. 2191 if (isTailCall) { 2192 // Force all the incoming stack arguments to be loaded from the stack 2193 // before any new outgoing arguments are stored to the stack, because the 2194 // outgoing stack slots may alias the incoming argument stack slots, and 2195 // the alias isn't otherwise explicit. This is slightly more conservative 2196 // than necessary, because it means that each store effectively depends 2197 // on every argument instead of just those arguments it would clobber. 2198 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2199 2200 SmallVector<SDValue, 8> MemOpChains2; 2201 SDValue FIN; 2202 int FI = 0; 2203 // Do not flag preceeding copytoreg stuff together with the following stuff. 2204 InFlag = SDValue(); 2205 if (GuaranteedTailCallOpt) { 2206 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2207 CCValAssign &VA = ArgLocs[i]; 2208 if (VA.isRegLoc()) 2209 continue; 2210 assert(VA.isMemLoc()); 2211 SDValue Arg = OutVals[i]; 2212 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2213 // Create frame index. 2214 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2215 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2216 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2217 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2218 2219 if (Flags.isByVal()) { 2220 // Copy relative to framepointer. 2221 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2222 if (StackPtr.getNode() == 0) 2223 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2224 getPointerTy()); 2225 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2226 2227 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2228 ArgChain, 2229 Flags, DAG, dl)); 2230 } else { 2231 // Store relative to framepointer. 2232 MemOpChains2.push_back( 2233 DAG.getStore(ArgChain, dl, Arg, FIN, 2234 MachinePointerInfo::getFixedStack(FI), 2235 false, false, 0)); 2236 } 2237 } 2238 } 2239 2240 if (!MemOpChains2.empty()) 2241 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2242 &MemOpChains2[0], MemOpChains2.size()); 2243 2244 // Copy arguments to their registers. 2245 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2246 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2247 RegsToPass[i].second, InFlag); 2248 InFlag = Chain.getValue(1); 2249 } 2250 InFlag =SDValue(); 2251 2252 // Store the return address to the appropriate stack slot. 2253 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2254 FPDiff, dl); 2255 } 2256 2257 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2258 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2259 // In the 64-bit large code model, we have to make all calls 2260 // through a register, since the call instruction's 32-bit 2261 // pc-relative offset may not be large enough to hold the whole 2262 // address. 2263 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2264 // If the callee is a GlobalAddress node (quite common, every direct call 2265 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2266 // it. 2267 2268 // We should use extra load for direct calls to dllimported functions in 2269 // non-JIT mode. 2270 const GlobalValue *GV = G->getGlobal(); 2271 if (!GV->hasDLLImportLinkage()) { 2272 unsigned char OpFlags = 0; 2273 2274 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2275 // external symbols most go through the PLT in PIC mode. If the symbol 2276 // has hidden or protected visibility, or if it is static or local, then 2277 // we don't need to use the PLT - we can directly call it. 2278 if (Subtarget->isTargetELF() && 2279 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2280 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2281 OpFlags = X86II::MO_PLT; 2282 } else if (Subtarget->isPICStyleStubAny() && 2283 (GV->isDeclaration() || GV->isWeakForLinker()) && 2284 Subtarget->getDarwinVers() < 9) { 2285 // PC-relative references to external symbols should go through $stub, 2286 // unless we're building with the leopard linker or later, which 2287 // automatically synthesizes these stubs. 2288 OpFlags = X86II::MO_DARWIN_STUB; 2289 } 2290 2291 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2292 G->getOffset(), OpFlags); 2293 } 2294 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2295 unsigned char OpFlags = 0; 2296 2297 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2298 // external symbols should go through the PLT. 2299 if (Subtarget->isTargetELF() && 2300 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2301 OpFlags = X86II::MO_PLT; 2302 } else if (Subtarget->isPICStyleStubAny() && 2303 Subtarget->getDarwinVers() < 9) { 2304 // PC-relative references to external symbols should go through $stub, 2305 // unless we're building with the leopard linker or later, which 2306 // automatically synthesizes these stubs. 2307 OpFlags = X86II::MO_DARWIN_STUB; 2308 } 2309 2310 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2311 OpFlags); 2312 } 2313 2314 // Returns a chain & a flag for retval copy to use. 2315 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2316 SmallVector<SDValue, 8> Ops; 2317 2318 if (!IsSibcall && isTailCall) { 2319 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2320 DAG.getIntPtrConstant(0, true), InFlag); 2321 InFlag = Chain.getValue(1); 2322 } 2323 2324 Ops.push_back(Chain); 2325 Ops.push_back(Callee); 2326 2327 if (isTailCall) 2328 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2329 2330 // Add argument registers to the end of the list so that they are known live 2331 // into the call. 2332 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2333 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2334 RegsToPass[i].second.getValueType())); 2335 2336 // Add an implicit use GOT pointer in EBX. 2337 if (!isTailCall && Subtarget->isPICStyleGOT()) 2338 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2339 2340 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2341 if (Is64Bit && isVarArg && !IsWin64) 2342 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2343 2344 if (InFlag.getNode()) 2345 Ops.push_back(InFlag); 2346 2347 if (isTailCall) { 2348 // We used to do: 2349 //// If this is the first return lowered for this function, add the regs 2350 //// to the liveout set for the function. 2351 // This isn't right, although it's probably harmless on x86; liveouts 2352 // should be computed from returns not tail calls. Consider a void 2353 // function making a tail call to a function returning int. 2354 return DAG.getNode(X86ISD::TC_RETURN, dl, 2355 NodeTys, &Ops[0], Ops.size()); 2356 } 2357 2358 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2359 InFlag = Chain.getValue(1); 2360 2361 // Create the CALLSEQ_END node. 2362 unsigned NumBytesForCalleeToPush; 2363 if (Subtarget->IsCalleePop(isVarArg, CallConv)) 2364 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2365 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2366 // If this is a call to a struct-return function, the callee 2367 // pops the hidden struct pointer, so we have to push it back. 2368 // This is common for Darwin/X86, Linux & Mingw32 targets. 2369 NumBytesForCalleeToPush = 4; 2370 else 2371 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2372 2373 // Returns a flag for retval copy to use. 2374 if (!IsSibcall) { 2375 Chain = DAG.getCALLSEQ_END(Chain, 2376 DAG.getIntPtrConstant(NumBytes, true), 2377 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2378 true), 2379 InFlag); 2380 InFlag = Chain.getValue(1); 2381 } 2382 2383 // Handle result values, copying them out of physregs into vregs that we 2384 // return. 2385 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2386 Ins, dl, DAG, InVals); 2387} 2388 2389 2390//===----------------------------------------------------------------------===// 2391// Fast Calling Convention (tail call) implementation 2392//===----------------------------------------------------------------------===// 2393 2394// Like std call, callee cleans arguments, convention except that ECX is 2395// reserved for storing the tail called function address. Only 2 registers are 2396// free for argument passing (inreg). Tail call optimization is performed 2397// provided: 2398// * tailcallopt is enabled 2399// * caller/callee are fastcc 2400// On X86_64 architecture with GOT-style position independent code only local 2401// (within module) calls are supported at the moment. 2402// To keep the stack aligned according to platform abi the function 2403// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2404// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2405// If a tail called function callee has more arguments than the caller the 2406// caller needs to make sure that there is room to move the RETADDR to. This is 2407// achieved by reserving an area the size of the argument delta right after the 2408// original REtADDR, but before the saved framepointer or the spilled registers 2409// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2410// stack layout: 2411// arg1 2412// arg2 2413// RETADDR 2414// [ new RETADDR 2415// move area ] 2416// (possible EBP) 2417// ESI 2418// EDI 2419// local1 .. 2420 2421/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2422/// for a 16 byte align requirement. 2423unsigned 2424X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2425 SelectionDAG& DAG) const { 2426 MachineFunction &MF = DAG.getMachineFunction(); 2427 const TargetMachine &TM = MF.getTarget(); 2428 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2429 unsigned StackAlignment = TFI.getStackAlignment(); 2430 uint64_t AlignMask = StackAlignment - 1; 2431 int64_t Offset = StackSize; 2432 uint64_t SlotSize = TD->getPointerSize(); 2433 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2434 // Number smaller than 12 so just add the difference. 2435 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2436 } else { 2437 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2438 Offset = ((~AlignMask) & Offset) + StackAlignment + 2439 (StackAlignment-SlotSize); 2440 } 2441 return Offset; 2442} 2443 2444/// MatchingStackOffset - Return true if the given stack call argument is 2445/// already available in the same position (relatively) of the caller's 2446/// incoming argument stack. 2447static 2448bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2449 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2450 const X86InstrInfo *TII) { 2451 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2452 int FI = INT_MAX; 2453 if (Arg.getOpcode() == ISD::CopyFromReg) { 2454 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2455 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2456 return false; 2457 MachineInstr *Def = MRI->getVRegDef(VR); 2458 if (!Def) 2459 return false; 2460 if (!Flags.isByVal()) { 2461 if (!TII->isLoadFromStackSlot(Def, FI)) 2462 return false; 2463 } else { 2464 unsigned Opcode = Def->getOpcode(); 2465 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2466 Def->getOperand(1).isFI()) { 2467 FI = Def->getOperand(1).getIndex(); 2468 Bytes = Flags.getByValSize(); 2469 } else 2470 return false; 2471 } 2472 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2473 if (Flags.isByVal()) 2474 // ByVal argument is passed in as a pointer but it's now being 2475 // dereferenced. e.g. 2476 // define @foo(%struct.X* %A) { 2477 // tail call @bar(%struct.X* byval %A) 2478 // } 2479 return false; 2480 SDValue Ptr = Ld->getBasePtr(); 2481 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2482 if (!FINode) 2483 return false; 2484 FI = FINode->getIndex(); 2485 } else 2486 return false; 2487 2488 assert(FI != INT_MAX); 2489 if (!MFI->isFixedObjectIndex(FI)) 2490 return false; 2491 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2492} 2493 2494/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2495/// for tail call optimization. Targets which want to do tail call 2496/// optimization should implement this function. 2497bool 2498X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2499 CallingConv::ID CalleeCC, 2500 bool isVarArg, 2501 bool isCalleeStructRet, 2502 bool isCallerStructRet, 2503 const SmallVectorImpl<ISD::OutputArg> &Outs, 2504 const SmallVectorImpl<SDValue> &OutVals, 2505 const SmallVectorImpl<ISD::InputArg> &Ins, 2506 SelectionDAG& DAG) const { 2507 if (!IsTailCallConvention(CalleeCC) && 2508 CalleeCC != CallingConv::C) 2509 return false; 2510 2511 // If -tailcallopt is specified, make fastcc functions tail-callable. 2512 const MachineFunction &MF = DAG.getMachineFunction(); 2513 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2514 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2515 bool CCMatch = CallerCC == CalleeCC; 2516 2517 if (GuaranteedTailCallOpt) { 2518 if (IsTailCallConvention(CalleeCC) && CCMatch) 2519 return true; 2520 return false; 2521 } 2522 2523 // Look for obvious safe cases to perform tail call optimization that do not 2524 // require ABI changes. This is what gcc calls sibcall. 2525 2526 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2527 // emit a special epilogue. 2528 if (RegInfo->needsStackRealignment(MF)) 2529 return false; 2530 2531 // Do not sibcall optimize vararg calls unless the call site is not passing 2532 // any arguments. 2533 if (isVarArg && !Outs.empty()) 2534 return false; 2535 2536 // Also avoid sibcall optimization if either caller or callee uses struct 2537 // return semantics. 2538 if (isCalleeStructRet || isCallerStructRet) 2539 return false; 2540 2541 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2542 // Therefore if it's not used by the call it is not safe to optimize this into 2543 // a sibcall. 2544 bool Unused = false; 2545 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2546 if (!Ins[i].Used) { 2547 Unused = true; 2548 break; 2549 } 2550 } 2551 if (Unused) { 2552 SmallVector<CCValAssign, 16> RVLocs; 2553 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2554 RVLocs, *DAG.getContext()); 2555 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2556 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2557 CCValAssign &VA = RVLocs[i]; 2558 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2559 return false; 2560 } 2561 } 2562 2563 // If the calling conventions do not match, then we'd better make sure the 2564 // results are returned in the same way as what the caller expects. 2565 if (!CCMatch) { 2566 SmallVector<CCValAssign, 16> RVLocs1; 2567 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 2568 RVLocs1, *DAG.getContext()); 2569 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2570 2571 SmallVector<CCValAssign, 16> RVLocs2; 2572 CCState CCInfo2(CallerCC, false, getTargetMachine(), 2573 RVLocs2, *DAG.getContext()); 2574 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2575 2576 if (RVLocs1.size() != RVLocs2.size()) 2577 return false; 2578 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2579 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2580 return false; 2581 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2582 return false; 2583 if (RVLocs1[i].isRegLoc()) { 2584 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2585 return false; 2586 } else { 2587 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2588 return false; 2589 } 2590 } 2591 } 2592 2593 // If the callee takes no arguments then go on to check the results of the 2594 // call. 2595 if (!Outs.empty()) { 2596 // Check if stack adjustment is needed. For now, do not do this if any 2597 // argument is passed on the stack. 2598 SmallVector<CCValAssign, 16> ArgLocs; 2599 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2600 ArgLocs, *DAG.getContext()); 2601 2602 // Allocate shadow area for Win64 2603 if (Subtarget->isTargetWin64()) { 2604 CCInfo.AllocateStack(32, 8); 2605 } 2606 2607 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2608 if (CCInfo.getNextStackOffset()) { 2609 MachineFunction &MF = DAG.getMachineFunction(); 2610 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2611 return false; 2612 2613 // Check if the arguments are already laid out in the right way as 2614 // the caller's fixed stack objects. 2615 MachineFrameInfo *MFI = MF.getFrameInfo(); 2616 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2617 const X86InstrInfo *TII = 2618 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2620 CCValAssign &VA = ArgLocs[i]; 2621 SDValue Arg = OutVals[i]; 2622 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2623 if (VA.getLocInfo() == CCValAssign::Indirect) 2624 return false; 2625 if (!VA.isRegLoc()) { 2626 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2627 MFI, MRI, TII)) 2628 return false; 2629 } 2630 } 2631 } 2632 2633 // If the tailcall address may be in a register, then make sure it's 2634 // possible to register allocate for it. In 32-bit, the call address can 2635 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2636 // callee-saved registers are restored. These happen to be the same 2637 // registers used to pass 'inreg' arguments so watch out for those. 2638 if (!Subtarget->is64Bit() && 2639 !isa<GlobalAddressSDNode>(Callee) && 2640 !isa<ExternalSymbolSDNode>(Callee)) { 2641 unsigned NumInRegs = 0; 2642 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2643 CCValAssign &VA = ArgLocs[i]; 2644 if (!VA.isRegLoc()) 2645 continue; 2646 unsigned Reg = VA.getLocReg(); 2647 switch (Reg) { 2648 default: break; 2649 case X86::EAX: case X86::EDX: case X86::ECX: 2650 if (++NumInRegs == 3) 2651 return false; 2652 break; 2653 } 2654 } 2655 } 2656 } 2657 2658 // An stdcall caller is expected to clean up its arguments; the callee 2659 // isn't going to do that. 2660 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2661 return false; 2662 2663 return true; 2664} 2665 2666FastISel * 2667X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2668 return X86::createFastISel(funcInfo); 2669} 2670 2671 2672//===----------------------------------------------------------------------===// 2673// Other Lowering Hooks 2674//===----------------------------------------------------------------------===// 2675 2676static bool MayFoldLoad(SDValue Op) { 2677 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2678} 2679 2680static bool MayFoldIntoStore(SDValue Op) { 2681 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2682} 2683 2684static bool isTargetShuffle(unsigned Opcode) { 2685 switch(Opcode) { 2686 default: return false; 2687 case X86ISD::PSHUFD: 2688 case X86ISD::PSHUFHW: 2689 case X86ISD::PSHUFLW: 2690 case X86ISD::SHUFPD: 2691 case X86ISD::PALIGN: 2692 case X86ISD::SHUFPS: 2693 case X86ISD::MOVLHPS: 2694 case X86ISD::MOVLHPD: 2695 case X86ISD::MOVHLPS: 2696 case X86ISD::MOVLPS: 2697 case X86ISD::MOVLPD: 2698 case X86ISD::MOVSHDUP: 2699 case X86ISD::MOVSLDUP: 2700 case X86ISD::MOVDDUP: 2701 case X86ISD::MOVSS: 2702 case X86ISD::MOVSD: 2703 case X86ISD::UNPCKLPS: 2704 case X86ISD::UNPCKLPD: 2705 case X86ISD::VUNPCKLPS: 2706 case X86ISD::VUNPCKLPD: 2707 case X86ISD::VUNPCKLPSY: 2708 case X86ISD::VUNPCKLPDY: 2709 case X86ISD::PUNPCKLWD: 2710 case X86ISD::PUNPCKLBW: 2711 case X86ISD::PUNPCKLDQ: 2712 case X86ISD::PUNPCKLQDQ: 2713 case X86ISD::UNPCKHPS: 2714 case X86ISD::UNPCKHPD: 2715 case X86ISD::PUNPCKHWD: 2716 case X86ISD::PUNPCKHBW: 2717 case X86ISD::PUNPCKHDQ: 2718 case X86ISD::PUNPCKHQDQ: 2719 return true; 2720 } 2721 return false; 2722} 2723 2724static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2725 SDValue V1, SelectionDAG &DAG) { 2726 switch(Opc) { 2727 default: llvm_unreachable("Unknown x86 shuffle node"); 2728 case X86ISD::MOVSHDUP: 2729 case X86ISD::MOVSLDUP: 2730 case X86ISD::MOVDDUP: 2731 return DAG.getNode(Opc, dl, VT, V1); 2732 } 2733 2734 return SDValue(); 2735} 2736 2737static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2738 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2739 switch(Opc) { 2740 default: llvm_unreachable("Unknown x86 shuffle node"); 2741 case X86ISD::PSHUFD: 2742 case X86ISD::PSHUFHW: 2743 case X86ISD::PSHUFLW: 2744 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2745 } 2746 2747 return SDValue(); 2748} 2749 2750static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2751 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2752 switch(Opc) { 2753 default: llvm_unreachable("Unknown x86 shuffle node"); 2754 case X86ISD::PALIGN: 2755 case X86ISD::SHUFPD: 2756 case X86ISD::SHUFPS: 2757 return DAG.getNode(Opc, dl, VT, V1, V2, 2758 DAG.getConstant(TargetMask, MVT::i8)); 2759 } 2760 return SDValue(); 2761} 2762 2763static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2764 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2765 switch(Opc) { 2766 default: llvm_unreachable("Unknown x86 shuffle node"); 2767 case X86ISD::MOVLHPS: 2768 case X86ISD::MOVLHPD: 2769 case X86ISD::MOVHLPS: 2770 case X86ISD::MOVLPS: 2771 case X86ISD::MOVLPD: 2772 case X86ISD::MOVSS: 2773 case X86ISD::MOVSD: 2774 case X86ISD::UNPCKLPS: 2775 case X86ISD::UNPCKLPD: 2776 case X86ISD::VUNPCKLPS: 2777 case X86ISD::VUNPCKLPD: 2778 case X86ISD::VUNPCKLPSY: 2779 case X86ISD::VUNPCKLPDY: 2780 case X86ISD::PUNPCKLWD: 2781 case X86ISD::PUNPCKLBW: 2782 case X86ISD::PUNPCKLDQ: 2783 case X86ISD::PUNPCKLQDQ: 2784 case X86ISD::UNPCKHPS: 2785 case X86ISD::UNPCKHPD: 2786 case X86ISD::PUNPCKHWD: 2787 case X86ISD::PUNPCKHBW: 2788 case X86ISD::PUNPCKHDQ: 2789 case X86ISD::PUNPCKHQDQ: 2790 return DAG.getNode(Opc, dl, VT, V1, V2); 2791 } 2792 return SDValue(); 2793} 2794 2795SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2796 MachineFunction &MF = DAG.getMachineFunction(); 2797 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2798 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2799 2800 if (ReturnAddrIndex == 0) { 2801 // Set up a frame object for the return address. 2802 uint64_t SlotSize = TD->getPointerSize(); 2803 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2804 false); 2805 FuncInfo->setRAIndex(ReturnAddrIndex); 2806 } 2807 2808 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2809} 2810 2811 2812bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2813 bool hasSymbolicDisplacement) { 2814 // Offset should fit into 32 bit immediate field. 2815 if (!isInt<32>(Offset)) 2816 return false; 2817 2818 // If we don't have a symbolic displacement - we don't have any extra 2819 // restrictions. 2820 if (!hasSymbolicDisplacement) 2821 return true; 2822 2823 // FIXME: Some tweaks might be needed for medium code model. 2824 if (M != CodeModel::Small && M != CodeModel::Kernel) 2825 return false; 2826 2827 // For small code model we assume that latest object is 16MB before end of 31 2828 // bits boundary. We may also accept pretty large negative constants knowing 2829 // that all objects are in the positive half of address space. 2830 if (M == CodeModel::Small && Offset < 16*1024*1024) 2831 return true; 2832 2833 // For kernel code model we know that all object resist in the negative half 2834 // of 32bits address space. We may not accept negative offsets, since they may 2835 // be just off and we may accept pretty large positive ones. 2836 if (M == CodeModel::Kernel && Offset > 0) 2837 return true; 2838 2839 return false; 2840} 2841 2842/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2843/// specific condition code, returning the condition code and the LHS/RHS of the 2844/// comparison to make. 2845static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2846 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2847 if (!isFP) { 2848 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2849 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2850 // X > -1 -> X == 0, jump !sign. 2851 RHS = DAG.getConstant(0, RHS.getValueType()); 2852 return X86::COND_NS; 2853 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2854 // X < 0 -> X == 0, jump on sign. 2855 return X86::COND_S; 2856 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2857 // X < 1 -> X <= 0 2858 RHS = DAG.getConstant(0, RHS.getValueType()); 2859 return X86::COND_LE; 2860 } 2861 } 2862 2863 switch (SetCCOpcode) { 2864 default: llvm_unreachable("Invalid integer condition!"); 2865 case ISD::SETEQ: return X86::COND_E; 2866 case ISD::SETGT: return X86::COND_G; 2867 case ISD::SETGE: return X86::COND_GE; 2868 case ISD::SETLT: return X86::COND_L; 2869 case ISD::SETLE: return X86::COND_LE; 2870 case ISD::SETNE: return X86::COND_NE; 2871 case ISD::SETULT: return X86::COND_B; 2872 case ISD::SETUGT: return X86::COND_A; 2873 case ISD::SETULE: return X86::COND_BE; 2874 case ISD::SETUGE: return X86::COND_AE; 2875 } 2876 } 2877 2878 // First determine if it is required or is profitable to flip the operands. 2879 2880 // If LHS is a foldable load, but RHS is not, flip the condition. 2881 if (ISD::isNON_EXTLoad(LHS.getNode()) && 2882 !ISD::isNON_EXTLoad(RHS.getNode())) { 2883 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2884 std::swap(LHS, RHS); 2885 } 2886 2887 switch (SetCCOpcode) { 2888 default: break; 2889 case ISD::SETOLT: 2890 case ISD::SETOLE: 2891 case ISD::SETUGT: 2892 case ISD::SETUGE: 2893 std::swap(LHS, RHS); 2894 break; 2895 } 2896 2897 // On a floating point condition, the flags are set as follows: 2898 // ZF PF CF op 2899 // 0 | 0 | 0 | X > Y 2900 // 0 | 0 | 1 | X < Y 2901 // 1 | 0 | 0 | X == Y 2902 // 1 | 1 | 1 | unordered 2903 switch (SetCCOpcode) { 2904 default: llvm_unreachable("Condcode should be pre-legalized away"); 2905 case ISD::SETUEQ: 2906 case ISD::SETEQ: return X86::COND_E; 2907 case ISD::SETOLT: // flipped 2908 case ISD::SETOGT: 2909 case ISD::SETGT: return X86::COND_A; 2910 case ISD::SETOLE: // flipped 2911 case ISD::SETOGE: 2912 case ISD::SETGE: return X86::COND_AE; 2913 case ISD::SETUGT: // flipped 2914 case ISD::SETULT: 2915 case ISD::SETLT: return X86::COND_B; 2916 case ISD::SETUGE: // flipped 2917 case ISD::SETULE: 2918 case ISD::SETLE: return X86::COND_BE; 2919 case ISD::SETONE: 2920 case ISD::SETNE: return X86::COND_NE; 2921 case ISD::SETUO: return X86::COND_P; 2922 case ISD::SETO: return X86::COND_NP; 2923 case ISD::SETOEQ: 2924 case ISD::SETUNE: return X86::COND_INVALID; 2925 } 2926} 2927 2928/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2929/// code. Current x86 isa includes the following FP cmov instructions: 2930/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2931static bool hasFPCMov(unsigned X86CC) { 2932 switch (X86CC) { 2933 default: 2934 return false; 2935 case X86::COND_B: 2936 case X86::COND_BE: 2937 case X86::COND_E: 2938 case X86::COND_P: 2939 case X86::COND_A: 2940 case X86::COND_AE: 2941 case X86::COND_NE: 2942 case X86::COND_NP: 2943 return true; 2944 } 2945} 2946 2947/// isFPImmLegal - Returns true if the target can instruction select the 2948/// specified FP immediate natively. If false, the legalizer will 2949/// materialize the FP immediate as a load from a constant pool. 2950bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2951 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2952 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2953 return true; 2954 } 2955 return false; 2956} 2957 2958/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2959/// the specified range (L, H]. 2960static bool isUndefOrInRange(int Val, int Low, int Hi) { 2961 return (Val < 0) || (Val >= Low && Val < Hi); 2962} 2963 2964/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2965/// specified value. 2966static bool isUndefOrEqual(int Val, int CmpVal) { 2967 if (Val < 0 || Val == CmpVal) 2968 return true; 2969 return false; 2970} 2971 2972/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2973/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2974/// the second operand. 2975static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2976 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 2977 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2978 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2979 return (Mask[0] < 2 && Mask[1] < 2); 2980 return false; 2981} 2982 2983bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2984 SmallVector<int, 8> M; 2985 N->getMask(M); 2986 return ::isPSHUFDMask(M, N->getValueType(0)); 2987} 2988 2989/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2990/// is suitable for input to PSHUFHW. 2991static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2992 if (VT != MVT::v8i16) 2993 return false; 2994 2995 // Lower quadword copied in order or undef. 2996 for (int i = 0; i != 4; ++i) 2997 if (Mask[i] >= 0 && Mask[i] != i) 2998 return false; 2999 3000 // Upper quadword shuffled. 3001 for (int i = 4; i != 8; ++i) 3002 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3003 return false; 3004 3005 return true; 3006} 3007 3008bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3009 SmallVector<int, 8> M; 3010 N->getMask(M); 3011 return ::isPSHUFHWMask(M, N->getValueType(0)); 3012} 3013 3014/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3015/// is suitable for input to PSHUFLW. 3016static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3017 if (VT != MVT::v8i16) 3018 return false; 3019 3020 // Upper quadword copied in order. 3021 for (int i = 4; i != 8; ++i) 3022 if (Mask[i] >= 0 && Mask[i] != i) 3023 return false; 3024 3025 // Lower quadword shuffled. 3026 for (int i = 0; i != 4; ++i) 3027 if (Mask[i] >= 4) 3028 return false; 3029 3030 return true; 3031} 3032 3033bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3034 SmallVector<int, 8> M; 3035 N->getMask(M); 3036 return ::isPSHUFLWMask(M, N->getValueType(0)); 3037} 3038 3039/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3040/// is suitable for input to PALIGNR. 3041static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3042 bool hasSSSE3) { 3043 int i, e = VT.getVectorNumElements(); 3044 3045 // Do not handle v2i64 / v2f64 shuffles with palignr. 3046 if (e < 4 || !hasSSSE3) 3047 return false; 3048 3049 for (i = 0; i != e; ++i) 3050 if (Mask[i] >= 0) 3051 break; 3052 3053 // All undef, not a palignr. 3054 if (i == e) 3055 return false; 3056 3057 // Determine if it's ok to perform a palignr with only the LHS, since we 3058 // don't have access to the actual shuffle elements to see if RHS is undef. 3059 bool Unary = Mask[i] < (int)e; 3060 bool NeedsUnary = false; 3061 3062 int s = Mask[i] - i; 3063 3064 // Check the rest of the elements to see if they are consecutive. 3065 for (++i; i != e; ++i) { 3066 int m = Mask[i]; 3067 if (m < 0) 3068 continue; 3069 3070 Unary = Unary && (m < (int)e); 3071 NeedsUnary = NeedsUnary || (m < s); 3072 3073 if (NeedsUnary && !Unary) 3074 return false; 3075 if (Unary && m != ((s+i) & (e-1))) 3076 return false; 3077 if (!Unary && m != (s+i)) 3078 return false; 3079 } 3080 return true; 3081} 3082 3083bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 3084 SmallVector<int, 8> M; 3085 N->getMask(M); 3086 return ::isPALIGNRMask(M, N->getValueType(0), true); 3087} 3088 3089/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3090/// specifies a shuffle of elements that is suitable for input to SHUFP*. 3091static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3092 int NumElems = VT.getVectorNumElements(); 3093 if (NumElems != 2 && NumElems != 4) 3094 return false; 3095 3096 int Half = NumElems / 2; 3097 for (int i = 0; i < Half; ++i) 3098 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3099 return false; 3100 for (int i = Half; i < NumElems; ++i) 3101 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3102 return false; 3103 3104 return true; 3105} 3106 3107bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3108 SmallVector<int, 8> M; 3109 N->getMask(M); 3110 return ::isSHUFPMask(M, N->getValueType(0)); 3111} 3112 3113/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3114/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3115/// half elements to come from vector 1 (which would equal the dest.) and 3116/// the upper half to come from vector 2. 3117static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3118 int NumElems = VT.getVectorNumElements(); 3119 3120 if (NumElems != 2 && NumElems != 4) 3121 return false; 3122 3123 int Half = NumElems / 2; 3124 for (int i = 0; i < Half; ++i) 3125 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3126 return false; 3127 for (int i = Half; i < NumElems; ++i) 3128 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3129 return false; 3130 return true; 3131} 3132 3133static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3134 SmallVector<int, 8> M; 3135 N->getMask(M); 3136 return isCommutedSHUFPMask(M, N->getValueType(0)); 3137} 3138 3139/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3140/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3141bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3142 if (N->getValueType(0).getVectorNumElements() != 4) 3143 return false; 3144 3145 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3146 return isUndefOrEqual(N->getMaskElt(0), 6) && 3147 isUndefOrEqual(N->getMaskElt(1), 7) && 3148 isUndefOrEqual(N->getMaskElt(2), 2) && 3149 isUndefOrEqual(N->getMaskElt(3), 3); 3150} 3151 3152/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3153/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3154/// <2, 3, 2, 3> 3155bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3156 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3157 3158 if (NumElems != 4) 3159 return false; 3160 3161 return isUndefOrEqual(N->getMaskElt(0), 2) && 3162 isUndefOrEqual(N->getMaskElt(1), 3) && 3163 isUndefOrEqual(N->getMaskElt(2), 2) && 3164 isUndefOrEqual(N->getMaskElt(3), 3); 3165} 3166 3167/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3168/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3169bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3170 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3171 3172 if (NumElems != 2 && NumElems != 4) 3173 return false; 3174 3175 for (unsigned i = 0; i < NumElems/2; ++i) 3176 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3177 return false; 3178 3179 for (unsigned i = NumElems/2; i < NumElems; ++i) 3180 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3181 return false; 3182 3183 return true; 3184} 3185 3186/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3187/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3188bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3189 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3190 3191 if ((NumElems != 2 && NumElems != 4) 3192 || N->getValueType(0).getSizeInBits() > 128) 3193 return false; 3194 3195 for (unsigned i = 0; i < NumElems/2; ++i) 3196 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3197 return false; 3198 3199 for (unsigned i = 0; i < NumElems/2; ++i) 3200 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3201 return false; 3202 3203 return true; 3204} 3205 3206/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3207/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3208static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3209 bool V2IsSplat = false) { 3210 int NumElts = VT.getVectorNumElements(); 3211 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3212 return false; 3213 3214 // Handle vector lengths > 128 bits. Define a "section" as a set of 3215 // 128 bits. AVX defines UNPCK* to operate independently on 128-bit 3216 // sections. 3217 unsigned NumSections = VT.getSizeInBits() / 128; 3218 if (NumSections == 0 ) NumSections = 1; // Handle MMX 3219 unsigned NumSectionElts = NumElts / NumSections; 3220 3221 unsigned Start = 0; 3222 unsigned End = NumSectionElts; 3223 for (unsigned s = 0; s < NumSections; ++s) { 3224 for (unsigned i = Start, j = s * NumSectionElts; 3225 i != End; 3226 i += 2, ++j) { 3227 int BitI = Mask[i]; 3228 int BitI1 = Mask[i+1]; 3229 if (!isUndefOrEqual(BitI, j)) 3230 return false; 3231 if (V2IsSplat) { 3232 if (!isUndefOrEqual(BitI1, NumElts)) 3233 return false; 3234 } else { 3235 if (!isUndefOrEqual(BitI1, j + NumElts)) 3236 return false; 3237 } 3238 } 3239 // Process the next 128 bits. 3240 Start += NumSectionElts; 3241 End += NumSectionElts; 3242 } 3243 3244 return true; 3245} 3246 3247bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3248 SmallVector<int, 8> M; 3249 N->getMask(M); 3250 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3251} 3252 3253/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3254/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3255static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3256 bool V2IsSplat = false) { 3257 int NumElts = VT.getVectorNumElements(); 3258 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3259 return false; 3260 3261 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3262 int BitI = Mask[i]; 3263 int BitI1 = Mask[i+1]; 3264 if (!isUndefOrEqual(BitI, j + NumElts/2)) 3265 return false; 3266 if (V2IsSplat) { 3267 if (isUndefOrEqual(BitI1, NumElts)) 3268 return false; 3269 } else { 3270 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 3271 return false; 3272 } 3273 } 3274 return true; 3275} 3276 3277bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3278 SmallVector<int, 8> M; 3279 N->getMask(M); 3280 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3281} 3282 3283/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3284/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3285/// <0, 0, 1, 1> 3286static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3287 int NumElems = VT.getVectorNumElements(); 3288 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3289 return false; 3290 3291 // Handle vector lengths > 128 bits. Define a "section" as a set of 3292 // 128 bits. AVX defines UNPCK* to operate independently on 128-bit 3293 // sections. 3294 unsigned NumSections = VT.getSizeInBits() / 128; 3295 if (NumSections == 0 ) NumSections = 1; // Handle MMX 3296 unsigned NumSectionElts = NumElems / NumSections; 3297 3298 for (unsigned s = 0; s < NumSections; ++s) { 3299 for (unsigned i = s * NumSectionElts, j = s * NumSectionElts; 3300 i != NumSectionElts * (s + 1); 3301 i += 2, ++j) { 3302 int BitI = Mask[i]; 3303 int BitI1 = Mask[i+1]; 3304 3305 if (!isUndefOrEqual(BitI, j)) 3306 return false; 3307 if (!isUndefOrEqual(BitI1, j)) 3308 return false; 3309 } 3310 } 3311 3312 return true; 3313} 3314 3315bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3316 SmallVector<int, 8> M; 3317 N->getMask(M); 3318 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3319} 3320 3321/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3322/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3323/// <2, 2, 3, 3> 3324static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3325 int NumElems = VT.getVectorNumElements(); 3326 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3327 return false; 3328 3329 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3330 int BitI = Mask[i]; 3331 int BitI1 = Mask[i+1]; 3332 if (!isUndefOrEqual(BitI, j)) 3333 return false; 3334 if (!isUndefOrEqual(BitI1, j)) 3335 return false; 3336 } 3337 return true; 3338} 3339 3340bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3341 SmallVector<int, 8> M; 3342 N->getMask(M); 3343 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3344} 3345 3346/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3347/// specifies a shuffle of elements that is suitable for input to MOVSS, 3348/// MOVSD, and MOVD, i.e. setting the lowest element. 3349static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3350 if (VT.getVectorElementType().getSizeInBits() < 32) 3351 return false; 3352 3353 int NumElts = VT.getVectorNumElements(); 3354 3355 if (!isUndefOrEqual(Mask[0], NumElts)) 3356 return false; 3357 3358 for (int i = 1; i < NumElts; ++i) 3359 if (!isUndefOrEqual(Mask[i], i)) 3360 return false; 3361 3362 return true; 3363} 3364 3365bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3366 SmallVector<int, 8> M; 3367 N->getMask(M); 3368 return ::isMOVLMask(M, N->getValueType(0)); 3369} 3370 3371/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3372/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3373/// element of vector 2 and the other elements to come from vector 1 in order. 3374static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3375 bool V2IsSplat = false, bool V2IsUndef = false) { 3376 int NumOps = VT.getVectorNumElements(); 3377 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3378 return false; 3379 3380 if (!isUndefOrEqual(Mask[0], 0)) 3381 return false; 3382 3383 for (int i = 1; i < NumOps; ++i) 3384 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3385 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3386 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3387 return false; 3388 3389 return true; 3390} 3391 3392static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3393 bool V2IsUndef = false) { 3394 SmallVector<int, 8> M; 3395 N->getMask(M); 3396 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3397} 3398 3399/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3400/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3401bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3402 if (N->getValueType(0).getVectorNumElements() != 4) 3403 return false; 3404 3405 // Expect 1, 1, 3, 3 3406 for (unsigned i = 0; i < 2; ++i) { 3407 int Elt = N->getMaskElt(i); 3408 if (Elt >= 0 && Elt != 1) 3409 return false; 3410 } 3411 3412 bool HasHi = false; 3413 for (unsigned i = 2; i < 4; ++i) { 3414 int Elt = N->getMaskElt(i); 3415 if (Elt >= 0 && Elt != 3) 3416 return false; 3417 if (Elt == 3) 3418 HasHi = true; 3419 } 3420 // Don't use movshdup if it can be done with a shufps. 3421 // FIXME: verify that matching u, u, 3, 3 is what we want. 3422 return HasHi; 3423} 3424 3425/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3426/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3427bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3428 if (N->getValueType(0).getVectorNumElements() != 4) 3429 return false; 3430 3431 // Expect 0, 0, 2, 2 3432 for (unsigned i = 0; i < 2; ++i) 3433 if (N->getMaskElt(i) > 0) 3434 return false; 3435 3436 bool HasHi = false; 3437 for (unsigned i = 2; i < 4; ++i) { 3438 int Elt = N->getMaskElt(i); 3439 if (Elt >= 0 && Elt != 2) 3440 return false; 3441 if (Elt == 2) 3442 HasHi = true; 3443 } 3444 // Don't use movsldup if it can be done with a shufps. 3445 return HasHi; 3446} 3447 3448/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3449/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3450bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3451 int e = N->getValueType(0).getVectorNumElements() / 2; 3452 3453 for (int i = 0; i < e; ++i) 3454 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3455 return false; 3456 for (int i = 0; i < e; ++i) 3457 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3458 return false; 3459 return true; 3460} 3461 3462/// isVEXTRACTF128Index - Return true if the specified 3463/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3464/// suitable for input to VEXTRACTF128. 3465bool X86::isVEXTRACTF128Index(SDNode *N) { 3466 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3467 return false; 3468 3469 // The index should be aligned on a 128-bit boundary. 3470 uint64_t Index = 3471 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3472 3473 unsigned VL = N->getValueType(0).getVectorNumElements(); 3474 unsigned VBits = N->getValueType(0).getSizeInBits(); 3475 unsigned ElSize = VBits / VL; 3476 bool Result = (Index * ElSize) % 128 == 0; 3477 3478 return Result; 3479} 3480 3481/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3482/// operand specifies a subvector insert that is suitable for input to 3483/// VINSERTF128. 3484bool X86::isVINSERTF128Index(SDNode *N) { 3485 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3486 return false; 3487 3488 // The index should be aligned on a 128-bit boundary. 3489 uint64_t Index = 3490 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3491 3492 unsigned VL = N->getValueType(0).getVectorNumElements(); 3493 unsigned VBits = N->getValueType(0).getSizeInBits(); 3494 unsigned ElSize = VBits / VL; 3495 bool Result = (Index * ElSize) % 128 == 0; 3496 3497 return Result; 3498} 3499 3500/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3501/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3502unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3503 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3504 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3505 3506 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3507 unsigned Mask = 0; 3508 for (int i = 0; i < NumOperands; ++i) { 3509 int Val = SVOp->getMaskElt(NumOperands-i-1); 3510 if (Val < 0) Val = 0; 3511 if (Val >= NumOperands) Val -= NumOperands; 3512 Mask |= Val; 3513 if (i != NumOperands - 1) 3514 Mask <<= Shift; 3515 } 3516 return Mask; 3517} 3518 3519/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3520/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3521unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3523 unsigned Mask = 0; 3524 // 8 nodes, but we only care about the last 4. 3525 for (unsigned i = 7; i >= 4; --i) { 3526 int Val = SVOp->getMaskElt(i); 3527 if (Val >= 0) 3528 Mask |= (Val - 4); 3529 if (i != 4) 3530 Mask <<= 2; 3531 } 3532 return Mask; 3533} 3534 3535/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3536/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3537unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3539 unsigned Mask = 0; 3540 // 8 nodes, but we only care about the first 4. 3541 for (int i = 3; i >= 0; --i) { 3542 int Val = SVOp->getMaskElt(i); 3543 if (Val >= 0) 3544 Mask |= Val; 3545 if (i != 0) 3546 Mask <<= 2; 3547 } 3548 return Mask; 3549} 3550 3551/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3552/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3553unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3554 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3555 EVT VVT = N->getValueType(0); 3556 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3557 int Val = 0; 3558 3559 unsigned i, e; 3560 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3561 Val = SVOp->getMaskElt(i); 3562 if (Val >= 0) 3563 break; 3564 } 3565 return (Val - i) * EltSize; 3566} 3567 3568/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3569/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3570/// instructions. 3571unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3572 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3573 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3574 3575 uint64_t Index = 3576 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3577 3578 EVT VecVT = N->getOperand(0).getValueType(); 3579 EVT ElVT = VecVT.getVectorElementType(); 3580 3581 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3582 3583 return Index / NumElemsPerChunk; 3584} 3585 3586/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3587/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3588/// instructions. 3589unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3590 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3591 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3592 3593 uint64_t Index = 3594 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3595 3596 EVT VecVT = N->getValueType(0); 3597 EVT ElVT = VecVT.getVectorElementType(); 3598 3599 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3600 3601 return Index / NumElemsPerChunk; 3602} 3603 3604/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3605/// constant +0.0. 3606bool X86::isZeroNode(SDValue Elt) { 3607 return ((isa<ConstantSDNode>(Elt) && 3608 cast<ConstantSDNode>(Elt)->isNullValue()) || 3609 (isa<ConstantFPSDNode>(Elt) && 3610 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3611} 3612 3613/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3614/// their permute mask. 3615static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3616 SelectionDAG &DAG) { 3617 EVT VT = SVOp->getValueType(0); 3618 unsigned NumElems = VT.getVectorNumElements(); 3619 SmallVector<int, 8> MaskVec; 3620 3621 for (unsigned i = 0; i != NumElems; ++i) { 3622 int idx = SVOp->getMaskElt(i); 3623 if (idx < 0) 3624 MaskVec.push_back(idx); 3625 else if (idx < (int)NumElems) 3626 MaskVec.push_back(idx + NumElems); 3627 else 3628 MaskVec.push_back(idx - NumElems); 3629 } 3630 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3631 SVOp->getOperand(0), &MaskVec[0]); 3632} 3633 3634/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3635/// the two vector operands have swapped position. 3636static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3637 unsigned NumElems = VT.getVectorNumElements(); 3638 for (unsigned i = 0; i != NumElems; ++i) { 3639 int idx = Mask[i]; 3640 if (idx < 0) 3641 continue; 3642 else if (idx < (int)NumElems) 3643 Mask[i] = idx + NumElems; 3644 else 3645 Mask[i] = idx - NumElems; 3646 } 3647} 3648 3649/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3650/// match movhlps. The lower half elements should come from upper half of 3651/// V1 (and in order), and the upper half elements should come from the upper 3652/// half of V2 (and in order). 3653static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3654 if (Op->getValueType(0).getVectorNumElements() != 4) 3655 return false; 3656 for (unsigned i = 0, e = 2; i != e; ++i) 3657 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3658 return false; 3659 for (unsigned i = 2; i != 4; ++i) 3660 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3661 return false; 3662 return true; 3663} 3664 3665/// isScalarLoadToVector - Returns true if the node is a scalar load that 3666/// is promoted to a vector. It also returns the LoadSDNode by reference if 3667/// required. 3668static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3669 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3670 return false; 3671 N = N->getOperand(0).getNode(); 3672 if (!ISD::isNON_EXTLoad(N)) 3673 return false; 3674 if (LD) 3675 *LD = cast<LoadSDNode>(N); 3676 return true; 3677} 3678 3679/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3680/// match movlp{s|d}. The lower half elements should come from lower half of 3681/// V1 (and in order), and the upper half elements should come from the upper 3682/// half of V2 (and in order). And since V1 will become the source of the 3683/// MOVLP, it must be either a vector load or a scalar load to vector. 3684static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3685 ShuffleVectorSDNode *Op) { 3686 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3687 return false; 3688 // Is V2 is a vector load, don't do this transformation. We will try to use 3689 // load folding shufps op. 3690 if (ISD::isNON_EXTLoad(V2)) 3691 return false; 3692 3693 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3694 3695 if (NumElems != 2 && NumElems != 4) 3696 return false; 3697 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3698 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3699 return false; 3700 for (unsigned i = NumElems/2; i != NumElems; ++i) 3701 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3702 return false; 3703 return true; 3704} 3705 3706/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3707/// all the same. 3708static bool isSplatVector(SDNode *N) { 3709 if (N->getOpcode() != ISD::BUILD_VECTOR) 3710 return false; 3711 3712 SDValue SplatValue = N->getOperand(0); 3713 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3714 if (N->getOperand(i) != SplatValue) 3715 return false; 3716 return true; 3717} 3718 3719/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3720/// to an zero vector. 3721/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3722static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3723 SDValue V1 = N->getOperand(0); 3724 SDValue V2 = N->getOperand(1); 3725 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3726 for (unsigned i = 0; i != NumElems; ++i) { 3727 int Idx = N->getMaskElt(i); 3728 if (Idx >= (int)NumElems) { 3729 unsigned Opc = V2.getOpcode(); 3730 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3731 continue; 3732 if (Opc != ISD::BUILD_VECTOR || 3733 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3734 return false; 3735 } else if (Idx >= 0) { 3736 unsigned Opc = V1.getOpcode(); 3737 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3738 continue; 3739 if (Opc != ISD::BUILD_VECTOR || 3740 !X86::isZeroNode(V1.getOperand(Idx))) 3741 return false; 3742 } 3743 } 3744 return true; 3745} 3746 3747/// getZeroVector - Returns a vector of specified type with all zero elements. 3748/// 3749static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3750 DebugLoc dl) { 3751 assert(VT.isVector() && "Expected a vector type"); 3752 3753 // Always build SSE zero vectors as <4 x i32> bitcasted 3754 // to their dest type. This ensures they get CSE'd. 3755 SDValue Vec; 3756 if (VT.getSizeInBits() == 128) { // SSE 3757 if (HasSSE2) { // SSE2 3758 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3759 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3760 } else { // SSE1 3761 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3762 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3763 } 3764 } else if (VT.getSizeInBits() == 256) { // AVX 3765 // 256-bit logic and arithmetic instructions in AVX are 3766 // all floating-point, no support for integer ops. Default 3767 // to emitting fp zeroed vectors then. 3768 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3769 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3770 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3771 } 3772 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3773} 3774 3775/// getOnesVector - Returns a vector of specified type with all bits set. 3776/// 3777static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3778 assert(VT.isVector() && "Expected a vector type"); 3779 3780 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3781 // type. This ensures they get CSE'd. 3782 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3783 SDValue Vec; 3784 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3785 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3786} 3787 3788 3789/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3790/// that point to V2 points to its first element. 3791static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3792 EVT VT = SVOp->getValueType(0); 3793 unsigned NumElems = VT.getVectorNumElements(); 3794 3795 bool Changed = false; 3796 SmallVector<int, 8> MaskVec; 3797 SVOp->getMask(MaskVec); 3798 3799 for (unsigned i = 0; i != NumElems; ++i) { 3800 if (MaskVec[i] > (int)NumElems) { 3801 MaskVec[i] = NumElems; 3802 Changed = true; 3803 } 3804 } 3805 if (Changed) 3806 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3807 SVOp->getOperand(1), &MaskVec[0]); 3808 return SDValue(SVOp, 0); 3809} 3810 3811/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3812/// operation of specified width. 3813static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3814 SDValue V2) { 3815 unsigned NumElems = VT.getVectorNumElements(); 3816 SmallVector<int, 8> Mask; 3817 Mask.push_back(NumElems); 3818 for (unsigned i = 1; i != NumElems; ++i) 3819 Mask.push_back(i); 3820 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3821} 3822 3823/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3824static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3825 SDValue V2) { 3826 unsigned NumElems = VT.getVectorNumElements(); 3827 SmallVector<int, 8> Mask; 3828 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3829 Mask.push_back(i); 3830 Mask.push_back(i + NumElems); 3831 } 3832 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3833} 3834 3835/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3836static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3837 SDValue V2) { 3838 unsigned NumElems = VT.getVectorNumElements(); 3839 unsigned Half = NumElems/2; 3840 SmallVector<int, 8> Mask; 3841 for (unsigned i = 0; i != Half; ++i) { 3842 Mask.push_back(i + Half); 3843 Mask.push_back(i + NumElems + Half); 3844 } 3845 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3846} 3847 3848/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32. 3849static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 3850 EVT PVT = MVT::v4f32; 3851 EVT VT = SV->getValueType(0); 3852 DebugLoc dl = SV->getDebugLoc(); 3853 SDValue V1 = SV->getOperand(0); 3854 int NumElems = VT.getVectorNumElements(); 3855 int EltNo = SV->getSplatIndex(); 3856 3857 // unpack elements to the correct location 3858 while (NumElems > 4) { 3859 if (EltNo < NumElems/2) { 3860 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3861 } else { 3862 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3863 EltNo -= NumElems/2; 3864 } 3865 NumElems >>= 1; 3866 } 3867 3868 // Perform the splat. 3869 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3870 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1); 3871 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3872 return DAG.getNode(ISD::BITCAST, dl, VT, V1); 3873} 3874 3875/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3876/// vector of zero or undef vector. This produces a shuffle where the low 3877/// element of V2 is swizzled into the zero/undef vector, landing at element 3878/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3879static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3880 bool isZero, bool HasSSE2, 3881 SelectionDAG &DAG) { 3882 EVT VT = V2.getValueType(); 3883 SDValue V1 = isZero 3884 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3885 unsigned NumElems = VT.getVectorNumElements(); 3886 SmallVector<int, 16> MaskVec; 3887 for (unsigned i = 0; i != NumElems; ++i) 3888 // If this is the insertion idx, put the low elt of V2 here. 3889 MaskVec.push_back(i == Idx ? NumElems : i); 3890 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3891} 3892 3893/// getShuffleScalarElt - Returns the scalar element that will make up the ith 3894/// element of the result of the vector shuffle. 3895SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 3896 unsigned Depth) { 3897 if (Depth == 6) 3898 return SDValue(); // Limit search depth. 3899 3900 SDValue V = SDValue(N, 0); 3901 EVT VT = V.getValueType(); 3902 unsigned Opcode = V.getOpcode(); 3903 3904 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 3905 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 3906 Index = SV->getMaskElt(Index); 3907 3908 if (Index < 0) 3909 return DAG.getUNDEF(VT.getVectorElementType()); 3910 3911 int NumElems = VT.getVectorNumElements(); 3912 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 3913 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 3914 } 3915 3916 // Recurse into target specific vector shuffles to find scalars. 3917 if (isTargetShuffle(Opcode)) { 3918 int NumElems = VT.getVectorNumElements(); 3919 SmallVector<unsigned, 16> ShuffleMask; 3920 SDValue ImmN; 3921 3922 switch(Opcode) { 3923 case X86ISD::SHUFPS: 3924 case X86ISD::SHUFPD: 3925 ImmN = N->getOperand(N->getNumOperands()-1); 3926 DecodeSHUFPSMask(NumElems, 3927 cast<ConstantSDNode>(ImmN)->getZExtValue(), 3928 ShuffleMask); 3929 break; 3930 case X86ISD::PUNPCKHBW: 3931 case X86ISD::PUNPCKHWD: 3932 case X86ISD::PUNPCKHDQ: 3933 case X86ISD::PUNPCKHQDQ: 3934 DecodePUNPCKHMask(NumElems, ShuffleMask); 3935 break; 3936 case X86ISD::UNPCKHPS: 3937 case X86ISD::UNPCKHPD: 3938 DecodeUNPCKHPMask(NumElems, ShuffleMask); 3939 break; 3940 case X86ISD::PUNPCKLBW: 3941 case X86ISD::PUNPCKLWD: 3942 case X86ISD::PUNPCKLDQ: 3943 case X86ISD::PUNPCKLQDQ: 3944 DecodePUNPCKLMask(VT, ShuffleMask); 3945 break; 3946 case X86ISD::UNPCKLPS: 3947 case X86ISD::UNPCKLPD: 3948 case X86ISD::VUNPCKLPS: 3949 case X86ISD::VUNPCKLPD: 3950 case X86ISD::VUNPCKLPSY: 3951 case X86ISD::VUNPCKLPDY: 3952 DecodeUNPCKLPMask(VT, ShuffleMask); 3953 break; 3954 case X86ISD::MOVHLPS: 3955 DecodeMOVHLPSMask(NumElems, ShuffleMask); 3956 break; 3957 case X86ISD::MOVLHPS: 3958 DecodeMOVLHPSMask(NumElems, ShuffleMask); 3959 break; 3960 case X86ISD::PSHUFD: 3961 ImmN = N->getOperand(N->getNumOperands()-1); 3962 DecodePSHUFMask(NumElems, 3963 cast<ConstantSDNode>(ImmN)->getZExtValue(), 3964 ShuffleMask); 3965 break; 3966 case X86ISD::PSHUFHW: 3967 ImmN = N->getOperand(N->getNumOperands()-1); 3968 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 3969 ShuffleMask); 3970 break; 3971 case X86ISD::PSHUFLW: 3972 ImmN = N->getOperand(N->getNumOperands()-1); 3973 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 3974 ShuffleMask); 3975 break; 3976 case X86ISD::MOVSS: 3977 case X86ISD::MOVSD: { 3978 // The index 0 always comes from the first element of the second source, 3979 // this is why MOVSS and MOVSD are used in the first place. The other 3980 // elements come from the other positions of the first source vector. 3981 unsigned OpNum = (Index == 0) ? 1 : 0; 3982 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 3983 Depth+1); 3984 } 3985 default: 3986 assert("not implemented for target shuffle node"); 3987 return SDValue(); 3988 } 3989 3990 Index = ShuffleMask[Index]; 3991 if (Index < 0) 3992 return DAG.getUNDEF(VT.getVectorElementType()); 3993 3994 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 3995 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 3996 Depth+1); 3997 } 3998 3999 // Actual nodes that may contain scalar elements 4000 if (Opcode == ISD::BITCAST) { 4001 V = V.getOperand(0); 4002 EVT SrcVT = V.getValueType(); 4003 unsigned NumElems = VT.getVectorNumElements(); 4004 4005 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4006 return SDValue(); 4007 } 4008 4009 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4010 return (Index == 0) ? V.getOperand(0) 4011 : DAG.getUNDEF(VT.getVectorElementType()); 4012 4013 if (V.getOpcode() == ISD::BUILD_VECTOR) 4014 return V.getOperand(Index); 4015 4016 return SDValue(); 4017} 4018 4019/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4020/// shuffle operation which come from a consecutively from a zero. The 4021/// search can start in two diferent directions, from left or right. 4022static 4023unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4024 bool ZerosFromLeft, SelectionDAG &DAG) { 4025 int i = 0; 4026 4027 while (i < NumElems) { 4028 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4029 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4030 if (!(Elt.getNode() && 4031 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4032 break; 4033 ++i; 4034 } 4035 4036 return i; 4037} 4038 4039/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4040/// MaskE correspond consecutively to elements from one of the vector operands, 4041/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4042static 4043bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4044 int OpIdx, int NumElems, unsigned &OpNum) { 4045 bool SeenV1 = false; 4046 bool SeenV2 = false; 4047 4048 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4049 int Idx = SVOp->getMaskElt(i); 4050 // Ignore undef indicies 4051 if (Idx < 0) 4052 continue; 4053 4054 if (Idx < NumElems) 4055 SeenV1 = true; 4056 else 4057 SeenV2 = true; 4058 4059 // Only accept consecutive elements from the same vector 4060 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4061 return false; 4062 } 4063 4064 OpNum = SeenV1 ? 0 : 1; 4065 return true; 4066} 4067 4068/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4069/// logical left shift of a vector. 4070static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4071 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4072 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4073 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4074 false /* check zeros from right */, DAG); 4075 unsigned OpSrc; 4076 4077 if (!NumZeros) 4078 return false; 4079 4080 // Considering the elements in the mask that are not consecutive zeros, 4081 // check if they consecutively come from only one of the source vectors. 4082 // 4083 // V1 = {X, A, B, C} 0 4084 // \ \ \ / 4085 // vector_shuffle V1, V2 <1, 2, 3, X> 4086 // 4087 if (!isShuffleMaskConsecutive(SVOp, 4088 0, // Mask Start Index 4089 NumElems-NumZeros-1, // Mask End Index 4090 NumZeros, // Where to start looking in the src vector 4091 NumElems, // Number of elements in vector 4092 OpSrc)) // Which source operand ? 4093 return false; 4094 4095 isLeft = false; 4096 ShAmt = NumZeros; 4097 ShVal = SVOp->getOperand(OpSrc); 4098 return true; 4099} 4100 4101/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4102/// logical left shift of a vector. 4103static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4104 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4105 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4106 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4107 true /* check zeros from left */, DAG); 4108 unsigned OpSrc; 4109 4110 if (!NumZeros) 4111 return false; 4112 4113 // Considering the elements in the mask that are not consecutive zeros, 4114 // check if they consecutively come from only one of the source vectors. 4115 // 4116 // 0 { A, B, X, X } = V2 4117 // / \ / / 4118 // vector_shuffle V1, V2 <X, X, 4, 5> 4119 // 4120 if (!isShuffleMaskConsecutive(SVOp, 4121 NumZeros, // Mask Start Index 4122 NumElems-1, // Mask End Index 4123 0, // Where to start looking in the src vector 4124 NumElems, // Number of elements in vector 4125 OpSrc)) // Which source operand ? 4126 return false; 4127 4128 isLeft = true; 4129 ShAmt = NumZeros; 4130 ShVal = SVOp->getOperand(OpSrc); 4131 return true; 4132} 4133 4134/// isVectorShift - Returns true if the shuffle can be implemented as a 4135/// logical left or right shift of a vector. 4136static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4137 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4138 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4139 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4140 return true; 4141 4142 return false; 4143} 4144 4145/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4146/// 4147static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4148 unsigned NumNonZero, unsigned NumZero, 4149 SelectionDAG &DAG, 4150 const TargetLowering &TLI) { 4151 if (NumNonZero > 8) 4152 return SDValue(); 4153 4154 DebugLoc dl = Op.getDebugLoc(); 4155 SDValue V(0, 0); 4156 bool First = true; 4157 for (unsigned i = 0; i < 16; ++i) { 4158 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4159 if (ThisIsNonZero && First) { 4160 if (NumZero) 4161 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4162 else 4163 V = DAG.getUNDEF(MVT::v8i16); 4164 First = false; 4165 } 4166 4167 if ((i & 1) != 0) { 4168 SDValue ThisElt(0, 0), LastElt(0, 0); 4169 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4170 if (LastIsNonZero) { 4171 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4172 MVT::i16, Op.getOperand(i-1)); 4173 } 4174 if (ThisIsNonZero) { 4175 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4176 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4177 ThisElt, DAG.getConstant(8, MVT::i8)); 4178 if (LastIsNonZero) 4179 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4180 } else 4181 ThisElt = LastElt; 4182 4183 if (ThisElt.getNode()) 4184 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4185 DAG.getIntPtrConstant(i/2)); 4186 } 4187 } 4188 4189 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4190} 4191 4192/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4193/// 4194static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4195 unsigned NumNonZero, unsigned NumZero, 4196 SelectionDAG &DAG, 4197 const TargetLowering &TLI) { 4198 if (NumNonZero > 4) 4199 return SDValue(); 4200 4201 DebugLoc dl = Op.getDebugLoc(); 4202 SDValue V(0, 0); 4203 bool First = true; 4204 for (unsigned i = 0; i < 8; ++i) { 4205 bool isNonZero = (NonZeros & (1 << i)) != 0; 4206 if (isNonZero) { 4207 if (First) { 4208 if (NumZero) 4209 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4210 else 4211 V = DAG.getUNDEF(MVT::v8i16); 4212 First = false; 4213 } 4214 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4215 MVT::v8i16, V, Op.getOperand(i), 4216 DAG.getIntPtrConstant(i)); 4217 } 4218 } 4219 4220 return V; 4221} 4222 4223/// getVShift - Return a vector logical shift node. 4224/// 4225static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4226 unsigned NumBits, SelectionDAG &DAG, 4227 const TargetLowering &TLI, DebugLoc dl) { 4228 EVT ShVT = MVT::v2i64; 4229 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4230 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4231 return DAG.getNode(ISD::BITCAST, dl, VT, 4232 DAG.getNode(Opc, dl, ShVT, SrcOp, 4233 DAG.getConstant(NumBits, 4234 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4235} 4236 4237SDValue 4238X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4239 SelectionDAG &DAG) const { 4240 4241 // Check if the scalar load can be widened into a vector load. And if 4242 // the address is "base + cst" see if the cst can be "absorbed" into 4243 // the shuffle mask. 4244 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4245 SDValue Ptr = LD->getBasePtr(); 4246 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4247 return SDValue(); 4248 EVT PVT = LD->getValueType(0); 4249 if (PVT != MVT::i32 && PVT != MVT::f32) 4250 return SDValue(); 4251 4252 int FI = -1; 4253 int64_t Offset = 0; 4254 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4255 FI = FINode->getIndex(); 4256 Offset = 0; 4257 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4258 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4259 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4260 Offset = Ptr.getConstantOperandVal(1); 4261 Ptr = Ptr.getOperand(0); 4262 } else { 4263 return SDValue(); 4264 } 4265 4266 SDValue Chain = LD->getChain(); 4267 // Make sure the stack object alignment is at least 16. 4268 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4269 if (DAG.InferPtrAlignment(Ptr) < 16) { 4270 if (MFI->isFixedObjectIndex(FI)) { 4271 // Can't change the alignment. FIXME: It's possible to compute 4272 // the exact stack offset and reference FI + adjust offset instead. 4273 // If someone *really* cares about this. That's the way to implement it. 4274 return SDValue(); 4275 } else { 4276 MFI->setObjectAlignment(FI, 16); 4277 } 4278 } 4279 4280 // (Offset % 16) must be multiple of 4. Then address is then 4281 // Ptr + (Offset & ~15). 4282 if (Offset < 0) 4283 return SDValue(); 4284 if ((Offset % 16) & 3) 4285 return SDValue(); 4286 int64_t StartOffset = Offset & ~15; 4287 if (StartOffset) 4288 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4289 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4290 4291 int EltNo = (Offset - StartOffset) >> 2; 4292 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 4293 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 4294 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr, 4295 LD->getPointerInfo().getWithOffset(StartOffset), 4296 false, false, 0); 4297 // Canonicalize it to a v4i32 shuffle. 4298 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); 4299 return DAG.getNode(ISD::BITCAST, dl, VT, 4300 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 4301 DAG.getUNDEF(MVT::v4i32),&Mask[0])); 4302 } 4303 4304 return SDValue(); 4305} 4306 4307/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4308/// vector of type 'VT', see if the elements can be replaced by a single large 4309/// load which has the same value as a build_vector whose operands are 'elts'. 4310/// 4311/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4312/// 4313/// FIXME: we'd also like to handle the case where the last elements are zero 4314/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4315/// There's even a handy isZeroNode for that purpose. 4316static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4317 DebugLoc &DL, SelectionDAG &DAG) { 4318 EVT EltVT = VT.getVectorElementType(); 4319 unsigned NumElems = Elts.size(); 4320 4321 LoadSDNode *LDBase = NULL; 4322 unsigned LastLoadedElt = -1U; 4323 4324 // For each element in the initializer, see if we've found a load or an undef. 4325 // If we don't find an initial load element, or later load elements are 4326 // non-consecutive, bail out. 4327 for (unsigned i = 0; i < NumElems; ++i) { 4328 SDValue Elt = Elts[i]; 4329 4330 if (!Elt.getNode() || 4331 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4332 return SDValue(); 4333 if (!LDBase) { 4334 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4335 return SDValue(); 4336 LDBase = cast<LoadSDNode>(Elt.getNode()); 4337 LastLoadedElt = i; 4338 continue; 4339 } 4340 if (Elt.getOpcode() == ISD::UNDEF) 4341 continue; 4342 4343 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4344 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4345 return SDValue(); 4346 LastLoadedElt = i; 4347 } 4348 4349 // If we have found an entire vector of loads and undefs, then return a large 4350 // load of the entire vector width starting at the base pointer. If we found 4351 // consecutive loads for the low half, generate a vzext_load node. 4352 if (LastLoadedElt == NumElems - 1) { 4353 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4354 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4355 LDBase->getPointerInfo(), 4356 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4357 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4358 LDBase->getPointerInfo(), 4359 LDBase->isVolatile(), LDBase->isNonTemporal(), 4360 LDBase->getAlignment()); 4361 } else if (NumElems == 4 && LastLoadedElt == 1) { 4362 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4363 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4364 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, 4365 Ops, 2, MVT::i32, 4366 LDBase->getMemOperand()); 4367 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4368 } 4369 return SDValue(); 4370} 4371 4372SDValue 4373X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4374 DebugLoc dl = Op.getDebugLoc(); 4375 4376 EVT VT = Op.getValueType(); 4377 EVT ExtVT = VT.getVectorElementType(); 4378 4379 unsigned NumElems = Op.getNumOperands(); 4380 4381 // For AVX-length vectors, build the individual 128-bit pieces and 4382 // use shuffles to put them in place. 4383 if (VT.getSizeInBits() > 256 && 4384 Subtarget->hasAVX() && 4385 !ISD::isBuildVectorAllZeros(Op.getNode())) { 4386 SmallVector<SDValue, 8> V; 4387 V.resize(NumElems); 4388 for (unsigned i = 0; i < NumElems; ++i) { 4389 V[i] = Op.getOperand(i); 4390 } 4391 4392 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 4393 4394 // Build the lower subvector. 4395 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 4396 // Build the upper subvector. 4397 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 4398 NumElems/2); 4399 4400 return ConcatVectors(Lower, Upper, DAG); 4401 } 4402 4403 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1. 4404 // All one's are handled with pcmpeqd. In AVX, zero's are handled with 4405 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd 4406 // is present, so AllOnes is ignored. 4407 if (ISD::isBuildVectorAllZeros(Op.getNode()) || 4408 (Op.getValueType().getSizeInBits() != 256 && 4409 ISD::isBuildVectorAllOnes(Op.getNode()))) { 4410 // Canonicalize this to <4 x i32> (SSE) to 4411 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 4412 // eliminated on x86-32 hosts. 4413 if (Op.getValueType() == MVT::v4i32) 4414 return Op; 4415 4416 if (ISD::isBuildVectorAllOnes(Op.getNode())) 4417 return getOnesVector(Op.getValueType(), DAG, dl); 4418 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4419 } 4420 4421 unsigned EVTBits = ExtVT.getSizeInBits(); 4422 4423 unsigned NumZero = 0; 4424 unsigned NumNonZero = 0; 4425 unsigned NonZeros = 0; 4426 bool IsAllConstants = true; 4427 SmallSet<SDValue, 8> Values; 4428 for (unsigned i = 0; i < NumElems; ++i) { 4429 SDValue Elt = Op.getOperand(i); 4430 if (Elt.getOpcode() == ISD::UNDEF) 4431 continue; 4432 Values.insert(Elt); 4433 if (Elt.getOpcode() != ISD::Constant && 4434 Elt.getOpcode() != ISD::ConstantFP) 4435 IsAllConstants = false; 4436 if (X86::isZeroNode(Elt)) 4437 NumZero++; 4438 else { 4439 NonZeros |= (1 << i); 4440 NumNonZero++; 4441 } 4442 } 4443 4444 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4445 if (NumNonZero == 0) 4446 return DAG.getUNDEF(VT); 4447 4448 // Special case for single non-zero, non-undef, element. 4449 if (NumNonZero == 1) { 4450 unsigned Idx = CountTrailingZeros_32(NonZeros); 4451 SDValue Item = Op.getOperand(Idx); 4452 4453 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4454 // the value are obviously zero, truncate the value to i32 and do the 4455 // insertion that way. Only do this if the value is non-constant or if the 4456 // value is a constant being inserted into element 0. It is cheaper to do 4457 // a constant pool load than it is to do a movd + shuffle. 4458 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4459 (!IsAllConstants || Idx == 0)) { 4460 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4461 // Handle SSE only. 4462 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 4463 EVT VecVT = MVT::v4i32; 4464 unsigned VecElts = 4; 4465 4466 // Truncate the value (which may itself be a constant) to i32, and 4467 // convert it to a vector with movd (S2V+shuffle to zero extend). 4468 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4469 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4470 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4471 Subtarget->hasSSE2(), DAG); 4472 4473 // Now we have our 32-bit value zero extended in the low element of 4474 // a vector. If Idx != 0, swizzle it into place. 4475 if (Idx != 0) { 4476 SmallVector<int, 4> Mask; 4477 Mask.push_back(Idx); 4478 for (unsigned i = 1; i != VecElts; ++i) 4479 Mask.push_back(i); 4480 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4481 DAG.getUNDEF(Item.getValueType()), 4482 &Mask[0]); 4483 } 4484 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 4485 } 4486 } 4487 4488 // If we have a constant or non-constant insertion into the low element of 4489 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4490 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4491 // depending on what the source datatype is. 4492 if (Idx == 0) { 4493 if (NumZero == 0) { 4494 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4495 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4496 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4497 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4498 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4499 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4500 DAG); 4501 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4502 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4503 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 4504 EVT MiddleVT = MVT::v4i32; 4505 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4506 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4507 Subtarget->hasSSE2(), DAG); 4508 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 4509 } 4510 } 4511 4512 // Is it a vector logical left shift? 4513 if (NumElems == 2 && Idx == 1 && 4514 X86::isZeroNode(Op.getOperand(0)) && 4515 !X86::isZeroNode(Op.getOperand(1))) { 4516 unsigned NumBits = VT.getSizeInBits(); 4517 return getVShift(true, VT, 4518 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4519 VT, Op.getOperand(1)), 4520 NumBits/2, DAG, *this, dl); 4521 } 4522 4523 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4524 return SDValue(); 4525 4526 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4527 // is a non-constant being inserted into an element other than the low one, 4528 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4529 // movd/movss) to move this into the low element, then shuffle it into 4530 // place. 4531 if (EVTBits == 32) { 4532 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4533 4534 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4535 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4536 Subtarget->hasSSE2(), DAG); 4537 SmallVector<int, 8> MaskVec; 4538 for (unsigned i = 0; i < NumElems; i++) 4539 MaskVec.push_back(i == Idx ? 0 : 1); 4540 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4541 } 4542 } 4543 4544 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4545 if (Values.size() == 1) { 4546 if (EVTBits == 32) { 4547 // Instead of a shuffle like this: 4548 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4549 // Check if it's possible to issue this instead. 4550 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4551 unsigned Idx = CountTrailingZeros_32(NonZeros); 4552 SDValue Item = Op.getOperand(Idx); 4553 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4554 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4555 } 4556 return SDValue(); 4557 } 4558 4559 // A vector full of immediates; various special cases are already 4560 // handled, so this is best done with a single constant-pool load. 4561 if (IsAllConstants) 4562 return SDValue(); 4563 4564 // Let legalizer expand 2-wide build_vectors. 4565 if (EVTBits == 64) { 4566 if (NumNonZero == 1) { 4567 // One half is zero or undef. 4568 unsigned Idx = CountTrailingZeros_32(NonZeros); 4569 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4570 Op.getOperand(Idx)); 4571 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4572 Subtarget->hasSSE2(), DAG); 4573 } 4574 return SDValue(); 4575 } 4576 4577 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4578 if (EVTBits == 8 && NumElems == 16) { 4579 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4580 *this); 4581 if (V.getNode()) return V; 4582 } 4583 4584 if (EVTBits == 16 && NumElems == 8) { 4585 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4586 *this); 4587 if (V.getNode()) return V; 4588 } 4589 4590 // If element VT is == 32 bits, turn it into a number of shuffles. 4591 SmallVector<SDValue, 8> V; 4592 V.resize(NumElems); 4593 if (NumElems == 4 && NumZero > 0) { 4594 for (unsigned i = 0; i < 4; ++i) { 4595 bool isZero = !(NonZeros & (1 << i)); 4596 if (isZero) 4597 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4598 else 4599 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4600 } 4601 4602 for (unsigned i = 0; i < 2; ++i) { 4603 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4604 default: break; 4605 case 0: 4606 V[i] = V[i*2]; // Must be a zero vector. 4607 break; 4608 case 1: 4609 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4610 break; 4611 case 2: 4612 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4613 break; 4614 case 3: 4615 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4616 break; 4617 } 4618 } 4619 4620 SmallVector<int, 8> MaskVec; 4621 bool Reverse = (NonZeros & 0x3) == 2; 4622 for (unsigned i = 0; i < 2; ++i) 4623 MaskVec.push_back(Reverse ? 1-i : i); 4624 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4625 for (unsigned i = 0; i < 2; ++i) 4626 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4627 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4628 } 4629 4630 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4631 // Check for a build vector of consecutive loads. 4632 for (unsigned i = 0; i < NumElems; ++i) 4633 V[i] = Op.getOperand(i); 4634 4635 // Check for elements which are consecutive loads. 4636 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4637 if (LD.getNode()) 4638 return LD; 4639 4640 // For SSE 4.1, use insertps to put the high elements into the low element. 4641 if (getSubtarget()->hasSSE41()) { 4642 SDValue Result; 4643 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4644 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4645 else 4646 Result = DAG.getUNDEF(VT); 4647 4648 for (unsigned i = 1; i < NumElems; ++i) { 4649 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4650 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4651 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4652 } 4653 return Result; 4654 } 4655 4656 // Otherwise, expand into a number of unpckl*, start by extending each of 4657 // our (non-undef) elements to the full vector width with the element in the 4658 // bottom slot of the vector (which generates no code for SSE). 4659 for (unsigned i = 0; i < NumElems; ++i) { 4660 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4661 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4662 else 4663 V[i] = DAG.getUNDEF(VT); 4664 } 4665 4666 // Next, we iteratively mix elements, e.g. for v4f32: 4667 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 4668 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 4669 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 4670 unsigned EltStride = NumElems >> 1; 4671 while (EltStride != 0) { 4672 for (unsigned i = 0; i < EltStride; ++i) { 4673 // If V[i+EltStride] is undef and this is the first round of mixing, 4674 // then it is safe to just drop this shuffle: V[i] is already in the 4675 // right place, the one element (since it's the first round) being 4676 // inserted as undef can be dropped. This isn't safe for successive 4677 // rounds because they will permute elements within both vectors. 4678 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 4679 EltStride == NumElems/2) 4680 continue; 4681 4682 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 4683 } 4684 EltStride >>= 1; 4685 } 4686 return V[0]; 4687 } 4688 return SDValue(); 4689} 4690 4691SDValue 4692X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 4693 // We support concatenate two MMX registers and place them in a MMX 4694 // register. This is better than doing a stack convert. 4695 DebugLoc dl = Op.getDebugLoc(); 4696 EVT ResVT = Op.getValueType(); 4697 assert(Op.getNumOperands() == 2); 4698 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 4699 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 4700 int Mask[2]; 4701 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 4702 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4703 InVec = Op.getOperand(1); 4704 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4705 unsigned NumElts = ResVT.getVectorNumElements(); 4706 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 4707 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 4708 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 4709 } else { 4710 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 4711 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4712 Mask[0] = 0; Mask[1] = 2; 4713 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 4714 } 4715 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 4716} 4717 4718// v8i16 shuffles - Prefer shuffles in the following order: 4719// 1. [all] pshuflw, pshufhw, optional move 4720// 2. [ssse3] 1 x pshufb 4721// 3. [ssse3] 2 x pshufb + 1 x por 4722// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4723SDValue 4724X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 4725 SelectionDAG &DAG) const { 4726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4727 SDValue V1 = SVOp->getOperand(0); 4728 SDValue V2 = SVOp->getOperand(1); 4729 DebugLoc dl = SVOp->getDebugLoc(); 4730 SmallVector<int, 8> MaskVals; 4731 4732 // Determine if more than 1 of the words in each of the low and high quadwords 4733 // of the result come from the same quadword of one of the two inputs. Undef 4734 // mask values count as coming from any quadword, for better codegen. 4735 SmallVector<unsigned, 4> LoQuad(4); 4736 SmallVector<unsigned, 4> HiQuad(4); 4737 BitVector InputQuads(4); 4738 for (unsigned i = 0; i < 8; ++i) { 4739 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4740 int EltIdx = SVOp->getMaskElt(i); 4741 MaskVals.push_back(EltIdx); 4742 if (EltIdx < 0) { 4743 ++Quad[0]; 4744 ++Quad[1]; 4745 ++Quad[2]; 4746 ++Quad[3]; 4747 continue; 4748 } 4749 ++Quad[EltIdx / 4]; 4750 InputQuads.set(EltIdx / 4); 4751 } 4752 4753 int BestLoQuad = -1; 4754 unsigned MaxQuad = 1; 4755 for (unsigned i = 0; i < 4; ++i) { 4756 if (LoQuad[i] > MaxQuad) { 4757 BestLoQuad = i; 4758 MaxQuad = LoQuad[i]; 4759 } 4760 } 4761 4762 int BestHiQuad = -1; 4763 MaxQuad = 1; 4764 for (unsigned i = 0; i < 4; ++i) { 4765 if (HiQuad[i] > MaxQuad) { 4766 BestHiQuad = i; 4767 MaxQuad = HiQuad[i]; 4768 } 4769 } 4770 4771 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4772 // of the two input vectors, shuffle them into one input vector so only a 4773 // single pshufb instruction is necessary. If There are more than 2 input 4774 // quads, disable the next transformation since it does not help SSSE3. 4775 bool V1Used = InputQuads[0] || InputQuads[1]; 4776 bool V2Used = InputQuads[2] || InputQuads[3]; 4777 if (Subtarget->hasSSSE3()) { 4778 if (InputQuads.count() == 2 && V1Used && V2Used) { 4779 BestLoQuad = InputQuads.find_first(); 4780 BestHiQuad = InputQuads.find_next(BestLoQuad); 4781 } 4782 if (InputQuads.count() > 2) { 4783 BestLoQuad = -1; 4784 BestHiQuad = -1; 4785 } 4786 } 4787 4788 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4789 // the shuffle mask. If a quad is scored as -1, that means that it contains 4790 // words from all 4 input quadwords. 4791 SDValue NewV; 4792 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4793 SmallVector<int, 8> MaskV; 4794 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4795 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4796 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4797 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 4798 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 4799 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 4800 4801 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4802 // source words for the shuffle, to aid later transformations. 4803 bool AllWordsInNewV = true; 4804 bool InOrder[2] = { true, true }; 4805 for (unsigned i = 0; i != 8; ++i) { 4806 int idx = MaskVals[i]; 4807 if (idx != (int)i) 4808 InOrder[i/4] = false; 4809 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4810 continue; 4811 AllWordsInNewV = false; 4812 break; 4813 } 4814 4815 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4816 if (AllWordsInNewV) { 4817 for (int i = 0; i != 8; ++i) { 4818 int idx = MaskVals[i]; 4819 if (idx < 0) 4820 continue; 4821 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4822 if ((idx != i) && idx < 4) 4823 pshufhw = false; 4824 if ((idx != i) && idx > 3) 4825 pshuflw = false; 4826 } 4827 V1 = NewV; 4828 V2Used = false; 4829 BestLoQuad = 0; 4830 BestHiQuad = 1; 4831 } 4832 4833 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4834 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4835 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4836 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 4837 unsigned TargetMask = 0; 4838 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4839 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4840 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 4841 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 4842 V1 = NewV.getOperand(0); 4843 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 4844 } 4845 } 4846 4847 // If we have SSSE3, and all words of the result are from 1 input vector, 4848 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4849 // is present, fall back to case 4. 4850 if (Subtarget->hasSSSE3()) { 4851 SmallVector<SDValue,16> pshufbMask; 4852 4853 // If we have elements from both input vectors, set the high bit of the 4854 // shuffle mask element to zero out elements that come from V2 in the V1 4855 // mask, and elements that come from V1 in the V2 mask, so that the two 4856 // results can be OR'd together. 4857 bool TwoInputs = V1Used && V2Used; 4858 for (unsigned i = 0; i != 8; ++i) { 4859 int EltIdx = MaskVals[i] * 2; 4860 if (TwoInputs && (EltIdx >= 16)) { 4861 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4862 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4863 continue; 4864 } 4865 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4866 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4867 } 4868 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 4869 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4870 DAG.getNode(ISD::BUILD_VECTOR, dl, 4871 MVT::v16i8, &pshufbMask[0], 16)); 4872 if (!TwoInputs) 4873 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 4874 4875 // Calculate the shuffle mask for the second input, shuffle it, and 4876 // OR it with the first shuffled input. 4877 pshufbMask.clear(); 4878 for (unsigned i = 0; i != 8; ++i) { 4879 int EltIdx = MaskVals[i] * 2; 4880 if (EltIdx < 16) { 4881 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4882 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4883 continue; 4884 } 4885 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4886 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4887 } 4888 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 4889 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4890 DAG.getNode(ISD::BUILD_VECTOR, dl, 4891 MVT::v16i8, &pshufbMask[0], 16)); 4892 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4893 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 4894 } 4895 4896 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4897 // and update MaskVals with new element order. 4898 BitVector InOrder(8); 4899 if (BestLoQuad >= 0) { 4900 SmallVector<int, 8> MaskV; 4901 for (int i = 0; i != 4; ++i) { 4902 int idx = MaskVals[i]; 4903 if (idx < 0) { 4904 MaskV.push_back(-1); 4905 InOrder.set(i); 4906 } else if ((idx / 4) == BestLoQuad) { 4907 MaskV.push_back(idx & 3); 4908 InOrder.set(i); 4909 } else { 4910 MaskV.push_back(-1); 4911 } 4912 } 4913 for (unsigned i = 4; i != 8; ++i) 4914 MaskV.push_back(i); 4915 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4916 &MaskV[0]); 4917 4918 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4919 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 4920 NewV.getOperand(0), 4921 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 4922 DAG); 4923 } 4924 4925 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4926 // and update MaskVals with the new element order. 4927 if (BestHiQuad >= 0) { 4928 SmallVector<int, 8> MaskV; 4929 for (unsigned i = 0; i != 4; ++i) 4930 MaskV.push_back(i); 4931 for (unsigned i = 4; i != 8; ++i) { 4932 int idx = MaskVals[i]; 4933 if (idx < 0) { 4934 MaskV.push_back(-1); 4935 InOrder.set(i); 4936 } else if ((idx / 4) == BestHiQuad) { 4937 MaskV.push_back((idx & 3) + 4); 4938 InOrder.set(i); 4939 } else { 4940 MaskV.push_back(-1); 4941 } 4942 } 4943 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4944 &MaskV[0]); 4945 4946 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4947 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 4948 NewV.getOperand(0), 4949 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 4950 DAG); 4951 } 4952 4953 // In case BestHi & BestLo were both -1, which means each quadword has a word 4954 // from each of the four input quadwords, calculate the InOrder bitvector now 4955 // before falling through to the insert/extract cleanup. 4956 if (BestLoQuad == -1 && BestHiQuad == -1) { 4957 NewV = V1; 4958 for (int i = 0; i != 8; ++i) 4959 if (MaskVals[i] < 0 || MaskVals[i] == i) 4960 InOrder.set(i); 4961 } 4962 4963 // The other elements are put in the right place using pextrw and pinsrw. 4964 for (unsigned i = 0; i != 8; ++i) { 4965 if (InOrder[i]) 4966 continue; 4967 int EltIdx = MaskVals[i]; 4968 if (EltIdx < 0) 4969 continue; 4970 SDValue ExtOp = (EltIdx < 8) 4971 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4972 DAG.getIntPtrConstant(EltIdx)) 4973 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4974 DAG.getIntPtrConstant(EltIdx - 8)); 4975 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4976 DAG.getIntPtrConstant(i)); 4977 } 4978 return NewV; 4979} 4980 4981// v16i8 shuffles - Prefer shuffles in the following order: 4982// 1. [ssse3] 1 x pshufb 4983// 2. [ssse3] 2 x pshufb + 1 x por 4984// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4985static 4986SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4987 SelectionDAG &DAG, 4988 const X86TargetLowering &TLI) { 4989 SDValue V1 = SVOp->getOperand(0); 4990 SDValue V2 = SVOp->getOperand(1); 4991 DebugLoc dl = SVOp->getDebugLoc(); 4992 SmallVector<int, 16> MaskVals; 4993 SVOp->getMask(MaskVals); 4994 4995 // If we have SSSE3, case 1 is generated when all result bytes come from 4996 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4997 // present, fall back to case 3. 4998 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4999 bool V1Only = true; 5000 bool V2Only = true; 5001 for (unsigned i = 0; i < 16; ++i) { 5002 int EltIdx = MaskVals[i]; 5003 if (EltIdx < 0) 5004 continue; 5005 if (EltIdx < 16) 5006 V2Only = false; 5007 else 5008 V1Only = false; 5009 } 5010 5011 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5012 if (TLI.getSubtarget()->hasSSSE3()) { 5013 SmallVector<SDValue,16> pshufbMask; 5014 5015 // If all result elements are from one input vector, then only translate 5016 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5017 // 5018 // Otherwise, we have elements from both input vectors, and must zero out 5019 // elements that come from V2 in the first mask, and V1 in the second mask 5020 // so that we can OR them together. 5021 bool TwoInputs = !(V1Only || V2Only); 5022 for (unsigned i = 0; i != 16; ++i) { 5023 int EltIdx = MaskVals[i]; 5024 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5025 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5026 continue; 5027 } 5028 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5029 } 5030 // If all the elements are from V2, assign it to V1 and return after 5031 // building the first pshufb. 5032 if (V2Only) 5033 V1 = V2; 5034 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5035 DAG.getNode(ISD::BUILD_VECTOR, dl, 5036 MVT::v16i8, &pshufbMask[0], 16)); 5037 if (!TwoInputs) 5038 return V1; 5039 5040 // Calculate the shuffle mask for the second input, shuffle it, and 5041 // OR it with the first shuffled input. 5042 pshufbMask.clear(); 5043 for (unsigned i = 0; i != 16; ++i) { 5044 int EltIdx = MaskVals[i]; 5045 if (EltIdx < 16) { 5046 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5047 continue; 5048 } 5049 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5050 } 5051 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5052 DAG.getNode(ISD::BUILD_VECTOR, dl, 5053 MVT::v16i8, &pshufbMask[0], 16)); 5054 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5055 } 5056 5057 // No SSSE3 - Calculate in place words and then fix all out of place words 5058 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5059 // the 16 different words that comprise the two doublequadword input vectors. 5060 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5061 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5062 SDValue NewV = V2Only ? V2 : V1; 5063 for (int i = 0; i != 8; ++i) { 5064 int Elt0 = MaskVals[i*2]; 5065 int Elt1 = MaskVals[i*2+1]; 5066 5067 // This word of the result is all undef, skip it. 5068 if (Elt0 < 0 && Elt1 < 0) 5069 continue; 5070 5071 // This word of the result is already in the correct place, skip it. 5072 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5073 continue; 5074 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5075 continue; 5076 5077 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5078 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5079 SDValue InsElt; 5080 5081 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5082 // using a single extract together, load it and store it. 5083 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5084 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5085 DAG.getIntPtrConstant(Elt1 / 2)); 5086 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5087 DAG.getIntPtrConstant(i)); 5088 continue; 5089 } 5090 5091 // If Elt1 is defined, extract it from the appropriate source. If the 5092 // source byte is not also odd, shift the extracted word left 8 bits 5093 // otherwise clear the bottom 8 bits if we need to do an or. 5094 if (Elt1 >= 0) { 5095 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5096 DAG.getIntPtrConstant(Elt1 / 2)); 5097 if ((Elt1 & 1) == 0) 5098 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5099 DAG.getConstant(8, 5100 TLI.getShiftAmountTy(InsElt.getValueType()))); 5101 else if (Elt0 >= 0) 5102 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5103 DAG.getConstant(0xFF00, MVT::i16)); 5104 } 5105 // If Elt0 is defined, extract it from the appropriate source. If the 5106 // source byte is not also even, shift the extracted word right 8 bits. If 5107 // Elt1 was also defined, OR the extracted values together before 5108 // inserting them in the result. 5109 if (Elt0 >= 0) { 5110 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5111 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5112 if ((Elt0 & 1) != 0) 5113 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5114 DAG.getConstant(8, 5115 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5116 else if (Elt1 >= 0) 5117 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5118 DAG.getConstant(0x00FF, MVT::i16)); 5119 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5120 : InsElt0; 5121 } 5122 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5123 DAG.getIntPtrConstant(i)); 5124 } 5125 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5126} 5127 5128/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5129/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5130/// done when every pair / quad of shuffle mask elements point to elements in 5131/// the right sequence. e.g. 5132/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5133static 5134SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5135 SelectionDAG &DAG, DebugLoc dl) { 5136 EVT VT = SVOp->getValueType(0); 5137 SDValue V1 = SVOp->getOperand(0); 5138 SDValue V2 = SVOp->getOperand(1); 5139 unsigned NumElems = VT.getVectorNumElements(); 5140 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5141 EVT NewVT; 5142 switch (VT.getSimpleVT().SimpleTy) { 5143 default: assert(false && "Unexpected!"); 5144 case MVT::v4f32: NewVT = MVT::v2f64; break; 5145 case MVT::v4i32: NewVT = MVT::v2i64; break; 5146 case MVT::v8i16: NewVT = MVT::v4i32; break; 5147 case MVT::v16i8: NewVT = MVT::v4i32; break; 5148 } 5149 5150 int Scale = NumElems / NewWidth; 5151 SmallVector<int, 8> MaskVec; 5152 for (unsigned i = 0; i < NumElems; i += Scale) { 5153 int StartIdx = -1; 5154 for (int j = 0; j < Scale; ++j) { 5155 int EltIdx = SVOp->getMaskElt(i+j); 5156 if (EltIdx < 0) 5157 continue; 5158 if (StartIdx == -1) 5159 StartIdx = EltIdx - (EltIdx % Scale); 5160 if (EltIdx != StartIdx + j) 5161 return SDValue(); 5162 } 5163 if (StartIdx == -1) 5164 MaskVec.push_back(-1); 5165 else 5166 MaskVec.push_back(StartIdx / Scale); 5167 } 5168 5169 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5170 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5171 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5172} 5173 5174/// getVZextMovL - Return a zero-extending vector move low node. 5175/// 5176static SDValue getVZextMovL(EVT VT, EVT OpVT, 5177 SDValue SrcOp, SelectionDAG &DAG, 5178 const X86Subtarget *Subtarget, DebugLoc dl) { 5179 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5180 LoadSDNode *LD = NULL; 5181 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5182 LD = dyn_cast<LoadSDNode>(SrcOp); 5183 if (!LD) { 5184 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5185 // instead. 5186 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5187 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5188 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5189 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5190 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5191 // PR2108 5192 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5193 return DAG.getNode(ISD::BITCAST, dl, VT, 5194 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5195 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5196 OpVT, 5197 SrcOp.getOperand(0) 5198 .getOperand(0)))); 5199 } 5200 } 5201 } 5202 5203 return DAG.getNode(ISD::BITCAST, dl, VT, 5204 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5205 DAG.getNode(ISD::BITCAST, dl, 5206 OpVT, SrcOp))); 5207} 5208 5209/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 5210/// shuffles. 5211static SDValue 5212LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5213 SDValue V1 = SVOp->getOperand(0); 5214 SDValue V2 = SVOp->getOperand(1); 5215 DebugLoc dl = SVOp->getDebugLoc(); 5216 EVT VT = SVOp->getValueType(0); 5217 5218 SmallVector<std::pair<int, int>, 8> Locs; 5219 Locs.resize(4); 5220 SmallVector<int, 8> Mask1(4U, -1); 5221 SmallVector<int, 8> PermMask; 5222 SVOp->getMask(PermMask); 5223 5224 unsigned NumHi = 0; 5225 unsigned NumLo = 0; 5226 for (unsigned i = 0; i != 4; ++i) { 5227 int Idx = PermMask[i]; 5228 if (Idx < 0) { 5229 Locs[i] = std::make_pair(-1, -1); 5230 } else { 5231 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5232 if (Idx < 4) { 5233 Locs[i] = std::make_pair(0, NumLo); 5234 Mask1[NumLo] = Idx; 5235 NumLo++; 5236 } else { 5237 Locs[i] = std::make_pair(1, NumHi); 5238 if (2+NumHi < 4) 5239 Mask1[2+NumHi] = Idx; 5240 NumHi++; 5241 } 5242 } 5243 } 5244 5245 if (NumLo <= 2 && NumHi <= 2) { 5246 // If no more than two elements come from either vector. This can be 5247 // implemented with two shuffles. First shuffle gather the elements. 5248 // The second shuffle, which takes the first shuffle as both of its 5249 // vector operands, put the elements into the right order. 5250 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5251 5252 SmallVector<int, 8> Mask2(4U, -1); 5253 5254 for (unsigned i = 0; i != 4; ++i) { 5255 if (Locs[i].first == -1) 5256 continue; 5257 else { 5258 unsigned Idx = (i < 2) ? 0 : 4; 5259 Idx += Locs[i].first * 2 + Locs[i].second; 5260 Mask2[i] = Idx; 5261 } 5262 } 5263 5264 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 5265 } else if (NumLo == 3 || NumHi == 3) { 5266 // Otherwise, we must have three elements from one vector, call it X, and 5267 // one element from the other, call it Y. First, use a shufps to build an 5268 // intermediate vector with the one element from Y and the element from X 5269 // that will be in the same half in the final destination (the indexes don't 5270 // matter). Then, use a shufps to build the final vector, taking the half 5271 // containing the element from Y from the intermediate, and the other half 5272 // from X. 5273 if (NumHi == 3) { 5274 // Normalize it so the 3 elements come from V1. 5275 CommuteVectorShuffleMask(PermMask, VT); 5276 std::swap(V1, V2); 5277 } 5278 5279 // Find the element from V2. 5280 unsigned HiIndex; 5281 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 5282 int Val = PermMask[HiIndex]; 5283 if (Val < 0) 5284 continue; 5285 if (Val >= 4) 5286 break; 5287 } 5288 5289 Mask1[0] = PermMask[HiIndex]; 5290 Mask1[1] = -1; 5291 Mask1[2] = PermMask[HiIndex^1]; 5292 Mask1[3] = -1; 5293 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5294 5295 if (HiIndex >= 2) { 5296 Mask1[0] = PermMask[0]; 5297 Mask1[1] = PermMask[1]; 5298 Mask1[2] = HiIndex & 1 ? 6 : 4; 5299 Mask1[3] = HiIndex & 1 ? 4 : 6; 5300 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5301 } else { 5302 Mask1[0] = HiIndex & 1 ? 2 : 0; 5303 Mask1[1] = HiIndex & 1 ? 0 : 2; 5304 Mask1[2] = PermMask[2]; 5305 Mask1[3] = PermMask[3]; 5306 if (Mask1[2] >= 0) 5307 Mask1[2] += 4; 5308 if (Mask1[3] >= 0) 5309 Mask1[3] += 4; 5310 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 5311 } 5312 } 5313 5314 // Break it into (shuffle shuffle_hi, shuffle_lo). 5315 Locs.clear(); 5316 Locs.resize(4); 5317 SmallVector<int,8> LoMask(4U, -1); 5318 SmallVector<int,8> HiMask(4U, -1); 5319 5320 SmallVector<int,8> *MaskPtr = &LoMask; 5321 unsigned MaskIdx = 0; 5322 unsigned LoIdx = 0; 5323 unsigned HiIdx = 2; 5324 for (unsigned i = 0; i != 4; ++i) { 5325 if (i == 2) { 5326 MaskPtr = &HiMask; 5327 MaskIdx = 1; 5328 LoIdx = 0; 5329 HiIdx = 2; 5330 } 5331 int Idx = PermMask[i]; 5332 if (Idx < 0) { 5333 Locs[i] = std::make_pair(-1, -1); 5334 } else if (Idx < 4) { 5335 Locs[i] = std::make_pair(MaskIdx, LoIdx); 5336 (*MaskPtr)[LoIdx] = Idx; 5337 LoIdx++; 5338 } else { 5339 Locs[i] = std::make_pair(MaskIdx, HiIdx); 5340 (*MaskPtr)[HiIdx] = Idx; 5341 HiIdx++; 5342 } 5343 } 5344 5345 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 5346 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 5347 SmallVector<int, 8> MaskOps; 5348 for (unsigned i = 0; i != 4; ++i) { 5349 if (Locs[i].first == -1) { 5350 MaskOps.push_back(-1); 5351 } else { 5352 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5353 MaskOps.push_back(Idx); 5354 } 5355 } 5356 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5357} 5358 5359static bool MayFoldVectorLoad(SDValue V) { 5360 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5361 V = V.getOperand(0); 5362 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5363 V = V.getOperand(0); 5364 if (MayFoldLoad(V)) 5365 return true; 5366 return false; 5367} 5368 5369// FIXME: the version above should always be used. Since there's 5370// a bug where several vector shuffles can't be folded because the 5371// DAG is not updated during lowering and a node claims to have two 5372// uses while it only has one, use this version, and let isel match 5373// another instruction if the load really happens to have more than 5374// one use. Remove this version after this bug get fixed. 5375// rdar://8434668, PR8156 5376static bool RelaxedMayFoldVectorLoad(SDValue V) { 5377 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5378 V = V.getOperand(0); 5379 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5380 V = V.getOperand(0); 5381 if (ISD::isNormalLoad(V.getNode())) 5382 return true; 5383 return false; 5384} 5385 5386/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 5387/// a vector extract, and if both can be later optimized into a single load. 5388/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 5389/// here because otherwise a target specific shuffle node is going to be 5390/// emitted for this shuffle, and the optimization not done. 5391/// FIXME: This is probably not the best approach, but fix the problem 5392/// until the right path is decided. 5393static 5394bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 5395 const TargetLowering &TLI) { 5396 EVT VT = V.getValueType(); 5397 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 5398 5399 // Be sure that the vector shuffle is present in a pattern like this: 5400 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 5401 if (!V.hasOneUse()) 5402 return false; 5403 5404 SDNode *N = *V.getNode()->use_begin(); 5405 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 5406 return false; 5407 5408 SDValue EltNo = N->getOperand(1); 5409 if (!isa<ConstantSDNode>(EltNo)) 5410 return false; 5411 5412 // If the bit convert changed the number of elements, it is unsafe 5413 // to examine the mask. 5414 bool HasShuffleIntoBitcast = false; 5415 if (V.getOpcode() == ISD::BITCAST) { 5416 EVT SrcVT = V.getOperand(0).getValueType(); 5417 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 5418 return false; 5419 V = V.getOperand(0); 5420 HasShuffleIntoBitcast = true; 5421 } 5422 5423 // Select the input vector, guarding against out of range extract vector. 5424 unsigned NumElems = VT.getVectorNumElements(); 5425 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5426 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 5427 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 5428 5429 // Skip one more bit_convert if necessary 5430 if (V.getOpcode() == ISD::BITCAST) 5431 V = V.getOperand(0); 5432 5433 if (ISD::isNormalLoad(V.getNode())) { 5434 // Is the original load suitable? 5435 LoadSDNode *LN0 = cast<LoadSDNode>(V); 5436 5437 // FIXME: avoid the multi-use bug that is preventing lots of 5438 // of foldings to be detected, this is still wrong of course, but 5439 // give the temporary desired behavior, and if it happens that 5440 // the load has real more uses, during isel it will not fold, and 5441 // will generate poor code. 5442 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 5443 return false; 5444 5445 if (!HasShuffleIntoBitcast) 5446 return true; 5447 5448 // If there's a bitcast before the shuffle, check if the load type and 5449 // alignment is valid. 5450 unsigned Align = LN0->getAlignment(); 5451 unsigned NewAlign = 5452 TLI.getTargetData()->getABITypeAlignment( 5453 VT.getTypeForEVT(*DAG.getContext())); 5454 5455 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 5456 return false; 5457 } 5458 5459 return true; 5460} 5461 5462static 5463SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 5464 EVT VT = Op.getValueType(); 5465 5466 // Canonizalize to v2f64. 5467 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 5468 return DAG.getNode(ISD::BITCAST, dl, VT, 5469 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 5470 V1, DAG)); 5471} 5472 5473static 5474SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5475 bool HasSSE2) { 5476 SDValue V1 = Op.getOperand(0); 5477 SDValue V2 = Op.getOperand(1); 5478 EVT VT = Op.getValueType(); 5479 5480 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5481 5482 if (HasSSE2 && VT == MVT::v2f64) 5483 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5484 5485 // v4f32 or v4i32 5486 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5487} 5488 5489static 5490SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 5491 SDValue V1 = Op.getOperand(0); 5492 SDValue V2 = Op.getOperand(1); 5493 EVT VT = Op.getValueType(); 5494 5495 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 5496 "unsupported shuffle type"); 5497 5498 if (V2.getOpcode() == ISD::UNDEF) 5499 V2 = V1; 5500 5501 // v4i32 or v4f32 5502 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 5503} 5504 5505static 5506SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 5507 SDValue V1 = Op.getOperand(0); 5508 SDValue V2 = Op.getOperand(1); 5509 EVT VT = Op.getValueType(); 5510 unsigned NumElems = VT.getVectorNumElements(); 5511 5512 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 5513 // operand of these instructions is only memory, so check if there's a 5514 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 5515 // same masks. 5516 bool CanFoldLoad = false; 5517 5518 // Trivial case, when V2 comes from a load. 5519 if (MayFoldVectorLoad(V2)) 5520 CanFoldLoad = true; 5521 5522 // When V1 is a load, it can be folded later into a store in isel, example: 5523 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 5524 // turns into: 5525 // (MOVLPSmr addr:$src1, VR128:$src2) 5526 // So, recognize this potential and also use MOVLPS or MOVLPD 5527 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 5528 CanFoldLoad = true; 5529 5530 // Both of them can't be memory operations though. 5531 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 5532 CanFoldLoad = false; 5533 5534 if (CanFoldLoad) { 5535 if (HasSSE2 && NumElems == 2) 5536 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 5537 5538 if (NumElems == 4) 5539 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 5540 } 5541 5542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5543 // movl and movlp will both match v2i64, but v2i64 is never matched by 5544 // movl earlier because we make it strict to avoid messing with the movlp load 5545 // folding logic (see the code above getMOVLP call). Match it here then, 5546 // this is horrible, but will stay like this until we move all shuffle 5547 // matching to x86 specific nodes. Note that for the 1st condition all 5548 // types are matched with movsd. 5549 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) 5550 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5551 else if (HasSSE2) 5552 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5553 5554 5555 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 5556 5557 // Invert the operand order and use SHUFPS to match it. 5558 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, 5559 X86::getShuffleSHUFImmediate(SVOp), DAG); 5560} 5561 5562static inline unsigned getUNPCKLOpcode(EVT VT, const X86Subtarget *Subtarget) { 5563 switch(VT.getSimpleVT().SimpleTy) { 5564 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 5565 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 5566 case MVT::v4f32: 5567 return Subtarget->hasAVX() ? X86ISD::VUNPCKLPS : X86ISD::UNPCKLPS; 5568 case MVT::v2f64: 5569 return Subtarget->hasAVX() ? X86ISD::VUNPCKLPD : X86ISD::UNPCKLPD; 5570 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 5571 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 5572 case MVT::v16i8: return X86ISD::PUNPCKLBW; 5573 case MVT::v8i16: return X86ISD::PUNPCKLWD; 5574 default: 5575 llvm_unreachable("Unknown type for unpckl"); 5576 } 5577 return 0; 5578} 5579 5580static inline unsigned getUNPCKHOpcode(EVT VT) { 5581 switch(VT.getSimpleVT().SimpleTy) { 5582 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 5583 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 5584 case MVT::v4f32: return X86ISD::UNPCKHPS; 5585 case MVT::v2f64: return X86ISD::UNPCKHPD; 5586 case MVT::v16i8: return X86ISD::PUNPCKHBW; 5587 case MVT::v8i16: return X86ISD::PUNPCKHWD; 5588 default: 5589 llvm_unreachable("Unknown type for unpckh"); 5590 } 5591 return 0; 5592} 5593 5594static 5595SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 5596 const TargetLowering &TLI, 5597 const X86Subtarget *Subtarget) { 5598 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5599 EVT VT = Op.getValueType(); 5600 DebugLoc dl = Op.getDebugLoc(); 5601 SDValue V1 = Op.getOperand(0); 5602 SDValue V2 = Op.getOperand(1); 5603 5604 if (isZeroShuffle(SVOp)) 5605 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5606 5607 // Handle splat operations 5608 if (SVOp->isSplat()) { 5609 // Special case, this is the only place now where it's 5610 // allowed to return a vector_shuffle operation without 5611 // using a target specific node, because *hopefully* it 5612 // will be optimized away by the dag combiner. 5613 if (VT.getVectorNumElements() <= 4 && 5614 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 5615 return Op; 5616 5617 // Handle splats by matching through known masks 5618 if (VT.getVectorNumElements() <= 4) 5619 return SDValue(); 5620 5621 // Canonicalize all of the remaining to v4f32. 5622 return PromoteSplat(SVOp, DAG); 5623 } 5624 5625 // If the shuffle can be profitably rewritten as a narrower shuffle, then 5626 // do it! 5627 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 5628 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5629 if (NewOp.getNode()) 5630 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 5631 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 5632 // FIXME: Figure out a cleaner way to do this. 5633 // Try to make use of movq to zero out the top part. 5634 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 5635 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5636 if (NewOp.getNode()) { 5637 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 5638 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 5639 DAG, Subtarget, dl); 5640 } 5641 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 5642 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 5643 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 5644 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 5645 DAG, Subtarget, dl); 5646 } 5647 } 5648 return SDValue(); 5649} 5650 5651SDValue 5652X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 5653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5654 SDValue V1 = Op.getOperand(0); 5655 SDValue V2 = Op.getOperand(1); 5656 EVT VT = Op.getValueType(); 5657 DebugLoc dl = Op.getDebugLoc(); 5658 unsigned NumElems = VT.getVectorNumElements(); 5659 bool isMMX = VT.getSizeInBits() == 64; 5660 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 5661 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 5662 bool V1IsSplat = false; 5663 bool V2IsSplat = false; 5664 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 5665 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 5666 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); 5667 MachineFunction &MF = DAG.getMachineFunction(); 5668 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 5669 5670 // Shuffle operations on MMX not supported. 5671 if (isMMX) 5672 return Op; 5673 5674 // Vector shuffle lowering takes 3 steps: 5675 // 5676 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 5677 // narrowing and commutation of operands should be handled. 5678 // 2) Matching of shuffles with known shuffle masks to x86 target specific 5679 // shuffle nodes. 5680 // 3) Rewriting of unmatched masks into new generic shuffle operations, 5681 // so the shuffle can be broken into other shuffles and the legalizer can 5682 // try the lowering again. 5683 // 5684 // The general ideia is that no vector_shuffle operation should be left to 5685 // be matched during isel, all of them must be converted to a target specific 5686 // node here. 5687 5688 // Normalize the input vectors. Here splats, zeroed vectors, profitable 5689 // narrowing and commutation of operands should be handled. The actual code 5690 // doesn't include all of those, work in progress... 5691 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 5692 if (NewOp.getNode()) 5693 return NewOp; 5694 5695 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 5696 // unpckh_undef). Only use pshufd if speed is more important than size. 5697 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 5698 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5699 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), dl, VT, V1, V1, DAG); 5700 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 5701 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5702 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5703 5704 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && 5705 RelaxedMayFoldVectorLoad(V1)) 5706 return getMOVDDup(Op, dl, V1, DAG); 5707 5708 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 5709 return getMOVHighToLow(Op, dl, DAG); 5710 5711 // Use to match splats 5712 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && 5713 (VT == MVT::v2f64 || VT == MVT::v2i64)) 5714 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5715 5716 if (X86::isPSHUFDMask(SVOp)) { 5717 // The actual implementation will match the mask in the if above and then 5718 // during isel it can match several different instructions, not only pshufd 5719 // as its name says, sad but true, emulate the behavior for now... 5720 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 5721 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 5722 5723 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5724 5725 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 5726 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 5727 5728 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5729 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 5730 TargetMask, DAG); 5731 5732 if (VT == MVT::v4f32) 5733 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 5734 TargetMask, DAG); 5735 } 5736 5737 // Check if this can be converted into a logical shift. 5738 bool isLeft = false; 5739 unsigned ShAmt = 0; 5740 SDValue ShVal; 5741 bool isShift = getSubtarget()->hasSSE2() && 5742 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 5743 if (isShift && ShVal.hasOneUse()) { 5744 // If the shifted value has multiple uses, it may be cheaper to use 5745 // v_set0 + movlhps or movhlps, etc. 5746 EVT EltVT = VT.getVectorElementType(); 5747 ShAmt *= EltVT.getSizeInBits(); 5748 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5749 } 5750 5751 if (X86::isMOVLMask(SVOp)) { 5752 if (V1IsUndef) 5753 return V2; 5754 if (ISD::isBuildVectorAllZeros(V1.getNode())) 5755 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 5756 if (!X86::isMOVLPMask(SVOp)) { 5757 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5758 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5759 5760 if (VT == MVT::v4i32 || VT == MVT::v4f32) 5761 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5762 } 5763 } 5764 5765 // FIXME: fold these into legal mask. 5766 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 5767 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 5768 5769 if (X86::isMOVHLPSMask(SVOp)) 5770 return getMOVHighToLow(Op, dl, DAG); 5771 5772 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5773 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 5774 5775 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5776 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 5777 5778 if (X86::isMOVLPMask(SVOp)) 5779 return getMOVLP(Op, dl, DAG, HasSSE2); 5780 5781 if (ShouldXformToMOVHLPS(SVOp) || 5782 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 5783 return CommuteVectorShuffle(SVOp, DAG); 5784 5785 if (isShift) { 5786 // No better options. Use a vshl / vsrl. 5787 EVT EltVT = VT.getVectorElementType(); 5788 ShAmt *= EltVT.getSizeInBits(); 5789 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5790 } 5791 5792 bool Commuted = false; 5793 // FIXME: This should also accept a bitcast of a splat? Be careful, not 5794 // 1,1,1,1 -> v8i16 though. 5795 V1IsSplat = isSplatVector(V1.getNode()); 5796 V2IsSplat = isSplatVector(V2.getNode()); 5797 5798 // Canonicalize the splat or undef, if present, to be on the RHS. 5799 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 5800 Op = CommuteVectorShuffle(SVOp, DAG); 5801 SVOp = cast<ShuffleVectorSDNode>(Op); 5802 V1 = SVOp->getOperand(0); 5803 V2 = SVOp->getOperand(1); 5804 std::swap(V1IsSplat, V2IsSplat); 5805 std::swap(V1IsUndef, V2IsUndef); 5806 Commuted = true; 5807 } 5808 5809 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 5810 // Shuffling low element of v1 into undef, just return v1. 5811 if (V2IsUndef) 5812 return V1; 5813 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 5814 // the instruction selector will not match, so get a canonical MOVL with 5815 // swapped operands to undo the commute. 5816 return getMOVL(DAG, dl, VT, V2, V1); 5817 } 5818 5819 if (X86::isUNPCKLMask(SVOp)) 5820 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), 5821 dl, VT, V1, V2, DAG); 5822 5823 if (X86::isUNPCKHMask(SVOp)) 5824 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 5825 5826 if (V2IsSplat) { 5827 // Normalize mask so all entries that point to V2 points to its first 5828 // element then try to match unpck{h|l} again. If match, return a 5829 // new vector_shuffle with the corrected mask. 5830 SDValue NewMask = NormalizeMask(SVOp, DAG); 5831 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 5832 if (NSVOp != SVOp) { 5833 if (X86::isUNPCKLMask(NSVOp, true)) { 5834 return NewMask; 5835 } else if (X86::isUNPCKHMask(NSVOp, true)) { 5836 return NewMask; 5837 } 5838 } 5839 } 5840 5841 if (Commuted) { 5842 // Commute is back and try unpck* again. 5843 // FIXME: this seems wrong. 5844 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 5845 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 5846 5847 if (X86::isUNPCKLMask(NewSVOp)) 5848 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), 5849 dl, VT, V2, V1, DAG); 5850 5851 if (X86::isUNPCKHMask(NewSVOp)) 5852 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 5853 } 5854 5855 // Normalize the node to match x86 shuffle ops if needed 5856 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 5857 return CommuteVectorShuffle(SVOp, DAG); 5858 5859 // The checks below are all present in isShuffleMaskLegal, but they are 5860 // inlined here right now to enable us to directly emit target specific 5861 // nodes, and remove one by one until they don't return Op anymore. 5862 SmallVector<int, 16> M; 5863 SVOp->getMask(M); 5864 5865 if (isPALIGNRMask(M, VT, HasSSSE3)) 5866 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 5867 X86::getShufflePALIGNRImmediate(SVOp), 5868 DAG); 5869 5870 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 5871 SVOp->getSplatIndex() == 0 && V2IsUndef) { 5872 if (VT == MVT::v2f64) { 5873 X86ISD::NodeType Opcode = 5874 getSubtarget()->hasAVX() ? X86ISD::VUNPCKLPD : X86ISD::UNPCKLPD; 5875 return getTargetShuffleNode(Opcode, dl, VT, V1, V1, DAG); 5876 } 5877 if (VT == MVT::v2i64) 5878 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 5879 } 5880 5881 if (isPSHUFHWMask(M, VT)) 5882 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 5883 X86::getShufflePSHUFHWImmediate(SVOp), 5884 DAG); 5885 5886 if (isPSHUFLWMask(M, VT)) 5887 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 5888 X86::getShufflePSHUFLWImmediate(SVOp), 5889 DAG); 5890 5891 if (isSHUFPMask(M, VT)) { 5892 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5893 if (VT == MVT::v4f32 || VT == MVT::v4i32) 5894 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, 5895 TargetMask, DAG); 5896 if (VT == MVT::v2f64 || VT == MVT::v2i64) 5897 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, 5898 TargetMask, DAG); 5899 } 5900 5901 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 5902 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5903 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), 5904 dl, VT, V1, V1, DAG); 5905 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 5906 if (VT != MVT::v2i64 && VT != MVT::v2f64) 5907 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 5908 5909 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 5910 if (VT == MVT::v8i16) { 5911 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 5912 if (NewOp.getNode()) 5913 return NewOp; 5914 } 5915 5916 if (VT == MVT::v16i8) { 5917 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 5918 if (NewOp.getNode()) 5919 return NewOp; 5920 } 5921 5922 // Handle all 4 wide cases with a number of shuffles. 5923 if (NumElems == 4) 5924 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 5925 5926 return SDValue(); 5927} 5928 5929SDValue 5930X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 5931 SelectionDAG &DAG) const { 5932 EVT VT = Op.getValueType(); 5933 DebugLoc dl = Op.getDebugLoc(); 5934 if (VT.getSizeInBits() == 8) { 5935 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 5936 Op.getOperand(0), Op.getOperand(1)); 5937 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5938 DAG.getValueType(VT)); 5939 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5940 } else if (VT.getSizeInBits() == 16) { 5941 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5942 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 5943 if (Idx == 0) 5944 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5945 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5946 DAG.getNode(ISD::BITCAST, dl, 5947 MVT::v4i32, 5948 Op.getOperand(0)), 5949 Op.getOperand(1))); 5950 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 5951 Op.getOperand(0), Op.getOperand(1)); 5952 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5953 DAG.getValueType(VT)); 5954 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5955 } else if (VT == MVT::f32) { 5956 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 5957 // the result back to FR32 register. It's only worth matching if the 5958 // result has a single use which is a store or a bitcast to i32. And in 5959 // the case of a store, it's not worth it if the index is a constant 0, 5960 // because a MOVSSmr can be used instead, which is smaller and faster. 5961 if (!Op.hasOneUse()) 5962 return SDValue(); 5963 SDNode *User = *Op.getNode()->use_begin(); 5964 if ((User->getOpcode() != ISD::STORE || 5965 (isa<ConstantSDNode>(Op.getOperand(1)) && 5966 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 5967 (User->getOpcode() != ISD::BITCAST || 5968 User->getValueType(0) != MVT::i32)) 5969 return SDValue(); 5970 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5971 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 5972 Op.getOperand(0)), 5973 Op.getOperand(1)); 5974 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 5975 } else if (VT == MVT::i32) { 5976 // ExtractPS works with constant index. 5977 if (isa<ConstantSDNode>(Op.getOperand(1))) 5978 return Op; 5979 } 5980 return SDValue(); 5981} 5982 5983 5984SDValue 5985X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5986 SelectionDAG &DAG) const { 5987 if (!isa<ConstantSDNode>(Op.getOperand(1))) 5988 return SDValue(); 5989 5990 SDValue Vec = Op.getOperand(0); 5991 EVT VecVT = Vec.getValueType(); 5992 5993 // If this is a 256-bit vector result, first extract the 128-bit 5994 // vector and then extract from the 128-bit vector. 5995 if (VecVT.getSizeInBits() > 128) { 5996 DebugLoc dl = Op.getNode()->getDebugLoc(); 5997 unsigned NumElems = VecVT.getVectorNumElements(); 5998 SDValue Idx = Op.getOperand(1); 5999 6000 if (!isa<ConstantSDNode>(Idx)) 6001 return SDValue(); 6002 6003 unsigned ExtractNumElems = NumElems / (VecVT.getSizeInBits() / 128); 6004 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6005 6006 // Get the 128-bit vector. 6007 bool Upper = IdxVal >= ExtractNumElems; 6008 Vec = Extract128BitVector(Vec, Idx, DAG, dl); 6009 6010 // Extract from it. 6011 SDValue ScaledIdx = Idx; 6012 if (Upper) 6013 ScaledIdx = DAG.getNode(ISD::SUB, dl, Idx.getValueType(), Idx, 6014 DAG.getConstant(ExtractNumElems, 6015 Idx.getValueType())); 6016 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6017 ScaledIdx); 6018 } 6019 6020 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6021 6022 if (Subtarget->hasSSE41()) { 6023 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6024 if (Res.getNode()) 6025 return Res; 6026 } 6027 6028 EVT VT = Op.getValueType(); 6029 DebugLoc dl = Op.getDebugLoc(); 6030 // TODO: handle v16i8. 6031 if (VT.getSizeInBits() == 16) { 6032 SDValue Vec = Op.getOperand(0); 6033 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6034 if (Idx == 0) 6035 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6036 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6037 DAG.getNode(ISD::BITCAST, dl, 6038 MVT::v4i32, Vec), 6039 Op.getOperand(1))); 6040 // Transform it so it match pextrw which produces a 32-bit result. 6041 EVT EltVT = MVT::i32; 6042 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6043 Op.getOperand(0), Op.getOperand(1)); 6044 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6045 DAG.getValueType(VT)); 6046 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6047 } else if (VT.getSizeInBits() == 32) { 6048 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6049 if (Idx == 0) 6050 return Op; 6051 6052 // SHUFPS the element to the lowest double word, then movss. 6053 int Mask[4] = { Idx, -1, -1, -1 }; 6054 EVT VVT = Op.getOperand(0).getValueType(); 6055 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6056 DAG.getUNDEF(VVT), Mask); 6057 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6058 DAG.getIntPtrConstant(0)); 6059 } else if (VT.getSizeInBits() == 64) { 6060 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6061 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6062 // to match extract_elt for f64. 6063 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6064 if (Idx == 0) 6065 return Op; 6066 6067 // UNPCKHPD the element to the lowest double word, then movsd. 6068 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6069 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6070 int Mask[2] = { 1, -1 }; 6071 EVT VVT = Op.getOperand(0).getValueType(); 6072 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6073 DAG.getUNDEF(VVT), Mask); 6074 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6075 DAG.getIntPtrConstant(0)); 6076 } 6077 6078 return SDValue(); 6079} 6080 6081SDValue 6082X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6083 SelectionDAG &DAG) const { 6084 EVT VT = Op.getValueType(); 6085 EVT EltVT = VT.getVectorElementType(); 6086 DebugLoc dl = Op.getDebugLoc(); 6087 6088 SDValue N0 = Op.getOperand(0); 6089 SDValue N1 = Op.getOperand(1); 6090 SDValue N2 = Op.getOperand(2); 6091 6092 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6093 isa<ConstantSDNode>(N2)) { 6094 unsigned Opc; 6095 if (VT == MVT::v8i16) 6096 Opc = X86ISD::PINSRW; 6097 else if (VT == MVT::v16i8) 6098 Opc = X86ISD::PINSRB; 6099 else 6100 Opc = X86ISD::PINSRB; 6101 6102 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6103 // argument. 6104 if (N1.getValueType() != MVT::i32) 6105 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6106 if (N2.getValueType() != MVT::i32) 6107 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6108 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6109 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6110 // Bits [7:6] of the constant are the source select. This will always be 6111 // zero here. The DAG Combiner may combine an extract_elt index into these 6112 // bits. For example (insert (extract, 3), 2) could be matched by putting 6113 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6114 // Bits [5:4] of the constant are the destination select. This is the 6115 // value of the incoming immediate. 6116 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6117 // combine either bitwise AND or insert of float 0.0 to set these bits. 6118 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6119 // Create this as a scalar to vector.. 6120 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6121 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6122 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 6123 // PINSR* works with constant index. 6124 return Op; 6125 } 6126 return SDValue(); 6127} 6128 6129SDValue 6130X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6131 EVT VT = Op.getValueType(); 6132 EVT EltVT = VT.getVectorElementType(); 6133 6134 DebugLoc dl = Op.getDebugLoc(); 6135 SDValue N0 = Op.getOperand(0); 6136 SDValue N1 = Op.getOperand(1); 6137 SDValue N2 = Op.getOperand(2); 6138 6139 // If this is a 256-bit vector result, first insert into a 128-bit 6140 // vector and then insert into the 256-bit vector. 6141 if (VT.getSizeInBits() > 128) { 6142 if (!isa<ConstantSDNode>(N2)) 6143 return SDValue(); 6144 6145 // Get the 128-bit vector. 6146 unsigned NumElems = VT.getVectorNumElements(); 6147 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6148 bool Upper = IdxVal >= NumElems / 2; 6149 6150 SDValue SubN0 = Extract128BitVector(N0, N2, DAG, dl); 6151 6152 // Insert into it. 6153 SDValue ScaledN2 = N2; 6154 if (Upper) 6155 ScaledN2 = DAG.getNode(ISD::SUB, dl, N2.getValueType(), N2, 6156 DAG.getConstant(NumElems / 6157 (VT.getSizeInBits() / 128), 6158 N2.getValueType())); 6159 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubN0.getValueType(), SubN0, 6160 N1, ScaledN2); 6161 6162 // Insert the 128-bit vector 6163 // FIXME: Why UNDEF? 6164 return Insert128BitVector(N0, Op, N2, DAG, dl); 6165 } 6166 6167 if (Subtarget->hasSSE41()) 6168 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6169 6170 if (EltVT == MVT::i8) 6171 return SDValue(); 6172 6173 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6174 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6175 // as its second argument. 6176 if (N1.getValueType() != MVT::i32) 6177 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6178 if (N2.getValueType() != MVT::i32) 6179 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6180 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6181 } 6182 return SDValue(); 6183} 6184 6185SDValue 6186X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6187 LLVMContext *Context = DAG.getContext(); 6188 DebugLoc dl = Op.getDebugLoc(); 6189 EVT OpVT = Op.getValueType(); 6190 6191 // If this is a 256-bit vector result, first insert into a 128-bit 6192 // vector and then insert into the 256-bit vector. 6193 if (OpVT.getSizeInBits() > 128) { 6194 // Insert into a 128-bit vector. 6195 EVT VT128 = EVT::getVectorVT(*Context, 6196 OpVT.getVectorElementType(), 6197 OpVT.getVectorNumElements() / 2); 6198 6199 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6200 6201 // Insert the 128-bit vector. 6202 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6203 DAG.getConstant(0, MVT::i32), 6204 DAG, dl); 6205 } 6206 6207 if (Op.getValueType() == MVT::v1i64 && 6208 Op.getOperand(0).getValueType() == MVT::i64) 6209 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6210 6211 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6212 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6213 "Expected an SSE type!"); 6214 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6215 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6216} 6217 6218// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6219// a simple subregister reference or explicit instructions to grab 6220// upper bits of a vector. 6221SDValue 6222X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6223 if (Subtarget->hasAVX()) { 6224 DebugLoc dl = Op.getNode()->getDebugLoc(); 6225 SDValue Vec = Op.getNode()->getOperand(0); 6226 SDValue Idx = Op.getNode()->getOperand(1); 6227 6228 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6229 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6230 return Extract128BitVector(Vec, Idx, DAG, dl); 6231 } 6232 } 6233 return SDValue(); 6234} 6235 6236// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6237// simple superregister reference or explicit instructions to insert 6238// the upper bits of a vector. 6239SDValue 6240X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6241 if (Subtarget->hasAVX()) { 6242 DebugLoc dl = Op.getNode()->getDebugLoc(); 6243 SDValue Vec = Op.getNode()->getOperand(0); 6244 SDValue SubVec = Op.getNode()->getOperand(1); 6245 SDValue Idx = Op.getNode()->getOperand(2); 6246 6247 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6248 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6249 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6250 } 6251 } 6252 return SDValue(); 6253} 6254 6255// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6256// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6257// one of the above mentioned nodes. It has to be wrapped because otherwise 6258// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6259// be used to form addressing mode. These wrapped nodes will be selected 6260// into MOV32ri. 6261SDValue 6262X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6263 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6264 6265 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6266 // global base reg. 6267 unsigned char OpFlag = 0; 6268 unsigned WrapperKind = X86ISD::Wrapper; 6269 CodeModel::Model M = getTargetMachine().getCodeModel(); 6270 6271 if (Subtarget->isPICStyleRIPRel() && 6272 (M == CodeModel::Small || M == CodeModel::Kernel)) 6273 WrapperKind = X86ISD::WrapperRIP; 6274 else if (Subtarget->isPICStyleGOT()) 6275 OpFlag = X86II::MO_GOTOFF; 6276 else if (Subtarget->isPICStyleStubPIC()) 6277 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6278 6279 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6280 CP->getAlignment(), 6281 CP->getOffset(), OpFlag); 6282 DebugLoc DL = CP->getDebugLoc(); 6283 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6284 // With PIC, the address is actually $g + Offset. 6285 if (OpFlag) { 6286 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6287 DAG.getNode(X86ISD::GlobalBaseReg, 6288 DebugLoc(), getPointerTy()), 6289 Result); 6290 } 6291 6292 return Result; 6293} 6294 6295SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6296 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6297 6298 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6299 // global base reg. 6300 unsigned char OpFlag = 0; 6301 unsigned WrapperKind = X86ISD::Wrapper; 6302 CodeModel::Model M = getTargetMachine().getCodeModel(); 6303 6304 if (Subtarget->isPICStyleRIPRel() && 6305 (M == CodeModel::Small || M == CodeModel::Kernel)) 6306 WrapperKind = X86ISD::WrapperRIP; 6307 else if (Subtarget->isPICStyleGOT()) 6308 OpFlag = X86II::MO_GOTOFF; 6309 else if (Subtarget->isPICStyleStubPIC()) 6310 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6311 6312 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 6313 OpFlag); 6314 DebugLoc DL = JT->getDebugLoc(); 6315 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6316 6317 // With PIC, the address is actually $g + Offset. 6318 if (OpFlag) 6319 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6320 DAG.getNode(X86ISD::GlobalBaseReg, 6321 DebugLoc(), getPointerTy()), 6322 Result); 6323 6324 return Result; 6325} 6326 6327SDValue 6328X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 6329 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 6330 6331 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6332 // global base reg. 6333 unsigned char OpFlag = 0; 6334 unsigned WrapperKind = X86ISD::Wrapper; 6335 CodeModel::Model M = getTargetMachine().getCodeModel(); 6336 6337 if (Subtarget->isPICStyleRIPRel() && 6338 (M == CodeModel::Small || M == CodeModel::Kernel)) 6339 WrapperKind = X86ISD::WrapperRIP; 6340 else if (Subtarget->isPICStyleGOT()) 6341 OpFlag = X86II::MO_GOTOFF; 6342 else if (Subtarget->isPICStyleStubPIC()) 6343 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6344 6345 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 6346 6347 DebugLoc DL = Op.getDebugLoc(); 6348 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6349 6350 6351 // With PIC, the address is actually $g + Offset. 6352 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 6353 !Subtarget->is64Bit()) { 6354 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6355 DAG.getNode(X86ISD::GlobalBaseReg, 6356 DebugLoc(), getPointerTy()), 6357 Result); 6358 } 6359 6360 return Result; 6361} 6362 6363SDValue 6364X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 6365 // Create the TargetBlockAddressAddress node. 6366 unsigned char OpFlags = 6367 Subtarget->ClassifyBlockAddressReference(); 6368 CodeModel::Model M = getTargetMachine().getCodeModel(); 6369 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 6370 DebugLoc dl = Op.getDebugLoc(); 6371 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 6372 /*isTarget=*/true, OpFlags); 6373 6374 if (Subtarget->isPICStyleRIPRel() && 6375 (M == CodeModel::Small || M == CodeModel::Kernel)) 6376 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6377 else 6378 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6379 6380 // With PIC, the address is actually $g + Offset. 6381 if (isGlobalRelativeToPICBase(OpFlags)) { 6382 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6383 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6384 Result); 6385 } 6386 6387 return Result; 6388} 6389 6390SDValue 6391X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 6392 int64_t Offset, 6393 SelectionDAG &DAG) const { 6394 // Create the TargetGlobalAddress node, folding in the constant 6395 // offset if it is legal. 6396 unsigned char OpFlags = 6397 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 6398 CodeModel::Model M = getTargetMachine().getCodeModel(); 6399 SDValue Result; 6400 if (OpFlags == X86II::MO_NO_FLAG && 6401 X86::isOffsetSuitableForCodeModel(Offset, M)) { 6402 // A direct static reference to a global. 6403 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 6404 Offset = 0; 6405 } else { 6406 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 6407 } 6408 6409 if (Subtarget->isPICStyleRIPRel() && 6410 (M == CodeModel::Small || M == CodeModel::Kernel)) 6411 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6412 else 6413 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6414 6415 // With PIC, the address is actually $g + Offset. 6416 if (isGlobalRelativeToPICBase(OpFlags)) { 6417 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6418 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6419 Result); 6420 } 6421 6422 // For globals that require a load from a stub to get the address, emit the 6423 // load. 6424 if (isGlobalStubReference(OpFlags)) 6425 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 6426 MachinePointerInfo::getGOT(), false, false, 0); 6427 6428 // If there was a non-zero offset that we didn't fold, create an explicit 6429 // addition for it. 6430 if (Offset != 0) 6431 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 6432 DAG.getConstant(Offset, getPointerTy())); 6433 6434 return Result; 6435} 6436 6437SDValue 6438X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 6439 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 6440 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 6441 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 6442} 6443 6444static SDValue 6445GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 6446 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 6447 unsigned char OperandFlags) { 6448 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6449 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6450 DebugLoc dl = GA->getDebugLoc(); 6451 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6452 GA->getValueType(0), 6453 GA->getOffset(), 6454 OperandFlags); 6455 if (InFlag) { 6456 SDValue Ops[] = { Chain, TGA, *InFlag }; 6457 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 6458 } else { 6459 SDValue Ops[] = { Chain, TGA }; 6460 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 6461 } 6462 6463 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 6464 MFI->setAdjustsStack(true); 6465 6466 SDValue Flag = Chain.getValue(1); 6467 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 6468} 6469 6470// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 6471static SDValue 6472LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6473 const EVT PtrVT) { 6474 SDValue InFlag; 6475 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 6476 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 6477 DAG.getNode(X86ISD::GlobalBaseReg, 6478 DebugLoc(), PtrVT), InFlag); 6479 InFlag = Chain.getValue(1); 6480 6481 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 6482} 6483 6484// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 6485static SDValue 6486LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6487 const EVT PtrVT) { 6488 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 6489 X86::RAX, X86II::MO_TLSGD); 6490} 6491 6492// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 6493// "local exec" model. 6494static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6495 const EVT PtrVT, TLSModel::Model model, 6496 bool is64Bit) { 6497 DebugLoc dl = GA->getDebugLoc(); 6498 6499 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 6500 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 6501 is64Bit ? 257 : 256)); 6502 6503 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 6504 DAG.getIntPtrConstant(0), 6505 MachinePointerInfo(Ptr), false, false, 0); 6506 6507 unsigned char OperandFlags = 0; 6508 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 6509 // initialexec. 6510 unsigned WrapperKind = X86ISD::Wrapper; 6511 if (model == TLSModel::LocalExec) { 6512 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 6513 } else if (is64Bit) { 6514 assert(model == TLSModel::InitialExec); 6515 OperandFlags = X86II::MO_GOTTPOFF; 6516 WrapperKind = X86ISD::WrapperRIP; 6517 } else { 6518 assert(model == TLSModel::InitialExec); 6519 OperandFlags = X86II::MO_INDNTPOFF; 6520 } 6521 6522 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 6523 // exec) 6524 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6525 GA->getValueType(0), 6526 GA->getOffset(), OperandFlags); 6527 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 6528 6529 if (model == TLSModel::InitialExec) 6530 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 6531 MachinePointerInfo::getGOT(), false, false, 0); 6532 6533 // The address of the thread local variable is the add of the thread 6534 // pointer with the offset of the variable. 6535 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 6536} 6537 6538SDValue 6539X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 6540 6541 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 6542 const GlobalValue *GV = GA->getGlobal(); 6543 6544 if (Subtarget->isTargetELF()) { 6545 // TODO: implement the "local dynamic" model 6546 // TODO: implement the "initial exec"model for pic executables 6547 6548 // If GV is an alias then use the aliasee for determining 6549 // thread-localness. 6550 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 6551 GV = GA->resolveAliasedGlobal(false); 6552 6553 TLSModel::Model model 6554 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 6555 6556 switch (model) { 6557 case TLSModel::GeneralDynamic: 6558 case TLSModel::LocalDynamic: // not implemented 6559 if (Subtarget->is64Bit()) 6560 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 6561 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 6562 6563 case TLSModel::InitialExec: 6564 case TLSModel::LocalExec: 6565 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 6566 Subtarget->is64Bit()); 6567 } 6568 } else if (Subtarget->isTargetDarwin()) { 6569 // Darwin only has one model of TLS. Lower to that. 6570 unsigned char OpFlag = 0; 6571 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 6572 X86ISD::WrapperRIP : X86ISD::Wrapper; 6573 6574 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6575 // global base reg. 6576 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 6577 !Subtarget->is64Bit(); 6578 if (PIC32) 6579 OpFlag = X86II::MO_TLVP_PIC_BASE; 6580 else 6581 OpFlag = X86II::MO_TLVP; 6582 DebugLoc DL = Op.getDebugLoc(); 6583 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 6584 GA->getValueType(0), 6585 GA->getOffset(), OpFlag); 6586 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6587 6588 // With PIC32, the address is actually $g + Offset. 6589 if (PIC32) 6590 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6591 DAG.getNode(X86ISD::GlobalBaseReg, 6592 DebugLoc(), getPointerTy()), 6593 Offset); 6594 6595 // Lowering the machine isd will make sure everything is in the right 6596 // location. 6597 SDValue Chain = DAG.getEntryNode(); 6598 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6599 SDValue Args[] = { Chain, Offset }; 6600 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 6601 6602 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 6603 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6604 MFI->setAdjustsStack(true); 6605 6606 // And our return value (tls address) is in the standard call return value 6607 // location. 6608 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 6609 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 6610 } 6611 6612 assert(false && 6613 "TLS not implemented for this target."); 6614 6615 llvm_unreachable("Unreachable"); 6616 return SDValue(); 6617} 6618 6619 6620/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 6621/// take a 2 x i32 value to shift plus a shift amount. 6622SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 6623 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 6624 EVT VT = Op.getValueType(); 6625 unsigned VTBits = VT.getSizeInBits(); 6626 DebugLoc dl = Op.getDebugLoc(); 6627 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 6628 SDValue ShOpLo = Op.getOperand(0); 6629 SDValue ShOpHi = Op.getOperand(1); 6630 SDValue ShAmt = Op.getOperand(2); 6631 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 6632 DAG.getConstant(VTBits - 1, MVT::i8)) 6633 : DAG.getConstant(0, VT); 6634 6635 SDValue Tmp2, Tmp3; 6636 if (Op.getOpcode() == ISD::SHL_PARTS) { 6637 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 6638 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 6639 } else { 6640 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 6641 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 6642 } 6643 6644 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 6645 DAG.getConstant(VTBits, MVT::i8)); 6646 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6647 AndNode, DAG.getConstant(0, MVT::i8)); 6648 6649 SDValue Hi, Lo; 6650 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6651 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 6652 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 6653 6654 if (Op.getOpcode() == ISD::SHL_PARTS) { 6655 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 6656 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 6657 } else { 6658 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 6659 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 6660 } 6661 6662 SDValue Ops[2] = { Lo, Hi }; 6663 return DAG.getMergeValues(Ops, 2, dl); 6664} 6665 6666SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 6667 SelectionDAG &DAG) const { 6668 EVT SrcVT = Op.getOperand(0).getValueType(); 6669 6670 if (SrcVT.isVector()) 6671 return SDValue(); 6672 6673 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 6674 "Unknown SINT_TO_FP to lower!"); 6675 6676 // These are really Legal; return the operand so the caller accepts it as 6677 // Legal. 6678 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 6679 return Op; 6680 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 6681 Subtarget->is64Bit()) { 6682 return Op; 6683 } 6684 6685 DebugLoc dl = Op.getDebugLoc(); 6686 unsigned Size = SrcVT.getSizeInBits()/8; 6687 MachineFunction &MF = DAG.getMachineFunction(); 6688 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 6689 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6690 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6691 StackSlot, 6692 MachinePointerInfo::getFixedStack(SSFI), 6693 false, false, 0); 6694 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 6695} 6696 6697SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 6698 SDValue StackSlot, 6699 SelectionDAG &DAG) const { 6700 // Build the FILD 6701 DebugLoc DL = Op.getDebugLoc(); 6702 SDVTList Tys; 6703 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 6704 if (useSSE) 6705 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 6706 else 6707 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 6708 6709 unsigned ByteSize = SrcVT.getSizeInBits()/8; 6710 6711 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 6712 MachineMemOperand *MMO = 6713 DAG.getMachineFunction() 6714 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6715 MachineMemOperand::MOLoad, ByteSize, ByteSize); 6716 6717 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 6718 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 6719 X86ISD::FILD, DL, 6720 Tys, Ops, array_lengthof(Ops), 6721 SrcVT, MMO); 6722 6723 if (useSSE) { 6724 Chain = Result.getValue(1); 6725 SDValue InFlag = Result.getValue(2); 6726 6727 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 6728 // shouldn't be necessary except that RFP cannot be live across 6729 // multiple blocks. When stackifier is fixed, they can be uncoupled. 6730 MachineFunction &MF = DAG.getMachineFunction(); 6731 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 6732 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 6733 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6734 Tys = DAG.getVTList(MVT::Other); 6735 SDValue Ops[] = { 6736 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 6737 }; 6738 MachineMemOperand *MMO = 6739 DAG.getMachineFunction() 6740 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6741 MachineMemOperand::MOStore, SSFISize, SSFISize); 6742 6743 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 6744 Ops, array_lengthof(Ops), 6745 Op.getValueType(), MMO); 6746 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 6747 MachinePointerInfo::getFixedStack(SSFI), 6748 false, false, 0); 6749 } 6750 6751 return Result; 6752} 6753 6754// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 6755SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 6756 SelectionDAG &DAG) const { 6757 // This algorithm is not obvious. Here it is in C code, more or less: 6758 /* 6759 double uint64_to_double( uint32_t hi, uint32_t lo ) { 6760 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 6761 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 6762 6763 // Copy ints to xmm registers. 6764 __m128i xh = _mm_cvtsi32_si128( hi ); 6765 __m128i xl = _mm_cvtsi32_si128( lo ); 6766 6767 // Combine into low half of a single xmm register. 6768 __m128i x = _mm_unpacklo_epi32( xh, xl ); 6769 __m128d d; 6770 double sd; 6771 6772 // Merge in appropriate exponents to give the integer bits the right 6773 // magnitude. 6774 x = _mm_unpacklo_epi32( x, exp ); 6775 6776 // Subtract away the biases to deal with the IEEE-754 double precision 6777 // implicit 1. 6778 d = _mm_sub_pd( (__m128d) x, bias ); 6779 6780 // All conversions up to here are exact. The correctly rounded result is 6781 // calculated using the current rounding mode using the following 6782 // horizontal add. 6783 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 6784 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 6785 // store doesn't really need to be here (except 6786 // maybe to zero the other double) 6787 return sd; 6788 } 6789 */ 6790 6791 DebugLoc dl = Op.getDebugLoc(); 6792 LLVMContext *Context = DAG.getContext(); 6793 6794 // Build some magic constants. 6795 std::vector<Constant*> CV0; 6796 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 6797 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 6798 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6799 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6800 Constant *C0 = ConstantVector::get(CV0); 6801 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 6802 6803 std::vector<Constant*> CV1; 6804 CV1.push_back( 6805 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 6806 CV1.push_back( 6807 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 6808 Constant *C1 = ConstantVector::get(CV1); 6809 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 6810 6811 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6812 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6813 Op.getOperand(0), 6814 DAG.getIntPtrConstant(1))); 6815 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6816 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6817 Op.getOperand(0), 6818 DAG.getIntPtrConstant(0))); 6819 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 6820 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 6821 MachinePointerInfo::getConstantPool(), 6822 false, false, 16); 6823 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 6824 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 6825 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 6826 MachinePointerInfo::getConstantPool(), 6827 false, false, 16); 6828 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 6829 6830 // Add the halves; easiest way is to swap them into another reg first. 6831 int ShufMask[2] = { 1, -1 }; 6832 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 6833 DAG.getUNDEF(MVT::v2f64), ShufMask); 6834 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 6835 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 6836 DAG.getIntPtrConstant(0)); 6837} 6838 6839// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 6840SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 6841 SelectionDAG &DAG) const { 6842 DebugLoc dl = Op.getDebugLoc(); 6843 // FP constant to bias correct the final result. 6844 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 6845 MVT::f64); 6846 6847 // Load the 32-bit value into an XMM register. 6848 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6849 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6850 Op.getOperand(0), 6851 DAG.getIntPtrConstant(0))); 6852 6853 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6854 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 6855 DAG.getIntPtrConstant(0)); 6856 6857 // Or the load with the bias. 6858 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 6859 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 6860 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6861 MVT::v2f64, Load)), 6862 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 6863 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6864 MVT::v2f64, Bias))); 6865 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6866 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 6867 DAG.getIntPtrConstant(0)); 6868 6869 // Subtract the bias. 6870 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 6871 6872 // Handle final rounding. 6873 EVT DestVT = Op.getValueType(); 6874 6875 if (DestVT.bitsLT(MVT::f64)) { 6876 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6877 DAG.getIntPtrConstant(0)); 6878 } else if (DestVT.bitsGT(MVT::f64)) { 6879 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6880 } 6881 6882 // Handle final rounding. 6883 return Sub; 6884} 6885 6886SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 6887 SelectionDAG &DAG) const { 6888 SDValue N0 = Op.getOperand(0); 6889 DebugLoc dl = Op.getDebugLoc(); 6890 6891 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 6892 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 6893 // the optimization here. 6894 if (DAG.SignBitIsZero(N0)) 6895 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 6896 6897 EVT SrcVT = N0.getValueType(); 6898 EVT DstVT = Op.getValueType(); 6899 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 6900 return LowerUINT_TO_FP_i64(Op, DAG); 6901 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 6902 return LowerUINT_TO_FP_i32(Op, DAG); 6903 6904 // Make a 64-bit buffer, and use it to build an FILD. 6905 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 6906 if (SrcVT == MVT::i32) { 6907 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 6908 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 6909 getPointerTy(), StackSlot, WordOff); 6910 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6911 StackSlot, MachinePointerInfo(), 6912 false, false, 0); 6913 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 6914 OffsetSlot, MachinePointerInfo(), 6915 false, false, 0); 6916 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 6917 return Fild; 6918 } 6919 6920 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 6921 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6922 StackSlot, MachinePointerInfo(), 6923 false, false, 0); 6924 // For i64 source, we need to add the appropriate power of 2 if the input 6925 // was negative. This is the same as the optimization in 6926 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 6927 // we must be careful to do the computation in x87 extended precision, not 6928 // in SSE. (The generic code can't know it's OK to do this, or how to.) 6929 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 6930 MachineMemOperand *MMO = 6931 DAG.getMachineFunction() 6932 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 6933 MachineMemOperand::MOLoad, 8, 8); 6934 6935 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 6936 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 6937 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 6938 MVT::i64, MMO); 6939 6940 APInt FF(32, 0x5F800000ULL); 6941 6942 // Check whether the sign bit is set. 6943 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 6944 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 6945 ISD::SETLT); 6946 6947 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 6948 SDValue FudgePtr = DAG.getConstantPool( 6949 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 6950 getPointerTy()); 6951 6952 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 6953 SDValue Zero = DAG.getIntPtrConstant(0); 6954 SDValue Four = DAG.getIntPtrConstant(4); 6955 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 6956 Zero, Four); 6957 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 6958 6959 // Load the value out, extending it from f32 to f80. 6960 // FIXME: Avoid the extend by constructing the right constant pool? 6961 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 6962 FudgePtr, MachinePointerInfo::getConstantPool(), 6963 MVT::f32, false, false, 4); 6964 // Extend everything to 80 bits to force it to be done on x87. 6965 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 6966 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 6967} 6968 6969std::pair<SDValue,SDValue> X86TargetLowering:: 6970FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 6971 DebugLoc DL = Op.getDebugLoc(); 6972 6973 EVT DstTy = Op.getValueType(); 6974 6975 if (!IsSigned) { 6976 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 6977 DstTy = MVT::i64; 6978 } 6979 6980 assert(DstTy.getSimpleVT() <= MVT::i64 && 6981 DstTy.getSimpleVT() >= MVT::i16 && 6982 "Unknown FP_TO_SINT to lower!"); 6983 6984 // These are really Legal. 6985 if (DstTy == MVT::i32 && 6986 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6987 return std::make_pair(SDValue(), SDValue()); 6988 if (Subtarget->is64Bit() && 6989 DstTy == MVT::i64 && 6990 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6991 return std::make_pair(SDValue(), SDValue()); 6992 6993 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 6994 // stack slot. 6995 MachineFunction &MF = DAG.getMachineFunction(); 6996 unsigned MemSize = DstTy.getSizeInBits()/8; 6997 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6998 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6999 7000 7001 7002 unsigned Opc; 7003 switch (DstTy.getSimpleVT().SimpleTy) { 7004 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7005 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7006 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7007 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7008 } 7009 7010 SDValue Chain = DAG.getEntryNode(); 7011 SDValue Value = Op.getOperand(0); 7012 EVT TheVT = Op.getOperand(0).getValueType(); 7013 if (isScalarFPTypeInSSEReg(TheVT)) { 7014 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7015 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7016 MachinePointerInfo::getFixedStack(SSFI), 7017 false, false, 0); 7018 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7019 SDValue Ops[] = { 7020 Chain, StackSlot, DAG.getValueType(TheVT) 7021 }; 7022 7023 MachineMemOperand *MMO = 7024 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7025 MachineMemOperand::MOLoad, MemSize, MemSize); 7026 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7027 DstTy, MMO); 7028 Chain = Value.getValue(1); 7029 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7030 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7031 } 7032 7033 MachineMemOperand *MMO = 7034 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7035 MachineMemOperand::MOStore, MemSize, MemSize); 7036 7037 // Build the FP_TO_INT*_IN_MEM 7038 SDValue Ops[] = { Chain, Value, StackSlot }; 7039 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7040 Ops, 3, DstTy, MMO); 7041 7042 return std::make_pair(FIST, StackSlot); 7043} 7044 7045SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7046 SelectionDAG &DAG) const { 7047 if (Op.getValueType().isVector()) 7048 return SDValue(); 7049 7050 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7051 SDValue FIST = Vals.first, StackSlot = Vals.second; 7052 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7053 if (FIST.getNode() == 0) return Op; 7054 7055 // Load the result. 7056 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7057 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7058} 7059 7060SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7061 SelectionDAG &DAG) const { 7062 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7063 SDValue FIST = Vals.first, StackSlot = Vals.second; 7064 assert(FIST.getNode() && "Unexpected failure"); 7065 7066 // Load the result. 7067 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7068 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7069} 7070 7071SDValue X86TargetLowering::LowerFABS(SDValue Op, 7072 SelectionDAG &DAG) const { 7073 LLVMContext *Context = DAG.getContext(); 7074 DebugLoc dl = Op.getDebugLoc(); 7075 EVT VT = Op.getValueType(); 7076 EVT EltVT = VT; 7077 if (VT.isVector()) 7078 EltVT = VT.getVectorElementType(); 7079 std::vector<Constant*> CV; 7080 if (EltVT == MVT::f64) { 7081 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7082 CV.push_back(C); 7083 CV.push_back(C); 7084 } else { 7085 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7086 CV.push_back(C); 7087 CV.push_back(C); 7088 CV.push_back(C); 7089 CV.push_back(C); 7090 } 7091 Constant *C = ConstantVector::get(CV); 7092 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7093 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7094 MachinePointerInfo::getConstantPool(), 7095 false, false, 16); 7096 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7097} 7098 7099SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7100 LLVMContext *Context = DAG.getContext(); 7101 DebugLoc dl = Op.getDebugLoc(); 7102 EVT VT = Op.getValueType(); 7103 EVT EltVT = VT; 7104 if (VT.isVector()) 7105 EltVT = VT.getVectorElementType(); 7106 std::vector<Constant*> CV; 7107 if (EltVT == MVT::f64) { 7108 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7109 CV.push_back(C); 7110 CV.push_back(C); 7111 } else { 7112 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7113 CV.push_back(C); 7114 CV.push_back(C); 7115 CV.push_back(C); 7116 CV.push_back(C); 7117 } 7118 Constant *C = ConstantVector::get(CV); 7119 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7120 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7121 MachinePointerInfo::getConstantPool(), 7122 false, false, 16); 7123 if (VT.isVector()) { 7124 return DAG.getNode(ISD::BITCAST, dl, VT, 7125 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 7126 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7127 Op.getOperand(0)), 7128 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 7129 } else { 7130 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7131 } 7132} 7133 7134SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7135 LLVMContext *Context = DAG.getContext(); 7136 SDValue Op0 = Op.getOperand(0); 7137 SDValue Op1 = Op.getOperand(1); 7138 DebugLoc dl = Op.getDebugLoc(); 7139 EVT VT = Op.getValueType(); 7140 EVT SrcVT = Op1.getValueType(); 7141 7142 // If second operand is smaller, extend it first. 7143 if (SrcVT.bitsLT(VT)) { 7144 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7145 SrcVT = VT; 7146 } 7147 // And if it is bigger, shrink it first. 7148 if (SrcVT.bitsGT(VT)) { 7149 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7150 SrcVT = VT; 7151 } 7152 7153 // At this point the operands and the result should have the same 7154 // type, and that won't be f80 since that is not custom lowered. 7155 7156 // First get the sign bit of second operand. 7157 std::vector<Constant*> CV; 7158 if (SrcVT == MVT::f64) { 7159 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7160 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7161 } else { 7162 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7163 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7164 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7165 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7166 } 7167 Constant *C = ConstantVector::get(CV); 7168 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7169 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7170 MachinePointerInfo::getConstantPool(), 7171 false, false, 16); 7172 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7173 7174 // Shift sign bit right or left if the two operands have different types. 7175 if (SrcVT.bitsGT(VT)) { 7176 // Op0 is MVT::f32, Op1 is MVT::f64. 7177 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7178 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7179 DAG.getConstant(32, MVT::i32)); 7180 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7181 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7182 DAG.getIntPtrConstant(0)); 7183 } 7184 7185 // Clear first operand sign bit. 7186 CV.clear(); 7187 if (VT == MVT::f64) { 7188 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7189 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7190 } else { 7191 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7192 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7193 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7194 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7195 } 7196 C = ConstantVector::get(CV); 7197 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7198 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7199 MachinePointerInfo::getConstantPool(), 7200 false, false, 16); 7201 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7202 7203 // Or the value with the sign bit. 7204 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7205} 7206 7207/// Emit nodes that will be selected as "test Op0,Op0", or something 7208/// equivalent. 7209SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7210 SelectionDAG &DAG) const { 7211 DebugLoc dl = Op.getDebugLoc(); 7212 7213 // CF and OF aren't always set the way we want. Determine which 7214 // of these we need. 7215 bool NeedCF = false; 7216 bool NeedOF = false; 7217 switch (X86CC) { 7218 default: break; 7219 case X86::COND_A: case X86::COND_AE: 7220 case X86::COND_B: case X86::COND_BE: 7221 NeedCF = true; 7222 break; 7223 case X86::COND_G: case X86::COND_GE: 7224 case X86::COND_L: case X86::COND_LE: 7225 case X86::COND_O: case X86::COND_NO: 7226 NeedOF = true; 7227 break; 7228 } 7229 7230 // See if we can use the EFLAGS value from the operand instead of 7231 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7232 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7233 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7234 // Emit a CMP with 0, which is the TEST pattern. 7235 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7236 DAG.getConstant(0, Op.getValueType())); 7237 7238 unsigned Opcode = 0; 7239 unsigned NumOperands = 0; 7240 switch (Op.getNode()->getOpcode()) { 7241 case ISD::ADD: 7242 // Due to an isel shortcoming, be conservative if this add is likely to be 7243 // selected as part of a load-modify-store instruction. When the root node 7244 // in a match is a store, isel doesn't know how to remap non-chain non-flag 7245 // uses of other nodes in the match, such as the ADD in this case. This 7246 // leads to the ADD being left around and reselected, with the result being 7247 // two adds in the output. Alas, even if none our users are stores, that 7248 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 7249 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 7250 // climbing the DAG back to the root, and it doesn't seem to be worth the 7251 // effort. 7252 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7253 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7254 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 7255 goto default_case; 7256 7257 if (ConstantSDNode *C = 7258 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 7259 // An add of one will be selected as an INC. 7260 if (C->getAPIntValue() == 1) { 7261 Opcode = X86ISD::INC; 7262 NumOperands = 1; 7263 break; 7264 } 7265 7266 // An add of negative one (subtract of one) will be selected as a DEC. 7267 if (C->getAPIntValue().isAllOnesValue()) { 7268 Opcode = X86ISD::DEC; 7269 NumOperands = 1; 7270 break; 7271 } 7272 } 7273 7274 // Otherwise use a regular EFLAGS-setting add. 7275 Opcode = X86ISD::ADD; 7276 NumOperands = 2; 7277 break; 7278 case ISD::AND: { 7279 // If the primary and result isn't used, don't bother using X86ISD::AND, 7280 // because a TEST instruction will be better. 7281 bool NonFlagUse = false; 7282 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7283 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 7284 SDNode *User = *UI; 7285 unsigned UOpNo = UI.getOperandNo(); 7286 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 7287 // Look pass truncate. 7288 UOpNo = User->use_begin().getOperandNo(); 7289 User = *User->use_begin(); 7290 } 7291 7292 if (User->getOpcode() != ISD::BRCOND && 7293 User->getOpcode() != ISD::SETCC && 7294 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 7295 NonFlagUse = true; 7296 break; 7297 } 7298 } 7299 7300 if (!NonFlagUse) 7301 break; 7302 } 7303 // FALL THROUGH 7304 case ISD::SUB: 7305 case ISD::OR: 7306 case ISD::XOR: 7307 // Due to the ISEL shortcoming noted above, be conservative if this op is 7308 // likely to be selected as part of a load-modify-store instruction. 7309 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7310 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7311 if (UI->getOpcode() == ISD::STORE) 7312 goto default_case; 7313 7314 // Otherwise use a regular EFLAGS-setting instruction. 7315 switch (Op.getNode()->getOpcode()) { 7316 default: llvm_unreachable("unexpected operator!"); 7317 case ISD::SUB: Opcode = X86ISD::SUB; break; 7318 case ISD::OR: Opcode = X86ISD::OR; break; 7319 case ISD::XOR: Opcode = X86ISD::XOR; break; 7320 case ISD::AND: Opcode = X86ISD::AND; break; 7321 } 7322 7323 NumOperands = 2; 7324 break; 7325 case X86ISD::ADD: 7326 case X86ISD::SUB: 7327 case X86ISD::INC: 7328 case X86ISD::DEC: 7329 case X86ISD::OR: 7330 case X86ISD::XOR: 7331 case X86ISD::AND: 7332 return SDValue(Op.getNode(), 1); 7333 default: 7334 default_case: 7335 break; 7336 } 7337 7338 if (Opcode == 0) 7339 // Emit a CMP with 0, which is the TEST pattern. 7340 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7341 DAG.getConstant(0, Op.getValueType())); 7342 7343 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 7344 SmallVector<SDValue, 4> Ops; 7345 for (unsigned i = 0; i != NumOperands; ++i) 7346 Ops.push_back(Op.getOperand(i)); 7347 7348 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 7349 DAG.ReplaceAllUsesWith(Op, New); 7350 return SDValue(New.getNode(), 1); 7351} 7352 7353/// Emit nodes that will be selected as "cmp Op0,Op1", or something 7354/// equivalent. 7355SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 7356 SelectionDAG &DAG) const { 7357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 7358 if (C->getAPIntValue() == 0) 7359 return EmitTest(Op0, X86CC, DAG); 7360 7361 DebugLoc dl = Op0.getDebugLoc(); 7362 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 7363} 7364 7365/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 7366/// if it's possible. 7367SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 7368 DebugLoc dl, SelectionDAG &DAG) const { 7369 SDValue Op0 = And.getOperand(0); 7370 SDValue Op1 = And.getOperand(1); 7371 if (Op0.getOpcode() == ISD::TRUNCATE) 7372 Op0 = Op0.getOperand(0); 7373 if (Op1.getOpcode() == ISD::TRUNCATE) 7374 Op1 = Op1.getOperand(0); 7375 7376 SDValue LHS, RHS; 7377 if (Op1.getOpcode() == ISD::SHL) 7378 std::swap(Op0, Op1); 7379 if (Op0.getOpcode() == ISD::SHL) { 7380 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 7381 if (And00C->getZExtValue() == 1) { 7382 // If we looked past a truncate, check that it's only truncating away 7383 // known zeros. 7384 unsigned BitWidth = Op0.getValueSizeInBits(); 7385 unsigned AndBitWidth = And.getValueSizeInBits(); 7386 if (BitWidth > AndBitWidth) { 7387 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 7388 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 7389 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 7390 return SDValue(); 7391 } 7392 LHS = Op1; 7393 RHS = Op0.getOperand(1); 7394 } 7395 } else if (Op1.getOpcode() == ISD::Constant) { 7396 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 7397 SDValue AndLHS = Op0; 7398 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 7399 LHS = AndLHS.getOperand(0); 7400 RHS = AndLHS.getOperand(1); 7401 } 7402 } 7403 7404 if (LHS.getNode()) { 7405 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 7406 // instruction. Since the shift amount is in-range-or-undefined, we know 7407 // that doing a bittest on the i32 value is ok. We extend to i32 because 7408 // the encoding for the i16 version is larger than the i32 version. 7409 // Also promote i16 to i32 for performance / code size reason. 7410 if (LHS.getValueType() == MVT::i8 || 7411 LHS.getValueType() == MVT::i16) 7412 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 7413 7414 // If the operand types disagree, extend the shift amount to match. Since 7415 // BT ignores high bits (like shifts) we can use anyextend. 7416 if (LHS.getValueType() != RHS.getValueType()) 7417 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 7418 7419 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 7420 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 7421 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7422 DAG.getConstant(Cond, MVT::i8), BT); 7423 } 7424 7425 return SDValue(); 7426} 7427 7428SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 7429 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 7430 SDValue Op0 = Op.getOperand(0); 7431 SDValue Op1 = Op.getOperand(1); 7432 DebugLoc dl = Op.getDebugLoc(); 7433 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 7434 7435 // Optimize to BT if possible. 7436 // Lower (X & (1 << N)) == 0 to BT(X, N). 7437 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 7438 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 7439 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 7440 Op1.getOpcode() == ISD::Constant && 7441 cast<ConstantSDNode>(Op1)->isNullValue() && 7442 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7443 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 7444 if (NewSetCC.getNode()) 7445 return NewSetCC; 7446 } 7447 7448 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 7449 // these. 7450 if (Op1.getOpcode() == ISD::Constant && 7451 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 7452 cast<ConstantSDNode>(Op1)->isNullValue()) && 7453 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7454 7455 // If the input is a setcc, then reuse the input setcc or use a new one with 7456 // the inverted condition. 7457 if (Op0.getOpcode() == X86ISD::SETCC) { 7458 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 7459 bool Invert = (CC == ISD::SETNE) ^ 7460 cast<ConstantSDNode>(Op1)->isNullValue(); 7461 if (!Invert) return Op0; 7462 7463 CCode = X86::GetOppositeBranchCondition(CCode); 7464 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7465 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 7466 } 7467 } 7468 7469 bool isFP = Op1.getValueType().isFloatingPoint(); 7470 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 7471 if (X86CC == X86::COND_INVALID) 7472 return SDValue(); 7473 7474 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 7475 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7476 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 7477} 7478 7479SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 7480 SDValue Cond; 7481 SDValue Op0 = Op.getOperand(0); 7482 SDValue Op1 = Op.getOperand(1); 7483 SDValue CC = Op.getOperand(2); 7484 EVT VT = Op.getValueType(); 7485 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 7486 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 7487 DebugLoc dl = Op.getDebugLoc(); 7488 7489 if (isFP) { 7490 unsigned SSECC = 8; 7491 EVT VT0 = Op0.getValueType(); 7492 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 7493 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 7494 bool Swap = false; 7495 7496 switch (SetCCOpcode) { 7497 default: break; 7498 case ISD::SETOEQ: 7499 case ISD::SETEQ: SSECC = 0; break; 7500 case ISD::SETOGT: 7501 case ISD::SETGT: Swap = true; // Fallthrough 7502 case ISD::SETLT: 7503 case ISD::SETOLT: SSECC = 1; break; 7504 case ISD::SETOGE: 7505 case ISD::SETGE: Swap = true; // Fallthrough 7506 case ISD::SETLE: 7507 case ISD::SETOLE: SSECC = 2; break; 7508 case ISD::SETUO: SSECC = 3; break; 7509 case ISD::SETUNE: 7510 case ISD::SETNE: SSECC = 4; break; 7511 case ISD::SETULE: Swap = true; 7512 case ISD::SETUGE: SSECC = 5; break; 7513 case ISD::SETULT: Swap = true; 7514 case ISD::SETUGT: SSECC = 6; break; 7515 case ISD::SETO: SSECC = 7; break; 7516 } 7517 if (Swap) 7518 std::swap(Op0, Op1); 7519 7520 // In the two special cases we can't handle, emit two comparisons. 7521 if (SSECC == 8) { 7522 if (SetCCOpcode == ISD::SETUEQ) { 7523 SDValue UNORD, EQ; 7524 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 7525 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 7526 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 7527 } 7528 else if (SetCCOpcode == ISD::SETONE) { 7529 SDValue ORD, NEQ; 7530 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 7531 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 7532 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 7533 } 7534 llvm_unreachable("Illegal FP comparison"); 7535 } 7536 // Handle all other FP comparisons here. 7537 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 7538 } 7539 7540 // We are handling one of the integer comparisons here. Since SSE only has 7541 // GT and EQ comparisons for integer, swapping operands and multiple 7542 // operations may be required for some comparisons. 7543 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 7544 bool Swap = false, Invert = false, FlipSigns = false; 7545 7546 switch (VT.getSimpleVT().SimpleTy) { 7547 default: break; 7548 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 7549 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 7550 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 7551 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 7552 } 7553 7554 switch (SetCCOpcode) { 7555 default: break; 7556 case ISD::SETNE: Invert = true; 7557 case ISD::SETEQ: Opc = EQOpc; break; 7558 case ISD::SETLT: Swap = true; 7559 case ISD::SETGT: Opc = GTOpc; break; 7560 case ISD::SETGE: Swap = true; 7561 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 7562 case ISD::SETULT: Swap = true; 7563 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 7564 case ISD::SETUGE: Swap = true; 7565 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 7566 } 7567 if (Swap) 7568 std::swap(Op0, Op1); 7569 7570 // Since SSE has no unsigned integer comparisons, we need to flip the sign 7571 // bits of the inputs before performing those operations. 7572 if (FlipSigns) { 7573 EVT EltVT = VT.getVectorElementType(); 7574 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 7575 EltVT); 7576 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 7577 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 7578 SignBits.size()); 7579 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 7580 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 7581 } 7582 7583 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 7584 7585 // If the logical-not of the result is required, perform that now. 7586 if (Invert) 7587 Result = DAG.getNOT(dl, Result, VT); 7588 7589 return Result; 7590} 7591 7592// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 7593static bool isX86LogicalCmp(SDValue Op) { 7594 unsigned Opc = Op.getNode()->getOpcode(); 7595 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 7596 return true; 7597 if (Op.getResNo() == 1 && 7598 (Opc == X86ISD::ADD || 7599 Opc == X86ISD::SUB || 7600 Opc == X86ISD::ADC || 7601 Opc == X86ISD::SBB || 7602 Opc == X86ISD::SMUL || 7603 Opc == X86ISD::UMUL || 7604 Opc == X86ISD::INC || 7605 Opc == X86ISD::DEC || 7606 Opc == X86ISD::OR || 7607 Opc == X86ISD::XOR || 7608 Opc == X86ISD::AND)) 7609 return true; 7610 7611 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 7612 return true; 7613 7614 return false; 7615} 7616 7617static bool isZero(SDValue V) { 7618 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 7619 return C && C->isNullValue(); 7620} 7621 7622static bool isAllOnes(SDValue V) { 7623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 7624 return C && C->isAllOnesValue(); 7625} 7626 7627SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 7628 bool addTest = true; 7629 SDValue Cond = Op.getOperand(0); 7630 SDValue Op1 = Op.getOperand(1); 7631 SDValue Op2 = Op.getOperand(2); 7632 DebugLoc DL = Op.getDebugLoc(); 7633 SDValue CC; 7634 7635 if (Cond.getOpcode() == ISD::SETCC) { 7636 SDValue NewCond = LowerSETCC(Cond, DAG); 7637 if (NewCond.getNode()) 7638 Cond = NewCond; 7639 } 7640 7641 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 7642 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 7643 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 7644 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 7645 if (Cond.getOpcode() == X86ISD::SETCC && 7646 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 7647 isZero(Cond.getOperand(1).getOperand(1))) { 7648 SDValue Cmp = Cond.getOperand(1); 7649 7650 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 7651 7652 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 7653 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 7654 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 7655 7656 SDValue CmpOp0 = Cmp.getOperand(0); 7657 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 7658 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 7659 7660 SDValue Res = // Res = 0 or -1. 7661 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 7662 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 7663 7664 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 7665 Res = DAG.getNOT(DL, Res, Res.getValueType()); 7666 7667 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 7668 if (N2C == 0 || !N2C->isNullValue()) 7669 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 7670 return Res; 7671 } 7672 } 7673 7674 // Look past (and (setcc_carry (cmp ...)), 1). 7675 if (Cond.getOpcode() == ISD::AND && 7676 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 7677 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 7678 if (C && C->getAPIntValue() == 1) 7679 Cond = Cond.getOperand(0); 7680 } 7681 7682 // If condition flag is set by a X86ISD::CMP, then use it as the condition 7683 // setting operand in place of the X86ISD::SETCC. 7684 if (Cond.getOpcode() == X86ISD::SETCC || 7685 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 7686 CC = Cond.getOperand(0); 7687 7688 SDValue Cmp = Cond.getOperand(1); 7689 unsigned Opc = Cmp.getOpcode(); 7690 EVT VT = Op.getValueType(); 7691 7692 bool IllegalFPCMov = false; 7693 if (VT.isFloatingPoint() && !VT.isVector() && 7694 !isScalarFPTypeInSSEReg(VT)) // FPStack? 7695 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 7696 7697 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 7698 Opc == X86ISD::BT) { // FIXME 7699 Cond = Cmp; 7700 addTest = false; 7701 } 7702 } 7703 7704 if (addTest) { 7705 // Look pass the truncate. 7706 if (Cond.getOpcode() == ISD::TRUNCATE) 7707 Cond = Cond.getOperand(0); 7708 7709 // We know the result of AND is compared against zero. Try to match 7710 // it to BT. 7711 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7712 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 7713 if (NewSetCC.getNode()) { 7714 CC = NewSetCC.getOperand(0); 7715 Cond = NewSetCC.getOperand(1); 7716 addTest = false; 7717 } 7718 } 7719 } 7720 7721 if (addTest) { 7722 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7723 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7724 } 7725 7726 // a < b ? -1 : 0 -> RES = ~setcc_carry 7727 // a < b ? 0 : -1 -> RES = setcc_carry 7728 // a >= b ? -1 : 0 -> RES = setcc_carry 7729 // a >= b ? 0 : -1 -> RES = ~setcc_carry 7730 if (Cond.getOpcode() == X86ISD::CMP) { 7731 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 7732 7733 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 7734 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 7735 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 7736 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 7737 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 7738 return DAG.getNOT(DL, Res, Res.getValueType()); 7739 return Res; 7740 } 7741 } 7742 7743 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 7744 // condition is true. 7745 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 7746 SDValue Ops[] = { Op2, Op1, CC, Cond }; 7747 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 7748} 7749 7750// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 7751// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 7752// from the AND / OR. 7753static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 7754 Opc = Op.getOpcode(); 7755 if (Opc != ISD::OR && Opc != ISD::AND) 7756 return false; 7757 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7758 Op.getOperand(0).hasOneUse() && 7759 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 7760 Op.getOperand(1).hasOneUse()); 7761} 7762 7763// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 7764// 1 and that the SETCC node has a single use. 7765static bool isXor1OfSetCC(SDValue Op) { 7766 if (Op.getOpcode() != ISD::XOR) 7767 return false; 7768 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7769 if (N1C && N1C->getAPIntValue() == 1) { 7770 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7771 Op.getOperand(0).hasOneUse(); 7772 } 7773 return false; 7774} 7775 7776SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 7777 bool addTest = true; 7778 SDValue Chain = Op.getOperand(0); 7779 SDValue Cond = Op.getOperand(1); 7780 SDValue Dest = Op.getOperand(2); 7781 DebugLoc dl = Op.getDebugLoc(); 7782 SDValue CC; 7783 7784 if (Cond.getOpcode() == ISD::SETCC) { 7785 SDValue NewCond = LowerSETCC(Cond, DAG); 7786 if (NewCond.getNode()) 7787 Cond = NewCond; 7788 } 7789#if 0 7790 // FIXME: LowerXALUO doesn't handle these!! 7791 else if (Cond.getOpcode() == X86ISD::ADD || 7792 Cond.getOpcode() == X86ISD::SUB || 7793 Cond.getOpcode() == X86ISD::SMUL || 7794 Cond.getOpcode() == X86ISD::UMUL) 7795 Cond = LowerXALUO(Cond, DAG); 7796#endif 7797 7798 // Look pass (and (setcc_carry (cmp ...)), 1). 7799 if (Cond.getOpcode() == ISD::AND && 7800 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 7801 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 7802 if (C && C->getAPIntValue() == 1) 7803 Cond = Cond.getOperand(0); 7804 } 7805 7806 // If condition flag is set by a X86ISD::CMP, then use it as the condition 7807 // setting operand in place of the X86ISD::SETCC. 7808 if (Cond.getOpcode() == X86ISD::SETCC || 7809 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 7810 CC = Cond.getOperand(0); 7811 7812 SDValue Cmp = Cond.getOperand(1); 7813 unsigned Opc = Cmp.getOpcode(); 7814 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 7815 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 7816 Cond = Cmp; 7817 addTest = false; 7818 } else { 7819 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 7820 default: break; 7821 case X86::COND_O: 7822 case X86::COND_B: 7823 // These can only come from an arithmetic instruction with overflow, 7824 // e.g. SADDO, UADDO. 7825 Cond = Cond.getNode()->getOperand(1); 7826 addTest = false; 7827 break; 7828 } 7829 } 7830 } else { 7831 unsigned CondOpc; 7832 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 7833 SDValue Cmp = Cond.getOperand(0).getOperand(1); 7834 if (CondOpc == ISD::OR) { 7835 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 7836 // two branches instead of an explicit OR instruction with a 7837 // separate test. 7838 if (Cmp == Cond.getOperand(1).getOperand(1) && 7839 isX86LogicalCmp(Cmp)) { 7840 CC = Cond.getOperand(0).getOperand(0); 7841 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7842 Chain, Dest, CC, Cmp); 7843 CC = Cond.getOperand(1).getOperand(0); 7844 Cond = Cmp; 7845 addTest = false; 7846 } 7847 } else { // ISD::AND 7848 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 7849 // two branches instead of an explicit AND instruction with a 7850 // separate test. However, we only do this if this block doesn't 7851 // have a fall-through edge, because this requires an explicit 7852 // jmp when the condition is false. 7853 if (Cmp == Cond.getOperand(1).getOperand(1) && 7854 isX86LogicalCmp(Cmp) && 7855 Op.getNode()->hasOneUse()) { 7856 X86::CondCode CCode = 7857 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7858 CCode = X86::GetOppositeBranchCondition(CCode); 7859 CC = DAG.getConstant(CCode, MVT::i8); 7860 SDNode *User = *Op.getNode()->use_begin(); 7861 // Look for an unconditional branch following this conditional branch. 7862 // We need this because we need to reverse the successors in order 7863 // to implement FCMP_OEQ. 7864 if (User->getOpcode() == ISD::BR) { 7865 SDValue FalseBB = User->getOperand(1); 7866 SDNode *NewBR = 7867 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 7868 assert(NewBR == User); 7869 (void)NewBR; 7870 Dest = FalseBB; 7871 7872 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7873 Chain, Dest, CC, Cmp); 7874 X86::CondCode CCode = 7875 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 7876 CCode = X86::GetOppositeBranchCondition(CCode); 7877 CC = DAG.getConstant(CCode, MVT::i8); 7878 Cond = Cmp; 7879 addTest = false; 7880 } 7881 } 7882 } 7883 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 7884 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 7885 // It should be transformed during dag combiner except when the condition 7886 // is set by a arithmetics with overflow node. 7887 X86::CondCode CCode = 7888 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7889 CCode = X86::GetOppositeBranchCondition(CCode); 7890 CC = DAG.getConstant(CCode, MVT::i8); 7891 Cond = Cond.getOperand(0).getOperand(1); 7892 addTest = false; 7893 } 7894 } 7895 7896 if (addTest) { 7897 // Look pass the truncate. 7898 if (Cond.getOpcode() == ISD::TRUNCATE) 7899 Cond = Cond.getOperand(0); 7900 7901 // We know the result of AND is compared against zero. Try to match 7902 // it to BT. 7903 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7904 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 7905 if (NewSetCC.getNode()) { 7906 CC = NewSetCC.getOperand(0); 7907 Cond = NewSetCC.getOperand(1); 7908 addTest = false; 7909 } 7910 } 7911 } 7912 7913 if (addTest) { 7914 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7915 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7916 } 7917 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7918 Chain, Dest, CC, Cond); 7919} 7920 7921 7922// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 7923// Calls to _alloca is needed to probe the stack when allocating more than 4k 7924// bytes in one go. Touching the stack at 4K increments is necessary to ensure 7925// that the guard pages used by the OS virtual memory manager are allocated in 7926// correct sequence. 7927SDValue 7928X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 7929 SelectionDAG &DAG) const { 7930 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && 7931 "This should be used only on Windows targets"); 7932 DebugLoc dl = Op.getDebugLoc(); 7933 7934 // Get the inputs. 7935 SDValue Chain = Op.getOperand(0); 7936 SDValue Size = Op.getOperand(1); 7937 // FIXME: Ensure alignment here 7938 7939 SDValue Flag; 7940 7941 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 7942 7943 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 7944 Flag = Chain.getValue(1); 7945 7946 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7947 7948 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 7949 Flag = Chain.getValue(1); 7950 7951 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 7952 7953 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 7954 return DAG.getMergeValues(Ops1, 2, dl); 7955} 7956 7957SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 7958 MachineFunction &MF = DAG.getMachineFunction(); 7959 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 7960 7961 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 7962 DebugLoc DL = Op.getDebugLoc(); 7963 7964 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 7965 // vastart just stores the address of the VarArgsFrameIndex slot into the 7966 // memory location argument. 7967 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7968 getPointerTy()); 7969 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 7970 MachinePointerInfo(SV), false, false, 0); 7971 } 7972 7973 // __va_list_tag: 7974 // gp_offset (0 - 6 * 8) 7975 // fp_offset (48 - 48 + 8 * 16) 7976 // overflow_arg_area (point to parameters coming in memory). 7977 // reg_save_area 7978 SmallVector<SDValue, 8> MemOps; 7979 SDValue FIN = Op.getOperand(1); 7980 // Store gp_offset 7981 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 7982 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 7983 MVT::i32), 7984 FIN, MachinePointerInfo(SV), false, false, 0); 7985 MemOps.push_back(Store); 7986 7987 // Store fp_offset 7988 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7989 FIN, DAG.getIntPtrConstant(4)); 7990 Store = DAG.getStore(Op.getOperand(0), DL, 7991 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 7992 MVT::i32), 7993 FIN, MachinePointerInfo(SV, 4), false, false, 0); 7994 MemOps.push_back(Store); 7995 7996 // Store ptr to overflow_arg_area 7997 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7998 FIN, DAG.getIntPtrConstant(4)); 7999 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8000 getPointerTy()); 8001 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8002 MachinePointerInfo(SV, 8), 8003 false, false, 0); 8004 MemOps.push_back(Store); 8005 8006 // Store ptr to reg_save_area. 8007 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8008 FIN, DAG.getIntPtrConstant(8)); 8009 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 8010 getPointerTy()); 8011 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 8012 MachinePointerInfo(SV, 16), false, false, 0); 8013 MemOps.push_back(Store); 8014 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 8015 &MemOps[0], MemOps.size()); 8016} 8017 8018SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 8019 assert(Subtarget->is64Bit() && 8020 "LowerVAARG only handles 64-bit va_arg!"); 8021 assert((Subtarget->isTargetLinux() || 8022 Subtarget->isTargetDarwin()) && 8023 "Unhandled target in LowerVAARG"); 8024 assert(Op.getNode()->getNumOperands() == 4); 8025 SDValue Chain = Op.getOperand(0); 8026 SDValue SrcPtr = Op.getOperand(1); 8027 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8028 unsigned Align = Op.getConstantOperandVal(3); 8029 DebugLoc dl = Op.getDebugLoc(); 8030 8031 EVT ArgVT = Op.getNode()->getValueType(0); 8032 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 8033 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 8034 uint8_t ArgMode; 8035 8036 // Decide which area this value should be read from. 8037 // TODO: Implement the AMD64 ABI in its entirety. This simple 8038 // selection mechanism works only for the basic types. 8039 if (ArgVT == MVT::f80) { 8040 llvm_unreachable("va_arg for f80 not yet implemented"); 8041 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 8042 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 8043 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 8044 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 8045 } else { 8046 llvm_unreachable("Unhandled argument type in LowerVAARG"); 8047 } 8048 8049 if (ArgMode == 2) { 8050 // Sanity Check: Make sure using fp_offset makes sense. 8051 assert(!UseSoftFloat && 8052 !(DAG.getMachineFunction() 8053 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 8054 Subtarget->hasXMM()); 8055 } 8056 8057 // Insert VAARG_64 node into the DAG 8058 // VAARG_64 returns two values: Variable Argument Address, Chain 8059 SmallVector<SDValue, 11> InstOps; 8060 InstOps.push_back(Chain); 8061 InstOps.push_back(SrcPtr); 8062 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 8063 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 8064 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 8065 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 8066 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 8067 VTs, &InstOps[0], InstOps.size(), 8068 MVT::i64, 8069 MachinePointerInfo(SV), 8070 /*Align=*/0, 8071 /*Volatile=*/false, 8072 /*ReadMem=*/true, 8073 /*WriteMem=*/true); 8074 Chain = VAARG.getValue(1); 8075 8076 // Load the next argument and return it 8077 return DAG.getLoad(ArgVT, dl, 8078 Chain, 8079 VAARG, 8080 MachinePointerInfo(), 8081 false, false, 0); 8082} 8083 8084SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 8085 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 8086 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 8087 SDValue Chain = Op.getOperand(0); 8088 SDValue DstPtr = Op.getOperand(1); 8089 SDValue SrcPtr = Op.getOperand(2); 8090 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 8091 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8092 DebugLoc DL = Op.getDebugLoc(); 8093 8094 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 8095 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 8096 false, 8097 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 8098} 8099 8100SDValue 8101X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 8102 DebugLoc dl = Op.getDebugLoc(); 8103 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8104 switch (IntNo) { 8105 default: return SDValue(); // Don't custom lower most intrinsics. 8106 // Comparison intrinsics. 8107 case Intrinsic::x86_sse_comieq_ss: 8108 case Intrinsic::x86_sse_comilt_ss: 8109 case Intrinsic::x86_sse_comile_ss: 8110 case Intrinsic::x86_sse_comigt_ss: 8111 case Intrinsic::x86_sse_comige_ss: 8112 case Intrinsic::x86_sse_comineq_ss: 8113 case Intrinsic::x86_sse_ucomieq_ss: 8114 case Intrinsic::x86_sse_ucomilt_ss: 8115 case Intrinsic::x86_sse_ucomile_ss: 8116 case Intrinsic::x86_sse_ucomigt_ss: 8117 case Intrinsic::x86_sse_ucomige_ss: 8118 case Intrinsic::x86_sse_ucomineq_ss: 8119 case Intrinsic::x86_sse2_comieq_sd: 8120 case Intrinsic::x86_sse2_comilt_sd: 8121 case Intrinsic::x86_sse2_comile_sd: 8122 case Intrinsic::x86_sse2_comigt_sd: 8123 case Intrinsic::x86_sse2_comige_sd: 8124 case Intrinsic::x86_sse2_comineq_sd: 8125 case Intrinsic::x86_sse2_ucomieq_sd: 8126 case Intrinsic::x86_sse2_ucomilt_sd: 8127 case Intrinsic::x86_sse2_ucomile_sd: 8128 case Intrinsic::x86_sse2_ucomigt_sd: 8129 case Intrinsic::x86_sse2_ucomige_sd: 8130 case Intrinsic::x86_sse2_ucomineq_sd: { 8131 unsigned Opc = 0; 8132 ISD::CondCode CC = ISD::SETCC_INVALID; 8133 switch (IntNo) { 8134 default: break; 8135 case Intrinsic::x86_sse_comieq_ss: 8136 case Intrinsic::x86_sse2_comieq_sd: 8137 Opc = X86ISD::COMI; 8138 CC = ISD::SETEQ; 8139 break; 8140 case Intrinsic::x86_sse_comilt_ss: 8141 case Intrinsic::x86_sse2_comilt_sd: 8142 Opc = X86ISD::COMI; 8143 CC = ISD::SETLT; 8144 break; 8145 case Intrinsic::x86_sse_comile_ss: 8146 case Intrinsic::x86_sse2_comile_sd: 8147 Opc = X86ISD::COMI; 8148 CC = ISD::SETLE; 8149 break; 8150 case Intrinsic::x86_sse_comigt_ss: 8151 case Intrinsic::x86_sse2_comigt_sd: 8152 Opc = X86ISD::COMI; 8153 CC = ISD::SETGT; 8154 break; 8155 case Intrinsic::x86_sse_comige_ss: 8156 case Intrinsic::x86_sse2_comige_sd: 8157 Opc = X86ISD::COMI; 8158 CC = ISD::SETGE; 8159 break; 8160 case Intrinsic::x86_sse_comineq_ss: 8161 case Intrinsic::x86_sse2_comineq_sd: 8162 Opc = X86ISD::COMI; 8163 CC = ISD::SETNE; 8164 break; 8165 case Intrinsic::x86_sse_ucomieq_ss: 8166 case Intrinsic::x86_sse2_ucomieq_sd: 8167 Opc = X86ISD::UCOMI; 8168 CC = ISD::SETEQ; 8169 break; 8170 case Intrinsic::x86_sse_ucomilt_ss: 8171 case Intrinsic::x86_sse2_ucomilt_sd: 8172 Opc = X86ISD::UCOMI; 8173 CC = ISD::SETLT; 8174 break; 8175 case Intrinsic::x86_sse_ucomile_ss: 8176 case Intrinsic::x86_sse2_ucomile_sd: 8177 Opc = X86ISD::UCOMI; 8178 CC = ISD::SETLE; 8179 break; 8180 case Intrinsic::x86_sse_ucomigt_ss: 8181 case Intrinsic::x86_sse2_ucomigt_sd: 8182 Opc = X86ISD::UCOMI; 8183 CC = ISD::SETGT; 8184 break; 8185 case Intrinsic::x86_sse_ucomige_ss: 8186 case Intrinsic::x86_sse2_ucomige_sd: 8187 Opc = X86ISD::UCOMI; 8188 CC = ISD::SETGE; 8189 break; 8190 case Intrinsic::x86_sse_ucomineq_ss: 8191 case Intrinsic::x86_sse2_ucomineq_sd: 8192 Opc = X86ISD::UCOMI; 8193 CC = ISD::SETNE; 8194 break; 8195 } 8196 8197 SDValue LHS = Op.getOperand(1); 8198 SDValue RHS = Op.getOperand(2); 8199 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 8200 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 8201 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 8202 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8203 DAG.getConstant(X86CC, MVT::i8), Cond); 8204 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8205 } 8206 // ptest and testp intrinsics. The intrinsic these come from are designed to 8207 // return an integer value, not just an instruction so lower it to the ptest 8208 // or testp pattern and a setcc for the result. 8209 case Intrinsic::x86_sse41_ptestz: 8210 case Intrinsic::x86_sse41_ptestc: 8211 case Intrinsic::x86_sse41_ptestnzc: 8212 case Intrinsic::x86_avx_ptestz_256: 8213 case Intrinsic::x86_avx_ptestc_256: 8214 case Intrinsic::x86_avx_ptestnzc_256: 8215 case Intrinsic::x86_avx_vtestz_ps: 8216 case Intrinsic::x86_avx_vtestc_ps: 8217 case Intrinsic::x86_avx_vtestnzc_ps: 8218 case Intrinsic::x86_avx_vtestz_pd: 8219 case Intrinsic::x86_avx_vtestc_pd: 8220 case Intrinsic::x86_avx_vtestnzc_pd: 8221 case Intrinsic::x86_avx_vtestz_ps_256: 8222 case Intrinsic::x86_avx_vtestc_ps_256: 8223 case Intrinsic::x86_avx_vtestnzc_ps_256: 8224 case Intrinsic::x86_avx_vtestz_pd_256: 8225 case Intrinsic::x86_avx_vtestc_pd_256: 8226 case Intrinsic::x86_avx_vtestnzc_pd_256: { 8227 bool IsTestPacked = false; 8228 unsigned X86CC = 0; 8229 switch (IntNo) { 8230 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 8231 case Intrinsic::x86_avx_vtestz_ps: 8232 case Intrinsic::x86_avx_vtestz_pd: 8233 case Intrinsic::x86_avx_vtestz_ps_256: 8234 case Intrinsic::x86_avx_vtestz_pd_256: 8235 IsTestPacked = true; // Fallthrough 8236 case Intrinsic::x86_sse41_ptestz: 8237 case Intrinsic::x86_avx_ptestz_256: 8238 // ZF = 1 8239 X86CC = X86::COND_E; 8240 break; 8241 case Intrinsic::x86_avx_vtestc_ps: 8242 case Intrinsic::x86_avx_vtestc_pd: 8243 case Intrinsic::x86_avx_vtestc_ps_256: 8244 case Intrinsic::x86_avx_vtestc_pd_256: 8245 IsTestPacked = true; // Fallthrough 8246 case Intrinsic::x86_sse41_ptestc: 8247 case Intrinsic::x86_avx_ptestc_256: 8248 // CF = 1 8249 X86CC = X86::COND_B; 8250 break; 8251 case Intrinsic::x86_avx_vtestnzc_ps: 8252 case Intrinsic::x86_avx_vtestnzc_pd: 8253 case Intrinsic::x86_avx_vtestnzc_ps_256: 8254 case Intrinsic::x86_avx_vtestnzc_pd_256: 8255 IsTestPacked = true; // Fallthrough 8256 case Intrinsic::x86_sse41_ptestnzc: 8257 case Intrinsic::x86_avx_ptestnzc_256: 8258 // ZF and CF = 0 8259 X86CC = X86::COND_A; 8260 break; 8261 } 8262 8263 SDValue LHS = Op.getOperand(1); 8264 SDValue RHS = Op.getOperand(2); 8265 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 8266 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 8267 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 8268 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 8269 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8270 } 8271 8272 // Fix vector shift instructions where the last operand is a non-immediate 8273 // i32 value. 8274 case Intrinsic::x86_sse2_pslli_w: 8275 case Intrinsic::x86_sse2_pslli_d: 8276 case Intrinsic::x86_sse2_pslli_q: 8277 case Intrinsic::x86_sse2_psrli_w: 8278 case Intrinsic::x86_sse2_psrli_d: 8279 case Intrinsic::x86_sse2_psrli_q: 8280 case Intrinsic::x86_sse2_psrai_w: 8281 case Intrinsic::x86_sse2_psrai_d: 8282 case Intrinsic::x86_mmx_pslli_w: 8283 case Intrinsic::x86_mmx_pslli_d: 8284 case Intrinsic::x86_mmx_pslli_q: 8285 case Intrinsic::x86_mmx_psrli_w: 8286 case Intrinsic::x86_mmx_psrli_d: 8287 case Intrinsic::x86_mmx_psrli_q: 8288 case Intrinsic::x86_mmx_psrai_w: 8289 case Intrinsic::x86_mmx_psrai_d: { 8290 SDValue ShAmt = Op.getOperand(2); 8291 if (isa<ConstantSDNode>(ShAmt)) 8292 return SDValue(); 8293 8294 unsigned NewIntNo = 0; 8295 EVT ShAmtVT = MVT::v4i32; 8296 switch (IntNo) { 8297 case Intrinsic::x86_sse2_pslli_w: 8298 NewIntNo = Intrinsic::x86_sse2_psll_w; 8299 break; 8300 case Intrinsic::x86_sse2_pslli_d: 8301 NewIntNo = Intrinsic::x86_sse2_psll_d; 8302 break; 8303 case Intrinsic::x86_sse2_pslli_q: 8304 NewIntNo = Intrinsic::x86_sse2_psll_q; 8305 break; 8306 case Intrinsic::x86_sse2_psrli_w: 8307 NewIntNo = Intrinsic::x86_sse2_psrl_w; 8308 break; 8309 case Intrinsic::x86_sse2_psrli_d: 8310 NewIntNo = Intrinsic::x86_sse2_psrl_d; 8311 break; 8312 case Intrinsic::x86_sse2_psrli_q: 8313 NewIntNo = Intrinsic::x86_sse2_psrl_q; 8314 break; 8315 case Intrinsic::x86_sse2_psrai_w: 8316 NewIntNo = Intrinsic::x86_sse2_psra_w; 8317 break; 8318 case Intrinsic::x86_sse2_psrai_d: 8319 NewIntNo = Intrinsic::x86_sse2_psra_d; 8320 break; 8321 default: { 8322 ShAmtVT = MVT::v2i32; 8323 switch (IntNo) { 8324 case Intrinsic::x86_mmx_pslli_w: 8325 NewIntNo = Intrinsic::x86_mmx_psll_w; 8326 break; 8327 case Intrinsic::x86_mmx_pslli_d: 8328 NewIntNo = Intrinsic::x86_mmx_psll_d; 8329 break; 8330 case Intrinsic::x86_mmx_pslli_q: 8331 NewIntNo = Intrinsic::x86_mmx_psll_q; 8332 break; 8333 case Intrinsic::x86_mmx_psrli_w: 8334 NewIntNo = Intrinsic::x86_mmx_psrl_w; 8335 break; 8336 case Intrinsic::x86_mmx_psrli_d: 8337 NewIntNo = Intrinsic::x86_mmx_psrl_d; 8338 break; 8339 case Intrinsic::x86_mmx_psrli_q: 8340 NewIntNo = Intrinsic::x86_mmx_psrl_q; 8341 break; 8342 case Intrinsic::x86_mmx_psrai_w: 8343 NewIntNo = Intrinsic::x86_mmx_psra_w; 8344 break; 8345 case Intrinsic::x86_mmx_psrai_d: 8346 NewIntNo = Intrinsic::x86_mmx_psra_d; 8347 break; 8348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 8349 } 8350 break; 8351 } 8352 } 8353 8354 // The vector shift intrinsics with scalars uses 32b shift amounts but 8355 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 8356 // to be zero. 8357 SDValue ShOps[4]; 8358 ShOps[0] = ShAmt; 8359 ShOps[1] = DAG.getConstant(0, MVT::i32); 8360 if (ShAmtVT == MVT::v4i32) { 8361 ShOps[2] = DAG.getUNDEF(MVT::i32); 8362 ShOps[3] = DAG.getUNDEF(MVT::i32); 8363 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 8364 } else { 8365 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 8366// FIXME this must be lowered to get rid of the invalid type. 8367 } 8368 8369 EVT VT = Op.getValueType(); 8370 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 8371 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8372 DAG.getConstant(NewIntNo, MVT::i32), 8373 Op.getOperand(1), ShAmt); 8374 } 8375 } 8376} 8377 8378SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 8379 SelectionDAG &DAG) const { 8380 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8381 MFI->setReturnAddressIsTaken(true); 8382 8383 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8384 DebugLoc dl = Op.getDebugLoc(); 8385 8386 if (Depth > 0) { 8387 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 8388 SDValue Offset = 8389 DAG.getConstant(TD->getPointerSize(), 8390 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8391 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8392 DAG.getNode(ISD::ADD, dl, getPointerTy(), 8393 FrameAddr, Offset), 8394 MachinePointerInfo(), false, false, 0); 8395 } 8396 8397 // Just load the return address. 8398 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 8399 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8400 RetAddrFI, MachinePointerInfo(), false, false, 0); 8401} 8402 8403SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 8404 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8405 MFI->setFrameAddressIsTaken(true); 8406 8407 EVT VT = Op.getValueType(); 8408 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 8409 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8410 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 8411 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 8412 while (Depth--) 8413 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 8414 MachinePointerInfo(), 8415 false, false, 0); 8416 return FrameAddr; 8417} 8418 8419SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 8420 SelectionDAG &DAG) const { 8421 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 8422} 8423 8424SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 8425 MachineFunction &MF = DAG.getMachineFunction(); 8426 SDValue Chain = Op.getOperand(0); 8427 SDValue Offset = Op.getOperand(1); 8428 SDValue Handler = Op.getOperand(2); 8429 DebugLoc dl = Op.getDebugLoc(); 8430 8431 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 8432 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 8433 getPointerTy()); 8434 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 8435 8436 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 8437 DAG.getIntPtrConstant(TD->getPointerSize())); 8438 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 8439 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 8440 false, false, 0); 8441 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 8442 MF.getRegInfo().addLiveOut(StoreAddrReg); 8443 8444 return DAG.getNode(X86ISD::EH_RETURN, dl, 8445 MVT::Other, 8446 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 8447} 8448 8449SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 8450 SelectionDAG &DAG) const { 8451 SDValue Root = Op.getOperand(0); 8452 SDValue Trmp = Op.getOperand(1); // trampoline 8453 SDValue FPtr = Op.getOperand(2); // nested function 8454 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 8455 DebugLoc dl = Op.getDebugLoc(); 8456 8457 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8458 8459 if (Subtarget->is64Bit()) { 8460 SDValue OutChains[6]; 8461 8462 // Large code-model. 8463 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 8464 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 8465 8466 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 8467 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 8468 8469 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 8470 8471 // Load the pointer to the nested function into R11. 8472 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 8473 SDValue Addr = Trmp; 8474 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8475 Addr, MachinePointerInfo(TrmpAddr), 8476 false, false, 0); 8477 8478 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8479 DAG.getConstant(2, MVT::i64)); 8480 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 8481 MachinePointerInfo(TrmpAddr, 2), 8482 false, false, 2); 8483 8484 // Load the 'nest' parameter value into R10. 8485 // R10 is specified in X86CallingConv.td 8486 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 8487 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8488 DAG.getConstant(10, MVT::i64)); 8489 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8490 Addr, MachinePointerInfo(TrmpAddr, 10), 8491 false, false, 0); 8492 8493 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8494 DAG.getConstant(12, MVT::i64)); 8495 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 8496 MachinePointerInfo(TrmpAddr, 12), 8497 false, false, 2); 8498 8499 // Jump to the nested function. 8500 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 8501 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8502 DAG.getConstant(20, MVT::i64)); 8503 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8504 Addr, MachinePointerInfo(TrmpAddr, 20), 8505 false, false, 0); 8506 8507 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 8508 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8509 DAG.getConstant(22, MVT::i64)); 8510 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 8511 MachinePointerInfo(TrmpAddr, 22), 8512 false, false, 0); 8513 8514 SDValue Ops[] = 8515 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 8516 return DAG.getMergeValues(Ops, 2, dl); 8517 } else { 8518 const Function *Func = 8519 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 8520 CallingConv::ID CC = Func->getCallingConv(); 8521 unsigned NestReg; 8522 8523 switch (CC) { 8524 default: 8525 llvm_unreachable("Unsupported calling convention"); 8526 case CallingConv::C: 8527 case CallingConv::X86_StdCall: { 8528 // Pass 'nest' parameter in ECX. 8529 // Must be kept in sync with X86CallingConv.td 8530 NestReg = X86::ECX; 8531 8532 // Check that ECX wasn't needed by an 'inreg' parameter. 8533 const FunctionType *FTy = Func->getFunctionType(); 8534 const AttrListPtr &Attrs = Func->getAttributes(); 8535 8536 if (!Attrs.isEmpty() && !Func->isVarArg()) { 8537 unsigned InRegCount = 0; 8538 unsigned Idx = 1; 8539 8540 for (FunctionType::param_iterator I = FTy->param_begin(), 8541 E = FTy->param_end(); I != E; ++I, ++Idx) 8542 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 8543 // FIXME: should only count parameters that are lowered to integers. 8544 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 8545 8546 if (InRegCount > 2) { 8547 report_fatal_error("Nest register in use - reduce number of inreg" 8548 " parameters!"); 8549 } 8550 } 8551 break; 8552 } 8553 case CallingConv::X86_FastCall: 8554 case CallingConv::X86_ThisCall: 8555 case CallingConv::Fast: 8556 // Pass 'nest' parameter in EAX. 8557 // Must be kept in sync with X86CallingConv.td 8558 NestReg = X86::EAX; 8559 break; 8560 } 8561 8562 SDValue OutChains[4]; 8563 SDValue Addr, Disp; 8564 8565 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8566 DAG.getConstant(10, MVT::i32)); 8567 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 8568 8569 // This is storing the opcode for MOV32ri. 8570 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 8571 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 8572 OutChains[0] = DAG.getStore(Root, dl, 8573 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 8574 Trmp, MachinePointerInfo(TrmpAddr), 8575 false, false, 0); 8576 8577 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8578 DAG.getConstant(1, MVT::i32)); 8579 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 8580 MachinePointerInfo(TrmpAddr, 1), 8581 false, false, 1); 8582 8583 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 8584 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8585 DAG.getConstant(5, MVT::i32)); 8586 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 8587 MachinePointerInfo(TrmpAddr, 5), 8588 false, false, 1); 8589 8590 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 8591 DAG.getConstant(6, MVT::i32)); 8592 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 8593 MachinePointerInfo(TrmpAddr, 6), 8594 false, false, 1); 8595 8596 SDValue Ops[] = 8597 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 8598 return DAG.getMergeValues(Ops, 2, dl); 8599 } 8600} 8601 8602SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 8603 SelectionDAG &DAG) const { 8604 /* 8605 The rounding mode is in bits 11:10 of FPSR, and has the following 8606 settings: 8607 00 Round to nearest 8608 01 Round to -inf 8609 10 Round to +inf 8610 11 Round to 0 8611 8612 FLT_ROUNDS, on the other hand, expects the following: 8613 -1 Undefined 8614 0 Round to 0 8615 1 Round to nearest 8616 2 Round to +inf 8617 3 Round to -inf 8618 8619 To perform the conversion, we do: 8620 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 8621 */ 8622 8623 MachineFunction &MF = DAG.getMachineFunction(); 8624 const TargetMachine &TM = MF.getTarget(); 8625 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 8626 unsigned StackAlignment = TFI.getStackAlignment(); 8627 EVT VT = Op.getValueType(); 8628 DebugLoc DL = Op.getDebugLoc(); 8629 8630 // Save FP Control Word to stack slot 8631 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 8632 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8633 8634 8635 MachineMemOperand *MMO = 8636 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8637 MachineMemOperand::MOStore, 2, 2); 8638 8639 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 8640 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 8641 DAG.getVTList(MVT::Other), 8642 Ops, 2, MVT::i16, MMO); 8643 8644 // Load FP Control Word from stack slot 8645 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 8646 MachinePointerInfo(), false, false, 0); 8647 8648 // Transform as necessary 8649 SDValue CWD1 = 8650 DAG.getNode(ISD::SRL, DL, MVT::i16, 8651 DAG.getNode(ISD::AND, DL, MVT::i16, 8652 CWD, DAG.getConstant(0x800, MVT::i16)), 8653 DAG.getConstant(11, MVT::i8)); 8654 SDValue CWD2 = 8655 DAG.getNode(ISD::SRL, DL, MVT::i16, 8656 DAG.getNode(ISD::AND, DL, MVT::i16, 8657 CWD, DAG.getConstant(0x400, MVT::i16)), 8658 DAG.getConstant(9, MVT::i8)); 8659 8660 SDValue RetVal = 8661 DAG.getNode(ISD::AND, DL, MVT::i16, 8662 DAG.getNode(ISD::ADD, DL, MVT::i16, 8663 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 8664 DAG.getConstant(1, MVT::i16)), 8665 DAG.getConstant(3, MVT::i16)); 8666 8667 8668 return DAG.getNode((VT.getSizeInBits() < 16 ? 8669 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 8670} 8671 8672SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 8673 EVT VT = Op.getValueType(); 8674 EVT OpVT = VT; 8675 unsigned NumBits = VT.getSizeInBits(); 8676 DebugLoc dl = Op.getDebugLoc(); 8677 8678 Op = Op.getOperand(0); 8679 if (VT == MVT::i8) { 8680 // Zero extend to i32 since there is not an i8 bsr. 8681 OpVT = MVT::i32; 8682 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 8683 } 8684 8685 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 8686 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 8687 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 8688 8689 // If src is zero (i.e. bsr sets ZF), returns NumBits. 8690 SDValue Ops[] = { 8691 Op, 8692 DAG.getConstant(NumBits+NumBits-1, OpVT), 8693 DAG.getConstant(X86::COND_E, MVT::i8), 8694 Op.getValue(1) 8695 }; 8696 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 8697 8698 // Finally xor with NumBits-1. 8699 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 8700 8701 if (VT == MVT::i8) 8702 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 8703 return Op; 8704} 8705 8706SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 8707 EVT VT = Op.getValueType(); 8708 EVT OpVT = VT; 8709 unsigned NumBits = VT.getSizeInBits(); 8710 DebugLoc dl = Op.getDebugLoc(); 8711 8712 Op = Op.getOperand(0); 8713 if (VT == MVT::i8) { 8714 OpVT = MVT::i32; 8715 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 8716 } 8717 8718 // Issue a bsf (scan bits forward) which also sets EFLAGS. 8719 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 8720 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 8721 8722 // If src is zero (i.e. bsf sets ZF), returns NumBits. 8723 SDValue Ops[] = { 8724 Op, 8725 DAG.getConstant(NumBits, OpVT), 8726 DAG.getConstant(X86::COND_E, MVT::i8), 8727 Op.getValue(1) 8728 }; 8729 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 8730 8731 if (VT == MVT::i8) 8732 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 8733 return Op; 8734} 8735 8736SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 8737 EVT VT = Op.getValueType(); 8738 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 8739 DebugLoc dl = Op.getDebugLoc(); 8740 8741 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 8742 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 8743 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 8744 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 8745 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 8746 // 8747 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 8748 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 8749 // return AloBlo + AloBhi + AhiBlo; 8750 8751 SDValue A = Op.getOperand(0); 8752 SDValue B = Op.getOperand(1); 8753 8754 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8755 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8756 A, DAG.getConstant(32, MVT::i32)); 8757 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8758 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8759 B, DAG.getConstant(32, MVT::i32)); 8760 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8761 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8762 A, B); 8763 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8764 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8765 A, Bhi); 8766 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8767 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 8768 Ahi, B); 8769 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8770 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8771 AloBhi, DAG.getConstant(32, MVT::i32)); 8772 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8773 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8774 AhiBlo, DAG.getConstant(32, MVT::i32)); 8775 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 8776 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 8777 return Res; 8778} 8779 8780SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { 8781 EVT VT = Op.getValueType(); 8782 DebugLoc dl = Op.getDebugLoc(); 8783 SDValue R = Op.getOperand(0); 8784 8785 LLVMContext *Context = DAG.getContext(); 8786 8787 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later"); 8788 8789 if (VT == MVT::v4i32) { 8790 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8791 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8792 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 8793 8794 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 8795 8796 std::vector<Constant*> CV(4, CI); 8797 Constant *C = ConstantVector::get(CV); 8798 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8799 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8800 MachinePointerInfo::getConstantPool(), 8801 false, false, 16); 8802 8803 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 8804 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 8805 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 8806 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 8807 } 8808 if (VT == MVT::v16i8) { 8809 // a = a << 5; 8810 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8811 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8812 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 8813 8814 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 8815 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 8816 8817 std::vector<Constant*> CVM1(16, CM1); 8818 std::vector<Constant*> CVM2(16, CM2); 8819 Constant *C = ConstantVector::get(CVM1); 8820 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8821 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8822 MachinePointerInfo::getConstantPool(), 8823 false, false, 16); 8824 8825 // r = pblendv(r, psllw(r & (char16)15, 4), a); 8826 M = DAG.getNode(ISD::AND, dl, VT, R, M); 8827 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8828 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8829 DAG.getConstant(4, MVT::i32)); 8830 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 8831 // a += a 8832 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8833 8834 C = ConstantVector::get(CVM2); 8835 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8836 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8837 MachinePointerInfo::getConstantPool(), 8838 false, false, 16); 8839 8840 // r = pblendv(r, psllw(r & (char16)63, 2), a); 8841 M = DAG.getNode(ISD::AND, dl, VT, R, M); 8842 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8843 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8844 DAG.getConstant(2, MVT::i32)); 8845 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 8846 // a += a 8847 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8848 8849 // return pblendv(r, r+r, a); 8850 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, 8851 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 8852 return R; 8853 } 8854 return SDValue(); 8855} 8856 8857SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 8858 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 8859 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 8860 // looks for this combo and may remove the "setcc" instruction if the "setcc" 8861 // has only one use. 8862 SDNode *N = Op.getNode(); 8863 SDValue LHS = N->getOperand(0); 8864 SDValue RHS = N->getOperand(1); 8865 unsigned BaseOp = 0; 8866 unsigned Cond = 0; 8867 DebugLoc DL = Op.getDebugLoc(); 8868 switch (Op.getOpcode()) { 8869 default: llvm_unreachable("Unknown ovf instruction!"); 8870 case ISD::SADDO: 8871 // A subtract of one will be selected as a INC. Note that INC doesn't 8872 // set CF, so we can't do this for UADDO. 8873 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 8874 if (C->isOne()) { 8875 BaseOp = X86ISD::INC; 8876 Cond = X86::COND_O; 8877 break; 8878 } 8879 BaseOp = X86ISD::ADD; 8880 Cond = X86::COND_O; 8881 break; 8882 case ISD::UADDO: 8883 BaseOp = X86ISD::ADD; 8884 Cond = X86::COND_B; 8885 break; 8886 case ISD::SSUBO: 8887 // A subtract of one will be selected as a DEC. Note that DEC doesn't 8888 // set CF, so we can't do this for USUBO. 8889 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 8890 if (C->isOne()) { 8891 BaseOp = X86ISD::DEC; 8892 Cond = X86::COND_O; 8893 break; 8894 } 8895 BaseOp = X86ISD::SUB; 8896 Cond = X86::COND_O; 8897 break; 8898 case ISD::USUBO: 8899 BaseOp = X86ISD::SUB; 8900 Cond = X86::COND_B; 8901 break; 8902 case ISD::SMULO: 8903 BaseOp = X86ISD::SMUL; 8904 Cond = X86::COND_O; 8905 break; 8906 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 8907 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 8908 MVT::i32); 8909 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 8910 8911 SDValue SetCC = 8912 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8913 DAG.getConstant(X86::COND_O, MVT::i32), 8914 SDValue(Sum.getNode(), 2)); 8915 8916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 8917 return Sum; 8918 } 8919 } 8920 8921 // Also sets EFLAGS. 8922 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 8923 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 8924 8925 SDValue SetCC = 8926 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 8927 DAG.getConstant(Cond, MVT::i32), 8928 SDValue(Sum.getNode(), 1)); 8929 8930 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 8931 return Sum; 8932} 8933 8934SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 8935 DebugLoc dl = Op.getDebugLoc(); 8936 8937 if (!Subtarget->hasSSE2()) { 8938 SDValue Chain = Op.getOperand(0); 8939 SDValue Zero = DAG.getConstant(0, 8940 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8941 SDValue Ops[] = { 8942 DAG.getRegister(X86::ESP, MVT::i32), // Base 8943 DAG.getTargetConstant(1, MVT::i8), // Scale 8944 DAG.getRegister(0, MVT::i32), // Index 8945 DAG.getTargetConstant(0, MVT::i32), // Disp 8946 DAG.getRegister(0, MVT::i32), // Segment. 8947 Zero, 8948 Chain 8949 }; 8950 SDNode *Res = 8951 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 8952 array_lengthof(Ops)); 8953 return SDValue(Res, 0); 8954 } 8955 8956 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 8957 if (!isDev) 8958 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 8959 8960 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 8961 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 8962 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 8963 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 8964 8965 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 8966 if (!Op1 && !Op2 && !Op3 && Op4) 8967 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 8968 8969 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 8970 if (Op1 && !Op2 && !Op3 && !Op4) 8971 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 8972 8973 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 8974 // (MFENCE)>; 8975 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 8976} 8977 8978SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 8979 EVT T = Op.getValueType(); 8980 DebugLoc DL = Op.getDebugLoc(); 8981 unsigned Reg = 0; 8982 unsigned size = 0; 8983 switch(T.getSimpleVT().SimpleTy) { 8984 default: 8985 assert(false && "Invalid value type!"); 8986 case MVT::i8: Reg = X86::AL; size = 1; break; 8987 case MVT::i16: Reg = X86::AX; size = 2; break; 8988 case MVT::i32: Reg = X86::EAX; size = 4; break; 8989 case MVT::i64: 8990 assert(Subtarget->is64Bit() && "Node not type legal!"); 8991 Reg = X86::RAX; size = 8; 8992 break; 8993 } 8994 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 8995 Op.getOperand(2), SDValue()); 8996 SDValue Ops[] = { cpIn.getValue(0), 8997 Op.getOperand(1), 8998 Op.getOperand(3), 8999 DAG.getTargetConstant(size, MVT::i8), 9000 cpIn.getValue(1) }; 9001 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9002 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 9003 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 9004 Ops, 5, T, MMO); 9005 SDValue cpOut = 9006 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 9007 return cpOut; 9008} 9009 9010SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 9011 SelectionDAG &DAG) const { 9012 assert(Subtarget->is64Bit() && "Result not type legalized?"); 9013 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9014 SDValue TheChain = Op.getOperand(0); 9015 DebugLoc dl = Op.getDebugLoc(); 9016 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9017 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 9018 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 9019 rax.getValue(2)); 9020 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 9021 DAG.getConstant(32, MVT::i8)); 9022 SDValue Ops[] = { 9023 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 9024 rdx.getValue(1) 9025 }; 9026 return DAG.getMergeValues(Ops, 2, dl); 9027} 9028 9029SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 9030 SelectionDAG &DAG) const { 9031 EVT SrcVT = Op.getOperand(0).getValueType(); 9032 EVT DstVT = Op.getValueType(); 9033 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 9034 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 9035 assert((DstVT == MVT::i64 || 9036 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 9037 "Unexpected custom BITCAST"); 9038 // i64 <=> MMX conversions are Legal. 9039 if (SrcVT==MVT::i64 && DstVT.isVector()) 9040 return Op; 9041 if (DstVT==MVT::i64 && SrcVT.isVector()) 9042 return Op; 9043 // MMX <=> MMX conversions are Legal. 9044 if (SrcVT.isVector() && DstVT.isVector()) 9045 return Op; 9046 // All other conversions need to be expanded. 9047 return SDValue(); 9048} 9049 9050SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 9051 SDNode *Node = Op.getNode(); 9052 DebugLoc dl = Node->getDebugLoc(); 9053 EVT T = Node->getValueType(0); 9054 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 9055 DAG.getConstant(0, T), Node->getOperand(2)); 9056 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 9057 cast<AtomicSDNode>(Node)->getMemoryVT(), 9058 Node->getOperand(0), 9059 Node->getOperand(1), negOp, 9060 cast<AtomicSDNode>(Node)->getSrcValue(), 9061 cast<AtomicSDNode>(Node)->getAlignment()); 9062} 9063 9064static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 9065 EVT VT = Op.getNode()->getValueType(0); 9066 9067 // Let legalize expand this if it isn't a legal type yet. 9068 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 9069 return SDValue(); 9070 9071 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9072 9073 unsigned Opc; 9074 bool ExtraOp = false; 9075 switch (Op.getOpcode()) { 9076 default: assert(0 && "Invalid code"); 9077 case ISD::ADDC: Opc = X86ISD::ADD; break; 9078 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 9079 case ISD::SUBC: Opc = X86ISD::SUB; break; 9080 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 9081 } 9082 9083 if (!ExtraOp) 9084 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9085 Op.getOperand(1)); 9086 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9087 Op.getOperand(1), Op.getOperand(2)); 9088} 9089 9090/// LowerOperation - Provide custom lowering hooks for some operations. 9091/// 9092SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 9093 switch (Op.getOpcode()) { 9094 default: llvm_unreachable("Should not custom lower this!"); 9095 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 9096 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 9097 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 9098 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 9099 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 9100 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 9101 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 9102 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 9103 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 9104 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 9105 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 9106 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 9107 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 9108 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 9109 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 9110 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 9111 case ISD::SHL_PARTS: 9112 case ISD::SRA_PARTS: 9113 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 9114 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 9115 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 9116 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 9117 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 9118 case ISD::FABS: return LowerFABS(Op, DAG); 9119 case ISD::FNEG: return LowerFNEG(Op, DAG); 9120 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 9121 case ISD::SETCC: return LowerSETCC(Op, DAG); 9122 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 9123 case ISD::SELECT: return LowerSELECT(Op, DAG); 9124 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 9125 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 9126 case ISD::VASTART: return LowerVASTART(Op, DAG); 9127 case ISD::VAARG: return LowerVAARG(Op, DAG); 9128 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 9129 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 9130 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 9131 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 9132 case ISD::FRAME_TO_ARGS_OFFSET: 9133 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 9134 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 9135 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 9136 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 9137 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 9138 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 9139 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 9140 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 9141 case ISD::SHL: return LowerSHL(Op, DAG); 9142 case ISD::SADDO: 9143 case ISD::UADDO: 9144 case ISD::SSUBO: 9145 case ISD::USUBO: 9146 case ISD::SMULO: 9147 case ISD::UMULO: return LowerXALUO(Op, DAG); 9148 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 9149 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 9150 case ISD::ADDC: 9151 case ISD::ADDE: 9152 case ISD::SUBC: 9153 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 9154 } 9155} 9156 9157void X86TargetLowering:: 9158ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 9159 SelectionDAG &DAG, unsigned NewOp) const { 9160 EVT T = Node->getValueType(0); 9161 DebugLoc dl = Node->getDebugLoc(); 9162 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 9163 9164 SDValue Chain = Node->getOperand(0); 9165 SDValue In1 = Node->getOperand(1); 9166 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9167 Node->getOperand(2), DAG.getIntPtrConstant(0)); 9168 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9169 Node->getOperand(2), DAG.getIntPtrConstant(1)); 9170 SDValue Ops[] = { Chain, In1, In2L, In2H }; 9171 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 9172 SDValue Result = 9173 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 9174 cast<MemSDNode>(Node)->getMemOperand()); 9175 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 9176 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9177 Results.push_back(Result.getValue(2)); 9178} 9179 9180/// ReplaceNodeResults - Replace a node with an illegal result type 9181/// with a new node built out of custom code. 9182void X86TargetLowering::ReplaceNodeResults(SDNode *N, 9183 SmallVectorImpl<SDValue>&Results, 9184 SelectionDAG &DAG) const { 9185 DebugLoc dl = N->getDebugLoc(); 9186 switch (N->getOpcode()) { 9187 default: 9188 assert(false && "Do not know how to custom type legalize this operation!"); 9189 return; 9190 case ISD::ADDC: 9191 case ISD::ADDE: 9192 case ISD::SUBC: 9193 case ISD::SUBE: 9194 // We don't want to expand or promote these. 9195 return; 9196 case ISD::FP_TO_SINT: { 9197 std::pair<SDValue,SDValue> Vals = 9198 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 9199 SDValue FIST = Vals.first, StackSlot = Vals.second; 9200 if (FIST.getNode() != 0) { 9201 EVT VT = N->getValueType(0); 9202 // Return a load from the stack slot. 9203 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 9204 MachinePointerInfo(), false, false, 0)); 9205 } 9206 return; 9207 } 9208 case ISD::READCYCLECOUNTER: { 9209 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9210 SDValue TheChain = N->getOperand(0); 9211 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9212 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 9213 rd.getValue(1)); 9214 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 9215 eax.getValue(2)); 9216 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 9217 SDValue Ops[] = { eax, edx }; 9218 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 9219 Results.push_back(edx.getValue(1)); 9220 return; 9221 } 9222 case ISD::ATOMIC_CMP_SWAP: { 9223 EVT T = N->getValueType(0); 9224 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 9225 SDValue cpInL, cpInH; 9226 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9227 DAG.getConstant(0, MVT::i32)); 9228 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9229 DAG.getConstant(1, MVT::i32)); 9230 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 9231 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 9232 cpInL.getValue(1)); 9233 SDValue swapInL, swapInH; 9234 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9235 DAG.getConstant(0, MVT::i32)); 9236 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9237 DAG.getConstant(1, MVT::i32)); 9238 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 9239 cpInH.getValue(1)); 9240 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 9241 swapInL.getValue(1)); 9242 SDValue Ops[] = { swapInH.getValue(0), 9243 N->getOperand(1), 9244 swapInH.getValue(1) }; 9245 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9246 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 9247 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, 9248 Ops, 3, T, MMO); 9249 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 9250 MVT::i32, Result.getValue(1)); 9251 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 9252 MVT::i32, cpOutL.getValue(2)); 9253 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 9254 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9255 Results.push_back(cpOutH.getValue(1)); 9256 return; 9257 } 9258 case ISD::ATOMIC_LOAD_ADD: 9259 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 9260 return; 9261 case ISD::ATOMIC_LOAD_AND: 9262 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 9263 return; 9264 case ISD::ATOMIC_LOAD_NAND: 9265 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 9266 return; 9267 case ISD::ATOMIC_LOAD_OR: 9268 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 9269 return; 9270 case ISD::ATOMIC_LOAD_SUB: 9271 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 9272 return; 9273 case ISD::ATOMIC_LOAD_XOR: 9274 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 9275 return; 9276 case ISD::ATOMIC_SWAP: 9277 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 9278 return; 9279 } 9280} 9281 9282const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 9283 switch (Opcode) { 9284 default: return NULL; 9285 case X86ISD::BSF: return "X86ISD::BSF"; 9286 case X86ISD::BSR: return "X86ISD::BSR"; 9287 case X86ISD::SHLD: return "X86ISD::SHLD"; 9288 case X86ISD::SHRD: return "X86ISD::SHRD"; 9289 case X86ISD::FAND: return "X86ISD::FAND"; 9290 case X86ISD::FOR: return "X86ISD::FOR"; 9291 case X86ISD::FXOR: return "X86ISD::FXOR"; 9292 case X86ISD::FSRL: return "X86ISD::FSRL"; 9293 case X86ISD::FILD: return "X86ISD::FILD"; 9294 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 9295 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 9296 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 9297 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 9298 case X86ISD::FLD: return "X86ISD::FLD"; 9299 case X86ISD::FST: return "X86ISD::FST"; 9300 case X86ISD::CALL: return "X86ISD::CALL"; 9301 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 9302 case X86ISD::BT: return "X86ISD::BT"; 9303 case X86ISD::CMP: return "X86ISD::CMP"; 9304 case X86ISD::COMI: return "X86ISD::COMI"; 9305 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 9306 case X86ISD::SETCC: return "X86ISD::SETCC"; 9307 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 9308 case X86ISD::CMOV: return "X86ISD::CMOV"; 9309 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 9310 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 9311 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 9312 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 9313 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 9314 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 9315 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 9316 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 9317 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 9318 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 9319 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 9320 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 9321 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 9322 case X86ISD::PANDN: return "X86ISD::PANDN"; 9323 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 9324 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 9325 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 9326 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB"; 9327 case X86ISD::FMAX: return "X86ISD::FMAX"; 9328 case X86ISD::FMIN: return "X86ISD::FMIN"; 9329 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 9330 case X86ISD::FRCP: return "X86ISD::FRCP"; 9331 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 9332 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 9333 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 9334 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 9335 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 9336 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 9337 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 9338 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 9339 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 9340 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 9341 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 9342 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 9343 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 9344 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 9345 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 9346 case X86ISD::VSHL: return "X86ISD::VSHL"; 9347 case X86ISD::VSRL: return "X86ISD::VSRL"; 9348 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 9349 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 9350 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 9351 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 9352 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 9353 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 9354 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 9355 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 9356 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 9357 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 9358 case X86ISD::ADD: return "X86ISD::ADD"; 9359 case X86ISD::SUB: return "X86ISD::SUB"; 9360 case X86ISD::ADC: return "X86ISD::ADC"; 9361 case X86ISD::SBB: return "X86ISD::SBB"; 9362 case X86ISD::SMUL: return "X86ISD::SMUL"; 9363 case X86ISD::UMUL: return "X86ISD::UMUL"; 9364 case X86ISD::INC: return "X86ISD::INC"; 9365 case X86ISD::DEC: return "X86ISD::DEC"; 9366 case X86ISD::OR: return "X86ISD::OR"; 9367 case X86ISD::XOR: return "X86ISD::XOR"; 9368 case X86ISD::AND: return "X86ISD::AND"; 9369 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 9370 case X86ISD::PTEST: return "X86ISD::PTEST"; 9371 case X86ISD::TESTP: return "X86ISD::TESTP"; 9372 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 9373 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 9374 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 9375 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 9376 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 9377 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 9378 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 9379 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 9380 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 9381 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 9382 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 9383 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 9384 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 9385 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 9386 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 9387 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 9388 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 9389 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 9390 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 9391 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 9392 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 9393 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 9394 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 9395 case X86ISD::VUNPCKLPS: return "X86ISD::VUNPCKLPS"; 9396 case X86ISD::VUNPCKLPD: return "X86ISD::VUNPCKLPD"; 9397 case X86ISD::VUNPCKLPSY: return "X86ISD::VUNPCKLPSY"; 9398 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 9399 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 9400 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 9401 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 9402 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 9403 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 9404 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 9405 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 9406 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 9407 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 9408 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 9409 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 9410 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 9411 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 9412 } 9413} 9414 9415// isLegalAddressingMode - Return true if the addressing mode represented 9416// by AM is legal for this target, for a load/store of the specified type. 9417bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 9418 const Type *Ty) const { 9419 // X86 supports extremely general addressing modes. 9420 CodeModel::Model M = getTargetMachine().getCodeModel(); 9421 Reloc::Model R = getTargetMachine().getRelocationModel(); 9422 9423 // X86 allows a sign-extended 32-bit immediate field as a displacement. 9424 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 9425 return false; 9426 9427 if (AM.BaseGV) { 9428 unsigned GVFlags = 9429 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 9430 9431 // If a reference to this global requires an extra load, we can't fold it. 9432 if (isGlobalStubReference(GVFlags)) 9433 return false; 9434 9435 // If BaseGV requires a register for the PIC base, we cannot also have a 9436 // BaseReg specified. 9437 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 9438 return false; 9439 9440 // If lower 4G is not available, then we must use rip-relative addressing. 9441 if ((M != CodeModel::Small || R != Reloc::Static) && 9442 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 9443 return false; 9444 } 9445 9446 switch (AM.Scale) { 9447 case 0: 9448 case 1: 9449 case 2: 9450 case 4: 9451 case 8: 9452 // These scales always work. 9453 break; 9454 case 3: 9455 case 5: 9456 case 9: 9457 // These scales are formed with basereg+scalereg. Only accept if there is 9458 // no basereg yet. 9459 if (AM.HasBaseReg) 9460 return false; 9461 break; 9462 default: // Other stuff never works. 9463 return false; 9464 } 9465 9466 return true; 9467} 9468 9469 9470bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 9471 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 9472 return false; 9473 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 9474 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 9475 if (NumBits1 <= NumBits2) 9476 return false; 9477 return true; 9478} 9479 9480bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 9481 if (!VT1.isInteger() || !VT2.isInteger()) 9482 return false; 9483 unsigned NumBits1 = VT1.getSizeInBits(); 9484 unsigned NumBits2 = VT2.getSizeInBits(); 9485 if (NumBits1 <= NumBits2) 9486 return false; 9487 return true; 9488} 9489 9490bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 9491 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 9492 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 9493} 9494 9495bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 9496 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 9497 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 9498} 9499 9500bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 9501 // i16 instructions are longer (0x66 prefix) and potentially slower. 9502 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 9503} 9504 9505/// isShuffleMaskLegal - Targets can use this to indicate that they only 9506/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 9507/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 9508/// are assumed to be legal. 9509bool 9510X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 9511 EVT VT) const { 9512 // Very little shuffling can be done for 64-bit vectors right now. 9513 if (VT.getSizeInBits() == 64) 9514 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 9515 9516 // FIXME: pshufb, blends, shifts. 9517 return (VT.getVectorNumElements() == 2 || 9518 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 9519 isMOVLMask(M, VT) || 9520 isSHUFPMask(M, VT) || 9521 isPSHUFDMask(M, VT) || 9522 isPSHUFHWMask(M, VT) || 9523 isPSHUFLWMask(M, VT) || 9524 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 9525 isUNPCKLMask(M, VT) || 9526 isUNPCKHMask(M, VT) || 9527 isUNPCKL_v_undef_Mask(M, VT) || 9528 isUNPCKH_v_undef_Mask(M, VT)); 9529} 9530 9531bool 9532X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 9533 EVT VT) const { 9534 unsigned NumElts = VT.getVectorNumElements(); 9535 // FIXME: This collection of masks seems suspect. 9536 if (NumElts == 2) 9537 return true; 9538 if (NumElts == 4 && VT.getSizeInBits() == 128) { 9539 return (isMOVLMask(Mask, VT) || 9540 isCommutedMOVLMask(Mask, VT, true) || 9541 isSHUFPMask(Mask, VT) || 9542 isCommutedSHUFPMask(Mask, VT)); 9543 } 9544 return false; 9545} 9546 9547//===----------------------------------------------------------------------===// 9548// X86 Scheduler Hooks 9549//===----------------------------------------------------------------------===// 9550 9551// private utility function 9552MachineBasicBlock * 9553X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 9554 MachineBasicBlock *MBB, 9555 unsigned regOpc, 9556 unsigned immOpc, 9557 unsigned LoadOpc, 9558 unsigned CXchgOpc, 9559 unsigned notOpc, 9560 unsigned EAXreg, 9561 TargetRegisterClass *RC, 9562 bool invSrc) const { 9563 // For the atomic bitwise operator, we generate 9564 // thisMBB: 9565 // newMBB: 9566 // ld t1 = [bitinstr.addr] 9567 // op t2 = t1, [bitinstr.val] 9568 // mov EAX = t1 9569 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 9570 // bz newMBB 9571 // fallthrough -->nextMBB 9572 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9573 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9574 MachineFunction::iterator MBBIter = MBB; 9575 ++MBBIter; 9576 9577 /// First build the CFG 9578 MachineFunction *F = MBB->getParent(); 9579 MachineBasicBlock *thisMBB = MBB; 9580 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9581 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9582 F->insert(MBBIter, newMBB); 9583 F->insert(MBBIter, nextMBB); 9584 9585 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9586 nextMBB->splice(nextMBB->begin(), thisMBB, 9587 llvm::next(MachineBasicBlock::iterator(bInstr)), 9588 thisMBB->end()); 9589 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9590 9591 // Update thisMBB to fall through to newMBB 9592 thisMBB->addSuccessor(newMBB); 9593 9594 // newMBB jumps to itself and fall through to nextMBB 9595 newMBB->addSuccessor(nextMBB); 9596 newMBB->addSuccessor(newMBB); 9597 9598 // Insert instructions into newMBB based on incoming instruction 9599 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 9600 "unexpected number of operands"); 9601 DebugLoc dl = bInstr->getDebugLoc(); 9602 MachineOperand& destOper = bInstr->getOperand(0); 9603 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9604 int numArgs = bInstr->getNumOperands() - 1; 9605 for (int i=0; i < numArgs; ++i) 9606 argOpers[i] = &bInstr->getOperand(i+1); 9607 9608 // x86 address has 4 operands: base, index, scale, and displacement 9609 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9610 int valArgIndx = lastAddrIndx + 1; 9611 9612 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 9613 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 9614 for (int i=0; i <= lastAddrIndx; ++i) 9615 (*MIB).addOperand(*argOpers[i]); 9616 9617 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 9618 if (invSrc) { 9619 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 9620 } 9621 else 9622 tt = t1; 9623 9624 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 9625 assert((argOpers[valArgIndx]->isReg() || 9626 argOpers[valArgIndx]->isImm()) && 9627 "invalid operand"); 9628 if (argOpers[valArgIndx]->isReg()) 9629 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 9630 else 9631 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 9632 MIB.addReg(tt); 9633 (*MIB).addOperand(*argOpers[valArgIndx]); 9634 9635 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 9636 MIB.addReg(t1); 9637 9638 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 9639 for (int i=0; i <= lastAddrIndx; ++i) 9640 (*MIB).addOperand(*argOpers[i]); 9641 MIB.addReg(t2); 9642 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9643 (*MIB).setMemRefs(bInstr->memoperands_begin(), 9644 bInstr->memoperands_end()); 9645 9646 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 9647 MIB.addReg(EAXreg); 9648 9649 // insert branch 9650 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9651 9652 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 9653 return nextMBB; 9654} 9655 9656// private utility function: 64 bit atomics on 32 bit host. 9657MachineBasicBlock * 9658X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 9659 MachineBasicBlock *MBB, 9660 unsigned regOpcL, 9661 unsigned regOpcH, 9662 unsigned immOpcL, 9663 unsigned immOpcH, 9664 bool invSrc) const { 9665 // For the atomic bitwise operator, we generate 9666 // thisMBB (instructions are in pairs, except cmpxchg8b) 9667 // ld t1,t2 = [bitinstr.addr] 9668 // newMBB: 9669 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 9670 // op t5, t6 <- out1, out2, [bitinstr.val] 9671 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 9672 // mov ECX, EBX <- t5, t6 9673 // mov EAX, EDX <- t1, t2 9674 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 9675 // mov t3, t4 <- EAX, EDX 9676 // bz newMBB 9677 // result in out1, out2 9678 // fallthrough -->nextMBB 9679 9680 const TargetRegisterClass *RC = X86::GR32RegisterClass; 9681 const unsigned LoadOpc = X86::MOV32rm; 9682 const unsigned NotOpc = X86::NOT32r; 9683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9684 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9685 MachineFunction::iterator MBBIter = MBB; 9686 ++MBBIter; 9687 9688 /// First build the CFG 9689 MachineFunction *F = MBB->getParent(); 9690 MachineBasicBlock *thisMBB = MBB; 9691 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9692 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9693 F->insert(MBBIter, newMBB); 9694 F->insert(MBBIter, nextMBB); 9695 9696 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9697 nextMBB->splice(nextMBB->begin(), thisMBB, 9698 llvm::next(MachineBasicBlock::iterator(bInstr)), 9699 thisMBB->end()); 9700 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9701 9702 // Update thisMBB to fall through to newMBB 9703 thisMBB->addSuccessor(newMBB); 9704 9705 // newMBB jumps to itself and fall through to nextMBB 9706 newMBB->addSuccessor(nextMBB); 9707 newMBB->addSuccessor(newMBB); 9708 9709 DebugLoc dl = bInstr->getDebugLoc(); 9710 // Insert instructions into newMBB based on incoming instruction 9711 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 9712 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 9713 "unexpected number of operands"); 9714 MachineOperand& dest1Oper = bInstr->getOperand(0); 9715 MachineOperand& dest2Oper = bInstr->getOperand(1); 9716 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9717 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 9718 argOpers[i] = &bInstr->getOperand(i+2); 9719 9720 // We use some of the operands multiple times, so conservatively just 9721 // clear any kill flags that might be present. 9722 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 9723 argOpers[i]->setIsKill(false); 9724 } 9725 9726 // x86 address has 5 operands: base, index, scale, displacement, and segment. 9727 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9728 9729 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 9730 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 9731 for (int i=0; i <= lastAddrIndx; ++i) 9732 (*MIB).addOperand(*argOpers[i]); 9733 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 9734 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 9735 // add 4 to displacement. 9736 for (int i=0; i <= lastAddrIndx-2; ++i) 9737 (*MIB).addOperand(*argOpers[i]); 9738 MachineOperand newOp3 = *(argOpers[3]); 9739 if (newOp3.isImm()) 9740 newOp3.setImm(newOp3.getImm()+4); 9741 else 9742 newOp3.setOffset(newOp3.getOffset()+4); 9743 (*MIB).addOperand(newOp3); 9744 (*MIB).addOperand(*argOpers[lastAddrIndx]); 9745 9746 // t3/4 are defined later, at the bottom of the loop 9747 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 9748 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 9749 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 9750 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 9751 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 9752 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 9753 9754 // The subsequent operations should be using the destination registers of 9755 //the PHI instructions. 9756 if (invSrc) { 9757 t1 = F->getRegInfo().createVirtualRegister(RC); 9758 t2 = F->getRegInfo().createVirtualRegister(RC); 9759 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 9760 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 9761 } else { 9762 t1 = dest1Oper.getReg(); 9763 t2 = dest2Oper.getReg(); 9764 } 9765 9766 int valArgIndx = lastAddrIndx + 1; 9767 assert((argOpers[valArgIndx]->isReg() || 9768 argOpers[valArgIndx]->isImm()) && 9769 "invalid operand"); 9770 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 9771 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 9772 if (argOpers[valArgIndx]->isReg()) 9773 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 9774 else 9775 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 9776 if (regOpcL != X86::MOV32rr) 9777 MIB.addReg(t1); 9778 (*MIB).addOperand(*argOpers[valArgIndx]); 9779 assert(argOpers[valArgIndx + 1]->isReg() == 9780 argOpers[valArgIndx]->isReg()); 9781 assert(argOpers[valArgIndx + 1]->isImm() == 9782 argOpers[valArgIndx]->isImm()); 9783 if (argOpers[valArgIndx + 1]->isReg()) 9784 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 9785 else 9786 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 9787 if (regOpcH != X86::MOV32rr) 9788 MIB.addReg(t2); 9789 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 9790 9791 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 9792 MIB.addReg(t1); 9793 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 9794 MIB.addReg(t2); 9795 9796 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 9797 MIB.addReg(t5); 9798 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 9799 MIB.addReg(t6); 9800 9801 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 9802 for (int i=0; i <= lastAddrIndx; ++i) 9803 (*MIB).addOperand(*argOpers[i]); 9804 9805 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9806 (*MIB).setMemRefs(bInstr->memoperands_begin(), 9807 bInstr->memoperands_end()); 9808 9809 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 9810 MIB.addReg(X86::EAX); 9811 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 9812 MIB.addReg(X86::EDX); 9813 9814 // insert branch 9815 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9816 9817 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 9818 return nextMBB; 9819} 9820 9821// private utility function 9822MachineBasicBlock * 9823X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 9824 MachineBasicBlock *MBB, 9825 unsigned cmovOpc) const { 9826 // For the atomic min/max operator, we generate 9827 // thisMBB: 9828 // newMBB: 9829 // ld t1 = [min/max.addr] 9830 // mov t2 = [min/max.val] 9831 // cmp t1, t2 9832 // cmov[cond] t2 = t1 9833 // mov EAX = t1 9834 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 9835 // bz newMBB 9836 // fallthrough -->nextMBB 9837 // 9838 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9839 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9840 MachineFunction::iterator MBBIter = MBB; 9841 ++MBBIter; 9842 9843 /// First build the CFG 9844 MachineFunction *F = MBB->getParent(); 9845 MachineBasicBlock *thisMBB = MBB; 9846 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 9847 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 9848 F->insert(MBBIter, newMBB); 9849 F->insert(MBBIter, nextMBB); 9850 9851 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 9852 nextMBB->splice(nextMBB->begin(), thisMBB, 9853 llvm::next(MachineBasicBlock::iterator(mInstr)), 9854 thisMBB->end()); 9855 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 9856 9857 // Update thisMBB to fall through to newMBB 9858 thisMBB->addSuccessor(newMBB); 9859 9860 // newMBB jumps to newMBB and fall through to nextMBB 9861 newMBB->addSuccessor(nextMBB); 9862 newMBB->addSuccessor(newMBB); 9863 9864 DebugLoc dl = mInstr->getDebugLoc(); 9865 // Insert instructions into newMBB based on incoming instruction 9866 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 9867 "unexpected number of operands"); 9868 MachineOperand& destOper = mInstr->getOperand(0); 9869 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 9870 int numArgs = mInstr->getNumOperands() - 1; 9871 for (int i=0; i < numArgs; ++i) 9872 argOpers[i] = &mInstr->getOperand(i+1); 9873 9874 // x86 address has 4 operands: base, index, scale, and displacement 9875 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 9876 int valArgIndx = lastAddrIndx + 1; 9877 9878 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9879 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 9880 for (int i=0; i <= lastAddrIndx; ++i) 9881 (*MIB).addOperand(*argOpers[i]); 9882 9883 // We only support register and immediate values 9884 assert((argOpers[valArgIndx]->isReg() || 9885 argOpers[valArgIndx]->isImm()) && 9886 "invalid operand"); 9887 9888 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9889 if (argOpers[valArgIndx]->isReg()) 9890 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 9891 else 9892 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 9893 (*MIB).addOperand(*argOpers[valArgIndx]); 9894 9895 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 9896 MIB.addReg(t1); 9897 9898 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 9899 MIB.addReg(t1); 9900 MIB.addReg(t2); 9901 9902 // Generate movc 9903 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9904 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 9905 MIB.addReg(t2); 9906 MIB.addReg(t1); 9907 9908 // Cmp and exchange if none has modified the memory location 9909 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 9910 for (int i=0; i <= lastAddrIndx; ++i) 9911 (*MIB).addOperand(*argOpers[i]); 9912 MIB.addReg(t3); 9913 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9914 (*MIB).setMemRefs(mInstr->memoperands_begin(), 9915 mInstr->memoperands_end()); 9916 9917 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 9918 MIB.addReg(X86::EAX); 9919 9920 // insert branch 9921 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9922 9923 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 9924 return nextMBB; 9925} 9926 9927// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 9928// or XMM0_V32I8 in AVX all of this code can be replaced with that 9929// in the .td file. 9930MachineBasicBlock * 9931X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 9932 unsigned numArgs, bool memArg) const { 9933 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 9934 "Target must have SSE4.2 or AVX features enabled"); 9935 9936 DebugLoc dl = MI->getDebugLoc(); 9937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9938 unsigned Opc; 9939 if (!Subtarget->hasAVX()) { 9940 if (memArg) 9941 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 9942 else 9943 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 9944 } else { 9945 if (memArg) 9946 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 9947 else 9948 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 9949 } 9950 9951 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 9952 for (unsigned i = 0; i < numArgs; ++i) { 9953 MachineOperand &Op = MI->getOperand(i+1); 9954 if (!(Op.isReg() && Op.isImplicit())) 9955 MIB.addOperand(Op); 9956 } 9957 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 9958 .addReg(X86::XMM0); 9959 9960 MI->eraseFromParent(); 9961 return BB; 9962} 9963 9964MachineBasicBlock * 9965X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 9966 DebugLoc dl = MI->getDebugLoc(); 9967 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9968 9969 // Address into RAX/EAX, other two args into ECX, EDX. 9970 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 9971 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 9972 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 9973 for (int i = 0; i < X86::AddrNumOperands; ++i) 9974 MIB.addOperand(MI->getOperand(i)); 9975 9976 unsigned ValOps = X86::AddrNumOperands; 9977 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 9978 .addReg(MI->getOperand(ValOps).getReg()); 9979 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 9980 .addReg(MI->getOperand(ValOps+1).getReg()); 9981 9982 // The instruction doesn't actually take any operands though. 9983 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 9984 9985 MI->eraseFromParent(); // The pseudo is gone now. 9986 return BB; 9987} 9988 9989MachineBasicBlock * 9990X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 9991 DebugLoc dl = MI->getDebugLoc(); 9992 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9993 9994 // First arg in ECX, the second in EAX. 9995 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 9996 .addReg(MI->getOperand(0).getReg()); 9997 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 9998 .addReg(MI->getOperand(1).getReg()); 9999 10000 // The instruction doesn't actually take any operands though. 10001 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 10002 10003 MI->eraseFromParent(); // The pseudo is gone now. 10004 return BB; 10005} 10006 10007MachineBasicBlock * 10008X86TargetLowering::EmitVAARG64WithCustomInserter( 10009 MachineInstr *MI, 10010 MachineBasicBlock *MBB) const { 10011 // Emit va_arg instruction on X86-64. 10012 10013 // Operands to this pseudo-instruction: 10014 // 0 ) Output : destination address (reg) 10015 // 1-5) Input : va_list address (addr, i64mem) 10016 // 6 ) ArgSize : Size (in bytes) of vararg type 10017 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 10018 // 8 ) Align : Alignment of type 10019 // 9 ) EFLAGS (implicit-def) 10020 10021 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 10022 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 10023 10024 unsigned DestReg = MI->getOperand(0).getReg(); 10025 MachineOperand &Base = MI->getOperand(1); 10026 MachineOperand &Scale = MI->getOperand(2); 10027 MachineOperand &Index = MI->getOperand(3); 10028 MachineOperand &Disp = MI->getOperand(4); 10029 MachineOperand &Segment = MI->getOperand(5); 10030 unsigned ArgSize = MI->getOperand(6).getImm(); 10031 unsigned ArgMode = MI->getOperand(7).getImm(); 10032 unsigned Align = MI->getOperand(8).getImm(); 10033 10034 // Memory Reference 10035 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 10036 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 10037 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 10038 10039 // Machine Information 10040 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10041 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 10042 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 10043 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 10044 DebugLoc DL = MI->getDebugLoc(); 10045 10046 // struct va_list { 10047 // i32 gp_offset 10048 // i32 fp_offset 10049 // i64 overflow_area (address) 10050 // i64 reg_save_area (address) 10051 // } 10052 // sizeof(va_list) = 24 10053 // alignment(va_list) = 8 10054 10055 unsigned TotalNumIntRegs = 6; 10056 unsigned TotalNumXMMRegs = 8; 10057 bool UseGPOffset = (ArgMode == 1); 10058 bool UseFPOffset = (ArgMode == 2); 10059 unsigned MaxOffset = TotalNumIntRegs * 8 + 10060 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 10061 10062 /* Align ArgSize to a multiple of 8 */ 10063 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 10064 bool NeedsAlign = (Align > 8); 10065 10066 MachineBasicBlock *thisMBB = MBB; 10067 MachineBasicBlock *overflowMBB; 10068 MachineBasicBlock *offsetMBB; 10069 MachineBasicBlock *endMBB; 10070 10071 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 10072 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 10073 unsigned OffsetReg = 0; 10074 10075 if (!UseGPOffset && !UseFPOffset) { 10076 // If we only pull from the overflow region, we don't create a branch. 10077 // We don't need to alter control flow. 10078 OffsetDestReg = 0; // unused 10079 OverflowDestReg = DestReg; 10080 10081 offsetMBB = NULL; 10082 overflowMBB = thisMBB; 10083 endMBB = thisMBB; 10084 } else { 10085 // First emit code to check if gp_offset (or fp_offset) is below the bound. 10086 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 10087 // If not, pull from overflow_area. (branch to overflowMBB) 10088 // 10089 // thisMBB 10090 // | . 10091 // | . 10092 // offsetMBB overflowMBB 10093 // | . 10094 // | . 10095 // endMBB 10096 10097 // Registers for the PHI in endMBB 10098 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 10099 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 10100 10101 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10102 MachineFunction *MF = MBB->getParent(); 10103 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10104 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10105 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10106 10107 MachineFunction::iterator MBBIter = MBB; 10108 ++MBBIter; 10109 10110 // Insert the new basic blocks 10111 MF->insert(MBBIter, offsetMBB); 10112 MF->insert(MBBIter, overflowMBB); 10113 MF->insert(MBBIter, endMBB); 10114 10115 // Transfer the remainder of MBB and its successor edges to endMBB. 10116 endMBB->splice(endMBB->begin(), thisMBB, 10117 llvm::next(MachineBasicBlock::iterator(MI)), 10118 thisMBB->end()); 10119 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10120 10121 // Make offsetMBB and overflowMBB successors of thisMBB 10122 thisMBB->addSuccessor(offsetMBB); 10123 thisMBB->addSuccessor(overflowMBB); 10124 10125 // endMBB is a successor of both offsetMBB and overflowMBB 10126 offsetMBB->addSuccessor(endMBB); 10127 overflowMBB->addSuccessor(endMBB); 10128 10129 // Load the offset value into a register 10130 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10131 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 10132 .addOperand(Base) 10133 .addOperand(Scale) 10134 .addOperand(Index) 10135 .addDisp(Disp, UseFPOffset ? 4 : 0) 10136 .addOperand(Segment) 10137 .setMemRefs(MMOBegin, MMOEnd); 10138 10139 // Check if there is enough room left to pull this argument. 10140 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 10141 .addReg(OffsetReg) 10142 .addImm(MaxOffset + 8 - ArgSizeA8); 10143 10144 // Branch to "overflowMBB" if offset >= max 10145 // Fall through to "offsetMBB" otherwise 10146 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 10147 .addMBB(overflowMBB); 10148 } 10149 10150 // In offsetMBB, emit code to use the reg_save_area. 10151 if (offsetMBB) { 10152 assert(OffsetReg != 0); 10153 10154 // Read the reg_save_area address. 10155 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 10156 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 10157 .addOperand(Base) 10158 .addOperand(Scale) 10159 .addOperand(Index) 10160 .addDisp(Disp, 16) 10161 .addOperand(Segment) 10162 .setMemRefs(MMOBegin, MMOEnd); 10163 10164 // Zero-extend the offset 10165 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 10166 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 10167 .addImm(0) 10168 .addReg(OffsetReg) 10169 .addImm(X86::sub_32bit); 10170 10171 // Add the offset to the reg_save_area to get the final address. 10172 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 10173 .addReg(OffsetReg64) 10174 .addReg(RegSaveReg); 10175 10176 // Compute the offset for the next argument 10177 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10178 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 10179 .addReg(OffsetReg) 10180 .addImm(UseFPOffset ? 16 : 8); 10181 10182 // Store it back into the va_list. 10183 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 10184 .addOperand(Base) 10185 .addOperand(Scale) 10186 .addOperand(Index) 10187 .addDisp(Disp, UseFPOffset ? 4 : 0) 10188 .addOperand(Segment) 10189 .addReg(NextOffsetReg) 10190 .setMemRefs(MMOBegin, MMOEnd); 10191 10192 // Jump to endMBB 10193 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 10194 .addMBB(endMBB); 10195 } 10196 10197 // 10198 // Emit code to use overflow area 10199 // 10200 10201 // Load the overflow_area address into a register. 10202 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 10203 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 10204 .addOperand(Base) 10205 .addOperand(Scale) 10206 .addOperand(Index) 10207 .addDisp(Disp, 8) 10208 .addOperand(Segment) 10209 .setMemRefs(MMOBegin, MMOEnd); 10210 10211 // If we need to align it, do so. Otherwise, just copy the address 10212 // to OverflowDestReg. 10213 if (NeedsAlign) { 10214 // Align the overflow address 10215 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 10216 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 10217 10218 // aligned_addr = (addr + (align-1)) & ~(align-1) 10219 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 10220 .addReg(OverflowAddrReg) 10221 .addImm(Align-1); 10222 10223 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 10224 .addReg(TmpReg) 10225 .addImm(~(uint64_t)(Align-1)); 10226 } else { 10227 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 10228 .addReg(OverflowAddrReg); 10229 } 10230 10231 // Compute the next overflow address after this argument. 10232 // (the overflow address should be kept 8-byte aligned) 10233 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 10234 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 10235 .addReg(OverflowDestReg) 10236 .addImm(ArgSizeA8); 10237 10238 // Store the new overflow address. 10239 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 10240 .addOperand(Base) 10241 .addOperand(Scale) 10242 .addOperand(Index) 10243 .addDisp(Disp, 8) 10244 .addOperand(Segment) 10245 .addReg(NextAddrReg) 10246 .setMemRefs(MMOBegin, MMOEnd); 10247 10248 // If we branched, emit the PHI to the front of endMBB. 10249 if (offsetMBB) { 10250 BuildMI(*endMBB, endMBB->begin(), DL, 10251 TII->get(X86::PHI), DestReg) 10252 .addReg(OffsetDestReg).addMBB(offsetMBB) 10253 .addReg(OverflowDestReg).addMBB(overflowMBB); 10254 } 10255 10256 // Erase the pseudo instruction 10257 MI->eraseFromParent(); 10258 10259 return endMBB; 10260} 10261 10262MachineBasicBlock * 10263X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 10264 MachineInstr *MI, 10265 MachineBasicBlock *MBB) const { 10266 // Emit code to save XMM registers to the stack. The ABI says that the 10267 // number of registers to save is given in %al, so it's theoretically 10268 // possible to do an indirect jump trick to avoid saving all of them, 10269 // however this code takes a simpler approach and just executes all 10270 // of the stores if %al is non-zero. It's less code, and it's probably 10271 // easier on the hardware branch predictor, and stores aren't all that 10272 // expensive anyway. 10273 10274 // Create the new basic blocks. One block contains all the XMM stores, 10275 // and one block is the final destination regardless of whether any 10276 // stores were performed. 10277 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10278 MachineFunction *F = MBB->getParent(); 10279 MachineFunction::iterator MBBIter = MBB; 10280 ++MBBIter; 10281 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 10282 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 10283 F->insert(MBBIter, XMMSaveMBB); 10284 F->insert(MBBIter, EndMBB); 10285 10286 // Transfer the remainder of MBB and its successor edges to EndMBB. 10287 EndMBB->splice(EndMBB->begin(), MBB, 10288 llvm::next(MachineBasicBlock::iterator(MI)), 10289 MBB->end()); 10290 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 10291 10292 // The original block will now fall through to the XMM save block. 10293 MBB->addSuccessor(XMMSaveMBB); 10294 // The XMMSaveMBB will fall through to the end block. 10295 XMMSaveMBB->addSuccessor(EndMBB); 10296 10297 // Now add the instructions. 10298 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10299 DebugLoc DL = MI->getDebugLoc(); 10300 10301 unsigned CountReg = MI->getOperand(0).getReg(); 10302 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 10303 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 10304 10305 if (!Subtarget->isTargetWin64()) { 10306 // If %al is 0, branch around the XMM save block. 10307 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 10308 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 10309 MBB->addSuccessor(EndMBB); 10310 } 10311 10312 // In the XMM save block, save all the XMM argument registers. 10313 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 10314 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 10315 MachineMemOperand *MMO = 10316 F->getMachineMemOperand( 10317 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 10318 MachineMemOperand::MOStore, 10319 /*Size=*/16, /*Align=*/16); 10320 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 10321 .addFrameIndex(RegSaveFrameIndex) 10322 .addImm(/*Scale=*/1) 10323 .addReg(/*IndexReg=*/0) 10324 .addImm(/*Disp=*/Offset) 10325 .addReg(/*Segment=*/0) 10326 .addReg(MI->getOperand(i).getReg()) 10327 .addMemOperand(MMO); 10328 } 10329 10330 MI->eraseFromParent(); // The pseudo instruction is gone now. 10331 10332 return EndMBB; 10333} 10334 10335MachineBasicBlock * 10336X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 10337 MachineBasicBlock *BB) const { 10338 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10339 DebugLoc DL = MI->getDebugLoc(); 10340 10341 // To "insert" a SELECT_CC instruction, we actually have to insert the 10342 // diamond control-flow pattern. The incoming instruction knows the 10343 // destination vreg to set, the condition code register to branch on, the 10344 // true/false values to select between, and a branch opcode to use. 10345 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 10346 MachineFunction::iterator It = BB; 10347 ++It; 10348 10349 // thisMBB: 10350 // ... 10351 // TrueVal = ... 10352 // cmpTY ccX, r1, r2 10353 // bCC copy1MBB 10354 // fallthrough --> copy0MBB 10355 MachineBasicBlock *thisMBB = BB; 10356 MachineFunction *F = BB->getParent(); 10357 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 10358 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 10359 F->insert(It, copy0MBB); 10360 F->insert(It, sinkMBB); 10361 10362 // If the EFLAGS register isn't dead in the terminator, then claim that it's 10363 // live into the sink and copy blocks. 10364 const MachineFunction *MF = BB->getParent(); 10365 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 10366 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 10367 10368 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 10369 const MachineOperand &MO = MI->getOperand(I); 10370 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 10371 unsigned Reg = MO.getReg(); 10372 if (Reg != X86::EFLAGS) continue; 10373 copy0MBB->addLiveIn(Reg); 10374 sinkMBB->addLiveIn(Reg); 10375 } 10376 10377 // Transfer the remainder of BB and its successor edges to sinkMBB. 10378 sinkMBB->splice(sinkMBB->begin(), BB, 10379 llvm::next(MachineBasicBlock::iterator(MI)), 10380 BB->end()); 10381 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 10382 10383 // Add the true and fallthrough blocks as its successors. 10384 BB->addSuccessor(copy0MBB); 10385 BB->addSuccessor(sinkMBB); 10386 10387 // Create the conditional branch instruction. 10388 unsigned Opc = 10389 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 10390 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 10391 10392 // copy0MBB: 10393 // %FalseValue = ... 10394 // # fallthrough to sinkMBB 10395 copy0MBB->addSuccessor(sinkMBB); 10396 10397 // sinkMBB: 10398 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 10399 // ... 10400 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 10401 TII->get(X86::PHI), MI->getOperand(0).getReg()) 10402 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 10403 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 10404 10405 MI->eraseFromParent(); // The pseudo instruction is gone now. 10406 return sinkMBB; 10407} 10408 10409MachineBasicBlock * 10410X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 10411 MachineBasicBlock *BB) const { 10412 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10413 DebugLoc DL = MI->getDebugLoc(); 10414 10415 // The lowering is pretty easy: we're just emitting the call to _alloca. The 10416 // non-trivial part is impdef of ESP. 10417 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 10418 // mingw-w64. 10419 10420 const char *StackProbeSymbol = 10421 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 10422 10423 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 10424 .addExternalSymbol(StackProbeSymbol) 10425 .addReg(X86::EAX, RegState::Implicit) 10426 .addReg(X86::ESP, RegState::Implicit) 10427 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 10428 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 10429 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 10430 10431 MI->eraseFromParent(); // The pseudo instruction is gone now. 10432 return BB; 10433} 10434 10435MachineBasicBlock * 10436X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 10437 MachineBasicBlock *BB) const { 10438 // This is pretty easy. We're taking the value that we received from 10439 // our load from the relocation, sticking it in either RDI (x86-64) 10440 // or EAX and doing an indirect call. The return value will then 10441 // be in the normal return register. 10442 const X86InstrInfo *TII 10443 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 10444 DebugLoc DL = MI->getDebugLoc(); 10445 MachineFunction *F = BB->getParent(); 10446 10447 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 10448 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 10449 10450 if (Subtarget->is64Bit()) { 10451 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 10452 TII->get(X86::MOV64rm), X86::RDI) 10453 .addReg(X86::RIP) 10454 .addImm(0).addReg(0) 10455 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 10456 MI->getOperand(3).getTargetFlags()) 10457 .addReg(0); 10458 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 10459 addDirectMem(MIB, X86::RDI); 10460 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 10461 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 10462 TII->get(X86::MOV32rm), X86::EAX) 10463 .addReg(0) 10464 .addImm(0).addReg(0) 10465 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 10466 MI->getOperand(3).getTargetFlags()) 10467 .addReg(0); 10468 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 10469 addDirectMem(MIB, X86::EAX); 10470 } else { 10471 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 10472 TII->get(X86::MOV32rm), X86::EAX) 10473 .addReg(TII->getGlobalBaseReg(F)) 10474 .addImm(0).addReg(0) 10475 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 10476 MI->getOperand(3).getTargetFlags()) 10477 .addReg(0); 10478 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 10479 addDirectMem(MIB, X86::EAX); 10480 } 10481 10482 MI->eraseFromParent(); // The pseudo instruction is gone now. 10483 return BB; 10484} 10485 10486MachineBasicBlock * 10487X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 10488 MachineBasicBlock *BB) const { 10489 switch (MI->getOpcode()) { 10490 default: assert(false && "Unexpected instr type to insert"); 10491 case X86::TAILJMPd64: 10492 case X86::TAILJMPr64: 10493 case X86::TAILJMPm64: 10494 assert(!"TAILJMP64 would not be touched here."); 10495 case X86::TCRETURNdi64: 10496 case X86::TCRETURNri64: 10497 case X86::TCRETURNmi64: 10498 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 10499 // On AMD64, additional defs should be added before register allocation. 10500 if (!Subtarget->isTargetWin64()) { 10501 MI->addRegisterDefined(X86::RSI); 10502 MI->addRegisterDefined(X86::RDI); 10503 MI->addRegisterDefined(X86::XMM6); 10504 MI->addRegisterDefined(X86::XMM7); 10505 MI->addRegisterDefined(X86::XMM8); 10506 MI->addRegisterDefined(X86::XMM9); 10507 MI->addRegisterDefined(X86::XMM10); 10508 MI->addRegisterDefined(X86::XMM11); 10509 MI->addRegisterDefined(X86::XMM12); 10510 MI->addRegisterDefined(X86::XMM13); 10511 MI->addRegisterDefined(X86::XMM14); 10512 MI->addRegisterDefined(X86::XMM15); 10513 } 10514 return BB; 10515 case X86::WIN_ALLOCA: 10516 return EmitLoweredWinAlloca(MI, BB); 10517 case X86::TLSCall_32: 10518 case X86::TLSCall_64: 10519 return EmitLoweredTLSCall(MI, BB); 10520 case X86::CMOV_GR8: 10521 case X86::CMOV_FR32: 10522 case X86::CMOV_FR64: 10523 case X86::CMOV_V4F32: 10524 case X86::CMOV_V2F64: 10525 case X86::CMOV_V2I64: 10526 case X86::CMOV_GR16: 10527 case X86::CMOV_GR32: 10528 case X86::CMOV_RFP32: 10529 case X86::CMOV_RFP64: 10530 case X86::CMOV_RFP80: 10531 return EmitLoweredSelect(MI, BB); 10532 10533 case X86::FP32_TO_INT16_IN_MEM: 10534 case X86::FP32_TO_INT32_IN_MEM: 10535 case X86::FP32_TO_INT64_IN_MEM: 10536 case X86::FP64_TO_INT16_IN_MEM: 10537 case X86::FP64_TO_INT32_IN_MEM: 10538 case X86::FP64_TO_INT64_IN_MEM: 10539 case X86::FP80_TO_INT16_IN_MEM: 10540 case X86::FP80_TO_INT32_IN_MEM: 10541 case X86::FP80_TO_INT64_IN_MEM: { 10542 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10543 DebugLoc DL = MI->getDebugLoc(); 10544 10545 // Change the floating point control register to use "round towards zero" 10546 // mode when truncating to an integer value. 10547 MachineFunction *F = BB->getParent(); 10548 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 10549 addFrameReference(BuildMI(*BB, MI, DL, 10550 TII->get(X86::FNSTCW16m)), CWFrameIdx); 10551 10552 // Load the old value of the high byte of the control word... 10553 unsigned OldCW = 10554 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 10555 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 10556 CWFrameIdx); 10557 10558 // Set the high part to be round to zero... 10559 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 10560 .addImm(0xC7F); 10561 10562 // Reload the modified control word now... 10563 addFrameReference(BuildMI(*BB, MI, DL, 10564 TII->get(X86::FLDCW16m)), CWFrameIdx); 10565 10566 // Restore the memory image of control word to original value 10567 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 10568 .addReg(OldCW); 10569 10570 // Get the X86 opcode to use. 10571 unsigned Opc; 10572 switch (MI->getOpcode()) { 10573 default: llvm_unreachable("illegal opcode!"); 10574 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 10575 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 10576 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 10577 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 10578 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 10579 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 10580 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 10581 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 10582 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 10583 } 10584 10585 X86AddressMode AM; 10586 MachineOperand &Op = MI->getOperand(0); 10587 if (Op.isReg()) { 10588 AM.BaseType = X86AddressMode::RegBase; 10589 AM.Base.Reg = Op.getReg(); 10590 } else { 10591 AM.BaseType = X86AddressMode::FrameIndexBase; 10592 AM.Base.FrameIndex = Op.getIndex(); 10593 } 10594 Op = MI->getOperand(1); 10595 if (Op.isImm()) 10596 AM.Scale = Op.getImm(); 10597 Op = MI->getOperand(2); 10598 if (Op.isImm()) 10599 AM.IndexReg = Op.getImm(); 10600 Op = MI->getOperand(3); 10601 if (Op.isGlobal()) { 10602 AM.GV = Op.getGlobal(); 10603 } else { 10604 AM.Disp = Op.getImm(); 10605 } 10606 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 10607 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 10608 10609 // Reload the original control word now. 10610 addFrameReference(BuildMI(*BB, MI, DL, 10611 TII->get(X86::FLDCW16m)), CWFrameIdx); 10612 10613 MI->eraseFromParent(); // The pseudo instruction is gone now. 10614 return BB; 10615 } 10616 // String/text processing lowering. 10617 case X86::PCMPISTRM128REG: 10618 case X86::VPCMPISTRM128REG: 10619 return EmitPCMP(MI, BB, 3, false /* in-mem */); 10620 case X86::PCMPISTRM128MEM: 10621 case X86::VPCMPISTRM128MEM: 10622 return EmitPCMP(MI, BB, 3, true /* in-mem */); 10623 case X86::PCMPESTRM128REG: 10624 case X86::VPCMPESTRM128REG: 10625 return EmitPCMP(MI, BB, 5, false /* in mem */); 10626 case X86::PCMPESTRM128MEM: 10627 case X86::VPCMPESTRM128MEM: 10628 return EmitPCMP(MI, BB, 5, true /* in mem */); 10629 10630 // Thread synchronization. 10631 case X86::MONITOR: 10632 return EmitMonitor(MI, BB); 10633 case X86::MWAIT: 10634 return EmitMwait(MI, BB); 10635 10636 // Atomic Lowering. 10637 case X86::ATOMAND32: 10638 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 10639 X86::AND32ri, X86::MOV32rm, 10640 X86::LCMPXCHG32, 10641 X86::NOT32r, X86::EAX, 10642 X86::GR32RegisterClass); 10643 case X86::ATOMOR32: 10644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 10645 X86::OR32ri, X86::MOV32rm, 10646 X86::LCMPXCHG32, 10647 X86::NOT32r, X86::EAX, 10648 X86::GR32RegisterClass); 10649 case X86::ATOMXOR32: 10650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 10651 X86::XOR32ri, X86::MOV32rm, 10652 X86::LCMPXCHG32, 10653 X86::NOT32r, X86::EAX, 10654 X86::GR32RegisterClass); 10655 case X86::ATOMNAND32: 10656 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 10657 X86::AND32ri, X86::MOV32rm, 10658 X86::LCMPXCHG32, 10659 X86::NOT32r, X86::EAX, 10660 X86::GR32RegisterClass, true); 10661 case X86::ATOMMIN32: 10662 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 10663 case X86::ATOMMAX32: 10664 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 10665 case X86::ATOMUMIN32: 10666 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 10667 case X86::ATOMUMAX32: 10668 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 10669 10670 case X86::ATOMAND16: 10671 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 10672 X86::AND16ri, X86::MOV16rm, 10673 X86::LCMPXCHG16, 10674 X86::NOT16r, X86::AX, 10675 X86::GR16RegisterClass); 10676 case X86::ATOMOR16: 10677 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 10678 X86::OR16ri, X86::MOV16rm, 10679 X86::LCMPXCHG16, 10680 X86::NOT16r, X86::AX, 10681 X86::GR16RegisterClass); 10682 case X86::ATOMXOR16: 10683 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 10684 X86::XOR16ri, X86::MOV16rm, 10685 X86::LCMPXCHG16, 10686 X86::NOT16r, X86::AX, 10687 X86::GR16RegisterClass); 10688 case X86::ATOMNAND16: 10689 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 10690 X86::AND16ri, X86::MOV16rm, 10691 X86::LCMPXCHG16, 10692 X86::NOT16r, X86::AX, 10693 X86::GR16RegisterClass, true); 10694 case X86::ATOMMIN16: 10695 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 10696 case X86::ATOMMAX16: 10697 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 10698 case X86::ATOMUMIN16: 10699 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 10700 case X86::ATOMUMAX16: 10701 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 10702 10703 case X86::ATOMAND8: 10704 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 10705 X86::AND8ri, X86::MOV8rm, 10706 X86::LCMPXCHG8, 10707 X86::NOT8r, X86::AL, 10708 X86::GR8RegisterClass); 10709 case X86::ATOMOR8: 10710 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 10711 X86::OR8ri, X86::MOV8rm, 10712 X86::LCMPXCHG8, 10713 X86::NOT8r, X86::AL, 10714 X86::GR8RegisterClass); 10715 case X86::ATOMXOR8: 10716 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 10717 X86::XOR8ri, X86::MOV8rm, 10718 X86::LCMPXCHG8, 10719 X86::NOT8r, X86::AL, 10720 X86::GR8RegisterClass); 10721 case X86::ATOMNAND8: 10722 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 10723 X86::AND8ri, X86::MOV8rm, 10724 X86::LCMPXCHG8, 10725 X86::NOT8r, X86::AL, 10726 X86::GR8RegisterClass, true); 10727 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 10728 // This group is for 64-bit host. 10729 case X86::ATOMAND64: 10730 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 10731 X86::AND64ri32, X86::MOV64rm, 10732 X86::LCMPXCHG64, 10733 X86::NOT64r, X86::RAX, 10734 X86::GR64RegisterClass); 10735 case X86::ATOMOR64: 10736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 10737 X86::OR64ri32, X86::MOV64rm, 10738 X86::LCMPXCHG64, 10739 X86::NOT64r, X86::RAX, 10740 X86::GR64RegisterClass); 10741 case X86::ATOMXOR64: 10742 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 10743 X86::XOR64ri32, X86::MOV64rm, 10744 X86::LCMPXCHG64, 10745 X86::NOT64r, X86::RAX, 10746 X86::GR64RegisterClass); 10747 case X86::ATOMNAND64: 10748 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 10749 X86::AND64ri32, X86::MOV64rm, 10750 X86::LCMPXCHG64, 10751 X86::NOT64r, X86::RAX, 10752 X86::GR64RegisterClass, true); 10753 case X86::ATOMMIN64: 10754 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 10755 case X86::ATOMMAX64: 10756 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 10757 case X86::ATOMUMIN64: 10758 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 10759 case X86::ATOMUMAX64: 10760 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 10761 10762 // This group does 64-bit operations on a 32-bit host. 10763 case X86::ATOMAND6432: 10764 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10765 X86::AND32rr, X86::AND32rr, 10766 X86::AND32ri, X86::AND32ri, 10767 false); 10768 case X86::ATOMOR6432: 10769 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10770 X86::OR32rr, X86::OR32rr, 10771 X86::OR32ri, X86::OR32ri, 10772 false); 10773 case X86::ATOMXOR6432: 10774 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10775 X86::XOR32rr, X86::XOR32rr, 10776 X86::XOR32ri, X86::XOR32ri, 10777 false); 10778 case X86::ATOMNAND6432: 10779 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10780 X86::AND32rr, X86::AND32rr, 10781 X86::AND32ri, X86::AND32ri, 10782 true); 10783 case X86::ATOMADD6432: 10784 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10785 X86::ADD32rr, X86::ADC32rr, 10786 X86::ADD32ri, X86::ADC32ri, 10787 false); 10788 case X86::ATOMSUB6432: 10789 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10790 X86::SUB32rr, X86::SBB32rr, 10791 X86::SUB32ri, X86::SBB32ri, 10792 false); 10793 case X86::ATOMSWAP6432: 10794 return EmitAtomicBit6432WithCustomInserter(MI, BB, 10795 X86::MOV32rr, X86::MOV32rr, 10796 X86::MOV32ri, X86::MOV32ri, 10797 false); 10798 case X86::VASTART_SAVE_XMM_REGS: 10799 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 10800 10801 case X86::VAARG_64: 10802 return EmitVAARG64WithCustomInserter(MI, BB); 10803 } 10804} 10805 10806//===----------------------------------------------------------------------===// 10807// X86 Optimization Hooks 10808//===----------------------------------------------------------------------===// 10809 10810void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 10811 const APInt &Mask, 10812 APInt &KnownZero, 10813 APInt &KnownOne, 10814 const SelectionDAG &DAG, 10815 unsigned Depth) const { 10816 unsigned Opc = Op.getOpcode(); 10817 assert((Opc >= ISD::BUILTIN_OP_END || 10818 Opc == ISD::INTRINSIC_WO_CHAIN || 10819 Opc == ISD::INTRINSIC_W_CHAIN || 10820 Opc == ISD::INTRINSIC_VOID) && 10821 "Should use MaskedValueIsZero if you don't know whether Op" 10822 " is a target node!"); 10823 10824 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 10825 switch (Opc) { 10826 default: break; 10827 case X86ISD::ADD: 10828 case X86ISD::SUB: 10829 case X86ISD::ADC: 10830 case X86ISD::SBB: 10831 case X86ISD::SMUL: 10832 case X86ISD::UMUL: 10833 case X86ISD::INC: 10834 case X86ISD::DEC: 10835 case X86ISD::OR: 10836 case X86ISD::XOR: 10837 case X86ISD::AND: 10838 // These nodes' second result is a boolean. 10839 if (Op.getResNo() == 0) 10840 break; 10841 // Fallthrough 10842 case X86ISD::SETCC: 10843 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 10844 Mask.getBitWidth() - 1); 10845 break; 10846 } 10847} 10848 10849unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 10850 unsigned Depth) const { 10851 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 10852 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 10853 return Op.getValueType().getScalarType().getSizeInBits(); 10854 10855 // Fallback case. 10856 return 1; 10857} 10858 10859/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 10860/// node is a GlobalAddress + offset. 10861bool X86TargetLowering::isGAPlusOffset(SDNode *N, 10862 const GlobalValue* &GA, 10863 int64_t &Offset) const { 10864 if (N->getOpcode() == X86ISD::Wrapper) { 10865 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 10866 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 10867 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 10868 return true; 10869 } 10870 } 10871 return TargetLowering::isGAPlusOffset(N, GA, Offset); 10872} 10873 10874/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 10875/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 10876/// if the load addresses are consecutive, non-overlapping, and in the right 10877/// order. 10878static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 10879 TargetLowering::DAGCombinerInfo &DCI) { 10880 DebugLoc dl = N->getDebugLoc(); 10881 EVT VT = N->getValueType(0); 10882 10883 if (VT.getSizeInBits() != 128) 10884 return SDValue(); 10885 10886 // Don't create instructions with illegal types after legalize types has run. 10887 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10888 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 10889 return SDValue(); 10890 10891 SmallVector<SDValue, 16> Elts; 10892 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 10893 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 10894 10895 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 10896} 10897 10898/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 10899/// generation and convert it from being a bunch of shuffles and extracts 10900/// to a simple store and scalar loads to extract the elements. 10901static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 10902 const TargetLowering &TLI) { 10903 SDValue InputVector = N->getOperand(0); 10904 10905 // Only operate on vectors of 4 elements, where the alternative shuffling 10906 // gets to be more expensive. 10907 if (InputVector.getValueType() != MVT::v4i32) 10908 return SDValue(); 10909 10910 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 10911 // single use which is a sign-extend or zero-extend, and all elements are 10912 // used. 10913 SmallVector<SDNode *, 4> Uses; 10914 unsigned ExtractedElements = 0; 10915 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 10916 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 10917 if (UI.getUse().getResNo() != InputVector.getResNo()) 10918 return SDValue(); 10919 10920 SDNode *Extract = *UI; 10921 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 10922 return SDValue(); 10923 10924 if (Extract->getValueType(0) != MVT::i32) 10925 return SDValue(); 10926 if (!Extract->hasOneUse()) 10927 return SDValue(); 10928 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 10929 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 10930 return SDValue(); 10931 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 10932 return SDValue(); 10933 10934 // Record which element was extracted. 10935 ExtractedElements |= 10936 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 10937 10938 Uses.push_back(Extract); 10939 } 10940 10941 // If not all the elements were used, this may not be worthwhile. 10942 if (ExtractedElements != 15) 10943 return SDValue(); 10944 10945 // Ok, we've now decided to do the transformation. 10946 DebugLoc dl = InputVector.getDebugLoc(); 10947 10948 // Store the value to a temporary stack slot. 10949 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 10950 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 10951 MachinePointerInfo(), false, false, 0); 10952 10953 // Replace each use (extract) with a load of the appropriate element. 10954 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 10955 UE = Uses.end(); UI != UE; ++UI) { 10956 SDNode *Extract = *UI; 10957 10958 // Compute the element's address. 10959 SDValue Idx = Extract->getOperand(1); 10960 unsigned EltSize = 10961 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 10962 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 10963 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 10964 10965 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), 10966 StackPtr, OffsetVal); 10967 10968 // Load the scalar. 10969 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 10970 ScalarAddr, MachinePointerInfo(), 10971 false, false, 0); 10972 10973 // Replace the exact with the load. 10974 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 10975 } 10976 10977 // The replacement was made in place; don't return anything. 10978 return SDValue(); 10979} 10980 10981/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 10982static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 10983 const X86Subtarget *Subtarget) { 10984 DebugLoc DL = N->getDebugLoc(); 10985 SDValue Cond = N->getOperand(0); 10986 // Get the LHS/RHS of the select. 10987 SDValue LHS = N->getOperand(1); 10988 SDValue RHS = N->getOperand(2); 10989 10990 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 10991 // instructions match the semantics of the common C idiom x<y?x:y but not 10992 // x<=y?x:y, because of how they handle negative zero (which can be 10993 // ignored in unsafe-math mode). 10994 if (Subtarget->hasSSE2() && 10995 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 10996 Cond.getOpcode() == ISD::SETCC) { 10997 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 10998 10999 unsigned Opcode = 0; 11000 // Check for x CC y ? x : y. 11001 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 11002 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 11003 switch (CC) { 11004 default: break; 11005 case ISD::SETULT: 11006 // Converting this to a min would handle NaNs incorrectly, and swapping 11007 // the operands would cause it to handle comparisons between positive 11008 // and negative zero incorrectly. 11009 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11010 if (!UnsafeFPMath && 11011 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11012 break; 11013 std::swap(LHS, RHS); 11014 } 11015 Opcode = X86ISD::FMIN; 11016 break; 11017 case ISD::SETOLE: 11018 // Converting this to a min would handle comparisons between positive 11019 // and negative zero incorrectly. 11020 if (!UnsafeFPMath && 11021 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 11022 break; 11023 Opcode = X86ISD::FMIN; 11024 break; 11025 case ISD::SETULE: 11026 // Converting this to a min would handle both negative zeros and NaNs 11027 // incorrectly, but we can swap the operands to fix both. 11028 std::swap(LHS, RHS); 11029 case ISD::SETOLT: 11030 case ISD::SETLT: 11031 case ISD::SETLE: 11032 Opcode = X86ISD::FMIN; 11033 break; 11034 11035 case ISD::SETOGE: 11036 // Converting this to a max would handle comparisons between positive 11037 // and negative zero incorrectly. 11038 if (!UnsafeFPMath && 11039 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 11040 break; 11041 Opcode = X86ISD::FMAX; 11042 break; 11043 case ISD::SETUGT: 11044 // Converting this to a max would handle NaNs incorrectly, and swapping 11045 // the operands would cause it to handle comparisons between positive 11046 // and negative zero incorrectly. 11047 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11048 if (!UnsafeFPMath && 11049 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11050 break; 11051 std::swap(LHS, RHS); 11052 } 11053 Opcode = X86ISD::FMAX; 11054 break; 11055 case ISD::SETUGE: 11056 // Converting this to a max would handle both negative zeros and NaNs 11057 // incorrectly, but we can swap the operands to fix both. 11058 std::swap(LHS, RHS); 11059 case ISD::SETOGT: 11060 case ISD::SETGT: 11061 case ISD::SETGE: 11062 Opcode = X86ISD::FMAX; 11063 break; 11064 } 11065 // Check for x CC y ? y : x -- a min/max with reversed arms. 11066 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 11067 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 11068 switch (CC) { 11069 default: break; 11070 case ISD::SETOGE: 11071 // Converting this to a min would handle comparisons between positive 11072 // and negative zero incorrectly, and swapping the operands would 11073 // cause it to handle NaNs incorrectly. 11074 if (!UnsafeFPMath && 11075 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 11076 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11077 break; 11078 std::swap(LHS, RHS); 11079 } 11080 Opcode = X86ISD::FMIN; 11081 break; 11082 case ISD::SETUGT: 11083 // Converting this to a min would handle NaNs incorrectly. 11084 if (!UnsafeFPMath && 11085 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 11086 break; 11087 Opcode = X86ISD::FMIN; 11088 break; 11089 case ISD::SETUGE: 11090 // Converting this to a min would handle both negative zeros and NaNs 11091 // incorrectly, but we can swap the operands to fix both. 11092 std::swap(LHS, RHS); 11093 case ISD::SETOGT: 11094 case ISD::SETGT: 11095 case ISD::SETGE: 11096 Opcode = X86ISD::FMIN; 11097 break; 11098 11099 case ISD::SETULT: 11100 // Converting this to a max would handle NaNs incorrectly. 11101 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11102 break; 11103 Opcode = X86ISD::FMAX; 11104 break; 11105 case ISD::SETOLE: 11106 // Converting this to a max would handle comparisons between positive 11107 // and negative zero incorrectly, and swapping the operands would 11108 // cause it to handle NaNs incorrectly. 11109 if (!UnsafeFPMath && 11110 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 11111 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11112 break; 11113 std::swap(LHS, RHS); 11114 } 11115 Opcode = X86ISD::FMAX; 11116 break; 11117 case ISD::SETULE: 11118 // Converting this to a max would handle both negative zeros and NaNs 11119 // incorrectly, but we can swap the operands to fix both. 11120 std::swap(LHS, RHS); 11121 case ISD::SETOLT: 11122 case ISD::SETLT: 11123 case ISD::SETLE: 11124 Opcode = X86ISD::FMAX; 11125 break; 11126 } 11127 } 11128 11129 if (Opcode) 11130 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 11131 } 11132 11133 // If this is a select between two integer constants, try to do some 11134 // optimizations. 11135 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 11136 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 11137 // Don't do this for crazy integer types. 11138 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 11139 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 11140 // so that TrueC (the true value) is larger than FalseC. 11141 bool NeedsCondInvert = false; 11142 11143 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 11144 // Efficiently invertible. 11145 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 11146 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 11147 isa<ConstantSDNode>(Cond.getOperand(1))))) { 11148 NeedsCondInvert = true; 11149 std::swap(TrueC, FalseC); 11150 } 11151 11152 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 11153 if (FalseC->getAPIntValue() == 0 && 11154 TrueC->getAPIntValue().isPowerOf2()) { 11155 if (NeedsCondInvert) // Invert the condition if needed. 11156 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11157 DAG.getConstant(1, Cond.getValueType())); 11158 11159 // Zero extend the condition if needed. 11160 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 11161 11162 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 11163 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 11164 DAG.getConstant(ShAmt, MVT::i8)); 11165 } 11166 11167 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 11168 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 11169 if (NeedsCondInvert) // Invert the condition if needed. 11170 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11171 DAG.getConstant(1, Cond.getValueType())); 11172 11173 // Zero extend the condition if needed. 11174 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 11175 FalseC->getValueType(0), Cond); 11176 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11177 SDValue(FalseC, 0)); 11178 } 11179 11180 // Optimize cases that will turn into an LEA instruction. This requires 11181 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 11182 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 11183 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 11184 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 11185 11186 bool isFastMultiplier = false; 11187 if (Diff < 10) { 11188 switch ((unsigned char)Diff) { 11189 default: break; 11190 case 1: // result = add base, cond 11191 case 2: // result = lea base( , cond*2) 11192 case 3: // result = lea base(cond, cond*2) 11193 case 4: // result = lea base( , cond*4) 11194 case 5: // result = lea base(cond, cond*4) 11195 case 8: // result = lea base( , cond*8) 11196 case 9: // result = lea base(cond, cond*8) 11197 isFastMultiplier = true; 11198 break; 11199 } 11200 } 11201 11202 if (isFastMultiplier) { 11203 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 11204 if (NeedsCondInvert) // Invert the condition if needed. 11205 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11206 DAG.getConstant(1, Cond.getValueType())); 11207 11208 // Zero extend the condition if needed. 11209 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 11210 Cond); 11211 // Scale the condition by the difference. 11212 if (Diff != 1) 11213 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 11214 DAG.getConstant(Diff, Cond.getValueType())); 11215 11216 // Add the base if non-zero. 11217 if (FalseC->getAPIntValue() != 0) 11218 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11219 SDValue(FalseC, 0)); 11220 return Cond; 11221 } 11222 } 11223 } 11224 } 11225 11226 return SDValue(); 11227} 11228 11229/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 11230static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 11231 TargetLowering::DAGCombinerInfo &DCI) { 11232 DebugLoc DL = N->getDebugLoc(); 11233 11234 // If the flag operand isn't dead, don't touch this CMOV. 11235 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 11236 return SDValue(); 11237 11238 // If this is a select between two integer constants, try to do some 11239 // optimizations. Note that the operands are ordered the opposite of SELECT 11240 // operands. 11241 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 11242 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 11243 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 11244 // larger than FalseC (the false value). 11245 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 11246 11247 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 11248 CC = X86::GetOppositeBranchCondition(CC); 11249 std::swap(TrueC, FalseC); 11250 } 11251 11252 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 11253 // This is efficient for any integer data type (including i8/i16) and 11254 // shift amount. 11255 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 11256 SDValue Cond = N->getOperand(3); 11257 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11258 DAG.getConstant(CC, MVT::i8), Cond); 11259 11260 // Zero extend the condition if needed. 11261 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 11262 11263 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 11264 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 11265 DAG.getConstant(ShAmt, MVT::i8)); 11266 if (N->getNumValues() == 2) // Dead flag value? 11267 return DCI.CombineTo(N, Cond, SDValue()); 11268 return Cond; 11269 } 11270 11271 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 11272 // for any integer data type, including i8/i16. 11273 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 11274 SDValue Cond = N->getOperand(3); 11275 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11276 DAG.getConstant(CC, MVT::i8), Cond); 11277 11278 // Zero extend the condition if needed. 11279 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 11280 FalseC->getValueType(0), Cond); 11281 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11282 SDValue(FalseC, 0)); 11283 11284 if (N->getNumValues() == 2) // Dead flag value? 11285 return DCI.CombineTo(N, Cond, SDValue()); 11286 return Cond; 11287 } 11288 11289 // Optimize cases that will turn into an LEA instruction. This requires 11290 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 11291 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 11292 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 11293 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 11294 11295 bool isFastMultiplier = false; 11296 if (Diff < 10) { 11297 switch ((unsigned char)Diff) { 11298 default: break; 11299 case 1: // result = add base, cond 11300 case 2: // result = lea base( , cond*2) 11301 case 3: // result = lea base(cond, cond*2) 11302 case 4: // result = lea base( , cond*4) 11303 case 5: // result = lea base(cond, cond*4) 11304 case 8: // result = lea base( , cond*8) 11305 case 9: // result = lea base(cond, cond*8) 11306 isFastMultiplier = true; 11307 break; 11308 } 11309 } 11310 11311 if (isFastMultiplier) { 11312 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 11313 SDValue Cond = N->getOperand(3); 11314 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11315 DAG.getConstant(CC, MVT::i8), Cond); 11316 // Zero extend the condition if needed. 11317 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 11318 Cond); 11319 // Scale the condition by the difference. 11320 if (Diff != 1) 11321 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 11322 DAG.getConstant(Diff, Cond.getValueType())); 11323 11324 // Add the base if non-zero. 11325 if (FalseC->getAPIntValue() != 0) 11326 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11327 SDValue(FalseC, 0)); 11328 if (N->getNumValues() == 2) // Dead flag value? 11329 return DCI.CombineTo(N, Cond, SDValue()); 11330 return Cond; 11331 } 11332 } 11333 } 11334 } 11335 return SDValue(); 11336} 11337 11338 11339/// PerformMulCombine - Optimize a single multiply with constant into two 11340/// in order to implement it with two cheaper instructions, e.g. 11341/// LEA + SHL, LEA + LEA. 11342static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 11343 TargetLowering::DAGCombinerInfo &DCI) { 11344 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 11345 return SDValue(); 11346 11347 EVT VT = N->getValueType(0); 11348 if (VT != MVT::i64) 11349 return SDValue(); 11350 11351 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 11352 if (!C) 11353 return SDValue(); 11354 uint64_t MulAmt = C->getZExtValue(); 11355 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 11356 return SDValue(); 11357 11358 uint64_t MulAmt1 = 0; 11359 uint64_t MulAmt2 = 0; 11360 if ((MulAmt % 9) == 0) { 11361 MulAmt1 = 9; 11362 MulAmt2 = MulAmt / 9; 11363 } else if ((MulAmt % 5) == 0) { 11364 MulAmt1 = 5; 11365 MulAmt2 = MulAmt / 5; 11366 } else if ((MulAmt % 3) == 0) { 11367 MulAmt1 = 3; 11368 MulAmt2 = MulAmt / 3; 11369 } 11370 if (MulAmt2 && 11371 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 11372 DebugLoc DL = N->getDebugLoc(); 11373 11374 if (isPowerOf2_64(MulAmt2) && 11375 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 11376 // If second multiplifer is pow2, issue it first. We want the multiply by 11377 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 11378 // is an add. 11379 std::swap(MulAmt1, MulAmt2); 11380 11381 SDValue NewMul; 11382 if (isPowerOf2_64(MulAmt1)) 11383 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 11384 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 11385 else 11386 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 11387 DAG.getConstant(MulAmt1, VT)); 11388 11389 if (isPowerOf2_64(MulAmt2)) 11390 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 11391 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 11392 else 11393 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 11394 DAG.getConstant(MulAmt2, VT)); 11395 11396 // Do not add new nodes to DAG combiner worklist. 11397 DCI.CombineTo(N, NewMul, false); 11398 } 11399 return SDValue(); 11400} 11401 11402static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 11403 SDValue N0 = N->getOperand(0); 11404 SDValue N1 = N->getOperand(1); 11405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 11406 EVT VT = N0.getValueType(); 11407 11408 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 11409 // since the result of setcc_c is all zero's or all ones. 11410 if (N1C && N0.getOpcode() == ISD::AND && 11411 N0.getOperand(1).getOpcode() == ISD::Constant) { 11412 SDValue N00 = N0.getOperand(0); 11413 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 11414 ((N00.getOpcode() == ISD::ANY_EXTEND || 11415 N00.getOpcode() == ISD::ZERO_EXTEND) && 11416 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 11417 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 11418 APInt ShAmt = N1C->getAPIntValue(); 11419 Mask = Mask.shl(ShAmt); 11420 if (Mask != 0) 11421 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 11422 N00, DAG.getConstant(Mask, VT)); 11423 } 11424 } 11425 11426 return SDValue(); 11427} 11428 11429/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 11430/// when possible. 11431static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 11432 const X86Subtarget *Subtarget) { 11433 EVT VT = N->getValueType(0); 11434 if (!VT.isVector() && VT.isInteger() && 11435 N->getOpcode() == ISD::SHL) 11436 return PerformSHLCombine(N, DAG); 11437 11438 // On X86 with SSE2 support, we can transform this to a vector shift if 11439 // all elements are shifted by the same amount. We can't do this in legalize 11440 // because the a constant vector is typically transformed to a constant pool 11441 // so we have no knowledge of the shift amount. 11442 if (!Subtarget->hasSSE2()) 11443 return SDValue(); 11444 11445 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 11446 return SDValue(); 11447 11448 SDValue ShAmtOp = N->getOperand(1); 11449 EVT EltVT = VT.getVectorElementType(); 11450 DebugLoc DL = N->getDebugLoc(); 11451 SDValue BaseShAmt = SDValue(); 11452 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 11453 unsigned NumElts = VT.getVectorNumElements(); 11454 unsigned i = 0; 11455 for (; i != NumElts; ++i) { 11456 SDValue Arg = ShAmtOp.getOperand(i); 11457 if (Arg.getOpcode() == ISD::UNDEF) continue; 11458 BaseShAmt = Arg; 11459 break; 11460 } 11461 for (; i != NumElts; ++i) { 11462 SDValue Arg = ShAmtOp.getOperand(i); 11463 if (Arg.getOpcode() == ISD::UNDEF) continue; 11464 if (Arg != BaseShAmt) { 11465 return SDValue(); 11466 } 11467 } 11468 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 11469 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 11470 SDValue InVec = ShAmtOp.getOperand(0); 11471 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 11472 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 11473 unsigned i = 0; 11474 for (; i != NumElts; ++i) { 11475 SDValue Arg = InVec.getOperand(i); 11476 if (Arg.getOpcode() == ISD::UNDEF) continue; 11477 BaseShAmt = Arg; 11478 break; 11479 } 11480 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 11481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 11482 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 11483 if (C->getZExtValue() == SplatIdx) 11484 BaseShAmt = InVec.getOperand(1); 11485 } 11486 } 11487 if (BaseShAmt.getNode() == 0) 11488 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 11489 DAG.getIntPtrConstant(0)); 11490 } else 11491 return SDValue(); 11492 11493 // The shift amount is an i32. 11494 if (EltVT.bitsGT(MVT::i32)) 11495 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 11496 else if (EltVT.bitsLT(MVT::i32)) 11497 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 11498 11499 // The shift amount is identical so we can do a vector shift. 11500 SDValue ValOp = N->getOperand(0); 11501 switch (N->getOpcode()) { 11502 default: 11503 llvm_unreachable("Unknown shift opcode!"); 11504 break; 11505 case ISD::SHL: 11506 if (VT == MVT::v2i64) 11507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11508 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 11509 ValOp, BaseShAmt); 11510 if (VT == MVT::v4i32) 11511 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11512 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 11513 ValOp, BaseShAmt); 11514 if (VT == MVT::v8i16) 11515 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11516 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 11517 ValOp, BaseShAmt); 11518 break; 11519 case ISD::SRA: 11520 if (VT == MVT::v4i32) 11521 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11522 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 11523 ValOp, BaseShAmt); 11524 if (VT == MVT::v8i16) 11525 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11526 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 11527 ValOp, BaseShAmt); 11528 break; 11529 case ISD::SRL: 11530 if (VT == MVT::v2i64) 11531 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11532 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 11533 ValOp, BaseShAmt); 11534 if (VT == MVT::v4i32) 11535 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11536 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 11537 ValOp, BaseShAmt); 11538 if (VT == MVT::v8i16) 11539 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 11540 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 11541 ValOp, BaseShAmt); 11542 break; 11543 } 11544 return SDValue(); 11545} 11546 11547 11548static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 11549 TargetLowering::DAGCombinerInfo &DCI, 11550 const X86Subtarget *Subtarget) { 11551 if (DCI.isBeforeLegalizeOps()) 11552 return SDValue(); 11553 11554 // Want to form PANDN nodes, in the hopes of then easily combining them with 11555 // OR and AND nodes to form PBLEND/PSIGN. 11556 EVT VT = N->getValueType(0); 11557 if (VT != MVT::v2i64) 11558 return SDValue(); 11559 11560 SDValue N0 = N->getOperand(0); 11561 SDValue N1 = N->getOperand(1); 11562 DebugLoc DL = N->getDebugLoc(); 11563 11564 // Check LHS for vnot 11565 if (N0.getOpcode() == ISD::XOR && 11566 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 11567 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1); 11568 11569 // Check RHS for vnot 11570 if (N1.getOpcode() == ISD::XOR && 11571 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 11572 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0); 11573 11574 return SDValue(); 11575} 11576 11577static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 11578 TargetLowering::DAGCombinerInfo &DCI, 11579 const X86Subtarget *Subtarget) { 11580 if (DCI.isBeforeLegalizeOps()) 11581 return SDValue(); 11582 11583 EVT VT = N->getValueType(0); 11584 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 11585 return SDValue(); 11586 11587 SDValue N0 = N->getOperand(0); 11588 SDValue N1 = N->getOperand(1); 11589 11590 // look for psign/blend 11591 if (Subtarget->hasSSSE3()) { 11592 if (VT == MVT::v2i64) { 11593 // Canonicalize pandn to RHS 11594 if (N0.getOpcode() == X86ISD::PANDN) 11595 std::swap(N0, N1); 11596 // or (and (m, x), (pandn m, y)) 11597 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) { 11598 SDValue Mask = N1.getOperand(0); 11599 SDValue X = N1.getOperand(1); 11600 SDValue Y; 11601 if (N0.getOperand(0) == Mask) 11602 Y = N0.getOperand(1); 11603 if (N0.getOperand(1) == Mask) 11604 Y = N0.getOperand(0); 11605 11606 // Check to see if the mask appeared in both the AND and PANDN and 11607 if (!Y.getNode()) 11608 return SDValue(); 11609 11610 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 11611 if (Mask.getOpcode() != ISD::BITCAST || 11612 X.getOpcode() != ISD::BITCAST || 11613 Y.getOpcode() != ISD::BITCAST) 11614 return SDValue(); 11615 11616 // Look through mask bitcast. 11617 Mask = Mask.getOperand(0); 11618 EVT MaskVT = Mask.getValueType(); 11619 11620 // Validate that the Mask operand is a vector sra node. The sra node 11621 // will be an intrinsic. 11622 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 11623 return SDValue(); 11624 11625 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 11626 // there is no psrai.b 11627 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 11628 case Intrinsic::x86_sse2_psrai_w: 11629 case Intrinsic::x86_sse2_psrai_d: 11630 break; 11631 default: return SDValue(); 11632 } 11633 11634 // Check that the SRA is all signbits. 11635 SDValue SraC = Mask.getOperand(2); 11636 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 11637 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 11638 if ((SraAmt + 1) != EltBits) 11639 return SDValue(); 11640 11641 DebugLoc DL = N->getDebugLoc(); 11642 11643 // Now we know we at least have a plendvb with the mask val. See if 11644 // we can form a psignb/w/d. 11645 // psign = x.type == y.type == mask.type && y = sub(0, x); 11646 X = X.getOperand(0); 11647 Y = Y.getOperand(0); 11648 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 11649 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 11650 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 11651 unsigned Opc = 0; 11652 switch (EltBits) { 11653 case 8: Opc = X86ISD::PSIGNB; break; 11654 case 16: Opc = X86ISD::PSIGNW; break; 11655 case 32: Opc = X86ISD::PSIGND; break; 11656 default: break; 11657 } 11658 if (Opc) { 11659 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 11660 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 11661 } 11662 } 11663 // PBLENDVB only available on SSE 4.1 11664 if (!Subtarget->hasSSE41()) 11665 return SDValue(); 11666 11667 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 11668 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 11669 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 11670 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask); 11671 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 11672 } 11673 } 11674 } 11675 11676 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 11677 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 11678 std::swap(N0, N1); 11679 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 11680 return SDValue(); 11681 if (!N0.hasOneUse() || !N1.hasOneUse()) 11682 return SDValue(); 11683 11684 SDValue ShAmt0 = N0.getOperand(1); 11685 if (ShAmt0.getValueType() != MVT::i8) 11686 return SDValue(); 11687 SDValue ShAmt1 = N1.getOperand(1); 11688 if (ShAmt1.getValueType() != MVT::i8) 11689 return SDValue(); 11690 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 11691 ShAmt0 = ShAmt0.getOperand(0); 11692 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 11693 ShAmt1 = ShAmt1.getOperand(0); 11694 11695 DebugLoc DL = N->getDebugLoc(); 11696 unsigned Opc = X86ISD::SHLD; 11697 SDValue Op0 = N0.getOperand(0); 11698 SDValue Op1 = N1.getOperand(0); 11699 if (ShAmt0.getOpcode() == ISD::SUB) { 11700 Opc = X86ISD::SHRD; 11701 std::swap(Op0, Op1); 11702 std::swap(ShAmt0, ShAmt1); 11703 } 11704 11705 unsigned Bits = VT.getSizeInBits(); 11706 if (ShAmt1.getOpcode() == ISD::SUB) { 11707 SDValue Sum = ShAmt1.getOperand(0); 11708 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 11709 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 11710 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 11711 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 11712 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 11713 return DAG.getNode(Opc, DL, VT, 11714 Op0, Op1, 11715 DAG.getNode(ISD::TRUNCATE, DL, 11716 MVT::i8, ShAmt0)); 11717 } 11718 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 11719 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 11720 if (ShAmt0C && 11721 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 11722 return DAG.getNode(Opc, DL, VT, 11723 N0.getOperand(0), N1.getOperand(0), 11724 DAG.getNode(ISD::TRUNCATE, DL, 11725 MVT::i8, ShAmt0)); 11726 } 11727 11728 return SDValue(); 11729} 11730 11731/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 11732static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 11733 const X86Subtarget *Subtarget) { 11734 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 11735 // the FP state in cases where an emms may be missing. 11736 // A preferable solution to the general problem is to figure out the right 11737 // places to insert EMMS. This qualifies as a quick hack. 11738 11739 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 11740 StoreSDNode *St = cast<StoreSDNode>(N); 11741 EVT VT = St->getValue().getValueType(); 11742 if (VT.getSizeInBits() != 64) 11743 return SDValue(); 11744 11745 const Function *F = DAG.getMachineFunction().getFunction(); 11746 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 11747 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 11748 && Subtarget->hasSSE2(); 11749 if ((VT.isVector() || 11750 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 11751 isa<LoadSDNode>(St->getValue()) && 11752 !cast<LoadSDNode>(St->getValue())->isVolatile() && 11753 St->getChain().hasOneUse() && !St->isVolatile()) { 11754 SDNode* LdVal = St->getValue().getNode(); 11755 LoadSDNode *Ld = 0; 11756 int TokenFactorIndex = -1; 11757 SmallVector<SDValue, 8> Ops; 11758 SDNode* ChainVal = St->getChain().getNode(); 11759 // Must be a store of a load. We currently handle two cases: the load 11760 // is a direct child, and it's under an intervening TokenFactor. It is 11761 // possible to dig deeper under nested TokenFactors. 11762 if (ChainVal == LdVal) 11763 Ld = cast<LoadSDNode>(St->getChain()); 11764 else if (St->getValue().hasOneUse() && 11765 ChainVal->getOpcode() == ISD::TokenFactor) { 11766 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 11767 if (ChainVal->getOperand(i).getNode() == LdVal) { 11768 TokenFactorIndex = i; 11769 Ld = cast<LoadSDNode>(St->getValue()); 11770 } else 11771 Ops.push_back(ChainVal->getOperand(i)); 11772 } 11773 } 11774 11775 if (!Ld || !ISD::isNormalLoad(Ld)) 11776 return SDValue(); 11777 11778 // If this is not the MMX case, i.e. we are just turning i64 load/store 11779 // into f64 load/store, avoid the transformation if there are multiple 11780 // uses of the loaded value. 11781 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 11782 return SDValue(); 11783 11784 DebugLoc LdDL = Ld->getDebugLoc(); 11785 DebugLoc StDL = N->getDebugLoc(); 11786 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 11787 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 11788 // pair instead. 11789 if (Subtarget->is64Bit() || F64IsLegal) { 11790 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 11791 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 11792 Ld->getPointerInfo(), Ld->isVolatile(), 11793 Ld->isNonTemporal(), Ld->getAlignment()); 11794 SDValue NewChain = NewLd.getValue(1); 11795 if (TokenFactorIndex != -1) { 11796 Ops.push_back(NewChain); 11797 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 11798 Ops.size()); 11799 } 11800 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 11801 St->getPointerInfo(), 11802 St->isVolatile(), St->isNonTemporal(), 11803 St->getAlignment()); 11804 } 11805 11806 // Otherwise, lower to two pairs of 32-bit loads / stores. 11807 SDValue LoAddr = Ld->getBasePtr(); 11808 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 11809 DAG.getConstant(4, MVT::i32)); 11810 11811 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 11812 Ld->getPointerInfo(), 11813 Ld->isVolatile(), Ld->isNonTemporal(), 11814 Ld->getAlignment()); 11815 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 11816 Ld->getPointerInfo().getWithOffset(4), 11817 Ld->isVolatile(), Ld->isNonTemporal(), 11818 MinAlign(Ld->getAlignment(), 4)); 11819 11820 SDValue NewChain = LoLd.getValue(1); 11821 if (TokenFactorIndex != -1) { 11822 Ops.push_back(LoLd); 11823 Ops.push_back(HiLd); 11824 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 11825 Ops.size()); 11826 } 11827 11828 LoAddr = St->getBasePtr(); 11829 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 11830 DAG.getConstant(4, MVT::i32)); 11831 11832 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 11833 St->getPointerInfo(), 11834 St->isVolatile(), St->isNonTemporal(), 11835 St->getAlignment()); 11836 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 11837 St->getPointerInfo().getWithOffset(4), 11838 St->isVolatile(), 11839 St->isNonTemporal(), 11840 MinAlign(St->getAlignment(), 4)); 11841 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 11842 } 11843 return SDValue(); 11844} 11845 11846/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 11847/// X86ISD::FXOR nodes. 11848static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 11849 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 11850 // F[X]OR(0.0, x) -> x 11851 // F[X]OR(x, 0.0) -> x 11852 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 11853 if (C->getValueAPF().isPosZero()) 11854 return N->getOperand(1); 11855 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 11856 if (C->getValueAPF().isPosZero()) 11857 return N->getOperand(0); 11858 return SDValue(); 11859} 11860 11861/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 11862static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 11863 // FAND(0.0, x) -> 0.0 11864 // FAND(x, 0.0) -> 0.0 11865 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 11866 if (C->getValueAPF().isPosZero()) 11867 return N->getOperand(0); 11868 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 11869 if (C->getValueAPF().isPosZero()) 11870 return N->getOperand(1); 11871 return SDValue(); 11872} 11873 11874static SDValue PerformBTCombine(SDNode *N, 11875 SelectionDAG &DAG, 11876 TargetLowering::DAGCombinerInfo &DCI) { 11877 // BT ignores high bits in the bit index operand. 11878 SDValue Op1 = N->getOperand(1); 11879 if (Op1.hasOneUse()) { 11880 unsigned BitWidth = Op1.getValueSizeInBits(); 11881 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 11882 APInt KnownZero, KnownOne; 11883 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 11884 !DCI.isBeforeLegalizeOps()); 11885 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11886 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 11887 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 11888 DCI.CommitTargetLoweringOpt(TLO); 11889 } 11890 return SDValue(); 11891} 11892 11893static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 11894 SDValue Op = N->getOperand(0); 11895 if (Op.getOpcode() == ISD::BITCAST) 11896 Op = Op.getOperand(0); 11897 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 11898 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 11899 VT.getVectorElementType().getSizeInBits() == 11900 OpVT.getVectorElementType().getSizeInBits()) { 11901 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 11902 } 11903 return SDValue(); 11904} 11905 11906static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 11907 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 11908 // (and (i32 x86isd::setcc_carry), 1) 11909 // This eliminates the zext. This transformation is necessary because 11910 // ISD::SETCC is always legalized to i8. 11911 DebugLoc dl = N->getDebugLoc(); 11912 SDValue N0 = N->getOperand(0); 11913 EVT VT = N->getValueType(0); 11914 if (N0.getOpcode() == ISD::AND && 11915 N0.hasOneUse() && 11916 N0.getOperand(0).hasOneUse()) { 11917 SDValue N00 = N0.getOperand(0); 11918 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 11919 return SDValue(); 11920 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 11921 if (!C || C->getZExtValue() != 1) 11922 return SDValue(); 11923 return DAG.getNode(ISD::AND, dl, VT, 11924 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 11925 N00.getOperand(0), N00.getOperand(1)), 11926 DAG.getConstant(1, VT)); 11927 } 11928 11929 return SDValue(); 11930} 11931 11932// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 11933static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 11934 unsigned X86CC = N->getConstantOperandVal(0); 11935 SDValue EFLAG = N->getOperand(1); 11936 DebugLoc DL = N->getDebugLoc(); 11937 11938 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 11939 // a zext and produces an all-ones bit which is more useful than 0/1 in some 11940 // cases. 11941 if (X86CC == X86::COND_B) 11942 return DAG.getNode(ISD::AND, DL, MVT::i8, 11943 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 11944 DAG.getConstant(X86CC, MVT::i8), EFLAG), 11945 DAG.getConstant(1, MVT::i8)); 11946 11947 return SDValue(); 11948} 11949 11950// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 11951static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 11952 X86TargetLowering::DAGCombinerInfo &DCI) { 11953 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 11954 // the result is either zero or one (depending on the input carry bit). 11955 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 11956 if (X86::isZeroNode(N->getOperand(0)) && 11957 X86::isZeroNode(N->getOperand(1)) && 11958 // We don't have a good way to replace an EFLAGS use, so only do this when 11959 // dead right now. 11960 SDValue(N, 1).use_empty()) { 11961 DebugLoc DL = N->getDebugLoc(); 11962 EVT VT = N->getValueType(0); 11963 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 11964 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 11965 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 11966 DAG.getConstant(X86::COND_B,MVT::i8), 11967 N->getOperand(2)), 11968 DAG.getConstant(1, VT)); 11969 return DCI.CombineTo(N, Res1, CarryOut); 11970 } 11971 11972 return SDValue(); 11973} 11974 11975// fold (add Y, (sete X, 0)) -> adc 0, Y 11976// (add Y, (setne X, 0)) -> sbb -1, Y 11977// (sub (sete X, 0), Y) -> sbb 0, Y 11978// (sub (setne X, 0), Y) -> adc -1, Y 11979static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) { 11980 DebugLoc DL = N->getDebugLoc(); 11981 11982 // Look through ZExts. 11983 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 11984 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 11985 return SDValue(); 11986 11987 SDValue SetCC = Ext.getOperand(0); 11988 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 11989 return SDValue(); 11990 11991 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 11992 if (CC != X86::COND_E && CC != X86::COND_NE) 11993 return SDValue(); 11994 11995 SDValue Cmp = SetCC.getOperand(1); 11996 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 11997 !X86::isZeroNode(Cmp.getOperand(1)) || 11998 !Cmp.getOperand(0).getValueType().isInteger()) 11999 return SDValue(); 12000 12001 SDValue CmpOp0 = Cmp.getOperand(0); 12002 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 12003 DAG.getConstant(1, CmpOp0.getValueType())); 12004 12005 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 12006 if (CC == X86::COND_NE) 12007 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 12008 DL, OtherVal.getValueType(), OtherVal, 12009 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 12010 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 12011 DL, OtherVal.getValueType(), OtherVal, 12012 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 12013} 12014 12015SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 12016 DAGCombinerInfo &DCI) const { 12017 SelectionDAG &DAG = DCI.DAG; 12018 switch (N->getOpcode()) { 12019 default: break; 12020 case ISD::EXTRACT_VECTOR_ELT: 12021 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 12022 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 12023 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 12024 case ISD::ADD: 12025 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG); 12026 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 12027 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 12028 case ISD::SHL: 12029 case ISD::SRA: 12030 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 12031 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 12032 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 12033 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 12034 case X86ISD::FXOR: 12035 case X86ISD::FOR: return PerformFORCombine(N, DAG); 12036 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 12037 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 12038 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 12039 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 12040 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 12041 case X86ISD::SHUFPS: // Handle all target specific shuffles 12042 case X86ISD::SHUFPD: 12043 case X86ISD::PALIGN: 12044 case X86ISD::PUNPCKHBW: 12045 case X86ISD::PUNPCKHWD: 12046 case X86ISD::PUNPCKHDQ: 12047 case X86ISD::PUNPCKHQDQ: 12048 case X86ISD::UNPCKHPS: 12049 case X86ISD::UNPCKHPD: 12050 case X86ISD::PUNPCKLBW: 12051 case X86ISD::PUNPCKLWD: 12052 case X86ISD::PUNPCKLDQ: 12053 case X86ISD::PUNPCKLQDQ: 12054 case X86ISD::UNPCKLPS: 12055 case X86ISD::UNPCKLPD: 12056 case X86ISD::VUNPCKLPS: 12057 case X86ISD::VUNPCKLPD: 12058 case X86ISD::VUNPCKLPSY: 12059 case X86ISD::VUNPCKLPDY: 12060 case X86ISD::MOVHLPS: 12061 case X86ISD::MOVLHPS: 12062 case X86ISD::PSHUFD: 12063 case X86ISD::PSHUFHW: 12064 case X86ISD::PSHUFLW: 12065 case X86ISD::MOVSS: 12066 case X86ISD::MOVSD: 12067 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI); 12068 } 12069 12070 return SDValue(); 12071} 12072 12073/// isTypeDesirableForOp - Return true if the target has native support for 12074/// the specified value type and it is 'desirable' to use the type for the 12075/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 12076/// instruction encodings are longer and some i16 instructions are slow. 12077bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 12078 if (!isTypeLegal(VT)) 12079 return false; 12080 if (VT != MVT::i16) 12081 return true; 12082 12083 switch (Opc) { 12084 default: 12085 return true; 12086 case ISD::LOAD: 12087 case ISD::SIGN_EXTEND: 12088 case ISD::ZERO_EXTEND: 12089 case ISD::ANY_EXTEND: 12090 case ISD::SHL: 12091 case ISD::SRL: 12092 case ISD::SUB: 12093 case ISD::ADD: 12094 case ISD::MUL: 12095 case ISD::AND: 12096 case ISD::OR: 12097 case ISD::XOR: 12098 return false; 12099 } 12100} 12101 12102/// IsDesirableToPromoteOp - This method query the target whether it is 12103/// beneficial for dag combiner to promote the specified node. If true, it 12104/// should return the desired promotion type by reference. 12105bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 12106 EVT VT = Op.getValueType(); 12107 if (VT != MVT::i16) 12108 return false; 12109 12110 bool Promote = false; 12111 bool Commute = false; 12112 switch (Op.getOpcode()) { 12113 default: break; 12114 case ISD::LOAD: { 12115 LoadSDNode *LD = cast<LoadSDNode>(Op); 12116 // If the non-extending load has a single use and it's not live out, then it 12117 // might be folded. 12118 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 12119 Op.hasOneUse()*/) { 12120 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 12121 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 12122 // The only case where we'd want to promote LOAD (rather then it being 12123 // promoted as an operand is when it's only use is liveout. 12124 if (UI->getOpcode() != ISD::CopyToReg) 12125 return false; 12126 } 12127 } 12128 Promote = true; 12129 break; 12130 } 12131 case ISD::SIGN_EXTEND: 12132 case ISD::ZERO_EXTEND: 12133 case ISD::ANY_EXTEND: 12134 Promote = true; 12135 break; 12136 case ISD::SHL: 12137 case ISD::SRL: { 12138 SDValue N0 = Op.getOperand(0); 12139 // Look out for (store (shl (load), x)). 12140 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 12141 return false; 12142 Promote = true; 12143 break; 12144 } 12145 case ISD::ADD: 12146 case ISD::MUL: 12147 case ISD::AND: 12148 case ISD::OR: 12149 case ISD::XOR: 12150 Commute = true; 12151 // fallthrough 12152 case ISD::SUB: { 12153 SDValue N0 = Op.getOperand(0); 12154 SDValue N1 = Op.getOperand(1); 12155 if (!Commute && MayFoldLoad(N1)) 12156 return false; 12157 // Avoid disabling potential load folding opportunities. 12158 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 12159 return false; 12160 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 12161 return false; 12162 Promote = true; 12163 } 12164 } 12165 12166 PVT = MVT::i32; 12167 return Promote; 12168} 12169 12170//===----------------------------------------------------------------------===// 12171// X86 Inline Assembly Support 12172//===----------------------------------------------------------------------===// 12173 12174bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 12175 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 12176 12177 std::string AsmStr = IA->getAsmString(); 12178 12179 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 12180 SmallVector<StringRef, 4> AsmPieces; 12181 SplitString(AsmStr, AsmPieces, ";\n"); 12182 12183 switch (AsmPieces.size()) { 12184 default: return false; 12185 case 1: 12186 AsmStr = AsmPieces[0]; 12187 AsmPieces.clear(); 12188 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 12189 12190 // FIXME: this should verify that we are targetting a 486 or better. If not, 12191 // we will turn this bswap into something that will be lowered to logical ops 12192 // instead of emitting the bswap asm. For now, we don't support 486 or lower 12193 // so don't worry about this. 12194 // bswap $0 12195 if (AsmPieces.size() == 2 && 12196 (AsmPieces[0] == "bswap" || 12197 AsmPieces[0] == "bswapq" || 12198 AsmPieces[0] == "bswapl") && 12199 (AsmPieces[1] == "$0" || 12200 AsmPieces[1] == "${0:q}")) { 12201 // No need to check constraints, nothing other than the equivalent of 12202 // "=r,0" would be valid here. 12203 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 12204 if (!Ty || Ty->getBitWidth() % 16 != 0) 12205 return false; 12206 return IntrinsicLowering::LowerToByteSwap(CI); 12207 } 12208 // rorw $$8, ${0:w} --> llvm.bswap.i16 12209 if (CI->getType()->isIntegerTy(16) && 12210 AsmPieces.size() == 3 && 12211 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 12212 AsmPieces[1] == "$$8," && 12213 AsmPieces[2] == "${0:w}" && 12214 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 12215 AsmPieces.clear(); 12216 const std::string &ConstraintsStr = IA->getConstraintString(); 12217 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 12218 std::sort(AsmPieces.begin(), AsmPieces.end()); 12219 if (AsmPieces.size() == 4 && 12220 AsmPieces[0] == "~{cc}" && 12221 AsmPieces[1] == "~{dirflag}" && 12222 AsmPieces[2] == "~{flags}" && 12223 AsmPieces[3] == "~{fpsr}") { 12224 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 12225 if (!Ty || Ty->getBitWidth() % 16 != 0) 12226 return false; 12227 return IntrinsicLowering::LowerToByteSwap(CI); 12228 } 12229 } 12230 break; 12231 case 3: 12232 if (CI->getType()->isIntegerTy(32) && 12233 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 12234 SmallVector<StringRef, 4> Words; 12235 SplitString(AsmPieces[0], Words, " \t,"); 12236 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 12237 Words[2] == "${0:w}") { 12238 Words.clear(); 12239 SplitString(AsmPieces[1], Words, " \t,"); 12240 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 12241 Words[2] == "$0") { 12242 Words.clear(); 12243 SplitString(AsmPieces[2], Words, " \t,"); 12244 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 12245 Words[2] == "${0:w}") { 12246 AsmPieces.clear(); 12247 const std::string &ConstraintsStr = IA->getConstraintString(); 12248 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 12249 std::sort(AsmPieces.begin(), AsmPieces.end()); 12250 if (AsmPieces.size() == 4 && 12251 AsmPieces[0] == "~{cc}" && 12252 AsmPieces[1] == "~{dirflag}" && 12253 AsmPieces[2] == "~{flags}" && 12254 AsmPieces[3] == "~{fpsr}") { 12255 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 12256 if (!Ty || Ty->getBitWidth() % 16 != 0) 12257 return false; 12258 return IntrinsicLowering::LowerToByteSwap(CI); 12259 } 12260 } 12261 } 12262 } 12263 } 12264 12265 if (CI->getType()->isIntegerTy(64)) { 12266 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 12267 if (Constraints.size() >= 2 && 12268 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 12269 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 12270 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 12271 SmallVector<StringRef, 4> Words; 12272 SplitString(AsmPieces[0], Words, " \t"); 12273 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 12274 Words.clear(); 12275 SplitString(AsmPieces[1], Words, " \t"); 12276 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 12277 Words.clear(); 12278 SplitString(AsmPieces[2], Words, " \t,"); 12279 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 12280 Words[2] == "%edx") { 12281 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 12282 if (!Ty || Ty->getBitWidth() % 16 != 0) 12283 return false; 12284 return IntrinsicLowering::LowerToByteSwap(CI); 12285 } 12286 } 12287 } 12288 } 12289 } 12290 break; 12291 } 12292 return false; 12293} 12294 12295 12296 12297/// getConstraintType - Given a constraint letter, return the type of 12298/// constraint it is for this target. 12299X86TargetLowering::ConstraintType 12300X86TargetLowering::getConstraintType(const std::string &Constraint) const { 12301 if (Constraint.size() == 1) { 12302 switch (Constraint[0]) { 12303 case 'R': 12304 case 'q': 12305 case 'Q': 12306 case 'f': 12307 case 't': 12308 case 'u': 12309 case 'y': 12310 case 'x': 12311 case 'Y': 12312 return C_RegisterClass; 12313 case 'a': 12314 case 'b': 12315 case 'c': 12316 case 'd': 12317 case 'S': 12318 case 'D': 12319 case 'A': 12320 return C_Register; 12321 case 'I': 12322 case 'J': 12323 case 'K': 12324 case 'L': 12325 case 'M': 12326 case 'N': 12327 case 'G': 12328 case 'C': 12329 case 'e': 12330 case 'Z': 12331 return C_Other; 12332 default: 12333 break; 12334 } 12335 } 12336 return TargetLowering::getConstraintType(Constraint); 12337} 12338 12339/// Examine constraint type and operand type and determine a weight value. 12340/// This object must already have been set up with the operand type 12341/// and the current alternative constraint selected. 12342TargetLowering::ConstraintWeight 12343 X86TargetLowering::getSingleConstraintMatchWeight( 12344 AsmOperandInfo &info, const char *constraint) const { 12345 ConstraintWeight weight = CW_Invalid; 12346 Value *CallOperandVal = info.CallOperandVal; 12347 // If we don't have a value, we can't do a match, 12348 // but allow it at the lowest weight. 12349 if (CallOperandVal == NULL) 12350 return CW_Default; 12351 const Type *type = CallOperandVal->getType(); 12352 // Look at the constraint type. 12353 switch (*constraint) { 12354 default: 12355 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 12356 case 'R': 12357 case 'q': 12358 case 'Q': 12359 case 'a': 12360 case 'b': 12361 case 'c': 12362 case 'd': 12363 case 'S': 12364 case 'D': 12365 case 'A': 12366 if (CallOperandVal->getType()->isIntegerTy()) 12367 weight = CW_SpecificReg; 12368 break; 12369 case 'f': 12370 case 't': 12371 case 'u': 12372 if (type->isFloatingPointTy()) 12373 weight = CW_SpecificReg; 12374 break; 12375 case 'y': 12376 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 12377 weight = CW_SpecificReg; 12378 break; 12379 case 'x': 12380 case 'Y': 12381 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 12382 weight = CW_Register; 12383 break; 12384 case 'I': 12385 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 12386 if (C->getZExtValue() <= 31) 12387 weight = CW_Constant; 12388 } 12389 break; 12390 case 'J': 12391 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12392 if (C->getZExtValue() <= 63) 12393 weight = CW_Constant; 12394 } 12395 break; 12396 case 'K': 12397 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12398 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 12399 weight = CW_Constant; 12400 } 12401 break; 12402 case 'L': 12403 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12404 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 12405 weight = CW_Constant; 12406 } 12407 break; 12408 case 'M': 12409 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12410 if (C->getZExtValue() <= 3) 12411 weight = CW_Constant; 12412 } 12413 break; 12414 case 'N': 12415 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12416 if (C->getZExtValue() <= 0xff) 12417 weight = CW_Constant; 12418 } 12419 break; 12420 case 'G': 12421 case 'C': 12422 if (dyn_cast<ConstantFP>(CallOperandVal)) { 12423 weight = CW_Constant; 12424 } 12425 break; 12426 case 'e': 12427 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12428 if ((C->getSExtValue() >= -0x80000000LL) && 12429 (C->getSExtValue() <= 0x7fffffffLL)) 12430 weight = CW_Constant; 12431 } 12432 break; 12433 case 'Z': 12434 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 12435 if (C->getZExtValue() <= 0xffffffff) 12436 weight = CW_Constant; 12437 } 12438 break; 12439 } 12440 return weight; 12441} 12442 12443/// LowerXConstraint - try to replace an X constraint, which matches anything, 12444/// with another that has more specific requirements based on the type of the 12445/// corresponding operand. 12446const char *X86TargetLowering:: 12447LowerXConstraint(EVT ConstraintVT) const { 12448 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 12449 // 'f' like normal targets. 12450 if (ConstraintVT.isFloatingPoint()) { 12451 if (Subtarget->hasXMMInt()) 12452 return "Y"; 12453 if (Subtarget->hasXMM()) 12454 return "x"; 12455 } 12456 12457 return TargetLowering::LowerXConstraint(ConstraintVT); 12458} 12459 12460/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 12461/// vector. If it is invalid, don't add anything to Ops. 12462void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 12463 char Constraint, 12464 std::vector<SDValue>&Ops, 12465 SelectionDAG &DAG) const { 12466 SDValue Result(0, 0); 12467 12468 switch (Constraint) { 12469 default: break; 12470 case 'I': 12471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12472 if (C->getZExtValue() <= 31) { 12473 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 12474 break; 12475 } 12476 } 12477 return; 12478 case 'J': 12479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12480 if (C->getZExtValue() <= 63) { 12481 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 12482 break; 12483 } 12484 } 12485 return; 12486 case 'K': 12487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12488 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 12489 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 12490 break; 12491 } 12492 } 12493 return; 12494 case 'N': 12495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12496 if (C->getZExtValue() <= 255) { 12497 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 12498 break; 12499 } 12500 } 12501 return; 12502 case 'e': { 12503 // 32-bit signed value 12504 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12505 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 12506 C->getSExtValue())) { 12507 // Widen to 64 bits here to get it sign extended. 12508 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 12509 break; 12510 } 12511 // FIXME gcc accepts some relocatable values here too, but only in certain 12512 // memory models; it's complicated. 12513 } 12514 return; 12515 } 12516 case 'Z': { 12517 // 32-bit unsigned value 12518 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 12519 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 12520 C->getZExtValue())) { 12521 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 12522 break; 12523 } 12524 } 12525 // FIXME gcc accepts some relocatable values here too, but only in certain 12526 // memory models; it's complicated. 12527 return; 12528 } 12529 case 'i': { 12530 // Literal immediates are always ok. 12531 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 12532 // Widen to 64 bits here to get it sign extended. 12533 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 12534 break; 12535 } 12536 12537 // In any sort of PIC mode addresses need to be computed at runtime by 12538 // adding in a register or some sort of table lookup. These can't 12539 // be used as immediates. 12540 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 12541 return; 12542 12543 // If we are in non-pic codegen mode, we allow the address of a global (with 12544 // an optional displacement) to be used with 'i'. 12545 GlobalAddressSDNode *GA = 0; 12546 int64_t Offset = 0; 12547 12548 // Match either (GA), (GA+C), (GA+C1+C2), etc. 12549 while (1) { 12550 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 12551 Offset += GA->getOffset(); 12552 break; 12553 } else if (Op.getOpcode() == ISD::ADD) { 12554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 12555 Offset += C->getZExtValue(); 12556 Op = Op.getOperand(0); 12557 continue; 12558 } 12559 } else if (Op.getOpcode() == ISD::SUB) { 12560 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 12561 Offset += -C->getZExtValue(); 12562 Op = Op.getOperand(0); 12563 continue; 12564 } 12565 } 12566 12567 // Otherwise, this isn't something we can handle, reject it. 12568 return; 12569 } 12570 12571 const GlobalValue *GV = GA->getGlobal(); 12572 // If we require an extra load to get this address, as in PIC mode, we 12573 // can't accept it. 12574 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 12575 getTargetMachine()))) 12576 return; 12577 12578 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 12579 GA->getValueType(0), Offset); 12580 break; 12581 } 12582 } 12583 12584 if (Result.getNode()) { 12585 Ops.push_back(Result); 12586 return; 12587 } 12588 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 12589} 12590 12591std::vector<unsigned> X86TargetLowering:: 12592getRegClassForInlineAsmConstraint(const std::string &Constraint, 12593 EVT VT) const { 12594 if (Constraint.size() == 1) { 12595 // FIXME: not handling fp-stack yet! 12596 switch (Constraint[0]) { // GCC X86 Constraint Letters 12597 default: break; // Unknown constraint letter 12598 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 12599 if (Subtarget->is64Bit()) { 12600 if (VT == MVT::i32) 12601 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 12602 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 12603 X86::R10D,X86::R11D,X86::R12D, 12604 X86::R13D,X86::R14D,X86::R15D, 12605 X86::EBP, X86::ESP, 0); 12606 else if (VT == MVT::i16) 12607 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 12608 X86::SI, X86::DI, X86::R8W,X86::R9W, 12609 X86::R10W,X86::R11W,X86::R12W, 12610 X86::R13W,X86::R14W,X86::R15W, 12611 X86::BP, X86::SP, 0); 12612 else if (VT == MVT::i8) 12613 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 12614 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 12615 X86::R10B,X86::R11B,X86::R12B, 12616 X86::R13B,X86::R14B,X86::R15B, 12617 X86::BPL, X86::SPL, 0); 12618 12619 else if (VT == MVT::i64) 12620 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 12621 X86::RSI, X86::RDI, X86::R8, X86::R9, 12622 X86::R10, X86::R11, X86::R12, 12623 X86::R13, X86::R14, X86::R15, 12624 X86::RBP, X86::RSP, 0); 12625 12626 break; 12627 } 12628 // 32-bit fallthrough 12629 case 'Q': // Q_REGS 12630 if (VT == MVT::i32) 12631 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 12632 else if (VT == MVT::i16) 12633 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 12634 else if (VT == MVT::i8) 12635 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 12636 else if (VT == MVT::i64) 12637 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 12638 break; 12639 } 12640 } 12641 12642 return std::vector<unsigned>(); 12643} 12644 12645std::pair<unsigned, const TargetRegisterClass*> 12646X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 12647 EVT VT) const { 12648 // First, see if this is a constraint that directly corresponds to an LLVM 12649 // register class. 12650 if (Constraint.size() == 1) { 12651 // GCC Constraint Letters 12652 switch (Constraint[0]) { 12653 default: break; 12654 case 'r': // GENERAL_REGS 12655 case 'l': // INDEX_REGS 12656 if (VT == MVT::i8) 12657 return std::make_pair(0U, X86::GR8RegisterClass); 12658 if (VT == MVT::i16) 12659 return std::make_pair(0U, X86::GR16RegisterClass); 12660 if (VT == MVT::i32 || !Subtarget->is64Bit()) 12661 return std::make_pair(0U, X86::GR32RegisterClass); 12662 return std::make_pair(0U, X86::GR64RegisterClass); 12663 case 'R': // LEGACY_REGS 12664 if (VT == MVT::i8) 12665 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 12666 if (VT == MVT::i16) 12667 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 12668 if (VT == MVT::i32 || !Subtarget->is64Bit()) 12669 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 12670 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 12671 case 'f': // FP Stack registers. 12672 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 12673 // value to the correct fpstack register class. 12674 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 12675 return std::make_pair(0U, X86::RFP32RegisterClass); 12676 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 12677 return std::make_pair(0U, X86::RFP64RegisterClass); 12678 return std::make_pair(0U, X86::RFP80RegisterClass); 12679 case 'y': // MMX_REGS if MMX allowed. 12680 if (!Subtarget->hasMMX()) break; 12681 return std::make_pair(0U, X86::VR64RegisterClass); 12682 case 'Y': // SSE_REGS if SSE2 allowed 12683 if (!Subtarget->hasXMMInt()) break; 12684 // FALL THROUGH. 12685 case 'x': // SSE_REGS if SSE1 allowed 12686 if (!Subtarget->hasXMM()) break; 12687 12688 switch (VT.getSimpleVT().SimpleTy) { 12689 default: break; 12690 // Scalar SSE types. 12691 case MVT::f32: 12692 case MVT::i32: 12693 return std::make_pair(0U, X86::FR32RegisterClass); 12694 case MVT::f64: 12695 case MVT::i64: 12696 return std::make_pair(0U, X86::FR64RegisterClass); 12697 // Vector types. 12698 case MVT::v16i8: 12699 case MVT::v8i16: 12700 case MVT::v4i32: 12701 case MVT::v2i64: 12702 case MVT::v4f32: 12703 case MVT::v2f64: 12704 return std::make_pair(0U, X86::VR128RegisterClass); 12705 } 12706 break; 12707 } 12708 } 12709 12710 // Use the default implementation in TargetLowering to convert the register 12711 // constraint into a member of a register class. 12712 std::pair<unsigned, const TargetRegisterClass*> Res; 12713 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 12714 12715 // Not found as a standard register? 12716 if (Res.second == 0) { 12717 // Map st(0) -> st(7) -> ST0 12718 if (Constraint.size() == 7 && Constraint[0] == '{' && 12719 tolower(Constraint[1]) == 's' && 12720 tolower(Constraint[2]) == 't' && 12721 Constraint[3] == '(' && 12722 (Constraint[4] >= '0' && Constraint[4] <= '7') && 12723 Constraint[5] == ')' && 12724 Constraint[6] == '}') { 12725 12726 Res.first = X86::ST0+Constraint[4]-'0'; 12727 Res.second = X86::RFP80RegisterClass; 12728 return Res; 12729 } 12730 12731 // GCC allows "st(0)" to be called just plain "st". 12732 if (StringRef("{st}").equals_lower(Constraint)) { 12733 Res.first = X86::ST0; 12734 Res.second = X86::RFP80RegisterClass; 12735 return Res; 12736 } 12737 12738 // flags -> EFLAGS 12739 if (StringRef("{flags}").equals_lower(Constraint)) { 12740 Res.first = X86::EFLAGS; 12741 Res.second = X86::CCRRegisterClass; 12742 return Res; 12743 } 12744 12745 // 'A' means EAX + EDX. 12746 if (Constraint == "A") { 12747 Res.first = X86::EAX; 12748 Res.second = X86::GR32_ADRegisterClass; 12749 return Res; 12750 } 12751 return Res; 12752 } 12753 12754 // Otherwise, check to see if this is a register class of the wrong value 12755 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 12756 // turn into {ax},{dx}. 12757 if (Res.second->hasType(VT)) 12758 return Res; // Correct type already, nothing to do. 12759 12760 // All of the single-register GCC register classes map their values onto 12761 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 12762 // really want an 8-bit or 32-bit register, map to the appropriate register 12763 // class and return the appropriate register. 12764 if (Res.second == X86::GR16RegisterClass) { 12765 if (VT == MVT::i8) { 12766 unsigned DestReg = 0; 12767 switch (Res.first) { 12768 default: break; 12769 case X86::AX: DestReg = X86::AL; break; 12770 case X86::DX: DestReg = X86::DL; break; 12771 case X86::CX: DestReg = X86::CL; break; 12772 case X86::BX: DestReg = X86::BL; break; 12773 } 12774 if (DestReg) { 12775 Res.first = DestReg; 12776 Res.second = X86::GR8RegisterClass; 12777 } 12778 } else if (VT == MVT::i32) { 12779 unsigned DestReg = 0; 12780 switch (Res.first) { 12781 default: break; 12782 case X86::AX: DestReg = X86::EAX; break; 12783 case X86::DX: DestReg = X86::EDX; break; 12784 case X86::CX: DestReg = X86::ECX; break; 12785 case X86::BX: DestReg = X86::EBX; break; 12786 case X86::SI: DestReg = X86::ESI; break; 12787 case X86::DI: DestReg = X86::EDI; break; 12788 case X86::BP: DestReg = X86::EBP; break; 12789 case X86::SP: DestReg = X86::ESP; break; 12790 } 12791 if (DestReg) { 12792 Res.first = DestReg; 12793 Res.second = X86::GR32RegisterClass; 12794 } 12795 } else if (VT == MVT::i64) { 12796 unsigned DestReg = 0; 12797 switch (Res.first) { 12798 default: break; 12799 case X86::AX: DestReg = X86::RAX; break; 12800 case X86::DX: DestReg = X86::RDX; break; 12801 case X86::CX: DestReg = X86::RCX; break; 12802 case X86::BX: DestReg = X86::RBX; break; 12803 case X86::SI: DestReg = X86::RSI; break; 12804 case X86::DI: DestReg = X86::RDI; break; 12805 case X86::BP: DestReg = X86::RBP; break; 12806 case X86::SP: DestReg = X86::RSP; break; 12807 } 12808 if (DestReg) { 12809 Res.first = DestReg; 12810 Res.second = X86::GR64RegisterClass; 12811 } 12812 } 12813 } else if (Res.second == X86::FR32RegisterClass || 12814 Res.second == X86::FR64RegisterClass || 12815 Res.second == X86::VR128RegisterClass) { 12816 // Handle references to XMM physical registers that got mapped into the 12817 // wrong class. This can happen with constraints like {xmm0} where the 12818 // target independent register mapper will just pick the first match it can 12819 // find, ignoring the required type. 12820 if (VT == MVT::f32) 12821 Res.second = X86::FR32RegisterClass; 12822 else if (VT == MVT::f64) 12823 Res.second = X86::FR64RegisterClass; 12824 else if (X86::VR128RegisterClass->hasType(VT)) 12825 Res.second = X86::VR128RegisterClass; 12826 } 12827 12828 return Res; 12829} 12830