X86ISelLowering.cpp revision b1cacc74232164a9d80ee65d20e0095b25eb74d8
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52#include <cctype> 53using namespace llvm; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57// Forward declarations. 58static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 59 SDValue V2); 60 61/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 62/// sets things up to match to an AVX VEXTRACTF128 instruction or a 63/// simple subregister reference. Idx is an index in the 128 bits we 64/// want. It need not be aligned to a 128-bit bounday. That makes 65/// lowering EXTRACT_VECTOR_ELT operations easier. 66static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 67 SelectionDAG &DAG, DebugLoc dl) { 68 EVT VT = Vec.getValueType(); 69 assert(VT.is256BitVector() && "Unexpected vector size!"); 70 EVT ElVT = VT.getVectorElementType(); 71 unsigned Factor = VT.getSizeInBits()/128; 72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 73 VT.getVectorNumElements()/Factor); 74 75 // Extract from UNDEF is UNDEF. 76 if (Vec.getOpcode() == ISD::UNDEF) 77 return DAG.getUNDEF(ResultVT); 78 79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 80 // we can match to VEXTRACTF128. 81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 82 83 // This is the index of the first element of the 128-bit chunk 84 // we want. 85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 86 * ElemsPerChunk); 87 88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 90 VecIdx); 91 92 return Result; 93} 94 95/// Generate a DAG to put 128-bits into a vector > 128 bits. This 96/// sets things up to match to an AVX VINSERTF128 instruction or a 97/// simple superregister reference. Idx is an index in the 128 bits 98/// we want. It need not be aligned to a 128-bit bounday. That makes 99/// lowering INSERT_VECTOR_ELT operations easier. 100static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 101 unsigned IdxVal, SelectionDAG &DAG, 102 DebugLoc dl) { 103 // Inserting UNDEF is Result 104 if (Vec.getOpcode() == ISD::UNDEF) 105 return Result; 106 107 EVT VT = Vec.getValueType(); 108 assert(VT.is128BitVector() && "Unexpected vector size!"); 109 110 EVT ElVT = VT.getVectorElementType(); 111 EVT ResultVT = Result.getValueType(); 112 113 // Insert the relevant 128 bits. 114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 115 116 // This is the index of the first element of the 128-bit chunk 117 // we want. 118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 119 * ElemsPerChunk); 120 121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 123 VecIdx); 124} 125 126/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 127/// instructions. This is used because creating CONCAT_VECTOR nodes of 128/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 129/// large BUILD_VECTORS. 130static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 131 unsigned NumElems, SelectionDAG &DAG, 132 DebugLoc dl) { 133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X86_64MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetLinux()) 148 return new X86LinuxTargetObjectFile(); 149 if (Subtarget->isTargetELF()) 150 return new TargetLoweringObjectFileELF(); 151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 152 return new TargetLoweringObjectFileCOFF(); 153 llvm_unreachable("unknown subtarget type"); 154} 155 156X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 157 : TargetLowering(TM, createTLOF(TM)) { 158 Subtarget = &TM.getSubtarget<X86Subtarget>(); 159 X86ScalarSSEf64 = Subtarget->hasSSE2(); 160 X86ScalarSSEf32 = Subtarget->hasSSE1(); 161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 162 163 RegInfo = TM.getRegisterInfo(); 164 TD = getTargetData(); 165 166 // Set up the TargetLowering object. 167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 168 169 // X86 is weird, it always uses i8 for shift amounts and setcc results. 170 setBooleanContents(ZeroOrOneBooleanContent); 171 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 173 174 // For 64-bit since we have so many registers use the ILP scheduler, for 175 // 32-bit code use the register pressure specific scheduling. 176 // For Atom, always use ILP scheduling. 177 if (Subtarget->isAtom()) 178 setSchedulingPreference(Sched::ILP); 179 else if (Subtarget->is64Bit()) 180 setSchedulingPreference(Sched::ILP); 181 else 182 setSchedulingPreference(Sched::RegPressure); 183 setStackPointerRegisterToSaveRestore(X86StackPtr); 184 185 // Bypass i32 with i8 on Atom when compiling with O2 186 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) 187 addBypassSlowDivType(Type::getInt32Ty(getGlobalContext()), Type::getInt8Ty(getGlobalContext())); 188 189 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 190 // Setup Windows compiler runtime calls. 191 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 192 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 193 setLibcallName(RTLIB::SREM_I64, "_allrem"); 194 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 195 setLibcallName(RTLIB::MUL_I64, "_allmul"); 196 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 197 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 198 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 199 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 200 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 201 202 // The _ftol2 runtime function has an unusual calling conv, which 203 // is modeled by a special pseudo-instruction. 204 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 205 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 206 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 207 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 208 } 209 210 if (Subtarget->isTargetDarwin()) { 211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 212 setUseUnderscoreSetJmp(false); 213 setUseUnderscoreLongJmp(false); 214 } else if (Subtarget->isTargetMingw()) { 215 // MS runtime is weird: it exports _setjmp, but longjmp! 216 setUseUnderscoreSetJmp(true); 217 setUseUnderscoreLongJmp(false); 218 } else { 219 setUseUnderscoreSetJmp(true); 220 setUseUnderscoreLongJmp(true); 221 } 222 223 // Set up the register classes. 224 addRegisterClass(MVT::i8, &X86::GR8RegClass); 225 addRegisterClass(MVT::i16, &X86::GR16RegClass); 226 addRegisterClass(MVT::i32, &X86::GR32RegClass); 227 if (Subtarget->is64Bit()) 228 addRegisterClass(MVT::i64, &X86::GR64RegClass); 229 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 231 232 // We don't accept any truncstore of integer registers. 233 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 234 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 236 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 239 240 // SETOEQ and SETUNE require checking two conditions. 241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 247 248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 249 // operation. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 253 254 if (Subtarget->is64Bit()) { 255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 257 } else if (!TM.Options.UseSoftFloat) { 258 // We have an algorithm for SSE2->double, and we turn this into a 259 // 64-bit FILD followed by conditional FADD for other targets. 260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 261 // We have an algorithm for SSE2, and we turn this into a 64-bit 262 // FILD for other targets. 263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 264 } 265 266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 267 // this operation. 268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 270 271 if (!TM.Options.UseSoftFloat) { 272 // SSE has no i16 to fp conversion, only i32 273 if (X86ScalarSSEf32) { 274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 275 // f32 and f64 cases are Legal, f80 case is not 276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 277 } else { 278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 280 } 281 } else { 282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 284 } 285 286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 287 // are Legal, f80 is custom lowered. 288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 290 291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 292 // this operation. 293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 295 296 if (X86ScalarSSEf32) { 297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 298 // f32 and f64 cases are Legal, f80 case is not 299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 300 } else { 301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 303 } 304 305 // Handle FP_TO_UINT by promoting the destination to a larger signed 306 // conversion. 307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 310 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 314 } else if (!TM.Options.UseSoftFloat) { 315 // Since AVX is a superset of SSE3, only check for SSE here. 316 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 317 // Expand FP_TO_UINT into a select. 318 // FIXME: We would like to use a Custom expander here eventually to do 319 // the optimal thing for SSE vs. the default expansion in the legalizer. 320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 321 else 322 // With SSE3 we can use fisttpll to convert to a signed i64; without 323 // SSE, we're stuck with a fistpll. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 325 } 326 327 if (isTargetFTOL()) { 328 // Use the _ftol2 runtime function, which has a pseudo-instruction 329 // to handle its weird calling convention. 330 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 331 } 332 333 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 334 if (!X86ScalarSSEf64) { 335 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 336 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 339 // Without SSE, i64->f64 goes through memory. 340 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 341 } 342 } 343 344 // Scalar integer divide and remainder are lowered to use operations that 345 // produce two results, to match the available instructions. This exposes 346 // the two-result form to trivial CSE, which is able to combine x/y and x%y 347 // into a single instruction. 348 // 349 // Scalar integer multiply-high is also lowered to use two-result 350 // operations, to match the available instructions. However, plain multiply 351 // (low) operations are left as Legal, as there are single-result 352 // instructions for this in x86. Using the two-result multiply instructions 353 // when both high and low results are needed must be arranged by dagcombine. 354 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 355 MVT VT = IntVTs[i]; 356 setOperationAction(ISD::MULHS, VT, Expand); 357 setOperationAction(ISD::MULHU, VT, Expand); 358 setOperationAction(ISD::SDIV, VT, Expand); 359 setOperationAction(ISD::UDIV, VT, Expand); 360 setOperationAction(ISD::SREM, VT, Expand); 361 setOperationAction(ISD::UREM, VT, Expand); 362 363 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 364 setOperationAction(ISD::ADDC, VT, Custom); 365 setOperationAction(ISD::ADDE, VT, Custom); 366 setOperationAction(ISD::SUBC, VT, Custom); 367 setOperationAction(ISD::SUBE, VT, Custom); 368 } 369 370 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 371 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 372 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 373 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 374 if (Subtarget->is64Bit()) 375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 379 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 380 setOperationAction(ISD::FREM , MVT::f32 , Expand); 381 setOperationAction(ISD::FREM , MVT::f64 , Expand); 382 setOperationAction(ISD::FREM , MVT::f80 , Expand); 383 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 384 385 // Promote the i8 variants and force them on up to i32 which has a shorter 386 // encoding. 387 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 388 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 390 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 391 if (Subtarget->hasBMI()) { 392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 393 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 394 if (Subtarget->is64Bit()) 395 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 396 } else { 397 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 398 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 399 if (Subtarget->is64Bit()) 400 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 401 } 402 403 if (Subtarget->hasLZCNT()) { 404 // When promoting the i8 variants, force them to i32 for a shorter 405 // encoding. 406 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 407 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 409 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 412 if (Subtarget->is64Bit()) 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 414 } else { 415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 416 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 417 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 421 if (Subtarget->is64Bit()) { 422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 424 } 425 } 426 427 if (Subtarget->hasPOPCNT()) { 428 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 429 } else { 430 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 431 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 432 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 433 if (Subtarget->is64Bit()) 434 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 435 } 436 437 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 438 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 439 440 // These should be promoted to a larger select which is supported. 441 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 442 // X86 wants to expand cmov itself. 443 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 444 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 445 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 446 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 447 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 448 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 449 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 450 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 452 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 453 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 454 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 455 if (Subtarget->is64Bit()) { 456 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 457 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 458 } 459 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 460 461 // Darwin ABI issue. 462 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 463 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 464 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 465 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 466 if (Subtarget->is64Bit()) 467 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 468 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 470 if (Subtarget->is64Bit()) { 471 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 472 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 473 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 474 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 475 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 476 } 477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 478 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 479 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 480 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 481 if (Subtarget->is64Bit()) { 482 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 483 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 484 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 485 } 486 487 if (Subtarget->hasSSE1()) 488 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 489 490 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 491 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 492 493 // On X86 and X86-64, atomic operations are lowered to locked instructions. 494 // Locked instructions, in turn, have implicit fence semantics (all memory 495 // operations are flushed before issuing the locked instruction, and they 496 // are not buffered), so we can fold away the common pattern of 497 // fence-atomic-fence. 498 setShouldFoldAtomicFences(true); 499 500 // Expand certain atomics 501 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 502 MVT VT = IntVTs[i]; 503 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 505 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 506 } 507 508 if (!Subtarget->is64Bit()) { 509 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 513 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 514 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 515 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 516 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 517 } 518 519 if (Subtarget->hasCmpxchg16b()) { 520 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 521 } 522 523 // FIXME - use subtarget debug flags 524 if (!Subtarget->isTargetDarwin() && 525 !Subtarget->isTargetELF() && 526 !Subtarget->isTargetCygMing()) { 527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 528 } 529 530 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 531 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 532 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 533 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 534 if (Subtarget->is64Bit()) { 535 setExceptionPointerRegister(X86::RAX); 536 setExceptionSelectorRegister(X86::RDX); 537 } else { 538 setExceptionPointerRegister(X86::EAX); 539 setExceptionSelectorRegister(X86::EDX); 540 } 541 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 542 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 543 544 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 545 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 546 547 setOperationAction(ISD::TRAP, MVT::Other, Legal); 548 549 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 550 setOperationAction(ISD::VASTART , MVT::Other, Custom); 551 setOperationAction(ISD::VAEND , MVT::Other, Expand); 552 if (Subtarget->is64Bit()) { 553 setOperationAction(ISD::VAARG , MVT::Other, Custom); 554 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 555 } else { 556 setOperationAction(ISD::VAARG , MVT::Other, Expand); 557 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 558 } 559 560 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 561 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 562 563 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Custom); 566 else if (TM.Options.EnableSegmentedStacks) 567 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 568 MVT::i64 : MVT::i32, Custom); 569 else 570 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 571 MVT::i64 : MVT::i32, Expand); 572 573 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 574 // f32 and f64 use SSE. 575 // Set up the FP register classes. 576 addRegisterClass(MVT::f32, &X86::FR32RegClass); 577 addRegisterClass(MVT::f64, &X86::FR64RegClass); 578 579 // Use ANDPD to simulate FABS. 580 setOperationAction(ISD::FABS , MVT::f64, Custom); 581 setOperationAction(ISD::FABS , MVT::f32, Custom); 582 583 // Use XORP to simulate FNEG. 584 setOperationAction(ISD::FNEG , MVT::f64, Custom); 585 setOperationAction(ISD::FNEG , MVT::f32, Custom); 586 587 // Use ANDPD and ORPD to simulate FCOPYSIGN. 588 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 589 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 590 591 // Lower this to FGETSIGNx86 plus an AND. 592 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 593 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 594 595 // We don't support sin/cos/fmod 596 setOperationAction(ISD::FSIN , MVT::f64, Expand); 597 setOperationAction(ISD::FCOS , MVT::f64, Expand); 598 setOperationAction(ISD::FSIN , MVT::f32, Expand); 599 setOperationAction(ISD::FCOS , MVT::f32, Expand); 600 601 // Expand FP immediates into loads from the stack, except for the special 602 // cases we handle. 603 addLegalFPImmediate(APFloat(+0.0)); // xorpd 604 addLegalFPImmediate(APFloat(+0.0f)); // xorps 605 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 606 // Use SSE for f32, x87 for f64. 607 // Set up the FP register classes. 608 addRegisterClass(MVT::f32, &X86::FR32RegClass); 609 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 610 611 // Use ANDPS to simulate FABS. 612 setOperationAction(ISD::FABS , MVT::f32, Custom); 613 614 // Use XORP to simulate FNEG. 615 setOperationAction(ISD::FNEG , MVT::f32, Custom); 616 617 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 618 619 // Use ANDPS and ORPS to simulate FCOPYSIGN. 620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 622 623 // We don't support sin/cos/fmod 624 setOperationAction(ISD::FSIN , MVT::f32, Expand); 625 setOperationAction(ISD::FCOS , MVT::f32, Expand); 626 627 // Special cases we handle for FP constants. 628 addLegalFPImmediate(APFloat(+0.0f)); // xorps 629 addLegalFPImmediate(APFloat(+0.0)); // FLD0 630 addLegalFPImmediate(APFloat(+1.0)); // FLD1 631 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 632 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 633 634 if (!TM.Options.UnsafeFPMath) { 635 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 636 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 637 } 638 } else if (!TM.Options.UseSoftFloat) { 639 // f32 and f64 in x87. 640 // Set up the FP register classes. 641 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 642 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 643 644 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 645 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 648 649 if (!TM.Options.UnsafeFPMath) { 650 setOperationAction(ISD::FSIN , MVT::f32 , Expand); 651 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 652 setOperationAction(ISD::FCOS , MVT::f32 , Expand); 653 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 654 } 655 addLegalFPImmediate(APFloat(+0.0)); // FLD0 656 addLegalFPImmediate(APFloat(+1.0)); // FLD1 657 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 658 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 659 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 660 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 661 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 662 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 663 } 664 665 // We don't support FMA. 666 setOperationAction(ISD::FMA, MVT::f64, Expand); 667 setOperationAction(ISD::FMA, MVT::f32, Expand); 668 669 // Long double always uses X87. 670 if (!TM.Options.UseSoftFloat) { 671 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 672 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 673 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 674 { 675 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 676 addLegalFPImmediate(TmpFlt); // FLD0 677 TmpFlt.changeSign(); 678 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 679 680 bool ignored; 681 APFloat TmpFlt2(+1.0); 682 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 683 &ignored); 684 addLegalFPImmediate(TmpFlt2); // FLD1 685 TmpFlt2.changeSign(); 686 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 687 } 688 689 if (!TM.Options.UnsafeFPMath) { 690 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 691 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 692 } 693 694 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 695 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 696 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 697 setOperationAction(ISD::FRINT, MVT::f80, Expand); 698 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 699 setOperationAction(ISD::FMA, MVT::f80, Expand); 700 } 701 702 // Always use a library call for pow. 703 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 704 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 705 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 706 707 setOperationAction(ISD::FLOG, MVT::f80, Expand); 708 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 709 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 710 setOperationAction(ISD::FEXP, MVT::f80, Expand); 711 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 712 713 // First set operation action for all vector types to either promote 714 // (for widening) or expand (for scalarization). Then we will selectively 715 // turn on ones that can be effectively codegen'd. 716 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 717 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) { 718 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 733 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 735 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 736 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::FFLOOR, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 769 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 770 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 771 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 772 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 773 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 774 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 775 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 776 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 777 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 778 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 779 setTruncStoreAction((MVT::SimpleValueType)VT, 780 (MVT::SimpleValueType)InnerVT, Expand); 781 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 782 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 783 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 784 } 785 786 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 787 // with -msoft-float, disable use of MMX as well. 788 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 789 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 790 // No operations on x86mmx supported, everything uses intrinsics. 791 } 792 793 // MMX-sized vectors (other than x86mmx) are expected to be expanded 794 // into smaller operations. 795 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 796 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 797 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 798 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 799 setOperationAction(ISD::AND, MVT::v8i8, Expand); 800 setOperationAction(ISD::AND, MVT::v4i16, Expand); 801 setOperationAction(ISD::AND, MVT::v2i32, Expand); 802 setOperationAction(ISD::AND, MVT::v1i64, Expand); 803 setOperationAction(ISD::OR, MVT::v8i8, Expand); 804 setOperationAction(ISD::OR, MVT::v4i16, Expand); 805 setOperationAction(ISD::OR, MVT::v2i32, Expand); 806 setOperationAction(ISD::OR, MVT::v1i64, Expand); 807 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 808 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 809 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 810 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 811 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 814 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 816 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 817 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 818 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 819 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 820 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 821 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 822 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 823 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 824 825 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 826 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 827 828 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 829 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 830 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 831 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 832 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 833 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 834 setOperationAction(ISD::FABS, MVT::v4f32, Custom); 835 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 836 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 837 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 838 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 839 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 840 } 841 842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 843 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 844 845 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 846 // registers cannot be used even for integer operations. 847 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 848 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 849 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 850 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 851 852 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 853 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 854 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 855 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 856 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 857 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 858 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 859 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 860 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 861 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 862 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 863 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 864 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 865 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 866 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 867 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 868 setOperationAction(ISD::FABS, MVT::v2f64, Custom); 869 870 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 871 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 872 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 873 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 874 875 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 876 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 877 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 878 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 879 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 880 881 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 882 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 883 MVT VT = (MVT::SimpleValueType)i; 884 // Do not attempt to custom lower non-power-of-2 vectors 885 if (!isPowerOf2_32(VT.getVectorNumElements())) 886 continue; 887 // Do not attempt to custom lower non-128-bit vectors 888 if (!VT.is128BitVector()) 889 continue; 890 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 891 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 892 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 893 } 894 895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 901 902 if (Subtarget->is64Bit()) { 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 905 } 906 907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 908 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 909 MVT VT = (MVT::SimpleValueType)i; 910 911 // Do not attempt to promote non-128-bit vectors 912 if (!VT.is128BitVector()) 913 continue; 914 915 setOperationAction(ISD::AND, VT, Promote); 916 AddPromotedToType (ISD::AND, VT, MVT::v2i64); 917 setOperationAction(ISD::OR, VT, Promote); 918 AddPromotedToType (ISD::OR, VT, MVT::v2i64); 919 setOperationAction(ISD::XOR, VT, Promote); 920 AddPromotedToType (ISD::XOR, VT, MVT::v2i64); 921 setOperationAction(ISD::LOAD, VT, Promote); 922 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); 923 setOperationAction(ISD::SELECT, VT, Promote); 924 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); 925 } 926 927 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 928 929 // Custom lower v2i64 and v2f64 selects. 930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 934 935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 937 938 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal); 939 } 940 941 if (Subtarget->hasSSE41()) { 942 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 943 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 944 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 945 setOperationAction(ISD::FRINT, MVT::f32, Legal); 946 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 947 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 948 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 949 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 950 setOperationAction(ISD::FRINT, MVT::f64, Legal); 951 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 952 953 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 954 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 955 956 // FIXME: Do we need to handle scalar-to-vector here? 957 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 958 959 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 960 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 961 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 962 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 963 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 964 965 // i8 and i16 vectors are custom , because the source register and source 966 // source memory operand types are not the same width. f32 vectors are 967 // custom since the immediate controlling the insert encodes additional 968 // information. 969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 973 974 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 978 979 // FIXME: these should be Legal but thats only for the case where 980 // the index is constant. For now custom expand to deal with that. 981 if (Subtarget->is64Bit()) { 982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 984 } 985 } 986 987 if (Subtarget->hasSSE2()) { 988 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 990 991 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 992 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 993 994 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 995 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 996 997 if (Subtarget->hasAVX2()) { 998 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 999 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 1000 1001 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 1002 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 1003 1004 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1005 } else { 1006 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1007 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1008 1009 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1010 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1011 1012 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1013 } 1014 } 1015 1016 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1017 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1018 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1019 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1020 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1021 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1022 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1023 1024 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1025 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1026 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1027 1028 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1031 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1033 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); 1034 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1035 setOperationAction(ISD::FABS, MVT::v8f32, Custom); 1036 1037 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1038 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1040 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1041 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1042 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); 1043 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1044 setOperationAction(ISD::FABS, MVT::v4f64, Custom); 1045 1046 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1047 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1048 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1049 1050 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal); 1051 1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1060 1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1065 1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1069 1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1074 1075 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) { 1076 setOperationAction(ISD::FMA, MVT::v8f32, Custom); 1077 setOperationAction(ISD::FMA, MVT::v4f64, Custom); 1078 setOperationAction(ISD::FMA, MVT::v4f32, Custom); 1079 setOperationAction(ISD::FMA, MVT::v2f64, Custom); 1080 setOperationAction(ISD::FMA, MVT::f32, Custom); 1081 setOperationAction(ISD::FMA, MVT::f64, Custom); 1082 } 1083 1084 if (Subtarget->hasAVX2()) { 1085 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1086 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1087 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1088 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1089 1090 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1091 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1092 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1093 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1094 1095 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1096 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1097 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1098 // Don't lower v32i8 because there is no 128-bit byte mul 1099 1100 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1101 1102 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1103 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1104 1105 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1106 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1107 1108 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1109 } else { 1110 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1111 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1112 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1113 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1114 1115 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1116 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1117 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1118 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1119 1120 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1121 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1122 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1123 // Don't lower v32i8 because there is no 128-bit byte mul 1124 1125 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1126 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1127 1128 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1129 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1130 1131 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1132 } 1133 1134 // Custom lower several nodes for 256-bit types. 1135 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1136 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1137 MVT VT = (MVT::SimpleValueType)i; 1138 1139 // Extract subvector is special because the value type 1140 // (result) is 128-bit but the source is 256-bit wide. 1141 if (VT.is128BitVector()) 1142 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1143 1144 // Do not attempt to custom lower other non-256-bit vectors 1145 if (!VT.is256BitVector()) 1146 continue; 1147 1148 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 1149 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1150 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1152 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 1153 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1154 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1155 } 1156 1157 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1158 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1159 MVT VT = (MVT::SimpleValueType)i; 1160 1161 // Do not attempt to promote non-256-bit vectors 1162 if (!VT.is256BitVector()) 1163 continue; 1164 1165 setOperationAction(ISD::AND, VT, Promote); 1166 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 1167 setOperationAction(ISD::OR, VT, Promote); 1168 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 1169 setOperationAction(ISD::XOR, VT, Promote); 1170 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 1171 setOperationAction(ISD::LOAD, VT, Promote); 1172 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 1173 setOperationAction(ISD::SELECT, VT, Promote); 1174 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 1175 } 1176 } 1177 1178 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1179 // of this type with custom code. 1180 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1181 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1182 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1183 Custom); 1184 } 1185 1186 // We want to custom lower some of our intrinsics. 1187 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1188 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 1189 1190 1191 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1192 // handle type legalization for these operations here. 1193 // 1194 // FIXME: We really should do custom legalization for addition and 1195 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1196 // than generic legalization for 64-bit multiplication-with-overflow, though. 1197 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1198 // Add/Sub/Mul with overflow operations are custom lowered. 1199 MVT VT = IntVTs[i]; 1200 setOperationAction(ISD::SADDO, VT, Custom); 1201 setOperationAction(ISD::UADDO, VT, Custom); 1202 setOperationAction(ISD::SSUBO, VT, Custom); 1203 setOperationAction(ISD::USUBO, VT, Custom); 1204 setOperationAction(ISD::SMULO, VT, Custom); 1205 setOperationAction(ISD::UMULO, VT, Custom); 1206 } 1207 1208 // There are no 8-bit 3-address imul/mul instructions 1209 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1210 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1211 1212 if (!Subtarget->is64Bit()) { 1213 // These libcalls are not available in 32-bit. 1214 setLibcallName(RTLIB::SHL_I128, 0); 1215 setLibcallName(RTLIB::SRL_I128, 0); 1216 setLibcallName(RTLIB::SRA_I128, 0); 1217 } 1218 1219 // We have target-specific dag combine patterns for the following nodes: 1220 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1221 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1222 setTargetDAGCombine(ISD::VSELECT); 1223 setTargetDAGCombine(ISD::SELECT); 1224 setTargetDAGCombine(ISD::SHL); 1225 setTargetDAGCombine(ISD::SRA); 1226 setTargetDAGCombine(ISD::SRL); 1227 setTargetDAGCombine(ISD::OR); 1228 setTargetDAGCombine(ISD::AND); 1229 setTargetDAGCombine(ISD::ADD); 1230 setTargetDAGCombine(ISD::FADD); 1231 setTargetDAGCombine(ISD::FSUB); 1232 setTargetDAGCombine(ISD::FMA); 1233 setTargetDAGCombine(ISD::SUB); 1234 setTargetDAGCombine(ISD::LOAD); 1235 setTargetDAGCombine(ISD::STORE); 1236 setTargetDAGCombine(ISD::ZERO_EXTEND); 1237 setTargetDAGCombine(ISD::ANY_EXTEND); 1238 setTargetDAGCombine(ISD::SIGN_EXTEND); 1239 setTargetDAGCombine(ISD::TRUNCATE); 1240 setTargetDAGCombine(ISD::UINT_TO_FP); 1241 setTargetDAGCombine(ISD::SINT_TO_FP); 1242 setTargetDAGCombine(ISD::SETCC); 1243 setTargetDAGCombine(ISD::FP_TO_SINT); 1244 if (Subtarget->is64Bit()) 1245 setTargetDAGCombine(ISD::MUL); 1246 setTargetDAGCombine(ISD::XOR); 1247 1248 computeRegisterProperties(); 1249 1250 // On Darwin, -Os means optimize for size without hurting performance, 1251 // do not reduce the limit. 1252 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1253 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1254 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1255 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1256 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1257 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1258 setPrefLoopAlignment(4); // 2^4 bytes. 1259 benefitFromCodePlacementOpt = true; 1260 1261 // Predictable cmov don't hurt on atom because it's in-order. 1262 predictableSelectIsExpensive = !Subtarget->isAtom(); 1263 1264 setPrefFunctionAlignment(4); // 2^4 bytes. 1265} 1266 1267 1268EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1269 if (!VT.isVector()) return MVT::i8; 1270 return VT.changeVectorElementTypeToInteger(); 1271} 1272 1273 1274/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1275/// the desired ByVal argument alignment. 1276static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1277 if (MaxAlign == 16) 1278 return; 1279 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1280 if (VTy->getBitWidth() == 128) 1281 MaxAlign = 16; 1282 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1283 unsigned EltAlign = 0; 1284 getMaxByValAlign(ATy->getElementType(), EltAlign); 1285 if (EltAlign > MaxAlign) 1286 MaxAlign = EltAlign; 1287 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1288 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1289 unsigned EltAlign = 0; 1290 getMaxByValAlign(STy->getElementType(i), EltAlign); 1291 if (EltAlign > MaxAlign) 1292 MaxAlign = EltAlign; 1293 if (MaxAlign == 16) 1294 break; 1295 } 1296 } 1297} 1298 1299/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1300/// function arguments in the caller parameter area. For X86, aggregates 1301/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1302/// are at 4-byte boundaries. 1303unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1304 if (Subtarget->is64Bit()) { 1305 // Max of 8 and alignment of type. 1306 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1307 if (TyAlign > 8) 1308 return TyAlign; 1309 return 8; 1310 } 1311 1312 unsigned Align = 4; 1313 if (Subtarget->hasSSE1()) 1314 getMaxByValAlign(Ty, Align); 1315 return Align; 1316} 1317 1318/// getOptimalMemOpType - Returns the target specific optimal type for load 1319/// and store operations as a result of memset, memcpy, and memmove 1320/// lowering. If DstAlign is zero that means it's safe to destination 1321/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1322/// means there isn't a need to check it against alignment requirement, 1323/// probably because the source does not need to be loaded. If 1324/// 'IsZeroVal' is true, that means it's safe to return a 1325/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1326/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1327/// constant so it does not need to be loaded. 1328/// It returns EVT::Other if the type should be determined using generic 1329/// target-independent logic. 1330EVT 1331X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1332 unsigned DstAlign, unsigned SrcAlign, 1333 bool IsZeroVal, 1334 bool MemcpyStrSrc, 1335 MachineFunction &MF) const { 1336 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1337 // linux. This is because the stack realignment code can't handle certain 1338 // cases like PR2962. This should be removed when PR2962 is fixed. 1339 const Function *F = MF.getFunction(); 1340 if (IsZeroVal && 1341 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1342 if (Size >= 16 && 1343 (Subtarget->isUnalignedMemAccessFast() || 1344 ((DstAlign == 0 || DstAlign >= 16) && 1345 (SrcAlign == 0 || SrcAlign >= 16))) && 1346 Subtarget->getStackAlignment() >= 16) { 1347 if (Subtarget->getStackAlignment() >= 32) { 1348 if (Subtarget->hasAVX2()) 1349 return MVT::v8i32; 1350 if (Subtarget->hasAVX()) 1351 return MVT::v8f32; 1352 } 1353 if (Subtarget->hasSSE2()) 1354 return MVT::v4i32; 1355 if (Subtarget->hasSSE1()) 1356 return MVT::v4f32; 1357 } else if (!MemcpyStrSrc && Size >= 8 && 1358 !Subtarget->is64Bit() && 1359 Subtarget->getStackAlignment() >= 8 && 1360 Subtarget->hasSSE2()) { 1361 // Do not use f64 to lower memcpy if source is string constant. It's 1362 // better to use i32 to avoid the loads. 1363 return MVT::f64; 1364 } 1365 } 1366 if (Subtarget->is64Bit() && Size >= 8) 1367 return MVT::i64; 1368 return MVT::i32; 1369} 1370 1371/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1372/// current function. The returned value is a member of the 1373/// MachineJumpTableInfo::JTEntryKind enum. 1374unsigned X86TargetLowering::getJumpTableEncoding() const { 1375 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1376 // symbol. 1377 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1378 Subtarget->isPICStyleGOT()) 1379 return MachineJumpTableInfo::EK_Custom32; 1380 1381 // Otherwise, use the normal jump table encoding heuristics. 1382 return TargetLowering::getJumpTableEncoding(); 1383} 1384 1385const MCExpr * 1386X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1387 const MachineBasicBlock *MBB, 1388 unsigned uid,MCContext &Ctx) const{ 1389 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1390 Subtarget->isPICStyleGOT()); 1391 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1392 // entries. 1393 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1394 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1395} 1396 1397/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1398/// jumptable. 1399SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1400 SelectionDAG &DAG) const { 1401 if (!Subtarget->is64Bit()) 1402 // This doesn't have DebugLoc associated with it, but is not really the 1403 // same as a Register. 1404 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1405 return Table; 1406} 1407 1408/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1409/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1410/// MCExpr. 1411const MCExpr *X86TargetLowering:: 1412getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1413 MCContext &Ctx) const { 1414 // X86-64 uses RIP relative addressing based on the jump table label. 1415 if (Subtarget->isPICStyleRIPRel()) 1416 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1417 1418 // Otherwise, the reference is relative to the PIC base. 1419 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1420} 1421 1422// FIXME: Why this routine is here? Move to RegInfo! 1423std::pair<const TargetRegisterClass*, uint8_t> 1424X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1425 const TargetRegisterClass *RRC = 0; 1426 uint8_t Cost = 1; 1427 switch (VT.getSimpleVT().SimpleTy) { 1428 default: 1429 return TargetLowering::findRepresentativeClass(VT); 1430 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1431 RRC = Subtarget->is64Bit() ? 1432 (const TargetRegisterClass*)&X86::GR64RegClass : 1433 (const TargetRegisterClass*)&X86::GR32RegClass; 1434 break; 1435 case MVT::x86mmx: 1436 RRC = &X86::VR64RegClass; 1437 break; 1438 case MVT::f32: case MVT::f64: 1439 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1440 case MVT::v4f32: case MVT::v2f64: 1441 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1442 case MVT::v4f64: 1443 RRC = &X86::VR128RegClass; 1444 break; 1445 } 1446 return std::make_pair(RRC, Cost); 1447} 1448 1449bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1450 unsigned &Offset) const { 1451 if (!Subtarget->isTargetLinux()) 1452 return false; 1453 1454 if (Subtarget->is64Bit()) { 1455 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1456 Offset = 0x28; 1457 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1458 AddressSpace = 256; 1459 else 1460 AddressSpace = 257; 1461 } else { 1462 // %gs:0x14 on i386 1463 Offset = 0x14; 1464 AddressSpace = 256; 1465 } 1466 return true; 1467} 1468 1469 1470//===----------------------------------------------------------------------===// 1471// Return Value Calling Convention Implementation 1472//===----------------------------------------------------------------------===// 1473 1474#include "X86GenCallingConv.inc" 1475 1476bool 1477X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1478 MachineFunction &MF, bool isVarArg, 1479 const SmallVectorImpl<ISD::OutputArg> &Outs, 1480 LLVMContext &Context) const { 1481 SmallVector<CCValAssign, 16> RVLocs; 1482 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1483 RVLocs, Context); 1484 return CCInfo.CheckReturn(Outs, RetCC_X86); 1485} 1486 1487SDValue 1488X86TargetLowering::LowerReturn(SDValue Chain, 1489 CallingConv::ID CallConv, bool isVarArg, 1490 const SmallVectorImpl<ISD::OutputArg> &Outs, 1491 const SmallVectorImpl<SDValue> &OutVals, 1492 DebugLoc dl, SelectionDAG &DAG) const { 1493 MachineFunction &MF = DAG.getMachineFunction(); 1494 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1495 1496 SmallVector<CCValAssign, 16> RVLocs; 1497 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1498 RVLocs, *DAG.getContext()); 1499 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1500 1501 // Add the regs to the liveout set for the function. 1502 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1503 for (unsigned i = 0; i != RVLocs.size(); ++i) 1504 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1505 MRI.addLiveOut(RVLocs[i].getLocReg()); 1506 1507 SDValue Flag; 1508 1509 SmallVector<SDValue, 6> RetOps; 1510 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1511 // Operand #1 = Bytes To Pop 1512 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1513 MVT::i16)); 1514 1515 // Copy the result values into the output registers. 1516 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1517 CCValAssign &VA = RVLocs[i]; 1518 assert(VA.isRegLoc() && "Can only return in registers!"); 1519 SDValue ValToCopy = OutVals[i]; 1520 EVT ValVT = ValToCopy.getValueType(); 1521 1522 // Promote values to the appropriate types 1523 if (VA.getLocInfo() == CCValAssign::SExt) 1524 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1525 else if (VA.getLocInfo() == CCValAssign::ZExt) 1526 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1527 else if (VA.getLocInfo() == CCValAssign::AExt) 1528 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1529 else if (VA.getLocInfo() == CCValAssign::BCvt) 1530 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); 1531 1532 // If this is x86-64, and we disabled SSE, we can't return FP values, 1533 // or SSE or MMX vectors. 1534 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1535 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1536 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1537 report_fatal_error("SSE register return with SSE disabled"); 1538 } 1539 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1540 // llvm-gcc has never done it right and no one has noticed, so this 1541 // should be OK for now. 1542 if (ValVT == MVT::f64 && 1543 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1544 report_fatal_error("SSE2 register return with SSE2 disabled"); 1545 1546 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1547 // the RET instruction and handled by the FP Stackifier. 1548 if (VA.getLocReg() == X86::ST0 || 1549 VA.getLocReg() == X86::ST1) { 1550 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1551 // change the value to the FP stack register class. 1552 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1553 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1554 RetOps.push_back(ValToCopy); 1555 // Don't emit a copytoreg. 1556 continue; 1557 } 1558 1559 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1560 // which is returned in RAX / RDX. 1561 if (Subtarget->is64Bit()) { 1562 if (ValVT == MVT::x86mmx) { 1563 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1564 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1565 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1566 ValToCopy); 1567 // If we don't have SSE2 available, convert to v4f32 so the generated 1568 // register is legal. 1569 if (!Subtarget->hasSSE2()) 1570 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1571 } 1572 } 1573 } 1574 1575 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1576 Flag = Chain.getValue(1); 1577 } 1578 1579 // The x86-64 ABI for returning structs by value requires that we copy 1580 // the sret argument into %rax for the return. We saved the argument into 1581 // a virtual register in the entry block, so now we copy the value out 1582 // and into %rax. 1583 if (Subtarget->is64Bit() && 1584 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1585 MachineFunction &MF = DAG.getMachineFunction(); 1586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1587 unsigned Reg = FuncInfo->getSRetReturnReg(); 1588 assert(Reg && 1589 "SRetReturnReg should have been set in LowerFormalArguments()."); 1590 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1591 1592 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1593 Flag = Chain.getValue(1); 1594 1595 // RAX now acts like a return value. 1596 MRI.addLiveOut(X86::RAX); 1597 } 1598 1599 RetOps[0] = Chain; // Update chain. 1600 1601 // Add the flag if we have it. 1602 if (Flag.getNode()) 1603 RetOps.push_back(Flag); 1604 1605 return DAG.getNode(X86ISD::RET_FLAG, dl, 1606 MVT::Other, &RetOps[0], RetOps.size()); 1607} 1608 1609bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1610 if (N->getNumValues() != 1) 1611 return false; 1612 if (!N->hasNUsesOfValue(1, 0)) 1613 return false; 1614 1615 SDValue TCChain = Chain; 1616 SDNode *Copy = *N->use_begin(); 1617 if (Copy->getOpcode() == ISD::CopyToReg) { 1618 // If the copy has a glue operand, we conservatively assume it isn't safe to 1619 // perform a tail call. 1620 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1621 return false; 1622 TCChain = Copy->getOperand(0); 1623 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1624 return false; 1625 1626 bool HasRet = false; 1627 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1628 UI != UE; ++UI) { 1629 if (UI->getOpcode() != X86ISD::RET_FLAG) 1630 return false; 1631 HasRet = true; 1632 } 1633 1634 if (!HasRet) 1635 return false; 1636 1637 Chain = TCChain; 1638 return true; 1639} 1640 1641EVT 1642X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1643 ISD::NodeType ExtendKind) const { 1644 MVT ReturnMVT; 1645 // TODO: Is this also valid on 32-bit? 1646 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1647 ReturnMVT = MVT::i8; 1648 else 1649 ReturnMVT = MVT::i32; 1650 1651 EVT MinVT = getRegisterType(Context, ReturnMVT); 1652 return VT.bitsLT(MinVT) ? MinVT : VT; 1653} 1654 1655/// LowerCallResult - Lower the result values of a call into the 1656/// appropriate copies out of appropriate physical registers. 1657/// 1658SDValue 1659X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1660 CallingConv::ID CallConv, bool isVarArg, 1661 const SmallVectorImpl<ISD::InputArg> &Ins, 1662 DebugLoc dl, SelectionDAG &DAG, 1663 SmallVectorImpl<SDValue> &InVals) const { 1664 1665 // Assign locations to each value returned by this call. 1666 SmallVector<CCValAssign, 16> RVLocs; 1667 bool Is64Bit = Subtarget->is64Bit(); 1668 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1669 getTargetMachine(), RVLocs, *DAG.getContext()); 1670 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1671 1672 // Copy all of the result registers out of their specified physreg. 1673 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1674 CCValAssign &VA = RVLocs[i]; 1675 EVT CopyVT = VA.getValVT(); 1676 1677 // If this is x86-64, and we disabled SSE, we can't return FP values 1678 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1679 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1680 report_fatal_error("SSE register return with SSE disabled"); 1681 } 1682 1683 SDValue Val; 1684 1685 // If this is a call to a function that returns an fp value on the floating 1686 // point stack, we must guarantee the value is popped from the stack, so 1687 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1688 // if the return value is not used. We use the FpPOP_RETVAL instruction 1689 // instead. 1690 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1691 // If we prefer to use the value in xmm registers, copy it out as f80 and 1692 // use a truncate to move it from fp stack reg to xmm reg. 1693 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1694 SDValue Ops[] = { Chain, InFlag }; 1695 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1696 MVT::Other, MVT::Glue, Ops, 2), 1); 1697 Val = Chain.getValue(0); 1698 1699 // Round the f80 to the right size, which also moves it to the appropriate 1700 // xmm register. 1701 if (CopyVT != VA.getValVT()) 1702 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1703 // This truncation won't change the value. 1704 DAG.getIntPtrConstant(1)); 1705 } else { 1706 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1707 CopyVT, InFlag).getValue(1); 1708 Val = Chain.getValue(0); 1709 } 1710 InFlag = Chain.getValue(2); 1711 InVals.push_back(Val); 1712 } 1713 1714 return Chain; 1715} 1716 1717 1718//===----------------------------------------------------------------------===// 1719// C & StdCall & Fast Calling Convention implementation 1720//===----------------------------------------------------------------------===// 1721// StdCall calling convention seems to be standard for many Windows' API 1722// routines and around. It differs from C calling convention just a little: 1723// callee should clean up the stack, not caller. Symbols should be also 1724// decorated in some fancy way :) It doesn't support any vector arguments. 1725// For info on fast calling convention see Fast Calling Convention (tail call) 1726// implementation LowerX86_32FastCCCallTo. 1727 1728/// CallIsStructReturn - Determines whether a call uses struct return 1729/// semantics. 1730enum StructReturnType { 1731 NotStructReturn, 1732 RegStructReturn, 1733 StackStructReturn 1734}; 1735static StructReturnType 1736callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1737 if (Outs.empty()) 1738 return NotStructReturn; 1739 1740 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 1741 if (!Flags.isSRet()) 1742 return NotStructReturn; 1743 if (Flags.isInReg()) 1744 return RegStructReturn; 1745 return StackStructReturn; 1746} 1747 1748/// ArgsAreStructReturn - Determines whether a function uses struct 1749/// return semantics. 1750static StructReturnType 1751argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1752 if (Ins.empty()) 1753 return NotStructReturn; 1754 1755 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; 1756 if (!Flags.isSRet()) 1757 return NotStructReturn; 1758 if (Flags.isInReg()) 1759 return RegStructReturn; 1760 return StackStructReturn; 1761} 1762 1763/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1764/// by "Src" to address "Dst" with size and alignment information specified by 1765/// the specific parameter attribute. The copy will be passed as a byval 1766/// function parameter. 1767static SDValue 1768CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1769 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1770 DebugLoc dl) { 1771 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1772 1773 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1774 /*isVolatile*/false, /*AlwaysInline=*/true, 1775 MachinePointerInfo(), MachinePointerInfo()); 1776} 1777 1778/// IsTailCallConvention - Return true if the calling convention is one that 1779/// supports tail call optimization. 1780static bool IsTailCallConvention(CallingConv::ID CC) { 1781 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1782} 1783 1784bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1785 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1786 return false; 1787 1788 CallSite CS(CI); 1789 CallingConv::ID CalleeCC = CS.getCallingConv(); 1790 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1791 return false; 1792 1793 return true; 1794} 1795 1796/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1797/// a tailcall target by changing its ABI. 1798static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1799 bool GuaranteedTailCallOpt) { 1800 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1801} 1802 1803SDValue 1804X86TargetLowering::LowerMemArgument(SDValue Chain, 1805 CallingConv::ID CallConv, 1806 const SmallVectorImpl<ISD::InputArg> &Ins, 1807 DebugLoc dl, SelectionDAG &DAG, 1808 const CCValAssign &VA, 1809 MachineFrameInfo *MFI, 1810 unsigned i) const { 1811 // Create the nodes corresponding to a load from this parameter slot. 1812 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1813 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1814 getTargetMachine().Options.GuaranteedTailCallOpt); 1815 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1816 EVT ValVT; 1817 1818 // If value is passed by pointer we have address passed instead of the value 1819 // itself. 1820 if (VA.getLocInfo() == CCValAssign::Indirect) 1821 ValVT = VA.getLocVT(); 1822 else 1823 ValVT = VA.getValVT(); 1824 1825 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1826 // changed with more analysis. 1827 // In case of tail call optimization mark all arguments mutable. Since they 1828 // could be overwritten by lowering of arguments in case of a tail call. 1829 if (Flags.isByVal()) { 1830 unsigned Bytes = Flags.getByValSize(); 1831 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1832 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1833 return DAG.getFrameIndex(FI, getPointerTy()); 1834 } else { 1835 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1836 VA.getLocMemOffset(), isImmutable); 1837 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1838 return DAG.getLoad(ValVT, dl, Chain, FIN, 1839 MachinePointerInfo::getFixedStack(FI), 1840 false, false, false, 0); 1841 } 1842} 1843 1844SDValue 1845X86TargetLowering::LowerFormalArguments(SDValue Chain, 1846 CallingConv::ID CallConv, 1847 bool isVarArg, 1848 const SmallVectorImpl<ISD::InputArg> &Ins, 1849 DebugLoc dl, 1850 SelectionDAG &DAG, 1851 SmallVectorImpl<SDValue> &InVals) 1852 const { 1853 MachineFunction &MF = DAG.getMachineFunction(); 1854 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1855 1856 const Function* Fn = MF.getFunction(); 1857 if (Fn->hasExternalLinkage() && 1858 Subtarget->isTargetCygMing() && 1859 Fn->getName() == "main") 1860 FuncInfo->setForceFramePointer(true); 1861 1862 MachineFrameInfo *MFI = MF.getFrameInfo(); 1863 bool Is64Bit = Subtarget->is64Bit(); 1864 bool IsWindows = Subtarget->isTargetWindows(); 1865 bool IsWin64 = Subtarget->isTargetWin64(); 1866 1867 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1868 "Var args not supported with calling convention fastcc or ghc"); 1869 1870 // Assign locations to all of the incoming arguments. 1871 SmallVector<CCValAssign, 16> ArgLocs; 1872 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1873 ArgLocs, *DAG.getContext()); 1874 1875 // Allocate shadow area for Win64 1876 if (IsWin64) { 1877 CCInfo.AllocateStack(32, 8); 1878 } 1879 1880 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1881 1882 unsigned LastVal = ~0U; 1883 SDValue ArgValue; 1884 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1885 CCValAssign &VA = ArgLocs[i]; 1886 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1887 // places. 1888 assert(VA.getValNo() != LastVal && 1889 "Don't support value assigned to multiple locs yet"); 1890 (void)LastVal; 1891 LastVal = VA.getValNo(); 1892 1893 if (VA.isRegLoc()) { 1894 EVT RegVT = VA.getLocVT(); 1895 const TargetRegisterClass *RC; 1896 if (RegVT == MVT::i32) 1897 RC = &X86::GR32RegClass; 1898 else if (Is64Bit && RegVT == MVT::i64) 1899 RC = &X86::GR64RegClass; 1900 else if (RegVT == MVT::f32) 1901 RC = &X86::FR32RegClass; 1902 else if (RegVT == MVT::f64) 1903 RC = &X86::FR64RegClass; 1904 else if (RegVT.is256BitVector()) 1905 RC = &X86::VR256RegClass; 1906 else if (RegVT.is128BitVector()) 1907 RC = &X86::VR128RegClass; 1908 else if (RegVT == MVT::x86mmx) 1909 RC = &X86::VR64RegClass; 1910 else 1911 llvm_unreachable("Unknown argument type!"); 1912 1913 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1914 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1915 1916 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1917 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1918 // right size. 1919 if (VA.getLocInfo() == CCValAssign::SExt) 1920 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1921 DAG.getValueType(VA.getValVT())); 1922 else if (VA.getLocInfo() == CCValAssign::ZExt) 1923 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1924 DAG.getValueType(VA.getValVT())); 1925 else if (VA.getLocInfo() == CCValAssign::BCvt) 1926 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1927 1928 if (VA.isExtInLoc()) { 1929 // Handle MMX values passed in XMM regs. 1930 if (RegVT.isVector()) { 1931 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1932 ArgValue); 1933 } else 1934 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1935 } 1936 } else { 1937 assert(VA.isMemLoc()); 1938 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1939 } 1940 1941 // If value is passed via pointer - do a load. 1942 if (VA.getLocInfo() == CCValAssign::Indirect) 1943 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1944 MachinePointerInfo(), false, false, false, 0); 1945 1946 InVals.push_back(ArgValue); 1947 } 1948 1949 // The x86-64 ABI for returning structs by value requires that we copy 1950 // the sret argument into %rax for the return. Save the argument into 1951 // a virtual register so that we can access it from the return points. 1952 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1953 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1954 unsigned Reg = FuncInfo->getSRetReturnReg(); 1955 if (!Reg) { 1956 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1957 FuncInfo->setSRetReturnReg(Reg); 1958 } 1959 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1960 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1961 } 1962 1963 unsigned StackSize = CCInfo.getNextStackOffset(); 1964 // Align stack specially for tail calls. 1965 if (FuncIsMadeTailCallSafe(CallConv, 1966 MF.getTarget().Options.GuaranteedTailCallOpt)) 1967 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1968 1969 // If the function takes variable number of arguments, make a frame index for 1970 // the start of the first vararg value... for expansion of llvm.va_start. 1971 if (isVarArg) { 1972 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1973 CallConv != CallingConv::X86_ThisCall)) { 1974 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1975 } 1976 if (Is64Bit) { 1977 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1978 1979 // FIXME: We should really autogenerate these arrays 1980 static const uint16_t GPR64ArgRegsWin64[] = { 1981 X86::RCX, X86::RDX, X86::R8, X86::R9 1982 }; 1983 static const uint16_t GPR64ArgRegs64Bit[] = { 1984 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1985 }; 1986 static const uint16_t XMMArgRegs64Bit[] = { 1987 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1988 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1989 }; 1990 const uint16_t *GPR64ArgRegs; 1991 unsigned NumXMMRegs = 0; 1992 1993 if (IsWin64) { 1994 // The XMM registers which might contain var arg parameters are shadowed 1995 // in their paired GPR. So we only need to save the GPR to their home 1996 // slots. 1997 TotalNumIntRegs = 4; 1998 GPR64ArgRegs = GPR64ArgRegsWin64; 1999 } else { 2000 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 2001 GPR64ArgRegs = GPR64ArgRegs64Bit; 2002 2003 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 2004 TotalNumXMMRegs); 2005 } 2006 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 2007 TotalNumIntRegs); 2008 2009 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 2010 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 2011 "SSE register cannot be used when SSE is disabled!"); 2012 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 2013 NoImplicitFloatOps) && 2014 "SSE register cannot be used when SSE is disabled!"); 2015 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 2016 !Subtarget->hasSSE1()) 2017 // Kernel mode asks for SSE to be disabled, so don't push them 2018 // on the stack. 2019 TotalNumXMMRegs = 0; 2020 2021 if (IsWin64) { 2022 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 2023 // Get to the caller-allocated home save location. Add 8 to account 2024 // for the return address. 2025 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 2026 FuncInfo->setRegSaveFrameIndex( 2027 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 2028 // Fixup to set vararg frame on shadow area (4 x i64). 2029 if (NumIntRegs < 4) 2030 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 2031 } else { 2032 // For X86-64, if there are vararg parameters that are passed via 2033 // registers, then we must store them to their spots on the stack so 2034 // they may be loaded by deferencing the result of va_next. 2035 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 2036 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 2037 FuncInfo->setRegSaveFrameIndex( 2038 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 2039 false)); 2040 } 2041 2042 // Store the integer parameter registers. 2043 SmallVector<SDValue, 8> MemOps; 2044 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2045 getPointerTy()); 2046 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2047 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2048 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2049 DAG.getIntPtrConstant(Offset)); 2050 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2051 &X86::GR64RegClass); 2052 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2053 SDValue Store = 2054 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2055 MachinePointerInfo::getFixedStack( 2056 FuncInfo->getRegSaveFrameIndex(), Offset), 2057 false, false, 0); 2058 MemOps.push_back(Store); 2059 Offset += 8; 2060 } 2061 2062 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2063 // Now store the XMM (fp + vector) parameter registers. 2064 SmallVector<SDValue, 11> SaveXMMOps; 2065 SaveXMMOps.push_back(Chain); 2066 2067 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2068 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2069 SaveXMMOps.push_back(ALVal); 2070 2071 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2072 FuncInfo->getRegSaveFrameIndex())); 2073 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2074 FuncInfo->getVarArgsFPOffset())); 2075 2076 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2077 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2078 &X86::VR128RegClass); 2079 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2080 SaveXMMOps.push_back(Val); 2081 } 2082 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2083 MVT::Other, 2084 &SaveXMMOps[0], SaveXMMOps.size())); 2085 } 2086 2087 if (!MemOps.empty()) 2088 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2089 &MemOps[0], MemOps.size()); 2090 } 2091 } 2092 2093 // Some CCs need callee pop. 2094 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2095 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2096 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2097 } else { 2098 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2099 // If this is an sret function, the return should pop the hidden pointer. 2100 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2101 argsAreStructReturn(Ins) == StackStructReturn) 2102 FuncInfo->setBytesToPopOnReturn(4); 2103 } 2104 2105 if (!Is64Bit) { 2106 // RegSaveFrameIndex is X86-64 only. 2107 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2108 if (CallConv == CallingConv::X86_FastCall || 2109 CallConv == CallingConv::X86_ThisCall) 2110 // fastcc functions can't have varargs. 2111 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2112 } 2113 2114 FuncInfo->setArgumentStackSize(StackSize); 2115 2116 return Chain; 2117} 2118 2119SDValue 2120X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2121 SDValue StackPtr, SDValue Arg, 2122 DebugLoc dl, SelectionDAG &DAG, 2123 const CCValAssign &VA, 2124 ISD::ArgFlagsTy Flags) const { 2125 unsigned LocMemOffset = VA.getLocMemOffset(); 2126 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2127 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2128 if (Flags.isByVal()) 2129 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2130 2131 return DAG.getStore(Chain, dl, Arg, PtrOff, 2132 MachinePointerInfo::getStack(LocMemOffset), 2133 false, false, 0); 2134} 2135 2136/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2137/// optimization is performed and it is required. 2138SDValue 2139X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2140 SDValue &OutRetAddr, SDValue Chain, 2141 bool IsTailCall, bool Is64Bit, 2142 int FPDiff, DebugLoc dl) const { 2143 // Adjust the Return address stack slot. 2144 EVT VT = getPointerTy(); 2145 OutRetAddr = getReturnAddressFrameIndex(DAG); 2146 2147 // Load the "old" Return address. 2148 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2149 false, false, false, 0); 2150 return SDValue(OutRetAddr.getNode(), 1); 2151} 2152 2153/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2154/// optimization is performed and it is required (FPDiff!=0). 2155static SDValue 2156EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2157 SDValue Chain, SDValue RetAddrFrIdx, 2158 bool Is64Bit, int FPDiff, DebugLoc dl) { 2159 // Store the return address to the appropriate stack slot. 2160 if (!FPDiff) return Chain; 2161 // Calculate the new stack slot for the return address. 2162 int SlotSize = Is64Bit ? 8 : 4; 2163 int NewReturnAddrFI = 2164 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2165 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2166 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2167 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2168 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2169 false, false, 0); 2170 return Chain; 2171} 2172 2173SDValue 2174X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2175 SmallVectorImpl<SDValue> &InVals) const { 2176 SelectionDAG &DAG = CLI.DAG; 2177 DebugLoc &dl = CLI.DL; 2178 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2179 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2180 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2181 SDValue Chain = CLI.Chain; 2182 SDValue Callee = CLI.Callee; 2183 CallingConv::ID CallConv = CLI.CallConv; 2184 bool &isTailCall = CLI.IsTailCall; 2185 bool isVarArg = CLI.IsVarArg; 2186 2187 MachineFunction &MF = DAG.getMachineFunction(); 2188 bool Is64Bit = Subtarget->is64Bit(); 2189 bool IsWin64 = Subtarget->isTargetWin64(); 2190 bool IsWindows = Subtarget->isTargetWindows(); 2191 StructReturnType SR = callIsStructReturn(Outs); 2192 bool IsSibcall = false; 2193 2194 if (MF.getTarget().Options.DisableTailCalls) 2195 isTailCall = false; 2196 2197 if (isTailCall) { 2198 // Check if it's really possible to do a tail call. 2199 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2200 isVarArg, SR != NotStructReturn, 2201 MF.getFunction()->hasStructRetAttr(), CLI.RetTy, 2202 Outs, OutVals, Ins, DAG); 2203 2204 // Sibcalls are automatically detected tailcalls which do not require 2205 // ABI changes. 2206 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2207 IsSibcall = true; 2208 2209 if (isTailCall) 2210 ++NumTailCalls; 2211 } 2212 2213 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2214 "Var args not supported with calling convention fastcc or ghc"); 2215 2216 // Analyze operands of the call, assigning locations to each operand. 2217 SmallVector<CCValAssign, 16> ArgLocs; 2218 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2219 ArgLocs, *DAG.getContext()); 2220 2221 // Allocate shadow area for Win64 2222 if (IsWin64) { 2223 CCInfo.AllocateStack(32, 8); 2224 } 2225 2226 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2227 2228 // Get a count of how many bytes are to be pushed on the stack. 2229 unsigned NumBytes = CCInfo.getNextStackOffset(); 2230 if (IsSibcall) 2231 // This is a sibcall. The memory operands are available in caller's 2232 // own caller's stack. 2233 NumBytes = 0; 2234 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2235 IsTailCallConvention(CallConv)) 2236 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2237 2238 int FPDiff = 0; 2239 if (isTailCall && !IsSibcall) { 2240 // Lower arguments at fp - stackoffset + fpdiff. 2241 unsigned NumBytesCallerPushed = 2242 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2243 FPDiff = NumBytesCallerPushed - NumBytes; 2244 2245 // Set the delta of movement of the returnaddr stackslot. 2246 // But only set if delta is greater than previous delta. 2247 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2248 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2249 } 2250 2251 if (!IsSibcall) 2252 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2253 2254 SDValue RetAddrFrIdx; 2255 // Load return address for tail calls. 2256 if (isTailCall && FPDiff) 2257 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2258 Is64Bit, FPDiff, dl); 2259 2260 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2261 SmallVector<SDValue, 8> MemOpChains; 2262 SDValue StackPtr; 2263 2264 // Walk the register/memloc assignments, inserting copies/loads. In the case 2265 // of tail call optimization arguments are handle later. 2266 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2267 CCValAssign &VA = ArgLocs[i]; 2268 EVT RegVT = VA.getLocVT(); 2269 SDValue Arg = OutVals[i]; 2270 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2271 bool isByVal = Flags.isByVal(); 2272 2273 // Promote the value if needed. 2274 switch (VA.getLocInfo()) { 2275 default: llvm_unreachable("Unknown loc info!"); 2276 case CCValAssign::Full: break; 2277 case CCValAssign::SExt: 2278 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2279 break; 2280 case CCValAssign::ZExt: 2281 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2282 break; 2283 case CCValAssign::AExt: 2284 if (RegVT.is128BitVector()) { 2285 // Special case: passing MMX values in XMM registers. 2286 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2287 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2288 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2289 } else 2290 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2291 break; 2292 case CCValAssign::BCvt: 2293 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2294 break; 2295 case CCValAssign::Indirect: { 2296 // Store the argument. 2297 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2298 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2299 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2300 MachinePointerInfo::getFixedStack(FI), 2301 false, false, 0); 2302 Arg = SpillSlot; 2303 break; 2304 } 2305 } 2306 2307 if (VA.isRegLoc()) { 2308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2309 if (isVarArg && IsWin64) { 2310 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2311 // shadow reg if callee is a varargs function. 2312 unsigned ShadowReg = 0; 2313 switch (VA.getLocReg()) { 2314 case X86::XMM0: ShadowReg = X86::RCX; break; 2315 case X86::XMM1: ShadowReg = X86::RDX; break; 2316 case X86::XMM2: ShadowReg = X86::R8; break; 2317 case X86::XMM3: ShadowReg = X86::R9; break; 2318 } 2319 if (ShadowReg) 2320 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2321 } 2322 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2323 assert(VA.isMemLoc()); 2324 if (StackPtr.getNode() == 0) 2325 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2326 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2327 dl, DAG, VA, Flags)); 2328 } 2329 } 2330 2331 if (!MemOpChains.empty()) 2332 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2333 &MemOpChains[0], MemOpChains.size()); 2334 2335 if (Subtarget->isPICStyleGOT()) { 2336 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2337 // GOT pointer. 2338 if (!isTailCall) { 2339 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX), 2340 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()))); 2341 } else { 2342 // If we are tail calling and generating PIC/GOT style code load the 2343 // address of the callee into ECX. The value in ecx is used as target of 2344 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2345 // for tail calls on PIC/GOT architectures. Normally we would just put the 2346 // address of GOT into ebx and then call target@PLT. But for tail calls 2347 // ebx would be restored (since ebx is callee saved) before jumping to the 2348 // target@PLT. 2349 2350 // Note: The actual moving to ECX is done further down. 2351 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2352 if (G && !G->getGlobal()->hasHiddenVisibility() && 2353 !G->getGlobal()->hasProtectedVisibility()) 2354 Callee = LowerGlobalAddress(Callee, DAG); 2355 else if (isa<ExternalSymbolSDNode>(Callee)) 2356 Callee = LowerExternalSymbol(Callee, DAG); 2357 } 2358 } 2359 2360 if (Is64Bit && isVarArg && !IsWin64) { 2361 // From AMD64 ABI document: 2362 // For calls that may call functions that use varargs or stdargs 2363 // (prototype-less calls or calls to functions containing ellipsis (...) in 2364 // the declaration) %al is used as hidden argument to specify the number 2365 // of SSE registers used. The contents of %al do not need to match exactly 2366 // the number of registers, but must be an ubound on the number of SSE 2367 // registers used and is in the range 0 - 8 inclusive. 2368 2369 // Count the number of XMM registers allocated. 2370 static const uint16_t XMMArgRegs[] = { 2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2372 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2373 }; 2374 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2375 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2376 && "SSE registers cannot be used when SSE is disabled"); 2377 2378 RegsToPass.push_back(std::make_pair(unsigned(X86::AL), 2379 DAG.getConstant(NumXMMRegs, MVT::i8))); 2380 } 2381 2382 // For tail calls lower the arguments to the 'real' stack slot. 2383 if (isTailCall) { 2384 // Force all the incoming stack arguments to be loaded from the stack 2385 // before any new outgoing arguments are stored to the stack, because the 2386 // outgoing stack slots may alias the incoming argument stack slots, and 2387 // the alias isn't otherwise explicit. This is slightly more conservative 2388 // than necessary, because it means that each store effectively depends 2389 // on every argument instead of just those arguments it would clobber. 2390 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2391 2392 SmallVector<SDValue, 8> MemOpChains2; 2393 SDValue FIN; 2394 int FI = 0; 2395 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2397 CCValAssign &VA = ArgLocs[i]; 2398 if (VA.isRegLoc()) 2399 continue; 2400 assert(VA.isMemLoc()); 2401 SDValue Arg = OutVals[i]; 2402 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2403 // Create frame index. 2404 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2405 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2406 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2407 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2408 2409 if (Flags.isByVal()) { 2410 // Copy relative to framepointer. 2411 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2412 if (StackPtr.getNode() == 0) 2413 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2414 getPointerTy()); 2415 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2416 2417 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2418 ArgChain, 2419 Flags, DAG, dl)); 2420 } else { 2421 // Store relative to framepointer. 2422 MemOpChains2.push_back( 2423 DAG.getStore(ArgChain, dl, Arg, FIN, 2424 MachinePointerInfo::getFixedStack(FI), 2425 false, false, 0)); 2426 } 2427 } 2428 } 2429 2430 if (!MemOpChains2.empty()) 2431 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2432 &MemOpChains2[0], MemOpChains2.size()); 2433 2434 // Store the return address to the appropriate stack slot. 2435 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2436 FPDiff, dl); 2437 } 2438 2439 // Build a sequence of copy-to-reg nodes chained together with token chain 2440 // and flag operands which copy the outgoing args into registers. 2441 SDValue InFlag; 2442 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2443 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2444 RegsToPass[i].second, InFlag); 2445 InFlag = Chain.getValue(1); 2446 } 2447 2448 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2449 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2450 // In the 64-bit large code model, we have to make all calls 2451 // through a register, since the call instruction's 32-bit 2452 // pc-relative offset may not be large enough to hold the whole 2453 // address. 2454 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2455 // If the callee is a GlobalAddress node (quite common, every direct call 2456 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2457 // it. 2458 2459 // We should use extra load for direct calls to dllimported functions in 2460 // non-JIT mode. 2461 const GlobalValue *GV = G->getGlobal(); 2462 if (!GV->hasDLLImportLinkage()) { 2463 unsigned char OpFlags = 0; 2464 bool ExtraLoad = false; 2465 unsigned WrapperKind = ISD::DELETED_NODE; 2466 2467 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2468 // external symbols most go through the PLT in PIC mode. If the symbol 2469 // has hidden or protected visibility, or if it is static or local, then 2470 // we don't need to use the PLT - we can directly call it. 2471 if (Subtarget->isTargetELF() && 2472 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2473 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2474 OpFlags = X86II::MO_PLT; 2475 } else if (Subtarget->isPICStyleStubAny() && 2476 (GV->isDeclaration() || GV->isWeakForLinker()) && 2477 (!Subtarget->getTargetTriple().isMacOSX() || 2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2479 // PC-relative references to external symbols should go through $stub, 2480 // unless we're building with the leopard linker or later, which 2481 // automatically synthesizes these stubs. 2482 OpFlags = X86II::MO_DARWIN_STUB; 2483 } else if (Subtarget->isPICStyleRIPRel() && 2484 isa<Function>(GV) && 2485 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2486 // If the function is marked as non-lazy, generate an indirect call 2487 // which loads from the GOT directly. This avoids runtime overhead 2488 // at the cost of eager binding (and one extra byte of encoding). 2489 OpFlags = X86II::MO_GOTPCREL; 2490 WrapperKind = X86ISD::WrapperRIP; 2491 ExtraLoad = true; 2492 } 2493 2494 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2495 G->getOffset(), OpFlags); 2496 2497 // Add a wrapper if needed. 2498 if (WrapperKind != ISD::DELETED_NODE) 2499 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2500 // Add extra indirection if needed. 2501 if (ExtraLoad) 2502 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2503 MachinePointerInfo::getGOT(), 2504 false, false, false, 0); 2505 } 2506 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2507 unsigned char OpFlags = 0; 2508 2509 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2510 // external symbols should go through the PLT. 2511 if (Subtarget->isTargetELF() && 2512 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2513 OpFlags = X86II::MO_PLT; 2514 } else if (Subtarget->isPICStyleStubAny() && 2515 (!Subtarget->getTargetTriple().isMacOSX() || 2516 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2517 // PC-relative references to external symbols should go through $stub, 2518 // unless we're building with the leopard linker or later, which 2519 // automatically synthesizes these stubs. 2520 OpFlags = X86II::MO_DARWIN_STUB; 2521 } 2522 2523 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2524 OpFlags); 2525 } 2526 2527 // Returns a chain & a flag for retval copy to use. 2528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2529 SmallVector<SDValue, 8> Ops; 2530 2531 if (!IsSibcall && isTailCall) { 2532 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2533 DAG.getIntPtrConstant(0, true), InFlag); 2534 InFlag = Chain.getValue(1); 2535 } 2536 2537 Ops.push_back(Chain); 2538 Ops.push_back(Callee); 2539 2540 if (isTailCall) 2541 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2542 2543 // Add argument registers to the end of the list so that they are known live 2544 // into the call. 2545 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2546 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2547 RegsToPass[i].second.getValueType())); 2548 2549 // Add a register mask operand representing the call-preserved registers. 2550 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2551 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2552 assert(Mask && "Missing call preserved mask for calling convention"); 2553 Ops.push_back(DAG.getRegisterMask(Mask)); 2554 2555 if (InFlag.getNode()) 2556 Ops.push_back(InFlag); 2557 2558 if (isTailCall) { 2559 // We used to do: 2560 //// If this is the first return lowered for this function, add the regs 2561 //// to the liveout set for the function. 2562 // This isn't right, although it's probably harmless on x86; liveouts 2563 // should be computed from returns not tail calls. Consider a void 2564 // function making a tail call to a function returning int. 2565 return DAG.getNode(X86ISD::TC_RETURN, dl, 2566 NodeTys, &Ops[0], Ops.size()); 2567 } 2568 2569 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2570 InFlag = Chain.getValue(1); 2571 2572 // Create the CALLSEQ_END node. 2573 unsigned NumBytesForCalleeToPush; 2574 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2575 getTargetMachine().Options.GuaranteedTailCallOpt)) 2576 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2577 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2578 SR == StackStructReturn) 2579 // If this is a call to a struct-return function, the callee 2580 // pops the hidden struct pointer, so we have to push it back. 2581 // This is common for Darwin/X86, Linux & Mingw32 targets. 2582 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2583 NumBytesForCalleeToPush = 4; 2584 else 2585 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2586 2587 // Returns a flag for retval copy to use. 2588 if (!IsSibcall) { 2589 Chain = DAG.getCALLSEQ_END(Chain, 2590 DAG.getIntPtrConstant(NumBytes, true), 2591 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2592 true), 2593 InFlag); 2594 InFlag = Chain.getValue(1); 2595 } 2596 2597 // Handle result values, copying them out of physregs into vregs that we 2598 // return. 2599 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2600 Ins, dl, DAG, InVals); 2601} 2602 2603 2604//===----------------------------------------------------------------------===// 2605// Fast Calling Convention (tail call) implementation 2606//===----------------------------------------------------------------------===// 2607 2608// Like std call, callee cleans arguments, convention except that ECX is 2609// reserved for storing the tail called function address. Only 2 registers are 2610// free for argument passing (inreg). Tail call optimization is performed 2611// provided: 2612// * tailcallopt is enabled 2613// * caller/callee are fastcc 2614// On X86_64 architecture with GOT-style position independent code only local 2615// (within module) calls are supported at the moment. 2616// To keep the stack aligned according to platform abi the function 2617// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2618// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2619// If a tail called function callee has more arguments than the caller the 2620// caller needs to make sure that there is room to move the RETADDR to. This is 2621// achieved by reserving an area the size of the argument delta right after the 2622// original REtADDR, but before the saved framepointer or the spilled registers 2623// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2624// stack layout: 2625// arg1 2626// arg2 2627// RETADDR 2628// [ new RETADDR 2629// move area ] 2630// (possible EBP) 2631// ESI 2632// EDI 2633// local1 .. 2634 2635/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2636/// for a 16 byte align requirement. 2637unsigned 2638X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2639 SelectionDAG& DAG) const { 2640 MachineFunction &MF = DAG.getMachineFunction(); 2641 const TargetMachine &TM = MF.getTarget(); 2642 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2643 unsigned StackAlignment = TFI.getStackAlignment(); 2644 uint64_t AlignMask = StackAlignment - 1; 2645 int64_t Offset = StackSize; 2646 uint64_t SlotSize = TD->getPointerSize(); 2647 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2648 // Number smaller than 12 so just add the difference. 2649 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2650 } else { 2651 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2652 Offset = ((~AlignMask) & Offset) + StackAlignment + 2653 (StackAlignment-SlotSize); 2654 } 2655 return Offset; 2656} 2657 2658/// MatchingStackOffset - Return true if the given stack call argument is 2659/// already available in the same position (relatively) of the caller's 2660/// incoming argument stack. 2661static 2662bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2663 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2664 const X86InstrInfo *TII) { 2665 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2666 int FI = INT_MAX; 2667 if (Arg.getOpcode() == ISD::CopyFromReg) { 2668 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2669 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2670 return false; 2671 MachineInstr *Def = MRI->getVRegDef(VR); 2672 if (!Def) 2673 return false; 2674 if (!Flags.isByVal()) { 2675 if (!TII->isLoadFromStackSlot(Def, FI)) 2676 return false; 2677 } else { 2678 unsigned Opcode = Def->getOpcode(); 2679 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2680 Def->getOperand(1).isFI()) { 2681 FI = Def->getOperand(1).getIndex(); 2682 Bytes = Flags.getByValSize(); 2683 } else 2684 return false; 2685 } 2686 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2687 if (Flags.isByVal()) 2688 // ByVal argument is passed in as a pointer but it's now being 2689 // dereferenced. e.g. 2690 // define @foo(%struct.X* %A) { 2691 // tail call @bar(%struct.X* byval %A) 2692 // } 2693 return false; 2694 SDValue Ptr = Ld->getBasePtr(); 2695 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2696 if (!FINode) 2697 return false; 2698 FI = FINode->getIndex(); 2699 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2700 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2701 FI = FINode->getIndex(); 2702 Bytes = Flags.getByValSize(); 2703 } else 2704 return false; 2705 2706 assert(FI != INT_MAX); 2707 if (!MFI->isFixedObjectIndex(FI)) 2708 return false; 2709 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2710} 2711 2712/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2713/// for tail call optimization. Targets which want to do tail call 2714/// optimization should implement this function. 2715bool 2716X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2717 CallingConv::ID CalleeCC, 2718 bool isVarArg, 2719 bool isCalleeStructRet, 2720 bool isCallerStructRet, 2721 Type *RetTy, 2722 const SmallVectorImpl<ISD::OutputArg> &Outs, 2723 const SmallVectorImpl<SDValue> &OutVals, 2724 const SmallVectorImpl<ISD::InputArg> &Ins, 2725 SelectionDAG& DAG) const { 2726 if (!IsTailCallConvention(CalleeCC) && 2727 CalleeCC != CallingConv::C) 2728 return false; 2729 2730 // If -tailcallopt is specified, make fastcc functions tail-callable. 2731 const MachineFunction &MF = DAG.getMachineFunction(); 2732 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2733 2734 // If the function return type is x86_fp80 and the callee return type is not, 2735 // then the FP_EXTEND of the call result is not a nop. It's not safe to 2736 // perform a tailcall optimization here. 2737 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty()) 2738 return false; 2739 2740 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2741 bool CCMatch = CallerCC == CalleeCC; 2742 2743 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2744 if (IsTailCallConvention(CalleeCC) && CCMatch) 2745 return true; 2746 return false; 2747 } 2748 2749 // Look for obvious safe cases to perform tail call optimization that do not 2750 // require ABI changes. This is what gcc calls sibcall. 2751 2752 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2753 // emit a special epilogue. 2754 if (RegInfo->needsStackRealignment(MF)) 2755 return false; 2756 2757 // Also avoid sibcall optimization if either caller or callee uses struct 2758 // return semantics. 2759 if (isCalleeStructRet || isCallerStructRet) 2760 return false; 2761 2762 // An stdcall caller is expected to clean up its arguments; the callee 2763 // isn't going to do that. 2764 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2765 return false; 2766 2767 // Do not sibcall optimize vararg calls unless all arguments are passed via 2768 // registers. 2769 if (isVarArg && !Outs.empty()) { 2770 2771 // Optimizing for varargs on Win64 is unlikely to be safe without 2772 // additional testing. 2773 if (Subtarget->isTargetWin64()) 2774 return false; 2775 2776 SmallVector<CCValAssign, 16> ArgLocs; 2777 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2778 getTargetMachine(), ArgLocs, *DAG.getContext()); 2779 2780 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2781 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2782 if (!ArgLocs[i].isRegLoc()) 2783 return false; 2784 } 2785 2786 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2787 // stack. Therefore, if it's not used by the call it is not safe to optimize 2788 // this into a sibcall. 2789 bool Unused = false; 2790 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2791 if (!Ins[i].Used) { 2792 Unused = true; 2793 break; 2794 } 2795 } 2796 if (Unused) { 2797 SmallVector<CCValAssign, 16> RVLocs; 2798 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2799 getTargetMachine(), RVLocs, *DAG.getContext()); 2800 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2801 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2802 CCValAssign &VA = RVLocs[i]; 2803 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2804 return false; 2805 } 2806 } 2807 2808 // If the calling conventions do not match, then we'd better make sure the 2809 // results are returned in the same way as what the caller expects. 2810 if (!CCMatch) { 2811 SmallVector<CCValAssign, 16> RVLocs1; 2812 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2813 getTargetMachine(), RVLocs1, *DAG.getContext()); 2814 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2815 2816 SmallVector<CCValAssign, 16> RVLocs2; 2817 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2818 getTargetMachine(), RVLocs2, *DAG.getContext()); 2819 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2820 2821 if (RVLocs1.size() != RVLocs2.size()) 2822 return false; 2823 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2824 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2825 return false; 2826 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2827 return false; 2828 if (RVLocs1[i].isRegLoc()) { 2829 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2830 return false; 2831 } else { 2832 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2833 return false; 2834 } 2835 } 2836 } 2837 2838 // If the callee takes no arguments then go on to check the results of the 2839 // call. 2840 if (!Outs.empty()) { 2841 // Check if stack adjustment is needed. For now, do not do this if any 2842 // argument is passed on the stack. 2843 SmallVector<CCValAssign, 16> ArgLocs; 2844 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2845 getTargetMachine(), ArgLocs, *DAG.getContext()); 2846 2847 // Allocate shadow area for Win64 2848 if (Subtarget->isTargetWin64()) { 2849 CCInfo.AllocateStack(32, 8); 2850 } 2851 2852 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2853 if (CCInfo.getNextStackOffset()) { 2854 MachineFunction &MF = DAG.getMachineFunction(); 2855 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2856 return false; 2857 2858 // Check if the arguments are already laid out in the right way as 2859 // the caller's fixed stack objects. 2860 MachineFrameInfo *MFI = MF.getFrameInfo(); 2861 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2862 const X86InstrInfo *TII = 2863 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2864 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2865 CCValAssign &VA = ArgLocs[i]; 2866 SDValue Arg = OutVals[i]; 2867 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2868 if (VA.getLocInfo() == CCValAssign::Indirect) 2869 return false; 2870 if (!VA.isRegLoc()) { 2871 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2872 MFI, MRI, TII)) 2873 return false; 2874 } 2875 } 2876 } 2877 2878 // If the tailcall address may be in a register, then make sure it's 2879 // possible to register allocate for it. In 32-bit, the call address can 2880 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2881 // callee-saved registers are restored. These happen to be the same 2882 // registers used to pass 'inreg' arguments so watch out for those. 2883 if (!Subtarget->is64Bit() && 2884 !isa<GlobalAddressSDNode>(Callee) && 2885 !isa<ExternalSymbolSDNode>(Callee)) { 2886 unsigned NumInRegs = 0; 2887 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2888 CCValAssign &VA = ArgLocs[i]; 2889 if (!VA.isRegLoc()) 2890 continue; 2891 unsigned Reg = VA.getLocReg(); 2892 switch (Reg) { 2893 default: break; 2894 case X86::EAX: case X86::EDX: case X86::ECX: 2895 if (++NumInRegs == 3) 2896 return false; 2897 break; 2898 } 2899 } 2900 } 2901 } 2902 2903 return true; 2904} 2905 2906FastISel * 2907X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 2908 const TargetLibraryInfo *libInfo) const { 2909 return X86::createFastISel(funcInfo, libInfo); 2910} 2911 2912 2913//===----------------------------------------------------------------------===// 2914// Other Lowering Hooks 2915//===----------------------------------------------------------------------===// 2916 2917static bool MayFoldLoad(SDValue Op) { 2918 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2919} 2920 2921static bool MayFoldIntoStore(SDValue Op) { 2922 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2923} 2924 2925static bool isTargetShuffle(unsigned Opcode) { 2926 switch(Opcode) { 2927 default: return false; 2928 case X86ISD::PSHUFD: 2929 case X86ISD::PSHUFHW: 2930 case X86ISD::PSHUFLW: 2931 case X86ISD::SHUFP: 2932 case X86ISD::PALIGN: 2933 case X86ISD::MOVLHPS: 2934 case X86ISD::MOVLHPD: 2935 case X86ISD::MOVHLPS: 2936 case X86ISD::MOVLPS: 2937 case X86ISD::MOVLPD: 2938 case X86ISD::MOVSHDUP: 2939 case X86ISD::MOVSLDUP: 2940 case X86ISD::MOVDDUP: 2941 case X86ISD::MOVSS: 2942 case X86ISD::MOVSD: 2943 case X86ISD::UNPCKL: 2944 case X86ISD::UNPCKH: 2945 case X86ISD::VPERMILP: 2946 case X86ISD::VPERM2X128: 2947 case X86ISD::VPERMI: 2948 return true; 2949 } 2950} 2951 2952static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2953 SDValue V1, SelectionDAG &DAG) { 2954 switch(Opc) { 2955 default: llvm_unreachable("Unknown x86 shuffle node"); 2956 case X86ISD::MOVSHDUP: 2957 case X86ISD::MOVSLDUP: 2958 case X86ISD::MOVDDUP: 2959 return DAG.getNode(Opc, dl, VT, V1); 2960 } 2961} 2962 2963static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2964 SDValue V1, unsigned TargetMask, 2965 SelectionDAG &DAG) { 2966 switch(Opc) { 2967 default: llvm_unreachable("Unknown x86 shuffle node"); 2968 case X86ISD::PSHUFD: 2969 case X86ISD::PSHUFHW: 2970 case X86ISD::PSHUFLW: 2971 case X86ISD::VPERMILP: 2972 case X86ISD::VPERMI: 2973 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2974 } 2975} 2976 2977static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2978 SDValue V1, SDValue V2, unsigned TargetMask, 2979 SelectionDAG &DAG) { 2980 switch(Opc) { 2981 default: llvm_unreachable("Unknown x86 shuffle node"); 2982 case X86ISD::PALIGN: 2983 case X86ISD::SHUFP: 2984 case X86ISD::VPERM2X128: 2985 return DAG.getNode(Opc, dl, VT, V1, V2, 2986 DAG.getConstant(TargetMask, MVT::i8)); 2987 } 2988} 2989 2990static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2991 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2992 switch(Opc) { 2993 default: llvm_unreachable("Unknown x86 shuffle node"); 2994 case X86ISD::MOVLHPS: 2995 case X86ISD::MOVLHPD: 2996 case X86ISD::MOVHLPS: 2997 case X86ISD::MOVLPS: 2998 case X86ISD::MOVLPD: 2999 case X86ISD::MOVSS: 3000 case X86ISD::MOVSD: 3001 case X86ISD::UNPCKL: 3002 case X86ISD::UNPCKH: 3003 return DAG.getNode(Opc, dl, VT, V1, V2); 3004 } 3005} 3006 3007SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 3008 MachineFunction &MF = DAG.getMachineFunction(); 3009 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 3010 int ReturnAddrIndex = FuncInfo->getRAIndex(); 3011 3012 if (ReturnAddrIndex == 0) { 3013 // Set up a frame object for the return address. 3014 uint64_t SlotSize = TD->getPointerSize(); 3015 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 3016 false); 3017 FuncInfo->setRAIndex(ReturnAddrIndex); 3018 } 3019 3020 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 3021} 3022 3023 3024bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 3025 bool hasSymbolicDisplacement) { 3026 // Offset should fit into 32 bit immediate field. 3027 if (!isInt<32>(Offset)) 3028 return false; 3029 3030 // If we don't have a symbolic displacement - we don't have any extra 3031 // restrictions. 3032 if (!hasSymbolicDisplacement) 3033 return true; 3034 3035 // FIXME: Some tweaks might be needed for medium code model. 3036 if (M != CodeModel::Small && M != CodeModel::Kernel) 3037 return false; 3038 3039 // For small code model we assume that latest object is 16MB before end of 31 3040 // bits boundary. We may also accept pretty large negative constants knowing 3041 // that all objects are in the positive half of address space. 3042 if (M == CodeModel::Small && Offset < 16*1024*1024) 3043 return true; 3044 3045 // For kernel code model we know that all object resist in the negative half 3046 // of 32bits address space. We may not accept negative offsets, since they may 3047 // be just off and we may accept pretty large positive ones. 3048 if (M == CodeModel::Kernel && Offset > 0) 3049 return true; 3050 3051 return false; 3052} 3053 3054/// isCalleePop - Determines whether the callee is required to pop its 3055/// own arguments. Callee pop is necessary to support tail calls. 3056bool X86::isCalleePop(CallingConv::ID CallingConv, 3057 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3058 if (IsVarArg) 3059 return false; 3060 3061 switch (CallingConv) { 3062 default: 3063 return false; 3064 case CallingConv::X86_StdCall: 3065 return !is64Bit; 3066 case CallingConv::X86_FastCall: 3067 return !is64Bit; 3068 case CallingConv::X86_ThisCall: 3069 return !is64Bit; 3070 case CallingConv::Fast: 3071 return TailCallOpt; 3072 case CallingConv::GHC: 3073 return TailCallOpt; 3074 } 3075} 3076 3077/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3078/// specific condition code, returning the condition code and the LHS/RHS of the 3079/// comparison to make. 3080static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3081 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3082 if (!isFP) { 3083 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3084 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3085 // X > -1 -> X == 0, jump !sign. 3086 RHS = DAG.getConstant(0, RHS.getValueType()); 3087 return X86::COND_NS; 3088 } 3089 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3090 // X < 0 -> X == 0, jump on sign. 3091 return X86::COND_S; 3092 } 3093 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3094 // X < 1 -> X <= 0 3095 RHS = DAG.getConstant(0, RHS.getValueType()); 3096 return X86::COND_LE; 3097 } 3098 } 3099 3100 switch (SetCCOpcode) { 3101 default: llvm_unreachable("Invalid integer condition!"); 3102 case ISD::SETEQ: return X86::COND_E; 3103 case ISD::SETGT: return X86::COND_G; 3104 case ISD::SETGE: return X86::COND_GE; 3105 case ISD::SETLT: return X86::COND_L; 3106 case ISD::SETLE: return X86::COND_LE; 3107 case ISD::SETNE: return X86::COND_NE; 3108 case ISD::SETULT: return X86::COND_B; 3109 case ISD::SETUGT: return X86::COND_A; 3110 case ISD::SETULE: return X86::COND_BE; 3111 case ISD::SETUGE: return X86::COND_AE; 3112 } 3113 } 3114 3115 // First determine if it is required or is profitable to flip the operands. 3116 3117 // If LHS is a foldable load, but RHS is not, flip the condition. 3118 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3119 !ISD::isNON_EXTLoad(RHS.getNode())) { 3120 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3121 std::swap(LHS, RHS); 3122 } 3123 3124 switch (SetCCOpcode) { 3125 default: break; 3126 case ISD::SETOLT: 3127 case ISD::SETOLE: 3128 case ISD::SETUGT: 3129 case ISD::SETUGE: 3130 std::swap(LHS, RHS); 3131 break; 3132 } 3133 3134 // On a floating point condition, the flags are set as follows: 3135 // ZF PF CF op 3136 // 0 | 0 | 0 | X > Y 3137 // 0 | 0 | 1 | X < Y 3138 // 1 | 0 | 0 | X == Y 3139 // 1 | 1 | 1 | unordered 3140 switch (SetCCOpcode) { 3141 default: llvm_unreachable("Condcode should be pre-legalized away"); 3142 case ISD::SETUEQ: 3143 case ISD::SETEQ: return X86::COND_E; 3144 case ISD::SETOLT: // flipped 3145 case ISD::SETOGT: 3146 case ISD::SETGT: return X86::COND_A; 3147 case ISD::SETOLE: // flipped 3148 case ISD::SETOGE: 3149 case ISD::SETGE: return X86::COND_AE; 3150 case ISD::SETUGT: // flipped 3151 case ISD::SETULT: 3152 case ISD::SETLT: return X86::COND_B; 3153 case ISD::SETUGE: // flipped 3154 case ISD::SETULE: 3155 case ISD::SETLE: return X86::COND_BE; 3156 case ISD::SETONE: 3157 case ISD::SETNE: return X86::COND_NE; 3158 case ISD::SETUO: return X86::COND_P; 3159 case ISD::SETO: return X86::COND_NP; 3160 case ISD::SETOEQ: 3161 case ISD::SETUNE: return X86::COND_INVALID; 3162 } 3163} 3164 3165/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3166/// code. Current x86 isa includes the following FP cmov instructions: 3167/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3168static bool hasFPCMov(unsigned X86CC) { 3169 switch (X86CC) { 3170 default: 3171 return false; 3172 case X86::COND_B: 3173 case X86::COND_BE: 3174 case X86::COND_E: 3175 case X86::COND_P: 3176 case X86::COND_A: 3177 case X86::COND_AE: 3178 case X86::COND_NE: 3179 case X86::COND_NP: 3180 return true; 3181 } 3182} 3183 3184/// isFPImmLegal - Returns true if the target can instruction select the 3185/// specified FP immediate natively. If false, the legalizer will 3186/// materialize the FP immediate as a load from a constant pool. 3187bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3188 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3189 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3190 return true; 3191 } 3192 return false; 3193} 3194 3195/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3196/// the specified range (L, H]. 3197static bool isUndefOrInRange(int Val, int Low, int Hi) { 3198 return (Val < 0) || (Val >= Low && Val < Hi); 3199} 3200 3201/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3202/// specified value. 3203static bool isUndefOrEqual(int Val, int CmpVal) { 3204 if (Val < 0 || Val == CmpVal) 3205 return true; 3206 return false; 3207} 3208 3209/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning 3210/// from position Pos and ending in Pos+Size, falls within the specified 3211/// sequential range (L, L+Pos]. or is undef. 3212static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3213 unsigned Pos, unsigned Size, int Low) { 3214 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3215 if (!isUndefOrEqual(Mask[i], Low)) 3216 return false; 3217 return true; 3218} 3219 3220/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3221/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3222/// the second operand. 3223static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3224 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3225 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3226 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3227 return (Mask[0] < 2 && Mask[1] < 2); 3228 return false; 3229} 3230 3231/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3232/// is suitable for input to PSHUFHW. 3233static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3234 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3235 return false; 3236 3237 // Lower quadword copied in order or undef. 3238 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3239 return false; 3240 3241 // Upper quadword shuffled. 3242 for (unsigned i = 4; i != 8; ++i) 3243 if (!isUndefOrInRange(Mask[i], 4, 8)) 3244 return false; 3245 3246 if (VT == MVT::v16i16) { 3247 // Lower quadword copied in order or undef. 3248 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3249 return false; 3250 3251 // Upper quadword shuffled. 3252 for (unsigned i = 12; i != 16; ++i) 3253 if (!isUndefOrInRange(Mask[i], 12, 16)) 3254 return false; 3255 } 3256 3257 return true; 3258} 3259 3260/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3261/// is suitable for input to PSHUFLW. 3262static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3263 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3264 return false; 3265 3266 // Upper quadword copied in order. 3267 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3268 return false; 3269 3270 // Lower quadword shuffled. 3271 for (unsigned i = 0; i != 4; ++i) 3272 if (!isUndefOrInRange(Mask[i], 0, 4)) 3273 return false; 3274 3275 if (VT == MVT::v16i16) { 3276 // Upper quadword copied in order. 3277 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3278 return false; 3279 3280 // Lower quadword shuffled. 3281 for (unsigned i = 8; i != 12; ++i) 3282 if (!isUndefOrInRange(Mask[i], 8, 12)) 3283 return false; 3284 } 3285 3286 return true; 3287} 3288 3289/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3290/// is suitable for input to PALIGNR. 3291static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3292 const X86Subtarget *Subtarget) { 3293 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3294 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3295 return false; 3296 3297 unsigned NumElts = VT.getVectorNumElements(); 3298 unsigned NumLanes = VT.getSizeInBits()/128; 3299 unsigned NumLaneElts = NumElts/NumLanes; 3300 3301 // Do not handle 64-bit element shuffles with palignr. 3302 if (NumLaneElts == 2) 3303 return false; 3304 3305 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3306 unsigned i; 3307 for (i = 0; i != NumLaneElts; ++i) { 3308 if (Mask[i+l] >= 0) 3309 break; 3310 } 3311 3312 // Lane is all undef, go to next lane 3313 if (i == NumLaneElts) 3314 continue; 3315 3316 int Start = Mask[i+l]; 3317 3318 // Make sure its in this lane in one of the sources 3319 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3320 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3321 return false; 3322 3323 // If not lane 0, then we must match lane 0 3324 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3325 return false; 3326 3327 // Correct second source to be contiguous with first source 3328 if (Start >= (int)NumElts) 3329 Start -= NumElts - NumLaneElts; 3330 3331 // Make sure we're shifting in the right direction. 3332 if (Start <= (int)(i+l)) 3333 return false; 3334 3335 Start -= i; 3336 3337 // Check the rest of the elements to see if they are consecutive. 3338 for (++i; i != NumLaneElts; ++i) { 3339 int Idx = Mask[i+l]; 3340 3341 // Make sure its in this lane 3342 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3343 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3344 return false; 3345 3346 // If not lane 0, then we must match lane 0 3347 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3348 return false; 3349 3350 if (Idx >= (int)NumElts) 3351 Idx -= NumElts - NumLaneElts; 3352 3353 if (!isUndefOrEqual(Idx, Start+i)) 3354 return false; 3355 3356 } 3357 } 3358 3359 return true; 3360} 3361 3362/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3363/// the two vector operands have swapped position. 3364static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3365 unsigned NumElems) { 3366 for (unsigned i = 0; i != NumElems; ++i) { 3367 int idx = Mask[i]; 3368 if (idx < 0) 3369 continue; 3370 else if (idx < (int)NumElems) 3371 Mask[i] = idx + NumElems; 3372 else 3373 Mask[i] = idx - NumElems; 3374 } 3375} 3376 3377/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3378/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3379/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3380/// reverse of what x86 shuffles want. 3381static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3382 bool Commuted = false) { 3383 if (!HasAVX && VT.getSizeInBits() == 256) 3384 return false; 3385 3386 unsigned NumElems = VT.getVectorNumElements(); 3387 unsigned NumLanes = VT.getSizeInBits()/128; 3388 unsigned NumLaneElems = NumElems/NumLanes; 3389 3390 if (NumLaneElems != 2 && NumLaneElems != 4) 3391 return false; 3392 3393 // VSHUFPSY divides the resulting vector into 4 chunks. 3394 // The sources are also splitted into 4 chunks, and each destination 3395 // chunk must come from a different source chunk. 3396 // 3397 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3398 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3399 // 3400 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3401 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3402 // 3403 // VSHUFPDY divides the resulting vector into 4 chunks. 3404 // The sources are also splitted into 4 chunks, and each destination 3405 // chunk must come from a different source chunk. 3406 // 3407 // SRC1 => X3 X2 X1 X0 3408 // SRC2 => Y3 Y2 Y1 Y0 3409 // 3410 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3411 // 3412 unsigned HalfLaneElems = NumLaneElems/2; 3413 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3414 for (unsigned i = 0; i != NumLaneElems; ++i) { 3415 int Idx = Mask[i+l]; 3416 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3417 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3418 return false; 3419 // For VSHUFPSY, the mask of the second half must be the same as the 3420 // first but with the appropriate offsets. This works in the same way as 3421 // VPERMILPS works with masks. 3422 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3423 continue; 3424 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3425 return false; 3426 } 3427 } 3428 3429 return true; 3430} 3431 3432/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3433/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3434static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3435 if (!VT.is128BitVector()) 3436 return false; 3437 3438 unsigned NumElems = VT.getVectorNumElements(); 3439 3440 if (NumElems != 4) 3441 return false; 3442 3443 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3444 return isUndefOrEqual(Mask[0], 6) && 3445 isUndefOrEqual(Mask[1], 7) && 3446 isUndefOrEqual(Mask[2], 2) && 3447 isUndefOrEqual(Mask[3], 3); 3448} 3449 3450/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3451/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3452/// <2, 3, 2, 3> 3453static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3454 if (!VT.is128BitVector()) 3455 return false; 3456 3457 unsigned NumElems = VT.getVectorNumElements(); 3458 3459 if (NumElems != 4) 3460 return false; 3461 3462 return isUndefOrEqual(Mask[0], 2) && 3463 isUndefOrEqual(Mask[1], 3) && 3464 isUndefOrEqual(Mask[2], 2) && 3465 isUndefOrEqual(Mask[3], 3); 3466} 3467 3468/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3469/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3470static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3471 if (!VT.is128BitVector()) 3472 return false; 3473 3474 unsigned NumElems = VT.getVectorNumElements(); 3475 3476 if (NumElems != 2 && NumElems != 4) 3477 return false; 3478 3479 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3480 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3481 return false; 3482 3483 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3484 if (!isUndefOrEqual(Mask[i], i)) 3485 return false; 3486 3487 return true; 3488} 3489 3490/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3491/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3492static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3493 if (!VT.is128BitVector()) 3494 return false; 3495 3496 unsigned NumElems = VT.getVectorNumElements(); 3497 3498 if (NumElems != 2 && NumElems != 4) 3499 return false; 3500 3501 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3502 if (!isUndefOrEqual(Mask[i], i)) 3503 return false; 3504 3505 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3506 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3507 return false; 3508 3509 return true; 3510} 3511 3512// 3513// Some special combinations that can be optimized. 3514// 3515static 3516SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, 3517 SelectionDAG &DAG) { 3518 EVT VT = SVOp->getValueType(0); 3519 DebugLoc dl = SVOp->getDebugLoc(); 3520 3521 if (VT != MVT::v8i32 && VT != MVT::v8f32) 3522 return SDValue(); 3523 3524 ArrayRef<int> Mask = SVOp->getMask(); 3525 3526 // These are the special masks that may be optimized. 3527 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14}; 3528 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15}; 3529 bool MatchEvenMask = true; 3530 bool MatchOddMask = true; 3531 for (int i=0; i<8; ++i) { 3532 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) 3533 MatchEvenMask = false; 3534 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) 3535 MatchOddMask = false; 3536 } 3537 3538 if (!MatchEvenMask && !MatchOddMask) 3539 return SDValue(); 3540 3541 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT); 3542 3543 SDValue Op0 = SVOp->getOperand(0); 3544 SDValue Op1 = SVOp->getOperand(1); 3545 3546 if (MatchEvenMask) { 3547 // Shift the second operand right to 32 bits. 3548 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 }; 3549 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask); 3550 } else { 3551 // Shift the first operand left to 32 bits. 3552 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 }; 3553 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask); 3554 } 3555 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15}; 3556 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask); 3557} 3558 3559/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3560/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3561static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3562 bool HasAVX2, bool V2IsSplat = false) { 3563 unsigned NumElts = VT.getVectorNumElements(); 3564 3565 assert((VT.is128BitVector() || VT.is256BitVector()) && 3566 "Unsupported vector type for unpckh"); 3567 3568 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3569 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3570 return false; 3571 3572 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3573 // independently on 128-bit lanes. 3574 unsigned NumLanes = VT.getSizeInBits()/128; 3575 unsigned NumLaneElts = NumElts/NumLanes; 3576 3577 for (unsigned l = 0; l != NumLanes; ++l) { 3578 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3579 i != (l+1)*NumLaneElts; 3580 i += 2, ++j) { 3581 int BitI = Mask[i]; 3582 int BitI1 = Mask[i+1]; 3583 if (!isUndefOrEqual(BitI, j)) 3584 return false; 3585 if (V2IsSplat) { 3586 if (!isUndefOrEqual(BitI1, NumElts)) 3587 return false; 3588 } else { 3589 if (!isUndefOrEqual(BitI1, j + NumElts)) 3590 return false; 3591 } 3592 } 3593 } 3594 3595 return true; 3596} 3597 3598/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3599/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3600static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3601 bool HasAVX2, bool V2IsSplat = false) { 3602 unsigned NumElts = VT.getVectorNumElements(); 3603 3604 assert((VT.is128BitVector() || VT.is256BitVector()) && 3605 "Unsupported vector type for unpckh"); 3606 3607 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3608 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3609 return false; 3610 3611 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3612 // independently on 128-bit lanes. 3613 unsigned NumLanes = VT.getSizeInBits()/128; 3614 unsigned NumLaneElts = NumElts/NumLanes; 3615 3616 for (unsigned l = 0; l != NumLanes; ++l) { 3617 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3618 i != (l+1)*NumLaneElts; i += 2, ++j) { 3619 int BitI = Mask[i]; 3620 int BitI1 = Mask[i+1]; 3621 if (!isUndefOrEqual(BitI, j)) 3622 return false; 3623 if (V2IsSplat) { 3624 if (isUndefOrEqual(BitI1, NumElts)) 3625 return false; 3626 } else { 3627 if (!isUndefOrEqual(BitI1, j+NumElts)) 3628 return false; 3629 } 3630 } 3631 } 3632 return true; 3633} 3634 3635/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3636/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3637/// <0, 0, 1, 1> 3638static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3639 bool HasAVX2) { 3640 unsigned NumElts = VT.getVectorNumElements(); 3641 3642 assert((VT.is128BitVector() || VT.is256BitVector()) && 3643 "Unsupported vector type for unpckh"); 3644 3645 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3646 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3647 return false; 3648 3649 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3650 // FIXME: Need a better way to get rid of this, there's no latency difference 3651 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3652 // the former later. We should also remove the "_undef" special mask. 3653 if (NumElts == 4 && VT.getSizeInBits() == 256) 3654 return false; 3655 3656 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3657 // independently on 128-bit lanes. 3658 unsigned NumLanes = VT.getSizeInBits()/128; 3659 unsigned NumLaneElts = NumElts/NumLanes; 3660 3661 for (unsigned l = 0; l != NumLanes; ++l) { 3662 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3663 i != (l+1)*NumLaneElts; 3664 i += 2, ++j) { 3665 int BitI = Mask[i]; 3666 int BitI1 = Mask[i+1]; 3667 3668 if (!isUndefOrEqual(BitI, j)) 3669 return false; 3670 if (!isUndefOrEqual(BitI1, j)) 3671 return false; 3672 } 3673 } 3674 3675 return true; 3676} 3677 3678/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3679/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3680/// <2, 2, 3, 3> 3681static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3682 unsigned NumElts = VT.getVectorNumElements(); 3683 3684 assert((VT.is128BitVector() || VT.is256BitVector()) && 3685 "Unsupported vector type for unpckh"); 3686 3687 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3688 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3689 return false; 3690 3691 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3692 // independently on 128-bit lanes. 3693 unsigned NumLanes = VT.getSizeInBits()/128; 3694 unsigned NumLaneElts = NumElts/NumLanes; 3695 3696 for (unsigned l = 0; l != NumLanes; ++l) { 3697 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3698 i != (l+1)*NumLaneElts; i += 2, ++j) { 3699 int BitI = Mask[i]; 3700 int BitI1 = Mask[i+1]; 3701 if (!isUndefOrEqual(BitI, j)) 3702 return false; 3703 if (!isUndefOrEqual(BitI1, j)) 3704 return false; 3705 } 3706 } 3707 return true; 3708} 3709 3710/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3711/// specifies a shuffle of elements that is suitable for input to MOVSS, 3712/// MOVSD, and MOVD, i.e. setting the lowest element. 3713static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3714 if (VT.getVectorElementType().getSizeInBits() < 32) 3715 return false; 3716 if (!VT.is128BitVector()) 3717 return false; 3718 3719 unsigned NumElts = VT.getVectorNumElements(); 3720 3721 if (!isUndefOrEqual(Mask[0], NumElts)) 3722 return false; 3723 3724 for (unsigned i = 1; i != NumElts; ++i) 3725 if (!isUndefOrEqual(Mask[i], i)) 3726 return false; 3727 3728 return true; 3729} 3730 3731/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3732/// as permutations between 128-bit chunks or halves. As an example: this 3733/// shuffle bellow: 3734/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3735/// The first half comes from the second half of V1 and the second half from the 3736/// the second half of V2. 3737static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3738 if (!HasAVX || !VT.is256BitVector()) 3739 return false; 3740 3741 // The shuffle result is divided into half A and half B. In total the two 3742 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3743 // B must come from C, D, E or F. 3744 unsigned HalfSize = VT.getVectorNumElements()/2; 3745 bool MatchA = false, MatchB = false; 3746 3747 // Check if A comes from one of C, D, E, F. 3748 for (unsigned Half = 0; Half != 4; ++Half) { 3749 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3750 MatchA = true; 3751 break; 3752 } 3753 } 3754 3755 // Check if B comes from one of C, D, E, F. 3756 for (unsigned Half = 0; Half != 4; ++Half) { 3757 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3758 MatchB = true; 3759 break; 3760 } 3761 } 3762 3763 return MatchA && MatchB; 3764} 3765 3766/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3767/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3768static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3769 EVT VT = SVOp->getValueType(0); 3770 3771 unsigned HalfSize = VT.getVectorNumElements()/2; 3772 3773 unsigned FstHalf = 0, SndHalf = 0; 3774 for (unsigned i = 0; i < HalfSize; ++i) { 3775 if (SVOp->getMaskElt(i) > 0) { 3776 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3777 break; 3778 } 3779 } 3780 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3781 if (SVOp->getMaskElt(i) > 0) { 3782 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3783 break; 3784 } 3785 } 3786 3787 return (FstHalf | (SndHalf << 4)); 3788} 3789 3790/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3791/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3792/// Note that VPERMIL mask matching is different depending whether theunderlying 3793/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3794/// to the same elements of the low, but to the higher half of the source. 3795/// In VPERMILPD the two lanes could be shuffled independently of each other 3796/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3797static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3798 if (!HasAVX) 3799 return false; 3800 3801 unsigned NumElts = VT.getVectorNumElements(); 3802 // Only match 256-bit with 32/64-bit types 3803 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3804 return false; 3805 3806 unsigned NumLanes = VT.getSizeInBits()/128; 3807 unsigned LaneSize = NumElts/NumLanes; 3808 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3809 for (unsigned i = 0; i != LaneSize; ++i) { 3810 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3811 return false; 3812 if (NumElts != 8 || l == 0) 3813 continue; 3814 // VPERMILPS handling 3815 if (Mask[i] < 0) 3816 continue; 3817 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3818 return false; 3819 } 3820 } 3821 3822 return true; 3823} 3824 3825/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3826/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3827/// element of vector 2 and the other elements to come from vector 1 in order. 3828static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3829 bool V2IsSplat = false, bool V2IsUndef = false) { 3830 if (!VT.is128BitVector()) 3831 return false; 3832 3833 unsigned NumOps = VT.getVectorNumElements(); 3834 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3835 return false; 3836 3837 if (!isUndefOrEqual(Mask[0], 0)) 3838 return false; 3839 3840 for (unsigned i = 1; i != NumOps; ++i) 3841 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3842 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3843 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3844 return false; 3845 3846 return true; 3847} 3848 3849/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3850/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3851/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3852static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3853 const X86Subtarget *Subtarget) { 3854 if (!Subtarget->hasSSE3()) 3855 return false; 3856 3857 unsigned NumElems = VT.getVectorNumElements(); 3858 3859 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3860 (VT.getSizeInBits() == 256 && NumElems != 8)) 3861 return false; 3862 3863 // "i+1" is the value the indexed mask element must have 3864 for (unsigned i = 0; i != NumElems; i += 2) 3865 if (!isUndefOrEqual(Mask[i], i+1) || 3866 !isUndefOrEqual(Mask[i+1], i+1)) 3867 return false; 3868 3869 return true; 3870} 3871 3872/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3873/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3874/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3875static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3876 const X86Subtarget *Subtarget) { 3877 if (!Subtarget->hasSSE3()) 3878 return false; 3879 3880 unsigned NumElems = VT.getVectorNumElements(); 3881 3882 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3883 (VT.getSizeInBits() == 256 && NumElems != 8)) 3884 return false; 3885 3886 // "i" is the value the indexed mask element must have 3887 for (unsigned i = 0; i != NumElems; i += 2) 3888 if (!isUndefOrEqual(Mask[i], i) || 3889 !isUndefOrEqual(Mask[i+1], i)) 3890 return false; 3891 3892 return true; 3893} 3894 3895/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3896/// specifies a shuffle of elements that is suitable for input to 256-bit 3897/// version of MOVDDUP. 3898static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3899 if (!HasAVX || !VT.is256BitVector()) 3900 return false; 3901 3902 unsigned NumElts = VT.getVectorNumElements(); 3903 if (NumElts != 4) 3904 return false; 3905 3906 for (unsigned i = 0; i != NumElts/2; ++i) 3907 if (!isUndefOrEqual(Mask[i], 0)) 3908 return false; 3909 for (unsigned i = NumElts/2; i != NumElts; ++i) 3910 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3911 return false; 3912 return true; 3913} 3914 3915/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3916/// specifies a shuffle of elements that is suitable for input to 128-bit 3917/// version of MOVDDUP. 3918static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3919 if (!VT.is128BitVector()) 3920 return false; 3921 3922 unsigned e = VT.getVectorNumElements() / 2; 3923 for (unsigned i = 0; i != e; ++i) 3924 if (!isUndefOrEqual(Mask[i], i)) 3925 return false; 3926 for (unsigned i = 0; i != e; ++i) 3927 if (!isUndefOrEqual(Mask[e+i], i)) 3928 return false; 3929 return true; 3930} 3931 3932/// isVEXTRACTF128Index - Return true if the specified 3933/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3934/// suitable for input to VEXTRACTF128. 3935bool X86::isVEXTRACTF128Index(SDNode *N) { 3936 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3937 return false; 3938 3939 // The index should be aligned on a 128-bit boundary. 3940 uint64_t Index = 3941 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3942 3943 unsigned VL = N->getValueType(0).getVectorNumElements(); 3944 unsigned VBits = N->getValueType(0).getSizeInBits(); 3945 unsigned ElSize = VBits / VL; 3946 bool Result = (Index * ElSize) % 128 == 0; 3947 3948 return Result; 3949} 3950 3951/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3952/// operand specifies a subvector insert that is suitable for input to 3953/// VINSERTF128. 3954bool X86::isVINSERTF128Index(SDNode *N) { 3955 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3956 return false; 3957 3958 // The index should be aligned on a 128-bit boundary. 3959 uint64_t Index = 3960 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3961 3962 unsigned VL = N->getValueType(0).getVectorNumElements(); 3963 unsigned VBits = N->getValueType(0).getSizeInBits(); 3964 unsigned ElSize = VBits / VL; 3965 bool Result = (Index * ElSize) % 128 == 0; 3966 3967 return Result; 3968} 3969 3970/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3971/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3972/// Handles 128-bit and 256-bit. 3973static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3974 EVT VT = N->getValueType(0); 3975 3976 assert((VT.is128BitVector() || VT.is256BitVector()) && 3977 "Unsupported vector type for PSHUF/SHUFP"); 3978 3979 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3980 // independently on 128-bit lanes. 3981 unsigned NumElts = VT.getVectorNumElements(); 3982 unsigned NumLanes = VT.getSizeInBits()/128; 3983 unsigned NumLaneElts = NumElts/NumLanes; 3984 3985 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3986 "Only supports 2 or 4 elements per lane"); 3987 3988 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3989 unsigned Mask = 0; 3990 for (unsigned i = 0; i != NumElts; ++i) { 3991 int Elt = N->getMaskElt(i); 3992 if (Elt < 0) continue; 3993 Elt &= NumLaneElts - 1; 3994 unsigned ShAmt = (i << Shift) % 8; 3995 Mask |= Elt << ShAmt; 3996 } 3997 3998 return Mask; 3999} 4000 4001/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4002/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4003static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 4004 EVT VT = N->getValueType(0); 4005 4006 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4007 "Unsupported vector type for PSHUFHW"); 4008 4009 unsigned NumElts = VT.getVectorNumElements(); 4010 4011 unsigned Mask = 0; 4012 for (unsigned l = 0; l != NumElts; l += 8) { 4013 // 8 nodes per lane, but we only care about the last 4. 4014 for (unsigned i = 0; i < 4; ++i) { 4015 int Elt = N->getMaskElt(l+i+4); 4016 if (Elt < 0) continue; 4017 Elt &= 0x3; // only 2-bits. 4018 Mask |= Elt << (i * 2); 4019 } 4020 } 4021 4022 return Mask; 4023} 4024 4025/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4026/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4027static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 4028 EVT VT = N->getValueType(0); 4029 4030 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4031 "Unsupported vector type for PSHUFHW"); 4032 4033 unsigned NumElts = VT.getVectorNumElements(); 4034 4035 unsigned Mask = 0; 4036 for (unsigned l = 0; l != NumElts; l += 8) { 4037 // 8 nodes per lane, but we only care about the first 4. 4038 for (unsigned i = 0; i < 4; ++i) { 4039 int Elt = N->getMaskElt(l+i); 4040 if (Elt < 0) continue; 4041 Elt &= 0x3; // only 2-bits 4042 Mask |= Elt << (i * 2); 4043 } 4044 } 4045 4046 return Mask; 4047} 4048 4049/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4050/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4051static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4052 EVT VT = SVOp->getValueType(0); 4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4054 4055 unsigned NumElts = VT.getVectorNumElements(); 4056 unsigned NumLanes = VT.getSizeInBits()/128; 4057 unsigned NumLaneElts = NumElts/NumLanes; 4058 4059 int Val = 0; 4060 unsigned i; 4061 for (i = 0; i != NumElts; ++i) { 4062 Val = SVOp->getMaskElt(i); 4063 if (Val >= 0) 4064 break; 4065 } 4066 if (Val >= (int)NumElts) 4067 Val -= NumElts - NumLaneElts; 4068 4069 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4070 return (Val - i) * EltSize; 4071} 4072 4073/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4074/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4075/// instructions. 4076unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4077 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4078 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4079 4080 uint64_t Index = 4081 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4082 4083 EVT VecVT = N->getOperand(0).getValueType(); 4084 EVT ElVT = VecVT.getVectorElementType(); 4085 4086 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4087 return Index / NumElemsPerChunk; 4088} 4089 4090/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4091/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4092/// instructions. 4093unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4094 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4095 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4096 4097 uint64_t Index = 4098 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4099 4100 EVT VecVT = N->getValueType(0); 4101 EVT ElVT = VecVT.getVectorElementType(); 4102 4103 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4104 return Index / NumElemsPerChunk; 4105} 4106 4107/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4108/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4109/// Handles 256-bit. 4110static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4111 EVT VT = N->getValueType(0); 4112 4113 unsigned NumElts = VT.getVectorNumElements(); 4114 4115 assert((VT.is256BitVector() && NumElts == 4) && 4116 "Unsupported vector type for VPERMQ/VPERMPD"); 4117 4118 unsigned Mask = 0; 4119 for (unsigned i = 0; i != NumElts; ++i) { 4120 int Elt = N->getMaskElt(i); 4121 if (Elt < 0) 4122 continue; 4123 Mask |= Elt << (i*2); 4124 } 4125 4126 return Mask; 4127} 4128/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4129/// constant +0.0. 4130bool X86::isZeroNode(SDValue Elt) { 4131 return ((isa<ConstantSDNode>(Elt) && 4132 cast<ConstantSDNode>(Elt)->isNullValue()) || 4133 (isa<ConstantFPSDNode>(Elt) && 4134 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4135} 4136 4137/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4138/// their permute mask. 4139static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4140 SelectionDAG &DAG) { 4141 EVT VT = SVOp->getValueType(0); 4142 unsigned NumElems = VT.getVectorNumElements(); 4143 SmallVector<int, 8> MaskVec; 4144 4145 for (unsigned i = 0; i != NumElems; ++i) { 4146 int Idx = SVOp->getMaskElt(i); 4147 if (Idx >= 0) { 4148 if (Idx < (int)NumElems) 4149 Idx += NumElems; 4150 else 4151 Idx -= NumElems; 4152 } 4153 MaskVec.push_back(Idx); 4154 } 4155 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4156 SVOp->getOperand(0), &MaskVec[0]); 4157} 4158 4159/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4160/// match movhlps. The lower half elements should come from upper half of 4161/// V1 (and in order), and the upper half elements should come from the upper 4162/// half of V2 (and in order). 4163static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4164 if (!VT.is128BitVector()) 4165 return false; 4166 if (VT.getVectorNumElements() != 4) 4167 return false; 4168 for (unsigned i = 0, e = 2; i != e; ++i) 4169 if (!isUndefOrEqual(Mask[i], i+2)) 4170 return false; 4171 for (unsigned i = 2; i != 4; ++i) 4172 if (!isUndefOrEqual(Mask[i], i+4)) 4173 return false; 4174 return true; 4175} 4176 4177/// isScalarLoadToVector - Returns true if the node is a scalar load that 4178/// is promoted to a vector. It also returns the LoadSDNode by reference if 4179/// required. 4180static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4181 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4182 return false; 4183 N = N->getOperand(0).getNode(); 4184 if (!ISD::isNON_EXTLoad(N)) 4185 return false; 4186 if (LD) 4187 *LD = cast<LoadSDNode>(N); 4188 return true; 4189} 4190 4191// Test whether the given value is a vector value which will be legalized 4192// into a load. 4193static bool WillBeConstantPoolLoad(SDNode *N) { 4194 if (N->getOpcode() != ISD::BUILD_VECTOR) 4195 return false; 4196 4197 // Check for any non-constant elements. 4198 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4199 switch (N->getOperand(i).getNode()->getOpcode()) { 4200 case ISD::UNDEF: 4201 case ISD::ConstantFP: 4202 case ISD::Constant: 4203 break; 4204 default: 4205 return false; 4206 } 4207 4208 // Vectors of all-zeros and all-ones are materialized with special 4209 // instructions rather than being loaded. 4210 return !ISD::isBuildVectorAllZeros(N) && 4211 !ISD::isBuildVectorAllOnes(N); 4212} 4213 4214/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4215/// match movlp{s|d}. The lower half elements should come from lower half of 4216/// V1 (and in order), and the upper half elements should come from the upper 4217/// half of V2 (and in order). And since V1 will become the source of the 4218/// MOVLP, it must be either a vector load or a scalar load to vector. 4219static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4220 ArrayRef<int> Mask, EVT VT) { 4221 if (!VT.is128BitVector()) 4222 return false; 4223 4224 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4225 return false; 4226 // Is V2 is a vector load, don't do this transformation. We will try to use 4227 // load folding shufps op. 4228 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4229 return false; 4230 4231 unsigned NumElems = VT.getVectorNumElements(); 4232 4233 if (NumElems != 2 && NumElems != 4) 4234 return false; 4235 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4236 if (!isUndefOrEqual(Mask[i], i)) 4237 return false; 4238 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4239 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4240 return false; 4241 return true; 4242} 4243 4244/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4245/// all the same. 4246static bool isSplatVector(SDNode *N) { 4247 if (N->getOpcode() != ISD::BUILD_VECTOR) 4248 return false; 4249 4250 SDValue SplatValue = N->getOperand(0); 4251 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4252 if (N->getOperand(i) != SplatValue) 4253 return false; 4254 return true; 4255} 4256 4257/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4258/// to an zero vector. 4259/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4260static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4261 SDValue V1 = N->getOperand(0); 4262 SDValue V2 = N->getOperand(1); 4263 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4264 for (unsigned i = 0; i != NumElems; ++i) { 4265 int Idx = N->getMaskElt(i); 4266 if (Idx >= (int)NumElems) { 4267 unsigned Opc = V2.getOpcode(); 4268 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4269 continue; 4270 if (Opc != ISD::BUILD_VECTOR || 4271 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4272 return false; 4273 } else if (Idx >= 0) { 4274 unsigned Opc = V1.getOpcode(); 4275 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4276 continue; 4277 if (Opc != ISD::BUILD_VECTOR || 4278 !X86::isZeroNode(V1.getOperand(Idx))) 4279 return false; 4280 } 4281 } 4282 return true; 4283} 4284 4285/// getZeroVector - Returns a vector of specified type with all zero elements. 4286/// 4287static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4288 SelectionDAG &DAG, DebugLoc dl) { 4289 assert(VT.isVector() && "Expected a vector type"); 4290 unsigned Size = VT.getSizeInBits(); 4291 4292 // Always build SSE zero vectors as <4 x i32> bitcasted 4293 // to their dest type. This ensures they get CSE'd. 4294 SDValue Vec; 4295 if (Size == 128) { // SSE 4296 if (Subtarget->hasSSE2()) { // SSE2 4297 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4298 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4299 } else { // SSE1 4300 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4301 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4302 } 4303 } else if (Size == 256) { // AVX 4304 if (Subtarget->hasAVX2()) { // AVX2 4305 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4306 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4307 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4308 } else { 4309 // 256-bit logic and arithmetic instructions in AVX are all 4310 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4311 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4312 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4313 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4314 } 4315 } else 4316 llvm_unreachable("Unexpected vector type"); 4317 4318 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4319} 4320 4321/// getOnesVector - Returns a vector of specified type with all bits set. 4322/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4323/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4324/// Then bitcast to their original type, ensuring they get CSE'd. 4325static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4326 DebugLoc dl) { 4327 assert(VT.isVector() && "Expected a vector type"); 4328 unsigned Size = VT.getSizeInBits(); 4329 4330 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4331 SDValue Vec; 4332 if (Size == 256) { 4333 if (HasAVX2) { // AVX2 4334 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4335 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4336 } else { // AVX 4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4338 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4339 } 4340 } else if (Size == 128) { 4341 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4342 } else 4343 llvm_unreachable("Unexpected vector type"); 4344 4345 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4346} 4347 4348/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4349/// that point to V2 points to its first element. 4350static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4351 for (unsigned i = 0; i != NumElems; ++i) { 4352 if (Mask[i] > (int)NumElems) { 4353 Mask[i] = NumElems; 4354 } 4355 } 4356} 4357 4358/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4359/// operation of specified width. 4360static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4361 SDValue V2) { 4362 unsigned NumElems = VT.getVectorNumElements(); 4363 SmallVector<int, 8> Mask; 4364 Mask.push_back(NumElems); 4365 for (unsigned i = 1; i != NumElems; ++i) 4366 Mask.push_back(i); 4367 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4368} 4369 4370/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4371static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4372 SDValue V2) { 4373 unsigned NumElems = VT.getVectorNumElements(); 4374 SmallVector<int, 8> Mask; 4375 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4376 Mask.push_back(i); 4377 Mask.push_back(i + NumElems); 4378 } 4379 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4380} 4381 4382/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4383static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4384 SDValue V2) { 4385 unsigned NumElems = VT.getVectorNumElements(); 4386 SmallVector<int, 8> Mask; 4387 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4388 Mask.push_back(i + Half); 4389 Mask.push_back(i + NumElems + Half); 4390 } 4391 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4392} 4393 4394// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4395// a generic shuffle instruction because the target has no such instructions. 4396// Generate shuffles which repeat i16 and i8 several times until they can be 4397// represented by v4f32 and then be manipulated by target suported shuffles. 4398static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4399 EVT VT = V.getValueType(); 4400 int NumElems = VT.getVectorNumElements(); 4401 DebugLoc dl = V.getDebugLoc(); 4402 4403 while (NumElems > 4) { 4404 if (EltNo < NumElems/2) { 4405 V = getUnpackl(DAG, dl, VT, V, V); 4406 } else { 4407 V = getUnpackh(DAG, dl, VT, V, V); 4408 EltNo -= NumElems/2; 4409 } 4410 NumElems >>= 1; 4411 } 4412 return V; 4413} 4414 4415/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4416static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4417 EVT VT = V.getValueType(); 4418 DebugLoc dl = V.getDebugLoc(); 4419 unsigned Size = VT.getSizeInBits(); 4420 4421 if (Size == 128) { 4422 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4423 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4424 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4425 &SplatMask[0]); 4426 } else if (Size == 256) { 4427 // To use VPERMILPS to splat scalars, the second half of indicies must 4428 // refer to the higher part, which is a duplication of the lower one, 4429 // because VPERMILPS can only handle in-lane permutations. 4430 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4431 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4432 4433 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4434 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4435 &SplatMask[0]); 4436 } else 4437 llvm_unreachable("Vector size not supported"); 4438 4439 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4440} 4441 4442/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4443static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4444 EVT SrcVT = SV->getValueType(0); 4445 SDValue V1 = SV->getOperand(0); 4446 DebugLoc dl = SV->getDebugLoc(); 4447 4448 int EltNo = SV->getSplatIndex(); 4449 int NumElems = SrcVT.getVectorNumElements(); 4450 unsigned Size = SrcVT.getSizeInBits(); 4451 4452 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4453 "Unknown how to promote splat for type"); 4454 4455 // Extract the 128-bit part containing the splat element and update 4456 // the splat element index when it refers to the higher register. 4457 if (Size == 256) { 4458 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4459 if (EltNo >= NumElems/2) 4460 EltNo -= NumElems/2; 4461 } 4462 4463 // All i16 and i8 vector types can't be used directly by a generic shuffle 4464 // instruction because the target has no such instruction. Generate shuffles 4465 // which repeat i16 and i8 several times until they fit in i32, and then can 4466 // be manipulated by target suported shuffles. 4467 EVT EltVT = SrcVT.getVectorElementType(); 4468 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4469 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4470 4471 // Recreate the 256-bit vector and place the same 128-bit vector 4472 // into the low and high part. This is necessary because we want 4473 // to use VPERM* to shuffle the vectors 4474 if (Size == 256) { 4475 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4476 } 4477 4478 return getLegalSplat(DAG, V1, EltNo); 4479} 4480 4481/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4482/// vector of zero or undef vector. This produces a shuffle where the low 4483/// element of V2 is swizzled into the zero/undef vector, landing at element 4484/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4485static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4486 bool IsZero, 4487 const X86Subtarget *Subtarget, 4488 SelectionDAG &DAG) { 4489 EVT VT = V2.getValueType(); 4490 SDValue V1 = IsZero 4491 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4492 unsigned NumElems = VT.getVectorNumElements(); 4493 SmallVector<int, 16> MaskVec; 4494 for (unsigned i = 0; i != NumElems; ++i) 4495 // If this is the insertion idx, put the low elt of V2 here. 4496 MaskVec.push_back(i == Idx ? NumElems : i); 4497 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4498} 4499 4500/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4501/// target specific opcode. Returns true if the Mask could be calculated. 4502/// Sets IsUnary to true if only uses one source. 4503static bool getTargetShuffleMask(SDNode *N, MVT VT, 4504 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4505 unsigned NumElems = VT.getVectorNumElements(); 4506 SDValue ImmN; 4507 4508 IsUnary = false; 4509 switch(N->getOpcode()) { 4510 case X86ISD::SHUFP: 4511 ImmN = N->getOperand(N->getNumOperands()-1); 4512 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4513 break; 4514 case X86ISD::UNPCKH: 4515 DecodeUNPCKHMask(VT, Mask); 4516 break; 4517 case X86ISD::UNPCKL: 4518 DecodeUNPCKLMask(VT, Mask); 4519 break; 4520 case X86ISD::MOVHLPS: 4521 DecodeMOVHLPSMask(NumElems, Mask); 4522 break; 4523 case X86ISD::MOVLHPS: 4524 DecodeMOVLHPSMask(NumElems, Mask); 4525 break; 4526 case X86ISD::PSHUFD: 4527 case X86ISD::VPERMILP: 4528 ImmN = N->getOperand(N->getNumOperands()-1); 4529 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4530 IsUnary = true; 4531 break; 4532 case X86ISD::PSHUFHW: 4533 ImmN = N->getOperand(N->getNumOperands()-1); 4534 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4535 IsUnary = true; 4536 break; 4537 case X86ISD::PSHUFLW: 4538 ImmN = N->getOperand(N->getNumOperands()-1); 4539 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4540 IsUnary = true; 4541 break; 4542 case X86ISD::VPERMI: 4543 ImmN = N->getOperand(N->getNumOperands()-1); 4544 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4545 IsUnary = true; 4546 break; 4547 case X86ISD::MOVSS: 4548 case X86ISD::MOVSD: { 4549 // The index 0 always comes from the first element of the second source, 4550 // this is why MOVSS and MOVSD are used in the first place. The other 4551 // elements come from the other positions of the first source vector 4552 Mask.push_back(NumElems); 4553 for (unsigned i = 1; i != NumElems; ++i) { 4554 Mask.push_back(i); 4555 } 4556 break; 4557 } 4558 case X86ISD::VPERM2X128: 4559 ImmN = N->getOperand(N->getNumOperands()-1); 4560 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4561 if (Mask.empty()) return false; 4562 break; 4563 case X86ISD::MOVDDUP: 4564 case X86ISD::MOVLHPD: 4565 case X86ISD::MOVLPD: 4566 case X86ISD::MOVLPS: 4567 case X86ISD::MOVSHDUP: 4568 case X86ISD::MOVSLDUP: 4569 case X86ISD::PALIGN: 4570 // Not yet implemented 4571 return false; 4572 default: llvm_unreachable("unknown target shuffle node"); 4573 } 4574 4575 return true; 4576} 4577 4578/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4579/// element of the result of the vector shuffle. 4580static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4581 unsigned Depth) { 4582 if (Depth == 6) 4583 return SDValue(); // Limit search depth. 4584 4585 SDValue V = SDValue(N, 0); 4586 EVT VT = V.getValueType(); 4587 unsigned Opcode = V.getOpcode(); 4588 4589 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4590 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4591 int Elt = SV->getMaskElt(Index); 4592 4593 if (Elt < 0) 4594 return DAG.getUNDEF(VT.getVectorElementType()); 4595 4596 unsigned NumElems = VT.getVectorNumElements(); 4597 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4598 : SV->getOperand(1); 4599 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4600 } 4601 4602 // Recurse into target specific vector shuffles to find scalars. 4603 if (isTargetShuffle(Opcode)) { 4604 MVT ShufVT = V.getValueType().getSimpleVT(); 4605 unsigned NumElems = ShufVT.getVectorNumElements(); 4606 SmallVector<int, 16> ShuffleMask; 4607 SDValue ImmN; 4608 bool IsUnary; 4609 4610 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 4611 return SDValue(); 4612 4613 int Elt = ShuffleMask[Index]; 4614 if (Elt < 0) 4615 return DAG.getUNDEF(ShufVT.getVectorElementType()); 4616 4617 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4618 : N->getOperand(1); 4619 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4620 Depth+1); 4621 } 4622 4623 // Actual nodes that may contain scalar elements 4624 if (Opcode == ISD::BITCAST) { 4625 V = V.getOperand(0); 4626 EVT SrcVT = V.getValueType(); 4627 unsigned NumElems = VT.getVectorNumElements(); 4628 4629 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4630 return SDValue(); 4631 } 4632 4633 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4634 return (Index == 0) ? V.getOperand(0) 4635 : DAG.getUNDEF(VT.getVectorElementType()); 4636 4637 if (V.getOpcode() == ISD::BUILD_VECTOR) 4638 return V.getOperand(Index); 4639 4640 return SDValue(); 4641} 4642 4643/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4644/// shuffle operation which come from a consecutively from a zero. The 4645/// search can start in two different directions, from left or right. 4646static 4647unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4648 bool ZerosFromLeft, SelectionDAG &DAG) { 4649 unsigned i; 4650 for (i = 0; i != NumElems; ++i) { 4651 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4652 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4653 if (!(Elt.getNode() && 4654 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4655 break; 4656 } 4657 4658 return i; 4659} 4660 4661/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4662/// correspond consecutively to elements from one of the vector operands, 4663/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4664static 4665bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4666 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4667 unsigned NumElems, unsigned &OpNum) { 4668 bool SeenV1 = false; 4669 bool SeenV2 = false; 4670 4671 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4672 int Idx = SVOp->getMaskElt(i); 4673 // Ignore undef indicies 4674 if (Idx < 0) 4675 continue; 4676 4677 if (Idx < (int)NumElems) 4678 SeenV1 = true; 4679 else 4680 SeenV2 = true; 4681 4682 // Only accept consecutive elements from the same vector 4683 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4684 return false; 4685 } 4686 4687 OpNum = SeenV1 ? 0 : 1; 4688 return true; 4689} 4690 4691/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4692/// logical left shift of a vector. 4693static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4694 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4695 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4696 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4697 false /* check zeros from right */, DAG); 4698 unsigned OpSrc; 4699 4700 if (!NumZeros) 4701 return false; 4702 4703 // Considering the elements in the mask that are not consecutive zeros, 4704 // check if they consecutively come from only one of the source vectors. 4705 // 4706 // V1 = {X, A, B, C} 0 4707 // \ \ \ / 4708 // vector_shuffle V1, V2 <1, 2, 3, X> 4709 // 4710 if (!isShuffleMaskConsecutive(SVOp, 4711 0, // Mask Start Index 4712 NumElems-NumZeros, // Mask End Index(exclusive) 4713 NumZeros, // Where to start looking in the src vector 4714 NumElems, // Number of elements in vector 4715 OpSrc)) // Which source operand ? 4716 return false; 4717 4718 isLeft = false; 4719 ShAmt = NumZeros; 4720 ShVal = SVOp->getOperand(OpSrc); 4721 return true; 4722} 4723 4724/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4725/// logical left shift of a vector. 4726static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4727 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4728 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4729 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4730 true /* check zeros from left */, DAG); 4731 unsigned OpSrc; 4732 4733 if (!NumZeros) 4734 return false; 4735 4736 // Considering the elements in the mask that are not consecutive zeros, 4737 // check if they consecutively come from only one of the source vectors. 4738 // 4739 // 0 { A, B, X, X } = V2 4740 // / \ / / 4741 // vector_shuffle V1, V2 <X, X, 4, 5> 4742 // 4743 if (!isShuffleMaskConsecutive(SVOp, 4744 NumZeros, // Mask Start Index 4745 NumElems, // Mask End Index(exclusive) 4746 0, // Where to start looking in the src vector 4747 NumElems, // Number of elements in vector 4748 OpSrc)) // Which source operand ? 4749 return false; 4750 4751 isLeft = true; 4752 ShAmt = NumZeros; 4753 ShVal = SVOp->getOperand(OpSrc); 4754 return true; 4755} 4756 4757/// isVectorShift - Returns true if the shuffle can be implemented as a 4758/// logical left or right shift of a vector. 4759static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4760 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4761 // Although the logic below support any bitwidth size, there are no 4762 // shift instructions which handle more than 128-bit vectors. 4763 if (!SVOp->getValueType(0).is128BitVector()) 4764 return false; 4765 4766 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4767 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4768 return true; 4769 4770 return false; 4771} 4772 4773/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4774/// 4775static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4776 unsigned NumNonZero, unsigned NumZero, 4777 SelectionDAG &DAG, 4778 const X86Subtarget* Subtarget, 4779 const TargetLowering &TLI) { 4780 if (NumNonZero > 8) 4781 return SDValue(); 4782 4783 DebugLoc dl = Op.getDebugLoc(); 4784 SDValue V(0, 0); 4785 bool First = true; 4786 for (unsigned i = 0; i < 16; ++i) { 4787 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4788 if (ThisIsNonZero && First) { 4789 if (NumZero) 4790 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4791 else 4792 V = DAG.getUNDEF(MVT::v8i16); 4793 First = false; 4794 } 4795 4796 if ((i & 1) != 0) { 4797 SDValue ThisElt(0, 0), LastElt(0, 0); 4798 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4799 if (LastIsNonZero) { 4800 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4801 MVT::i16, Op.getOperand(i-1)); 4802 } 4803 if (ThisIsNonZero) { 4804 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4805 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4806 ThisElt, DAG.getConstant(8, MVT::i8)); 4807 if (LastIsNonZero) 4808 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4809 } else 4810 ThisElt = LastElt; 4811 4812 if (ThisElt.getNode()) 4813 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4814 DAG.getIntPtrConstant(i/2)); 4815 } 4816 } 4817 4818 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4819} 4820 4821/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4822/// 4823static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4824 unsigned NumNonZero, unsigned NumZero, 4825 SelectionDAG &DAG, 4826 const X86Subtarget* Subtarget, 4827 const TargetLowering &TLI) { 4828 if (NumNonZero > 4) 4829 return SDValue(); 4830 4831 DebugLoc dl = Op.getDebugLoc(); 4832 SDValue V(0, 0); 4833 bool First = true; 4834 for (unsigned i = 0; i < 8; ++i) { 4835 bool isNonZero = (NonZeros & (1 << i)) != 0; 4836 if (isNonZero) { 4837 if (First) { 4838 if (NumZero) 4839 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4840 else 4841 V = DAG.getUNDEF(MVT::v8i16); 4842 First = false; 4843 } 4844 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4845 MVT::v8i16, V, Op.getOperand(i), 4846 DAG.getIntPtrConstant(i)); 4847 } 4848 } 4849 4850 return V; 4851} 4852 4853/// getVShift - Return a vector logical shift node. 4854/// 4855static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4856 unsigned NumBits, SelectionDAG &DAG, 4857 const TargetLowering &TLI, DebugLoc dl) { 4858 assert(VT.is128BitVector() && "Unknown type for VShift"); 4859 EVT ShVT = MVT::v2i64; 4860 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4861 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4862 return DAG.getNode(ISD::BITCAST, dl, VT, 4863 DAG.getNode(Opc, dl, ShVT, SrcOp, 4864 DAG.getConstant(NumBits, 4865 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4866} 4867 4868SDValue 4869X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4870 SelectionDAG &DAG) const { 4871 4872 // Check if the scalar load can be widened into a vector load. And if 4873 // the address is "base + cst" see if the cst can be "absorbed" into 4874 // the shuffle mask. 4875 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4876 SDValue Ptr = LD->getBasePtr(); 4877 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4878 return SDValue(); 4879 EVT PVT = LD->getValueType(0); 4880 if (PVT != MVT::i32 && PVT != MVT::f32) 4881 return SDValue(); 4882 4883 int FI = -1; 4884 int64_t Offset = 0; 4885 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4886 FI = FINode->getIndex(); 4887 Offset = 0; 4888 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4889 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4890 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4891 Offset = Ptr.getConstantOperandVal(1); 4892 Ptr = Ptr.getOperand(0); 4893 } else { 4894 return SDValue(); 4895 } 4896 4897 // FIXME: 256-bit vector instructions don't require a strict alignment, 4898 // improve this code to support it better. 4899 unsigned RequiredAlign = VT.getSizeInBits()/8; 4900 SDValue Chain = LD->getChain(); 4901 // Make sure the stack object alignment is at least 16 or 32. 4902 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4903 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4904 if (MFI->isFixedObjectIndex(FI)) { 4905 // Can't change the alignment. FIXME: It's possible to compute 4906 // the exact stack offset and reference FI + adjust offset instead. 4907 // If someone *really* cares about this. That's the way to implement it. 4908 return SDValue(); 4909 } else { 4910 MFI->setObjectAlignment(FI, RequiredAlign); 4911 } 4912 } 4913 4914 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4915 // Ptr + (Offset & ~15). 4916 if (Offset < 0) 4917 return SDValue(); 4918 if ((Offset % RequiredAlign) & 3) 4919 return SDValue(); 4920 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4921 if (StartOffset) 4922 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4923 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4924 4925 int EltNo = (Offset - StartOffset) >> 2; 4926 unsigned NumElems = VT.getVectorNumElements(); 4927 4928 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4929 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4930 LD->getPointerInfo().getWithOffset(StartOffset), 4931 false, false, false, 0); 4932 4933 SmallVector<int, 8> Mask; 4934 for (unsigned i = 0; i != NumElems; ++i) 4935 Mask.push_back(EltNo); 4936 4937 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4938 } 4939 4940 return SDValue(); 4941} 4942 4943/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4944/// vector of type 'VT', see if the elements can be replaced by a single large 4945/// load which has the same value as a build_vector whose operands are 'elts'. 4946/// 4947/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4948/// 4949/// FIXME: we'd also like to handle the case where the last elements are zero 4950/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4951/// There's even a handy isZeroNode for that purpose. 4952static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4953 DebugLoc &DL, SelectionDAG &DAG) { 4954 EVT EltVT = VT.getVectorElementType(); 4955 unsigned NumElems = Elts.size(); 4956 4957 LoadSDNode *LDBase = NULL; 4958 unsigned LastLoadedElt = -1U; 4959 4960 // For each element in the initializer, see if we've found a load or an undef. 4961 // If we don't find an initial load element, or later load elements are 4962 // non-consecutive, bail out. 4963 for (unsigned i = 0; i < NumElems; ++i) { 4964 SDValue Elt = Elts[i]; 4965 4966 if (!Elt.getNode() || 4967 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4968 return SDValue(); 4969 if (!LDBase) { 4970 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4971 return SDValue(); 4972 LDBase = cast<LoadSDNode>(Elt.getNode()); 4973 LastLoadedElt = i; 4974 continue; 4975 } 4976 if (Elt.getOpcode() == ISD::UNDEF) 4977 continue; 4978 4979 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4980 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4981 return SDValue(); 4982 LastLoadedElt = i; 4983 } 4984 4985 // If we have found an entire vector of loads and undefs, then return a large 4986 // load of the entire vector width starting at the base pointer. If we found 4987 // consecutive loads for the low half, generate a vzext_load node. 4988 if (LastLoadedElt == NumElems - 1) { 4989 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4990 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4991 LDBase->getPointerInfo(), 4992 LDBase->isVolatile(), LDBase->isNonTemporal(), 4993 LDBase->isInvariant(), 0); 4994 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4995 LDBase->getPointerInfo(), 4996 LDBase->isVolatile(), LDBase->isNonTemporal(), 4997 LDBase->isInvariant(), LDBase->getAlignment()); 4998 } 4999 if (NumElems == 4 && LastLoadedElt == 1 && 5000 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5001 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5002 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5003 SDValue ResNode = 5004 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5005 LDBase->getPointerInfo(), 5006 LDBase->getAlignment(), 5007 false/*isVolatile*/, true/*ReadMem*/, 5008 false/*WriteMem*/); 5009 5010 // Make sure the newly-created LOAD is in the same position as LDBase in 5011 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and 5012 // update uses of LDBase's output chain to use the TokenFactor. 5013 if (LDBase->hasAnyUseOfValue(1)) { 5014 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 5015 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1)); 5016 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain); 5017 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1), 5018 SDValue(ResNode.getNode(), 1)); 5019 } 5020 5021 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5022 } 5023 return SDValue(); 5024} 5025 5026/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 5027/// to generate a splat value for the following cases: 5028/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 5029/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5030/// a scalar load, or a constant. 5031/// The VBROADCAST node is returned when a pattern is found, 5032/// or SDValue() otherwise. 5033SDValue 5034X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const { 5035 if (!Subtarget->hasAVX()) 5036 return SDValue(); 5037 5038 EVT VT = Op.getValueType(); 5039 DebugLoc dl = Op.getDebugLoc(); 5040 5041 assert((VT.is128BitVector() || VT.is256BitVector()) && 5042 "Unsupported vector type for broadcast."); 5043 5044 SDValue Ld; 5045 bool ConstSplatVal; 5046 5047 switch (Op.getOpcode()) { 5048 default: 5049 // Unknown pattern found. 5050 return SDValue(); 5051 5052 case ISD::BUILD_VECTOR: { 5053 // The BUILD_VECTOR node must be a splat. 5054 if (!isSplatVector(Op.getNode())) 5055 return SDValue(); 5056 5057 Ld = Op.getOperand(0); 5058 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5059 Ld.getOpcode() == ISD::ConstantFP); 5060 5061 // The suspected load node has several users. Make sure that all 5062 // of its users are from the BUILD_VECTOR node. 5063 // Constants may have multiple users. 5064 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5065 return SDValue(); 5066 break; 5067 } 5068 5069 case ISD::VECTOR_SHUFFLE: { 5070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5071 5072 // Shuffles must have a splat mask where the first element is 5073 // broadcasted. 5074 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5075 return SDValue(); 5076 5077 SDValue Sc = Op.getOperand(0); 5078 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 5079 Sc.getOpcode() != ISD::BUILD_VECTOR) { 5080 5081 if (!Subtarget->hasAVX2()) 5082 return SDValue(); 5083 5084 // Use the register form of the broadcast instruction available on AVX2. 5085 if (VT.is256BitVector()) 5086 Sc = Extract128BitVector(Sc, 0, DAG, dl); 5087 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc); 5088 } 5089 5090 Ld = Sc.getOperand(0); 5091 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5092 Ld.getOpcode() == ISD::ConstantFP); 5093 5094 // The scalar_to_vector node and the suspected 5095 // load node must have exactly one user. 5096 // Constants may have multiple users. 5097 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 5098 return SDValue(); 5099 break; 5100 } 5101 } 5102 5103 bool Is256 = VT.is256BitVector(); 5104 5105 // Handle the broadcasting a single constant scalar from the constant pool 5106 // into a vector. On Sandybridge it is still better to load a constant vector 5107 // from the constant pool and not to broadcast it from a scalar. 5108 if (ConstSplatVal && Subtarget->hasAVX2()) { 5109 EVT CVT = Ld.getValueType(); 5110 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5111 unsigned ScalarSize = CVT.getSizeInBits(); 5112 5113 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) { 5114 const Constant *C = 0; 5115 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5116 C = CI->getConstantIntValue(); 5117 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5118 C = CF->getConstantFPValue(); 5119 5120 assert(C && "Invalid constant type"); 5121 5122 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 5123 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5124 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5125 MachinePointerInfo::getConstantPool(), 5126 false, false, false, Alignment); 5127 5128 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5129 } 5130 } 5131 5132 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); 5133 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5134 5135 // Handle AVX2 in-register broadcasts. 5136 if (!IsLoad && Subtarget->hasAVX2() && 5137 (ScalarSize == 32 || (Is256 && ScalarSize == 64))) 5138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5139 5140 // The scalar source must be a normal load. 5141 if (!IsLoad) 5142 return SDValue(); 5143 5144 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) 5145 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5146 5147 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5148 // double since there is no vbroadcastsd xmm 5149 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5150 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5151 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5152 } 5153 5154 // Unsupported broadcast. 5155 return SDValue(); 5156} 5157 5158// LowerVectorFpExtend - Recognize the scalarized FP_EXTEND from v2f32 to v2f64 5159// and convert it into X86ISD::VFPEXT due to the current ISD::FP_EXTEND has the 5160// constraint of matching input/output vector elements. 5161SDValue 5162X86TargetLowering::LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const { 5163 DebugLoc DL = Op.getDebugLoc(); 5164 SDNode *N = Op.getNode(); 5165 EVT VT = Op.getValueType(); 5166 unsigned NumElts = Op.getNumOperands(); 5167 5168 // Check supported types and sub-targets. 5169 // 5170 // Only v2f32 -> v2f64 needs special handling. 5171 if (VT != MVT::v2f64 || !Subtarget->hasSSE2()) 5172 return SDValue(); 5173 5174 SDValue VecIn; 5175 EVT VecInVT; 5176 SmallVector<int, 8> Mask; 5177 EVT SrcVT = MVT::Other; 5178 5179 // Check the patterns could be translated into X86vfpext. 5180 for (unsigned i = 0; i < NumElts; ++i) { 5181 SDValue In = N->getOperand(i); 5182 unsigned Opcode = In.getOpcode(); 5183 5184 // Skip if the element is undefined. 5185 if (Opcode == ISD::UNDEF) { 5186 Mask.push_back(-1); 5187 continue; 5188 } 5189 5190 // Quit if one of the elements is not defined from 'fpext'. 5191 if (Opcode != ISD::FP_EXTEND) 5192 return SDValue(); 5193 5194 // Check how the source of 'fpext' is defined. 5195 SDValue L2In = In.getOperand(0); 5196 EVT L2InVT = L2In.getValueType(); 5197 5198 // Check the original type 5199 if (SrcVT == MVT::Other) 5200 SrcVT = L2InVT; 5201 else if (SrcVT != L2InVT) // Quit if non-homogenous typed. 5202 return SDValue(); 5203 5204 // Check whether the value being 'fpext'ed is extracted from the same 5205 // source. 5206 Opcode = L2In.getOpcode(); 5207 5208 // Quit if it's not extracted with a constant index. 5209 if (Opcode != ISD::EXTRACT_VECTOR_ELT || 5210 !isa<ConstantSDNode>(L2In.getOperand(1))) 5211 return SDValue(); 5212 5213 SDValue ExtractedFromVec = L2In.getOperand(0); 5214 5215 if (VecIn.getNode() == 0) { 5216 VecIn = ExtractedFromVec; 5217 VecInVT = ExtractedFromVec.getValueType(); 5218 } else if (VecIn != ExtractedFromVec) // Quit if built from more than 1 vec. 5219 return SDValue(); 5220 5221 Mask.push_back(cast<ConstantSDNode>(L2In.getOperand(1))->getZExtValue()); 5222 } 5223 5224 // Quit if all operands of BUILD_VECTOR are undefined. 5225 if (!VecIn.getNode()) 5226 return SDValue(); 5227 5228 // Fill the remaining mask as undef. 5229 for (unsigned i = NumElts; i < VecInVT.getVectorNumElements(); ++i) 5230 Mask.push_back(-1); 5231 5232 return DAG.getNode(X86ISD::VFPEXT, DL, VT, 5233 DAG.getVectorShuffle(VecInVT, DL, 5234 VecIn, DAG.getUNDEF(VecInVT), 5235 &Mask[0])); 5236} 5237 5238SDValue 5239X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5240 DebugLoc dl = Op.getDebugLoc(); 5241 5242 EVT VT = Op.getValueType(); 5243 EVT ExtVT = VT.getVectorElementType(); 5244 unsigned NumElems = Op.getNumOperands(); 5245 5246 // Vectors containing all zeros can be matched by pxor and xorps later 5247 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5248 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5249 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5250 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5251 return Op; 5252 5253 return getZeroVector(VT, Subtarget, DAG, dl); 5254 } 5255 5256 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5257 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5258 // vpcmpeqd on 256-bit vectors. 5259 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5260 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5261 return Op; 5262 5263 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5264 } 5265 5266 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5267 if (Broadcast.getNode()) 5268 return Broadcast; 5269 5270 SDValue FpExt = LowerVectorFpExtend(Op, DAG); 5271 if (FpExt.getNode()) 5272 return FpExt; 5273 5274 unsigned EVTBits = ExtVT.getSizeInBits(); 5275 5276 unsigned NumZero = 0; 5277 unsigned NumNonZero = 0; 5278 unsigned NonZeros = 0; 5279 bool IsAllConstants = true; 5280 SmallSet<SDValue, 8> Values; 5281 for (unsigned i = 0; i < NumElems; ++i) { 5282 SDValue Elt = Op.getOperand(i); 5283 if (Elt.getOpcode() == ISD::UNDEF) 5284 continue; 5285 Values.insert(Elt); 5286 if (Elt.getOpcode() != ISD::Constant && 5287 Elt.getOpcode() != ISD::ConstantFP) 5288 IsAllConstants = false; 5289 if (X86::isZeroNode(Elt)) 5290 NumZero++; 5291 else { 5292 NonZeros |= (1 << i); 5293 NumNonZero++; 5294 } 5295 } 5296 5297 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5298 if (NumNonZero == 0) 5299 return DAG.getUNDEF(VT); 5300 5301 // Special case for single non-zero, non-undef, element. 5302 if (NumNonZero == 1) { 5303 unsigned Idx = CountTrailingZeros_32(NonZeros); 5304 SDValue Item = Op.getOperand(Idx); 5305 5306 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5307 // the value are obviously zero, truncate the value to i32 and do the 5308 // insertion that way. Only do this if the value is non-constant or if the 5309 // value is a constant being inserted into element 0. It is cheaper to do 5310 // a constant pool load than it is to do a movd + shuffle. 5311 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5312 (!IsAllConstants || Idx == 0)) { 5313 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5314 // Handle SSE only. 5315 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5316 EVT VecVT = MVT::v4i32; 5317 unsigned VecElts = 4; 5318 5319 // Truncate the value (which may itself be a constant) to i32, and 5320 // convert it to a vector with movd (S2V+shuffle to zero extend). 5321 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5322 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5323 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5324 5325 // Now we have our 32-bit value zero extended in the low element of 5326 // a vector. If Idx != 0, swizzle it into place. 5327 if (Idx != 0) { 5328 SmallVector<int, 4> Mask; 5329 Mask.push_back(Idx); 5330 for (unsigned i = 1; i != VecElts; ++i) 5331 Mask.push_back(i); 5332 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5333 &Mask[0]); 5334 } 5335 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5336 } 5337 } 5338 5339 // If we have a constant or non-constant insertion into the low element of 5340 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5341 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5342 // depending on what the source datatype is. 5343 if (Idx == 0) { 5344 if (NumZero == 0) 5345 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5346 5347 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5348 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5349 if (VT.is256BitVector()) { 5350 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5351 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5352 Item, DAG.getIntPtrConstant(0)); 5353 } 5354 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5355 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5356 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5357 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5358 } 5359 5360 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5361 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5362 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5363 if (VT.is256BitVector()) { 5364 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5365 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5366 } else { 5367 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5368 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5369 } 5370 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5371 } 5372 } 5373 5374 // Is it a vector logical left shift? 5375 if (NumElems == 2 && Idx == 1 && 5376 X86::isZeroNode(Op.getOperand(0)) && 5377 !X86::isZeroNode(Op.getOperand(1))) { 5378 unsigned NumBits = VT.getSizeInBits(); 5379 return getVShift(true, VT, 5380 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5381 VT, Op.getOperand(1)), 5382 NumBits/2, DAG, *this, dl); 5383 } 5384 5385 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5386 return SDValue(); 5387 5388 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5389 // is a non-constant being inserted into an element other than the low one, 5390 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5391 // movd/movss) to move this into the low element, then shuffle it into 5392 // place. 5393 if (EVTBits == 32) { 5394 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5395 5396 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5397 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5398 SmallVector<int, 8> MaskVec; 5399 for (unsigned i = 0; i != NumElems; ++i) 5400 MaskVec.push_back(i == Idx ? 0 : 1); 5401 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5402 } 5403 } 5404 5405 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5406 if (Values.size() == 1) { 5407 if (EVTBits == 32) { 5408 // Instead of a shuffle like this: 5409 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5410 // Check if it's possible to issue this instead. 5411 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5412 unsigned Idx = CountTrailingZeros_32(NonZeros); 5413 SDValue Item = Op.getOperand(Idx); 5414 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5415 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5416 } 5417 return SDValue(); 5418 } 5419 5420 // A vector full of immediates; various special cases are already 5421 // handled, so this is best done with a single constant-pool load. 5422 if (IsAllConstants) 5423 return SDValue(); 5424 5425 // For AVX-length vectors, build the individual 128-bit pieces and use 5426 // shuffles to put them in place. 5427 if (VT.is256BitVector()) { 5428 SmallVector<SDValue, 32> V; 5429 for (unsigned i = 0; i != NumElems; ++i) 5430 V.push_back(Op.getOperand(i)); 5431 5432 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5433 5434 // Build both the lower and upper subvector. 5435 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5436 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5437 NumElems/2); 5438 5439 // Recreate the wider vector with the lower and upper part. 5440 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5441 } 5442 5443 // Let legalizer expand 2-wide build_vectors. 5444 if (EVTBits == 64) { 5445 if (NumNonZero == 1) { 5446 // One half is zero or undef. 5447 unsigned Idx = CountTrailingZeros_32(NonZeros); 5448 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5449 Op.getOperand(Idx)); 5450 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5451 } 5452 return SDValue(); 5453 } 5454 5455 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5456 if (EVTBits == 8 && NumElems == 16) { 5457 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5458 Subtarget, *this); 5459 if (V.getNode()) return V; 5460 } 5461 5462 if (EVTBits == 16 && NumElems == 8) { 5463 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5464 Subtarget, *this); 5465 if (V.getNode()) return V; 5466 } 5467 5468 // If element VT is == 32 bits, turn it into a number of shuffles. 5469 SmallVector<SDValue, 8> V(NumElems); 5470 if (NumElems == 4 && NumZero > 0) { 5471 for (unsigned i = 0; i < 4; ++i) { 5472 bool isZero = !(NonZeros & (1 << i)); 5473 if (isZero) 5474 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5475 else 5476 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5477 } 5478 5479 for (unsigned i = 0; i < 2; ++i) { 5480 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5481 default: break; 5482 case 0: 5483 V[i] = V[i*2]; // Must be a zero vector. 5484 break; 5485 case 1: 5486 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5487 break; 5488 case 2: 5489 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5490 break; 5491 case 3: 5492 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5493 break; 5494 } 5495 } 5496 5497 bool Reverse1 = (NonZeros & 0x3) == 2; 5498 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5499 int MaskVec[] = { 5500 Reverse1 ? 1 : 0, 5501 Reverse1 ? 0 : 1, 5502 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5503 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5504 }; 5505 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5506 } 5507 5508 if (Values.size() > 1 && VT.is128BitVector()) { 5509 // Check for a build vector of consecutive loads. 5510 for (unsigned i = 0; i < NumElems; ++i) 5511 V[i] = Op.getOperand(i); 5512 5513 // Check for elements which are consecutive loads. 5514 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5515 if (LD.getNode()) 5516 return LD; 5517 5518 // For SSE 4.1, use insertps to put the high elements into the low element. 5519 if (getSubtarget()->hasSSE41()) { 5520 SDValue Result; 5521 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5522 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5523 else 5524 Result = DAG.getUNDEF(VT); 5525 5526 for (unsigned i = 1; i < NumElems; ++i) { 5527 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5528 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5529 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5530 } 5531 return Result; 5532 } 5533 5534 // Otherwise, expand into a number of unpckl*, start by extending each of 5535 // our (non-undef) elements to the full vector width with the element in the 5536 // bottom slot of the vector (which generates no code for SSE). 5537 for (unsigned i = 0; i < NumElems; ++i) { 5538 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5539 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5540 else 5541 V[i] = DAG.getUNDEF(VT); 5542 } 5543 5544 // Next, we iteratively mix elements, e.g. for v4f32: 5545 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5546 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5547 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5548 unsigned EltStride = NumElems >> 1; 5549 while (EltStride != 0) { 5550 for (unsigned i = 0; i < EltStride; ++i) { 5551 // If V[i+EltStride] is undef and this is the first round of mixing, 5552 // then it is safe to just drop this shuffle: V[i] is already in the 5553 // right place, the one element (since it's the first round) being 5554 // inserted as undef can be dropped. This isn't safe for successive 5555 // rounds because they will permute elements within both vectors. 5556 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5557 EltStride == NumElems/2) 5558 continue; 5559 5560 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5561 } 5562 EltStride >>= 1; 5563 } 5564 return V[0]; 5565 } 5566 return SDValue(); 5567} 5568 5569// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5570// to create 256-bit vectors from two other 128-bit ones. 5571static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5572 DebugLoc dl = Op.getDebugLoc(); 5573 EVT ResVT = Op.getValueType(); 5574 5575 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide"); 5576 5577 SDValue V1 = Op.getOperand(0); 5578 SDValue V2 = Op.getOperand(1); 5579 unsigned NumElems = ResVT.getVectorNumElements(); 5580 5581 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5582} 5583 5584static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5585 assert(Op.getNumOperands() == 2); 5586 5587 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5588 // from two other 128-bit ones. 5589 return LowerAVXCONCAT_VECTORS(Op, DAG); 5590} 5591 5592// Try to lower a shuffle node into a simple blend instruction. 5593static SDValue 5594LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5595 const X86Subtarget *Subtarget, SelectionDAG &DAG) { 5596 SDValue V1 = SVOp->getOperand(0); 5597 SDValue V2 = SVOp->getOperand(1); 5598 DebugLoc dl = SVOp->getDebugLoc(); 5599 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5600 unsigned NumElems = VT.getVectorNumElements(); 5601 5602 if (!Subtarget->hasSSE41()) 5603 return SDValue(); 5604 5605 unsigned ISDNo = 0; 5606 MVT OpTy; 5607 5608 switch (VT.SimpleTy) { 5609 default: return SDValue(); 5610 case MVT::v8i16: 5611 ISDNo = X86ISD::BLENDPW; 5612 OpTy = MVT::v8i16; 5613 break; 5614 case MVT::v4i32: 5615 case MVT::v4f32: 5616 ISDNo = X86ISD::BLENDPS; 5617 OpTy = MVT::v4f32; 5618 break; 5619 case MVT::v2i64: 5620 case MVT::v2f64: 5621 ISDNo = X86ISD::BLENDPD; 5622 OpTy = MVT::v2f64; 5623 break; 5624 case MVT::v8i32: 5625 case MVT::v8f32: 5626 if (!Subtarget->hasAVX()) 5627 return SDValue(); 5628 ISDNo = X86ISD::BLENDPS; 5629 OpTy = MVT::v8f32; 5630 break; 5631 case MVT::v4i64: 5632 case MVT::v4f64: 5633 if (!Subtarget->hasAVX()) 5634 return SDValue(); 5635 ISDNo = X86ISD::BLENDPD; 5636 OpTy = MVT::v4f64; 5637 break; 5638 } 5639 assert(ISDNo && "Invalid Op Number"); 5640 5641 unsigned MaskVals = 0; 5642 5643 for (unsigned i = 0; i != NumElems; ++i) { 5644 int EltIdx = SVOp->getMaskElt(i); 5645 if (EltIdx == (int)i || EltIdx < 0) 5646 MaskVals |= (1<<i); 5647 else if (EltIdx == (int)(i + NumElems)) 5648 continue; // Bit is set to zero; 5649 else 5650 return SDValue(); 5651 } 5652 5653 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5654 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5655 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5656 DAG.getConstant(MaskVals, MVT::i32)); 5657 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5658} 5659 5660// v8i16 shuffles - Prefer shuffles in the following order: 5661// 1. [all] pshuflw, pshufhw, optional move 5662// 2. [ssse3] 1 x pshufb 5663// 3. [ssse3] 2 x pshufb + 1 x por 5664// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5665static SDValue 5666LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, 5667 SelectionDAG &DAG) { 5668 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5669 SDValue V1 = SVOp->getOperand(0); 5670 SDValue V2 = SVOp->getOperand(1); 5671 DebugLoc dl = SVOp->getDebugLoc(); 5672 SmallVector<int, 8> MaskVals; 5673 5674 // Determine if more than 1 of the words in each of the low and high quadwords 5675 // of the result come from the same quadword of one of the two inputs. Undef 5676 // mask values count as coming from any quadword, for better codegen. 5677 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5678 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5679 std::bitset<4> InputQuads; 5680 for (unsigned i = 0; i < 8; ++i) { 5681 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5682 int EltIdx = SVOp->getMaskElt(i); 5683 MaskVals.push_back(EltIdx); 5684 if (EltIdx < 0) { 5685 ++Quad[0]; 5686 ++Quad[1]; 5687 ++Quad[2]; 5688 ++Quad[3]; 5689 continue; 5690 } 5691 ++Quad[EltIdx / 4]; 5692 InputQuads.set(EltIdx / 4); 5693 } 5694 5695 int BestLoQuad = -1; 5696 unsigned MaxQuad = 1; 5697 for (unsigned i = 0; i < 4; ++i) { 5698 if (LoQuad[i] > MaxQuad) { 5699 BestLoQuad = i; 5700 MaxQuad = LoQuad[i]; 5701 } 5702 } 5703 5704 int BestHiQuad = -1; 5705 MaxQuad = 1; 5706 for (unsigned i = 0; i < 4; ++i) { 5707 if (HiQuad[i] > MaxQuad) { 5708 BestHiQuad = i; 5709 MaxQuad = HiQuad[i]; 5710 } 5711 } 5712 5713 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5714 // of the two input vectors, shuffle them into one input vector so only a 5715 // single pshufb instruction is necessary. If There are more than 2 input 5716 // quads, disable the next transformation since it does not help SSSE3. 5717 bool V1Used = InputQuads[0] || InputQuads[1]; 5718 bool V2Used = InputQuads[2] || InputQuads[3]; 5719 if (Subtarget->hasSSSE3()) { 5720 if (InputQuads.count() == 2 && V1Used && V2Used) { 5721 BestLoQuad = InputQuads[0] ? 0 : 1; 5722 BestHiQuad = InputQuads[2] ? 2 : 3; 5723 } 5724 if (InputQuads.count() > 2) { 5725 BestLoQuad = -1; 5726 BestHiQuad = -1; 5727 } 5728 } 5729 5730 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5731 // the shuffle mask. If a quad is scored as -1, that means that it contains 5732 // words from all 4 input quadwords. 5733 SDValue NewV; 5734 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5735 int MaskV[] = { 5736 BestLoQuad < 0 ? 0 : BestLoQuad, 5737 BestHiQuad < 0 ? 1 : BestHiQuad 5738 }; 5739 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5740 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5741 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5742 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5743 5744 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5745 // source words for the shuffle, to aid later transformations. 5746 bool AllWordsInNewV = true; 5747 bool InOrder[2] = { true, true }; 5748 for (unsigned i = 0; i != 8; ++i) { 5749 int idx = MaskVals[i]; 5750 if (idx != (int)i) 5751 InOrder[i/4] = false; 5752 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5753 continue; 5754 AllWordsInNewV = false; 5755 break; 5756 } 5757 5758 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5759 if (AllWordsInNewV) { 5760 for (int i = 0; i != 8; ++i) { 5761 int idx = MaskVals[i]; 5762 if (idx < 0) 5763 continue; 5764 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5765 if ((idx != i) && idx < 4) 5766 pshufhw = false; 5767 if ((idx != i) && idx > 3) 5768 pshuflw = false; 5769 } 5770 V1 = NewV; 5771 V2Used = false; 5772 BestLoQuad = 0; 5773 BestHiQuad = 1; 5774 } 5775 5776 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5777 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5778 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5779 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5780 unsigned TargetMask = 0; 5781 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5782 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5783 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5784 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5785 getShufflePSHUFLWImmediate(SVOp); 5786 V1 = NewV.getOperand(0); 5787 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5788 } 5789 } 5790 5791 // If we have SSSE3, and all words of the result are from 1 input vector, 5792 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5793 // is present, fall back to case 4. 5794 if (Subtarget->hasSSSE3()) { 5795 SmallVector<SDValue,16> pshufbMask; 5796 5797 // If we have elements from both input vectors, set the high bit of the 5798 // shuffle mask element to zero out elements that come from V2 in the V1 5799 // mask, and elements that come from V1 in the V2 mask, so that the two 5800 // results can be OR'd together. 5801 bool TwoInputs = V1Used && V2Used; 5802 for (unsigned i = 0; i != 8; ++i) { 5803 int EltIdx = MaskVals[i] * 2; 5804 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx; 5805 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1; 5806 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5807 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5808 } 5809 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5810 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5811 DAG.getNode(ISD::BUILD_VECTOR, dl, 5812 MVT::v16i8, &pshufbMask[0], 16)); 5813 if (!TwoInputs) 5814 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5815 5816 // Calculate the shuffle mask for the second input, shuffle it, and 5817 // OR it with the first shuffled input. 5818 pshufbMask.clear(); 5819 for (unsigned i = 0; i != 8; ++i) { 5820 int EltIdx = MaskVals[i] * 2; 5821 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5822 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15; 5823 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5824 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5825 } 5826 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5827 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5828 DAG.getNode(ISD::BUILD_VECTOR, dl, 5829 MVT::v16i8, &pshufbMask[0], 16)); 5830 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5831 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5832 } 5833 5834 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5835 // and update MaskVals with new element order. 5836 std::bitset<8> InOrder; 5837 if (BestLoQuad >= 0) { 5838 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5839 for (int i = 0; i != 4; ++i) { 5840 int idx = MaskVals[i]; 5841 if (idx < 0) { 5842 InOrder.set(i); 5843 } else if ((idx / 4) == BestLoQuad) { 5844 MaskV[i] = idx & 3; 5845 InOrder.set(i); 5846 } 5847 } 5848 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5849 &MaskV[0]); 5850 5851 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5852 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5853 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5854 NewV.getOperand(0), 5855 getShufflePSHUFLWImmediate(SVOp), DAG); 5856 } 5857 } 5858 5859 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5860 // and update MaskVals with the new element order. 5861 if (BestHiQuad >= 0) { 5862 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5863 for (unsigned i = 4; i != 8; ++i) { 5864 int idx = MaskVals[i]; 5865 if (idx < 0) { 5866 InOrder.set(i); 5867 } else if ((idx / 4) == BestHiQuad) { 5868 MaskV[i] = (idx & 3) + 4; 5869 InOrder.set(i); 5870 } 5871 } 5872 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5873 &MaskV[0]); 5874 5875 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5876 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5877 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5878 NewV.getOperand(0), 5879 getShufflePSHUFHWImmediate(SVOp), DAG); 5880 } 5881 } 5882 5883 // In case BestHi & BestLo were both -1, which means each quadword has a word 5884 // from each of the four input quadwords, calculate the InOrder bitvector now 5885 // before falling through to the insert/extract cleanup. 5886 if (BestLoQuad == -1 && BestHiQuad == -1) { 5887 NewV = V1; 5888 for (int i = 0; i != 8; ++i) 5889 if (MaskVals[i] < 0 || MaskVals[i] == i) 5890 InOrder.set(i); 5891 } 5892 5893 // The other elements are put in the right place using pextrw and pinsrw. 5894 for (unsigned i = 0; i != 8; ++i) { 5895 if (InOrder[i]) 5896 continue; 5897 int EltIdx = MaskVals[i]; 5898 if (EltIdx < 0) 5899 continue; 5900 SDValue ExtOp = (EltIdx < 8) ? 5901 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5902 DAG.getIntPtrConstant(EltIdx)) : 5903 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5904 DAG.getIntPtrConstant(EltIdx - 8)); 5905 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5906 DAG.getIntPtrConstant(i)); 5907 } 5908 return NewV; 5909} 5910 5911// v16i8 shuffles - Prefer shuffles in the following order: 5912// 1. [ssse3] 1 x pshufb 5913// 2. [ssse3] 2 x pshufb + 1 x por 5914// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5915static 5916SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5917 SelectionDAG &DAG, 5918 const X86TargetLowering &TLI) { 5919 SDValue V1 = SVOp->getOperand(0); 5920 SDValue V2 = SVOp->getOperand(1); 5921 DebugLoc dl = SVOp->getDebugLoc(); 5922 ArrayRef<int> MaskVals = SVOp->getMask(); 5923 5924 // If we have SSSE3, case 1 is generated when all result bytes come from 5925 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5926 // present, fall back to case 3. 5927 5928 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5929 if (TLI.getSubtarget()->hasSSSE3()) { 5930 SmallVector<SDValue,16> pshufbMask; 5931 5932 // If all result elements are from one input vector, then only translate 5933 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5934 // 5935 // Otherwise, we have elements from both input vectors, and must zero out 5936 // elements that come from V2 in the first mask, and V1 in the second mask 5937 // so that we can OR them together. 5938 for (unsigned i = 0; i != 16; ++i) { 5939 int EltIdx = MaskVals[i]; 5940 if (EltIdx < 0 || EltIdx >= 16) 5941 EltIdx = 0x80; 5942 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5943 } 5944 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5945 DAG.getNode(ISD::BUILD_VECTOR, dl, 5946 MVT::v16i8, &pshufbMask[0], 16)); 5947 5948 // As PSHUFB will zero elements with negative indices, it's safe to ignore 5949 // the 2nd operand if it's undefined or zero. 5950 if (V2.getOpcode() == ISD::UNDEF || 5951 ISD::isBuildVectorAllZeros(V2.getNode())) 5952 return V1; 5953 5954 // Calculate the shuffle mask for the second input, shuffle it, and 5955 // OR it with the first shuffled input. 5956 pshufbMask.clear(); 5957 for (unsigned i = 0; i != 16; ++i) { 5958 int EltIdx = MaskVals[i]; 5959 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5960 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5961 } 5962 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5963 DAG.getNode(ISD::BUILD_VECTOR, dl, 5964 MVT::v16i8, &pshufbMask[0], 16)); 5965 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5966 } 5967 5968 // No SSSE3 - Calculate in place words and then fix all out of place words 5969 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5970 // the 16 different words that comprise the two doublequadword input vectors. 5971 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5972 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5973 SDValue NewV = V1; 5974 for (int i = 0; i != 8; ++i) { 5975 int Elt0 = MaskVals[i*2]; 5976 int Elt1 = MaskVals[i*2+1]; 5977 5978 // This word of the result is all undef, skip it. 5979 if (Elt0 < 0 && Elt1 < 0) 5980 continue; 5981 5982 // This word of the result is already in the correct place, skip it. 5983 if ((Elt0 == i*2) && (Elt1 == i*2+1)) 5984 continue; 5985 5986 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5987 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5988 SDValue InsElt; 5989 5990 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5991 // using a single extract together, load it and store it. 5992 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5993 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5994 DAG.getIntPtrConstant(Elt1 / 2)); 5995 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5996 DAG.getIntPtrConstant(i)); 5997 continue; 5998 } 5999 6000 // If Elt1 is defined, extract it from the appropriate source. If the 6001 // source byte is not also odd, shift the extracted word left 8 bits 6002 // otherwise clear the bottom 8 bits if we need to do an or. 6003 if (Elt1 >= 0) { 6004 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6005 DAG.getIntPtrConstant(Elt1 / 2)); 6006 if ((Elt1 & 1) == 0) 6007 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 6008 DAG.getConstant(8, 6009 TLI.getShiftAmountTy(InsElt.getValueType()))); 6010 else if (Elt0 >= 0) 6011 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 6012 DAG.getConstant(0xFF00, MVT::i16)); 6013 } 6014 // If Elt0 is defined, extract it from the appropriate source. If the 6015 // source byte is not also even, shift the extracted word right 8 bits. If 6016 // Elt1 was also defined, OR the extracted values together before 6017 // inserting them in the result. 6018 if (Elt0 >= 0) { 6019 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 6020 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 6021 if ((Elt0 & 1) != 0) 6022 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 6023 DAG.getConstant(8, 6024 TLI.getShiftAmountTy(InsElt0.getValueType()))); 6025 else if (Elt1 >= 0) 6026 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 6027 DAG.getConstant(0x00FF, MVT::i16)); 6028 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 6029 : InsElt0; 6030 } 6031 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6032 DAG.getIntPtrConstant(i)); 6033 } 6034 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 6035} 6036 6037// v32i8 shuffles - Translate to VPSHUFB if possible. 6038static 6039SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, 6040 const X86Subtarget *Subtarget, 6041 SelectionDAG &DAG) { 6042 EVT VT = SVOp->getValueType(0); 6043 SDValue V1 = SVOp->getOperand(0); 6044 SDValue V2 = SVOp->getOperand(1); 6045 DebugLoc dl = SVOp->getDebugLoc(); 6046 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end()); 6047 6048 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6049 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode()); 6050 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode()); 6051 6052 // VPSHUFB may be generated if 6053 // (1) one of input vector is undefined or zeroinitializer. 6054 // The mask value 0x80 puts 0 in the corresponding slot of the vector. 6055 // And (2) the mask indexes don't cross the 128-bit lane. 6056 if (VT != MVT::v32i8 || !Subtarget->hasAVX2() || 6057 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero)) 6058 return SDValue(); 6059 6060 if (V1IsAllZero && !V2IsAllZero) { 6061 CommuteVectorShuffleMask(MaskVals, 32); 6062 V1 = V2; 6063 } 6064 SmallVector<SDValue, 32> pshufbMask; 6065 for (unsigned i = 0; i != 32; i++) { 6066 int EltIdx = MaskVals[i]; 6067 if (EltIdx < 0 || EltIdx >= 32) 6068 EltIdx = 0x80; 6069 else { 6070 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16)) 6071 // Cross lane is not allowed. 6072 return SDValue(); 6073 EltIdx &= 0xf; 6074 } 6075 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6076 } 6077 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1, 6078 DAG.getNode(ISD::BUILD_VECTOR, dl, 6079 MVT::v32i8, &pshufbMask[0], 32)); 6080} 6081 6082/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 6083/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 6084/// done when every pair / quad of shuffle mask elements point to elements in 6085/// the right sequence. e.g. 6086/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 6087static 6088SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 6089 SelectionDAG &DAG, DebugLoc dl) { 6090 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6091 unsigned NumElems = VT.getVectorNumElements(); 6092 MVT NewVT; 6093 unsigned Scale; 6094 switch (VT.SimpleTy) { 6095 default: llvm_unreachable("Unexpected!"); 6096 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 6097 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 6098 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 6099 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 6100 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 6101 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 6102 } 6103 6104 SmallVector<int, 8> MaskVec; 6105 for (unsigned i = 0; i != NumElems; i += Scale) { 6106 int StartIdx = -1; 6107 for (unsigned j = 0; j != Scale; ++j) { 6108 int EltIdx = SVOp->getMaskElt(i+j); 6109 if (EltIdx < 0) 6110 continue; 6111 if (StartIdx < 0) 6112 StartIdx = (EltIdx / Scale); 6113 if (EltIdx != (int)(StartIdx*Scale + j)) 6114 return SDValue(); 6115 } 6116 MaskVec.push_back(StartIdx); 6117 } 6118 6119 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 6120 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 6121 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6122} 6123 6124/// getVZextMovL - Return a zero-extending vector move low node. 6125/// 6126static SDValue getVZextMovL(EVT VT, EVT OpVT, 6127 SDValue SrcOp, SelectionDAG &DAG, 6128 const X86Subtarget *Subtarget, DebugLoc dl) { 6129 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6130 LoadSDNode *LD = NULL; 6131 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6132 LD = dyn_cast<LoadSDNode>(SrcOp); 6133 if (!LD) { 6134 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6135 // instead. 6136 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6137 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6138 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6139 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6140 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6141 // PR2108 6142 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6143 return DAG.getNode(ISD::BITCAST, dl, VT, 6144 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6145 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6146 OpVT, 6147 SrcOp.getOperand(0) 6148 .getOperand(0)))); 6149 } 6150 } 6151 } 6152 6153 return DAG.getNode(ISD::BITCAST, dl, VT, 6154 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6155 DAG.getNode(ISD::BITCAST, dl, 6156 OpVT, SrcOp))); 6157} 6158 6159/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6160/// which could not be matched by any known target speficic shuffle 6161static SDValue 6162LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6163 6164 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); 6165 if (NewOp.getNode()) 6166 return NewOp; 6167 6168 EVT VT = SVOp->getValueType(0); 6169 6170 unsigned NumElems = VT.getVectorNumElements(); 6171 unsigned NumLaneElems = NumElems / 2; 6172 6173 DebugLoc dl = SVOp->getDebugLoc(); 6174 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 6175 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 6176 SDValue Output[2]; 6177 6178 SmallVector<int, 16> Mask; 6179 for (unsigned l = 0; l < 2; ++l) { 6180 // Build a shuffle mask for the output, discovering on the fly which 6181 // input vectors to use as shuffle operands (recorded in InputUsed). 6182 // If building a suitable shuffle vector proves too hard, then bail 6183 // out with UseBuildVector set. 6184 bool UseBuildVector = false; 6185 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6186 unsigned LaneStart = l * NumLaneElems; 6187 for (unsigned i = 0; i != NumLaneElems; ++i) { 6188 // The mask element. This indexes into the input. 6189 int Idx = SVOp->getMaskElt(i+LaneStart); 6190 if (Idx < 0) { 6191 // the mask element does not index into any input vector. 6192 Mask.push_back(-1); 6193 continue; 6194 } 6195 6196 // The input vector this mask element indexes into. 6197 int Input = Idx / NumLaneElems; 6198 6199 // Turn the index into an offset from the start of the input vector. 6200 Idx -= Input * NumLaneElems; 6201 6202 // Find or create a shuffle vector operand to hold this input. 6203 unsigned OpNo; 6204 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6205 if (InputUsed[OpNo] == Input) 6206 // This input vector is already an operand. 6207 break; 6208 if (InputUsed[OpNo] < 0) { 6209 // Create a new operand for this input vector. 6210 InputUsed[OpNo] = Input; 6211 break; 6212 } 6213 } 6214 6215 if (OpNo >= array_lengthof(InputUsed)) { 6216 // More than two input vectors used! Give up on trying to create a 6217 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 6218 UseBuildVector = true; 6219 break; 6220 } 6221 6222 // Add the mask index for the new shuffle vector. 6223 Mask.push_back(Idx + OpNo * NumLaneElems); 6224 } 6225 6226 if (UseBuildVector) { 6227 SmallVector<SDValue, 16> SVOps; 6228 for (unsigned i = 0; i != NumLaneElems; ++i) { 6229 // The mask element. This indexes into the input. 6230 int Idx = SVOp->getMaskElt(i+LaneStart); 6231 if (Idx < 0) { 6232 SVOps.push_back(DAG.getUNDEF(EltVT)); 6233 continue; 6234 } 6235 6236 // The input vector this mask element indexes into. 6237 int Input = Idx / NumElems; 6238 6239 // Turn the index into an offset from the start of the input vector. 6240 Idx -= Input * NumElems; 6241 6242 // Extract the vector element by hand. 6243 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 6244 SVOp->getOperand(Input), 6245 DAG.getIntPtrConstant(Idx))); 6246 } 6247 6248 // Construct the output using a BUILD_VECTOR. 6249 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0], 6250 SVOps.size()); 6251 } else if (InputUsed[0] < 0) { 6252 // No input vectors were used! The result is undefined. 6253 Output[l] = DAG.getUNDEF(NVT); 6254 } else { 6255 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6256 (InputUsed[0] % 2) * NumLaneElems, 6257 DAG, dl); 6258 // If only one input was used, use an undefined vector for the other. 6259 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6260 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6261 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6262 // At least one input vector was used. Create a new shuffle vector. 6263 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6264 } 6265 6266 Mask.clear(); 6267 } 6268 6269 // Concatenate the result back 6270 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); 6271} 6272 6273/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6274/// 4 elements, and match them with several different shuffle types. 6275static SDValue 6276LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6277 SDValue V1 = SVOp->getOperand(0); 6278 SDValue V2 = SVOp->getOperand(1); 6279 DebugLoc dl = SVOp->getDebugLoc(); 6280 EVT VT = SVOp->getValueType(0); 6281 6282 assert(VT.is128BitVector() && "Unsupported vector size"); 6283 6284 std::pair<int, int> Locs[4]; 6285 int Mask1[] = { -1, -1, -1, -1 }; 6286 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6287 6288 unsigned NumHi = 0; 6289 unsigned NumLo = 0; 6290 for (unsigned i = 0; i != 4; ++i) { 6291 int Idx = PermMask[i]; 6292 if (Idx < 0) { 6293 Locs[i] = std::make_pair(-1, -1); 6294 } else { 6295 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6296 if (Idx < 4) { 6297 Locs[i] = std::make_pair(0, NumLo); 6298 Mask1[NumLo] = Idx; 6299 NumLo++; 6300 } else { 6301 Locs[i] = std::make_pair(1, NumHi); 6302 if (2+NumHi < 4) 6303 Mask1[2+NumHi] = Idx; 6304 NumHi++; 6305 } 6306 } 6307 } 6308 6309 if (NumLo <= 2 && NumHi <= 2) { 6310 // If no more than two elements come from either vector. This can be 6311 // implemented with two shuffles. First shuffle gather the elements. 6312 // The second shuffle, which takes the first shuffle as both of its 6313 // vector operands, put the elements into the right order. 6314 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6315 6316 int Mask2[] = { -1, -1, -1, -1 }; 6317 6318 for (unsigned i = 0; i != 4; ++i) 6319 if (Locs[i].first != -1) { 6320 unsigned Idx = (i < 2) ? 0 : 4; 6321 Idx += Locs[i].first * 2 + Locs[i].second; 6322 Mask2[i] = Idx; 6323 } 6324 6325 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6326 } 6327 6328 if (NumLo == 3 || NumHi == 3) { 6329 // Otherwise, we must have three elements from one vector, call it X, and 6330 // one element from the other, call it Y. First, use a shufps to build an 6331 // intermediate vector with the one element from Y and the element from X 6332 // that will be in the same half in the final destination (the indexes don't 6333 // matter). Then, use a shufps to build the final vector, taking the half 6334 // containing the element from Y from the intermediate, and the other half 6335 // from X. 6336 if (NumHi == 3) { 6337 // Normalize it so the 3 elements come from V1. 6338 CommuteVectorShuffleMask(PermMask, 4); 6339 std::swap(V1, V2); 6340 } 6341 6342 // Find the element from V2. 6343 unsigned HiIndex; 6344 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6345 int Val = PermMask[HiIndex]; 6346 if (Val < 0) 6347 continue; 6348 if (Val >= 4) 6349 break; 6350 } 6351 6352 Mask1[0] = PermMask[HiIndex]; 6353 Mask1[1] = -1; 6354 Mask1[2] = PermMask[HiIndex^1]; 6355 Mask1[3] = -1; 6356 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6357 6358 if (HiIndex >= 2) { 6359 Mask1[0] = PermMask[0]; 6360 Mask1[1] = PermMask[1]; 6361 Mask1[2] = HiIndex & 1 ? 6 : 4; 6362 Mask1[3] = HiIndex & 1 ? 4 : 6; 6363 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6364 } 6365 6366 Mask1[0] = HiIndex & 1 ? 2 : 0; 6367 Mask1[1] = HiIndex & 1 ? 0 : 2; 6368 Mask1[2] = PermMask[2]; 6369 Mask1[3] = PermMask[3]; 6370 if (Mask1[2] >= 0) 6371 Mask1[2] += 4; 6372 if (Mask1[3] >= 0) 6373 Mask1[3] += 4; 6374 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6375 } 6376 6377 // Break it into (shuffle shuffle_hi, shuffle_lo). 6378 int LoMask[] = { -1, -1, -1, -1 }; 6379 int HiMask[] = { -1, -1, -1, -1 }; 6380 6381 int *MaskPtr = LoMask; 6382 unsigned MaskIdx = 0; 6383 unsigned LoIdx = 0; 6384 unsigned HiIdx = 2; 6385 for (unsigned i = 0; i != 4; ++i) { 6386 if (i == 2) { 6387 MaskPtr = HiMask; 6388 MaskIdx = 1; 6389 LoIdx = 0; 6390 HiIdx = 2; 6391 } 6392 int Idx = PermMask[i]; 6393 if (Idx < 0) { 6394 Locs[i] = std::make_pair(-1, -1); 6395 } else if (Idx < 4) { 6396 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6397 MaskPtr[LoIdx] = Idx; 6398 LoIdx++; 6399 } else { 6400 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6401 MaskPtr[HiIdx] = Idx; 6402 HiIdx++; 6403 } 6404 } 6405 6406 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6407 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6408 int MaskOps[] = { -1, -1, -1, -1 }; 6409 for (unsigned i = 0; i != 4; ++i) 6410 if (Locs[i].first != -1) 6411 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6412 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6413} 6414 6415static bool MayFoldVectorLoad(SDValue V) { 6416 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6417 V = V.getOperand(0); 6418 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6419 V = V.getOperand(0); 6420 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6421 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6422 // BUILD_VECTOR (load), undef 6423 V = V.getOperand(0); 6424 if (MayFoldLoad(V)) 6425 return true; 6426 return false; 6427} 6428 6429// FIXME: the version above should always be used. Since there's 6430// a bug where several vector shuffles can't be folded because the 6431// DAG is not updated during lowering and a node claims to have two 6432// uses while it only has one, use this version, and let isel match 6433// another instruction if the load really happens to have more than 6434// one use. Remove this version after this bug get fixed. 6435// rdar://8434668, PR8156 6436static bool RelaxedMayFoldVectorLoad(SDValue V) { 6437 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6438 V = V.getOperand(0); 6439 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6440 V = V.getOperand(0); 6441 if (ISD::isNormalLoad(V.getNode())) 6442 return true; 6443 return false; 6444} 6445 6446static 6447SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6448 EVT VT = Op.getValueType(); 6449 6450 // Canonizalize to v2f64. 6451 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6452 return DAG.getNode(ISD::BITCAST, dl, VT, 6453 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6454 V1, DAG)); 6455} 6456 6457static 6458SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6459 bool HasSSE2) { 6460 SDValue V1 = Op.getOperand(0); 6461 SDValue V2 = Op.getOperand(1); 6462 EVT VT = Op.getValueType(); 6463 6464 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6465 6466 if (HasSSE2 && VT == MVT::v2f64) 6467 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6468 6469 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6470 return DAG.getNode(ISD::BITCAST, dl, VT, 6471 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6472 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6473 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6474} 6475 6476static 6477SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6478 SDValue V1 = Op.getOperand(0); 6479 SDValue V2 = Op.getOperand(1); 6480 EVT VT = Op.getValueType(); 6481 6482 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6483 "unsupported shuffle type"); 6484 6485 if (V2.getOpcode() == ISD::UNDEF) 6486 V2 = V1; 6487 6488 // v4i32 or v4f32 6489 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6490} 6491 6492static 6493SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6494 SDValue V1 = Op.getOperand(0); 6495 SDValue V2 = Op.getOperand(1); 6496 EVT VT = Op.getValueType(); 6497 unsigned NumElems = VT.getVectorNumElements(); 6498 6499 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6500 // operand of these instructions is only memory, so check if there's a 6501 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6502 // same masks. 6503 bool CanFoldLoad = false; 6504 6505 // Trivial case, when V2 comes from a load. 6506 if (MayFoldVectorLoad(V2)) 6507 CanFoldLoad = true; 6508 6509 // When V1 is a load, it can be folded later into a store in isel, example: 6510 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6511 // turns into: 6512 // (MOVLPSmr addr:$src1, VR128:$src2) 6513 // So, recognize this potential and also use MOVLPS or MOVLPD 6514 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6515 CanFoldLoad = true; 6516 6517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6518 if (CanFoldLoad) { 6519 if (HasSSE2 && NumElems == 2) 6520 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6521 6522 if (NumElems == 4) 6523 // If we don't care about the second element, proceed to use movss. 6524 if (SVOp->getMaskElt(1) != -1) 6525 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6526 } 6527 6528 // movl and movlp will both match v2i64, but v2i64 is never matched by 6529 // movl earlier because we make it strict to avoid messing with the movlp load 6530 // folding logic (see the code above getMOVLP call). Match it here then, 6531 // this is horrible, but will stay like this until we move all shuffle 6532 // matching to x86 specific nodes. Note that for the 1st condition all 6533 // types are matched with movsd. 6534 if (HasSSE2) { 6535 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6536 // as to remove this logic from here, as much as possible 6537 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6538 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6539 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6540 } 6541 6542 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6543 6544 // Invert the operand order and use SHUFPS to match it. 6545 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6546 getShuffleSHUFImmediate(SVOp), DAG); 6547} 6548 6549SDValue 6550X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6551 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6552 EVT VT = Op.getValueType(); 6553 DebugLoc dl = Op.getDebugLoc(); 6554 SDValue V1 = Op.getOperand(0); 6555 SDValue V2 = Op.getOperand(1); 6556 6557 if (isZeroShuffle(SVOp)) 6558 return getZeroVector(VT, Subtarget, DAG, dl); 6559 6560 // Handle splat operations 6561 if (SVOp->isSplat()) { 6562 unsigned NumElem = VT.getVectorNumElements(); 6563 int Size = VT.getSizeInBits(); 6564 6565 // Use vbroadcast whenever the splat comes from a foldable load 6566 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6567 if (Broadcast.getNode()) 6568 return Broadcast; 6569 6570 // Handle splats by matching through known shuffle masks 6571 if ((Size == 128 && NumElem <= 4) || 6572 (Size == 256 && NumElem < 8)) 6573 return SDValue(); 6574 6575 // All remaning splats are promoted to target supported vector shuffles. 6576 return PromoteSplat(SVOp, DAG); 6577 } 6578 6579 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6580 // do it! 6581 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 6582 VT == MVT::v16i16 || VT == MVT::v32i8) { 6583 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6584 if (NewOp.getNode()) 6585 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6586 } else if ((VT == MVT::v4i32 || 6587 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6588 // FIXME: Figure out a cleaner way to do this. 6589 // Try to make use of movq to zero out the top part. 6590 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6591 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6592 if (NewOp.getNode()) { 6593 EVT NewVT = NewOp.getValueType(); 6594 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6595 NewVT, true, false)) 6596 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6597 DAG, Subtarget, dl); 6598 } 6599 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6600 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6601 if (NewOp.getNode()) { 6602 EVT NewVT = NewOp.getValueType(); 6603 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6604 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6605 DAG, Subtarget, dl); 6606 } 6607 } 6608 } 6609 return SDValue(); 6610} 6611 6612SDValue 6613X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6614 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6615 SDValue V1 = Op.getOperand(0); 6616 SDValue V2 = Op.getOperand(1); 6617 EVT VT = Op.getValueType(); 6618 DebugLoc dl = Op.getDebugLoc(); 6619 unsigned NumElems = VT.getVectorNumElements(); 6620 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6621 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6622 bool V1IsSplat = false; 6623 bool V2IsSplat = false; 6624 bool HasSSE2 = Subtarget->hasSSE2(); 6625 bool HasAVX = Subtarget->hasAVX(); 6626 bool HasAVX2 = Subtarget->hasAVX2(); 6627 MachineFunction &MF = DAG.getMachineFunction(); 6628 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6629 6630 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6631 6632 if (V1IsUndef && V2IsUndef) 6633 return DAG.getUNDEF(VT); 6634 6635 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6636 6637 // Vector shuffle lowering takes 3 steps: 6638 // 6639 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6640 // narrowing and commutation of operands should be handled. 6641 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6642 // shuffle nodes. 6643 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6644 // so the shuffle can be broken into other shuffles and the legalizer can 6645 // try the lowering again. 6646 // 6647 // The general idea is that no vector_shuffle operation should be left to 6648 // be matched during isel, all of them must be converted to a target specific 6649 // node here. 6650 6651 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6652 // narrowing and commutation of operands should be handled. The actual code 6653 // doesn't include all of those, work in progress... 6654 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6655 if (NewOp.getNode()) 6656 return NewOp; 6657 6658 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6659 6660 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6661 // unpckh_undef). Only use pshufd if speed is more important than size. 6662 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6663 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6664 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6665 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6666 6667 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6668 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6669 return getMOVDDup(Op, dl, V1, DAG); 6670 6671 if (isMOVHLPS_v_undef_Mask(M, VT)) 6672 return getMOVHighToLow(Op, dl, DAG); 6673 6674 // Use to match splats 6675 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6676 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6677 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6678 6679 if (isPSHUFDMask(M, VT)) { 6680 // The actual implementation will match the mask in the if above and then 6681 // during isel it can match several different instructions, not only pshufd 6682 // as its name says, sad but true, emulate the behavior for now... 6683 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6684 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6685 6686 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6687 6688 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6689 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6690 6691 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6692 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6693 6694 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6695 TargetMask, DAG); 6696 } 6697 6698 // Check if this can be converted into a logical shift. 6699 bool isLeft = false; 6700 unsigned ShAmt = 0; 6701 SDValue ShVal; 6702 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6703 if (isShift && ShVal.hasOneUse()) { 6704 // If the shifted value has multiple uses, it may be cheaper to use 6705 // v_set0 + movlhps or movhlps, etc. 6706 EVT EltVT = VT.getVectorElementType(); 6707 ShAmt *= EltVT.getSizeInBits(); 6708 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6709 } 6710 6711 if (isMOVLMask(M, VT)) { 6712 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6713 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6714 if (!isMOVLPMask(M, VT)) { 6715 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6716 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6717 6718 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6719 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6720 } 6721 } 6722 6723 // FIXME: fold these into legal mask. 6724 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6725 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6726 6727 if (isMOVHLPSMask(M, VT)) 6728 return getMOVHighToLow(Op, dl, DAG); 6729 6730 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6731 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6732 6733 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6734 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6735 6736 if (isMOVLPMask(M, VT)) 6737 return getMOVLP(Op, dl, DAG, HasSSE2); 6738 6739 if (ShouldXformToMOVHLPS(M, VT) || 6740 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6741 return CommuteVectorShuffle(SVOp, DAG); 6742 6743 if (isShift) { 6744 // No better options. Use a vshldq / vsrldq. 6745 EVT EltVT = VT.getVectorElementType(); 6746 ShAmt *= EltVT.getSizeInBits(); 6747 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6748 } 6749 6750 bool Commuted = false; 6751 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6752 // 1,1,1,1 -> v8i16 though. 6753 V1IsSplat = isSplatVector(V1.getNode()); 6754 V2IsSplat = isSplatVector(V2.getNode()); 6755 6756 // Canonicalize the splat or undef, if present, to be on the RHS. 6757 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6758 CommuteVectorShuffleMask(M, NumElems); 6759 std::swap(V1, V2); 6760 std::swap(V1IsSplat, V2IsSplat); 6761 Commuted = true; 6762 } 6763 6764 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6765 // Shuffling low element of v1 into undef, just return v1. 6766 if (V2IsUndef) 6767 return V1; 6768 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6769 // the instruction selector will not match, so get a canonical MOVL with 6770 // swapped operands to undo the commute. 6771 return getMOVL(DAG, dl, VT, V2, V1); 6772 } 6773 6774 if (isUNPCKLMask(M, VT, HasAVX2)) 6775 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6776 6777 if (isUNPCKHMask(M, VT, HasAVX2)) 6778 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6779 6780 if (V2IsSplat) { 6781 // Normalize mask so all entries that point to V2 points to its first 6782 // element then try to match unpck{h|l} again. If match, return a 6783 // new vector_shuffle with the corrected mask.p 6784 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6785 NormalizeMask(NewMask, NumElems); 6786 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) 6787 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6788 if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) 6789 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6790 } 6791 6792 if (Commuted) { 6793 // Commute is back and try unpck* again. 6794 // FIXME: this seems wrong. 6795 CommuteVectorShuffleMask(M, NumElems); 6796 std::swap(V1, V2); 6797 std::swap(V1IsSplat, V2IsSplat); 6798 Commuted = false; 6799 6800 if (isUNPCKLMask(M, VT, HasAVX2)) 6801 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6802 6803 if (isUNPCKHMask(M, VT, HasAVX2)) 6804 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6805 } 6806 6807 // Normalize the node to match x86 shuffle ops if needed 6808 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6809 return CommuteVectorShuffle(SVOp, DAG); 6810 6811 // The checks below are all present in isShuffleMaskLegal, but they are 6812 // inlined here right now to enable us to directly emit target specific 6813 // nodes, and remove one by one until they don't return Op anymore. 6814 6815 if (isPALIGNRMask(M, VT, Subtarget)) 6816 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6817 getShufflePALIGNRImmediate(SVOp), 6818 DAG); 6819 6820 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6821 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6822 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6823 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6824 } 6825 6826 if (isPSHUFHWMask(M, VT, HasAVX2)) 6827 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6828 getShufflePSHUFHWImmediate(SVOp), 6829 DAG); 6830 6831 if (isPSHUFLWMask(M, VT, HasAVX2)) 6832 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6833 getShufflePSHUFLWImmediate(SVOp), 6834 DAG); 6835 6836 if (isSHUFPMask(M, VT, HasAVX)) 6837 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6838 getShuffleSHUFImmediate(SVOp), DAG); 6839 6840 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6841 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6842 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6843 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6844 6845 //===--------------------------------------------------------------------===// 6846 // Generate target specific nodes for 128 or 256-bit shuffles only 6847 // supported in the AVX instruction set. 6848 // 6849 6850 // Handle VMOVDDUPY permutations 6851 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6852 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6853 6854 // Handle VPERMILPS/D* permutations 6855 if (isVPERMILPMask(M, VT, HasAVX)) { 6856 if (HasAVX2 && VT == MVT::v8i32) 6857 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6858 getShuffleSHUFImmediate(SVOp), DAG); 6859 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6860 getShuffleSHUFImmediate(SVOp), DAG); 6861 } 6862 6863 // Handle VPERM2F128/VPERM2I128 permutations 6864 if (isVPERM2X128Mask(M, VT, HasAVX)) 6865 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6866 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6867 6868 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6869 if (BlendOp.getNode()) 6870 return BlendOp; 6871 6872 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6873 SmallVector<SDValue, 8> permclMask; 6874 for (unsigned i = 0; i != 8; ++i) { 6875 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6876 } 6877 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6878 &permclMask[0], 8); 6879 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6880 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6881 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6882 } 6883 6884 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6885 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6886 getShuffleCLImmediate(SVOp), DAG); 6887 6888 6889 //===--------------------------------------------------------------------===// 6890 // Since no target specific shuffle was selected for this generic one, 6891 // lower it into other known shuffles. FIXME: this isn't true yet, but 6892 // this is the plan. 6893 // 6894 6895 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6896 if (VT == MVT::v8i16) { 6897 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG); 6898 if (NewOp.getNode()) 6899 return NewOp; 6900 } 6901 6902 if (VT == MVT::v16i8) { 6903 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6904 if (NewOp.getNode()) 6905 return NewOp; 6906 } 6907 6908 if (VT == MVT::v32i8) { 6909 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG); 6910 if (NewOp.getNode()) 6911 return NewOp; 6912 } 6913 6914 // Handle all 128-bit wide vectors with 4 elements, and match them with 6915 // several different shuffle types. 6916 if (NumElems == 4 && VT.is128BitVector()) 6917 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6918 6919 // Handle general 256-bit shuffles 6920 if (VT.is256BitVector()) 6921 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6922 6923 return SDValue(); 6924} 6925 6926SDValue 6927X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6928 SelectionDAG &DAG) const { 6929 EVT VT = Op.getValueType(); 6930 DebugLoc dl = Op.getDebugLoc(); 6931 6932 if (!Op.getOperand(0).getValueType().is128BitVector()) 6933 return SDValue(); 6934 6935 if (VT.getSizeInBits() == 8) { 6936 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6937 Op.getOperand(0), Op.getOperand(1)); 6938 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6939 DAG.getValueType(VT)); 6940 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6941 } 6942 6943 if (VT.getSizeInBits() == 16) { 6944 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6945 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6946 if (Idx == 0) 6947 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6948 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6949 DAG.getNode(ISD::BITCAST, dl, 6950 MVT::v4i32, 6951 Op.getOperand(0)), 6952 Op.getOperand(1))); 6953 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6954 Op.getOperand(0), Op.getOperand(1)); 6955 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6956 DAG.getValueType(VT)); 6957 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6958 } 6959 6960 if (VT == MVT::f32) { 6961 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6962 // the result back to FR32 register. It's only worth matching if the 6963 // result has a single use which is a store or a bitcast to i32. And in 6964 // the case of a store, it's not worth it if the index is a constant 0, 6965 // because a MOVSSmr can be used instead, which is smaller and faster. 6966 if (!Op.hasOneUse()) 6967 return SDValue(); 6968 SDNode *User = *Op.getNode()->use_begin(); 6969 if ((User->getOpcode() != ISD::STORE || 6970 (isa<ConstantSDNode>(Op.getOperand(1)) && 6971 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6972 (User->getOpcode() != ISD::BITCAST || 6973 User->getValueType(0) != MVT::i32)) 6974 return SDValue(); 6975 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6976 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6977 Op.getOperand(0)), 6978 Op.getOperand(1)); 6979 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6980 } 6981 6982 if (VT == MVT::i32 || VT == MVT::i64) { 6983 // ExtractPS/pextrq works with constant index. 6984 if (isa<ConstantSDNode>(Op.getOperand(1))) 6985 return Op; 6986 } 6987 return SDValue(); 6988} 6989 6990 6991SDValue 6992X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6993 SelectionDAG &DAG) const { 6994 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6995 return SDValue(); 6996 6997 SDValue Vec = Op.getOperand(0); 6998 EVT VecVT = Vec.getValueType(); 6999 7000 // If this is a 256-bit vector result, first extract the 128-bit vector and 7001 // then extract the element from the 128-bit vector. 7002 if (VecVT.is256BitVector()) { 7003 DebugLoc dl = Op.getNode()->getDebugLoc(); 7004 unsigned NumElems = VecVT.getVectorNumElements(); 7005 SDValue Idx = Op.getOperand(1); 7006 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7007 7008 // Get the 128-bit vector. 7009 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 7010 7011 if (IdxVal >= NumElems/2) 7012 IdxVal -= NumElems/2; 7013 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 7014 DAG.getConstant(IdxVal, MVT::i32)); 7015 } 7016 7017 assert(VecVT.is128BitVector() && "Unexpected vector length"); 7018 7019 if (Subtarget->hasSSE41()) { 7020 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7021 if (Res.getNode()) 7022 return Res; 7023 } 7024 7025 EVT VT = Op.getValueType(); 7026 DebugLoc dl = Op.getDebugLoc(); 7027 // TODO: handle v16i8. 7028 if (VT.getSizeInBits() == 16) { 7029 SDValue Vec = Op.getOperand(0); 7030 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7031 if (Idx == 0) 7032 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7033 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7034 DAG.getNode(ISD::BITCAST, dl, 7035 MVT::v4i32, Vec), 7036 Op.getOperand(1))); 7037 // Transform it so it match pextrw which produces a 32-bit result. 7038 EVT EltVT = MVT::i32; 7039 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7040 Op.getOperand(0), Op.getOperand(1)); 7041 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7042 DAG.getValueType(VT)); 7043 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7044 } 7045 7046 if (VT.getSizeInBits() == 32) { 7047 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7048 if (Idx == 0) 7049 return Op; 7050 7051 // SHUFPS the element to the lowest double word, then movss. 7052 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7053 EVT VVT = Op.getOperand(0).getValueType(); 7054 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7055 DAG.getUNDEF(VVT), Mask); 7056 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7057 DAG.getIntPtrConstant(0)); 7058 } 7059 7060 if (VT.getSizeInBits() == 64) { 7061 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7062 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7063 // to match extract_elt for f64. 7064 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7065 if (Idx == 0) 7066 return Op; 7067 7068 // UNPCKHPD the element to the lowest double word, then movsd. 7069 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7070 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7071 int Mask[2] = { 1, -1 }; 7072 EVT VVT = Op.getOperand(0).getValueType(); 7073 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7074 DAG.getUNDEF(VVT), Mask); 7075 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7076 DAG.getIntPtrConstant(0)); 7077 } 7078 7079 return SDValue(); 7080} 7081 7082SDValue 7083X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 7084 SelectionDAG &DAG) const { 7085 EVT VT = Op.getValueType(); 7086 EVT EltVT = VT.getVectorElementType(); 7087 DebugLoc dl = Op.getDebugLoc(); 7088 7089 SDValue N0 = Op.getOperand(0); 7090 SDValue N1 = Op.getOperand(1); 7091 SDValue N2 = Op.getOperand(2); 7092 7093 if (!VT.is128BitVector()) 7094 return SDValue(); 7095 7096 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7097 isa<ConstantSDNode>(N2)) { 7098 unsigned Opc; 7099 if (VT == MVT::v8i16) 7100 Opc = X86ISD::PINSRW; 7101 else if (VT == MVT::v16i8) 7102 Opc = X86ISD::PINSRB; 7103 else 7104 Opc = X86ISD::PINSRB; 7105 7106 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7107 // argument. 7108 if (N1.getValueType() != MVT::i32) 7109 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7110 if (N2.getValueType() != MVT::i32) 7111 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7112 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7113 } 7114 7115 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7116 // Bits [7:6] of the constant are the source select. This will always be 7117 // zero here. The DAG Combiner may combine an extract_elt index into these 7118 // bits. For example (insert (extract, 3), 2) could be matched by putting 7119 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7120 // Bits [5:4] of the constant are the destination select. This is the 7121 // value of the incoming immediate. 7122 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7123 // combine either bitwise AND or insert of float 0.0 to set these bits. 7124 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7125 // Create this as a scalar to vector.. 7126 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7127 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7128 } 7129 7130 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 7131 // PINSR* works with constant index. 7132 return Op; 7133 } 7134 return SDValue(); 7135} 7136 7137SDValue 7138X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7139 EVT VT = Op.getValueType(); 7140 EVT EltVT = VT.getVectorElementType(); 7141 7142 DebugLoc dl = Op.getDebugLoc(); 7143 SDValue N0 = Op.getOperand(0); 7144 SDValue N1 = Op.getOperand(1); 7145 SDValue N2 = Op.getOperand(2); 7146 7147 // If this is a 256-bit vector result, first extract the 128-bit vector, 7148 // insert the element into the extracted half and then place it back. 7149 if (VT.is256BitVector()) { 7150 if (!isa<ConstantSDNode>(N2)) 7151 return SDValue(); 7152 7153 // Get the desired 128-bit vector half. 7154 unsigned NumElems = VT.getVectorNumElements(); 7155 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7156 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 7157 7158 // Insert the element into the desired half. 7159 bool Upper = IdxVal >= NumElems/2; 7160 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 7161 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 7162 7163 // Insert the changed part back to the 256-bit vector 7164 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 7165 } 7166 7167 if (Subtarget->hasSSE41()) 7168 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7169 7170 if (EltVT == MVT::i8) 7171 return SDValue(); 7172 7173 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7174 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7175 // as its second argument. 7176 if (N1.getValueType() != MVT::i32) 7177 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7178 if (N2.getValueType() != MVT::i32) 7179 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7180 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7181 } 7182 return SDValue(); 7183} 7184 7185static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 7186 LLVMContext *Context = DAG.getContext(); 7187 DebugLoc dl = Op.getDebugLoc(); 7188 EVT OpVT = Op.getValueType(); 7189 7190 // If this is a 256-bit vector result, first insert into a 128-bit 7191 // vector and then insert into the 256-bit vector. 7192 if (!OpVT.is128BitVector()) { 7193 // Insert into a 128-bit vector. 7194 EVT VT128 = EVT::getVectorVT(*Context, 7195 OpVT.getVectorElementType(), 7196 OpVT.getVectorNumElements() / 2); 7197 7198 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7199 7200 // Insert the 128-bit vector. 7201 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 7202 } 7203 7204 if (OpVT == MVT::v1i64 && 7205 Op.getOperand(0).getValueType() == MVT::i64) 7206 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7207 7208 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7209 assert(OpVT.is128BitVector() && "Expected an SSE type!"); 7210 return DAG.getNode(ISD::BITCAST, dl, OpVT, 7211 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7212} 7213 7214// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7215// a simple subregister reference or explicit instructions to grab 7216// upper bits of a vector. 7217static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7218 SelectionDAG &DAG) { 7219 if (Subtarget->hasAVX()) { 7220 DebugLoc dl = Op.getNode()->getDebugLoc(); 7221 SDValue Vec = Op.getNode()->getOperand(0); 7222 SDValue Idx = Op.getNode()->getOperand(1); 7223 7224 if (Op.getNode()->getValueType(0).is128BitVector() && 7225 Vec.getNode()->getValueType(0).is256BitVector() && 7226 isa<ConstantSDNode>(Idx)) { 7227 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7228 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7229 } 7230 } 7231 return SDValue(); 7232} 7233 7234// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7235// simple superregister reference or explicit instructions to insert 7236// the upper bits of a vector. 7237static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7238 SelectionDAG &DAG) { 7239 if (Subtarget->hasAVX()) { 7240 DebugLoc dl = Op.getNode()->getDebugLoc(); 7241 SDValue Vec = Op.getNode()->getOperand(0); 7242 SDValue SubVec = Op.getNode()->getOperand(1); 7243 SDValue Idx = Op.getNode()->getOperand(2); 7244 7245 if (Op.getNode()->getValueType(0).is256BitVector() && 7246 SubVec.getNode()->getValueType(0).is128BitVector() && 7247 isa<ConstantSDNode>(Idx)) { 7248 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7249 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7250 } 7251 } 7252 return SDValue(); 7253} 7254 7255// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7256// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7257// one of the above mentioned nodes. It has to be wrapped because otherwise 7258// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7259// be used to form addressing mode. These wrapped nodes will be selected 7260// into MOV32ri. 7261SDValue 7262X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7263 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7264 7265 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7266 // global base reg. 7267 unsigned char OpFlag = 0; 7268 unsigned WrapperKind = X86ISD::Wrapper; 7269 CodeModel::Model M = getTargetMachine().getCodeModel(); 7270 7271 if (Subtarget->isPICStyleRIPRel() && 7272 (M == CodeModel::Small || M == CodeModel::Kernel)) 7273 WrapperKind = X86ISD::WrapperRIP; 7274 else if (Subtarget->isPICStyleGOT()) 7275 OpFlag = X86II::MO_GOTOFF; 7276 else if (Subtarget->isPICStyleStubPIC()) 7277 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7278 7279 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7280 CP->getAlignment(), 7281 CP->getOffset(), OpFlag); 7282 DebugLoc DL = CP->getDebugLoc(); 7283 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7284 // With PIC, the address is actually $g + Offset. 7285 if (OpFlag) { 7286 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7287 DAG.getNode(X86ISD::GlobalBaseReg, 7288 DebugLoc(), getPointerTy()), 7289 Result); 7290 } 7291 7292 return Result; 7293} 7294 7295SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7296 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7297 7298 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7299 // global base reg. 7300 unsigned char OpFlag = 0; 7301 unsigned WrapperKind = X86ISD::Wrapper; 7302 CodeModel::Model M = getTargetMachine().getCodeModel(); 7303 7304 if (Subtarget->isPICStyleRIPRel() && 7305 (M == CodeModel::Small || M == CodeModel::Kernel)) 7306 WrapperKind = X86ISD::WrapperRIP; 7307 else if (Subtarget->isPICStyleGOT()) 7308 OpFlag = X86II::MO_GOTOFF; 7309 else if (Subtarget->isPICStyleStubPIC()) 7310 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7311 7312 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7313 OpFlag); 7314 DebugLoc DL = JT->getDebugLoc(); 7315 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7316 7317 // With PIC, the address is actually $g + Offset. 7318 if (OpFlag) 7319 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7320 DAG.getNode(X86ISD::GlobalBaseReg, 7321 DebugLoc(), getPointerTy()), 7322 Result); 7323 7324 return Result; 7325} 7326 7327SDValue 7328X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7329 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7330 7331 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7332 // global base reg. 7333 unsigned char OpFlag = 0; 7334 unsigned WrapperKind = X86ISD::Wrapper; 7335 CodeModel::Model M = getTargetMachine().getCodeModel(); 7336 7337 if (Subtarget->isPICStyleRIPRel() && 7338 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7339 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7340 OpFlag = X86II::MO_GOTPCREL; 7341 WrapperKind = X86ISD::WrapperRIP; 7342 } else if (Subtarget->isPICStyleGOT()) { 7343 OpFlag = X86II::MO_GOT; 7344 } else if (Subtarget->isPICStyleStubPIC()) { 7345 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7346 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7347 OpFlag = X86II::MO_DARWIN_NONLAZY; 7348 } 7349 7350 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7351 7352 DebugLoc DL = Op.getDebugLoc(); 7353 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7354 7355 7356 // With PIC, the address is actually $g + Offset. 7357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7358 !Subtarget->is64Bit()) { 7359 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7360 DAG.getNode(X86ISD::GlobalBaseReg, 7361 DebugLoc(), getPointerTy()), 7362 Result); 7363 } 7364 7365 // For symbols that require a load from a stub to get the address, emit the 7366 // load. 7367 if (isGlobalStubReference(OpFlag)) 7368 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7369 MachinePointerInfo::getGOT(), false, false, false, 0); 7370 7371 return Result; 7372} 7373 7374SDValue 7375X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7376 // Create the TargetBlockAddressAddress node. 7377 unsigned char OpFlags = 7378 Subtarget->ClassifyBlockAddressReference(); 7379 CodeModel::Model M = getTargetMachine().getCodeModel(); 7380 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7381 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset(); 7382 DebugLoc dl = Op.getDebugLoc(); 7383 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset, 7384 OpFlags); 7385 7386 if (Subtarget->isPICStyleRIPRel() && 7387 (M == CodeModel::Small || M == CodeModel::Kernel)) 7388 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7389 else 7390 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7391 7392 // With PIC, the address is actually $g + Offset. 7393 if (isGlobalRelativeToPICBase(OpFlags)) { 7394 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7395 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7396 Result); 7397 } 7398 7399 return Result; 7400} 7401 7402SDValue 7403X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7404 int64_t Offset, 7405 SelectionDAG &DAG) const { 7406 // Create the TargetGlobalAddress node, folding in the constant 7407 // offset if it is legal. 7408 unsigned char OpFlags = 7409 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7410 CodeModel::Model M = getTargetMachine().getCodeModel(); 7411 SDValue Result; 7412 if (OpFlags == X86II::MO_NO_FLAG && 7413 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7414 // A direct static reference to a global. 7415 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7416 Offset = 0; 7417 } else { 7418 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7419 } 7420 7421 if (Subtarget->isPICStyleRIPRel() && 7422 (M == CodeModel::Small || M == CodeModel::Kernel)) 7423 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7424 else 7425 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7426 7427 // With PIC, the address is actually $g + Offset. 7428 if (isGlobalRelativeToPICBase(OpFlags)) { 7429 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7430 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7431 Result); 7432 } 7433 7434 // For globals that require a load from a stub to get the address, emit the 7435 // load. 7436 if (isGlobalStubReference(OpFlags)) 7437 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7438 MachinePointerInfo::getGOT(), false, false, false, 0); 7439 7440 // If there was a non-zero offset that we didn't fold, create an explicit 7441 // addition for it. 7442 if (Offset != 0) 7443 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7444 DAG.getConstant(Offset, getPointerTy())); 7445 7446 return Result; 7447} 7448 7449SDValue 7450X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7451 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7452 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7453 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7454} 7455 7456static SDValue 7457GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7458 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7459 unsigned char OperandFlags, bool LocalDynamic = false) { 7460 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7461 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7462 DebugLoc dl = GA->getDebugLoc(); 7463 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7464 GA->getValueType(0), 7465 GA->getOffset(), 7466 OperandFlags); 7467 7468 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR 7469 : X86ISD::TLSADDR; 7470 7471 if (InFlag) { 7472 SDValue Ops[] = { Chain, TGA, *InFlag }; 7473 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3); 7474 } else { 7475 SDValue Ops[] = { Chain, TGA }; 7476 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2); 7477 } 7478 7479 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7480 MFI->setAdjustsStack(true); 7481 7482 SDValue Flag = Chain.getValue(1); 7483 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7484} 7485 7486// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7487static SDValue 7488LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7489 const EVT PtrVT) { 7490 SDValue InFlag; 7491 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7492 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7493 DAG.getNode(X86ISD::GlobalBaseReg, 7494 DebugLoc(), PtrVT), InFlag); 7495 InFlag = Chain.getValue(1); 7496 7497 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7498} 7499 7500// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7501static SDValue 7502LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7503 const EVT PtrVT) { 7504 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7505 X86::RAX, X86II::MO_TLSGD); 7506} 7507 7508static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, 7509 SelectionDAG &DAG, 7510 const EVT PtrVT, 7511 bool is64Bit) { 7512 DebugLoc dl = GA->getDebugLoc(); 7513 7514 // Get the start address of the TLS block for this module. 7515 X86MachineFunctionInfo* MFI = DAG.getMachineFunction() 7516 .getInfo<X86MachineFunctionInfo>(); 7517 MFI->incNumLocalDynamicTLSAccesses(); 7518 7519 SDValue Base; 7520 if (is64Bit) { 7521 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, 7522 X86II::MO_TLSLD, /*LocalDynamic=*/true); 7523 } else { 7524 SDValue InFlag; 7525 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7526 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag); 7527 InFlag = Chain.getValue(1); 7528 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, 7529 X86II::MO_TLSLDM, /*LocalDynamic=*/true); 7530 } 7531 7532 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations 7533 // of Base. 7534 7535 // Build x@dtpoff. 7536 unsigned char OperandFlags = X86II::MO_DTPOFF; 7537 unsigned WrapperKind = X86ISD::Wrapper; 7538 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7539 GA->getValueType(0), 7540 GA->getOffset(), OperandFlags); 7541 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7542 7543 // Add x@dtpoff with the base. 7544 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base); 7545} 7546 7547// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 7548static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7549 const EVT PtrVT, TLSModel::Model model, 7550 bool is64Bit, bool isPIC) { 7551 DebugLoc dl = GA->getDebugLoc(); 7552 7553 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7554 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7555 is64Bit ? 257 : 256)); 7556 7557 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7558 DAG.getIntPtrConstant(0), 7559 MachinePointerInfo(Ptr), 7560 false, false, false, 0); 7561 7562 unsigned char OperandFlags = 0; 7563 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7564 // initialexec. 7565 unsigned WrapperKind = X86ISD::Wrapper; 7566 if (model == TLSModel::LocalExec) { 7567 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7568 } else if (model == TLSModel::InitialExec) { 7569 if (is64Bit) { 7570 OperandFlags = X86II::MO_GOTTPOFF; 7571 WrapperKind = X86ISD::WrapperRIP; 7572 } else { 7573 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 7574 } 7575 } else { 7576 llvm_unreachable("Unexpected model"); 7577 } 7578 7579 // emit "addl x@ntpoff,%eax" (local exec) 7580 // or "addl x@indntpoff,%eax" (initial exec) 7581 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 7582 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7583 GA->getValueType(0), 7584 GA->getOffset(), OperandFlags); 7585 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7586 7587 if (model == TLSModel::InitialExec) { 7588 if (isPIC && !is64Bit) { 7589 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 7590 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), 7591 Offset); 7592 } 7593 7594 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7595 MachinePointerInfo::getGOT(), false, false, false, 7596 0); 7597 } 7598 7599 // The address of the thread local variable is the add of the thread 7600 // pointer with the offset of the variable. 7601 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7602} 7603 7604SDValue 7605X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7606 7607 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7608 const GlobalValue *GV = GA->getGlobal(); 7609 7610 if (Subtarget->isTargetELF()) { 7611 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7612 7613 switch (model) { 7614 case TLSModel::GeneralDynamic: 7615 if (Subtarget->is64Bit()) 7616 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7617 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7618 case TLSModel::LocalDynamic: 7619 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(), 7620 Subtarget->is64Bit()); 7621 case TLSModel::InitialExec: 7622 case TLSModel::LocalExec: 7623 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7624 Subtarget->is64Bit(), 7625 getTargetMachine().getRelocationModel() == Reloc::PIC_); 7626 } 7627 llvm_unreachable("Unknown TLS model."); 7628 } 7629 7630 if (Subtarget->isTargetDarwin()) { 7631 // Darwin only has one model of TLS. Lower to that. 7632 unsigned char OpFlag = 0; 7633 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7634 X86ISD::WrapperRIP : X86ISD::Wrapper; 7635 7636 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7637 // global base reg. 7638 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7639 !Subtarget->is64Bit(); 7640 if (PIC32) 7641 OpFlag = X86II::MO_TLVP_PIC_BASE; 7642 else 7643 OpFlag = X86II::MO_TLVP; 7644 DebugLoc DL = Op.getDebugLoc(); 7645 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7646 GA->getValueType(0), 7647 GA->getOffset(), OpFlag); 7648 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7649 7650 // With PIC32, the address is actually $g + Offset. 7651 if (PIC32) 7652 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7653 DAG.getNode(X86ISD::GlobalBaseReg, 7654 DebugLoc(), getPointerTy()), 7655 Offset); 7656 7657 // Lowering the machine isd will make sure everything is in the right 7658 // location. 7659 SDValue Chain = DAG.getEntryNode(); 7660 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7661 SDValue Args[] = { Chain, Offset }; 7662 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7663 7664 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7665 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7666 MFI->setAdjustsStack(true); 7667 7668 // And our return value (tls address) is in the standard call return value 7669 // location. 7670 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7671 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7672 Chain.getValue(1)); 7673 } 7674 7675 if (Subtarget->isTargetWindows()) { 7676 // Just use the implicit TLS architecture 7677 // Need to generate someting similar to: 7678 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7679 // ; from TEB 7680 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7681 // mov rcx, qword [rdx+rcx*8] 7682 // mov eax, .tls$:tlsvar 7683 // [rax+rcx] contains the address 7684 // Windows 64bit: gs:0x58 7685 // Windows 32bit: fs:__tls_array 7686 7687 // If GV is an alias then use the aliasee for determining 7688 // thread-localness. 7689 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7690 GV = GA->resolveAliasedGlobal(false); 7691 DebugLoc dl = GA->getDebugLoc(); 7692 SDValue Chain = DAG.getEntryNode(); 7693 7694 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7695 // %gs:0x58 (64-bit). 7696 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7697 ? Type::getInt8PtrTy(*DAG.getContext(), 7698 256) 7699 : Type::getInt32PtrTy(*DAG.getContext(), 7700 257)); 7701 7702 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7703 Subtarget->is64Bit() 7704 ? DAG.getIntPtrConstant(0x58) 7705 : DAG.getExternalSymbol("_tls_array", 7706 getPointerTy()), 7707 MachinePointerInfo(Ptr), 7708 false, false, false, 0); 7709 7710 // Load the _tls_index variable 7711 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7712 if (Subtarget->is64Bit()) 7713 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7714 IDX, MachinePointerInfo(), MVT::i32, 7715 false, false, 0); 7716 else 7717 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7718 false, false, false, 0); 7719 7720 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7721 getPointerTy()); 7722 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7723 7724 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7725 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7726 false, false, false, 0); 7727 7728 // Get the offset of start of .tls section 7729 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7730 GA->getValueType(0), 7731 GA->getOffset(), X86II::MO_SECREL); 7732 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7733 7734 // The address of the thread local variable is the add of the thread 7735 // pointer with the offset of the variable. 7736 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7737 } 7738 7739 llvm_unreachable("TLS not implemented for this target."); 7740} 7741 7742 7743/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7744/// and take a 2 x i32 value to shift plus a shift amount. 7745SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7746 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7747 EVT VT = Op.getValueType(); 7748 unsigned VTBits = VT.getSizeInBits(); 7749 DebugLoc dl = Op.getDebugLoc(); 7750 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7751 SDValue ShOpLo = Op.getOperand(0); 7752 SDValue ShOpHi = Op.getOperand(1); 7753 SDValue ShAmt = Op.getOperand(2); 7754 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7755 DAG.getConstant(VTBits - 1, MVT::i8)) 7756 : DAG.getConstant(0, VT); 7757 7758 SDValue Tmp2, Tmp3; 7759 if (Op.getOpcode() == ISD::SHL_PARTS) { 7760 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7761 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7762 } else { 7763 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7764 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7765 } 7766 7767 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7768 DAG.getConstant(VTBits, MVT::i8)); 7769 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7770 AndNode, DAG.getConstant(0, MVT::i8)); 7771 7772 SDValue Hi, Lo; 7773 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7774 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7775 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7776 7777 if (Op.getOpcode() == ISD::SHL_PARTS) { 7778 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7779 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7780 } else { 7781 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7782 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7783 } 7784 7785 SDValue Ops[2] = { Lo, Hi }; 7786 return DAG.getMergeValues(Ops, 2, dl); 7787} 7788 7789SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7790 SelectionDAG &DAG) const { 7791 EVT SrcVT = Op.getOperand(0).getValueType(); 7792 7793 if (SrcVT.isVector()) 7794 return SDValue(); 7795 7796 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7797 "Unknown SINT_TO_FP to lower!"); 7798 7799 // These are really Legal; return the operand so the caller accepts it as 7800 // Legal. 7801 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7802 return Op; 7803 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7804 Subtarget->is64Bit()) { 7805 return Op; 7806 } 7807 7808 DebugLoc dl = Op.getDebugLoc(); 7809 unsigned Size = SrcVT.getSizeInBits()/8; 7810 MachineFunction &MF = DAG.getMachineFunction(); 7811 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7812 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7813 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7814 StackSlot, 7815 MachinePointerInfo::getFixedStack(SSFI), 7816 false, false, 0); 7817 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7818} 7819 7820SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7821 SDValue StackSlot, 7822 SelectionDAG &DAG) const { 7823 // Build the FILD 7824 DebugLoc DL = Op.getDebugLoc(); 7825 SDVTList Tys; 7826 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7827 if (useSSE) 7828 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7829 else 7830 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7831 7832 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7833 7834 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7835 MachineMemOperand *MMO; 7836 if (FI) { 7837 int SSFI = FI->getIndex(); 7838 MMO = 7839 DAG.getMachineFunction() 7840 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7841 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7842 } else { 7843 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7844 StackSlot = StackSlot.getOperand(1); 7845 } 7846 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7847 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7848 X86ISD::FILD, DL, 7849 Tys, Ops, array_lengthof(Ops), 7850 SrcVT, MMO); 7851 7852 if (useSSE) { 7853 Chain = Result.getValue(1); 7854 SDValue InFlag = Result.getValue(2); 7855 7856 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7857 // shouldn't be necessary except that RFP cannot be live across 7858 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7859 MachineFunction &MF = DAG.getMachineFunction(); 7860 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7861 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7862 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7863 Tys = DAG.getVTList(MVT::Other); 7864 SDValue Ops[] = { 7865 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7866 }; 7867 MachineMemOperand *MMO = 7868 DAG.getMachineFunction() 7869 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7870 MachineMemOperand::MOStore, SSFISize, SSFISize); 7871 7872 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7873 Ops, array_lengthof(Ops), 7874 Op.getValueType(), MMO); 7875 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7876 MachinePointerInfo::getFixedStack(SSFI), 7877 false, false, false, 0); 7878 } 7879 7880 return Result; 7881} 7882 7883// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7884SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7885 SelectionDAG &DAG) const { 7886 // This algorithm is not obvious. Here it is what we're trying to output: 7887 /* 7888 movq %rax, %xmm0 7889 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7890 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7891 #ifdef __SSE3__ 7892 haddpd %xmm0, %xmm0 7893 #else 7894 pshufd $0x4e, %xmm0, %xmm1 7895 addpd %xmm1, %xmm0 7896 #endif 7897 */ 7898 7899 DebugLoc dl = Op.getDebugLoc(); 7900 LLVMContext *Context = DAG.getContext(); 7901 7902 // Build some magic constants. 7903 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7904 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7905 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7906 7907 SmallVector<Constant*,2> CV1; 7908 CV1.push_back( 7909 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7910 CV1.push_back( 7911 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7912 Constant *C1 = ConstantVector::get(CV1); 7913 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7914 7915 // Load the 64-bit value into an XMM register. 7916 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7917 Op.getOperand(0)); 7918 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7919 MachinePointerInfo::getConstantPool(), 7920 false, false, false, 16); 7921 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7922 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7923 CLod0); 7924 7925 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7926 MachinePointerInfo::getConstantPool(), 7927 false, false, false, 16); 7928 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7929 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7930 SDValue Result; 7931 7932 if (Subtarget->hasSSE3()) { 7933 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7934 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7935 } else { 7936 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7937 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7938 S2F, 0x4E, DAG); 7939 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7940 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7941 Sub); 7942 } 7943 7944 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7945 DAG.getIntPtrConstant(0)); 7946} 7947 7948// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7949SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7950 SelectionDAG &DAG) const { 7951 DebugLoc dl = Op.getDebugLoc(); 7952 // FP constant to bias correct the final result. 7953 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7954 MVT::f64); 7955 7956 // Load the 32-bit value into an XMM register. 7957 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7958 Op.getOperand(0)); 7959 7960 // Zero out the upper parts of the register. 7961 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7962 7963 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7964 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7965 DAG.getIntPtrConstant(0)); 7966 7967 // Or the load with the bias. 7968 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7969 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7970 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7971 MVT::v2f64, Load)), 7972 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7973 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7974 MVT::v2f64, Bias))); 7975 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7976 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7977 DAG.getIntPtrConstant(0)); 7978 7979 // Subtract the bias. 7980 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7981 7982 // Handle final rounding. 7983 EVT DestVT = Op.getValueType(); 7984 7985 if (DestVT.bitsLT(MVT::f64)) 7986 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7987 DAG.getIntPtrConstant(0)); 7988 if (DestVT.bitsGT(MVT::f64)) 7989 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7990 7991 // Handle final rounding. 7992 return Sub; 7993} 7994 7995SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7996 SelectionDAG &DAG) const { 7997 SDValue N0 = Op.getOperand(0); 7998 DebugLoc dl = Op.getDebugLoc(); 7999 8000 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 8001 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 8002 // the optimization here. 8003 if (DAG.SignBitIsZero(N0)) 8004 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 8005 8006 EVT SrcVT = N0.getValueType(); 8007 EVT DstVT = Op.getValueType(); 8008 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 8009 return LowerUINT_TO_FP_i64(Op, DAG); 8010 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 8011 return LowerUINT_TO_FP_i32(Op, DAG); 8012 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 8013 return SDValue(); 8014 8015 // Make a 64-bit buffer, and use it to build an FILD. 8016 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 8017 if (SrcVT == MVT::i32) { 8018 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 8019 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 8020 getPointerTy(), StackSlot, WordOff); 8021 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8022 StackSlot, MachinePointerInfo(), 8023 false, false, 0); 8024 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 8025 OffsetSlot, MachinePointerInfo(), 8026 false, false, 0); 8027 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 8028 return Fild; 8029 } 8030 8031 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 8032 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8033 StackSlot, MachinePointerInfo(), 8034 false, false, 0); 8035 // For i64 source, we need to add the appropriate power of 2 if the input 8036 // was negative. This is the same as the optimization in 8037 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 8038 // we must be careful to do the computation in x87 extended precision, not 8039 // in SSE. (The generic code can't know it's OK to do this, or how to.) 8040 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 8041 MachineMemOperand *MMO = 8042 DAG.getMachineFunction() 8043 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8044 MachineMemOperand::MOLoad, 8, 8); 8045 8046 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 8047 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 8048 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 8049 MVT::i64, MMO); 8050 8051 APInt FF(32, 0x5F800000ULL); 8052 8053 // Check whether the sign bit is set. 8054 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 8055 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 8056 ISD::SETLT); 8057 8058 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 8059 SDValue FudgePtr = DAG.getConstantPool( 8060 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 8061 getPointerTy()); 8062 8063 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 8064 SDValue Zero = DAG.getIntPtrConstant(0); 8065 SDValue Four = DAG.getIntPtrConstant(4); 8066 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 8067 Zero, Four); 8068 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 8069 8070 // Load the value out, extending it from f32 to f80. 8071 // FIXME: Avoid the extend by constructing the right constant pool? 8072 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 8073 FudgePtr, MachinePointerInfo::getConstantPool(), 8074 MVT::f32, false, false, 4); 8075 // Extend everything to 80 bits to force it to be done on x87. 8076 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 8077 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 8078} 8079 8080std::pair<SDValue,SDValue> X86TargetLowering:: 8081FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 8082 DebugLoc DL = Op.getDebugLoc(); 8083 8084 EVT DstTy = Op.getValueType(); 8085 8086 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 8087 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 8088 DstTy = MVT::i64; 8089 } 8090 8091 assert(DstTy.getSimpleVT() <= MVT::i64 && 8092 DstTy.getSimpleVT() >= MVT::i16 && 8093 "Unknown FP_TO_INT to lower!"); 8094 8095 // These are really Legal. 8096 if (DstTy == MVT::i32 && 8097 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8098 return std::make_pair(SDValue(), SDValue()); 8099 if (Subtarget->is64Bit() && 8100 DstTy == MVT::i64 && 8101 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8102 return std::make_pair(SDValue(), SDValue()); 8103 8104 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 8105 // stack slot, or into the FTOL runtime function. 8106 MachineFunction &MF = DAG.getMachineFunction(); 8107 unsigned MemSize = DstTy.getSizeInBits()/8; 8108 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8109 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8110 8111 unsigned Opc; 8112 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 8113 Opc = X86ISD::WIN_FTOL; 8114 else 8115 switch (DstTy.getSimpleVT().SimpleTy) { 8116 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8117 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8118 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8119 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8120 } 8121 8122 SDValue Chain = DAG.getEntryNode(); 8123 SDValue Value = Op.getOperand(0); 8124 EVT TheVT = Op.getOperand(0).getValueType(); 8125 // FIXME This causes a redundant load/store if the SSE-class value is already 8126 // in memory, such as if it is on the callstack. 8127 if (isScalarFPTypeInSSEReg(TheVT)) { 8128 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8129 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8130 MachinePointerInfo::getFixedStack(SSFI), 8131 false, false, 0); 8132 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8133 SDValue Ops[] = { 8134 Chain, StackSlot, DAG.getValueType(TheVT) 8135 }; 8136 8137 MachineMemOperand *MMO = 8138 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8139 MachineMemOperand::MOLoad, MemSize, MemSize); 8140 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8141 DstTy, MMO); 8142 Chain = Value.getValue(1); 8143 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8144 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8145 } 8146 8147 MachineMemOperand *MMO = 8148 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8149 MachineMemOperand::MOStore, MemSize, MemSize); 8150 8151 if (Opc != X86ISD::WIN_FTOL) { 8152 // Build the FP_TO_INT*_IN_MEM 8153 SDValue Ops[] = { Chain, Value, StackSlot }; 8154 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8155 Ops, 3, DstTy, MMO); 8156 return std::make_pair(FIST, StackSlot); 8157 } else { 8158 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 8159 DAG.getVTList(MVT::Other, MVT::Glue), 8160 Chain, Value); 8161 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 8162 MVT::i32, ftol.getValue(1)); 8163 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 8164 MVT::i32, eax.getValue(2)); 8165 SDValue Ops[] = { eax, edx }; 8166 SDValue pair = IsReplace 8167 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 8168 : DAG.getMergeValues(Ops, 2, DL); 8169 return std::make_pair(pair, SDValue()); 8170 } 8171} 8172 8173SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8174 SelectionDAG &DAG) const { 8175 if (Op.getValueType().isVector()) 8176 return SDValue(); 8177 8178 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8179 /*IsSigned=*/ true, /*IsReplace=*/ false); 8180 SDValue FIST = Vals.first, StackSlot = Vals.second; 8181 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8182 if (FIST.getNode() == 0) return Op; 8183 8184 if (StackSlot.getNode()) 8185 // Load the result. 8186 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8187 FIST, StackSlot, MachinePointerInfo(), 8188 false, false, false, 0); 8189 8190 // The node is the result. 8191 return FIST; 8192} 8193 8194SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8195 SelectionDAG &DAG) const { 8196 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8197 /*IsSigned=*/ false, /*IsReplace=*/ false); 8198 SDValue FIST = Vals.first, StackSlot = Vals.second; 8199 assert(FIST.getNode() && "Unexpected failure"); 8200 8201 if (StackSlot.getNode()) 8202 // Load the result. 8203 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8204 FIST, StackSlot, MachinePointerInfo(), 8205 false, false, false, 0); 8206 8207 // The node is the result. 8208 return FIST; 8209} 8210 8211SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 8212 LLVMContext *Context = DAG.getContext(); 8213 DebugLoc dl = Op.getDebugLoc(); 8214 EVT VT = Op.getValueType(); 8215 EVT EltVT = VT; 8216 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8217 if (VT.isVector()) { 8218 EltVT = VT.getVectorElementType(); 8219 NumElts = VT.getVectorNumElements(); 8220 } 8221 Constant *C; 8222 if (EltVT == MVT::f64) 8223 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8224 else 8225 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8226 C = ConstantVector::getSplat(NumElts, C); 8227 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8228 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8229 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8230 MachinePointerInfo::getConstantPool(), 8231 false, false, false, Alignment); 8232 if (VT.isVector()) { 8233 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8234 return DAG.getNode(ISD::BITCAST, dl, VT, 8235 DAG.getNode(ISD::AND, dl, ANDVT, 8236 DAG.getNode(ISD::BITCAST, dl, ANDVT, 8237 Op.getOperand(0)), 8238 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask))); 8239 } 8240 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8241} 8242 8243SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8244 LLVMContext *Context = DAG.getContext(); 8245 DebugLoc dl = Op.getDebugLoc(); 8246 EVT VT = Op.getValueType(); 8247 EVT EltVT = VT; 8248 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8249 if (VT.isVector()) { 8250 EltVT = VT.getVectorElementType(); 8251 NumElts = VT.getVectorNumElements(); 8252 } 8253 Constant *C; 8254 if (EltVT == MVT::f64) 8255 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8256 else 8257 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8258 C = ConstantVector::getSplat(NumElts, C); 8259 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8260 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8261 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8262 MachinePointerInfo::getConstantPool(), 8263 false, false, false, Alignment); 8264 if (VT.isVector()) { 8265 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8266 return DAG.getNode(ISD::BITCAST, dl, VT, 8267 DAG.getNode(ISD::XOR, dl, XORVT, 8268 DAG.getNode(ISD::BITCAST, dl, XORVT, 8269 Op.getOperand(0)), 8270 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 8271 } 8272 8273 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8274} 8275 8276SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8277 LLVMContext *Context = DAG.getContext(); 8278 SDValue Op0 = Op.getOperand(0); 8279 SDValue Op1 = Op.getOperand(1); 8280 DebugLoc dl = Op.getDebugLoc(); 8281 EVT VT = Op.getValueType(); 8282 EVT SrcVT = Op1.getValueType(); 8283 8284 // If second operand is smaller, extend it first. 8285 if (SrcVT.bitsLT(VT)) { 8286 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8287 SrcVT = VT; 8288 } 8289 // And if it is bigger, shrink it first. 8290 if (SrcVT.bitsGT(VT)) { 8291 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8292 SrcVT = VT; 8293 } 8294 8295 // At this point the operands and the result should have the same 8296 // type, and that won't be f80 since that is not custom lowered. 8297 8298 // First get the sign bit of second operand. 8299 SmallVector<Constant*,4> CV; 8300 if (SrcVT == MVT::f64) { 8301 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8302 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8303 } else { 8304 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8305 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8306 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8307 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8308 } 8309 Constant *C = ConstantVector::get(CV); 8310 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8311 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8312 MachinePointerInfo::getConstantPool(), 8313 false, false, false, 16); 8314 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8315 8316 // Shift sign bit right or left if the two operands have different types. 8317 if (SrcVT.bitsGT(VT)) { 8318 // Op0 is MVT::f32, Op1 is MVT::f64. 8319 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8320 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8321 DAG.getConstant(32, MVT::i32)); 8322 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8323 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8324 DAG.getIntPtrConstant(0)); 8325 } 8326 8327 // Clear first operand sign bit. 8328 CV.clear(); 8329 if (VT == MVT::f64) { 8330 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8331 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8332 } else { 8333 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8334 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8335 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8336 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8337 } 8338 C = ConstantVector::get(CV); 8339 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8340 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8341 MachinePointerInfo::getConstantPool(), 8342 false, false, false, 16); 8343 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8344 8345 // Or the value with the sign bit. 8346 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8347} 8348 8349static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) { 8350 SDValue N0 = Op.getOperand(0); 8351 DebugLoc dl = Op.getDebugLoc(); 8352 EVT VT = Op.getValueType(); 8353 8354 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8355 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8356 DAG.getConstant(1, VT)); 8357 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8358} 8359 8360// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able. 8361// 8362SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const { 8363 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree."); 8364 8365 if (!Subtarget->hasSSE41()) 8366 return SDValue(); 8367 8368 if (!Op->hasOneUse()) 8369 return SDValue(); 8370 8371 SDNode *N = Op.getNode(); 8372 DebugLoc DL = N->getDebugLoc(); 8373 8374 SmallVector<SDValue, 8> Opnds; 8375 DenseMap<SDValue, unsigned> VecInMap; 8376 EVT VT = MVT::Other; 8377 8378 // Recognize a special case where a vector is casted into wide integer to 8379 // test all 0s. 8380 Opnds.push_back(N->getOperand(0)); 8381 Opnds.push_back(N->getOperand(1)); 8382 8383 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) { 8384 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot; 8385 // BFS traverse all OR'd operands. 8386 if (I->getOpcode() == ISD::OR) { 8387 Opnds.push_back(I->getOperand(0)); 8388 Opnds.push_back(I->getOperand(1)); 8389 // Re-evaluate the number of nodes to be traversed. 8390 e += 2; // 2 more nodes (LHS and RHS) are pushed. 8391 continue; 8392 } 8393 8394 // Quit if a non-EXTRACT_VECTOR_ELT 8395 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8396 return SDValue(); 8397 8398 // Quit if without a constant index. 8399 SDValue Idx = I->getOperand(1); 8400 if (!isa<ConstantSDNode>(Idx)) 8401 return SDValue(); 8402 8403 SDValue ExtractedFromVec = I->getOperand(0); 8404 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec); 8405 if (M == VecInMap.end()) { 8406 VT = ExtractedFromVec.getValueType(); 8407 // Quit if not 128/256-bit vector. 8408 if (!VT.is128BitVector() && !VT.is256BitVector()) 8409 return SDValue(); 8410 // Quit if not the same type. 8411 if (VecInMap.begin() != VecInMap.end() && 8412 VT != VecInMap.begin()->first.getValueType()) 8413 return SDValue(); 8414 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first; 8415 } 8416 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue(); 8417 } 8418 8419 assert((VT.is128BitVector() || VT.is256BitVector()) && 8420 "Not extracted from 128-/256-bit vector."); 8421 8422 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U; 8423 SmallVector<SDValue, 8> VecIns; 8424 8425 for (DenseMap<SDValue, unsigned>::const_iterator 8426 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) { 8427 // Quit if not all elements are used. 8428 if (I->second != FullMask) 8429 return SDValue(); 8430 VecIns.push_back(I->first); 8431 } 8432 8433 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8434 8435 // Cast all vectors into TestVT for PTEST. 8436 for (unsigned i = 0, e = VecIns.size(); i < e; ++i) 8437 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]); 8438 8439 // If more than one full vectors are evaluated, OR them first before PTEST. 8440 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) { 8441 // Each iteration will OR 2 nodes and append the result until there is only 8442 // 1 node left, i.e. the final OR'd value of all vectors. 8443 SDValue LHS = VecIns[Slot]; 8444 SDValue RHS = VecIns[Slot + 1]; 8445 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS)); 8446 } 8447 8448 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, 8449 VecIns.back(), VecIns.back()); 8450} 8451 8452/// Emit nodes that will be selected as "test Op0,Op0", or something 8453/// equivalent. 8454SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8455 SelectionDAG &DAG) const { 8456 DebugLoc dl = Op.getDebugLoc(); 8457 8458 // CF and OF aren't always set the way we want. Determine which 8459 // of these we need. 8460 bool NeedCF = false; 8461 bool NeedOF = false; 8462 switch (X86CC) { 8463 default: break; 8464 case X86::COND_A: case X86::COND_AE: 8465 case X86::COND_B: case X86::COND_BE: 8466 NeedCF = true; 8467 break; 8468 case X86::COND_G: case X86::COND_GE: 8469 case X86::COND_L: case X86::COND_LE: 8470 case X86::COND_O: case X86::COND_NO: 8471 NeedOF = true; 8472 break; 8473 } 8474 8475 // See if we can use the EFLAGS value from the operand instead of 8476 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8477 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8478 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8479 // Emit a CMP with 0, which is the TEST pattern. 8480 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8481 DAG.getConstant(0, Op.getValueType())); 8482 8483 unsigned Opcode = 0; 8484 unsigned NumOperands = 0; 8485 8486 // Truncate operations may prevent the merge of the SETCC instruction 8487 // and the arithmetic intruction before it. Attempt to truncate the operands 8488 // of the arithmetic instruction and use a reduced bit-width instruction. 8489 bool NeedTruncation = false; 8490 SDValue ArithOp = Op; 8491 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { 8492 SDValue Arith = Op->getOperand(0); 8493 // Both the trunc and the arithmetic op need to have one user each. 8494 if (Arith->hasOneUse()) 8495 switch (Arith.getOpcode()) { 8496 default: break; 8497 case ISD::ADD: 8498 case ISD::SUB: 8499 case ISD::AND: 8500 case ISD::OR: 8501 case ISD::XOR: { 8502 NeedTruncation = true; 8503 ArithOp = Arith; 8504 } 8505 } 8506 } 8507 8508 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation 8509 // which may be the result of a CAST. We use the variable 'Op', which is the 8510 // non-casted variable when we check for possible users. 8511 switch (ArithOp.getOpcode()) { 8512 case ISD::ADD: 8513 // Due to an isel shortcoming, be conservative if this add is likely to be 8514 // selected as part of a load-modify-store instruction. When the root node 8515 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8516 // uses of other nodes in the match, such as the ADD in this case. This 8517 // leads to the ADD being left around and reselected, with the result being 8518 // two adds in the output. Alas, even if none our users are stores, that 8519 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8520 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8521 // climbing the DAG back to the root, and it doesn't seem to be worth the 8522 // effort. 8523 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8524 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8525 if (UI->getOpcode() != ISD::CopyToReg && 8526 UI->getOpcode() != ISD::SETCC && 8527 UI->getOpcode() != ISD::STORE) 8528 goto default_case; 8529 8530 if (ConstantSDNode *C = 8531 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) { 8532 // An add of one will be selected as an INC. 8533 if (C->getAPIntValue() == 1) { 8534 Opcode = X86ISD::INC; 8535 NumOperands = 1; 8536 break; 8537 } 8538 8539 // An add of negative one (subtract of one) will be selected as a DEC. 8540 if (C->getAPIntValue().isAllOnesValue()) { 8541 Opcode = X86ISD::DEC; 8542 NumOperands = 1; 8543 break; 8544 } 8545 } 8546 8547 // Otherwise use a regular EFLAGS-setting add. 8548 Opcode = X86ISD::ADD; 8549 NumOperands = 2; 8550 break; 8551 case ISD::AND: { 8552 // If the primary and result isn't used, don't bother using X86ISD::AND, 8553 // because a TEST instruction will be better. 8554 bool NonFlagUse = false; 8555 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8556 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8557 SDNode *User = *UI; 8558 unsigned UOpNo = UI.getOperandNo(); 8559 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8560 // Look pass truncate. 8561 UOpNo = User->use_begin().getOperandNo(); 8562 User = *User->use_begin(); 8563 } 8564 8565 if (User->getOpcode() != ISD::BRCOND && 8566 User->getOpcode() != ISD::SETCC && 8567 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) { 8568 NonFlagUse = true; 8569 break; 8570 } 8571 } 8572 8573 if (!NonFlagUse) 8574 break; 8575 } 8576 // FALL THROUGH 8577 case ISD::SUB: 8578 case ISD::OR: 8579 case ISD::XOR: 8580 // Due to the ISEL shortcoming noted above, be conservative if this op is 8581 // likely to be selected as part of a load-modify-store instruction. 8582 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8583 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8584 if (UI->getOpcode() == ISD::STORE) 8585 goto default_case; 8586 8587 // Otherwise use a regular EFLAGS-setting instruction. 8588 switch (ArithOp.getOpcode()) { 8589 default: llvm_unreachable("unexpected operator!"); 8590 case ISD::SUB: Opcode = X86ISD::SUB; break; 8591 case ISD::XOR: Opcode = X86ISD::XOR; break; 8592 case ISD::AND: Opcode = X86ISD::AND; break; 8593 case ISD::OR: { 8594 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) { 8595 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG); 8596 if (EFLAGS.getNode()) 8597 return EFLAGS; 8598 } 8599 Opcode = X86ISD::OR; 8600 break; 8601 } 8602 } 8603 8604 NumOperands = 2; 8605 break; 8606 case X86ISD::ADD: 8607 case X86ISD::SUB: 8608 case X86ISD::INC: 8609 case X86ISD::DEC: 8610 case X86ISD::OR: 8611 case X86ISD::XOR: 8612 case X86ISD::AND: 8613 return SDValue(Op.getNode(), 1); 8614 default: 8615 default_case: 8616 break; 8617 } 8618 8619 // If we found that truncation is beneficial, perform the truncation and 8620 // update 'Op'. 8621 if (NeedTruncation) { 8622 EVT VT = Op.getValueType(); 8623 SDValue WideVal = Op->getOperand(0); 8624 EVT WideVT = WideVal.getValueType(); 8625 unsigned ConvertedOp = 0; 8626 // Use a target machine opcode to prevent further DAGCombine 8627 // optimizations that may separate the arithmetic operations 8628 // from the setcc node. 8629 switch (WideVal.getOpcode()) { 8630 default: break; 8631 case ISD::ADD: ConvertedOp = X86ISD::ADD; break; 8632 case ISD::SUB: ConvertedOp = X86ISD::SUB; break; 8633 case ISD::AND: ConvertedOp = X86ISD::AND; break; 8634 case ISD::OR: ConvertedOp = X86ISD::OR; break; 8635 case ISD::XOR: ConvertedOp = X86ISD::XOR; break; 8636 } 8637 8638 if (ConvertedOp) { 8639 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8640 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { 8641 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0)); 8642 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1)); 8643 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1); 8644 } 8645 } 8646 } 8647 8648 if (Opcode == 0) 8649 // Emit a CMP with 0, which is the TEST pattern. 8650 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8651 DAG.getConstant(0, Op.getValueType())); 8652 8653 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8654 SmallVector<SDValue, 4> Ops; 8655 for (unsigned i = 0; i != NumOperands; ++i) 8656 Ops.push_back(Op.getOperand(i)); 8657 8658 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8659 DAG.ReplaceAllUsesWith(Op, New); 8660 return SDValue(New.getNode(), 1); 8661} 8662 8663/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8664/// equivalent. 8665SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8666 SelectionDAG &DAG) const { 8667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8668 if (C->getAPIntValue() == 0) 8669 return EmitTest(Op0, X86CC, DAG); 8670 8671 DebugLoc dl = Op0.getDebugLoc(); 8672 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || 8673 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { 8674 // Use SUB instead of CMP to enable CSE between SUB and CMP. 8675 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); 8676 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, 8677 Op0, Op1); 8678 return SDValue(Sub.getNode(), 1); 8679 } 8680 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8681} 8682 8683/// Convert a comparison if required by the subtarget. 8684SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 8685 SelectionDAG &DAG) const { 8686 // If the subtarget does not support the FUCOMI instruction, floating-point 8687 // comparisons have to be converted. 8688 if (Subtarget->hasCMov() || 8689 Cmp.getOpcode() != X86ISD::CMP || 8690 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 8691 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 8692 return Cmp; 8693 8694 // The instruction selector will select an FUCOM instruction instead of 8695 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 8696 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 8697 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 8698 DebugLoc dl = Cmp.getDebugLoc(); 8699 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 8700 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 8701 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 8702 DAG.getConstant(8, MVT::i8)); 8703 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 8704 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 8705} 8706 8707/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8708/// if it's possible. 8709SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8710 DebugLoc dl, SelectionDAG &DAG) const { 8711 SDValue Op0 = And.getOperand(0); 8712 SDValue Op1 = And.getOperand(1); 8713 if (Op0.getOpcode() == ISD::TRUNCATE) 8714 Op0 = Op0.getOperand(0); 8715 if (Op1.getOpcode() == ISD::TRUNCATE) 8716 Op1 = Op1.getOperand(0); 8717 8718 SDValue LHS, RHS; 8719 if (Op1.getOpcode() == ISD::SHL) 8720 std::swap(Op0, Op1); 8721 if (Op0.getOpcode() == ISD::SHL) { 8722 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8723 if (And00C->getZExtValue() == 1) { 8724 // If we looked past a truncate, check that it's only truncating away 8725 // known zeros. 8726 unsigned BitWidth = Op0.getValueSizeInBits(); 8727 unsigned AndBitWidth = And.getValueSizeInBits(); 8728 if (BitWidth > AndBitWidth) { 8729 APInt Zeros, Ones; 8730 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8731 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8732 return SDValue(); 8733 } 8734 LHS = Op1; 8735 RHS = Op0.getOperand(1); 8736 } 8737 } else if (Op1.getOpcode() == ISD::Constant) { 8738 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8739 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8740 SDValue AndLHS = Op0; 8741 8742 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8743 LHS = AndLHS.getOperand(0); 8744 RHS = AndLHS.getOperand(1); 8745 } 8746 8747 // Use BT if the immediate can't be encoded in a TEST instruction. 8748 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8749 LHS = AndLHS; 8750 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8751 } 8752 } 8753 8754 if (LHS.getNode()) { 8755 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8756 // instruction. Since the shift amount is in-range-or-undefined, we know 8757 // that doing a bittest on the i32 value is ok. We extend to i32 because 8758 // the encoding for the i16 version is larger than the i32 version. 8759 // Also promote i16 to i32 for performance / code size reason. 8760 if (LHS.getValueType() == MVT::i8 || 8761 LHS.getValueType() == MVT::i16) 8762 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8763 8764 // If the operand types disagree, extend the shift amount to match. Since 8765 // BT ignores high bits (like shifts) we can use anyextend. 8766 if (LHS.getValueType() != RHS.getValueType()) 8767 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8768 8769 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8770 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8771 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8772 DAG.getConstant(Cond, MVT::i8), BT); 8773 } 8774 8775 return SDValue(); 8776} 8777 8778SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8779 8780 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8781 8782 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8783 SDValue Op0 = Op.getOperand(0); 8784 SDValue Op1 = Op.getOperand(1); 8785 DebugLoc dl = Op.getDebugLoc(); 8786 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8787 8788 // Optimize to BT if possible. 8789 // Lower (X & (1 << N)) == 0 to BT(X, N). 8790 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8791 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8792 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8793 Op1.getOpcode() == ISD::Constant && 8794 cast<ConstantSDNode>(Op1)->isNullValue() && 8795 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8796 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8797 if (NewSetCC.getNode()) 8798 return NewSetCC; 8799 } 8800 8801 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8802 // these. 8803 if (Op1.getOpcode() == ISD::Constant && 8804 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8805 cast<ConstantSDNode>(Op1)->isNullValue()) && 8806 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8807 8808 // If the input is a setcc, then reuse the input setcc or use a new one with 8809 // the inverted condition. 8810 if (Op0.getOpcode() == X86ISD::SETCC) { 8811 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8812 bool Invert = (CC == ISD::SETNE) ^ 8813 cast<ConstantSDNode>(Op1)->isNullValue(); 8814 if (!Invert) return Op0; 8815 8816 CCode = X86::GetOppositeBranchCondition(CCode); 8817 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8818 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8819 } 8820 } 8821 8822 bool isFP = Op1.getValueType().isFloatingPoint(); 8823 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8824 if (X86CC == X86::COND_INVALID) 8825 return SDValue(); 8826 8827 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8828 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 8829 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8830 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8831} 8832 8833// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8834// ones, and then concatenate the result back. 8835static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8836 EVT VT = Op.getValueType(); 8837 8838 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && 8839 "Unsupported value type for operation"); 8840 8841 unsigned NumElems = VT.getVectorNumElements(); 8842 DebugLoc dl = Op.getDebugLoc(); 8843 SDValue CC = Op.getOperand(2); 8844 8845 // Extract the LHS vectors 8846 SDValue LHS = Op.getOperand(0); 8847 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 8848 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 8849 8850 // Extract the RHS vectors 8851 SDValue RHS = Op.getOperand(1); 8852 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 8853 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 8854 8855 // Issue the operation on the smaller types and concatenate the result back 8856 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8857 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8858 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8859 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8860 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8861} 8862 8863 8864SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8865 SDValue Cond; 8866 SDValue Op0 = Op.getOperand(0); 8867 SDValue Op1 = Op.getOperand(1); 8868 SDValue CC = Op.getOperand(2); 8869 EVT VT = Op.getValueType(); 8870 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8871 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8872 DebugLoc dl = Op.getDebugLoc(); 8873 8874 if (isFP) { 8875#ifndef NDEBUG 8876 EVT EltVT = Op0.getValueType().getVectorElementType(); 8877 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8878#endif 8879 8880 unsigned SSECC; 8881 bool Swap = false; 8882 8883 // SSE Condition code mapping: 8884 // 0 - EQ 8885 // 1 - LT 8886 // 2 - LE 8887 // 3 - UNORD 8888 // 4 - NEQ 8889 // 5 - NLT 8890 // 6 - NLE 8891 // 7 - ORD 8892 switch (SetCCOpcode) { 8893 default: llvm_unreachable("Unexpected SETCC condition"); 8894 case ISD::SETOEQ: 8895 case ISD::SETEQ: SSECC = 0; break; 8896 case ISD::SETOGT: 8897 case ISD::SETGT: Swap = true; // Fallthrough 8898 case ISD::SETLT: 8899 case ISD::SETOLT: SSECC = 1; break; 8900 case ISD::SETOGE: 8901 case ISD::SETGE: Swap = true; // Fallthrough 8902 case ISD::SETLE: 8903 case ISD::SETOLE: SSECC = 2; break; 8904 case ISD::SETUO: SSECC = 3; break; 8905 case ISD::SETUNE: 8906 case ISD::SETNE: SSECC = 4; break; 8907 case ISD::SETULE: Swap = true; // Fallthrough 8908 case ISD::SETUGE: SSECC = 5; break; 8909 case ISD::SETULT: Swap = true; // Fallthrough 8910 case ISD::SETUGT: SSECC = 6; break; 8911 case ISD::SETO: SSECC = 7; break; 8912 case ISD::SETUEQ: 8913 case ISD::SETONE: SSECC = 8; break; 8914 } 8915 if (Swap) 8916 std::swap(Op0, Op1); 8917 8918 // In the two special cases we can't handle, emit two comparisons. 8919 if (SSECC == 8) { 8920 unsigned CC0, CC1; 8921 unsigned CombineOpc; 8922 if (SetCCOpcode == ISD::SETUEQ) { 8923 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR; 8924 } else { 8925 assert(SetCCOpcode == ISD::SETONE); 8926 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND; 8927 } 8928 8929 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8930 DAG.getConstant(CC0, MVT::i8)); 8931 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8932 DAG.getConstant(CC1, MVT::i8)); 8933 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); 8934 } 8935 // Handle all other FP comparisons here. 8936 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8937 DAG.getConstant(SSECC, MVT::i8)); 8938 } 8939 8940 // Break 256-bit integer vector compare into smaller ones. 8941 if (VT.is256BitVector() && !Subtarget->hasAVX2()) 8942 return Lower256IntVSETCC(Op, DAG); 8943 8944 // We are handling one of the integer comparisons here. Since SSE only has 8945 // GT and EQ comparisons for integer, swapping operands and multiple 8946 // operations may be required for some comparisons. 8947 unsigned Opc; 8948 bool Swap = false, Invert = false, FlipSigns = false; 8949 8950 switch (SetCCOpcode) { 8951 default: llvm_unreachable("Unexpected SETCC condition"); 8952 case ISD::SETNE: Invert = true; 8953 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8954 case ISD::SETLT: Swap = true; 8955 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8956 case ISD::SETGE: Swap = true; 8957 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8958 case ISD::SETULT: Swap = true; 8959 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8960 case ISD::SETUGE: Swap = true; 8961 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8962 } 8963 if (Swap) 8964 std::swap(Op0, Op1); 8965 8966 // Check that the operation in question is available (most are plain SSE2, 8967 // but PCMPGTQ and PCMPEQQ have different requirements). 8968 if (VT == MVT::v2i64) { 8969 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) 8970 return SDValue(); 8971 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) 8972 return SDValue(); 8973 } 8974 8975 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8976 // bits of the inputs before performing those operations. 8977 if (FlipSigns) { 8978 EVT EltVT = VT.getVectorElementType(); 8979 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8980 EltVT); 8981 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8982 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8983 SignBits.size()); 8984 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8985 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8986 } 8987 8988 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8989 8990 // If the logical-not of the result is required, perform that now. 8991 if (Invert) 8992 Result = DAG.getNOT(dl, Result, VT); 8993 8994 return Result; 8995} 8996 8997// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8998static bool isX86LogicalCmp(SDValue Op) { 8999 unsigned Opc = Op.getNode()->getOpcode(); 9000 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 9001 Opc == X86ISD::SAHF) 9002 return true; 9003 if (Op.getResNo() == 1 && 9004 (Opc == X86ISD::ADD || 9005 Opc == X86ISD::SUB || 9006 Opc == X86ISD::ADC || 9007 Opc == X86ISD::SBB || 9008 Opc == X86ISD::SMUL || 9009 Opc == X86ISD::UMUL || 9010 Opc == X86ISD::INC || 9011 Opc == X86ISD::DEC || 9012 Opc == X86ISD::OR || 9013 Opc == X86ISD::XOR || 9014 Opc == X86ISD::AND)) 9015 return true; 9016 9017 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 9018 return true; 9019 9020 return false; 9021} 9022 9023static bool isZero(SDValue V) { 9024 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9025 return C && C->isNullValue(); 9026} 9027 9028static bool isAllOnes(SDValue V) { 9029 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9030 return C && C->isAllOnesValue(); 9031} 9032 9033static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) { 9034 if (V.getOpcode() != ISD::TRUNCATE) 9035 return false; 9036 9037 SDValue VOp0 = V.getOperand(0); 9038 unsigned InBits = VOp0.getValueSizeInBits(); 9039 unsigned Bits = V.getValueSizeInBits(); 9040 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits)); 9041} 9042 9043SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 9044 bool addTest = true; 9045 SDValue Cond = Op.getOperand(0); 9046 SDValue Op1 = Op.getOperand(1); 9047 SDValue Op2 = Op.getOperand(2); 9048 DebugLoc DL = Op.getDebugLoc(); 9049 SDValue CC; 9050 9051 if (Cond.getOpcode() == ISD::SETCC) { 9052 SDValue NewCond = LowerSETCC(Cond, DAG); 9053 if (NewCond.getNode()) 9054 Cond = NewCond; 9055 } 9056 9057 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 9058 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 9059 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 9060 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 9061 if (Cond.getOpcode() == X86ISD::SETCC && 9062 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 9063 isZero(Cond.getOperand(1).getOperand(1))) { 9064 SDValue Cmp = Cond.getOperand(1); 9065 9066 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 9067 9068 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 9069 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 9070 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 9071 9072 SDValue CmpOp0 = Cmp.getOperand(0); 9073 // Apply further optimizations for special cases 9074 // (select (x != 0), -1, 0) -> neg & sbb 9075 // (select (x == 0), 0, -1) -> neg & sbb 9076 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 9077 if (YC->isNullValue() && 9078 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 9079 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 9080 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 9081 DAG.getConstant(0, CmpOp0.getValueType()), 9082 CmpOp0); 9083 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9084 DAG.getConstant(X86::COND_B, MVT::i8), 9085 SDValue(Neg.getNode(), 1)); 9086 return Res; 9087 } 9088 9089 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 9090 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 9091 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9092 9093 SDValue Res = // Res = 0 or -1. 9094 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9095 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 9096 9097 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 9098 Res = DAG.getNOT(DL, Res, Res.getValueType()); 9099 9100 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 9101 if (N2C == 0 || !N2C->isNullValue()) 9102 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 9103 return Res; 9104 } 9105 } 9106 9107 // Look past (and (setcc_carry (cmp ...)), 1). 9108 if (Cond.getOpcode() == ISD::AND && 9109 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9110 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9111 if (C && C->getAPIntValue() == 1) 9112 Cond = Cond.getOperand(0); 9113 } 9114 9115 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9116 // setting operand in place of the X86ISD::SETCC. 9117 unsigned CondOpcode = Cond.getOpcode(); 9118 if (CondOpcode == X86ISD::SETCC || 9119 CondOpcode == X86ISD::SETCC_CARRY) { 9120 CC = Cond.getOperand(0); 9121 9122 SDValue Cmp = Cond.getOperand(1); 9123 unsigned Opc = Cmp.getOpcode(); 9124 EVT VT = Op.getValueType(); 9125 9126 bool IllegalFPCMov = false; 9127 if (VT.isFloatingPoint() && !VT.isVector() && 9128 !isScalarFPTypeInSSEReg(VT)) // FPStack? 9129 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 9130 9131 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 9132 Opc == X86ISD::BT) { // FIXME 9133 Cond = Cmp; 9134 addTest = false; 9135 } 9136 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9137 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9138 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9139 Cond.getOperand(0).getValueType() != MVT::i8)) { 9140 SDValue LHS = Cond.getOperand(0); 9141 SDValue RHS = Cond.getOperand(1); 9142 unsigned X86Opcode; 9143 unsigned X86Cond; 9144 SDVTList VTs; 9145 switch (CondOpcode) { 9146 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9147 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9148 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9149 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9150 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9151 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9152 default: llvm_unreachable("unexpected overflowing operator"); 9153 } 9154 if (CondOpcode == ISD::UMULO) 9155 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9156 MVT::i32); 9157 else 9158 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9159 9160 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 9161 9162 if (CondOpcode == ISD::UMULO) 9163 Cond = X86Op.getValue(2); 9164 else 9165 Cond = X86Op.getValue(1); 9166 9167 CC = DAG.getConstant(X86Cond, MVT::i8); 9168 addTest = false; 9169 } 9170 9171 if (addTest) { 9172 // Look pass the truncate if the high bits are known zero. 9173 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9174 Cond = Cond.getOperand(0); 9175 9176 // We know the result of AND is compared against zero. Try to match 9177 // it to BT. 9178 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9179 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 9180 if (NewSetCC.getNode()) { 9181 CC = NewSetCC.getOperand(0); 9182 Cond = NewSetCC.getOperand(1); 9183 addTest = false; 9184 } 9185 } 9186 } 9187 9188 if (addTest) { 9189 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9190 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9191 } 9192 9193 // a < b ? -1 : 0 -> RES = ~setcc_carry 9194 // a < b ? 0 : -1 -> RES = setcc_carry 9195 // a >= b ? -1 : 0 -> RES = setcc_carry 9196 // a >= b ? 0 : -1 -> RES = ~setcc_carry 9197 if (Cond.getOpcode() == X86ISD::SUB) { 9198 Cond = ConvertCmpIfNecessary(Cond, DAG); 9199 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 9200 9201 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 9202 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 9203 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9204 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 9205 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 9206 return DAG.getNOT(DL, Res, Res.getValueType()); 9207 return Res; 9208 } 9209 } 9210 9211 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 9212 // condition is true. 9213 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 9214 SDValue Ops[] = { Op2, Op1, CC, Cond }; 9215 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 9216} 9217 9218// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 9219// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 9220// from the AND / OR. 9221static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 9222 Opc = Op.getOpcode(); 9223 if (Opc != ISD::OR && Opc != ISD::AND) 9224 return false; 9225 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9226 Op.getOperand(0).hasOneUse() && 9227 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 9228 Op.getOperand(1).hasOneUse()); 9229} 9230 9231// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 9232// 1 and that the SETCC node has a single use. 9233static bool isXor1OfSetCC(SDValue Op) { 9234 if (Op.getOpcode() != ISD::XOR) 9235 return false; 9236 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9237 if (N1C && N1C->getAPIntValue() == 1) { 9238 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9239 Op.getOperand(0).hasOneUse(); 9240 } 9241 return false; 9242} 9243 9244SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 9245 bool addTest = true; 9246 SDValue Chain = Op.getOperand(0); 9247 SDValue Cond = Op.getOperand(1); 9248 SDValue Dest = Op.getOperand(2); 9249 DebugLoc dl = Op.getDebugLoc(); 9250 SDValue CC; 9251 bool Inverted = false; 9252 9253 if (Cond.getOpcode() == ISD::SETCC) { 9254 // Check for setcc([su]{add,sub,mul}o == 0). 9255 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 9256 isa<ConstantSDNode>(Cond.getOperand(1)) && 9257 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 9258 Cond.getOperand(0).getResNo() == 1 && 9259 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 9260 Cond.getOperand(0).getOpcode() == ISD::UADDO || 9261 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 9262 Cond.getOperand(0).getOpcode() == ISD::USUBO || 9263 Cond.getOperand(0).getOpcode() == ISD::SMULO || 9264 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 9265 Inverted = true; 9266 Cond = Cond.getOperand(0); 9267 } else { 9268 SDValue NewCond = LowerSETCC(Cond, DAG); 9269 if (NewCond.getNode()) 9270 Cond = NewCond; 9271 } 9272 } 9273#if 0 9274 // FIXME: LowerXALUO doesn't handle these!! 9275 else if (Cond.getOpcode() == X86ISD::ADD || 9276 Cond.getOpcode() == X86ISD::SUB || 9277 Cond.getOpcode() == X86ISD::SMUL || 9278 Cond.getOpcode() == X86ISD::UMUL) 9279 Cond = LowerXALUO(Cond, DAG); 9280#endif 9281 9282 // Look pass (and (setcc_carry (cmp ...)), 1). 9283 if (Cond.getOpcode() == ISD::AND && 9284 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9285 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9286 if (C && C->getAPIntValue() == 1) 9287 Cond = Cond.getOperand(0); 9288 } 9289 9290 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9291 // setting operand in place of the X86ISD::SETCC. 9292 unsigned CondOpcode = Cond.getOpcode(); 9293 if (CondOpcode == X86ISD::SETCC || 9294 CondOpcode == X86ISD::SETCC_CARRY) { 9295 CC = Cond.getOperand(0); 9296 9297 SDValue Cmp = Cond.getOperand(1); 9298 unsigned Opc = Cmp.getOpcode(); 9299 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 9300 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 9301 Cond = Cmp; 9302 addTest = false; 9303 } else { 9304 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 9305 default: break; 9306 case X86::COND_O: 9307 case X86::COND_B: 9308 // These can only come from an arithmetic instruction with overflow, 9309 // e.g. SADDO, UADDO. 9310 Cond = Cond.getNode()->getOperand(1); 9311 addTest = false; 9312 break; 9313 } 9314 } 9315 } 9316 CondOpcode = Cond.getOpcode(); 9317 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9318 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9319 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9320 Cond.getOperand(0).getValueType() != MVT::i8)) { 9321 SDValue LHS = Cond.getOperand(0); 9322 SDValue RHS = Cond.getOperand(1); 9323 unsigned X86Opcode; 9324 unsigned X86Cond; 9325 SDVTList VTs; 9326 switch (CondOpcode) { 9327 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9328 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9329 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9330 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9331 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9332 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9333 default: llvm_unreachable("unexpected overflowing operator"); 9334 } 9335 if (Inverted) 9336 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 9337 if (CondOpcode == ISD::UMULO) 9338 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9339 MVT::i32); 9340 else 9341 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9342 9343 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 9344 9345 if (CondOpcode == ISD::UMULO) 9346 Cond = X86Op.getValue(2); 9347 else 9348 Cond = X86Op.getValue(1); 9349 9350 CC = DAG.getConstant(X86Cond, MVT::i8); 9351 addTest = false; 9352 } else { 9353 unsigned CondOpc; 9354 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 9355 SDValue Cmp = Cond.getOperand(0).getOperand(1); 9356 if (CondOpc == ISD::OR) { 9357 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 9358 // two branches instead of an explicit OR instruction with a 9359 // separate test. 9360 if (Cmp == Cond.getOperand(1).getOperand(1) && 9361 isX86LogicalCmp(Cmp)) { 9362 CC = Cond.getOperand(0).getOperand(0); 9363 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9364 Chain, Dest, CC, Cmp); 9365 CC = Cond.getOperand(1).getOperand(0); 9366 Cond = Cmp; 9367 addTest = false; 9368 } 9369 } else { // ISD::AND 9370 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9371 // two branches instead of an explicit AND instruction with a 9372 // separate test. However, we only do this if this block doesn't 9373 // have a fall-through edge, because this requires an explicit 9374 // jmp when the condition is false. 9375 if (Cmp == Cond.getOperand(1).getOperand(1) && 9376 isX86LogicalCmp(Cmp) && 9377 Op.getNode()->hasOneUse()) { 9378 X86::CondCode CCode = 9379 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9380 CCode = X86::GetOppositeBranchCondition(CCode); 9381 CC = DAG.getConstant(CCode, MVT::i8); 9382 SDNode *User = *Op.getNode()->use_begin(); 9383 // Look for an unconditional branch following this conditional branch. 9384 // We need this because we need to reverse the successors in order 9385 // to implement FCMP_OEQ. 9386 if (User->getOpcode() == ISD::BR) { 9387 SDValue FalseBB = User->getOperand(1); 9388 SDNode *NewBR = 9389 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9390 assert(NewBR == User); 9391 (void)NewBR; 9392 Dest = FalseBB; 9393 9394 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9395 Chain, Dest, CC, Cmp); 9396 X86::CondCode CCode = 9397 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9398 CCode = X86::GetOppositeBranchCondition(CCode); 9399 CC = DAG.getConstant(CCode, MVT::i8); 9400 Cond = Cmp; 9401 addTest = false; 9402 } 9403 } 9404 } 9405 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9406 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9407 // It should be transformed during dag combiner except when the condition 9408 // is set by a arithmetics with overflow node. 9409 X86::CondCode CCode = 9410 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9411 CCode = X86::GetOppositeBranchCondition(CCode); 9412 CC = DAG.getConstant(CCode, MVT::i8); 9413 Cond = Cond.getOperand(0).getOperand(1); 9414 addTest = false; 9415 } else if (Cond.getOpcode() == ISD::SETCC && 9416 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9417 // For FCMP_OEQ, we can emit 9418 // two branches instead of an explicit AND instruction with a 9419 // separate test. However, we only do this if this block doesn't 9420 // have a fall-through edge, because this requires an explicit 9421 // jmp when the condition is false. 9422 if (Op.getNode()->hasOneUse()) { 9423 SDNode *User = *Op.getNode()->use_begin(); 9424 // Look for an unconditional branch following this conditional branch. 9425 // We need this because we need to reverse the successors in order 9426 // to implement FCMP_OEQ. 9427 if (User->getOpcode() == ISD::BR) { 9428 SDValue FalseBB = User->getOperand(1); 9429 SDNode *NewBR = 9430 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9431 assert(NewBR == User); 9432 (void)NewBR; 9433 Dest = FalseBB; 9434 9435 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9436 Cond.getOperand(0), Cond.getOperand(1)); 9437 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9438 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9439 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9440 Chain, Dest, CC, Cmp); 9441 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9442 Cond = Cmp; 9443 addTest = false; 9444 } 9445 } 9446 } else if (Cond.getOpcode() == ISD::SETCC && 9447 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9448 // For FCMP_UNE, we can emit 9449 // two branches instead of an explicit AND instruction with a 9450 // separate test. However, we only do this if this block doesn't 9451 // have a fall-through edge, because this requires an explicit 9452 // jmp when the condition is false. 9453 if (Op.getNode()->hasOneUse()) { 9454 SDNode *User = *Op.getNode()->use_begin(); 9455 // Look for an unconditional branch following this conditional branch. 9456 // We need this because we need to reverse the successors in order 9457 // to implement FCMP_UNE. 9458 if (User->getOpcode() == ISD::BR) { 9459 SDValue FalseBB = User->getOperand(1); 9460 SDNode *NewBR = 9461 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9462 assert(NewBR == User); 9463 (void)NewBR; 9464 9465 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9466 Cond.getOperand(0), Cond.getOperand(1)); 9467 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9468 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9469 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9470 Chain, Dest, CC, Cmp); 9471 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9472 Cond = Cmp; 9473 addTest = false; 9474 Dest = FalseBB; 9475 } 9476 } 9477 } 9478 } 9479 9480 if (addTest) { 9481 // Look pass the truncate if the high bits are known zero. 9482 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9483 Cond = Cond.getOperand(0); 9484 9485 // We know the result of AND is compared against zero. Try to match 9486 // it to BT. 9487 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9488 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9489 if (NewSetCC.getNode()) { 9490 CC = NewSetCC.getOperand(0); 9491 Cond = NewSetCC.getOperand(1); 9492 addTest = false; 9493 } 9494 } 9495 } 9496 9497 if (addTest) { 9498 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9499 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9500 } 9501 Cond = ConvertCmpIfNecessary(Cond, DAG); 9502 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9503 Chain, Dest, CC, Cond); 9504} 9505 9506 9507// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9508// Calls to _alloca is needed to probe the stack when allocating more than 4k 9509// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9510// that the guard pages used by the OS virtual memory manager are allocated in 9511// correct sequence. 9512SDValue 9513X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9514 SelectionDAG &DAG) const { 9515 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9516 getTargetMachine().Options.EnableSegmentedStacks) && 9517 "This should be used only on Windows targets or when segmented stacks " 9518 "are being used"); 9519 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9520 DebugLoc dl = Op.getDebugLoc(); 9521 9522 // Get the inputs. 9523 SDValue Chain = Op.getOperand(0); 9524 SDValue Size = Op.getOperand(1); 9525 // FIXME: Ensure alignment here 9526 9527 bool Is64Bit = Subtarget->is64Bit(); 9528 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9529 9530 if (getTargetMachine().Options.EnableSegmentedStacks) { 9531 MachineFunction &MF = DAG.getMachineFunction(); 9532 MachineRegisterInfo &MRI = MF.getRegInfo(); 9533 9534 if (Is64Bit) { 9535 // The 64 bit implementation of segmented stacks needs to clobber both r10 9536 // r11. This makes it impossible to use it along with nested parameters. 9537 const Function *F = MF.getFunction(); 9538 9539 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9540 I != E; ++I) 9541 if (I->hasNestAttr()) 9542 report_fatal_error("Cannot use segmented stacks with functions that " 9543 "have nested arguments."); 9544 } 9545 9546 const TargetRegisterClass *AddrRegClass = 9547 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9548 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9549 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9550 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9551 DAG.getRegister(Vreg, SPTy)); 9552 SDValue Ops1[2] = { Value, Chain }; 9553 return DAG.getMergeValues(Ops1, 2, dl); 9554 } else { 9555 SDValue Flag; 9556 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9557 9558 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9559 Flag = Chain.getValue(1); 9560 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9561 9562 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9563 Flag = Chain.getValue(1); 9564 9565 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9566 9567 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9568 return DAG.getMergeValues(Ops1, 2, dl); 9569 } 9570} 9571 9572SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9573 MachineFunction &MF = DAG.getMachineFunction(); 9574 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9575 9576 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9577 DebugLoc DL = Op.getDebugLoc(); 9578 9579 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9580 // vastart just stores the address of the VarArgsFrameIndex slot into the 9581 // memory location argument. 9582 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9583 getPointerTy()); 9584 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9585 MachinePointerInfo(SV), false, false, 0); 9586 } 9587 9588 // __va_list_tag: 9589 // gp_offset (0 - 6 * 8) 9590 // fp_offset (48 - 48 + 8 * 16) 9591 // overflow_arg_area (point to parameters coming in memory). 9592 // reg_save_area 9593 SmallVector<SDValue, 8> MemOps; 9594 SDValue FIN = Op.getOperand(1); 9595 // Store gp_offset 9596 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9597 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9598 MVT::i32), 9599 FIN, MachinePointerInfo(SV), false, false, 0); 9600 MemOps.push_back(Store); 9601 9602 // Store fp_offset 9603 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9604 FIN, DAG.getIntPtrConstant(4)); 9605 Store = DAG.getStore(Op.getOperand(0), DL, 9606 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9607 MVT::i32), 9608 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9609 MemOps.push_back(Store); 9610 9611 // Store ptr to overflow_arg_area 9612 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9613 FIN, DAG.getIntPtrConstant(4)); 9614 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9615 getPointerTy()); 9616 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9617 MachinePointerInfo(SV, 8), 9618 false, false, 0); 9619 MemOps.push_back(Store); 9620 9621 // Store ptr to reg_save_area. 9622 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9623 FIN, DAG.getIntPtrConstant(8)); 9624 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9625 getPointerTy()); 9626 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9627 MachinePointerInfo(SV, 16), false, false, 0); 9628 MemOps.push_back(Store); 9629 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9630 &MemOps[0], MemOps.size()); 9631} 9632 9633SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9634 assert(Subtarget->is64Bit() && 9635 "LowerVAARG only handles 64-bit va_arg!"); 9636 assert((Subtarget->isTargetLinux() || 9637 Subtarget->isTargetDarwin()) && 9638 "Unhandled target in LowerVAARG"); 9639 assert(Op.getNode()->getNumOperands() == 4); 9640 SDValue Chain = Op.getOperand(0); 9641 SDValue SrcPtr = Op.getOperand(1); 9642 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9643 unsigned Align = Op.getConstantOperandVal(3); 9644 DebugLoc dl = Op.getDebugLoc(); 9645 9646 EVT ArgVT = Op.getNode()->getValueType(0); 9647 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9648 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9649 uint8_t ArgMode; 9650 9651 // Decide which area this value should be read from. 9652 // TODO: Implement the AMD64 ABI in its entirety. This simple 9653 // selection mechanism works only for the basic types. 9654 if (ArgVT == MVT::f80) { 9655 llvm_unreachable("va_arg for f80 not yet implemented"); 9656 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9657 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9658 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9659 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9660 } else { 9661 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9662 } 9663 9664 if (ArgMode == 2) { 9665 // Sanity Check: Make sure using fp_offset makes sense. 9666 assert(!getTargetMachine().Options.UseSoftFloat && 9667 !(DAG.getMachineFunction() 9668 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9669 Subtarget->hasSSE1()); 9670 } 9671 9672 // Insert VAARG_64 node into the DAG 9673 // VAARG_64 returns two values: Variable Argument Address, Chain 9674 SmallVector<SDValue, 11> InstOps; 9675 InstOps.push_back(Chain); 9676 InstOps.push_back(SrcPtr); 9677 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9678 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9679 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9680 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9681 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9682 VTs, &InstOps[0], InstOps.size(), 9683 MVT::i64, 9684 MachinePointerInfo(SV), 9685 /*Align=*/0, 9686 /*Volatile=*/false, 9687 /*ReadMem=*/true, 9688 /*WriteMem=*/true); 9689 Chain = VAARG.getValue(1); 9690 9691 // Load the next argument and return it 9692 return DAG.getLoad(ArgVT, dl, 9693 Chain, 9694 VAARG, 9695 MachinePointerInfo(), 9696 false, false, false, 0); 9697} 9698 9699static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, 9700 SelectionDAG &DAG) { 9701 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9702 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9703 SDValue Chain = Op.getOperand(0); 9704 SDValue DstPtr = Op.getOperand(1); 9705 SDValue SrcPtr = Op.getOperand(2); 9706 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9707 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9708 DebugLoc DL = Op.getDebugLoc(); 9709 9710 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9711 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9712 false, 9713 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9714} 9715 9716// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9717// may or may not be a constant. Takes immediate version of shift as input. 9718static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9719 SDValue SrcOp, SDValue ShAmt, 9720 SelectionDAG &DAG) { 9721 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9722 9723 if (isa<ConstantSDNode>(ShAmt)) { 9724 // Constant may be a TargetConstant. Use a regular constant. 9725 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 9726 switch (Opc) { 9727 default: llvm_unreachable("Unknown target vector shift node"); 9728 case X86ISD::VSHLI: 9729 case X86ISD::VSRLI: 9730 case X86ISD::VSRAI: 9731 return DAG.getNode(Opc, dl, VT, SrcOp, 9732 DAG.getConstant(ShiftAmt, MVT::i32)); 9733 } 9734 } 9735 9736 // Change opcode to non-immediate version 9737 switch (Opc) { 9738 default: llvm_unreachable("Unknown target vector shift node"); 9739 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9740 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9741 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9742 } 9743 9744 // Need to build a vector containing shift amount 9745 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9746 SDValue ShOps[4]; 9747 ShOps[0] = ShAmt; 9748 ShOps[1] = DAG.getConstant(0, MVT::i32); 9749 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32); 9750 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9751 9752 // The return type has to be a 128-bit type with the same element 9753 // type as the input type. 9754 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9755 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); 9756 9757 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt); 9758 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9759} 9760 9761static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 9762 DebugLoc dl = Op.getDebugLoc(); 9763 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9764 switch (IntNo) { 9765 default: return SDValue(); // Don't custom lower most intrinsics. 9766 // Comparison intrinsics. 9767 case Intrinsic::x86_sse_comieq_ss: 9768 case Intrinsic::x86_sse_comilt_ss: 9769 case Intrinsic::x86_sse_comile_ss: 9770 case Intrinsic::x86_sse_comigt_ss: 9771 case Intrinsic::x86_sse_comige_ss: 9772 case Intrinsic::x86_sse_comineq_ss: 9773 case Intrinsic::x86_sse_ucomieq_ss: 9774 case Intrinsic::x86_sse_ucomilt_ss: 9775 case Intrinsic::x86_sse_ucomile_ss: 9776 case Intrinsic::x86_sse_ucomigt_ss: 9777 case Intrinsic::x86_sse_ucomige_ss: 9778 case Intrinsic::x86_sse_ucomineq_ss: 9779 case Intrinsic::x86_sse2_comieq_sd: 9780 case Intrinsic::x86_sse2_comilt_sd: 9781 case Intrinsic::x86_sse2_comile_sd: 9782 case Intrinsic::x86_sse2_comigt_sd: 9783 case Intrinsic::x86_sse2_comige_sd: 9784 case Intrinsic::x86_sse2_comineq_sd: 9785 case Intrinsic::x86_sse2_ucomieq_sd: 9786 case Intrinsic::x86_sse2_ucomilt_sd: 9787 case Intrinsic::x86_sse2_ucomile_sd: 9788 case Intrinsic::x86_sse2_ucomigt_sd: 9789 case Intrinsic::x86_sse2_ucomige_sd: 9790 case Intrinsic::x86_sse2_ucomineq_sd: { 9791 unsigned Opc; 9792 ISD::CondCode CC; 9793 switch (IntNo) { 9794 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9795 case Intrinsic::x86_sse_comieq_ss: 9796 case Intrinsic::x86_sse2_comieq_sd: 9797 Opc = X86ISD::COMI; 9798 CC = ISD::SETEQ; 9799 break; 9800 case Intrinsic::x86_sse_comilt_ss: 9801 case Intrinsic::x86_sse2_comilt_sd: 9802 Opc = X86ISD::COMI; 9803 CC = ISD::SETLT; 9804 break; 9805 case Intrinsic::x86_sse_comile_ss: 9806 case Intrinsic::x86_sse2_comile_sd: 9807 Opc = X86ISD::COMI; 9808 CC = ISD::SETLE; 9809 break; 9810 case Intrinsic::x86_sse_comigt_ss: 9811 case Intrinsic::x86_sse2_comigt_sd: 9812 Opc = X86ISD::COMI; 9813 CC = ISD::SETGT; 9814 break; 9815 case Intrinsic::x86_sse_comige_ss: 9816 case Intrinsic::x86_sse2_comige_sd: 9817 Opc = X86ISD::COMI; 9818 CC = ISD::SETGE; 9819 break; 9820 case Intrinsic::x86_sse_comineq_ss: 9821 case Intrinsic::x86_sse2_comineq_sd: 9822 Opc = X86ISD::COMI; 9823 CC = ISD::SETNE; 9824 break; 9825 case Intrinsic::x86_sse_ucomieq_ss: 9826 case Intrinsic::x86_sse2_ucomieq_sd: 9827 Opc = X86ISD::UCOMI; 9828 CC = ISD::SETEQ; 9829 break; 9830 case Intrinsic::x86_sse_ucomilt_ss: 9831 case Intrinsic::x86_sse2_ucomilt_sd: 9832 Opc = X86ISD::UCOMI; 9833 CC = ISD::SETLT; 9834 break; 9835 case Intrinsic::x86_sse_ucomile_ss: 9836 case Intrinsic::x86_sse2_ucomile_sd: 9837 Opc = X86ISD::UCOMI; 9838 CC = ISD::SETLE; 9839 break; 9840 case Intrinsic::x86_sse_ucomigt_ss: 9841 case Intrinsic::x86_sse2_ucomigt_sd: 9842 Opc = X86ISD::UCOMI; 9843 CC = ISD::SETGT; 9844 break; 9845 case Intrinsic::x86_sse_ucomige_ss: 9846 case Intrinsic::x86_sse2_ucomige_sd: 9847 Opc = X86ISD::UCOMI; 9848 CC = ISD::SETGE; 9849 break; 9850 case Intrinsic::x86_sse_ucomineq_ss: 9851 case Intrinsic::x86_sse2_ucomineq_sd: 9852 Opc = X86ISD::UCOMI; 9853 CC = ISD::SETNE; 9854 break; 9855 } 9856 9857 SDValue LHS = Op.getOperand(1); 9858 SDValue RHS = Op.getOperand(2); 9859 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9860 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9861 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9862 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9863 DAG.getConstant(X86CC, MVT::i8), Cond); 9864 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9865 } 9866 9867 // Arithmetic intrinsics. 9868 case Intrinsic::x86_sse2_pmulu_dq: 9869 case Intrinsic::x86_avx2_pmulu_dq: 9870 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9871 Op.getOperand(1), Op.getOperand(2)); 9872 9873 // SSE3/AVX horizontal add/sub intrinsics 9874 case Intrinsic::x86_sse3_hadd_ps: 9875 case Intrinsic::x86_sse3_hadd_pd: 9876 case Intrinsic::x86_avx_hadd_ps_256: 9877 case Intrinsic::x86_avx_hadd_pd_256: 9878 case Intrinsic::x86_sse3_hsub_ps: 9879 case Intrinsic::x86_sse3_hsub_pd: 9880 case Intrinsic::x86_avx_hsub_ps_256: 9881 case Intrinsic::x86_avx_hsub_pd_256: 9882 case Intrinsic::x86_ssse3_phadd_w_128: 9883 case Intrinsic::x86_ssse3_phadd_d_128: 9884 case Intrinsic::x86_avx2_phadd_w: 9885 case Intrinsic::x86_avx2_phadd_d: 9886 case Intrinsic::x86_ssse3_phsub_w_128: 9887 case Intrinsic::x86_ssse3_phsub_d_128: 9888 case Intrinsic::x86_avx2_phsub_w: 9889 case Intrinsic::x86_avx2_phsub_d: { 9890 unsigned Opcode; 9891 switch (IntNo) { 9892 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9893 case Intrinsic::x86_sse3_hadd_ps: 9894 case Intrinsic::x86_sse3_hadd_pd: 9895 case Intrinsic::x86_avx_hadd_ps_256: 9896 case Intrinsic::x86_avx_hadd_pd_256: 9897 Opcode = X86ISD::FHADD; 9898 break; 9899 case Intrinsic::x86_sse3_hsub_ps: 9900 case Intrinsic::x86_sse3_hsub_pd: 9901 case Intrinsic::x86_avx_hsub_ps_256: 9902 case Intrinsic::x86_avx_hsub_pd_256: 9903 Opcode = X86ISD::FHSUB; 9904 break; 9905 case Intrinsic::x86_ssse3_phadd_w_128: 9906 case Intrinsic::x86_ssse3_phadd_d_128: 9907 case Intrinsic::x86_avx2_phadd_w: 9908 case Intrinsic::x86_avx2_phadd_d: 9909 Opcode = X86ISD::HADD; 9910 break; 9911 case Intrinsic::x86_ssse3_phsub_w_128: 9912 case Intrinsic::x86_ssse3_phsub_d_128: 9913 case Intrinsic::x86_avx2_phsub_w: 9914 case Intrinsic::x86_avx2_phsub_d: 9915 Opcode = X86ISD::HSUB; 9916 break; 9917 } 9918 return DAG.getNode(Opcode, dl, Op.getValueType(), 9919 Op.getOperand(1), Op.getOperand(2)); 9920 } 9921 9922 // AVX2 variable shift intrinsics 9923 case Intrinsic::x86_avx2_psllv_d: 9924 case Intrinsic::x86_avx2_psllv_q: 9925 case Intrinsic::x86_avx2_psllv_d_256: 9926 case Intrinsic::x86_avx2_psllv_q_256: 9927 case Intrinsic::x86_avx2_psrlv_d: 9928 case Intrinsic::x86_avx2_psrlv_q: 9929 case Intrinsic::x86_avx2_psrlv_d_256: 9930 case Intrinsic::x86_avx2_psrlv_q_256: 9931 case Intrinsic::x86_avx2_psrav_d: 9932 case Intrinsic::x86_avx2_psrav_d_256: { 9933 unsigned Opcode; 9934 switch (IntNo) { 9935 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9936 case Intrinsic::x86_avx2_psllv_d: 9937 case Intrinsic::x86_avx2_psllv_q: 9938 case Intrinsic::x86_avx2_psllv_d_256: 9939 case Intrinsic::x86_avx2_psllv_q_256: 9940 Opcode = ISD::SHL; 9941 break; 9942 case Intrinsic::x86_avx2_psrlv_d: 9943 case Intrinsic::x86_avx2_psrlv_q: 9944 case Intrinsic::x86_avx2_psrlv_d_256: 9945 case Intrinsic::x86_avx2_psrlv_q_256: 9946 Opcode = ISD::SRL; 9947 break; 9948 case Intrinsic::x86_avx2_psrav_d: 9949 case Intrinsic::x86_avx2_psrav_d_256: 9950 Opcode = ISD::SRA; 9951 break; 9952 } 9953 return DAG.getNode(Opcode, dl, Op.getValueType(), 9954 Op.getOperand(1), Op.getOperand(2)); 9955 } 9956 9957 case Intrinsic::x86_ssse3_pshuf_b_128: 9958 case Intrinsic::x86_avx2_pshuf_b: 9959 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9960 Op.getOperand(1), Op.getOperand(2)); 9961 9962 case Intrinsic::x86_ssse3_psign_b_128: 9963 case Intrinsic::x86_ssse3_psign_w_128: 9964 case Intrinsic::x86_ssse3_psign_d_128: 9965 case Intrinsic::x86_avx2_psign_b: 9966 case Intrinsic::x86_avx2_psign_w: 9967 case Intrinsic::x86_avx2_psign_d: 9968 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9969 Op.getOperand(1), Op.getOperand(2)); 9970 9971 case Intrinsic::x86_sse41_insertps: 9972 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9973 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9974 9975 case Intrinsic::x86_avx_vperm2f128_ps_256: 9976 case Intrinsic::x86_avx_vperm2f128_pd_256: 9977 case Intrinsic::x86_avx_vperm2f128_si_256: 9978 case Intrinsic::x86_avx2_vperm2i128: 9979 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9980 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9981 9982 case Intrinsic::x86_avx2_permd: 9983 case Intrinsic::x86_avx2_permps: 9984 // Operands intentionally swapped. Mask is last operand to intrinsic, 9985 // but second operand for node/intruction. 9986 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9987 Op.getOperand(2), Op.getOperand(1)); 9988 9989 // ptest and testp intrinsics. The intrinsic these come from are designed to 9990 // return an integer value, not just an instruction so lower it to the ptest 9991 // or testp pattern and a setcc for the result. 9992 case Intrinsic::x86_sse41_ptestz: 9993 case Intrinsic::x86_sse41_ptestc: 9994 case Intrinsic::x86_sse41_ptestnzc: 9995 case Intrinsic::x86_avx_ptestz_256: 9996 case Intrinsic::x86_avx_ptestc_256: 9997 case Intrinsic::x86_avx_ptestnzc_256: 9998 case Intrinsic::x86_avx_vtestz_ps: 9999 case Intrinsic::x86_avx_vtestc_ps: 10000 case Intrinsic::x86_avx_vtestnzc_ps: 10001 case Intrinsic::x86_avx_vtestz_pd: 10002 case Intrinsic::x86_avx_vtestc_pd: 10003 case Intrinsic::x86_avx_vtestnzc_pd: 10004 case Intrinsic::x86_avx_vtestz_ps_256: 10005 case Intrinsic::x86_avx_vtestc_ps_256: 10006 case Intrinsic::x86_avx_vtestnzc_ps_256: 10007 case Intrinsic::x86_avx_vtestz_pd_256: 10008 case Intrinsic::x86_avx_vtestc_pd_256: 10009 case Intrinsic::x86_avx_vtestnzc_pd_256: { 10010 bool IsTestPacked = false; 10011 unsigned X86CC; 10012 switch (IntNo) { 10013 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 10014 case Intrinsic::x86_avx_vtestz_ps: 10015 case Intrinsic::x86_avx_vtestz_pd: 10016 case Intrinsic::x86_avx_vtestz_ps_256: 10017 case Intrinsic::x86_avx_vtestz_pd_256: 10018 IsTestPacked = true; // Fallthrough 10019 case Intrinsic::x86_sse41_ptestz: 10020 case Intrinsic::x86_avx_ptestz_256: 10021 // ZF = 1 10022 X86CC = X86::COND_E; 10023 break; 10024 case Intrinsic::x86_avx_vtestc_ps: 10025 case Intrinsic::x86_avx_vtestc_pd: 10026 case Intrinsic::x86_avx_vtestc_ps_256: 10027 case Intrinsic::x86_avx_vtestc_pd_256: 10028 IsTestPacked = true; // Fallthrough 10029 case Intrinsic::x86_sse41_ptestc: 10030 case Intrinsic::x86_avx_ptestc_256: 10031 // CF = 1 10032 X86CC = X86::COND_B; 10033 break; 10034 case Intrinsic::x86_avx_vtestnzc_ps: 10035 case Intrinsic::x86_avx_vtestnzc_pd: 10036 case Intrinsic::x86_avx_vtestnzc_ps_256: 10037 case Intrinsic::x86_avx_vtestnzc_pd_256: 10038 IsTestPacked = true; // Fallthrough 10039 case Intrinsic::x86_sse41_ptestnzc: 10040 case Intrinsic::x86_avx_ptestnzc_256: 10041 // ZF and CF = 0 10042 X86CC = X86::COND_A; 10043 break; 10044 } 10045 10046 SDValue LHS = Op.getOperand(1); 10047 SDValue RHS = Op.getOperand(2); 10048 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 10049 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 10050 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 10051 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 10052 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10053 } 10054 10055 // SSE/AVX shift intrinsics 10056 case Intrinsic::x86_sse2_psll_w: 10057 case Intrinsic::x86_sse2_psll_d: 10058 case Intrinsic::x86_sse2_psll_q: 10059 case Intrinsic::x86_avx2_psll_w: 10060 case Intrinsic::x86_avx2_psll_d: 10061 case Intrinsic::x86_avx2_psll_q: 10062 case Intrinsic::x86_sse2_psrl_w: 10063 case Intrinsic::x86_sse2_psrl_d: 10064 case Intrinsic::x86_sse2_psrl_q: 10065 case Intrinsic::x86_avx2_psrl_w: 10066 case Intrinsic::x86_avx2_psrl_d: 10067 case Intrinsic::x86_avx2_psrl_q: 10068 case Intrinsic::x86_sse2_psra_w: 10069 case Intrinsic::x86_sse2_psra_d: 10070 case Intrinsic::x86_avx2_psra_w: 10071 case Intrinsic::x86_avx2_psra_d: { 10072 unsigned Opcode; 10073 switch (IntNo) { 10074 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10075 case Intrinsic::x86_sse2_psll_w: 10076 case Intrinsic::x86_sse2_psll_d: 10077 case Intrinsic::x86_sse2_psll_q: 10078 case Intrinsic::x86_avx2_psll_w: 10079 case Intrinsic::x86_avx2_psll_d: 10080 case Intrinsic::x86_avx2_psll_q: 10081 Opcode = X86ISD::VSHL; 10082 break; 10083 case Intrinsic::x86_sse2_psrl_w: 10084 case Intrinsic::x86_sse2_psrl_d: 10085 case Intrinsic::x86_sse2_psrl_q: 10086 case Intrinsic::x86_avx2_psrl_w: 10087 case Intrinsic::x86_avx2_psrl_d: 10088 case Intrinsic::x86_avx2_psrl_q: 10089 Opcode = X86ISD::VSRL; 10090 break; 10091 case Intrinsic::x86_sse2_psra_w: 10092 case Intrinsic::x86_sse2_psra_d: 10093 case Intrinsic::x86_avx2_psra_w: 10094 case Intrinsic::x86_avx2_psra_d: 10095 Opcode = X86ISD::VSRA; 10096 break; 10097 } 10098 return DAG.getNode(Opcode, dl, Op.getValueType(), 10099 Op.getOperand(1), Op.getOperand(2)); 10100 } 10101 10102 // SSE/AVX immediate shift intrinsics 10103 case Intrinsic::x86_sse2_pslli_w: 10104 case Intrinsic::x86_sse2_pslli_d: 10105 case Intrinsic::x86_sse2_pslli_q: 10106 case Intrinsic::x86_avx2_pslli_w: 10107 case Intrinsic::x86_avx2_pslli_d: 10108 case Intrinsic::x86_avx2_pslli_q: 10109 case Intrinsic::x86_sse2_psrli_w: 10110 case Intrinsic::x86_sse2_psrli_d: 10111 case Intrinsic::x86_sse2_psrli_q: 10112 case Intrinsic::x86_avx2_psrli_w: 10113 case Intrinsic::x86_avx2_psrli_d: 10114 case Intrinsic::x86_avx2_psrli_q: 10115 case Intrinsic::x86_sse2_psrai_w: 10116 case Intrinsic::x86_sse2_psrai_d: 10117 case Intrinsic::x86_avx2_psrai_w: 10118 case Intrinsic::x86_avx2_psrai_d: { 10119 unsigned Opcode; 10120 switch (IntNo) { 10121 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10122 case Intrinsic::x86_sse2_pslli_w: 10123 case Intrinsic::x86_sse2_pslli_d: 10124 case Intrinsic::x86_sse2_pslli_q: 10125 case Intrinsic::x86_avx2_pslli_w: 10126 case Intrinsic::x86_avx2_pslli_d: 10127 case Intrinsic::x86_avx2_pslli_q: 10128 Opcode = X86ISD::VSHLI; 10129 break; 10130 case Intrinsic::x86_sse2_psrli_w: 10131 case Intrinsic::x86_sse2_psrli_d: 10132 case Intrinsic::x86_sse2_psrli_q: 10133 case Intrinsic::x86_avx2_psrli_w: 10134 case Intrinsic::x86_avx2_psrli_d: 10135 case Intrinsic::x86_avx2_psrli_q: 10136 Opcode = X86ISD::VSRLI; 10137 break; 10138 case Intrinsic::x86_sse2_psrai_w: 10139 case Intrinsic::x86_sse2_psrai_d: 10140 case Intrinsic::x86_avx2_psrai_w: 10141 case Intrinsic::x86_avx2_psrai_d: 10142 Opcode = X86ISD::VSRAI; 10143 break; 10144 } 10145 return getTargetVShiftNode(Opcode, dl, Op.getValueType(), 10146 Op.getOperand(1), Op.getOperand(2), DAG); 10147 } 10148 10149 case Intrinsic::x86_sse42_pcmpistria128: 10150 case Intrinsic::x86_sse42_pcmpestria128: 10151 case Intrinsic::x86_sse42_pcmpistric128: 10152 case Intrinsic::x86_sse42_pcmpestric128: 10153 case Intrinsic::x86_sse42_pcmpistrio128: 10154 case Intrinsic::x86_sse42_pcmpestrio128: 10155 case Intrinsic::x86_sse42_pcmpistris128: 10156 case Intrinsic::x86_sse42_pcmpestris128: 10157 case Intrinsic::x86_sse42_pcmpistriz128: 10158 case Intrinsic::x86_sse42_pcmpestriz128: { 10159 unsigned Opcode; 10160 unsigned X86CC; 10161 switch (IntNo) { 10162 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10163 case Intrinsic::x86_sse42_pcmpistria128: 10164 Opcode = X86ISD::PCMPISTRI; 10165 X86CC = X86::COND_A; 10166 break; 10167 case Intrinsic::x86_sse42_pcmpestria128: 10168 Opcode = X86ISD::PCMPESTRI; 10169 X86CC = X86::COND_A; 10170 break; 10171 case Intrinsic::x86_sse42_pcmpistric128: 10172 Opcode = X86ISD::PCMPISTRI; 10173 X86CC = X86::COND_B; 10174 break; 10175 case Intrinsic::x86_sse42_pcmpestric128: 10176 Opcode = X86ISD::PCMPESTRI; 10177 X86CC = X86::COND_B; 10178 break; 10179 case Intrinsic::x86_sse42_pcmpistrio128: 10180 Opcode = X86ISD::PCMPISTRI; 10181 X86CC = X86::COND_O; 10182 break; 10183 case Intrinsic::x86_sse42_pcmpestrio128: 10184 Opcode = X86ISD::PCMPESTRI; 10185 X86CC = X86::COND_O; 10186 break; 10187 case Intrinsic::x86_sse42_pcmpistris128: 10188 Opcode = X86ISD::PCMPISTRI; 10189 X86CC = X86::COND_S; 10190 break; 10191 case Intrinsic::x86_sse42_pcmpestris128: 10192 Opcode = X86ISD::PCMPESTRI; 10193 X86CC = X86::COND_S; 10194 break; 10195 case Intrinsic::x86_sse42_pcmpistriz128: 10196 Opcode = X86ISD::PCMPISTRI; 10197 X86CC = X86::COND_E; 10198 break; 10199 case Intrinsic::x86_sse42_pcmpestriz128: 10200 Opcode = X86ISD::PCMPESTRI; 10201 X86CC = X86::COND_E; 10202 break; 10203 } 10204 SmallVector<SDValue, 5> NewOps; 10205 NewOps.append(Op->op_begin()+1, Op->op_end()); 10206 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10207 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10208 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10209 DAG.getConstant(X86CC, MVT::i8), 10210 SDValue(PCMP.getNode(), 1)); 10211 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10212 } 10213 10214 case Intrinsic::x86_sse42_pcmpistri128: 10215 case Intrinsic::x86_sse42_pcmpestri128: { 10216 unsigned Opcode; 10217 if (IntNo == Intrinsic::x86_sse42_pcmpistri128) 10218 Opcode = X86ISD::PCMPISTRI; 10219 else 10220 Opcode = X86ISD::PCMPESTRI; 10221 10222 SmallVector<SDValue, 5> NewOps; 10223 NewOps.append(Op->op_begin()+1, Op->op_end()); 10224 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10225 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10226 } 10227 case Intrinsic::x86_fma_vfmadd_ps: 10228 case Intrinsic::x86_fma_vfmadd_pd: 10229 case Intrinsic::x86_fma_vfmsub_ps: 10230 case Intrinsic::x86_fma_vfmsub_pd: 10231 case Intrinsic::x86_fma_vfnmadd_ps: 10232 case Intrinsic::x86_fma_vfnmadd_pd: 10233 case Intrinsic::x86_fma_vfnmsub_ps: 10234 case Intrinsic::x86_fma_vfnmsub_pd: 10235 case Intrinsic::x86_fma_vfmaddsub_ps: 10236 case Intrinsic::x86_fma_vfmaddsub_pd: 10237 case Intrinsic::x86_fma_vfmsubadd_ps: 10238 case Intrinsic::x86_fma_vfmsubadd_pd: 10239 case Intrinsic::x86_fma_vfmadd_ps_256: 10240 case Intrinsic::x86_fma_vfmadd_pd_256: 10241 case Intrinsic::x86_fma_vfmsub_ps_256: 10242 case Intrinsic::x86_fma_vfmsub_pd_256: 10243 case Intrinsic::x86_fma_vfnmadd_ps_256: 10244 case Intrinsic::x86_fma_vfnmadd_pd_256: 10245 case Intrinsic::x86_fma_vfnmsub_ps_256: 10246 case Intrinsic::x86_fma_vfnmsub_pd_256: 10247 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10248 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10249 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10250 case Intrinsic::x86_fma_vfmsubadd_pd_256: { 10251 unsigned Opc; 10252 switch (IntNo) { 10253 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10254 case Intrinsic::x86_fma_vfmadd_ps: 10255 case Intrinsic::x86_fma_vfmadd_pd: 10256 case Intrinsic::x86_fma_vfmadd_ps_256: 10257 case Intrinsic::x86_fma_vfmadd_pd_256: 10258 Opc = X86ISD::FMADD; 10259 break; 10260 case Intrinsic::x86_fma_vfmsub_ps: 10261 case Intrinsic::x86_fma_vfmsub_pd: 10262 case Intrinsic::x86_fma_vfmsub_ps_256: 10263 case Intrinsic::x86_fma_vfmsub_pd_256: 10264 Opc = X86ISD::FMSUB; 10265 break; 10266 case Intrinsic::x86_fma_vfnmadd_ps: 10267 case Intrinsic::x86_fma_vfnmadd_pd: 10268 case Intrinsic::x86_fma_vfnmadd_ps_256: 10269 case Intrinsic::x86_fma_vfnmadd_pd_256: 10270 Opc = X86ISD::FNMADD; 10271 break; 10272 case Intrinsic::x86_fma_vfnmsub_ps: 10273 case Intrinsic::x86_fma_vfnmsub_pd: 10274 case Intrinsic::x86_fma_vfnmsub_ps_256: 10275 case Intrinsic::x86_fma_vfnmsub_pd_256: 10276 Opc = X86ISD::FNMSUB; 10277 break; 10278 case Intrinsic::x86_fma_vfmaddsub_ps: 10279 case Intrinsic::x86_fma_vfmaddsub_pd: 10280 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10281 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10282 Opc = X86ISD::FMADDSUB; 10283 break; 10284 case Intrinsic::x86_fma_vfmsubadd_ps: 10285 case Intrinsic::x86_fma_vfmsubadd_pd: 10286 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10287 case Intrinsic::x86_fma_vfmsubadd_pd_256: 10288 Opc = X86ISD::FMSUBADD; 10289 break; 10290 } 10291 10292 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1), 10293 Op.getOperand(2), Op.getOperand(3)); 10294 } 10295 } 10296} 10297 10298static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) { 10299 DebugLoc dl = Op.getDebugLoc(); 10300 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10301 switch (IntNo) { 10302 default: return SDValue(); // Don't custom lower most intrinsics. 10303 10304 // RDRAND intrinsics. 10305 case Intrinsic::x86_rdrand_16: 10306 case Intrinsic::x86_rdrand_32: 10307 case Intrinsic::x86_rdrand_64: { 10308 // Emit the node with the right value type. 10309 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other); 10310 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0)); 10311 10312 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise 10313 // return the value from Rand, which is always 0, casted to i32. 10314 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)), 10315 DAG.getConstant(1, Op->getValueType(1)), 10316 DAG.getConstant(X86::COND_B, MVT::i32), 10317 SDValue(Result.getNode(), 1) }; 10318 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, 10319 DAG.getVTList(Op->getValueType(1), MVT::Glue), 10320 Ops, 4); 10321 10322 // Return { result, isValid, chain }. 10323 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 10324 SDValue(Result.getNode(), 2)); 10325 } 10326 } 10327} 10328 10329SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 10330 SelectionDAG &DAG) const { 10331 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10332 MFI->setReturnAddressIsTaken(true); 10333 10334 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10335 DebugLoc dl = Op.getDebugLoc(); 10336 10337 if (Depth > 0) { 10338 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 10339 SDValue Offset = 10340 DAG.getConstant(TD->getPointerSize(), 10341 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 10342 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 10343 DAG.getNode(ISD::ADD, dl, getPointerTy(), 10344 FrameAddr, Offset), 10345 MachinePointerInfo(), false, false, false, 0); 10346 } 10347 10348 // Just load the return address. 10349 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 10350 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 10351 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 10352} 10353 10354SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 10355 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10356 MFI->setFrameAddressIsTaken(true); 10357 10358 EVT VT = Op.getValueType(); 10359 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 10360 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10361 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 10362 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 10363 while (Depth--) 10364 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 10365 MachinePointerInfo(), 10366 false, false, false, 0); 10367 return FrameAddr; 10368} 10369 10370SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 10371 SelectionDAG &DAG) const { 10372 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 10373} 10374 10375SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 10376 SDValue Chain = Op.getOperand(0); 10377 SDValue Offset = Op.getOperand(1); 10378 SDValue Handler = Op.getOperand(2); 10379 DebugLoc dl = Op.getDebugLoc(); 10380 10381 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 10382 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 10383 getPointerTy()); 10384 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 10385 10386 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 10387 DAG.getIntPtrConstant(TD->getPointerSize())); 10388 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 10389 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 10390 false, false, 0); 10391 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 10392 10393 return DAG.getNode(X86ISD::EH_RETURN, dl, 10394 MVT::Other, 10395 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 10396} 10397 10398static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 10399 return Op.getOperand(0); 10400} 10401 10402SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 10403 SelectionDAG &DAG) const { 10404 SDValue Root = Op.getOperand(0); 10405 SDValue Trmp = Op.getOperand(1); // trampoline 10406 SDValue FPtr = Op.getOperand(2); // nested function 10407 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 10408 DebugLoc dl = Op.getDebugLoc(); 10409 10410 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 10411 10412 if (Subtarget->is64Bit()) { 10413 SDValue OutChains[6]; 10414 10415 // Large code-model. 10416 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 10417 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 10418 10419 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 10420 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 10421 10422 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 10423 10424 // Load the pointer to the nested function into R11. 10425 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 10426 SDValue Addr = Trmp; 10427 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10428 Addr, MachinePointerInfo(TrmpAddr), 10429 false, false, 0); 10430 10431 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10432 DAG.getConstant(2, MVT::i64)); 10433 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 10434 MachinePointerInfo(TrmpAddr, 2), 10435 false, false, 2); 10436 10437 // Load the 'nest' parameter value into R10. 10438 // R10 is specified in X86CallingConv.td 10439 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 10440 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10441 DAG.getConstant(10, MVT::i64)); 10442 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10443 Addr, MachinePointerInfo(TrmpAddr, 10), 10444 false, false, 0); 10445 10446 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10447 DAG.getConstant(12, MVT::i64)); 10448 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 10449 MachinePointerInfo(TrmpAddr, 12), 10450 false, false, 2); 10451 10452 // Jump to the nested function. 10453 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 10454 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10455 DAG.getConstant(20, MVT::i64)); 10456 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10457 Addr, MachinePointerInfo(TrmpAddr, 20), 10458 false, false, 0); 10459 10460 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 10461 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10462 DAG.getConstant(22, MVT::i64)); 10463 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 10464 MachinePointerInfo(TrmpAddr, 22), 10465 false, false, 0); 10466 10467 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 10468 } else { 10469 const Function *Func = 10470 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 10471 CallingConv::ID CC = Func->getCallingConv(); 10472 unsigned NestReg; 10473 10474 switch (CC) { 10475 default: 10476 llvm_unreachable("Unsupported calling convention"); 10477 case CallingConv::C: 10478 case CallingConv::X86_StdCall: { 10479 // Pass 'nest' parameter in ECX. 10480 // Must be kept in sync with X86CallingConv.td 10481 NestReg = X86::ECX; 10482 10483 // Check that ECX wasn't needed by an 'inreg' parameter. 10484 FunctionType *FTy = Func->getFunctionType(); 10485 const AttrListPtr &Attrs = Func->getAttributes(); 10486 10487 if (!Attrs.isEmpty() && !Func->isVarArg()) { 10488 unsigned InRegCount = 0; 10489 unsigned Idx = 1; 10490 10491 for (FunctionType::param_iterator I = FTy->param_begin(), 10492 E = FTy->param_end(); I != E; ++I, ++Idx) 10493 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 10494 // FIXME: should only count parameters that are lowered to integers. 10495 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 10496 10497 if (InRegCount > 2) { 10498 report_fatal_error("Nest register in use - reduce number of inreg" 10499 " parameters!"); 10500 } 10501 } 10502 break; 10503 } 10504 case CallingConv::X86_FastCall: 10505 case CallingConv::X86_ThisCall: 10506 case CallingConv::Fast: 10507 // Pass 'nest' parameter in EAX. 10508 // Must be kept in sync with X86CallingConv.td 10509 NestReg = X86::EAX; 10510 break; 10511 } 10512 10513 SDValue OutChains[4]; 10514 SDValue Addr, Disp; 10515 10516 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10517 DAG.getConstant(10, MVT::i32)); 10518 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 10519 10520 // This is storing the opcode for MOV32ri. 10521 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 10522 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 10523 OutChains[0] = DAG.getStore(Root, dl, 10524 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 10525 Trmp, MachinePointerInfo(TrmpAddr), 10526 false, false, 0); 10527 10528 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10529 DAG.getConstant(1, MVT::i32)); 10530 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10531 MachinePointerInfo(TrmpAddr, 1), 10532 false, false, 1); 10533 10534 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10535 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10536 DAG.getConstant(5, MVT::i32)); 10537 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10538 MachinePointerInfo(TrmpAddr, 5), 10539 false, false, 1); 10540 10541 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10542 DAG.getConstant(6, MVT::i32)); 10543 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10544 MachinePointerInfo(TrmpAddr, 6), 10545 false, false, 1); 10546 10547 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10548 } 10549} 10550 10551SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10552 SelectionDAG &DAG) const { 10553 /* 10554 The rounding mode is in bits 11:10 of FPSR, and has the following 10555 settings: 10556 00 Round to nearest 10557 01 Round to -inf 10558 10 Round to +inf 10559 11 Round to 0 10560 10561 FLT_ROUNDS, on the other hand, expects the following: 10562 -1 Undefined 10563 0 Round to 0 10564 1 Round to nearest 10565 2 Round to +inf 10566 3 Round to -inf 10567 10568 To perform the conversion, we do: 10569 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10570 */ 10571 10572 MachineFunction &MF = DAG.getMachineFunction(); 10573 const TargetMachine &TM = MF.getTarget(); 10574 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10575 unsigned StackAlignment = TFI.getStackAlignment(); 10576 EVT VT = Op.getValueType(); 10577 DebugLoc DL = Op.getDebugLoc(); 10578 10579 // Save FP Control Word to stack slot 10580 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10581 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10582 10583 10584 MachineMemOperand *MMO = 10585 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10586 MachineMemOperand::MOStore, 2, 2); 10587 10588 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10589 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10590 DAG.getVTList(MVT::Other), 10591 Ops, 2, MVT::i16, MMO); 10592 10593 // Load FP Control Word from stack slot 10594 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10595 MachinePointerInfo(), false, false, false, 0); 10596 10597 // Transform as necessary 10598 SDValue CWD1 = 10599 DAG.getNode(ISD::SRL, DL, MVT::i16, 10600 DAG.getNode(ISD::AND, DL, MVT::i16, 10601 CWD, DAG.getConstant(0x800, MVT::i16)), 10602 DAG.getConstant(11, MVT::i8)); 10603 SDValue CWD2 = 10604 DAG.getNode(ISD::SRL, DL, MVT::i16, 10605 DAG.getNode(ISD::AND, DL, MVT::i16, 10606 CWD, DAG.getConstant(0x400, MVT::i16)), 10607 DAG.getConstant(9, MVT::i8)); 10608 10609 SDValue RetVal = 10610 DAG.getNode(ISD::AND, DL, MVT::i16, 10611 DAG.getNode(ISD::ADD, DL, MVT::i16, 10612 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10613 DAG.getConstant(1, MVT::i16)), 10614 DAG.getConstant(3, MVT::i16)); 10615 10616 10617 return DAG.getNode((VT.getSizeInBits() < 16 ? 10618 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10619} 10620 10621static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 10622 EVT VT = Op.getValueType(); 10623 EVT OpVT = VT; 10624 unsigned NumBits = VT.getSizeInBits(); 10625 DebugLoc dl = Op.getDebugLoc(); 10626 10627 Op = Op.getOperand(0); 10628 if (VT == MVT::i8) { 10629 // Zero extend to i32 since there is not an i8 bsr. 10630 OpVT = MVT::i32; 10631 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10632 } 10633 10634 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10635 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10636 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10637 10638 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10639 SDValue Ops[] = { 10640 Op, 10641 DAG.getConstant(NumBits+NumBits-1, OpVT), 10642 DAG.getConstant(X86::COND_E, MVT::i8), 10643 Op.getValue(1) 10644 }; 10645 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10646 10647 // Finally xor with NumBits-1. 10648 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10649 10650 if (VT == MVT::i8) 10651 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10652 return Op; 10653} 10654 10655static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) { 10656 EVT VT = Op.getValueType(); 10657 EVT OpVT = VT; 10658 unsigned NumBits = VT.getSizeInBits(); 10659 DebugLoc dl = Op.getDebugLoc(); 10660 10661 Op = Op.getOperand(0); 10662 if (VT == MVT::i8) { 10663 // Zero extend to i32 since there is not an i8 bsr. 10664 OpVT = MVT::i32; 10665 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10666 } 10667 10668 // Issue a bsr (scan bits in reverse). 10669 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10670 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10671 10672 // And xor with NumBits-1. 10673 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10674 10675 if (VT == MVT::i8) 10676 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10677 return Op; 10678} 10679 10680static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 10681 EVT VT = Op.getValueType(); 10682 unsigned NumBits = VT.getSizeInBits(); 10683 DebugLoc dl = Op.getDebugLoc(); 10684 Op = Op.getOperand(0); 10685 10686 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10687 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10688 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10689 10690 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10691 SDValue Ops[] = { 10692 Op, 10693 DAG.getConstant(NumBits, VT), 10694 DAG.getConstant(X86::COND_E, MVT::i8), 10695 Op.getValue(1) 10696 }; 10697 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10698} 10699 10700// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10701// ones, and then concatenate the result back. 10702static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10703 EVT VT = Op.getValueType(); 10704 10705 assert(VT.is256BitVector() && VT.isInteger() && 10706 "Unsupported value type for operation"); 10707 10708 unsigned NumElems = VT.getVectorNumElements(); 10709 DebugLoc dl = Op.getDebugLoc(); 10710 10711 // Extract the LHS vectors 10712 SDValue LHS = Op.getOperand(0); 10713 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10714 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10715 10716 // Extract the RHS vectors 10717 SDValue RHS = Op.getOperand(1); 10718 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 10719 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 10720 10721 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10722 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10723 10724 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10725 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10726 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10727} 10728 10729static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) { 10730 assert(Op.getValueType().is256BitVector() && 10731 Op.getValueType().isInteger() && 10732 "Only handle AVX 256-bit vector integer operation"); 10733 return Lower256IntArith(Op, DAG); 10734} 10735 10736static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) { 10737 assert(Op.getValueType().is256BitVector() && 10738 Op.getValueType().isInteger() && 10739 "Only handle AVX 256-bit vector integer operation"); 10740 return Lower256IntArith(Op, DAG); 10741} 10742 10743static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget, 10744 SelectionDAG &DAG) { 10745 EVT VT = Op.getValueType(); 10746 10747 // Decompose 256-bit ops into smaller 128-bit ops. 10748 if (VT.is256BitVector() && !Subtarget->hasAVX2()) 10749 return Lower256IntArith(Op, DAG); 10750 10751 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10752 "Only know how to lower V2I64/V4I64 multiply"); 10753 10754 DebugLoc dl = Op.getDebugLoc(); 10755 10756 // Ahi = psrlqi(a, 32); 10757 // Bhi = psrlqi(b, 32); 10758 // 10759 // AloBlo = pmuludq(a, b); 10760 // AloBhi = pmuludq(a, Bhi); 10761 // AhiBlo = pmuludq(Ahi, b); 10762 10763 // AloBhi = psllqi(AloBhi, 32); 10764 // AhiBlo = psllqi(AhiBlo, 32); 10765 // return AloBlo + AloBhi + AhiBlo; 10766 10767 SDValue A = Op.getOperand(0); 10768 SDValue B = Op.getOperand(1); 10769 10770 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10771 10772 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10773 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10774 10775 // Bit cast to 32-bit vectors for MULUDQ 10776 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10777 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10778 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10779 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10780 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10781 10782 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10783 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10784 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10785 10786 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10787 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10788 10789 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10790 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10791} 10792 10793SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10794 10795 EVT VT = Op.getValueType(); 10796 DebugLoc dl = Op.getDebugLoc(); 10797 SDValue R = Op.getOperand(0); 10798 SDValue Amt = Op.getOperand(1); 10799 LLVMContext *Context = DAG.getContext(); 10800 10801 if (!Subtarget->hasSSE2()) 10802 return SDValue(); 10803 10804 // Optimize shl/srl/sra with constant shift amount. 10805 if (isSplatVector(Amt.getNode())) { 10806 SDValue SclrAmt = Amt->getOperand(0); 10807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10808 uint64_t ShiftAmt = C->getZExtValue(); 10809 10810 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10811 (Subtarget->hasAVX2() && 10812 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10813 if (Op.getOpcode() == ISD::SHL) 10814 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10815 DAG.getConstant(ShiftAmt, MVT::i32)); 10816 if (Op.getOpcode() == ISD::SRL) 10817 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10818 DAG.getConstant(ShiftAmt, MVT::i32)); 10819 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10820 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10821 DAG.getConstant(ShiftAmt, MVT::i32)); 10822 } 10823 10824 if (VT == MVT::v16i8) { 10825 if (Op.getOpcode() == ISD::SHL) { 10826 // Make a large shift. 10827 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10828 DAG.getConstant(ShiftAmt, MVT::i32)); 10829 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10830 // Zero out the rightmost bits. 10831 SmallVector<SDValue, 16> V(16, 10832 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10833 MVT::i8)); 10834 return DAG.getNode(ISD::AND, dl, VT, SHL, 10835 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10836 } 10837 if (Op.getOpcode() == ISD::SRL) { 10838 // Make a large shift. 10839 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10840 DAG.getConstant(ShiftAmt, MVT::i32)); 10841 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10842 // Zero out the leftmost bits. 10843 SmallVector<SDValue, 16> V(16, 10844 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10845 MVT::i8)); 10846 return DAG.getNode(ISD::AND, dl, VT, SRL, 10847 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10848 } 10849 if (Op.getOpcode() == ISD::SRA) { 10850 if (ShiftAmt == 7) { 10851 // R s>> 7 === R s< 0 10852 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10853 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10854 } 10855 10856 // R s>> a === ((R u>> a) ^ m) - m 10857 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10858 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10859 MVT::i8)); 10860 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10861 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10862 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10863 return Res; 10864 } 10865 llvm_unreachable("Unknown shift opcode."); 10866 } 10867 10868 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10869 if (Op.getOpcode() == ISD::SHL) { 10870 // Make a large shift. 10871 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10872 DAG.getConstant(ShiftAmt, MVT::i32)); 10873 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10874 // Zero out the rightmost bits. 10875 SmallVector<SDValue, 32> V(32, 10876 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10877 MVT::i8)); 10878 return DAG.getNode(ISD::AND, dl, VT, SHL, 10879 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10880 } 10881 if (Op.getOpcode() == ISD::SRL) { 10882 // Make a large shift. 10883 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10884 DAG.getConstant(ShiftAmt, MVT::i32)); 10885 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10886 // Zero out the leftmost bits. 10887 SmallVector<SDValue, 32> V(32, 10888 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10889 MVT::i8)); 10890 return DAG.getNode(ISD::AND, dl, VT, SRL, 10891 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10892 } 10893 if (Op.getOpcode() == ISD::SRA) { 10894 if (ShiftAmt == 7) { 10895 // R s>> 7 === R s< 0 10896 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10897 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10898 } 10899 10900 // R s>> a === ((R u>> a) ^ m) - m 10901 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10902 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10903 MVT::i8)); 10904 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10905 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10906 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10907 return Res; 10908 } 10909 llvm_unreachable("Unknown shift opcode."); 10910 } 10911 } 10912 } 10913 10914 // Lower SHL with variable shift amount. 10915 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10916 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10917 DAG.getConstant(23, MVT::i32)); 10918 10919 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10920 Constant *C = ConstantDataVector::get(*Context, CV); 10921 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10922 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10923 MachinePointerInfo::getConstantPool(), 10924 false, false, false, 16); 10925 10926 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10927 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10928 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10929 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10930 } 10931 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10932 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10933 10934 // a = a << 5; 10935 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10936 DAG.getConstant(5, MVT::i32)); 10937 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10938 10939 // Turn 'a' into a mask suitable for VSELECT 10940 SDValue VSelM = DAG.getConstant(0x80, VT); 10941 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10942 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10943 10944 SDValue CM1 = DAG.getConstant(0x0f, VT); 10945 SDValue CM2 = DAG.getConstant(0x3f, VT); 10946 10947 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10948 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10949 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10950 DAG.getConstant(4, MVT::i32), DAG); 10951 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10952 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10953 10954 // a += a 10955 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10956 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10957 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10958 10959 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10960 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10961 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10962 DAG.getConstant(2, MVT::i32), DAG); 10963 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10964 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10965 10966 // a += a 10967 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10968 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10969 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10970 10971 // return VSELECT(r, r+r, a); 10972 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10973 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10974 return R; 10975 } 10976 10977 // Decompose 256-bit shifts into smaller 128-bit shifts. 10978 if (VT.is256BitVector()) { 10979 unsigned NumElems = VT.getVectorNumElements(); 10980 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10981 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10982 10983 // Extract the two vectors 10984 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 10985 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 10986 10987 // Recreate the shift amount vectors 10988 SDValue Amt1, Amt2; 10989 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10990 // Constant shift amount 10991 SmallVector<SDValue, 4> Amt1Csts; 10992 SmallVector<SDValue, 4> Amt2Csts; 10993 for (unsigned i = 0; i != NumElems/2; ++i) 10994 Amt1Csts.push_back(Amt->getOperand(i)); 10995 for (unsigned i = NumElems/2; i != NumElems; ++i) 10996 Amt2Csts.push_back(Amt->getOperand(i)); 10997 10998 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10999 &Amt1Csts[0], NumElems/2); 11000 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 11001 &Amt2Csts[0], NumElems/2); 11002 } else { 11003 // Variable shift amount 11004 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 11005 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 11006 } 11007 11008 // Issue new vector shifts for the smaller types 11009 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 11010 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 11011 11012 // Concatenate the result back 11013 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 11014 } 11015 11016 return SDValue(); 11017} 11018 11019static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 11020 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 11021 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 11022 // looks for this combo and may remove the "setcc" instruction if the "setcc" 11023 // has only one use. 11024 SDNode *N = Op.getNode(); 11025 SDValue LHS = N->getOperand(0); 11026 SDValue RHS = N->getOperand(1); 11027 unsigned BaseOp = 0; 11028 unsigned Cond = 0; 11029 DebugLoc DL = Op.getDebugLoc(); 11030 switch (Op.getOpcode()) { 11031 default: llvm_unreachable("Unknown ovf instruction!"); 11032 case ISD::SADDO: 11033 // A subtract of one will be selected as a INC. Note that INC doesn't 11034 // set CF, so we can't do this for UADDO. 11035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11036 if (C->isOne()) { 11037 BaseOp = X86ISD::INC; 11038 Cond = X86::COND_O; 11039 break; 11040 } 11041 BaseOp = X86ISD::ADD; 11042 Cond = X86::COND_O; 11043 break; 11044 case ISD::UADDO: 11045 BaseOp = X86ISD::ADD; 11046 Cond = X86::COND_B; 11047 break; 11048 case ISD::SSUBO: 11049 // A subtract of one will be selected as a DEC. Note that DEC doesn't 11050 // set CF, so we can't do this for USUBO. 11051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11052 if (C->isOne()) { 11053 BaseOp = X86ISD::DEC; 11054 Cond = X86::COND_O; 11055 break; 11056 } 11057 BaseOp = X86ISD::SUB; 11058 Cond = X86::COND_O; 11059 break; 11060 case ISD::USUBO: 11061 BaseOp = X86ISD::SUB; 11062 Cond = X86::COND_B; 11063 break; 11064 case ISD::SMULO: 11065 BaseOp = X86ISD::SMUL; 11066 Cond = X86::COND_O; 11067 break; 11068 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 11069 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 11070 MVT::i32); 11071 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 11072 11073 SDValue SetCC = 11074 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11075 DAG.getConstant(X86::COND_O, MVT::i32), 11076 SDValue(Sum.getNode(), 2)); 11077 11078 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11079 } 11080 } 11081 11082 // Also sets EFLAGS. 11083 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 11084 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 11085 11086 SDValue SetCC = 11087 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 11088 DAG.getConstant(Cond, MVT::i32), 11089 SDValue(Sum.getNode(), 1)); 11090 11091 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11092} 11093 11094SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 11095 SelectionDAG &DAG) const { 11096 DebugLoc dl = Op.getDebugLoc(); 11097 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 11098 EVT VT = Op.getValueType(); 11099 11100 if (!Subtarget->hasSSE2() || !VT.isVector()) 11101 return SDValue(); 11102 11103 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 11104 ExtraVT.getScalarType().getSizeInBits(); 11105 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 11106 11107 switch (VT.getSimpleVT().SimpleTy) { 11108 default: return SDValue(); 11109 case MVT::v8i32: 11110 case MVT::v16i16: 11111 if (!Subtarget->hasAVX()) 11112 return SDValue(); 11113 if (!Subtarget->hasAVX2()) { 11114 // needs to be split 11115 unsigned NumElems = VT.getVectorNumElements(); 11116 11117 // Extract the LHS vectors 11118 SDValue LHS = Op.getOperand(0); 11119 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 11120 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 11121 11122 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11123 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11124 11125 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 11126 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 11127 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 11128 ExtraNumElems/2); 11129 SDValue Extra = DAG.getValueType(ExtraVT); 11130 11131 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 11132 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 11133 11134 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2); 11135 } 11136 // fall through 11137 case MVT::v4i32: 11138 case MVT::v8i16: { 11139 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 11140 Op.getOperand(0), ShAmt, DAG); 11141 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 11142 } 11143 } 11144} 11145 11146 11147static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget, 11148 SelectionDAG &DAG) { 11149 DebugLoc dl = Op.getDebugLoc(); 11150 11151 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 11152 // There isn't any reason to disable it if the target processor supports it. 11153 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 11154 SDValue Chain = Op.getOperand(0); 11155 SDValue Zero = DAG.getConstant(0, MVT::i32); 11156 SDValue Ops[] = { 11157 DAG.getRegister(X86::ESP, MVT::i32), // Base 11158 DAG.getTargetConstant(1, MVT::i8), // Scale 11159 DAG.getRegister(0, MVT::i32), // Index 11160 DAG.getTargetConstant(0, MVT::i32), // Disp 11161 DAG.getRegister(0, MVT::i32), // Segment. 11162 Zero, 11163 Chain 11164 }; 11165 SDNode *Res = 11166 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 11167 array_lengthof(Ops)); 11168 return SDValue(Res, 0); 11169 } 11170 11171 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 11172 if (!isDev) 11173 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 11174 11175 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 11176 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 11177 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 11178 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 11179 11180 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 11181 if (!Op1 && !Op2 && !Op3 && Op4) 11182 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 11183 11184 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 11185 if (Op1 && !Op2 && !Op3 && !Op4) 11186 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 11187 11188 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 11189 // (MFENCE)>; 11190 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 11191} 11192 11193static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, 11194 SelectionDAG &DAG) { 11195 DebugLoc dl = Op.getDebugLoc(); 11196 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 11197 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 11198 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 11199 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 11200 11201 // The only fence that needs an instruction is a sequentially-consistent 11202 // cross-thread fence. 11203 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 11204 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 11205 // no-sse2). There isn't any reason to disable it if the target processor 11206 // supports it. 11207 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 11208 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 11209 11210 SDValue Chain = Op.getOperand(0); 11211 SDValue Zero = DAG.getConstant(0, MVT::i32); 11212 SDValue Ops[] = { 11213 DAG.getRegister(X86::ESP, MVT::i32), // Base 11214 DAG.getTargetConstant(1, MVT::i8), // Scale 11215 DAG.getRegister(0, MVT::i32), // Index 11216 DAG.getTargetConstant(0, MVT::i32), // Disp 11217 DAG.getRegister(0, MVT::i32), // Segment. 11218 Zero, 11219 Chain 11220 }; 11221 SDNode *Res = 11222 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 11223 array_lengthof(Ops)); 11224 return SDValue(Res, 0); 11225 } 11226 11227 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 11228 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 11229} 11230 11231 11232static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, 11233 SelectionDAG &DAG) { 11234 EVT T = Op.getValueType(); 11235 DebugLoc DL = Op.getDebugLoc(); 11236 unsigned Reg = 0; 11237 unsigned size = 0; 11238 switch(T.getSimpleVT().SimpleTy) { 11239 default: llvm_unreachable("Invalid value type!"); 11240 case MVT::i8: Reg = X86::AL; size = 1; break; 11241 case MVT::i16: Reg = X86::AX; size = 2; break; 11242 case MVT::i32: Reg = X86::EAX; size = 4; break; 11243 case MVT::i64: 11244 assert(Subtarget->is64Bit() && "Node not type legal!"); 11245 Reg = X86::RAX; size = 8; 11246 break; 11247 } 11248 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 11249 Op.getOperand(2), SDValue()); 11250 SDValue Ops[] = { cpIn.getValue(0), 11251 Op.getOperand(1), 11252 Op.getOperand(3), 11253 DAG.getTargetConstant(size, MVT::i8), 11254 cpIn.getValue(1) }; 11255 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11256 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 11257 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 11258 Ops, 5, T, MMO); 11259 SDValue cpOut = 11260 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 11261 return cpOut; 11262} 11263 11264static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, 11265 SelectionDAG &DAG) { 11266 assert(Subtarget->is64Bit() && "Result not type legalized?"); 11267 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11268 SDValue TheChain = Op.getOperand(0); 11269 DebugLoc dl = Op.getDebugLoc(); 11270 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11271 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 11272 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 11273 rax.getValue(2)); 11274 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 11275 DAG.getConstant(32, MVT::i8)); 11276 SDValue Ops[] = { 11277 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 11278 rdx.getValue(1) 11279 }; 11280 return DAG.getMergeValues(Ops, 2, dl); 11281} 11282 11283SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { 11284 EVT SrcVT = Op.getOperand(0).getValueType(); 11285 EVT DstVT = Op.getValueType(); 11286 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 11287 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 11288 assert((DstVT == MVT::i64 || 11289 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 11290 "Unexpected custom BITCAST"); 11291 // i64 <=> MMX conversions are Legal. 11292 if (SrcVT==MVT::i64 && DstVT.isVector()) 11293 return Op; 11294 if (DstVT==MVT::i64 && SrcVT.isVector()) 11295 return Op; 11296 // MMX <=> MMX conversions are Legal. 11297 if (SrcVT.isVector() && DstVT.isVector()) 11298 return Op; 11299 // All other conversions need to be expanded. 11300 return SDValue(); 11301} 11302 11303static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 11304 SDNode *Node = Op.getNode(); 11305 DebugLoc dl = Node->getDebugLoc(); 11306 EVT T = Node->getValueType(0); 11307 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 11308 DAG.getConstant(0, T), Node->getOperand(2)); 11309 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 11310 cast<AtomicSDNode>(Node)->getMemoryVT(), 11311 Node->getOperand(0), 11312 Node->getOperand(1), negOp, 11313 cast<AtomicSDNode>(Node)->getSrcValue(), 11314 cast<AtomicSDNode>(Node)->getAlignment(), 11315 cast<AtomicSDNode>(Node)->getOrdering(), 11316 cast<AtomicSDNode>(Node)->getSynchScope()); 11317} 11318 11319static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 11320 SDNode *Node = Op.getNode(); 11321 DebugLoc dl = Node->getDebugLoc(); 11322 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11323 11324 // Convert seq_cst store -> xchg 11325 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 11326 // FIXME: On 32-bit, store -> fist or movq would be more efficient 11327 // (The only way to get a 16-byte store is cmpxchg16b) 11328 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 11329 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 11330 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 11331 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 11332 cast<AtomicSDNode>(Node)->getMemoryVT(), 11333 Node->getOperand(0), 11334 Node->getOperand(1), Node->getOperand(2), 11335 cast<AtomicSDNode>(Node)->getMemOperand(), 11336 cast<AtomicSDNode>(Node)->getOrdering(), 11337 cast<AtomicSDNode>(Node)->getSynchScope()); 11338 return Swap.getValue(1); 11339 } 11340 // Other atomic stores have a simple pattern. 11341 return Op; 11342} 11343 11344static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 11345 EVT VT = Op.getNode()->getValueType(0); 11346 11347 // Let legalize expand this if it isn't a legal type yet. 11348 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 11349 return SDValue(); 11350 11351 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 11352 11353 unsigned Opc; 11354 bool ExtraOp = false; 11355 switch (Op.getOpcode()) { 11356 default: llvm_unreachable("Invalid code"); 11357 case ISD::ADDC: Opc = X86ISD::ADD; break; 11358 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 11359 case ISD::SUBC: Opc = X86ISD::SUB; break; 11360 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 11361 } 11362 11363 if (!ExtraOp) 11364 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 11365 Op.getOperand(1)); 11366 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 11367 Op.getOperand(1), Op.getOperand(2)); 11368} 11369 11370/// LowerOperation - Provide custom lowering hooks for some operations. 11371/// 11372SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 11373 switch (Op.getOpcode()) { 11374 default: llvm_unreachable("Should not custom lower this!"); 11375 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 11376 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG); 11377 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG); 11378 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG); 11379 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 11380 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 11381 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 11382 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 11383 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 11384 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 11385 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 11386 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG); 11387 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); 11388 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 11389 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 11390 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 11391 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 11392 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 11393 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 11394 case ISD::SHL_PARTS: 11395 case ISD::SRA_PARTS: 11396 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 11397 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 11398 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 11399 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 11400 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 11401 case ISD::FABS: return LowerFABS(Op, DAG); 11402 case ISD::FNEG: return LowerFNEG(Op, DAG); 11403 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 11404 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 11405 case ISD::SETCC: return LowerSETCC(Op, DAG); 11406 case ISD::SELECT: return LowerSELECT(Op, DAG); 11407 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 11408 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 11409 case ISD::VASTART: return LowerVASTART(Op, DAG); 11410 case ISD::VAARG: return LowerVAARG(Op, DAG); 11411 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG); 11412 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 11413 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 11414 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 11415 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 11416 case ISD::FRAME_TO_ARGS_OFFSET: 11417 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 11418 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 11419 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 11420 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 11421 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 11422 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 11423 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 11424 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 11425 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 11426 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG); 11427 case ISD::SRA: 11428 case ISD::SRL: 11429 case ISD::SHL: return LowerShift(Op, DAG); 11430 case ISD::SADDO: 11431 case ISD::UADDO: 11432 case ISD::SSUBO: 11433 case ISD::USUBO: 11434 case ISD::SMULO: 11435 case ISD::UMULO: return LowerXALUO(Op, DAG); 11436 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG); 11437 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 11438 case ISD::ADDC: 11439 case ISD::ADDE: 11440 case ISD::SUBC: 11441 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 11442 case ISD::ADD: return LowerADD(Op, DAG); 11443 case ISD::SUB: return LowerSUB(Op, DAG); 11444 } 11445} 11446 11447static void ReplaceATOMIC_LOAD(SDNode *Node, 11448 SmallVectorImpl<SDValue> &Results, 11449 SelectionDAG &DAG) { 11450 DebugLoc dl = Node->getDebugLoc(); 11451 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11452 11453 // Convert wide load -> cmpxchg8b/cmpxchg16b 11454 // FIXME: On 32-bit, load -> fild or movq would be more efficient 11455 // (The only way to get a 16-byte load is cmpxchg16b) 11456 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 11457 SDValue Zero = DAG.getConstant(0, VT); 11458 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 11459 Node->getOperand(0), 11460 Node->getOperand(1), Zero, Zero, 11461 cast<AtomicSDNode>(Node)->getMemOperand(), 11462 cast<AtomicSDNode>(Node)->getOrdering(), 11463 cast<AtomicSDNode>(Node)->getSynchScope()); 11464 Results.push_back(Swap.getValue(0)); 11465 Results.push_back(Swap.getValue(1)); 11466} 11467 11468static void 11469ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 11470 SelectionDAG &DAG, unsigned NewOp) { 11471 DebugLoc dl = Node->getDebugLoc(); 11472 assert (Node->getValueType(0) == MVT::i64 && 11473 "Only know how to expand i64 atomics"); 11474 11475 SDValue Chain = Node->getOperand(0); 11476 SDValue In1 = Node->getOperand(1); 11477 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11478 Node->getOperand(2), DAG.getIntPtrConstant(0)); 11479 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11480 Node->getOperand(2), DAG.getIntPtrConstant(1)); 11481 SDValue Ops[] = { Chain, In1, In2L, In2H }; 11482 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 11483 SDValue Result = 11484 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 11485 cast<MemSDNode>(Node)->getMemOperand()); 11486 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 11487 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 11488 Results.push_back(Result.getValue(2)); 11489} 11490 11491/// ReplaceNodeResults - Replace a node with an illegal result type 11492/// with a new node built out of custom code. 11493void X86TargetLowering::ReplaceNodeResults(SDNode *N, 11494 SmallVectorImpl<SDValue>&Results, 11495 SelectionDAG &DAG) const { 11496 DebugLoc dl = N->getDebugLoc(); 11497 switch (N->getOpcode()) { 11498 default: 11499 llvm_unreachable("Do not know how to custom type legalize this operation!"); 11500 case ISD::SIGN_EXTEND_INREG: 11501 case ISD::ADDC: 11502 case ISD::ADDE: 11503 case ISD::SUBC: 11504 case ISD::SUBE: 11505 // We don't want to expand or promote these. 11506 return; 11507 case ISD::FP_TO_SINT: 11508 case ISD::FP_TO_UINT: { 11509 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 11510 11511 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 11512 return; 11513 11514 std::pair<SDValue,SDValue> Vals = 11515 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 11516 SDValue FIST = Vals.first, StackSlot = Vals.second; 11517 if (FIST.getNode() != 0) { 11518 EVT VT = N->getValueType(0); 11519 // Return a load from the stack slot. 11520 if (StackSlot.getNode() != 0) 11521 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 11522 MachinePointerInfo(), 11523 false, false, false, 0)); 11524 else 11525 Results.push_back(FIST); 11526 } 11527 return; 11528 } 11529 case ISD::READCYCLECOUNTER: { 11530 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11531 SDValue TheChain = N->getOperand(0); 11532 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11533 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11534 rd.getValue(1)); 11535 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11536 eax.getValue(2)); 11537 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11538 SDValue Ops[] = { eax, edx }; 11539 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11540 Results.push_back(edx.getValue(1)); 11541 return; 11542 } 11543 case ISD::ATOMIC_CMP_SWAP: { 11544 EVT T = N->getValueType(0); 11545 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11546 bool Regs64bit = T == MVT::i128; 11547 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11548 SDValue cpInL, cpInH; 11549 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11550 DAG.getConstant(0, HalfT)); 11551 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11552 DAG.getConstant(1, HalfT)); 11553 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11554 Regs64bit ? X86::RAX : X86::EAX, 11555 cpInL, SDValue()); 11556 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11557 Regs64bit ? X86::RDX : X86::EDX, 11558 cpInH, cpInL.getValue(1)); 11559 SDValue swapInL, swapInH; 11560 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11561 DAG.getConstant(0, HalfT)); 11562 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11563 DAG.getConstant(1, HalfT)); 11564 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11565 Regs64bit ? X86::RBX : X86::EBX, 11566 swapInL, cpInH.getValue(1)); 11567 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11568 Regs64bit ? X86::RCX : X86::ECX, 11569 swapInH, swapInL.getValue(1)); 11570 SDValue Ops[] = { swapInH.getValue(0), 11571 N->getOperand(1), 11572 swapInH.getValue(1) }; 11573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11574 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11575 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11576 X86ISD::LCMPXCHG8_DAG; 11577 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11578 Ops, 3, T, MMO); 11579 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11580 Regs64bit ? X86::RAX : X86::EAX, 11581 HalfT, Result.getValue(1)); 11582 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11583 Regs64bit ? X86::RDX : X86::EDX, 11584 HalfT, cpOutL.getValue(2)); 11585 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11586 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11587 Results.push_back(cpOutH.getValue(1)); 11588 return; 11589 } 11590 case ISD::ATOMIC_LOAD_ADD: 11591 case ISD::ATOMIC_LOAD_AND: 11592 case ISD::ATOMIC_LOAD_NAND: 11593 case ISD::ATOMIC_LOAD_OR: 11594 case ISD::ATOMIC_LOAD_SUB: 11595 case ISD::ATOMIC_LOAD_XOR: 11596 case ISD::ATOMIC_SWAP: { 11597 unsigned Opc; 11598 switch (N->getOpcode()) { 11599 default: llvm_unreachable("Unexpected opcode"); 11600 case ISD::ATOMIC_LOAD_ADD: 11601 Opc = X86ISD::ATOMADD64_DAG; 11602 break; 11603 case ISD::ATOMIC_LOAD_AND: 11604 Opc = X86ISD::ATOMAND64_DAG; 11605 break; 11606 case ISD::ATOMIC_LOAD_NAND: 11607 Opc = X86ISD::ATOMNAND64_DAG; 11608 break; 11609 case ISD::ATOMIC_LOAD_OR: 11610 Opc = X86ISD::ATOMOR64_DAG; 11611 break; 11612 case ISD::ATOMIC_LOAD_SUB: 11613 Opc = X86ISD::ATOMSUB64_DAG; 11614 break; 11615 case ISD::ATOMIC_LOAD_XOR: 11616 Opc = X86ISD::ATOMXOR64_DAG; 11617 break; 11618 case ISD::ATOMIC_SWAP: 11619 Opc = X86ISD::ATOMSWAP64_DAG; 11620 break; 11621 } 11622 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc); 11623 return; 11624 } 11625 case ISD::ATOMIC_LOAD: 11626 ReplaceATOMIC_LOAD(N, Results, DAG); 11627 } 11628} 11629 11630const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11631 switch (Opcode) { 11632 default: return NULL; 11633 case X86ISD::BSF: return "X86ISD::BSF"; 11634 case X86ISD::BSR: return "X86ISD::BSR"; 11635 case X86ISD::SHLD: return "X86ISD::SHLD"; 11636 case X86ISD::SHRD: return "X86ISD::SHRD"; 11637 case X86ISD::FAND: return "X86ISD::FAND"; 11638 case X86ISD::FOR: return "X86ISD::FOR"; 11639 case X86ISD::FXOR: return "X86ISD::FXOR"; 11640 case X86ISD::FSRL: return "X86ISD::FSRL"; 11641 case X86ISD::FILD: return "X86ISD::FILD"; 11642 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11643 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11644 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11645 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11646 case X86ISD::FLD: return "X86ISD::FLD"; 11647 case X86ISD::FST: return "X86ISD::FST"; 11648 case X86ISD::CALL: return "X86ISD::CALL"; 11649 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11650 case X86ISD::BT: return "X86ISD::BT"; 11651 case X86ISD::CMP: return "X86ISD::CMP"; 11652 case X86ISD::COMI: return "X86ISD::COMI"; 11653 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11654 case X86ISD::SETCC: return "X86ISD::SETCC"; 11655 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11656 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11657 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11658 case X86ISD::CMOV: return "X86ISD::CMOV"; 11659 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11660 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11661 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11662 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11663 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11664 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11665 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11666 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11667 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11668 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11669 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11670 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11671 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11672 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11673 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11674 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11675 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11676 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11677 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11678 case X86ISD::HADD: return "X86ISD::HADD"; 11679 case X86ISD::HSUB: return "X86ISD::HSUB"; 11680 case X86ISD::FHADD: return "X86ISD::FHADD"; 11681 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11682 case X86ISD::FMAX: return "X86ISD::FMAX"; 11683 case X86ISD::FMIN: return "X86ISD::FMIN"; 11684 case X86ISD::FMAXC: return "X86ISD::FMAXC"; 11685 case X86ISD::FMINC: return "X86ISD::FMINC"; 11686 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11687 case X86ISD::FRCP: return "X86ISD::FRCP"; 11688 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11689 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR"; 11690 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11691 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11692 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11693 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11694 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 11695 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11696 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11697 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11698 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11699 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11700 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11701 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11702 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11703 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11704 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL"; 11705 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11706 case X86ISD::VFPEXT: return "X86ISD::VFPEXT"; 11707 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11708 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11709 case X86ISD::VSHL: return "X86ISD::VSHL"; 11710 case X86ISD::VSRL: return "X86ISD::VSRL"; 11711 case X86ISD::VSRA: return "X86ISD::VSRA"; 11712 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11713 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11714 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11715 case X86ISD::CMPP: return "X86ISD::CMPP"; 11716 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11717 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11718 case X86ISD::ADD: return "X86ISD::ADD"; 11719 case X86ISD::SUB: return "X86ISD::SUB"; 11720 case X86ISD::ADC: return "X86ISD::ADC"; 11721 case X86ISD::SBB: return "X86ISD::SBB"; 11722 case X86ISD::SMUL: return "X86ISD::SMUL"; 11723 case X86ISD::UMUL: return "X86ISD::UMUL"; 11724 case X86ISD::INC: return "X86ISD::INC"; 11725 case X86ISD::DEC: return "X86ISD::DEC"; 11726 case X86ISD::OR: return "X86ISD::OR"; 11727 case X86ISD::XOR: return "X86ISD::XOR"; 11728 case X86ISD::AND: return "X86ISD::AND"; 11729 case X86ISD::ANDN: return "X86ISD::ANDN"; 11730 case X86ISD::BLSI: return "X86ISD::BLSI"; 11731 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11732 case X86ISD::BLSR: return "X86ISD::BLSR"; 11733 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11734 case X86ISD::PTEST: return "X86ISD::PTEST"; 11735 case X86ISD::TESTP: return "X86ISD::TESTP"; 11736 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11737 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11738 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11739 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11740 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11741 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11742 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11743 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11744 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11745 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11746 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11747 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11748 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11749 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11750 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11751 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11752 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11753 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11754 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11755 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11756 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11757 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11758 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11759 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11760 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11761 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11762 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11763 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11764 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11765 case X86ISD::SAHF: return "X86ISD::SAHF"; 11766 case X86ISD::RDRAND: return "X86ISD::RDRAND"; 11767 case X86ISD::FMADD: return "X86ISD::FMADD"; 11768 case X86ISD::FMSUB: return "X86ISD::FMSUB"; 11769 case X86ISD::FNMADD: return "X86ISD::FNMADD"; 11770 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; 11771 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB"; 11772 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD"; 11773 } 11774} 11775 11776// isLegalAddressingMode - Return true if the addressing mode represented 11777// by AM is legal for this target, for a load/store of the specified type. 11778bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11779 Type *Ty) const { 11780 // X86 supports extremely general addressing modes. 11781 CodeModel::Model M = getTargetMachine().getCodeModel(); 11782 Reloc::Model R = getTargetMachine().getRelocationModel(); 11783 11784 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11785 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11786 return false; 11787 11788 if (AM.BaseGV) { 11789 unsigned GVFlags = 11790 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11791 11792 // If a reference to this global requires an extra load, we can't fold it. 11793 if (isGlobalStubReference(GVFlags)) 11794 return false; 11795 11796 // If BaseGV requires a register for the PIC base, we cannot also have a 11797 // BaseReg specified. 11798 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11799 return false; 11800 11801 // If lower 4G is not available, then we must use rip-relative addressing. 11802 if ((M != CodeModel::Small || R != Reloc::Static) && 11803 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11804 return false; 11805 } 11806 11807 switch (AM.Scale) { 11808 case 0: 11809 case 1: 11810 case 2: 11811 case 4: 11812 case 8: 11813 // These scales always work. 11814 break; 11815 case 3: 11816 case 5: 11817 case 9: 11818 // These scales are formed with basereg+scalereg. Only accept if there is 11819 // no basereg yet. 11820 if (AM.HasBaseReg) 11821 return false; 11822 break; 11823 default: // Other stuff never works. 11824 return false; 11825 } 11826 11827 return true; 11828} 11829 11830 11831bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11832 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11833 return false; 11834 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11835 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11836 if (NumBits1 <= NumBits2) 11837 return false; 11838 return true; 11839} 11840 11841bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { 11842 return Imm == (int32_t)Imm; 11843} 11844 11845bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { 11846 // Can also use sub to handle negated immediates. 11847 return Imm == (int32_t)Imm; 11848} 11849 11850bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11851 if (!VT1.isInteger() || !VT2.isInteger()) 11852 return false; 11853 unsigned NumBits1 = VT1.getSizeInBits(); 11854 unsigned NumBits2 = VT2.getSizeInBits(); 11855 if (NumBits1 <= NumBits2) 11856 return false; 11857 return true; 11858} 11859 11860bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11861 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11862 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11863} 11864 11865bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11866 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11867 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11868} 11869 11870bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11871 // i16 instructions are longer (0x66 prefix) and potentially slower. 11872 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11873} 11874 11875/// isShuffleMaskLegal - Targets can use this to indicate that they only 11876/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11877/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11878/// are assumed to be legal. 11879bool 11880X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11881 EVT VT) const { 11882 // Very little shuffling can be done for 64-bit vectors right now. 11883 if (VT.getSizeInBits() == 64) 11884 return false; 11885 11886 // FIXME: pshufb, blends, shifts. 11887 return (VT.getVectorNumElements() == 2 || 11888 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11889 isMOVLMask(M, VT) || 11890 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11891 isPSHUFDMask(M, VT) || 11892 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) || 11893 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) || 11894 isPALIGNRMask(M, VT, Subtarget) || 11895 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11896 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11897 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11898 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11899} 11900 11901bool 11902X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11903 EVT VT) const { 11904 unsigned NumElts = VT.getVectorNumElements(); 11905 // FIXME: This collection of masks seems suspect. 11906 if (NumElts == 2) 11907 return true; 11908 if (NumElts == 4 && VT.is128BitVector()) { 11909 return (isMOVLMask(Mask, VT) || 11910 isCommutedMOVLMask(Mask, VT, true) || 11911 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11912 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11913 } 11914 return false; 11915} 11916 11917//===----------------------------------------------------------------------===// 11918// X86 Scheduler Hooks 11919//===----------------------------------------------------------------------===// 11920 11921// private utility function 11922 11923// Get CMPXCHG opcode for the specified data type. 11924static unsigned getCmpXChgOpcode(EVT VT) { 11925 switch (VT.getSimpleVT().SimpleTy) { 11926 case MVT::i8: return X86::LCMPXCHG8; 11927 case MVT::i16: return X86::LCMPXCHG16; 11928 case MVT::i32: return X86::LCMPXCHG32; 11929 case MVT::i64: return X86::LCMPXCHG64; 11930 default: 11931 break; 11932 } 11933 llvm_unreachable("Invalid operand size!"); 11934} 11935 11936// Get LOAD opcode for the specified data type. 11937static unsigned getLoadOpcode(EVT VT) { 11938 switch (VT.getSimpleVT().SimpleTy) { 11939 case MVT::i8: return X86::MOV8rm; 11940 case MVT::i16: return X86::MOV16rm; 11941 case MVT::i32: return X86::MOV32rm; 11942 case MVT::i64: return X86::MOV64rm; 11943 default: 11944 break; 11945 } 11946 llvm_unreachable("Invalid operand size!"); 11947} 11948 11949// Get opcode of the non-atomic one from the specified atomic instruction. 11950static unsigned getNonAtomicOpcode(unsigned Opc) { 11951 switch (Opc) { 11952 case X86::ATOMAND8: return X86::AND8rr; 11953 case X86::ATOMAND16: return X86::AND16rr; 11954 case X86::ATOMAND32: return X86::AND32rr; 11955 case X86::ATOMAND64: return X86::AND64rr; 11956 case X86::ATOMOR8: return X86::OR8rr; 11957 case X86::ATOMOR16: return X86::OR16rr; 11958 case X86::ATOMOR32: return X86::OR32rr; 11959 case X86::ATOMOR64: return X86::OR64rr; 11960 case X86::ATOMXOR8: return X86::XOR8rr; 11961 case X86::ATOMXOR16: return X86::XOR16rr; 11962 case X86::ATOMXOR32: return X86::XOR32rr; 11963 case X86::ATOMXOR64: return X86::XOR64rr; 11964 } 11965 llvm_unreachable("Unhandled atomic-load-op opcode!"); 11966} 11967 11968// Get opcode of the non-atomic one from the specified atomic instruction with 11969// extra opcode. 11970static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc, 11971 unsigned &ExtraOpc) { 11972 switch (Opc) { 11973 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr; 11974 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr; 11975 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr; 11976 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr; 11977 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr; 11978 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr; 11979 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr; 11980 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr; 11981 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr; 11982 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr; 11983 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr; 11984 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr; 11985 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr; 11986 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr; 11987 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr; 11988 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr; 11989 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr; 11990 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr; 11991 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr; 11992 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr; 11993 } 11994 llvm_unreachable("Unhandled atomic-load-op opcode!"); 11995} 11996 11997// Get opcode of the non-atomic one from the specified atomic instruction for 11998// 64-bit data type on 32-bit target. 11999static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) { 12000 switch (Opc) { 12001 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr; 12002 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr; 12003 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr; 12004 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr; 12005 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr; 12006 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr; 12007 } 12008 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12009} 12010 12011// Get opcode of the non-atomic one from the specified atomic instruction for 12012// 64-bit data type on 32-bit target with extra opcode. 12013static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc, 12014 unsigned &HiOpc, 12015 unsigned &ExtraOpc) { 12016 switch (Opc) { 12017 case X86::ATOMNAND6432: 12018 ExtraOpc = X86::NOT32r; 12019 HiOpc = X86::AND32rr; 12020 return X86::AND32rr; 12021 } 12022 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12023} 12024 12025// Get pseudo CMOV opcode from the specified data type. 12026static unsigned getPseudoCMOVOpc(EVT VT) { 12027 switch (VT.getSimpleVT().SimpleTy) { 12028 case MVT::i8: return X86::CMOV_GR8; 12029 case MVT::i16: return X86::CMOV_GR16; 12030 case MVT::i32: return X86::CMOV_GR32; 12031 default: 12032 break; 12033 } 12034 llvm_unreachable("Unknown CMOV opcode!"); 12035} 12036 12037// EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions. 12038// They will be translated into a spin-loop or compare-exchange loop from 12039// 12040// ... 12041// dst = atomic-fetch-op MI.addr, MI.val 12042// ... 12043// 12044// to 12045// 12046// ... 12047// EAX = LOAD MI.addr 12048// loop: 12049// t1 = OP MI.val, EAX 12050// LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 12051// JNE loop 12052// sink: 12053// dst = EAX 12054// ... 12055MachineBasicBlock * 12056X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI, 12057 MachineBasicBlock *MBB) const { 12058 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12059 DebugLoc DL = MI->getDebugLoc(); 12060 12061 MachineFunction *MF = MBB->getParent(); 12062 MachineRegisterInfo &MRI = MF->getRegInfo(); 12063 12064 const BasicBlock *BB = MBB->getBasicBlock(); 12065 MachineFunction::iterator I = MBB; 12066 ++I; 12067 12068 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 && 12069 "Unexpected number of operands"); 12070 12071 assert(MI->hasOneMemOperand() && 12072 "Expected atomic-load-op to have one memoperand"); 12073 12074 // Memory Reference 12075 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 12076 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 12077 12078 unsigned DstReg, SrcReg; 12079 unsigned MemOpndSlot; 12080 12081 unsigned CurOp = 0; 12082 12083 DstReg = MI->getOperand(CurOp++).getReg(); 12084 MemOpndSlot = CurOp; 12085 CurOp += X86::AddrNumOperands; 12086 SrcReg = MI->getOperand(CurOp++).getReg(); 12087 12088 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 12089 EVT VT = *RC->vt_begin(); 12090 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT); 12091 12092 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT); 12093 unsigned LOADOpc = getLoadOpcode(VT); 12094 12095 // For the atomic load-arith operator, we generate 12096 // 12097 // thisMBB: 12098 // EAX = LOAD [MI.addr] 12099 // mainMBB: 12100 // t1 = OP MI.val, EAX 12101 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 12102 // JNE mainMBB 12103 // sinkMBB: 12104 12105 MachineBasicBlock *thisMBB = MBB; 12106 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 12107 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 12108 MF->insert(I, mainMBB); 12109 MF->insert(I, sinkMBB); 12110 12111 MachineInstrBuilder MIB; 12112 12113 // Transfer the remainder of BB and its successor edges to sinkMBB. 12114 sinkMBB->splice(sinkMBB->begin(), MBB, 12115 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 12116 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 12117 12118 // thisMBB: 12119 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg); 12120 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 12121 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12122 MIB.setMemRefs(MMOBegin, MMOEnd); 12123 12124 thisMBB->addSuccessor(mainMBB); 12125 12126 // mainMBB: 12127 MachineBasicBlock *origMainMBB = mainMBB; 12128 mainMBB->addLiveIn(AccPhyReg); 12129 12130 // Copy AccPhyReg as it is used more than once. 12131 unsigned AccReg = MRI.createVirtualRegister(RC); 12132 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg) 12133 .addReg(AccPhyReg); 12134 12135 unsigned t1 = MRI.createVirtualRegister(RC); 12136 unsigned Opc = MI->getOpcode(); 12137 switch (Opc) { 12138 default: 12139 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12140 case X86::ATOMAND8: 12141 case X86::ATOMAND16: 12142 case X86::ATOMAND32: 12143 case X86::ATOMAND64: 12144 case X86::ATOMOR8: 12145 case X86::ATOMOR16: 12146 case X86::ATOMOR32: 12147 case X86::ATOMOR64: 12148 case X86::ATOMXOR8: 12149 case X86::ATOMXOR16: 12150 case X86::ATOMXOR32: 12151 case X86::ATOMXOR64: { 12152 unsigned ARITHOpc = getNonAtomicOpcode(Opc); 12153 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg) 12154 .addReg(AccReg); 12155 break; 12156 } 12157 case X86::ATOMNAND8: 12158 case X86::ATOMNAND16: 12159 case X86::ATOMNAND32: 12160 case X86::ATOMNAND64: { 12161 unsigned t2 = MRI.createVirtualRegister(RC); 12162 unsigned NOTOpc; 12163 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc); 12164 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg) 12165 .addReg(AccReg); 12166 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2); 12167 break; 12168 } 12169 case X86::ATOMMAX8: 12170 case X86::ATOMMAX16: 12171 case X86::ATOMMAX32: 12172 case X86::ATOMMAX64: 12173 case X86::ATOMMIN8: 12174 case X86::ATOMMIN16: 12175 case X86::ATOMMIN32: 12176 case X86::ATOMMIN64: 12177 case X86::ATOMUMAX8: 12178 case X86::ATOMUMAX16: 12179 case X86::ATOMUMAX32: 12180 case X86::ATOMUMAX64: 12181 case X86::ATOMUMIN8: 12182 case X86::ATOMUMIN16: 12183 case X86::ATOMUMIN32: 12184 case X86::ATOMUMIN64: { 12185 unsigned CMPOpc; 12186 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc); 12187 12188 BuildMI(mainMBB, DL, TII->get(CMPOpc)) 12189 .addReg(SrcReg) 12190 .addReg(AccReg); 12191 12192 if (Subtarget->hasCMov()) { 12193 if (VT != MVT::i8) { 12194 // Native support 12195 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1) 12196 .addReg(SrcReg) 12197 .addReg(AccReg); 12198 } else { 12199 // Promote i8 to i32 to use CMOV32 12200 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32); 12201 unsigned SrcReg32 = MRI.createVirtualRegister(RC32); 12202 unsigned AccReg32 = MRI.createVirtualRegister(RC32); 12203 unsigned t2 = MRI.createVirtualRegister(RC32); 12204 12205 unsigned Undef = MRI.createVirtualRegister(RC32); 12206 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef); 12207 12208 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32) 12209 .addReg(Undef) 12210 .addReg(SrcReg) 12211 .addImm(X86::sub_8bit); 12212 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32) 12213 .addReg(Undef) 12214 .addReg(AccReg) 12215 .addImm(X86::sub_8bit); 12216 12217 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2) 12218 .addReg(SrcReg32) 12219 .addReg(AccReg32); 12220 12221 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1) 12222 .addReg(t2, 0, X86::sub_8bit); 12223 } 12224 } else { 12225 // Use pseudo select and lower them. 12226 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && 12227 "Invalid atomic-load-op transformation!"); 12228 unsigned SelOpc = getPseudoCMOVOpc(VT); 12229 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc); 12230 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!"); 12231 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1) 12232 .addReg(SrcReg).addReg(AccReg) 12233 .addImm(CC); 12234 mainMBB = EmitLoweredSelect(MIB, mainMBB); 12235 } 12236 break; 12237 } 12238 } 12239 12240 // Copy AccPhyReg back from virtual register. 12241 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg) 12242 .addReg(AccReg); 12243 12244 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 12245 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 12246 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12247 MIB.addReg(t1); 12248 MIB.setMemRefs(MMOBegin, MMOEnd); 12249 12250 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 12251 12252 mainMBB->addSuccessor(origMainMBB); 12253 mainMBB->addSuccessor(sinkMBB); 12254 12255 // sinkMBB: 12256 sinkMBB->addLiveIn(AccPhyReg); 12257 12258 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12259 TII->get(TargetOpcode::COPY), DstReg) 12260 .addReg(AccPhyReg); 12261 12262 MI->eraseFromParent(); 12263 return sinkMBB; 12264} 12265 12266// EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic 12267// instructions. They will be translated into a spin-loop or compare-exchange 12268// loop from 12269// 12270// ... 12271// dst = atomic-fetch-op MI.addr, MI.val 12272// ... 12273// 12274// to 12275// 12276// ... 12277// EAX = LOAD [MI.addr + 0] 12278// EDX = LOAD [MI.addr + 4] 12279// loop: 12280// EBX = OP MI.val.lo, EAX 12281// ECX = OP MI.val.hi, EDX 12282// LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 12283// JNE loop 12284// sink: 12285// dst = EDX:EAX 12286// ... 12287MachineBasicBlock * 12288X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, 12289 MachineBasicBlock *MBB) const { 12290 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12291 DebugLoc DL = MI->getDebugLoc(); 12292 12293 MachineFunction *MF = MBB->getParent(); 12294 MachineRegisterInfo &MRI = MF->getRegInfo(); 12295 12296 const BasicBlock *BB = MBB->getBasicBlock(); 12297 MachineFunction::iterator I = MBB; 12298 ++I; 12299 12300 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 && 12301 "Unexpected number of operands"); 12302 12303 assert(MI->hasOneMemOperand() && 12304 "Expected atomic-load-op32 to have one memoperand"); 12305 12306 // Memory Reference 12307 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 12308 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 12309 12310 unsigned DstLoReg, DstHiReg; 12311 unsigned SrcLoReg, SrcHiReg; 12312 unsigned MemOpndSlot; 12313 12314 unsigned CurOp = 0; 12315 12316 DstLoReg = MI->getOperand(CurOp++).getReg(); 12317 DstHiReg = MI->getOperand(CurOp++).getReg(); 12318 MemOpndSlot = CurOp; 12319 CurOp += X86::AddrNumOperands; 12320 SrcLoReg = MI->getOperand(CurOp++).getReg(); 12321 SrcHiReg = MI->getOperand(CurOp++).getReg(); 12322 12323 const TargetRegisterClass *RC = &X86::GR32RegClass; 12324 12325 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B; 12326 unsigned LOADOpc = X86::MOV32rm; 12327 12328 // For the atomic load-arith operator, we generate 12329 // 12330 // thisMBB: 12331 // EAX = LOAD [MI.addr + 0] 12332 // EDX = LOAD [MI.addr + 4] 12333 // mainMBB: 12334 // EBX = OP MI.vallo, EAX 12335 // ECX = OP MI.valhi, EDX 12336 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 12337 // JNE mainMBB 12338 // sinkMBB: 12339 12340 MachineBasicBlock *thisMBB = MBB; 12341 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 12342 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 12343 MF->insert(I, mainMBB); 12344 MF->insert(I, sinkMBB); 12345 12346 MachineInstrBuilder MIB; 12347 12348 // Transfer the remainder of BB and its successor edges to sinkMBB. 12349 sinkMBB->splice(sinkMBB->begin(), MBB, 12350 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 12351 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 12352 12353 // thisMBB: 12354 // Lo 12355 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX); 12356 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 12357 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12358 MIB.setMemRefs(MMOBegin, MMOEnd); 12359 // Hi 12360 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX); 12361 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 12362 if (i == X86::AddrDisp) 12363 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32) 12364 else 12365 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12366 } 12367 MIB.setMemRefs(MMOBegin, MMOEnd); 12368 12369 thisMBB->addSuccessor(mainMBB); 12370 12371 // mainMBB: 12372 MachineBasicBlock *origMainMBB = mainMBB; 12373 mainMBB->addLiveIn(X86::EAX); 12374 mainMBB->addLiveIn(X86::EDX); 12375 12376 // Copy EDX:EAX as they are used more than once. 12377 unsigned LoReg = MRI.createVirtualRegister(RC); 12378 unsigned HiReg = MRI.createVirtualRegister(RC); 12379 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX); 12380 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX); 12381 12382 unsigned t1L = MRI.createVirtualRegister(RC); 12383 unsigned t1H = MRI.createVirtualRegister(RC); 12384 12385 unsigned Opc = MI->getOpcode(); 12386 switch (Opc) { 12387 default: 12388 llvm_unreachable("Unhandled atomic-load-op6432 opcode!"); 12389 case X86::ATOMAND6432: 12390 case X86::ATOMOR6432: 12391 case X86::ATOMXOR6432: 12392 case X86::ATOMADD6432: 12393 case X86::ATOMSUB6432: { 12394 unsigned HiOpc; 12395 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 12396 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg).addReg(LoReg); 12397 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg).addReg(HiReg); 12398 break; 12399 } 12400 case X86::ATOMNAND6432: { 12401 unsigned HiOpc, NOTOpc; 12402 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc); 12403 unsigned t2L = MRI.createVirtualRegister(RC); 12404 unsigned t2H = MRI.createVirtualRegister(RC); 12405 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg); 12406 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg); 12407 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L); 12408 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H); 12409 break; 12410 } 12411 case X86::ATOMSWAP6432: { 12412 unsigned HiOpc; 12413 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 12414 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg); 12415 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg); 12416 break; 12417 } 12418 } 12419 12420 // Copy EDX:EAX back from HiReg:LoReg 12421 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg); 12422 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg); 12423 // Copy ECX:EBX from t1H:t1L 12424 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L); 12425 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H); 12426 12427 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 12428 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 12429 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12430 MIB.setMemRefs(MMOBegin, MMOEnd); 12431 12432 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 12433 12434 mainMBB->addSuccessor(origMainMBB); 12435 mainMBB->addSuccessor(sinkMBB); 12436 12437 // sinkMBB: 12438 sinkMBB->addLiveIn(X86::EAX); 12439 sinkMBB->addLiveIn(X86::EDX); 12440 12441 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12442 TII->get(TargetOpcode::COPY), DstLoReg) 12443 .addReg(X86::EAX); 12444 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12445 TII->get(TargetOpcode::COPY), DstHiReg) 12446 .addReg(X86::EDX); 12447 12448 MI->eraseFromParent(); 12449 return sinkMBB; 12450} 12451 12452// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 12453// or XMM0_V32I8 in AVX all of this code can be replaced with that 12454// in the .td file. 12455MachineBasicBlock * 12456X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 12457 unsigned numArgs, bool memArg) const { 12458 assert(Subtarget->hasSSE42() && 12459 "Target must have SSE4.2 or AVX features enabled"); 12460 12461 DebugLoc dl = MI->getDebugLoc(); 12462 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12463 unsigned Opc; 12464 if (!Subtarget->hasAVX()) { 12465 if (memArg) 12466 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 12467 else 12468 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 12469 } else { 12470 if (memArg) 12471 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 12472 else 12473 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 12474 } 12475 12476 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 12477 for (unsigned i = 0; i < numArgs; ++i) { 12478 MachineOperand &Op = MI->getOperand(i+1); 12479 if (!(Op.isReg() && Op.isImplicit())) 12480 MIB.addOperand(Op); 12481 } 12482 BuildMI(*BB, MI, dl, 12483 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 12484 .addReg(X86::XMM0); 12485 12486 MI->eraseFromParent(); 12487 return BB; 12488} 12489 12490MachineBasicBlock * 12491X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 12492 DebugLoc dl = MI->getDebugLoc(); 12493 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12494 12495 // Address into RAX/EAX, other two args into ECX, EDX. 12496 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 12497 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 12498 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 12499 for (int i = 0; i < X86::AddrNumOperands; ++i) 12500 MIB.addOperand(MI->getOperand(i)); 12501 12502 unsigned ValOps = X86::AddrNumOperands; 12503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 12504 .addReg(MI->getOperand(ValOps).getReg()); 12505 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 12506 .addReg(MI->getOperand(ValOps+1).getReg()); 12507 12508 // The instruction doesn't actually take any operands though. 12509 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 12510 12511 MI->eraseFromParent(); // The pseudo is gone now. 12512 return BB; 12513} 12514 12515MachineBasicBlock * 12516X86TargetLowering::EmitVAARG64WithCustomInserter( 12517 MachineInstr *MI, 12518 MachineBasicBlock *MBB) const { 12519 // Emit va_arg instruction on X86-64. 12520 12521 // Operands to this pseudo-instruction: 12522 // 0 ) Output : destination address (reg) 12523 // 1-5) Input : va_list address (addr, i64mem) 12524 // 6 ) ArgSize : Size (in bytes) of vararg type 12525 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 12526 // 8 ) Align : Alignment of type 12527 // 9 ) EFLAGS (implicit-def) 12528 12529 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 12530 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 12531 12532 unsigned DestReg = MI->getOperand(0).getReg(); 12533 MachineOperand &Base = MI->getOperand(1); 12534 MachineOperand &Scale = MI->getOperand(2); 12535 MachineOperand &Index = MI->getOperand(3); 12536 MachineOperand &Disp = MI->getOperand(4); 12537 MachineOperand &Segment = MI->getOperand(5); 12538 unsigned ArgSize = MI->getOperand(6).getImm(); 12539 unsigned ArgMode = MI->getOperand(7).getImm(); 12540 unsigned Align = MI->getOperand(8).getImm(); 12541 12542 // Memory Reference 12543 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 12544 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 12545 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 12546 12547 // Machine Information 12548 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12549 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 12550 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 12551 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 12552 DebugLoc DL = MI->getDebugLoc(); 12553 12554 // struct va_list { 12555 // i32 gp_offset 12556 // i32 fp_offset 12557 // i64 overflow_area (address) 12558 // i64 reg_save_area (address) 12559 // } 12560 // sizeof(va_list) = 24 12561 // alignment(va_list) = 8 12562 12563 unsigned TotalNumIntRegs = 6; 12564 unsigned TotalNumXMMRegs = 8; 12565 bool UseGPOffset = (ArgMode == 1); 12566 bool UseFPOffset = (ArgMode == 2); 12567 unsigned MaxOffset = TotalNumIntRegs * 8 + 12568 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 12569 12570 /* Align ArgSize to a multiple of 8 */ 12571 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 12572 bool NeedsAlign = (Align > 8); 12573 12574 MachineBasicBlock *thisMBB = MBB; 12575 MachineBasicBlock *overflowMBB; 12576 MachineBasicBlock *offsetMBB; 12577 MachineBasicBlock *endMBB; 12578 12579 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 12580 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 12581 unsigned OffsetReg = 0; 12582 12583 if (!UseGPOffset && !UseFPOffset) { 12584 // If we only pull from the overflow region, we don't create a branch. 12585 // We don't need to alter control flow. 12586 OffsetDestReg = 0; // unused 12587 OverflowDestReg = DestReg; 12588 12589 offsetMBB = NULL; 12590 overflowMBB = thisMBB; 12591 endMBB = thisMBB; 12592 } else { 12593 // First emit code to check if gp_offset (or fp_offset) is below the bound. 12594 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 12595 // If not, pull from overflow_area. (branch to overflowMBB) 12596 // 12597 // thisMBB 12598 // | . 12599 // | . 12600 // offsetMBB overflowMBB 12601 // | . 12602 // | . 12603 // endMBB 12604 12605 // Registers for the PHI in endMBB 12606 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 12607 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 12608 12609 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12610 MachineFunction *MF = MBB->getParent(); 12611 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12612 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12613 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12614 12615 MachineFunction::iterator MBBIter = MBB; 12616 ++MBBIter; 12617 12618 // Insert the new basic blocks 12619 MF->insert(MBBIter, offsetMBB); 12620 MF->insert(MBBIter, overflowMBB); 12621 MF->insert(MBBIter, endMBB); 12622 12623 // Transfer the remainder of MBB and its successor edges to endMBB. 12624 endMBB->splice(endMBB->begin(), thisMBB, 12625 llvm::next(MachineBasicBlock::iterator(MI)), 12626 thisMBB->end()); 12627 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 12628 12629 // Make offsetMBB and overflowMBB successors of thisMBB 12630 thisMBB->addSuccessor(offsetMBB); 12631 thisMBB->addSuccessor(overflowMBB); 12632 12633 // endMBB is a successor of both offsetMBB and overflowMBB 12634 offsetMBB->addSuccessor(endMBB); 12635 overflowMBB->addSuccessor(endMBB); 12636 12637 // Load the offset value into a register 12638 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12639 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 12640 .addOperand(Base) 12641 .addOperand(Scale) 12642 .addOperand(Index) 12643 .addDisp(Disp, UseFPOffset ? 4 : 0) 12644 .addOperand(Segment) 12645 .setMemRefs(MMOBegin, MMOEnd); 12646 12647 // Check if there is enough room left to pull this argument. 12648 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 12649 .addReg(OffsetReg) 12650 .addImm(MaxOffset + 8 - ArgSizeA8); 12651 12652 // Branch to "overflowMBB" if offset >= max 12653 // Fall through to "offsetMBB" otherwise 12654 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 12655 .addMBB(overflowMBB); 12656 } 12657 12658 // In offsetMBB, emit code to use the reg_save_area. 12659 if (offsetMBB) { 12660 assert(OffsetReg != 0); 12661 12662 // Read the reg_save_area address. 12663 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 12664 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 12665 .addOperand(Base) 12666 .addOperand(Scale) 12667 .addOperand(Index) 12668 .addDisp(Disp, 16) 12669 .addOperand(Segment) 12670 .setMemRefs(MMOBegin, MMOEnd); 12671 12672 // Zero-extend the offset 12673 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 12674 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 12675 .addImm(0) 12676 .addReg(OffsetReg) 12677 .addImm(X86::sub_32bit); 12678 12679 // Add the offset to the reg_save_area to get the final address. 12680 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 12681 .addReg(OffsetReg64) 12682 .addReg(RegSaveReg); 12683 12684 // Compute the offset for the next argument 12685 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12686 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 12687 .addReg(OffsetReg) 12688 .addImm(UseFPOffset ? 16 : 8); 12689 12690 // Store it back into the va_list. 12691 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 12692 .addOperand(Base) 12693 .addOperand(Scale) 12694 .addOperand(Index) 12695 .addDisp(Disp, UseFPOffset ? 4 : 0) 12696 .addOperand(Segment) 12697 .addReg(NextOffsetReg) 12698 .setMemRefs(MMOBegin, MMOEnd); 12699 12700 // Jump to endMBB 12701 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12702 .addMBB(endMBB); 12703 } 12704 12705 // 12706 // Emit code to use overflow area 12707 // 12708 12709 // Load the overflow_area address into a register. 12710 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12711 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12712 .addOperand(Base) 12713 .addOperand(Scale) 12714 .addOperand(Index) 12715 .addDisp(Disp, 8) 12716 .addOperand(Segment) 12717 .setMemRefs(MMOBegin, MMOEnd); 12718 12719 // If we need to align it, do so. Otherwise, just copy the address 12720 // to OverflowDestReg. 12721 if (NeedsAlign) { 12722 // Align the overflow address 12723 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12724 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12725 12726 // aligned_addr = (addr + (align-1)) & ~(align-1) 12727 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12728 .addReg(OverflowAddrReg) 12729 .addImm(Align-1); 12730 12731 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12732 .addReg(TmpReg) 12733 .addImm(~(uint64_t)(Align-1)); 12734 } else { 12735 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12736 .addReg(OverflowAddrReg); 12737 } 12738 12739 // Compute the next overflow address after this argument. 12740 // (the overflow address should be kept 8-byte aligned) 12741 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12742 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12743 .addReg(OverflowDestReg) 12744 .addImm(ArgSizeA8); 12745 12746 // Store the new overflow address. 12747 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12748 .addOperand(Base) 12749 .addOperand(Scale) 12750 .addOperand(Index) 12751 .addDisp(Disp, 8) 12752 .addOperand(Segment) 12753 .addReg(NextAddrReg) 12754 .setMemRefs(MMOBegin, MMOEnd); 12755 12756 // If we branched, emit the PHI to the front of endMBB. 12757 if (offsetMBB) { 12758 BuildMI(*endMBB, endMBB->begin(), DL, 12759 TII->get(X86::PHI), DestReg) 12760 .addReg(OffsetDestReg).addMBB(offsetMBB) 12761 .addReg(OverflowDestReg).addMBB(overflowMBB); 12762 } 12763 12764 // Erase the pseudo instruction 12765 MI->eraseFromParent(); 12766 12767 return endMBB; 12768} 12769 12770MachineBasicBlock * 12771X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12772 MachineInstr *MI, 12773 MachineBasicBlock *MBB) const { 12774 // Emit code to save XMM registers to the stack. The ABI says that the 12775 // number of registers to save is given in %al, so it's theoretically 12776 // possible to do an indirect jump trick to avoid saving all of them, 12777 // however this code takes a simpler approach and just executes all 12778 // of the stores if %al is non-zero. It's less code, and it's probably 12779 // easier on the hardware branch predictor, and stores aren't all that 12780 // expensive anyway. 12781 12782 // Create the new basic blocks. One block contains all the XMM stores, 12783 // and one block is the final destination regardless of whether any 12784 // stores were performed. 12785 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12786 MachineFunction *F = MBB->getParent(); 12787 MachineFunction::iterator MBBIter = MBB; 12788 ++MBBIter; 12789 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12790 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12791 F->insert(MBBIter, XMMSaveMBB); 12792 F->insert(MBBIter, EndMBB); 12793 12794 // Transfer the remainder of MBB and its successor edges to EndMBB. 12795 EndMBB->splice(EndMBB->begin(), MBB, 12796 llvm::next(MachineBasicBlock::iterator(MI)), 12797 MBB->end()); 12798 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12799 12800 // The original block will now fall through to the XMM save block. 12801 MBB->addSuccessor(XMMSaveMBB); 12802 // The XMMSaveMBB will fall through to the end block. 12803 XMMSaveMBB->addSuccessor(EndMBB); 12804 12805 // Now add the instructions. 12806 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12807 DebugLoc DL = MI->getDebugLoc(); 12808 12809 unsigned CountReg = MI->getOperand(0).getReg(); 12810 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12811 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12812 12813 if (!Subtarget->isTargetWin64()) { 12814 // If %al is 0, branch around the XMM save block. 12815 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12816 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12817 MBB->addSuccessor(EndMBB); 12818 } 12819 12820 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12821 // In the XMM save block, save all the XMM argument registers. 12822 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12823 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12824 MachineMemOperand *MMO = 12825 F->getMachineMemOperand( 12826 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12827 MachineMemOperand::MOStore, 12828 /*Size=*/16, /*Align=*/16); 12829 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12830 .addFrameIndex(RegSaveFrameIndex) 12831 .addImm(/*Scale=*/1) 12832 .addReg(/*IndexReg=*/0) 12833 .addImm(/*Disp=*/Offset) 12834 .addReg(/*Segment=*/0) 12835 .addReg(MI->getOperand(i).getReg()) 12836 .addMemOperand(MMO); 12837 } 12838 12839 MI->eraseFromParent(); // The pseudo instruction is gone now. 12840 12841 return EndMBB; 12842} 12843 12844// The EFLAGS operand of SelectItr might be missing a kill marker 12845// because there were multiple uses of EFLAGS, and ISel didn't know 12846// which to mark. Figure out whether SelectItr should have had a 12847// kill marker, and set it if it should. Returns the correct kill 12848// marker value. 12849static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12850 MachineBasicBlock* BB, 12851 const TargetRegisterInfo* TRI) { 12852 // Scan forward through BB for a use/def of EFLAGS. 12853 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12854 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12855 const MachineInstr& mi = *miI; 12856 if (mi.readsRegister(X86::EFLAGS)) 12857 return false; 12858 if (mi.definesRegister(X86::EFLAGS)) 12859 break; // Should have kill-flag - update below. 12860 } 12861 12862 // If we hit the end of the block, check whether EFLAGS is live into a 12863 // successor. 12864 if (miI == BB->end()) { 12865 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12866 sEnd = BB->succ_end(); 12867 sItr != sEnd; ++sItr) { 12868 MachineBasicBlock* succ = *sItr; 12869 if (succ->isLiveIn(X86::EFLAGS)) 12870 return false; 12871 } 12872 } 12873 12874 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12875 // out. SelectMI should have a kill flag on EFLAGS. 12876 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12877 return true; 12878} 12879 12880MachineBasicBlock * 12881X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12882 MachineBasicBlock *BB) const { 12883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12884 DebugLoc DL = MI->getDebugLoc(); 12885 12886 // To "insert" a SELECT_CC instruction, we actually have to insert the 12887 // diamond control-flow pattern. The incoming instruction knows the 12888 // destination vreg to set, the condition code register to branch on, the 12889 // true/false values to select between, and a branch opcode to use. 12890 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12891 MachineFunction::iterator It = BB; 12892 ++It; 12893 12894 // thisMBB: 12895 // ... 12896 // TrueVal = ... 12897 // cmpTY ccX, r1, r2 12898 // bCC copy1MBB 12899 // fallthrough --> copy0MBB 12900 MachineBasicBlock *thisMBB = BB; 12901 MachineFunction *F = BB->getParent(); 12902 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12903 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12904 F->insert(It, copy0MBB); 12905 F->insert(It, sinkMBB); 12906 12907 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12908 // live into the sink and copy blocks. 12909 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12910 if (!MI->killsRegister(X86::EFLAGS) && 12911 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12912 copy0MBB->addLiveIn(X86::EFLAGS); 12913 sinkMBB->addLiveIn(X86::EFLAGS); 12914 } 12915 12916 // Transfer the remainder of BB and its successor edges to sinkMBB. 12917 sinkMBB->splice(sinkMBB->begin(), BB, 12918 llvm::next(MachineBasicBlock::iterator(MI)), 12919 BB->end()); 12920 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12921 12922 // Add the true and fallthrough blocks as its successors. 12923 BB->addSuccessor(copy0MBB); 12924 BB->addSuccessor(sinkMBB); 12925 12926 // Create the conditional branch instruction. 12927 unsigned Opc = 12928 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12929 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12930 12931 // copy0MBB: 12932 // %FalseValue = ... 12933 // # fallthrough to sinkMBB 12934 copy0MBB->addSuccessor(sinkMBB); 12935 12936 // sinkMBB: 12937 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12938 // ... 12939 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12940 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12941 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12942 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12943 12944 MI->eraseFromParent(); // The pseudo instruction is gone now. 12945 return sinkMBB; 12946} 12947 12948MachineBasicBlock * 12949X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12950 bool Is64Bit) const { 12951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12952 DebugLoc DL = MI->getDebugLoc(); 12953 MachineFunction *MF = BB->getParent(); 12954 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12955 12956 assert(getTargetMachine().Options.EnableSegmentedStacks); 12957 12958 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12959 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12960 12961 // BB: 12962 // ... [Till the alloca] 12963 // If stacklet is not large enough, jump to mallocMBB 12964 // 12965 // bumpMBB: 12966 // Allocate by subtracting from RSP 12967 // Jump to continueMBB 12968 // 12969 // mallocMBB: 12970 // Allocate by call to runtime 12971 // 12972 // continueMBB: 12973 // ... 12974 // [rest of original BB] 12975 // 12976 12977 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12978 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12979 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12980 12981 MachineRegisterInfo &MRI = MF->getRegInfo(); 12982 const TargetRegisterClass *AddrRegClass = 12983 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12984 12985 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12986 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12987 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12988 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12989 sizeVReg = MI->getOperand(1).getReg(), 12990 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12991 12992 MachineFunction::iterator MBBIter = BB; 12993 ++MBBIter; 12994 12995 MF->insert(MBBIter, bumpMBB); 12996 MF->insert(MBBIter, mallocMBB); 12997 MF->insert(MBBIter, continueMBB); 12998 12999 continueMBB->splice(continueMBB->begin(), BB, llvm::next 13000 (MachineBasicBlock::iterator(MI)), BB->end()); 13001 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 13002 13003 // Add code to the main basic block to check if the stack limit has been hit, 13004 // and if so, jump to mallocMBB otherwise to bumpMBB. 13005 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 13006 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 13007 .addReg(tmpSPVReg).addReg(sizeVReg); 13008 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 13009 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 13010 .addReg(SPLimitVReg); 13011 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 13012 13013 // bumpMBB simply decreases the stack pointer, since we know the current 13014 // stacklet has enough space. 13015 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 13016 .addReg(SPLimitVReg); 13017 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 13018 .addReg(SPLimitVReg); 13019 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 13020 13021 // Calls into a routine in libgcc to allocate more space from the heap. 13022 const uint32_t *RegMask = 13023 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 13024 if (Is64Bit) { 13025 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 13026 .addReg(sizeVReg); 13027 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 13028 .addExternalSymbol("__morestack_allocate_stack_space") 13029 .addRegMask(RegMask) 13030 .addReg(X86::RDI, RegState::Implicit) 13031 .addReg(X86::RAX, RegState::ImplicitDefine); 13032 } else { 13033 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 13034 .addImm(12); 13035 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 13036 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 13037 .addExternalSymbol("__morestack_allocate_stack_space") 13038 .addRegMask(RegMask) 13039 .addReg(X86::EAX, RegState::ImplicitDefine); 13040 } 13041 13042 if (!Is64Bit) 13043 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 13044 .addImm(16); 13045 13046 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 13047 .addReg(Is64Bit ? X86::RAX : X86::EAX); 13048 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 13049 13050 // Set up the CFG correctly. 13051 BB->addSuccessor(bumpMBB); 13052 BB->addSuccessor(mallocMBB); 13053 mallocMBB->addSuccessor(continueMBB); 13054 bumpMBB->addSuccessor(continueMBB); 13055 13056 // Take care of the PHI nodes. 13057 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 13058 MI->getOperand(0).getReg()) 13059 .addReg(mallocPtrVReg).addMBB(mallocMBB) 13060 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 13061 13062 // Delete the original pseudo instruction. 13063 MI->eraseFromParent(); 13064 13065 // And we're done. 13066 return continueMBB; 13067} 13068 13069MachineBasicBlock * 13070X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 13071 MachineBasicBlock *BB) const { 13072 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13073 DebugLoc DL = MI->getDebugLoc(); 13074 13075 assert(!Subtarget->isTargetEnvMacho()); 13076 13077 // The lowering is pretty easy: we're just emitting the call to _alloca. The 13078 // non-trivial part is impdef of ESP. 13079 13080 if (Subtarget->isTargetWin64()) { 13081 if (Subtarget->isTargetCygMing()) { 13082 // ___chkstk(Mingw64): 13083 // Clobbers R10, R11, RAX and EFLAGS. 13084 // Updates RSP. 13085 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 13086 .addExternalSymbol("___chkstk") 13087 .addReg(X86::RAX, RegState::Implicit) 13088 .addReg(X86::RSP, RegState::Implicit) 13089 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 13090 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 13091 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13092 } else { 13093 // __chkstk(MSVCRT): does not update stack pointer. 13094 // Clobbers R10, R11 and EFLAGS. 13095 // FIXME: RAX(allocated size) might be reused and not killed. 13096 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 13097 .addExternalSymbol("__chkstk") 13098 .addReg(X86::RAX, RegState::Implicit) 13099 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13100 // RAX has the offset to subtracted from RSP. 13101 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 13102 .addReg(X86::RSP) 13103 .addReg(X86::RAX); 13104 } 13105 } else { 13106 const char *StackProbeSymbol = 13107 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 13108 13109 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 13110 .addExternalSymbol(StackProbeSymbol) 13111 .addReg(X86::EAX, RegState::Implicit) 13112 .addReg(X86::ESP, RegState::Implicit) 13113 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 13114 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 13115 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13116 } 13117 13118 MI->eraseFromParent(); // The pseudo instruction is gone now. 13119 return BB; 13120} 13121 13122MachineBasicBlock * 13123X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 13124 MachineBasicBlock *BB) const { 13125 // This is pretty easy. We're taking the value that we received from 13126 // our load from the relocation, sticking it in either RDI (x86-64) 13127 // or EAX and doing an indirect call. The return value will then 13128 // be in the normal return register. 13129 const X86InstrInfo *TII 13130 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 13131 DebugLoc DL = MI->getDebugLoc(); 13132 MachineFunction *F = BB->getParent(); 13133 13134 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 13135 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 13136 13137 // Get a register mask for the lowered call. 13138 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 13139 // proper register mask. 13140 const uint32_t *RegMask = 13141 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 13142 if (Subtarget->is64Bit()) { 13143 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 13144 TII->get(X86::MOV64rm), X86::RDI) 13145 .addReg(X86::RIP) 13146 .addImm(0).addReg(0) 13147 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 13148 MI->getOperand(3).getTargetFlags()) 13149 .addReg(0); 13150 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 13151 addDirectMem(MIB, X86::RDI); 13152 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 13153 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 13154 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 13155 TII->get(X86::MOV32rm), X86::EAX) 13156 .addReg(0) 13157 .addImm(0).addReg(0) 13158 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 13159 MI->getOperand(3).getTargetFlags()) 13160 .addReg(0); 13161 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 13162 addDirectMem(MIB, X86::EAX); 13163 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 13164 } else { 13165 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 13166 TII->get(X86::MOV32rm), X86::EAX) 13167 .addReg(TII->getGlobalBaseReg(F)) 13168 .addImm(0).addReg(0) 13169 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 13170 MI->getOperand(3).getTargetFlags()) 13171 .addReg(0); 13172 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 13173 addDirectMem(MIB, X86::EAX); 13174 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 13175 } 13176 13177 MI->eraseFromParent(); // The pseudo instruction is gone now. 13178 return BB; 13179} 13180 13181MachineBasicBlock * 13182X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 13183 MachineBasicBlock *BB) const { 13184 switch (MI->getOpcode()) { 13185 default: llvm_unreachable("Unexpected instr type to insert"); 13186 case X86::TAILJMPd64: 13187 case X86::TAILJMPr64: 13188 case X86::TAILJMPm64: 13189 llvm_unreachable("TAILJMP64 would not be touched here."); 13190 case X86::TCRETURNdi64: 13191 case X86::TCRETURNri64: 13192 case X86::TCRETURNmi64: 13193 return BB; 13194 case X86::WIN_ALLOCA: 13195 return EmitLoweredWinAlloca(MI, BB); 13196 case X86::SEG_ALLOCA_32: 13197 return EmitLoweredSegAlloca(MI, BB, false); 13198 case X86::SEG_ALLOCA_64: 13199 return EmitLoweredSegAlloca(MI, BB, true); 13200 case X86::TLSCall_32: 13201 case X86::TLSCall_64: 13202 return EmitLoweredTLSCall(MI, BB); 13203 case X86::CMOV_GR8: 13204 case X86::CMOV_FR32: 13205 case X86::CMOV_FR64: 13206 case X86::CMOV_V4F32: 13207 case X86::CMOV_V2F64: 13208 case X86::CMOV_V2I64: 13209 case X86::CMOV_V8F32: 13210 case X86::CMOV_V4F64: 13211 case X86::CMOV_V4I64: 13212 case X86::CMOV_GR16: 13213 case X86::CMOV_GR32: 13214 case X86::CMOV_RFP32: 13215 case X86::CMOV_RFP64: 13216 case X86::CMOV_RFP80: 13217 return EmitLoweredSelect(MI, BB); 13218 13219 case X86::FP32_TO_INT16_IN_MEM: 13220 case X86::FP32_TO_INT32_IN_MEM: 13221 case X86::FP32_TO_INT64_IN_MEM: 13222 case X86::FP64_TO_INT16_IN_MEM: 13223 case X86::FP64_TO_INT32_IN_MEM: 13224 case X86::FP64_TO_INT64_IN_MEM: 13225 case X86::FP80_TO_INT16_IN_MEM: 13226 case X86::FP80_TO_INT32_IN_MEM: 13227 case X86::FP80_TO_INT64_IN_MEM: { 13228 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13229 DebugLoc DL = MI->getDebugLoc(); 13230 13231 // Change the floating point control register to use "round towards zero" 13232 // mode when truncating to an integer value. 13233 MachineFunction *F = BB->getParent(); 13234 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 13235 addFrameReference(BuildMI(*BB, MI, DL, 13236 TII->get(X86::FNSTCW16m)), CWFrameIdx); 13237 13238 // Load the old value of the high byte of the control word... 13239 unsigned OldCW = 13240 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 13241 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 13242 CWFrameIdx); 13243 13244 // Set the high part to be round to zero... 13245 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 13246 .addImm(0xC7F); 13247 13248 // Reload the modified control word now... 13249 addFrameReference(BuildMI(*BB, MI, DL, 13250 TII->get(X86::FLDCW16m)), CWFrameIdx); 13251 13252 // Restore the memory image of control word to original value 13253 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 13254 .addReg(OldCW); 13255 13256 // Get the X86 opcode to use. 13257 unsigned Opc; 13258 switch (MI->getOpcode()) { 13259 default: llvm_unreachable("illegal opcode!"); 13260 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 13261 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 13262 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 13263 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 13264 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 13265 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 13266 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 13267 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 13268 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 13269 } 13270 13271 X86AddressMode AM; 13272 MachineOperand &Op = MI->getOperand(0); 13273 if (Op.isReg()) { 13274 AM.BaseType = X86AddressMode::RegBase; 13275 AM.Base.Reg = Op.getReg(); 13276 } else { 13277 AM.BaseType = X86AddressMode::FrameIndexBase; 13278 AM.Base.FrameIndex = Op.getIndex(); 13279 } 13280 Op = MI->getOperand(1); 13281 if (Op.isImm()) 13282 AM.Scale = Op.getImm(); 13283 Op = MI->getOperand(2); 13284 if (Op.isImm()) 13285 AM.IndexReg = Op.getImm(); 13286 Op = MI->getOperand(3); 13287 if (Op.isGlobal()) { 13288 AM.GV = Op.getGlobal(); 13289 } else { 13290 AM.Disp = Op.getImm(); 13291 } 13292 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 13293 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 13294 13295 // Reload the original control word now. 13296 addFrameReference(BuildMI(*BB, MI, DL, 13297 TII->get(X86::FLDCW16m)), CWFrameIdx); 13298 13299 MI->eraseFromParent(); // The pseudo instruction is gone now. 13300 return BB; 13301 } 13302 // String/text processing lowering. 13303 case X86::PCMPISTRM128REG: 13304 case X86::VPCMPISTRM128REG: 13305 case X86::PCMPISTRM128MEM: 13306 case X86::VPCMPISTRM128MEM: 13307 case X86::PCMPESTRM128REG: 13308 case X86::VPCMPESTRM128REG: 13309 case X86::PCMPESTRM128MEM: 13310 case X86::VPCMPESTRM128MEM: { 13311 unsigned NumArgs; 13312 bool MemArg; 13313 switch (MI->getOpcode()) { 13314 default: llvm_unreachable("illegal opcode!"); 13315 case X86::PCMPISTRM128REG: 13316 case X86::VPCMPISTRM128REG: 13317 NumArgs = 3; MemArg = false; break; 13318 case X86::PCMPISTRM128MEM: 13319 case X86::VPCMPISTRM128MEM: 13320 NumArgs = 3; MemArg = true; break; 13321 case X86::PCMPESTRM128REG: 13322 case X86::VPCMPESTRM128REG: 13323 NumArgs = 5; MemArg = false; break; 13324 case X86::PCMPESTRM128MEM: 13325 case X86::VPCMPESTRM128MEM: 13326 NumArgs = 5; MemArg = true; break; 13327 } 13328 return EmitPCMP(MI, BB, NumArgs, MemArg); 13329 } 13330 13331 // Thread synchronization. 13332 case X86::MONITOR: 13333 return EmitMonitor(MI, BB); 13334 13335 // Atomic Lowering. 13336 case X86::ATOMAND8: 13337 case X86::ATOMAND16: 13338 case X86::ATOMAND32: 13339 case X86::ATOMAND64: 13340 // Fall through 13341 case X86::ATOMOR8: 13342 case X86::ATOMOR16: 13343 case X86::ATOMOR32: 13344 case X86::ATOMOR64: 13345 // Fall through 13346 case X86::ATOMXOR16: 13347 case X86::ATOMXOR8: 13348 case X86::ATOMXOR32: 13349 case X86::ATOMXOR64: 13350 // Fall through 13351 case X86::ATOMNAND8: 13352 case X86::ATOMNAND16: 13353 case X86::ATOMNAND32: 13354 case X86::ATOMNAND64: 13355 // Fall through 13356 case X86::ATOMMAX8: 13357 case X86::ATOMMAX16: 13358 case X86::ATOMMAX32: 13359 case X86::ATOMMAX64: 13360 // Fall through 13361 case X86::ATOMMIN8: 13362 case X86::ATOMMIN16: 13363 case X86::ATOMMIN32: 13364 case X86::ATOMMIN64: 13365 // Fall through 13366 case X86::ATOMUMAX8: 13367 case X86::ATOMUMAX16: 13368 case X86::ATOMUMAX32: 13369 case X86::ATOMUMAX64: 13370 // Fall through 13371 case X86::ATOMUMIN8: 13372 case X86::ATOMUMIN16: 13373 case X86::ATOMUMIN32: 13374 case X86::ATOMUMIN64: 13375 return EmitAtomicLoadArith(MI, BB); 13376 13377 // This group does 64-bit operations on a 32-bit host. 13378 case X86::ATOMAND6432: 13379 case X86::ATOMOR6432: 13380 case X86::ATOMXOR6432: 13381 case X86::ATOMNAND6432: 13382 case X86::ATOMADD6432: 13383 case X86::ATOMSUB6432: 13384 case X86::ATOMSWAP6432: 13385 return EmitAtomicLoadArith6432(MI, BB); 13386 13387 case X86::VASTART_SAVE_XMM_REGS: 13388 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 13389 13390 case X86::VAARG_64: 13391 return EmitVAARG64WithCustomInserter(MI, BB); 13392 } 13393} 13394 13395//===----------------------------------------------------------------------===// 13396// X86 Optimization Hooks 13397//===----------------------------------------------------------------------===// 13398 13399void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 13400 APInt &KnownZero, 13401 APInt &KnownOne, 13402 const SelectionDAG &DAG, 13403 unsigned Depth) const { 13404 unsigned BitWidth = KnownZero.getBitWidth(); 13405 unsigned Opc = Op.getOpcode(); 13406 assert((Opc >= ISD::BUILTIN_OP_END || 13407 Opc == ISD::INTRINSIC_WO_CHAIN || 13408 Opc == ISD::INTRINSIC_W_CHAIN || 13409 Opc == ISD::INTRINSIC_VOID) && 13410 "Should use MaskedValueIsZero if you don't know whether Op" 13411 " is a target node!"); 13412 13413 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 13414 switch (Opc) { 13415 default: break; 13416 case X86ISD::ADD: 13417 case X86ISD::SUB: 13418 case X86ISD::ADC: 13419 case X86ISD::SBB: 13420 case X86ISD::SMUL: 13421 case X86ISD::UMUL: 13422 case X86ISD::INC: 13423 case X86ISD::DEC: 13424 case X86ISD::OR: 13425 case X86ISD::XOR: 13426 case X86ISD::AND: 13427 // These nodes' second result is a boolean. 13428 if (Op.getResNo() == 0) 13429 break; 13430 // Fallthrough 13431 case X86ISD::SETCC: 13432 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 13433 break; 13434 case ISD::INTRINSIC_WO_CHAIN: { 13435 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 13436 unsigned NumLoBits = 0; 13437 switch (IntId) { 13438 default: break; 13439 case Intrinsic::x86_sse_movmsk_ps: 13440 case Intrinsic::x86_avx_movmsk_ps_256: 13441 case Intrinsic::x86_sse2_movmsk_pd: 13442 case Intrinsic::x86_avx_movmsk_pd_256: 13443 case Intrinsic::x86_mmx_pmovmskb: 13444 case Intrinsic::x86_sse2_pmovmskb_128: 13445 case Intrinsic::x86_avx2_pmovmskb: { 13446 // High bits of movmskp{s|d}, pmovmskb are known zero. 13447 switch (IntId) { 13448 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 13449 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 13450 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 13451 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 13452 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 13453 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 13454 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 13455 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 13456 } 13457 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 13458 break; 13459 } 13460 } 13461 break; 13462 } 13463 } 13464} 13465 13466unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 13467 unsigned Depth) const { 13468 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 13469 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 13470 return Op.getValueType().getScalarType().getSizeInBits(); 13471 13472 // Fallback case. 13473 return 1; 13474} 13475 13476/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 13477/// node is a GlobalAddress + offset. 13478bool X86TargetLowering::isGAPlusOffset(SDNode *N, 13479 const GlobalValue* &GA, 13480 int64_t &Offset) const { 13481 if (N->getOpcode() == X86ISD::Wrapper) { 13482 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 13483 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 13484 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 13485 return true; 13486 } 13487 } 13488 return TargetLowering::isGAPlusOffset(N, GA, Offset); 13489} 13490 13491/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 13492/// same as extracting the high 128-bit part of 256-bit vector and then 13493/// inserting the result into the low part of a new 256-bit vector 13494static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 13495 EVT VT = SVOp->getValueType(0); 13496 unsigned NumElems = VT.getVectorNumElements(); 13497 13498 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13499 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 13500 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 13501 SVOp->getMaskElt(j) >= 0) 13502 return false; 13503 13504 return true; 13505} 13506 13507/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 13508/// same as extracting the low 128-bit part of 256-bit vector and then 13509/// inserting the result into the high part of a new 256-bit vector 13510static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 13511 EVT VT = SVOp->getValueType(0); 13512 unsigned NumElems = VT.getVectorNumElements(); 13513 13514 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13515 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 13516 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 13517 SVOp->getMaskElt(j) >= 0) 13518 return false; 13519 13520 return true; 13521} 13522 13523/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 13524static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 13525 TargetLowering::DAGCombinerInfo &DCI, 13526 const X86Subtarget* Subtarget) { 13527 DebugLoc dl = N->getDebugLoc(); 13528 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 13529 SDValue V1 = SVOp->getOperand(0); 13530 SDValue V2 = SVOp->getOperand(1); 13531 EVT VT = SVOp->getValueType(0); 13532 unsigned NumElems = VT.getVectorNumElements(); 13533 13534 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 13535 V2.getOpcode() == ISD::CONCAT_VECTORS) { 13536 // 13537 // 0,0,0,... 13538 // | 13539 // V UNDEF BUILD_VECTOR UNDEF 13540 // \ / \ / 13541 // CONCAT_VECTOR CONCAT_VECTOR 13542 // \ / 13543 // \ / 13544 // RESULT: V + zero extended 13545 // 13546 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 13547 V2.getOperand(1).getOpcode() != ISD::UNDEF || 13548 V1.getOperand(1).getOpcode() != ISD::UNDEF) 13549 return SDValue(); 13550 13551 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 13552 return SDValue(); 13553 13554 // To match the shuffle mask, the first half of the mask should 13555 // be exactly the first vector, and all the rest a splat with the 13556 // first element of the second one. 13557 for (unsigned i = 0; i != NumElems/2; ++i) 13558 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 13559 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 13560 return SDValue(); 13561 13562 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 13563 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 13564 if (Ld->hasNUsesOfValue(1, 0)) { 13565 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 13566 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 13567 SDValue ResNode = 13568 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 13569 Ld->getMemoryVT(), 13570 Ld->getPointerInfo(), 13571 Ld->getAlignment(), 13572 false/*isVolatile*/, true/*ReadMem*/, 13573 false/*WriteMem*/); 13574 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 13575 } 13576 } 13577 13578 // Emit a zeroed vector and insert the desired subvector on its 13579 // first half. 13580 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 13581 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 13582 return DCI.CombineTo(N, InsV); 13583 } 13584 13585 //===--------------------------------------------------------------------===// 13586 // Combine some shuffles into subvector extracts and inserts: 13587 // 13588 13589 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13590 if (isShuffleHigh128VectorInsertLow(SVOp)) { 13591 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 13592 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 13593 return DCI.CombineTo(N, InsV); 13594 } 13595 13596 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13597 if (isShuffleLow128VectorInsertHigh(SVOp)) { 13598 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 13599 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 13600 return DCI.CombineTo(N, InsV); 13601 } 13602 13603 return SDValue(); 13604} 13605 13606/// PerformShuffleCombine - Performs several different shuffle combines. 13607static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13608 TargetLowering::DAGCombinerInfo &DCI, 13609 const X86Subtarget *Subtarget) { 13610 DebugLoc dl = N->getDebugLoc(); 13611 EVT VT = N->getValueType(0); 13612 13613 // Don't create instructions with illegal types after legalize types has run. 13614 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13615 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13616 return SDValue(); 13617 13618 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13619 if (Subtarget->hasAVX() && VT.is256BitVector() && 13620 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13621 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13622 13623 // Only handle 128 wide vector from here on. 13624 if (!VT.is128BitVector()) 13625 return SDValue(); 13626 13627 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13628 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13629 // consecutive, non-overlapping, and in the right order. 13630 SmallVector<SDValue, 16> Elts; 13631 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13632 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13633 13634 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13635} 13636 13637 13638/// PerformTruncateCombine - Converts truncate operation to 13639/// a sequence of vector shuffle operations. 13640/// It is possible when we truncate 256-bit vector to 128-bit vector 13641static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13642 TargetLowering::DAGCombinerInfo &DCI, 13643 const X86Subtarget *Subtarget) { 13644 if (!DCI.isBeforeLegalizeOps()) 13645 return SDValue(); 13646 13647 if (!Subtarget->hasAVX()) 13648 return SDValue(); 13649 13650 EVT VT = N->getValueType(0); 13651 SDValue Op = N->getOperand(0); 13652 EVT OpVT = Op.getValueType(); 13653 DebugLoc dl = N->getDebugLoc(); 13654 13655 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13656 13657 if (Subtarget->hasAVX2()) { 13658 // AVX2: v4i64 -> v4i32 13659 13660 // VPERMD 13661 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 13662 13663 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op); 13664 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32), 13665 ShufMask); 13666 13667 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, 13668 DAG.getIntPtrConstant(0)); 13669 } 13670 13671 // AVX: v4i64 -> v4i32 13672 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13673 DAG.getIntPtrConstant(0)); 13674 13675 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13676 DAG.getIntPtrConstant(2)); 13677 13678 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13679 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13680 13681 // PSHUFD 13682 static const int ShufMask1[] = {0, 2, 0, 0}; 13683 13684 SDValue Undef = DAG.getUNDEF(VT); 13685 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1); 13686 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1); 13687 13688 // MOVLHPS 13689 static const int ShufMask2[] = {0, 1, 4, 5}; 13690 13691 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13692 } 13693 13694 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13695 13696 if (Subtarget->hasAVX2()) { 13697 // AVX2: v8i32 -> v8i16 13698 13699 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op); 13700 13701 // PSHUFB 13702 SmallVector<SDValue,32> pshufbMask; 13703 for (unsigned i = 0; i < 2; ++i) { 13704 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 13705 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 13706 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 13707 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 13708 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 13709 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 13710 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 13711 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 13712 for (unsigned j = 0; j < 8; ++j) 13713 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 13714 } 13715 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, 13716 &pshufbMask[0], 32); 13717 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV); 13718 13719 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op); 13720 13721 static const int ShufMask[] = {0, 2, -1, -1}; 13722 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64), 13723 &ShufMask[0]); 13724 13725 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13726 DAG.getIntPtrConstant(0)); 13727 13728 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 13729 } 13730 13731 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13732 DAG.getIntPtrConstant(0)); 13733 13734 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13735 DAG.getIntPtrConstant(4)); 13736 13737 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13738 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13739 13740 // PSHUFB 13741 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13742 -1, -1, -1, -1, -1, -1, -1, -1}; 13743 13744 SDValue Undef = DAG.getUNDEF(MVT::v16i8); 13745 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1); 13746 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1); 13747 13748 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13749 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13750 13751 // MOVLHPS 13752 static const int ShufMask2[] = {0, 1, 4, 5}; 13753 13754 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13755 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13756 } 13757 13758 return SDValue(); 13759} 13760 13761/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13762/// specific shuffle of a load can be folded into a single element load. 13763/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13764/// shuffles have been customed lowered so we need to handle those here. 13765static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13766 TargetLowering::DAGCombinerInfo &DCI) { 13767 if (DCI.isBeforeLegalizeOps()) 13768 return SDValue(); 13769 13770 SDValue InVec = N->getOperand(0); 13771 SDValue EltNo = N->getOperand(1); 13772 13773 if (!isa<ConstantSDNode>(EltNo)) 13774 return SDValue(); 13775 13776 EVT VT = InVec.getValueType(); 13777 13778 bool HasShuffleIntoBitcast = false; 13779 if (InVec.getOpcode() == ISD::BITCAST) { 13780 // Don't duplicate a load with other uses. 13781 if (!InVec.hasOneUse()) 13782 return SDValue(); 13783 EVT BCVT = InVec.getOperand(0).getValueType(); 13784 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13785 return SDValue(); 13786 InVec = InVec.getOperand(0); 13787 HasShuffleIntoBitcast = true; 13788 } 13789 13790 if (!isTargetShuffle(InVec.getOpcode())) 13791 return SDValue(); 13792 13793 // Don't duplicate a load with other uses. 13794 if (!InVec.hasOneUse()) 13795 return SDValue(); 13796 13797 SmallVector<int, 16> ShuffleMask; 13798 bool UnaryShuffle; 13799 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 13800 UnaryShuffle)) 13801 return SDValue(); 13802 13803 // Select the input vector, guarding against out of range extract vector. 13804 unsigned NumElems = VT.getVectorNumElements(); 13805 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13806 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13807 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13808 : InVec.getOperand(1); 13809 13810 // If inputs to shuffle are the same for both ops, then allow 2 uses 13811 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13812 13813 if (LdNode.getOpcode() == ISD::BITCAST) { 13814 // Don't duplicate a load with other uses. 13815 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13816 return SDValue(); 13817 13818 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13819 LdNode = LdNode.getOperand(0); 13820 } 13821 13822 if (!ISD::isNormalLoad(LdNode.getNode())) 13823 return SDValue(); 13824 13825 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13826 13827 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13828 return SDValue(); 13829 13830 if (HasShuffleIntoBitcast) { 13831 // If there's a bitcast before the shuffle, check if the load type and 13832 // alignment is valid. 13833 unsigned Align = LN0->getAlignment(); 13834 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13835 unsigned NewAlign = TLI.getTargetData()-> 13836 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13837 13838 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13839 return SDValue(); 13840 } 13841 13842 // All checks match so transform back to vector_shuffle so that DAG combiner 13843 // can finish the job 13844 DebugLoc dl = N->getDebugLoc(); 13845 13846 // Create shuffle node taking into account the case that its a unary shuffle 13847 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13848 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13849 InVec.getOperand(0), Shuffle, 13850 &ShuffleMask[0]); 13851 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13852 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13853 EltNo); 13854} 13855 13856/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13857/// generation and convert it from being a bunch of shuffles and extracts 13858/// to a simple store and scalar loads to extract the elements. 13859static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13860 TargetLowering::DAGCombinerInfo &DCI) { 13861 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13862 if (NewOp.getNode()) 13863 return NewOp; 13864 13865 SDValue InputVector = N->getOperand(0); 13866 13867 // Only operate on vectors of 4 elements, where the alternative shuffling 13868 // gets to be more expensive. 13869 if (InputVector.getValueType() != MVT::v4i32) 13870 return SDValue(); 13871 13872 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13873 // single use which is a sign-extend or zero-extend, and all elements are 13874 // used. 13875 SmallVector<SDNode *, 4> Uses; 13876 unsigned ExtractedElements = 0; 13877 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13878 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13879 if (UI.getUse().getResNo() != InputVector.getResNo()) 13880 return SDValue(); 13881 13882 SDNode *Extract = *UI; 13883 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13884 return SDValue(); 13885 13886 if (Extract->getValueType(0) != MVT::i32) 13887 return SDValue(); 13888 if (!Extract->hasOneUse()) 13889 return SDValue(); 13890 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13891 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13892 return SDValue(); 13893 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13894 return SDValue(); 13895 13896 // Record which element was extracted. 13897 ExtractedElements |= 13898 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13899 13900 Uses.push_back(Extract); 13901 } 13902 13903 // If not all the elements were used, this may not be worthwhile. 13904 if (ExtractedElements != 15) 13905 return SDValue(); 13906 13907 // Ok, we've now decided to do the transformation. 13908 DebugLoc dl = InputVector.getDebugLoc(); 13909 13910 // Store the value to a temporary stack slot. 13911 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13912 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13913 MachinePointerInfo(), false, false, 0); 13914 13915 // Replace each use (extract) with a load of the appropriate element. 13916 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13917 UE = Uses.end(); UI != UE; ++UI) { 13918 SDNode *Extract = *UI; 13919 13920 // cOMpute the element's address. 13921 SDValue Idx = Extract->getOperand(1); 13922 unsigned EltSize = 13923 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13924 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13925 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13926 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13927 13928 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13929 StackPtr, OffsetVal); 13930 13931 // Load the scalar. 13932 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13933 ScalarAddr, MachinePointerInfo(), 13934 false, false, false, 0); 13935 13936 // Replace the exact with the load. 13937 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13938 } 13939 13940 // The replacement was made in place; don't return anything. 13941 return SDValue(); 13942} 13943 13944/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13945/// nodes. 13946static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13947 TargetLowering::DAGCombinerInfo &DCI, 13948 const X86Subtarget *Subtarget) { 13949 DebugLoc DL = N->getDebugLoc(); 13950 SDValue Cond = N->getOperand(0); 13951 // Get the LHS/RHS of the select. 13952 SDValue LHS = N->getOperand(1); 13953 SDValue RHS = N->getOperand(2); 13954 EVT VT = LHS.getValueType(); 13955 13956 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13957 // instructions match the semantics of the common C idiom x<y?x:y but not 13958 // x<=y?x:y, because of how they handle negative zero (which can be 13959 // ignored in unsafe-math mode). 13960 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13961 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13962 (Subtarget->hasSSE2() || 13963 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13964 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13965 13966 unsigned Opcode = 0; 13967 // Check for x CC y ? x : y. 13968 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13969 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13970 switch (CC) { 13971 default: break; 13972 case ISD::SETULT: 13973 // Converting this to a min would handle NaNs incorrectly, and swapping 13974 // the operands would cause it to handle comparisons between positive 13975 // and negative zero incorrectly. 13976 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13977 if (!DAG.getTarget().Options.UnsafeFPMath && 13978 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13979 break; 13980 std::swap(LHS, RHS); 13981 } 13982 Opcode = X86ISD::FMIN; 13983 break; 13984 case ISD::SETOLE: 13985 // Converting this to a min would handle comparisons between positive 13986 // and negative zero incorrectly. 13987 if (!DAG.getTarget().Options.UnsafeFPMath && 13988 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13989 break; 13990 Opcode = X86ISD::FMIN; 13991 break; 13992 case ISD::SETULE: 13993 // Converting this to a min would handle both negative zeros and NaNs 13994 // incorrectly, but we can swap the operands to fix both. 13995 std::swap(LHS, RHS); 13996 case ISD::SETOLT: 13997 case ISD::SETLT: 13998 case ISD::SETLE: 13999 Opcode = X86ISD::FMIN; 14000 break; 14001 14002 case ISD::SETOGE: 14003 // Converting this to a max would handle comparisons between positive 14004 // and negative zero incorrectly. 14005 if (!DAG.getTarget().Options.UnsafeFPMath && 14006 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 14007 break; 14008 Opcode = X86ISD::FMAX; 14009 break; 14010 case ISD::SETUGT: 14011 // Converting this to a max would handle NaNs incorrectly, and swapping 14012 // the operands would cause it to handle comparisons between positive 14013 // and negative zero incorrectly. 14014 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 14015 if (!DAG.getTarget().Options.UnsafeFPMath && 14016 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 14017 break; 14018 std::swap(LHS, RHS); 14019 } 14020 Opcode = X86ISD::FMAX; 14021 break; 14022 case ISD::SETUGE: 14023 // Converting this to a max would handle both negative zeros and NaNs 14024 // incorrectly, but we can swap the operands to fix both. 14025 std::swap(LHS, RHS); 14026 case ISD::SETOGT: 14027 case ISD::SETGT: 14028 case ISD::SETGE: 14029 Opcode = X86ISD::FMAX; 14030 break; 14031 } 14032 // Check for x CC y ? y : x -- a min/max with reversed arms. 14033 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 14034 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 14035 switch (CC) { 14036 default: break; 14037 case ISD::SETOGE: 14038 // Converting this to a min would handle comparisons between positive 14039 // and negative zero incorrectly, and swapping the operands would 14040 // cause it to handle NaNs incorrectly. 14041 if (!DAG.getTarget().Options.UnsafeFPMath && 14042 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 14043 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 14044 break; 14045 std::swap(LHS, RHS); 14046 } 14047 Opcode = X86ISD::FMIN; 14048 break; 14049 case ISD::SETUGT: 14050 // Converting this to a min would handle NaNs incorrectly. 14051 if (!DAG.getTarget().Options.UnsafeFPMath && 14052 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 14053 break; 14054 Opcode = X86ISD::FMIN; 14055 break; 14056 case ISD::SETUGE: 14057 // Converting this to a min would handle both negative zeros and NaNs 14058 // incorrectly, but we can swap the operands to fix both. 14059 std::swap(LHS, RHS); 14060 case ISD::SETOGT: 14061 case ISD::SETGT: 14062 case ISD::SETGE: 14063 Opcode = X86ISD::FMIN; 14064 break; 14065 14066 case ISD::SETULT: 14067 // Converting this to a max would handle NaNs incorrectly. 14068 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 14069 break; 14070 Opcode = X86ISD::FMAX; 14071 break; 14072 case ISD::SETOLE: 14073 // Converting this to a max would handle comparisons between positive 14074 // and negative zero incorrectly, and swapping the operands would 14075 // cause it to handle NaNs incorrectly. 14076 if (!DAG.getTarget().Options.UnsafeFPMath && 14077 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 14078 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 14079 break; 14080 std::swap(LHS, RHS); 14081 } 14082 Opcode = X86ISD::FMAX; 14083 break; 14084 case ISD::SETULE: 14085 // Converting this to a max would handle both negative zeros and NaNs 14086 // incorrectly, but we can swap the operands to fix both. 14087 std::swap(LHS, RHS); 14088 case ISD::SETOLT: 14089 case ISD::SETLT: 14090 case ISD::SETLE: 14091 Opcode = X86ISD::FMAX; 14092 break; 14093 } 14094 } 14095 14096 if (Opcode) 14097 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 14098 } 14099 14100 // If this is a select between two integer constants, try to do some 14101 // optimizations. 14102 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 14103 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 14104 // Don't do this for crazy integer types. 14105 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 14106 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 14107 // so that TrueC (the true value) is larger than FalseC. 14108 bool NeedsCondInvert = false; 14109 14110 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 14111 // Efficiently invertible. 14112 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 14113 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 14114 isa<ConstantSDNode>(Cond.getOperand(1))))) { 14115 NeedsCondInvert = true; 14116 std::swap(TrueC, FalseC); 14117 } 14118 14119 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 14120 if (FalseC->getAPIntValue() == 0 && 14121 TrueC->getAPIntValue().isPowerOf2()) { 14122 if (NeedsCondInvert) // Invert the condition if needed. 14123 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 14124 DAG.getConstant(1, Cond.getValueType())); 14125 14126 // Zero extend the condition if needed. 14127 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 14128 14129 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 14130 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 14131 DAG.getConstant(ShAmt, MVT::i8)); 14132 } 14133 14134 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 14135 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 14136 if (NeedsCondInvert) // Invert the condition if needed. 14137 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 14138 DAG.getConstant(1, Cond.getValueType())); 14139 14140 // Zero extend the condition if needed. 14141 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 14142 FalseC->getValueType(0), Cond); 14143 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 14144 SDValue(FalseC, 0)); 14145 } 14146 14147 // Optimize cases that will turn into an LEA instruction. This requires 14148 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 14149 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 14150 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 14151 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 14152 14153 bool isFastMultiplier = false; 14154 if (Diff < 10) { 14155 switch ((unsigned char)Diff) { 14156 default: break; 14157 case 1: // result = add base, cond 14158 case 2: // result = lea base( , cond*2) 14159 case 3: // result = lea base(cond, cond*2) 14160 case 4: // result = lea base( , cond*4) 14161 case 5: // result = lea base(cond, cond*4) 14162 case 8: // result = lea base( , cond*8) 14163 case 9: // result = lea base(cond, cond*8) 14164 isFastMultiplier = true; 14165 break; 14166 } 14167 } 14168 14169 if (isFastMultiplier) { 14170 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 14171 if (NeedsCondInvert) // Invert the condition if needed. 14172 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 14173 DAG.getConstant(1, Cond.getValueType())); 14174 14175 // Zero extend the condition if needed. 14176 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 14177 Cond); 14178 // Scale the condition by the difference. 14179 if (Diff != 1) 14180 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 14181 DAG.getConstant(Diff, Cond.getValueType())); 14182 14183 // Add the base if non-zero. 14184 if (FalseC->getAPIntValue() != 0) 14185 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 14186 SDValue(FalseC, 0)); 14187 return Cond; 14188 } 14189 } 14190 } 14191 } 14192 14193 // Canonicalize max and min: 14194 // (x > y) ? x : y -> (x >= y) ? x : y 14195 // (x < y) ? x : y -> (x <= y) ? x : y 14196 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 14197 // the need for an extra compare 14198 // against zero. e.g. 14199 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 14200 // subl %esi, %edi 14201 // testl %edi, %edi 14202 // movl $0, %eax 14203 // cmovgl %edi, %eax 14204 // => 14205 // xorl %eax, %eax 14206 // subl %esi, $edi 14207 // cmovsl %eax, %edi 14208 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 14209 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 14210 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 14211 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 14212 switch (CC) { 14213 default: break; 14214 case ISD::SETLT: 14215 case ISD::SETGT: { 14216 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 14217 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 14218 Cond.getOperand(0), Cond.getOperand(1), NewCC); 14219 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 14220 } 14221 } 14222 } 14223 14224 // If we know that this node is legal then we know that it is going to be 14225 // matched by one of the SSE/AVX BLEND instructions. These instructions only 14226 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 14227 // to simplify previous instructions. 14228 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14229 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 14230 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) { 14231 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 14232 14233 // Don't optimize vector selects that map to mask-registers. 14234 if (BitWidth == 1) 14235 return SDValue(); 14236 14237 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 14238 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 14239 14240 APInt KnownZero, KnownOne; 14241 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 14242 DCI.isBeforeLegalizeOps()); 14243 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 14244 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 14245 DCI.CommitTargetLoweringOpt(TLO); 14246 } 14247 14248 return SDValue(); 14249} 14250 14251// Check whether a boolean test is testing a boolean value generated by 14252// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition 14253// code. 14254// 14255// Simplify the following patterns: 14256// (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or 14257// (Op (CMP (SETCC Cond EFLAGS) 0) NEQ) 14258// to (Op EFLAGS Cond) 14259// 14260// (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or 14261// (Op (CMP (SETCC Cond EFLAGS) 1) NEQ) 14262// to (Op EFLAGS !Cond) 14263// 14264// where Op could be BRCOND or CMOV. 14265// 14266static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) { 14267 // Quit if not CMP and SUB with its value result used. 14268 if (Cmp.getOpcode() != X86ISD::CMP && 14269 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0))) 14270 return SDValue(); 14271 14272 // Quit if not used as a boolean value. 14273 if (CC != X86::COND_E && CC != X86::COND_NE) 14274 return SDValue(); 14275 14276 // Check CMP operands. One of them should be 0 or 1 and the other should be 14277 // an SetCC or extended from it. 14278 SDValue Op1 = Cmp.getOperand(0); 14279 SDValue Op2 = Cmp.getOperand(1); 14280 14281 SDValue SetCC; 14282 const ConstantSDNode* C = 0; 14283 bool needOppositeCond = (CC == X86::COND_E); 14284 14285 if ((C = dyn_cast<ConstantSDNode>(Op1))) 14286 SetCC = Op2; 14287 else if ((C = dyn_cast<ConstantSDNode>(Op2))) 14288 SetCC = Op1; 14289 else // Quit if all operands are not constants. 14290 return SDValue(); 14291 14292 if (C->getZExtValue() == 1) 14293 needOppositeCond = !needOppositeCond; 14294 else if (C->getZExtValue() != 0) 14295 // Quit if the constant is neither 0 or 1. 14296 return SDValue(); 14297 14298 // Skip 'zext' node. 14299 if (SetCC.getOpcode() == ISD::ZERO_EXTEND) 14300 SetCC = SetCC.getOperand(0); 14301 14302 switch (SetCC.getOpcode()) { 14303 case X86ISD::SETCC: 14304 // Set the condition code or opposite one if necessary. 14305 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); 14306 if (needOppositeCond) 14307 CC = X86::GetOppositeBranchCondition(CC); 14308 return SetCC.getOperand(1); 14309 case X86ISD::CMOV: { 14310 // Check whether false/true value has canonical one, i.e. 0 or 1. 14311 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0)); 14312 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1)); 14313 // Quit if true value is not a constant. 14314 if (!TVal) 14315 return SDValue(); 14316 // Quit if false value is not a constant. 14317 if (!FVal) { 14318 // A special case for rdrand, where 0 is set if false cond is found. 14319 SDValue Op = SetCC.getOperand(0); 14320 if (Op.getOpcode() != X86ISD::RDRAND) 14321 return SDValue(); 14322 } 14323 // Quit if false value is not the constant 0 or 1. 14324 bool FValIsFalse = true; 14325 if (FVal && FVal->getZExtValue() != 0) { 14326 if (FVal->getZExtValue() != 1) 14327 return SDValue(); 14328 // If FVal is 1, opposite cond is needed. 14329 needOppositeCond = !needOppositeCond; 14330 FValIsFalse = false; 14331 } 14332 // Quit if TVal is not the constant opposite of FVal. 14333 if (FValIsFalse && TVal->getZExtValue() != 1) 14334 return SDValue(); 14335 if (!FValIsFalse && TVal->getZExtValue() != 0) 14336 return SDValue(); 14337 CC = X86::CondCode(SetCC.getConstantOperandVal(2)); 14338 if (needOppositeCond) 14339 CC = X86::GetOppositeBranchCondition(CC); 14340 return SetCC.getOperand(3); 14341 } 14342 } 14343 14344 return SDValue(); 14345} 14346 14347/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 14348static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 14349 TargetLowering::DAGCombinerInfo &DCI, 14350 const X86Subtarget *Subtarget) { 14351 DebugLoc DL = N->getDebugLoc(); 14352 14353 // If the flag operand isn't dead, don't touch this CMOV. 14354 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 14355 return SDValue(); 14356 14357 SDValue FalseOp = N->getOperand(0); 14358 SDValue TrueOp = N->getOperand(1); 14359 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 14360 SDValue Cond = N->getOperand(3); 14361 14362 if (CC == X86::COND_E || CC == X86::COND_NE) { 14363 switch (Cond.getOpcode()) { 14364 default: break; 14365 case X86ISD::BSR: 14366 case X86ISD::BSF: 14367 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 14368 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 14369 return (CC == X86::COND_E) ? FalseOp : TrueOp; 14370 } 14371 } 14372 14373 SDValue Flags; 14374 14375 Flags = checkBoolTestSetCCCombine(Cond, CC); 14376 if (Flags.getNode() && 14377 // Extra check as FCMOV only supports a subset of X86 cond. 14378 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) { 14379 SDValue Ops[] = { FalseOp, TrueOp, 14380 DAG.getConstant(CC, MVT::i8), Flags }; 14381 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), 14382 Ops, array_lengthof(Ops)); 14383 } 14384 14385 // If this is a select between two integer constants, try to do some 14386 // optimizations. Note that the operands are ordered the opposite of SELECT 14387 // operands. 14388 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 14389 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 14390 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 14391 // larger than FalseC (the false value). 14392 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 14393 CC = X86::GetOppositeBranchCondition(CC); 14394 std::swap(TrueC, FalseC); 14395 } 14396 14397 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 14398 // This is efficient for any integer data type (including i8/i16) and 14399 // shift amount. 14400 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 14401 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 14402 DAG.getConstant(CC, MVT::i8), Cond); 14403 14404 // Zero extend the condition if needed. 14405 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 14406 14407 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 14408 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 14409 DAG.getConstant(ShAmt, MVT::i8)); 14410 if (N->getNumValues() == 2) // Dead flag value? 14411 return DCI.CombineTo(N, Cond, SDValue()); 14412 return Cond; 14413 } 14414 14415 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 14416 // for any integer data type, including i8/i16. 14417 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 14418 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 14419 DAG.getConstant(CC, MVT::i8), Cond); 14420 14421 // Zero extend the condition if needed. 14422 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 14423 FalseC->getValueType(0), Cond); 14424 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 14425 SDValue(FalseC, 0)); 14426 14427 if (N->getNumValues() == 2) // Dead flag value? 14428 return DCI.CombineTo(N, Cond, SDValue()); 14429 return Cond; 14430 } 14431 14432 // Optimize cases that will turn into an LEA instruction. This requires 14433 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 14434 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 14435 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 14436 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 14437 14438 bool isFastMultiplier = false; 14439 if (Diff < 10) { 14440 switch ((unsigned char)Diff) { 14441 default: break; 14442 case 1: // result = add base, cond 14443 case 2: // result = lea base( , cond*2) 14444 case 3: // result = lea base(cond, cond*2) 14445 case 4: // result = lea base( , cond*4) 14446 case 5: // result = lea base(cond, cond*4) 14447 case 8: // result = lea base( , cond*8) 14448 case 9: // result = lea base(cond, cond*8) 14449 isFastMultiplier = true; 14450 break; 14451 } 14452 } 14453 14454 if (isFastMultiplier) { 14455 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 14456 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 14457 DAG.getConstant(CC, MVT::i8), Cond); 14458 // Zero extend the condition if needed. 14459 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 14460 Cond); 14461 // Scale the condition by the difference. 14462 if (Diff != 1) 14463 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 14464 DAG.getConstant(Diff, Cond.getValueType())); 14465 14466 // Add the base if non-zero. 14467 if (FalseC->getAPIntValue() != 0) 14468 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 14469 SDValue(FalseC, 0)); 14470 if (N->getNumValues() == 2) // Dead flag value? 14471 return DCI.CombineTo(N, Cond, SDValue()); 14472 return Cond; 14473 } 14474 } 14475 } 14476 } 14477 return SDValue(); 14478} 14479 14480 14481/// PerformMulCombine - Optimize a single multiply with constant into two 14482/// in order to implement it with two cheaper instructions, e.g. 14483/// LEA + SHL, LEA + LEA. 14484static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 14485 TargetLowering::DAGCombinerInfo &DCI) { 14486 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 14487 return SDValue(); 14488 14489 EVT VT = N->getValueType(0); 14490 if (VT != MVT::i64) 14491 return SDValue(); 14492 14493 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 14494 if (!C) 14495 return SDValue(); 14496 uint64_t MulAmt = C->getZExtValue(); 14497 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 14498 return SDValue(); 14499 14500 uint64_t MulAmt1 = 0; 14501 uint64_t MulAmt2 = 0; 14502 if ((MulAmt % 9) == 0) { 14503 MulAmt1 = 9; 14504 MulAmt2 = MulAmt / 9; 14505 } else if ((MulAmt % 5) == 0) { 14506 MulAmt1 = 5; 14507 MulAmt2 = MulAmt / 5; 14508 } else if ((MulAmt % 3) == 0) { 14509 MulAmt1 = 3; 14510 MulAmt2 = MulAmt / 3; 14511 } 14512 if (MulAmt2 && 14513 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 14514 DebugLoc DL = N->getDebugLoc(); 14515 14516 if (isPowerOf2_64(MulAmt2) && 14517 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 14518 // If second multiplifer is pow2, issue it first. We want the multiply by 14519 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 14520 // is an add. 14521 std::swap(MulAmt1, MulAmt2); 14522 14523 SDValue NewMul; 14524 if (isPowerOf2_64(MulAmt1)) 14525 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 14526 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 14527 else 14528 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 14529 DAG.getConstant(MulAmt1, VT)); 14530 14531 if (isPowerOf2_64(MulAmt2)) 14532 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 14533 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 14534 else 14535 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 14536 DAG.getConstant(MulAmt2, VT)); 14537 14538 // Do not add new nodes to DAG combiner worklist. 14539 DCI.CombineTo(N, NewMul, false); 14540 } 14541 return SDValue(); 14542} 14543 14544static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 14545 SDValue N0 = N->getOperand(0); 14546 SDValue N1 = N->getOperand(1); 14547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 14548 EVT VT = N0.getValueType(); 14549 14550 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 14551 // since the result of setcc_c is all zero's or all ones. 14552 if (VT.isInteger() && !VT.isVector() && 14553 N1C && N0.getOpcode() == ISD::AND && 14554 N0.getOperand(1).getOpcode() == ISD::Constant) { 14555 SDValue N00 = N0.getOperand(0); 14556 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 14557 ((N00.getOpcode() == ISD::ANY_EXTEND || 14558 N00.getOpcode() == ISD::ZERO_EXTEND) && 14559 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 14560 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 14561 APInt ShAmt = N1C->getAPIntValue(); 14562 Mask = Mask.shl(ShAmt); 14563 if (Mask != 0) 14564 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 14565 N00, DAG.getConstant(Mask, VT)); 14566 } 14567 } 14568 14569 14570 // Hardware support for vector shifts is sparse which makes us scalarize the 14571 // vector operations in many cases. Also, on sandybridge ADD is faster than 14572 // shl. 14573 // (shl V, 1) -> add V,V 14574 if (isSplatVector(N1.getNode())) { 14575 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 14576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 14577 // We shift all of the values by one. In many cases we do not have 14578 // hardware support for this operation. This is better expressed as an ADD 14579 // of two values. 14580 if (N1C && (1 == N1C->getZExtValue())) { 14581 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 14582 } 14583 } 14584 14585 return SDValue(); 14586} 14587 14588/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 14589/// when possible. 14590static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 14591 TargetLowering::DAGCombinerInfo &DCI, 14592 const X86Subtarget *Subtarget) { 14593 EVT VT = N->getValueType(0); 14594 if (N->getOpcode() == ISD::SHL) { 14595 SDValue V = PerformSHLCombine(N, DAG); 14596 if (V.getNode()) return V; 14597 } 14598 14599 // On X86 with SSE2 support, we can transform this to a vector shift if 14600 // all elements are shifted by the same amount. We can't do this in legalize 14601 // because the a constant vector is typically transformed to a constant pool 14602 // so we have no knowledge of the shift amount. 14603 if (!Subtarget->hasSSE2()) 14604 return SDValue(); 14605 14606 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 14607 (!Subtarget->hasAVX2() || 14608 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 14609 return SDValue(); 14610 14611 SDValue ShAmtOp = N->getOperand(1); 14612 EVT EltVT = VT.getVectorElementType(); 14613 DebugLoc DL = N->getDebugLoc(); 14614 SDValue BaseShAmt = SDValue(); 14615 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 14616 unsigned NumElts = VT.getVectorNumElements(); 14617 unsigned i = 0; 14618 for (; i != NumElts; ++i) { 14619 SDValue Arg = ShAmtOp.getOperand(i); 14620 if (Arg.getOpcode() == ISD::UNDEF) continue; 14621 BaseShAmt = Arg; 14622 break; 14623 } 14624 // Handle the case where the build_vector is all undef 14625 // FIXME: Should DAG allow this? 14626 if (i == NumElts) 14627 return SDValue(); 14628 14629 for (; i != NumElts; ++i) { 14630 SDValue Arg = ShAmtOp.getOperand(i); 14631 if (Arg.getOpcode() == ISD::UNDEF) continue; 14632 if (Arg != BaseShAmt) { 14633 return SDValue(); 14634 } 14635 } 14636 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 14637 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 14638 SDValue InVec = ShAmtOp.getOperand(0); 14639 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 14640 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 14641 unsigned i = 0; 14642 for (; i != NumElts; ++i) { 14643 SDValue Arg = InVec.getOperand(i); 14644 if (Arg.getOpcode() == ISD::UNDEF) continue; 14645 BaseShAmt = Arg; 14646 break; 14647 } 14648 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 14649 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 14650 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 14651 if (C->getZExtValue() == SplatIdx) 14652 BaseShAmt = InVec.getOperand(1); 14653 } 14654 } 14655 if (BaseShAmt.getNode() == 0) { 14656 // Don't create instructions with illegal types after legalize 14657 // types has run. 14658 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 14659 !DCI.isBeforeLegalize()) 14660 return SDValue(); 14661 14662 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 14663 DAG.getIntPtrConstant(0)); 14664 } 14665 } else 14666 return SDValue(); 14667 14668 // The shift amount is an i32. 14669 if (EltVT.bitsGT(MVT::i32)) 14670 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 14671 else if (EltVT.bitsLT(MVT::i32)) 14672 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 14673 14674 // The shift amount is identical so we can do a vector shift. 14675 SDValue ValOp = N->getOperand(0); 14676 switch (N->getOpcode()) { 14677 default: 14678 llvm_unreachable("Unknown shift opcode!"); 14679 case ISD::SHL: 14680 switch (VT.getSimpleVT().SimpleTy) { 14681 default: return SDValue(); 14682 case MVT::v2i64: 14683 case MVT::v4i32: 14684 case MVT::v8i16: 14685 case MVT::v4i64: 14686 case MVT::v8i32: 14687 case MVT::v16i16: 14688 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 14689 } 14690 case ISD::SRA: 14691 switch (VT.getSimpleVT().SimpleTy) { 14692 default: return SDValue(); 14693 case MVT::v4i32: 14694 case MVT::v8i16: 14695 case MVT::v8i32: 14696 case MVT::v16i16: 14697 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 14698 } 14699 case ISD::SRL: 14700 switch (VT.getSimpleVT().SimpleTy) { 14701 default: return SDValue(); 14702 case MVT::v2i64: 14703 case MVT::v4i32: 14704 case MVT::v8i16: 14705 case MVT::v4i64: 14706 case MVT::v8i32: 14707 case MVT::v16i16: 14708 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 14709 } 14710 } 14711} 14712 14713 14714// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 14715// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 14716// and friends. Likewise for OR -> CMPNEQSS. 14717static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 14718 TargetLowering::DAGCombinerInfo &DCI, 14719 const X86Subtarget *Subtarget) { 14720 unsigned opcode; 14721 14722 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 14723 // we're requiring SSE2 for both. 14724 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 14725 SDValue N0 = N->getOperand(0); 14726 SDValue N1 = N->getOperand(1); 14727 SDValue CMP0 = N0->getOperand(1); 14728 SDValue CMP1 = N1->getOperand(1); 14729 DebugLoc DL = N->getDebugLoc(); 14730 14731 // The SETCCs should both refer to the same CMP. 14732 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 14733 return SDValue(); 14734 14735 SDValue CMP00 = CMP0->getOperand(0); 14736 SDValue CMP01 = CMP0->getOperand(1); 14737 EVT VT = CMP00.getValueType(); 14738 14739 if (VT == MVT::f32 || VT == MVT::f64) { 14740 bool ExpectingFlags = false; 14741 // Check for any users that want flags: 14742 for (SDNode::use_iterator UI = N->use_begin(), 14743 UE = N->use_end(); 14744 !ExpectingFlags && UI != UE; ++UI) 14745 switch (UI->getOpcode()) { 14746 default: 14747 case ISD::BR_CC: 14748 case ISD::BRCOND: 14749 case ISD::SELECT: 14750 ExpectingFlags = true; 14751 break; 14752 case ISD::CopyToReg: 14753 case ISD::SIGN_EXTEND: 14754 case ISD::ZERO_EXTEND: 14755 case ISD::ANY_EXTEND: 14756 break; 14757 } 14758 14759 if (!ExpectingFlags) { 14760 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 14761 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 14762 14763 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 14764 X86::CondCode tmp = cc0; 14765 cc0 = cc1; 14766 cc1 = tmp; 14767 } 14768 14769 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 14770 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 14771 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 14772 X86ISD::NodeType NTOperator = is64BitFP ? 14773 X86ISD::FSETCCsd : X86ISD::FSETCCss; 14774 // FIXME: need symbolic constants for these magic numbers. 14775 // See X86ATTInstPrinter.cpp:printSSECC(). 14776 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14777 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14778 DAG.getConstant(x86cc, MVT::i8)); 14779 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14780 OnesOrZeroesF); 14781 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14782 DAG.getConstant(1, MVT::i32)); 14783 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14784 return OneBitOfTruth; 14785 } 14786 } 14787 } 14788 } 14789 return SDValue(); 14790} 14791 14792/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14793/// so it can be folded inside ANDNP. 14794static bool CanFoldXORWithAllOnes(const SDNode *N) { 14795 EVT VT = N->getValueType(0); 14796 14797 // Match direct AllOnes for 128 and 256-bit vectors 14798 if (ISD::isBuildVectorAllOnes(N)) 14799 return true; 14800 14801 // Look through a bit convert. 14802 if (N->getOpcode() == ISD::BITCAST) 14803 N = N->getOperand(0).getNode(); 14804 14805 // Sometimes the operand may come from a insert_subvector building a 256-bit 14806 // allones vector 14807 if (VT.is256BitVector() && 14808 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14809 SDValue V1 = N->getOperand(0); 14810 SDValue V2 = N->getOperand(1); 14811 14812 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14813 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14814 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14815 ISD::isBuildVectorAllOnes(V2.getNode())) 14816 return true; 14817 } 14818 14819 return false; 14820} 14821 14822static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14823 TargetLowering::DAGCombinerInfo &DCI, 14824 const X86Subtarget *Subtarget) { 14825 if (DCI.isBeforeLegalizeOps()) 14826 return SDValue(); 14827 14828 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14829 if (R.getNode()) 14830 return R; 14831 14832 EVT VT = N->getValueType(0); 14833 14834 // Create ANDN, BLSI, and BLSR instructions 14835 // BLSI is X & (-X) 14836 // BLSR is X & (X-1) 14837 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14838 SDValue N0 = N->getOperand(0); 14839 SDValue N1 = N->getOperand(1); 14840 DebugLoc DL = N->getDebugLoc(); 14841 14842 // Check LHS for not 14843 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14844 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14845 // Check RHS for not 14846 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14847 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14848 14849 // Check LHS for neg 14850 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14851 isZero(N0.getOperand(0))) 14852 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14853 14854 // Check RHS for neg 14855 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14856 isZero(N1.getOperand(0))) 14857 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14858 14859 // Check LHS for X-1 14860 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14861 isAllOnes(N0.getOperand(1))) 14862 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14863 14864 // Check RHS for X-1 14865 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14866 isAllOnes(N1.getOperand(1))) 14867 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14868 14869 return SDValue(); 14870 } 14871 14872 // Want to form ANDNP nodes: 14873 // 1) In the hopes of then easily combining them with OR and AND nodes 14874 // to form PBLEND/PSIGN. 14875 // 2) To match ANDN packed intrinsics 14876 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14877 return SDValue(); 14878 14879 SDValue N0 = N->getOperand(0); 14880 SDValue N1 = N->getOperand(1); 14881 DebugLoc DL = N->getDebugLoc(); 14882 14883 // Check LHS for vnot 14884 if (N0.getOpcode() == ISD::XOR && 14885 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14886 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14887 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14888 14889 // Check RHS for vnot 14890 if (N1.getOpcode() == ISD::XOR && 14891 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14892 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14893 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14894 14895 return SDValue(); 14896} 14897 14898static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14899 TargetLowering::DAGCombinerInfo &DCI, 14900 const X86Subtarget *Subtarget) { 14901 if (DCI.isBeforeLegalizeOps()) 14902 return SDValue(); 14903 14904 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14905 if (R.getNode()) 14906 return R; 14907 14908 EVT VT = N->getValueType(0); 14909 14910 SDValue N0 = N->getOperand(0); 14911 SDValue N1 = N->getOperand(1); 14912 14913 // look for psign/blend 14914 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14915 if (!Subtarget->hasSSSE3() || 14916 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14917 return SDValue(); 14918 14919 // Canonicalize pandn to RHS 14920 if (N0.getOpcode() == X86ISD::ANDNP) 14921 std::swap(N0, N1); 14922 // or (and (m, y), (pandn m, x)) 14923 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14924 SDValue Mask = N1.getOperand(0); 14925 SDValue X = N1.getOperand(1); 14926 SDValue Y; 14927 if (N0.getOperand(0) == Mask) 14928 Y = N0.getOperand(1); 14929 if (N0.getOperand(1) == Mask) 14930 Y = N0.getOperand(0); 14931 14932 // Check to see if the mask appeared in both the AND and ANDNP and 14933 if (!Y.getNode()) 14934 return SDValue(); 14935 14936 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14937 // Look through mask bitcast. 14938 if (Mask.getOpcode() == ISD::BITCAST) 14939 Mask = Mask.getOperand(0); 14940 if (X.getOpcode() == ISD::BITCAST) 14941 X = X.getOperand(0); 14942 if (Y.getOpcode() == ISD::BITCAST) 14943 Y = Y.getOperand(0); 14944 14945 EVT MaskVT = Mask.getValueType(); 14946 14947 // Validate that the Mask operand is a vector sra node. 14948 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14949 // there is no psrai.b 14950 if (Mask.getOpcode() != X86ISD::VSRAI) 14951 return SDValue(); 14952 14953 // Check that the SRA is all signbits. 14954 SDValue SraC = Mask.getOperand(1); 14955 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14956 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14957 if ((SraAmt + 1) != EltBits) 14958 return SDValue(); 14959 14960 DebugLoc DL = N->getDebugLoc(); 14961 14962 // Now we know we at least have a plendvb with the mask val. See if 14963 // we can form a psignb/w/d. 14964 // psign = x.type == y.type == mask.type && y = sub(0, x); 14965 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14966 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14967 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14968 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14969 "Unsupported VT for PSIGN"); 14970 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14971 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14972 } 14973 // PBLENDVB only available on SSE 4.1 14974 if (!Subtarget->hasSSE41()) 14975 return SDValue(); 14976 14977 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14978 14979 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14980 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14981 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14982 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14983 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14984 } 14985 } 14986 14987 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14988 return SDValue(); 14989 14990 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14991 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14992 std::swap(N0, N1); 14993 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14994 return SDValue(); 14995 if (!N0.hasOneUse() || !N1.hasOneUse()) 14996 return SDValue(); 14997 14998 SDValue ShAmt0 = N0.getOperand(1); 14999 if (ShAmt0.getValueType() != MVT::i8) 15000 return SDValue(); 15001 SDValue ShAmt1 = N1.getOperand(1); 15002 if (ShAmt1.getValueType() != MVT::i8) 15003 return SDValue(); 15004 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 15005 ShAmt0 = ShAmt0.getOperand(0); 15006 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 15007 ShAmt1 = ShAmt1.getOperand(0); 15008 15009 DebugLoc DL = N->getDebugLoc(); 15010 unsigned Opc = X86ISD::SHLD; 15011 SDValue Op0 = N0.getOperand(0); 15012 SDValue Op1 = N1.getOperand(0); 15013 if (ShAmt0.getOpcode() == ISD::SUB) { 15014 Opc = X86ISD::SHRD; 15015 std::swap(Op0, Op1); 15016 std::swap(ShAmt0, ShAmt1); 15017 } 15018 15019 unsigned Bits = VT.getSizeInBits(); 15020 if (ShAmt1.getOpcode() == ISD::SUB) { 15021 SDValue Sum = ShAmt1.getOperand(0); 15022 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 15023 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 15024 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 15025 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 15026 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 15027 return DAG.getNode(Opc, DL, VT, 15028 Op0, Op1, 15029 DAG.getNode(ISD::TRUNCATE, DL, 15030 MVT::i8, ShAmt0)); 15031 } 15032 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 15033 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 15034 if (ShAmt0C && 15035 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 15036 return DAG.getNode(Opc, DL, VT, 15037 N0.getOperand(0), N1.getOperand(0), 15038 DAG.getNode(ISD::TRUNCATE, DL, 15039 MVT::i8, ShAmt0)); 15040 } 15041 15042 return SDValue(); 15043} 15044 15045// Generate NEG and CMOV for integer abs. 15046static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 15047 EVT VT = N->getValueType(0); 15048 15049 // Since X86 does not have CMOV for 8-bit integer, we don't convert 15050 // 8-bit integer abs to NEG and CMOV. 15051 if (VT.isInteger() && VT.getSizeInBits() == 8) 15052 return SDValue(); 15053 15054 SDValue N0 = N->getOperand(0); 15055 SDValue N1 = N->getOperand(1); 15056 DebugLoc DL = N->getDebugLoc(); 15057 15058 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 15059 // and change it to SUB and CMOV. 15060 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 15061 N0.getOpcode() == ISD::ADD && 15062 N0.getOperand(1) == N1 && 15063 N1.getOpcode() == ISD::SRA && 15064 N1.getOperand(0) == N0.getOperand(0)) 15065 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 15066 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { 15067 // Generate SUB & CMOV. 15068 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32), 15069 DAG.getConstant(0, VT), N0.getOperand(0)); 15070 15071 SDValue Ops[] = { N0.getOperand(0), Neg, 15072 DAG.getConstant(X86::COND_GE, MVT::i8), 15073 SDValue(Neg.getNode(), 1) }; 15074 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), 15075 Ops, array_lengthof(Ops)); 15076 } 15077 return SDValue(); 15078} 15079 15080// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 15081static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 15082 TargetLowering::DAGCombinerInfo &DCI, 15083 const X86Subtarget *Subtarget) { 15084 if (DCI.isBeforeLegalizeOps()) 15085 return SDValue(); 15086 15087 if (Subtarget->hasCMov()) { 15088 SDValue RV = performIntegerAbsCombine(N, DAG); 15089 if (RV.getNode()) 15090 return RV; 15091 } 15092 15093 // Try forming BMI if it is available. 15094 if (!Subtarget->hasBMI()) 15095 return SDValue(); 15096 15097 EVT VT = N->getValueType(0); 15098 15099 if (VT != MVT::i32 && VT != MVT::i64) 15100 return SDValue(); 15101 15102 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 15103 15104 // Create BLSMSK instructions by finding X ^ (X-1) 15105 SDValue N0 = N->getOperand(0); 15106 SDValue N1 = N->getOperand(1); 15107 DebugLoc DL = N->getDebugLoc(); 15108 15109 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 15110 isAllOnes(N0.getOperand(1))) 15111 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 15112 15113 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 15114 isAllOnes(N1.getOperand(1))) 15115 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 15116 15117 return SDValue(); 15118} 15119 15120/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 15121static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 15122 TargetLowering::DAGCombinerInfo &DCI, 15123 const X86Subtarget *Subtarget) { 15124 LoadSDNode *Ld = cast<LoadSDNode>(N); 15125 EVT RegVT = Ld->getValueType(0); 15126 EVT MemVT = Ld->getMemoryVT(); 15127 DebugLoc dl = Ld->getDebugLoc(); 15128 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15129 15130 ISD::LoadExtType Ext = Ld->getExtensionType(); 15131 15132 // If this is a vector EXT Load then attempt to optimize it using a 15133 // shuffle. We need SSE4 for the shuffles. 15134 // TODO: It is possible to support ZExt by zeroing the undef values 15135 // during the shuffle phase or after the shuffle. 15136 if (RegVT.isVector() && RegVT.isInteger() && 15137 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 15138 assert(MemVT != RegVT && "Cannot extend to the same type"); 15139 assert(MemVT.isVector() && "Must load a vector from memory"); 15140 15141 unsigned NumElems = RegVT.getVectorNumElements(); 15142 unsigned RegSz = RegVT.getSizeInBits(); 15143 unsigned MemSz = MemVT.getSizeInBits(); 15144 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 15145 15146 // All sizes must be a power of two. 15147 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) 15148 return SDValue(); 15149 15150 // Attempt to load the original value using scalar loads. 15151 // Find the largest scalar type that divides the total loaded size. 15152 MVT SclrLoadTy = MVT::i8; 15153 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 15154 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 15155 MVT Tp = (MVT::SimpleValueType)tp; 15156 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { 15157 SclrLoadTy = Tp; 15158 } 15159 } 15160 15161 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 15162 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && 15163 (64 <= MemSz)) 15164 SclrLoadTy = MVT::f64; 15165 15166 // Calculate the number of scalar loads that we need to perform 15167 // in order to load our vector from memory. 15168 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); 15169 15170 // Represent our vector as a sequence of elements which are the 15171 // largest scalar that we can load. 15172 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 15173 RegSz/SclrLoadTy.getSizeInBits()); 15174 15175 // Represent the data using the same element type that is stored in 15176 // memory. In practice, we ''widen'' MemVT. 15177 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 15178 RegSz/MemVT.getScalarType().getSizeInBits()); 15179 15180 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && 15181 "Invalid vector type"); 15182 15183 // We can't shuffle using an illegal type. 15184 if (!TLI.isTypeLegal(WideVecVT)) 15185 return SDValue(); 15186 15187 SmallVector<SDValue, 8> Chains; 15188 SDValue Ptr = Ld->getBasePtr(); 15189 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8, 15190 TLI.getPointerTy()); 15191 SDValue Res = DAG.getUNDEF(LoadUnitVecVT); 15192 15193 for (unsigned i = 0; i < NumLoads; ++i) { 15194 // Perform a single load. 15195 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 15196 Ptr, Ld->getPointerInfo(), 15197 Ld->isVolatile(), Ld->isNonTemporal(), 15198 Ld->isInvariant(), Ld->getAlignment()); 15199 Chains.push_back(ScalarLoad.getValue(1)); 15200 // Create the first element type using SCALAR_TO_VECTOR in order to avoid 15201 // another round of DAGCombining. 15202 if (i == 0) 15203 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad); 15204 else 15205 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res, 15206 ScalarLoad, DAG.getIntPtrConstant(i)); 15207 15208 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 15209 } 15210 15211 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 15212 Chains.size()); 15213 15214 // Bitcast the loaded value to a vector of the original element type, in 15215 // the size of the target vector type. 15216 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res); 15217 unsigned SizeRatio = RegSz/MemSz; 15218 15219 // Redistribute the loaded elements into the different locations. 15220 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 15221 for (unsigned i = 0; i != NumElems; ++i) 15222 ShuffleVec[i*SizeRatio] = i; 15223 15224 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 15225 DAG.getUNDEF(WideVecVT), 15226 &ShuffleVec[0]); 15227 15228 // Bitcast to the requested type. 15229 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 15230 // Replace the original load with the new sequence 15231 // and return the new chain. 15232 return DCI.CombineTo(N, Shuff, TF, true); 15233 } 15234 15235 return SDValue(); 15236} 15237 15238/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 15239static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 15240 const X86Subtarget *Subtarget) { 15241 StoreSDNode *St = cast<StoreSDNode>(N); 15242 EVT VT = St->getValue().getValueType(); 15243 EVT StVT = St->getMemoryVT(); 15244 DebugLoc dl = St->getDebugLoc(); 15245 SDValue StoredVal = St->getOperand(1); 15246 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15247 15248 // If we are saving a concatenation of two XMM registers, perform two stores. 15249 // On Sandy Bridge, 256-bit memory operations are executed by two 15250 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit 15251 // memory operation. 15252 if (VT.is256BitVector() && !Subtarget->hasAVX2() && 15253 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 15254 StoredVal.getNumOperands() == 2) { 15255 SDValue Value0 = StoredVal.getOperand(0); 15256 SDValue Value1 = StoredVal.getOperand(1); 15257 15258 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 15259 SDValue Ptr0 = St->getBasePtr(); 15260 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 15261 15262 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 15263 St->getPointerInfo(), St->isVolatile(), 15264 St->isNonTemporal(), St->getAlignment()); 15265 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 15266 St->getPointerInfo(), St->isVolatile(), 15267 St->isNonTemporal(), St->getAlignment()); 15268 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 15269 } 15270 15271 // Optimize trunc store (of multiple scalars) to shuffle and store. 15272 // First, pack all of the elements in one place. Next, store to memory 15273 // in fewer chunks. 15274 if (St->isTruncatingStore() && VT.isVector()) { 15275 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15276 unsigned NumElems = VT.getVectorNumElements(); 15277 assert(StVT != VT && "Cannot truncate to the same type"); 15278 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 15279 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 15280 15281 // From, To sizes and ElemCount must be pow of two 15282 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 15283 // We are going to use the original vector elt for storing. 15284 // Accumulated smaller vector elements must be a multiple of the store size. 15285 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 15286 15287 unsigned SizeRatio = FromSz / ToSz; 15288 15289 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 15290 15291 // Create a type on which we perform the shuffle 15292 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 15293 StVT.getScalarType(), NumElems*SizeRatio); 15294 15295 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 15296 15297 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 15298 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 15299 for (unsigned i = 0; i != NumElems; ++i) 15300 ShuffleVec[i] = i * SizeRatio; 15301 15302 // Can't shuffle using an illegal type. 15303 if (!TLI.isTypeLegal(WideVecVT)) 15304 return SDValue(); 15305 15306 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 15307 DAG.getUNDEF(WideVecVT), 15308 &ShuffleVec[0]); 15309 // At this point all of the data is stored at the bottom of the 15310 // register. We now need to save it to mem. 15311 15312 // Find the largest store unit 15313 MVT StoreType = MVT::i8; 15314 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 15315 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 15316 MVT Tp = (MVT::SimpleValueType)tp; 15317 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) 15318 StoreType = Tp; 15319 } 15320 15321 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 15322 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && 15323 (64 <= NumElems * ToSz)) 15324 StoreType = MVT::f64; 15325 15326 // Bitcast the original vector into a vector of store-size units 15327 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 15328 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); 15329 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 15330 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 15331 SmallVector<SDValue, 8> Chains; 15332 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 15333 TLI.getPointerTy()); 15334 SDValue Ptr = St->getBasePtr(); 15335 15336 // Perform one or more big stores into memory. 15337 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 15338 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 15339 StoreType, ShuffWide, 15340 DAG.getIntPtrConstant(i)); 15341 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 15342 St->getPointerInfo(), St->isVolatile(), 15343 St->isNonTemporal(), St->getAlignment()); 15344 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 15345 Chains.push_back(Ch); 15346 } 15347 15348 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 15349 Chains.size()); 15350 } 15351 15352 15353 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 15354 // the FP state in cases where an emms may be missing. 15355 // A preferable solution to the general problem is to figure out the right 15356 // places to insert EMMS. This qualifies as a quick hack. 15357 15358 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 15359 if (VT.getSizeInBits() != 64) 15360 return SDValue(); 15361 15362 const Function *F = DAG.getMachineFunction().getFunction(); 15363 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 15364 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 15365 && Subtarget->hasSSE2(); 15366 if ((VT.isVector() || 15367 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 15368 isa<LoadSDNode>(St->getValue()) && 15369 !cast<LoadSDNode>(St->getValue())->isVolatile() && 15370 St->getChain().hasOneUse() && !St->isVolatile()) { 15371 SDNode* LdVal = St->getValue().getNode(); 15372 LoadSDNode *Ld = 0; 15373 int TokenFactorIndex = -1; 15374 SmallVector<SDValue, 8> Ops; 15375 SDNode* ChainVal = St->getChain().getNode(); 15376 // Must be a store of a load. We currently handle two cases: the load 15377 // is a direct child, and it's under an intervening TokenFactor. It is 15378 // possible to dig deeper under nested TokenFactors. 15379 if (ChainVal == LdVal) 15380 Ld = cast<LoadSDNode>(St->getChain()); 15381 else if (St->getValue().hasOneUse() && 15382 ChainVal->getOpcode() == ISD::TokenFactor) { 15383 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 15384 if (ChainVal->getOperand(i).getNode() == LdVal) { 15385 TokenFactorIndex = i; 15386 Ld = cast<LoadSDNode>(St->getValue()); 15387 } else 15388 Ops.push_back(ChainVal->getOperand(i)); 15389 } 15390 } 15391 15392 if (!Ld || !ISD::isNormalLoad(Ld)) 15393 return SDValue(); 15394 15395 // If this is not the MMX case, i.e. we are just turning i64 load/store 15396 // into f64 load/store, avoid the transformation if there are multiple 15397 // uses of the loaded value. 15398 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 15399 return SDValue(); 15400 15401 DebugLoc LdDL = Ld->getDebugLoc(); 15402 DebugLoc StDL = N->getDebugLoc(); 15403 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 15404 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 15405 // pair instead. 15406 if (Subtarget->is64Bit() || F64IsLegal) { 15407 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 15408 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 15409 Ld->getPointerInfo(), Ld->isVolatile(), 15410 Ld->isNonTemporal(), Ld->isInvariant(), 15411 Ld->getAlignment()); 15412 SDValue NewChain = NewLd.getValue(1); 15413 if (TokenFactorIndex != -1) { 15414 Ops.push_back(NewChain); 15415 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 15416 Ops.size()); 15417 } 15418 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 15419 St->getPointerInfo(), 15420 St->isVolatile(), St->isNonTemporal(), 15421 St->getAlignment()); 15422 } 15423 15424 // Otherwise, lower to two pairs of 32-bit loads / stores. 15425 SDValue LoAddr = Ld->getBasePtr(); 15426 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 15427 DAG.getConstant(4, MVT::i32)); 15428 15429 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 15430 Ld->getPointerInfo(), 15431 Ld->isVolatile(), Ld->isNonTemporal(), 15432 Ld->isInvariant(), Ld->getAlignment()); 15433 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 15434 Ld->getPointerInfo().getWithOffset(4), 15435 Ld->isVolatile(), Ld->isNonTemporal(), 15436 Ld->isInvariant(), 15437 MinAlign(Ld->getAlignment(), 4)); 15438 15439 SDValue NewChain = LoLd.getValue(1); 15440 if (TokenFactorIndex != -1) { 15441 Ops.push_back(LoLd); 15442 Ops.push_back(HiLd); 15443 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 15444 Ops.size()); 15445 } 15446 15447 LoAddr = St->getBasePtr(); 15448 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 15449 DAG.getConstant(4, MVT::i32)); 15450 15451 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 15452 St->getPointerInfo(), 15453 St->isVolatile(), St->isNonTemporal(), 15454 St->getAlignment()); 15455 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 15456 St->getPointerInfo().getWithOffset(4), 15457 St->isVolatile(), 15458 St->isNonTemporal(), 15459 MinAlign(St->getAlignment(), 4)); 15460 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 15461 } 15462 return SDValue(); 15463} 15464 15465/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 15466/// and return the operands for the horizontal operation in LHS and RHS. A 15467/// horizontal operation performs the binary operation on successive elements 15468/// of its first operand, then on successive elements of its second operand, 15469/// returning the resulting values in a vector. For example, if 15470/// A = < float a0, float a1, float a2, float a3 > 15471/// and 15472/// B = < float b0, float b1, float b2, float b3 > 15473/// then the result of doing a horizontal operation on A and B is 15474/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 15475/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 15476/// A horizontal-op B, for some already available A and B, and if so then LHS is 15477/// set to A, RHS to B, and the routine returns 'true'. 15478/// Note that the binary operation should have the property that if one of the 15479/// operands is UNDEF then the result is UNDEF. 15480static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 15481 // Look for the following pattern: if 15482 // A = < float a0, float a1, float a2, float a3 > 15483 // B = < float b0, float b1, float b2, float b3 > 15484 // and 15485 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 15486 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 15487 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 15488 // which is A horizontal-op B. 15489 15490 // At least one of the operands should be a vector shuffle. 15491 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 15492 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 15493 return false; 15494 15495 EVT VT = LHS.getValueType(); 15496 15497 assert((VT.is128BitVector() || VT.is256BitVector()) && 15498 "Unsupported vector type for horizontal add/sub"); 15499 15500 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 15501 // operate independently on 128-bit lanes. 15502 unsigned NumElts = VT.getVectorNumElements(); 15503 unsigned NumLanes = VT.getSizeInBits()/128; 15504 unsigned NumLaneElts = NumElts / NumLanes; 15505 assert((NumLaneElts % 2 == 0) && 15506 "Vector type should have an even number of elements in each lane"); 15507 unsigned HalfLaneElts = NumLaneElts/2; 15508 15509 // View LHS in the form 15510 // LHS = VECTOR_SHUFFLE A, B, LMask 15511 // If LHS is not a shuffle then pretend it is the shuffle 15512 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 15513 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 15514 // type VT. 15515 SDValue A, B; 15516 SmallVector<int, 16> LMask(NumElts); 15517 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 15518 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 15519 A = LHS.getOperand(0); 15520 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 15521 B = LHS.getOperand(1); 15522 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 15523 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 15524 } else { 15525 if (LHS.getOpcode() != ISD::UNDEF) 15526 A = LHS; 15527 for (unsigned i = 0; i != NumElts; ++i) 15528 LMask[i] = i; 15529 } 15530 15531 // Likewise, view RHS in the form 15532 // RHS = VECTOR_SHUFFLE C, D, RMask 15533 SDValue C, D; 15534 SmallVector<int, 16> RMask(NumElts); 15535 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 15536 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 15537 C = RHS.getOperand(0); 15538 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 15539 D = RHS.getOperand(1); 15540 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 15541 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 15542 } else { 15543 if (RHS.getOpcode() != ISD::UNDEF) 15544 C = RHS; 15545 for (unsigned i = 0; i != NumElts; ++i) 15546 RMask[i] = i; 15547 } 15548 15549 // Check that the shuffles are both shuffling the same vectors. 15550 if (!(A == C && B == D) && !(A == D && B == C)) 15551 return false; 15552 15553 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 15554 if (!A.getNode() && !B.getNode()) 15555 return false; 15556 15557 // If A and B occur in reverse order in RHS, then "swap" them (which means 15558 // rewriting the mask). 15559 if (A != C) 15560 CommuteVectorShuffleMask(RMask, NumElts); 15561 15562 // At this point LHS and RHS are equivalent to 15563 // LHS = VECTOR_SHUFFLE A, B, LMask 15564 // RHS = VECTOR_SHUFFLE A, B, RMask 15565 // Check that the masks correspond to performing a horizontal operation. 15566 for (unsigned i = 0; i != NumElts; ++i) { 15567 int LIdx = LMask[i], RIdx = RMask[i]; 15568 15569 // Ignore any UNDEF components. 15570 if (LIdx < 0 || RIdx < 0 || 15571 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 15572 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 15573 continue; 15574 15575 // Check that successive elements are being operated on. If not, this is 15576 // not a horizontal operation. 15577 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 15578 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 15579 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 15580 if (!(LIdx == Index && RIdx == Index + 1) && 15581 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 15582 return false; 15583 } 15584 15585 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 15586 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 15587 return true; 15588} 15589 15590/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 15591static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 15592 const X86Subtarget *Subtarget) { 15593 EVT VT = N->getValueType(0); 15594 SDValue LHS = N->getOperand(0); 15595 SDValue RHS = N->getOperand(1); 15596 15597 // Try to synthesize horizontal adds from adds of shuffles. 15598 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 15599 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 15600 isHorizontalBinOp(LHS, RHS, true)) 15601 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 15602 return SDValue(); 15603} 15604 15605/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 15606static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 15607 const X86Subtarget *Subtarget) { 15608 EVT VT = N->getValueType(0); 15609 SDValue LHS = N->getOperand(0); 15610 SDValue RHS = N->getOperand(1); 15611 15612 // Try to synthesize horizontal subs from subs of shuffles. 15613 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 15614 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 15615 isHorizontalBinOp(LHS, RHS, false)) 15616 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 15617 return SDValue(); 15618} 15619 15620/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 15621/// X86ISD::FXOR nodes. 15622static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 15623 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 15624 // F[X]OR(0.0, x) -> x 15625 // F[X]OR(x, 0.0) -> x 15626 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 15627 if (C->getValueAPF().isPosZero()) 15628 return N->getOperand(1); 15629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 15630 if (C->getValueAPF().isPosZero()) 15631 return N->getOperand(0); 15632 return SDValue(); 15633} 15634 15635/// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and 15636/// X86ISD::FMAX nodes. 15637static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) { 15638 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); 15639 15640 // Only perform optimizations if UnsafeMath is used. 15641 if (!DAG.getTarget().Options.UnsafeFPMath) 15642 return SDValue(); 15643 15644 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes 15645 // into FMINC and FMAXC, which are Commutative operations. 15646 unsigned NewOp = 0; 15647 switch (N->getOpcode()) { 15648 default: llvm_unreachable("unknown opcode"); 15649 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; 15650 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break; 15651 } 15652 15653 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0), 15654 N->getOperand(0), N->getOperand(1)); 15655} 15656 15657 15658/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 15659static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 15660 // FAND(0.0, x) -> 0.0 15661 // FAND(x, 0.0) -> 0.0 15662 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 15663 if (C->getValueAPF().isPosZero()) 15664 return N->getOperand(0); 15665 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 15666 if (C->getValueAPF().isPosZero()) 15667 return N->getOperand(1); 15668 return SDValue(); 15669} 15670 15671static SDValue PerformBTCombine(SDNode *N, 15672 SelectionDAG &DAG, 15673 TargetLowering::DAGCombinerInfo &DCI) { 15674 // BT ignores high bits in the bit index operand. 15675 SDValue Op1 = N->getOperand(1); 15676 if (Op1.hasOneUse()) { 15677 unsigned BitWidth = Op1.getValueSizeInBits(); 15678 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 15679 APInt KnownZero, KnownOne; 15680 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 15681 !DCI.isBeforeLegalizeOps()); 15682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15683 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 15684 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 15685 DCI.CommitTargetLoweringOpt(TLO); 15686 } 15687 return SDValue(); 15688} 15689 15690static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 15691 SDValue Op = N->getOperand(0); 15692 if (Op.getOpcode() == ISD::BITCAST) 15693 Op = Op.getOperand(0); 15694 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 15695 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 15696 VT.getVectorElementType().getSizeInBits() == 15697 OpVT.getVectorElementType().getSizeInBits()) { 15698 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 15699 } 15700 return SDValue(); 15701} 15702 15703static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 15704 TargetLowering::DAGCombinerInfo &DCI, 15705 const X86Subtarget *Subtarget) { 15706 if (!DCI.isBeforeLegalizeOps()) 15707 return SDValue(); 15708 15709 if (!Subtarget->hasAVX()) 15710 return SDValue(); 15711 15712 EVT VT = N->getValueType(0); 15713 SDValue Op = N->getOperand(0); 15714 EVT OpVT = Op.getValueType(); 15715 DebugLoc dl = N->getDebugLoc(); 15716 15717 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 15718 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 15719 15720 if (Subtarget->hasAVX2()) 15721 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); 15722 15723 // Optimize vectors in AVX mode 15724 // Sign extend v8i16 to v8i32 and 15725 // v4i32 to v4i64 15726 // 15727 // Divide input vector into two parts 15728 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 15729 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 15730 // concat the vectors to original VT 15731 15732 unsigned NumElems = OpVT.getVectorNumElements(); 15733 SDValue Undef = DAG.getUNDEF(OpVT); 15734 15735 SmallVector<int,8> ShufMask1(NumElems, -1); 15736 for (unsigned i = 0; i != NumElems/2; ++i) 15737 ShufMask1[i] = i; 15738 15739 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]); 15740 15741 SmallVector<int,8> ShufMask2(NumElems, -1); 15742 for (unsigned i = 0; i != NumElems/2; ++i) 15743 ShufMask2[i] = i + NumElems/2; 15744 15745 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]); 15746 15747 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 15748 VT.getVectorNumElements()/2); 15749 15750 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 15751 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 15752 15753 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15754 } 15755 return SDValue(); 15756} 15757 15758static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, 15759 const X86Subtarget* Subtarget) { 15760 DebugLoc dl = N->getDebugLoc(); 15761 EVT VT = N->getValueType(0); 15762 15763 // Let legalize expand this if it isn't a legal type yet. 15764 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 15765 return SDValue(); 15766 15767 EVT ScalarVT = VT.getScalarType(); 15768 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || 15769 (!Subtarget->hasFMA() && !Subtarget->hasFMA4())) 15770 return SDValue(); 15771 15772 SDValue A = N->getOperand(0); 15773 SDValue B = N->getOperand(1); 15774 SDValue C = N->getOperand(2); 15775 15776 bool NegA = (A.getOpcode() == ISD::FNEG); 15777 bool NegB = (B.getOpcode() == ISD::FNEG); 15778 bool NegC = (C.getOpcode() == ISD::FNEG); 15779 15780 // Negative multiplication when NegA xor NegB 15781 bool NegMul = (NegA != NegB); 15782 if (NegA) 15783 A = A.getOperand(0); 15784 if (NegB) 15785 B = B.getOperand(0); 15786 if (NegC) 15787 C = C.getOperand(0); 15788 15789 unsigned Opcode; 15790 if (!NegMul) 15791 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; 15792 else 15793 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; 15794 15795 return DAG.getNode(Opcode, dl, VT, A, B, C); 15796} 15797 15798static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 15799 TargetLowering::DAGCombinerInfo &DCI, 15800 const X86Subtarget *Subtarget) { 15801 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 15802 // (and (i32 x86isd::setcc_carry), 1) 15803 // This eliminates the zext. This transformation is necessary because 15804 // ISD::SETCC is always legalized to i8. 15805 DebugLoc dl = N->getDebugLoc(); 15806 SDValue N0 = N->getOperand(0); 15807 EVT VT = N->getValueType(0); 15808 EVT OpVT = N0.getValueType(); 15809 15810 if (N0.getOpcode() == ISD::AND && 15811 N0.hasOneUse() && 15812 N0.getOperand(0).hasOneUse()) { 15813 SDValue N00 = N0.getOperand(0); 15814 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 15815 return SDValue(); 15816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 15817 if (!C || C->getZExtValue() != 1) 15818 return SDValue(); 15819 return DAG.getNode(ISD::AND, dl, VT, 15820 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 15821 N00.getOperand(0), N00.getOperand(1)), 15822 DAG.getConstant(1, VT)); 15823 } 15824 15825 // Optimize vectors in AVX mode: 15826 // 15827 // v8i16 -> v8i32 15828 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 15829 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 15830 // Concat upper and lower parts. 15831 // 15832 // v4i32 -> v4i64 15833 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 15834 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 15835 // Concat upper and lower parts. 15836 // 15837 if (!DCI.isBeforeLegalizeOps()) 15838 return SDValue(); 15839 15840 if (!Subtarget->hasAVX()) 15841 return SDValue(); 15842 15843 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 15844 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 15845 15846 if (Subtarget->hasAVX2()) 15847 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0); 15848 15849 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 15850 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec); 15851 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec); 15852 15853 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 15854 VT.getVectorNumElements()/2); 15855 15856 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 15857 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 15858 15859 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15860 } 15861 15862 return SDValue(); 15863} 15864 15865// Optimize x == -y --> x+y == 0 15866// x != -y --> x+y != 0 15867static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15868 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 15869 SDValue LHS = N->getOperand(0); 15870 SDValue RHS = N->getOperand(1); 15871 15872 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 15873 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 15874 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 15875 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15876 LHS.getValueType(), RHS, LHS.getOperand(1)); 15877 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15878 addV, DAG.getConstant(0, addV.getValueType()), CC); 15879 } 15880 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 15881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 15882 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 15883 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15884 RHS.getValueType(), LHS, RHS.getOperand(1)); 15885 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15886 addV, DAG.getConstant(0, addV.getValueType()), CC); 15887 } 15888 return SDValue(); 15889} 15890 15891// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 15892static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, 15893 TargetLowering::DAGCombinerInfo &DCI, 15894 const X86Subtarget *Subtarget) { 15895 DebugLoc DL = N->getDebugLoc(); 15896 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0)); 15897 SDValue EFLAGS = N->getOperand(1); 15898 15899 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 15900 // a zext and produces an all-ones bit which is more useful than 0/1 in some 15901 // cases. 15902 if (CC == X86::COND_B) 15903 return DAG.getNode(ISD::AND, DL, MVT::i8, 15904 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 15905 DAG.getConstant(CC, MVT::i8), EFLAGS), 15906 DAG.getConstant(1, MVT::i8)); 15907 15908 SDValue Flags; 15909 15910 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 15911 if (Flags.getNode()) { 15912 SDValue Cond = DAG.getConstant(CC, MVT::i8); 15913 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); 15914 } 15915 15916 return SDValue(); 15917} 15918 15919// Optimize branch condition evaluation. 15920// 15921static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, 15922 TargetLowering::DAGCombinerInfo &DCI, 15923 const X86Subtarget *Subtarget) { 15924 DebugLoc DL = N->getDebugLoc(); 15925 SDValue Chain = N->getOperand(0); 15926 SDValue Dest = N->getOperand(1); 15927 SDValue EFLAGS = N->getOperand(3); 15928 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2)); 15929 15930 SDValue Flags; 15931 15932 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 15933 if (Flags.getNode()) { 15934 SDValue Cond = DAG.getConstant(CC, MVT::i8); 15935 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond, 15936 Flags); 15937 } 15938 15939 return SDValue(); 15940} 15941 15942static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) { 15943 SDValue Op0 = N->getOperand(0); 15944 EVT InVT = Op0->getValueType(0); 15945 15946 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15947 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15948 DebugLoc dl = N->getDebugLoc(); 15949 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15950 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); 15951 // Notice that we use SINT_TO_FP because we know that the high bits 15952 // are zero and SINT_TO_FP is better supported by the hardware. 15953 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15954 } 15955 15956 return SDValue(); 15957} 15958 15959static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 15960 const X86TargetLowering *XTLI) { 15961 SDValue Op0 = N->getOperand(0); 15962 EVT InVT = Op0->getValueType(0); 15963 15964 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15965 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15966 DebugLoc dl = N->getDebugLoc(); 15967 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15968 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 15969 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15970 } 15971 15972 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 15973 // a 32-bit target where SSE doesn't support i64->FP operations. 15974 if (Op0.getOpcode() == ISD::LOAD) { 15975 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 15976 EVT VT = Ld->getValueType(0); 15977 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 15978 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 15979 !XTLI->getSubtarget()->is64Bit() && 15980 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 15981 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 15982 Ld->getChain(), Op0, DAG); 15983 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 15984 return FILDChain; 15985 } 15986 } 15987 return SDValue(); 15988} 15989 15990static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) { 15991 EVT VT = N->getValueType(0); 15992 15993 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() 15994 if (VT == MVT::v8i8 || VT == MVT::v4i8) { 15995 DebugLoc dl = N->getDebugLoc(); 15996 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15997 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); 15998 return DAG.getNode(ISD::TRUNCATE, dl, VT, I); 15999 } 16000 16001 return SDValue(); 16002} 16003 16004// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 16005static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 16006 X86TargetLowering::DAGCombinerInfo &DCI) { 16007 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 16008 // the result is either zero or one (depending on the input carry bit). 16009 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 16010 if (X86::isZeroNode(N->getOperand(0)) && 16011 X86::isZeroNode(N->getOperand(1)) && 16012 // We don't have a good way to replace an EFLAGS use, so only do this when 16013 // dead right now. 16014 SDValue(N, 1).use_empty()) { 16015 DebugLoc DL = N->getDebugLoc(); 16016 EVT VT = N->getValueType(0); 16017 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 16018 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 16019 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 16020 DAG.getConstant(X86::COND_B,MVT::i8), 16021 N->getOperand(2)), 16022 DAG.getConstant(1, VT)); 16023 return DCI.CombineTo(N, Res1, CarryOut); 16024 } 16025 16026 return SDValue(); 16027} 16028 16029// fold (add Y, (sete X, 0)) -> adc 0, Y 16030// (add Y, (setne X, 0)) -> sbb -1, Y 16031// (sub (sete X, 0), Y) -> sbb 0, Y 16032// (sub (setne X, 0), Y) -> adc -1, Y 16033static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 16034 DebugLoc DL = N->getDebugLoc(); 16035 16036 // Look through ZExts. 16037 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 16038 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 16039 return SDValue(); 16040 16041 SDValue SetCC = Ext.getOperand(0); 16042 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 16043 return SDValue(); 16044 16045 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 16046 if (CC != X86::COND_E && CC != X86::COND_NE) 16047 return SDValue(); 16048 16049 SDValue Cmp = SetCC.getOperand(1); 16050 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 16051 !X86::isZeroNode(Cmp.getOperand(1)) || 16052 !Cmp.getOperand(0).getValueType().isInteger()) 16053 return SDValue(); 16054 16055 SDValue CmpOp0 = Cmp.getOperand(0); 16056 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 16057 DAG.getConstant(1, CmpOp0.getValueType())); 16058 16059 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 16060 if (CC == X86::COND_NE) 16061 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 16062 DL, OtherVal.getValueType(), OtherVal, 16063 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 16064 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 16065 DL, OtherVal.getValueType(), OtherVal, 16066 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 16067} 16068 16069/// PerformADDCombine - Do target-specific dag combines on integer adds. 16070static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 16071 const X86Subtarget *Subtarget) { 16072 EVT VT = N->getValueType(0); 16073 SDValue Op0 = N->getOperand(0); 16074 SDValue Op1 = N->getOperand(1); 16075 16076 // Try to synthesize horizontal adds from adds of shuffles. 16077 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 16078 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 16079 isHorizontalBinOp(Op0, Op1, true)) 16080 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 16081 16082 return OptimizeConditionalInDecrement(N, DAG); 16083} 16084 16085static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 16086 const X86Subtarget *Subtarget) { 16087 SDValue Op0 = N->getOperand(0); 16088 SDValue Op1 = N->getOperand(1); 16089 16090 // X86 can't encode an immediate LHS of a sub. See if we can push the 16091 // negation into a preceding instruction. 16092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 16093 // If the RHS of the sub is a XOR with one use and a constant, invert the 16094 // immediate. Then add one to the LHS of the sub so we can turn 16095 // X-Y -> X+~Y+1, saving one register. 16096 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 16097 isa<ConstantSDNode>(Op1.getOperand(1))) { 16098 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 16099 EVT VT = Op0.getValueType(); 16100 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 16101 Op1.getOperand(0), 16102 DAG.getConstant(~XorC, VT)); 16103 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 16104 DAG.getConstant(C->getAPIntValue()+1, VT)); 16105 } 16106 } 16107 16108 // Try to synthesize horizontal adds from adds of shuffles. 16109 EVT VT = N->getValueType(0); 16110 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 16111 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 16112 isHorizontalBinOp(Op0, Op1, true)) 16113 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 16114 16115 return OptimizeConditionalInDecrement(N, DAG); 16116} 16117 16118SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 16119 DAGCombinerInfo &DCI) const { 16120 SelectionDAG &DAG = DCI.DAG; 16121 switch (N->getOpcode()) { 16122 default: break; 16123 case ISD::EXTRACT_VECTOR_ELT: 16124 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 16125 case ISD::VSELECT: 16126 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 16127 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); 16128 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 16129 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 16130 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 16131 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 16132 case ISD::SHL: 16133 case ISD::SRA: 16134 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 16135 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 16136 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 16137 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 16138 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); 16139 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 16140 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG); 16141 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 16142 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG); 16143 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 16144 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 16145 case X86ISD::FXOR: 16146 case X86ISD::FOR: return PerformFORCombine(N, DAG); 16147 case X86ISD::FMIN: 16148 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG); 16149 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 16150 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 16151 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 16152 case ISD::ANY_EXTEND: 16153 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 16154 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 16155 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget); 16156 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 16157 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); 16158 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); 16159 case X86ISD::SHUFP: // Handle all target specific shuffles 16160 case X86ISD::PALIGN: 16161 case X86ISD::UNPCKH: 16162 case X86ISD::UNPCKL: 16163 case X86ISD::MOVHLPS: 16164 case X86ISD::MOVLHPS: 16165 case X86ISD::PSHUFD: 16166 case X86ISD::PSHUFHW: 16167 case X86ISD::PSHUFLW: 16168 case X86ISD::MOVSS: 16169 case X86ISD::MOVSD: 16170 case X86ISD::VPERMILP: 16171 case X86ISD::VPERM2X128: 16172 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 16173 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget); 16174 } 16175 16176 return SDValue(); 16177} 16178 16179/// isTypeDesirableForOp - Return true if the target has native support for 16180/// the specified value type and it is 'desirable' to use the type for the 16181/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 16182/// instruction encodings are longer and some i16 instructions are slow. 16183bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 16184 if (!isTypeLegal(VT)) 16185 return false; 16186 if (VT != MVT::i16) 16187 return true; 16188 16189 switch (Opc) { 16190 default: 16191 return true; 16192 case ISD::LOAD: 16193 case ISD::SIGN_EXTEND: 16194 case ISD::ZERO_EXTEND: 16195 case ISD::ANY_EXTEND: 16196 case ISD::SHL: 16197 case ISD::SRL: 16198 case ISD::SUB: 16199 case ISD::ADD: 16200 case ISD::MUL: 16201 case ISD::AND: 16202 case ISD::OR: 16203 case ISD::XOR: 16204 return false; 16205 } 16206} 16207 16208/// IsDesirableToPromoteOp - This method query the target whether it is 16209/// beneficial for dag combiner to promote the specified node. If true, it 16210/// should return the desired promotion type by reference. 16211bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 16212 EVT VT = Op.getValueType(); 16213 if (VT != MVT::i16) 16214 return false; 16215 16216 bool Promote = false; 16217 bool Commute = false; 16218 switch (Op.getOpcode()) { 16219 default: break; 16220 case ISD::LOAD: { 16221 LoadSDNode *LD = cast<LoadSDNode>(Op); 16222 // If the non-extending load has a single use and it's not live out, then it 16223 // might be folded. 16224 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 16225 Op.hasOneUse()*/) { 16226 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 16227 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 16228 // The only case where we'd want to promote LOAD (rather then it being 16229 // promoted as an operand is when it's only use is liveout. 16230 if (UI->getOpcode() != ISD::CopyToReg) 16231 return false; 16232 } 16233 } 16234 Promote = true; 16235 break; 16236 } 16237 case ISD::SIGN_EXTEND: 16238 case ISD::ZERO_EXTEND: 16239 case ISD::ANY_EXTEND: 16240 Promote = true; 16241 break; 16242 case ISD::SHL: 16243 case ISD::SRL: { 16244 SDValue N0 = Op.getOperand(0); 16245 // Look out for (store (shl (load), x)). 16246 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 16247 return false; 16248 Promote = true; 16249 break; 16250 } 16251 case ISD::ADD: 16252 case ISD::MUL: 16253 case ISD::AND: 16254 case ISD::OR: 16255 case ISD::XOR: 16256 Commute = true; 16257 // fallthrough 16258 case ISD::SUB: { 16259 SDValue N0 = Op.getOperand(0); 16260 SDValue N1 = Op.getOperand(1); 16261 if (!Commute && MayFoldLoad(N1)) 16262 return false; 16263 // Avoid disabling potential load folding opportunities. 16264 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 16265 return false; 16266 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 16267 return false; 16268 Promote = true; 16269 } 16270 } 16271 16272 PVT = MVT::i32; 16273 return Promote; 16274} 16275 16276//===----------------------------------------------------------------------===// 16277// X86 Inline Assembly Support 16278//===----------------------------------------------------------------------===// 16279 16280namespace { 16281 // Helper to match a string separated by whitespace. 16282 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 16283 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 16284 16285 for (unsigned i = 0, e = args.size(); i != e; ++i) { 16286 StringRef piece(*args[i]); 16287 if (!s.startswith(piece)) // Check if the piece matches. 16288 return false; 16289 16290 s = s.substr(piece.size()); 16291 StringRef::size_type pos = s.find_first_not_of(" \t"); 16292 if (pos == 0) // We matched a prefix. 16293 return false; 16294 16295 s = s.substr(pos); 16296 } 16297 16298 return s.empty(); 16299 } 16300 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 16301} 16302 16303bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 16304 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 16305 16306 std::string AsmStr = IA->getAsmString(); 16307 16308 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 16309 if (!Ty || Ty->getBitWidth() % 16 != 0) 16310 return false; 16311 16312 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 16313 SmallVector<StringRef, 4> AsmPieces; 16314 SplitString(AsmStr, AsmPieces, ";\n"); 16315 16316 switch (AsmPieces.size()) { 16317 default: return false; 16318 case 1: 16319 // FIXME: this should verify that we are targeting a 486 or better. If not, 16320 // we will turn this bswap into something that will be lowered to logical 16321 // ops instead of emitting the bswap asm. For now, we don't support 486 or 16322 // lower so don't worry about this. 16323 // bswap $0 16324 if (matchAsm(AsmPieces[0], "bswap", "$0") || 16325 matchAsm(AsmPieces[0], "bswapl", "$0") || 16326 matchAsm(AsmPieces[0], "bswapq", "$0") || 16327 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 16328 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 16329 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 16330 // No need to check constraints, nothing other than the equivalent of 16331 // "=r,0" would be valid here. 16332 return IntrinsicLowering::LowerToByteSwap(CI); 16333 } 16334 16335 // rorw $$8, ${0:w} --> llvm.bswap.i16 16336 if (CI->getType()->isIntegerTy(16) && 16337 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 16338 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 16339 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 16340 AsmPieces.clear(); 16341 const std::string &ConstraintsStr = IA->getConstraintString(); 16342 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 16343 std::sort(AsmPieces.begin(), AsmPieces.end()); 16344 if (AsmPieces.size() == 4 && 16345 AsmPieces[0] == "~{cc}" && 16346 AsmPieces[1] == "~{dirflag}" && 16347 AsmPieces[2] == "~{flags}" && 16348 AsmPieces[3] == "~{fpsr}") 16349 return IntrinsicLowering::LowerToByteSwap(CI); 16350 } 16351 break; 16352 case 3: 16353 if (CI->getType()->isIntegerTy(32) && 16354 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 16355 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 16356 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 16357 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 16358 AsmPieces.clear(); 16359 const std::string &ConstraintsStr = IA->getConstraintString(); 16360 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 16361 std::sort(AsmPieces.begin(), AsmPieces.end()); 16362 if (AsmPieces.size() == 4 && 16363 AsmPieces[0] == "~{cc}" && 16364 AsmPieces[1] == "~{dirflag}" && 16365 AsmPieces[2] == "~{flags}" && 16366 AsmPieces[3] == "~{fpsr}") 16367 return IntrinsicLowering::LowerToByteSwap(CI); 16368 } 16369 16370 if (CI->getType()->isIntegerTy(64)) { 16371 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 16372 if (Constraints.size() >= 2 && 16373 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 16374 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 16375 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 16376 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 16377 matchAsm(AsmPieces[1], "bswap", "%edx") && 16378 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 16379 return IntrinsicLowering::LowerToByteSwap(CI); 16380 } 16381 } 16382 break; 16383 } 16384 return false; 16385} 16386 16387 16388 16389/// getConstraintType - Given a constraint letter, return the type of 16390/// constraint it is for this target. 16391X86TargetLowering::ConstraintType 16392X86TargetLowering::getConstraintType(const std::string &Constraint) const { 16393 if (Constraint.size() == 1) { 16394 switch (Constraint[0]) { 16395 case 'R': 16396 case 'q': 16397 case 'Q': 16398 case 'f': 16399 case 't': 16400 case 'u': 16401 case 'y': 16402 case 'x': 16403 case 'Y': 16404 case 'l': 16405 return C_RegisterClass; 16406 case 'a': 16407 case 'b': 16408 case 'c': 16409 case 'd': 16410 case 'S': 16411 case 'D': 16412 case 'A': 16413 return C_Register; 16414 case 'I': 16415 case 'J': 16416 case 'K': 16417 case 'L': 16418 case 'M': 16419 case 'N': 16420 case 'G': 16421 case 'C': 16422 case 'e': 16423 case 'Z': 16424 return C_Other; 16425 default: 16426 break; 16427 } 16428 } 16429 return TargetLowering::getConstraintType(Constraint); 16430} 16431 16432/// Examine constraint type and operand type and determine a weight value. 16433/// This object must already have been set up with the operand type 16434/// and the current alternative constraint selected. 16435TargetLowering::ConstraintWeight 16436 X86TargetLowering::getSingleConstraintMatchWeight( 16437 AsmOperandInfo &info, const char *constraint) const { 16438 ConstraintWeight weight = CW_Invalid; 16439 Value *CallOperandVal = info.CallOperandVal; 16440 // If we don't have a value, we can't do a match, 16441 // but allow it at the lowest weight. 16442 if (CallOperandVal == NULL) 16443 return CW_Default; 16444 Type *type = CallOperandVal->getType(); 16445 // Look at the constraint type. 16446 switch (*constraint) { 16447 default: 16448 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 16449 case 'R': 16450 case 'q': 16451 case 'Q': 16452 case 'a': 16453 case 'b': 16454 case 'c': 16455 case 'd': 16456 case 'S': 16457 case 'D': 16458 case 'A': 16459 if (CallOperandVal->getType()->isIntegerTy()) 16460 weight = CW_SpecificReg; 16461 break; 16462 case 'f': 16463 case 't': 16464 case 'u': 16465 if (type->isFloatingPointTy()) 16466 weight = CW_SpecificReg; 16467 break; 16468 case 'y': 16469 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 16470 weight = CW_SpecificReg; 16471 break; 16472 case 'x': 16473 case 'Y': 16474 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 16475 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 16476 weight = CW_Register; 16477 break; 16478 case 'I': 16479 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 16480 if (C->getZExtValue() <= 31) 16481 weight = CW_Constant; 16482 } 16483 break; 16484 case 'J': 16485 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16486 if (C->getZExtValue() <= 63) 16487 weight = CW_Constant; 16488 } 16489 break; 16490 case 'K': 16491 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16492 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 16493 weight = CW_Constant; 16494 } 16495 break; 16496 case 'L': 16497 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16498 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 16499 weight = CW_Constant; 16500 } 16501 break; 16502 case 'M': 16503 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16504 if (C->getZExtValue() <= 3) 16505 weight = CW_Constant; 16506 } 16507 break; 16508 case 'N': 16509 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16510 if (C->getZExtValue() <= 0xff) 16511 weight = CW_Constant; 16512 } 16513 break; 16514 case 'G': 16515 case 'C': 16516 if (dyn_cast<ConstantFP>(CallOperandVal)) { 16517 weight = CW_Constant; 16518 } 16519 break; 16520 case 'e': 16521 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16522 if ((C->getSExtValue() >= -0x80000000LL) && 16523 (C->getSExtValue() <= 0x7fffffffLL)) 16524 weight = CW_Constant; 16525 } 16526 break; 16527 case 'Z': 16528 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 16529 if (C->getZExtValue() <= 0xffffffff) 16530 weight = CW_Constant; 16531 } 16532 break; 16533 } 16534 return weight; 16535} 16536 16537/// LowerXConstraint - try to replace an X constraint, which matches anything, 16538/// with another that has more specific requirements based on the type of the 16539/// corresponding operand. 16540const char *X86TargetLowering:: 16541LowerXConstraint(EVT ConstraintVT) const { 16542 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 16543 // 'f' like normal targets. 16544 if (ConstraintVT.isFloatingPoint()) { 16545 if (Subtarget->hasSSE2()) 16546 return "Y"; 16547 if (Subtarget->hasSSE1()) 16548 return "x"; 16549 } 16550 16551 return TargetLowering::LowerXConstraint(ConstraintVT); 16552} 16553 16554/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 16555/// vector. If it is invalid, don't add anything to Ops. 16556void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 16557 std::string &Constraint, 16558 std::vector<SDValue>&Ops, 16559 SelectionDAG &DAG) const { 16560 SDValue Result(0, 0); 16561 16562 // Only support length 1 constraints for now. 16563 if (Constraint.length() > 1) return; 16564 16565 char ConstraintLetter = Constraint[0]; 16566 switch (ConstraintLetter) { 16567 default: break; 16568 case 'I': 16569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16570 if (C->getZExtValue() <= 31) { 16571 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 16572 break; 16573 } 16574 } 16575 return; 16576 case 'J': 16577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16578 if (C->getZExtValue() <= 63) { 16579 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 16580 break; 16581 } 16582 } 16583 return; 16584 case 'K': 16585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16586 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 16587 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 16588 break; 16589 } 16590 } 16591 return; 16592 case 'N': 16593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16594 if (C->getZExtValue() <= 255) { 16595 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 16596 break; 16597 } 16598 } 16599 return; 16600 case 'e': { 16601 // 32-bit signed value 16602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16603 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 16604 C->getSExtValue())) { 16605 // Widen to 64 bits here to get it sign extended. 16606 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 16607 break; 16608 } 16609 // FIXME gcc accepts some relocatable values here too, but only in certain 16610 // memory models; it's complicated. 16611 } 16612 return; 16613 } 16614 case 'Z': { 16615 // 32-bit unsigned value 16616 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 16617 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 16618 C->getZExtValue())) { 16619 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 16620 break; 16621 } 16622 } 16623 // FIXME gcc accepts some relocatable values here too, but only in certain 16624 // memory models; it's complicated. 16625 return; 16626 } 16627 case 'i': { 16628 // Literal immediates are always ok. 16629 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 16630 // Widen to 64 bits here to get it sign extended. 16631 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 16632 break; 16633 } 16634 16635 // In any sort of PIC mode addresses need to be computed at runtime by 16636 // adding in a register or some sort of table lookup. These can't 16637 // be used as immediates. 16638 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 16639 return; 16640 16641 // If we are in non-pic codegen mode, we allow the address of a global (with 16642 // an optional displacement) to be used with 'i'. 16643 GlobalAddressSDNode *GA = 0; 16644 int64_t Offset = 0; 16645 16646 // Match either (GA), (GA+C), (GA+C1+C2), etc. 16647 while (1) { 16648 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 16649 Offset += GA->getOffset(); 16650 break; 16651 } else if (Op.getOpcode() == ISD::ADD) { 16652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 16653 Offset += C->getZExtValue(); 16654 Op = Op.getOperand(0); 16655 continue; 16656 } 16657 } else if (Op.getOpcode() == ISD::SUB) { 16658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 16659 Offset += -C->getZExtValue(); 16660 Op = Op.getOperand(0); 16661 continue; 16662 } 16663 } 16664 16665 // Otherwise, this isn't something we can handle, reject it. 16666 return; 16667 } 16668 16669 const GlobalValue *GV = GA->getGlobal(); 16670 // If we require an extra load to get this address, as in PIC mode, we 16671 // can't accept it. 16672 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 16673 getTargetMachine()))) 16674 return; 16675 16676 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 16677 GA->getValueType(0), Offset); 16678 break; 16679 } 16680 } 16681 16682 if (Result.getNode()) { 16683 Ops.push_back(Result); 16684 return; 16685 } 16686 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 16687} 16688 16689std::pair<unsigned, const TargetRegisterClass*> 16690X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 16691 EVT VT) const { 16692 // First, see if this is a constraint that directly corresponds to an LLVM 16693 // register class. 16694 if (Constraint.size() == 1) { 16695 // GCC Constraint Letters 16696 switch (Constraint[0]) { 16697 default: break; 16698 // TODO: Slight differences here in allocation order and leaving 16699 // RIP in the class. Do they matter any more here than they do 16700 // in the normal allocation? 16701 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 16702 if (Subtarget->is64Bit()) { 16703 if (VT == MVT::i32 || VT == MVT::f32) 16704 return std::make_pair(0U, &X86::GR32RegClass); 16705 if (VT == MVT::i16) 16706 return std::make_pair(0U, &X86::GR16RegClass); 16707 if (VT == MVT::i8 || VT == MVT::i1) 16708 return std::make_pair(0U, &X86::GR8RegClass); 16709 if (VT == MVT::i64 || VT == MVT::f64) 16710 return std::make_pair(0U, &X86::GR64RegClass); 16711 break; 16712 } 16713 // 32-bit fallthrough 16714 case 'Q': // Q_REGS 16715 if (VT == MVT::i32 || VT == MVT::f32) 16716 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 16717 if (VT == MVT::i16) 16718 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 16719 if (VT == MVT::i8 || VT == MVT::i1) 16720 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 16721 if (VT == MVT::i64) 16722 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 16723 break; 16724 case 'r': // GENERAL_REGS 16725 case 'l': // INDEX_REGS 16726 if (VT == MVT::i8 || VT == MVT::i1) 16727 return std::make_pair(0U, &X86::GR8RegClass); 16728 if (VT == MVT::i16) 16729 return std::make_pair(0U, &X86::GR16RegClass); 16730 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 16731 return std::make_pair(0U, &X86::GR32RegClass); 16732 return std::make_pair(0U, &X86::GR64RegClass); 16733 case 'R': // LEGACY_REGS 16734 if (VT == MVT::i8 || VT == MVT::i1) 16735 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 16736 if (VT == MVT::i16) 16737 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 16738 if (VT == MVT::i32 || !Subtarget->is64Bit()) 16739 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 16740 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 16741 case 'f': // FP Stack registers. 16742 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 16743 // value to the correct fpstack register class. 16744 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 16745 return std::make_pair(0U, &X86::RFP32RegClass); 16746 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 16747 return std::make_pair(0U, &X86::RFP64RegClass); 16748 return std::make_pair(0U, &X86::RFP80RegClass); 16749 case 'y': // MMX_REGS if MMX allowed. 16750 if (!Subtarget->hasMMX()) break; 16751 return std::make_pair(0U, &X86::VR64RegClass); 16752 case 'Y': // SSE_REGS if SSE2 allowed 16753 if (!Subtarget->hasSSE2()) break; 16754 // FALL THROUGH. 16755 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 16756 if (!Subtarget->hasSSE1()) break; 16757 16758 switch (VT.getSimpleVT().SimpleTy) { 16759 default: break; 16760 // Scalar SSE types. 16761 case MVT::f32: 16762 case MVT::i32: 16763 return std::make_pair(0U, &X86::FR32RegClass); 16764 case MVT::f64: 16765 case MVT::i64: 16766 return std::make_pair(0U, &X86::FR64RegClass); 16767 // Vector types. 16768 case MVT::v16i8: 16769 case MVT::v8i16: 16770 case MVT::v4i32: 16771 case MVT::v2i64: 16772 case MVT::v4f32: 16773 case MVT::v2f64: 16774 return std::make_pair(0U, &X86::VR128RegClass); 16775 // AVX types. 16776 case MVT::v32i8: 16777 case MVT::v16i16: 16778 case MVT::v8i32: 16779 case MVT::v4i64: 16780 case MVT::v8f32: 16781 case MVT::v4f64: 16782 return std::make_pair(0U, &X86::VR256RegClass); 16783 } 16784 break; 16785 } 16786 } 16787 16788 // Use the default implementation in TargetLowering to convert the register 16789 // constraint into a member of a register class. 16790 std::pair<unsigned, const TargetRegisterClass*> Res; 16791 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 16792 16793 // Not found as a standard register? 16794 if (Res.second == 0) { 16795 // Map st(0) -> st(7) -> ST0 16796 if (Constraint.size() == 7 && Constraint[0] == '{' && 16797 tolower(Constraint[1]) == 's' && 16798 tolower(Constraint[2]) == 't' && 16799 Constraint[3] == '(' && 16800 (Constraint[4] >= '0' && Constraint[4] <= '7') && 16801 Constraint[5] == ')' && 16802 Constraint[6] == '}') { 16803 16804 Res.first = X86::ST0+Constraint[4]-'0'; 16805 Res.second = &X86::RFP80RegClass; 16806 return Res; 16807 } 16808 16809 // GCC allows "st(0)" to be called just plain "st". 16810 if (StringRef("{st}").equals_lower(Constraint)) { 16811 Res.first = X86::ST0; 16812 Res.second = &X86::RFP80RegClass; 16813 return Res; 16814 } 16815 16816 // flags -> EFLAGS 16817 if (StringRef("{flags}").equals_lower(Constraint)) { 16818 Res.first = X86::EFLAGS; 16819 Res.second = &X86::CCRRegClass; 16820 return Res; 16821 } 16822 16823 // 'A' means EAX + EDX. 16824 if (Constraint == "A") { 16825 Res.first = X86::EAX; 16826 Res.second = &X86::GR32_ADRegClass; 16827 return Res; 16828 } 16829 return Res; 16830 } 16831 16832 // Otherwise, check to see if this is a register class of the wrong value 16833 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 16834 // turn into {ax},{dx}. 16835 if (Res.second->hasType(VT)) 16836 return Res; // Correct type already, nothing to do. 16837 16838 // All of the single-register GCC register classes map their values onto 16839 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 16840 // really want an 8-bit or 32-bit register, map to the appropriate register 16841 // class and return the appropriate register. 16842 if (Res.second == &X86::GR16RegClass) { 16843 if (VT == MVT::i8) { 16844 unsigned DestReg = 0; 16845 switch (Res.first) { 16846 default: break; 16847 case X86::AX: DestReg = X86::AL; break; 16848 case X86::DX: DestReg = X86::DL; break; 16849 case X86::CX: DestReg = X86::CL; break; 16850 case X86::BX: DestReg = X86::BL; break; 16851 } 16852 if (DestReg) { 16853 Res.first = DestReg; 16854 Res.second = &X86::GR8RegClass; 16855 } 16856 } else if (VT == MVT::i32) { 16857 unsigned DestReg = 0; 16858 switch (Res.first) { 16859 default: break; 16860 case X86::AX: DestReg = X86::EAX; break; 16861 case X86::DX: DestReg = X86::EDX; break; 16862 case X86::CX: DestReg = X86::ECX; break; 16863 case X86::BX: DestReg = X86::EBX; break; 16864 case X86::SI: DestReg = X86::ESI; break; 16865 case X86::DI: DestReg = X86::EDI; break; 16866 case X86::BP: DestReg = X86::EBP; break; 16867 case X86::SP: DestReg = X86::ESP; break; 16868 } 16869 if (DestReg) { 16870 Res.first = DestReg; 16871 Res.second = &X86::GR32RegClass; 16872 } 16873 } else if (VT == MVT::i64) { 16874 unsigned DestReg = 0; 16875 switch (Res.first) { 16876 default: break; 16877 case X86::AX: DestReg = X86::RAX; break; 16878 case X86::DX: DestReg = X86::RDX; break; 16879 case X86::CX: DestReg = X86::RCX; break; 16880 case X86::BX: DestReg = X86::RBX; break; 16881 case X86::SI: DestReg = X86::RSI; break; 16882 case X86::DI: DestReg = X86::RDI; break; 16883 case X86::BP: DestReg = X86::RBP; break; 16884 case X86::SP: DestReg = X86::RSP; break; 16885 } 16886 if (DestReg) { 16887 Res.first = DestReg; 16888 Res.second = &X86::GR64RegClass; 16889 } 16890 } 16891 } else if (Res.second == &X86::FR32RegClass || 16892 Res.second == &X86::FR64RegClass || 16893 Res.second == &X86::VR128RegClass) { 16894 // Handle references to XMM physical registers that got mapped into the 16895 // wrong class. This can happen with constraints like {xmm0} where the 16896 // target independent register mapper will just pick the first match it can 16897 // find, ignoring the required type. 16898 16899 if (VT == MVT::f32 || VT == MVT::i32) 16900 Res.second = &X86::FR32RegClass; 16901 else if (VT == MVT::f64 || VT == MVT::i64) 16902 Res.second = &X86::FR64RegClass; 16903 else if (X86::VR128RegClass.hasType(VT)) 16904 Res.second = &X86::VR128RegClass; 16905 else if (X86::VR256RegClass.hasType(VT)) 16906 Res.second = &X86::VR256RegClass; 16907 } 16908 16909 return Res; 16910} 16911