X86ISelLowering.cpp revision b2c9290a01c5a6f2206f4c47c702086834b65339 
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "x86-isel"
16#include "X86.h"
17#include "X86InstrBuilder.h"
18#include "X86ISelLowering.h"
19#include "X86TargetMachine.h"
20#include "X86TargetObjectFile.h"
21#include "llvm/CallingConv.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/GlobalAlias.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/Function.h"
27#include "llvm/Instructions.h"
28#include "llvm/Intrinsics.h"
29#include "llvm/LLVMContext.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/MC/MCAsmInfo.h"
38#include "llvm/MC/MCContext.h"
39#include "llvm/MC/MCExpr.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/ADT/BitVector.h"
42#include "llvm/ADT/SmallSet.h"
43#include "llvm/ADT/Statistic.h"
44#include "llvm/ADT/StringExtras.h"
45#include "llvm/ADT/VectorExtras.h"
46#include "llvm/Support/CommandLine.h"
47#include "llvm/Support/Debug.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/MathExtras.h"
50#include "llvm/Support/raw_ostream.h"
51using namespace llvm;
52
53STATISTIC(NumTailCalls, "Number of tail calls");
54
55static cl::opt<bool>
56DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
57
58// Disable16Bit - 16-bit operations typically have a larger encoding than
59// corresponding 32-bit instructions, and 16-bit code is slow on some
60// processors. This is an experimental flag to disable 16-bit operations
61// (which forces them to be Legalized to 32-bit operations).
62static cl::opt<bool>
63Disable16Bit("disable-16bit", cl::Hidden,
64             cl::desc("Disable use of 16-bit instructions"));
65
66// Forward declarations.
67static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68                       SDValue V2);
69
70static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
71  switch (TM.getSubtarget<X86Subtarget>().TargetType) {
72  default: llvm_unreachable("unknown subtarget type");
73  case X86Subtarget::isDarwin:
74    if (TM.getSubtarget<X86Subtarget>().is64Bit())
75      return new X8664_MachoTargetObjectFile();
76    return new X8632_MachoTargetObjectFile();
77  case X86Subtarget::isELF:
78    return new TargetLoweringObjectFileELF();
79  case X86Subtarget::isMingw:
80  case X86Subtarget::isCygwin:
81  case X86Subtarget::isWindows:
82    return new TargetLoweringObjectFileCOFF();
83  }
84
85}
86
87X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
88  : TargetLowering(TM, createTLOF(TM)) {
89  Subtarget = &TM.getSubtarget<X86Subtarget>();
90  X86ScalarSSEf64 = Subtarget->hasSSE2();
91  X86ScalarSSEf32 = Subtarget->hasSSE1();
92  X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
93
94  RegInfo = TM.getRegisterInfo();
95  TD = getTargetData();
96
97  // Set up the TargetLowering object.
98
99  // X86 is weird, it always uses i8 for shift amounts and setcc results.
100  setShiftAmountType(MVT::i8);
101  setBooleanContents(ZeroOrOneBooleanContent);
102  setSchedulingPreference(SchedulingForRegPressure);
103  setStackPointerRegisterToSaveRestore(X86StackPtr);
104
105  if (Subtarget->isTargetDarwin()) {
106    // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
107    setUseUnderscoreSetJmp(false);
108    setUseUnderscoreLongJmp(false);
109  } else if (Subtarget->isTargetMingw()) {
110    // MS runtime is weird: it exports _setjmp, but longjmp!
111    setUseUnderscoreSetJmp(true);
112    setUseUnderscoreLongJmp(false);
113  } else {
114    setUseUnderscoreSetJmp(true);
115    setUseUnderscoreLongJmp(true);
116  }
117
118  // Set up the register classes.
119  addRegisterClass(MVT::i8, X86::GR8RegisterClass);
120  if (!Disable16Bit)
121    addRegisterClass(MVT::i16, X86::GR16RegisterClass);
122  addRegisterClass(MVT::i32, X86::GR32RegisterClass);
123  if (Subtarget->is64Bit())
124    addRegisterClass(MVT::i64, X86::GR64RegisterClass);
125
126  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
127
128  // We don't accept any truncstore of integer registers.
129  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
130  if (!Disable16Bit)
131    setTruncStoreAction(MVT::i64, MVT::i16, Expand);
132  setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
133  if (!Disable16Bit)
134    setTruncStoreAction(MVT::i32, MVT::i16, Expand);
135  setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
136  setTruncStoreAction(MVT::i16, MVT::i8,  Expand);
137
138  // SETOEQ and SETUNE require checking two conditions.
139  setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
140  setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
141  setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
142  setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
143  setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
144  setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
145
146  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
147  // operation.
148  setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
149  setOperationAction(ISD::UINT_TO_FP       , MVT::i8   , Promote);
150  setOperationAction(ISD::UINT_TO_FP       , MVT::i16  , Promote);
151
152  if (Subtarget->is64Bit()) {
153    setOperationAction(ISD::UINT_TO_FP     , MVT::i32  , Promote);
154    setOperationAction(ISD::UINT_TO_FP     , MVT::i64  , Expand);
155  } else if (!UseSoftFloat) {
156    if (X86ScalarSSEf64) {
157      // We have an impenetrably clever algorithm for ui64->double only.
158      setOperationAction(ISD::UINT_TO_FP   , MVT::i64  , Custom);
159    }
160    // We have an algorithm for SSE2, and we turn this into a 64-bit
161    // FILD for other targets.
162    setOperationAction(ISD::UINT_TO_FP   , MVT::i32  , Custom);
163  }
164
165  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
166  // this operation.
167  setOperationAction(ISD::SINT_TO_FP       , MVT::i1   , Promote);
168  setOperationAction(ISD::SINT_TO_FP       , MVT::i8   , Promote);
169
170  if (!UseSoftFloat) {
171    // SSE has no i16 to fp conversion, only i32
172    if (X86ScalarSSEf32) {
173      setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Promote);
174      // f32 and f64 cases are Legal, f80 case is not
175      setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
176    } else {
177      setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Custom);
178      setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
179    }
180  } else {
181    setOperationAction(ISD::SINT_TO_FP     , MVT::i16  , Promote);
182    setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Promote);
183  }
184
185  // In 32-bit mode these are custom lowered.  In 64-bit mode F32 and F64
186  // are Legal, f80 is custom lowered.
187  setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);
188  setOperationAction(ISD::SINT_TO_FP     , MVT::i64  , Custom);
189
190  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
191  // this operation.
192  setOperationAction(ISD::FP_TO_SINT       , MVT::i1   , Promote);
193  setOperationAction(ISD::FP_TO_SINT       , MVT::i8   , Promote);
194
195  if (X86ScalarSSEf32) {
196    setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Promote);
197    // f32 and f64 cases are Legal, f80 case is not
198    setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);
199  } else {
200    setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Custom);
201    setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);
202  }
203
204  // Handle FP_TO_UINT by promoting the destination to a larger signed
205  // conversion.
206  setOperationAction(ISD::FP_TO_UINT       , MVT::i1   , Promote);
207  setOperationAction(ISD::FP_TO_UINT       , MVT::i8   , Promote);
208  setOperationAction(ISD::FP_TO_UINT       , MVT::i16  , Promote);
209
210  if (Subtarget->is64Bit()) {
211    setOperationAction(ISD::FP_TO_UINT     , MVT::i64  , Expand);
212    setOperationAction(ISD::FP_TO_UINT     , MVT::i32  , Promote);
213  } else if (!UseSoftFloat) {
214    if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
215      // Expand FP_TO_UINT into a select.
216      // FIXME: We would like to use a Custom expander here eventually to do
217      // the optimal thing for SSE vs. the default expansion in the legalizer.
218      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Expand);
219    else
220      // With SSE3 we can use fisttpll to convert to a signed i64; without
221      // SSE, we're stuck with a fistpll.
222      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Custom);
223  }
224
225  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
226  if (!X86ScalarSSEf64) {
227    setOperationAction(ISD::BIT_CONVERT      , MVT::f32  , Expand);
228    setOperationAction(ISD::BIT_CONVERT      , MVT::i32  , Expand);
229  }
230
231  // Scalar integer divide and remainder are lowered to use operations that
232  // produce two results, to match the available instructions. This exposes
233  // the two-result form to trivial CSE, which is able to combine x/y and x%y
234  // into a single instruction.
235  //
236  // Scalar integer multiply-high is also lowered to use two-result
237  // operations, to match the available instructions. However, plain multiply
238  // (low) operations are left as Legal, as there are single-result
239  // instructions for this in x86. Using the two-result multiply instructions
240  // when both high and low results are needed must be arranged by dagcombine.
241  setOperationAction(ISD::MULHS           , MVT::i8    , Expand);
242  setOperationAction(ISD::MULHU           , MVT::i8    , Expand);
243  setOperationAction(ISD::SDIV            , MVT::i8    , Expand);
244  setOperationAction(ISD::UDIV            , MVT::i8    , Expand);
245  setOperationAction(ISD::SREM            , MVT::i8    , Expand);
246  setOperationAction(ISD::UREM            , MVT::i8    , Expand);
247  setOperationAction(ISD::MULHS           , MVT::i16   , Expand);
248  setOperationAction(ISD::MULHU           , MVT::i16   , Expand);
249  setOperationAction(ISD::SDIV            , MVT::i16   , Expand);
250  setOperationAction(ISD::UDIV            , MVT::i16   , Expand);
251  setOperationAction(ISD::SREM            , MVT::i16   , Expand);
252  setOperationAction(ISD::UREM            , MVT::i16   , Expand);
253  setOperationAction(ISD::MULHS           , MVT::i32   , Expand);
254  setOperationAction(ISD::MULHU           , MVT::i32   , Expand);
255  setOperationAction(ISD::SDIV            , MVT::i32   , Expand);
256  setOperationAction(ISD::UDIV            , MVT::i32   , Expand);
257  setOperationAction(ISD::SREM            , MVT::i32   , Expand);
258  setOperationAction(ISD::UREM            , MVT::i32   , Expand);
259  setOperationAction(ISD::MULHS           , MVT::i64   , Expand);
260  setOperationAction(ISD::MULHU           , MVT::i64   , Expand);
261  setOperationAction(ISD::SDIV            , MVT::i64   , Expand);
262  setOperationAction(ISD::UDIV            , MVT::i64   , Expand);
263  setOperationAction(ISD::SREM            , MVT::i64   , Expand);
264  setOperationAction(ISD::UREM            , MVT::i64   , Expand);
265
266  setOperationAction(ISD::BR_JT            , MVT::Other, Expand);
267  setOperationAction(ISD::BRCOND           , MVT::Other, Custom);
268  setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
269  setOperationAction(ISD::SELECT_CC        , MVT::Other, Expand);
270  if (Subtarget->is64Bit())
271    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
272  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Legal);
273  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Legal);
274  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
275  setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
276  setOperationAction(ISD::FREM             , MVT::f32  , Expand);
277  setOperationAction(ISD::FREM             , MVT::f64  , Expand);
278  setOperationAction(ISD::FREM             , MVT::f80  , Expand);
279  setOperationAction(ISD::FLT_ROUNDS_      , MVT::i32  , Custom);
280
281  setOperationAction(ISD::CTPOP            , MVT::i8   , Expand);
282  setOperationAction(ISD::CTTZ             , MVT::i8   , Custom);
283  setOperationAction(ISD::CTLZ             , MVT::i8   , Custom);
284  setOperationAction(ISD::CTPOP            , MVT::i16  , Expand);
285  if (Disable16Bit) {
286    setOperationAction(ISD::CTTZ           , MVT::i16  , Expand);
287    setOperationAction(ISD::CTLZ           , MVT::i16  , Expand);
288  } else {
289    setOperationAction(ISD::CTTZ           , MVT::i16  , Custom);
290    setOperationAction(ISD::CTLZ           , MVT::i16  , Custom);
291  }
292  setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
293  setOperationAction(ISD::CTTZ             , MVT::i32  , Custom);
294  setOperationAction(ISD::CTLZ             , MVT::i32  , Custom);
295  if (Subtarget->is64Bit()) {
296    setOperationAction(ISD::CTPOP          , MVT::i64  , Expand);
297    setOperationAction(ISD::CTTZ           , MVT::i64  , Custom);
298    setOperationAction(ISD::CTLZ           , MVT::i64  , Custom);
299  }
300
301  setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
302  setOperationAction(ISD::BSWAP            , MVT::i16  , Expand);
303
304  // These should be promoted to a larger select which is supported.
305  setOperationAction(ISD::SELECT          , MVT::i1   , Promote);
306  // X86 wants to expand cmov itself.
307  setOperationAction(ISD::SELECT          , MVT::i8   , Custom);
308  if (Disable16Bit)
309    setOperationAction(ISD::SELECT        , MVT::i16  , Expand);
310  else
311    setOperationAction(ISD::SELECT        , MVT::i16  , Custom);
312  setOperationAction(ISD::SELECT          , MVT::i32  , Custom);
313  setOperationAction(ISD::SELECT          , MVT::f32  , Custom);
314  setOperationAction(ISD::SELECT          , MVT::f64  , Custom);
315  setOperationAction(ISD::SELECT          , MVT::f80  , Custom);
316  setOperationAction(ISD::SETCC           , MVT::i8   , Custom);
317  if (Disable16Bit)
318    setOperationAction(ISD::SETCC         , MVT::i16  , Expand);
319  else
320    setOperationAction(ISD::SETCC         , MVT::i16  , Custom);
321  setOperationAction(ISD::SETCC           , MVT::i32  , Custom);
322  setOperationAction(ISD::SETCC           , MVT::f32  , Custom);
323  setOperationAction(ISD::SETCC           , MVT::f64  , Custom);
324  setOperationAction(ISD::SETCC           , MVT::f80  , Custom);
325  if (Subtarget->is64Bit()) {
326    setOperationAction(ISD::SELECT        , MVT::i64  , Custom);
327    setOperationAction(ISD::SETCC         , MVT::i64  , Custom);
328  }
329  setOperationAction(ISD::EH_RETURN       , MVT::Other, Custom);
330
331  // Darwin ABI issue.
332  setOperationAction(ISD::ConstantPool    , MVT::i32  , Custom);
333  setOperationAction(ISD::JumpTable       , MVT::i32  , Custom);
334  setOperationAction(ISD::GlobalAddress   , MVT::i32  , Custom);
335  setOperationAction(ISD::GlobalTLSAddress, MVT::i32  , Custom);
336  if (Subtarget->is64Bit())
337    setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
338  setOperationAction(ISD::ExternalSymbol  , MVT::i32  , Custom);
339  setOperationAction(ISD::BlockAddress    , MVT::i32  , Custom);
340  if (Subtarget->is64Bit()) {
341    setOperationAction(ISD::ConstantPool  , MVT::i64  , Custom);
342    setOperationAction(ISD::JumpTable     , MVT::i64  , Custom);
343    setOperationAction(ISD::GlobalAddress , MVT::i64  , Custom);
344    setOperationAction(ISD::ExternalSymbol, MVT::i64  , Custom);
345    setOperationAction(ISD::BlockAddress  , MVT::i64  , Custom);
346  }
347  // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
348  setOperationAction(ISD::SHL_PARTS       , MVT::i32  , Custom);
349  setOperationAction(ISD::SRA_PARTS       , MVT::i32  , Custom);
350  setOperationAction(ISD::SRL_PARTS       , MVT::i32  , Custom);
351  if (Subtarget->is64Bit()) {
352    setOperationAction(ISD::SHL_PARTS     , MVT::i64  , Custom);
353    setOperationAction(ISD::SRA_PARTS     , MVT::i64  , Custom);
354    setOperationAction(ISD::SRL_PARTS     , MVT::i64  , Custom);
355  }
356
357  if (Subtarget->hasSSE1())
358    setOperationAction(ISD::PREFETCH      , MVT::Other, Legal);
359
360  if (!Subtarget->hasSSE2())
361    setOperationAction(ISD::MEMBARRIER    , MVT::Other, Expand);
362
363  // Expand certain atomics
364  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
365  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
366  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
367  setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
368
369  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
370  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
371  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
372  setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
373
374  if (!Subtarget->is64Bit()) {
375    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
376    setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377    setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
378    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
379    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
380    setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
381    setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
382  }
383
384  // FIXME - use subtarget debug flags
385  if (!Subtarget->isTargetDarwin() &&
386      !Subtarget->isTargetELF() &&
387      !Subtarget->isTargetCygMing()) {
388    setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
389  }
390
391  setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
392  setOperationAction(ISD::EHSELECTION,   MVT::i64, Expand);
393  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
394  setOperationAction(ISD::EHSELECTION,   MVT::i32, Expand);
395  if (Subtarget->is64Bit()) {
396    setExceptionPointerRegister(X86::RAX);
397    setExceptionSelectorRegister(X86::RDX);
398  } else {
399    setExceptionPointerRegister(X86::EAX);
400    setExceptionSelectorRegister(X86::EDX);
401  }
402  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
403  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
404
405  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
406
407  setOperationAction(ISD::TRAP, MVT::Other, Legal);
408
409  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
410  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
411  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
412  if (Subtarget->is64Bit()) {
413    setOperationAction(ISD::VAARG           , MVT::Other, Custom);
414    setOperationAction(ISD::VACOPY          , MVT::Other, Custom);
415  } else {
416    setOperationAction(ISD::VAARG           , MVT::Other, Expand);
417    setOperationAction(ISD::VACOPY          , MVT::Other, Expand);
418  }
419
420  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
421  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
422  if (Subtarget->is64Bit())
423    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
424  if (Subtarget->isTargetCygMing())
425    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
426  else
427    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
428
429  if (!UseSoftFloat && X86ScalarSSEf64) {
430    // f32 and f64 use SSE.
431    // Set up the FP register classes.
432    addRegisterClass(MVT::f32, X86::FR32RegisterClass);
433    addRegisterClass(MVT::f64, X86::FR64RegisterClass);
434
435    // Use ANDPD to simulate FABS.
436    setOperationAction(ISD::FABS , MVT::f64, Custom);
437    setOperationAction(ISD::FABS , MVT::f32, Custom);
438
439    // Use XORP to simulate FNEG.
440    setOperationAction(ISD::FNEG , MVT::f64, Custom);
441    setOperationAction(ISD::FNEG , MVT::f32, Custom);
442
443    // Use ANDPD and ORPD to simulate FCOPYSIGN.
444    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
445    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
446
447    // We don't support sin/cos/fmod
448    setOperationAction(ISD::FSIN , MVT::f64, Expand);
449    setOperationAction(ISD::FCOS , MVT::f64, Expand);
450    setOperationAction(ISD::FSIN , MVT::f32, Expand);
451    setOperationAction(ISD::FCOS , MVT::f32, Expand);
452
453    // Expand FP immediates into loads from the stack, except for the special
454    // cases we handle.
455    addLegalFPImmediate(APFloat(+0.0)); // xorpd
456    addLegalFPImmediate(APFloat(+0.0f)); // xorps
457  } else if (!UseSoftFloat && X86ScalarSSEf32) {
458    // Use SSE for f32, x87 for f64.
459    // Set up the FP register classes.
460    addRegisterClass(MVT::f32, X86::FR32RegisterClass);
461    addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
462
463    // Use ANDPS to simulate FABS.
464    setOperationAction(ISD::FABS , MVT::f32, Custom);
465
466    // Use XORP to simulate FNEG.
467    setOperationAction(ISD::FNEG , MVT::f32, Custom);
468
469    setOperationAction(ISD::UNDEF,     MVT::f64, Expand);
470
471    // Use ANDPS and ORPS to simulate FCOPYSIGN.
472    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
473    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
474
475    // We don't support sin/cos/fmod
476    setOperationAction(ISD::FSIN , MVT::f32, Expand);
477    setOperationAction(ISD::FCOS , MVT::f32, Expand);
478
479    // Special cases we handle for FP constants.
480    addLegalFPImmediate(APFloat(+0.0f)); // xorps
481    addLegalFPImmediate(APFloat(+0.0)); // FLD0
482    addLegalFPImmediate(APFloat(+1.0)); // FLD1
483    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
484    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
485
486    if (!UnsafeFPMath) {
487      setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
488      setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
489    }
490  } else if (!UseSoftFloat) {
491    // f32 and f64 in x87.
492    // Set up the FP register classes.
493    addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
494    addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
495
496    setOperationAction(ISD::UNDEF,     MVT::f64, Expand);
497    setOperationAction(ISD::UNDEF,     MVT::f32, Expand);
498    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
499    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
500
501    if (!UnsafeFPMath) {
502      setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
503      setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
504    }
505    addLegalFPImmediate(APFloat(+0.0)); // FLD0
506    addLegalFPImmediate(APFloat(+1.0)); // FLD1
507    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
508    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
509    addLegalFPImmediate(APFloat(+0.0f)); // FLD0
510    addLegalFPImmediate(APFloat(+1.0f)); // FLD1
511    addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
512    addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
513  }
514
515  // Long double always uses X87.
516  if (!UseSoftFloat) {
517    addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
518    setOperationAction(ISD::UNDEF,     MVT::f80, Expand);
519    setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
520    {
521      bool ignored;
522      APFloat TmpFlt(+0.0);
523      TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
524                     &ignored);
525      addLegalFPImmediate(TmpFlt);  // FLD0
526      TmpFlt.changeSign();
527      addLegalFPImmediate(TmpFlt);  // FLD0/FCHS
528      APFloat TmpFlt2(+1.0);
529      TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
530                      &ignored);
531      addLegalFPImmediate(TmpFlt2);  // FLD1
532      TmpFlt2.changeSign();
533      addLegalFPImmediate(TmpFlt2);  // FLD1/FCHS
534    }
535
536    if (!UnsafeFPMath) {
537      setOperationAction(ISD::FSIN           , MVT::f80  , Expand);
538      setOperationAction(ISD::FCOS           , MVT::f80  , Expand);
539    }
540  }
541
542  // Always use a library call for pow.
543  setOperationAction(ISD::FPOW             , MVT::f32  , Expand);
544  setOperationAction(ISD::FPOW             , MVT::f64  , Expand);
545  setOperationAction(ISD::FPOW             , MVT::f80  , Expand);
546
547  setOperationAction(ISD::FLOG, MVT::f80, Expand);
548  setOperationAction(ISD::FLOG2, MVT::f80, Expand);
549  setOperationAction(ISD::FLOG10, MVT::f80, Expand);
550  setOperationAction(ISD::FEXP, MVT::f80, Expand);
551  setOperationAction(ISD::FEXP2, MVT::f80, Expand);
552
553  // First set operation action for all vector types to either promote
554  // (for widening) or expand (for scalarization). Then we will selectively
555  // turn on ones that can be effectively codegen'd.
556  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
557       VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
558    setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
559    setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
560    setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
561    setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
562    setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
563    setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
564    setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
565    setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
566    setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
567    setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
568    setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
569    setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
570    setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
571    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
572    setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
573    setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
574    setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
575    setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
576    setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
577    setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
578    setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
579    setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
580    setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
581    setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
582    setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
583    setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584    setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
585    setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
586    setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
587    setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
588    setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
589    setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
590    setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
591    setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
592    setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
593    setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
594    setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
595    setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
596    setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
597    setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
598    setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
599    setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
600    setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
601    setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
602    setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
603    setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
604    setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
605    setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606    setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
607    setOperationAction(ISD::TRUNCATE,  (MVT::SimpleValueType)VT, Expand);
608    setOperationAction(ISD::SIGN_EXTEND,  (MVT::SimpleValueType)VT, Expand);
609    setOperationAction(ISD::ZERO_EXTEND,  (MVT::SimpleValueType)VT, Expand);
610    setOperationAction(ISD::ANY_EXTEND,  (MVT::SimpleValueType)VT, Expand);
611    for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
612         InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
613      setTruncStoreAction((MVT::SimpleValueType)VT,
614                          (MVT::SimpleValueType)InnerVT, Expand);
615    setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
616    setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617    setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
618  }
619
620  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
621  // with -msoft-float, disable use of MMX as well.
622  if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
623    addRegisterClass(MVT::v8i8,  X86::VR64RegisterClass);
624    addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
625    addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
626    addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
627    addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
628
629    setOperationAction(ISD::ADD,                MVT::v8i8,  Legal);
630    setOperationAction(ISD::ADD,                MVT::v4i16, Legal);
631    setOperationAction(ISD::ADD,                MVT::v2i32, Legal);
632    setOperationAction(ISD::ADD,                MVT::v1i64, Legal);
633
634    setOperationAction(ISD::SUB,                MVT::v8i8,  Legal);
635    setOperationAction(ISD::SUB,                MVT::v4i16, Legal);
636    setOperationAction(ISD::SUB,                MVT::v2i32, Legal);
637    setOperationAction(ISD::SUB,                MVT::v1i64, Legal);
638
639    setOperationAction(ISD::MULHS,              MVT::v4i16, Legal);
640    setOperationAction(ISD::MUL,                MVT::v4i16, Legal);
641
642    setOperationAction(ISD::AND,                MVT::v8i8,  Promote);
643    AddPromotedToType (ISD::AND,                MVT::v8i8,  MVT::v1i64);
644    setOperationAction(ISD::AND,                MVT::v4i16, Promote);
645    AddPromotedToType (ISD::AND,                MVT::v4i16, MVT::v1i64);
646    setOperationAction(ISD::AND,                MVT::v2i32, Promote);
647    AddPromotedToType (ISD::AND,                MVT::v2i32, MVT::v1i64);
648    setOperationAction(ISD::AND,                MVT::v1i64, Legal);
649
650    setOperationAction(ISD::OR,                 MVT::v8i8,  Promote);
651    AddPromotedToType (ISD::OR,                 MVT::v8i8,  MVT::v1i64);
652    setOperationAction(ISD::OR,                 MVT::v4i16, Promote);
653    AddPromotedToType (ISD::OR,                 MVT::v4i16, MVT::v1i64);
654    setOperationAction(ISD::OR,                 MVT::v2i32, Promote);
655    AddPromotedToType (ISD::OR,                 MVT::v2i32, MVT::v1i64);
656    setOperationAction(ISD::OR,                 MVT::v1i64, Legal);
657
658    setOperationAction(ISD::XOR,                MVT::v8i8,  Promote);
659    AddPromotedToType (ISD::XOR,                MVT::v8i8,  MVT::v1i64);
660    setOperationAction(ISD::XOR,                MVT::v4i16, Promote);
661    AddPromotedToType (ISD::XOR,                MVT::v4i16, MVT::v1i64);
662    setOperationAction(ISD::XOR,                MVT::v2i32, Promote);
663    AddPromotedToType (ISD::XOR,                MVT::v2i32, MVT::v1i64);
664    setOperationAction(ISD::XOR,                MVT::v1i64, Legal);
665
666    setOperationAction(ISD::LOAD,               MVT::v8i8,  Promote);
667    AddPromotedToType (ISD::LOAD,               MVT::v8i8,  MVT::v1i64);
668    setOperationAction(ISD::LOAD,               MVT::v4i16, Promote);
669    AddPromotedToType (ISD::LOAD,               MVT::v4i16, MVT::v1i64);
670    setOperationAction(ISD::LOAD,               MVT::v2i32, Promote);
671    AddPromotedToType (ISD::LOAD,               MVT::v2i32, MVT::v1i64);
672    setOperationAction(ISD::LOAD,               MVT::v2f32, Promote);
673    AddPromotedToType (ISD::LOAD,               MVT::v2f32, MVT::v1i64);
674    setOperationAction(ISD::LOAD,               MVT::v1i64, Legal);
675
676    setOperationAction(ISD::BUILD_VECTOR,       MVT::v8i8,  Custom);
677    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i16, Custom);
678    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i32, Custom);
679    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2f32, Custom);
680    setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i64, Custom);
681
682    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i8,  Custom);
683    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4i16, Custom);
684    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i32, Custom);
685    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v1i64, Custom);
686
687    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v2f32, Custom);
688    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i8,  Custom);
689    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v4i16, Custom);
690    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v1i64, Custom);
691
692    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i16, Custom);
693
694    setOperationAction(ISD::SELECT,             MVT::v8i8, Promote);
695    setOperationAction(ISD::SELECT,             MVT::v4i16, Promote);
696    setOperationAction(ISD::SELECT,             MVT::v2i32, Promote);
697    setOperationAction(ISD::SELECT,             MVT::v1i64, Custom);
698    setOperationAction(ISD::VSETCC,             MVT::v8i8, Custom);
699    setOperationAction(ISD::VSETCC,             MVT::v4i16, Custom);
700    setOperationAction(ISD::VSETCC,             MVT::v2i32, Custom);
701  }
702
703  if (!UseSoftFloat && Subtarget->hasSSE1()) {
704    addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
705
706    setOperationAction(ISD::FADD,               MVT::v4f32, Legal);
707    setOperationAction(ISD::FSUB,               MVT::v4f32, Legal);
708    setOperationAction(ISD::FMUL,               MVT::v4f32, Legal);
709    setOperationAction(ISD::FDIV,               MVT::v4f32, Legal);
710    setOperationAction(ISD::FSQRT,              MVT::v4f32, Legal);
711    setOperationAction(ISD::FNEG,               MVT::v4f32, Custom);
712    setOperationAction(ISD::LOAD,               MVT::v4f32, Legal);
713    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4f32, Custom);
714    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f32, Custom);
715    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
716    setOperationAction(ISD::SELECT,             MVT::v4f32, Custom);
717    setOperationAction(ISD::VSETCC,             MVT::v4f32, Custom);
718  }
719
720  if (!UseSoftFloat && Subtarget->hasSSE2()) {
721    addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
722
723    // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
724    // registers cannot be used even for integer operations.
725    addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
726    addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
727    addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
728    addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
729
730    setOperationAction(ISD::ADD,                MVT::v16i8, Legal);
731    setOperationAction(ISD::ADD,                MVT::v8i16, Legal);
732    setOperationAction(ISD::ADD,                MVT::v4i32, Legal);
733    setOperationAction(ISD::ADD,                MVT::v2i64, Legal);
734    setOperationAction(ISD::MUL,                MVT::v2i64, Custom);
735    setOperationAction(ISD::SUB,                MVT::v16i8, Legal);
736    setOperationAction(ISD::SUB,                MVT::v8i16, Legal);
737    setOperationAction(ISD::SUB,                MVT::v4i32, Legal);
738    setOperationAction(ISD::SUB,                MVT::v2i64, Legal);
739    setOperationAction(ISD::MUL,                MVT::v8i16, Legal);
740    setOperationAction(ISD::FADD,               MVT::v2f64, Legal);
741    setOperationAction(ISD::FSUB,               MVT::v2f64, Legal);
742    setOperationAction(ISD::FMUL,               MVT::v2f64, Legal);
743    setOperationAction(ISD::FDIV,               MVT::v2f64, Legal);
744    setOperationAction(ISD::FSQRT,              MVT::v2f64, Legal);
745    setOperationAction(ISD::FNEG,               MVT::v2f64, Custom);
746
747    setOperationAction(ISD::VSETCC,             MVT::v2f64, Custom);
748    setOperationAction(ISD::VSETCC,             MVT::v16i8, Custom);
749    setOperationAction(ISD::VSETCC,             MVT::v8i16, Custom);
750    setOperationAction(ISD::VSETCC,             MVT::v4i32, Custom);
751
752    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i8, Custom);
753    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i16, Custom);
754    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
755    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);
756    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);
757
758    setOperationAction(ISD::CONCAT_VECTORS,     MVT::v2f64, Custom);
759    setOperationAction(ISD::CONCAT_VECTORS,     MVT::v2i64, Custom);
760    setOperationAction(ISD::CONCAT_VECTORS,     MVT::v16i8, Custom);
761    setOperationAction(ISD::CONCAT_VECTORS,     MVT::v8i16, Custom);
762    setOperationAction(ISD::CONCAT_VECTORS,     MVT::v4i32, Custom);
763
764    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
765    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
766      EVT VT = (MVT::SimpleValueType)i;
767      // Do not attempt to custom lower non-power-of-2 vectors
768      if (!isPowerOf2_32(VT.getVectorNumElements()))
769        continue;
770      // Do not attempt to custom lower non-128-bit vectors
771      if (!VT.is128BitVector())
772        continue;
773      setOperationAction(ISD::BUILD_VECTOR,
774                         VT.getSimpleVT().SimpleTy, Custom);
775      setOperationAction(ISD::VECTOR_SHUFFLE,
776                         VT.getSimpleVT().SimpleTy, Custom);
777      setOperationAction(ISD::EXTRACT_VECTOR_ELT,
778                         VT.getSimpleVT().SimpleTy, Custom);
779    }
780
781    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2f64, Custom);
782    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i64, Custom);
783    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2f64, Custom);
784    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i64, Custom);
785    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2f64, Custom);
786    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
787
788    if (Subtarget->is64Bit()) {
789      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);
790      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
791    }
792
793    // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
794    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
795      MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
796      EVT VT = SVT;
797
798      // Do not attempt to promote non-128-bit vectors
799      if (!VT.is128BitVector()) {
800        continue;
801      }
802      setOperationAction(ISD::AND,    SVT, Promote);
803      AddPromotedToType (ISD::AND,    SVT, MVT::v2i64);
804      setOperationAction(ISD::OR,     SVT, Promote);
805      AddPromotedToType (ISD::OR,     SVT, MVT::v2i64);
806      setOperationAction(ISD::XOR,    SVT, Promote);
807      AddPromotedToType (ISD::XOR,    SVT, MVT::v2i64);
808      setOperationAction(ISD::LOAD,   SVT, Promote);
809      AddPromotedToType (ISD::LOAD,   SVT, MVT::v2i64);
810      setOperationAction(ISD::SELECT, SVT, Promote);
811      AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
812    }
813
814    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
815
816    // Custom lower v2i64 and v2f64 selects.
817    setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
818    setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
819    setOperationAction(ISD::SELECT,             MVT::v2f64, Custom);
820    setOperationAction(ISD::SELECT,             MVT::v2i64, Custom);
821
822    setOperationAction(ISD::FP_TO_SINT,         MVT::v4i32, Legal);
823    setOperationAction(ISD::SINT_TO_FP,         MVT::v4i32, Legal);
824    if (!DisableMMX && Subtarget->hasMMX()) {
825      setOperationAction(ISD::FP_TO_SINT,         MVT::v2i32, Custom);
826      setOperationAction(ISD::SINT_TO_FP,         MVT::v2i32, Custom);
827    }
828  }
829
830  if (Subtarget->hasSSE41()) {
831    // FIXME: Do we need to handle scalar-to-vector here?
832    setOperationAction(ISD::MUL,                MVT::v4i32, Legal);
833
834    // i8 and i16 vectors are custom , because the source register and source
835    // source memory operand types are not the same width.  f32 vectors are
836    // custom since the immediate controlling the insert encodes additional
837    // information.
838    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);
839    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
840    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);
841    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);
842
843    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
844    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
845    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
846    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
847
848    if (Subtarget->is64Bit()) {
849      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Legal);
850      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
851    }
852  }
853
854  if (Subtarget->hasSSE42()) {
855    setOperationAction(ISD::VSETCC,             MVT::v2i64, Custom);
856  }
857
858  if (!UseSoftFloat && Subtarget->hasAVX()) {
859    addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
860    addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
861    addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
862    addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
863
864    setOperationAction(ISD::LOAD,               MVT::v8f32, Legal);
865    setOperationAction(ISD::LOAD,               MVT::v8i32, Legal);
866    setOperationAction(ISD::LOAD,               MVT::v4f64, Legal);
867    setOperationAction(ISD::LOAD,               MVT::v4i64, Legal);
868    setOperationAction(ISD::FADD,               MVT::v8f32, Legal);
869    setOperationAction(ISD::FSUB,               MVT::v8f32, Legal);
870    setOperationAction(ISD::FMUL,               MVT::v8f32, Legal);
871    setOperationAction(ISD::FDIV,               MVT::v8f32, Legal);
872    setOperationAction(ISD::FSQRT,              MVT::v8f32, Legal);
873    setOperationAction(ISD::FNEG,               MVT::v8f32, Custom);
874    //setOperationAction(ISD::BUILD_VECTOR,       MVT::v8f32, Custom);
875    //setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8f32, Custom);
876    //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
877    //setOperationAction(ISD::SELECT,             MVT::v8f32, Custom);
878    //setOperationAction(ISD::VSETCC,             MVT::v8f32, Custom);
879
880    // Operations to consider commented out -v16i16 v32i8
881    //setOperationAction(ISD::ADD,                MVT::v16i16, Legal);
882    setOperationAction(ISD::ADD,                MVT::v8i32, Custom);
883    setOperationAction(ISD::ADD,                MVT::v4i64, Custom);
884    //setOperationAction(ISD::SUB,                MVT::v32i8, Legal);
885    //setOperationAction(ISD::SUB,                MVT::v16i16, Legal);
886    setOperationAction(ISD::SUB,                MVT::v8i32, Custom);
887    setOperationAction(ISD::SUB,                MVT::v4i64, Custom);
888    //setOperationAction(ISD::MUL,                MVT::v16i16, Legal);
889    setOperationAction(ISD::FADD,               MVT::v4f64, Legal);
890    setOperationAction(ISD::FSUB,               MVT::v4f64, Legal);
891    setOperationAction(ISD::FMUL,               MVT::v4f64, Legal);
892    setOperationAction(ISD::FDIV,               MVT::v4f64, Legal);
893    setOperationAction(ISD::FSQRT,              MVT::v4f64, Legal);
894    setOperationAction(ISD::FNEG,               MVT::v4f64, Custom);
895
896    setOperationAction(ISD::VSETCC,             MVT::v4f64, Custom);
897    // setOperationAction(ISD::VSETCC,             MVT::v32i8, Custom);
898    // setOperationAction(ISD::VSETCC,             MVT::v16i16, Custom);
899    setOperationAction(ISD::VSETCC,             MVT::v8i32, Custom);
900
901    // setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v32i8, Custom);
902    // setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i16, Custom);
903    // setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i16, Custom);
904    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i32, Custom);
905    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8f32, Custom);
906
907    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4f64, Custom);
908    setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i64, Custom);
909    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f64, Custom);
910    setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4i64, Custom);
911    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f64, Custom);
912    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
913
914#if 0
915    // Not sure we want to do this since there are no 256-bit integer
916    // operations in AVX
917
918    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
919    // This includes 256-bit vectors
920    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
921      EVT VT = (MVT::SimpleValueType)i;
922
923      // Do not attempt to custom lower non-power-of-2 vectors
924      if (!isPowerOf2_32(VT.getVectorNumElements()))
925        continue;
926
927      setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
928      setOperationAction(ISD::VECTOR_SHUFFLE,     VT, Custom);
929      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
930    }
931
932    if (Subtarget->is64Bit()) {
933      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i64, Custom);
934      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
935    }
936#endif
937
938#if 0
939    // Not sure we want to do this since there are no 256-bit integer
940    // operations in AVX
941
942    // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
943    // Including 256-bit vectors
944    for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
945      EVT VT = (MVT::SimpleValueType)i;
946
947      if (!VT.is256BitVector()) {
948        continue;
949      }
950      setOperationAction(ISD::AND,    VT, Promote);
951      AddPromotedToType (ISD::AND,    VT, MVT::v4i64);
952      setOperationAction(ISD::OR,     VT, Promote);
953      AddPromotedToType (ISD::OR,     VT, MVT::v4i64);
954      setOperationAction(ISD::XOR,    VT, Promote);
955      AddPromotedToType (ISD::XOR,    VT, MVT::v4i64);
956      setOperationAction(ISD::LOAD,   VT, Promote);
957      AddPromotedToType (ISD::LOAD,   VT, MVT::v4i64);
958      setOperationAction(ISD::SELECT, VT, Promote);
959      AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
960    }
961
962    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
963#endif
964  }
965
966  // We want to custom lower some of our intrinsics.
967  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
968
969  // Add/Sub/Mul with overflow operations are custom lowered.
970  setOperationAction(ISD::SADDO, MVT::i32, Custom);
971  setOperationAction(ISD::SADDO, MVT::i64, Custom);
972  setOperationAction(ISD::UADDO, MVT::i32, Custom);
973  setOperationAction(ISD::UADDO, MVT::i64, Custom);
974  setOperationAction(ISD::SSUBO, MVT::i32, Custom);
975  setOperationAction(ISD::SSUBO, MVT::i64, Custom);
976  setOperationAction(ISD::USUBO, MVT::i32, Custom);
977  setOperationAction(ISD::USUBO, MVT::i64, Custom);
978  setOperationAction(ISD::SMULO, MVT::i32, Custom);
979  setOperationAction(ISD::SMULO, MVT::i64, Custom);
980
981  if (!Subtarget->is64Bit()) {
982    // These libcalls are not available in 32-bit.
983    setLibcallName(RTLIB::SHL_I128, 0);
984    setLibcallName(RTLIB::SRL_I128, 0);
985    setLibcallName(RTLIB::SRA_I128, 0);
986  }
987
988  // We have target-specific dag combine patterns for the following nodes:
989  setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
990  setTargetDAGCombine(ISD::BUILD_VECTOR);
991  setTargetDAGCombine(ISD::SELECT);
992  setTargetDAGCombine(ISD::SHL);
993  setTargetDAGCombine(ISD::SRA);
994  setTargetDAGCombine(ISD::SRL);
995  setTargetDAGCombine(ISD::OR);
996  setTargetDAGCombine(ISD::STORE);
997  setTargetDAGCombine(ISD::MEMBARRIER);
998  setTargetDAGCombine(ISD::ZERO_EXTEND);
999  if (Subtarget->is64Bit())
1000    setTargetDAGCombine(ISD::MUL);
1001
1002  computeRegisterProperties();
1003
1004  // Divide and reminder operations have no vector equivalent and can
1005  // trap. Do a custom widening for these operations in which we never
1006  // generate more divides/remainder than the original vector width.
1007  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1008       VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
1009    if (!isTypeLegal((MVT::SimpleValueType)VT)) {
1010      setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
1011      setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
1012      setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
1013      setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
1014    }
1015  }
1016
1017  // FIXME: These should be based on subtarget info. Plus, the values should
1018  // be smaller when we are in optimizing for size mode.
1019  maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1020  maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1021  maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1022  setPrefLoopAlignment(16);
1023  benefitFromCodePlacementOpt = true;
1024}
1025
1026
1027MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1028  return MVT::i8;
1029}
1030
1031
1032/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1033/// the desired ByVal argument alignment.
1034static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1035  if (MaxAlign == 16)
1036    return;
1037  if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1038    if (VTy->getBitWidth() == 128)
1039      MaxAlign = 16;
1040  } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1041    unsigned EltAlign = 0;
1042    getMaxByValAlign(ATy->getElementType(), EltAlign);
1043    if (EltAlign > MaxAlign)
1044      MaxAlign = EltAlign;
1045  } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1046    for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1047      unsigned EltAlign = 0;
1048      getMaxByValAlign(STy->getElementType(i), EltAlign);
1049      if (EltAlign > MaxAlign)
1050        MaxAlign = EltAlign;
1051      if (MaxAlign == 16)
1052        break;
1053    }
1054  }
1055  return;
1056}
1057
1058/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1059/// function arguments in the caller parameter area. For X86, aggregates
1060/// that contain SSE vectors are placed at 16-byte boundaries while the rest
1061/// are at 4-byte boundaries.
1062unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1063  if (Subtarget->is64Bit()) {
1064    // Max of 8 and alignment of type.
1065    unsigned TyAlign = TD->getABITypeAlignment(Ty);
1066    if (TyAlign > 8)
1067      return TyAlign;
1068    return 8;
1069  }
1070
1071  unsigned Align = 4;
1072  if (Subtarget->hasSSE1())
1073    getMaxByValAlign(Ty, Align);
1074  return Align;
1075}
1076
1077/// getOptimalMemOpType - Returns the target specific optimal type for load
1078/// and store operations as a result of memset, memcpy, and memmove
1079/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1080/// determining it.
1081EVT
1082X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1083                                       bool isSrcConst, bool isSrcStr,
1084                                       SelectionDAG &DAG) const {
1085  // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1086  // linux.  This is because the stack realignment code can't handle certain
1087  // cases like PR2962.  This should be removed when PR2962 is fixed.
1088  const Function *F = DAG.getMachineFunction().getFunction();
1089  bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1090  if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1091    if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1092      return MVT::v4i32;
1093    if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1094      return MVT::v4f32;
1095  }
1096  if (Subtarget->is64Bit() && Size >= 8)
1097    return MVT::i64;
1098  return MVT::i32;
1099}
1100
1101/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1102/// current function.  The returned value is a member of the
1103/// MachineJumpTableInfo::JTEntryKind enum.
1104unsigned X86TargetLowering::getJumpTableEncoding() const {
1105  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1106  // symbol.
1107  if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1108      Subtarget->isPICStyleGOT())
1109    return MachineJumpTableInfo::EK_Custom32;
1110
1111  // Otherwise, use the normal jump table encoding heuristics.
1112  return TargetLowering::getJumpTableEncoding();
1113}
1114
1115/// getPICBaseSymbol - Return the X86-32 PIC base.
1116MCSymbol *
1117X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1118                                    MCContext &Ctx) const {
1119  const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1120  return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1121                               Twine(MF->getFunctionNumber())+"$pb");
1122}
1123
1124
1125const MCExpr *
1126X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1127                                             const MachineBasicBlock *MBB,
1128                                             unsigned uid,MCContext &Ctx) const{
1129  assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1130         Subtarget->isPICStyleGOT());
1131  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1132  // entries.
1133
1134  // FIXME: @GOTOFF should be a property of MCSymbolRefExpr not in the MCSymbol.
1135  std::string Name = MBB->getSymbol(Ctx)->getName() + "@GOTOFF";
1136  return MCSymbolRefExpr::Create(Ctx.GetOrCreateSymbol(StringRef(Name)), Ctx);
1137}
1138
1139/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1140/// jumptable.
1141SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1142                                                    SelectionDAG &DAG) const {
1143  if (!Subtarget->is64Bit())
1144    // This doesn't have DebugLoc associated with it, but is not really the
1145    // same as a Register.
1146    return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1147                       getPointerTy());
1148  return Table;
1149}
1150
1151/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1152/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1153/// MCExpr.
1154const MCExpr *X86TargetLowering::
1155getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1156                             MCContext &Ctx) const {
1157  // X86-64 uses RIP relative addressing based on the jump table label.
1158  if (Subtarget->isPICStyleRIPRel())
1159    return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1160
1161  // Otherwise, the reference is relative to the PIC base.
1162  return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1163}
1164
1165/// getFunctionAlignment - Return the Log2 alignment of this function.
1166unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1167  return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1168}
1169
1170//===----------------------------------------------------------------------===//
1171//               Return Value Calling Convention Implementation
1172//===----------------------------------------------------------------------===//
1173
1174#include "X86GenCallingConv.inc"
1175
1176bool
1177X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1178                        const SmallVectorImpl<EVT> &OutTys,
1179                        const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1180                        SelectionDAG &DAG) {
1181  SmallVector<CCValAssign, 16> RVLocs;
1182  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1183                 RVLocs, *DAG.getContext());
1184  return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1185}
1186
1187SDValue
1188X86TargetLowering::LowerReturn(SDValue Chain,
1189                               CallingConv::ID CallConv, bool isVarArg,
1190                               const SmallVectorImpl<ISD::OutputArg> &Outs,
1191                               DebugLoc dl, SelectionDAG &DAG) {
1192
1193  SmallVector<CCValAssign, 16> RVLocs;
1194  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1195                 RVLocs, *DAG.getContext());
1196  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1197
1198  // If this is the first return lowered for this function, add the regs to the
1199  // liveout set for the function.
1200  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1201    for (unsigned i = 0; i != RVLocs.size(); ++i)
1202      if (RVLocs[i].isRegLoc())
1203        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1204  }
1205
1206  SDValue Flag;
1207
1208  SmallVector<SDValue, 6> RetOps;
1209  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1210  // Operand #1 = Bytes To Pop
1211  RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1212
1213  // Copy the result values into the output registers.
1214  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1215    CCValAssign &VA = RVLocs[i];
1216    assert(VA.isRegLoc() && "Can only return in registers!");
1217    SDValue ValToCopy = Outs[i].Val;
1218
1219    // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1220    // the RET instruction and handled by the FP Stackifier.
1221    if (VA.getLocReg() == X86::ST0 ||
1222        VA.getLocReg() == X86::ST1) {
1223      // If this is a copy from an xmm register to ST(0), use an FPExtend to
1224      // change the value to the FP stack register class.
1225      if (isScalarFPTypeInSSEReg(VA.getValVT()))
1226        ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1227      RetOps.push_back(ValToCopy);
1228      // Don't emit a copytoreg.
1229      continue;
1230    }
1231
1232    // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1233    // which is returned in RAX / RDX.
1234    if (Subtarget->is64Bit()) {
1235      EVT ValVT = ValToCopy.getValueType();
1236      if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1237        ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1238        if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1239          ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1240      }
1241    }
1242
1243    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1244    Flag = Chain.getValue(1);
1245  }
1246
1247  // The x86-64 ABI for returning structs by value requires that we copy
1248  // the sret argument into %rax for the return. We saved the argument into
1249  // a virtual register in the entry block, so now we copy the value out
1250  // and into %rax.
1251  if (Subtarget->is64Bit() &&
1252      DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1253    MachineFunction &MF = DAG.getMachineFunction();
1254    X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1255    unsigned Reg = FuncInfo->getSRetReturnReg();
1256    if (!Reg) {
1257      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1258      FuncInfo->setSRetReturnReg(Reg);
1259    }
1260    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1261
1262    Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1263    Flag = Chain.getValue(1);
1264
1265    // RAX now acts like a return value.
1266    MF.getRegInfo().addLiveOut(X86::RAX);
1267  }
1268
1269  RetOps[0] = Chain;  // Update chain.
1270
1271  // Add the flag if we have it.
1272  if (Flag.getNode())
1273    RetOps.push_back(Flag);
1274
1275  return DAG.getNode(X86ISD::RET_FLAG, dl,
1276                     MVT::Other, &RetOps[0], RetOps.size());
1277}
1278
1279/// LowerCallResult - Lower the result values of a call into the
1280/// appropriate copies out of appropriate physical registers.
1281///
1282SDValue
1283X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1284                                   CallingConv::ID CallConv, bool isVarArg,
1285                                   const SmallVectorImpl<ISD::InputArg> &Ins,
1286                                   DebugLoc dl, SelectionDAG &DAG,
1287                                   SmallVectorImpl<SDValue> &InVals) {
1288
1289  // Assign locations to each value returned by this call.
1290  SmallVector<CCValAssign, 16> RVLocs;
1291  bool Is64Bit = Subtarget->is64Bit();
1292  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1293                 RVLocs, *DAG.getContext());
1294  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1295
1296  // Copy all of the result registers out of their specified physreg.
1297  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1298    CCValAssign &VA = RVLocs[i];
1299    EVT CopyVT = VA.getValVT();
1300
1301    // If this is x86-64, and we disabled SSE, we can't return FP values
1302    if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1303        ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1304      llvm_report_error("SSE register return with SSE disabled");
1305    }
1306
1307    // If this is a call to a function that returns an fp value on the floating
1308    // point stack, but where we prefer to use the value in xmm registers, copy
1309    // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1310    if ((VA.getLocReg() == X86::ST0 ||
1311         VA.getLocReg() == X86::ST1) &&
1312        isScalarFPTypeInSSEReg(VA.getValVT())) {
1313      CopyVT = MVT::f80;
1314    }
1315
1316    SDValue Val;
1317    if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1318      // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1319      if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1320        Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1321                                   MVT::v2i64, InFlag).getValue(1);
1322        Val = Chain.getValue(0);
1323        Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1324                          Val, DAG.getConstant(0, MVT::i64));
1325      } else {
1326        Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1327                                   MVT::i64, InFlag).getValue(1);
1328        Val = Chain.getValue(0);
1329      }
1330      Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1331    } else {
1332      Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1333                                 CopyVT, InFlag).getValue(1);
1334      Val = Chain.getValue(0);
1335    }
1336    InFlag = Chain.getValue(2);
1337
1338    if (CopyVT != VA.getValVT()) {
1339      // Round the F80 the right size, which also moves to the appropriate xmm
1340      // register.
1341      Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1342                        // This truncation won't change the value.
1343                        DAG.getIntPtrConstant(1));
1344    }
1345
1346    InVals.push_back(Val);
1347  }
1348
1349  return Chain;
1350}
1351
1352
1353//===----------------------------------------------------------------------===//
1354//                C & StdCall & Fast Calling Convention implementation
1355//===----------------------------------------------------------------------===//
1356//  StdCall calling convention seems to be standard for many Windows' API
1357//  routines and around. It differs from C calling convention just a little:
1358//  callee should clean up the stack, not caller. Symbols should be also
1359//  decorated in some fancy way :) It doesn't support any vector arguments.
1360//  For info on fast calling convention see Fast Calling Convention (tail call)
1361//  implementation LowerX86_32FastCCCallTo.
1362
1363/// CallIsStructReturn - Determines whether a call uses struct return
1364/// semantics.
1365static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1366  if (Outs.empty())
1367    return false;
1368
1369  return Outs[0].Flags.isSRet();
1370}
1371
1372/// ArgsAreStructReturn - Determines whether a function uses struct
1373/// return semantics.
1374static bool
1375ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1376  if (Ins.empty())
1377    return false;
1378
1379  return Ins[0].Flags.isSRet();
1380}
1381
1382/// IsCalleePop - Determines whether the callee is required to pop its
1383/// own arguments. Callee pop is necessary to support tail calls.
1384bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1385  if (IsVarArg)
1386    return false;
1387
1388  switch (CallingConv) {
1389  default:
1390    return false;
1391  case CallingConv::X86_StdCall:
1392    return !Subtarget->is64Bit();
1393  case CallingConv::X86_FastCall:
1394    return !Subtarget->is64Bit();
1395  case CallingConv::Fast:
1396    return PerformTailCallOpt;
1397  }
1398}
1399
1400/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1401/// given CallingConvention value.
1402CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1403  if (Subtarget->is64Bit()) {
1404    if (Subtarget->isTargetWin64())
1405      return CC_X86_Win64_C;
1406    else
1407      return CC_X86_64_C;
1408  }
1409
1410  if (CC == CallingConv::X86_FastCall)
1411    return CC_X86_32_FastCall;
1412  else if (CC == CallingConv::Fast)
1413    return CC_X86_32_FastCC;
1414  else
1415    return CC_X86_32_C;
1416}
1417
1418/// NameDecorationForCallConv - Selects the appropriate decoration to
1419/// apply to a MachineFunction containing a given calling convention.
1420NameDecorationStyle
1421X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1422  if (CallConv == CallingConv::X86_FastCall)
1423    return FastCall;
1424  else if (CallConv == CallingConv::X86_StdCall)
1425    return StdCall;
1426  return None;
1427}
1428
1429
1430/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1431/// by "Src" to address "Dst" with size and alignment information specified by
1432/// the specific parameter attribute. The copy will be passed as a byval
1433/// function parameter.
1434static SDValue
1435CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1436                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1437                          DebugLoc dl) {
1438  SDValue SizeNode     = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1439  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1440                       /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1441}
1442
1443/// FuncIsMadeTailCallSafe - Return true if the function is being made into
1444/// a tailcall target by changing its ABI.
1445static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1446  return PerformTailCallOpt && CC == CallingConv::Fast;
1447}
1448
1449SDValue
1450X86TargetLowering::LowerMemArgument(SDValue Chain,
1451                                    CallingConv::ID CallConv,
1452                                    const SmallVectorImpl<ISD::InputArg> &Ins,
1453                                    DebugLoc dl, SelectionDAG &DAG,
1454                                    const CCValAssign &VA,
1455                                    MachineFrameInfo *MFI,
1456                                    unsigned i) {
1457  // Create the nodes corresponding to a load from this parameter slot.
1458  ISD::ArgFlagsTy Flags = Ins[i].Flags;
1459  bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1460  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1461  EVT ValVT;
1462
1463  // If value is passed by pointer we have address passed instead of the value
1464  // itself.
1465  if (VA.getLocInfo() == CCValAssign::Indirect)
1466    ValVT = VA.getLocVT();
1467  else
1468    ValVT = VA.getValVT();
1469
1470  // FIXME: For now, all byval parameter objects are marked mutable. This can be
1471  // changed with more analysis.
1472  // In case of tail call optimization mark all arguments mutable. Since they
1473  // could be overwritten by lowering of arguments in case of a tail call.
1474  int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1475                                  VA.getLocMemOffset(), isImmutable, false);
1476  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1477  if (Flags.isByVal())
1478    return FIN;
1479  return DAG.getLoad(ValVT, dl, Chain, FIN,
1480                     PseudoSourceValue::getFixedStack(FI), 0);
1481}
1482
1483SDValue
1484X86TargetLowering::LowerFormalArguments(SDValue Chain,
1485                                        CallingConv::ID CallConv,
1486                                        bool isVarArg,
1487                                      const SmallVectorImpl<ISD::InputArg> &Ins,
1488                                        DebugLoc dl,
1489                                        SelectionDAG &DAG,
1490                                        SmallVectorImpl<SDValue> &InVals) {
1491
1492  MachineFunction &MF = DAG.getMachineFunction();
1493  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1494
1495  const Function* Fn = MF.getFunction();
1496  if (Fn->hasExternalLinkage() &&
1497      Subtarget->isTargetCygMing() &&
1498      Fn->getName() == "main")
1499    FuncInfo->setForceFramePointer(true);
1500
1501  // Decorate the function name.
1502  FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1503
1504  MachineFrameInfo *MFI = MF.getFrameInfo();
1505  bool Is64Bit = Subtarget->is64Bit();
1506  bool IsWin64 = Subtarget->isTargetWin64();
1507
1508  assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1509         "Var args not supported with calling convention fastcc");
1510
1511  // Assign locations to all of the incoming arguments.
1512  SmallVector<CCValAssign, 16> ArgLocs;
1513  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1514                 ArgLocs, *DAG.getContext());
1515  CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1516
1517  unsigned LastVal = ~0U;
1518  SDValue ArgValue;
1519  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1520    CCValAssign &VA = ArgLocs[i];
1521    // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1522    // places.
1523    assert(VA.getValNo() != LastVal &&
1524           "Don't support value assigned to multiple locs yet");
1525    LastVal = VA.getValNo();
1526
1527    if (VA.isRegLoc()) {
1528      EVT RegVT = VA.getLocVT();
1529      TargetRegisterClass *RC = NULL;
1530      if (RegVT == MVT::i32)
1531        RC = X86::GR32RegisterClass;
1532      else if (Is64Bit && RegVT == MVT::i64)
1533        RC = X86::GR64RegisterClass;
1534      else if (RegVT == MVT::f32)
1535        RC = X86::FR32RegisterClass;
1536      else if (RegVT == MVT::f64)
1537        RC = X86::FR64RegisterClass;
1538      else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1539        RC = X86::VR128RegisterClass;
1540      else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1541        RC = X86::VR64RegisterClass;
1542      else
1543        llvm_unreachable("Unknown argument type!");
1544
1545      unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1546      ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1547
1548      // If this is an 8 or 16-bit value, it is really passed promoted to 32
1549      // bits.  Insert an assert[sz]ext to capture this, then truncate to the
1550      // right size.
1551      if (VA.getLocInfo() == CCValAssign::SExt)
1552        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1553                               DAG.getValueType(VA.getValVT()));
1554      else if (VA.getLocInfo() == CCValAssign::ZExt)
1555        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1556                               DAG.getValueType(VA.getValVT()));
1557      else if (VA.getLocInfo() == CCValAssign::BCvt)
1558        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1559
1560      if (VA.isExtInLoc()) {
1561        // Handle MMX values passed in XMM regs.
1562        if (RegVT.isVector()) {
1563          ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1564                                 ArgValue, DAG.getConstant(0, MVT::i64));
1565          ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1566        } else
1567          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1568      }
1569    } else {
1570      assert(VA.isMemLoc());
1571      ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1572    }
1573
1574    // If value is passed via pointer - do a load.
1575    if (VA.getLocInfo() == CCValAssign::Indirect)
1576      ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1577
1578    InVals.push_back(ArgValue);
1579  }
1580
1581  // The x86-64 ABI for returning structs by value requires that we copy
1582  // the sret argument into %rax for the return. Save the argument into
1583  // a virtual register so that we can access it from the return points.
1584  if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1585    X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1586    unsigned Reg = FuncInfo->getSRetReturnReg();
1587    if (!Reg) {
1588      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1589      FuncInfo->setSRetReturnReg(Reg);
1590    }
1591    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1592    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1593  }
1594
1595  unsigned StackSize = CCInfo.getNextStackOffset();
1596  // Align stack specially for tail calls.
1597  if (FuncIsMadeTailCallSafe(CallConv))
1598    StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1599
1600  // If the function takes variable number of arguments, make a frame index for
1601  // the start of the first vararg value... for expansion of llvm.va_start.
1602  if (isVarArg) {
1603    if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1604      VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1605    }
1606    if (Is64Bit) {
1607      unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1608
1609      // FIXME: We should really autogenerate these arrays
1610      static const unsigned GPR64ArgRegsWin64[] = {
1611        X86::RCX, X86::RDX, X86::R8,  X86::R9
1612      };
1613      static const unsigned XMMArgRegsWin64[] = {
1614        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1615      };
1616      static const unsigned GPR64ArgRegs64Bit[] = {
1617        X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1618      };
1619      static const unsigned XMMArgRegs64Bit[] = {
1620        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1621        X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1622      };
1623      const unsigned *GPR64ArgRegs, *XMMArgRegs;
1624
1625      if (IsWin64) {
1626        TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1627        GPR64ArgRegs = GPR64ArgRegsWin64;
1628        XMMArgRegs = XMMArgRegsWin64;
1629      } else {
1630        TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1631        GPR64ArgRegs = GPR64ArgRegs64Bit;
1632        XMMArgRegs = XMMArgRegs64Bit;
1633      }
1634      unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1635                                                       TotalNumIntRegs);
1636      unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1637                                                       TotalNumXMMRegs);
1638
1639      bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1640      assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1641             "SSE register cannot be used when SSE is disabled!");
1642      assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1643             "SSE register cannot be used when SSE is disabled!");
1644      if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1645        // Kernel mode asks for SSE to be disabled, so don't push them
1646        // on the stack.
1647        TotalNumXMMRegs = 0;
1648
1649      // For X86-64, if there are vararg parameters that are passed via
1650      // registers, then we must store them to their spots on the stack so they
1651      // may be loaded by deferencing the result of va_next.
1652      VarArgsGPOffset = NumIntRegs * 8;
1653      VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1654      RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1655                                                 TotalNumXMMRegs * 16, 16,
1656                                                 false);
1657
1658      // Store the integer parameter registers.
1659      SmallVector<SDValue, 8> MemOps;
1660      SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1661      unsigned Offset = VarArgsGPOffset;
1662      for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1663        SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1664                                  DAG.getIntPtrConstant(Offset));
1665        unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1666                                     X86::GR64RegisterClass);
1667        SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1668        SDValue Store =
1669          DAG.getStore(Val.getValue(1), dl, Val, FIN,
1670                       PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1671                       Offset);
1672        MemOps.push_back(Store);
1673        Offset += 8;
1674      }
1675
1676      if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1677        // Now store the XMM (fp + vector) parameter registers.
1678        SmallVector<SDValue, 11> SaveXMMOps;
1679        SaveXMMOps.push_back(Chain);
1680
1681        unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1682        SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1683        SaveXMMOps.push_back(ALVal);
1684
1685        SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1686        SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1687
1688        for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1689          unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1690                                       X86::VR128RegisterClass);
1691          SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1692          SaveXMMOps.push_back(Val);
1693        }
1694        MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1695                                     MVT::Other,
1696                                     &SaveXMMOps[0], SaveXMMOps.size()));
1697      }
1698
1699      if (!MemOps.empty())
1700        Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1701                            &MemOps[0], MemOps.size());
1702    }
1703  }
1704
1705  // Some CCs need callee pop.
1706  if (IsCalleePop(isVarArg, CallConv)) {
1707    BytesToPopOnReturn  = StackSize; // Callee pops everything.
1708  } else {
1709    BytesToPopOnReturn  = 0; // Callee pops nothing.
1710    // If this is an sret function, the return should pop the hidden pointer.
1711    if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1712      BytesToPopOnReturn = 4;
1713  }
1714
1715  if (!Is64Bit) {
1716    RegSaveFrameIndex = 0xAAAAAAA;   // RegSaveFrameIndex is X86-64 only.
1717    if (CallConv == CallingConv::X86_FastCall)
1718      VarArgsFrameIndex = 0xAAAAAAA;   // fastcc functions can't have varargs.
1719  }
1720
1721  FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1722
1723  return Chain;
1724}
1725
1726SDValue
1727X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1728                                    SDValue StackPtr, SDValue Arg,
1729                                    DebugLoc dl, SelectionDAG &DAG,
1730                                    const CCValAssign &VA,
1731                                    ISD::ArgFlagsTy Flags) {
1732  const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1733  unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1734  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1735  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1736  if (Flags.isByVal()) {
1737    return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1738  }
1739  return DAG.getStore(Chain, dl, Arg, PtrOff,
1740                      PseudoSourceValue::getStack(), LocMemOffset);
1741}
1742
1743/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1744/// optimization is performed and it is required.
1745SDValue
1746X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1747                                           SDValue &OutRetAddr, SDValue Chain,
1748                                           bool IsTailCall, bool Is64Bit,
1749                                           int FPDiff, DebugLoc dl) {
1750  if (!IsTailCall || FPDiff==0) return Chain;
1751
1752  // Adjust the Return address stack slot.
1753  EVT VT = getPointerTy();
1754  OutRetAddr = getReturnAddressFrameIndex(DAG);
1755
1756  // Load the "old" Return address.
1757  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1758  return SDValue(OutRetAddr.getNode(), 1);
1759}
1760
1761/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1762/// optimization is performed and it is required (FPDiff!=0).
1763static SDValue
1764EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1765                         SDValue Chain, SDValue RetAddrFrIdx,
1766                         bool Is64Bit, int FPDiff, DebugLoc dl) {
1767  // Store the return address to the appropriate stack slot.
1768  if (!FPDiff) return Chain;
1769  // Calculate the new stack slot for the return address.
1770  int SlotSize = Is64Bit ? 8 : 4;
1771  int NewReturnAddrFI =
1772    MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false);
1773  EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1774  SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1775  Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1776                       PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1777  return Chain;
1778}
1779
1780SDValue
1781X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1782                             CallingConv::ID CallConv, bool isVarArg,
1783                             bool &isTailCall,
1784                             const SmallVectorImpl<ISD::OutputArg> &Outs,
1785                             const SmallVectorImpl<ISD::InputArg> &Ins,
1786                             DebugLoc dl, SelectionDAG &DAG,
1787                             SmallVectorImpl<SDValue> &InVals) {
1788  MachineFunction &MF = DAG.getMachineFunction();
1789  bool Is64Bit        = Subtarget->is64Bit();
1790  bool IsStructRet    = CallIsStructReturn(Outs);
1791
1792  if (isTailCall)
1793    // Check if it's really possible to do a tail call.
1794    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
1795                                                   Outs, Ins, DAG);
1796
1797  assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1798         "Var args not supported with calling convention fastcc");
1799
1800  // Analyze operands of the call, assigning locations to each operand.
1801  SmallVector<CCValAssign, 16> ArgLocs;
1802  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1803                 ArgLocs, *DAG.getContext());
1804  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1805
1806  // Get a count of how many bytes are to be pushed on the stack.
1807  unsigned NumBytes = CCInfo.getNextStackOffset();
1808  if (FuncIsMadeTailCallSafe(CallConv))
1809    NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1810  else if (isTailCall && !PerformTailCallOpt)
1811    // This is a sibcall. The memory operands are available in caller's
1812    // own caller's stack.
1813    NumBytes = 0;
1814
1815  int FPDiff = 0;
1816  if (isTailCall) {
1817    ++NumTailCalls;
1818
1819    // Lower arguments at fp - stackoffset + fpdiff.
1820    unsigned NumBytesCallerPushed =
1821      MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1822    FPDiff = NumBytesCallerPushed - NumBytes;
1823
1824    // Set the delta of movement of the returnaddr stackslot.
1825    // But only set if delta is greater than previous delta.
1826    if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1827      MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1828  }
1829
1830  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1831
1832  SDValue RetAddrFrIdx;
1833  // Load return adress for tail calls.
1834  Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1835                                  FPDiff, dl);
1836
1837  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1838  SmallVector<SDValue, 8> MemOpChains;
1839  SDValue StackPtr;
1840
1841  // Walk the register/memloc assignments, inserting copies/loads.  In the case
1842  // of tail call optimization arguments are handle later.
1843  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1844    CCValAssign &VA = ArgLocs[i];
1845    EVT RegVT = VA.getLocVT();
1846    SDValue Arg = Outs[i].Val;
1847    ISD::ArgFlagsTy Flags = Outs[i].Flags;
1848    bool isByVal = Flags.isByVal();
1849
1850    // Promote the value if needed.
1851    switch (VA.getLocInfo()) {
1852    default: llvm_unreachable("Unknown loc info!");
1853    case CCValAssign::Full: break;
1854    case CCValAssign::SExt:
1855      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1856      break;
1857    case CCValAssign::ZExt:
1858      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1859      break;
1860    case CCValAssign::AExt:
1861      if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1862        // Special case: passing MMX values in XMM registers.
1863        Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1864        Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1865        Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1866      } else
1867        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1868      break;
1869    case CCValAssign::BCvt:
1870      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1871      break;
1872    case CCValAssign::Indirect: {
1873      // Store the argument.
1874      SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1875      int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1876      Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1877                           PseudoSourceValue::getFixedStack(FI), 0);
1878      Arg = SpillSlot;
1879      break;
1880    }
1881    }
1882
1883    if (VA.isRegLoc()) {
1884      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1885    } else {
1886      if (!isTailCall || (isTailCall && isByVal)) {
1887        assert(VA.isMemLoc());
1888        if (StackPtr.getNode() == 0)
1889          StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1890
1891        MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1892                                               dl, DAG, VA, Flags));
1893      }
1894    }
1895  }
1896
1897  if (!MemOpChains.empty())
1898    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1899                        &MemOpChains[0], MemOpChains.size());
1900
1901  // Build a sequence of copy-to-reg nodes chained together with token chain
1902  // and flag operands which copy the outgoing args into registers.
1903  SDValue InFlag;
1904  // Tail call byval lowering might overwrite argument registers so in case of
1905  // tail call optimization the copies to registers are lowered later.
1906  if (!isTailCall)
1907    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1908      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1909                               RegsToPass[i].second, InFlag);
1910      InFlag = Chain.getValue(1);
1911    }
1912
1913
1914  if (Subtarget->isPICStyleGOT()) {
1915    // ELF / PIC requires GOT in the EBX register before function calls via PLT
1916    // GOT pointer.
1917    if (!isTailCall) {
1918      Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1919                               DAG.getNode(X86ISD::GlobalBaseReg,
1920                                           DebugLoc::getUnknownLoc(),
1921                                           getPointerTy()),
1922                               InFlag);
1923      InFlag = Chain.getValue(1);
1924    } else {
1925      // If we are tail calling and generating PIC/GOT style code load the
1926      // address of the callee into ECX. The value in ecx is used as target of
1927      // the tail jump. This is done to circumvent the ebx/callee-saved problem
1928      // for tail calls on PIC/GOT architectures. Normally we would just put the
1929      // address of GOT into ebx and then call target@PLT. But for tail calls
1930      // ebx would be restored (since ebx is callee saved) before jumping to the
1931      // target@PLT.
1932
1933      // Note: The actual moving to ECX is done further down.
1934      GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1935      if (G && !G->getGlobal()->hasHiddenVisibility() &&
1936          !G->getGlobal()->hasProtectedVisibility())
1937        Callee = LowerGlobalAddress(Callee, DAG);
1938      else if (isa<ExternalSymbolSDNode>(Callee))
1939        Callee = LowerExternalSymbol(Callee, DAG);
1940    }
1941  }
1942
1943  if (Is64Bit && isVarArg) {
1944    // From AMD64 ABI document:
1945    // For calls that may call functions that use varargs or stdargs
1946    // (prototype-less calls or calls to functions containing ellipsis (...) in
1947    // the declaration) %al is used as hidden argument to specify the number
1948    // of SSE registers used. The contents of %al do not need to match exactly
1949    // the number of registers, but must be an ubound on the number of SSE
1950    // registers used and is in the range 0 - 8 inclusive.
1951
1952    // FIXME: Verify this on Win64
1953    // Count the number of XMM registers allocated.
1954    static const unsigned XMMArgRegs[] = {
1955      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1956      X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1957    };
1958    unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1959    assert((Subtarget->hasSSE1() || !NumXMMRegs)
1960           && "SSE registers cannot be used when SSE is disabled");
1961
1962    Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1963                             DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1964    InFlag = Chain.getValue(1);
1965  }
1966
1967
1968  // For tail calls lower the arguments to the 'real' stack slot.
1969  if (isTailCall) {
1970    // Force all the incoming stack arguments to be loaded from the stack
1971    // before any new outgoing arguments are stored to the stack, because the
1972    // outgoing stack slots may alias the incoming argument stack slots, and
1973    // the alias isn't otherwise explicit. This is slightly more conservative
1974    // than necessary, because it means that each store effectively depends
1975    // on every argument instead of just those arguments it would clobber.
1976    SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1977
1978    SmallVector<SDValue, 8> MemOpChains2;
1979    SDValue FIN;
1980    int FI = 0;
1981    // Do not flag preceeding copytoreg stuff together with the following stuff.
1982    InFlag = SDValue();
1983    if (PerformTailCallOpt) {
1984      for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1985        CCValAssign &VA = ArgLocs[i];
1986        if (VA.isRegLoc())
1987          continue;
1988        assert(VA.isMemLoc());
1989        SDValue Arg = Outs[i].Val;
1990        ISD::ArgFlagsTy Flags = Outs[i].Flags;
1991        // Create frame index.
1992        int32_t Offset = VA.getLocMemOffset()+FPDiff;
1993        uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1994        FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1995        FIN = DAG.getFrameIndex(FI, getPointerTy());
1996
1997        if (Flags.isByVal()) {
1998          // Copy relative to framepointer.
1999          SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2000          if (StackPtr.getNode() == 0)
2001            StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2002                                          getPointerTy());
2003          Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2004
2005          MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2006                                                           ArgChain,
2007                                                           Flags, DAG, dl));
2008        } else {
2009          // Store relative to framepointer.
2010          MemOpChains2.push_back(
2011            DAG.getStore(ArgChain, dl, Arg, FIN,
2012                         PseudoSourceValue::getFixedStack(FI), 0));
2013        }
2014      }
2015    }
2016
2017    if (!MemOpChains2.empty())
2018      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2019                          &MemOpChains2[0], MemOpChains2.size());
2020
2021    // Copy arguments to their registers.
2022    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2023      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2024                               RegsToPass[i].second, InFlag);
2025      InFlag = Chain.getValue(1);
2026    }
2027    InFlag =SDValue();
2028
2029    // Store the return address to the appropriate stack slot.
2030    Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2031                                     FPDiff, dl);
2032  }
2033
2034  bool WasGlobalOrExternal = false;
2035  if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2036    assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2037    // In the 64-bit large code model, we have to make all calls
2038    // through a register, since the call instruction's 32-bit
2039    // pc-relative offset may not be large enough to hold the whole
2040    // address.
2041  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2042    WasGlobalOrExternal = true;
2043    // If the callee is a GlobalAddress node (quite common, every direct call
2044    // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2045    // it.
2046
2047    // We should use extra load for direct calls to dllimported functions in
2048    // non-JIT mode.
2049    GlobalValue *GV = G->getGlobal();
2050    if (!GV->hasDLLImportLinkage()) {
2051      unsigned char OpFlags = 0;
2052
2053      // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2054      // external symbols most go through the PLT in PIC mode.  If the symbol
2055      // has hidden or protected visibility, or if it is static or local, then
2056      // we don't need to use the PLT - we can directly call it.
2057      if (Subtarget->isTargetELF() &&
2058          getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2059          GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2060        OpFlags = X86II::MO_PLT;
2061      } else if (Subtarget->isPICStyleStubAny() &&
2062               (GV->isDeclaration() || GV->isWeakForLinker()) &&
2063               Subtarget->getDarwinVers() < 9) {
2064        // PC-relative references to external symbols should go through $stub,
2065        // unless we're building with the leopard linker or later, which
2066        // automatically synthesizes these stubs.
2067        OpFlags = X86II::MO_DARWIN_STUB;
2068      }
2069
2070      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2071                                          G->getOffset(), OpFlags);
2072    }
2073  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2074    WasGlobalOrExternal = true;
2075    unsigned char OpFlags = 0;
2076
2077    // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2078    // symbols should go through the PLT.
2079    if (Subtarget->isTargetELF() &&
2080        getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2081      OpFlags = X86II::MO_PLT;
2082    } else if (Subtarget->isPICStyleStubAny() &&
2083             Subtarget->getDarwinVers() < 9) {
2084      // PC-relative references to external symbols should go through $stub,
2085      // unless we're building with the leopard linker or later, which
2086      // automatically synthesizes these stubs.
2087      OpFlags = X86II::MO_DARWIN_STUB;
2088    }
2089
2090    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2091                                         OpFlags);
2092  }
2093
2094  if (isTailCall && !WasGlobalOrExternal) {
2095    unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2096
2097    Chain = DAG.getCopyToReg(Chain,  dl,
2098                             DAG.getRegister(Opc, getPointerTy()),
2099                             Callee,InFlag);
2100    Callee = DAG.getRegister(Opc, getPointerTy());
2101    // Add register as live out.
2102    MF.getRegInfo().addLiveOut(Opc);
2103  }
2104
2105  // Returns a chain & a flag for retval copy to use.
2106  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2107  SmallVector<SDValue, 8> Ops;
2108
2109  if (isTailCall) {
2110    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2111                           DAG.getIntPtrConstant(0, true), InFlag);
2112    InFlag = Chain.getValue(1);
2113  }
2114
2115  Ops.push_back(Chain);
2116  Ops.push_back(Callee);
2117
2118  if (isTailCall)
2119    Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2120
2121  // Add argument registers to the end of the list so that they are known live
2122  // into the call.
2123  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2124    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2125                                  RegsToPass[i].second.getValueType()));
2126
2127  // Add an implicit use GOT pointer in EBX.
2128  if (!isTailCall && Subtarget->isPICStyleGOT())
2129    Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2130
2131  // Add an implicit use of AL for x86 vararg functions.
2132  if (Is64Bit && isVarArg)
2133    Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2134
2135  if (InFlag.getNode())
2136    Ops.push_back(InFlag);
2137
2138  if (isTailCall) {
2139    // If this is the first return lowered for this function, add the regs
2140    // to the liveout set for the function.
2141    if (MF.getRegInfo().liveout_empty()) {
2142      SmallVector<CCValAssign, 16> RVLocs;
2143      CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2144                     *DAG.getContext());
2145      CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2146      for (unsigned i = 0; i != RVLocs.size(); ++i)
2147        if (RVLocs[i].isRegLoc())
2148          MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2149    }
2150
2151    assert(((Callee.getOpcode() == ISD::Register &&
2152               (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2153                cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
2154              Callee.getOpcode() == ISD::TargetExternalSymbol ||
2155              Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2156           "Expecting a global address, external symbol, or scratch register");
2157
2158    return DAG.getNode(X86ISD::TC_RETURN, dl,
2159                       NodeTys, &Ops[0], Ops.size());
2160  }
2161
2162  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2163  InFlag = Chain.getValue(1);
2164
2165  // Create the CALLSEQ_END node.
2166  unsigned NumBytesForCalleeToPush;
2167  if (IsCalleePop(isVarArg, CallConv))
2168    NumBytesForCalleeToPush = NumBytes;    // Callee pops everything
2169  else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2170    // If this is is a call to a struct-return function, the callee
2171    // pops the hidden struct pointer, so we have to push it back.
2172    // This is common for Darwin/X86, Linux & Mingw32 targets.
2173    NumBytesForCalleeToPush = 4;
2174  else
2175    NumBytesForCalleeToPush = 0;  // Callee pops nothing.
2176
2177  // Returns a flag for retval copy to use.
2178  Chain = DAG.getCALLSEQ_END(Chain,
2179                             DAG.getIntPtrConstant(NumBytes, true),
2180                             DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2181                                                   true),
2182                             InFlag);
2183  InFlag = Chain.getValue(1);
2184
2185  // Handle result values, copying them out of physregs into vregs that we
2186  // return.
2187  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2188                         Ins, dl, DAG, InVals);
2189}
2190
2191
2192//===----------------------------------------------------------------------===//
2193//                Fast Calling Convention (tail call) implementation
2194//===----------------------------------------------------------------------===//
2195
2196//  Like std call, callee cleans arguments, convention except that ECX is
2197//  reserved for storing the tail called function address. Only 2 registers are
2198//  free for argument passing (inreg). Tail call optimization is performed
2199//  provided:
2200//                * tailcallopt is enabled
2201//                * caller/callee are fastcc
2202//  On X86_64 architecture with GOT-style position independent code only local
2203//  (within module) calls are supported at the moment.
2204//  To keep the stack aligned according to platform abi the function
2205//  GetAlignedArgumentStackSize ensures that argument delta is always multiples
2206//  of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2207//  If a tail called function callee has more arguments than the caller the
2208//  caller needs to make sure that there is room to move the RETADDR to. This is
2209//  achieved by reserving an area the size of the argument delta right after the
2210//  original REtADDR, but before the saved framepointer or the spilled registers
2211//  e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2212//  stack layout:
2213//    arg1
2214//    arg2
2215//    RETADDR
2216//    [ new RETADDR
2217//      move area ]
2218//    (possible EBP)
2219//    ESI
2220//    EDI
2221//    local1 ..
2222
2223/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2224/// for a 16 byte align requirement.
2225unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2226                                                        SelectionDAG& DAG) {
2227  MachineFunction &MF = DAG.getMachineFunction();
2228  const TargetMachine &TM = MF.getTarget();
2229  const TargetFrameInfo &TFI = *TM.getFrameInfo();
2230  unsigned StackAlignment = TFI.getStackAlignment();
2231  uint64_t AlignMask = StackAlignment - 1;
2232  int64_t Offset = StackSize;
2233  uint64_t SlotSize = TD->getPointerSize();
2234  if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2235    // Number smaller than 12 so just add the difference.
2236    Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2237  } else {
2238    // Mask out lower bits, add stackalignment once plus the 12 bytes.
2239    Offset = ((~AlignMask) & Offset) + StackAlignment +
2240      (StackAlignment-SlotSize);
2241  }
2242  return Offset;
2243}
2244
2245/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2246/// for tail call optimization. Targets which want to do tail call
2247/// optimization should implement this function.
2248bool
2249X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2250                                                     CallingConv::ID CalleeCC,
2251                                                     bool isVarArg,
2252                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
2253                                    const SmallVectorImpl<ISD::InputArg> &Ins,
2254                                                     SelectionDAG& DAG) const {
2255  if (CalleeCC != CallingConv::Fast &&
2256      CalleeCC != CallingConv::C)
2257    return false;
2258
2259  // If -tailcallopt is specified, make fastcc functions tail-callable.
2260  const Function *CallerF = DAG.getMachineFunction().getFunction();
2261  if (PerformTailCallOpt) {
2262    if (CalleeCC == CallingConv::Fast &&
2263        CallerF->getCallingConv() == CalleeCC)
2264      return true;
2265    return false;
2266  }
2267
2268
2269  // Look for obvious safe cases to perform tail call optimization that does not
2270  // requite ABI changes. This is what gcc calls sibcall.
2271
2272  // Do not tail call optimize vararg calls for now.
2273  if (isVarArg)
2274    return false;
2275
2276  // If the callee takes no arguments then go on to check the results of the
2277  // call.
2278  if (!Outs.empty()) {
2279    // Check if stack adjustment is needed. For now, do not do this if any
2280    // argument is passed on the stack.
2281    SmallVector<CCValAssign, 16> ArgLocs;
2282    CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2283                   ArgLocs, *DAG.getContext());
2284    CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2285    if (CCInfo.getNextStackOffset()) {
2286      MachineFunction &MF = DAG.getMachineFunction();
2287      if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2288        return false;
2289      if (Subtarget->isTargetWin64())
2290        // Win64 ABI has additional complications.
2291        return false;
2292
2293      // Check if the arguments are already laid out in the right way as
2294      // the caller's fixed stack objects.
2295      MachineFrameInfo *MFI = MF.getFrameInfo();
2296      for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2297        CCValAssign &VA = ArgLocs[i];
2298        EVT RegVT = VA.getLocVT();
2299        SDValue Arg = Outs[i].Val;
2300        ISD::ArgFlagsTy Flags = Outs[i].Flags;
2301        if (Flags.isByVal())
2302          return false; // TODO
2303        if (VA.getLocInfo() == CCValAssign::Indirect)
2304          return false;
2305        if (!VA.isRegLoc()) {
2306          LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg);
2307          if (!Ld)
2308            return false;
2309          SDValue Ptr = Ld->getBasePtr();
2310          FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2311          if (!FINode)
2312            return false;
2313          int FI = FINode->getIndex();
2314          if (!MFI->isFixedObjectIndex(FI))
2315            return false;
2316          if (VA.getLocMemOffset() != MFI->getObjectOffset(FI))
2317            return false;
2318        }
2319      }
2320    }
2321  }
2322
2323  // If the caller does not return a value, then this is obviously safe.
2324  // This is one case where it's safe to perform this optimization even
2325  // if the return types do not match.
2326  const Type *CallerRetTy = CallerF->getReturnType();
2327  if (CallerRetTy->isVoidTy())
2328    return true;
2329
2330  // If the return types match, then it's safe.
2331  // Don't tail call optimize recursive call.
2332  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2333  if (!G) return false;  // FIXME: common external symbols?
2334  if (const Function *CalleeF = dyn_cast<Function>(G->getGlobal())) {
2335    const Type *CalleeRetTy = CalleeF->getReturnType();
2336    return CallerRetTy == CalleeRetTy;
2337  }
2338  return false;
2339}
2340
2341FastISel *
2342X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2343                            DwarfWriter *dw,
2344                            DenseMap<const Value *, unsigned> &vm,
2345                            DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2346                            DenseMap<const AllocaInst *, int> &am
2347#ifndef NDEBUG
2348                          , SmallSet<Instruction*, 8> &cil
2349#endif
2350                                  ) {
2351  return X86::createFastISel(mf, mmo, dw, vm, bm, am
2352#ifndef NDEBUG
2353                             , cil
2354#endif
2355                             );
2356}
2357
2358
2359//===----------------------------------------------------------------------===//
2360//                           Other Lowering Hooks
2361//===----------------------------------------------------------------------===//
2362
2363
2364SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2365  MachineFunction &MF = DAG.getMachineFunction();
2366  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2367  int ReturnAddrIndex = FuncInfo->getRAIndex();
2368
2369  if (ReturnAddrIndex == 0) {
2370    // Set up a frame object for the return address.
2371    uint64_t SlotSize = TD->getPointerSize();
2372    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2373                                                           true, false);
2374    FuncInfo->setRAIndex(ReturnAddrIndex);
2375  }
2376
2377  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2378}
2379
2380
2381bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2382                                       bool hasSymbolicDisplacement) {
2383  // Offset should fit into 32 bit immediate field.
2384  if (!isInt32(Offset))
2385    return false;
2386
2387  // If we don't have a symbolic displacement - we don't have any extra
2388  // restrictions.
2389  if (!hasSymbolicDisplacement)
2390    return true;
2391
2392  // FIXME: Some tweaks might be needed for medium code model.
2393  if (M != CodeModel::Small && M != CodeModel::Kernel)
2394    return false;
2395
2396  // For small code model we assume that latest object is 16MB before end of 31
2397  // bits boundary. We may also accept pretty large negative constants knowing
2398  // that all objects are in the positive half of address space.
2399  if (M == CodeModel::Small && Offset < 16*1024*1024)
2400    return true;
2401
2402  // For kernel code model we know that all object resist in the negative half
2403  // of 32bits address space. We may not accept negative offsets, since they may
2404  // be just off and we may accept pretty large positive ones.
2405  if (M == CodeModel::Kernel && Offset > 0)
2406    return true;
2407
2408  return false;
2409}
2410
2411/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2412/// specific condition code, returning the condition code and the LHS/RHS of the
2413/// comparison to make.
2414static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2415                               SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2416  if (!isFP) {
2417    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2418      if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2419        // X > -1   -> X == 0, jump !sign.
2420        RHS = DAG.getConstant(0, RHS.getValueType());
2421        return X86::COND_NS;
2422      } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2423        // X < 0   -> X == 0, jump on sign.
2424        return X86::COND_S;
2425      } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2426        // X < 1   -> X <= 0
2427        RHS = DAG.getConstant(0, RHS.getValueType());
2428        return X86::COND_LE;
2429      }
2430    }
2431
2432    switch (SetCCOpcode) {
2433    default: llvm_unreachable("Invalid integer condition!");
2434    case ISD::SETEQ:  return X86::COND_E;
2435    case ISD::SETGT:  return X86::COND_G;
2436    case ISD::SETGE:  return X86::COND_GE;
2437    case ISD::SETLT:  return X86::COND_L;
2438    case ISD::SETLE:  return X86::COND_LE;
2439    case ISD::SETNE:  return X86::COND_NE;
2440    case ISD::SETULT: return X86::COND_B;
2441    case ISD::SETUGT: return X86::COND_A;
2442    case ISD::SETULE: return X86::COND_BE;
2443    case ISD::SETUGE: return X86::COND_AE;
2444    }
2445  }
2446
2447  // First determine if it is required or is profitable to flip the operands.
2448
2449  // If LHS is a foldable load, but RHS is not, flip the condition.
2450  if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2451      !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2452    SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2453    std::swap(LHS, RHS);
2454  }
2455
2456  switch (SetCCOpcode) {
2457  default: break;
2458  case ISD::SETOLT:
2459  case ISD::SETOLE:
2460  case ISD::SETUGT:
2461  case ISD::SETUGE:
2462    std::swap(LHS, RHS);
2463    break;
2464  }
2465
2466  // On a floating point condition, the flags are set as follows:
2467  // ZF  PF  CF   op
2468  //  0 | 0 | 0 | X > Y
2469  //  0 | 0 | 1 | X < Y
2470  //  1 | 0 | 0 | X == Y
2471  //  1 | 1 | 1 | unordered
2472  switch (SetCCOpcode) {
2473  default: llvm_unreachable("Condcode should be pre-legalized away");
2474  case ISD::SETUEQ:
2475  case ISD::SETEQ:   return X86::COND_E;
2476  case ISD::SETOLT:              // flipped
2477  case ISD::SETOGT:
2478  case ISD::SETGT:   return X86::COND_A;
2479  case ISD::SETOLE:              // flipped
2480  case ISD::SETOGE:
2481  case ISD::SETGE:   return X86::COND_AE;
2482  case ISD::SETUGT:              // flipped
2483  case ISD::SETULT:
2484  case ISD::SETLT:   return X86::COND_B;
2485  case ISD::SETUGE:              // flipped
2486  case ISD::SETULE:
2487  case ISD::SETLE:   return X86::COND_BE;
2488  case ISD::SETONE:
2489  case ISD::SETNE:   return X86::COND_NE;
2490  case ISD::SETUO:   return X86::COND_P;
2491  case ISD::SETO:    return X86::COND_NP;
2492  case ISD::SETOEQ:
2493  case ISD::SETUNE:  return X86::COND_INVALID;
2494  }
2495}
2496
2497/// hasFPCMov - is there a floating point cmov for the specific X86 condition
2498/// code. Current x86 isa includes the following FP cmov instructions:
2499/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2500static bool hasFPCMov(unsigned X86CC) {
2501  switch (X86CC) {
2502  default:
2503    return false;
2504  case X86::COND_B:
2505  case X86::COND_BE:
2506  case X86::COND_E:
2507  case X86::COND_P:
2508  case X86::COND_A:
2509  case X86::COND_AE:
2510  case X86::COND_NE:
2511  case X86::COND_NP:
2512    return true;
2513  }
2514}
2515
2516/// isFPImmLegal - Returns true if the target can instruction select the
2517/// specified FP immediate natively. If false, the legalizer will
2518/// materialize the FP immediate as a load from a constant pool.
2519bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2520  for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2521    if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2522      return true;
2523  }
2524  return false;
2525}
2526
2527/// isUndefOrInRange - Return true if Val is undef or if its value falls within
2528/// the specified range (L, H].
2529static bool isUndefOrInRange(int Val, int Low, int Hi) {
2530  return (Val < 0) || (Val >= Low && Val < Hi);
2531}
2532
2533/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2534/// specified value.
2535static bool isUndefOrEqual(int Val, int CmpVal) {
2536  if (Val < 0 || Val == CmpVal)
2537    return true;
2538  return false;
2539}
2540
2541/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2542/// is suitable for input to PSHUFD or PSHUFW.  That is, it doesn't reference
2543/// the second operand.
2544static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2545  if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2546    return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2547  if (VT == MVT::v2f64 || VT == MVT::v2i64)
2548    return (Mask[0] < 2 && Mask[1] < 2);
2549  return false;
2550}
2551
2552bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2553  SmallVector<int, 8> M;
2554  N->getMask(M);
2555  return ::isPSHUFDMask(M, N->getValueType(0));
2556}
2557
2558/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2559/// is suitable for input to PSHUFHW.
2560static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2561  if (VT != MVT::v8i16)
2562    return false;
2563
2564  // Lower quadword copied in order or undef.
2565  for (int i = 0; i != 4; ++i)
2566    if (Mask[i] >= 0 && Mask[i] != i)
2567      return false;
2568
2569  // Upper quadword shuffled.
2570  for (int i = 4; i != 8; ++i)
2571    if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2572      return false;
2573
2574  return true;
2575}
2576
2577bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2578  SmallVector<int, 8> M;
2579  N->getMask(M);
2580  return ::isPSHUFHWMask(M, N->getValueType(0));
2581}
2582
2583/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2584/// is suitable for input to PSHUFLW.
2585static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2586  if (VT != MVT::v8i16)
2587    return false;
2588
2589  // Upper quadword copied in order.
2590  for (int i = 4; i != 8; ++i)
2591    if (Mask[i] >= 0 && Mask[i] != i)
2592      return false;
2593
2594  // Lower quadword shuffled.
2595  for (int i = 0; i != 4; ++i)
2596    if (Mask[i] >= 4)
2597      return false;
2598
2599  return true;
2600}
2601
2602bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2603  SmallVector<int, 8> M;
2604  N->getMask(M);
2605  return ::isPSHUFLWMask(M, N->getValueType(0));
2606}
2607
2608/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2609/// is suitable for input to PALIGNR.
2610static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2611                          bool hasSSSE3) {
2612  int i, e = VT.getVectorNumElements();
2613
2614  // Do not handle v2i64 / v2f64 shuffles with palignr.
2615  if (e < 4 || !hasSSSE3)
2616    return false;
2617
2618  for (i = 0; i != e; ++i)
2619    if (Mask[i] >= 0)
2620      break;
2621
2622  // All undef, not a palignr.
2623  if (i == e)
2624    return false;
2625
2626  // Determine if it's ok to perform a palignr with only the LHS, since we
2627  // don't have access to the actual shuffle elements to see if RHS is undef.
2628  bool Unary = Mask[i] < (int)e;
2629  bool NeedsUnary = false;
2630
2631  int s = Mask[i] - i;
2632
2633  // Check the rest of the elements to see if they are consecutive.
2634  for (++i; i != e; ++i) {
2635    int m = Mask[i];
2636    if (m < 0)
2637      continue;
2638
2639    Unary = Unary && (m < (int)e);
2640    NeedsUnary = NeedsUnary || (m < s);
2641
2642    if (NeedsUnary && !Unary)
2643      return false;
2644    if (Unary && m != ((s+i) & (e-1)))
2645      return false;
2646    if (!Unary && m != (s+i))
2647      return false;
2648  }
2649  return true;
2650}
2651
2652bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2653  SmallVector<int, 8> M;
2654  N->getMask(M);
2655  return ::isPALIGNRMask(M, N->getValueType(0), true);
2656}
2657
2658/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2659/// specifies a shuffle of elements that is suitable for input to SHUFP*.
2660static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2661  int NumElems = VT.getVectorNumElements();
2662  if (NumElems != 2 && NumElems != 4)
2663    return false;
2664
2665  int Half = NumElems / 2;
2666  for (int i = 0; i < Half; ++i)
2667    if (!isUndefOrInRange(Mask[i], 0, NumElems))
2668      return false;
2669  for (int i = Half; i < NumElems; ++i)
2670    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2671      return false;
2672
2673  return true;
2674}
2675
2676bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2677  SmallVector<int, 8> M;
2678  N->getMask(M);
2679  return ::isSHUFPMask(M, N->getValueType(0));
2680}
2681
2682/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2683/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2684/// half elements to come from vector 1 (which would equal the dest.) and
2685/// the upper half to come from vector 2.
2686static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2687  int NumElems = VT.getVectorNumElements();
2688
2689  if (NumElems != 2 && NumElems != 4)
2690    return false;
2691
2692  int Half = NumElems / 2;
2693  for (int i = 0; i < Half; ++i)
2694    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2695      return false;
2696  for (int i = Half; i < NumElems; ++i)
2697    if (!isUndefOrInRange(Mask[i], 0, NumElems))
2698      return false;
2699  return true;
2700}
2701
2702static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2703  SmallVector<int, 8> M;
2704  N->getMask(M);
2705  return isCommutedSHUFPMask(M, N->getValueType(0));
2706}
2707
2708/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2709/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2710bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2711  if (N->getValueType(0).getVectorNumElements() != 4)
2712    return false;
2713
2714  // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2715  return isUndefOrEqual(N->getMaskElt(0), 6) &&
2716         isUndefOrEqual(N->getMaskElt(1), 7) &&
2717         isUndefOrEqual(N->getMaskElt(2), 2) &&
2718         isUndefOrEqual(N->getMaskElt(3), 3);
2719}
2720
2721/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2722/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2723/// <2, 3, 2, 3>
2724bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2725  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2726
2727  if (NumElems != 4)
2728    return false;
2729
2730  return isUndefOrEqual(N->getMaskElt(0), 2) &&
2731  isUndefOrEqual(N->getMaskElt(1), 3) &&
2732  isUndefOrEqual(N->getMaskElt(2), 2) &&
2733  isUndefOrEqual(N->getMaskElt(3), 3);
2734}
2735
2736/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2737/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2738bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2739  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2740
2741  if (NumElems != 2 && NumElems != 4)
2742    return false;
2743
2744  for (unsigned i = 0; i < NumElems/2; ++i)
2745    if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2746      return false;
2747
2748  for (unsigned i = NumElems/2; i < NumElems; ++i)
2749    if (!isUndefOrEqual(N->getMaskElt(i), i))
2750      return false;
2751
2752  return true;
2753}
2754
2755/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2756/// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2757bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2758  unsigned NumElems = N->getValueType(0).getVectorNumElements();
2759
2760  if (NumElems != 2 && NumElems != 4)
2761    return false;
2762
2763  for (unsigned i = 0; i < NumElems/2; ++i)
2764    if (!isUndefOrEqual(N->getMaskElt(i), i))
2765      return false;
2766
2767  for (unsigned i = 0; i < NumElems/2; ++i)
2768    if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2769      return false;
2770
2771  return true;
2772}
2773
2774/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2775/// specifies a shuffle of elements that is suitable for input to UNPCKL.
2776static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2777                         bool V2IsSplat = false) {
2778  int NumElts = VT.getVectorNumElements();
2779  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2780    return false;
2781
2782  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2783    int BitI  = Mask[i];
2784    int BitI1 = Mask[i+1];
2785    if (!isUndefOrEqual(BitI, j))
2786      return false;
2787    if (V2IsSplat) {
2788      if (!isUndefOrEqual(BitI1, NumElts))
2789        return false;
2790    } else {
2791      if (!isUndefOrEqual(BitI1, j + NumElts))
2792        return false;
2793    }
2794  }
2795  return true;
2796}
2797
2798bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2799  SmallVector<int, 8> M;
2800  N->getMask(M);
2801  return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2802}
2803
2804/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2805/// specifies a shuffle of elements that is suitable for input to UNPCKH.
2806static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2807                         bool V2IsSplat = false) {
2808  int NumElts = VT.getVectorNumElements();
2809  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2810    return false;
2811
2812  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2813    int BitI  = Mask[i];
2814    int BitI1 = Mask[i+1];
2815    if (!isUndefOrEqual(BitI, j + NumElts/2))
2816      return false;
2817    if (V2IsSplat) {
2818      if (isUndefOrEqual(BitI1, NumElts))
2819        return false;
2820    } else {
2821      if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2822        return false;
2823    }
2824  }
2825  return true;
2826}
2827
2828bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2829  SmallVector<int, 8> M;
2830  N->getMask(M);
2831  return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2832}
2833
2834/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2835/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2836/// <0, 0, 1, 1>
2837static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2838  int NumElems = VT.getVectorNumElements();
2839  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2840    return false;
2841
2842  for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2843    int BitI  = Mask[i];
2844    int BitI1 = Mask[i+1];
2845    if (!isUndefOrEqual(BitI, j))
2846      return false;
2847    if (!isUndefOrEqual(BitI1, j))
2848      return false;
2849  }
2850  return true;
2851}
2852
2853bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2854  SmallVector<int, 8> M;
2855  N->getMask(M);
2856  return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2857}
2858
2859/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2860/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2861/// <2, 2, 3, 3>
2862static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2863  int NumElems = VT.getVectorNumElements();
2864  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2865    return false;
2866
2867  for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2868    int BitI  = Mask[i];
2869    int BitI1 = Mask[i+1];
2870    if (!isUndefOrEqual(BitI, j))
2871      return false;
2872    if (!isUndefOrEqual(BitI1, j))
2873      return false;
2874  }
2875  return true;
2876}
2877
2878bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2879  SmallVector<int, 8> M;
2880  N->getMask(M);
2881  return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2882}
2883
2884/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2885/// specifies a shuffle of elements that is suitable for input to MOVSS,
2886/// MOVSD, and MOVD, i.e. setting the lowest element.
2887static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2888  if (VT.getVectorElementType().getSizeInBits() < 32)
2889    return false;
2890
2891  int NumElts = VT.getVectorNumElements();
2892
2893  if (!isUndefOrEqual(Mask[0], NumElts))
2894    return false;
2895
2896  for (int i = 1; i < NumElts; ++i)
2897    if (!isUndefOrEqual(Mask[i], i))
2898      return false;
2899
2900  return true;
2901}
2902
2903bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2904  SmallVector<int, 8> M;
2905  N->getMask(M);
2906  return ::isMOVLMask(M, N->getValueType(0));
2907}
2908
2909/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2910/// of what x86 movss want. X86 movs requires the lowest  element to be lowest
2911/// element of vector 2 and the other elements to come from vector 1 in order.
2912static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2913                               bool V2IsSplat = false, bool V2IsUndef = false) {
2914  int NumOps = VT.getVectorNumElements();
2915  if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2916    return false;
2917
2918  if (!isUndefOrEqual(Mask[0], 0))
2919    return false;
2920
2921  for (int i = 1; i < NumOps; ++i)
2922    if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2923          (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2924          (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2925      return false;
2926
2927  return true;
2928}
2929
2930static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2931                           bool V2IsUndef = false) {
2932  SmallVector<int, 8> M;
2933  N->getMask(M);
2934  return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2935}
2936
2937/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2938/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2939bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2940  if (N->getValueType(0).getVectorNumElements() != 4)
2941    return false;
2942
2943  // Expect 1, 1, 3, 3
2944  for (unsigned i = 0; i < 2; ++i) {
2945    int Elt = N->getMaskElt(i);
2946    if (Elt >= 0 && Elt != 1)
2947      return false;
2948  }
2949
2950  bool HasHi = false;
2951  for (unsigned i = 2; i < 4; ++i) {
2952    int Elt = N->getMaskElt(i);
2953    if (Elt >= 0 && Elt != 3)
2954      return false;
2955    if (Elt == 3)
2956      HasHi = true;
2957  }
2958  // Don't use movshdup if it can be done with a shufps.
2959  // FIXME: verify that matching u, u, 3, 3 is what we want.
2960  return HasHi;
2961}
2962
2963/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2964/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2965bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2966  if (N->getValueType(0).getVectorNumElements() != 4)
2967    return false;
2968
2969  // Expect 0, 0, 2, 2
2970  for (unsigned i = 0; i < 2; ++i)
2971    if (N->getMaskElt(i) > 0)
2972      return false;
2973
2974  bool HasHi = false;
2975  for (unsigned i = 2; i < 4; ++i) {
2976    int Elt = N->getMaskElt(i);
2977    if (Elt >= 0 && Elt != 2)
2978      return false;
2979    if (Elt == 2)
2980      HasHi = true;
2981  }
2982  // Don't use movsldup if it can be done with a shufps.
2983  return HasHi;
2984}
2985
2986/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2987/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2988bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2989  int e = N->getValueType(0).getVectorNumElements() / 2;
2990
2991  for (int i = 0; i < e; ++i)
2992    if (!isUndefOrEqual(N->getMaskElt(i), i))
2993      return false;
2994  for (int i = 0; i < e; ++i)
2995    if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2996      return false;
2997  return true;
2998}
2999
3000/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3001/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3002unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3003  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3004  int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3005
3006  unsigned Shift = (NumOperands == 4) ? 2 : 1;
3007  unsigned Mask = 0;
3008  for (int i = 0; i < NumOperands; ++i) {
3009    int Val = SVOp->getMaskElt(NumOperands-i-1);
3010    if (Val < 0) Val = 0;
3011    if (Val >= NumOperands) Val -= NumOperands;
3012    Mask |= Val;
3013    if (i != NumOperands - 1)
3014      Mask <<= Shift;
3015  }
3016  return Mask;
3017}
3018
3019/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3020/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3021unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3022  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3023  unsigned Mask = 0;
3024  // 8 nodes, but we only care about the last 4.
3025  for (unsigned i = 7; i >= 4; --i) {
3026    int Val = SVOp->getMaskElt(i);
3027    if (Val >= 0)
3028      Mask |= (Val - 4);
3029    if (i != 4)
3030      Mask <<= 2;
3031  }
3032  return Mask;
3033}
3034
3035/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3036/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3037unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3038  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3039  unsigned Mask = 0;
3040  // 8 nodes, but we only care about the first 4.
3041  for (int i = 3; i >= 0; --i) {
3042    int Val = SVOp->getMaskElt(i);
3043    if (Val >= 0)
3044      Mask |= Val;
3045    if (i != 0)
3046      Mask <<= 2;
3047  }
3048  return Mask;
3049}
3050
3051/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3052/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3053unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3054  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3055  EVT VVT = N->getValueType(0);
3056  unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3057  int Val = 0;
3058
3059  unsigned i, e;
3060  for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3061    Val = SVOp->getMaskElt(i);
3062    if (Val >= 0)
3063      break;
3064  }
3065  return (Val - i) * EltSize;
3066}
3067
3068/// isZeroNode - Returns true if Elt is a constant zero or a floating point
3069/// constant +0.0.
3070bool X86::isZeroNode(SDValue Elt) {
3071  return ((isa<ConstantSDNode>(Elt) &&
3072           cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3073          (isa<ConstantFPSDNode>(Elt) &&
3074           cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3075}
3076
3077/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3078/// their permute mask.
3079static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3080                                    SelectionDAG &DAG) {
3081  EVT VT = SVOp->getValueType(0);
3082  unsigned NumElems = VT.getVectorNumElements();
3083  SmallVector<int, 8> MaskVec;
3084
3085  for (unsigned i = 0; i != NumElems; ++i) {
3086    int idx = SVOp->getMaskElt(i);
3087    if (idx < 0)
3088      MaskVec.push_back(idx);
3089    else if (idx < (int)NumElems)
3090      MaskVec.push_back(idx + NumElems);
3091    else
3092      MaskVec.push_back(idx - NumElems);
3093  }
3094  return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3095                              SVOp->getOperand(0), &MaskVec[0]);
3096}
3097
3098/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3099/// the two vector operands have swapped position.
3100static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3101  unsigned NumElems = VT.getVectorNumElements();
3102  for (unsigned i = 0; i != NumElems; ++i) {
3103    int idx = Mask[i];
3104    if (idx < 0)
3105      continue;
3106    else if (idx < (int)NumElems)
3107      Mask[i] = idx + NumElems;
3108    else
3109      Mask[i] = idx - NumElems;
3110  }
3111}
3112
3113/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3114/// match movhlps. The lower half elements should come from upper half of
3115/// V1 (and in order), and the upper half elements should come from the upper
3116/// half of V2 (and in order).
3117static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3118  if (Op->getValueType(0).getVectorNumElements() != 4)
3119    return false;
3120  for (unsigned i = 0, e = 2; i != e; ++i)
3121    if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3122      return false;
3123  for (unsigned i = 2; i != 4; ++i)
3124    if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3125      return false;
3126  return true;
3127}
3128
3129/// isScalarLoadToVector - Returns true if the node is a scalar load that
3130/// is promoted to a vector. It also returns the LoadSDNode by reference if
3131/// required.
3132static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3133  if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3134    return false;
3135  N = N->getOperand(0).getNode();
3136  if (!ISD::isNON_EXTLoad(N))
3137    return false;
3138  if (LD)
3139    *LD = cast<LoadSDNode>(N);
3140  return true;
3141}
3142
3143/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3144/// match movlp{s|d}. The lower half elements should come from lower half of
3145/// V1 (and in order), and the upper half elements should come from the upper
3146/// half of V2 (and in order). And since V1 will become the source of the
3147/// MOVLP, it must be either a vector load or a scalar load to vector.
3148static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3149                               ShuffleVectorSDNode *Op) {
3150  if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3151    return false;
3152  // Is V2 is a vector load, don't do this transformation. We will try to use
3153  // load folding shufps op.
3154  if (ISD::isNON_EXTLoad(V2))
3155    return false;
3156
3157  unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3158
3159  if (NumElems != 2 && NumElems != 4)
3160    return false;
3161  for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3162    if (!isUndefOrEqual(Op->getMaskElt(i), i))
3163      return false;
3164  for (unsigned i = NumElems/2; i != NumElems; ++i)
3165    if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3166      return false;
3167  return true;
3168}
3169
3170/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3171/// all the same.
3172static bool isSplatVector(SDNode *N) {
3173  if (N->getOpcode() != ISD::BUILD_VECTOR)
3174    return false;
3175
3176  SDValue SplatValue = N->getOperand(0);
3177  for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3178    if (N->getOperand(i) != SplatValue)
3179      return false;
3180  return true;
3181}
3182
3183/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3184/// to an zero vector.
3185/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3186static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3187  SDValue V1 = N->getOperand(0);
3188  SDValue V2 = N->getOperand(1);
3189  unsigned NumElems = N->getValueType(0).getVectorNumElements();
3190  for (unsigned i = 0; i != NumElems; ++i) {
3191    int Idx = N->getMaskElt(i);
3192    if (Idx >= (int)NumElems) {
3193      unsigned Opc = V2.getOpcode();
3194      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3195        continue;
3196      if (Opc != ISD::BUILD_VECTOR ||
3197          !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3198        return false;
3199    } else if (Idx >= 0) {
3200      unsigned Opc = V1.getOpcode();
3201      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3202        continue;
3203      if (Opc != ISD::BUILD_VECTOR ||
3204          !X86::isZeroNode(V1.getOperand(Idx)))
3205        return false;
3206    }
3207  }
3208  return true;
3209}
3210
3211/// getZeroVector - Returns a vector of specified type with all zero elements.
3212///
3213static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3214                             DebugLoc dl) {
3215  assert(VT.isVector() && "Expected a vector type");
3216
3217  // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3218  // type.  This ensures they get CSE'd.
3219  SDValue Vec;
3220  if (VT.getSizeInBits() == 64) { // MMX
3221    SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3222    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3223  } else if (HasSSE2) {  // SSE2
3224    SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3225    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3226  } else { // SSE1
3227    SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3228    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3229  }
3230  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3231}
3232
3233/// getOnesVector - Returns a vector of specified type with all bits set.
3234///
3235static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3236  assert(VT.isVector() && "Expected a vector type");
3237
3238  // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3239  // type.  This ensures they get CSE'd.
3240  SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3241  SDValue Vec;
3242  if (VT.getSizeInBits() == 64)  // MMX
3243    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3244  else                                              // SSE
3245    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3246  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3247}
3248
3249
3250/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3251/// that point to V2 points to its first element.
3252static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3253  EVT VT = SVOp->getValueType(0);
3254  unsigned NumElems = VT.getVectorNumElements();
3255
3256  bool Changed = false;
3257  SmallVector<int, 8> MaskVec;
3258  SVOp->getMask(MaskVec);
3259
3260  for (unsigned i = 0; i != NumElems; ++i) {
3261    if (MaskVec[i] > (int)NumElems) {
3262      MaskVec[i] = NumElems;
3263      Changed = true;
3264    }
3265  }
3266  if (Changed)
3267    return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3268                                SVOp->getOperand(1), &MaskVec[0]);
3269  return SDValue(SVOp, 0);
3270}
3271
3272/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3273/// operation of specified width.
3274static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3275                       SDValue V2) {
3276  unsigned NumElems = VT.getVectorNumElements();
3277  SmallVector<int, 8> Mask;
3278  Mask.push_back(NumElems);
3279  for (unsigned i = 1; i != NumElems; ++i)
3280    Mask.push_back(i);
3281  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3282}
3283
3284/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3285static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3286                          SDValue V2) {
3287  unsigned NumElems = VT.getVectorNumElements();
3288  SmallVector<int, 8> Mask;
3289  for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3290    Mask.push_back(i);
3291    Mask.push_back(i + NumElems);
3292  }
3293  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3294}
3295
3296/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3297static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3298                          SDValue V2) {
3299  unsigned NumElems = VT.getVectorNumElements();
3300  unsigned Half = NumElems/2;
3301  SmallVector<int, 8> Mask;
3302  for (unsigned i = 0; i != Half; ++i) {
3303    Mask.push_back(i + Half);
3304    Mask.push_back(i + NumElems + Half);
3305  }
3306  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3307}
3308
3309/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3310static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3311                            bool HasSSE2) {
3312  if (SV->getValueType(0).getVectorNumElements() <= 4)
3313    return SDValue(SV, 0);
3314
3315  EVT PVT = MVT::v4f32;
3316  EVT VT = SV->getValueType(0);
3317  DebugLoc dl = SV->getDebugLoc();
3318  SDValue V1 = SV->getOperand(0);
3319  int NumElems = VT.getVectorNumElements();
3320  int EltNo = SV->getSplatIndex();
3321
3322  // unpack elements to the correct location
3323  while (NumElems > 4) {
3324    if (EltNo < NumElems/2) {
3325      V1 = getUnpackl(DAG, dl, VT, V1, V1);
3326    } else {
3327      V1 = getUnpackh(DAG, dl, VT, V1, V1);
3328      EltNo -= NumElems/2;
3329    }
3330    NumElems >>= 1;
3331  }
3332
3333  // Perform the splat.
3334  int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3335  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3336  V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3337  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3338}
3339
3340/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3341/// vector of zero or undef vector.  This produces a shuffle where the low
3342/// element of V2 is swizzled into the zero/undef vector, landing at element
3343/// Idx.  This produces a shuffle mask like 4,1,2,3 (idx=0) or  0,1,2,4 (idx=3).
3344static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3345                                             bool isZero, bool HasSSE2,
3346                                             SelectionDAG &DAG) {
3347  EVT VT = V2.getValueType();
3348  SDValue V1 = isZero
3349    ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3350  unsigned NumElems = VT.getVectorNumElements();
3351  SmallVector<int, 16> MaskVec;
3352  for (unsigned i = 0; i != NumElems; ++i)
3353    // If this is the insertion idx, put the low elt of V2 here.
3354    MaskVec.push_back(i == Idx ? NumElems : i);
3355  return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3356}
3357
3358/// getNumOfConsecutiveZeros - Return the number of elements in a result of
3359/// a shuffle that is zero.
3360static
3361unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3362                                  bool Low, SelectionDAG &DAG) {
3363  unsigned NumZeros = 0;
3364  for (int i = 0; i < NumElems; ++i) {
3365    unsigned Index = Low ? i : NumElems-i-1;
3366    int Idx = SVOp->getMaskElt(Index);
3367    if (Idx < 0) {
3368      ++NumZeros;
3369      continue;
3370    }
3371    SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3372    if (Elt.getNode() && X86::isZeroNode(Elt))
3373      ++NumZeros;
3374    else
3375      break;
3376  }
3377  return NumZeros;
3378}
3379
3380/// isVectorShift - Returns true if the shuffle can be implemented as a
3381/// logical left or right shift of a vector.
3382/// FIXME: split into pslldqi, psrldqi, palignr variants.
3383static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3384                          bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3385  int NumElems = SVOp->getValueType(0).getVectorNumElements();
3386
3387  isLeft = true;
3388  unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3389  if (!NumZeros) {
3390    isLeft = false;
3391    NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3392    if (!NumZeros)
3393      return false;
3394  }
3395  bool SeenV1 = false;
3396  bool SeenV2 = false;
3397  for (int i = NumZeros; i < NumElems; ++i) {
3398    int Val = isLeft ? (i - NumZeros) : i;
3399    int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3400    if (Idx < 0)
3401      continue;
3402    if (Idx < NumElems)
3403      SeenV1 = true;
3404    else {
3405      Idx -= NumElems;
3406      SeenV2 = true;
3407    }
3408    if (Idx != Val)
3409      return false;
3410  }
3411  if (SeenV1 && SeenV2)
3412    return false;
3413
3414  ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3415  ShAmt = NumZeros;
3416  return true;
3417}
3418
3419
3420/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3421///
3422static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3423                                       unsigned NumNonZero, unsigned NumZero,
3424                                       SelectionDAG &DAG, TargetLowering &TLI) {
3425  if (NumNonZero > 8)
3426    return SDValue();
3427
3428  DebugLoc dl = Op.getDebugLoc();
3429  SDValue V(0, 0);
3430  bool First = true;
3431  for (unsigned i = 0; i < 16; ++i) {
3432    bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3433    if (ThisIsNonZero && First) {
3434      if (NumZero)
3435        V = getZeroVector(MVT::v8i16, true, DAG, dl);
3436      else
3437        V = DAG.getUNDEF(MVT::v8i16);
3438      First = false;
3439    }
3440
3441    if ((i & 1) != 0) {
3442      SDValue ThisElt(0, 0), LastElt(0, 0);
3443      bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3444      if (LastIsNonZero) {
3445        LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3446                              MVT::i16, Op.getOperand(i-1));
3447      }
3448      if (ThisIsNonZero) {
3449        ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3450        ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3451                              ThisElt, DAG.getConstant(8, MVT::i8));
3452        if (LastIsNonZero)
3453          ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3454      } else
3455        ThisElt = LastElt;
3456
3457      if (ThisElt.getNode())
3458        V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3459                        DAG.getIntPtrConstant(i/2));
3460    }
3461  }
3462
3463  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3464}
3465
3466/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3467///
3468static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3469                                       unsigned NumNonZero, unsigned NumZero,
3470                                       SelectionDAG &DAG, TargetLowering &TLI) {
3471  if (NumNonZero > 4)
3472    return SDValue();
3473
3474  DebugLoc dl = Op.getDebugLoc();
3475  SDValue V(0, 0);
3476  bool First = true;
3477  for (unsigned i = 0; i < 8; ++i) {
3478    bool isNonZero = (NonZeros & (1 << i)) != 0;
3479    if (isNonZero) {
3480      if (First) {
3481        if (NumZero)
3482          V = getZeroVector(MVT::v8i16, true, DAG, dl);
3483        else
3484          V = DAG.getUNDEF(MVT::v8i16);
3485        First = false;
3486      }
3487      V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3488                      MVT::v8i16, V, Op.getOperand(i),
3489                      DAG.getIntPtrConstant(i));
3490    }
3491  }
3492
3493  return V;
3494}
3495
3496/// getVShift - Return a vector logical shift node.
3497///
3498static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3499                         unsigned NumBits, SelectionDAG &DAG,
3500                         const TargetLowering &TLI, DebugLoc dl) {
3501  bool isMMX = VT.getSizeInBits() == 64;
3502  EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3503  unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3504  SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3505  return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3506                     DAG.getNode(Opc, dl, ShVT, SrcOp,
3507                             DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3508}
3509
3510SDValue
3511X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3512                                          SelectionDAG &DAG) {
3513
3514  // Check if the scalar load can be widened into a vector load. And if
3515  // the address is "base + cst" see if the cst can be "absorbed" into
3516  // the shuffle mask.
3517  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3518    SDValue Ptr = LD->getBasePtr();
3519    if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3520      return SDValue();
3521    EVT PVT = LD->getValueType(0);
3522    if (PVT != MVT::i32 && PVT != MVT::f32)
3523      return SDValue();
3524
3525    int FI = -1;
3526    int64_t Offset = 0;
3527    if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3528      FI = FINode->getIndex();
3529      Offset = 0;
3530    } else if (Ptr.getOpcode() == ISD::ADD &&
3531               isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3532               isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3533      FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3534      Offset = Ptr.getConstantOperandVal(1);
3535      Ptr = Ptr.getOperand(0);
3536    } else {
3537      return SDValue();
3538    }
3539
3540    SDValue Chain = LD->getChain();
3541    // Make sure the stack object alignment is at least 16.
3542    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3543    if (DAG.InferPtrAlignment(Ptr) < 16) {
3544      if (MFI->isFixedObjectIndex(FI)) {
3545        // Can't change the alignment. FIXME: It's possible to compute
3546        // the exact stack offset and reference FI + adjust offset instead.
3547        // If someone *really* cares about this. That's the way to implement it.
3548        return SDValue();
3549      } else {
3550        MFI->setObjectAlignment(FI, 16);
3551      }
3552    }
3553
3554    // (Offset % 16) must be multiple of 4. Then address is then
3555    // Ptr + (Offset & ~15).
3556    if (Offset < 0)
3557      return SDValue();
3558    if ((Offset % 16) & 3)
3559      return SDValue();
3560    int64_t StartOffset = Offset & ~15;
3561    if (StartOffset)
3562      Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3563                        Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3564
3565    int EltNo = (Offset - StartOffset) >> 2;
3566    int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3567    EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3568    SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3569    // Canonicalize it to a v4i32 shuffle.
3570    V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3571    return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3572                       DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3573                                            DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3574  }
3575
3576  return SDValue();
3577}
3578
3579SDValue
3580X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3581  DebugLoc dl = Op.getDebugLoc();
3582  // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3583  if (ISD::isBuildVectorAllZeros(Op.getNode())
3584      || ISD::isBuildVectorAllOnes(Op.getNode())) {
3585    // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3586    // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3587    // eliminated on x86-32 hosts.
3588    if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3589      return Op;
3590
3591    if (ISD::isBuildVectorAllOnes(Op.getNode()))
3592      return getOnesVector(Op.getValueType(), DAG, dl);
3593    return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3594  }
3595
3596  EVT VT = Op.getValueType();
3597  EVT ExtVT = VT.getVectorElementType();
3598  unsigned EVTBits = ExtVT.getSizeInBits();
3599
3600  unsigned NumElems = Op.getNumOperands();
3601  unsigned NumZero  = 0;
3602  unsigned NumNonZero = 0;
3603  unsigned NonZeros = 0;
3604  bool IsAllConstants = true;
3605  SmallSet<SDValue, 8> Values;
3606  for (unsigned i = 0; i < NumElems; ++i) {
3607    SDValue Elt = Op.getOperand(i);
3608    if (Elt.getOpcode() == ISD::UNDEF)
3609      continue;
3610    Values.insert(Elt);
3611    if (Elt.getOpcode() != ISD::Constant &&
3612        Elt.getOpcode() != ISD::ConstantFP)
3613      IsAllConstants = false;
3614    if (X86::isZeroNode(Elt))
3615      NumZero++;
3616    else {
3617      NonZeros |= (1 << i);
3618      NumNonZero++;
3619    }
3620  }
3621
3622  if (NumNonZero == 0) {
3623    // All undef vector. Return an UNDEF.  All zero vectors were handled above.
3624    return DAG.getUNDEF(VT);
3625  }
3626
3627  // Special case for single non-zero, non-undef, element.
3628  if (NumNonZero == 1) {
3629    unsigned Idx = CountTrailingZeros_32(NonZeros);
3630    SDValue Item = Op.getOperand(Idx);
3631
3632    // If this is an insertion of an i64 value on x86-32, and if the top bits of
3633    // the value are obviously zero, truncate the value to i32 and do the
3634    // insertion that way.  Only do this if the value is non-constant or if the
3635    // value is a constant being inserted into element 0.  It is cheaper to do
3636    // a constant pool load than it is to do a movd + shuffle.
3637    if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3638        (!IsAllConstants || Idx == 0)) {
3639      if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3640        // Handle MMX and SSE both.
3641        EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3642        unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3643
3644        // Truncate the value (which may itself be a constant) to i32, and
3645        // convert it to a vector with movd (S2V+shuffle to zero extend).
3646        Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3647        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3648        Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3649                                           Subtarget->hasSSE2(), DAG);
3650
3651        // Now we have our 32-bit value zero extended in the low element of
3652        // a vector.  If Idx != 0, swizzle it into place.
3653        if (Idx != 0) {
3654          SmallVector<int, 4> Mask;
3655          Mask.push_back(Idx);
3656          for (unsigned i = 1; i != VecElts; ++i)
3657            Mask.push_back(i);
3658          Item = DAG.getVectorShuffle(VecVT, dl, Item,
3659                                      DAG.getUNDEF(Item.getValueType()),
3660                                      &Mask[0]);
3661        }
3662        return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3663      }
3664    }
3665
3666    // If we have a constant or non-constant insertion into the low element of
3667    // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3668    // the rest of the elements.  This will be matched as movd/movq/movss/movsd
3669    // depending on what the source datatype is.
3670    if (Idx == 0) {
3671      if (NumZero == 0) {
3672        return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3673      } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3674          (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3675        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3676        // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3677        return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3678                                           DAG);
3679      } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3680        Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3681        EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3682        Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3683        Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3684                                           Subtarget->hasSSE2(), DAG);
3685        return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3686      }
3687    }
3688
3689    // Is it a vector logical left shift?
3690    if (NumElems == 2 && Idx == 1 &&
3691        X86::isZeroNode(Op.getOperand(0)) &&
3692        !X86::isZeroNode(Op.getOperand(1))) {
3693      unsigned NumBits = VT.getSizeInBits();
3694      return getVShift(true, VT,
3695                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3696                                   VT, Op.getOperand(1)),
3697                       NumBits/2, DAG, *this, dl);
3698    }
3699
3700    if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3701      return SDValue();
3702
3703    // Otherwise, if this is a vector with i32 or f32 elements, and the element
3704    // is a non-constant being inserted into an element other than the low one,
3705    // we can't use a constant pool load.  Instead, use SCALAR_TO_VECTOR (aka
3706    // movd/movss) to move this into the low element, then shuffle it into
3707    // place.
3708    if (EVTBits == 32) {
3709      Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3710
3711      // Turn it into a shuffle of zero and zero-extended scalar to vector.
3712      Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3713                                         Subtarget->hasSSE2(), DAG);
3714      SmallVector<int, 8> MaskVec;
3715      for (unsigned i = 0; i < NumElems; i++)
3716        MaskVec.push_back(i == Idx ? 0 : 1);
3717      return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3718    }
3719  }
3720
3721  // Splat is obviously ok. Let legalizer expand it to a shuffle.
3722  if (Values.size() == 1) {
3723    if (EVTBits == 32) {
3724      // Instead of a shuffle like this:
3725      // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3726      // Check if it's possible to issue this instead.
3727      // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3728      unsigned Idx = CountTrailingZeros_32(NonZeros);
3729      SDValue Item = Op.getOperand(Idx);
3730      if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3731        return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3732    }
3733    return SDValue();
3734  }
3735
3736  // A vector full of immediates; various special cases are already
3737  // handled, so this is best done with a single constant-pool load.
3738  if (IsAllConstants)
3739    return SDValue();
3740
3741  // Let legalizer expand 2-wide build_vectors.
3742  if (EVTBits == 64) {
3743    if (NumNonZero == 1) {
3744      // One half is zero or undef.
3745      unsigned Idx = CountTrailingZeros_32(NonZeros);
3746      SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3747                                 Op.getOperand(Idx));
3748      return getShuffleVectorZeroOrUndef(V2, Idx, true,
3749                                         Subtarget->hasSSE2(), DAG);
3750    }
3751    return SDValue();
3752  }
3753
3754  // If element VT is < 32 bits, convert it to inserts into a zero vector.
3755  if (EVTBits == 8 && NumElems == 16) {
3756    SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3757                                        *this);
3758    if (V.getNode()) return V;
3759  }
3760
3761  if (EVTBits == 16 && NumElems == 8) {
3762    SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3763                                        *this);
3764    if (V.getNode()) return V;
3765  }
3766
3767  // If element VT is == 32 bits, turn it into a number of shuffles.
3768  SmallVector<SDValue, 8> V;
3769  V.resize(NumElems);
3770  if (NumElems == 4 && NumZero > 0) {
3771    for (unsigned i = 0; i < 4; ++i) {
3772      bool isZero = !(NonZeros & (1 << i));
3773      if (isZero)
3774        V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3775      else
3776        V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3777    }
3778
3779    for (unsigned i = 0; i < 2; ++i) {
3780      switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3781        default: break;
3782        case 0:
3783          V[i] = V[i*2];  // Must be a zero vector.
3784          break;
3785        case 1:
3786          V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3787          break;
3788        case 2:
3789          V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3790          break;
3791        case 3:
3792          V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3793          break;
3794      }
3795    }
3796
3797    SmallVector<int, 8> MaskVec;
3798    bool Reverse = (NonZeros & 0x3) == 2;
3799    for (unsigned i = 0; i < 2; ++i)
3800      MaskVec.push_back(Reverse ? 1-i : i);
3801    Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3802    for (unsigned i = 0; i < 2; ++i)
3803      MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3804    return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3805  }
3806
3807  if (Values.size() > 2) {
3808    // If we have SSE 4.1, Expand into a number of inserts unless the number of
3809    // values to be inserted is equal to the number of elements, in which case
3810    // use the unpack code below in the hopes of matching the consecutive elts
3811    // load merge pattern for shuffles.
3812    // FIXME: We could probably just check that here directly.
3813    if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3814        getSubtarget()->hasSSE41()) {
3815      V[0] = DAG.getUNDEF(VT);
3816      for (unsigned i = 0; i < NumElems; ++i)
3817        if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3818          V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3819                             Op.getOperand(i), DAG.getIntPtrConstant(i));
3820      return V[0];
3821    }
3822    // Expand into a number of unpckl*.
3823    // e.g. for v4f32
3824    //   Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3825    //         : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3826    //   Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>
3827    for (unsigned i = 0; i < NumElems; ++i)
3828      V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3829    NumElems >>= 1;
3830    while (NumElems != 0) {
3831      for (unsigned i = 0; i < NumElems; ++i)
3832        V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3833      NumElems >>= 1;
3834    }
3835    return V[0];
3836  }
3837
3838  return SDValue();
3839}
3840
3841SDValue
3842X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3843  // We support concatenate two MMX registers and place them in a MMX
3844  // register.  This is better than doing a stack convert.
3845  DebugLoc dl = Op.getDebugLoc();
3846  EVT ResVT = Op.getValueType();
3847  assert(Op.getNumOperands() == 2);
3848  assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3849         ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3850  int Mask[2];
3851  SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3852  SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3853  InVec = Op.getOperand(1);
3854  if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3855    unsigned NumElts = ResVT.getVectorNumElements();
3856    VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3857    VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3858                       InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3859  } else {
3860    InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3861    SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3862    Mask[0] = 0; Mask[1] = 2;
3863    VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3864  }
3865  return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3866}
3867
3868// v8i16 shuffles - Prefer shuffles in the following order:
3869// 1. [all]   pshuflw, pshufhw, optional move
3870// 2. [ssse3] 1 x pshufb
3871// 3. [ssse3] 2 x pshufb + 1 x por
3872// 4. [all]   mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3873static
3874SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3875                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
3876  SDValue V1 = SVOp->getOperand(0);
3877  SDValue V2 = SVOp->getOperand(1);
3878  DebugLoc dl = SVOp->getDebugLoc();
3879  SmallVector<int, 8> MaskVals;
3880
3881  // Determine if more than 1 of the words in each of the low and high quadwords
3882  // of the result come from the same quadword of one of the two inputs.  Undef
3883  // mask values count as coming from any quadword, for better codegen.
3884  SmallVector<unsigned, 4> LoQuad(4);
3885  SmallVector<unsigned, 4> HiQuad(4);
3886  BitVector InputQuads(4);
3887  for (unsigned i = 0; i < 8; ++i) {
3888    SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3889    int EltIdx = SVOp->getMaskElt(i);
3890    MaskVals.push_back(EltIdx);
3891    if (EltIdx < 0) {
3892      ++Quad[0];
3893      ++Quad[1];
3894      ++Quad[2];
3895      ++Quad[3];
3896      continue;
3897    }
3898    ++Quad[EltIdx / 4];
3899    InputQuads.set(EltIdx / 4);
3900  }
3901
3902  int BestLoQuad = -1;
3903  unsigned MaxQuad = 1;
3904  for (unsigned i = 0; i < 4; ++i) {
3905    if (LoQuad[i] > MaxQuad) {
3906      BestLoQuad = i;
3907      MaxQuad = LoQuad[i];
3908    }
3909  }
3910
3911  int BestHiQuad = -1;
3912  MaxQuad = 1;
3913  for (unsigned i = 0; i < 4; ++i) {
3914    if (HiQuad[i] > MaxQuad) {
3915      BestHiQuad = i;
3916      MaxQuad = HiQuad[i];
3917    }
3918  }
3919
3920  // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3921  // of the two input vectors, shuffle them into one input vector so only a
3922  // single pshufb instruction is necessary. If There are more than 2 input
3923  // quads, disable the next transformation since it does not help SSSE3.
3924  bool V1Used = InputQuads[0] || InputQuads[1];
3925  bool V2Used = InputQuads[2] || InputQuads[3];
3926  if (TLI.getSubtarget()->hasSSSE3()) {
3927    if (InputQuads.count() == 2 && V1Used && V2Used) {
3928      BestLoQuad = InputQuads.find_first();
3929      BestHiQuad = InputQuads.find_next(BestLoQuad);
3930    }
3931    if (InputQuads.count() > 2) {
3932      BestLoQuad = -1;
3933      BestHiQuad = -1;
3934    }
3935  }
3936
3937  // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3938  // the shuffle mask.  If a quad is scored as -1, that means that it contains
3939  // words from all 4 input quadwords.
3940  SDValue NewV;
3941  if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3942    SmallVector<int, 8> MaskV;
3943    MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3944    MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3945    NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3946                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3947                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3948    NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3949
3950    // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3951    // source words for the shuffle, to aid later transformations.
3952    bool AllWordsInNewV = true;
3953    bool InOrder[2] = { true, true };
3954    for (unsigned i = 0; i != 8; ++i) {
3955      int idx = MaskVals[i];
3956      if (idx != (int)i)
3957        InOrder[i/4] = false;
3958      if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3959        continue;
3960      AllWordsInNewV = false;
3961      break;
3962    }
3963
3964    bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3965    if (AllWordsInNewV) {
3966      for (int i = 0; i != 8; ++i) {
3967        int idx = MaskVals[i];
3968        if (idx < 0)
3969          continue;
3970        idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3971        if ((idx != i) && idx < 4)
3972          pshufhw = false;
3973        if ((idx != i) && idx > 3)
3974          pshuflw = false;
3975      }
3976      V1 = NewV;
3977      V2Used = false;
3978      BestLoQuad = 0;
3979      BestHiQuad = 1;
3980    }
3981
3982    // If we've eliminated the use of V2, and the new mask is a pshuflw or
3983    // pshufhw, that's as cheap as it gets.  Return the new shuffle.
3984    if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3985      return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3986                                  DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3987    }
3988  }
3989
3990  // If we have SSSE3, and all words of the result are from 1 input vector,
3991  // case 2 is generated, otherwise case 3 is generated.  If no SSSE3
3992  // is present, fall back to case 4.
3993  if (TLI.getSubtarget()->hasSSSE3()) {
3994    SmallVector<SDValue,16> pshufbMask;
3995
3996    // If we have elements from both input vectors, set the high bit of the
3997    // shuffle mask element to zero out elements that come from V2 in the V1
3998    // mask, and elements that come from V1 in the V2 mask, so that the two
3999    // results can be OR'd together.
4000    bool TwoInputs = V1Used && V2Used;
4001    for (unsigned i = 0; i != 8; ++i) {
4002      int EltIdx = MaskVals[i] * 2;
4003      if (TwoInputs && (EltIdx >= 16)) {
4004        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4005        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4006        continue;
4007      }
4008      pshufbMask.push_back(DAG.getConstant(EltIdx,   MVT::i8));
4009      pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4010    }
4011    V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4012    V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4013                     DAG.getNode(ISD::BUILD_VECTOR, dl,
4014                                 MVT::v16i8, &pshufbMask[0], 16));
4015    if (!TwoInputs)
4016      return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4017
4018    // Calculate the shuffle mask for the second input, shuffle it, and
4019    // OR it with the first shuffled input.
4020    pshufbMask.clear();
4021    for (unsigned i = 0; i != 8; ++i) {
4022      int EltIdx = MaskVals[i] * 2;
4023      if (EltIdx < 16) {
4024        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4025        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4026        continue;
4027      }
4028      pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4029      pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4030    }
4031    V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4032    V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4033                     DAG.getNode(ISD::BUILD_VECTOR, dl,
4034                                 MVT::v16i8, &pshufbMask[0], 16));
4035    V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4036    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4037  }
4038
4039  // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4040  // and update MaskVals with new element order.
4041  BitVector InOrder(8);
4042  if (BestLoQuad >= 0) {
4043    SmallVector<int, 8> MaskV;
4044    for (int i = 0; i != 4; ++i) {
4045      int idx = MaskVals[i];
4046      if (idx < 0) {
4047        MaskV.push_back(-1);
4048        InOrder.set(i);
4049      } else if ((idx / 4) == BestLoQuad) {
4050        MaskV.push_back(idx & 3);
4051        InOrder.set(i);
4052      } else {
4053        MaskV.push_back(-1);
4054      }
4055    }
4056    for (unsigned i = 4; i != 8; ++i)
4057      MaskV.push_back(i);
4058    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4059                                &MaskV[0]);
4060  }
4061
4062  // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4063  // and update MaskVals with the new element order.
4064  if (BestHiQuad >= 0) {
4065    SmallVector<int, 8> MaskV;
4066    for (unsigned i = 0; i != 4; ++i)
4067      MaskV.push_back(i);
4068    for (unsigned i = 4; i != 8; ++i) {
4069      int idx = MaskVals[i];
4070      if (idx < 0) {
4071        MaskV.push_back(-1);
4072        InOrder.set(i);
4073      } else if ((idx / 4) == BestHiQuad) {
4074        MaskV.push_back((idx & 3) + 4);
4075        InOrder.set(i);
4076      } else {
4077        MaskV.push_back(-1);
4078      }
4079    }
4080    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4081                                &MaskV[0]);
4082  }
4083
4084  // In case BestHi & BestLo were both -1, which means each quadword has a word
4085  // from each of the four input quadwords, calculate the InOrder bitvector now
4086  // before falling through to the insert/extract cleanup.
4087  if (BestLoQuad == -1 && BestHiQuad == -1) {
4088    NewV = V1;
4089    for (int i = 0; i != 8; ++i)
4090      if (MaskVals[i] < 0 || MaskVals[i] == i)
4091        InOrder.set(i);
4092  }
4093
4094  // The other elements are put in the right place using pextrw and pinsrw.
4095  for (unsigned i = 0; i != 8; ++i) {
4096    if (InOrder[i])
4097      continue;
4098    int EltIdx = MaskVals[i];
4099    if (EltIdx < 0)
4100      continue;
4101    SDValue ExtOp = (EltIdx < 8)
4102    ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4103                  DAG.getIntPtrConstant(EltIdx))
4104    : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4105                  DAG.getIntPtrConstant(EltIdx - 8));
4106    NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4107                       DAG.getIntPtrConstant(i));
4108  }
4109  return NewV;
4110}
4111
4112// v16i8 shuffles - Prefer shuffles in the following order:
4113// 1. [ssse3] 1 x pshufb
4114// 2. [ssse3] 2 x pshufb + 1 x por
4115// 3. [all]   v8i16 shuffle + N x pextrw + rotate + pinsrw
4116static
4117SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4118                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
4119  SDValue V1 = SVOp->getOperand(0);
4120  SDValue V2 = SVOp->getOperand(1);
4121  DebugLoc dl = SVOp->getDebugLoc();
4122  SmallVector<int, 16> MaskVals;
4123  SVOp->getMask(MaskVals);
4124
4125  // If we have SSSE3, case 1 is generated when all result bytes come from
4126  // one of  the inputs.  Otherwise, case 2 is generated.  If no SSSE3 is
4127  // present, fall back to case 3.
4128  // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4129  bool V1Only = true;
4130  bool V2Only = true;
4131  for (unsigned i = 0; i < 16; ++i) {
4132    int EltIdx = MaskVals[i];
4133    if (EltIdx < 0)
4134      continue;
4135    if (EltIdx < 16)
4136      V2Only = false;
4137    else
4138      V1Only = false;
4139  }
4140
4141  // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4142  if (TLI.getSubtarget()->hasSSSE3()) {
4143    SmallVector<SDValue,16> pshufbMask;
4144
4145    // If all result elements are from one input vector, then only translate
4146    // undef mask values to 0x80 (zero out result) in the pshufb mask.
4147    //
4148    // Otherwise, we have elements from both input vectors, and must zero out
4149    // elements that come from V2 in the first mask, and V1 in the second mask
4150    // so that we can OR them together.
4151    bool TwoInputs = !(V1Only || V2Only);
4152    for (unsigned i = 0; i != 16; ++i) {
4153      int EltIdx = MaskVals[i];
4154      if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4155        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4156        continue;
4157      }
4158      pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4159    }
4160    // If all the elements are from V2, assign it to V1 and return after
4161    // building the first pshufb.
4162    if (V2Only)
4163      V1 = V2;
4164    V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4165                     DAG.getNode(ISD::BUILD_VECTOR, dl,
4166                                 MVT::v16i8, &pshufbMask[0], 16));
4167    if (!TwoInputs)
4168      return V1;
4169
4170    // Calculate the shuffle mask for the second input, shuffle it, and
4171    // OR it with the first shuffled input.
4172    pshufbMask.clear();
4173    for (unsigned i = 0; i != 16; ++i) {
4174      int EltIdx = MaskVals[i];
4175      if (EltIdx < 16) {
4176        pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4177        continue;
4178      }
4179      pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4180    }
4181    V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4182                     DAG.getNode(ISD::BUILD_VECTOR, dl,
4183                                 MVT::v16i8, &pshufbMask[0], 16));
4184    return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4185  }
4186
4187  // No SSSE3 - Calculate in place words and then fix all out of place words
4188  // With 0-16 extracts & inserts.  Worst case is 16 bytes out of order from
4189  // the 16 different words that comprise the two doublequadword input vectors.
4190  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4191  V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4192  SDValue NewV = V2Only ? V2 : V1;
4193  for (int i = 0; i != 8; ++i) {
4194    int Elt0 = MaskVals[i*2];
4195    int Elt1 = MaskVals[i*2+1];
4196
4197    // This word of the result is all undef, skip it.
4198    if (Elt0 < 0 && Elt1 < 0)
4199      continue;
4200
4201    // This word of the result is already in the correct place, skip it.
4202    if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4203      continue;
4204    if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4205      continue;
4206
4207    SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4208    SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4209    SDValue InsElt;
4210
4211    // If Elt0 and Elt1 are defined, are consecutive, and can be load
4212    // using a single extract together, load it and store it.
4213    if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4214      InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4215                           DAG.getIntPtrConstant(Elt1 / 2));
4216      NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4217                        DAG.getIntPtrConstant(i));
4218      continue;
4219    }
4220
4221    // If Elt1 is defined, extract it from the appropriate source.  If the
4222    // source byte is not also odd, shift the extracted word left 8 bits
4223    // otherwise clear the bottom 8 bits if we need to do an or.
4224    if (Elt1 >= 0) {
4225      InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4226                           DAG.getIntPtrConstant(Elt1 / 2));
4227      if ((Elt1 & 1) == 0)
4228        InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4229                             DAG.getConstant(8, TLI.getShiftAmountTy()));
4230      else if (Elt0 >= 0)
4231        InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4232                             DAG.getConstant(0xFF00, MVT::i16));
4233    }
4234    // If Elt0 is defined, extract it from the appropriate source.  If the
4235    // source byte is not also even, shift the extracted word right 8 bits. If
4236    // Elt1 was also defined, OR the extracted values together before
4237    // inserting them in the result.
4238    if (Elt0 >= 0) {
4239      SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4240                                    Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4241      if ((Elt0 & 1) != 0)
4242        InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4243                              DAG.getConstant(8, TLI.getShiftAmountTy()));
4244      else if (Elt1 >= 0)
4245        InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4246                             DAG.getConstant(0x00FF, MVT::i16));
4247      InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4248                         : InsElt0;
4249    }
4250    NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4251                       DAG.getIntPtrConstant(i));
4252  }
4253  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4254}
4255
4256/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4257/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4258/// done when every pair / quad of shuffle mask elements point to elements in
4259/// the right sequence. e.g.
4260/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4261static
4262SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4263                                 SelectionDAG &DAG,
4264                                 TargetLowering &TLI, DebugLoc dl) {
4265  EVT VT = SVOp->getValueType(0);
4266  SDValue V1 = SVOp->getOperand(0);
4267  SDValue V2 = SVOp->getOperand(1);
4268  unsigned NumElems = VT.getVectorNumElements();
4269  unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4270  EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4271  EVT MaskEltVT = MaskVT.getVectorElementType();
4272  EVT NewVT = MaskVT;
4273  switch (VT.getSimpleVT().SimpleTy) {
4274  default: assert(false && "Unexpected!");
4275  case MVT::v4f32: NewVT = MVT::v2f64; break;
4276  case MVT::v4i32: NewVT = MVT::v2i64; break;
4277  case MVT::v8i16: NewVT = MVT::v4i32; break;
4278  case MVT::v16i8: NewVT = MVT::v4i32; break;
4279  }
4280
4281  if (NewWidth == 2) {
4282    if (VT.isInteger())
4283      NewVT = MVT::v2i64;
4284    else
4285      NewVT = MVT::v2f64;
4286  }
4287  int Scale = NumElems / NewWidth;
4288  SmallVector<int, 8> MaskVec;
4289  for (unsigned i = 0; i < NumElems; i += Scale) {
4290    int StartIdx = -1;
4291    for (int j = 0; j < Scale; ++j) {
4292      int EltIdx = SVOp->getMaskElt(i+j);
4293      if (EltIdx < 0)
4294        continue;
4295      if (StartIdx == -1)
4296        StartIdx = EltIdx - (EltIdx % Scale);
4297      if (EltIdx != StartIdx + j)
4298        return SDValue();
4299    }
4300    if (StartIdx == -1)
4301      MaskVec.push_back(-1);
4302    else
4303      MaskVec.push_back(StartIdx / Scale);
4304  }
4305
4306  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4307  V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4308  return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4309}
4310
4311/// getVZextMovL - Return a zero-extending vector move low node.
4312///
4313static SDValue getVZextMovL(EVT VT, EVT OpVT,
4314                            SDValue SrcOp, SelectionDAG &DAG,
4315                            const X86Subtarget *Subtarget, DebugLoc dl) {
4316  if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4317    LoadSDNode *LD = NULL;
4318    if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4319      LD = dyn_cast<LoadSDNode>(SrcOp);
4320    if (!LD) {
4321      // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4322      // instead.
4323      MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4324      if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4325          SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4326          SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4327          SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4328        // PR2108
4329        OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4330        return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4331                           DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4332                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4333                                                   OpVT,
4334                                                   SrcOp.getOperand(0)
4335                                                          .getOperand(0))));
4336      }
4337    }
4338  }
4339
4340  return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4341                     DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4342                                 DAG.getNode(ISD::BIT_CONVERT, dl,
4343                                             OpVT, SrcOp)));
4344}
4345
4346/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4347/// shuffles.
4348static SDValue
4349LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4350  SDValue V1 = SVOp->getOperand(0);
4351  SDValue V2 = SVOp->getOperand(1);
4352  DebugLoc dl = SVOp->getDebugLoc();
4353  EVT VT = SVOp->getValueType(0);
4354
4355  SmallVector<std::pair<int, int>, 8> Locs;
4356  Locs.resize(4);
4357  SmallVector<int, 8> Mask1(4U, -1);
4358  SmallVector<int, 8> PermMask;
4359  SVOp->getMask(PermMask);
4360
4361  unsigned NumHi = 0;
4362  unsigned NumLo = 0;
4363  for (unsigned i = 0; i != 4; ++i) {
4364    int Idx = PermMask[i];
4365    if (Idx < 0) {
4366      Locs[i] = std::make_pair(-1, -1);
4367    } else {
4368      assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4369      if (Idx < 4) {
4370        Locs[i] = std::make_pair(0, NumLo);
4371        Mask1[NumLo] = Idx;
4372        NumLo++;
4373      } else {
4374        Locs[i] = std::make_pair(1, NumHi);
4375        if (2+NumHi < 4)
4376          Mask1[2+NumHi] = Idx;
4377        NumHi++;
4378      }
4379    }
4380  }
4381
4382  if (NumLo <= 2 && NumHi <= 2) {
4383    // If no more than two elements come from either vector. This can be
4384    // implemented with two shuffles. First shuffle gather the elements.
4385    // The second shuffle, which takes the first shuffle as both of its
4386    // vector operands, put the elements into the right order.
4387    V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4388
4389    SmallVector<int, 8> Mask2(4U, -1);
4390
4391    for (unsigned i = 0; i != 4; ++i) {
4392      if (Locs[i].first == -1)
4393        continue;
4394      else {
4395        unsigned Idx = (i < 2) ? 0 : 4;
4396        Idx += Locs[i].first * 2 + Locs[i].second;
4397        Mask2[i] = Idx;
4398      }
4399    }
4400
4401    return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4402  } else if (NumLo == 3 || NumHi == 3) {
4403    // Otherwise, we must have three elements from one vector, call it X, and
4404    // one element from the other, call it Y.  First, use a shufps to build an
4405    // intermediate vector with the one element from Y and the element from X
4406    // that will be in the same half in the final destination (the indexes don't
4407    // matter). Then, use a shufps to build the final vector, taking the half
4408    // containing the element from Y from the intermediate, and the other half
4409    // from X.
4410    if (NumHi == 3) {
4411      // Normalize it so the 3 elements come from V1.
4412      CommuteVectorShuffleMask(PermMask, VT);
4413      std::swap(V1, V2);
4414    }
4415
4416    // Find the element from V2.
4417    unsigned HiIndex;
4418    for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4419      int Val = PermMask[HiIndex];
4420      if (Val < 0)
4421        continue;
4422      if (Val >= 4)
4423        break;
4424    }
4425
4426    Mask1[0] = PermMask[HiIndex];
4427    Mask1[1] = -1;
4428    Mask1[2] = PermMask[HiIndex^1];
4429    Mask1[3] = -1;
4430    V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4431
4432    if (HiIndex >= 2) {
4433      Mask1[0] = PermMask[0];
4434      Mask1[1] = PermMask[1];
4435      Mask1[2] = HiIndex & 1 ? 6 : 4;
4436      Mask1[3] = HiIndex & 1 ? 4 : 6;
4437      return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4438    } else {
4439      Mask1[0] = HiIndex & 1 ? 2 : 0;
4440      Mask1[1] = HiIndex & 1 ? 0 : 2;
4441      Mask1[2] = PermMask[2];
4442      Mask1[3] = PermMask[3];
4443      if (Mask1[2] >= 0)
4444        Mask1[2] += 4;
4445      if (Mask1[3] >= 0)
4446        Mask1[3] += 4;
4447      return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4448    }
4449  }
4450
4451  // Break it into (shuffle shuffle_hi, shuffle_lo).
4452  Locs.clear();
4453  SmallVector<int,8> LoMask(4U, -1);
4454  SmallVector<int,8> HiMask(4U, -1);
4455
4456  SmallVector<int,8> *MaskPtr = &LoMask;
4457  unsigned MaskIdx = 0;
4458  unsigned LoIdx = 0;
4459  unsigned HiIdx = 2;
4460  for (unsigned i = 0; i != 4; ++i) {
4461    if (i == 2) {
4462      MaskPtr = &HiMask;
4463      MaskIdx = 1;
4464      LoIdx = 0;
4465      HiIdx = 2;
4466    }
4467    int Idx = PermMask[i];
4468    if (Idx < 0) {
4469      Locs[i] = std::make_pair(-1, -1);
4470    } else if (Idx < 4) {
4471      Locs[i] = std::make_pair(MaskIdx, LoIdx);
4472      (*MaskPtr)[LoIdx] = Idx;
4473      LoIdx++;
4474    } else {
4475      Locs[i] = std::make_pair(MaskIdx, HiIdx);
4476      (*MaskPtr)[HiIdx] = Idx;
4477      HiIdx++;
4478    }
4479  }
4480
4481  SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4482  SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4483  SmallVector<int, 8> MaskOps;
4484  for (unsigned i = 0; i != 4; ++i) {
4485    if (Locs[i].first == -1) {
4486      MaskOps.push_back(-1);
4487    } else {
4488      unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4489      MaskOps.push_back(Idx);
4490    }
4491  }
4492  return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4493}
4494
4495SDValue
4496X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4497  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4498  SDValue V1 = Op.getOperand(0);
4499  SDValue V2 = Op.getOperand(1);
4500  EVT VT = Op.getValueType();
4501  DebugLoc dl = Op.getDebugLoc();
4502  unsigned NumElems = VT.getVectorNumElements();
4503  bool isMMX = VT.getSizeInBits() == 64;
4504  bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4505  bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4506  bool V1IsSplat = false;
4507  bool V2IsSplat = false;
4508
4509  if (isZeroShuffle(SVOp))
4510    return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4511
4512  // Promote splats to v4f32.
4513  if (SVOp->isSplat()) {
4514    if (isMMX || NumElems < 4)
4515      return Op;
4516    return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4517  }
4518
4519  // If the shuffle can be profitably rewritten as a narrower shuffle, then
4520  // do it!
4521  if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4522    SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4523    if (NewOp.getNode())
4524      return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4525                         LowerVECTOR_SHUFFLE(NewOp, DAG));
4526  } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4527    // FIXME: Figure out a cleaner way to do this.
4528    // Try to make use of movq to zero out the top part.
4529    if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4530      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4531      if (NewOp.getNode()) {
4532        if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4533          return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4534                              DAG, Subtarget, dl);
4535      }
4536    } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4537      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4538      if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4539        return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4540                            DAG, Subtarget, dl);
4541    }
4542  }
4543
4544  if (X86::isPSHUFDMask(SVOp))
4545    return Op;
4546
4547  // Check if this can be converted into a logical shift.
4548  bool isLeft = false;
4549  unsigned ShAmt = 0;
4550  SDValue ShVal;
4551  bool isShift = getSubtarget()->hasSSE2() &&
4552    isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4553  if (isShift && ShVal.hasOneUse()) {
4554    // If the shifted value has multiple uses, it may be cheaper to use
4555    // v_set0 + movlhps or movhlps, etc.
4556    EVT EltVT = VT.getVectorElementType();
4557    ShAmt *= EltVT.getSizeInBits();
4558    return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4559  }
4560
4561  if (X86::isMOVLMask(SVOp)) {
4562    if (V1IsUndef)
4563      return V2;
4564    if (ISD::isBuildVectorAllZeros(V1.getNode()))
4565      return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4566    if (!isMMX)
4567      return Op;
4568  }
4569
4570  // FIXME: fold these into legal mask.
4571  if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4572                 X86::isMOVSLDUPMask(SVOp) ||
4573                 X86::isMOVHLPSMask(SVOp) ||
4574                 X86::isMOVLHPSMask(SVOp) ||
4575                 X86::isMOVLPMask(SVOp)))
4576    return Op;
4577
4578  if (ShouldXformToMOVHLPS(SVOp) ||
4579      ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4580    return CommuteVectorShuffle(SVOp, DAG);
4581
4582  if (isShift) {
4583    // No better options. Use a vshl / vsrl.
4584    EVT EltVT = VT.getVectorElementType();
4585    ShAmt *= EltVT.getSizeInBits();
4586    return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4587  }
4588
4589  bool Commuted = false;
4590  // FIXME: This should also accept a bitcast of a splat?  Be careful, not
4591  // 1,1,1,1 -> v8i16 though.
4592  V1IsSplat = isSplatVector(V1.getNode());
4593  V2IsSplat = isSplatVector(V2.getNode());
4594
4595  // Canonicalize the splat or undef, if present, to be on the RHS.
4596  if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4597    Op = CommuteVectorShuffle(SVOp, DAG);
4598    SVOp = cast<ShuffleVectorSDNode>(Op);
4599    V1 = SVOp->getOperand(0);
4600    V2 = SVOp->getOperand(1);
4601    std::swap(V1IsSplat, V2IsSplat);
4602    std::swap(V1IsUndef, V2IsUndef);
4603    Commuted = true;
4604  }
4605
4606  if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4607    // Shuffling low element of v1 into undef, just return v1.
4608    if (V2IsUndef)
4609      return V1;
4610    // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4611    // the instruction selector will not match, so get a canonical MOVL with
4612    // swapped operands to undo the commute.
4613    return getMOVL(DAG, dl, VT, V2, V1);
4614  }
4615
4616  if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4617      X86::isUNPCKH_v_undef_Mask(SVOp) ||
4618      X86::isUNPCKLMask(SVOp) ||
4619      X86::isUNPCKHMask(SVOp))
4620    return Op;
4621
4622  if (V2IsSplat) {
4623    // Normalize mask so all entries that point to V2 points to its first
4624    // element then try to match unpck{h|l} again. If match, return a
4625    // new vector_shuffle with the corrected mask.
4626    SDValue NewMask = NormalizeMask(SVOp, DAG);
4627    ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4628    if (NSVOp != SVOp) {
4629      if (X86::isUNPCKLMask(NSVOp, true)) {
4630        return NewMask;
4631      } else if (X86::isUNPCKHMask(NSVOp, true)) {
4632        return NewMask;
4633      }
4634    }
4635  }
4636
4637  if (Commuted) {
4638    // Commute is back and try unpck* again.
4639    // FIXME: this seems wrong.
4640    SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4641    ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4642    if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4643        X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4644        X86::isUNPCKLMask(NewSVOp) ||
4645        X86::isUNPCKHMask(NewSVOp))
4646      return NewOp;
4647  }
4648
4649  // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4650
4651  // Normalize the node to match x86 shuffle ops if needed
4652  if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4653    return CommuteVectorShuffle(SVOp, DAG);
4654
4655  // Check for legal shuffle and return?
4656  SmallVector<int, 16> PermMask;
4657  SVOp->getMask(PermMask);
4658  if (isShuffleMaskLegal(PermMask, VT))
4659    return Op;
4660
4661  // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4662  if (VT == MVT::v8i16) {
4663    SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4664    if (NewOp.getNode())
4665      return NewOp;
4666  }
4667
4668  if (VT == MVT::v16i8) {
4669    SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4670    if (NewOp.getNode())
4671      return NewOp;
4672  }
4673
4674  // Handle all 4 wide cases with a number of shuffles except for MMX.
4675  if (NumElems == 4 && !isMMX)
4676    return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4677
4678  return SDValue();
4679}
4680
4681SDValue
4682X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4683                                                SelectionDAG &DAG) {
4684  EVT VT = Op.getValueType();
4685  DebugLoc dl = Op.getDebugLoc();
4686  if (VT.getSizeInBits() == 8) {
4687    SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4688                                    Op.getOperand(0), Op.getOperand(1));
4689    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4690                                    DAG.getValueType(VT));
4691    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4692  } else if (VT.getSizeInBits() == 16) {
4693    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4694    // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4695    if (Idx == 0)
4696      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4697                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4698                                     DAG.getNode(ISD::BIT_CONVERT, dl,
4699                                                 MVT::v4i32,
4700                                                 Op.getOperand(0)),
4701                                     Op.getOperand(1)));
4702    SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4703                                    Op.getOperand(0), Op.getOperand(1));
4704    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4705                                    DAG.getValueType(VT));
4706    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4707  } else if (VT == MVT::f32) {
4708    // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4709    // the result back to FR32 register. It's only worth matching if the
4710    // result has a single use which is a store or a bitcast to i32.  And in
4711    // the case of a store, it's not worth it if the index is a constant 0,
4712    // because a MOVSSmr can be used instead, which is smaller and faster.
4713    if (!Op.hasOneUse())
4714      return SDValue();
4715    SDNode *User = *Op.getNode()->use_begin();
4716    if ((User->getOpcode() != ISD::STORE ||
4717         (isa<ConstantSDNode>(Op.getOperand(1)) &&
4718          cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4719        (User->getOpcode() != ISD::BIT_CONVERT ||
4720         User->getValueType(0) != MVT::i32))
4721      return SDValue();
4722    SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4723                                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4724                                              Op.getOperand(0)),
4725                                              Op.getOperand(1));
4726    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4727  } else if (VT == MVT::i32) {
4728    // ExtractPS works with constant index.
4729    if (isa<ConstantSDNode>(Op.getOperand(1)))
4730      return Op;
4731  }
4732  return SDValue();
4733}
4734
4735
4736SDValue
4737X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4738  if (!isa<ConstantSDNode>(Op.getOperand(1)))
4739    return SDValue();
4740
4741  if (Subtarget->hasSSE41()) {
4742    SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4743    if (Res.getNode())
4744      return Res;
4745  }
4746
4747  EVT VT = Op.getValueType();
4748  DebugLoc dl = Op.getDebugLoc();
4749  // TODO: handle v16i8.
4750  if (VT.getSizeInBits() == 16) {
4751    SDValue Vec = Op.getOperand(0);
4752    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4753    if (Idx == 0)
4754      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4755                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4756                                     DAG.getNode(ISD::BIT_CONVERT, dl,
4757                                                 MVT::v4i32, Vec),
4758                                     Op.getOperand(1)));
4759    // Transform it so it match pextrw which produces a 32-bit result.
4760    EVT EltVT = MVT::i32;
4761    SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4762                                    Op.getOperand(0), Op.getOperand(1));
4763    SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4764                                    DAG.getValueType(VT));
4765    return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4766  } else if (VT.getSizeInBits() == 32) {
4767    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4768    if (Idx == 0)
4769      return Op;
4770
4771    // SHUFPS the element to the lowest double word, then movss.
4772    int Mask[4] = { Idx, -1, -1, -1 };
4773    EVT VVT = Op.getOperand(0).getValueType();
4774    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4775                                       DAG.getUNDEF(VVT), Mask);
4776    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4777                       DAG.getIntPtrConstant(0));
4778  } else if (VT.getSizeInBits() == 64) {
4779    // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4780    // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4781    //        to match extract_elt for f64.
4782    unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4783    if (Idx == 0)
4784      return Op;
4785
4786    // UNPCKHPD the element to the lowest double word, then movsd.
4787    // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4788    // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4789    int Mask[2] = { 1, -1 };
4790    EVT VVT = Op.getOperand(0).getValueType();
4791    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4792                                       DAG.getUNDEF(VVT), Mask);
4793    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4794                       DAG.getIntPtrConstant(0));
4795  }
4796
4797  return SDValue();
4798}
4799
4800SDValue
4801X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4802  EVT VT = Op.getValueType();
4803  EVT EltVT = VT.getVectorElementType();
4804  DebugLoc dl = Op.getDebugLoc();
4805
4806  SDValue N0 = Op.getOperand(0);
4807  SDValue N1 = Op.getOperand(1);
4808  SDValue N2 = Op.getOperand(2);
4809
4810  if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4811      isa<ConstantSDNode>(N2)) {
4812    unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4813                                                : X86ISD::PINSRW;
4814    // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4815    // argument.
4816    if (N1.getValueType() != MVT::i32)
4817      N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4818    if (N2.getValueType() != MVT::i32)
4819      N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4820    return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4821  } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4822    // Bits [7:6] of the constant are the source select.  This will always be
4823    //  zero here.  The DAG Combiner may combine an extract_elt index into these
4824    //  bits.  For example (insert (extract, 3), 2) could be matched by putting
4825    //  the '3' into bits [7:6] of X86ISD::INSERTPS.
4826    // Bits [5:4] of the constant are the destination select.  This is the
4827    //  value of the incoming immediate.
4828    // Bits [3:0] of the constant are the zero mask.  The DAG Combiner may
4829    //   combine either bitwise AND or insert of float 0.0 to set these bits.
4830    N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4831    // Create this as a scalar to vector..
4832    N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4833    return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4834  } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4835    // PINSR* works with constant index.
4836    return Op;
4837  }
4838  return SDValue();
4839}
4840
4841SDValue
4842X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4843  EVT VT = Op.getValueType();
4844  EVT EltVT = VT.getVectorElementType();
4845
4846  if (Subtarget->hasSSE41())
4847    return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4848
4849  if (EltVT == MVT::i8)
4850    return SDValue();
4851
4852  DebugLoc dl = Op.getDebugLoc();
4853  SDValue N0 = Op.getOperand(0);
4854  SDValue N1 = Op.getOperand(1);
4855  SDValue N2 = Op.getOperand(2);
4856
4857  if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4858    // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4859    // as its second argument.
4860    if (N1.getValueType() != MVT::i32)
4861      N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4862    if (N2.getValueType() != MVT::i32)
4863      N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4864    return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4865  }
4866  return SDValue();
4867}
4868
4869SDValue
4870X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4871  DebugLoc dl = Op.getDebugLoc();
4872  if (Op.getValueType() == MVT::v2f32)
4873    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4874                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4875                                   DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4876                                               Op.getOperand(0))));
4877
4878  if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4879    return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4880
4881  SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4882  EVT VT = MVT::v2i32;
4883  switch (Op.getValueType().getSimpleVT().SimpleTy) {
4884  default: break;
4885  case MVT::v16i8:
4886  case MVT::v8i16:
4887    VT = MVT::v4i32;
4888    break;
4889  }
4890  return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4891                     DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4892}
4893
4894// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4895// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4896// one of the above mentioned nodes. It has to be wrapped because otherwise
4897// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4898// be used to form addressing mode. These wrapped nodes will be selected
4899// into MOV32ri.
4900SDValue
4901X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4902  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4903
4904  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4905  // global base reg.
4906  unsigned char OpFlag = 0;
4907  unsigned WrapperKind = X86ISD::Wrapper;
4908  CodeModel::Model M = getTargetMachine().getCodeModel();
4909
4910  if (Subtarget->isPICStyleRIPRel() &&
4911      (M == CodeModel::Small || M == CodeModel::Kernel))
4912    WrapperKind = X86ISD::WrapperRIP;
4913  else if (Subtarget->isPICStyleGOT())
4914    OpFlag = X86II::MO_GOTOFF;
4915  else if (Subtarget->isPICStyleStubPIC())
4916    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4917
4918  SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4919                                             CP->getAlignment(),
4920                                             CP->getOffset(), OpFlag);
4921  DebugLoc DL = CP->getDebugLoc();
4922  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4923  // With PIC, the address is actually $g + Offset.
4924  if (OpFlag) {
4925    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4926                         DAG.getNode(X86ISD::GlobalBaseReg,
4927                                     DebugLoc::getUnknownLoc(), getPointerTy()),
4928                         Result);
4929  }
4930
4931  return Result;
4932}
4933
4934SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4935  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4936
4937  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4938  // global base reg.
4939  unsigned char OpFlag = 0;
4940  unsigned WrapperKind = X86ISD::Wrapper;
4941  CodeModel::Model M = getTargetMachine().getCodeModel();
4942
4943  if (Subtarget->isPICStyleRIPRel() &&
4944      (M == CodeModel::Small || M == CodeModel::Kernel))
4945    WrapperKind = X86ISD::WrapperRIP;
4946  else if (Subtarget->isPICStyleGOT())
4947    OpFlag = X86II::MO_GOTOFF;
4948  else if (Subtarget->isPICStyleStubPIC())
4949    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4950
4951  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4952                                          OpFlag);
4953  DebugLoc DL = JT->getDebugLoc();
4954  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4955
4956  // With PIC, the address is actually $g + Offset.
4957  if (OpFlag) {
4958    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4959                         DAG.getNode(X86ISD::GlobalBaseReg,
4960                                     DebugLoc::getUnknownLoc(), getPointerTy()),
4961                         Result);
4962  }
4963
4964  return Result;
4965}
4966
4967SDValue
4968X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4969  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4970
4971  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4972  // global base reg.
4973  unsigned char OpFlag = 0;
4974  unsigned WrapperKind = X86ISD::Wrapper;
4975  CodeModel::Model M = getTargetMachine().getCodeModel();
4976
4977  if (Subtarget->isPICStyleRIPRel() &&
4978      (M == CodeModel::Small || M == CodeModel::Kernel))
4979    WrapperKind = X86ISD::WrapperRIP;
4980  else if (Subtarget->isPICStyleGOT())
4981    OpFlag = X86II::MO_GOTOFF;
4982  else if (Subtarget->isPICStyleStubPIC())
4983    OpFlag = X86II::MO_PIC_BASE_OFFSET;
4984
4985  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4986
4987  DebugLoc DL = Op.getDebugLoc();
4988  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4989
4990
4991  // With PIC, the address is actually $g + Offset.
4992  if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4993      !Subtarget->is64Bit()) {
4994    Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4995                         DAG.getNode(X86ISD::GlobalBaseReg,
4996                                     DebugLoc::getUnknownLoc(),
4997                                     getPointerTy()),
4998                         Result);
4999  }
5000
5001  return Result;
5002}
5003
5004SDValue
5005X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5006  // Create the TargetBlockAddressAddress node.
5007  unsigned char OpFlags =
5008    Subtarget->ClassifyBlockAddressReference();
5009  CodeModel::Model M = getTargetMachine().getCodeModel();
5010  BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5011  DebugLoc dl = Op.getDebugLoc();
5012  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5013                                       /*isTarget=*/true, OpFlags);
5014
5015  if (Subtarget->isPICStyleRIPRel() &&
5016      (M == CodeModel::Small || M == CodeModel::Kernel))
5017    Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5018  else
5019    Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5020
5021  // With PIC, the address is actually $g + Offset.
5022  if (isGlobalRelativeToPICBase(OpFlags)) {
5023    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5024                         DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5025                         Result);
5026  }
5027
5028  return Result;
5029}
5030
5031SDValue
5032X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5033                                      int64_t Offset,
5034                                      SelectionDAG &DAG) const {
5035  // Create the TargetGlobalAddress node, folding in the constant
5036  // offset if it is legal.
5037  unsigned char OpFlags =
5038    Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5039  CodeModel::Model M = getTargetMachine().getCodeModel();
5040  SDValue Result;
5041  if (OpFlags == X86II::MO_NO_FLAG &&
5042      X86::isOffsetSuitableForCodeModel(Offset, M)) {
5043    // A direct static reference to a global.
5044    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5045    Offset = 0;
5046  } else {
5047    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5048  }
5049
5050  if (Subtarget->isPICStyleRIPRel() &&
5051      (M == CodeModel::Small || M == CodeModel::Kernel))
5052    Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5053  else
5054    Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5055
5056  // With PIC, the address is actually $g + Offset.
5057  if (isGlobalRelativeToPICBase(OpFlags)) {
5058    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5059                         DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5060                         Result);
5061  }
5062
5063  // For globals that require a load from a stub to get the address, emit the
5064  // load.
5065  if (isGlobalStubReference(OpFlags))
5066    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5067                         PseudoSourceValue::getGOT(), 0);
5068
5069  // If there was a non-zero offset that we didn't fold, create an explicit
5070  // addition for it.
5071  if (Offset != 0)
5072    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5073                         DAG.getConstant(Offset, getPointerTy()));
5074
5075  return Result;
5076}
5077
5078SDValue
5079X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5080  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5081  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5082  return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5083}
5084
5085static SDValue
5086GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5087           SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5088           unsigned char OperandFlags) {
5089  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5090  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5091  DebugLoc dl = GA->getDebugLoc();
5092  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5093                                           GA->getValueType(0),
5094                                           GA->getOffset(),
5095                                           OperandFlags);
5096  if (InFlag) {
5097    SDValue Ops[] = { Chain,  TGA, *InFlag };
5098    Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5099  } else {
5100    SDValue Ops[]  = { Chain, TGA };
5101    Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5102  }
5103
5104  // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5105  MFI->setHasCalls(true);
5106
5107  SDValue Flag = Chain.getValue(1);
5108  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5109}
5110
5111// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5112static SDValue
5113LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5114                                const EVT PtrVT) {
5115  SDValue InFlag;
5116  DebugLoc dl = GA->getDebugLoc();  // ? function entry point might be better
5117  SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5118                                     DAG.getNode(X86ISD::GlobalBaseReg,
5119                                                 DebugLoc::getUnknownLoc(),
5120                                                 PtrVT), InFlag);
5121  InFlag = Chain.getValue(1);
5122
5123  return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5124}
5125
5126// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5127static SDValue
5128LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5129                                const EVT PtrVT) {
5130  return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5131                    X86::RAX, X86II::MO_TLSGD);
5132}
5133
5134// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5135// "local exec" model.
5136static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5137                                   const EVT PtrVT, TLSModel::Model model,
5138                                   bool is64Bit) {
5139  DebugLoc dl = GA->getDebugLoc();
5140  // Get the Thread Pointer
5141  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5142                             DebugLoc::getUnknownLoc(), PtrVT,
5143                             DAG.getRegister(is64Bit? X86::FS : X86::GS,
5144                                             MVT::i32));
5145
5146  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5147                                      NULL, 0);
5148
5149  unsigned char OperandFlags = 0;
5150  // Most TLS accesses are not RIP relative, even on x86-64.  One exception is
5151  // initialexec.
5152  unsigned WrapperKind = X86ISD::Wrapper;
5153  if (model == TLSModel::LocalExec) {
5154    OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5155  } else if (is64Bit) {
5156    assert(model == TLSModel::InitialExec);
5157    OperandFlags = X86II::MO_GOTTPOFF;
5158    WrapperKind = X86ISD::WrapperRIP;
5159  } else {
5160    assert(model == TLSModel::InitialExec);
5161    OperandFlags = X86II::MO_INDNTPOFF;
5162  }
5163
5164  // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5165  // exec)
5166  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5167                                           GA->getOffset(), OperandFlags);
5168  SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5169
5170  if (model == TLSModel::InitialExec)
5171    Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5172                         PseudoSourceValue::getGOT(), 0);
5173
5174  // The address of the thread local variable is the add of the thread
5175  // pointer with the offset of the variable.
5176  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5177}
5178
5179SDValue
5180X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5181  // TODO: implement the "local dynamic" model
5182  // TODO: implement the "initial exec"model for pic executables
5183  assert(Subtarget->isTargetELF() &&
5184         "TLS not implemented for non-ELF targets");
5185  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5186  const GlobalValue *GV = GA->getGlobal();
5187
5188  // If GV is an alias then use the aliasee for determining
5189  // thread-localness.
5190  if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5191    GV = GA->resolveAliasedGlobal(false);
5192
5193  TLSModel::Model model = getTLSModel(GV,
5194                                      getTargetMachine().getRelocationModel());
5195
5196  switch (model) {
5197  case TLSModel::GeneralDynamic:
5198  case TLSModel::LocalDynamic: // not implemented
5199    if (Subtarget->is64Bit())
5200      return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5201    return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5202
5203  case TLSModel::InitialExec:
5204  case TLSModel::LocalExec:
5205    return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5206                               Subtarget->is64Bit());
5207  }
5208
5209  llvm_unreachable("Unreachable");
5210  return SDValue();
5211}
5212
5213
5214/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5215/// take a 2 x i32 value to shift plus a shift amount.
5216SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5217  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5218  EVT VT = Op.getValueType();
5219  unsigned VTBits = VT.getSizeInBits();
5220  DebugLoc dl = Op.getDebugLoc();
5221  bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5222  SDValue ShOpLo = Op.getOperand(0);
5223  SDValue ShOpHi = Op.getOperand(1);
5224  SDValue ShAmt  = Op.getOperand(2);
5225  SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5226                                     DAG.getConstant(VTBits - 1, MVT::i8))
5227                       : DAG.getConstant(0, VT);
5228
5229  SDValue Tmp2, Tmp3;
5230  if (Op.getOpcode() == ISD::SHL_PARTS) {
5231    Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5232    Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5233  } else {
5234    Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5235    Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5236  }
5237
5238  SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5239                                DAG.getConstant(VTBits, MVT::i8));
5240  SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5241                             AndNode, DAG.getConstant(0, MVT::i8));
5242
5243  SDValue Hi, Lo;
5244  SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5245  SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5246  SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5247
5248  if (Op.getOpcode() == ISD::SHL_PARTS) {
5249    Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5250    Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5251  } else {
5252    Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5253    Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5254  }
5255
5256  SDValue Ops[2] = { Lo, Hi };
5257  return DAG.getMergeValues(Ops, 2, dl);
5258}
5259
5260SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5261  EVT SrcVT = Op.getOperand(0).getValueType();
5262
5263  if (SrcVT.isVector()) {
5264    if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5265      return Op;
5266    }
5267    return SDValue();
5268  }
5269
5270  assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5271         "Unknown SINT_TO_FP to lower!");
5272
5273  // These are really Legal; return the operand so the caller accepts it as
5274  // Legal.
5275  if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5276    return Op;
5277  if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5278      Subtarget->is64Bit()) {
5279    return Op;
5280  }
5281
5282  DebugLoc dl = Op.getDebugLoc();
5283  unsigned Size = SrcVT.getSizeInBits()/8;
5284  MachineFunction &MF = DAG.getMachineFunction();
5285  int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5286  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5287  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5288                               StackSlot,
5289                               PseudoSourceValue::getFixedStack(SSFI), 0);
5290  return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5291}
5292
5293SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5294                                     SDValue StackSlot,
5295                                     SelectionDAG &DAG) {
5296  // Build the FILD
5297  DebugLoc dl = Op.getDebugLoc();
5298  SDVTList Tys;
5299  bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5300  if (useSSE)
5301    Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5302  else
5303    Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5304  SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5305  SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5306                               Tys, Ops, array_lengthof(Ops));
5307
5308  if (useSSE) {
5309    Chain = Result.getValue(1);
5310    SDValue InFlag = Result.getValue(2);
5311
5312    // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5313    // shouldn't be necessary except that RFP cannot be live across
5314    // multiple blocks. When stackifier is fixed, they can be uncoupled.
5315    MachineFunction &MF = DAG.getMachineFunction();
5316    int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5317    SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5318    Tys = DAG.getVTList(MVT::Other);
5319    SDValue Ops[] = {
5320      Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5321    };
5322    Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5323    Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5324                         PseudoSourceValue::getFixedStack(SSFI), 0);
5325  }
5326
5327  return Result;
5328}
5329
5330// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5331SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5332  // This algorithm is not obvious. Here it is in C code, more or less:
5333  /*
5334    double uint64_to_double( uint32_t hi, uint32_t lo ) {
5335      static const __m128i exp = { 0x4330000045300000ULL, 0 };
5336      static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5337
5338      // Copy ints to xmm registers.
5339      __m128i xh = _mm_cvtsi32_si128( hi );
5340      __m128i xl = _mm_cvtsi32_si128( lo );
5341
5342      // Combine into low half of a single xmm register.
5343      __m128i x = _mm_unpacklo_epi32( xh, xl );
5344      __m128d d;
5345      double sd;
5346
5347      // Merge in appropriate exponents to give the integer bits the right
5348      // magnitude.
5349      x = _mm_unpacklo_epi32( x, exp );
5350
5351      // Subtract away the biases to deal with the IEEE-754 double precision
5352      // implicit 1.
5353      d = _mm_sub_pd( (__m128d) x, bias );
5354
5355      // All conversions up to here are exact. The correctly rounded result is
5356      // calculated using the current rounding mode using the following
5357      // horizontal add.
5358      d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5359      _mm_store_sd( &sd, d );   // Because we are returning doubles in XMM, this
5360                                // store doesn't really need to be here (except
5361                                // maybe to zero the other double)
5362      return sd;
5363    }
5364  */
5365
5366  DebugLoc dl = Op.getDebugLoc();
5367  LLVMContext *Context = DAG.getContext();
5368
5369  // Build some magic constants.
5370  std::vector<Constant*> CV0;
5371  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5372  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5373  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5374  CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5375  Constant *C0 = ConstantVector::get(CV0);
5376  SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5377
5378  std::vector<Constant*> CV1;
5379  CV1.push_back(
5380    ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5381  CV1.push_back(
5382    ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5383  Constant *C1 = ConstantVector::get(CV1);
5384  SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5385
5386  SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5387                            DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5388                                        Op.getOperand(0),
5389                                        DAG.getIntPtrConstant(1)));
5390  SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5391                            DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5392                                        Op.getOperand(0),
5393                                        DAG.getIntPtrConstant(0)));
5394  SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5395  SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5396                              PseudoSourceValue::getConstantPool(), 0,
5397                              false, 16);
5398  SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5399  SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5400  SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5401                              PseudoSourceValue::getConstantPool(), 0,
5402                              false, 16);
5403  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5404
5405  // Add the halves; easiest way is to swap them into another reg first.
5406  int ShufMask[2] = { 1, -1 };
5407  SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5408                                      DAG.getUNDEF(MVT::v2f64), ShufMask);
5409  SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5410  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5411                     DAG.getIntPtrConstant(0));
5412}
5413
5414// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5415SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5416  DebugLoc dl = Op.getDebugLoc();
5417  // FP constant to bias correct the final result.
5418  SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5419                                   MVT::f64);
5420
5421  // Load the 32-bit value into an XMM register.
5422  SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5423                             DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5424                                         Op.getOperand(0),
5425                                         DAG.getIntPtrConstant(0)));
5426
5427  Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5428                     DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5429                     DAG.getIntPtrConstant(0));
5430
5431  // Or the load with the bias.
5432  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5433                           DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5434                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5435                                                   MVT::v2f64, Load)),
5436                           DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5437                                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5438                                                   MVT::v2f64, Bias)));
5439  Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5440                   DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5441                   DAG.getIntPtrConstant(0));
5442
5443  // Subtract the bias.
5444  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5445
5446  // Handle final rounding.
5447  EVT DestVT = Op.getValueType();
5448
5449  if (DestVT.bitsLT(MVT::f64)) {
5450    return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5451                       DAG.getIntPtrConstant(0));
5452  } else if (DestVT.bitsGT(MVT::f64)) {
5453    return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5454  }
5455
5456  // Handle final rounding.
5457  return Sub;
5458}
5459
5460SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5461  SDValue N0 = Op.getOperand(0);
5462  DebugLoc dl = Op.getDebugLoc();
5463
5464  // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5465  // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5466  // the optimization here.
5467  if (DAG.SignBitIsZero(N0))
5468    return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5469
5470  EVT SrcVT = N0.getValueType();
5471  if (SrcVT == MVT::i64) {
5472    // We only handle SSE2 f64 target here; caller can expand the rest.
5473    if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5474      return SDValue();
5475
5476    return LowerUINT_TO_FP_i64(Op, DAG);
5477  } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5478    return LowerUINT_TO_FP_i32(Op, DAG);
5479  }
5480
5481  assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5482
5483  // Make a 64-bit buffer, and use it to build an FILD.
5484  SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5485  SDValue WordOff = DAG.getConstant(4, getPointerTy());
5486  SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5487                                   getPointerTy(), StackSlot, WordOff);
5488  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5489                                StackSlot, NULL, 0);
5490  SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5491                                OffsetSlot, NULL, 0);
5492  return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5493}
5494
5495std::pair<SDValue,SDValue> X86TargetLowering::
5496FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5497  DebugLoc dl = Op.getDebugLoc();
5498
5499  EVT DstTy = Op.getValueType();
5500
5501  if (!IsSigned) {
5502    assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5503    DstTy = MVT::i64;
5504  }
5505
5506  assert(DstTy.getSimpleVT() <= MVT::i64 &&
5507         DstTy.getSimpleVT() >= MVT::i16 &&
5508         "Unknown FP_TO_SINT to lower!");
5509
5510  // These are really Legal.
5511  if (DstTy == MVT::i32 &&
5512      isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5513    return std::make_pair(SDValue(), SDValue());
5514  if (Subtarget->is64Bit() &&
5515      DstTy == MVT::i64 &&
5516      isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5517    return std::make_pair(SDValue(), SDValue());
5518
5519  // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5520  // stack slot.
5521  MachineFunction &MF = DAG.getMachineFunction();
5522  unsigned MemSize = DstTy.getSizeInBits()/8;
5523  int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5524  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5525
5526  unsigned Opc;
5527  switch (DstTy.getSimpleVT().SimpleTy) {
5528  default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5529  case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5530  case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5531  case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5532  }
5533
5534  SDValue Chain = DAG.getEntryNode();
5535  SDValue Value = Op.getOperand(0);
5536  if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5537    assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5538    Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5539                         PseudoSourceValue::getFixedStack(SSFI), 0);
5540    SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5541    SDValue Ops[] = {
5542      Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5543    };
5544    Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5545    Chain = Value.getValue(1);
5546    SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5547    StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5548  }
5549
5550  // Build the FP_TO_INT*_IN_MEM
5551  SDValue Ops[] = { Chain, Value, StackSlot };
5552  SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5553
5554  return std::make_pair(FIST, StackSlot);
5555}
5556
5557SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5558  if (Op.getValueType().isVector()) {
5559    if (Op.getValueType() == MVT::v2i32 &&
5560        Op.getOperand(0).getValueType() == MVT::v2f64) {
5561      return Op;
5562    }
5563    return SDValue();
5564  }
5565
5566  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5567  SDValue FIST = Vals.first, StackSlot = Vals.second;
5568  // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5569  if (FIST.getNode() == 0) return Op;
5570
5571  // Load the result.
5572  return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5573                     FIST, StackSlot, NULL, 0);
5574}
5575
5576SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5577  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5578  SDValue FIST = Vals.first, StackSlot = Vals.second;
5579  assert(FIST.getNode() && "Unexpected failure");
5580
5581  // Load the result.
5582  return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5583                     FIST, StackSlot, NULL, 0);
5584}
5585
5586SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5587  LLVMContext *Context = DAG.getContext();
5588  DebugLoc dl = Op.getDebugLoc();
5589  EVT VT = Op.getValueType();
5590  EVT EltVT = VT;
5591  if (VT.isVector())
5592    EltVT = VT.getVectorElementType();
5593  std::vector<Constant*> CV;
5594  if (EltVT == MVT::f64) {
5595    Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5596    CV.push_back(C);
5597    CV.push_back(C);
5598  } else {
5599    Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5600    CV.push_back(C);
5601    CV.push_back(C);
5602    CV.push_back(C);
5603    CV.push_back(C);
5604  }
5605  Constant *C = ConstantVector::get(CV);
5606  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5607  SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5608                               PseudoSourceValue::getConstantPool(), 0,
5609                               false, 16);
5610  return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5611}
5612
5613SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5614  LLVMContext *Context = DAG.getContext();
5615  DebugLoc dl = Op.getDebugLoc();
5616  EVT VT = Op.getValueType();
5617  EVT EltVT = VT;
5618  if (VT.isVector())
5619    EltVT = VT.getVectorElementType();
5620  std::vector<Constant*> CV;
5621  if (EltVT == MVT::f64) {
5622    Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5623    CV.push_back(C);
5624    CV.push_back(C);
5625  } else {
5626    Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5627    CV.push_back(C);
5628    CV.push_back(C);
5629    CV.push_back(C);
5630    CV.push_back(C);
5631  }
5632  Constant *C = ConstantVector::get(CV);
5633  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5634  SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5635                               PseudoSourceValue::getConstantPool(), 0,
5636                               false, 16);
5637  if (VT.isVector()) {
5638    return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5639                       DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5640                    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5641                                Op.getOperand(0)),
5642                    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5643  } else {
5644    return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5645  }
5646}
5647
5648SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5649  LLVMContext *Context = DAG.getContext();
5650  SDValue Op0 = Op.getOperand(0);
5651  SDValue Op1 = Op.getOperand(1);
5652  DebugLoc dl = Op.getDebugLoc();
5653  EVT VT = Op.getValueType();
5654  EVT SrcVT = Op1.getValueType();
5655
5656  // If second operand is smaller, extend it first.
5657  if (SrcVT.bitsLT(VT)) {
5658    Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5659    SrcVT = VT;
5660  }
5661  // And if it is bigger, shrink it first.
5662  if (SrcVT.bitsGT(VT)) {
5663    Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5664    SrcVT = VT;
5665  }
5666
5667  // At this point the operands and the result should have the same
5668  // type, and that won't be f80 since that is not custom lowered.
5669
5670  // First get the sign bit of second operand.
5671  std::vector<Constant*> CV;
5672  if (SrcVT == MVT::f64) {
5673    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5674    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5675  } else {
5676    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5677    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5678    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5679    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5680  }
5681  Constant *C = ConstantVector::get(CV);
5682  SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5683  SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5684                                PseudoSourceValue::getConstantPool(), 0,
5685                                false, 16);
5686  SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5687
5688  // Shift sign bit right or left if the two operands have different types.
5689  if (SrcVT.bitsGT(VT)) {
5690    // Op0 is MVT::f32, Op1 is MVT::f64.
5691    SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5692    SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5693                          DAG.getConstant(32, MVT::i32));
5694    SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5695    SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5696                          DAG.getIntPtrConstant(0));
5697  }
5698
5699  // Clear first operand sign bit.
5700  CV.clear();
5701  if (VT == MVT::f64) {
5702    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5703    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5704  } else {
5705    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5706    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5707    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5708    CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5709  }
5710  C = ConstantVector::get(CV);
5711  CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5712  SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5713                                PseudoSourceValue::getConstantPool(), 0,
5714                                false, 16);
5715  SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5716
5717  // Or the value with the sign bit.
5718  return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5719}
5720
5721/// Emit nodes that will be selected as "test Op0,Op0", or something
5722/// equivalent.
5723SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5724                                    SelectionDAG &DAG) {
5725  DebugLoc dl = Op.getDebugLoc();
5726
5727  // CF and OF aren't always set the way we want. Determine which
5728  // of these we need.
5729  bool NeedCF = false;
5730  bool NeedOF = false;
5731  switch (X86CC) {
5732  case X86::COND_A: case X86::COND_AE:
5733  case X86::COND_B: case X86::COND_BE:
5734    NeedCF = true;
5735    break;
5736  case X86::COND_G: case X86::COND_GE:
5737  case X86::COND_L: case X86::COND_LE:
5738  case X86::COND_O: case X86::COND_NO:
5739    NeedOF = true;
5740    break;
5741  default: break;
5742  }
5743
5744  // See if we can use the EFLAGS value from the operand instead of
5745  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5746  // we prove that the arithmetic won't overflow, we can't use OF or CF.
5747  if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5748    unsigned Opcode = 0;
5749    unsigned NumOperands = 0;
5750    switch (Op.getNode()->getOpcode()) {
5751    case ISD::ADD:
5752      // Due to an isel shortcoming, be conservative if this add is likely to
5753      // be selected as part of a load-modify-store instruction. When the root
5754      // node in a match is a store, isel doesn't know how to remap non-chain
5755      // non-flag uses of other nodes in the match, such as the ADD in this
5756      // case. This leads to the ADD being left around and reselected, with
5757      // the result being two adds in the output.
5758      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5759           UE = Op.getNode()->use_end(); UI != UE; ++UI)
5760        if (UI->getOpcode() == ISD::STORE)
5761          goto default_case;
5762      if (ConstantSDNode *C =
5763            dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5764        // An add of one will be selected as an INC.
5765        if (C->getAPIntValue() == 1) {
5766          Opcode = X86ISD::INC;
5767          NumOperands = 1;
5768          break;
5769        }
5770        // An add of negative one (subtract of one) will be selected as a DEC.
5771        if (C->getAPIntValue().isAllOnesValue()) {
5772          Opcode = X86ISD::DEC;
5773          NumOperands = 1;
5774          break;
5775        }
5776      }
5777      // Otherwise use a regular EFLAGS-setting add.
5778      Opcode = X86ISD::ADD;
5779      NumOperands = 2;
5780      break;
5781    case ISD::AND: {
5782      // If the primary and result isn't used, don't bother using X86ISD::AND,
5783      // because a TEST instruction will be better.
5784      bool NonFlagUse = false;
5785      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5786             UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5787        SDNode *User = *UI;
5788        unsigned UOpNo = UI.getOperandNo();
5789        if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5790          // Look pass truncate.
5791          UOpNo = User->use_begin().getOperandNo();
5792          User = *User->use_begin();
5793        }
5794        if (User->getOpcode() != ISD::BRCOND &&
5795            User->getOpcode() != ISD::SETCC &&
5796            (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5797          NonFlagUse = true;
5798          break;
5799        }
5800      }
5801      if (!NonFlagUse)
5802        break;
5803    }
5804    // FALL THROUGH
5805    case ISD::SUB:
5806    case ISD::OR:
5807    case ISD::XOR:
5808      // Due to the ISEL shortcoming noted above, be conservative if this op is
5809      // likely to be selected as part of a load-modify-store instruction.
5810      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5811           UE = Op.getNode()->use_end(); UI != UE; ++UI)
5812        if (UI->getOpcode() == ISD::STORE)
5813          goto default_case;
5814      // Otherwise use a regular EFLAGS-setting instruction.
5815      switch (Op.getNode()->getOpcode()) {
5816      case ISD::SUB: Opcode = X86ISD::SUB; break;
5817      case ISD::OR:  Opcode = X86ISD::OR;  break;
5818      case ISD::XOR: Opcode = X86ISD::XOR; break;
5819      case ISD::AND: Opcode = X86ISD::AND; break;
5820      default: llvm_unreachable("unexpected operator!");
5821      }
5822      NumOperands = 2;
5823      break;
5824    case X86ISD::ADD:
5825    case X86ISD::SUB:
5826    case X86ISD::INC:
5827    case X86ISD::DEC:
5828    case X86ISD::OR:
5829    case X86ISD::XOR:
5830    case X86ISD::AND:
5831      return SDValue(Op.getNode(), 1);
5832    default:
5833    default_case:
5834      break;
5835    }
5836    if (Opcode != 0) {
5837      SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5838      SmallVector<SDValue, 4> Ops;
5839      for (unsigned i = 0; i != NumOperands; ++i)
5840        Ops.push_back(Op.getOperand(i));
5841      SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5842      DAG.ReplaceAllUsesWith(Op, New);
5843      return SDValue(New.getNode(), 1);
5844    }
5845  }
5846
5847  // Otherwise just emit a CMP with 0, which is the TEST pattern.
5848  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5849                     DAG.getConstant(0, Op.getValueType()));
5850}
5851
5852/// Emit nodes that will be selected as "cmp Op0,Op1", or something
5853/// equivalent.
5854SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5855                                   SelectionDAG &DAG) {
5856  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5857    if (C->getAPIntValue() == 0)
5858      return EmitTest(Op0, X86CC, DAG);
5859
5860  DebugLoc dl = Op0.getDebugLoc();
5861  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5862}
5863
5864/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5865/// if it's possible.
5866static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC,
5867                         DebugLoc dl, SelectionDAG &DAG) {
5868  SDValue LHS, RHS;
5869  if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5870    if (ConstantSDNode *Op010C =
5871        dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5872      if (Op010C->getZExtValue() == 1) {
5873        LHS = Op0.getOperand(0);
5874        RHS = Op0.getOperand(1).getOperand(1);
5875      }
5876  } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5877    if (ConstantSDNode *Op000C =
5878        dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5879      if (Op000C->getZExtValue() == 1) {
5880        LHS = Op0.getOperand(1);
5881        RHS = Op0.getOperand(0).getOperand(1);
5882      }
5883  } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5884    ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5885    SDValue AndLHS = Op0.getOperand(0);
5886    if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5887      LHS = AndLHS.getOperand(0);
5888      RHS = AndLHS.getOperand(1);
5889    }
5890  }
5891
5892  if (LHS.getNode()) {
5893    // If LHS is i8, promote it to i16 with any_extend.  There is no i8 BT
5894    // instruction.  Since the shift amount is in-range-or-undefined, we know
5895    // that doing a bittest on the i16 value is ok.  We extend to i32 because
5896    // the encoding for the i16 version is larger than the i32 version.
5897    if (LHS.getValueType() == MVT::i8)
5898      LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5899
5900    // If the operand types disagree, extend the shift amount to match.  Since
5901    // BT ignores high bits (like shifts) we can use anyextend.
5902    if (LHS.getValueType() != RHS.getValueType())
5903      RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5904
5905    SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5906    unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5907    return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5908                       DAG.getConstant(Cond, MVT::i8), BT);
5909  }
5910
5911  return SDValue();
5912}
5913
5914SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5915  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5916  SDValue Op0 = Op.getOperand(0);
5917  SDValue Op1 = Op.getOperand(1);
5918  DebugLoc dl = Op.getDebugLoc();
5919  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5920
5921  // Optimize to BT if possible.
5922  // Lower (X & (1 << N)) == 0 to BT(X, N).
5923  // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5924  // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5925  if (Op0.getOpcode() == ISD::AND &&
5926      Op0.hasOneUse() &&
5927      Op1.getOpcode() == ISD::Constant &&
5928      cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5929      (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5930    SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5931    if (NewSetCC.getNode())
5932      return NewSetCC;
5933  }
5934
5935  bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5936  unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5937  if (X86CC == X86::COND_INVALID)
5938    return SDValue();
5939
5940  SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5941
5942  // Use sbb x, x to materialize carry bit into a GPR.
5943  if (X86CC == X86::COND_B)
5944    return DAG.getNode(ISD::AND, dl, MVT::i8,
5945                       DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5946                                   DAG.getConstant(X86CC, MVT::i8), Cond),
5947                       DAG.getConstant(1, MVT::i8));
5948
5949  return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5950                     DAG.getConstant(X86CC, MVT::i8), Cond);
5951}
5952
5953SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5954  SDValue Cond;
5955  SDValue Op0 = Op.getOperand(0);
5956  SDValue Op1 = Op.getOperand(1);
5957  SDValue CC = Op.getOperand(2);
5958  EVT VT = Op.getValueType();
5959  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5960  bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5961  DebugLoc dl = Op.getDebugLoc();
5962
5963  if (isFP) {
5964    unsigned SSECC = 8;
5965    EVT VT0 = Op0.getValueType();
5966    assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5967    unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5968    bool Swap = false;
5969
5970    switch (SetCCOpcode) {
5971    default: break;
5972    case ISD::SETOEQ:
5973    case ISD::SETEQ:  SSECC = 0; break;
5974    case ISD::SETOGT:
5975    case ISD::SETGT: Swap = true; // Fallthrough
5976    case ISD::SETLT:
5977    case ISD::SETOLT: SSECC = 1; break;
5978    case ISD::SETOGE:
5979    case ISD::SETGE: Swap = true; // Fallthrough
5980    case ISD::SETLE:
5981    case ISD::SETOLE: SSECC = 2; break;
5982    case ISD::SETUO:  SSECC = 3; break;
5983    case ISD::SETUNE:
5984    case ISD::SETNE:  SSECC = 4; break;
5985    case ISD::SETULE: Swap = true;
5986    case ISD::SETUGE: SSECC = 5; break;
5987    case ISD::SETULT: Swap = true;
5988    case ISD::SETUGT: SSECC = 6; break;
5989    case ISD::SETO:   SSECC = 7; break;
5990    }
5991    if (Swap)
5992      std::swap(Op0, Op1);
5993
5994    // In the two special cases we can't handle, emit two comparisons.
5995    if (SSECC == 8) {
5996      if (SetCCOpcode == ISD::SETUEQ) {
5997        SDValue UNORD, EQ;
5998        UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5999        EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6000        return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6001      }
6002      else if (SetCCOpcode == ISD::SETONE) {
6003        SDValue ORD, NEQ;
6004        ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6005        NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6006        return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6007      }
6008      llvm_unreachable("Illegal FP comparison");
6009    }
6010    // Handle all other FP comparisons here.
6011    return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6012  }
6013
6014  // We are handling one of the integer comparisons here.  Since SSE only has
6015  // GT and EQ comparisons for integer, swapping operands and multiple
6016  // operations may be required for some comparisons.
6017  unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6018  bool Swap = false, Invert = false, FlipSigns = false;
6019
6020  switch (VT.getSimpleVT().SimpleTy) {
6021  default: break;
6022  case MVT::v8i8:
6023  case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6024  case MVT::v4i16:
6025  case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6026  case MVT::v2i32:
6027  case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6028  case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6029  }
6030
6031  switch (SetCCOpcode) {
6032  default: break;
6033  case ISD::SETNE:  Invert = true;
6034  case ISD::SETEQ:  Opc = EQOpc; break;
6035  case ISD::SETLT:  Swap = true;
6036  case ISD::SETGT:  Opc = GTOpc; break;
6037  case ISD::SETGE:  Swap = true;
6038  case ISD::SETLE:  Opc = GTOpc; Invert = true; break;
6039  case ISD::SETULT: Swap = true;
6040  case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6041  case ISD::SETUGE: Swap = true;
6042  case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6043  }
6044  if (Swap)
6045    std::swap(Op0, Op1);
6046
6047  // Since SSE has no unsigned integer comparisons, we need to flip  the sign
6048  // bits of the inputs before performing those operations.
6049  if (FlipSigns) {
6050    EVT EltVT = VT.getVectorElementType();
6051    SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6052                                      EltVT);
6053    std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6054    SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6055                                    SignBits.size());
6056    Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6057    Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6058  }
6059
6060  SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6061
6062  // If the logical-not of the result is required, perform that now.
6063  if (Invert)
6064    Result = DAG.getNOT(dl, Result, VT);
6065
6066  return Result;
6067}
6068
6069// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6070static bool isX86LogicalCmp(SDValue Op) {
6071  unsigned Opc = Op.getNode()->getOpcode();
6072  if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6073    return true;
6074  if (Op.getResNo() == 1 &&
6075      (Opc == X86ISD::ADD ||
6076       Opc == X86ISD::SUB ||
6077       Opc == X86ISD::SMUL ||
6078       Opc == X86ISD::UMUL ||
6079       Opc == X86ISD::INC ||
6080       Opc == X86ISD::DEC ||
6081       Opc == X86ISD::OR ||
6082       Opc == X86ISD::XOR ||
6083       Opc == X86ISD::AND))
6084    return true;
6085
6086  return false;
6087}
6088
6089SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6090  bool addTest = true;
6091  SDValue Cond  = Op.getOperand(0);
6092  DebugLoc dl = Op.getDebugLoc();
6093  SDValue CC;
6094
6095  if (Cond.getOpcode() == ISD::SETCC) {
6096    SDValue NewCond = LowerSETCC(Cond, DAG);
6097    if (NewCond.getNode())
6098      Cond = NewCond;
6099  }
6100
6101  // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6102  SDValue Op1 = Op.getOperand(1);
6103  SDValue Op2 = Op.getOperand(2);
6104  if (Cond.getOpcode() == X86ISD::SETCC &&
6105      cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6106    SDValue Cmp = Cond.getOperand(1);
6107    if (Cmp.getOpcode() == X86ISD::CMP) {
6108      ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6109      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6110      ConstantSDNode *RHSC =
6111        dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6112      if (N1C && N1C->isAllOnesValue() &&
6113          N2C && N2C->isNullValue() &&
6114          RHSC && RHSC->isNullValue()) {
6115        SDValue CmpOp0 = Cmp.getOperand(0);
6116        Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(),
6117                          CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6118        return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6119                           DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6120      }
6121    }
6122  }
6123
6124  // Look pass (and (setcc_carry (cmp ...)), 1).
6125  if (Cond.getOpcode() == ISD::AND &&
6126      Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6127    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6128    if (C && C->getAPIntValue() == 1)
6129      Cond = Cond.getOperand(0);
6130  }
6131
6132  // If condition flag is set by a X86ISD::CMP, then use it as the condition
6133  // setting operand in place of the X86ISD::SETCC.
6134  if (Cond.getOpcode() == X86ISD::SETCC ||
6135      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6136    CC = Cond.getOperand(0);
6137
6138    SDValue Cmp = Cond.getOperand(1);
6139    unsigned Opc = Cmp.getOpcode();
6140    EVT VT = Op.getValueType();
6141
6142    bool IllegalFPCMov = false;
6143    if (VT.isFloatingPoint() && !VT.isVector() &&
6144        !isScalarFPTypeInSSEReg(VT))  // FPStack?
6145      IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6146
6147    if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6148        Opc == X86ISD::BT) { // FIXME
6149      Cond = Cmp;
6150      addTest = false;
6151    }
6152  }
6153
6154  if (addTest) {
6155    // Look pass the truncate.
6156    if (Cond.getOpcode() == ISD::TRUNCATE)
6157      Cond = Cond.getOperand(0);
6158
6159    // We know the result of AND is compared against zero. Try to match
6160    // it to BT.
6161    if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6162      SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6163      if (NewSetCC.getNode()) {
6164        CC = NewSetCC.getOperand(0);
6165        Cond = NewSetCC.getOperand(1);
6166        addTest = false;
6167      }
6168    }
6169  }
6170
6171  if (addTest) {
6172    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6173    Cond = EmitTest(Cond, X86::COND_NE, DAG);
6174  }
6175
6176  // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6177  // condition is true.
6178  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6179  SDValue Ops[] = { Op2, Op1, CC, Cond };
6180  return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6181}
6182
6183// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6184// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6185// from the AND / OR.
6186static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6187  Opc = Op.getOpcode();
6188  if (Opc != ISD::OR && Opc != ISD::AND)
6189    return false;
6190  return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6191          Op.getOperand(0).hasOneUse() &&
6192          Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6193          Op.getOperand(1).hasOneUse());
6194}
6195
6196// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6197// 1 and that the SETCC node has a single use.
6198static bool isXor1OfSetCC(SDValue Op) {
6199  if (Op.getOpcode() != ISD::XOR)
6200    return false;
6201  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6202  if (N1C && N1C->getAPIntValue() == 1) {
6203    return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6204      Op.getOperand(0).hasOneUse();
6205  }
6206  return false;
6207}
6208
6209SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6210  bool addTest = true;
6211  SDValue Chain = Op.getOperand(0);
6212  SDValue Cond  = Op.getOperand(1);
6213  SDValue Dest  = Op.getOperand(2);
6214  DebugLoc dl = Op.getDebugLoc();
6215  SDValue CC;
6216
6217  if (Cond.getOpcode() == ISD::SETCC) {
6218    SDValue NewCond = LowerSETCC(Cond, DAG);
6219    if (NewCond.getNode())
6220      Cond = NewCond;
6221  }
6222#if 0
6223  // FIXME: LowerXALUO doesn't handle these!!
6224  else if (Cond.getOpcode() == X86ISD::ADD  ||
6225           Cond.getOpcode() == X86ISD::SUB  ||
6226           Cond.getOpcode() == X86ISD::SMUL ||
6227           Cond.getOpcode() == X86ISD::UMUL)
6228    Cond = LowerXALUO(Cond, DAG);
6229#endif
6230
6231  // Look pass (and (setcc_carry (cmp ...)), 1).
6232  if (Cond.getOpcode() == ISD::AND &&
6233      Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6234    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6235    if (C && C->getAPIntValue() == 1)
6236      Cond = Cond.getOperand(0);
6237  }
6238
6239  // If condition flag is set by a X86ISD::CMP, then use it as the condition
6240  // setting operand in place of the X86ISD::SETCC.
6241  if (Cond.getOpcode() == X86ISD::SETCC ||
6242      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6243    CC = Cond.getOperand(0);
6244
6245    SDValue Cmp = Cond.getOperand(1);
6246    unsigned Opc = Cmp.getOpcode();
6247    // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6248    if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6249      Cond = Cmp;
6250      addTest = false;
6251    } else {
6252      switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6253      default: break;
6254      case X86::COND_O:
6255      case X86::COND_B:
6256        // These can only come from an arithmetic instruction with overflow,
6257        // e.g. SADDO, UADDO.
6258        Cond = Cond.getNode()->getOperand(1);
6259        addTest = false;
6260        break;
6261      }
6262    }
6263  } else {
6264    unsigned CondOpc;
6265    if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6266      SDValue Cmp = Cond.getOperand(0).getOperand(1);
6267      if (CondOpc == ISD::OR) {
6268        // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6269        // two branches instead of an explicit OR instruction with a
6270        // separate test.
6271        if (Cmp == Cond.getOperand(1).getOperand(1) &&
6272            isX86LogicalCmp(Cmp)) {
6273          CC = Cond.getOperand(0).getOperand(0);
6274          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6275                              Chain, Dest, CC, Cmp);
6276          CC = Cond.getOperand(1).getOperand(0);
6277          Cond = Cmp;
6278          addTest = false;
6279        }
6280      } else { // ISD::AND
6281        // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6282        // two branches instead of an explicit AND instruction with a
6283        // separate test. However, we only do this if this block doesn't
6284        // have a fall-through edge, because this requires an explicit
6285        // jmp when the condition is false.
6286        if (Cmp == Cond.getOperand(1).getOperand(1) &&
6287            isX86LogicalCmp(Cmp) &&
6288            Op.getNode()->hasOneUse()) {
6289          X86::CondCode CCode =
6290            (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6291          CCode = X86::GetOppositeBranchCondition(CCode);
6292          CC = DAG.getConstant(CCode, MVT::i8);
6293          SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6294          // Look for an unconditional branch following this conditional branch.
6295          // We need this because we need to reverse the successors in order
6296          // to implement FCMP_OEQ.
6297          if (User.getOpcode() == ISD::BR) {
6298            SDValue FalseBB = User.getOperand(1);
6299            SDValue NewBR =
6300              DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6301            assert(NewBR == User);
6302            Dest = FalseBB;
6303
6304            Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6305                                Chain, Dest, CC, Cmp);
6306            X86::CondCode CCode =
6307              (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6308            CCode = X86::GetOppositeBranchCondition(CCode);
6309            CC = DAG.getConstant(CCode, MVT::i8);
6310            Cond = Cmp;
6311            addTest = false;
6312          }
6313        }
6314      }
6315    } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6316      // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6317      // It should be transformed during dag combiner except when the condition
6318      // is set by a arithmetics with overflow node.
6319      X86::CondCode CCode =
6320        (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6321      CCode = X86::GetOppositeBranchCondition(CCode);
6322      CC = DAG.getConstant(CCode, MVT::i8);
6323      Cond = Cond.getOperand(0).getOperand(1);
6324      addTest = false;
6325    }
6326  }
6327
6328  if (addTest) {
6329    // Look pass the truncate.
6330    if (Cond.getOpcode() == ISD::TRUNCATE)
6331      Cond = Cond.getOperand(0);
6332
6333    // We know the result of AND is compared against zero. Try to match
6334    // it to BT.
6335    if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6336      SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6337      if (NewSetCC.getNode()) {
6338        CC = NewSetCC.getOperand(0);
6339        Cond = NewSetCC.getOperand(1);
6340        addTest = false;
6341      }
6342    }
6343  }
6344
6345  if (addTest) {
6346    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6347    Cond = EmitTest(Cond, X86::COND_NE, DAG);
6348  }
6349  return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6350                     Chain, Dest, CC, Cond);
6351}
6352
6353
6354// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6355// Calls to _alloca is needed to probe the stack when allocating more than 4k
6356// bytes in one go. Touching the stack at 4K increments is necessary to ensure
6357// that the guard pages used by the OS virtual memory manager are allocated in
6358// correct sequence.
6359SDValue
6360X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6361                                           SelectionDAG &DAG) {
6362  assert(Subtarget->isTargetCygMing() &&
6363         "This should be used only on Cygwin/Mingw targets");
6364  DebugLoc dl = Op.getDebugLoc();
6365
6366  // Get the inputs.
6367  SDValue Chain = Op.getOperand(0);
6368  SDValue Size  = Op.getOperand(1);
6369  // FIXME: Ensure alignment here
6370
6371  SDValue Flag;
6372
6373  EVT IntPtr = getPointerTy();
6374  EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6375
6376  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6377
6378  Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6379  Flag = Chain.getValue(1);
6380
6381  SDVTList  NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6382  SDValue Ops[] = { Chain,
6383                      DAG.getTargetExternalSymbol("_alloca", IntPtr),
6384                      DAG.getRegister(X86::EAX, IntPtr),
6385                      DAG.getRegister(X86StackPtr, SPTy),
6386                      Flag };
6387  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6388  Flag = Chain.getValue(1);
6389
6390  Chain = DAG.getCALLSEQ_END(Chain,
6391                             DAG.getIntPtrConstant(0, true),
6392                             DAG.getIntPtrConstant(0, true),
6393                             Flag);
6394
6395  Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6396
6397  SDValue Ops1[2] = { Chain.getValue(0), Chain };
6398  return DAG.getMergeValues(Ops1, 2, dl);
6399}
6400
6401SDValue
6402X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6403                                           SDValue Chain,
6404                                           SDValue Dst, SDValue Src,
6405                                           SDValue Size, unsigned Align,
6406                                           const Value *DstSV,
6407                                           uint64_t DstSVOff) {
6408  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6409
6410  // If not DWORD aligned or size is more than the threshold, call the library.
6411  // The libc version is likely to be faster for these cases. It can use the
6412  // address value and run time information about the CPU.
6413  if ((Align & 3) != 0 ||
6414      !ConstantSize ||
6415      ConstantSize->getZExtValue() >
6416        getSubtarget()->getMaxInlineSizeThreshold()) {
6417    SDValue InFlag(0, 0);
6418
6419    // Check to see if there is a specialized entry-point for memory zeroing.
6420    ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6421
6422    if (const char *bzeroEntry =  V &&
6423        V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6424      EVT IntPtr = getPointerTy();
6425      const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6426      TargetLowering::ArgListTy Args;
6427      TargetLowering::ArgListEntry Entry;
6428      Entry.Node = Dst;
6429      Entry.Ty = IntPtrTy;
6430      Args.push_back(Entry);
6431      Entry.Node = Size;
6432      Args.push_back(Entry);
6433      std::pair<SDValue,SDValue> CallResult =
6434        LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6435                    false, false, false, false,
6436                    0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6437                    DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6438                    DAG.GetOrdering(Chain.getNode()));
6439      return CallResult.second;
6440    }
6441
6442    // Otherwise have the target-independent code call memset.
6443    return SDValue();
6444  }
6445
6446  uint64_t SizeVal = ConstantSize->getZExtValue();
6447  SDValue InFlag(0, 0);
6448  EVT AVT;
6449  SDValue Count;
6450  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6451  unsigned BytesLeft = 0;
6452  bool TwoRepStos = false;
6453  if (ValC) {
6454    unsigned ValReg;
6455    uint64_t Val = ValC->getZExtValue() & 255;
6456
6457    // If the value is a constant, then we can potentially use larger sets.
6458    switch (Align & 3) {
6459    case 2:   // WORD aligned
6460      AVT = MVT::i16;
6461      ValReg = X86::AX;
6462      Val = (Val << 8) | Val;
6463      break;
6464    case 0:  // DWORD aligned
6465      AVT = MVT::i32;
6466      ValReg = X86::EAX;
6467      Val = (Val << 8)  | Val;
6468      Val = (Val << 16) | Val;
6469      if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) {  // QWORD aligned
6470        AVT = MVT::i64;
6471        ValReg = X86::RAX;
6472        Val = (Val << 32) | Val;
6473      }
6474      break;
6475    default:  // Byte aligned
6476      AVT = MVT::i8;
6477      ValReg = X86::AL;
6478      Count = DAG.getIntPtrConstant(SizeVal);
6479      break;
6480    }
6481
6482    if (AVT.bitsGT(MVT::i8)) {
6483      unsigned UBytes = AVT.getSizeInBits() / 8;
6484      Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6485      BytesLeft = SizeVal % UBytes;
6486    }
6487
6488    Chain  = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6489                              InFlag);
6490    InFlag = Chain.getValue(1);
6491  } else {
6492    AVT = MVT::i8;
6493    Count  = DAG.getIntPtrConstant(SizeVal);
6494    Chain  = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6495    InFlag = Chain.getValue(1);
6496  }
6497
6498  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6499                                                              X86::ECX,
6500                            Count, InFlag);
6501  InFlag = Chain.getValue(1);
6502  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6503                                                              X86::EDI,
6504                            Dst, InFlag);
6505  InFlag = Chain.getValue(1);
6506
6507  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6508  SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6509  Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6510
6511  if (TwoRepStos) {
6512    InFlag = Chain.getValue(1);
6513    Count  = Size;
6514    EVT CVT = Count.getValueType();
6515    SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6516                               DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6517    Chain  = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6518                                                             X86::ECX,
6519                              Left, InFlag);
6520    InFlag = Chain.getValue(1);
6521    Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6522    SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6523    Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6524  } else if (BytesLeft) {
6525    // Handle the last 1 - 7 bytes.
6526    unsigned Offset = SizeVal - BytesLeft;
6527    EVT AddrVT = Dst.getValueType();
6528    EVT SizeVT = Size.getValueType();
6529
6530    Chain = DAG.getMemset(Chain, dl,
6531                          DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6532                                      DAG.getConstant(Offset, AddrVT)),
6533                          Src,
6534                          DAG.getConstant(BytesLeft, SizeVT),
6535                          Align, DstSV, DstSVOff + Offset);
6536  }
6537
6538  // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6539  return Chain;
6540}
6541
6542SDValue
6543X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6544                                      SDValue Chain, SDValue Dst, SDValue Src,
6545                                      SDValue Size, unsigned Align,
6546                                      bool AlwaysInline,
6547                                      const Value *DstSV, uint64_t DstSVOff,
6548                                      const Value *SrcSV, uint64_t SrcSVOff) {
6549  // This requires the copy size to be a constant, preferrably
6550  // within a subtarget-specific limit.
6551  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6552  if (!ConstantSize)
6553    return SDValue();
6554  uint64_t SizeVal = ConstantSize->getZExtValue();
6555  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6556    return SDValue();
6557
6558  /// If not DWORD aligned, call the library.
6559  if ((Align & 3) != 0)
6560    return SDValue();
6561
6562  // DWORD aligned
6563  EVT AVT = MVT::i32;
6564  if (Subtarget->is64Bit() && ((Align & 0x7) == 0))  // QWORD aligned
6565    AVT = MVT::i64;
6566
6567  unsigned UBytes = AVT.getSizeInBits() / 8;
6568  unsigned CountVal = SizeVal / UBytes;
6569  SDValue Count = DAG.getIntPtrConstant(CountVal);
6570  unsigned BytesLeft = SizeVal % UBytes;
6571
6572  SDValue InFlag(0, 0);
6573  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6574                                                              X86::ECX,
6575                            Count, InFlag);
6576  InFlag = Chain.getValue(1);
6577  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6578                                                             X86::EDI,
6579                            Dst, InFlag);
6580  InFlag = Chain.getValue(1);
6581  Chain  = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6582                                                              X86::ESI,
6583                            Src, InFlag);
6584  InFlag = Chain.getValue(1);
6585
6586  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6587  SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6588  SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6589                                array_lengthof(Ops));
6590
6591  SmallVector<SDValue, 4> Results;
6592  Results.push_back(RepMovs);
6593  if (BytesLeft) {
6594    // Handle the last 1 - 7 bytes.
6595    unsigned Offset = SizeVal - BytesLeft;
6596    EVT DstVT = Dst.getValueType();
6597    EVT SrcVT = Src.getValueType();
6598    EVT SizeVT = Size.getValueType();
6599    Results.push_back(DAG.getMemcpy(Chain, dl,
6600                                    DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6601                                                DAG.getConstant(Offset, DstVT)),
6602                                    DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6603                                                DAG.getConstant(Offset, SrcVT)),
6604                                    DAG.getConstant(BytesLeft, SizeVT),
6605                                    Align, AlwaysInline,
6606                                    DstSV, DstSVOff + Offset,
6607                                    SrcSV, SrcSVOff + Offset));
6608  }
6609
6610  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6611                     &Results[0], Results.size());
6612}
6613
6614SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6615  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6616  DebugLoc dl = Op.getDebugLoc();
6617
6618  if (!Subtarget->is64Bit()) {
6619    // vastart just stores the address of the VarArgsFrameIndex slot into the
6620    // memory location argument.
6621    SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6622    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6623  }
6624
6625  // __va_list_tag:
6626  //   gp_offset         (0 - 6 * 8)
6627  //   fp_offset         (48 - 48 + 8 * 16)
6628  //   overflow_arg_area (point to parameters coming in memory).
6629  //   reg_save_area
6630  SmallVector<SDValue, 8> MemOps;
6631  SDValue FIN = Op.getOperand(1);
6632  // Store gp_offset
6633  SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6634                                 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6635                                 FIN, SV, 0);
6636  MemOps.push_back(Store);
6637
6638  // Store fp_offset
6639  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6640                    FIN, DAG.getIntPtrConstant(4));
6641  Store = DAG.getStore(Op.getOperand(0), dl,
6642                       DAG.getConstant(VarArgsFPOffset, MVT::i32),
6643                       FIN, SV, 0);
6644  MemOps.push_back(Store);
6645
6646  // Store ptr to overflow_arg_area
6647  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6648                    FIN, DAG.getIntPtrConstant(4));
6649  SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6650  Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6651  MemOps.push_back(Store);
6652
6653  // Store ptr to reg_save_area.
6654  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6655                    FIN, DAG.getIntPtrConstant(8));
6656  SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6657  Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6658  MemOps.push_back(Store);
6659  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6660                     &MemOps[0], MemOps.size());
6661}
6662
6663SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6664  // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6665  assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6666  SDValue Chain = Op.getOperand(0);
6667  SDValue SrcPtr = Op.getOperand(1);
6668  SDValue SrcSV = Op.getOperand(2);
6669
6670  llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6671  return SDValue();
6672}
6673
6674SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6675  // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6676  assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6677  SDValue Chain = Op.getOperand(0);
6678  SDValue DstPtr = Op.getOperand(1);
6679  SDValue SrcPtr = Op.getOperand(2);
6680  const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6681  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6682  DebugLoc dl = Op.getDebugLoc();
6683
6684  return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6685                       DAG.getIntPtrConstant(24), 8, false,
6686                       DstSV, 0, SrcSV, 0);
6687}
6688
6689SDValue
6690X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6691  DebugLoc dl = Op.getDebugLoc();
6692  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6693  switch (IntNo) {
6694  default: return SDValue();    // Don't custom lower most intrinsics.
6695  // Comparison intrinsics.
6696  case Intrinsic::x86_sse_comieq_ss:
6697  case Intrinsic::x86_sse_comilt_ss:
6698  case Intrinsic::x86_sse_comile_ss:
6699  case Intrinsic::x86_sse_comigt_ss:
6700  case Intrinsic::x86_sse_comige_ss:
6701  case Intrinsic::x86_sse_comineq_ss:
6702  case Intrinsic::x86_sse_ucomieq_ss:
6703  case Intrinsic::x86_sse_ucomilt_ss:
6704  case Intrinsic::x86_sse_ucomile_ss:
6705  case Intrinsic::x86_sse_ucomigt_ss:
6706  case Intrinsic::x86_sse_ucomige_ss:
6707  case Intrinsic::x86_sse_ucomineq_ss:
6708  case Intrinsic::x86_sse2_comieq_sd:
6709  case Intrinsic::x86_sse2_comilt_sd:
6710  case Intrinsic::x86_sse2_comile_sd:
6711  case Intrinsic::x86_sse2_comigt_sd:
6712  case Intrinsic::x86_sse2_comige_sd:
6713  case Intrinsic::x86_sse2_comineq_sd:
6714  case Intrinsic::x86_sse2_ucomieq_sd:
6715  case Intrinsic::x86_sse2_ucomilt_sd:
6716  case Intrinsic::x86_sse2_ucomile_sd:
6717  case Intrinsic::x86_sse2_ucomigt_sd:
6718  case Intrinsic::x86_sse2_ucomige_sd:
6719  case Intrinsic::x86_sse2_ucomineq_sd: {
6720    unsigned Opc = 0;
6721    ISD::CondCode CC = ISD::SETCC_INVALID;
6722    switch (IntNo) {
6723    default: break;
6724    case Intrinsic::x86_sse_comieq_ss:
6725    case Intrinsic::x86_sse2_comieq_sd:
6726      Opc = X86ISD::COMI;
6727      CC = ISD::SETEQ;
6728      break;
6729    case Intrinsic::x86_sse_comilt_ss:
6730    case Intrinsic::x86_sse2_comilt_sd:
6731      Opc = X86ISD::COMI;
6732      CC = ISD::SETLT;
6733      break;
6734    case Intrinsic::x86_sse_comile_ss:
6735    case Intrinsic::x86_sse2_comile_sd:
6736      Opc = X86ISD::COMI;
6737      CC = ISD::SETLE;
6738      break;
6739    case Intrinsic::x86_sse_comigt_ss:
6740    case Intrinsic::x86_sse2_comigt_sd:
6741      Opc = X86ISD::COMI;
6742      CC = ISD::SETGT;
6743      break;
6744    case Intrinsic::x86_sse_comige_ss:
6745    case Intrinsic::x86_sse2_comige_sd:
6746      Opc = X86ISD::COMI;
6747      CC = ISD::SETGE;
6748      break;
6749    case Intrinsic::x86_sse_comineq_ss:
6750    case Intrinsic::x86_sse2_comineq_sd:
6751      Opc = X86ISD::COMI;
6752      CC = ISD::SETNE;
6753      break;
6754    case Intrinsic::x86_sse_ucomieq_ss:
6755    case Intrinsic::x86_sse2_ucomieq_sd:
6756      Opc = X86ISD::UCOMI;
6757      CC = ISD::SETEQ;
6758      break;
6759    case Intrinsic::x86_sse_ucomilt_ss:
6760    case Intrinsic::x86_sse2_ucomilt_sd:
6761      Opc = X86ISD::UCOMI;
6762      CC = ISD::SETLT;
6763      break;
6764    case Intrinsic::x86_sse_ucomile_ss:
6765    case Intrinsic::x86_sse2_ucomile_sd:
6766      Opc = X86ISD::UCOMI;
6767      CC = ISD::SETLE;
6768      break;
6769    case Intrinsic::x86_sse_ucomigt_ss:
6770    case Intrinsic::x86_sse2_ucomigt_sd:
6771      Opc = X86ISD::UCOMI;
6772      CC = ISD::SETGT;
6773      break;
6774    case Intrinsic::x86_sse_ucomige_ss:
6775    case Intrinsic::x86_sse2_ucomige_sd:
6776      Opc = X86ISD::UCOMI;
6777      CC = ISD::SETGE;
6778      break;
6779    case Intrinsic::x86_sse_ucomineq_ss:
6780    case Intrinsic::x86_sse2_ucomineq_sd:
6781      Opc = X86ISD::UCOMI;
6782      CC = ISD::SETNE;
6783      break;
6784    }
6785
6786    SDValue LHS = Op.getOperand(1);
6787    SDValue RHS = Op.getOperand(2);
6788    unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6789    assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6790    SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6791    SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6792                                DAG.getConstant(X86CC, MVT::i8), Cond);
6793    return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6794  }
6795  // ptest intrinsics. The intrinsic these come from are designed to return
6796  // an integer value, not just an instruction so lower it to the ptest
6797  // pattern and a setcc for the result.
6798  case Intrinsic::x86_sse41_ptestz:
6799  case Intrinsic::x86_sse41_ptestc:
6800  case Intrinsic::x86_sse41_ptestnzc:{
6801    unsigned X86CC = 0;
6802    switch (IntNo) {
6803    default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6804    case Intrinsic::x86_sse41_ptestz:
6805      // ZF = 1
6806      X86CC = X86::COND_E;
6807      break;
6808    case Intrinsic::x86_sse41_ptestc:
6809      // CF = 1
6810      X86CC = X86::COND_B;
6811      break;
6812    case Intrinsic::x86_sse41_ptestnzc:
6813      // ZF and CF = 0
6814      X86CC = X86::COND_A;
6815      break;
6816    }
6817
6818    SDValue LHS = Op.getOperand(1);
6819    SDValue RHS = Op.getOperand(2);
6820    SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6821    SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6822    SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6823    return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6824  }
6825
6826  // Fix vector shift instructions where the last operand is a non-immediate
6827  // i32 value.
6828  case Intrinsic::x86_sse2_pslli_w:
6829  case Intrinsic::x86_sse2_pslli_d:
6830  case Intrinsic::x86_sse2_pslli_q:
6831  case Intrinsic::x86_sse2_psrli_w:
6832  case Intrinsic::x86_sse2_psrli_d:
6833  case Intrinsic::x86_sse2_psrli_q:
6834  case Intrinsic::x86_sse2_psrai_w:
6835  case Intrinsic::x86_sse2_psrai_d:
6836  case Intrinsic::x86_mmx_pslli_w:
6837  case Intrinsic::x86_mmx_pslli_d:
6838  case Intrinsic::x86_mmx_pslli_q:
6839  case Intrinsic::x86_mmx_psrli_w:
6840  case Intrinsic::x86_mmx_psrli_d:
6841  case Intrinsic::x86_mmx_psrli_q:
6842  case Intrinsic::x86_mmx_psrai_w:
6843  case Intrinsic::x86_mmx_psrai_d: {
6844    SDValue ShAmt = Op.getOperand(2);
6845    if (isa<ConstantSDNode>(ShAmt))
6846      return SDValue();
6847
6848    unsigned NewIntNo = 0;
6849    EVT ShAmtVT = MVT::v4i32;
6850    switch (IntNo) {
6851    case Intrinsic::x86_sse2_pslli_w:
6852      NewIntNo = Intrinsic::x86_sse2_psll_w;
6853      break;
6854    case Intrinsic::x86_sse2_pslli_d:
6855      NewIntNo = Intrinsic::x86_sse2_psll_d;
6856      break;
6857    case Intrinsic::x86_sse2_pslli_q:
6858      NewIntNo = Intrinsic::x86_sse2_psll_q;
6859      break;
6860    case Intrinsic::x86_sse2_psrli_w:
6861      NewIntNo = Intrinsic::x86_sse2_psrl_w;
6862      break;
6863    case Intrinsic::x86_sse2_psrli_d:
6864      NewIntNo = Intrinsic::x86_sse2_psrl_d;
6865      break;
6866    case Intrinsic::x86_sse2_psrli_q:
6867      NewIntNo = Intrinsic::x86_sse2_psrl_q;
6868      break;
6869    case Intrinsic::x86_sse2_psrai_w:
6870      NewIntNo = Intrinsic::x86_sse2_psra_w;
6871      break;
6872    case Intrinsic::x86_sse2_psrai_d:
6873      NewIntNo = Intrinsic::x86_sse2_psra_d;
6874      break;
6875    default: {
6876      ShAmtVT = MVT::v2i32;
6877      switch (IntNo) {
6878      case Intrinsic::x86_mmx_pslli_w:
6879        NewIntNo = Intrinsic::x86_mmx_psll_w;
6880        break;
6881      case Intrinsic::x86_mmx_pslli_d:
6882        NewIntNo = Intrinsic::x86_mmx_psll_d;
6883        break;
6884      case Intrinsic::x86_mmx_pslli_q:
6885        NewIntNo = Intrinsic::x86_mmx_psll_q;
6886        break;
6887      case Intrinsic::x86_mmx_psrli_w:
6888        NewIntNo = Intrinsic::x86_mmx_psrl_w;
6889        break;
6890      case Intrinsic::x86_mmx_psrli_d:
6891        NewIntNo = Intrinsic::x86_mmx_psrl_d;
6892        break;
6893      case Intrinsic::x86_mmx_psrli_q:
6894        NewIntNo = Intrinsic::x86_mmx_psrl_q;
6895        break;
6896      case Intrinsic::x86_mmx_psrai_w:
6897        NewIntNo = Intrinsic::x86_mmx_psra_w;
6898        break;
6899      case Intrinsic::x86_mmx_psrai_d:
6900        NewIntNo = Intrinsic::x86_mmx_psra_d;
6901        break;
6902      default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
6903      }
6904      break;
6905    }
6906    }
6907
6908    // The vector shift intrinsics with scalars uses 32b shift amounts but
6909    // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6910    // to be zero.
6911    SDValue ShOps[4];
6912    ShOps[0] = ShAmt;
6913    ShOps[1] = DAG.getConstant(0, MVT::i32);
6914    if (ShAmtVT == MVT::v4i32) {
6915      ShOps[2] = DAG.getUNDEF(MVT::i32);
6916      ShOps[3] = DAG.getUNDEF(MVT::i32);
6917      ShAmt =  DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6918    } else {
6919      ShAmt =  DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6920    }
6921
6922    EVT VT = Op.getValueType();
6923    ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6924    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6925                       DAG.getConstant(NewIntNo, MVT::i32),
6926                       Op.getOperand(1), ShAmt);
6927  }
6928  }
6929}
6930
6931SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6932  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6933  DebugLoc dl = Op.getDebugLoc();
6934
6935  if (Depth > 0) {
6936    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6937    SDValue Offset =
6938      DAG.getConstant(TD->getPointerSize(),
6939                      Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6940    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6941                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
6942                                   FrameAddr, Offset),
6943                       NULL, 0);
6944  }
6945
6946  // Just load the return address.
6947  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6948  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6949                     RetAddrFI, NULL, 0);
6950}
6951
6952SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6953  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6954  MFI->setFrameAddressIsTaken(true);
6955  EVT VT = Op.getValueType();
6956  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
6957  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6958  unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6959  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6960  while (Depth--)
6961    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6962  return FrameAddr;
6963}
6964
6965SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6966                                                     SelectionDAG &DAG) {
6967  return DAG.getIntPtrConstant(2*TD->getPointerSize());
6968}
6969
6970SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6971{
6972  MachineFunction &MF = DAG.getMachineFunction();
6973  SDValue Chain     = Op.getOperand(0);
6974  SDValue Offset    = Op.getOperand(1);
6975  SDValue Handler   = Op.getOperand(2);
6976  DebugLoc dl       = Op.getDebugLoc();
6977
6978  SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6979                                  getPointerTy());
6980  unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6981
6982  SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6983                                  DAG.getIntPtrConstant(-TD->getPointerSize()));
6984  StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6985  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6986  Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6987  MF.getRegInfo().addLiveOut(StoreAddrReg);
6988
6989  return DAG.getNode(X86ISD::EH_RETURN, dl,
6990                     MVT::Other,
6991                     Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6992}
6993
6994SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6995                                             SelectionDAG &DAG) {
6996  SDValue Root = Op.getOperand(0);
6997  SDValue Trmp = Op.getOperand(1); // trampoline
6998  SDValue FPtr = Op.getOperand(2); // nested function
6999  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7000  DebugLoc dl  = Op.getDebugLoc();
7001
7002  const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7003
7004  const X86InstrInfo *TII =
7005    ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
7006
7007  if (Subtarget->is64Bit()) {
7008    SDValue OutChains[6];
7009
7010    // Large code-model.
7011
7012    const unsigned char JMP64r  = TII->getBaseOpcodeFor(X86::JMP64r);
7013    const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
7014
7015    const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7016    const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7017
7018    const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7019
7020    // Load the pointer to the nested function into R11.
7021    unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7022    SDValue Addr = Trmp;
7023    OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7024                                Addr, TrmpAddr, 0);
7025
7026    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7027                       DAG.getConstant(2, MVT::i64));
7028    OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
7029
7030    // Load the 'nest' parameter value into R10.
7031    // R10 is specified in X86CallingConv.td
7032    OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7033    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7034                       DAG.getConstant(10, MVT::i64));
7035    OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7036                                Addr, TrmpAddr, 10);
7037
7038    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7039                       DAG.getConstant(12, MVT::i64));
7040    OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
7041
7042    // Jump to the nested function.
7043    OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7044    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7045                       DAG.getConstant(20, MVT::i64));
7046    OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7047                                Addr, TrmpAddr, 20);
7048
7049    unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7050    Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7051                       DAG.getConstant(22, MVT::i64));
7052    OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7053                                TrmpAddr, 22);
7054
7055    SDValue Ops[] =
7056      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7057    return DAG.getMergeValues(Ops, 2, dl);
7058  } else {
7059    const Function *Func =
7060      cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7061    CallingConv::ID CC = Func->getCallingConv();
7062    unsigned NestReg;
7063
7064    switch (CC) {
7065    default:
7066      llvm_unreachable("Unsupported calling convention");
7067    case CallingConv::C:
7068    case CallingConv::X86_StdCall: {
7069      // Pass 'nest' parameter in ECX.
7070      // Must be kept in sync with X86CallingConv.td
7071      NestReg = X86::ECX;
7072
7073      // Check that ECX wasn't needed by an 'inreg' parameter.
7074      const FunctionType *FTy = Func->getFunctionType();
7075      const AttrListPtr &Attrs = Func->getAttributes();
7076
7077      if (!Attrs.isEmpty() && !Func->isVarArg()) {
7078        unsigned InRegCount = 0;
7079        unsigned Idx = 1;
7080
7081        for (FunctionType::param_iterator I = FTy->param_begin(),
7082             E = FTy->param_end(); I != E; ++I, ++Idx)
7083          if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7084            // FIXME: should only count parameters that are lowered to integers.
7085            InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7086
7087        if (InRegCount > 2) {
7088          llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7089        }
7090      }
7091      break;
7092    }
7093    case CallingConv::X86_FastCall:
7094    case CallingConv::Fast:
7095      // Pass 'nest' parameter in EAX.
7096      // Must be kept in sync with X86CallingConv.td
7097      NestReg = X86::EAX;
7098      break;
7099    }
7100
7101    SDValue OutChains[4];
7102    SDValue Addr, Disp;
7103
7104    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7105                       DAG.getConstant(10, MVT::i32));
7106    Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7107
7108    const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
7109    const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7110    OutChains[0] = DAG.getStore(Root, dl,
7111                                DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7112                                Trmp, TrmpAddr, 0);
7113
7114    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7115                       DAG.getConstant(1, MVT::i32));
7116    OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
7117
7118    const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
7119    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7120                       DAG.getConstant(5, MVT::i32));
7121    OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7122                                TrmpAddr, 5, false, 1);
7123
7124    Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7125                       DAG.getConstant(6, MVT::i32));
7126    OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
7127
7128    SDValue Ops[] =
7129      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7130    return DAG.getMergeValues(Ops, 2, dl);
7131  }
7132}
7133
7134SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7135  /*
7136   The rounding mode is in bits 11:10 of FPSR, and has the following
7137   settings:
7138     00 Round to nearest
7139     01 Round to -inf
7140     10 Round to +inf
7141     11 Round to 0
7142
7143  FLT_ROUNDS, on the other hand, expects the following:
7144    -1 Undefined
7145     0 Round to 0
7146     1 Round to nearest
7147     2 Round to +inf
7148     3 Round to -inf
7149
7150  To perform the conversion, we do:
7151    (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7152  */
7153
7154  MachineFunction &MF = DAG.getMachineFunction();
7155  const TargetMachine &TM = MF.getTarget();
7156  const TargetFrameInfo &TFI = *TM.getFrameInfo();
7157  unsigned StackAlignment = TFI.getStackAlignment();
7158  EVT VT = Op.getValueType();
7159  DebugLoc dl = Op.getDebugLoc();
7160
7161  // Save FP Control Word to stack slot
7162  int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7163  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7164
7165  SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7166                              DAG.getEntryNode(), StackSlot);
7167
7168  // Load FP Control Word from stack slot
7169  SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
7170
7171  // Transform as necessary
7172  SDValue CWD1 =
7173    DAG.getNode(ISD::SRL, dl, MVT::i16,
7174                DAG.getNode(ISD::AND, dl, MVT::i16,
7175                            CWD, DAG.getConstant(0x800, MVT::i16)),
7176                DAG.getConstant(11, MVT::i8));
7177  SDValue CWD2 =
7178    DAG.getNode(ISD::SRL, dl, MVT::i16,
7179                DAG.getNode(ISD::AND, dl, MVT::i16,
7180                            CWD, DAG.getConstant(0x400, MVT::i16)),
7181                DAG.getConstant(9, MVT::i8));
7182
7183  SDValue RetVal =
7184    DAG.getNode(ISD::AND, dl, MVT::i16,
7185                DAG.getNode(ISD::ADD, dl, MVT::i16,
7186                            DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7187                            DAG.getConstant(1, MVT::i16)),
7188                DAG.getConstant(3, MVT::i16));
7189
7190
7191  return DAG.getNode((VT.getSizeInBits() < 16 ?
7192                      ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7193}
7194
7195SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7196  EVT VT = Op.getValueType();
7197  EVT OpVT = VT;
7198  unsigned NumBits = VT.getSizeInBits();
7199  DebugLoc dl = Op.getDebugLoc();
7200
7201  Op = Op.getOperand(0);
7202  if (VT == MVT::i8) {
7203    // Zero extend to i32 since there is not an i8 bsr.
7204    OpVT = MVT::i32;
7205    Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7206  }
7207
7208  // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7209  SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7210  Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7211
7212  // If src is zero (i.e. bsr sets ZF), returns NumBits.
7213  SDValue Ops[] = {
7214    Op,
7215    DAG.getConstant(NumBits+NumBits-1, OpVT),
7216    DAG.getConstant(X86::COND_E, MVT::i8),
7217    Op.getValue(1)
7218  };
7219  Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7220
7221  // Finally xor with NumBits-1.
7222  Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7223
7224  if (VT == MVT::i8)
7225    Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7226  return Op;
7227}
7228
7229SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7230  EVT VT = Op.getValueType();
7231  EVT OpVT = VT;
7232  unsigned NumBits = VT.getSizeInBits();
7233  DebugLoc dl = Op.getDebugLoc();
7234
7235  Op = Op.getOperand(0);
7236  if (VT == MVT::i8) {
7237    OpVT = MVT::i32;
7238    Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7239  }
7240
7241  // Issue a bsf (scan bits forward) which also sets EFLAGS.
7242  SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7243  Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7244
7245  // If src is zero (i.e. bsf sets ZF), returns NumBits.
7246  SDValue Ops[] = {
7247    Op,
7248    DAG.getConstant(NumBits, OpVT),
7249    DAG.getConstant(X86::COND_E, MVT::i8),
7250    Op.getValue(1)
7251  };
7252  Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7253
7254  if (VT == MVT::i8)
7255    Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7256  return Op;
7257}
7258
7259SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7260  EVT VT = Op.getValueType();
7261  assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7262  DebugLoc dl = Op.getDebugLoc();
7263
7264  //  ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7265  //  ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7266  //  ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7267  //  ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7268  //  ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7269  //
7270  //  AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7271  //  AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7272  //  return AloBlo + AloBhi + AhiBlo;
7273
7274  SDValue A = Op.getOperand(0);
7275  SDValue B = Op.getOperand(1);
7276
7277  SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7278                       DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7279                       A, DAG.getConstant(32, MVT::i32));
7280  SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7281                       DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7282                       B, DAG.getConstant(32, MVT::i32));
7283  SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7284                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7285                       A, B);
7286  SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7287                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7288                       A, Bhi);
7289  SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7290                       DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7291                       Ahi, B);
7292  AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7293                       DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7294                       AloBhi, DAG.getConstant(32, MVT::i32));
7295  AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7296                       DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7297                       AhiBlo, DAG.getConstant(32, MVT::i32));
7298  SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7299  Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7300  return Res;
7301}
7302
7303
7304SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7305  // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7306  // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7307  // looks for this combo and may remove the "setcc" instruction if the "setcc"
7308  // has only one use.
7309  SDNode *N = Op.getNode();
7310  SDValue LHS = N->getOperand(0);
7311  SDValue RHS = N->getOperand(1);
7312  unsigned BaseOp = 0;
7313  unsigned Cond = 0;
7314  DebugLoc dl = Op.getDebugLoc();
7315
7316  switch (Op.getOpcode()) {
7317  default: llvm_unreachable("Unknown ovf instruction!");
7318  case ISD::SADDO:
7319    // A subtract of one will be selected as a INC. Note that INC doesn't
7320    // set CF, so we can't do this for UADDO.
7321    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7322      if (C->getAPIntValue() == 1) {
7323        BaseOp = X86ISD::INC;
7324        Cond = X86::COND_O;
7325        break;
7326      }
7327    BaseOp = X86ISD::ADD;
7328    Cond = X86::COND_O;
7329    break;
7330  case ISD::UADDO:
7331    BaseOp = X86ISD::ADD;
7332    Cond = X86::COND_B;
7333    break;
7334  case ISD::SSUBO:
7335    // A subtract of one will be selected as a DEC. Note that DEC doesn't
7336    // set CF, so we can't do this for USUBO.
7337    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7338      if (C->getAPIntValue() == 1) {
7339        BaseOp = X86ISD::DEC;
7340        Cond = X86::COND_O;
7341        break;
7342      }
7343    BaseOp = X86ISD::SUB;
7344    Cond = X86::COND_O;
7345    break;
7346  case ISD::USUBO:
7347    BaseOp = X86ISD::SUB;
7348    Cond = X86::COND_B;
7349    break;
7350  case ISD::SMULO:
7351    BaseOp = X86ISD::SMUL;
7352    Cond = X86::COND_O;
7353    break;
7354  case ISD::UMULO:
7355    BaseOp = X86ISD::UMUL;
7356    Cond = X86::COND_B;
7357    break;
7358  }
7359
7360  // Also sets EFLAGS.
7361  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7362  SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7363
7364  SDValue SetCC =
7365    DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7366                DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7367
7368  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7369  return Sum;
7370}
7371
7372SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7373  EVT T = Op.getValueType();
7374  DebugLoc dl = Op.getDebugLoc();
7375  unsigned Reg = 0;
7376  unsigned size = 0;
7377  switch(T.getSimpleVT().SimpleTy) {
7378  default:
7379    assert(false && "Invalid value type!");
7380  case MVT::i8:  Reg = X86::AL;  size = 1; break;
7381  case MVT::i16: Reg = X86::AX;  size = 2; break;
7382  case MVT::i32: Reg = X86::EAX; size = 4; break;
7383  case MVT::i64:
7384    assert(Subtarget->is64Bit() && "Node not type legal!");
7385    Reg = X86::RAX; size = 8;
7386    break;
7387  }
7388  SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7389                                    Op.getOperand(2), SDValue());
7390  SDValue Ops[] = { cpIn.getValue(0),
7391                    Op.getOperand(1),
7392                    Op.getOperand(3),
7393                    DAG.getTargetConstant(size, MVT::i8),
7394                    cpIn.getValue(1) };
7395  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7396  SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7397  SDValue cpOut =
7398    DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7399  return cpOut;
7400}
7401
7402SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7403                                                 SelectionDAG &DAG) {
7404  assert(Subtarget->is64Bit() && "Result not type legalized?");
7405  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7406  SDValue TheChain = Op.getOperand(0);
7407  DebugLoc dl = Op.getDebugLoc();
7408  SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7409  SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7410  SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7411                                   rax.getValue(2));
7412  SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7413                            DAG.getConstant(32, MVT::i8));
7414  SDValue Ops[] = {
7415    DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7416    rdx.getValue(1)
7417  };
7418  return DAG.getMergeValues(Ops, 2, dl);
7419}
7420
7421SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7422  SDNode *Node = Op.getNode();
7423  DebugLoc dl = Node->getDebugLoc();
7424  EVT T = Node->getValueType(0);
7425  SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7426                              DAG.getConstant(0, T), Node->getOperand(2));
7427  return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7428                       cast<AtomicSDNode>(Node)->getMemoryVT(),
7429                       Node->getOperand(0),
7430                       Node->getOperand(1), negOp,
7431                       cast<AtomicSDNode>(Node)->getSrcValue(),
7432                       cast<AtomicSDNode>(Node)->getAlignment());
7433}
7434
7435/// LowerOperation - Provide custom lowering hooks for some operations.
7436///
7437SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7438  switch (Op.getOpcode()) {
7439  default: llvm_unreachable("Should not custom lower this!");
7440  case ISD::ATOMIC_CMP_SWAP:    return LowerCMP_SWAP(Op,DAG);
7441  case ISD::ATOMIC_LOAD_SUB:    return LowerLOAD_SUB(Op,DAG);
7442  case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
7443  case ISD::CONCAT_VECTORS:     return LowerCONCAT_VECTORS(Op, DAG);
7444  case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
7445  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7446  case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);
7447  case ISD::SCALAR_TO_VECTOR:   return LowerSCALAR_TO_VECTOR(Op, DAG);
7448  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
7449  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
7450  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
7451  case ISD::ExternalSymbol:     return LowerExternalSymbol(Op, DAG);
7452  case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
7453  case ISD::SHL_PARTS:
7454  case ISD::SRA_PARTS:
7455  case ISD::SRL_PARTS:          return LowerShift(Op, DAG);
7456  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
7457  case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG);
7458  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
7459  case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG);
7460  case ISD::FABS:               return LowerFABS(Op, DAG);
7461  case ISD::FNEG:               return LowerFNEG(Op, DAG);
7462  case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
7463  case ISD::SETCC:              return LowerSETCC(Op, DAG);
7464  case ISD::VSETCC:             return LowerVSETCC(Op, DAG);
7465  case ISD::SELECT:             return LowerSELECT(Op, DAG);
7466  case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
7467  case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
7468  case ISD::VASTART:            return LowerVASTART(Op, DAG);
7469  case ISD::VAARG:              return LowerVAARG(Op, DAG);
7470  case ISD::VACOPY:             return LowerVACOPY(Op, DAG);
7471  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7472  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
7473  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
7474  case ISD::FRAME_TO_ARGS_OFFSET:
7475                                return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7476  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7477  case ISD::EH_RETURN:          return LowerEH_RETURN(Op, DAG);
7478  case ISD::TRAMPOLINE:         return LowerTRAMPOLINE(Op, DAG);
7479  case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
7480  case ISD::CTLZ:               return LowerCTLZ(Op, DAG);
7481  case ISD::CTTZ:               return LowerCTTZ(Op, DAG);
7482  case ISD::MUL:                return LowerMUL_V2I64(Op, DAG);
7483  case ISD::SADDO:
7484  case ISD::UADDO:
7485  case ISD::SSUBO:
7486  case ISD::USUBO:
7487  case ISD::SMULO:
7488  case ISD::UMULO:              return LowerXALUO(Op, DAG);
7489  case ISD::READCYCLECOUNTER:   return LowerREADCYCLECOUNTER(Op, DAG);
7490  }
7491}
7492
7493void X86TargetLowering::
7494ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7495                        SelectionDAG &DAG, unsigned NewOp) {
7496  EVT T = Node->getValueType(0);
7497  DebugLoc dl = Node->getDebugLoc();
7498  assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7499
7500  SDValue Chain = Node->getOperand(0);
7501  SDValue In1 = Node->getOperand(1);
7502  SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7503                             Node->getOperand(2), DAG.getIntPtrConstant(0));
7504  SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7505                             Node->getOperand(2), DAG.getIntPtrConstant(1));
7506  SDValue Ops[] = { Chain, In1, In2L, In2H };
7507  SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7508  SDValue Result =
7509    DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7510                            cast<MemSDNode>(Node)->getMemOperand());
7511  SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7512  Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7513  Results.push_back(Result.getValue(2));
7514}
7515
7516/// ReplaceNodeResults - Replace a node with an illegal result type
7517/// with a new node built out of custom code.
7518void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7519                                           SmallVectorImpl<SDValue>&Results,
7520                                           SelectionDAG &DAG) {
7521  DebugLoc dl = N->getDebugLoc();
7522  switch (N->getOpcode()) {
7523  default:
7524    assert(false && "Do not know how to custom type legalize this operation!");
7525    return;
7526  case ISD::FP_TO_SINT: {
7527    std::pair<SDValue,SDValue> Vals =
7528        FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7529    SDValue FIST = Vals.first, StackSlot = Vals.second;
7530    if (FIST.getNode() != 0) {
7531      EVT VT = N->getValueType(0);
7532      // Return a load from the stack slot.
7533      Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7534    }
7535    return;
7536  }
7537  case ISD::READCYCLECOUNTER: {
7538    SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7539    SDValue TheChain = N->getOperand(0);
7540    SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7541    SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7542                                     rd.getValue(1));
7543    SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7544                                     eax.getValue(2));
7545    // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7546    SDValue Ops[] = { eax, edx };
7547    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7548    Results.push_back(edx.getValue(1));
7549    return;
7550  }
7551  case ISD::SDIV:
7552  case ISD::UDIV:
7553  case ISD::SREM:
7554  case ISD::UREM: {
7555    EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7556    Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7557    return;
7558  }
7559  case ISD::ATOMIC_CMP_SWAP: {
7560    EVT T = N->getValueType(0);
7561    assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7562    SDValue cpInL, cpInH;
7563    cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7564                        DAG.getConstant(0, MVT::i32));
7565    cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7566                        DAG.getConstant(1, MVT::i32));
7567    cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7568    cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7569                             cpInL.getValue(1));
7570    SDValue swapInL, swapInH;
7571    swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7572                          DAG.getConstant(0, MVT::i32));
7573    swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7574                          DAG.getConstant(1, MVT::i32));
7575    swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7576                               cpInH.getValue(1));
7577    swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7578                               swapInL.getValue(1));
7579    SDValue Ops[] = { swapInH.getValue(0),
7580                      N->getOperand(1),
7581                      swapInH.getValue(1) };
7582    SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7583    SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7584    SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7585                                        MVT::i32, Result.getValue(1));
7586    SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7587                                        MVT::i32, cpOutL.getValue(2));
7588    SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7589    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7590    Results.push_back(cpOutH.getValue(1));
7591    return;
7592  }
7593  case ISD::ATOMIC_LOAD_ADD:
7594    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7595    return;
7596  case ISD::ATOMIC_LOAD_AND:
7597    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7598    return;
7599  case ISD::ATOMIC_LOAD_NAND:
7600    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7601    return;
7602  case ISD::ATOMIC_LOAD_OR:
7603    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7604    return;
7605  case ISD::ATOMIC_LOAD_SUB:
7606    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7607    return;
7608  case ISD::ATOMIC_LOAD_XOR:
7609    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7610    return;
7611  case ISD::ATOMIC_SWAP:
7612    ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7613    return;
7614  }
7615}
7616
7617const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7618  switch (Opcode) {
7619  default: return NULL;
7620  case X86ISD::BSF:                return "X86ISD::BSF";
7621  case X86ISD::BSR:                return "X86ISD::BSR";
7622  case X86ISD::SHLD:               return "X86ISD::SHLD";
7623  case X86ISD::SHRD:               return "X86ISD::SHRD";
7624  case X86ISD::FAND:               return "X86ISD::FAND";
7625  case X86ISD::FOR:                return "X86ISD::FOR";
7626  case X86ISD::FXOR:               return "X86ISD::FXOR";
7627  case X86ISD::FSRL:               return "X86ISD::FSRL";
7628  case X86ISD::FILD:               return "X86ISD::FILD";
7629  case X86ISD::FILD_FLAG:          return "X86ISD::FILD_FLAG";
7630  case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7631  case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7632  case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7633  case X86ISD::FLD:                return "X86ISD::FLD";
7634  case X86ISD::FST:                return "X86ISD::FST";
7635  case X86ISD::CALL:               return "X86ISD::CALL";
7636  case X86ISD::RDTSC_DAG:          return "X86ISD::RDTSC_DAG";
7637  case X86ISD::BT:                 return "X86ISD::BT";
7638  case X86ISD::CMP:                return "X86ISD::CMP";
7639  case X86ISD::COMI:               return "X86ISD::COMI";
7640  case X86ISD::UCOMI:              return "X86ISD::UCOMI";
7641  case X86ISD::SETCC:              return "X86ISD::SETCC";
7642  case X86ISD::SETCC_CARRY:        return "X86ISD::SETCC_CARRY";
7643  case X86ISD::CMOV:               return "X86ISD::CMOV";
7644  case X86ISD::BRCOND:             return "X86ISD::BRCOND";
7645  case X86ISD::RET_FLAG:           return "X86ISD::RET_FLAG";
7646  case X86ISD::REP_STOS:           return "X86ISD::REP_STOS";
7647  case X86ISD::REP_MOVS:           return "X86ISD::REP_MOVS";
7648  case X86ISD::GlobalBaseReg:      return "X86ISD::GlobalBaseReg";
7649  case X86ISD::Wrapper:            return "X86ISD::Wrapper";
7650  case X86ISD::WrapperRIP:         return "X86ISD::WrapperRIP";
7651  case X86ISD::PEXTRB:             return "X86ISD::PEXTRB";
7652  case X86ISD::PEXTRW:             return "X86ISD::PEXTRW";
7653  case X86ISD::INSERTPS:           return "X86ISD::INSERTPS";
7654  case X86ISD::PINSRB:             return "X86ISD::PINSRB";
7655  case X86ISD::PINSRW:             return "X86ISD::PINSRW";
7656  case X86ISD::PSHUFB:             return "X86ISD::PSHUFB";
7657  case X86ISD::FMAX:               return "X86ISD::FMAX";
7658  case X86ISD::FMIN:               return "X86ISD::FMIN";
7659  case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
7660  case X86ISD::FRCP:               return "X86ISD::FRCP";
7661  case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
7662  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7663  case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
7664  case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
7665  case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";
7666  case X86ISD::LCMPXCHG_DAG:       return "X86ISD::LCMPXCHG_DAG";
7667  case X86ISD::LCMPXCHG8_DAG:      return "X86ISD::LCMPXCHG8_DAG";
7668  case X86ISD::ATOMADD64_DAG:      return "X86ISD::ATOMADD64_DAG";
7669  case X86ISD::ATOMSUB64_DAG:      return "X86ISD::ATOMSUB64_DAG";
7670  case X86ISD::ATOMOR64_DAG:       return "X86ISD::ATOMOR64_DAG";
7671  case X86ISD::ATOMXOR64_DAG:      return "X86ISD::ATOMXOR64_DAG";
7672  case X86ISD::ATOMAND64_DAG:      return "X86ISD::ATOMAND64_DAG";
7673  case X86ISD::ATOMNAND64_DAG:     return "X86ISD::ATOMNAND64_DAG";
7674  case X86ISD::VZEXT_MOVL:         return "X86ISD::VZEXT_MOVL";
7675  case X86ISD::VZEXT_LOAD:         return "X86ISD::VZEXT_LOAD";
7676  case X86ISD::VSHL:               return "X86ISD::VSHL";
7677  case X86ISD::VSRL:               return "X86ISD::VSRL";
7678  case X86ISD::CMPPD:              return "X86ISD::CMPPD";
7679  case X86ISD::CMPPS:              return "X86ISD::CMPPS";
7680  case X86ISD::PCMPEQB:            return "X86ISD::PCMPEQB";
7681  case X86ISD::PCMPEQW:            return "X86ISD::PCMPEQW";
7682  case X86ISD::PCMPEQD:            return "X86ISD::PCMPEQD";
7683  case X86ISD::PCMPEQQ:            return "X86ISD::PCMPEQQ";
7684  case X86ISD::PCMPGTB:            return "X86ISD::PCMPGTB";
7685  case X86ISD::PCMPGTW:            return "X86ISD::PCMPGTW";
7686  case X86ISD::PCMPGTD:            return "X86ISD::PCMPGTD";
7687  case X86ISD::PCMPGTQ:            return "X86ISD::PCMPGTQ";
7688  case X86ISD::ADD:                return "X86ISD::ADD";
7689  case X86ISD::SUB:                return "X86ISD::SUB";
7690  case X86ISD::SMUL:               return "X86ISD::SMUL";
7691  case X86ISD::UMUL:               return "X86ISD::UMUL";
7692  case X86ISD::INC:                return "X86ISD::INC";
7693  case X86ISD::DEC:                return "X86ISD::DEC";
7694  case X86ISD::OR:                 return "X86ISD::OR";
7695  case X86ISD::XOR:                return "X86ISD::XOR";
7696  case X86ISD::AND:                return "X86ISD::AND";
7697  case X86ISD::MUL_IMM:            return "X86ISD::MUL_IMM";
7698  case X86ISD::PTEST:              return "X86ISD::PTEST";
7699  case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7700  }
7701}
7702
7703// isLegalAddressingMode - Return true if the addressing mode represented
7704// by AM is legal for this target, for a load/store of the specified type.
7705bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7706                                              const Type *Ty) const {
7707  // X86 supports extremely general addressing modes.
7708  CodeModel::Model M = getTargetMachine().getCodeModel();
7709
7710  // X86 allows a sign-extended 32-bit immediate field as a displacement.
7711  if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7712    return false;
7713
7714  if (AM.BaseGV) {
7715    unsigned GVFlags =
7716      Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7717
7718    // If a reference to this global requires an extra load, we can't fold it.
7719    if (isGlobalStubReference(GVFlags))
7720      return false;
7721
7722    // If BaseGV requires a register for the PIC base, we cannot also have a
7723    // BaseReg specified.
7724    if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7725      return false;
7726
7727    // If lower 4G is not available, then we must use rip-relative addressing.
7728    if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7729      return false;
7730  }
7731
7732  switch (AM.Scale) {
7733  case 0:
7734  case 1:
7735  case 2:
7736  case 4:
7737  case 8:
7738    // These scales always work.
7739    break;
7740  case 3:
7741  case 5:
7742  case 9:
7743    // These scales are formed with basereg+scalereg.  Only accept if there is
7744    // no basereg yet.
7745    if (AM.HasBaseReg)
7746      return false;
7747    break;
7748  default:  // Other stuff never works.
7749    return false;
7750  }
7751
7752  return true;
7753}
7754
7755
7756bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7757  if (!Ty1->isInteger() || !Ty2->isInteger())
7758    return false;
7759  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7760  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7761  if (NumBits1 <= NumBits2)
7762    return false;
7763  return Subtarget->is64Bit() || NumBits1 < 64;
7764}
7765
7766bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7767  if (!VT1.isInteger() || !VT2.isInteger())
7768    return false;
7769  unsigned NumBits1 = VT1.getSizeInBits();
7770  unsigned NumBits2 = VT2.getSizeInBits();
7771  if (NumBits1 <= NumBits2)
7772    return false;
7773  return Subtarget->is64Bit() || NumBits1 < 64;
7774}
7775
7776bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7777  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7778  return Ty1->isInteger(32) && Ty2->isInteger(64) && Subtarget->is64Bit();
7779}
7780
7781bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7782  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7783  return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7784}
7785
7786bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7787  // i16 instructions are longer (0x66 prefix) and potentially slower.
7788  return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7789}
7790
7791/// isShuffleMaskLegal - Targets can use this to indicate that they only
7792/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7793/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7794/// are assumed to be legal.
7795bool
7796X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7797                                      EVT VT) const {
7798  // Only do shuffles on 128-bit vector types for now.
7799  if (VT.getSizeInBits() == 64)
7800    return false;
7801
7802  // FIXME: pshufb, blends, shifts.
7803  return (VT.getVectorNumElements() == 2 ||
7804          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7805          isMOVLMask(M, VT) ||
7806          isSHUFPMask(M, VT) ||
7807          isPSHUFDMask(M, VT) ||
7808          isPSHUFHWMask(M, VT) ||
7809          isPSHUFLWMask(M, VT) ||
7810          isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7811          isUNPCKLMask(M, VT) ||
7812          isUNPCKHMask(M, VT) ||
7813          isUNPCKL_v_undef_Mask(M, VT) ||
7814          isUNPCKH_v_undef_Mask(M, VT));
7815}
7816
7817bool
7818X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7819                                          EVT VT) const {
7820  unsigned NumElts = VT.getVectorNumElements();
7821  // FIXME: This collection of masks seems suspect.
7822  if (NumElts == 2)
7823    return true;
7824  if (NumElts == 4 && VT.getSizeInBits() == 128) {
7825    return (isMOVLMask(Mask, VT)  ||
7826            isCommutedMOVLMask(Mask, VT, true) ||
7827            isSHUFPMask(Mask, VT) ||
7828            isCommutedSHUFPMask(Mask, VT));
7829  }
7830  return false;
7831}
7832
7833//===----------------------------------------------------------------------===//
7834//                           X86 Scheduler Hooks
7835//===----------------------------------------------------------------------===//
7836
7837// private utility function
7838MachineBasicBlock *
7839X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7840                                                       MachineBasicBlock *MBB,
7841                                                       unsigned regOpc,
7842                                                       unsigned immOpc,
7843                                                       unsigned LoadOpc,
7844                                                       unsigned CXchgOpc,
7845                                                       unsigned copyOpc,
7846                                                       unsigned notOpc,
7847                                                       unsigned EAXreg,
7848                                                       TargetRegisterClass *RC,
7849                                                       bool invSrc) const {
7850  // For the atomic bitwise operator, we generate
7851  //   thisMBB:
7852  //   newMBB:
7853  //     ld  t1 = [bitinstr.addr]
7854  //     op  t2 = t1, [bitinstr.val]
7855  //     mov EAX = t1
7856  //     lcs dest = [bitinstr.addr], t2  [EAX is implicit]
7857  //     bz  newMBB
7858  //     fallthrough -->nextMBB
7859  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7860  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7861  MachineFunction::iterator MBBIter = MBB;
7862  ++MBBIter;
7863
7864  /// First build the CFG
7865  MachineFunction *F = MBB->getParent();
7866  MachineBasicBlock *thisMBB = MBB;
7867  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7868  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7869  F->insert(MBBIter, newMBB);
7870  F->insert(MBBIter, nextMBB);
7871
7872  // Move all successors to thisMBB to nextMBB
7873  nextMBB->transferSuccessors(thisMBB);
7874
7875  // Update thisMBB to fall through to newMBB
7876  thisMBB->addSuccessor(newMBB);
7877
7878  // newMBB jumps to itself and fall through to nextMBB
7879  newMBB->addSuccessor(nextMBB);
7880  newMBB->addSuccessor(newMBB);
7881
7882  // Insert instructions into newMBB based on incoming instruction
7883  assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7884         "unexpected number of operands");
7885  DebugLoc dl = bInstr->getDebugLoc();
7886  MachineOperand& destOper = bInstr->getOperand(0);
7887  MachineOperand* argOpers[2 + X86AddrNumOperands];
7888  int numArgs = bInstr->getNumOperands() - 1;
7889  for (int i=0; i < numArgs; ++i)
7890    argOpers[i] = &bInstr->getOperand(i+1);
7891
7892  // x86 address has 4 operands: base, index, scale, and displacement
7893  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7894  int valArgIndx = lastAddrIndx + 1;
7895
7896  unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7897  MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7898  for (int i=0; i <= lastAddrIndx; ++i)
7899    (*MIB).addOperand(*argOpers[i]);
7900
7901  unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7902  if (invSrc) {
7903    MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7904  }
7905  else
7906    tt = t1;
7907
7908  unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7909  assert((argOpers[valArgIndx]->isReg() ||
7910          argOpers[valArgIndx]->isImm()) &&
7911         "invalid operand");
7912  if (argOpers[valArgIndx]->isReg())
7913    MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7914  else
7915    MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7916  MIB.addReg(tt);
7917  (*MIB).addOperand(*argOpers[valArgIndx]);
7918
7919  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7920  MIB.addReg(t1);
7921
7922  MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7923  for (int i=0; i <= lastAddrIndx; ++i)
7924    (*MIB).addOperand(*argOpers[i]);
7925  MIB.addReg(t2);
7926  assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7927  (*MIB).setMemRefs(bInstr->memoperands_begin(),
7928                    bInstr->memoperands_end());
7929
7930  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7931  MIB.addReg(EAXreg);
7932
7933  // insert branch
7934  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7935
7936  F->DeleteMachineInstr(bInstr);   // The pseudo instruction is gone now.
7937  return nextMBB;
7938}
7939
7940// private utility function:  64 bit atomics on 32 bit host.
7941MachineBasicBlock *
7942X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7943                                                       MachineBasicBlock *MBB,
7944                                                       unsigned regOpcL,
7945                                                       unsigned regOpcH,
7946                                                       unsigned immOpcL,
7947                                                       unsigned immOpcH,
7948                                                       bool invSrc) const {
7949  // For the atomic bitwise operator, we generate
7950  //   thisMBB (instructions are in pairs, except cmpxchg8b)
7951  //     ld t1,t2 = [bitinstr.addr]
7952  //   newMBB:
7953  //     out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7954  //     op  t5, t6 <- out1, out2, [bitinstr.val]
7955  //      (for SWAP, substitute:  mov t5, t6 <- [bitinstr.val])
7956  //     mov ECX, EBX <- t5, t6
7957  //     mov EAX, EDX <- t1, t2
7958  //     cmpxchg8b [bitinstr.addr]  [EAX, EDX, EBX, ECX implicit]
7959  //     mov t3, t4 <- EAX, EDX
7960  //     bz  newMBB
7961  //     result in out1, out2
7962  //     fallthrough -->nextMBB
7963
7964  const TargetRegisterClass *RC = X86::GR32RegisterClass;
7965  const unsigned LoadOpc = X86::MOV32rm;
7966  const unsigned copyOpc = X86::MOV32rr;
7967  const unsigned NotOpc = X86::NOT32r;
7968  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7969  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7970  MachineFunction::iterator MBBIter = MBB;
7971  ++MBBIter;
7972
7973  /// First build the CFG
7974  MachineFunction *F = MBB->getParent();
7975  MachineBasicBlock *thisMBB = MBB;
7976  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7977  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7978  F->insert(MBBIter, newMBB);
7979  F->insert(MBBIter, nextMBB);
7980
7981  // Move all successors to thisMBB to nextMBB
7982  nextMBB->transferSuccessors(thisMBB);
7983
7984  // Update thisMBB to fall through to newMBB
7985  thisMBB->addSuccessor(newMBB);
7986
7987  // newMBB jumps to itself and fall through to nextMBB
7988  newMBB->addSuccessor(nextMBB);
7989  newMBB->addSuccessor(newMBB);
7990
7991  DebugLoc dl = bInstr->getDebugLoc();
7992  // Insert instructions into newMBB based on incoming instruction
7993  // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7994  assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7995         "unexpected number of operands");
7996  MachineOperand& dest1Oper = bInstr->getOperand(0);
7997  MachineOperand& dest2Oper = bInstr->getOperand(1);
7998  MachineOperand* argOpers[2 + X86AddrNumOperands];
7999  for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8000    argOpers[i] = &bInstr->getOperand(i+2);
8001
8002  // x86 address has 5 operands: base, index, scale, displacement, and segment.
8003  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8004
8005  unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8006  MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8007  for (int i=0; i <= lastAddrIndx; ++i)
8008    (*MIB).addOperand(*argOpers[i]);
8009  unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8010  MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8011  // add 4 to displacement.
8012  for (int i=0; i <= lastAddrIndx-2; ++i)
8013    (*MIB).addOperand(*argOpers[i]);
8014  MachineOperand newOp3 = *(argOpers[3]);
8015  if (newOp3.isImm())
8016    newOp3.setImm(newOp3.getImm()+4);
8017  else
8018    newOp3.setOffset(newOp3.getOffset()+4);
8019  (*MIB).addOperand(newOp3);
8020  (*MIB).addOperand(*argOpers[lastAddrIndx]);
8021
8022  // t3/4 are defined later, at the bottom of the loop
8023  unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8024  unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8025  BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8026    .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8027  BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8028    .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8029
8030  // The subsequent operations should be using the destination registers of
8031  //the PHI instructions.
8032  if (invSrc) {
8033    t1 = F->getRegInfo().createVirtualRegister(RC);
8034    t2 = F->getRegInfo().createVirtualRegister(RC);
8035    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8036    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8037  } else {
8038    t1 = dest1Oper.getReg();
8039    t2 = dest2Oper.getReg();
8040  }
8041
8042  int valArgIndx = lastAddrIndx + 1;
8043  assert((argOpers[valArgIndx]->isReg() ||
8044          argOpers[valArgIndx]->isImm()) &&
8045         "invalid operand");
8046  unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8047  unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8048  if (argOpers[valArgIndx]->isReg())
8049    MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8050  else
8051    MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8052  if (regOpcL != X86::MOV32rr)
8053    MIB.addReg(t1);
8054  (*MIB).addOperand(*argOpers[valArgIndx]);
8055  assert(argOpers[valArgIndx + 1]->isReg() ==
8056         argOpers[valArgIndx]->isReg());
8057  assert(argOpers[valArgIndx + 1]->isImm() ==
8058         argOpers[valArgIndx]->isImm());
8059  if (argOpers[valArgIndx + 1]->isReg())
8060    MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8061  else
8062    MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8063  if (regOpcH != X86::MOV32rr)
8064    MIB.addReg(t2);
8065  (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8066
8067  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8068  MIB.addReg(t1);
8069  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8070  MIB.addReg(t2);
8071
8072  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8073  MIB.addReg(t5);
8074  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8075  MIB.addReg(t6);
8076
8077  MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8078  for (int i=0; i <= lastAddrIndx; ++i)
8079    (*MIB).addOperand(*argOpers[i]);
8080
8081  assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8082  (*MIB).setMemRefs(bInstr->memoperands_begin(),
8083                    bInstr->memoperands_end());
8084
8085  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8086  MIB.addReg(X86::EAX);
8087  MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8088  MIB.addReg(X86::EDX);
8089
8090  // insert branch
8091  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
8092
8093  F->DeleteMachineInstr(bInstr);   // The pseudo instruction is gone now.
8094  return nextMBB;
8095}
8096
8097// private utility function
8098MachineBasicBlock *
8099X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8100                                                      MachineBasicBlock *MBB,
8101                                                      unsigned cmovOpc) const {
8102  // For the atomic min/max operator, we generate
8103  //   thisMBB:
8104  //   newMBB:
8105  //     ld t1 = [min/max.addr]
8106  //     mov t2 = [min/max.val]
8107  //     cmp  t1, t2
8108  //     cmov[cond] t2 = t1
8109  //     mov EAX = t1
8110  //     lcs dest = [bitinstr.addr], t2  [EAX is implicit]
8111  //     bz   newMBB
8112  //     fallthrough -->nextMBB
8113  //
8114  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8115  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8116  MachineFunction::iterator MBBIter = MBB;
8117  ++MBBIter;
8118
8119  /// First build the CFG
8120  MachineFunction *F = MBB->getParent();
8121  MachineBasicBlock *thisMBB = MBB;
8122  MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8123  MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8124  F->insert(MBBIter, newMBB);
8125  F->insert(MBBIter, nextMBB);
8126
8127  // Move all successors of thisMBB to nextMBB
8128  nextMBB->transferSuccessors(thisMBB);
8129
8130  // Update thisMBB to fall through to newMBB
8131  thisMBB->addSuccessor(newMBB);
8132
8133  // newMBB jumps to newMBB and fall through to nextMBB
8134  newMBB->addSuccessor(nextMBB);
8135  newMBB->addSuccessor(newMBB);
8136
8137  DebugLoc dl = mInstr->getDebugLoc();
8138  // Insert instructions into newMBB based on incoming instruction
8139  assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8140         "unexpected number of operands");
8141  MachineOperand& destOper = mInstr->getOperand(0);
8142  MachineOperand* argOpers[2 + X86AddrNumOperands];
8143  int numArgs = mInstr->getNumOperands() - 1;
8144  for (int i=0; i < numArgs; ++i)
8145    argOpers[i] = &mInstr->getOperand(i+1);
8146
8147  // x86 address has 4 operands: base, index, scale, and displacement
8148  int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8149  int valArgIndx = lastAddrIndx + 1;
8150
8151  unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8152  MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8153  for (int i=0; i <= lastAddrIndx; ++i)
8154    (*MIB).addOperand(*argOpers[i]);
8155
8156  // We only support register and immediate values
8157  assert((argOpers[valArgIndx]->isReg() ||
8158          argOpers[valArgIndx]->isImm()) &&
8159         "invalid operand");
8160
8161  unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8162  if (argOpers[valArgIndx]->isReg())
8163    MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8164  else
8165    MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8166  (*MIB).addOperand(*argOpers[valArgIndx]);
8167
8168  MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8169  MIB.addReg(t1);
8170
8171  MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8172  MIB.addReg(t1);
8173  MIB.addReg(t2);
8174
8175  // Generate movc
8176  unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8177  MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8178  MIB.addReg(t2);
8179  MIB.addReg(t1);
8180
8181  // Cmp and exchange if none has modified the memory location
8182  MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8183  for (int i=0; i <= lastAddrIndx; ++i)
8184    (*MIB).addOperand(*argOpers[i]);
8185  MIB.addReg(t3);
8186  assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8187  (*MIB).setMemRefs(mInstr->memoperands_begin(),
8188                    mInstr->memoperands_end());
8189
8190  MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8191  MIB.addReg(X86::EAX);
8192
8193  // insert branch
8194  BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
8195
8196  F->DeleteMachineInstr(mInstr);   // The pseudo instruction is gone now.
8197  return nextMBB;
8198}
8199
8200// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8201// all of this code can be replaced with that in the .td file.
8202MachineBasicBlock *
8203X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8204                            unsigned numArgs, bool memArg) const {
8205
8206  MachineFunction *F = BB->getParent();
8207  DebugLoc dl = MI->getDebugLoc();
8208  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8209
8210  unsigned Opc;
8211  if (memArg)
8212    Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8213  else
8214    Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8215
8216  MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8217
8218  for (unsigned i = 0; i < numArgs; ++i) {
8219    MachineOperand &Op = MI->getOperand(i+1);
8220
8221    if (!(Op.isReg() && Op.isImplicit()))
8222      MIB.addOperand(Op);
8223  }
8224
8225  BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8226    .addReg(X86::XMM0);
8227
8228  F->DeleteMachineInstr(MI);
8229
8230  return BB;
8231}
8232
8233MachineBasicBlock *
8234X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8235                                                 MachineInstr *MI,
8236                                                 MachineBasicBlock *MBB) const {
8237  // Emit code to save XMM registers to the stack. The ABI says that the
8238  // number of registers to save is given in %al, so it's theoretically
8239  // possible to do an indirect jump trick to avoid saving all of them,
8240  // however this code takes a simpler approach and just executes all
8241  // of the stores if %al is non-zero. It's less code, and it's probably
8242  // easier on the hardware branch predictor, and stores aren't all that
8243  // expensive anyway.
8244
8245  // Create the new basic blocks. One block contains all the XMM stores,
8246  // and one block is the final destination regardless of whether any
8247  // stores were performed.
8248  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8249  MachineFunction *F = MBB->getParent();
8250  MachineFunction::iterator MBBIter = MBB;
8251  ++MBBIter;
8252  MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8253  MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8254  F->insert(MBBIter, XMMSaveMBB);
8255  F->insert(MBBIter, EndMBB);
8256
8257  // Set up the CFG.
8258  // Move any original successors of MBB to the end block.
8259  EndMBB->transferSuccessors(MBB);
8260  // The original block will now fall through to the XMM save block.
8261  MBB->addSuccessor(XMMSaveMBB);
8262  // The XMMSaveMBB will fall through to the end block.
8263  XMMSaveMBB->addSuccessor(EndMBB);
8264
8265  // Now add the instructions.
8266  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8267  DebugLoc DL = MI->getDebugLoc();
8268
8269  unsigned CountReg = MI->getOperand(0).getReg();
8270  int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8271  int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8272
8273  if (!Subtarget->isTargetWin64()) {
8274    // If %al is 0, branch around the XMM save block.
8275    BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8276    BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8277    MBB->addSuccessor(EndMBB);
8278  }
8279
8280  // In the XMM save block, save all the XMM argument registers.
8281  for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8282    int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8283    MachineMemOperand *MMO =
8284      F->getMachineMemOperand(
8285        PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8286        MachineMemOperand::MOStore, Offset,
8287        /*Size=*/16, /*Align=*/16);
8288    BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8289      .addFrameIndex(RegSaveFrameIndex)
8290      .addImm(/*Scale=*/1)
8291      .addReg(/*IndexReg=*/0)
8292      .addImm(/*Disp=*/Offset)
8293      .addReg(/*Segment=*/0)
8294      .addReg(MI->getOperand(i).getReg())
8295      .addMemOperand(MMO);
8296  }
8297
8298  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8299
8300  return EndMBB;
8301}
8302
8303MachineBasicBlock *
8304X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8305                                     MachineBasicBlock *BB,
8306                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8307  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8308  DebugLoc DL = MI->getDebugLoc();
8309
8310  // To "insert" a SELECT_CC instruction, we actually have to insert the
8311  // diamond control-flow pattern.  The incoming instruction knows the
8312  // destination vreg to set, the condition code register to branch on, the
8313  // true/false values to select between, and a branch opcode to use.
8314  const BasicBlock *LLVM_BB = BB->getBasicBlock();
8315  MachineFunction::iterator It = BB;
8316  ++It;
8317
8318  //  thisMBB:
8319  //  ...
8320  //   TrueVal = ...
8321  //   cmpTY ccX, r1, r2
8322  //   bCC copy1MBB
8323  //   fallthrough --> copy0MBB
8324  MachineBasicBlock *thisMBB = BB;
8325  MachineFunction *F = BB->getParent();
8326  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8327  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8328  unsigned Opc =
8329    X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8330  BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8331  F->insert(It, copy0MBB);
8332  F->insert(It, sinkMBB);
8333  // Update machine-CFG edges by first adding all successors of the current
8334  // block to the new block which will contain the Phi node for the select.
8335  // Also inform sdisel of the edge changes.
8336  for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8337         E = BB->succ_end(); I != E; ++I) {
8338    EM->insert(std::make_pair(*I, sinkMBB));
8339    sinkMBB->addSuccessor(*I);
8340  }
8341  // Next, remove all successors of the current block, and add the true
8342  // and fallthrough blocks as its successors.
8343  while (!BB->succ_empty())
8344    BB->removeSuccessor(BB->succ_begin());
8345  // Add the true and fallthrough blocks as its successors.
8346  BB->addSuccessor(copy0MBB);
8347  BB->addSuccessor(sinkMBB);
8348
8349  //  copy0MBB:
8350  //   %FalseValue = ...
8351  //   # fallthrough to sinkMBB
8352  BB = copy0MBB;
8353
8354  // Update machine-CFG edges
8355  BB->addSuccessor(sinkMBB);
8356
8357  //  sinkMBB:
8358  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8359  //  ...
8360  BB = sinkMBB;
8361  BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8362    .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8363    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8364
8365  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8366  return BB;
8367}
8368
8369
8370MachineBasicBlock *
8371X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8372                                               MachineBasicBlock *BB,
8373                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8374  switch (MI->getOpcode()) {
8375  default: assert(false && "Unexpected instr type to insert");
8376  case X86::CMOV_GR8:
8377  case X86::CMOV_V1I64:
8378  case X86::CMOV_FR32:
8379  case X86::CMOV_FR64:
8380  case X86::CMOV_V4F32:
8381  case X86::CMOV_V2F64:
8382  case X86::CMOV_V2I64:
8383    return EmitLoweredSelect(MI, BB, EM);
8384
8385  case X86::FP32_TO_INT16_IN_MEM:
8386  case X86::FP32_TO_INT32_IN_MEM:
8387  case X86::FP32_TO_INT64_IN_MEM:
8388  case X86::FP64_TO_INT16_IN_MEM:
8389  case X86::FP64_TO_INT32_IN_MEM:
8390  case X86::FP64_TO_INT64_IN_MEM:
8391  case X86::FP80_TO_INT16_IN_MEM:
8392  case X86::FP80_TO_INT32_IN_MEM:
8393  case X86::FP80_TO_INT64_IN_MEM: {
8394    const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8395    DebugLoc DL = MI->getDebugLoc();
8396
8397    // Change the floating point control register to use "round towards zero"
8398    // mode when truncating to an integer value.
8399    MachineFunction *F = BB->getParent();
8400    int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8401    addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8402
8403    // Load the old value of the high byte of the control word...
8404    unsigned OldCW =
8405      F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8406    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8407                      CWFrameIdx);
8408
8409    // Set the high part to be round to zero...
8410    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8411      .addImm(0xC7F);
8412
8413    // Reload the modified control word now...
8414    addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8415
8416    // Restore the memory image of control word to original value
8417    addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8418      .addReg(OldCW);
8419
8420    // Get the X86 opcode to use.
8421    unsigned Opc;
8422    switch (MI->getOpcode()) {
8423    default: llvm_unreachable("illegal opcode!");
8424    case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8425    case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8426    case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8427    case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8428    case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8429    case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8430    case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8431    case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8432    case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8433    }
8434
8435    X86AddressMode AM;
8436    MachineOperand &Op = MI->getOperand(0);
8437    if (Op.isReg()) {
8438      AM.BaseType = X86AddressMode::RegBase;
8439      AM.Base.Reg = Op.getReg();
8440    } else {
8441      AM.BaseType = X86AddressMode::FrameIndexBase;
8442      AM.Base.FrameIndex = Op.getIndex();
8443    }
8444    Op = MI->getOperand(1);
8445    if (Op.isImm())
8446      AM.Scale = Op.getImm();
8447    Op = MI->getOperand(2);
8448    if (Op.isImm())
8449      AM.IndexReg = Op.getImm();
8450    Op = MI->getOperand(3);
8451    if (Op.isGlobal()) {
8452      AM.GV = Op.getGlobal();
8453    } else {
8454      AM.Disp = Op.getImm();
8455    }
8456    addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8457                      .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8458
8459    // Reload the original control word now.
8460    addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8461
8462    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
8463    return BB;
8464  }
8465    // String/text processing lowering.
8466  case X86::PCMPISTRM128REG:
8467    return EmitPCMP(MI, BB, 3, false /* in-mem */);
8468  case X86::PCMPISTRM128MEM:
8469    return EmitPCMP(MI, BB, 3, true /* in-mem */);
8470  case X86::PCMPESTRM128REG:
8471    return EmitPCMP(MI, BB, 5, false /* in mem */);
8472  case X86::PCMPESTRM128MEM:
8473    return EmitPCMP(MI, BB, 5, true /* in mem */);
8474
8475    // Atomic Lowering.
8476  case X86::ATOMAND32:
8477    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8478                                               X86::AND32ri, X86::MOV32rm,
8479                                               X86::LCMPXCHG32, X86::MOV32rr,
8480                                               X86::NOT32r, X86::EAX,
8481                                               X86::GR32RegisterClass);
8482  case X86::ATOMOR32:
8483    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8484                                               X86::OR32ri, X86::MOV32rm,
8485                                               X86::LCMPXCHG32, X86::MOV32rr,
8486                                               X86::NOT32r, X86::EAX,
8487                                               X86::GR32RegisterClass);
8488  case X86::ATOMXOR32:
8489    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8490                                               X86::XOR32ri, X86::MOV32rm,
8491                                               X86::LCMPXCHG32, X86::MOV32rr,
8492                                               X86::NOT32r, X86::EAX,
8493                                               X86::GR32RegisterClass);
8494  case X86::ATOMNAND32:
8495    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8496                                               X86::AND32ri, X86::MOV32rm,
8497                                               X86::LCMPXCHG32, X86::MOV32rr,
8498                                               X86::NOT32r, X86::EAX,
8499                                               X86::GR32RegisterClass, true);
8500  case X86::ATOMMIN32:
8501    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8502  case X86::ATOMMAX32:
8503    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8504  case X86::ATOMUMIN32:
8505    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8506  case X86::ATOMUMAX32:
8507    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8508
8509  case X86::ATOMAND16:
8510    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8511                                               X86::AND16ri, X86::MOV16rm,
8512                                               X86::LCMPXCHG16, X86::MOV16rr,
8513                                               X86::NOT16r, X86::AX,
8514                                               X86::GR16RegisterClass);
8515  case X86::ATOMOR16:
8516    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8517                                               X86::OR16ri, X86::MOV16rm,
8518                                               X86::LCMPXCHG16, X86::MOV16rr,
8519                                               X86::NOT16r, X86::AX,
8520                                               X86::GR16RegisterClass);
8521  case X86::ATOMXOR16:
8522    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8523                                               X86::XOR16ri, X86::MOV16rm,
8524                                               X86::LCMPXCHG16, X86::MOV16rr,
8525                                               X86::NOT16r, X86::AX,
8526                                               X86::GR16RegisterClass);
8527  case X86::ATOMNAND16:
8528    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8529                                               X86::AND16ri, X86::MOV16rm,
8530                                               X86::LCMPXCHG16, X86::MOV16rr,
8531                                               X86::NOT16r, X86::AX,
8532                                               X86::GR16RegisterClass, true);
8533  case X86::ATOMMIN16:
8534    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8535  case X86::ATOMMAX16:
8536    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8537  case X86::ATOMUMIN16:
8538    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8539  case X86::ATOMUMAX16:
8540    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8541
8542  case X86::ATOMAND8:
8543    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8544                                               X86::AND8ri, X86::MOV8rm,
8545                                               X86::LCMPXCHG8, X86::MOV8rr,
8546                                               X86::NOT8r, X86::AL,
8547                                               X86::GR8RegisterClass);
8548  case X86::ATOMOR8:
8549    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8550                                               X86::OR8ri, X86::MOV8rm,
8551                                               X86::LCMPXCHG8, X86::MOV8rr,
8552                                               X86::NOT8r, X86::AL,
8553                                               X86::GR8RegisterClass);
8554  case X86::ATOMXOR8:
8555    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8556                                               X86::XOR8ri, X86::MOV8rm,
8557                                               X86::LCMPXCHG8, X86::MOV8rr,
8558                                               X86::NOT8r, X86::AL,
8559                                               X86::GR8RegisterClass);
8560  case X86::ATOMNAND8:
8561    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8562                                               X86::AND8ri, X86::MOV8rm,
8563                                               X86::LCMPXCHG8, X86::MOV8rr,
8564                                               X86::NOT8r, X86::AL,
8565                                               X86::GR8RegisterClass, true);
8566  // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8567  // This group is for 64-bit host.
8568  case X86::ATOMAND64:
8569    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8570                                               X86::AND64ri32, X86::MOV64rm,
8571                                               X86::LCMPXCHG64, X86::MOV64rr,
8572                                               X86::NOT64r, X86::RAX,
8573                                               X86::GR64RegisterClass);
8574  case X86::ATOMOR64:
8575    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8576                                               X86::OR64ri32, X86::MOV64rm,
8577                                               X86::LCMPXCHG64, X86::MOV64rr,
8578                                               X86::NOT64r, X86::RAX,
8579                                               X86::GR64RegisterClass);
8580  case X86::ATOMXOR64:
8581    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8582                                               X86::XOR64ri32, X86::MOV64rm,
8583                                               X86::LCMPXCHG64, X86::MOV64rr,
8584                                               X86::NOT64r, X86::RAX,
8585                                               X86::GR64RegisterClass);
8586  case X86::ATOMNAND64:
8587    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8588                                               X86::AND64ri32, X86::MOV64rm,
8589                                               X86::LCMPXCHG64, X86::MOV64rr,
8590                                               X86::NOT64r, X86::RAX,
8591                                               X86::GR64RegisterClass, true);
8592  case X86::ATOMMIN64:
8593    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8594  case X86::ATOMMAX64:
8595    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8596  case X86::ATOMUMIN64:
8597    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8598  case X86::ATOMUMAX64:
8599    return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8600
8601  // This group does 64-bit operations on a 32-bit host.
8602  case X86::ATOMAND6432:
8603    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8604                                               X86::AND32rr, X86::AND32rr,
8605                                               X86::AND32ri, X86::AND32ri,
8606                                               false);
8607  case X86::ATOMOR6432:
8608    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8609                                               X86::OR32rr, X86::OR32rr,
8610                                               X86::OR32ri, X86::OR32ri,
8611                                               false);
8612  case X86::ATOMXOR6432:
8613    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8614                                               X86::XOR32rr, X86::XOR32rr,
8615                                               X86::XOR32ri, X86::XOR32ri,
8616                                               false);
8617  case X86::ATOMNAND6432:
8618    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8619                                               X86::AND32rr, X86::AND32rr,
8620                                               X86::AND32ri, X86::AND32ri,
8621                                               true);
8622  case X86::ATOMADD6432:
8623    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8624                                               X86::ADD32rr, X86::ADC32rr,
8625                                               X86::ADD32ri, X86::ADC32ri,
8626                                               false);
8627  case X86::ATOMSUB6432:
8628    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8629                                               X86::SUB32rr, X86::SBB32rr,
8630                                               X86::SUB32ri, X86::SBB32ri,
8631                                               false);
8632  case X86::ATOMSWAP6432:
8633    return EmitAtomicBit6432WithCustomInserter(MI, BB,
8634                                               X86::MOV32rr, X86::MOV32rr,
8635                                               X86::MOV32ri, X86::MOV32ri,
8636                                               false);
8637  case X86::VASTART_SAVE_XMM_REGS:
8638    return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8639  }
8640}
8641
8642//===----------------------------------------------------------------------===//
8643//                           X86 Optimization Hooks
8644//===----------------------------------------------------------------------===//
8645
8646void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8647                                                       const APInt &Mask,
8648                                                       APInt &KnownZero,
8649                                                       APInt &KnownOne,
8650                                                       const SelectionDAG &DAG,
8651                                                       unsigned Depth) const {
8652  unsigned Opc = Op.getOpcode();
8653  assert((Opc >= ISD::BUILTIN_OP_END ||
8654          Opc == ISD::INTRINSIC_WO_CHAIN ||
8655          Opc == ISD::INTRINSIC_W_CHAIN ||
8656          Opc == ISD::INTRINSIC_VOID) &&
8657         "Should use MaskedValueIsZero if you don't know whether Op"
8658         " is a target node!");
8659
8660  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
8661  switch (Opc) {
8662  default: break;
8663  case X86ISD::ADD:
8664  case X86ISD::SUB:
8665  case X86ISD::SMUL:
8666  case X86ISD::UMUL:
8667  case X86ISD::INC:
8668  case X86ISD::DEC:
8669  case X86ISD::OR:
8670  case X86ISD::XOR:
8671  case X86ISD::AND:
8672    // These nodes' second result is a boolean.
8673    if (Op.getResNo() == 0)
8674      break;
8675    // Fallthrough
8676  case X86ISD::SETCC:
8677    KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8678                                       Mask.getBitWidth() - 1);
8679    break;
8680  }
8681}
8682
8683/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8684/// node is a GlobalAddress + offset.
8685bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8686                                       GlobalValue* &GA, int64_t &Offset) const{
8687  if (N->getOpcode() == X86ISD::Wrapper) {
8688    if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8689      GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8690      Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8691      return true;
8692    }
8693  }
8694  return TargetLowering::isGAPlusOffset(N, GA, Offset);
8695}
8696
8697static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8698                                     EVT EltVT, LoadSDNode *&LDBase,
8699                                     unsigned &LastLoadedElt,
8700                                     SelectionDAG &DAG, MachineFrameInfo *MFI,
8701                                     const TargetLowering &TLI) {
8702  LDBase = NULL;
8703  LastLoadedElt = -1U;
8704  for (unsigned i = 0; i < NumElems; ++i) {
8705    if (N->getMaskElt(i) < 0) {
8706      if (!LDBase)
8707        return false;
8708      continue;
8709    }
8710
8711    SDValue Elt = DAG.getShuffleScalarElt(N, i);
8712    if (!Elt.getNode() ||
8713        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8714      return false;
8715    if (!LDBase) {
8716      if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8717        return false;
8718      LDBase = cast<LoadSDNode>(Elt.getNode());
8719      LastLoadedElt = i;
8720      continue;
8721    }
8722    if (Elt.getOpcode() == ISD::UNDEF)
8723      continue;
8724
8725    LoadSDNode *LD = cast<LoadSDNode>(Elt);
8726    if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8727      return false;
8728    LastLoadedElt = i;
8729  }
8730  return true;
8731}
8732
8733/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8734/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8735/// if the load addresses are consecutive, non-overlapping, and in the right
8736/// order.  In the case of v2i64, it will see if it can rewrite the
8737/// shuffle to be an appropriate build vector so it can take advantage of
8738// performBuildVectorCombine.
8739static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8740                                     const TargetLowering &TLI) {
8741  DebugLoc dl = N->getDebugLoc();
8742  EVT VT = N->getValueType(0);
8743  EVT EltVT = VT.getVectorElementType();
8744  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8745  unsigned NumElems = VT.getVectorNumElements();
8746
8747  if (VT.getSizeInBits() != 128)
8748    return SDValue();
8749
8750  // Try to combine a vector_shuffle into a 128-bit load.
8751  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8752  LoadSDNode *LD = NULL;
8753  unsigned LastLoadedElt;
8754  if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8755                                MFI, TLI))
8756    return SDValue();
8757
8758  if (LastLoadedElt == NumElems - 1) {
8759    if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8760      return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8761                         LD->getSrcValue(), LD->getSrcValueOffset(),
8762                         LD->isVolatile());
8763    return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8764                       LD->getSrcValue(), LD->getSrcValueOffset(),
8765                       LD->isVolatile(), LD->getAlignment());
8766  } else if (NumElems == 4 && LastLoadedElt == 1) {
8767    SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8768    SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8769    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8770    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8771  }
8772  return SDValue();
8773}
8774
8775/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8776static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8777                                    const X86Subtarget *Subtarget) {
8778  DebugLoc DL = N->getDebugLoc();
8779  SDValue Cond = N->getOperand(0);
8780  // Get the LHS/RHS of the select.
8781  SDValue LHS = N->getOperand(1);
8782  SDValue RHS = N->getOperand(2);
8783
8784  // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8785  // instructions have the peculiarity that if either operand is a NaN,
8786  // they chose what we call the RHS operand (and as such are not symmetric).
8787  // It happens that this matches the semantics of the common C idiom
8788  // x<y?x:y and related forms, so we can recognize these cases.
8789  if (Subtarget->hasSSE2() &&
8790      (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8791      Cond.getOpcode() == ISD::SETCC) {
8792    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8793
8794    unsigned Opcode = 0;
8795    // Check for x CC y ? x : y.
8796    if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8797      switch (CC) {
8798      default: break;
8799      case ISD::SETULT:
8800        // This can be a min if we can prove that at least one of the operands
8801        // is not a nan.
8802        if (!FiniteOnlyFPMath()) {
8803          if (DAG.isKnownNeverNaN(RHS)) {
8804            // Put the potential NaN in the RHS so that SSE will preserve it.
8805            std::swap(LHS, RHS);
8806          } else if (!DAG.isKnownNeverNaN(LHS))
8807            break;
8808        }
8809        Opcode = X86ISD::FMIN;
8810        break;
8811      case ISD::SETOLE:
8812        // This can be a min if we can prove that at least one of the operands
8813        // is not a nan.
8814        if (!FiniteOnlyFPMath()) {
8815          if (DAG.isKnownNeverNaN(LHS)) {
8816            // Put the potential NaN in the RHS so that SSE will preserve it.
8817            std::swap(LHS, RHS);
8818          } else if (!DAG.isKnownNeverNaN(RHS))
8819            break;
8820        }
8821        Opcode = X86ISD::FMIN;
8822        break;
8823      case ISD::SETULE:
8824        // This can be a min, but if either operand is a NaN we need it to
8825        // preserve the original LHS.
8826        std::swap(LHS, RHS);
8827      case ISD::SETOLT:
8828      case ISD::SETLT:
8829      case ISD::SETLE:
8830        Opcode = X86ISD::FMIN;
8831        break;
8832
8833      case ISD::SETOGE:
8834        // This can be a max if we can prove that at least one of the operands
8835        // is not a nan.
8836        if (!FiniteOnlyFPMath()) {
8837          if (DAG.isKnownNeverNaN(LHS)) {
8838            // Put the potential NaN in the RHS so that SSE will preserve it.
8839            std::swap(LHS, RHS);
8840          } else if (!DAG.isKnownNeverNaN(RHS))
8841            break;
8842        }
8843        Opcode = X86ISD::FMAX;
8844        break;
8845      case ISD::SETUGT:
8846        // This can be a max if we can prove that at least one of the operands
8847        // is not a nan.
8848        if (!FiniteOnlyFPMath()) {
8849          if (DAG.isKnownNeverNaN(RHS)) {
8850            // Put the potential NaN in the RHS so that SSE will preserve it.
8851            std::swap(LHS, RHS);
8852          } else if (!DAG.isKnownNeverNaN(LHS))
8853            break;
8854        }
8855        Opcode = X86ISD::FMAX;
8856        break;
8857      case ISD::SETUGE:
8858        // This can be a max, but if either operand is a NaN we need it to
8859        // preserve the original LHS.
8860        std::swap(LHS, RHS);
8861      case ISD::SETOGT:
8862      case ISD::SETGT:
8863      case ISD::SETGE:
8864        Opcode = X86ISD::FMAX;
8865        break;
8866      }
8867    // Check for x CC y ? y : x -- a min/max with reversed arms.
8868    } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8869      switch (CC) {
8870      default: break;
8871      case ISD::SETOGE:
8872        // This can be a min if we can prove that at least one of the operands
8873        // is not a nan.
8874        if (!FiniteOnlyFPMath()) {
8875          if (DAG.isKnownNeverNaN(RHS)) {
8876            // Put the potential NaN in the RHS so that SSE will preserve it.
8877            std::swap(LHS, RHS);
8878          } else if (!DAG.isKnownNeverNaN(LHS))
8879            break;
8880        }
8881        Opcode = X86ISD::FMIN;
8882        break;
8883      case ISD::SETUGT:
8884        // This can be a min if we can prove that at least one of the operands
8885        // is not a nan.
8886        if (!FiniteOnlyFPMath()) {
8887          if (DAG.isKnownNeverNaN(LHS)) {
8888            // Put the potential NaN in the RHS so that SSE will preserve it.
8889            std::swap(LHS, RHS);
8890          } else if (!DAG.isKnownNeverNaN(RHS))
8891            break;
8892        }
8893        Opcode = X86ISD::FMIN;
8894        break;
8895      case ISD::SETUGE:
8896        // This can be a min, but if either operand is a NaN we need it to
8897        // preserve the original LHS.
8898        std::swap(LHS, RHS);
8899      case ISD::SETOGT:
8900      case ISD::SETGT:
8901      case ISD::SETGE:
8902        Opcode = X86ISD::FMIN;
8903        break;
8904
8905      case ISD::SETULT:
8906        // This can be a max if we can prove that at least one of the operands
8907        // is not a nan.
8908        if (!FiniteOnlyFPMath()) {
8909          if (DAG.isKnownNeverNaN(LHS)) {
8910            // Put the potential NaN in the RHS so that SSE will preserve it.
8911            std::swap(LHS, RHS);
8912          } else if (!DAG.isKnownNeverNaN(RHS))
8913            break;
8914        }
8915        Opcode = X86ISD::FMAX;
8916        break;
8917      case ISD::SETOLE:
8918        // This can be a max if we can prove that at least one of the operands
8919        // is not a nan.
8920        if (!FiniteOnlyFPMath()) {
8921          if (DAG.isKnownNeverNaN(RHS)) {
8922            // Put the potential NaN in the RHS so that SSE will preserve it.
8923            std::swap(LHS, RHS);
8924          } else if (!DAG.isKnownNeverNaN(LHS))
8925            break;
8926        }
8927        Opcode = X86ISD::FMAX;
8928        break;
8929      case ISD::SETULE:
8930        // This can be a max, but if either operand is a NaN we need it to
8931        // preserve the original LHS.
8932        std::swap(LHS, RHS);
8933      case ISD::SETOLT:
8934      case ISD::SETLT:
8935      case ISD::SETLE:
8936        Opcode = X86ISD::FMAX;
8937        break;
8938      }
8939    }
8940
8941    if (Opcode)
8942      return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8943  }
8944
8945  // If this is a select between two integer constants, try to do some
8946  // optimizations.
8947  if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8948    if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8949      // Don't do this for crazy integer types.
8950      if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8951        // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8952        // so that TrueC (the true value) is larger than FalseC.
8953        bool NeedsCondInvert = false;
8954
8955        if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8956            // Efficiently invertible.
8957            (Cond.getOpcode() == ISD::SETCC ||  // setcc -> invertible.
8958             (Cond.getOpcode() == ISD::XOR &&   // xor(X, C) -> invertible.
8959              isa<ConstantSDNode>(Cond.getOperand(1))))) {
8960          NeedsCondInvert = true;
8961          std::swap(TrueC, FalseC);
8962        }
8963
8964        // Optimize C ? 8 : 0 -> zext(C) << 3.  Likewise for any pow2/0.
8965        if (FalseC->getAPIntValue() == 0 &&
8966            TrueC->getAPIntValue().isPowerOf2()) {
8967          if (NeedsCondInvert) // Invert the condition if needed.
8968            Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8969                               DAG.getConstant(1, Cond.getValueType()));
8970
8971          // Zero extend the condition if needed.
8972          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8973
8974          unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8975          return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8976                             DAG.getConstant(ShAmt, MVT::i8));
8977        }
8978
8979        // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8980        if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8981          if (NeedsCondInvert) // Invert the condition if needed.
8982            Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8983                               DAG.getConstant(1, Cond.getValueType()));
8984
8985          // Zero extend the condition if needed.
8986          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8987                             FalseC->getValueType(0), Cond);
8988          return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8989                             SDValue(FalseC, 0));
8990        }
8991
8992        // Optimize cases that will turn into an LEA instruction.  This requires
8993        // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8994        if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8995          uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8996          if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8997
8998          bool isFastMultiplier = false;
8999          if (Diff < 10) {
9000            switch ((unsigned char)Diff) {
9001              default: break;
9002              case 1:  // result = add base, cond
9003              case 2:  // result = lea base(    , cond*2)
9004              case 3:  // result = lea base(cond, cond*2)
9005              case 4:  // result = lea base(    , cond*4)
9006              case 5:  // result = lea base(cond, cond*4)
9007              case 8:  // result = lea base(    , cond*8)
9008              case 9:  // result = lea base(cond, cond*8)
9009                isFastMultiplier = true;
9010                break;
9011            }
9012          }
9013
9014          if (isFastMultiplier) {
9015            APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9016            if (NeedsCondInvert) // Invert the condition if needed.
9017              Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9018                                 DAG.getConstant(1, Cond.getValueType()));
9019
9020            // Zero extend the condition if needed.
9021            Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9022                               Cond);
9023            // Scale the condition by the difference.
9024            if (Diff != 1)
9025              Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9026                                 DAG.getConstant(Diff, Cond.getValueType()));
9027
9028            // Add the base if non-zero.
9029            if (FalseC->getAPIntValue() != 0)
9030              Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9031                                 SDValue(FalseC, 0));
9032            return Cond;
9033          }
9034        }
9035      }
9036  }
9037
9038  return SDValue();
9039}
9040
9041/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9042static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9043                                  TargetLowering::DAGCombinerInfo &DCI) {
9044  DebugLoc DL = N->getDebugLoc();
9045
9046  // If the flag operand isn't dead, don't touch this CMOV.
9047  if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9048    return SDValue();
9049
9050  // If this is a select between two integer constants, try to do some
9051  // optimizations.  Note that the operands are ordered the opposite of SELECT
9052  // operands.
9053  if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9054    if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9055      // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9056      // larger than FalseC (the false value).
9057      X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9058
9059      if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9060        CC = X86::GetOppositeBranchCondition(CC);
9061        std::swap(TrueC, FalseC);
9062      }
9063
9064      // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3.  Likewise for any pow2/0.
9065      // This is efficient for any integer data type (including i8/i16) and
9066      // shift amount.
9067      if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9068        SDValue Cond = N->getOperand(3);
9069        Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9070                           DAG.getConstant(CC, MVT::i8), Cond);
9071
9072        // Zero extend the condition if needed.
9073        Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9074
9075        unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9076        Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9077                           DAG.getConstant(ShAmt, MVT::i8));
9078        if (N->getNumValues() == 2)  // Dead flag value?
9079          return DCI.CombineTo(N, Cond, SDValue());
9080        return Cond;
9081      }
9082
9083      // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.  This is efficient
9084      // for any integer data type, including i8/i16.
9085      if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9086        SDValue Cond = N->getOperand(3);
9087        Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9088                           DAG.getConstant(CC, MVT::i8), Cond);
9089
9090        // Zero extend the condition if needed.
9091        Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9092                           FalseC->getValueType(0), Cond);
9093        Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9094                           SDValue(FalseC, 0));
9095
9096        if (N->getNumValues() == 2)  // Dead flag value?
9097          return DCI.CombineTo(N, Cond, SDValue());
9098        return Cond;
9099      }
9100
9101      // Optimize cases that will turn into an LEA instruction.  This requires
9102      // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9103      if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9104        uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9105        if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9106
9107        bool isFastMultiplier = false;
9108        if (Diff < 10) {
9109          switch ((unsigned char)Diff) {
9110          default: break;
9111          case 1:  // result = add base, cond
9112          case 2:  // result = lea base(    , cond*2)
9113          case 3:  // result = lea base(cond, cond*2)
9114          case 4:  // result = lea base(    , cond*4)
9115          case 5:  // result = lea base(cond, cond*4)
9116          case 8:  // result = lea base(    , cond*8)
9117          case 9:  // result = lea base(cond, cond*8)
9118            isFastMultiplier = true;
9119            break;
9120          }
9121        }
9122
9123        if (isFastMultiplier) {
9124          APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9125          SDValue Cond = N->getOperand(3);
9126          Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9127                             DAG.getConstant(CC, MVT::i8), Cond);
9128          // Zero extend the condition if needed.
9129          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9130                             Cond);
9131          // Scale the condition by the difference.
9132          if (Diff != 1)
9133            Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9134                               DAG.getConstant(Diff, Cond.getValueType()));
9135
9136          // Add the base if non-zero.
9137          if (FalseC->getAPIntValue() != 0)
9138            Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9139                               SDValue(FalseC, 0));
9140          if (N->getNumValues() == 2)  // Dead flag value?
9141            return DCI.CombineTo(N, Cond, SDValue());
9142          return Cond;
9143        }
9144      }
9145    }
9146  }
9147  return SDValue();
9148}
9149
9150
9151/// PerformMulCombine - Optimize a single multiply with constant into two
9152/// in order to implement it with two cheaper instructions, e.g.
9153/// LEA + SHL, LEA + LEA.
9154static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9155                                 TargetLowering::DAGCombinerInfo &DCI) {
9156  if (DAG.getMachineFunction().
9157      getFunction()->hasFnAttr(Attribute::OptimizeForSize))
9158    return SDValue();
9159
9160  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9161    return SDValue();
9162
9163  EVT VT = N->getValueType(0);
9164  if (VT != MVT::i64)
9165    return SDValue();
9166
9167  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9168  if (!C)
9169    return SDValue();
9170  uint64_t MulAmt = C->getZExtValue();
9171  if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9172    return SDValue();
9173
9174  uint64_t MulAmt1 = 0;
9175  uint64_t MulAmt2 = 0;
9176  if ((MulAmt % 9) == 0) {
9177    MulAmt1 = 9;
9178    MulAmt2 = MulAmt / 9;
9179  } else if ((MulAmt % 5) == 0) {
9180    MulAmt1 = 5;
9181    MulAmt2 = MulAmt / 5;
9182  } else if ((MulAmt % 3) == 0) {
9183    MulAmt1 = 3;
9184    MulAmt2 = MulAmt / 3;
9185  }
9186  if (MulAmt2 &&
9187      (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9188    DebugLoc DL = N->getDebugLoc();
9189
9190    if (isPowerOf2_64(MulAmt2) &&
9191        !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9192      // If second multiplifer is pow2, issue it first. We want the multiply by
9193      // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9194      // is an add.
9195      std::swap(MulAmt1, MulAmt2);
9196
9197    SDValue NewMul;
9198    if (isPowerOf2_64(MulAmt1))
9199      NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9200                           DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9201    else
9202      NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9203                           DAG.getConstant(MulAmt1, VT));
9204
9205    if (isPowerOf2_64(MulAmt2))
9206      NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9207                           DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9208    else
9209      NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9210                           DAG.getConstant(MulAmt2, VT));
9211
9212    // Do not add new nodes to DAG combiner worklist.
9213    DCI.CombineTo(N, NewMul, false);
9214  }
9215  return SDValue();
9216}
9217
9218static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9219  SDValue N0 = N->getOperand(0);
9220  SDValue N1 = N->getOperand(1);
9221  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9222  EVT VT = N0.getValueType();
9223
9224  // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9225  // since the result of setcc_c is all zero's or all ones.
9226  if (N1C && N0.getOpcode() == ISD::AND &&
9227      N0.getOperand(1).getOpcode() == ISD::Constant) {
9228    SDValue N00 = N0.getOperand(0);
9229    if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9230        ((N00.getOpcode() == ISD::ANY_EXTEND ||
9231          N00.getOpcode() == ISD::ZERO_EXTEND) &&
9232         N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9233      APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9234      APInt ShAmt = N1C->getAPIntValue();
9235      Mask = Mask.shl(ShAmt);
9236      if (Mask != 0)
9237        return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9238                           N00, DAG.getConstant(Mask, VT));
9239    }
9240  }
9241
9242  return SDValue();
9243}
9244
9245/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9246///                       when possible.
9247static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9248                                   const X86Subtarget *Subtarget) {
9249  EVT VT = N->getValueType(0);
9250  if (!VT.isVector() && VT.isInteger() &&
9251      N->getOpcode() == ISD::SHL)
9252    return PerformSHLCombine(N, DAG);
9253
9254  // On X86 with SSE2 support, we can transform this to a vector shift if
9255  // all elements are shifted by the same amount.  We can't do this in legalize
9256  // because the a constant vector is typically transformed to a constant pool
9257  // so we have no knowledge of the shift amount.
9258  if (!Subtarget->hasSSE2())
9259    return SDValue();
9260
9261  if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9262    return SDValue();
9263
9264  SDValue ShAmtOp = N->getOperand(1);
9265  EVT EltVT = VT.getVectorElementType();
9266  DebugLoc DL = N->getDebugLoc();
9267  SDValue BaseShAmt = SDValue();
9268  if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9269    unsigned NumElts = VT.getVectorNumElements();
9270    unsigned i = 0;
9271    for (; i != NumElts; ++i) {
9272      SDValue Arg = ShAmtOp.getOperand(i);
9273      if (Arg.getOpcode() == ISD::UNDEF) continue;
9274      BaseShAmt = Arg;
9275      break;
9276    }
9277    for (; i != NumElts; ++i) {
9278      SDValue Arg = ShAmtOp.getOperand(i);
9279      if (Arg.getOpcode() == ISD::UNDEF) continue;
9280      if (Arg != BaseShAmt) {
9281        return SDValue();
9282      }
9283    }
9284  } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9285             cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9286    SDValue InVec = ShAmtOp.getOperand(0);
9287    if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9288      unsigned NumElts = InVec.getValueType().getVectorNumElements();
9289      unsigned i = 0;
9290      for (; i != NumElts; ++i) {
9291        SDValue Arg = InVec.getOperand(i);
9292        if (Arg.getOpcode() == ISD::UNDEF) continue;
9293        BaseShAmt = Arg;
9294        break;
9295      }
9296    } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9297       if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9298         unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9299         if (C->getZExtValue() == SplatIdx)
9300           BaseShAmt = InVec.getOperand(1);
9301       }
9302    }
9303    if (BaseShAmt.getNode() == 0)
9304      BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9305                              DAG.getIntPtrConstant(0));
9306  } else
9307    return SDValue();
9308
9309  // The shift amount is an i32.
9310  if (EltVT.bitsGT(MVT::i32))
9311    BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9312  else if (EltVT.bitsLT(MVT::i32))
9313    BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9314
9315  // The shift amount is identical so we can do a vector shift.
9316  SDValue  ValOp = N->getOperand(0);
9317  switch (N->getOpcode()) {
9318  default:
9319    llvm_unreachable("Unknown shift opcode!");
9320    break;
9321  case ISD::SHL:
9322    if (VT == MVT::v2i64)
9323      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9324                         DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9325                         ValOp, BaseShAmt);
9326    if (VT == MVT::v4i32)
9327      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9328                         DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9329                         ValOp, BaseShAmt);
9330    if (VT == MVT::v8i16)
9331      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9332                         DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9333                         ValOp, BaseShAmt);
9334    break;
9335  case ISD::SRA:
9336    if (VT == MVT::v4i32)
9337      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9338                         DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9339                         ValOp, BaseShAmt);
9340    if (VT == MVT::v8i16)
9341      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9342                         DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9343                         ValOp, BaseShAmt);
9344    break;
9345  case ISD::SRL:
9346    if (VT == MVT::v2i64)
9347      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9348                         DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9349                         ValOp, BaseShAmt);
9350    if (VT == MVT::v4i32)
9351      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9352                         DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9353                         ValOp, BaseShAmt);
9354    if (VT ==  MVT::v8i16)
9355      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9356                         DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9357                         ValOp, BaseShAmt);
9358    break;
9359  }
9360  return SDValue();
9361}
9362
9363static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9364                                const X86Subtarget *Subtarget) {
9365  EVT VT = N->getValueType(0);
9366  if (VT != MVT::i64 || !Subtarget->is64Bit())
9367    return SDValue();
9368
9369  // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9370  SDValue N0 = N->getOperand(0);
9371  SDValue N1 = N->getOperand(1);
9372  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9373    std::swap(N0, N1);
9374  if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9375    return SDValue();
9376
9377  SDValue ShAmt0 = N0.getOperand(1);
9378  if (ShAmt0.getValueType() != MVT::i8)
9379    return SDValue();
9380  SDValue ShAmt1 = N1.getOperand(1);
9381  if (ShAmt1.getValueType() != MVT::i8)
9382    return SDValue();
9383  if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9384    ShAmt0 = ShAmt0.getOperand(0);
9385  if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9386    ShAmt1 = ShAmt1.getOperand(0);
9387
9388  DebugLoc DL = N->getDebugLoc();
9389  unsigned Opc = X86ISD::SHLD;
9390  SDValue Op0 = N0.getOperand(0);
9391  SDValue Op1 = N1.getOperand(0);
9392  if (ShAmt0.getOpcode() == ISD::SUB) {
9393    Opc = X86ISD::SHRD;
9394    std::swap(Op0, Op1);
9395    std::swap(ShAmt0, ShAmt1);
9396  }
9397
9398  if (ShAmt1.getOpcode() == ISD::SUB) {
9399    SDValue Sum = ShAmt1.getOperand(0);
9400    if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9401      if (SumC->getSExtValue() == 64 &&
9402          ShAmt1.getOperand(1) == ShAmt0)
9403        return DAG.getNode(Opc, DL, VT,
9404                           Op0, Op1,
9405                           DAG.getNode(ISD::TRUNCATE, DL,
9406                                       MVT::i8, ShAmt0));
9407    }
9408  } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9409    ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9410    if (ShAmt0C &&
9411        ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9412      return DAG.getNode(Opc, DL, VT,
9413                         N0.getOperand(0), N1.getOperand(0),
9414                         DAG.getNode(ISD::TRUNCATE, DL,
9415                                       MVT::i8, ShAmt0));
9416  }
9417
9418  return SDValue();
9419}
9420
9421/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9422static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9423                                   const X86Subtarget *Subtarget) {
9424  // Turn load->store of MMX types into GPR load/stores.  This avoids clobbering
9425  // the FP state in cases where an emms may be missing.
9426  // A preferable solution to the general problem is to figure out the right
9427  // places to insert EMMS.  This qualifies as a quick hack.
9428
9429  // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9430  StoreSDNode *St = cast<StoreSDNode>(N);
9431  EVT VT = St->getValue().getValueType();
9432  if (VT.getSizeInBits() != 64)
9433    return SDValue();
9434
9435  const Function *F = DAG.getMachineFunction().getFunction();
9436  bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9437  bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9438    && Subtarget->hasSSE2();
9439  if ((VT.isVector() ||
9440       (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9441      isa<LoadSDNode>(St->getValue()) &&
9442      !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9443      St->getChain().hasOneUse() && !St->isVolatile()) {
9444    SDNode* LdVal = St->getValue().getNode();
9445    LoadSDNode *Ld = 0;
9446    int TokenFactorIndex = -1;
9447    SmallVector<SDValue, 8> Ops;
9448    SDNode* ChainVal = St->getChain().getNode();
9449    // Must be a store of a load.  We currently handle two cases:  the load
9450    // is a direct child, and it's under an intervening TokenFactor.  It is
9451    // possible to dig deeper under nested TokenFactors.
9452    if (ChainVal == LdVal)
9453      Ld = cast<LoadSDNode>(St->getChain());
9454    else if (St->getValue().hasOneUse() &&
9455             ChainVal->getOpcode() == ISD::TokenFactor) {
9456      for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9457        if (ChainVal->getOperand(i).getNode() == LdVal) {
9458          TokenFactorIndex = i;
9459          Ld = cast<LoadSDNode>(St->getValue());
9460        } else
9461          Ops.push_back(ChainVal->getOperand(i));
9462      }
9463    }
9464
9465    if (!Ld || !ISD::isNormalLoad(Ld))
9466      return SDValue();
9467
9468    // If this is not the MMX case, i.e. we are just turning i64 load/store
9469    // into f64 load/store, avoid the transformation if there are multiple
9470    // uses of the loaded value.
9471    if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9472      return SDValue();
9473
9474    DebugLoc LdDL = Ld->getDebugLoc();
9475    DebugLoc StDL = N->getDebugLoc();
9476    // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9477    // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9478    // pair instead.
9479    if (Subtarget->is64Bit() || F64IsLegal) {
9480      EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9481      SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9482                                  Ld->getBasePtr(), Ld->getSrcValue(),
9483                                  Ld->getSrcValueOffset(), Ld->isVolatile(),
9484                                  Ld->getAlignment());
9485      SDValue NewChain = NewLd.getValue(1);
9486      if (TokenFactorIndex != -1) {
9487        Ops.push_back(NewChain);
9488        NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9489                               Ops.size());
9490      }
9491      return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9492                          St->getSrcValue(), St->getSrcValueOffset(),
9493                          St->isVolatile(), St->getAlignment());
9494    }
9495
9496    // Otherwise, lower to two pairs of 32-bit loads / stores.
9497    SDValue LoAddr = Ld->getBasePtr();
9498    SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9499                                 DAG.getConstant(4, MVT::i32));
9500
9501    SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9502                               Ld->getSrcValue(), Ld->getSrcValueOffset(),
9503                               Ld->isVolatile(), Ld->getAlignment());
9504    SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9505                               Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9506                               Ld->isVolatile(),
9507                               MinAlign(Ld->getAlignment(), 4));
9508
9509    SDValue NewChain = LoLd.getValue(1);
9510    if (TokenFactorIndex != -1) {
9511      Ops.push_back(LoLd);
9512      Ops.push_back(HiLd);
9513      NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9514                             Ops.size());
9515    }
9516
9517    LoAddr = St->getBasePtr();
9518    HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9519                         DAG.getConstant(4, MVT::i32));
9520
9521    SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9522                                St->getSrcValue(), St->getSrcValueOffset(),
9523                                St->isVolatile(), St->getAlignment());
9524    SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9525                                St->getSrcValue(),
9526                                St->getSrcValueOffset() + 4,
9527                                St->isVolatile(),
9528                                MinAlign(St->getAlignment(), 4));
9529    return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9530  }
9531  return SDValue();
9532}
9533
9534/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9535/// X86ISD::FXOR nodes.
9536static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9537  assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9538  // F[X]OR(0.0, x) -> x
9539  // F[X]OR(x, 0.0) -> x
9540  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9541    if (C->getValueAPF().isPosZero())
9542      return N->getOperand(1);
9543  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9544    if (C->getValueAPF().isPosZero())
9545      return N->getOperand(0);
9546  return SDValue();
9547}
9548
9549/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9550static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9551  // FAND(0.0, x) -> 0.0
9552  // FAND(x, 0.0) -> 0.0
9553  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9554    if (C->getValueAPF().isPosZero())
9555      return N->getOperand(0);
9556  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9557    if (C->getValueAPF().isPosZero())
9558      return N->getOperand(1);
9559  return SDValue();
9560}
9561
9562static SDValue PerformBTCombine(SDNode *N,
9563                                SelectionDAG &DAG,
9564                                TargetLowering::DAGCombinerInfo &DCI) {
9565  // BT ignores high bits in the bit index operand.
9566  SDValue Op1 = N->getOperand(1);
9567  if (Op1.hasOneUse()) {
9568    unsigned BitWidth = Op1.getValueSizeInBits();
9569    APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9570    APInt KnownZero, KnownOne;
9571    TargetLowering::TargetLoweringOpt TLO(DAG);
9572    TargetLowering &TLI = DAG.getTargetLoweringInfo();
9573    if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9574        TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9575      DCI.CommitTargetLoweringOpt(TLO);
9576  }
9577  return SDValue();
9578}
9579
9580static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9581  SDValue Op = N->getOperand(0);
9582  if (Op.getOpcode() == ISD::BIT_CONVERT)
9583    Op = Op.getOperand(0);
9584  EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9585  if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9586      VT.getVectorElementType().getSizeInBits() ==
9587      OpVT.getVectorElementType().getSizeInBits()) {
9588    return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9589  }
9590  return SDValue();
9591}
9592
9593// On X86 and X86-64, atomic operations are lowered to locked instructions.
9594// Locked instructions, in turn, have implicit fence semantics (all memory
9595// operations are flushed before issuing the locked instruction, and the
9596// are not buffered), so we can fold away the common pattern of
9597// fence-atomic-fence.
9598static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9599  SDValue atomic = N->getOperand(0);
9600  switch (atomic.getOpcode()) {
9601    case ISD::ATOMIC_CMP_SWAP:
9602    case ISD::ATOMIC_SWAP:
9603    case ISD::ATOMIC_LOAD_ADD:
9604    case ISD::ATOMIC_LOAD_SUB:
9605    case ISD::ATOMIC_LOAD_AND:
9606    case ISD::ATOMIC_LOAD_OR:
9607    case ISD::ATOMIC_LOAD_XOR:
9608    case ISD::ATOMIC_LOAD_NAND:
9609    case ISD::ATOMIC_LOAD_MIN:
9610    case ISD::ATOMIC_LOAD_MAX:
9611    case ISD::ATOMIC_LOAD_UMIN:
9612    case ISD::ATOMIC_LOAD_UMAX:
9613      break;
9614    default:
9615      return SDValue();
9616  }
9617
9618  SDValue fence = atomic.getOperand(0);
9619  if (fence.getOpcode() != ISD::MEMBARRIER)
9620    return SDValue();
9621
9622  switch (atomic.getOpcode()) {
9623    case ISD::ATOMIC_CMP_SWAP:
9624      return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9625                                    atomic.getOperand(1), atomic.getOperand(2),
9626                                    atomic.getOperand(3));
9627    case ISD::ATOMIC_SWAP:
9628    case ISD::ATOMIC_LOAD_ADD:
9629    case ISD::ATOMIC_LOAD_SUB:
9630    case ISD::ATOMIC_LOAD_AND:
9631    case ISD::ATOMIC_LOAD_OR:
9632    case ISD::ATOMIC_LOAD_XOR:
9633    case ISD::ATOMIC_LOAD_NAND:
9634    case ISD::ATOMIC_LOAD_MIN:
9635    case ISD::ATOMIC_LOAD_MAX:
9636    case ISD::ATOMIC_LOAD_UMIN:
9637    case ISD::ATOMIC_LOAD_UMAX:
9638      return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9639                                    atomic.getOperand(1), atomic.getOperand(2));
9640    default:
9641      return SDValue();
9642  }
9643}
9644
9645static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9646  // (i32 zext (and (i8  x86isd::setcc_carry), 1)) ->
9647  //           (and (i32 x86isd::setcc_carry), 1)
9648  // This eliminates the zext. This transformation is necessary because
9649  // ISD::SETCC is always legalized to i8.
9650  DebugLoc dl = N->getDebugLoc();
9651  SDValue N0 = N->getOperand(0);
9652  EVT VT = N->getValueType(0);
9653  if (N0.getOpcode() == ISD::AND &&
9654      N0.hasOneUse() &&
9655      N0.getOperand(0).hasOneUse()) {
9656    SDValue N00 = N0.getOperand(0);
9657    if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9658      return SDValue();
9659    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9660    if (!C || C->getZExtValue() != 1)
9661      return SDValue();
9662    return DAG.getNode(ISD::AND, dl, VT,
9663                       DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9664                                   N00.getOperand(0), N00.getOperand(1)),
9665                       DAG.getConstant(1, VT));
9666  }
9667
9668  return SDValue();
9669}
9670
9671SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9672                                             DAGCombinerInfo &DCI) const {
9673  SelectionDAG &DAG = DCI.DAG;
9674  switch (N->getOpcode()) {
9675  default: break;
9676  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9677  case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
9678  case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
9679  case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
9680  case ISD::SHL:
9681  case ISD::SRA:
9682  case ISD::SRL:            return PerformShiftCombine(N, DAG, Subtarget);
9683  case ISD::OR:             return PerformOrCombine(N, DAG, Subtarget);
9684  case ISD::STORE:          return PerformSTORECombine(N, DAG, Subtarget);
9685  case X86ISD::FXOR:
9686  case X86ISD::FOR:         return PerformFORCombine(N, DAG);
9687  case X86ISD::FAND:        return PerformFANDCombine(N, DAG);
9688  case X86ISD::BT:          return PerformBTCombine(N, DAG, DCI);
9689  case X86ISD::VZEXT_MOVL:  return PerformVZEXT_MOVLCombine(N, DAG);
9690  case ISD::MEMBARRIER:     return PerformMEMBARRIERCombine(N, DAG);
9691  case ISD::ZERO_EXTEND:    return PerformZExtCombine(N, DAG);
9692  }
9693
9694  return SDValue();
9695}
9696
9697//===----------------------------------------------------------------------===//
9698//                           X86 Inline Assembly Support
9699//===----------------------------------------------------------------------===//
9700
9701static bool LowerToBSwap(CallInst *CI) {
9702  // FIXME: this should verify that we are targetting a 486 or better.  If not,
9703  // we will turn this bswap into something that will be lowered to logical ops
9704  // instead of emitting the bswap asm.  For now, we don't support 486 or lower
9705  // so don't worry about this.
9706
9707  // Verify this is a simple bswap.
9708  if (CI->getNumOperands() != 2 ||
9709      CI->getType() != CI->getOperand(1)->getType() ||
9710      !CI->getType()->isInteger())
9711    return false;
9712
9713  const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9714  if (!Ty || Ty->getBitWidth() % 16 != 0)
9715    return false;
9716
9717  // Okay, we can do this xform, do so now.
9718  const Type *Tys[] = { Ty };
9719  Module *M = CI->getParent()->getParent()->getParent();
9720  Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9721
9722  Value *Op = CI->getOperand(1);
9723  Op = CallInst::Create(Int, Op, CI->getName(), CI);
9724
9725  CI->replaceAllUsesWith(Op);
9726  CI->eraseFromParent();
9727  return true;
9728}
9729
9730bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9731  InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9732  std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9733
9734  std::string AsmStr = IA->getAsmString();
9735
9736  // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9737  SmallVector<StringRef, 4> AsmPieces;
9738  SplitString(AsmStr, AsmPieces, "\n");  // ; as separator?
9739
9740  switch (AsmPieces.size()) {
9741  default: return false;
9742  case 1:
9743    AsmStr = AsmPieces[0];
9744    AsmPieces.clear();
9745    SplitString(AsmStr, AsmPieces, " \t");  // Split with whitespace.
9746
9747    // bswap $0
9748    if (AsmPieces.size() == 2 &&
9749        (AsmPieces[0] == "bswap" ||
9750         AsmPieces[0] == "bswapq" ||
9751         AsmPieces[0] == "bswapl") &&
9752        (AsmPieces[1] == "$0" ||
9753         AsmPieces[1] == "${0:q}")) {
9754      // No need to check constraints, nothing other than the equivalent of
9755      // "=r,0" would be valid here.
9756      return LowerToBSwap(CI);
9757    }
9758    // rorw $$8, ${0:w}  -->  llvm.bswap.i16
9759    if (CI->getType()->isInteger(16) &&
9760        AsmPieces.size() == 3 &&
9761        AsmPieces[0] == "rorw" &&
9762        AsmPieces[1] == "$$8," &&
9763        AsmPieces[2] == "${0:w}" &&
9764        IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9765      return LowerToBSwap(CI);
9766    }
9767    break;
9768  case 3:
9769    if (CI->getType()->isInteger(64) &&
9770        Constraints.size() >= 2 &&
9771        Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9772        Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9773      // bswap %eax / bswap %edx / xchgl %eax, %edx  -> llvm.bswap.i64
9774      SmallVector<StringRef, 4> Words;
9775      SplitString(AsmPieces[0], Words, " \t");
9776      if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9777        Words.clear();
9778        SplitString(AsmPieces[1], Words, " \t");
9779        if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9780          Words.clear();
9781          SplitString(AsmPieces[2], Words, " \t,");
9782          if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9783              Words[2] == "%edx") {
9784            return LowerToBSwap(CI);
9785          }
9786        }
9787      }
9788    }
9789    break;
9790  }
9791  return false;
9792}
9793
9794
9795
9796/// getConstraintType - Given a constraint letter, return the type of
9797/// constraint it is for this target.
9798X86TargetLowering::ConstraintType
9799X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9800  if (Constraint.size() == 1) {
9801    switch (Constraint[0]) {
9802    case 'A':
9803      return C_Register;
9804    case 'f':
9805    case 'r':
9806    case 'R':
9807    case 'l':
9808    case 'q':
9809    case 'Q':
9810    case 'x':
9811    case 'y':
9812    case 'Y':
9813      return C_RegisterClass;
9814    case 'e':
9815    case 'Z':
9816      return C_Other;
9817    default:
9818      break;
9819    }
9820  }
9821  return TargetLowering::getConstraintType(Constraint);
9822}
9823
9824/// LowerXConstraint - try to replace an X constraint, which matches anything,
9825/// with another that has more specific requirements based on the type of the
9826/// corresponding operand.
9827const char *X86TargetLowering::
9828LowerXConstraint(EVT ConstraintVT) const {
9829  // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9830  // 'f' like normal targets.
9831  if (ConstraintVT.isFloatingPoint()) {
9832    if (Subtarget->hasSSE2())
9833      return "Y";
9834    if (Subtarget->hasSSE1())
9835      return "x";
9836  }
9837
9838  return TargetLowering::LowerXConstraint(ConstraintVT);
9839}
9840
9841/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9842/// vector.  If it is invalid, don't add anything to Ops.
9843void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9844                                                     char Constraint,
9845                                                     bool hasMemory,
9846                                                     std::vector<SDValue>&Ops,
9847                                                     SelectionDAG &DAG) const {
9848  SDValue Result(0, 0);
9849
9850  switch (Constraint) {
9851  default: break;
9852  case 'I':
9853    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9854      if (C->getZExtValue() <= 31) {
9855        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9856        break;
9857      }
9858    }
9859    return;
9860  case 'J':
9861    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9862      if (C->getZExtValue() <= 63) {
9863        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9864        break;
9865      }
9866    }
9867    return;
9868  case 'K':
9869    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9870      if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9871        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9872        break;
9873      }
9874    }
9875    return;
9876  case 'N':
9877    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9878      if (C->getZExtValue() <= 255) {
9879        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9880        break;
9881      }
9882    }
9883    return;
9884  case 'e': {
9885    // 32-bit signed value
9886    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9887      const ConstantInt *CI = C->getConstantIntValue();
9888      if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9889                                  C->getSExtValue())) {
9890        // Widen to 64 bits here to get it sign extended.
9891        Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9892        break;
9893      }
9894    // FIXME gcc accepts some relocatable values here too, but only in certain
9895    // memory models; it's complicated.
9896    }
9897    return;
9898  }
9899  case 'Z': {
9900    // 32-bit unsigned value
9901    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9902      const ConstantInt *CI = C->getConstantIntValue();
9903      if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9904                                  C->getZExtValue())) {
9905        Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9906        break;
9907      }
9908    }
9909    // FIXME gcc accepts some relocatable values here too, but only in certain
9910    // memory models; it's complicated.
9911    return;
9912  }
9913  case 'i': {
9914    // Literal immediates are always ok.
9915    if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9916      // Widen to 64 bits here to get it sign extended.
9917      Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9918      break;
9919    }
9920
9921    // If we are in non-pic codegen mode, we allow the address of a global (with
9922    // an optional displacement) to be used with 'i'.
9923    GlobalAddressSDNode *GA = 0;
9924    int64_t Offset = 0;
9925
9926    // Match either (GA), (GA+C), (GA+C1+C2), etc.
9927    while (1) {
9928      if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9929        Offset += GA->getOffset();
9930        break;
9931      } else if (Op.getOpcode() == ISD::ADD) {
9932        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9933          Offset += C->getZExtValue();
9934          Op = Op.getOperand(0);
9935          continue;
9936        }
9937      } else if (Op.getOpcode() == ISD::SUB) {
9938        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9939          Offset += -C->getZExtValue();
9940          Op = Op.getOperand(0);
9941          continue;
9942        }
9943      }
9944
9945      // Otherwise, this isn't something we can handle, reject it.
9946      return;
9947    }
9948
9949    GlobalValue *GV = GA->getGlobal();
9950    // If we require an extra load to get this address, as in PIC mode, we
9951    // can't accept it.
9952    if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9953                                                        getTargetMachine())))
9954      return;
9955
9956    if (hasMemory)
9957      Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9958    else
9959      Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9960    Result = Op;
9961    break;
9962  }
9963  }
9964
9965  if (Result.getNode()) {
9966    Ops.push_back(Result);
9967    return;
9968  }
9969  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9970                                                      Ops, DAG);
9971}
9972
9973std::vector<unsigned> X86TargetLowering::
9974getRegClassForInlineAsmConstraint(const std::string &Constraint,
9975                                  EVT VT) const {
9976  if (Constraint.size() == 1) {
9977    // FIXME: not handling fp-stack yet!
9978    switch (Constraint[0]) {      // GCC X86 Constraint Letters
9979    default: break;  // Unknown constraint letter
9980    case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9981      if (Subtarget->is64Bit()) {
9982        if (VT == MVT::i32)
9983          return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9984                                       X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9985                                       X86::R10D,X86::R11D,X86::R12D,
9986                                       X86::R13D,X86::R14D,X86::R15D,
9987                                       X86::EBP, X86::ESP, 0);
9988        else if (VT == MVT::i16)
9989          return make_vector<unsigned>(X86::AX,  X86::DX,  X86::CX, X86::BX,
9990                                       X86::SI,  X86::DI,  X86::R8W,X86::R9W,
9991                                       X86::R10W,X86::R11W,X86::R12W,
9992                                       X86::R13W,X86::R14W,X86::R15W,
9993                                       X86::BP,  X86::SP, 0);
9994        else if (VT == MVT::i8)
9995          return make_vector<unsigned>(X86::AL,  X86::DL,  X86::CL, X86::BL,
9996                                       X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9997                                       X86::R10B,X86::R11B,X86::R12B,
9998                                       X86::R13B,X86::R14B,X86::R15B,
9999                                       X86::BPL, X86::SPL, 0);
10000
10001        else if (VT == MVT::i64)
10002          return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10003                                       X86::RSI, X86::RDI, X86::R8,  X86::R9,
10004                                       X86::R10, X86::R11, X86::R12,
10005                                       X86::R13, X86::R14, X86::R15,
10006                                       X86::RBP, X86::RSP, 0);
10007
10008        break;
10009      }
10010      // 32-bit fallthrough
10011    case 'Q':   // Q_REGS
10012      if (VT == MVT::i32)
10013        return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10014      else if (VT == MVT::i16)
10015        return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10016      else if (VT == MVT::i8)
10017        return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10018      else if (VT == MVT::i64)
10019        return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10020      break;
10021    }
10022  }
10023
10024  return std::vector<unsigned>();
10025}
10026
10027std::pair<unsigned, const TargetRegisterClass*>
10028X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10029                                                EVT VT) const {
10030  // First, see if this is a constraint that directly corresponds to an LLVM
10031  // register class.
10032  if (Constraint.size() == 1) {
10033    // GCC Constraint Letters
10034    switch (Constraint[0]) {
10035    default: break;
10036    case 'r':   // GENERAL_REGS
10037    case 'l':   // INDEX_REGS
10038      if (VT == MVT::i8)
10039        return std::make_pair(0U, X86::GR8RegisterClass);
10040      if (VT == MVT::i16)
10041        return std::make_pair(0U, X86::GR16RegisterClass);
10042      if (VT == MVT::i32 || !Subtarget->is64Bit())
10043        return std::make_pair(0U, X86::GR32RegisterClass);
10044      return std::make_pair(0U, X86::GR64RegisterClass);
10045    case 'R':   // LEGACY_REGS
10046      if (VT == MVT::i8)
10047        return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10048      if (VT == MVT::i16)
10049        return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10050      if (VT == MVT::i32 || !Subtarget->is64Bit())
10051        return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10052      return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10053    case 'f':  // FP Stack registers.
10054      // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10055      // value to the correct fpstack register class.
10056      if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10057        return std::make_pair(0U, X86::RFP32RegisterClass);
10058      if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10059        return std::make_pair(0U, X86::RFP64RegisterClass);
10060      return std::make_pair(0U, X86::RFP80RegisterClass);
10061    case 'y':   // MMX_REGS if MMX allowed.
10062      if (!Subtarget->hasMMX()) break;
10063      return std::make_pair(0U, X86::VR64RegisterClass);
10064    case 'Y':   // SSE_REGS if SSE2 allowed
10065      if (!Subtarget->hasSSE2()) break;
10066      // FALL THROUGH.
10067    case 'x':   // SSE_REGS if SSE1 allowed
10068      if (!Subtarget->hasSSE1()) break;
10069
10070      switch (VT.getSimpleVT().SimpleTy) {
10071      default: break;
10072      // Scalar SSE types.
10073      case MVT::f32:
10074      case MVT::i32:
10075        return std::make_pair(0U, X86::FR32RegisterClass);
10076      case MVT::f64:
10077      case MVT::i64:
10078        return std::make_pair(0U, X86::FR64RegisterClass);
10079      // Vector types.
10080      case MVT::v16i8:
10081      case MVT::v8i16:
10082      case MVT::v4i32:
10083      case MVT::v2i64:
10084      case MVT::v4f32:
10085      case MVT::v2f64:
10086        return std::make_pair(0U, X86::VR128RegisterClass);
10087      }
10088      break;
10089    }
10090  }
10091
10092  // Use the default implementation in TargetLowering to convert the register
10093  // constraint into a member of a register class.
10094  std::pair<unsigned, const TargetRegisterClass*> Res;
10095  Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10096
10097  // Not found as a standard register?
10098  if (Res.second == 0) {
10099    // Map st(0) -> st(7) -> ST0
10100    if (Constraint.size() == 7 && Constraint[0] == '{' &&
10101        tolower(Constraint[1]) == 's' &&
10102        tolower(Constraint[2]) == 't' &&
10103        Constraint[3] == '(' &&
10104        (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10105        Constraint[5] == ')' &&
10106        Constraint[6] == '}') {
10107
10108      Res.first = X86::ST0+Constraint[4]-'0';
10109      Res.second = X86::RFP80RegisterClass;
10110      return Res;
10111    }
10112
10113    // GCC allows "st(0)" to be called just plain "st".
10114    if (StringRef("{st}").equals_lower(Constraint)) {
10115      Res.first = X86::ST0;
10116      Res.second = X86::RFP80RegisterClass;
10117      return Res;
10118    }
10119
10120    // flags -> EFLAGS
10121    if (StringRef("{flags}").equals_lower(Constraint)) {
10122      Res.first = X86::EFLAGS;
10123      Res.second = X86::CCRRegisterClass;
10124      return Res;
10125    }
10126
10127    // 'A' means EAX + EDX.
10128    if (Constraint == "A") {
10129      Res.first = X86::EAX;
10130      Res.second = X86::GR32_ADRegisterClass;
10131      return Res;
10132    }
10133    return Res;
10134  }
10135
10136  // Otherwise, check to see if this is a register class of the wrong value
10137  // type.  For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10138  // turn into {ax},{dx}.
10139  if (Res.second->hasType(VT))
10140    return Res;   // Correct type already, nothing to do.
10141
10142  // All of the single-register GCC register classes map their values onto
10143  // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp".  If we
10144  // really want an 8-bit or 32-bit register, map to the appropriate register
10145  // class and return the appropriate register.
10146  if (Res.second == X86::GR16RegisterClass) {
10147    if (VT == MVT::i8) {
10148      unsigned DestReg = 0;
10149      switch (Res.first) {
10150      default: break;
10151      case X86::AX: DestReg = X86::AL; break;
10152      case X86::DX: DestReg = X86::DL; break;
10153      case X86::CX: DestReg = X86::CL; break;
10154      case X86::BX: DestReg = X86::BL; break;
10155      }
10156      if (DestReg) {
10157        Res.first = DestReg;
10158        Res.second = X86::GR8RegisterClass;
10159      }
10160    } else if (VT == MVT::i32) {
10161      unsigned DestReg = 0;
10162      switch (Res.first) {
10163      default: break;
10164      case X86::AX: DestReg = X86::EAX; break;
10165      case X86::DX: DestReg = X86::EDX; break;
10166      case X86::CX: DestReg = X86::ECX; break;
10167      case X86::BX: DestReg = X86::EBX; break;
10168      case X86::SI: DestReg = X86::ESI; break;
10169      case X86::DI: DestReg = X86::EDI; break;
10170      case X86::BP: DestReg = X86::EBP; break;
10171      case X86::SP: DestReg = X86::ESP; break;
10172      }
10173      if (DestReg) {
10174        Res.first = DestReg;
10175        Res.second = X86::GR32RegisterClass;
10176      }
10177    } else if (VT == MVT::i64) {
10178      unsigned DestReg = 0;
10179      switch (Res.first) {
10180      default: break;
10181      case X86::AX: DestReg = X86::RAX; break;
10182      case X86::DX: DestReg = X86::RDX; break;
10183      case X86::CX: DestReg = X86::RCX; break;
10184      case X86::BX: DestReg = X86::RBX; break;
10185      case X86::SI: DestReg = X86::RSI; break;
10186      case X86::DI: DestReg = X86::RDI; break;
10187      case X86::BP: DestReg = X86::RBP; break;
10188      case X86::SP: DestReg = X86::RSP; break;
10189      }
10190      if (DestReg) {
10191        Res.first = DestReg;
10192        Res.second = X86::GR64RegisterClass;
10193      }
10194    }
10195  } else if (Res.second == X86::FR32RegisterClass ||
10196             Res.second == X86::FR64RegisterClass ||
10197             Res.second == X86::VR128RegisterClass) {
10198    // Handle references to XMM physical registers that got mapped into the
10199    // wrong class.  This can happen with constraints like {xmm0} where the
10200    // target independent register mapper will just pick the first match it can
10201    // find, ignoring the required type.
10202    if (VT == MVT::f32)
10203      Res.second = X86::FR32RegisterClass;
10204    else if (VT == MVT::f64)
10205      Res.second = X86::FR64RegisterClass;
10206    else if (X86::VR128RegisterClass->hasType(VT))
10207      Res.second = X86::VR128RegisterClass;
10208  }
10209
10210  return Res;
10211}
10212
10213//===----------------------------------------------------------------------===//
10214//                           X86 Widen vector type
10215//===----------------------------------------------------------------------===//
10216
10217/// getWidenVectorType: given a vector type, returns the type to widen
10218/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10219/// If there is no vector type that we want to widen to, returns MVT::Other
10220/// When and where to widen is target dependent based on the cost of
10221/// scalarizing vs using the wider vector type.
10222
10223EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10224  assert(VT.isVector());
10225  if (isTypeLegal(VT))
10226    return VT;
10227
10228  // TODO: In computeRegisterProperty, we can compute the list of legal vector
10229  //       type based on element type.  This would speed up our search (though
10230  //       it may not be worth it since the size of the list is relatively
10231  //       small).
10232  EVT EltVT = VT.getVectorElementType();
10233  unsigned NElts = VT.getVectorNumElements();
10234
10235  // On X86, it make sense to widen any vector wider than 1
10236  if (NElts <= 1)
10237    return MVT::Other;
10238
10239  for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10240       nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10241    EVT SVT = (MVT::SimpleValueType)nVT;
10242
10243    if (isTypeLegal(SVT) &&
10244        SVT.getVectorElementType() == EltVT &&
10245        SVT.getVectorNumElements() > NElts)
10246      return SVT;
10247  }
10248  return MVT::Other;
10249}
10250