X86ISelLowering.cpp revision c76d23f2e2550c60aaa26ec23711aecebea7f533
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Forward declarations. 61static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 65 66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 67 68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) { 69 if (is64Bit) return new X8664_MachoTargetObjectFile(); 70 return new TargetLoweringObjectFileMachO(); 71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){ 72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM); 73 return new X8632_ELFTargetObjectFile(TM); 74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) { 75 return new TargetLoweringObjectFileCOFF(); 76 } 77 llvm_unreachable("unknown subtarget type"); 78} 79 80X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 81 : TargetLowering(TM, createTLOF(TM)) { 82 Subtarget = &TM.getSubtarget<X86Subtarget>(); 83 X86ScalarSSEf64 = Subtarget->hasSSE2(); 84 X86ScalarSSEf32 = Subtarget->hasSSE1(); 85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 86 87 RegInfo = TM.getRegisterInfo(); 88 TD = getTargetData(); 89 90 // Set up the TargetLowering object. 91 92 // X86 is weird, it always uses i8 for shift amounts and setcc results. 93 setShiftAmountType(MVT::i8); 94 setBooleanContents(ZeroOrOneBooleanContent); 95 setSchedulingPreference(Sched::RegPressure); 96 setStackPointerRegisterToSaveRestore(X86StackPtr); 97 98 if (Subtarget->isTargetDarwin()) { 99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 100 setUseUnderscoreSetJmp(false); 101 setUseUnderscoreLongJmp(false); 102 } else if (Subtarget->isTargetMingw()) { 103 // MS runtime is weird: it exports _setjmp, but longjmp! 104 setUseUnderscoreSetJmp(true); 105 setUseUnderscoreLongJmp(false); 106 } else { 107 setUseUnderscoreSetJmp(true); 108 setUseUnderscoreLongJmp(true); 109 } 110 111 // Set up the register classes. 112 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 113 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 114 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 115 if (Subtarget->is64Bit()) 116 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 117 118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 119 120 // We don't accept any truncstore of integer registers. 121 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 122 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 124 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 126 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 127 128 // SETOEQ and SETUNE require checking two conditions. 129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 135 136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 137 // operation. 138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 141 142 if (Subtarget->is64Bit()) { 143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 145 } else if (!UseSoftFloat) { 146 // We have an algorithm for SSE2->double, and we turn this into a 147 // 64-bit FILD followed by conditional FADD for other targets. 148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 149 // We have an algorithm for SSE2, and we turn this into a 64-bit 150 // FILD for other targets. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 152 } 153 154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 155 // this operation. 156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 158 159 if (!UseSoftFloat) { 160 // SSE has no i16 to fp conversion, only i32 161 if (X86ScalarSSEf32) { 162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 163 // f32 and f64 cases are Legal, f80 case is not 164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 165 } else { 166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 168 } 169 } else { 170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 172 } 173 174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 175 // are Legal, f80 is custom lowered. 176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 178 179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 180 // this operation. 181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 183 184 if (X86ScalarSSEf32) { 185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 186 // f32 and f64 cases are Legal, f80 case is not 187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 188 } else { 189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 191 } 192 193 // Handle FP_TO_UINT by promoting the destination to a larger signed 194 // conversion. 195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 198 199 if (Subtarget->is64Bit()) { 200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 202 } else if (!UseSoftFloat) { 203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 204 // Expand FP_TO_UINT into a select. 205 // FIXME: We would like to use a Custom expander here eventually to do 206 // the optimal thing for SSE vs. the default expansion in the legalizer. 207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 208 else 209 // With SSE3 we can use fisttpll to convert to a signed i64; without 210 // SSE, we're stuck with a fistpll. 211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 212 } 213 214 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 215 if (!X86ScalarSSEf64) { 216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 218 if (Subtarget->is64Bit()) { 219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand); 220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal. 221 if (Subtarget->hasMMX() && !DisableMMX) 222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom); 223 else 224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand); 225 } 226 } 227 228 // Scalar integer divide and remainder are lowered to use operations that 229 // produce two results, to match the available instructions. This exposes 230 // the two-result form to trivial CSE, which is able to combine x/y and x%y 231 // into a single instruction. 232 // 233 // Scalar integer multiply-high is also lowered to use two-result 234 // operations, to match the available instructions. However, plain multiply 235 // (low) operations are left as Legal, as there are single-result 236 // instructions for this in x86. Using the two-result multiply instructions 237 // when both high and low results are needed must be arranged by dagcombine. 238 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 239 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 240 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 241 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 242 setOperationAction(ISD::SREM , MVT::i8 , Expand); 243 setOperationAction(ISD::UREM , MVT::i8 , Expand); 244 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 248 setOperationAction(ISD::SREM , MVT::i16 , Expand); 249 setOperationAction(ISD::UREM , MVT::i16 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 254 setOperationAction(ISD::SREM , MVT::i32 , Expand); 255 setOperationAction(ISD::UREM , MVT::i32 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 260 setOperationAction(ISD::SREM , MVT::i64 , Expand); 261 setOperationAction(ISD::UREM , MVT::i64 , Expand); 262 263 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 264 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 265 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 267 if (Subtarget->is64Bit()) 268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 273 setOperationAction(ISD::FREM , MVT::f32 , Expand); 274 setOperationAction(ISD::FREM , MVT::f64 , Expand); 275 setOperationAction(ISD::FREM , MVT::f80 , Expand); 276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 277 278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 291 } 292 293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 295 296 // These should be promoted to a larger select which is supported. 297 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 298 // X86 wants to expand cmov itself. 299 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 300 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 301 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 302 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 303 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 304 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 305 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 306 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 307 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 308 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 309 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 310 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 313 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 314 } 315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 316 317 // Darwin ABI issue. 318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 322 if (Subtarget->is64Bit()) 323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 326 if (Subtarget->is64Bit()) { 327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 332 } 333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 341 } 342 343 if (Subtarget->hasSSE1()) 344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 345 346 // We may not have a libcall for MEMBARRIER so we should lower this. 347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 348 349 // On X86 and X86-64, atomic operations are lowered to locked instructions. 350 // Locked instructions, in turn, have implicit fence semantics (all memory 351 // operations are flushed before issuing the locked instruction, and they 352 // are not buffered), so we can fold away the common pattern of 353 // fence-atomic-fence. 354 setShouldFoldAtomicFences(true); 355 356 // Expand certain atomics 357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 361 362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 366 367 if (!Subtarget->is64Bit()) { 368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 375 } 376 377 // FIXME - use subtarget debug flags 378 if (!Subtarget->isTargetDarwin() && 379 !Subtarget->isTargetELF() && 380 !Subtarget->isTargetCygMing()) { 381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 382 } 383 384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 388 if (Subtarget->is64Bit()) { 389 setExceptionPointerRegister(X86::RAX); 390 setExceptionSelectorRegister(X86::RDX); 391 } else { 392 setExceptionPointerRegister(X86::EAX); 393 setExceptionSelectorRegister(X86::EDX); 394 } 395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 397 398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 399 400 setOperationAction(ISD::TRAP, MVT::Other, Legal); 401 402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 403 setOperationAction(ISD::VASTART , MVT::Other, Custom); 404 setOperationAction(ISD::VAEND , MVT::Other, Expand); 405 if (Subtarget->is64Bit()) { 406 setOperationAction(ISD::VAARG , MVT::Other, Custom); 407 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 408 } else { 409 setOperationAction(ISD::VAARG , MVT::Other, Expand); 410 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 411 } 412 413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 415 if (Subtarget->is64Bit()) 416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 417 if (Subtarget->isTargetCygMing()) 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 419 else 420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 421 422 if (!UseSoftFloat && X86ScalarSSEf64) { 423 // f32 and f64 use SSE. 424 // Set up the FP register classes. 425 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 426 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 427 428 // Use ANDPD to simulate FABS. 429 setOperationAction(ISD::FABS , MVT::f64, Custom); 430 setOperationAction(ISD::FABS , MVT::f32, Custom); 431 432 // Use XORP to simulate FNEG. 433 setOperationAction(ISD::FNEG , MVT::f64, Custom); 434 setOperationAction(ISD::FNEG , MVT::f32, Custom); 435 436 // Use ANDPD and ORPD to simulate FCOPYSIGN. 437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 439 440 // We don't support sin/cos/fmod 441 setOperationAction(ISD::FSIN , MVT::f64, Expand); 442 setOperationAction(ISD::FCOS , MVT::f64, Expand); 443 setOperationAction(ISD::FSIN , MVT::f32, Expand); 444 setOperationAction(ISD::FCOS , MVT::f32, Expand); 445 446 // Expand FP immediates into loads from the stack, except for the special 447 // cases we handle. 448 addLegalFPImmediate(APFloat(+0.0)); // xorpd 449 addLegalFPImmediate(APFloat(+0.0f)); // xorps 450 } else if (!UseSoftFloat && X86ScalarSSEf32) { 451 // Use SSE for f32, x87 for f64. 452 // Set up the FP register classes. 453 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 455 456 // Use ANDPS to simulate FABS. 457 setOperationAction(ISD::FABS , MVT::f32, Custom); 458 459 // Use XORP to simulate FNEG. 460 setOperationAction(ISD::FNEG , MVT::f32, Custom); 461 462 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 463 464 // Use ANDPS and ORPS to simulate FCOPYSIGN. 465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 467 468 // We don't support sin/cos/fmod 469 setOperationAction(ISD::FSIN , MVT::f32, Expand); 470 setOperationAction(ISD::FCOS , MVT::f32, Expand); 471 472 // Special cases we handle for FP constants. 473 addLegalFPImmediate(APFloat(+0.0f)); // xorps 474 addLegalFPImmediate(APFloat(+0.0)); // FLD0 475 addLegalFPImmediate(APFloat(+1.0)); // FLD1 476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 478 479 if (!UnsafeFPMath) { 480 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 481 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 482 } 483 } else if (!UseSoftFloat) { 484 // f32 and f64 in x87. 485 // Set up the FP register classes. 486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 488 489 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 490 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 493 494 if (!UnsafeFPMath) { 495 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 496 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 497 } 498 addLegalFPImmediate(APFloat(+0.0)); // FLD0 499 addLegalFPImmediate(APFloat(+1.0)); // FLD1 500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 506 } 507 508 // Long double always uses X87. 509 if (!UseSoftFloat) { 510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 511 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 513 { 514 bool ignored; 515 APFloat TmpFlt(+0.0); 516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 517 &ignored); 518 addLegalFPImmediate(TmpFlt); // FLD0 519 TmpFlt.changeSign(); 520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 521 APFloat TmpFlt2(+1.0); 522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 523 &ignored); 524 addLegalFPImmediate(TmpFlt2); // FLD1 525 TmpFlt2.changeSign(); 526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 527 } 528 529 if (!UnsafeFPMath) { 530 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 531 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 532 } 533 } 534 535 // Always use a library call for pow. 536 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 537 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 538 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 539 540 setOperationAction(ISD::FLOG, MVT::f80, Expand); 541 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 542 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 543 setOperationAction(ISD::FEXP, MVT::f80, Expand); 544 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 545 546 // First set operation action for all vector types to either promote 547 // (for widening) or expand (for scalarization). Then we will selectively 548 // turn on ones that can be effectively codegen'd. 549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 606 setTruncStoreAction((MVT::SimpleValueType)VT, 607 (MVT::SimpleValueType)InnerVT, Expand); 608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 611 } 612 613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 614 // with -msoft-float, disable use of MMX as well. 615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false); 617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false); 618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false); 619 620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false); 621 622 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 623 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 624 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 625 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 626 627 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 628 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 629 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 630 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 631 632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 633 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 634 635 setOperationAction(ISD::AND, MVT::v8i8, Promote); 636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 637 setOperationAction(ISD::AND, MVT::v4i16, Promote); 638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 639 setOperationAction(ISD::AND, MVT::v2i32, Promote); 640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 641 setOperationAction(ISD::AND, MVT::v1i64, Legal); 642 643 setOperationAction(ISD::OR, MVT::v8i8, Promote); 644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 645 setOperationAction(ISD::OR, MVT::v4i16, Promote); 646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 647 setOperationAction(ISD::OR, MVT::v2i32, Promote); 648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 649 setOperationAction(ISD::OR, MVT::v1i64, Legal); 650 651 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 653 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 655 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 657 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 658 659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 666 667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 671 672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 676 677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 680 681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 682 683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 690 691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) { 692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom); 693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom); 694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom); 695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom); 696 } 697 } 698 699 if (!UseSoftFloat && Subtarget->hasSSE1()) { 700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 701 702 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 714 } 715 716 if (!UseSoftFloat && Subtarget->hasSSE2()) { 717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 718 719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 720 // registers cannot be used even for integer operations. 721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 725 726 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 727 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 728 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 729 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 730 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 731 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 732 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 733 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 734 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 735 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 736 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 742 743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 747 748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 753 754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 759 760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 762 EVT VT = (MVT::SimpleValueType)i; 763 // Do not attempt to custom lower non-power-of-2 vectors 764 if (!isPowerOf2_32(VT.getVectorNumElements())) 765 continue; 766 // Do not attempt to custom lower non-128-bit vectors 767 if (!VT.is128BitVector()) 768 continue; 769 setOperationAction(ISD::BUILD_VECTOR, 770 VT.getSimpleVT().SimpleTy, Custom); 771 setOperationAction(ISD::VECTOR_SHUFFLE, 772 VT.getSimpleVT().SimpleTy, Custom); 773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 774 VT.getSimpleVT().SimpleTy, Custom); 775 } 776 777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 783 784 if (Subtarget->is64Bit()) { 785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 787 } 788 789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 792 EVT VT = SVT; 793 794 // Do not attempt to promote non-128-bit vectors 795 if (!VT.is128BitVector()) 796 continue; 797 798 setOperationAction(ISD::AND, SVT, Promote); 799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 800 setOperationAction(ISD::OR, SVT, Promote); 801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 802 setOperationAction(ISD::XOR, SVT, Promote); 803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 804 setOperationAction(ISD::LOAD, SVT, Promote); 805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 806 setOperationAction(ISD::SELECT, SVT, Promote); 807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 808 } 809 810 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 811 812 // Custom lower v2i64 and v2f64 selects. 813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 817 818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 820 if (!DisableMMX && Subtarget->hasMMX()) { 821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 823 } 824 } 825 826 if (Subtarget->hasSSE41()) { 827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 828 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 830 setOperationAction(ISD::FRINT, MVT::f32, Legal); 831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 833 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 835 setOperationAction(ISD::FRINT, MVT::f64, Legal); 836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 837 838 // FIXME: Do we need to handle scalar-to-vector here? 839 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 840 841 // i8 and i16 vectors are custom , because the source register and source 842 // source memory operand types are not the same width. f32 vectors are 843 // custom since the immediate controlling the insert encodes additional 844 // information. 845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 849 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 854 855 if (Subtarget->is64Bit()) { 856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 858 } 859 } 860 861 if (Subtarget->hasSSE42()) { 862 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 863 } 864 865 if (!UseSoftFloat && Subtarget->hasAVX()) { 866 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 867 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 868 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 869 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 870 871 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 872 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 873 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 874 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 875 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 876 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 877 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 878 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 879 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 880 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 881 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 882 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 883 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 884 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 885 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 886 887 // Operations to consider commented out -v16i16 v32i8 888 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 889 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 890 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 891 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 892 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 893 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 894 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 895 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 896 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 897 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 898 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 899 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 900 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 901 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 902 903 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 904 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 905 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 906 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 907 908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 909 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 910 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 913 914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 917 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 920 921#if 0 922 // Not sure we want to do this since there are no 256-bit integer 923 // operations in AVX 924 925 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 926 // This includes 256-bit vectors 927 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 928 EVT VT = (MVT::SimpleValueType)i; 929 930 // Do not attempt to custom lower non-power-of-2 vectors 931 if (!isPowerOf2_32(VT.getVectorNumElements())) 932 continue; 933 934 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 935 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 937 } 938 939 if (Subtarget->is64Bit()) { 940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 942 } 943#endif 944 945#if 0 946 // Not sure we want to do this since there are no 256-bit integer 947 // operations in AVX 948 949 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 950 // Including 256-bit vectors 951 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 952 EVT VT = (MVT::SimpleValueType)i; 953 954 if (!VT.is256BitVector()) { 955 continue; 956 } 957 setOperationAction(ISD::AND, VT, Promote); 958 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 959 setOperationAction(ISD::OR, VT, Promote); 960 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 961 setOperationAction(ISD::XOR, VT, Promote); 962 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 963 setOperationAction(ISD::LOAD, VT, Promote); 964 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 965 setOperationAction(ISD::SELECT, VT, Promote); 966 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 967 } 968 969 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 970#endif 971 } 972 973 // We want to custom lower some of our intrinsics. 974 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 975 976 // Add/Sub/Mul with overflow operations are custom lowered. 977 setOperationAction(ISD::SADDO, MVT::i32, Custom); 978 setOperationAction(ISD::UADDO, MVT::i32, Custom); 979 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 980 setOperationAction(ISD::USUBO, MVT::i32, Custom); 981 setOperationAction(ISD::SMULO, MVT::i32, Custom); 982 983 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 984 // handle type legalization for these operations here. 985 // 986 // FIXME: We really should do custom legalization for addition and 987 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 988 // than generic legalization for 64-bit multiplication-with-overflow, though. 989 if (Subtarget->is64Bit()) { 990 setOperationAction(ISD::SADDO, MVT::i64, Custom); 991 setOperationAction(ISD::UADDO, MVT::i64, Custom); 992 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 993 setOperationAction(ISD::USUBO, MVT::i64, Custom); 994 setOperationAction(ISD::SMULO, MVT::i64, Custom); 995 } 996 997 if (!Subtarget->is64Bit()) { 998 // These libcalls are not available in 32-bit. 999 setLibcallName(RTLIB::SHL_I128, 0); 1000 setLibcallName(RTLIB::SRL_I128, 0); 1001 setLibcallName(RTLIB::SRA_I128, 0); 1002 } 1003 1004 // We have target-specific dag combine patterns for the following nodes: 1005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1006 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1007 setTargetDAGCombine(ISD::BUILD_VECTOR); 1008 setTargetDAGCombine(ISD::SELECT); 1009 setTargetDAGCombine(ISD::SHL); 1010 setTargetDAGCombine(ISD::SRA); 1011 setTargetDAGCombine(ISD::SRL); 1012 setTargetDAGCombine(ISD::OR); 1013 setTargetDAGCombine(ISD::STORE); 1014 setTargetDAGCombine(ISD::ZERO_EXTEND); 1015 if (Subtarget->is64Bit()) 1016 setTargetDAGCombine(ISD::MUL); 1017 1018 computeRegisterProperties(); 1019 1020 // FIXME: These should be based on subtarget info. Plus, the values should 1021 // be smaller when we are in optimizing for size mode. 1022 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1023 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1024 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1025 setPrefLoopAlignment(16); 1026 benefitFromCodePlacementOpt = true; 1027} 1028 1029 1030MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1031 return MVT::i8; 1032} 1033 1034 1035/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1036/// the desired ByVal argument alignment. 1037static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1038 if (MaxAlign == 16) 1039 return; 1040 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1041 if (VTy->getBitWidth() == 128) 1042 MaxAlign = 16; 1043 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1044 unsigned EltAlign = 0; 1045 getMaxByValAlign(ATy->getElementType(), EltAlign); 1046 if (EltAlign > MaxAlign) 1047 MaxAlign = EltAlign; 1048 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1049 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1050 unsigned EltAlign = 0; 1051 getMaxByValAlign(STy->getElementType(i), EltAlign); 1052 if (EltAlign > MaxAlign) 1053 MaxAlign = EltAlign; 1054 if (MaxAlign == 16) 1055 break; 1056 } 1057 } 1058 return; 1059} 1060 1061/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1062/// function arguments in the caller parameter area. For X86, aggregates 1063/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1064/// are at 4-byte boundaries. 1065unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1066 if (Subtarget->is64Bit()) { 1067 // Max of 8 and alignment of type. 1068 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1069 if (TyAlign > 8) 1070 return TyAlign; 1071 return 8; 1072 } 1073 1074 unsigned Align = 4; 1075 if (Subtarget->hasSSE1()) 1076 getMaxByValAlign(Ty, Align); 1077 return Align; 1078} 1079 1080/// getOptimalMemOpType - Returns the target specific optimal type for load 1081/// and store operations as a result of memset, memcpy, and memmove 1082/// lowering. If DstAlign is zero that means it's safe to destination 1083/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1084/// means there isn't a need to check it against alignment requirement, 1085/// probably because the source does not need to be loaded. If 1086/// 'NonScalarIntSafe' is true, that means it's safe to return a 1087/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1088/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1089/// constant so it does not need to be loaded. 1090/// It returns EVT::Other if the type should be determined using generic 1091/// target-independent logic. 1092EVT 1093X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1094 unsigned DstAlign, unsigned SrcAlign, 1095 bool NonScalarIntSafe, 1096 bool MemcpyStrSrc, 1097 MachineFunction &MF) const { 1098 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1099 // linux. This is because the stack realignment code can't handle certain 1100 // cases like PR2962. This should be removed when PR2962 is fixed. 1101 const Function *F = MF.getFunction(); 1102 if (NonScalarIntSafe && 1103 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1104 if (Size >= 16 && 1105 (Subtarget->isUnalignedMemAccessFast() || 1106 ((DstAlign == 0 || DstAlign >= 16) && 1107 (SrcAlign == 0 || SrcAlign >= 16))) && 1108 Subtarget->getStackAlignment() >= 16) { 1109 if (Subtarget->hasSSE2()) 1110 return MVT::v4i32; 1111 if (Subtarget->hasSSE1()) 1112 return MVT::v4f32; 1113 } else if (!MemcpyStrSrc && Size >= 8 && 1114 !Subtarget->is64Bit() && 1115 Subtarget->getStackAlignment() >= 8 && 1116 Subtarget->hasSSE2()) { 1117 // Do not use f64 to lower memcpy if source is string constant. It's 1118 // better to use i32 to avoid the loads. 1119 return MVT::f64; 1120 } 1121 } 1122 if (Subtarget->is64Bit() && Size >= 8) 1123 return MVT::i64; 1124 return MVT::i32; 1125} 1126 1127/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1128/// current function. The returned value is a member of the 1129/// MachineJumpTableInfo::JTEntryKind enum. 1130unsigned X86TargetLowering::getJumpTableEncoding() const { 1131 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1132 // symbol. 1133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1134 Subtarget->isPICStyleGOT()) 1135 return MachineJumpTableInfo::EK_Custom32; 1136 1137 // Otherwise, use the normal jump table encoding heuristics. 1138 return TargetLowering::getJumpTableEncoding(); 1139} 1140 1141/// getPICBaseSymbol - Return the X86-32 PIC base. 1142MCSymbol * 1143X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1144 MCContext &Ctx) const { 1145 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1146 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1147 Twine(MF->getFunctionNumber())+"$pb"); 1148} 1149 1150 1151const MCExpr * 1152X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1153 const MachineBasicBlock *MBB, 1154 unsigned uid,MCContext &Ctx) const{ 1155 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1156 Subtarget->isPICStyleGOT()); 1157 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1158 // entries. 1159 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1160 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1161} 1162 1163/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1164/// jumptable. 1165SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1166 SelectionDAG &DAG) const { 1167 if (!Subtarget->is64Bit()) 1168 // This doesn't have DebugLoc associated with it, but is not really the 1169 // same as a Register. 1170 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1171 return Table; 1172} 1173 1174/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1175/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1176/// MCExpr. 1177const MCExpr *X86TargetLowering:: 1178getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1179 MCContext &Ctx) const { 1180 // X86-64 uses RIP relative addressing based on the jump table label. 1181 if (Subtarget->isPICStyleRIPRel()) 1182 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1183 1184 // Otherwise, the reference is relative to the PIC base. 1185 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1186} 1187 1188/// getFunctionAlignment - Return the Log2 alignment of this function. 1189unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1190 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1191} 1192 1193bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1194 unsigned &Offset) const { 1195 if (!Subtarget->isTargetLinux()) 1196 return false; 1197 1198 if (Subtarget->is64Bit()) { 1199 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1200 Offset = 0x28; 1201 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1202 AddressSpace = 256; 1203 else 1204 AddressSpace = 257; 1205 } else { 1206 // %gs:0x14 on i386 1207 Offset = 0x14; 1208 AddressSpace = 256; 1209 } 1210 return true; 1211} 1212 1213 1214//===----------------------------------------------------------------------===// 1215// Return Value Calling Convention Implementation 1216//===----------------------------------------------------------------------===// 1217 1218#include "X86GenCallingConv.inc" 1219 1220bool 1221X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1222 const SmallVectorImpl<ISD::OutputArg> &Outs, 1223 LLVMContext &Context) const { 1224 SmallVector<CCValAssign, 16> RVLocs; 1225 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1226 RVLocs, Context); 1227 return CCInfo.CheckReturn(Outs, RetCC_X86); 1228} 1229 1230SDValue 1231X86TargetLowering::LowerReturn(SDValue Chain, 1232 CallingConv::ID CallConv, bool isVarArg, 1233 const SmallVectorImpl<ISD::OutputArg> &Outs, 1234 const SmallVectorImpl<SDValue> &OutVals, 1235 DebugLoc dl, SelectionDAG &DAG) const { 1236 MachineFunction &MF = DAG.getMachineFunction(); 1237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1238 1239 SmallVector<CCValAssign, 16> RVLocs; 1240 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1241 RVLocs, *DAG.getContext()); 1242 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1243 1244 // Add the regs to the liveout set for the function. 1245 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1246 for (unsigned i = 0; i != RVLocs.size(); ++i) 1247 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1248 MRI.addLiveOut(RVLocs[i].getLocReg()); 1249 1250 SDValue Flag; 1251 1252 SmallVector<SDValue, 6> RetOps; 1253 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1254 // Operand #1 = Bytes To Pop 1255 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1256 MVT::i16)); 1257 1258 // Copy the result values into the output registers. 1259 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1260 CCValAssign &VA = RVLocs[i]; 1261 assert(VA.isRegLoc() && "Can only return in registers!"); 1262 SDValue ValToCopy = OutVals[i]; 1263 EVT ValVT = ValToCopy.getValueType(); 1264 1265 // If this is x86-64, and we disabled SSE, we can't return FP values 1266 if ((ValVT == MVT::f32 || ValVT == MVT::f64) && 1267 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1268 report_fatal_error("SSE register return with SSE disabled"); 1269 } 1270 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1271 // llvm-gcc has never done it right and no one has noticed, so this 1272 // should be OK for now. 1273 if (ValVT == MVT::f64 && 1274 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) { 1275 report_fatal_error("SSE2 register return with SSE2 disabled"); 1276 } 1277 1278 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1279 // the RET instruction and handled by the FP Stackifier. 1280 if (VA.getLocReg() == X86::ST0 || 1281 VA.getLocReg() == X86::ST1) { 1282 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1283 // change the value to the FP stack register class. 1284 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1285 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1286 RetOps.push_back(ValToCopy); 1287 // Don't emit a copytoreg. 1288 continue; 1289 } 1290 1291 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1292 // which is returned in RAX / RDX. 1293 if (Subtarget->is64Bit()) { 1294 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1295 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1296 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1297 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1298 ValToCopy); 1299 } 1300 } 1301 1302 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1303 Flag = Chain.getValue(1); 1304 } 1305 1306 // The x86-64 ABI for returning structs by value requires that we copy 1307 // the sret argument into %rax for the return. We saved the argument into 1308 // a virtual register in the entry block, so now we copy the value out 1309 // and into %rax. 1310 if (Subtarget->is64Bit() && 1311 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1312 MachineFunction &MF = DAG.getMachineFunction(); 1313 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1314 unsigned Reg = FuncInfo->getSRetReturnReg(); 1315 assert(Reg && 1316 "SRetReturnReg should have been set in LowerFormalArguments()."); 1317 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1318 1319 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1320 Flag = Chain.getValue(1); 1321 1322 // RAX now acts like a return value. 1323 MRI.addLiveOut(X86::RAX); 1324 } 1325 1326 RetOps[0] = Chain; // Update chain. 1327 1328 // Add the flag if we have it. 1329 if (Flag.getNode()) 1330 RetOps.push_back(Flag); 1331 1332 return DAG.getNode(X86ISD::RET_FLAG, dl, 1333 MVT::Other, &RetOps[0], RetOps.size()); 1334} 1335 1336/// LowerCallResult - Lower the result values of a call into the 1337/// appropriate copies out of appropriate physical registers. 1338/// 1339SDValue 1340X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1341 CallingConv::ID CallConv, bool isVarArg, 1342 const SmallVectorImpl<ISD::InputArg> &Ins, 1343 DebugLoc dl, SelectionDAG &DAG, 1344 SmallVectorImpl<SDValue> &InVals) const { 1345 1346 // Assign locations to each value returned by this call. 1347 SmallVector<CCValAssign, 16> RVLocs; 1348 bool Is64Bit = Subtarget->is64Bit(); 1349 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1350 RVLocs, *DAG.getContext()); 1351 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1352 1353 // Copy all of the result registers out of their specified physreg. 1354 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1355 CCValAssign &VA = RVLocs[i]; 1356 EVT CopyVT = VA.getValVT(); 1357 1358 // If this is x86-64, and we disabled SSE, we can't return FP values 1359 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1360 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1361 report_fatal_error("SSE register return with SSE disabled"); 1362 } 1363 1364 SDValue Val; 1365 1366 // If this is a call to a function that returns an fp value on the floating 1367 // point stack, we must guarantee the the value is popped from the stack, so 1368 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1369 // if the return value is not used. We use the FpGET_ST0 instructions 1370 // instead. 1371 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1372 // If we prefer to use the value in xmm registers, copy it out as f80 and 1373 // use a truncate to move it from fp stack reg to xmm reg. 1374 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1375 bool isST0 = VA.getLocReg() == X86::ST0; 1376 unsigned Opc = 0; 1377 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; 1378 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; 1379 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; 1380 SDValue Ops[] = { Chain, InFlag }; 1381 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag, 1382 Ops, 2), 1); 1383 Val = Chain.getValue(0); 1384 1385 // Round the f80 to the right size, which also moves it to the appropriate 1386 // xmm register. 1387 if (CopyVT != VA.getValVT()) 1388 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1389 // This truncation won't change the value. 1390 DAG.getIntPtrConstant(1)); 1391 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1392 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1393 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1394 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1395 MVT::v2i64, InFlag).getValue(1); 1396 Val = Chain.getValue(0); 1397 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1398 Val, DAG.getConstant(0, MVT::i64)); 1399 } else { 1400 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1401 MVT::i64, InFlag).getValue(1); 1402 Val = Chain.getValue(0); 1403 } 1404 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1405 } else { 1406 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1407 CopyVT, InFlag).getValue(1); 1408 Val = Chain.getValue(0); 1409 } 1410 InFlag = Chain.getValue(2); 1411 InVals.push_back(Val); 1412 } 1413 1414 return Chain; 1415} 1416 1417 1418//===----------------------------------------------------------------------===// 1419// C & StdCall & Fast Calling Convention implementation 1420//===----------------------------------------------------------------------===// 1421// StdCall calling convention seems to be standard for many Windows' API 1422// routines and around. It differs from C calling convention just a little: 1423// callee should clean up the stack, not caller. Symbols should be also 1424// decorated in some fancy way :) It doesn't support any vector arguments. 1425// For info on fast calling convention see Fast Calling Convention (tail call) 1426// implementation LowerX86_32FastCCCallTo. 1427 1428/// CallIsStructReturn - Determines whether a call uses struct return 1429/// semantics. 1430static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1431 if (Outs.empty()) 1432 return false; 1433 1434 return Outs[0].Flags.isSRet(); 1435} 1436 1437/// ArgsAreStructReturn - Determines whether a function uses struct 1438/// return semantics. 1439static bool 1440ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1441 if (Ins.empty()) 1442 return false; 1443 1444 return Ins[0].Flags.isSRet(); 1445} 1446 1447/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1448/// given CallingConvention value. 1449CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1450 if (Subtarget->is64Bit()) { 1451 if (CC == CallingConv::GHC) 1452 return CC_X86_64_GHC; 1453 else if (Subtarget->isTargetWin64()) 1454 return CC_X86_Win64_C; 1455 else 1456 return CC_X86_64_C; 1457 } 1458 1459 if (CC == CallingConv::X86_FastCall) 1460 return CC_X86_32_FastCall; 1461 else if (CC == CallingConv::X86_ThisCall) 1462 return CC_X86_32_ThisCall; 1463 else if (CC == CallingConv::Fast) 1464 return CC_X86_32_FastCC; 1465 else if (CC == CallingConv::GHC) 1466 return CC_X86_32_GHC; 1467 else 1468 return CC_X86_32_C; 1469} 1470 1471/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1472/// by "Src" to address "Dst" with size and alignment information specified by 1473/// the specific parameter attribute. The copy will be passed as a byval 1474/// function parameter. 1475static SDValue 1476CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1477 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1478 DebugLoc dl) { 1479 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1480 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1481 /*isVolatile*/false, /*AlwaysInline=*/true, 1482 NULL, 0, NULL, 0); 1483} 1484 1485/// IsTailCallConvention - Return true if the calling convention is one that 1486/// supports tail call optimization. 1487static bool IsTailCallConvention(CallingConv::ID CC) { 1488 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1489} 1490 1491/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1492/// a tailcall target by changing its ABI. 1493static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1494 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1495} 1496 1497SDValue 1498X86TargetLowering::LowerMemArgument(SDValue Chain, 1499 CallingConv::ID CallConv, 1500 const SmallVectorImpl<ISD::InputArg> &Ins, 1501 DebugLoc dl, SelectionDAG &DAG, 1502 const CCValAssign &VA, 1503 MachineFrameInfo *MFI, 1504 unsigned i) const { 1505 // Create the nodes corresponding to a load from this parameter slot. 1506 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1507 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1508 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1509 EVT ValVT; 1510 1511 // If value is passed by pointer we have address passed instead of the value 1512 // itself. 1513 if (VA.getLocInfo() == CCValAssign::Indirect) 1514 ValVT = VA.getLocVT(); 1515 else 1516 ValVT = VA.getValVT(); 1517 1518 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1519 // changed with more analysis. 1520 // In case of tail call optimization mark all arguments mutable. Since they 1521 // could be overwritten by lowering of arguments in case of a tail call. 1522 if (Flags.isByVal()) { 1523 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1524 VA.getLocMemOffset(), isImmutable); 1525 return DAG.getFrameIndex(FI, getPointerTy()); 1526 } else { 1527 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1528 VA.getLocMemOffset(), isImmutable); 1529 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1530 return DAG.getLoad(ValVT, dl, Chain, FIN, 1531 PseudoSourceValue::getFixedStack(FI), 0, 1532 false, false, 0); 1533 } 1534} 1535 1536SDValue 1537X86TargetLowering::LowerFormalArguments(SDValue Chain, 1538 CallingConv::ID CallConv, 1539 bool isVarArg, 1540 const SmallVectorImpl<ISD::InputArg> &Ins, 1541 DebugLoc dl, 1542 SelectionDAG &DAG, 1543 SmallVectorImpl<SDValue> &InVals) 1544 const { 1545 MachineFunction &MF = DAG.getMachineFunction(); 1546 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1547 1548 const Function* Fn = MF.getFunction(); 1549 if (Fn->hasExternalLinkage() && 1550 Subtarget->isTargetCygMing() && 1551 Fn->getName() == "main") 1552 FuncInfo->setForceFramePointer(true); 1553 1554 MachineFrameInfo *MFI = MF.getFrameInfo(); 1555 bool Is64Bit = Subtarget->is64Bit(); 1556 bool IsWin64 = Subtarget->isTargetWin64(); 1557 1558 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1559 "Var args not supported with calling convention fastcc or ghc"); 1560 1561 // Assign locations to all of the incoming arguments. 1562 SmallVector<CCValAssign, 16> ArgLocs; 1563 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1564 ArgLocs, *DAG.getContext()); 1565 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1566 1567 unsigned LastVal = ~0U; 1568 SDValue ArgValue; 1569 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1570 CCValAssign &VA = ArgLocs[i]; 1571 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1572 // places. 1573 assert(VA.getValNo() != LastVal && 1574 "Don't support value assigned to multiple locs yet"); 1575 LastVal = VA.getValNo(); 1576 1577 if (VA.isRegLoc()) { 1578 EVT RegVT = VA.getLocVT(); 1579 TargetRegisterClass *RC = NULL; 1580 if (RegVT == MVT::i32) 1581 RC = X86::GR32RegisterClass; 1582 else if (Is64Bit && RegVT == MVT::i64) 1583 RC = X86::GR64RegisterClass; 1584 else if (RegVT == MVT::f32) 1585 RC = X86::FR32RegisterClass; 1586 else if (RegVT == MVT::f64) 1587 RC = X86::FR64RegisterClass; 1588 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1589 RC = X86::VR128RegisterClass; 1590 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1591 RC = X86::VR64RegisterClass; 1592 else 1593 llvm_unreachable("Unknown argument type!"); 1594 1595 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1596 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1597 1598 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1599 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1600 // right size. 1601 if (VA.getLocInfo() == CCValAssign::SExt) 1602 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1603 DAG.getValueType(VA.getValVT())); 1604 else if (VA.getLocInfo() == CCValAssign::ZExt) 1605 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1606 DAG.getValueType(VA.getValVT())); 1607 else if (VA.getLocInfo() == CCValAssign::BCvt) 1608 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1609 1610 if (VA.isExtInLoc()) { 1611 // Handle MMX values passed in XMM regs. 1612 if (RegVT.isVector()) { 1613 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1614 ArgValue, DAG.getConstant(0, MVT::i64)); 1615 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1616 } else 1617 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1618 } 1619 } else { 1620 assert(VA.isMemLoc()); 1621 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1622 } 1623 1624 // If value is passed via pointer - do a load. 1625 if (VA.getLocInfo() == CCValAssign::Indirect) 1626 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1627 false, false, 0); 1628 1629 InVals.push_back(ArgValue); 1630 } 1631 1632 // The x86-64 ABI for returning structs by value requires that we copy 1633 // the sret argument into %rax for the return. Save the argument into 1634 // a virtual register so that we can access it from the return points. 1635 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1636 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1637 unsigned Reg = FuncInfo->getSRetReturnReg(); 1638 if (!Reg) { 1639 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1640 FuncInfo->setSRetReturnReg(Reg); 1641 } 1642 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1644 } 1645 1646 unsigned StackSize = CCInfo.getNextStackOffset(); 1647 // Align stack specially for tail calls. 1648 if (FuncIsMadeTailCallSafe(CallConv)) 1649 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1650 1651 // If the function takes variable number of arguments, make a frame index for 1652 // the start of the first vararg value... for expansion of llvm.va_start. 1653 if (isVarArg) { 1654 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1655 CallConv != CallingConv::X86_ThisCall)) { 1656 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1657 } 1658 if (Is64Bit) { 1659 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1660 1661 // FIXME: We should really autogenerate these arrays 1662 static const unsigned GPR64ArgRegsWin64[] = { 1663 X86::RCX, X86::RDX, X86::R8, X86::R9 1664 }; 1665 static const unsigned XMMArgRegsWin64[] = { 1666 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1667 }; 1668 static const unsigned GPR64ArgRegs64Bit[] = { 1669 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1670 }; 1671 static const unsigned XMMArgRegs64Bit[] = { 1672 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1673 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1674 }; 1675 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1676 1677 if (IsWin64) { 1678 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1679 GPR64ArgRegs = GPR64ArgRegsWin64; 1680 XMMArgRegs = XMMArgRegsWin64; 1681 } else { 1682 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1683 GPR64ArgRegs = GPR64ArgRegs64Bit; 1684 XMMArgRegs = XMMArgRegs64Bit; 1685 } 1686 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1687 TotalNumIntRegs); 1688 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1689 TotalNumXMMRegs); 1690 1691 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1692 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1693 "SSE register cannot be used when SSE is disabled!"); 1694 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1695 "SSE register cannot be used when SSE is disabled!"); 1696 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1697 // Kernel mode asks for SSE to be disabled, so don't push them 1698 // on the stack. 1699 TotalNumXMMRegs = 0; 1700 1701 // For X86-64, if there are vararg parameters that are passed via 1702 // registers, then we must store them to their spots on the stack so they 1703 // may be loaded by deferencing the result of va_next. 1704 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1705 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1706 FuncInfo->setRegSaveFrameIndex( 1707 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1708 false)); 1709 1710 // Store the integer parameter registers. 1711 SmallVector<SDValue, 8> MemOps; 1712 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1713 getPointerTy()); 1714 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1715 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1716 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1717 DAG.getIntPtrConstant(Offset)); 1718 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1719 X86::GR64RegisterClass); 1720 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1721 SDValue Store = 1722 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1723 PseudoSourceValue::getFixedStack( 1724 FuncInfo->getRegSaveFrameIndex()), 1725 Offset, false, false, 0); 1726 MemOps.push_back(Store); 1727 Offset += 8; 1728 } 1729 1730 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1731 // Now store the XMM (fp + vector) parameter registers. 1732 SmallVector<SDValue, 11> SaveXMMOps; 1733 SaveXMMOps.push_back(Chain); 1734 1735 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1736 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1737 SaveXMMOps.push_back(ALVal); 1738 1739 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1740 FuncInfo->getRegSaveFrameIndex())); 1741 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1742 FuncInfo->getVarArgsFPOffset())); 1743 1744 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1745 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1746 X86::VR128RegisterClass); 1747 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1748 SaveXMMOps.push_back(Val); 1749 } 1750 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1751 MVT::Other, 1752 &SaveXMMOps[0], SaveXMMOps.size())); 1753 } 1754 1755 if (!MemOps.empty()) 1756 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1757 &MemOps[0], MemOps.size()); 1758 } 1759 } 1760 1761 // Some CCs need callee pop. 1762 if (Subtarget->IsCalleePop(isVarArg, CallConv)) { 1763 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1764 } else { 1765 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1766 // If this is an sret function, the return should pop the hidden pointer. 1767 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1768 FuncInfo->setBytesToPopOnReturn(4); 1769 } 1770 1771 if (!Is64Bit) { 1772 // RegSaveFrameIndex is X86-64 only. 1773 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1774 if (CallConv == CallingConv::X86_FastCall || 1775 CallConv == CallingConv::X86_ThisCall) 1776 // fastcc functions can't have varargs. 1777 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1778 } 1779 1780 return Chain; 1781} 1782 1783SDValue 1784X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1785 SDValue StackPtr, SDValue Arg, 1786 DebugLoc dl, SelectionDAG &DAG, 1787 const CCValAssign &VA, 1788 ISD::ArgFlagsTy Flags) const { 1789 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1790 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1791 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1792 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1793 if (Flags.isByVal()) { 1794 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1795 } 1796 return DAG.getStore(Chain, dl, Arg, PtrOff, 1797 PseudoSourceValue::getStack(), LocMemOffset, 1798 false, false, 0); 1799} 1800 1801/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1802/// optimization is performed and it is required. 1803SDValue 1804X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1805 SDValue &OutRetAddr, SDValue Chain, 1806 bool IsTailCall, bool Is64Bit, 1807 int FPDiff, DebugLoc dl) const { 1808 // Adjust the Return address stack slot. 1809 EVT VT = getPointerTy(); 1810 OutRetAddr = getReturnAddressFrameIndex(DAG); 1811 1812 // Load the "old" Return address. 1813 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1814 return SDValue(OutRetAddr.getNode(), 1); 1815} 1816 1817/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1818/// optimization is performed and it is required (FPDiff!=0). 1819static SDValue 1820EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1821 SDValue Chain, SDValue RetAddrFrIdx, 1822 bool Is64Bit, int FPDiff, DebugLoc dl) { 1823 // Store the return address to the appropriate stack slot. 1824 if (!FPDiff) return Chain; 1825 // Calculate the new stack slot for the return address. 1826 int SlotSize = Is64Bit ? 8 : 4; 1827 int NewReturnAddrFI = 1828 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1829 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1830 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1831 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1832 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1833 false, false, 0); 1834 return Chain; 1835} 1836 1837SDValue 1838X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1839 CallingConv::ID CallConv, bool isVarArg, 1840 bool &isTailCall, 1841 const SmallVectorImpl<ISD::OutputArg> &Outs, 1842 const SmallVectorImpl<SDValue> &OutVals, 1843 const SmallVectorImpl<ISD::InputArg> &Ins, 1844 DebugLoc dl, SelectionDAG &DAG, 1845 SmallVectorImpl<SDValue> &InVals) const { 1846 MachineFunction &MF = DAG.getMachineFunction(); 1847 bool Is64Bit = Subtarget->is64Bit(); 1848 bool IsStructRet = CallIsStructReturn(Outs); 1849 bool IsSibcall = false; 1850 1851 if (isTailCall) { 1852 // Check if it's really possible to do a tail call. 1853 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1854 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1855 Outs, OutVals, Ins, DAG); 1856 1857 // Sibcalls are automatically detected tailcalls which do not require 1858 // ABI changes. 1859 if (!GuaranteedTailCallOpt && isTailCall) 1860 IsSibcall = true; 1861 1862 if (isTailCall) 1863 ++NumTailCalls; 1864 } 1865 1866 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1867 "Var args not supported with calling convention fastcc or ghc"); 1868 1869 // Analyze operands of the call, assigning locations to each operand. 1870 SmallVector<CCValAssign, 16> ArgLocs; 1871 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1872 ArgLocs, *DAG.getContext()); 1873 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1874 1875 // Get a count of how many bytes are to be pushed on the stack. 1876 unsigned NumBytes = CCInfo.getNextStackOffset(); 1877 if (IsSibcall) 1878 // This is a sibcall. The memory operands are available in caller's 1879 // own caller's stack. 1880 NumBytes = 0; 1881 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1882 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1883 1884 int FPDiff = 0; 1885 if (isTailCall && !IsSibcall) { 1886 // Lower arguments at fp - stackoffset + fpdiff. 1887 unsigned NumBytesCallerPushed = 1888 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1889 FPDiff = NumBytesCallerPushed - NumBytes; 1890 1891 // Set the delta of movement of the returnaddr stackslot. 1892 // But only set if delta is greater than previous delta. 1893 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1894 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1895 } 1896 1897 if (!IsSibcall) 1898 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1899 1900 SDValue RetAddrFrIdx; 1901 // Load return adress for tail calls. 1902 if (isTailCall && FPDiff) 1903 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1904 Is64Bit, FPDiff, dl); 1905 1906 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1907 SmallVector<SDValue, 8> MemOpChains; 1908 SDValue StackPtr; 1909 1910 // Walk the register/memloc assignments, inserting copies/loads. In the case 1911 // of tail call optimization arguments are handle later. 1912 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1913 CCValAssign &VA = ArgLocs[i]; 1914 EVT RegVT = VA.getLocVT(); 1915 SDValue Arg = OutVals[i]; 1916 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1917 bool isByVal = Flags.isByVal(); 1918 1919 // Promote the value if needed. 1920 switch (VA.getLocInfo()) { 1921 default: llvm_unreachable("Unknown loc info!"); 1922 case CCValAssign::Full: break; 1923 case CCValAssign::SExt: 1924 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1925 break; 1926 case CCValAssign::ZExt: 1927 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1928 break; 1929 case CCValAssign::AExt: 1930 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1931 // Special case: passing MMX values in XMM registers. 1932 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1933 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1934 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1935 } else 1936 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1937 break; 1938 case CCValAssign::BCvt: 1939 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1940 break; 1941 case CCValAssign::Indirect: { 1942 // Store the argument. 1943 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1944 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1945 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1946 PseudoSourceValue::getFixedStack(FI), 0, 1947 false, false, 0); 1948 Arg = SpillSlot; 1949 break; 1950 } 1951 } 1952 1953 if (VA.isRegLoc()) { 1954 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1955 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1956 assert(VA.isMemLoc()); 1957 if (StackPtr.getNode() == 0) 1958 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1959 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1960 dl, DAG, VA, Flags)); 1961 } 1962 } 1963 1964 if (!MemOpChains.empty()) 1965 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1966 &MemOpChains[0], MemOpChains.size()); 1967 1968 // Build a sequence of copy-to-reg nodes chained together with token chain 1969 // and flag operands which copy the outgoing args into registers. 1970 SDValue InFlag; 1971 // Tail call byval lowering might overwrite argument registers so in case of 1972 // tail call optimization the copies to registers are lowered later. 1973 if (!isTailCall) 1974 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1975 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1976 RegsToPass[i].second, InFlag); 1977 InFlag = Chain.getValue(1); 1978 } 1979 1980 if (Subtarget->isPICStyleGOT()) { 1981 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1982 // GOT pointer. 1983 if (!isTailCall) { 1984 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1985 DAG.getNode(X86ISD::GlobalBaseReg, 1986 DebugLoc(), getPointerTy()), 1987 InFlag); 1988 InFlag = Chain.getValue(1); 1989 } else { 1990 // If we are tail calling and generating PIC/GOT style code load the 1991 // address of the callee into ECX. The value in ecx is used as target of 1992 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1993 // for tail calls on PIC/GOT architectures. Normally we would just put the 1994 // address of GOT into ebx and then call target@PLT. But for tail calls 1995 // ebx would be restored (since ebx is callee saved) before jumping to the 1996 // target@PLT. 1997 1998 // Note: The actual moving to ECX is done further down. 1999 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2000 if (G && !G->getGlobal()->hasHiddenVisibility() && 2001 !G->getGlobal()->hasProtectedVisibility()) 2002 Callee = LowerGlobalAddress(Callee, DAG); 2003 else if (isa<ExternalSymbolSDNode>(Callee)) 2004 Callee = LowerExternalSymbol(Callee, DAG); 2005 } 2006 } 2007 2008 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { 2009 // From AMD64 ABI document: 2010 // For calls that may call functions that use varargs or stdargs 2011 // (prototype-less calls or calls to functions containing ellipsis (...) in 2012 // the declaration) %al is used as hidden argument to specify the number 2013 // of SSE registers used. The contents of %al do not need to match exactly 2014 // the number of registers, but must be an ubound on the number of SSE 2015 // registers used and is in the range 0 - 8 inclusive. 2016 2017 // Count the number of XMM registers allocated. 2018 static const unsigned XMMArgRegs[] = { 2019 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2020 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2021 }; 2022 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2023 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2024 && "SSE registers cannot be used when SSE is disabled"); 2025 2026 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2027 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2028 InFlag = Chain.getValue(1); 2029 } 2030 2031 2032 // For tail calls lower the arguments to the 'real' stack slot. 2033 if (isTailCall) { 2034 // Force all the incoming stack arguments to be loaded from the stack 2035 // before any new outgoing arguments are stored to the stack, because the 2036 // outgoing stack slots may alias the incoming argument stack slots, and 2037 // the alias isn't otherwise explicit. This is slightly more conservative 2038 // than necessary, because it means that each store effectively depends 2039 // on every argument instead of just those arguments it would clobber. 2040 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2041 2042 SmallVector<SDValue, 8> MemOpChains2; 2043 SDValue FIN; 2044 int FI = 0; 2045 // Do not flag preceeding copytoreg stuff together with the following stuff. 2046 InFlag = SDValue(); 2047 if (GuaranteedTailCallOpt) { 2048 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2049 CCValAssign &VA = ArgLocs[i]; 2050 if (VA.isRegLoc()) 2051 continue; 2052 assert(VA.isMemLoc()); 2053 SDValue Arg = OutVals[i]; 2054 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2055 // Create frame index. 2056 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2057 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2058 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2059 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2060 2061 if (Flags.isByVal()) { 2062 // Copy relative to framepointer. 2063 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2064 if (StackPtr.getNode() == 0) 2065 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2066 getPointerTy()); 2067 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2068 2069 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2070 ArgChain, 2071 Flags, DAG, dl)); 2072 } else { 2073 // Store relative to framepointer. 2074 MemOpChains2.push_back( 2075 DAG.getStore(ArgChain, dl, Arg, FIN, 2076 PseudoSourceValue::getFixedStack(FI), 0, 2077 false, false, 0)); 2078 } 2079 } 2080 } 2081 2082 if (!MemOpChains2.empty()) 2083 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2084 &MemOpChains2[0], MemOpChains2.size()); 2085 2086 // Copy arguments to their registers. 2087 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2088 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2089 RegsToPass[i].second, InFlag); 2090 InFlag = Chain.getValue(1); 2091 } 2092 InFlag =SDValue(); 2093 2094 // Store the return address to the appropriate stack slot. 2095 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2096 FPDiff, dl); 2097 } 2098 2099 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2100 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2101 // In the 64-bit large code model, we have to make all calls 2102 // through a register, since the call instruction's 32-bit 2103 // pc-relative offset may not be large enough to hold the whole 2104 // address. 2105 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2106 // If the callee is a GlobalAddress node (quite common, every direct call 2107 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2108 // it. 2109 2110 // We should use extra load for direct calls to dllimported functions in 2111 // non-JIT mode. 2112 const GlobalValue *GV = G->getGlobal(); 2113 if (!GV->hasDLLImportLinkage()) { 2114 unsigned char OpFlags = 0; 2115 2116 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2117 // external symbols most go through the PLT in PIC mode. If the symbol 2118 // has hidden or protected visibility, or if it is static or local, then 2119 // we don't need to use the PLT - we can directly call it. 2120 if (Subtarget->isTargetELF() && 2121 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2122 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2123 OpFlags = X86II::MO_PLT; 2124 } else if (Subtarget->isPICStyleStubAny() && 2125 (GV->isDeclaration() || GV->isWeakForLinker()) && 2126 Subtarget->getDarwinVers() < 9) { 2127 // PC-relative references to external symbols should go through $stub, 2128 // unless we're building with the leopard linker or later, which 2129 // automatically synthesizes these stubs. 2130 OpFlags = X86II::MO_DARWIN_STUB; 2131 } 2132 2133 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2134 G->getOffset(), OpFlags); 2135 } 2136 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2137 unsigned char OpFlags = 0; 2138 2139 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2140 // symbols should go through the PLT. 2141 if (Subtarget->isTargetELF() && 2142 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2143 OpFlags = X86II::MO_PLT; 2144 } else if (Subtarget->isPICStyleStubAny() && 2145 Subtarget->getDarwinVers() < 9) { 2146 // PC-relative references to external symbols should go through $stub, 2147 // unless we're building with the leopard linker or later, which 2148 // automatically synthesizes these stubs. 2149 OpFlags = X86II::MO_DARWIN_STUB; 2150 } 2151 2152 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2153 OpFlags); 2154 } 2155 2156 // Returns a chain & a flag for retval copy to use. 2157 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2158 SmallVector<SDValue, 8> Ops; 2159 2160 if (!IsSibcall && isTailCall) { 2161 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2162 DAG.getIntPtrConstant(0, true), InFlag); 2163 InFlag = Chain.getValue(1); 2164 } 2165 2166 Ops.push_back(Chain); 2167 Ops.push_back(Callee); 2168 2169 if (isTailCall) 2170 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2171 2172 // Add argument registers to the end of the list so that they are known live 2173 // into the call. 2174 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2175 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2176 RegsToPass[i].second.getValueType())); 2177 2178 // Add an implicit use GOT pointer in EBX. 2179 if (!isTailCall && Subtarget->isPICStyleGOT()) 2180 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2181 2182 // Add an implicit use of AL for x86 vararg functions. 2183 if (Is64Bit && isVarArg) 2184 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2185 2186 if (InFlag.getNode()) 2187 Ops.push_back(InFlag); 2188 2189 if (isTailCall) { 2190 // We used to do: 2191 //// If this is the first return lowered for this function, add the regs 2192 //// to the liveout set for the function. 2193 // This isn't right, although it's probably harmless on x86; liveouts 2194 // should be computed from returns not tail calls. Consider a void 2195 // function making a tail call to a function returning int. 2196 return DAG.getNode(X86ISD::TC_RETURN, dl, 2197 NodeTys, &Ops[0], Ops.size()); 2198 } 2199 2200 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2201 InFlag = Chain.getValue(1); 2202 2203 // Create the CALLSEQ_END node. 2204 unsigned NumBytesForCalleeToPush; 2205 if (Subtarget->IsCalleePop(isVarArg, CallConv)) 2206 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2207 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2208 // If this is a call to a struct-return function, the callee 2209 // pops the hidden struct pointer, so we have to push it back. 2210 // This is common for Darwin/X86, Linux & Mingw32 targets. 2211 NumBytesForCalleeToPush = 4; 2212 else 2213 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2214 2215 // Returns a flag for retval copy to use. 2216 if (!IsSibcall) { 2217 Chain = DAG.getCALLSEQ_END(Chain, 2218 DAG.getIntPtrConstant(NumBytes, true), 2219 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2220 true), 2221 InFlag); 2222 InFlag = Chain.getValue(1); 2223 } 2224 2225 // Handle result values, copying them out of physregs into vregs that we 2226 // return. 2227 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2228 Ins, dl, DAG, InVals); 2229} 2230 2231 2232//===----------------------------------------------------------------------===// 2233// Fast Calling Convention (tail call) implementation 2234//===----------------------------------------------------------------------===// 2235 2236// Like std call, callee cleans arguments, convention except that ECX is 2237// reserved for storing the tail called function address. Only 2 registers are 2238// free for argument passing (inreg). Tail call optimization is performed 2239// provided: 2240// * tailcallopt is enabled 2241// * caller/callee are fastcc 2242// On X86_64 architecture with GOT-style position independent code only local 2243// (within module) calls are supported at the moment. 2244// To keep the stack aligned according to platform abi the function 2245// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2246// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2247// If a tail called function callee has more arguments than the caller the 2248// caller needs to make sure that there is room to move the RETADDR to. This is 2249// achieved by reserving an area the size of the argument delta right after the 2250// original REtADDR, but before the saved framepointer or the spilled registers 2251// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2252// stack layout: 2253// arg1 2254// arg2 2255// RETADDR 2256// [ new RETADDR 2257// move area ] 2258// (possible EBP) 2259// ESI 2260// EDI 2261// local1 .. 2262 2263/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2264/// for a 16 byte align requirement. 2265unsigned 2266X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2267 SelectionDAG& DAG) const { 2268 MachineFunction &MF = DAG.getMachineFunction(); 2269 const TargetMachine &TM = MF.getTarget(); 2270 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2271 unsigned StackAlignment = TFI.getStackAlignment(); 2272 uint64_t AlignMask = StackAlignment - 1; 2273 int64_t Offset = StackSize; 2274 uint64_t SlotSize = TD->getPointerSize(); 2275 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2276 // Number smaller than 12 so just add the difference. 2277 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2278 } else { 2279 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2280 Offset = ((~AlignMask) & Offset) + StackAlignment + 2281 (StackAlignment-SlotSize); 2282 } 2283 return Offset; 2284} 2285 2286/// MatchingStackOffset - Return true if the given stack call argument is 2287/// already available in the same position (relatively) of the caller's 2288/// incoming argument stack. 2289static 2290bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2291 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2292 const X86InstrInfo *TII) { 2293 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2294 int FI = INT_MAX; 2295 if (Arg.getOpcode() == ISD::CopyFromReg) { 2296 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2297 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2298 return false; 2299 MachineInstr *Def = MRI->getVRegDef(VR); 2300 if (!Def) 2301 return false; 2302 if (!Flags.isByVal()) { 2303 if (!TII->isLoadFromStackSlot(Def, FI)) 2304 return false; 2305 } else { 2306 unsigned Opcode = Def->getOpcode(); 2307 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2308 Def->getOperand(1).isFI()) { 2309 FI = Def->getOperand(1).getIndex(); 2310 Bytes = Flags.getByValSize(); 2311 } else 2312 return false; 2313 } 2314 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2315 if (Flags.isByVal()) 2316 // ByVal argument is passed in as a pointer but it's now being 2317 // dereferenced. e.g. 2318 // define @foo(%struct.X* %A) { 2319 // tail call @bar(%struct.X* byval %A) 2320 // } 2321 return false; 2322 SDValue Ptr = Ld->getBasePtr(); 2323 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2324 if (!FINode) 2325 return false; 2326 FI = FINode->getIndex(); 2327 } else 2328 return false; 2329 2330 assert(FI != INT_MAX); 2331 if (!MFI->isFixedObjectIndex(FI)) 2332 return false; 2333 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2334} 2335 2336/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2337/// for tail call optimization. Targets which want to do tail call 2338/// optimization should implement this function. 2339bool 2340X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2341 CallingConv::ID CalleeCC, 2342 bool isVarArg, 2343 bool isCalleeStructRet, 2344 bool isCallerStructRet, 2345 const SmallVectorImpl<ISD::OutputArg> &Outs, 2346 const SmallVectorImpl<SDValue> &OutVals, 2347 const SmallVectorImpl<ISD::InputArg> &Ins, 2348 SelectionDAG& DAG) const { 2349 if (!IsTailCallConvention(CalleeCC) && 2350 CalleeCC != CallingConv::C) 2351 return false; 2352 2353 // If -tailcallopt is specified, make fastcc functions tail-callable. 2354 const MachineFunction &MF = DAG.getMachineFunction(); 2355 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2356 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2357 bool CCMatch = CallerCC == CalleeCC; 2358 2359 if (GuaranteedTailCallOpt) { 2360 if (IsTailCallConvention(CalleeCC) && CCMatch) 2361 return true; 2362 return false; 2363 } 2364 2365 // Look for obvious safe cases to perform tail call optimization that do not 2366 // require ABI changes. This is what gcc calls sibcall. 2367 2368 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2369 // emit a special epilogue. 2370 if (RegInfo->needsStackRealignment(MF)) 2371 return false; 2372 2373 // Do not sibcall optimize vararg calls unless the call site is not passing 2374 // any arguments. 2375 if (isVarArg && !Outs.empty()) 2376 return false; 2377 2378 // Also avoid sibcall optimization if either caller or callee uses struct 2379 // return semantics. 2380 if (isCalleeStructRet || isCallerStructRet) 2381 return false; 2382 2383 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2384 // Therefore if it's not used by the call it is not safe to optimize this into 2385 // a sibcall. 2386 bool Unused = false; 2387 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2388 if (!Ins[i].Used) { 2389 Unused = true; 2390 break; 2391 } 2392 } 2393 if (Unused) { 2394 SmallVector<CCValAssign, 16> RVLocs; 2395 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2396 RVLocs, *DAG.getContext()); 2397 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2398 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2399 CCValAssign &VA = RVLocs[i]; 2400 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2401 return false; 2402 } 2403 } 2404 2405 // If the calling conventions do not match, then we'd better make sure the 2406 // results are returned in the same way as what the caller expects. 2407 if (!CCMatch) { 2408 SmallVector<CCValAssign, 16> RVLocs1; 2409 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 2410 RVLocs1, *DAG.getContext()); 2411 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2412 2413 SmallVector<CCValAssign, 16> RVLocs2; 2414 CCState CCInfo2(CallerCC, false, getTargetMachine(), 2415 RVLocs2, *DAG.getContext()); 2416 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2417 2418 if (RVLocs1.size() != RVLocs2.size()) 2419 return false; 2420 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2421 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2422 return false; 2423 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2424 return false; 2425 if (RVLocs1[i].isRegLoc()) { 2426 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2427 return false; 2428 } else { 2429 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2430 return false; 2431 } 2432 } 2433 } 2434 2435 // If the callee takes no arguments then go on to check the results of the 2436 // call. 2437 if (!Outs.empty()) { 2438 // Check if stack adjustment is needed. For now, do not do this if any 2439 // argument is passed on the stack. 2440 SmallVector<CCValAssign, 16> ArgLocs; 2441 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2442 ArgLocs, *DAG.getContext()); 2443 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2444 if (CCInfo.getNextStackOffset()) { 2445 MachineFunction &MF = DAG.getMachineFunction(); 2446 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2447 return false; 2448 if (Subtarget->isTargetWin64()) 2449 // Win64 ABI has additional complications. 2450 return false; 2451 2452 // Check if the arguments are already laid out in the right way as 2453 // the caller's fixed stack objects. 2454 MachineFrameInfo *MFI = MF.getFrameInfo(); 2455 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2456 const X86InstrInfo *TII = 2457 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2458 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2459 CCValAssign &VA = ArgLocs[i]; 2460 SDValue Arg = OutVals[i]; 2461 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2462 if (VA.getLocInfo() == CCValAssign::Indirect) 2463 return false; 2464 if (!VA.isRegLoc()) { 2465 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2466 MFI, MRI, TII)) 2467 return false; 2468 } 2469 } 2470 } 2471 2472 // If the tailcall address may be in a register, then make sure it's 2473 // possible to register allocate for it. In 32-bit, the call address can 2474 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2475 // callee-saved registers are restored. These happen to be the same 2476 // registers used to pass 'inreg' arguments so watch out for those. 2477 if (!Subtarget->is64Bit() && 2478 !isa<GlobalAddressSDNode>(Callee) && 2479 !isa<ExternalSymbolSDNode>(Callee)) { 2480 unsigned NumInRegs = 0; 2481 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2482 CCValAssign &VA = ArgLocs[i]; 2483 if (!VA.isRegLoc()) 2484 continue; 2485 unsigned Reg = VA.getLocReg(); 2486 switch (Reg) { 2487 default: break; 2488 case X86::EAX: case X86::EDX: case X86::ECX: 2489 if (++NumInRegs == 3) 2490 return false; 2491 break; 2492 } 2493 } 2494 } 2495 } 2496 2497 return true; 2498} 2499 2500FastISel * 2501X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2502 return X86::createFastISel(funcInfo); 2503} 2504 2505 2506//===----------------------------------------------------------------------===// 2507// Other Lowering Hooks 2508//===----------------------------------------------------------------------===// 2509 2510 2511SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2512 MachineFunction &MF = DAG.getMachineFunction(); 2513 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2514 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2515 2516 if (ReturnAddrIndex == 0) { 2517 // Set up a frame object for the return address. 2518 uint64_t SlotSize = TD->getPointerSize(); 2519 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2520 false); 2521 FuncInfo->setRAIndex(ReturnAddrIndex); 2522 } 2523 2524 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2525} 2526 2527 2528bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2529 bool hasSymbolicDisplacement) { 2530 // Offset should fit into 32 bit immediate field. 2531 if (!isInt<32>(Offset)) 2532 return false; 2533 2534 // If we don't have a symbolic displacement - we don't have any extra 2535 // restrictions. 2536 if (!hasSymbolicDisplacement) 2537 return true; 2538 2539 // FIXME: Some tweaks might be needed for medium code model. 2540 if (M != CodeModel::Small && M != CodeModel::Kernel) 2541 return false; 2542 2543 // For small code model we assume that latest object is 16MB before end of 31 2544 // bits boundary. We may also accept pretty large negative constants knowing 2545 // that all objects are in the positive half of address space. 2546 if (M == CodeModel::Small && Offset < 16*1024*1024) 2547 return true; 2548 2549 // For kernel code model we know that all object resist in the negative half 2550 // of 32bits address space. We may not accept negative offsets, since they may 2551 // be just off and we may accept pretty large positive ones. 2552 if (M == CodeModel::Kernel && Offset > 0) 2553 return true; 2554 2555 return false; 2556} 2557 2558/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2559/// specific condition code, returning the condition code and the LHS/RHS of the 2560/// comparison to make. 2561static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2562 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2563 if (!isFP) { 2564 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2565 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2566 // X > -1 -> X == 0, jump !sign. 2567 RHS = DAG.getConstant(0, RHS.getValueType()); 2568 return X86::COND_NS; 2569 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2570 // X < 0 -> X == 0, jump on sign. 2571 return X86::COND_S; 2572 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2573 // X < 1 -> X <= 0 2574 RHS = DAG.getConstant(0, RHS.getValueType()); 2575 return X86::COND_LE; 2576 } 2577 } 2578 2579 switch (SetCCOpcode) { 2580 default: llvm_unreachable("Invalid integer condition!"); 2581 case ISD::SETEQ: return X86::COND_E; 2582 case ISD::SETGT: return X86::COND_G; 2583 case ISD::SETGE: return X86::COND_GE; 2584 case ISD::SETLT: return X86::COND_L; 2585 case ISD::SETLE: return X86::COND_LE; 2586 case ISD::SETNE: return X86::COND_NE; 2587 case ISD::SETULT: return X86::COND_B; 2588 case ISD::SETUGT: return X86::COND_A; 2589 case ISD::SETULE: return X86::COND_BE; 2590 case ISD::SETUGE: return X86::COND_AE; 2591 } 2592 } 2593 2594 // First determine if it is required or is profitable to flip the operands. 2595 2596 // If LHS is a foldable load, but RHS is not, flip the condition. 2597 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2598 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2599 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2600 std::swap(LHS, RHS); 2601 } 2602 2603 switch (SetCCOpcode) { 2604 default: break; 2605 case ISD::SETOLT: 2606 case ISD::SETOLE: 2607 case ISD::SETUGT: 2608 case ISD::SETUGE: 2609 std::swap(LHS, RHS); 2610 break; 2611 } 2612 2613 // On a floating point condition, the flags are set as follows: 2614 // ZF PF CF op 2615 // 0 | 0 | 0 | X > Y 2616 // 0 | 0 | 1 | X < Y 2617 // 1 | 0 | 0 | X == Y 2618 // 1 | 1 | 1 | unordered 2619 switch (SetCCOpcode) { 2620 default: llvm_unreachable("Condcode should be pre-legalized away"); 2621 case ISD::SETUEQ: 2622 case ISD::SETEQ: return X86::COND_E; 2623 case ISD::SETOLT: // flipped 2624 case ISD::SETOGT: 2625 case ISD::SETGT: return X86::COND_A; 2626 case ISD::SETOLE: // flipped 2627 case ISD::SETOGE: 2628 case ISD::SETGE: return X86::COND_AE; 2629 case ISD::SETUGT: // flipped 2630 case ISD::SETULT: 2631 case ISD::SETLT: return X86::COND_B; 2632 case ISD::SETUGE: // flipped 2633 case ISD::SETULE: 2634 case ISD::SETLE: return X86::COND_BE; 2635 case ISD::SETONE: 2636 case ISD::SETNE: return X86::COND_NE; 2637 case ISD::SETUO: return X86::COND_P; 2638 case ISD::SETO: return X86::COND_NP; 2639 case ISD::SETOEQ: 2640 case ISD::SETUNE: return X86::COND_INVALID; 2641 } 2642} 2643 2644/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2645/// code. Current x86 isa includes the following FP cmov instructions: 2646/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2647static bool hasFPCMov(unsigned X86CC) { 2648 switch (X86CC) { 2649 default: 2650 return false; 2651 case X86::COND_B: 2652 case X86::COND_BE: 2653 case X86::COND_E: 2654 case X86::COND_P: 2655 case X86::COND_A: 2656 case X86::COND_AE: 2657 case X86::COND_NE: 2658 case X86::COND_NP: 2659 return true; 2660 } 2661} 2662 2663/// isFPImmLegal - Returns true if the target can instruction select the 2664/// specified FP immediate natively. If false, the legalizer will 2665/// materialize the FP immediate as a load from a constant pool. 2666bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2667 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2668 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2669 return true; 2670 } 2671 return false; 2672} 2673 2674/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2675/// the specified range (L, H]. 2676static bool isUndefOrInRange(int Val, int Low, int Hi) { 2677 return (Val < 0) || (Val >= Low && Val < Hi); 2678} 2679 2680/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2681/// specified value. 2682static bool isUndefOrEqual(int Val, int CmpVal) { 2683 if (Val < 0 || Val == CmpVal) 2684 return true; 2685 return false; 2686} 2687 2688/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2689/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2690/// the second operand. 2691static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2692 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2693 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2694 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2695 return (Mask[0] < 2 && Mask[1] < 2); 2696 return false; 2697} 2698 2699bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2700 SmallVector<int, 8> M; 2701 N->getMask(M); 2702 return ::isPSHUFDMask(M, N->getValueType(0)); 2703} 2704 2705/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2706/// is suitable for input to PSHUFHW. 2707static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2708 if (VT != MVT::v8i16) 2709 return false; 2710 2711 // Lower quadword copied in order or undef. 2712 for (int i = 0; i != 4; ++i) 2713 if (Mask[i] >= 0 && Mask[i] != i) 2714 return false; 2715 2716 // Upper quadword shuffled. 2717 for (int i = 4; i != 8; ++i) 2718 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2719 return false; 2720 2721 return true; 2722} 2723 2724bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2725 SmallVector<int, 8> M; 2726 N->getMask(M); 2727 return ::isPSHUFHWMask(M, N->getValueType(0)); 2728} 2729 2730/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2731/// is suitable for input to PSHUFLW. 2732static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2733 if (VT != MVT::v8i16) 2734 return false; 2735 2736 // Upper quadword copied in order. 2737 for (int i = 4; i != 8; ++i) 2738 if (Mask[i] >= 0 && Mask[i] != i) 2739 return false; 2740 2741 // Lower quadword shuffled. 2742 for (int i = 0; i != 4; ++i) 2743 if (Mask[i] >= 4) 2744 return false; 2745 2746 return true; 2747} 2748 2749bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2750 SmallVector<int, 8> M; 2751 N->getMask(M); 2752 return ::isPSHUFLWMask(M, N->getValueType(0)); 2753} 2754 2755/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2756/// is suitable for input to PALIGNR. 2757static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2758 bool hasSSSE3) { 2759 int i, e = VT.getVectorNumElements(); 2760 2761 // Do not handle v2i64 / v2f64 shuffles with palignr. 2762 if (e < 4 || !hasSSSE3) 2763 return false; 2764 2765 for (i = 0; i != e; ++i) 2766 if (Mask[i] >= 0) 2767 break; 2768 2769 // All undef, not a palignr. 2770 if (i == e) 2771 return false; 2772 2773 // Determine if it's ok to perform a palignr with only the LHS, since we 2774 // don't have access to the actual shuffle elements to see if RHS is undef. 2775 bool Unary = Mask[i] < (int)e; 2776 bool NeedsUnary = false; 2777 2778 int s = Mask[i] - i; 2779 2780 // Check the rest of the elements to see if they are consecutive. 2781 for (++i; i != e; ++i) { 2782 int m = Mask[i]; 2783 if (m < 0) 2784 continue; 2785 2786 Unary = Unary && (m < (int)e); 2787 NeedsUnary = NeedsUnary || (m < s); 2788 2789 if (NeedsUnary && !Unary) 2790 return false; 2791 if (Unary && m != ((s+i) & (e-1))) 2792 return false; 2793 if (!Unary && m != (s+i)) 2794 return false; 2795 } 2796 return true; 2797} 2798 2799bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2800 SmallVector<int, 8> M; 2801 N->getMask(M); 2802 return ::isPALIGNRMask(M, N->getValueType(0), true); 2803} 2804 2805/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2806/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2807static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2808 int NumElems = VT.getVectorNumElements(); 2809 if (NumElems != 2 && NumElems != 4) 2810 return false; 2811 2812 int Half = NumElems / 2; 2813 for (int i = 0; i < Half; ++i) 2814 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2815 return false; 2816 for (int i = Half; i < NumElems; ++i) 2817 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2818 return false; 2819 2820 return true; 2821} 2822 2823bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2824 SmallVector<int, 8> M; 2825 N->getMask(M); 2826 return ::isSHUFPMask(M, N->getValueType(0)); 2827} 2828 2829/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2830/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2831/// half elements to come from vector 1 (which would equal the dest.) and 2832/// the upper half to come from vector 2. 2833static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2834 int NumElems = VT.getVectorNumElements(); 2835 2836 if (NumElems != 2 && NumElems != 4) 2837 return false; 2838 2839 int Half = NumElems / 2; 2840 for (int i = 0; i < Half; ++i) 2841 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2842 return false; 2843 for (int i = Half; i < NumElems; ++i) 2844 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2845 return false; 2846 return true; 2847} 2848 2849static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2850 SmallVector<int, 8> M; 2851 N->getMask(M); 2852 return isCommutedSHUFPMask(M, N->getValueType(0)); 2853} 2854 2855/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2856/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2857bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2858 if (N->getValueType(0).getVectorNumElements() != 4) 2859 return false; 2860 2861 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2862 return isUndefOrEqual(N->getMaskElt(0), 6) && 2863 isUndefOrEqual(N->getMaskElt(1), 7) && 2864 isUndefOrEqual(N->getMaskElt(2), 2) && 2865 isUndefOrEqual(N->getMaskElt(3), 3); 2866} 2867 2868/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2869/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2870/// <2, 3, 2, 3> 2871bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2872 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2873 2874 if (NumElems != 4) 2875 return false; 2876 2877 return isUndefOrEqual(N->getMaskElt(0), 2) && 2878 isUndefOrEqual(N->getMaskElt(1), 3) && 2879 isUndefOrEqual(N->getMaskElt(2), 2) && 2880 isUndefOrEqual(N->getMaskElt(3), 3); 2881} 2882 2883/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2884/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2885bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2886 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2887 2888 if (NumElems != 2 && NumElems != 4) 2889 return false; 2890 2891 for (unsigned i = 0; i < NumElems/2; ++i) 2892 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2893 return false; 2894 2895 for (unsigned i = NumElems/2; i < NumElems; ++i) 2896 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2897 return false; 2898 2899 return true; 2900} 2901 2902/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2903/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2904bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2905 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2906 2907 if (NumElems != 2 && NumElems != 4) 2908 return false; 2909 2910 for (unsigned i = 0; i < NumElems/2; ++i) 2911 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2912 return false; 2913 2914 for (unsigned i = 0; i < NumElems/2; ++i) 2915 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2916 return false; 2917 2918 return true; 2919} 2920 2921/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2922/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2923static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2924 bool V2IsSplat = false) { 2925 int NumElts = VT.getVectorNumElements(); 2926 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2927 return false; 2928 2929 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2930 int BitI = Mask[i]; 2931 int BitI1 = Mask[i+1]; 2932 if (!isUndefOrEqual(BitI, j)) 2933 return false; 2934 if (V2IsSplat) { 2935 if (!isUndefOrEqual(BitI1, NumElts)) 2936 return false; 2937 } else { 2938 if (!isUndefOrEqual(BitI1, j + NumElts)) 2939 return false; 2940 } 2941 } 2942 return true; 2943} 2944 2945bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2946 SmallVector<int, 8> M; 2947 N->getMask(M); 2948 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2949} 2950 2951/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2952/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2953static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2954 bool V2IsSplat = false) { 2955 int NumElts = VT.getVectorNumElements(); 2956 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2957 return false; 2958 2959 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2960 int BitI = Mask[i]; 2961 int BitI1 = Mask[i+1]; 2962 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2963 return false; 2964 if (V2IsSplat) { 2965 if (isUndefOrEqual(BitI1, NumElts)) 2966 return false; 2967 } else { 2968 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2969 return false; 2970 } 2971 } 2972 return true; 2973} 2974 2975bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2976 SmallVector<int, 8> M; 2977 N->getMask(M); 2978 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2979} 2980 2981/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2982/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2983/// <0, 0, 1, 1> 2984static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2985 int NumElems = VT.getVectorNumElements(); 2986 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2987 return false; 2988 2989 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2990 int BitI = Mask[i]; 2991 int BitI1 = Mask[i+1]; 2992 if (!isUndefOrEqual(BitI, j)) 2993 return false; 2994 if (!isUndefOrEqual(BitI1, j)) 2995 return false; 2996 } 2997 return true; 2998} 2999 3000bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3001 SmallVector<int, 8> M; 3002 N->getMask(M); 3003 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3004} 3005 3006/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3007/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3008/// <2, 2, 3, 3> 3009static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3010 int NumElems = VT.getVectorNumElements(); 3011 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3012 return false; 3013 3014 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3015 int BitI = Mask[i]; 3016 int BitI1 = Mask[i+1]; 3017 if (!isUndefOrEqual(BitI, j)) 3018 return false; 3019 if (!isUndefOrEqual(BitI1, j)) 3020 return false; 3021 } 3022 return true; 3023} 3024 3025bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3026 SmallVector<int, 8> M; 3027 N->getMask(M); 3028 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3029} 3030 3031/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3032/// specifies a shuffle of elements that is suitable for input to MOVSS, 3033/// MOVSD, and MOVD, i.e. setting the lowest element. 3034static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3035 if (VT.getVectorElementType().getSizeInBits() < 32) 3036 return false; 3037 3038 int NumElts = VT.getVectorNumElements(); 3039 3040 if (!isUndefOrEqual(Mask[0], NumElts)) 3041 return false; 3042 3043 for (int i = 1; i < NumElts; ++i) 3044 if (!isUndefOrEqual(Mask[i], i)) 3045 return false; 3046 3047 return true; 3048} 3049 3050bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3051 SmallVector<int, 8> M; 3052 N->getMask(M); 3053 return ::isMOVLMask(M, N->getValueType(0)); 3054} 3055 3056/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3057/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3058/// element of vector 2 and the other elements to come from vector 1 in order. 3059static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3060 bool V2IsSplat = false, bool V2IsUndef = false) { 3061 int NumOps = VT.getVectorNumElements(); 3062 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3063 return false; 3064 3065 if (!isUndefOrEqual(Mask[0], 0)) 3066 return false; 3067 3068 for (int i = 1; i < NumOps; ++i) 3069 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3070 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3071 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3072 return false; 3073 3074 return true; 3075} 3076 3077static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3078 bool V2IsUndef = false) { 3079 SmallVector<int, 8> M; 3080 N->getMask(M); 3081 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3082} 3083 3084/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3085/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3086bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3087 if (N->getValueType(0).getVectorNumElements() != 4) 3088 return false; 3089 3090 // Expect 1, 1, 3, 3 3091 for (unsigned i = 0; i < 2; ++i) { 3092 int Elt = N->getMaskElt(i); 3093 if (Elt >= 0 && Elt != 1) 3094 return false; 3095 } 3096 3097 bool HasHi = false; 3098 for (unsigned i = 2; i < 4; ++i) { 3099 int Elt = N->getMaskElt(i); 3100 if (Elt >= 0 && Elt != 3) 3101 return false; 3102 if (Elt == 3) 3103 HasHi = true; 3104 } 3105 // Don't use movshdup if it can be done with a shufps. 3106 // FIXME: verify that matching u, u, 3, 3 is what we want. 3107 return HasHi; 3108} 3109 3110/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3111/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3112bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3113 if (N->getValueType(0).getVectorNumElements() != 4) 3114 return false; 3115 3116 // Expect 0, 0, 2, 2 3117 for (unsigned i = 0; i < 2; ++i) 3118 if (N->getMaskElt(i) > 0) 3119 return false; 3120 3121 bool HasHi = false; 3122 for (unsigned i = 2; i < 4; ++i) { 3123 int Elt = N->getMaskElt(i); 3124 if (Elt >= 0 && Elt != 2) 3125 return false; 3126 if (Elt == 2) 3127 HasHi = true; 3128 } 3129 // Don't use movsldup if it can be done with a shufps. 3130 return HasHi; 3131} 3132 3133/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3134/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3135bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3136 int e = N->getValueType(0).getVectorNumElements() / 2; 3137 3138 for (int i = 0; i < e; ++i) 3139 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3140 return false; 3141 for (int i = 0; i < e; ++i) 3142 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3143 return false; 3144 return true; 3145} 3146 3147/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3148/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3149unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3150 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3151 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3152 3153 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3154 unsigned Mask = 0; 3155 for (int i = 0; i < NumOperands; ++i) { 3156 int Val = SVOp->getMaskElt(NumOperands-i-1); 3157 if (Val < 0) Val = 0; 3158 if (Val >= NumOperands) Val -= NumOperands; 3159 Mask |= Val; 3160 if (i != NumOperands - 1) 3161 Mask <<= Shift; 3162 } 3163 return Mask; 3164} 3165 3166/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3167/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3168unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3170 unsigned Mask = 0; 3171 // 8 nodes, but we only care about the last 4. 3172 for (unsigned i = 7; i >= 4; --i) { 3173 int Val = SVOp->getMaskElt(i); 3174 if (Val >= 0) 3175 Mask |= (Val - 4); 3176 if (i != 4) 3177 Mask <<= 2; 3178 } 3179 return Mask; 3180} 3181 3182/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3183/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3184unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3185 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3186 unsigned Mask = 0; 3187 // 8 nodes, but we only care about the first 4. 3188 for (int i = 3; i >= 0; --i) { 3189 int Val = SVOp->getMaskElt(i); 3190 if (Val >= 0) 3191 Mask |= Val; 3192 if (i != 0) 3193 Mask <<= 2; 3194 } 3195 return Mask; 3196} 3197 3198/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3199/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3200unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3202 EVT VVT = N->getValueType(0); 3203 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3204 int Val = 0; 3205 3206 unsigned i, e; 3207 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3208 Val = SVOp->getMaskElt(i); 3209 if (Val >= 0) 3210 break; 3211 } 3212 return (Val - i) * EltSize; 3213} 3214 3215/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3216/// constant +0.0. 3217bool X86::isZeroNode(SDValue Elt) { 3218 return ((isa<ConstantSDNode>(Elt) && 3219 cast<ConstantSDNode>(Elt)->isNullValue()) || 3220 (isa<ConstantFPSDNode>(Elt) && 3221 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3222} 3223 3224/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3225/// their permute mask. 3226static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3227 SelectionDAG &DAG) { 3228 EVT VT = SVOp->getValueType(0); 3229 unsigned NumElems = VT.getVectorNumElements(); 3230 SmallVector<int, 8> MaskVec; 3231 3232 for (unsigned i = 0; i != NumElems; ++i) { 3233 int idx = SVOp->getMaskElt(i); 3234 if (idx < 0) 3235 MaskVec.push_back(idx); 3236 else if (idx < (int)NumElems) 3237 MaskVec.push_back(idx + NumElems); 3238 else 3239 MaskVec.push_back(idx - NumElems); 3240 } 3241 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3242 SVOp->getOperand(0), &MaskVec[0]); 3243} 3244 3245/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3246/// the two vector operands have swapped position. 3247static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3248 unsigned NumElems = VT.getVectorNumElements(); 3249 for (unsigned i = 0; i != NumElems; ++i) { 3250 int idx = Mask[i]; 3251 if (idx < 0) 3252 continue; 3253 else if (idx < (int)NumElems) 3254 Mask[i] = idx + NumElems; 3255 else 3256 Mask[i] = idx - NumElems; 3257 } 3258} 3259 3260/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3261/// match movhlps. The lower half elements should come from upper half of 3262/// V1 (and in order), and the upper half elements should come from the upper 3263/// half of V2 (and in order). 3264static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3265 if (Op->getValueType(0).getVectorNumElements() != 4) 3266 return false; 3267 for (unsigned i = 0, e = 2; i != e; ++i) 3268 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3269 return false; 3270 for (unsigned i = 2; i != 4; ++i) 3271 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3272 return false; 3273 return true; 3274} 3275 3276/// isScalarLoadToVector - Returns true if the node is a scalar load that 3277/// is promoted to a vector. It also returns the LoadSDNode by reference if 3278/// required. 3279static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3280 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3281 return false; 3282 N = N->getOperand(0).getNode(); 3283 if (!ISD::isNON_EXTLoad(N)) 3284 return false; 3285 if (LD) 3286 *LD = cast<LoadSDNode>(N); 3287 return true; 3288} 3289 3290/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3291/// match movlp{s|d}. The lower half elements should come from lower half of 3292/// V1 (and in order), and the upper half elements should come from the upper 3293/// half of V2 (and in order). And since V1 will become the source of the 3294/// MOVLP, it must be either a vector load or a scalar load to vector. 3295static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3296 ShuffleVectorSDNode *Op) { 3297 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3298 return false; 3299 // Is V2 is a vector load, don't do this transformation. We will try to use 3300 // load folding shufps op. 3301 if (ISD::isNON_EXTLoad(V2)) 3302 return false; 3303 3304 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3305 3306 if (NumElems != 2 && NumElems != 4) 3307 return false; 3308 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3309 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3310 return false; 3311 for (unsigned i = NumElems/2; i != NumElems; ++i) 3312 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3313 return false; 3314 return true; 3315} 3316 3317/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3318/// all the same. 3319static bool isSplatVector(SDNode *N) { 3320 if (N->getOpcode() != ISD::BUILD_VECTOR) 3321 return false; 3322 3323 SDValue SplatValue = N->getOperand(0); 3324 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3325 if (N->getOperand(i) != SplatValue) 3326 return false; 3327 return true; 3328} 3329 3330/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3331/// to an zero vector. 3332/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3333static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3334 SDValue V1 = N->getOperand(0); 3335 SDValue V2 = N->getOperand(1); 3336 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3337 for (unsigned i = 0; i != NumElems; ++i) { 3338 int Idx = N->getMaskElt(i); 3339 if (Idx >= (int)NumElems) { 3340 unsigned Opc = V2.getOpcode(); 3341 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3342 continue; 3343 if (Opc != ISD::BUILD_VECTOR || 3344 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3345 return false; 3346 } else if (Idx >= 0) { 3347 unsigned Opc = V1.getOpcode(); 3348 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3349 continue; 3350 if (Opc != ISD::BUILD_VECTOR || 3351 !X86::isZeroNode(V1.getOperand(Idx))) 3352 return false; 3353 } 3354 } 3355 return true; 3356} 3357 3358/// getZeroVector - Returns a vector of specified type with all zero elements. 3359/// 3360static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3361 DebugLoc dl) { 3362 assert(VT.isVector() && "Expected a vector type"); 3363 3364 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3365 // type. This ensures they get CSE'd. 3366 SDValue Vec; 3367 if (VT.getSizeInBits() == 64) { // MMX 3368 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3369 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3370 } else if (HasSSE2) { // SSE2 3371 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3372 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3373 } else { // SSE1 3374 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3375 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3376 } 3377 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3378} 3379 3380/// getOnesVector - Returns a vector of specified type with all bits set. 3381/// 3382static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3383 assert(VT.isVector() && "Expected a vector type"); 3384 3385 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3386 // type. This ensures they get CSE'd. 3387 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3388 SDValue Vec; 3389 if (VT.getSizeInBits() == 64) // MMX 3390 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3391 else // SSE 3392 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3393 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3394} 3395 3396 3397/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3398/// that point to V2 points to its first element. 3399static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3400 EVT VT = SVOp->getValueType(0); 3401 unsigned NumElems = VT.getVectorNumElements(); 3402 3403 bool Changed = false; 3404 SmallVector<int, 8> MaskVec; 3405 SVOp->getMask(MaskVec); 3406 3407 for (unsigned i = 0; i != NumElems; ++i) { 3408 if (MaskVec[i] > (int)NumElems) { 3409 MaskVec[i] = NumElems; 3410 Changed = true; 3411 } 3412 } 3413 if (Changed) 3414 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3415 SVOp->getOperand(1), &MaskVec[0]); 3416 return SDValue(SVOp, 0); 3417} 3418 3419/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3420/// operation of specified width. 3421static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3422 SDValue V2) { 3423 unsigned NumElems = VT.getVectorNumElements(); 3424 SmallVector<int, 8> Mask; 3425 Mask.push_back(NumElems); 3426 for (unsigned i = 1; i != NumElems; ++i) 3427 Mask.push_back(i); 3428 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3429} 3430 3431/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3432static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3433 SDValue V2) { 3434 unsigned NumElems = VT.getVectorNumElements(); 3435 SmallVector<int, 8> Mask; 3436 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3437 Mask.push_back(i); 3438 Mask.push_back(i + NumElems); 3439 } 3440 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3441} 3442 3443/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3444static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3445 SDValue V2) { 3446 unsigned NumElems = VT.getVectorNumElements(); 3447 unsigned Half = NumElems/2; 3448 SmallVector<int, 8> Mask; 3449 for (unsigned i = 0; i != Half; ++i) { 3450 Mask.push_back(i + Half); 3451 Mask.push_back(i + NumElems + Half); 3452 } 3453 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3454} 3455 3456/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3457static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3458 bool HasSSE2) { 3459 if (SV->getValueType(0).getVectorNumElements() <= 4) 3460 return SDValue(SV, 0); 3461 3462 EVT PVT = MVT::v4f32; 3463 EVT VT = SV->getValueType(0); 3464 DebugLoc dl = SV->getDebugLoc(); 3465 SDValue V1 = SV->getOperand(0); 3466 int NumElems = VT.getVectorNumElements(); 3467 int EltNo = SV->getSplatIndex(); 3468 3469 // unpack elements to the correct location 3470 while (NumElems > 4) { 3471 if (EltNo < NumElems/2) { 3472 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3473 } else { 3474 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3475 EltNo -= NumElems/2; 3476 } 3477 NumElems >>= 1; 3478 } 3479 3480 // Perform the splat. 3481 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3482 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3483 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3484 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3485} 3486 3487/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3488/// vector of zero or undef vector. This produces a shuffle where the low 3489/// element of V2 is swizzled into the zero/undef vector, landing at element 3490/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3491static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3492 bool isZero, bool HasSSE2, 3493 SelectionDAG &DAG) { 3494 EVT VT = V2.getValueType(); 3495 SDValue V1 = isZero 3496 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3497 unsigned NumElems = VT.getVectorNumElements(); 3498 SmallVector<int, 16> MaskVec; 3499 for (unsigned i = 0; i != NumElems; ++i) 3500 // If this is the insertion idx, put the low elt of V2 here. 3501 MaskVec.push_back(i == Idx ? NumElems : i); 3502 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3503} 3504 3505/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3506/// a shuffle that is zero. 3507static 3508unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3509 bool Low, SelectionDAG &DAG) { 3510 unsigned NumZeros = 0; 3511 for (int i = 0; i < NumElems; ++i) { 3512 unsigned Index = Low ? i : NumElems-i-1; 3513 int Idx = SVOp->getMaskElt(Index); 3514 if (Idx < 0) { 3515 ++NumZeros; 3516 continue; 3517 } 3518 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3519 if (Elt.getNode() && X86::isZeroNode(Elt)) 3520 ++NumZeros; 3521 else 3522 break; 3523 } 3524 return NumZeros; 3525} 3526 3527/// isVectorShift - Returns true if the shuffle can be implemented as a 3528/// logical left or right shift of a vector. 3529/// FIXME: split into pslldqi, psrldqi, palignr variants. 3530static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3531 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3532 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3533 3534 isLeft = true; 3535 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3536 if (!NumZeros) { 3537 isLeft = false; 3538 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3539 if (!NumZeros) 3540 return false; 3541 } 3542 bool SeenV1 = false; 3543 bool SeenV2 = false; 3544 for (unsigned i = NumZeros; i < NumElems; ++i) { 3545 unsigned Val = isLeft ? (i - NumZeros) : i; 3546 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3547 if (Idx_ < 0) 3548 continue; 3549 unsigned Idx = (unsigned) Idx_; 3550 if (Idx < NumElems) 3551 SeenV1 = true; 3552 else { 3553 Idx -= NumElems; 3554 SeenV2 = true; 3555 } 3556 if (Idx != Val) 3557 return false; 3558 } 3559 if (SeenV1 && SeenV2) 3560 return false; 3561 3562 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3563 ShAmt = NumZeros; 3564 return true; 3565} 3566 3567 3568/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3569/// 3570static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3571 unsigned NumNonZero, unsigned NumZero, 3572 SelectionDAG &DAG, 3573 const TargetLowering &TLI) { 3574 if (NumNonZero > 8) 3575 return SDValue(); 3576 3577 DebugLoc dl = Op.getDebugLoc(); 3578 SDValue V(0, 0); 3579 bool First = true; 3580 for (unsigned i = 0; i < 16; ++i) { 3581 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3582 if (ThisIsNonZero && First) { 3583 if (NumZero) 3584 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3585 else 3586 V = DAG.getUNDEF(MVT::v8i16); 3587 First = false; 3588 } 3589 3590 if ((i & 1) != 0) { 3591 SDValue ThisElt(0, 0), LastElt(0, 0); 3592 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3593 if (LastIsNonZero) { 3594 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3595 MVT::i16, Op.getOperand(i-1)); 3596 } 3597 if (ThisIsNonZero) { 3598 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3599 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3600 ThisElt, DAG.getConstant(8, MVT::i8)); 3601 if (LastIsNonZero) 3602 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3603 } else 3604 ThisElt = LastElt; 3605 3606 if (ThisElt.getNode()) 3607 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3608 DAG.getIntPtrConstant(i/2)); 3609 } 3610 } 3611 3612 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3613} 3614 3615/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3616/// 3617static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3618 unsigned NumNonZero, unsigned NumZero, 3619 SelectionDAG &DAG, 3620 const TargetLowering &TLI) { 3621 if (NumNonZero > 4) 3622 return SDValue(); 3623 3624 DebugLoc dl = Op.getDebugLoc(); 3625 SDValue V(0, 0); 3626 bool First = true; 3627 for (unsigned i = 0; i < 8; ++i) { 3628 bool isNonZero = (NonZeros & (1 << i)) != 0; 3629 if (isNonZero) { 3630 if (First) { 3631 if (NumZero) 3632 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3633 else 3634 V = DAG.getUNDEF(MVT::v8i16); 3635 First = false; 3636 } 3637 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3638 MVT::v8i16, V, Op.getOperand(i), 3639 DAG.getIntPtrConstant(i)); 3640 } 3641 } 3642 3643 return V; 3644} 3645 3646/// getVShift - Return a vector logical shift node. 3647/// 3648static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3649 unsigned NumBits, SelectionDAG &DAG, 3650 const TargetLowering &TLI, DebugLoc dl) { 3651 bool isMMX = VT.getSizeInBits() == 64; 3652 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3653 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3654 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3655 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3656 DAG.getNode(Opc, dl, ShVT, SrcOp, 3657 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3658} 3659 3660SDValue 3661X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3662 SelectionDAG &DAG) const { 3663 3664 // Check if the scalar load can be widened into a vector load. And if 3665 // the address is "base + cst" see if the cst can be "absorbed" into 3666 // the shuffle mask. 3667 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3668 SDValue Ptr = LD->getBasePtr(); 3669 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3670 return SDValue(); 3671 EVT PVT = LD->getValueType(0); 3672 if (PVT != MVT::i32 && PVT != MVT::f32) 3673 return SDValue(); 3674 3675 int FI = -1; 3676 int64_t Offset = 0; 3677 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3678 FI = FINode->getIndex(); 3679 Offset = 0; 3680 } else if (Ptr.getOpcode() == ISD::ADD && 3681 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3682 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3683 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3684 Offset = Ptr.getConstantOperandVal(1); 3685 Ptr = Ptr.getOperand(0); 3686 } else { 3687 return SDValue(); 3688 } 3689 3690 SDValue Chain = LD->getChain(); 3691 // Make sure the stack object alignment is at least 16. 3692 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3693 if (DAG.InferPtrAlignment(Ptr) < 16) { 3694 if (MFI->isFixedObjectIndex(FI)) { 3695 // Can't change the alignment. FIXME: It's possible to compute 3696 // the exact stack offset and reference FI + adjust offset instead. 3697 // If someone *really* cares about this. That's the way to implement it. 3698 return SDValue(); 3699 } else { 3700 MFI->setObjectAlignment(FI, 16); 3701 } 3702 } 3703 3704 // (Offset % 16) must be multiple of 4. Then address is then 3705 // Ptr + (Offset & ~15). 3706 if (Offset < 0) 3707 return SDValue(); 3708 if ((Offset % 16) & 3) 3709 return SDValue(); 3710 int64_t StartOffset = Offset & ~15; 3711 if (StartOffset) 3712 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3713 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3714 3715 int EltNo = (Offset - StartOffset) >> 2; 3716 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3717 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3718 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3719 false, false, 0); 3720 // Canonicalize it to a v4i32 shuffle. 3721 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3722 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3723 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3724 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3725 } 3726 3727 return SDValue(); 3728} 3729 3730/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 3731/// vector of type 'VT', see if the elements can be replaced by a single large 3732/// load which has the same value as a build_vector whose operands are 'elts'. 3733/// 3734/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 3735/// 3736/// FIXME: we'd also like to handle the case where the last elements are zero 3737/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 3738/// There's even a handy isZeroNode for that purpose. 3739static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 3740 DebugLoc &dl, SelectionDAG &DAG) { 3741 EVT EltVT = VT.getVectorElementType(); 3742 unsigned NumElems = Elts.size(); 3743 3744 LoadSDNode *LDBase = NULL; 3745 unsigned LastLoadedElt = -1U; 3746 3747 // For each element in the initializer, see if we've found a load or an undef. 3748 // If we don't find an initial load element, or later load elements are 3749 // non-consecutive, bail out. 3750 for (unsigned i = 0; i < NumElems; ++i) { 3751 SDValue Elt = Elts[i]; 3752 3753 if (!Elt.getNode() || 3754 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 3755 return SDValue(); 3756 if (!LDBase) { 3757 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 3758 return SDValue(); 3759 LDBase = cast<LoadSDNode>(Elt.getNode()); 3760 LastLoadedElt = i; 3761 continue; 3762 } 3763 if (Elt.getOpcode() == ISD::UNDEF) 3764 continue; 3765 3766 LoadSDNode *LD = cast<LoadSDNode>(Elt); 3767 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 3768 return SDValue(); 3769 LastLoadedElt = i; 3770 } 3771 3772 // If we have found an entire vector of loads and undefs, then return a large 3773 // load of the entire vector width starting at the base pointer. If we found 3774 // consecutive loads for the low half, generate a vzext_load node. 3775 if (LastLoadedElt == NumElems - 1) { 3776 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 3777 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3778 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3779 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 3780 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3781 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3782 LDBase->isVolatile(), LDBase->isNonTemporal(), 3783 LDBase->getAlignment()); 3784 } else if (NumElems == 4 && LastLoadedElt == 1) { 3785 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 3786 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 3787 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 3788 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 3789 } 3790 return SDValue(); 3791} 3792 3793SDValue 3794X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 3795 DebugLoc dl = Op.getDebugLoc(); 3796 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3797 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3798 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3799 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3800 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3801 // eliminated on x86-32 hosts. 3802 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3803 return Op; 3804 3805 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3806 return getOnesVector(Op.getValueType(), DAG, dl); 3807 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3808 } 3809 3810 EVT VT = Op.getValueType(); 3811 EVT ExtVT = VT.getVectorElementType(); 3812 unsigned EVTBits = ExtVT.getSizeInBits(); 3813 3814 unsigned NumElems = Op.getNumOperands(); 3815 unsigned NumZero = 0; 3816 unsigned NumNonZero = 0; 3817 unsigned NonZeros = 0; 3818 bool IsAllConstants = true; 3819 SmallSet<SDValue, 8> Values; 3820 for (unsigned i = 0; i < NumElems; ++i) { 3821 SDValue Elt = Op.getOperand(i); 3822 if (Elt.getOpcode() == ISD::UNDEF) 3823 continue; 3824 Values.insert(Elt); 3825 if (Elt.getOpcode() != ISD::Constant && 3826 Elt.getOpcode() != ISD::ConstantFP) 3827 IsAllConstants = false; 3828 if (X86::isZeroNode(Elt)) 3829 NumZero++; 3830 else { 3831 NonZeros |= (1 << i); 3832 NumNonZero++; 3833 } 3834 } 3835 3836 if (NumNonZero == 0) { 3837 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3838 return DAG.getUNDEF(VT); 3839 } 3840 3841 // Special case for single non-zero, non-undef, element. 3842 if (NumNonZero == 1) { 3843 unsigned Idx = CountTrailingZeros_32(NonZeros); 3844 SDValue Item = Op.getOperand(Idx); 3845 3846 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3847 // the value are obviously zero, truncate the value to i32 and do the 3848 // insertion that way. Only do this if the value is non-constant or if the 3849 // value is a constant being inserted into element 0. It is cheaper to do 3850 // a constant pool load than it is to do a movd + shuffle. 3851 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3852 (!IsAllConstants || Idx == 0)) { 3853 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3854 // Handle MMX and SSE both. 3855 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3856 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3857 3858 // Truncate the value (which may itself be a constant) to i32, and 3859 // convert it to a vector with movd (S2V+shuffle to zero extend). 3860 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3861 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3862 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3863 Subtarget->hasSSE2(), DAG); 3864 3865 // Now we have our 32-bit value zero extended in the low element of 3866 // a vector. If Idx != 0, swizzle it into place. 3867 if (Idx != 0) { 3868 SmallVector<int, 4> Mask; 3869 Mask.push_back(Idx); 3870 for (unsigned i = 1; i != VecElts; ++i) 3871 Mask.push_back(i); 3872 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3873 DAG.getUNDEF(Item.getValueType()), 3874 &Mask[0]); 3875 } 3876 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3877 } 3878 } 3879 3880 // If we have a constant or non-constant insertion into the low element of 3881 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3882 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3883 // depending on what the source datatype is. 3884 if (Idx == 0) { 3885 if (NumZero == 0) { 3886 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3887 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3888 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3890 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3891 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3892 DAG); 3893 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3894 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3895 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3896 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3897 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3898 Subtarget->hasSSE2(), DAG); 3899 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3900 } 3901 } 3902 3903 // Is it a vector logical left shift? 3904 if (NumElems == 2 && Idx == 1 && 3905 X86::isZeroNode(Op.getOperand(0)) && 3906 !X86::isZeroNode(Op.getOperand(1))) { 3907 unsigned NumBits = VT.getSizeInBits(); 3908 return getVShift(true, VT, 3909 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3910 VT, Op.getOperand(1)), 3911 NumBits/2, DAG, *this, dl); 3912 } 3913 3914 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3915 return SDValue(); 3916 3917 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3918 // is a non-constant being inserted into an element other than the low one, 3919 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3920 // movd/movss) to move this into the low element, then shuffle it into 3921 // place. 3922 if (EVTBits == 32) { 3923 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3924 3925 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3926 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3927 Subtarget->hasSSE2(), DAG); 3928 SmallVector<int, 8> MaskVec; 3929 for (unsigned i = 0; i < NumElems; i++) 3930 MaskVec.push_back(i == Idx ? 0 : 1); 3931 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3932 } 3933 } 3934 3935 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3936 if (Values.size() == 1) { 3937 if (EVTBits == 32) { 3938 // Instead of a shuffle like this: 3939 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3940 // Check if it's possible to issue this instead. 3941 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3942 unsigned Idx = CountTrailingZeros_32(NonZeros); 3943 SDValue Item = Op.getOperand(Idx); 3944 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3945 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3946 } 3947 return SDValue(); 3948 } 3949 3950 // A vector full of immediates; various special cases are already 3951 // handled, so this is best done with a single constant-pool load. 3952 if (IsAllConstants) 3953 return SDValue(); 3954 3955 // Let legalizer expand 2-wide build_vectors. 3956 if (EVTBits == 64) { 3957 if (NumNonZero == 1) { 3958 // One half is zero or undef. 3959 unsigned Idx = CountTrailingZeros_32(NonZeros); 3960 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3961 Op.getOperand(Idx)); 3962 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3963 Subtarget->hasSSE2(), DAG); 3964 } 3965 return SDValue(); 3966 } 3967 3968 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3969 if (EVTBits == 8 && NumElems == 16) { 3970 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3971 *this); 3972 if (V.getNode()) return V; 3973 } 3974 3975 if (EVTBits == 16 && NumElems == 8) { 3976 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3977 *this); 3978 if (V.getNode()) return V; 3979 } 3980 3981 // If element VT is == 32 bits, turn it into a number of shuffles. 3982 SmallVector<SDValue, 8> V; 3983 V.resize(NumElems); 3984 if (NumElems == 4 && NumZero > 0) { 3985 for (unsigned i = 0; i < 4; ++i) { 3986 bool isZero = !(NonZeros & (1 << i)); 3987 if (isZero) 3988 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3989 else 3990 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3991 } 3992 3993 for (unsigned i = 0; i < 2; ++i) { 3994 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3995 default: break; 3996 case 0: 3997 V[i] = V[i*2]; // Must be a zero vector. 3998 break; 3999 case 1: 4000 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4001 break; 4002 case 2: 4003 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4004 break; 4005 case 3: 4006 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4007 break; 4008 } 4009 } 4010 4011 SmallVector<int, 8> MaskVec; 4012 bool Reverse = (NonZeros & 0x3) == 2; 4013 for (unsigned i = 0; i < 2; ++i) 4014 MaskVec.push_back(Reverse ? 1-i : i); 4015 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4016 for (unsigned i = 0; i < 2; ++i) 4017 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4018 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4019 } 4020 4021 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4022 // Check for a build vector of consecutive loads. 4023 for (unsigned i = 0; i < NumElems; ++i) 4024 V[i] = Op.getOperand(i); 4025 4026 // Check for elements which are consecutive loads. 4027 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4028 if (LD.getNode()) 4029 return LD; 4030 4031 // For SSE 4.1, use inserts into undef. 4032 if (getSubtarget()->hasSSE41()) { 4033 V[0] = DAG.getUNDEF(VT); 4034 for (unsigned i = 0; i < NumElems; ++i) 4035 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4036 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 4037 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4038 return V[0]; 4039 } 4040 4041 // Otherwise, expand into a number of unpckl* 4042 // e.g. for v4f32 4043 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 4044 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 4045 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 4046 for (unsigned i = 0; i < NumElems; ++i) 4047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4048 NumElems >>= 1; 4049 while (NumElems != 0) { 4050 for (unsigned i = 0; i < NumElems; ++i) 4051 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 4052 NumElems >>= 1; 4053 } 4054 return V[0]; 4055 } 4056 return SDValue(); 4057} 4058 4059SDValue 4060X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 4061 // We support concatenate two MMX registers and place them in a MMX 4062 // register. This is better than doing a stack convert. 4063 DebugLoc dl = Op.getDebugLoc(); 4064 EVT ResVT = Op.getValueType(); 4065 assert(Op.getNumOperands() == 2); 4066 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 4067 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 4068 int Mask[2]; 4069 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 4070 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4071 InVec = Op.getOperand(1); 4072 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4073 unsigned NumElts = ResVT.getVectorNumElements(); 4074 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4075 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 4076 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 4077 } else { 4078 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 4079 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4080 Mask[0] = 0; Mask[1] = 2; 4081 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 4082 } 4083 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4084} 4085 4086// v8i16 shuffles - Prefer shuffles in the following order: 4087// 1. [all] pshuflw, pshufhw, optional move 4088// 2. [ssse3] 1 x pshufb 4089// 3. [ssse3] 2 x pshufb + 1 x por 4090// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4091static 4092SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 4093 SelectionDAG &DAG, 4094 const X86TargetLowering &TLI) { 4095 SDValue V1 = SVOp->getOperand(0); 4096 SDValue V2 = SVOp->getOperand(1); 4097 DebugLoc dl = SVOp->getDebugLoc(); 4098 SmallVector<int, 8> MaskVals; 4099 4100 // Determine if more than 1 of the words in each of the low and high quadwords 4101 // of the result come from the same quadword of one of the two inputs. Undef 4102 // mask values count as coming from any quadword, for better codegen. 4103 SmallVector<unsigned, 4> LoQuad(4); 4104 SmallVector<unsigned, 4> HiQuad(4); 4105 BitVector InputQuads(4); 4106 for (unsigned i = 0; i < 8; ++i) { 4107 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4108 int EltIdx = SVOp->getMaskElt(i); 4109 MaskVals.push_back(EltIdx); 4110 if (EltIdx < 0) { 4111 ++Quad[0]; 4112 ++Quad[1]; 4113 ++Quad[2]; 4114 ++Quad[3]; 4115 continue; 4116 } 4117 ++Quad[EltIdx / 4]; 4118 InputQuads.set(EltIdx / 4); 4119 } 4120 4121 int BestLoQuad = -1; 4122 unsigned MaxQuad = 1; 4123 for (unsigned i = 0; i < 4; ++i) { 4124 if (LoQuad[i] > MaxQuad) { 4125 BestLoQuad = i; 4126 MaxQuad = LoQuad[i]; 4127 } 4128 } 4129 4130 int BestHiQuad = -1; 4131 MaxQuad = 1; 4132 for (unsigned i = 0; i < 4; ++i) { 4133 if (HiQuad[i] > MaxQuad) { 4134 BestHiQuad = i; 4135 MaxQuad = HiQuad[i]; 4136 } 4137 } 4138 4139 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4140 // of the two input vectors, shuffle them into one input vector so only a 4141 // single pshufb instruction is necessary. If There are more than 2 input 4142 // quads, disable the next transformation since it does not help SSSE3. 4143 bool V1Used = InputQuads[0] || InputQuads[1]; 4144 bool V2Used = InputQuads[2] || InputQuads[3]; 4145 if (TLI.getSubtarget()->hasSSSE3()) { 4146 if (InputQuads.count() == 2 && V1Used && V2Used) { 4147 BestLoQuad = InputQuads.find_first(); 4148 BestHiQuad = InputQuads.find_next(BestLoQuad); 4149 } 4150 if (InputQuads.count() > 2) { 4151 BestLoQuad = -1; 4152 BestHiQuad = -1; 4153 } 4154 } 4155 4156 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4157 // the shuffle mask. If a quad is scored as -1, that means that it contains 4158 // words from all 4 input quadwords. 4159 SDValue NewV; 4160 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4161 SmallVector<int, 8> MaskV; 4162 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4163 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4164 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4165 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 4166 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 4167 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 4168 4169 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4170 // source words for the shuffle, to aid later transformations. 4171 bool AllWordsInNewV = true; 4172 bool InOrder[2] = { true, true }; 4173 for (unsigned i = 0; i != 8; ++i) { 4174 int idx = MaskVals[i]; 4175 if (idx != (int)i) 4176 InOrder[i/4] = false; 4177 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4178 continue; 4179 AllWordsInNewV = false; 4180 break; 4181 } 4182 4183 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4184 if (AllWordsInNewV) { 4185 for (int i = 0; i != 8; ++i) { 4186 int idx = MaskVals[i]; 4187 if (idx < 0) 4188 continue; 4189 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4190 if ((idx != i) && idx < 4) 4191 pshufhw = false; 4192 if ((idx != i) && idx > 3) 4193 pshuflw = false; 4194 } 4195 V1 = NewV; 4196 V2Used = false; 4197 BestLoQuad = 0; 4198 BestHiQuad = 1; 4199 } 4200 4201 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4202 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4203 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4204 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4205 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4206 } 4207 } 4208 4209 // If we have SSSE3, and all words of the result are from 1 input vector, 4210 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4211 // is present, fall back to case 4. 4212 if (TLI.getSubtarget()->hasSSSE3()) { 4213 SmallVector<SDValue,16> pshufbMask; 4214 4215 // If we have elements from both input vectors, set the high bit of the 4216 // shuffle mask element to zero out elements that come from V2 in the V1 4217 // mask, and elements that come from V1 in the V2 mask, so that the two 4218 // results can be OR'd together. 4219 bool TwoInputs = V1Used && V2Used; 4220 for (unsigned i = 0; i != 8; ++i) { 4221 int EltIdx = MaskVals[i] * 2; 4222 if (TwoInputs && (EltIdx >= 16)) { 4223 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4224 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4225 continue; 4226 } 4227 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4228 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4229 } 4230 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4231 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4232 DAG.getNode(ISD::BUILD_VECTOR, dl, 4233 MVT::v16i8, &pshufbMask[0], 16)); 4234 if (!TwoInputs) 4235 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4236 4237 // Calculate the shuffle mask for the second input, shuffle it, and 4238 // OR it with the first shuffled input. 4239 pshufbMask.clear(); 4240 for (unsigned i = 0; i != 8; ++i) { 4241 int EltIdx = MaskVals[i] * 2; 4242 if (EltIdx < 16) { 4243 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4244 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4245 continue; 4246 } 4247 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4248 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4249 } 4250 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4251 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4252 DAG.getNode(ISD::BUILD_VECTOR, dl, 4253 MVT::v16i8, &pshufbMask[0], 16)); 4254 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4255 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4256 } 4257 4258 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4259 // and update MaskVals with new element order. 4260 BitVector InOrder(8); 4261 if (BestLoQuad >= 0) { 4262 SmallVector<int, 8> MaskV; 4263 for (int i = 0; i != 4; ++i) { 4264 int idx = MaskVals[i]; 4265 if (idx < 0) { 4266 MaskV.push_back(-1); 4267 InOrder.set(i); 4268 } else if ((idx / 4) == BestLoQuad) { 4269 MaskV.push_back(idx & 3); 4270 InOrder.set(i); 4271 } else { 4272 MaskV.push_back(-1); 4273 } 4274 } 4275 for (unsigned i = 4; i != 8; ++i) 4276 MaskV.push_back(i); 4277 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4278 &MaskV[0]); 4279 } 4280 4281 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4282 // and update MaskVals with the new element order. 4283 if (BestHiQuad >= 0) { 4284 SmallVector<int, 8> MaskV; 4285 for (unsigned i = 0; i != 4; ++i) 4286 MaskV.push_back(i); 4287 for (unsigned i = 4; i != 8; ++i) { 4288 int idx = MaskVals[i]; 4289 if (idx < 0) { 4290 MaskV.push_back(-1); 4291 InOrder.set(i); 4292 } else if ((idx / 4) == BestHiQuad) { 4293 MaskV.push_back((idx & 3) + 4); 4294 InOrder.set(i); 4295 } else { 4296 MaskV.push_back(-1); 4297 } 4298 } 4299 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4300 &MaskV[0]); 4301 } 4302 4303 // In case BestHi & BestLo were both -1, which means each quadword has a word 4304 // from each of the four input quadwords, calculate the InOrder bitvector now 4305 // before falling through to the insert/extract cleanup. 4306 if (BestLoQuad == -1 && BestHiQuad == -1) { 4307 NewV = V1; 4308 for (int i = 0; i != 8; ++i) 4309 if (MaskVals[i] < 0 || MaskVals[i] == i) 4310 InOrder.set(i); 4311 } 4312 4313 // The other elements are put in the right place using pextrw and pinsrw. 4314 for (unsigned i = 0; i != 8; ++i) { 4315 if (InOrder[i]) 4316 continue; 4317 int EltIdx = MaskVals[i]; 4318 if (EltIdx < 0) 4319 continue; 4320 SDValue ExtOp = (EltIdx < 8) 4321 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4322 DAG.getIntPtrConstant(EltIdx)) 4323 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4324 DAG.getIntPtrConstant(EltIdx - 8)); 4325 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4326 DAG.getIntPtrConstant(i)); 4327 } 4328 return NewV; 4329} 4330 4331// v16i8 shuffles - Prefer shuffles in the following order: 4332// 1. [ssse3] 1 x pshufb 4333// 2. [ssse3] 2 x pshufb + 1 x por 4334// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4335static 4336SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4337 SelectionDAG &DAG, 4338 const X86TargetLowering &TLI) { 4339 SDValue V1 = SVOp->getOperand(0); 4340 SDValue V2 = SVOp->getOperand(1); 4341 DebugLoc dl = SVOp->getDebugLoc(); 4342 SmallVector<int, 16> MaskVals; 4343 SVOp->getMask(MaskVals); 4344 4345 // If we have SSSE3, case 1 is generated when all result bytes come from 4346 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4347 // present, fall back to case 3. 4348 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4349 bool V1Only = true; 4350 bool V2Only = true; 4351 for (unsigned i = 0; i < 16; ++i) { 4352 int EltIdx = MaskVals[i]; 4353 if (EltIdx < 0) 4354 continue; 4355 if (EltIdx < 16) 4356 V2Only = false; 4357 else 4358 V1Only = false; 4359 } 4360 4361 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4362 if (TLI.getSubtarget()->hasSSSE3()) { 4363 SmallVector<SDValue,16> pshufbMask; 4364 4365 // If all result elements are from one input vector, then only translate 4366 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4367 // 4368 // Otherwise, we have elements from both input vectors, and must zero out 4369 // elements that come from V2 in the first mask, and V1 in the second mask 4370 // so that we can OR them together. 4371 bool TwoInputs = !(V1Only || V2Only); 4372 for (unsigned i = 0; i != 16; ++i) { 4373 int EltIdx = MaskVals[i]; 4374 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4375 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4376 continue; 4377 } 4378 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4379 } 4380 // If all the elements are from V2, assign it to V1 and return after 4381 // building the first pshufb. 4382 if (V2Only) 4383 V1 = V2; 4384 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4385 DAG.getNode(ISD::BUILD_VECTOR, dl, 4386 MVT::v16i8, &pshufbMask[0], 16)); 4387 if (!TwoInputs) 4388 return V1; 4389 4390 // Calculate the shuffle mask for the second input, shuffle it, and 4391 // OR it with the first shuffled input. 4392 pshufbMask.clear(); 4393 for (unsigned i = 0; i != 16; ++i) { 4394 int EltIdx = MaskVals[i]; 4395 if (EltIdx < 16) { 4396 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4397 continue; 4398 } 4399 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4400 } 4401 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4402 DAG.getNode(ISD::BUILD_VECTOR, dl, 4403 MVT::v16i8, &pshufbMask[0], 16)); 4404 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4405 } 4406 4407 // No SSSE3 - Calculate in place words and then fix all out of place words 4408 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4409 // the 16 different words that comprise the two doublequadword input vectors. 4410 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4411 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4412 SDValue NewV = V2Only ? V2 : V1; 4413 for (int i = 0; i != 8; ++i) { 4414 int Elt0 = MaskVals[i*2]; 4415 int Elt1 = MaskVals[i*2+1]; 4416 4417 // This word of the result is all undef, skip it. 4418 if (Elt0 < 0 && Elt1 < 0) 4419 continue; 4420 4421 // This word of the result is already in the correct place, skip it. 4422 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4423 continue; 4424 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4425 continue; 4426 4427 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4428 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4429 SDValue InsElt; 4430 4431 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4432 // using a single extract together, load it and store it. 4433 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4434 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4435 DAG.getIntPtrConstant(Elt1 / 2)); 4436 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4437 DAG.getIntPtrConstant(i)); 4438 continue; 4439 } 4440 4441 // If Elt1 is defined, extract it from the appropriate source. If the 4442 // source byte is not also odd, shift the extracted word left 8 bits 4443 // otherwise clear the bottom 8 bits if we need to do an or. 4444 if (Elt1 >= 0) { 4445 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4446 DAG.getIntPtrConstant(Elt1 / 2)); 4447 if ((Elt1 & 1) == 0) 4448 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4449 DAG.getConstant(8, TLI.getShiftAmountTy())); 4450 else if (Elt0 >= 0) 4451 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4452 DAG.getConstant(0xFF00, MVT::i16)); 4453 } 4454 // If Elt0 is defined, extract it from the appropriate source. If the 4455 // source byte is not also even, shift the extracted word right 8 bits. If 4456 // Elt1 was also defined, OR the extracted values together before 4457 // inserting them in the result. 4458 if (Elt0 >= 0) { 4459 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4460 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4461 if ((Elt0 & 1) != 0) 4462 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4463 DAG.getConstant(8, TLI.getShiftAmountTy())); 4464 else if (Elt1 >= 0) 4465 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4466 DAG.getConstant(0x00FF, MVT::i16)); 4467 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4468 : InsElt0; 4469 } 4470 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4471 DAG.getIntPtrConstant(i)); 4472 } 4473 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4474} 4475 4476/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4477/// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be 4478/// done when every pair / quad of shuffle mask elements point to elements in 4479/// the right sequence. e.g. 4480/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4481static 4482SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4483 SelectionDAG &DAG, 4484 const TargetLowering &TLI, DebugLoc dl) { 4485 EVT VT = SVOp->getValueType(0); 4486 SDValue V1 = SVOp->getOperand(0); 4487 SDValue V2 = SVOp->getOperand(1); 4488 unsigned NumElems = VT.getVectorNumElements(); 4489 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4490 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4491 EVT NewVT = MaskVT; 4492 switch (VT.getSimpleVT().SimpleTy) { 4493 default: assert(false && "Unexpected!"); 4494 case MVT::v4f32: NewVT = MVT::v2f64; break; 4495 case MVT::v4i32: NewVT = MVT::v2i64; break; 4496 case MVT::v8i16: NewVT = MVT::v4i32; break; 4497 case MVT::v16i8: NewVT = MVT::v4i32; break; 4498 } 4499 4500 if (NewWidth == 2) { 4501 if (VT.isInteger()) 4502 NewVT = MVT::v2i64; 4503 else 4504 NewVT = MVT::v2f64; 4505 } 4506 int Scale = NumElems / NewWidth; 4507 SmallVector<int, 8> MaskVec; 4508 for (unsigned i = 0; i < NumElems; i += Scale) { 4509 int StartIdx = -1; 4510 for (int j = 0; j < Scale; ++j) { 4511 int EltIdx = SVOp->getMaskElt(i+j); 4512 if (EltIdx < 0) 4513 continue; 4514 if (StartIdx == -1) 4515 StartIdx = EltIdx - (EltIdx % Scale); 4516 if (EltIdx != StartIdx + j) 4517 return SDValue(); 4518 } 4519 if (StartIdx == -1) 4520 MaskVec.push_back(-1); 4521 else 4522 MaskVec.push_back(StartIdx / Scale); 4523 } 4524 4525 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4526 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4527 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4528} 4529 4530/// getVZextMovL - Return a zero-extending vector move low node. 4531/// 4532static SDValue getVZextMovL(EVT VT, EVT OpVT, 4533 SDValue SrcOp, SelectionDAG &DAG, 4534 const X86Subtarget *Subtarget, DebugLoc dl) { 4535 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4536 LoadSDNode *LD = NULL; 4537 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4538 LD = dyn_cast<LoadSDNode>(SrcOp); 4539 if (!LD) { 4540 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4541 // instead. 4542 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4543 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4544 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4545 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4546 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4547 // PR2108 4548 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4549 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4550 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4551 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4552 OpVT, 4553 SrcOp.getOperand(0) 4554 .getOperand(0)))); 4555 } 4556 } 4557 } 4558 4559 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4560 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4561 DAG.getNode(ISD::BIT_CONVERT, dl, 4562 OpVT, SrcOp))); 4563} 4564 4565/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4566/// shuffles. 4567static SDValue 4568LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4569 SDValue V1 = SVOp->getOperand(0); 4570 SDValue V2 = SVOp->getOperand(1); 4571 DebugLoc dl = SVOp->getDebugLoc(); 4572 EVT VT = SVOp->getValueType(0); 4573 4574 SmallVector<std::pair<int, int>, 8> Locs; 4575 Locs.resize(4); 4576 SmallVector<int, 8> Mask1(4U, -1); 4577 SmallVector<int, 8> PermMask; 4578 SVOp->getMask(PermMask); 4579 4580 unsigned NumHi = 0; 4581 unsigned NumLo = 0; 4582 for (unsigned i = 0; i != 4; ++i) { 4583 int Idx = PermMask[i]; 4584 if (Idx < 0) { 4585 Locs[i] = std::make_pair(-1, -1); 4586 } else { 4587 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4588 if (Idx < 4) { 4589 Locs[i] = std::make_pair(0, NumLo); 4590 Mask1[NumLo] = Idx; 4591 NumLo++; 4592 } else { 4593 Locs[i] = std::make_pair(1, NumHi); 4594 if (2+NumHi < 4) 4595 Mask1[2+NumHi] = Idx; 4596 NumHi++; 4597 } 4598 } 4599 } 4600 4601 if (NumLo <= 2 && NumHi <= 2) { 4602 // If no more than two elements come from either vector. This can be 4603 // implemented with two shuffles. First shuffle gather the elements. 4604 // The second shuffle, which takes the first shuffle as both of its 4605 // vector operands, put the elements into the right order. 4606 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4607 4608 SmallVector<int, 8> Mask2(4U, -1); 4609 4610 for (unsigned i = 0; i != 4; ++i) { 4611 if (Locs[i].first == -1) 4612 continue; 4613 else { 4614 unsigned Idx = (i < 2) ? 0 : 4; 4615 Idx += Locs[i].first * 2 + Locs[i].second; 4616 Mask2[i] = Idx; 4617 } 4618 } 4619 4620 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4621 } else if (NumLo == 3 || NumHi == 3) { 4622 // Otherwise, we must have three elements from one vector, call it X, and 4623 // one element from the other, call it Y. First, use a shufps to build an 4624 // intermediate vector with the one element from Y and the element from X 4625 // that will be in the same half in the final destination (the indexes don't 4626 // matter). Then, use a shufps to build the final vector, taking the half 4627 // containing the element from Y from the intermediate, and the other half 4628 // from X. 4629 if (NumHi == 3) { 4630 // Normalize it so the 3 elements come from V1. 4631 CommuteVectorShuffleMask(PermMask, VT); 4632 std::swap(V1, V2); 4633 } 4634 4635 // Find the element from V2. 4636 unsigned HiIndex; 4637 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4638 int Val = PermMask[HiIndex]; 4639 if (Val < 0) 4640 continue; 4641 if (Val >= 4) 4642 break; 4643 } 4644 4645 Mask1[0] = PermMask[HiIndex]; 4646 Mask1[1] = -1; 4647 Mask1[2] = PermMask[HiIndex^1]; 4648 Mask1[3] = -1; 4649 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4650 4651 if (HiIndex >= 2) { 4652 Mask1[0] = PermMask[0]; 4653 Mask1[1] = PermMask[1]; 4654 Mask1[2] = HiIndex & 1 ? 6 : 4; 4655 Mask1[3] = HiIndex & 1 ? 4 : 6; 4656 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4657 } else { 4658 Mask1[0] = HiIndex & 1 ? 2 : 0; 4659 Mask1[1] = HiIndex & 1 ? 0 : 2; 4660 Mask1[2] = PermMask[2]; 4661 Mask1[3] = PermMask[3]; 4662 if (Mask1[2] >= 0) 4663 Mask1[2] += 4; 4664 if (Mask1[3] >= 0) 4665 Mask1[3] += 4; 4666 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4667 } 4668 } 4669 4670 // Break it into (shuffle shuffle_hi, shuffle_lo). 4671 Locs.clear(); 4672 SmallVector<int,8> LoMask(4U, -1); 4673 SmallVector<int,8> HiMask(4U, -1); 4674 4675 SmallVector<int,8> *MaskPtr = &LoMask; 4676 unsigned MaskIdx = 0; 4677 unsigned LoIdx = 0; 4678 unsigned HiIdx = 2; 4679 for (unsigned i = 0; i != 4; ++i) { 4680 if (i == 2) { 4681 MaskPtr = &HiMask; 4682 MaskIdx = 1; 4683 LoIdx = 0; 4684 HiIdx = 2; 4685 } 4686 int Idx = PermMask[i]; 4687 if (Idx < 0) { 4688 Locs[i] = std::make_pair(-1, -1); 4689 } else if (Idx < 4) { 4690 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4691 (*MaskPtr)[LoIdx] = Idx; 4692 LoIdx++; 4693 } else { 4694 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4695 (*MaskPtr)[HiIdx] = Idx; 4696 HiIdx++; 4697 } 4698 } 4699 4700 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4701 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4702 SmallVector<int, 8> MaskOps; 4703 for (unsigned i = 0; i != 4; ++i) { 4704 if (Locs[i].first == -1) { 4705 MaskOps.push_back(-1); 4706 } else { 4707 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4708 MaskOps.push_back(Idx); 4709 } 4710 } 4711 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4712} 4713 4714SDValue 4715X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 4716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4717 SDValue V1 = Op.getOperand(0); 4718 SDValue V2 = Op.getOperand(1); 4719 EVT VT = Op.getValueType(); 4720 DebugLoc dl = Op.getDebugLoc(); 4721 unsigned NumElems = VT.getVectorNumElements(); 4722 bool isMMX = VT.getSizeInBits() == 64; 4723 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4724 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4725 bool V1IsSplat = false; 4726 bool V2IsSplat = false; 4727 4728 if (isZeroShuffle(SVOp)) 4729 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4730 4731 // Promote splats to v4f32. 4732 if (SVOp->isSplat()) { 4733 if (isMMX || NumElems < 4) 4734 return Op; 4735 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4736 } 4737 4738 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4739 // do it! 4740 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4741 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4742 if (NewOp.getNode()) 4743 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4744 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4745 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4746 // FIXME: Figure out a cleaner way to do this. 4747 // Try to make use of movq to zero out the top part. 4748 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4749 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4750 if (NewOp.getNode()) { 4751 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4752 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4753 DAG, Subtarget, dl); 4754 } 4755 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4756 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4757 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4758 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4759 DAG, Subtarget, dl); 4760 } 4761 } 4762 4763 if (X86::isPSHUFDMask(SVOp)) 4764 return Op; 4765 4766 // Check if this can be converted into a logical shift. 4767 bool isLeft = false; 4768 unsigned ShAmt = 0; 4769 SDValue ShVal; 4770 bool isShift = getSubtarget()->hasSSE2() && 4771 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4772 if (isShift && ShVal.hasOneUse()) { 4773 // If the shifted value has multiple uses, it may be cheaper to use 4774 // v_set0 + movlhps or movhlps, etc. 4775 EVT EltVT = VT.getVectorElementType(); 4776 ShAmt *= EltVT.getSizeInBits(); 4777 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4778 } 4779 4780 if (X86::isMOVLMask(SVOp)) { 4781 if (V1IsUndef) 4782 return V2; 4783 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4784 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4785 if (!isMMX) 4786 return Op; 4787 } 4788 4789 // FIXME: fold these into legal mask. 4790 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4791 X86::isMOVSLDUPMask(SVOp) || 4792 X86::isMOVHLPSMask(SVOp) || 4793 X86::isMOVLHPSMask(SVOp) || 4794 X86::isMOVLPMask(SVOp))) 4795 return Op; 4796 4797 if (ShouldXformToMOVHLPS(SVOp) || 4798 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4799 return CommuteVectorShuffle(SVOp, DAG); 4800 4801 if (isShift) { 4802 // No better options. Use a vshl / vsrl. 4803 EVT EltVT = VT.getVectorElementType(); 4804 ShAmt *= EltVT.getSizeInBits(); 4805 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4806 } 4807 4808 bool Commuted = false; 4809 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4810 // 1,1,1,1 -> v8i16 though. 4811 V1IsSplat = isSplatVector(V1.getNode()); 4812 V2IsSplat = isSplatVector(V2.getNode()); 4813 4814 // Canonicalize the splat or undef, if present, to be on the RHS. 4815 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4816 Op = CommuteVectorShuffle(SVOp, DAG); 4817 SVOp = cast<ShuffleVectorSDNode>(Op); 4818 V1 = SVOp->getOperand(0); 4819 V2 = SVOp->getOperand(1); 4820 std::swap(V1IsSplat, V2IsSplat); 4821 std::swap(V1IsUndef, V2IsUndef); 4822 Commuted = true; 4823 } 4824 4825 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4826 // Shuffling low element of v1 into undef, just return v1. 4827 if (V2IsUndef) 4828 return V1; 4829 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4830 // the instruction selector will not match, so get a canonical MOVL with 4831 // swapped operands to undo the commute. 4832 return getMOVL(DAG, dl, VT, V2, V1); 4833 } 4834 4835 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4836 X86::isUNPCKH_v_undef_Mask(SVOp) || 4837 X86::isUNPCKLMask(SVOp) || 4838 X86::isUNPCKHMask(SVOp)) 4839 return Op; 4840 4841 if (V2IsSplat) { 4842 // Normalize mask so all entries that point to V2 points to its first 4843 // element then try to match unpck{h|l} again. If match, return a 4844 // new vector_shuffle with the corrected mask. 4845 SDValue NewMask = NormalizeMask(SVOp, DAG); 4846 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4847 if (NSVOp != SVOp) { 4848 if (X86::isUNPCKLMask(NSVOp, true)) { 4849 return NewMask; 4850 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4851 return NewMask; 4852 } 4853 } 4854 } 4855 4856 if (Commuted) { 4857 // Commute is back and try unpck* again. 4858 // FIXME: this seems wrong. 4859 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4860 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4861 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4862 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4863 X86::isUNPCKLMask(NewSVOp) || 4864 X86::isUNPCKHMask(NewSVOp)) 4865 return NewOp; 4866 } 4867 4868 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4869 4870 // Normalize the node to match x86 shuffle ops if needed 4871 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4872 return CommuteVectorShuffle(SVOp, DAG); 4873 4874 // Check for legal shuffle and return? 4875 SmallVector<int, 16> PermMask; 4876 SVOp->getMask(PermMask); 4877 if (isShuffleMaskLegal(PermMask, VT)) 4878 return Op; 4879 4880 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4881 if (VT == MVT::v8i16) { 4882 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4883 if (NewOp.getNode()) 4884 return NewOp; 4885 } 4886 4887 if (VT == MVT::v16i8) { 4888 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4889 if (NewOp.getNode()) 4890 return NewOp; 4891 } 4892 4893 // Handle all 4 wide cases with a number of shuffles except for MMX. 4894 if (NumElems == 4 && !isMMX) 4895 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4896 4897 return SDValue(); 4898} 4899 4900SDValue 4901X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4902 SelectionDAG &DAG) const { 4903 EVT VT = Op.getValueType(); 4904 DebugLoc dl = Op.getDebugLoc(); 4905 if (VT.getSizeInBits() == 8) { 4906 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4907 Op.getOperand(0), Op.getOperand(1)); 4908 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4909 DAG.getValueType(VT)); 4910 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4911 } else if (VT.getSizeInBits() == 16) { 4912 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4913 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4914 if (Idx == 0) 4915 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4916 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4917 DAG.getNode(ISD::BIT_CONVERT, dl, 4918 MVT::v4i32, 4919 Op.getOperand(0)), 4920 Op.getOperand(1))); 4921 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4922 Op.getOperand(0), Op.getOperand(1)); 4923 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4924 DAG.getValueType(VT)); 4925 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4926 } else if (VT == MVT::f32) { 4927 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4928 // the result back to FR32 register. It's only worth matching if the 4929 // result has a single use which is a store or a bitcast to i32. And in 4930 // the case of a store, it's not worth it if the index is a constant 0, 4931 // because a MOVSSmr can be used instead, which is smaller and faster. 4932 if (!Op.hasOneUse()) 4933 return SDValue(); 4934 SDNode *User = *Op.getNode()->use_begin(); 4935 if ((User->getOpcode() != ISD::STORE || 4936 (isa<ConstantSDNode>(Op.getOperand(1)) && 4937 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4938 (User->getOpcode() != ISD::BIT_CONVERT || 4939 User->getValueType(0) != MVT::i32)) 4940 return SDValue(); 4941 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4942 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4943 Op.getOperand(0)), 4944 Op.getOperand(1)); 4945 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4946 } else if (VT == MVT::i32) { 4947 // ExtractPS works with constant index. 4948 if (isa<ConstantSDNode>(Op.getOperand(1))) 4949 return Op; 4950 } 4951 return SDValue(); 4952} 4953 4954 4955SDValue 4956X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 4957 SelectionDAG &DAG) const { 4958 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4959 return SDValue(); 4960 4961 if (Subtarget->hasSSE41()) { 4962 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4963 if (Res.getNode()) 4964 return Res; 4965 } 4966 4967 EVT VT = Op.getValueType(); 4968 DebugLoc dl = Op.getDebugLoc(); 4969 // TODO: handle v16i8. 4970 if (VT.getSizeInBits() == 16) { 4971 SDValue Vec = Op.getOperand(0); 4972 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4973 if (Idx == 0) 4974 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4975 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4976 DAG.getNode(ISD::BIT_CONVERT, dl, 4977 MVT::v4i32, Vec), 4978 Op.getOperand(1))); 4979 // Transform it so it match pextrw which produces a 32-bit result. 4980 EVT EltVT = MVT::i32; 4981 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4982 Op.getOperand(0), Op.getOperand(1)); 4983 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4984 DAG.getValueType(VT)); 4985 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4986 } else if (VT.getSizeInBits() == 32) { 4987 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4988 if (Idx == 0) 4989 return Op; 4990 4991 // SHUFPS the element to the lowest double word, then movss. 4992 int Mask[4] = { Idx, -1, -1, -1 }; 4993 EVT VVT = Op.getOperand(0).getValueType(); 4994 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4995 DAG.getUNDEF(VVT), Mask); 4996 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4997 DAG.getIntPtrConstant(0)); 4998 } else if (VT.getSizeInBits() == 64) { 4999 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 5000 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 5001 // to match extract_elt for f64. 5002 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5003 if (Idx == 0) 5004 return Op; 5005 5006 // UNPCKHPD the element to the lowest double word, then movsd. 5007 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 5008 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 5009 int Mask[2] = { 1, -1 }; 5010 EVT VVT = Op.getOperand(0).getValueType(); 5011 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5012 DAG.getUNDEF(VVT), Mask); 5013 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5014 DAG.getIntPtrConstant(0)); 5015 } 5016 5017 return SDValue(); 5018} 5019 5020SDValue 5021X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 5022 SelectionDAG &DAG) const { 5023 EVT VT = Op.getValueType(); 5024 EVT EltVT = VT.getVectorElementType(); 5025 DebugLoc dl = Op.getDebugLoc(); 5026 5027 SDValue N0 = Op.getOperand(0); 5028 SDValue N1 = Op.getOperand(1); 5029 SDValue N2 = Op.getOperand(2); 5030 5031 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 5032 isa<ConstantSDNode>(N2)) { 5033 unsigned Opc; 5034 if (VT == MVT::v8i16) 5035 Opc = X86ISD::PINSRW; 5036 else if (VT == MVT::v4i16) 5037 Opc = X86ISD::MMX_PINSRW; 5038 else if (VT == MVT::v16i8) 5039 Opc = X86ISD::PINSRB; 5040 else 5041 Opc = X86ISD::PINSRB; 5042 5043 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 5044 // argument. 5045 if (N1.getValueType() != MVT::i32) 5046 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5047 if (N2.getValueType() != MVT::i32) 5048 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5049 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 5050 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 5051 // Bits [7:6] of the constant are the source select. This will always be 5052 // zero here. The DAG Combiner may combine an extract_elt index into these 5053 // bits. For example (insert (extract, 3), 2) could be matched by putting 5054 // the '3' into bits [7:6] of X86ISD::INSERTPS. 5055 // Bits [5:4] of the constant are the destination select. This is the 5056 // value of the incoming immediate. 5057 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 5058 // combine either bitwise AND or insert of float 0.0 to set these bits. 5059 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 5060 // Create this as a scalar to vector.. 5061 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 5062 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 5063 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 5064 // PINSR* works with constant index. 5065 return Op; 5066 } 5067 return SDValue(); 5068} 5069 5070SDValue 5071X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 5072 EVT VT = Op.getValueType(); 5073 EVT EltVT = VT.getVectorElementType(); 5074 5075 if (Subtarget->hasSSE41()) 5076 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 5077 5078 if (EltVT == MVT::i8) 5079 return SDValue(); 5080 5081 DebugLoc dl = Op.getDebugLoc(); 5082 SDValue N0 = Op.getOperand(0); 5083 SDValue N1 = Op.getOperand(1); 5084 SDValue N2 = Op.getOperand(2); 5085 5086 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 5087 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 5088 // as its second argument. 5089 if (N1.getValueType() != MVT::i32) 5090 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5091 if (N2.getValueType() != MVT::i32) 5092 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5093 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 5094 dl, VT, N0, N1, N2); 5095 } 5096 return SDValue(); 5097} 5098 5099SDValue 5100X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5101 DebugLoc dl = Op.getDebugLoc(); 5102 5103 if (Op.getValueType() == MVT::v1i64 && 5104 Op.getOperand(0).getValueType() == MVT::i64) 5105 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 5106 5107 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 5108 EVT VT = MVT::v2i32; 5109 switch (Op.getValueType().getSimpleVT().SimpleTy) { 5110 default: break; 5111 case MVT::v16i8: 5112 case MVT::v8i16: 5113 VT = MVT::v4i32; 5114 break; 5115 } 5116 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 5117 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 5118} 5119 5120// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5121// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5122// one of the above mentioned nodes. It has to be wrapped because otherwise 5123// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5124// be used to form addressing mode. These wrapped nodes will be selected 5125// into MOV32ri. 5126SDValue 5127X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 5128 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5129 5130 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5131 // global base reg. 5132 unsigned char OpFlag = 0; 5133 unsigned WrapperKind = X86ISD::Wrapper; 5134 CodeModel::Model M = getTargetMachine().getCodeModel(); 5135 5136 if (Subtarget->isPICStyleRIPRel() && 5137 (M == CodeModel::Small || M == CodeModel::Kernel)) 5138 WrapperKind = X86ISD::WrapperRIP; 5139 else if (Subtarget->isPICStyleGOT()) 5140 OpFlag = X86II::MO_GOTOFF; 5141 else if (Subtarget->isPICStyleStubPIC()) 5142 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5143 5144 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5145 CP->getAlignment(), 5146 CP->getOffset(), OpFlag); 5147 DebugLoc DL = CP->getDebugLoc(); 5148 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5149 // With PIC, the address is actually $g + Offset. 5150 if (OpFlag) { 5151 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5152 DAG.getNode(X86ISD::GlobalBaseReg, 5153 DebugLoc(), getPointerTy()), 5154 Result); 5155 } 5156 5157 return Result; 5158} 5159 5160SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 5161 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5162 5163 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5164 // global base reg. 5165 unsigned char OpFlag = 0; 5166 unsigned WrapperKind = X86ISD::Wrapper; 5167 CodeModel::Model M = getTargetMachine().getCodeModel(); 5168 5169 if (Subtarget->isPICStyleRIPRel() && 5170 (M == CodeModel::Small || M == CodeModel::Kernel)) 5171 WrapperKind = X86ISD::WrapperRIP; 5172 else if (Subtarget->isPICStyleGOT()) 5173 OpFlag = X86II::MO_GOTOFF; 5174 else if (Subtarget->isPICStyleStubPIC()) 5175 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5176 5177 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5178 OpFlag); 5179 DebugLoc DL = JT->getDebugLoc(); 5180 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5181 5182 // With PIC, the address is actually $g + Offset. 5183 if (OpFlag) { 5184 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5185 DAG.getNode(X86ISD::GlobalBaseReg, 5186 DebugLoc(), getPointerTy()), 5187 Result); 5188 } 5189 5190 return Result; 5191} 5192 5193SDValue 5194X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 5195 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5196 5197 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5198 // global base reg. 5199 unsigned char OpFlag = 0; 5200 unsigned WrapperKind = X86ISD::Wrapper; 5201 CodeModel::Model M = getTargetMachine().getCodeModel(); 5202 5203 if (Subtarget->isPICStyleRIPRel() && 5204 (M == CodeModel::Small || M == CodeModel::Kernel)) 5205 WrapperKind = X86ISD::WrapperRIP; 5206 else if (Subtarget->isPICStyleGOT()) 5207 OpFlag = X86II::MO_GOTOFF; 5208 else if (Subtarget->isPICStyleStubPIC()) 5209 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5210 5211 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5212 5213 DebugLoc DL = Op.getDebugLoc(); 5214 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5215 5216 5217 // With PIC, the address is actually $g + Offset. 5218 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5219 !Subtarget->is64Bit()) { 5220 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5221 DAG.getNode(X86ISD::GlobalBaseReg, 5222 DebugLoc(), getPointerTy()), 5223 Result); 5224 } 5225 5226 return Result; 5227} 5228 5229SDValue 5230X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 5231 // Create the TargetBlockAddressAddress node. 5232 unsigned char OpFlags = 5233 Subtarget->ClassifyBlockAddressReference(); 5234 CodeModel::Model M = getTargetMachine().getCodeModel(); 5235 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5236 DebugLoc dl = Op.getDebugLoc(); 5237 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5238 /*isTarget=*/true, OpFlags); 5239 5240 if (Subtarget->isPICStyleRIPRel() && 5241 (M == CodeModel::Small || M == CodeModel::Kernel)) 5242 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5243 else 5244 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5245 5246 // With PIC, the address is actually $g + Offset. 5247 if (isGlobalRelativeToPICBase(OpFlags)) { 5248 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5249 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5250 Result); 5251 } 5252 5253 return Result; 5254} 5255 5256SDValue 5257X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5258 int64_t Offset, 5259 SelectionDAG &DAG) const { 5260 // Create the TargetGlobalAddress node, folding in the constant 5261 // offset if it is legal. 5262 unsigned char OpFlags = 5263 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5264 CodeModel::Model M = getTargetMachine().getCodeModel(); 5265 SDValue Result; 5266 if (OpFlags == X86II::MO_NO_FLAG && 5267 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5268 // A direct static reference to a global. 5269 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 5270 Offset = 0; 5271 } else { 5272 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 5273 } 5274 5275 if (Subtarget->isPICStyleRIPRel() && 5276 (M == CodeModel::Small || M == CodeModel::Kernel)) 5277 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5278 else 5279 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5280 5281 // With PIC, the address is actually $g + Offset. 5282 if (isGlobalRelativeToPICBase(OpFlags)) { 5283 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5284 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5285 Result); 5286 } 5287 5288 // For globals that require a load from a stub to get the address, emit the 5289 // load. 5290 if (isGlobalStubReference(OpFlags)) 5291 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5292 PseudoSourceValue::getGOT(), 0, false, false, 0); 5293 5294 // If there was a non-zero offset that we didn't fold, create an explicit 5295 // addition for it. 5296 if (Offset != 0) 5297 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5298 DAG.getConstant(Offset, getPointerTy())); 5299 5300 return Result; 5301} 5302 5303SDValue 5304X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 5305 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5306 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5307 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5308} 5309 5310static SDValue 5311GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5312 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5313 unsigned char OperandFlags) { 5314 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5315 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5316 DebugLoc dl = GA->getDebugLoc(); 5317 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5318 GA->getValueType(0), 5319 GA->getOffset(), 5320 OperandFlags); 5321 if (InFlag) { 5322 SDValue Ops[] = { Chain, TGA, *InFlag }; 5323 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5324 } else { 5325 SDValue Ops[] = { Chain, TGA }; 5326 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5327 } 5328 5329 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5330 MFI->setAdjustsStack(true); 5331 5332 SDValue Flag = Chain.getValue(1); 5333 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5334} 5335 5336// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5337static SDValue 5338LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5339 const EVT PtrVT) { 5340 SDValue InFlag; 5341 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5342 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5343 DAG.getNode(X86ISD::GlobalBaseReg, 5344 DebugLoc(), PtrVT), InFlag); 5345 InFlag = Chain.getValue(1); 5346 5347 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5348} 5349 5350// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5351static SDValue 5352LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5353 const EVT PtrVT) { 5354 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5355 X86::RAX, X86II::MO_TLSGD); 5356} 5357 5358// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5359// "local exec" model. 5360static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5361 const EVT PtrVT, TLSModel::Model model, 5362 bool is64Bit) { 5363 DebugLoc dl = GA->getDebugLoc(); 5364 // Get the Thread Pointer 5365 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5366 DebugLoc(), PtrVT, 5367 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5368 MVT::i32)); 5369 5370 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5371 NULL, 0, false, false, 0); 5372 5373 unsigned char OperandFlags = 0; 5374 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5375 // initialexec. 5376 unsigned WrapperKind = X86ISD::Wrapper; 5377 if (model == TLSModel::LocalExec) { 5378 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5379 } else if (is64Bit) { 5380 assert(model == TLSModel::InitialExec); 5381 OperandFlags = X86II::MO_GOTTPOFF; 5382 WrapperKind = X86ISD::WrapperRIP; 5383 } else { 5384 assert(model == TLSModel::InitialExec); 5385 OperandFlags = X86II::MO_INDNTPOFF; 5386 } 5387 5388 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5389 // exec) 5390 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5391 GA->getValueType(0), 5392 GA->getOffset(), OperandFlags); 5393 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5394 5395 if (model == TLSModel::InitialExec) 5396 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5397 PseudoSourceValue::getGOT(), 0, false, false, 0); 5398 5399 // The address of the thread local variable is the add of the thread 5400 // pointer with the offset of the variable. 5401 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5402} 5403 5404SDValue 5405X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 5406 5407 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5408 const GlobalValue *GV = GA->getGlobal(); 5409 5410 if (Subtarget->isTargetELF()) { 5411 // TODO: implement the "local dynamic" model 5412 // TODO: implement the "initial exec"model for pic executables 5413 5414 // If GV is an alias then use the aliasee for determining 5415 // thread-localness. 5416 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5417 GV = GA->resolveAliasedGlobal(false); 5418 5419 TLSModel::Model model 5420 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 5421 5422 switch (model) { 5423 case TLSModel::GeneralDynamic: 5424 case TLSModel::LocalDynamic: // not implemented 5425 if (Subtarget->is64Bit()) 5426 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5427 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5428 5429 case TLSModel::InitialExec: 5430 case TLSModel::LocalExec: 5431 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5432 Subtarget->is64Bit()); 5433 } 5434 } else if (Subtarget->isTargetDarwin()) { 5435 // Darwin only has one model of TLS. Lower to that. 5436 unsigned char OpFlag = 0; 5437 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 5438 X86ISD::WrapperRIP : X86ISD::Wrapper; 5439 5440 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5441 // global base reg. 5442 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 5443 !Subtarget->is64Bit(); 5444 if (PIC32) 5445 OpFlag = X86II::MO_TLVP_PIC_BASE; 5446 else 5447 OpFlag = X86II::MO_TLVP; 5448 DebugLoc DL = Op.getDebugLoc(); 5449 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 5450 getPointerTy(), 5451 GA->getOffset(), OpFlag); 5452 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5453 5454 // With PIC32, the address is actually $g + Offset. 5455 if (PIC32) 5456 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5457 DAG.getNode(X86ISD::GlobalBaseReg, 5458 DebugLoc(), getPointerTy()), 5459 Offset); 5460 5461 // Lowering the machine isd will make sure everything is in the right 5462 // location. 5463 SDValue Args[] = { Offset }; 5464 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1); 5465 5466 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 5467 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5468 MFI->setAdjustsStack(true); 5469 5470 // And our return value (tls address) is in the standard call return value 5471 // location. 5472 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 5473 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 5474 } 5475 5476 assert(false && 5477 "TLS not implemented for this target."); 5478 5479 llvm_unreachable("Unreachable"); 5480 return SDValue(); 5481} 5482 5483 5484/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5485/// take a 2 x i32 value to shift plus a shift amount. 5486SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 5487 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5488 EVT VT = Op.getValueType(); 5489 unsigned VTBits = VT.getSizeInBits(); 5490 DebugLoc dl = Op.getDebugLoc(); 5491 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5492 SDValue ShOpLo = Op.getOperand(0); 5493 SDValue ShOpHi = Op.getOperand(1); 5494 SDValue ShAmt = Op.getOperand(2); 5495 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5496 DAG.getConstant(VTBits - 1, MVT::i8)) 5497 : DAG.getConstant(0, VT); 5498 5499 SDValue Tmp2, Tmp3; 5500 if (Op.getOpcode() == ISD::SHL_PARTS) { 5501 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5502 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5503 } else { 5504 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5505 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5506 } 5507 5508 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5509 DAG.getConstant(VTBits, MVT::i8)); 5510 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5511 AndNode, DAG.getConstant(0, MVT::i8)); 5512 5513 SDValue Hi, Lo; 5514 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5515 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5516 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5517 5518 if (Op.getOpcode() == ISD::SHL_PARTS) { 5519 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5520 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5521 } else { 5522 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5523 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5524 } 5525 5526 SDValue Ops[2] = { Lo, Hi }; 5527 return DAG.getMergeValues(Ops, 2, dl); 5528} 5529 5530SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 5531 SelectionDAG &DAG) const { 5532 EVT SrcVT = Op.getOperand(0).getValueType(); 5533 5534 if (SrcVT.isVector()) { 5535 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5536 return Op; 5537 } 5538 return SDValue(); 5539 } 5540 5541 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5542 "Unknown SINT_TO_FP to lower!"); 5543 5544 // These are really Legal; return the operand so the caller accepts it as 5545 // Legal. 5546 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5547 return Op; 5548 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5549 Subtarget->is64Bit()) { 5550 return Op; 5551 } 5552 5553 DebugLoc dl = Op.getDebugLoc(); 5554 unsigned Size = SrcVT.getSizeInBits()/8; 5555 MachineFunction &MF = DAG.getMachineFunction(); 5556 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5557 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5558 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5559 StackSlot, 5560 PseudoSourceValue::getFixedStack(SSFI), 0, 5561 false, false, 0); 5562 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5563} 5564 5565SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5566 SDValue StackSlot, 5567 SelectionDAG &DAG) const { 5568 // Build the FILD 5569 DebugLoc dl = Op.getDebugLoc(); 5570 SDVTList Tys; 5571 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5572 if (useSSE) 5573 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5574 else 5575 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5576 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5577 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5578 Tys, Ops, array_lengthof(Ops)); 5579 5580 if (useSSE) { 5581 Chain = Result.getValue(1); 5582 SDValue InFlag = Result.getValue(2); 5583 5584 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5585 // shouldn't be necessary except that RFP cannot be live across 5586 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5587 MachineFunction &MF = DAG.getMachineFunction(); 5588 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5589 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5590 Tys = DAG.getVTList(MVT::Other); 5591 SDValue Ops[] = { 5592 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5593 }; 5594 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5595 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5596 PseudoSourceValue::getFixedStack(SSFI), 0, 5597 false, false, 0); 5598 } 5599 5600 return Result; 5601} 5602 5603// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5604SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 5605 SelectionDAG &DAG) const { 5606 // This algorithm is not obvious. Here it is in C code, more or less: 5607 /* 5608 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5609 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5610 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5611 5612 // Copy ints to xmm registers. 5613 __m128i xh = _mm_cvtsi32_si128( hi ); 5614 __m128i xl = _mm_cvtsi32_si128( lo ); 5615 5616 // Combine into low half of a single xmm register. 5617 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5618 __m128d d; 5619 double sd; 5620 5621 // Merge in appropriate exponents to give the integer bits the right 5622 // magnitude. 5623 x = _mm_unpacklo_epi32( x, exp ); 5624 5625 // Subtract away the biases to deal with the IEEE-754 double precision 5626 // implicit 1. 5627 d = _mm_sub_pd( (__m128d) x, bias ); 5628 5629 // All conversions up to here are exact. The correctly rounded result is 5630 // calculated using the current rounding mode using the following 5631 // horizontal add. 5632 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5633 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5634 // store doesn't really need to be here (except 5635 // maybe to zero the other double) 5636 return sd; 5637 } 5638 */ 5639 5640 DebugLoc dl = Op.getDebugLoc(); 5641 LLVMContext *Context = DAG.getContext(); 5642 5643 // Build some magic constants. 5644 std::vector<Constant*> CV0; 5645 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5646 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5647 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5648 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5649 Constant *C0 = ConstantVector::get(CV0); 5650 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5651 5652 std::vector<Constant*> CV1; 5653 CV1.push_back( 5654 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5655 CV1.push_back( 5656 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5657 Constant *C1 = ConstantVector::get(CV1); 5658 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5659 5660 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5661 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5662 Op.getOperand(0), 5663 DAG.getIntPtrConstant(1))); 5664 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5665 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5666 Op.getOperand(0), 5667 DAG.getIntPtrConstant(0))); 5668 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5669 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5670 PseudoSourceValue::getConstantPool(), 0, 5671 false, false, 16); 5672 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5673 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5674 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5675 PseudoSourceValue::getConstantPool(), 0, 5676 false, false, 16); 5677 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5678 5679 // Add the halves; easiest way is to swap them into another reg first. 5680 int ShufMask[2] = { 1, -1 }; 5681 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5682 DAG.getUNDEF(MVT::v2f64), ShufMask); 5683 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5684 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5685 DAG.getIntPtrConstant(0)); 5686} 5687 5688// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5689SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 5690 SelectionDAG &DAG) const { 5691 DebugLoc dl = Op.getDebugLoc(); 5692 // FP constant to bias correct the final result. 5693 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5694 MVT::f64); 5695 5696 // Load the 32-bit value into an XMM register. 5697 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5698 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5699 Op.getOperand(0), 5700 DAG.getIntPtrConstant(0))); 5701 5702 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5703 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5704 DAG.getIntPtrConstant(0)); 5705 5706 // Or the load with the bias. 5707 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5708 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5709 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5710 MVT::v2f64, Load)), 5711 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5712 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5713 MVT::v2f64, Bias))); 5714 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5715 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5716 DAG.getIntPtrConstant(0)); 5717 5718 // Subtract the bias. 5719 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5720 5721 // Handle final rounding. 5722 EVT DestVT = Op.getValueType(); 5723 5724 if (DestVT.bitsLT(MVT::f64)) { 5725 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5726 DAG.getIntPtrConstant(0)); 5727 } else if (DestVT.bitsGT(MVT::f64)) { 5728 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5729 } 5730 5731 // Handle final rounding. 5732 return Sub; 5733} 5734 5735SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 5736 SelectionDAG &DAG) const { 5737 SDValue N0 = Op.getOperand(0); 5738 DebugLoc dl = Op.getDebugLoc(); 5739 5740 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 5741 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5742 // the optimization here. 5743 if (DAG.SignBitIsZero(N0)) 5744 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5745 5746 EVT SrcVT = N0.getValueType(); 5747 EVT DstVT = Op.getValueType(); 5748 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 5749 return LowerUINT_TO_FP_i64(Op, DAG); 5750 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 5751 return LowerUINT_TO_FP_i32(Op, DAG); 5752 5753 // Make a 64-bit buffer, and use it to build an FILD. 5754 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5755 if (SrcVT == MVT::i32) { 5756 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5757 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5758 getPointerTy(), StackSlot, WordOff); 5759 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5760 StackSlot, NULL, 0, false, false, 0); 5761 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5762 OffsetSlot, NULL, 0, false, false, 0); 5763 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5764 return Fild; 5765 } 5766 5767 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 5768 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5769 StackSlot, NULL, 0, false, false, 0); 5770 // For i64 source, we need to add the appropriate power of 2 if the input 5771 // was negative. This is the same as the optimization in 5772 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 5773 // we must be careful to do the computation in x87 extended precision, not 5774 // in SSE. (The generic code can't know it's OK to do this, or how to.) 5775 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 5776 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 5777 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3); 5778 5779 APInt FF(32, 0x5F800000ULL); 5780 5781 // Check whether the sign bit is set. 5782 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 5783 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 5784 ISD::SETLT); 5785 5786 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 5787 SDValue FudgePtr = DAG.getConstantPool( 5788 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 5789 getPointerTy()); 5790 5791 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 5792 SDValue Zero = DAG.getIntPtrConstant(0); 5793 SDValue Four = DAG.getIntPtrConstant(4); 5794 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 5795 Zero, Four); 5796 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 5797 5798 // Load the value out, extending it from f32 to f80. 5799 // FIXME: Avoid the extend by constructing the right constant pool? 5800 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(), 5801 FudgePtr, PseudoSourceValue::getConstantPool(), 5802 0, MVT::f32, false, false, 4); 5803 // Extend everything to 80 bits to force it to be done on x87. 5804 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 5805 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 5806} 5807 5808std::pair<SDValue,SDValue> X86TargetLowering:: 5809FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 5810 DebugLoc dl = Op.getDebugLoc(); 5811 5812 EVT DstTy = Op.getValueType(); 5813 5814 if (!IsSigned) { 5815 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5816 DstTy = MVT::i64; 5817 } 5818 5819 assert(DstTy.getSimpleVT() <= MVT::i64 && 5820 DstTy.getSimpleVT() >= MVT::i16 && 5821 "Unknown FP_TO_SINT to lower!"); 5822 5823 // These are really Legal. 5824 if (DstTy == MVT::i32 && 5825 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5826 return std::make_pair(SDValue(), SDValue()); 5827 if (Subtarget->is64Bit() && 5828 DstTy == MVT::i64 && 5829 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5830 return std::make_pair(SDValue(), SDValue()); 5831 5832 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5833 // stack slot. 5834 MachineFunction &MF = DAG.getMachineFunction(); 5835 unsigned MemSize = DstTy.getSizeInBits()/8; 5836 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5837 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5838 5839 unsigned Opc; 5840 switch (DstTy.getSimpleVT().SimpleTy) { 5841 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5842 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5843 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5844 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5845 } 5846 5847 SDValue Chain = DAG.getEntryNode(); 5848 SDValue Value = Op.getOperand(0); 5849 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5850 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5851 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5852 PseudoSourceValue::getFixedStack(SSFI), 0, 5853 false, false, 0); 5854 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5855 SDValue Ops[] = { 5856 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5857 }; 5858 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5859 Chain = Value.getValue(1); 5860 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5861 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5862 } 5863 5864 // Build the FP_TO_INT*_IN_MEM 5865 SDValue Ops[] = { Chain, Value, StackSlot }; 5866 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5867 5868 return std::make_pair(FIST, StackSlot); 5869} 5870 5871SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 5872 SelectionDAG &DAG) const { 5873 if (Op.getValueType().isVector()) { 5874 if (Op.getValueType() == MVT::v2i32 && 5875 Op.getOperand(0).getValueType() == MVT::v2f64) { 5876 return Op; 5877 } 5878 return SDValue(); 5879 } 5880 5881 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5882 SDValue FIST = Vals.first, StackSlot = Vals.second; 5883 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5884 if (FIST.getNode() == 0) return Op; 5885 5886 // Load the result. 5887 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5888 FIST, StackSlot, NULL, 0, false, false, 0); 5889} 5890 5891SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 5892 SelectionDAG &DAG) const { 5893 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5894 SDValue FIST = Vals.first, StackSlot = Vals.second; 5895 assert(FIST.getNode() && "Unexpected failure"); 5896 5897 // Load the result. 5898 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5899 FIST, StackSlot, NULL, 0, false, false, 0); 5900} 5901 5902SDValue X86TargetLowering::LowerFABS(SDValue Op, 5903 SelectionDAG &DAG) const { 5904 LLVMContext *Context = DAG.getContext(); 5905 DebugLoc dl = Op.getDebugLoc(); 5906 EVT VT = Op.getValueType(); 5907 EVT EltVT = VT; 5908 if (VT.isVector()) 5909 EltVT = VT.getVectorElementType(); 5910 std::vector<Constant*> CV; 5911 if (EltVT == MVT::f64) { 5912 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5913 CV.push_back(C); 5914 CV.push_back(C); 5915 } else { 5916 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5917 CV.push_back(C); 5918 CV.push_back(C); 5919 CV.push_back(C); 5920 CV.push_back(C); 5921 } 5922 Constant *C = ConstantVector::get(CV); 5923 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5924 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5925 PseudoSourceValue::getConstantPool(), 0, 5926 false, false, 16); 5927 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5928} 5929 5930SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 5931 LLVMContext *Context = DAG.getContext(); 5932 DebugLoc dl = Op.getDebugLoc(); 5933 EVT VT = Op.getValueType(); 5934 EVT EltVT = VT; 5935 if (VT.isVector()) 5936 EltVT = VT.getVectorElementType(); 5937 std::vector<Constant*> CV; 5938 if (EltVT == MVT::f64) { 5939 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5940 CV.push_back(C); 5941 CV.push_back(C); 5942 } else { 5943 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5944 CV.push_back(C); 5945 CV.push_back(C); 5946 CV.push_back(C); 5947 CV.push_back(C); 5948 } 5949 Constant *C = ConstantVector::get(CV); 5950 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5951 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5952 PseudoSourceValue::getConstantPool(), 0, 5953 false, false, 16); 5954 if (VT.isVector()) { 5955 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5956 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5957 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5958 Op.getOperand(0)), 5959 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5960 } else { 5961 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5962 } 5963} 5964 5965SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 5966 LLVMContext *Context = DAG.getContext(); 5967 SDValue Op0 = Op.getOperand(0); 5968 SDValue Op1 = Op.getOperand(1); 5969 DebugLoc dl = Op.getDebugLoc(); 5970 EVT VT = Op.getValueType(); 5971 EVT SrcVT = Op1.getValueType(); 5972 5973 // If second operand is smaller, extend it first. 5974 if (SrcVT.bitsLT(VT)) { 5975 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5976 SrcVT = VT; 5977 } 5978 // And if it is bigger, shrink it first. 5979 if (SrcVT.bitsGT(VT)) { 5980 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5981 SrcVT = VT; 5982 } 5983 5984 // At this point the operands and the result should have the same 5985 // type, and that won't be f80 since that is not custom lowered. 5986 5987 // First get the sign bit of second operand. 5988 std::vector<Constant*> CV; 5989 if (SrcVT == MVT::f64) { 5990 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5991 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5992 } else { 5993 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5994 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5995 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5996 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5997 } 5998 Constant *C = ConstantVector::get(CV); 5999 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6000 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 6001 PseudoSourceValue::getConstantPool(), 0, 6002 false, false, 16); 6003 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 6004 6005 // Shift sign bit right or left if the two operands have different types. 6006 if (SrcVT.bitsGT(VT)) { 6007 // Op0 is MVT::f32, Op1 is MVT::f64. 6008 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 6009 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 6010 DAG.getConstant(32, MVT::i32)); 6011 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 6012 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 6013 DAG.getIntPtrConstant(0)); 6014 } 6015 6016 // Clear first operand sign bit. 6017 CV.clear(); 6018 if (VT == MVT::f64) { 6019 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 6020 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6021 } else { 6022 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 6023 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6024 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6025 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6026 } 6027 C = ConstantVector::get(CV); 6028 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6029 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6030 PseudoSourceValue::getConstantPool(), 0, 6031 false, false, 16); 6032 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 6033 6034 // Or the value with the sign bit. 6035 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 6036} 6037 6038/// Emit nodes that will be selected as "test Op0,Op0", or something 6039/// equivalent. 6040SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 6041 SelectionDAG &DAG) const { 6042 DebugLoc dl = Op.getDebugLoc(); 6043 6044 // CF and OF aren't always set the way we want. Determine which 6045 // of these we need. 6046 bool NeedCF = false; 6047 bool NeedOF = false; 6048 switch (X86CC) { 6049 default: break; 6050 case X86::COND_A: case X86::COND_AE: 6051 case X86::COND_B: case X86::COND_BE: 6052 NeedCF = true; 6053 break; 6054 case X86::COND_G: case X86::COND_GE: 6055 case X86::COND_L: case X86::COND_LE: 6056 case X86::COND_O: case X86::COND_NO: 6057 NeedOF = true; 6058 break; 6059 } 6060 6061 // See if we can use the EFLAGS value from the operand instead of 6062 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 6063 // we prove that the arithmetic won't overflow, we can't use OF or CF. 6064 if (Op.getResNo() != 0 || NeedOF || NeedCF) 6065 // Emit a CMP with 0, which is the TEST pattern. 6066 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6067 DAG.getConstant(0, Op.getValueType())); 6068 6069 unsigned Opcode = 0; 6070 unsigned NumOperands = 0; 6071 switch (Op.getNode()->getOpcode()) { 6072 case ISD::ADD: 6073 // Due to an isel shortcoming, be conservative if this add is likely to be 6074 // selected as part of a load-modify-store instruction. When the root node 6075 // in a match is a store, isel doesn't know how to remap non-chain non-flag 6076 // uses of other nodes in the match, such as the ADD in this case. This 6077 // leads to the ADD being left around and reselected, with the result being 6078 // two adds in the output. Alas, even if none our users are stores, that 6079 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 6080 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 6081 // climbing the DAG back to the root, and it doesn't seem to be worth the 6082 // effort. 6083 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6084 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6085 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 6086 goto default_case; 6087 6088 if (ConstantSDNode *C = 6089 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 6090 // An add of one will be selected as an INC. 6091 if (C->getAPIntValue() == 1) { 6092 Opcode = X86ISD::INC; 6093 NumOperands = 1; 6094 break; 6095 } 6096 6097 // An add of negative one (subtract of one) will be selected as a DEC. 6098 if (C->getAPIntValue().isAllOnesValue()) { 6099 Opcode = X86ISD::DEC; 6100 NumOperands = 1; 6101 break; 6102 } 6103 } 6104 6105 // Otherwise use a regular EFLAGS-setting add. 6106 Opcode = X86ISD::ADD; 6107 NumOperands = 2; 6108 break; 6109 case ISD::AND: { 6110 // If the primary and result isn't used, don't bother using X86ISD::AND, 6111 // because a TEST instruction will be better. 6112 bool NonFlagUse = false; 6113 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6114 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 6115 SDNode *User = *UI; 6116 unsigned UOpNo = UI.getOperandNo(); 6117 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 6118 // Look pass truncate. 6119 UOpNo = User->use_begin().getOperandNo(); 6120 User = *User->use_begin(); 6121 } 6122 6123 if (User->getOpcode() != ISD::BRCOND && 6124 User->getOpcode() != ISD::SETCC && 6125 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 6126 NonFlagUse = true; 6127 break; 6128 } 6129 } 6130 6131 if (!NonFlagUse) 6132 break; 6133 } 6134 // FALL THROUGH 6135 case ISD::SUB: 6136 case ISD::OR: 6137 case ISD::XOR: 6138 // Due to the ISEL shortcoming noted above, be conservative if this op is 6139 // likely to be selected as part of a load-modify-store instruction. 6140 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6141 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6142 if (UI->getOpcode() == ISD::STORE) 6143 goto default_case; 6144 6145 // Otherwise use a regular EFLAGS-setting instruction. 6146 switch (Op.getNode()->getOpcode()) { 6147 default: llvm_unreachable("unexpected operator!"); 6148 case ISD::SUB: Opcode = X86ISD::SUB; break; 6149 case ISD::OR: Opcode = X86ISD::OR; break; 6150 case ISD::XOR: Opcode = X86ISD::XOR; break; 6151 case ISD::AND: Opcode = X86ISD::AND; break; 6152 } 6153 6154 NumOperands = 2; 6155 break; 6156 case X86ISD::ADD: 6157 case X86ISD::SUB: 6158 case X86ISD::INC: 6159 case X86ISD::DEC: 6160 case X86ISD::OR: 6161 case X86ISD::XOR: 6162 case X86ISD::AND: 6163 return SDValue(Op.getNode(), 1); 6164 default: 6165 default_case: 6166 break; 6167 } 6168 6169 if (Opcode == 0) 6170 // Emit a CMP with 0, which is the TEST pattern. 6171 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6172 DAG.getConstant(0, Op.getValueType())); 6173 6174 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 6175 SmallVector<SDValue, 4> Ops; 6176 for (unsigned i = 0; i != NumOperands; ++i) 6177 Ops.push_back(Op.getOperand(i)); 6178 6179 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 6180 DAG.ReplaceAllUsesWith(Op, New); 6181 return SDValue(New.getNode(), 1); 6182} 6183 6184/// Emit nodes that will be selected as "cmp Op0,Op1", or something 6185/// equivalent. 6186SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 6187 SelectionDAG &DAG) const { 6188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 6189 if (C->getAPIntValue() == 0) 6190 return EmitTest(Op0, X86CC, DAG); 6191 6192 DebugLoc dl = Op0.getDebugLoc(); 6193 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 6194} 6195 6196/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 6197/// if it's possible. 6198SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 6199 DebugLoc dl, SelectionDAG &DAG) const { 6200 SDValue Op0 = And.getOperand(0); 6201 SDValue Op1 = And.getOperand(1); 6202 if (Op0.getOpcode() == ISD::TRUNCATE) 6203 Op0 = Op0.getOperand(0); 6204 if (Op1.getOpcode() == ISD::TRUNCATE) 6205 Op1 = Op1.getOperand(0); 6206 6207 SDValue LHS, RHS; 6208 if (Op1.getOpcode() == ISD::SHL) 6209 std::swap(Op0, Op1); 6210 if (Op0.getOpcode() == ISD::SHL) { 6211 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6212 if (And00C->getZExtValue() == 1) { 6213 // If we looked past a truncate, check that it's only truncating away 6214 // known zeros. 6215 unsigned BitWidth = Op0.getValueSizeInBits(); 6216 unsigned AndBitWidth = And.getValueSizeInBits(); 6217 if (BitWidth > AndBitWidth) { 6218 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 6219 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 6220 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 6221 return SDValue(); 6222 } 6223 LHS = Op1; 6224 RHS = Op0.getOperand(1); 6225 } 6226 } else if (Op1.getOpcode() == ISD::Constant) { 6227 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6228 SDValue AndLHS = Op0; 6229 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6230 LHS = AndLHS.getOperand(0); 6231 RHS = AndLHS.getOperand(1); 6232 } 6233 } 6234 6235 if (LHS.getNode()) { 6236 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 6237 // instruction. Since the shift amount is in-range-or-undefined, we know 6238 // that doing a bittest on the i32 value is ok. We extend to i32 because 6239 // the encoding for the i16 version is larger than the i32 version. 6240 // Also promote i16 to i32 for performance / code size reason. 6241 if (LHS.getValueType() == MVT::i8 || 6242 LHS.getValueType() == MVT::i16) 6243 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 6244 6245 // If the operand types disagree, extend the shift amount to match. Since 6246 // BT ignores high bits (like shifts) we can use anyextend. 6247 if (LHS.getValueType() != RHS.getValueType()) 6248 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 6249 6250 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 6251 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 6252 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6253 DAG.getConstant(Cond, MVT::i8), BT); 6254 } 6255 6256 return SDValue(); 6257} 6258 6259SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 6260 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 6261 SDValue Op0 = Op.getOperand(0); 6262 SDValue Op1 = Op.getOperand(1); 6263 DebugLoc dl = Op.getDebugLoc(); 6264 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6265 6266 // Optimize to BT if possible. 6267 // Lower (X & (1 << N)) == 0 to BT(X, N). 6268 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 6269 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 6270 if (Op0.getOpcode() == ISD::AND && 6271 Op0.hasOneUse() && 6272 Op1.getOpcode() == ISD::Constant && 6273 cast<ConstantSDNode>(Op1)->isNullValue() && 6274 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6275 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 6276 if (NewSetCC.getNode()) 6277 return NewSetCC; 6278 } 6279 6280 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 6281 if (Op0.getOpcode() == X86ISD::SETCC && 6282 Op1.getOpcode() == ISD::Constant && 6283 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 6284 cast<ConstantSDNode>(Op1)->isNullValue()) && 6285 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6286 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 6287 bool Invert = (CC == ISD::SETNE) ^ 6288 cast<ConstantSDNode>(Op1)->isNullValue(); 6289 if (Invert) 6290 CCode = X86::GetOppositeBranchCondition(CCode); 6291 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6292 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6293 } 6294 6295 bool isFP = Op1.getValueType().isFloatingPoint(); 6296 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6297 if (X86CC == X86::COND_INVALID) 6298 return SDValue(); 6299 6300 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6301 6302 // Use sbb x, x to materialize carry bit into a GPR. 6303 if (X86CC == X86::COND_B) 6304 return DAG.getNode(ISD::AND, dl, MVT::i8, 6305 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6306 DAG.getConstant(X86CC, MVT::i8), Cond), 6307 DAG.getConstant(1, MVT::i8)); 6308 6309 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6310 DAG.getConstant(X86CC, MVT::i8), Cond); 6311} 6312 6313SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 6314 SDValue Cond; 6315 SDValue Op0 = Op.getOperand(0); 6316 SDValue Op1 = Op.getOperand(1); 6317 SDValue CC = Op.getOperand(2); 6318 EVT VT = Op.getValueType(); 6319 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6320 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6321 DebugLoc dl = Op.getDebugLoc(); 6322 6323 if (isFP) { 6324 unsigned SSECC = 8; 6325 EVT VT0 = Op0.getValueType(); 6326 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6327 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6328 bool Swap = false; 6329 6330 switch (SetCCOpcode) { 6331 default: break; 6332 case ISD::SETOEQ: 6333 case ISD::SETEQ: SSECC = 0; break; 6334 case ISD::SETOGT: 6335 case ISD::SETGT: Swap = true; // Fallthrough 6336 case ISD::SETLT: 6337 case ISD::SETOLT: SSECC = 1; break; 6338 case ISD::SETOGE: 6339 case ISD::SETGE: Swap = true; // Fallthrough 6340 case ISD::SETLE: 6341 case ISD::SETOLE: SSECC = 2; break; 6342 case ISD::SETUO: SSECC = 3; break; 6343 case ISD::SETUNE: 6344 case ISD::SETNE: SSECC = 4; break; 6345 case ISD::SETULE: Swap = true; 6346 case ISD::SETUGE: SSECC = 5; break; 6347 case ISD::SETULT: Swap = true; 6348 case ISD::SETUGT: SSECC = 6; break; 6349 case ISD::SETO: SSECC = 7; break; 6350 } 6351 if (Swap) 6352 std::swap(Op0, Op1); 6353 6354 // In the two special cases we can't handle, emit two comparisons. 6355 if (SSECC == 8) { 6356 if (SetCCOpcode == ISD::SETUEQ) { 6357 SDValue UNORD, EQ; 6358 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6359 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6360 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6361 } 6362 else if (SetCCOpcode == ISD::SETONE) { 6363 SDValue ORD, NEQ; 6364 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6365 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6366 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6367 } 6368 llvm_unreachable("Illegal FP comparison"); 6369 } 6370 // Handle all other FP comparisons here. 6371 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6372 } 6373 6374 // We are handling one of the integer comparisons here. Since SSE only has 6375 // GT and EQ comparisons for integer, swapping operands and multiple 6376 // operations may be required for some comparisons. 6377 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6378 bool Swap = false, Invert = false, FlipSigns = false; 6379 6380 switch (VT.getSimpleVT().SimpleTy) { 6381 default: break; 6382 case MVT::v8i8: 6383 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6384 case MVT::v4i16: 6385 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6386 case MVT::v2i32: 6387 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6388 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6389 } 6390 6391 switch (SetCCOpcode) { 6392 default: break; 6393 case ISD::SETNE: Invert = true; 6394 case ISD::SETEQ: Opc = EQOpc; break; 6395 case ISD::SETLT: Swap = true; 6396 case ISD::SETGT: Opc = GTOpc; break; 6397 case ISD::SETGE: Swap = true; 6398 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6399 case ISD::SETULT: Swap = true; 6400 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6401 case ISD::SETUGE: Swap = true; 6402 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6403 } 6404 if (Swap) 6405 std::swap(Op0, Op1); 6406 6407 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6408 // bits of the inputs before performing those operations. 6409 if (FlipSigns) { 6410 EVT EltVT = VT.getVectorElementType(); 6411 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6412 EltVT); 6413 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6414 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6415 SignBits.size()); 6416 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6417 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6418 } 6419 6420 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6421 6422 // If the logical-not of the result is required, perform that now. 6423 if (Invert) 6424 Result = DAG.getNOT(dl, Result, VT); 6425 6426 return Result; 6427} 6428 6429// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6430static bool isX86LogicalCmp(SDValue Op) { 6431 unsigned Opc = Op.getNode()->getOpcode(); 6432 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6433 return true; 6434 if (Op.getResNo() == 1 && 6435 (Opc == X86ISD::ADD || 6436 Opc == X86ISD::SUB || 6437 Opc == X86ISD::SMUL || 6438 Opc == X86ISD::UMUL || 6439 Opc == X86ISD::INC || 6440 Opc == X86ISD::DEC || 6441 Opc == X86ISD::OR || 6442 Opc == X86ISD::XOR || 6443 Opc == X86ISD::AND)) 6444 return true; 6445 6446 return false; 6447} 6448 6449SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 6450 bool addTest = true; 6451 SDValue Cond = Op.getOperand(0); 6452 DebugLoc dl = Op.getDebugLoc(); 6453 SDValue CC; 6454 6455 if (Cond.getOpcode() == ISD::SETCC) { 6456 SDValue NewCond = LowerSETCC(Cond, DAG); 6457 if (NewCond.getNode()) 6458 Cond = NewCond; 6459 } 6460 6461 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6462 SDValue Op1 = Op.getOperand(1); 6463 SDValue Op2 = Op.getOperand(2); 6464 if (Cond.getOpcode() == X86ISD::SETCC && 6465 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6466 SDValue Cmp = Cond.getOperand(1); 6467 if (Cmp.getOpcode() == X86ISD::CMP) { 6468 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6469 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6470 ConstantSDNode *RHSC = 6471 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6472 if (N1C && N1C->isAllOnesValue() && 6473 N2C && N2C->isNullValue() && 6474 RHSC && RHSC->isNullValue()) { 6475 SDValue CmpOp0 = Cmp.getOperand(0); 6476 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6477 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6478 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6479 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6480 } 6481 } 6482 } 6483 6484 // Look pass (and (setcc_carry (cmp ...)), 1). 6485 if (Cond.getOpcode() == ISD::AND && 6486 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6487 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6488 if (C && C->getAPIntValue() == 1) 6489 Cond = Cond.getOperand(0); 6490 } 6491 6492 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6493 // setting operand in place of the X86ISD::SETCC. 6494 if (Cond.getOpcode() == X86ISD::SETCC || 6495 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6496 CC = Cond.getOperand(0); 6497 6498 SDValue Cmp = Cond.getOperand(1); 6499 unsigned Opc = Cmp.getOpcode(); 6500 EVT VT = Op.getValueType(); 6501 6502 bool IllegalFPCMov = false; 6503 if (VT.isFloatingPoint() && !VT.isVector() && 6504 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6505 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6506 6507 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6508 Opc == X86ISD::BT) { // FIXME 6509 Cond = Cmp; 6510 addTest = false; 6511 } 6512 } 6513 6514 if (addTest) { 6515 // Look pass the truncate. 6516 if (Cond.getOpcode() == ISD::TRUNCATE) 6517 Cond = Cond.getOperand(0); 6518 6519 // We know the result of AND is compared against zero. Try to match 6520 // it to BT. 6521 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6522 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6523 if (NewSetCC.getNode()) { 6524 CC = NewSetCC.getOperand(0); 6525 Cond = NewSetCC.getOperand(1); 6526 addTest = false; 6527 } 6528 } 6529 } 6530 6531 if (addTest) { 6532 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6533 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6534 } 6535 6536 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6537 // condition is true. 6538 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6539 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6540 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6541} 6542 6543// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6544// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6545// from the AND / OR. 6546static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6547 Opc = Op.getOpcode(); 6548 if (Opc != ISD::OR && Opc != ISD::AND) 6549 return false; 6550 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6551 Op.getOperand(0).hasOneUse() && 6552 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6553 Op.getOperand(1).hasOneUse()); 6554} 6555 6556// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6557// 1 and that the SETCC node has a single use. 6558static bool isXor1OfSetCC(SDValue Op) { 6559 if (Op.getOpcode() != ISD::XOR) 6560 return false; 6561 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6562 if (N1C && N1C->getAPIntValue() == 1) { 6563 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6564 Op.getOperand(0).hasOneUse(); 6565 } 6566 return false; 6567} 6568 6569SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 6570 bool addTest = true; 6571 SDValue Chain = Op.getOperand(0); 6572 SDValue Cond = Op.getOperand(1); 6573 SDValue Dest = Op.getOperand(2); 6574 DebugLoc dl = Op.getDebugLoc(); 6575 SDValue CC; 6576 6577 if (Cond.getOpcode() == ISD::SETCC) { 6578 SDValue NewCond = LowerSETCC(Cond, DAG); 6579 if (NewCond.getNode()) 6580 Cond = NewCond; 6581 } 6582#if 0 6583 // FIXME: LowerXALUO doesn't handle these!! 6584 else if (Cond.getOpcode() == X86ISD::ADD || 6585 Cond.getOpcode() == X86ISD::SUB || 6586 Cond.getOpcode() == X86ISD::SMUL || 6587 Cond.getOpcode() == X86ISD::UMUL) 6588 Cond = LowerXALUO(Cond, DAG); 6589#endif 6590 6591 // Look pass (and (setcc_carry (cmp ...)), 1). 6592 if (Cond.getOpcode() == ISD::AND && 6593 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6595 if (C && C->getAPIntValue() == 1) 6596 Cond = Cond.getOperand(0); 6597 } 6598 6599 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6600 // setting operand in place of the X86ISD::SETCC. 6601 if (Cond.getOpcode() == X86ISD::SETCC || 6602 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6603 CC = Cond.getOperand(0); 6604 6605 SDValue Cmp = Cond.getOperand(1); 6606 unsigned Opc = Cmp.getOpcode(); 6607 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6608 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6609 Cond = Cmp; 6610 addTest = false; 6611 } else { 6612 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6613 default: break; 6614 case X86::COND_O: 6615 case X86::COND_B: 6616 // These can only come from an arithmetic instruction with overflow, 6617 // e.g. SADDO, UADDO. 6618 Cond = Cond.getNode()->getOperand(1); 6619 addTest = false; 6620 break; 6621 } 6622 } 6623 } else { 6624 unsigned CondOpc; 6625 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6626 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6627 if (CondOpc == ISD::OR) { 6628 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6629 // two branches instead of an explicit OR instruction with a 6630 // separate test. 6631 if (Cmp == Cond.getOperand(1).getOperand(1) && 6632 isX86LogicalCmp(Cmp)) { 6633 CC = Cond.getOperand(0).getOperand(0); 6634 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6635 Chain, Dest, CC, Cmp); 6636 CC = Cond.getOperand(1).getOperand(0); 6637 Cond = Cmp; 6638 addTest = false; 6639 } 6640 } else { // ISD::AND 6641 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6642 // two branches instead of an explicit AND instruction with a 6643 // separate test. However, we only do this if this block doesn't 6644 // have a fall-through edge, because this requires an explicit 6645 // jmp when the condition is false. 6646 if (Cmp == Cond.getOperand(1).getOperand(1) && 6647 isX86LogicalCmp(Cmp) && 6648 Op.getNode()->hasOneUse()) { 6649 X86::CondCode CCode = 6650 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6651 CCode = X86::GetOppositeBranchCondition(CCode); 6652 CC = DAG.getConstant(CCode, MVT::i8); 6653 SDNode *User = *Op.getNode()->use_begin(); 6654 // Look for an unconditional branch following this conditional branch. 6655 // We need this because we need to reverse the successors in order 6656 // to implement FCMP_OEQ. 6657 if (User->getOpcode() == ISD::BR) { 6658 SDValue FalseBB = User->getOperand(1); 6659 SDNode *NewBR = 6660 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 6661 assert(NewBR == User); 6662 (void)NewBR; 6663 Dest = FalseBB; 6664 6665 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6666 Chain, Dest, CC, Cmp); 6667 X86::CondCode CCode = 6668 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6669 CCode = X86::GetOppositeBranchCondition(CCode); 6670 CC = DAG.getConstant(CCode, MVT::i8); 6671 Cond = Cmp; 6672 addTest = false; 6673 } 6674 } 6675 } 6676 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6677 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6678 // It should be transformed during dag combiner except when the condition 6679 // is set by a arithmetics with overflow node. 6680 X86::CondCode CCode = 6681 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6682 CCode = X86::GetOppositeBranchCondition(CCode); 6683 CC = DAG.getConstant(CCode, MVT::i8); 6684 Cond = Cond.getOperand(0).getOperand(1); 6685 addTest = false; 6686 } 6687 } 6688 6689 if (addTest) { 6690 // Look pass the truncate. 6691 if (Cond.getOpcode() == ISD::TRUNCATE) 6692 Cond = Cond.getOperand(0); 6693 6694 // We know the result of AND is compared against zero. Try to match 6695 // it to BT. 6696 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6697 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6698 if (NewSetCC.getNode()) { 6699 CC = NewSetCC.getOperand(0); 6700 Cond = NewSetCC.getOperand(1); 6701 addTest = false; 6702 } 6703 } 6704 } 6705 6706 if (addTest) { 6707 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6708 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6709 } 6710 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6711 Chain, Dest, CC, Cond); 6712} 6713 6714 6715// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6716// Calls to _alloca is needed to probe the stack when allocating more than 4k 6717// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6718// that the guard pages used by the OS virtual memory manager are allocated in 6719// correct sequence. 6720SDValue 6721X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6722 SelectionDAG &DAG) const { 6723 assert(Subtarget->isTargetCygMing() && 6724 "This should be used only on Cygwin/Mingw targets"); 6725 DebugLoc dl = Op.getDebugLoc(); 6726 6727 // Get the inputs. 6728 SDValue Chain = Op.getOperand(0); 6729 SDValue Size = Op.getOperand(1); 6730 // FIXME: Ensure alignment here 6731 6732 SDValue Flag; 6733 6734 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6735 6736 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6737 Flag = Chain.getValue(1); 6738 6739 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6740 6741 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 6742 Flag = Chain.getValue(1); 6743 6744 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6745 6746 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6747 return DAG.getMergeValues(Ops1, 2, dl); 6748} 6749 6750SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 6751 MachineFunction &MF = DAG.getMachineFunction(); 6752 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 6753 6754 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6755 DebugLoc dl = Op.getDebugLoc(); 6756 6757 if (!Subtarget->is64Bit()) { 6758 // vastart just stores the address of the VarArgsFrameIndex slot into the 6759 // memory location argument. 6760 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 6761 getPointerTy()); 6762 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6763 false, false, 0); 6764 } 6765 6766 // __va_list_tag: 6767 // gp_offset (0 - 6 * 8) 6768 // fp_offset (48 - 48 + 8 * 16) 6769 // overflow_arg_area (point to parameters coming in memory). 6770 // reg_save_area 6771 SmallVector<SDValue, 8> MemOps; 6772 SDValue FIN = Op.getOperand(1); 6773 // Store gp_offset 6774 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6775 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 6776 MVT::i32), 6777 FIN, SV, 0, false, false, 0); 6778 MemOps.push_back(Store); 6779 6780 // Store fp_offset 6781 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6782 FIN, DAG.getIntPtrConstant(4)); 6783 Store = DAG.getStore(Op.getOperand(0), dl, 6784 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 6785 MVT::i32), 6786 FIN, SV, 4, false, false, 0); 6787 MemOps.push_back(Store); 6788 6789 // Store ptr to overflow_arg_area 6790 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6791 FIN, DAG.getIntPtrConstant(4)); 6792 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 6793 getPointerTy()); 6794 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8, 6795 false, false, 0); 6796 MemOps.push_back(Store); 6797 6798 // Store ptr to reg_save_area. 6799 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6800 FIN, DAG.getIntPtrConstant(8)); 6801 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 6802 getPointerTy()); 6803 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16, 6804 false, false, 0); 6805 MemOps.push_back(Store); 6806 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6807 &MemOps[0], MemOps.size()); 6808} 6809 6810SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 6811 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6812 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6813 6814 report_fatal_error("VAArgInst is not yet implemented for x86-64!"); 6815 return SDValue(); 6816} 6817 6818SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 6819 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6820 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6821 SDValue Chain = Op.getOperand(0); 6822 SDValue DstPtr = Op.getOperand(1); 6823 SDValue SrcPtr = Op.getOperand(2); 6824 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6825 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6826 DebugLoc dl = Op.getDebugLoc(); 6827 6828 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6829 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 6830 false, DstSV, 0, SrcSV, 0); 6831} 6832 6833SDValue 6834X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 6835 DebugLoc dl = Op.getDebugLoc(); 6836 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6837 switch (IntNo) { 6838 default: return SDValue(); // Don't custom lower most intrinsics. 6839 // Comparison intrinsics. 6840 case Intrinsic::x86_sse_comieq_ss: 6841 case Intrinsic::x86_sse_comilt_ss: 6842 case Intrinsic::x86_sse_comile_ss: 6843 case Intrinsic::x86_sse_comigt_ss: 6844 case Intrinsic::x86_sse_comige_ss: 6845 case Intrinsic::x86_sse_comineq_ss: 6846 case Intrinsic::x86_sse_ucomieq_ss: 6847 case Intrinsic::x86_sse_ucomilt_ss: 6848 case Intrinsic::x86_sse_ucomile_ss: 6849 case Intrinsic::x86_sse_ucomigt_ss: 6850 case Intrinsic::x86_sse_ucomige_ss: 6851 case Intrinsic::x86_sse_ucomineq_ss: 6852 case Intrinsic::x86_sse2_comieq_sd: 6853 case Intrinsic::x86_sse2_comilt_sd: 6854 case Intrinsic::x86_sse2_comile_sd: 6855 case Intrinsic::x86_sse2_comigt_sd: 6856 case Intrinsic::x86_sse2_comige_sd: 6857 case Intrinsic::x86_sse2_comineq_sd: 6858 case Intrinsic::x86_sse2_ucomieq_sd: 6859 case Intrinsic::x86_sse2_ucomilt_sd: 6860 case Intrinsic::x86_sse2_ucomile_sd: 6861 case Intrinsic::x86_sse2_ucomigt_sd: 6862 case Intrinsic::x86_sse2_ucomige_sd: 6863 case Intrinsic::x86_sse2_ucomineq_sd: { 6864 unsigned Opc = 0; 6865 ISD::CondCode CC = ISD::SETCC_INVALID; 6866 switch (IntNo) { 6867 default: break; 6868 case Intrinsic::x86_sse_comieq_ss: 6869 case Intrinsic::x86_sse2_comieq_sd: 6870 Opc = X86ISD::COMI; 6871 CC = ISD::SETEQ; 6872 break; 6873 case Intrinsic::x86_sse_comilt_ss: 6874 case Intrinsic::x86_sse2_comilt_sd: 6875 Opc = X86ISD::COMI; 6876 CC = ISD::SETLT; 6877 break; 6878 case Intrinsic::x86_sse_comile_ss: 6879 case Intrinsic::x86_sse2_comile_sd: 6880 Opc = X86ISD::COMI; 6881 CC = ISD::SETLE; 6882 break; 6883 case Intrinsic::x86_sse_comigt_ss: 6884 case Intrinsic::x86_sse2_comigt_sd: 6885 Opc = X86ISD::COMI; 6886 CC = ISD::SETGT; 6887 break; 6888 case Intrinsic::x86_sse_comige_ss: 6889 case Intrinsic::x86_sse2_comige_sd: 6890 Opc = X86ISD::COMI; 6891 CC = ISD::SETGE; 6892 break; 6893 case Intrinsic::x86_sse_comineq_ss: 6894 case Intrinsic::x86_sse2_comineq_sd: 6895 Opc = X86ISD::COMI; 6896 CC = ISD::SETNE; 6897 break; 6898 case Intrinsic::x86_sse_ucomieq_ss: 6899 case Intrinsic::x86_sse2_ucomieq_sd: 6900 Opc = X86ISD::UCOMI; 6901 CC = ISD::SETEQ; 6902 break; 6903 case Intrinsic::x86_sse_ucomilt_ss: 6904 case Intrinsic::x86_sse2_ucomilt_sd: 6905 Opc = X86ISD::UCOMI; 6906 CC = ISD::SETLT; 6907 break; 6908 case Intrinsic::x86_sse_ucomile_ss: 6909 case Intrinsic::x86_sse2_ucomile_sd: 6910 Opc = X86ISD::UCOMI; 6911 CC = ISD::SETLE; 6912 break; 6913 case Intrinsic::x86_sse_ucomigt_ss: 6914 case Intrinsic::x86_sse2_ucomigt_sd: 6915 Opc = X86ISD::UCOMI; 6916 CC = ISD::SETGT; 6917 break; 6918 case Intrinsic::x86_sse_ucomige_ss: 6919 case Intrinsic::x86_sse2_ucomige_sd: 6920 Opc = X86ISD::UCOMI; 6921 CC = ISD::SETGE; 6922 break; 6923 case Intrinsic::x86_sse_ucomineq_ss: 6924 case Intrinsic::x86_sse2_ucomineq_sd: 6925 Opc = X86ISD::UCOMI; 6926 CC = ISD::SETNE; 6927 break; 6928 } 6929 6930 SDValue LHS = Op.getOperand(1); 6931 SDValue RHS = Op.getOperand(2); 6932 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6933 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6934 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6935 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6936 DAG.getConstant(X86CC, MVT::i8), Cond); 6937 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6938 } 6939 // ptest intrinsics. The intrinsic these come from are designed to return 6940 // an integer value, not just an instruction so lower it to the ptest 6941 // pattern and a setcc for the result. 6942 case Intrinsic::x86_sse41_ptestz: 6943 case Intrinsic::x86_sse41_ptestc: 6944 case Intrinsic::x86_sse41_ptestnzc:{ 6945 unsigned X86CC = 0; 6946 switch (IntNo) { 6947 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6948 case Intrinsic::x86_sse41_ptestz: 6949 // ZF = 1 6950 X86CC = X86::COND_E; 6951 break; 6952 case Intrinsic::x86_sse41_ptestc: 6953 // CF = 1 6954 X86CC = X86::COND_B; 6955 break; 6956 case Intrinsic::x86_sse41_ptestnzc: 6957 // ZF and CF = 0 6958 X86CC = X86::COND_A; 6959 break; 6960 } 6961 6962 SDValue LHS = Op.getOperand(1); 6963 SDValue RHS = Op.getOperand(2); 6964 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6965 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6966 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6967 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6968 } 6969 6970 // Fix vector shift instructions where the last operand is a non-immediate 6971 // i32 value. 6972 case Intrinsic::x86_sse2_pslli_w: 6973 case Intrinsic::x86_sse2_pslli_d: 6974 case Intrinsic::x86_sse2_pslli_q: 6975 case Intrinsic::x86_sse2_psrli_w: 6976 case Intrinsic::x86_sse2_psrli_d: 6977 case Intrinsic::x86_sse2_psrli_q: 6978 case Intrinsic::x86_sse2_psrai_w: 6979 case Intrinsic::x86_sse2_psrai_d: 6980 case Intrinsic::x86_mmx_pslli_w: 6981 case Intrinsic::x86_mmx_pslli_d: 6982 case Intrinsic::x86_mmx_pslli_q: 6983 case Intrinsic::x86_mmx_psrli_w: 6984 case Intrinsic::x86_mmx_psrli_d: 6985 case Intrinsic::x86_mmx_psrli_q: 6986 case Intrinsic::x86_mmx_psrai_w: 6987 case Intrinsic::x86_mmx_psrai_d: { 6988 SDValue ShAmt = Op.getOperand(2); 6989 if (isa<ConstantSDNode>(ShAmt)) 6990 return SDValue(); 6991 6992 unsigned NewIntNo = 0; 6993 EVT ShAmtVT = MVT::v4i32; 6994 switch (IntNo) { 6995 case Intrinsic::x86_sse2_pslli_w: 6996 NewIntNo = Intrinsic::x86_sse2_psll_w; 6997 break; 6998 case Intrinsic::x86_sse2_pslli_d: 6999 NewIntNo = Intrinsic::x86_sse2_psll_d; 7000 break; 7001 case Intrinsic::x86_sse2_pslli_q: 7002 NewIntNo = Intrinsic::x86_sse2_psll_q; 7003 break; 7004 case Intrinsic::x86_sse2_psrli_w: 7005 NewIntNo = Intrinsic::x86_sse2_psrl_w; 7006 break; 7007 case Intrinsic::x86_sse2_psrli_d: 7008 NewIntNo = Intrinsic::x86_sse2_psrl_d; 7009 break; 7010 case Intrinsic::x86_sse2_psrli_q: 7011 NewIntNo = Intrinsic::x86_sse2_psrl_q; 7012 break; 7013 case Intrinsic::x86_sse2_psrai_w: 7014 NewIntNo = Intrinsic::x86_sse2_psra_w; 7015 break; 7016 case Intrinsic::x86_sse2_psrai_d: 7017 NewIntNo = Intrinsic::x86_sse2_psra_d; 7018 break; 7019 default: { 7020 ShAmtVT = MVT::v2i32; 7021 switch (IntNo) { 7022 case Intrinsic::x86_mmx_pslli_w: 7023 NewIntNo = Intrinsic::x86_mmx_psll_w; 7024 break; 7025 case Intrinsic::x86_mmx_pslli_d: 7026 NewIntNo = Intrinsic::x86_mmx_psll_d; 7027 break; 7028 case Intrinsic::x86_mmx_pslli_q: 7029 NewIntNo = Intrinsic::x86_mmx_psll_q; 7030 break; 7031 case Intrinsic::x86_mmx_psrli_w: 7032 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7033 break; 7034 case Intrinsic::x86_mmx_psrli_d: 7035 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7036 break; 7037 case Intrinsic::x86_mmx_psrli_q: 7038 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7039 break; 7040 case Intrinsic::x86_mmx_psrai_w: 7041 NewIntNo = Intrinsic::x86_mmx_psra_w; 7042 break; 7043 case Intrinsic::x86_mmx_psrai_d: 7044 NewIntNo = Intrinsic::x86_mmx_psra_d; 7045 break; 7046 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7047 } 7048 break; 7049 } 7050 } 7051 7052 // The vector shift intrinsics with scalars uses 32b shift amounts but 7053 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7054 // to be zero. 7055 SDValue ShOps[4]; 7056 ShOps[0] = ShAmt; 7057 ShOps[1] = DAG.getConstant(0, MVT::i32); 7058 if (ShAmtVT == MVT::v4i32) { 7059 ShOps[2] = DAG.getUNDEF(MVT::i32); 7060 ShOps[3] = DAG.getUNDEF(MVT::i32); 7061 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7062 } else { 7063 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7064 } 7065 7066 EVT VT = Op.getValueType(); 7067 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 7068 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7069 DAG.getConstant(NewIntNo, MVT::i32), 7070 Op.getOperand(1), ShAmt); 7071 } 7072 } 7073} 7074 7075SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 7076 SelectionDAG &DAG) const { 7077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7078 MFI->setReturnAddressIsTaken(true); 7079 7080 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7081 DebugLoc dl = Op.getDebugLoc(); 7082 7083 if (Depth > 0) { 7084 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7085 SDValue Offset = 7086 DAG.getConstant(TD->getPointerSize(), 7087 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7088 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7089 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7090 FrameAddr, Offset), 7091 NULL, 0, false, false, 0); 7092 } 7093 7094 // Just load the return address. 7095 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7096 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7097 RetAddrFI, NULL, 0, false, false, 0); 7098} 7099 7100SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 7101 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7102 MFI->setFrameAddressIsTaken(true); 7103 7104 EVT VT = Op.getValueType(); 7105 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7106 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7107 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7108 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7109 while (Depth--) 7110 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7111 false, false, 0); 7112 return FrameAddr; 7113} 7114 7115SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7116 SelectionDAG &DAG) const { 7117 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7118} 7119 7120SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 7121 MachineFunction &MF = DAG.getMachineFunction(); 7122 SDValue Chain = Op.getOperand(0); 7123 SDValue Offset = Op.getOperand(1); 7124 SDValue Handler = Op.getOperand(2); 7125 DebugLoc dl = Op.getDebugLoc(); 7126 7127 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7128 getPointerTy()); 7129 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7130 7131 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 7132 DAG.getIntPtrConstant(-TD->getPointerSize())); 7133 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7134 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7135 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7136 MF.getRegInfo().addLiveOut(StoreAddrReg); 7137 7138 return DAG.getNode(X86ISD::EH_RETURN, dl, 7139 MVT::Other, 7140 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7141} 7142 7143SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7144 SelectionDAG &DAG) const { 7145 SDValue Root = Op.getOperand(0); 7146 SDValue Trmp = Op.getOperand(1); // trampoline 7147 SDValue FPtr = Op.getOperand(2); // nested function 7148 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7149 DebugLoc dl = Op.getDebugLoc(); 7150 7151 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7152 7153 if (Subtarget->is64Bit()) { 7154 SDValue OutChains[6]; 7155 7156 // Large code-model. 7157 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7158 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7159 7160 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7161 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7162 7163 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7164 7165 // Load the pointer to the nested function into R11. 7166 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7167 SDValue Addr = Trmp; 7168 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7169 Addr, TrmpAddr, 0, false, false, 0); 7170 7171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7172 DAG.getConstant(2, MVT::i64)); 7173 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7174 false, false, 2); 7175 7176 // Load the 'nest' parameter value into R10. 7177 // R10 is specified in X86CallingConv.td 7178 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7180 DAG.getConstant(10, MVT::i64)); 7181 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7182 Addr, TrmpAddr, 10, false, false, 0); 7183 7184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7185 DAG.getConstant(12, MVT::i64)); 7186 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7187 false, false, 2); 7188 7189 // Jump to the nested function. 7190 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7191 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7192 DAG.getConstant(20, MVT::i64)); 7193 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7194 Addr, TrmpAddr, 20, false, false, 0); 7195 7196 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7197 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7198 DAG.getConstant(22, MVT::i64)); 7199 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7200 TrmpAddr, 22, false, false, 0); 7201 7202 SDValue Ops[] = 7203 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7204 return DAG.getMergeValues(Ops, 2, dl); 7205 } else { 7206 const Function *Func = 7207 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7208 CallingConv::ID CC = Func->getCallingConv(); 7209 unsigned NestReg; 7210 7211 switch (CC) { 7212 default: 7213 llvm_unreachable("Unsupported calling convention"); 7214 case CallingConv::C: 7215 case CallingConv::X86_StdCall: { 7216 // Pass 'nest' parameter in ECX. 7217 // Must be kept in sync with X86CallingConv.td 7218 NestReg = X86::ECX; 7219 7220 // Check that ECX wasn't needed by an 'inreg' parameter. 7221 const FunctionType *FTy = Func->getFunctionType(); 7222 const AttrListPtr &Attrs = Func->getAttributes(); 7223 7224 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7225 unsigned InRegCount = 0; 7226 unsigned Idx = 1; 7227 7228 for (FunctionType::param_iterator I = FTy->param_begin(), 7229 E = FTy->param_end(); I != E; ++I, ++Idx) 7230 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7231 // FIXME: should only count parameters that are lowered to integers. 7232 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7233 7234 if (InRegCount > 2) { 7235 report_fatal_error("Nest register in use - reduce number of inreg" 7236 " parameters!"); 7237 } 7238 } 7239 break; 7240 } 7241 case CallingConv::X86_FastCall: 7242 case CallingConv::X86_ThisCall: 7243 case CallingConv::Fast: 7244 // Pass 'nest' parameter in EAX. 7245 // Must be kept in sync with X86CallingConv.td 7246 NestReg = X86::EAX; 7247 break; 7248 } 7249 7250 SDValue OutChains[4]; 7251 SDValue Addr, Disp; 7252 7253 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7254 DAG.getConstant(10, MVT::i32)); 7255 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7256 7257 // This is storing the opcode for MOV32ri. 7258 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7259 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7260 OutChains[0] = DAG.getStore(Root, dl, 7261 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7262 Trmp, TrmpAddr, 0, false, false, 0); 7263 7264 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7265 DAG.getConstant(1, MVT::i32)); 7266 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7267 false, false, 1); 7268 7269 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7270 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7271 DAG.getConstant(5, MVT::i32)); 7272 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7273 TrmpAddr, 5, false, false, 1); 7274 7275 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7276 DAG.getConstant(6, MVT::i32)); 7277 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7278 false, false, 1); 7279 7280 SDValue Ops[] = 7281 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7282 return DAG.getMergeValues(Ops, 2, dl); 7283 } 7284} 7285 7286SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 7287 SelectionDAG &DAG) const { 7288 /* 7289 The rounding mode is in bits 11:10 of FPSR, and has the following 7290 settings: 7291 00 Round to nearest 7292 01 Round to -inf 7293 10 Round to +inf 7294 11 Round to 0 7295 7296 FLT_ROUNDS, on the other hand, expects the following: 7297 -1 Undefined 7298 0 Round to 0 7299 1 Round to nearest 7300 2 Round to +inf 7301 3 Round to -inf 7302 7303 To perform the conversion, we do: 7304 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7305 */ 7306 7307 MachineFunction &MF = DAG.getMachineFunction(); 7308 const TargetMachine &TM = MF.getTarget(); 7309 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7310 unsigned StackAlignment = TFI.getStackAlignment(); 7311 EVT VT = Op.getValueType(); 7312 DebugLoc dl = Op.getDebugLoc(); 7313 7314 // Save FP Control Word to stack slot 7315 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7316 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7317 7318 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7319 DAG.getEntryNode(), StackSlot); 7320 7321 // Load FP Control Word from stack slot 7322 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7323 false, false, 0); 7324 7325 // Transform as necessary 7326 SDValue CWD1 = 7327 DAG.getNode(ISD::SRL, dl, MVT::i16, 7328 DAG.getNode(ISD::AND, dl, MVT::i16, 7329 CWD, DAG.getConstant(0x800, MVT::i16)), 7330 DAG.getConstant(11, MVT::i8)); 7331 SDValue CWD2 = 7332 DAG.getNode(ISD::SRL, dl, MVT::i16, 7333 DAG.getNode(ISD::AND, dl, MVT::i16, 7334 CWD, DAG.getConstant(0x400, MVT::i16)), 7335 DAG.getConstant(9, MVT::i8)); 7336 7337 SDValue RetVal = 7338 DAG.getNode(ISD::AND, dl, MVT::i16, 7339 DAG.getNode(ISD::ADD, dl, MVT::i16, 7340 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7341 DAG.getConstant(1, MVT::i16)), 7342 DAG.getConstant(3, MVT::i16)); 7343 7344 7345 return DAG.getNode((VT.getSizeInBits() < 16 ? 7346 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7347} 7348 7349SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 7350 EVT VT = Op.getValueType(); 7351 EVT OpVT = VT; 7352 unsigned NumBits = VT.getSizeInBits(); 7353 DebugLoc dl = Op.getDebugLoc(); 7354 7355 Op = Op.getOperand(0); 7356 if (VT == MVT::i8) { 7357 // Zero extend to i32 since there is not an i8 bsr. 7358 OpVT = MVT::i32; 7359 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7360 } 7361 7362 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7363 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7364 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7365 7366 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7367 SDValue Ops[] = { 7368 Op, 7369 DAG.getConstant(NumBits+NumBits-1, OpVT), 7370 DAG.getConstant(X86::COND_E, MVT::i8), 7371 Op.getValue(1) 7372 }; 7373 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7374 7375 // Finally xor with NumBits-1. 7376 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7377 7378 if (VT == MVT::i8) 7379 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7380 return Op; 7381} 7382 7383SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 7384 EVT VT = Op.getValueType(); 7385 EVT OpVT = VT; 7386 unsigned NumBits = VT.getSizeInBits(); 7387 DebugLoc dl = Op.getDebugLoc(); 7388 7389 Op = Op.getOperand(0); 7390 if (VT == MVT::i8) { 7391 OpVT = MVT::i32; 7392 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7393 } 7394 7395 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7396 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7397 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7398 7399 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7400 SDValue Ops[] = { 7401 Op, 7402 DAG.getConstant(NumBits, OpVT), 7403 DAG.getConstant(X86::COND_E, MVT::i8), 7404 Op.getValue(1) 7405 }; 7406 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7407 7408 if (VT == MVT::i8) 7409 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7410 return Op; 7411} 7412 7413SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 7414 EVT VT = Op.getValueType(); 7415 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7416 DebugLoc dl = Op.getDebugLoc(); 7417 7418 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7419 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7420 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7421 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7422 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7423 // 7424 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7425 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7426 // return AloBlo + AloBhi + AhiBlo; 7427 7428 SDValue A = Op.getOperand(0); 7429 SDValue B = Op.getOperand(1); 7430 7431 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7432 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7433 A, DAG.getConstant(32, MVT::i32)); 7434 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7435 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7436 B, DAG.getConstant(32, MVT::i32)); 7437 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7438 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7439 A, B); 7440 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7441 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7442 A, Bhi); 7443 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7444 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7445 Ahi, B); 7446 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7447 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7448 AloBhi, DAG.getConstant(32, MVT::i32)); 7449 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7450 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7451 AhiBlo, DAG.getConstant(32, MVT::i32)); 7452 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7453 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7454 return Res; 7455} 7456 7457 7458SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 7459 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7460 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7461 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7462 // has only one use. 7463 SDNode *N = Op.getNode(); 7464 SDValue LHS = N->getOperand(0); 7465 SDValue RHS = N->getOperand(1); 7466 unsigned BaseOp = 0; 7467 unsigned Cond = 0; 7468 DebugLoc dl = Op.getDebugLoc(); 7469 7470 switch (Op.getOpcode()) { 7471 default: llvm_unreachable("Unknown ovf instruction!"); 7472 case ISD::SADDO: 7473 // A subtract of one will be selected as a INC. Note that INC doesn't 7474 // set CF, so we can't do this for UADDO. 7475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7476 if (C->getAPIntValue() == 1) { 7477 BaseOp = X86ISD::INC; 7478 Cond = X86::COND_O; 7479 break; 7480 } 7481 BaseOp = X86ISD::ADD; 7482 Cond = X86::COND_O; 7483 break; 7484 case ISD::UADDO: 7485 BaseOp = X86ISD::ADD; 7486 Cond = X86::COND_B; 7487 break; 7488 case ISD::SSUBO: 7489 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7490 // set CF, so we can't do this for USUBO. 7491 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7492 if (C->getAPIntValue() == 1) { 7493 BaseOp = X86ISD::DEC; 7494 Cond = X86::COND_O; 7495 break; 7496 } 7497 BaseOp = X86ISD::SUB; 7498 Cond = X86::COND_O; 7499 break; 7500 case ISD::USUBO: 7501 BaseOp = X86ISD::SUB; 7502 Cond = X86::COND_B; 7503 break; 7504 case ISD::SMULO: 7505 BaseOp = X86ISD::SMUL; 7506 Cond = X86::COND_O; 7507 break; 7508 case ISD::UMULO: 7509 BaseOp = X86ISD::UMUL; 7510 Cond = X86::COND_B; 7511 break; 7512 } 7513 7514 // Also sets EFLAGS. 7515 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7516 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7517 7518 SDValue SetCC = 7519 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7520 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7521 7522 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7523 return Sum; 7524} 7525 7526SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 7527 DebugLoc dl = Op.getDebugLoc(); 7528 7529 if (!Subtarget->hasSSE2()) 7530 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 7531 DAG.getConstant(0, MVT::i32)); 7532 7533 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 7534 if(!isDev) 7535 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 7536 else { 7537 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7538 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 7539 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 7540 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 7541 7542 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 7543 if (!Op1 && !Op2 && !Op3 && Op4) 7544 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 7545 7546 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 7547 if (Op1 && !Op2 && !Op3 && !Op4) 7548 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 7549 7550 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 7551 // (MFENCE)>; 7552 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 7553 } 7554} 7555 7556SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 7557 EVT T = Op.getValueType(); 7558 DebugLoc dl = Op.getDebugLoc(); 7559 unsigned Reg = 0; 7560 unsigned size = 0; 7561 switch(T.getSimpleVT().SimpleTy) { 7562 default: 7563 assert(false && "Invalid value type!"); 7564 case MVT::i8: Reg = X86::AL; size = 1; break; 7565 case MVT::i16: Reg = X86::AX; size = 2; break; 7566 case MVT::i32: Reg = X86::EAX; size = 4; break; 7567 case MVT::i64: 7568 assert(Subtarget->is64Bit() && "Node not type legal!"); 7569 Reg = X86::RAX; size = 8; 7570 break; 7571 } 7572 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7573 Op.getOperand(2), SDValue()); 7574 SDValue Ops[] = { cpIn.getValue(0), 7575 Op.getOperand(1), 7576 Op.getOperand(3), 7577 DAG.getTargetConstant(size, MVT::i8), 7578 cpIn.getValue(1) }; 7579 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7580 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7581 SDValue cpOut = 7582 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7583 return cpOut; 7584} 7585 7586SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7587 SelectionDAG &DAG) const { 7588 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7589 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7590 SDValue TheChain = Op.getOperand(0); 7591 DebugLoc dl = Op.getDebugLoc(); 7592 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7593 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7594 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7595 rax.getValue(2)); 7596 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7597 DAG.getConstant(32, MVT::i8)); 7598 SDValue Ops[] = { 7599 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7600 rdx.getValue(1) 7601 }; 7602 return DAG.getMergeValues(Ops, 2, dl); 7603} 7604 7605SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op, 7606 SelectionDAG &DAG) const { 7607 EVT SrcVT = Op.getOperand(0).getValueType(); 7608 EVT DstVT = Op.getValueType(); 7609 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && 7610 Subtarget->hasMMX() && !DisableMMX) && 7611 "Unexpected custom BIT_CONVERT"); 7612 assert((DstVT == MVT::i64 || 7613 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 7614 "Unexpected custom BIT_CONVERT"); 7615 // i64 <=> MMX conversions are Legal. 7616 if (SrcVT==MVT::i64 && DstVT.isVector()) 7617 return Op; 7618 if (DstVT==MVT::i64 && SrcVT.isVector()) 7619 return Op; 7620 // MMX <=> MMX conversions are Legal. 7621 if (SrcVT.isVector() && DstVT.isVector()) 7622 return Op; 7623 // All other conversions need to be expanded. 7624 return SDValue(); 7625} 7626SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 7627 SDNode *Node = Op.getNode(); 7628 DebugLoc dl = Node->getDebugLoc(); 7629 EVT T = Node->getValueType(0); 7630 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7631 DAG.getConstant(0, T), Node->getOperand(2)); 7632 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7633 cast<AtomicSDNode>(Node)->getMemoryVT(), 7634 Node->getOperand(0), 7635 Node->getOperand(1), negOp, 7636 cast<AtomicSDNode>(Node)->getSrcValue(), 7637 cast<AtomicSDNode>(Node)->getAlignment()); 7638} 7639 7640/// LowerOperation - Provide custom lowering hooks for some operations. 7641/// 7642SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 7643 switch (Op.getOpcode()) { 7644 default: llvm_unreachable("Should not custom lower this!"); 7645 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 7646 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7647 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7648 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7649 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7650 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7651 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7652 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7653 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7654 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7655 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7656 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7657 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7658 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7659 case ISD::SHL_PARTS: 7660 case ISD::SRA_PARTS: 7661 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7662 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7663 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7664 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7665 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7666 case ISD::FABS: return LowerFABS(Op, DAG); 7667 case ISD::FNEG: return LowerFNEG(Op, DAG); 7668 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7669 case ISD::SETCC: return LowerSETCC(Op, DAG); 7670 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7671 case ISD::SELECT: return LowerSELECT(Op, DAG); 7672 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7673 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7674 case ISD::VASTART: return LowerVASTART(Op, DAG); 7675 case ISD::VAARG: return LowerVAARG(Op, DAG); 7676 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7677 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7678 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7679 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7680 case ISD::FRAME_TO_ARGS_OFFSET: 7681 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7682 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7683 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7684 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7685 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7686 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7687 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7688 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7689 case ISD::SADDO: 7690 case ISD::UADDO: 7691 case ISD::SSUBO: 7692 case ISD::USUBO: 7693 case ISD::SMULO: 7694 case ISD::UMULO: return LowerXALUO(Op, DAG); 7695 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7696 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 7697 } 7698} 7699 7700void X86TargetLowering:: 7701ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7702 SelectionDAG &DAG, unsigned NewOp) const { 7703 EVT T = Node->getValueType(0); 7704 DebugLoc dl = Node->getDebugLoc(); 7705 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7706 7707 SDValue Chain = Node->getOperand(0); 7708 SDValue In1 = Node->getOperand(1); 7709 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7710 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7711 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7712 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7713 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7714 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7715 SDValue Result = 7716 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7717 cast<MemSDNode>(Node)->getMemOperand()); 7718 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7719 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7720 Results.push_back(Result.getValue(2)); 7721} 7722 7723/// ReplaceNodeResults - Replace a node with an illegal result type 7724/// with a new node built out of custom code. 7725void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7726 SmallVectorImpl<SDValue>&Results, 7727 SelectionDAG &DAG) const { 7728 DebugLoc dl = N->getDebugLoc(); 7729 switch (N->getOpcode()) { 7730 default: 7731 assert(false && "Do not know how to custom type legalize this operation!"); 7732 return; 7733 case ISD::FP_TO_SINT: { 7734 std::pair<SDValue,SDValue> Vals = 7735 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7736 SDValue FIST = Vals.first, StackSlot = Vals.second; 7737 if (FIST.getNode() != 0) { 7738 EVT VT = N->getValueType(0); 7739 // Return a load from the stack slot. 7740 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7741 false, false, 0)); 7742 } 7743 return; 7744 } 7745 case ISD::READCYCLECOUNTER: { 7746 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7747 SDValue TheChain = N->getOperand(0); 7748 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7749 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7750 rd.getValue(1)); 7751 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7752 eax.getValue(2)); 7753 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7754 SDValue Ops[] = { eax, edx }; 7755 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7756 Results.push_back(edx.getValue(1)); 7757 return; 7758 } 7759 case ISD::ATOMIC_CMP_SWAP: { 7760 EVT T = N->getValueType(0); 7761 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7762 SDValue cpInL, cpInH; 7763 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7764 DAG.getConstant(0, MVT::i32)); 7765 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7766 DAG.getConstant(1, MVT::i32)); 7767 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7768 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7769 cpInL.getValue(1)); 7770 SDValue swapInL, swapInH; 7771 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7772 DAG.getConstant(0, MVT::i32)); 7773 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7774 DAG.getConstant(1, MVT::i32)); 7775 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7776 cpInH.getValue(1)); 7777 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7778 swapInL.getValue(1)); 7779 SDValue Ops[] = { swapInH.getValue(0), 7780 N->getOperand(1), 7781 swapInH.getValue(1) }; 7782 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7783 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7784 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7785 MVT::i32, Result.getValue(1)); 7786 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7787 MVT::i32, cpOutL.getValue(2)); 7788 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7789 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7790 Results.push_back(cpOutH.getValue(1)); 7791 return; 7792 } 7793 case ISD::ATOMIC_LOAD_ADD: 7794 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7795 return; 7796 case ISD::ATOMIC_LOAD_AND: 7797 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7798 return; 7799 case ISD::ATOMIC_LOAD_NAND: 7800 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7801 return; 7802 case ISD::ATOMIC_LOAD_OR: 7803 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7804 return; 7805 case ISD::ATOMIC_LOAD_SUB: 7806 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7807 return; 7808 case ISD::ATOMIC_LOAD_XOR: 7809 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7810 return; 7811 case ISD::ATOMIC_SWAP: 7812 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7813 return; 7814 } 7815} 7816 7817const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7818 switch (Opcode) { 7819 default: return NULL; 7820 case X86ISD::BSF: return "X86ISD::BSF"; 7821 case X86ISD::BSR: return "X86ISD::BSR"; 7822 case X86ISD::SHLD: return "X86ISD::SHLD"; 7823 case X86ISD::SHRD: return "X86ISD::SHRD"; 7824 case X86ISD::FAND: return "X86ISD::FAND"; 7825 case X86ISD::FOR: return "X86ISD::FOR"; 7826 case X86ISD::FXOR: return "X86ISD::FXOR"; 7827 case X86ISD::FSRL: return "X86ISD::FSRL"; 7828 case X86ISD::FILD: return "X86ISD::FILD"; 7829 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7830 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7831 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7832 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7833 case X86ISD::FLD: return "X86ISD::FLD"; 7834 case X86ISD::FST: return "X86ISD::FST"; 7835 case X86ISD::CALL: return "X86ISD::CALL"; 7836 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7837 case X86ISD::BT: return "X86ISD::BT"; 7838 case X86ISD::CMP: return "X86ISD::CMP"; 7839 case X86ISD::COMI: return "X86ISD::COMI"; 7840 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7841 case X86ISD::SETCC: return "X86ISD::SETCC"; 7842 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7843 case X86ISD::CMOV: return "X86ISD::CMOV"; 7844 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7845 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7846 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7847 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7848 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7849 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7850 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7851 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7852 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7853 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7854 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7855 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7856 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 7857 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7858 case X86ISD::FMAX: return "X86ISD::FMAX"; 7859 case X86ISD::FMIN: return "X86ISD::FMIN"; 7860 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7861 case X86ISD::FRCP: return "X86ISD::FRCP"; 7862 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7863 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 7864 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7865 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7866 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7867 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7868 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7869 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7870 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7871 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7872 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7873 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7874 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7875 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7876 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7877 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7878 case X86ISD::VSHL: return "X86ISD::VSHL"; 7879 case X86ISD::VSRL: return "X86ISD::VSRL"; 7880 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7881 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7882 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7883 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7884 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7885 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7886 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7887 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7888 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7889 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7890 case X86ISD::ADD: return "X86ISD::ADD"; 7891 case X86ISD::SUB: return "X86ISD::SUB"; 7892 case X86ISD::SMUL: return "X86ISD::SMUL"; 7893 case X86ISD::UMUL: return "X86ISD::UMUL"; 7894 case X86ISD::INC: return "X86ISD::INC"; 7895 case X86ISD::DEC: return "X86ISD::DEC"; 7896 case X86ISD::OR: return "X86ISD::OR"; 7897 case X86ISD::XOR: return "X86ISD::XOR"; 7898 case X86ISD::AND: return "X86ISD::AND"; 7899 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7900 case X86ISD::PTEST: return "X86ISD::PTEST"; 7901 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7902 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 7903 } 7904} 7905 7906// isLegalAddressingMode - Return true if the addressing mode represented 7907// by AM is legal for this target, for a load/store of the specified type. 7908bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7909 const Type *Ty) const { 7910 // X86 supports extremely general addressing modes. 7911 CodeModel::Model M = getTargetMachine().getCodeModel(); 7912 7913 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7914 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7915 return false; 7916 7917 if (AM.BaseGV) { 7918 unsigned GVFlags = 7919 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7920 7921 // If a reference to this global requires an extra load, we can't fold it. 7922 if (isGlobalStubReference(GVFlags)) 7923 return false; 7924 7925 // If BaseGV requires a register for the PIC base, we cannot also have a 7926 // BaseReg specified. 7927 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7928 return false; 7929 7930 // If lower 4G is not available, then we must use rip-relative addressing. 7931 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7932 return false; 7933 } 7934 7935 switch (AM.Scale) { 7936 case 0: 7937 case 1: 7938 case 2: 7939 case 4: 7940 case 8: 7941 // These scales always work. 7942 break; 7943 case 3: 7944 case 5: 7945 case 9: 7946 // These scales are formed with basereg+scalereg. Only accept if there is 7947 // no basereg yet. 7948 if (AM.HasBaseReg) 7949 return false; 7950 break; 7951 default: // Other stuff never works. 7952 return false; 7953 } 7954 7955 return true; 7956} 7957 7958 7959bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7960 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7961 return false; 7962 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7963 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7964 if (NumBits1 <= NumBits2) 7965 return false; 7966 return true; 7967} 7968 7969bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7970 if (!VT1.isInteger() || !VT2.isInteger()) 7971 return false; 7972 unsigned NumBits1 = VT1.getSizeInBits(); 7973 unsigned NumBits2 = VT2.getSizeInBits(); 7974 if (NumBits1 <= NumBits2) 7975 return false; 7976 return true; 7977} 7978 7979bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7980 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7981 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7982} 7983 7984bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7985 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7986 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7987} 7988 7989bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7990 // i16 instructions are longer (0x66 prefix) and potentially slower. 7991 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7992} 7993 7994/// isShuffleMaskLegal - Targets can use this to indicate that they only 7995/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7996/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7997/// are assumed to be legal. 7998bool 7999X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 8000 EVT VT) const { 8001 // Very little shuffling can be done for 64-bit vectors right now. 8002 if (VT.getSizeInBits() == 64) 8003 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 8004 8005 // FIXME: pshufb, blends, shifts. 8006 return (VT.getVectorNumElements() == 2 || 8007 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 8008 isMOVLMask(M, VT) || 8009 isSHUFPMask(M, VT) || 8010 isPSHUFDMask(M, VT) || 8011 isPSHUFHWMask(M, VT) || 8012 isPSHUFLWMask(M, VT) || 8013 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 8014 isUNPCKLMask(M, VT) || 8015 isUNPCKHMask(M, VT) || 8016 isUNPCKL_v_undef_Mask(M, VT) || 8017 isUNPCKH_v_undef_Mask(M, VT)); 8018} 8019 8020bool 8021X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 8022 EVT VT) const { 8023 unsigned NumElts = VT.getVectorNumElements(); 8024 // FIXME: This collection of masks seems suspect. 8025 if (NumElts == 2) 8026 return true; 8027 if (NumElts == 4 && VT.getSizeInBits() == 128) { 8028 return (isMOVLMask(Mask, VT) || 8029 isCommutedMOVLMask(Mask, VT, true) || 8030 isSHUFPMask(Mask, VT) || 8031 isCommutedSHUFPMask(Mask, VT)); 8032 } 8033 return false; 8034} 8035 8036//===----------------------------------------------------------------------===// 8037// X86 Scheduler Hooks 8038//===----------------------------------------------------------------------===// 8039 8040// private utility function 8041MachineBasicBlock * 8042X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 8043 MachineBasicBlock *MBB, 8044 unsigned regOpc, 8045 unsigned immOpc, 8046 unsigned LoadOpc, 8047 unsigned CXchgOpc, 8048 unsigned notOpc, 8049 unsigned EAXreg, 8050 TargetRegisterClass *RC, 8051 bool invSrc) const { 8052 // For the atomic bitwise operator, we generate 8053 // thisMBB: 8054 // newMBB: 8055 // ld t1 = [bitinstr.addr] 8056 // op t2 = t1, [bitinstr.val] 8057 // mov EAX = t1 8058 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8059 // bz newMBB 8060 // fallthrough -->nextMBB 8061 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8062 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8063 MachineFunction::iterator MBBIter = MBB; 8064 ++MBBIter; 8065 8066 /// First build the CFG 8067 MachineFunction *F = MBB->getParent(); 8068 MachineBasicBlock *thisMBB = MBB; 8069 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8070 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8071 F->insert(MBBIter, newMBB); 8072 F->insert(MBBIter, nextMBB); 8073 8074 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8075 nextMBB->splice(nextMBB->begin(), thisMBB, 8076 llvm::next(MachineBasicBlock::iterator(bInstr)), 8077 thisMBB->end()); 8078 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8079 8080 // Update thisMBB to fall through to newMBB 8081 thisMBB->addSuccessor(newMBB); 8082 8083 // newMBB jumps to itself and fall through to nextMBB 8084 newMBB->addSuccessor(nextMBB); 8085 newMBB->addSuccessor(newMBB); 8086 8087 // Insert instructions into newMBB based on incoming instruction 8088 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8089 "unexpected number of operands"); 8090 DebugLoc dl = bInstr->getDebugLoc(); 8091 MachineOperand& destOper = bInstr->getOperand(0); 8092 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8093 int numArgs = bInstr->getNumOperands() - 1; 8094 for (int i=0; i < numArgs; ++i) 8095 argOpers[i] = &bInstr->getOperand(i+1); 8096 8097 // x86 address has 4 operands: base, index, scale, and displacement 8098 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8099 int valArgIndx = lastAddrIndx + 1; 8100 8101 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8102 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 8103 for (int i=0; i <= lastAddrIndx; ++i) 8104 (*MIB).addOperand(*argOpers[i]); 8105 8106 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 8107 if (invSrc) { 8108 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 8109 } 8110 else 8111 tt = t1; 8112 8113 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8114 assert((argOpers[valArgIndx]->isReg() || 8115 argOpers[valArgIndx]->isImm()) && 8116 "invalid operand"); 8117 if (argOpers[valArgIndx]->isReg()) 8118 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 8119 else 8120 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 8121 MIB.addReg(tt); 8122 (*MIB).addOperand(*argOpers[valArgIndx]); 8123 8124 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 8125 MIB.addReg(t1); 8126 8127 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 8128 for (int i=0; i <= lastAddrIndx; ++i) 8129 (*MIB).addOperand(*argOpers[i]); 8130 MIB.addReg(t2); 8131 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8132 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8133 bInstr->memoperands_end()); 8134 8135 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 8136 MIB.addReg(EAXreg); 8137 8138 // insert branch 8139 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8140 8141 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8142 return nextMBB; 8143} 8144 8145// private utility function: 64 bit atomics on 32 bit host. 8146MachineBasicBlock * 8147X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8148 MachineBasicBlock *MBB, 8149 unsigned regOpcL, 8150 unsigned regOpcH, 8151 unsigned immOpcL, 8152 unsigned immOpcH, 8153 bool invSrc) const { 8154 // For the atomic bitwise operator, we generate 8155 // thisMBB (instructions are in pairs, except cmpxchg8b) 8156 // ld t1,t2 = [bitinstr.addr] 8157 // newMBB: 8158 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8159 // op t5, t6 <- out1, out2, [bitinstr.val] 8160 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8161 // mov ECX, EBX <- t5, t6 8162 // mov EAX, EDX <- t1, t2 8163 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8164 // mov t3, t4 <- EAX, EDX 8165 // bz newMBB 8166 // result in out1, out2 8167 // fallthrough -->nextMBB 8168 8169 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8170 const unsigned LoadOpc = X86::MOV32rm; 8171 const unsigned NotOpc = X86::NOT32r; 8172 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8173 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8174 MachineFunction::iterator MBBIter = MBB; 8175 ++MBBIter; 8176 8177 /// First build the CFG 8178 MachineFunction *F = MBB->getParent(); 8179 MachineBasicBlock *thisMBB = MBB; 8180 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8181 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8182 F->insert(MBBIter, newMBB); 8183 F->insert(MBBIter, nextMBB); 8184 8185 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8186 nextMBB->splice(nextMBB->begin(), thisMBB, 8187 llvm::next(MachineBasicBlock::iterator(bInstr)), 8188 thisMBB->end()); 8189 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8190 8191 // Update thisMBB to fall through to newMBB 8192 thisMBB->addSuccessor(newMBB); 8193 8194 // newMBB jumps to itself and fall through to nextMBB 8195 newMBB->addSuccessor(nextMBB); 8196 newMBB->addSuccessor(newMBB); 8197 8198 DebugLoc dl = bInstr->getDebugLoc(); 8199 // Insert instructions into newMBB based on incoming instruction 8200 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8201 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 8202 "unexpected number of operands"); 8203 MachineOperand& dest1Oper = bInstr->getOperand(0); 8204 MachineOperand& dest2Oper = bInstr->getOperand(1); 8205 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8206 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 8207 argOpers[i] = &bInstr->getOperand(i+2); 8208 8209 // We use some of the operands multiple times, so conservatively just 8210 // clear any kill flags that might be present. 8211 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 8212 argOpers[i]->setIsKill(false); 8213 } 8214 8215 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8216 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8217 8218 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8219 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8220 for (int i=0; i <= lastAddrIndx; ++i) 8221 (*MIB).addOperand(*argOpers[i]); 8222 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8223 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8224 // add 4 to displacement. 8225 for (int i=0; i <= lastAddrIndx-2; ++i) 8226 (*MIB).addOperand(*argOpers[i]); 8227 MachineOperand newOp3 = *(argOpers[3]); 8228 if (newOp3.isImm()) 8229 newOp3.setImm(newOp3.getImm()+4); 8230 else 8231 newOp3.setOffset(newOp3.getOffset()+4); 8232 (*MIB).addOperand(newOp3); 8233 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8234 8235 // t3/4 are defined later, at the bottom of the loop 8236 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8237 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8238 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8239 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8240 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8241 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8242 8243 // The subsequent operations should be using the destination registers of 8244 //the PHI instructions. 8245 if (invSrc) { 8246 t1 = F->getRegInfo().createVirtualRegister(RC); 8247 t2 = F->getRegInfo().createVirtualRegister(RC); 8248 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8249 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8250 } else { 8251 t1 = dest1Oper.getReg(); 8252 t2 = dest2Oper.getReg(); 8253 } 8254 8255 int valArgIndx = lastAddrIndx + 1; 8256 assert((argOpers[valArgIndx]->isReg() || 8257 argOpers[valArgIndx]->isImm()) && 8258 "invalid operand"); 8259 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8260 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8261 if (argOpers[valArgIndx]->isReg()) 8262 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8263 else 8264 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8265 if (regOpcL != X86::MOV32rr) 8266 MIB.addReg(t1); 8267 (*MIB).addOperand(*argOpers[valArgIndx]); 8268 assert(argOpers[valArgIndx + 1]->isReg() == 8269 argOpers[valArgIndx]->isReg()); 8270 assert(argOpers[valArgIndx + 1]->isImm() == 8271 argOpers[valArgIndx]->isImm()); 8272 if (argOpers[valArgIndx + 1]->isReg()) 8273 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8274 else 8275 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8276 if (regOpcH != X86::MOV32rr) 8277 MIB.addReg(t2); 8278 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8279 8280 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 8281 MIB.addReg(t1); 8282 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 8283 MIB.addReg(t2); 8284 8285 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 8286 MIB.addReg(t5); 8287 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 8288 MIB.addReg(t6); 8289 8290 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8291 for (int i=0; i <= lastAddrIndx; ++i) 8292 (*MIB).addOperand(*argOpers[i]); 8293 8294 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8295 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8296 bInstr->memoperands_end()); 8297 8298 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 8299 MIB.addReg(X86::EAX); 8300 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 8301 MIB.addReg(X86::EDX); 8302 8303 // insert branch 8304 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8305 8306 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8307 return nextMBB; 8308} 8309 8310// private utility function 8311MachineBasicBlock * 8312X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8313 MachineBasicBlock *MBB, 8314 unsigned cmovOpc) const { 8315 // For the atomic min/max operator, we generate 8316 // thisMBB: 8317 // newMBB: 8318 // ld t1 = [min/max.addr] 8319 // mov t2 = [min/max.val] 8320 // cmp t1, t2 8321 // cmov[cond] t2 = t1 8322 // mov EAX = t1 8323 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8324 // bz newMBB 8325 // fallthrough -->nextMBB 8326 // 8327 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8328 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8329 MachineFunction::iterator MBBIter = MBB; 8330 ++MBBIter; 8331 8332 /// First build the CFG 8333 MachineFunction *F = MBB->getParent(); 8334 MachineBasicBlock *thisMBB = MBB; 8335 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8336 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8337 F->insert(MBBIter, newMBB); 8338 F->insert(MBBIter, nextMBB); 8339 8340 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8341 nextMBB->splice(nextMBB->begin(), thisMBB, 8342 llvm::next(MachineBasicBlock::iterator(mInstr)), 8343 thisMBB->end()); 8344 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8345 8346 // Update thisMBB to fall through to newMBB 8347 thisMBB->addSuccessor(newMBB); 8348 8349 // newMBB jumps to newMBB and fall through to nextMBB 8350 newMBB->addSuccessor(nextMBB); 8351 newMBB->addSuccessor(newMBB); 8352 8353 DebugLoc dl = mInstr->getDebugLoc(); 8354 // Insert instructions into newMBB based on incoming instruction 8355 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8356 "unexpected number of operands"); 8357 MachineOperand& destOper = mInstr->getOperand(0); 8358 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8359 int numArgs = mInstr->getNumOperands() - 1; 8360 for (int i=0; i < numArgs; ++i) 8361 argOpers[i] = &mInstr->getOperand(i+1); 8362 8363 // x86 address has 4 operands: base, index, scale, and displacement 8364 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8365 int valArgIndx = lastAddrIndx + 1; 8366 8367 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8368 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8369 for (int i=0; i <= lastAddrIndx; ++i) 8370 (*MIB).addOperand(*argOpers[i]); 8371 8372 // We only support register and immediate values 8373 assert((argOpers[valArgIndx]->isReg() || 8374 argOpers[valArgIndx]->isImm()) && 8375 "invalid operand"); 8376 8377 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8378 if (argOpers[valArgIndx]->isReg()) 8379 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 8380 else 8381 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8382 (*MIB).addOperand(*argOpers[valArgIndx]); 8383 8384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 8385 MIB.addReg(t1); 8386 8387 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8388 MIB.addReg(t1); 8389 MIB.addReg(t2); 8390 8391 // Generate movc 8392 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8393 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8394 MIB.addReg(t2); 8395 MIB.addReg(t1); 8396 8397 // Cmp and exchange if none has modified the memory location 8398 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8399 for (int i=0; i <= lastAddrIndx; ++i) 8400 (*MIB).addOperand(*argOpers[i]); 8401 MIB.addReg(t3); 8402 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8403 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8404 mInstr->memoperands_end()); 8405 8406 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 8407 MIB.addReg(X86::EAX); 8408 8409 // insert branch 8410 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8411 8412 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 8413 return nextMBB; 8414} 8415 8416// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8417// all of this code can be replaced with that in the .td file. 8418MachineBasicBlock * 8419X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8420 unsigned numArgs, bool memArg) const { 8421 8422 DebugLoc dl = MI->getDebugLoc(); 8423 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8424 8425 unsigned Opc; 8426 if (memArg) 8427 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8428 else 8429 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8430 8431 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8432 8433 for (unsigned i = 0; i < numArgs; ++i) { 8434 MachineOperand &Op = MI->getOperand(i+1); 8435 8436 if (!(Op.isReg() && Op.isImplicit())) 8437 MIB.addOperand(Op); 8438 } 8439 8440 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8441 .addReg(X86::XMM0); 8442 8443 MI->eraseFromParent(); 8444 8445 return BB; 8446} 8447 8448MachineBasicBlock * 8449X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8450 MachineInstr *MI, 8451 MachineBasicBlock *MBB) const { 8452 // Emit code to save XMM registers to the stack. The ABI says that the 8453 // number of registers to save is given in %al, so it's theoretically 8454 // possible to do an indirect jump trick to avoid saving all of them, 8455 // however this code takes a simpler approach and just executes all 8456 // of the stores if %al is non-zero. It's less code, and it's probably 8457 // easier on the hardware branch predictor, and stores aren't all that 8458 // expensive anyway. 8459 8460 // Create the new basic blocks. One block contains all the XMM stores, 8461 // and one block is the final destination regardless of whether any 8462 // stores were performed. 8463 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8464 MachineFunction *F = MBB->getParent(); 8465 MachineFunction::iterator MBBIter = MBB; 8466 ++MBBIter; 8467 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8468 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8469 F->insert(MBBIter, XMMSaveMBB); 8470 F->insert(MBBIter, EndMBB); 8471 8472 // Transfer the remainder of MBB and its successor edges to EndMBB. 8473 EndMBB->splice(EndMBB->begin(), MBB, 8474 llvm::next(MachineBasicBlock::iterator(MI)), 8475 MBB->end()); 8476 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 8477 8478 // The original block will now fall through to the XMM save block. 8479 MBB->addSuccessor(XMMSaveMBB); 8480 // The XMMSaveMBB will fall through to the end block. 8481 XMMSaveMBB->addSuccessor(EndMBB); 8482 8483 // Now add the instructions. 8484 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8485 DebugLoc DL = MI->getDebugLoc(); 8486 8487 unsigned CountReg = MI->getOperand(0).getReg(); 8488 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8489 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8490 8491 if (!Subtarget->isTargetWin64()) { 8492 // If %al is 0, branch around the XMM save block. 8493 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8494 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8495 MBB->addSuccessor(EndMBB); 8496 } 8497 8498 // In the XMM save block, save all the XMM argument registers. 8499 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8500 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8501 MachineMemOperand *MMO = 8502 F->getMachineMemOperand( 8503 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8504 MachineMemOperand::MOStore, Offset, 8505 /*Size=*/16, /*Align=*/16); 8506 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8507 .addFrameIndex(RegSaveFrameIndex) 8508 .addImm(/*Scale=*/1) 8509 .addReg(/*IndexReg=*/0) 8510 .addImm(/*Disp=*/Offset) 8511 .addReg(/*Segment=*/0) 8512 .addReg(MI->getOperand(i).getReg()) 8513 .addMemOperand(MMO); 8514 } 8515 8516 MI->eraseFromParent(); // The pseudo instruction is gone now. 8517 8518 return EndMBB; 8519} 8520 8521MachineBasicBlock * 8522X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8523 MachineBasicBlock *BB) const { 8524 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8525 DebugLoc DL = MI->getDebugLoc(); 8526 8527 // To "insert" a SELECT_CC instruction, we actually have to insert the 8528 // diamond control-flow pattern. The incoming instruction knows the 8529 // destination vreg to set, the condition code register to branch on, the 8530 // true/false values to select between, and a branch opcode to use. 8531 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8532 MachineFunction::iterator It = BB; 8533 ++It; 8534 8535 // thisMBB: 8536 // ... 8537 // TrueVal = ... 8538 // cmpTY ccX, r1, r2 8539 // bCC copy1MBB 8540 // fallthrough --> copy0MBB 8541 MachineBasicBlock *thisMBB = BB; 8542 MachineFunction *F = BB->getParent(); 8543 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8544 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8545 F->insert(It, copy0MBB); 8546 F->insert(It, sinkMBB); 8547 8548 // If the EFLAGS register isn't dead in the terminator, then claim that it's 8549 // live into the sink and copy blocks. 8550 const MachineFunction *MF = BB->getParent(); 8551 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 8552 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 8553 8554 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 8555 const MachineOperand &MO = MI->getOperand(I); 8556 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 8557 unsigned Reg = MO.getReg(); 8558 if (Reg != X86::EFLAGS) continue; 8559 copy0MBB->addLiveIn(Reg); 8560 sinkMBB->addLiveIn(Reg); 8561 } 8562 8563 // Transfer the remainder of BB and its successor edges to sinkMBB. 8564 sinkMBB->splice(sinkMBB->begin(), BB, 8565 llvm::next(MachineBasicBlock::iterator(MI)), 8566 BB->end()); 8567 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 8568 8569 // Add the true and fallthrough blocks as its successors. 8570 BB->addSuccessor(copy0MBB); 8571 BB->addSuccessor(sinkMBB); 8572 8573 // Create the conditional branch instruction. 8574 unsigned Opc = 8575 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8576 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8577 8578 // copy0MBB: 8579 // %FalseValue = ... 8580 // # fallthrough to sinkMBB 8581 copy0MBB->addSuccessor(sinkMBB); 8582 8583 // sinkMBB: 8584 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8585 // ... 8586 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 8587 TII->get(X86::PHI), MI->getOperand(0).getReg()) 8588 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8589 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8590 8591 MI->eraseFromParent(); // The pseudo instruction is gone now. 8592 return sinkMBB; 8593} 8594 8595MachineBasicBlock * 8596X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 8597 MachineBasicBlock *BB) const { 8598 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8599 DebugLoc DL = MI->getDebugLoc(); 8600 8601 // The lowering is pretty easy: we're just emitting the call to _alloca. The 8602 // non-trivial part is impdef of ESP. 8603 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 8604 // mingw-w64. 8605 8606 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 8607 .addExternalSymbol("_alloca") 8608 .addReg(X86::EAX, RegState::Implicit) 8609 .addReg(X86::ESP, RegState::Implicit) 8610 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 8611 .addReg(X86::ESP, RegState::Define | RegState::Implicit); 8612 8613 MI->eraseFromParent(); // The pseudo instruction is gone now. 8614 return BB; 8615} 8616 8617MachineBasicBlock * 8618X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 8619 MachineBasicBlock *BB) const { 8620 // This is pretty easy. We're taking the value that we received from 8621 // our load from the relocation, sticking it in either RDI (x86-64) 8622 // or EAX and doing an indirect call. The return value will then 8623 // be in the normal return register. 8624 const X86InstrInfo *TII 8625 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 8626 DebugLoc DL = MI->getDebugLoc(); 8627 MachineFunction *F = BB->getParent(); 8628 8629 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 8630 8631 if (Subtarget->is64Bit()) { 8632 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 8633 TII->get(X86::MOV64rm), X86::RDI) 8634 .addReg(X86::RIP) 8635 .addImm(0).addReg(0) 8636 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 8637 MI->getOperand(3).getTargetFlags()) 8638 .addReg(0); 8639 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 8640 addDirectMem(MIB, X86::RDI); 8641 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 8642 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 8643 TII->get(X86::MOV32rm), X86::EAX) 8644 .addReg(0) 8645 .addImm(0).addReg(0) 8646 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 8647 MI->getOperand(3).getTargetFlags()) 8648 .addReg(0); 8649 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 8650 addDirectMem(MIB, X86::EAX); 8651 } else { 8652 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 8653 TII->get(X86::MOV32rm), X86::EAX) 8654 .addReg(TII->getGlobalBaseReg(F)) 8655 .addImm(0).addReg(0) 8656 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 8657 MI->getOperand(3).getTargetFlags()) 8658 .addReg(0); 8659 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 8660 addDirectMem(MIB, X86::EAX); 8661 } 8662 8663 MI->eraseFromParent(); // The pseudo instruction is gone now. 8664 return BB; 8665} 8666 8667MachineBasicBlock * 8668X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8669 MachineBasicBlock *BB) const { 8670 switch (MI->getOpcode()) { 8671 default: assert(false && "Unexpected instr type to insert"); 8672 case X86::MINGW_ALLOCA: 8673 return EmitLoweredMingwAlloca(MI, BB); 8674 case X86::TLSCall_32: 8675 case X86::TLSCall_64: 8676 return EmitLoweredTLSCall(MI, BB); 8677 case X86::CMOV_GR8: 8678 case X86::CMOV_V1I64: 8679 case X86::CMOV_FR32: 8680 case X86::CMOV_FR64: 8681 case X86::CMOV_V4F32: 8682 case X86::CMOV_V2F64: 8683 case X86::CMOV_V2I64: 8684 case X86::CMOV_GR16: 8685 case X86::CMOV_GR32: 8686 case X86::CMOV_RFP32: 8687 case X86::CMOV_RFP64: 8688 case X86::CMOV_RFP80: 8689 return EmitLoweredSelect(MI, BB); 8690 8691 case X86::FP32_TO_INT16_IN_MEM: 8692 case X86::FP32_TO_INT32_IN_MEM: 8693 case X86::FP32_TO_INT64_IN_MEM: 8694 case X86::FP64_TO_INT16_IN_MEM: 8695 case X86::FP64_TO_INT32_IN_MEM: 8696 case X86::FP64_TO_INT64_IN_MEM: 8697 case X86::FP80_TO_INT16_IN_MEM: 8698 case X86::FP80_TO_INT32_IN_MEM: 8699 case X86::FP80_TO_INT64_IN_MEM: { 8700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8701 DebugLoc DL = MI->getDebugLoc(); 8702 8703 // Change the floating point control register to use "round towards zero" 8704 // mode when truncating to an integer value. 8705 MachineFunction *F = BB->getParent(); 8706 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8707 addFrameReference(BuildMI(*BB, MI, DL, 8708 TII->get(X86::FNSTCW16m)), CWFrameIdx); 8709 8710 // Load the old value of the high byte of the control word... 8711 unsigned OldCW = 8712 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8713 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 8714 CWFrameIdx); 8715 8716 // Set the high part to be round to zero... 8717 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8718 .addImm(0xC7F); 8719 8720 // Reload the modified control word now... 8721 addFrameReference(BuildMI(*BB, MI, DL, 8722 TII->get(X86::FLDCW16m)), CWFrameIdx); 8723 8724 // Restore the memory image of control word to original value 8725 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8726 .addReg(OldCW); 8727 8728 // Get the X86 opcode to use. 8729 unsigned Opc; 8730 switch (MI->getOpcode()) { 8731 default: llvm_unreachable("illegal opcode!"); 8732 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8733 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8734 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8735 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8736 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8737 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8738 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8739 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8740 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8741 } 8742 8743 X86AddressMode AM; 8744 MachineOperand &Op = MI->getOperand(0); 8745 if (Op.isReg()) { 8746 AM.BaseType = X86AddressMode::RegBase; 8747 AM.Base.Reg = Op.getReg(); 8748 } else { 8749 AM.BaseType = X86AddressMode::FrameIndexBase; 8750 AM.Base.FrameIndex = Op.getIndex(); 8751 } 8752 Op = MI->getOperand(1); 8753 if (Op.isImm()) 8754 AM.Scale = Op.getImm(); 8755 Op = MI->getOperand(2); 8756 if (Op.isImm()) 8757 AM.IndexReg = Op.getImm(); 8758 Op = MI->getOperand(3); 8759 if (Op.isGlobal()) { 8760 AM.GV = Op.getGlobal(); 8761 } else { 8762 AM.Disp = Op.getImm(); 8763 } 8764 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 8765 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 8766 8767 // Reload the original control word now. 8768 addFrameReference(BuildMI(*BB, MI, DL, 8769 TII->get(X86::FLDCW16m)), CWFrameIdx); 8770 8771 MI->eraseFromParent(); // The pseudo instruction is gone now. 8772 return BB; 8773 } 8774 // String/text processing lowering. 8775 case X86::PCMPISTRM128REG: 8776 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8777 case X86::PCMPISTRM128MEM: 8778 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8779 case X86::PCMPESTRM128REG: 8780 return EmitPCMP(MI, BB, 5, false /* in mem */); 8781 case X86::PCMPESTRM128MEM: 8782 return EmitPCMP(MI, BB, 5, true /* in mem */); 8783 8784 // Atomic Lowering. 8785 case X86::ATOMAND32: 8786 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8787 X86::AND32ri, X86::MOV32rm, 8788 X86::LCMPXCHG32, 8789 X86::NOT32r, X86::EAX, 8790 X86::GR32RegisterClass); 8791 case X86::ATOMOR32: 8792 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8793 X86::OR32ri, X86::MOV32rm, 8794 X86::LCMPXCHG32, 8795 X86::NOT32r, X86::EAX, 8796 X86::GR32RegisterClass); 8797 case X86::ATOMXOR32: 8798 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8799 X86::XOR32ri, X86::MOV32rm, 8800 X86::LCMPXCHG32, 8801 X86::NOT32r, X86::EAX, 8802 X86::GR32RegisterClass); 8803 case X86::ATOMNAND32: 8804 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8805 X86::AND32ri, X86::MOV32rm, 8806 X86::LCMPXCHG32, 8807 X86::NOT32r, X86::EAX, 8808 X86::GR32RegisterClass, true); 8809 case X86::ATOMMIN32: 8810 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8811 case X86::ATOMMAX32: 8812 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8813 case X86::ATOMUMIN32: 8814 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8815 case X86::ATOMUMAX32: 8816 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8817 8818 case X86::ATOMAND16: 8819 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8820 X86::AND16ri, X86::MOV16rm, 8821 X86::LCMPXCHG16, 8822 X86::NOT16r, X86::AX, 8823 X86::GR16RegisterClass); 8824 case X86::ATOMOR16: 8825 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8826 X86::OR16ri, X86::MOV16rm, 8827 X86::LCMPXCHG16, 8828 X86::NOT16r, X86::AX, 8829 X86::GR16RegisterClass); 8830 case X86::ATOMXOR16: 8831 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8832 X86::XOR16ri, X86::MOV16rm, 8833 X86::LCMPXCHG16, 8834 X86::NOT16r, X86::AX, 8835 X86::GR16RegisterClass); 8836 case X86::ATOMNAND16: 8837 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8838 X86::AND16ri, X86::MOV16rm, 8839 X86::LCMPXCHG16, 8840 X86::NOT16r, X86::AX, 8841 X86::GR16RegisterClass, true); 8842 case X86::ATOMMIN16: 8843 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8844 case X86::ATOMMAX16: 8845 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8846 case X86::ATOMUMIN16: 8847 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8848 case X86::ATOMUMAX16: 8849 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8850 8851 case X86::ATOMAND8: 8852 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8853 X86::AND8ri, X86::MOV8rm, 8854 X86::LCMPXCHG8, 8855 X86::NOT8r, X86::AL, 8856 X86::GR8RegisterClass); 8857 case X86::ATOMOR8: 8858 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8859 X86::OR8ri, X86::MOV8rm, 8860 X86::LCMPXCHG8, 8861 X86::NOT8r, X86::AL, 8862 X86::GR8RegisterClass); 8863 case X86::ATOMXOR8: 8864 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8865 X86::XOR8ri, X86::MOV8rm, 8866 X86::LCMPXCHG8, 8867 X86::NOT8r, X86::AL, 8868 X86::GR8RegisterClass); 8869 case X86::ATOMNAND8: 8870 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8871 X86::AND8ri, X86::MOV8rm, 8872 X86::LCMPXCHG8, 8873 X86::NOT8r, X86::AL, 8874 X86::GR8RegisterClass, true); 8875 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8876 // This group is for 64-bit host. 8877 case X86::ATOMAND64: 8878 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8879 X86::AND64ri32, X86::MOV64rm, 8880 X86::LCMPXCHG64, 8881 X86::NOT64r, X86::RAX, 8882 X86::GR64RegisterClass); 8883 case X86::ATOMOR64: 8884 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8885 X86::OR64ri32, X86::MOV64rm, 8886 X86::LCMPXCHG64, 8887 X86::NOT64r, X86::RAX, 8888 X86::GR64RegisterClass); 8889 case X86::ATOMXOR64: 8890 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8891 X86::XOR64ri32, X86::MOV64rm, 8892 X86::LCMPXCHG64, 8893 X86::NOT64r, X86::RAX, 8894 X86::GR64RegisterClass); 8895 case X86::ATOMNAND64: 8896 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8897 X86::AND64ri32, X86::MOV64rm, 8898 X86::LCMPXCHG64, 8899 X86::NOT64r, X86::RAX, 8900 X86::GR64RegisterClass, true); 8901 case X86::ATOMMIN64: 8902 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8903 case X86::ATOMMAX64: 8904 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8905 case X86::ATOMUMIN64: 8906 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8907 case X86::ATOMUMAX64: 8908 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8909 8910 // This group does 64-bit operations on a 32-bit host. 8911 case X86::ATOMAND6432: 8912 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8913 X86::AND32rr, X86::AND32rr, 8914 X86::AND32ri, X86::AND32ri, 8915 false); 8916 case X86::ATOMOR6432: 8917 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8918 X86::OR32rr, X86::OR32rr, 8919 X86::OR32ri, X86::OR32ri, 8920 false); 8921 case X86::ATOMXOR6432: 8922 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8923 X86::XOR32rr, X86::XOR32rr, 8924 X86::XOR32ri, X86::XOR32ri, 8925 false); 8926 case X86::ATOMNAND6432: 8927 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8928 X86::AND32rr, X86::AND32rr, 8929 X86::AND32ri, X86::AND32ri, 8930 true); 8931 case X86::ATOMADD6432: 8932 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8933 X86::ADD32rr, X86::ADC32rr, 8934 X86::ADD32ri, X86::ADC32ri, 8935 false); 8936 case X86::ATOMSUB6432: 8937 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8938 X86::SUB32rr, X86::SBB32rr, 8939 X86::SUB32ri, X86::SBB32ri, 8940 false); 8941 case X86::ATOMSWAP6432: 8942 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8943 X86::MOV32rr, X86::MOV32rr, 8944 X86::MOV32ri, X86::MOV32ri, 8945 false); 8946 case X86::VASTART_SAVE_XMM_REGS: 8947 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8948 } 8949} 8950 8951//===----------------------------------------------------------------------===// 8952// X86 Optimization Hooks 8953//===----------------------------------------------------------------------===// 8954 8955void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8956 const APInt &Mask, 8957 APInt &KnownZero, 8958 APInt &KnownOne, 8959 const SelectionDAG &DAG, 8960 unsigned Depth) const { 8961 unsigned Opc = Op.getOpcode(); 8962 assert((Opc >= ISD::BUILTIN_OP_END || 8963 Opc == ISD::INTRINSIC_WO_CHAIN || 8964 Opc == ISD::INTRINSIC_W_CHAIN || 8965 Opc == ISD::INTRINSIC_VOID) && 8966 "Should use MaskedValueIsZero if you don't know whether Op" 8967 " is a target node!"); 8968 8969 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8970 switch (Opc) { 8971 default: break; 8972 case X86ISD::ADD: 8973 case X86ISD::SUB: 8974 case X86ISD::SMUL: 8975 case X86ISD::UMUL: 8976 case X86ISD::INC: 8977 case X86ISD::DEC: 8978 case X86ISD::OR: 8979 case X86ISD::XOR: 8980 case X86ISD::AND: 8981 // These nodes' second result is a boolean. 8982 if (Op.getResNo() == 0) 8983 break; 8984 // Fallthrough 8985 case X86ISD::SETCC: 8986 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8987 Mask.getBitWidth() - 1); 8988 break; 8989 } 8990} 8991 8992/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8993/// node is a GlobalAddress + offset. 8994bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8995 const GlobalValue* &GA, 8996 int64_t &Offset) const { 8997 if (N->getOpcode() == X86ISD::Wrapper) { 8998 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8999 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 9000 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 9001 return true; 9002 } 9003 } 9004 return TargetLowering::isGAPlusOffset(N, GA, Offset); 9005} 9006 9007/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 9008/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 9009/// if the load addresses are consecutive, non-overlapping, and in the right 9010/// order. 9011static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 9012 const TargetLowering &TLI) { 9013 DebugLoc dl = N->getDebugLoc(); 9014 EVT VT = N->getValueType(0); 9015 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9016 9017 if (VT.getSizeInBits() != 128) 9018 return SDValue(); 9019 9020 SmallVector<SDValue, 16> Elts; 9021 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 9022 Elts.push_back(DAG.getShuffleScalarElt(SVN, i)); 9023 9024 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 9025} 9026 9027/// PerformShuffleCombine - Detect vector gather/scatter index generation 9028/// and convert it from being a bunch of shuffles and extracts to a simple 9029/// store and scalar loads to extract the elements. 9030static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 9031 const TargetLowering &TLI) { 9032 SDValue InputVector = N->getOperand(0); 9033 9034 // Only operate on vectors of 4 elements, where the alternative shuffling 9035 // gets to be more expensive. 9036 if (InputVector.getValueType() != MVT::v4i32) 9037 return SDValue(); 9038 9039 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 9040 // single use which is a sign-extend or zero-extend, and all elements are 9041 // used. 9042 SmallVector<SDNode *, 4> Uses; 9043 unsigned ExtractedElements = 0; 9044 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 9045 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 9046 if (UI.getUse().getResNo() != InputVector.getResNo()) 9047 return SDValue(); 9048 9049 SDNode *Extract = *UI; 9050 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 9051 return SDValue(); 9052 9053 if (Extract->getValueType(0) != MVT::i32) 9054 return SDValue(); 9055 if (!Extract->hasOneUse()) 9056 return SDValue(); 9057 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 9058 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 9059 return SDValue(); 9060 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 9061 return SDValue(); 9062 9063 // Record which element was extracted. 9064 ExtractedElements |= 9065 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 9066 9067 Uses.push_back(Extract); 9068 } 9069 9070 // If not all the elements were used, this may not be worthwhile. 9071 if (ExtractedElements != 15) 9072 return SDValue(); 9073 9074 // Ok, we've now decided to do the transformation. 9075 DebugLoc dl = InputVector.getDebugLoc(); 9076 9077 // Store the value to a temporary stack slot. 9078 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 9079 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 9080 0, false, false, 0); 9081 9082 // Replace each use (extract) with a load of the appropriate element. 9083 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 9084 UE = Uses.end(); UI != UE; ++UI) { 9085 SDNode *Extract = *UI; 9086 9087 // Compute the element's address. 9088 SDValue Idx = Extract->getOperand(1); 9089 unsigned EltSize = 9090 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 9091 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 9092 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 9093 9094 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), 9095 OffsetVal, StackPtr); 9096 9097 // Load the scalar. 9098 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 9099 ScalarAddr, NULL, 0, false, false, 0); 9100 9101 // Replace the exact with the load. 9102 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 9103 } 9104 9105 // The replacement was made in place; don't return anything. 9106 return SDValue(); 9107} 9108 9109/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 9110static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 9111 const X86Subtarget *Subtarget) { 9112 DebugLoc DL = N->getDebugLoc(); 9113 SDValue Cond = N->getOperand(0); 9114 // Get the LHS/RHS of the select. 9115 SDValue LHS = N->getOperand(1); 9116 SDValue RHS = N->getOperand(2); 9117 9118 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 9119 // instructions match the semantics of the common C idiom x<y?x:y but not 9120 // x<=y?x:y, because of how they handle negative zero (which can be 9121 // ignored in unsafe-math mode). 9122 if (Subtarget->hasSSE2() && 9123 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 9124 Cond.getOpcode() == ISD::SETCC) { 9125 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 9126 9127 unsigned Opcode = 0; 9128 // Check for x CC y ? x : y. 9129 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 9130 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 9131 switch (CC) { 9132 default: break; 9133 case ISD::SETULT: 9134 // Converting this to a min would handle NaNs incorrectly, and swapping 9135 // the operands would cause it to handle comparisons between positive 9136 // and negative zero incorrectly. 9137 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9138 if (!UnsafeFPMath && 9139 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9140 break; 9141 std::swap(LHS, RHS); 9142 } 9143 Opcode = X86ISD::FMIN; 9144 break; 9145 case ISD::SETOLE: 9146 // Converting this to a min would handle comparisons between positive 9147 // and negative zero incorrectly. 9148 if (!UnsafeFPMath && 9149 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9150 break; 9151 Opcode = X86ISD::FMIN; 9152 break; 9153 case ISD::SETULE: 9154 // Converting this to a min would handle both negative zeros and NaNs 9155 // incorrectly, but we can swap the operands to fix both. 9156 std::swap(LHS, RHS); 9157 case ISD::SETOLT: 9158 case ISD::SETLT: 9159 case ISD::SETLE: 9160 Opcode = X86ISD::FMIN; 9161 break; 9162 9163 case ISD::SETOGE: 9164 // Converting this to a max would handle comparisons between positive 9165 // and negative zero incorrectly. 9166 if (!UnsafeFPMath && 9167 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9168 break; 9169 Opcode = X86ISD::FMAX; 9170 break; 9171 case ISD::SETUGT: 9172 // Converting this to a max would handle NaNs incorrectly, and swapping 9173 // the operands would cause it to handle comparisons between positive 9174 // and negative zero incorrectly. 9175 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9176 if (!UnsafeFPMath && 9177 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9178 break; 9179 std::swap(LHS, RHS); 9180 } 9181 Opcode = X86ISD::FMAX; 9182 break; 9183 case ISD::SETUGE: 9184 // Converting this to a max would handle both negative zeros and NaNs 9185 // incorrectly, but we can swap the operands to fix both. 9186 std::swap(LHS, RHS); 9187 case ISD::SETOGT: 9188 case ISD::SETGT: 9189 case ISD::SETGE: 9190 Opcode = X86ISD::FMAX; 9191 break; 9192 } 9193 // Check for x CC y ? y : x -- a min/max with reversed arms. 9194 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9195 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9196 switch (CC) { 9197 default: break; 9198 case ISD::SETOGE: 9199 // Converting this to a min would handle comparisons between positive 9200 // and negative zero incorrectly, and swapping the operands would 9201 // cause it to handle NaNs incorrectly. 9202 if (!UnsafeFPMath && 9203 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9204 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9205 break; 9206 std::swap(LHS, RHS); 9207 } 9208 Opcode = X86ISD::FMIN; 9209 break; 9210 case ISD::SETUGT: 9211 // Converting this to a min would handle NaNs incorrectly. 9212 if (!UnsafeFPMath && 9213 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9214 break; 9215 Opcode = X86ISD::FMIN; 9216 break; 9217 case ISD::SETUGE: 9218 // Converting this to a min would handle both negative zeros and NaNs 9219 // incorrectly, but we can swap the operands to fix both. 9220 std::swap(LHS, RHS); 9221 case ISD::SETOGT: 9222 case ISD::SETGT: 9223 case ISD::SETGE: 9224 Opcode = X86ISD::FMIN; 9225 break; 9226 9227 case ISD::SETULT: 9228 // Converting this to a max would handle NaNs incorrectly. 9229 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9230 break; 9231 Opcode = X86ISD::FMAX; 9232 break; 9233 case ISD::SETOLE: 9234 // Converting this to a max would handle comparisons between positive 9235 // and negative zero incorrectly, and swapping the operands would 9236 // cause it to handle NaNs incorrectly. 9237 if (!UnsafeFPMath && 9238 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9239 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9240 break; 9241 std::swap(LHS, RHS); 9242 } 9243 Opcode = X86ISD::FMAX; 9244 break; 9245 case ISD::SETULE: 9246 // Converting this to a max would handle both negative zeros and NaNs 9247 // incorrectly, but we can swap the operands to fix both. 9248 std::swap(LHS, RHS); 9249 case ISD::SETOLT: 9250 case ISD::SETLT: 9251 case ISD::SETLE: 9252 Opcode = X86ISD::FMAX; 9253 break; 9254 } 9255 } 9256 9257 if (Opcode) 9258 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9259 } 9260 9261 // If this is a select between two integer constants, try to do some 9262 // optimizations. 9263 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9264 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9265 // Don't do this for crazy integer types. 9266 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9267 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9268 // so that TrueC (the true value) is larger than FalseC. 9269 bool NeedsCondInvert = false; 9270 9271 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9272 // Efficiently invertible. 9273 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9274 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9275 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9276 NeedsCondInvert = true; 9277 std::swap(TrueC, FalseC); 9278 } 9279 9280 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9281 if (FalseC->getAPIntValue() == 0 && 9282 TrueC->getAPIntValue().isPowerOf2()) { 9283 if (NeedsCondInvert) // Invert the condition if needed. 9284 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9285 DAG.getConstant(1, Cond.getValueType())); 9286 9287 // Zero extend the condition if needed. 9288 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9289 9290 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9291 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9292 DAG.getConstant(ShAmt, MVT::i8)); 9293 } 9294 9295 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9296 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9297 if (NeedsCondInvert) // Invert the condition if needed. 9298 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9299 DAG.getConstant(1, Cond.getValueType())); 9300 9301 // Zero extend the condition if needed. 9302 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9303 FalseC->getValueType(0), Cond); 9304 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9305 SDValue(FalseC, 0)); 9306 } 9307 9308 // Optimize cases that will turn into an LEA instruction. This requires 9309 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9310 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9311 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9312 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9313 9314 bool isFastMultiplier = false; 9315 if (Diff < 10) { 9316 switch ((unsigned char)Diff) { 9317 default: break; 9318 case 1: // result = add base, cond 9319 case 2: // result = lea base( , cond*2) 9320 case 3: // result = lea base(cond, cond*2) 9321 case 4: // result = lea base( , cond*4) 9322 case 5: // result = lea base(cond, cond*4) 9323 case 8: // result = lea base( , cond*8) 9324 case 9: // result = lea base(cond, cond*8) 9325 isFastMultiplier = true; 9326 break; 9327 } 9328 } 9329 9330 if (isFastMultiplier) { 9331 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9332 if (NeedsCondInvert) // Invert the condition if needed. 9333 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9334 DAG.getConstant(1, Cond.getValueType())); 9335 9336 // Zero extend the condition if needed. 9337 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9338 Cond); 9339 // Scale the condition by the difference. 9340 if (Diff != 1) 9341 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9342 DAG.getConstant(Diff, Cond.getValueType())); 9343 9344 // Add the base if non-zero. 9345 if (FalseC->getAPIntValue() != 0) 9346 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9347 SDValue(FalseC, 0)); 9348 return Cond; 9349 } 9350 } 9351 } 9352 } 9353 9354 return SDValue(); 9355} 9356 9357/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9358static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9359 TargetLowering::DAGCombinerInfo &DCI) { 9360 DebugLoc DL = N->getDebugLoc(); 9361 9362 // If the flag operand isn't dead, don't touch this CMOV. 9363 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9364 return SDValue(); 9365 9366 // If this is a select between two integer constants, try to do some 9367 // optimizations. Note that the operands are ordered the opposite of SELECT 9368 // operands. 9369 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9370 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9371 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9372 // larger than FalseC (the false value). 9373 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9374 9375 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9376 CC = X86::GetOppositeBranchCondition(CC); 9377 std::swap(TrueC, FalseC); 9378 } 9379 9380 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9381 // This is efficient for any integer data type (including i8/i16) and 9382 // shift amount. 9383 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9384 SDValue Cond = N->getOperand(3); 9385 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9386 DAG.getConstant(CC, MVT::i8), Cond); 9387 9388 // Zero extend the condition if needed. 9389 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9390 9391 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9392 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9393 DAG.getConstant(ShAmt, MVT::i8)); 9394 if (N->getNumValues() == 2) // Dead flag value? 9395 return DCI.CombineTo(N, Cond, SDValue()); 9396 return Cond; 9397 } 9398 9399 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9400 // for any integer data type, including i8/i16. 9401 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9402 SDValue Cond = N->getOperand(3); 9403 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9404 DAG.getConstant(CC, MVT::i8), Cond); 9405 9406 // Zero extend the condition if needed. 9407 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9408 FalseC->getValueType(0), Cond); 9409 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9410 SDValue(FalseC, 0)); 9411 9412 if (N->getNumValues() == 2) // Dead flag value? 9413 return DCI.CombineTo(N, Cond, SDValue()); 9414 return Cond; 9415 } 9416 9417 // Optimize cases that will turn into an LEA instruction. This requires 9418 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9419 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9420 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9421 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9422 9423 bool isFastMultiplier = false; 9424 if (Diff < 10) { 9425 switch ((unsigned char)Diff) { 9426 default: break; 9427 case 1: // result = add base, cond 9428 case 2: // result = lea base( , cond*2) 9429 case 3: // result = lea base(cond, cond*2) 9430 case 4: // result = lea base( , cond*4) 9431 case 5: // result = lea base(cond, cond*4) 9432 case 8: // result = lea base( , cond*8) 9433 case 9: // result = lea base(cond, cond*8) 9434 isFastMultiplier = true; 9435 break; 9436 } 9437 } 9438 9439 if (isFastMultiplier) { 9440 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9441 SDValue Cond = N->getOperand(3); 9442 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9443 DAG.getConstant(CC, MVT::i8), Cond); 9444 // Zero extend the condition if needed. 9445 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9446 Cond); 9447 // Scale the condition by the difference. 9448 if (Diff != 1) 9449 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9450 DAG.getConstant(Diff, Cond.getValueType())); 9451 9452 // Add the base if non-zero. 9453 if (FalseC->getAPIntValue() != 0) 9454 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9455 SDValue(FalseC, 0)); 9456 if (N->getNumValues() == 2) // Dead flag value? 9457 return DCI.CombineTo(N, Cond, SDValue()); 9458 return Cond; 9459 } 9460 } 9461 } 9462 } 9463 return SDValue(); 9464} 9465 9466 9467/// PerformMulCombine - Optimize a single multiply with constant into two 9468/// in order to implement it with two cheaper instructions, e.g. 9469/// LEA + SHL, LEA + LEA. 9470static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9471 TargetLowering::DAGCombinerInfo &DCI) { 9472 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9473 return SDValue(); 9474 9475 EVT VT = N->getValueType(0); 9476 if (VT != MVT::i64) 9477 return SDValue(); 9478 9479 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9480 if (!C) 9481 return SDValue(); 9482 uint64_t MulAmt = C->getZExtValue(); 9483 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9484 return SDValue(); 9485 9486 uint64_t MulAmt1 = 0; 9487 uint64_t MulAmt2 = 0; 9488 if ((MulAmt % 9) == 0) { 9489 MulAmt1 = 9; 9490 MulAmt2 = MulAmt / 9; 9491 } else if ((MulAmt % 5) == 0) { 9492 MulAmt1 = 5; 9493 MulAmt2 = MulAmt / 5; 9494 } else if ((MulAmt % 3) == 0) { 9495 MulAmt1 = 3; 9496 MulAmt2 = MulAmt / 3; 9497 } 9498 if (MulAmt2 && 9499 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9500 DebugLoc DL = N->getDebugLoc(); 9501 9502 if (isPowerOf2_64(MulAmt2) && 9503 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9504 // If second multiplifer is pow2, issue it first. We want the multiply by 9505 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9506 // is an add. 9507 std::swap(MulAmt1, MulAmt2); 9508 9509 SDValue NewMul; 9510 if (isPowerOf2_64(MulAmt1)) 9511 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9512 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9513 else 9514 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9515 DAG.getConstant(MulAmt1, VT)); 9516 9517 if (isPowerOf2_64(MulAmt2)) 9518 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9519 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9520 else 9521 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9522 DAG.getConstant(MulAmt2, VT)); 9523 9524 // Do not add new nodes to DAG combiner worklist. 9525 DCI.CombineTo(N, NewMul, false); 9526 } 9527 return SDValue(); 9528} 9529 9530static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9531 SDValue N0 = N->getOperand(0); 9532 SDValue N1 = N->getOperand(1); 9533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9534 EVT VT = N0.getValueType(); 9535 9536 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9537 // since the result of setcc_c is all zero's or all ones. 9538 if (N1C && N0.getOpcode() == ISD::AND && 9539 N0.getOperand(1).getOpcode() == ISD::Constant) { 9540 SDValue N00 = N0.getOperand(0); 9541 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9542 ((N00.getOpcode() == ISD::ANY_EXTEND || 9543 N00.getOpcode() == ISD::ZERO_EXTEND) && 9544 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9545 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9546 APInt ShAmt = N1C->getAPIntValue(); 9547 Mask = Mask.shl(ShAmt); 9548 if (Mask != 0) 9549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9550 N00, DAG.getConstant(Mask, VT)); 9551 } 9552 } 9553 9554 return SDValue(); 9555} 9556 9557/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9558/// when possible. 9559static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9560 const X86Subtarget *Subtarget) { 9561 EVT VT = N->getValueType(0); 9562 if (!VT.isVector() && VT.isInteger() && 9563 N->getOpcode() == ISD::SHL) 9564 return PerformSHLCombine(N, DAG); 9565 9566 // On X86 with SSE2 support, we can transform this to a vector shift if 9567 // all elements are shifted by the same amount. We can't do this in legalize 9568 // because the a constant vector is typically transformed to a constant pool 9569 // so we have no knowledge of the shift amount. 9570 if (!Subtarget->hasSSE2()) 9571 return SDValue(); 9572 9573 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9574 return SDValue(); 9575 9576 SDValue ShAmtOp = N->getOperand(1); 9577 EVT EltVT = VT.getVectorElementType(); 9578 DebugLoc DL = N->getDebugLoc(); 9579 SDValue BaseShAmt = SDValue(); 9580 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9581 unsigned NumElts = VT.getVectorNumElements(); 9582 unsigned i = 0; 9583 for (; i != NumElts; ++i) { 9584 SDValue Arg = ShAmtOp.getOperand(i); 9585 if (Arg.getOpcode() == ISD::UNDEF) continue; 9586 BaseShAmt = Arg; 9587 break; 9588 } 9589 for (; i != NumElts; ++i) { 9590 SDValue Arg = ShAmtOp.getOperand(i); 9591 if (Arg.getOpcode() == ISD::UNDEF) continue; 9592 if (Arg != BaseShAmt) { 9593 return SDValue(); 9594 } 9595 } 9596 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9597 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9598 SDValue InVec = ShAmtOp.getOperand(0); 9599 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9600 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9601 unsigned i = 0; 9602 for (; i != NumElts; ++i) { 9603 SDValue Arg = InVec.getOperand(i); 9604 if (Arg.getOpcode() == ISD::UNDEF) continue; 9605 BaseShAmt = Arg; 9606 break; 9607 } 9608 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9610 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9611 if (C->getZExtValue() == SplatIdx) 9612 BaseShAmt = InVec.getOperand(1); 9613 } 9614 } 9615 if (BaseShAmt.getNode() == 0) 9616 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9617 DAG.getIntPtrConstant(0)); 9618 } else 9619 return SDValue(); 9620 9621 // The shift amount is an i32. 9622 if (EltVT.bitsGT(MVT::i32)) 9623 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9624 else if (EltVT.bitsLT(MVT::i32)) 9625 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9626 9627 // The shift amount is identical so we can do a vector shift. 9628 SDValue ValOp = N->getOperand(0); 9629 switch (N->getOpcode()) { 9630 default: 9631 llvm_unreachable("Unknown shift opcode!"); 9632 break; 9633 case ISD::SHL: 9634 if (VT == MVT::v2i64) 9635 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9636 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9637 ValOp, BaseShAmt); 9638 if (VT == MVT::v4i32) 9639 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9640 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9641 ValOp, BaseShAmt); 9642 if (VT == MVT::v8i16) 9643 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9644 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9645 ValOp, BaseShAmt); 9646 break; 9647 case ISD::SRA: 9648 if (VT == MVT::v4i32) 9649 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9650 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9651 ValOp, BaseShAmt); 9652 if (VT == MVT::v8i16) 9653 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9654 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9655 ValOp, BaseShAmt); 9656 break; 9657 case ISD::SRL: 9658 if (VT == MVT::v2i64) 9659 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9660 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9661 ValOp, BaseShAmt); 9662 if (VT == MVT::v4i32) 9663 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9664 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9665 ValOp, BaseShAmt); 9666 if (VT == MVT::v8i16) 9667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9668 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9669 ValOp, BaseShAmt); 9670 break; 9671 } 9672 return SDValue(); 9673} 9674 9675static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9676 TargetLowering::DAGCombinerInfo &DCI, 9677 const X86Subtarget *Subtarget) { 9678 if (DCI.isBeforeLegalizeOps()) 9679 return SDValue(); 9680 9681 EVT VT = N->getValueType(0); 9682 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 9683 return SDValue(); 9684 9685 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9686 SDValue N0 = N->getOperand(0); 9687 SDValue N1 = N->getOperand(1); 9688 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9689 std::swap(N0, N1); 9690 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9691 return SDValue(); 9692 if (!N0.hasOneUse() || !N1.hasOneUse()) 9693 return SDValue(); 9694 9695 SDValue ShAmt0 = N0.getOperand(1); 9696 if (ShAmt0.getValueType() != MVT::i8) 9697 return SDValue(); 9698 SDValue ShAmt1 = N1.getOperand(1); 9699 if (ShAmt1.getValueType() != MVT::i8) 9700 return SDValue(); 9701 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9702 ShAmt0 = ShAmt0.getOperand(0); 9703 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9704 ShAmt1 = ShAmt1.getOperand(0); 9705 9706 DebugLoc DL = N->getDebugLoc(); 9707 unsigned Opc = X86ISD::SHLD; 9708 SDValue Op0 = N0.getOperand(0); 9709 SDValue Op1 = N1.getOperand(0); 9710 if (ShAmt0.getOpcode() == ISD::SUB) { 9711 Opc = X86ISD::SHRD; 9712 std::swap(Op0, Op1); 9713 std::swap(ShAmt0, ShAmt1); 9714 } 9715 9716 unsigned Bits = VT.getSizeInBits(); 9717 if (ShAmt1.getOpcode() == ISD::SUB) { 9718 SDValue Sum = ShAmt1.getOperand(0); 9719 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9720 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 9721 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 9722 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 9723 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 9724 return DAG.getNode(Opc, DL, VT, 9725 Op0, Op1, 9726 DAG.getNode(ISD::TRUNCATE, DL, 9727 MVT::i8, ShAmt0)); 9728 } 9729 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9730 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9731 if (ShAmt0C && 9732 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 9733 return DAG.getNode(Opc, DL, VT, 9734 N0.getOperand(0), N1.getOperand(0), 9735 DAG.getNode(ISD::TRUNCATE, DL, 9736 MVT::i8, ShAmt0)); 9737 } 9738 9739 return SDValue(); 9740} 9741 9742/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9743static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9744 const X86Subtarget *Subtarget) { 9745 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9746 // the FP state in cases where an emms may be missing. 9747 // A preferable solution to the general problem is to figure out the right 9748 // places to insert EMMS. This qualifies as a quick hack. 9749 9750 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9751 StoreSDNode *St = cast<StoreSDNode>(N); 9752 EVT VT = St->getValue().getValueType(); 9753 if (VT.getSizeInBits() != 64) 9754 return SDValue(); 9755 9756 const Function *F = DAG.getMachineFunction().getFunction(); 9757 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9758 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9759 && Subtarget->hasSSE2(); 9760 if ((VT.isVector() || 9761 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9762 isa<LoadSDNode>(St->getValue()) && 9763 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9764 St->getChain().hasOneUse() && !St->isVolatile()) { 9765 SDNode* LdVal = St->getValue().getNode(); 9766 LoadSDNode *Ld = 0; 9767 int TokenFactorIndex = -1; 9768 SmallVector<SDValue, 8> Ops; 9769 SDNode* ChainVal = St->getChain().getNode(); 9770 // Must be a store of a load. We currently handle two cases: the load 9771 // is a direct child, and it's under an intervening TokenFactor. It is 9772 // possible to dig deeper under nested TokenFactors. 9773 if (ChainVal == LdVal) 9774 Ld = cast<LoadSDNode>(St->getChain()); 9775 else if (St->getValue().hasOneUse() && 9776 ChainVal->getOpcode() == ISD::TokenFactor) { 9777 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9778 if (ChainVal->getOperand(i).getNode() == LdVal) { 9779 TokenFactorIndex = i; 9780 Ld = cast<LoadSDNode>(St->getValue()); 9781 } else 9782 Ops.push_back(ChainVal->getOperand(i)); 9783 } 9784 } 9785 9786 if (!Ld || !ISD::isNormalLoad(Ld)) 9787 return SDValue(); 9788 9789 // If this is not the MMX case, i.e. we are just turning i64 load/store 9790 // into f64 load/store, avoid the transformation if there are multiple 9791 // uses of the loaded value. 9792 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9793 return SDValue(); 9794 9795 DebugLoc LdDL = Ld->getDebugLoc(); 9796 DebugLoc StDL = N->getDebugLoc(); 9797 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9798 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9799 // pair instead. 9800 if (Subtarget->is64Bit() || F64IsLegal) { 9801 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9802 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9803 Ld->getBasePtr(), Ld->getSrcValue(), 9804 Ld->getSrcValueOffset(), Ld->isVolatile(), 9805 Ld->isNonTemporal(), Ld->getAlignment()); 9806 SDValue NewChain = NewLd.getValue(1); 9807 if (TokenFactorIndex != -1) { 9808 Ops.push_back(NewChain); 9809 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9810 Ops.size()); 9811 } 9812 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9813 St->getSrcValue(), St->getSrcValueOffset(), 9814 St->isVolatile(), St->isNonTemporal(), 9815 St->getAlignment()); 9816 } 9817 9818 // Otherwise, lower to two pairs of 32-bit loads / stores. 9819 SDValue LoAddr = Ld->getBasePtr(); 9820 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9821 DAG.getConstant(4, MVT::i32)); 9822 9823 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9824 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9825 Ld->isVolatile(), Ld->isNonTemporal(), 9826 Ld->getAlignment()); 9827 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9828 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9829 Ld->isVolatile(), Ld->isNonTemporal(), 9830 MinAlign(Ld->getAlignment(), 4)); 9831 9832 SDValue NewChain = LoLd.getValue(1); 9833 if (TokenFactorIndex != -1) { 9834 Ops.push_back(LoLd); 9835 Ops.push_back(HiLd); 9836 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9837 Ops.size()); 9838 } 9839 9840 LoAddr = St->getBasePtr(); 9841 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9842 DAG.getConstant(4, MVT::i32)); 9843 9844 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9845 St->getSrcValue(), St->getSrcValueOffset(), 9846 St->isVolatile(), St->isNonTemporal(), 9847 St->getAlignment()); 9848 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9849 St->getSrcValue(), 9850 St->getSrcValueOffset() + 4, 9851 St->isVolatile(), 9852 St->isNonTemporal(), 9853 MinAlign(St->getAlignment(), 4)); 9854 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9855 } 9856 return SDValue(); 9857} 9858 9859/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9860/// X86ISD::FXOR nodes. 9861static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9862 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9863 // F[X]OR(0.0, x) -> x 9864 // F[X]OR(x, 0.0) -> x 9865 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9866 if (C->getValueAPF().isPosZero()) 9867 return N->getOperand(1); 9868 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9869 if (C->getValueAPF().isPosZero()) 9870 return N->getOperand(0); 9871 return SDValue(); 9872} 9873 9874/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9875static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9876 // FAND(0.0, x) -> 0.0 9877 // FAND(x, 0.0) -> 0.0 9878 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9879 if (C->getValueAPF().isPosZero()) 9880 return N->getOperand(0); 9881 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9882 if (C->getValueAPF().isPosZero()) 9883 return N->getOperand(1); 9884 return SDValue(); 9885} 9886 9887static SDValue PerformBTCombine(SDNode *N, 9888 SelectionDAG &DAG, 9889 TargetLowering::DAGCombinerInfo &DCI) { 9890 // BT ignores high bits in the bit index operand. 9891 SDValue Op1 = N->getOperand(1); 9892 if (Op1.hasOneUse()) { 9893 unsigned BitWidth = Op1.getValueSizeInBits(); 9894 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9895 APInt KnownZero, KnownOne; 9896 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 9897 !DCI.isBeforeLegalizeOps()); 9898 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9899 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9900 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9901 DCI.CommitTargetLoweringOpt(TLO); 9902 } 9903 return SDValue(); 9904} 9905 9906static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9907 SDValue Op = N->getOperand(0); 9908 if (Op.getOpcode() == ISD::BIT_CONVERT) 9909 Op = Op.getOperand(0); 9910 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9911 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9912 VT.getVectorElementType().getSizeInBits() == 9913 OpVT.getVectorElementType().getSizeInBits()) { 9914 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9915 } 9916 return SDValue(); 9917} 9918 9919static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9920 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9921 // (and (i32 x86isd::setcc_carry), 1) 9922 // This eliminates the zext. This transformation is necessary because 9923 // ISD::SETCC is always legalized to i8. 9924 DebugLoc dl = N->getDebugLoc(); 9925 SDValue N0 = N->getOperand(0); 9926 EVT VT = N->getValueType(0); 9927 if (N0.getOpcode() == ISD::AND && 9928 N0.hasOneUse() && 9929 N0.getOperand(0).hasOneUse()) { 9930 SDValue N00 = N0.getOperand(0); 9931 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9932 return SDValue(); 9933 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9934 if (!C || C->getZExtValue() != 1) 9935 return SDValue(); 9936 return DAG.getNode(ISD::AND, dl, VT, 9937 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9938 N00.getOperand(0), N00.getOperand(1)), 9939 DAG.getConstant(1, VT)); 9940 } 9941 9942 return SDValue(); 9943} 9944 9945SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9946 DAGCombinerInfo &DCI) const { 9947 SelectionDAG &DAG = DCI.DAG; 9948 switch (N->getOpcode()) { 9949 default: break; 9950 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9951 case ISD::EXTRACT_VECTOR_ELT: 9952 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 9953 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9954 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9955 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9956 case ISD::SHL: 9957 case ISD::SRA: 9958 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9959 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 9960 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9961 case X86ISD::FXOR: 9962 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9963 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9964 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9965 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9966 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9967 } 9968 9969 return SDValue(); 9970} 9971 9972/// isTypeDesirableForOp - Return true if the target has native support for 9973/// the specified value type and it is 'desirable' to use the type for the 9974/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 9975/// instruction encodings are longer and some i16 instructions are slow. 9976bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 9977 if (!isTypeLegal(VT)) 9978 return false; 9979 if (VT != MVT::i16) 9980 return true; 9981 9982 switch (Opc) { 9983 default: 9984 return true; 9985 case ISD::LOAD: 9986 case ISD::SIGN_EXTEND: 9987 case ISD::ZERO_EXTEND: 9988 case ISD::ANY_EXTEND: 9989 case ISD::SHL: 9990 case ISD::SRL: 9991 case ISD::SUB: 9992 case ISD::ADD: 9993 case ISD::MUL: 9994 case ISD::AND: 9995 case ISD::OR: 9996 case ISD::XOR: 9997 return false; 9998 } 9999} 10000 10001static bool MayFoldLoad(SDValue Op) { 10002 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 10003} 10004 10005static bool MayFoldIntoStore(SDValue Op) { 10006 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 10007} 10008 10009/// IsDesirableToPromoteOp - This method query the target whether it is 10010/// beneficial for dag combiner to promote the specified node. If true, it 10011/// should return the desired promotion type by reference. 10012bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 10013 EVT VT = Op.getValueType(); 10014 if (VT != MVT::i16) 10015 return false; 10016 10017 bool Promote = false; 10018 bool Commute = false; 10019 switch (Op.getOpcode()) { 10020 default: break; 10021 case ISD::LOAD: { 10022 LoadSDNode *LD = cast<LoadSDNode>(Op); 10023 // If the non-extending load has a single use and it's not live out, then it 10024 // might be folded. 10025 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 10026 Op.hasOneUse()*/) { 10027 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 10028 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 10029 // The only case where we'd want to promote LOAD (rather then it being 10030 // promoted as an operand is when it's only use is liveout. 10031 if (UI->getOpcode() != ISD::CopyToReg) 10032 return false; 10033 } 10034 } 10035 Promote = true; 10036 break; 10037 } 10038 case ISD::SIGN_EXTEND: 10039 case ISD::ZERO_EXTEND: 10040 case ISD::ANY_EXTEND: 10041 Promote = true; 10042 break; 10043 case ISD::SHL: 10044 case ISD::SRL: { 10045 SDValue N0 = Op.getOperand(0); 10046 // Look out for (store (shl (load), x)). 10047 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 10048 return false; 10049 Promote = true; 10050 break; 10051 } 10052 case ISD::ADD: 10053 case ISD::MUL: 10054 case ISD::AND: 10055 case ISD::OR: 10056 case ISD::XOR: 10057 Commute = true; 10058 // fallthrough 10059 case ISD::SUB: { 10060 SDValue N0 = Op.getOperand(0); 10061 SDValue N1 = Op.getOperand(1); 10062 if (!Commute && MayFoldLoad(N1)) 10063 return false; 10064 // Avoid disabling potential load folding opportunities. 10065 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 10066 return false; 10067 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 10068 return false; 10069 Promote = true; 10070 } 10071 } 10072 10073 PVT = MVT::i32; 10074 return Promote; 10075} 10076 10077//===----------------------------------------------------------------------===// 10078// X86 Inline Assembly Support 10079//===----------------------------------------------------------------------===// 10080 10081static bool LowerToBSwap(CallInst *CI) { 10082 // FIXME: this should verify that we are targetting a 486 or better. If not, 10083 // we will turn this bswap into something that will be lowered to logical ops 10084 // instead of emitting the bswap asm. For now, we don't support 486 or lower 10085 // so don't worry about this. 10086 10087 // Verify this is a simple bswap. 10088 if (CI->getNumArgOperands() != 1 || 10089 CI->getType() != CI->getArgOperand(0)->getType() || 10090 !CI->getType()->isIntegerTy()) 10091 return false; 10092 10093 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 10094 if (!Ty || Ty->getBitWidth() % 16 != 0) 10095 return false; 10096 10097 // Okay, we can do this xform, do so now. 10098 const Type *Tys[] = { Ty }; 10099 Module *M = CI->getParent()->getParent()->getParent(); 10100 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 10101 10102 Value *Op = CI->getArgOperand(0); 10103 Op = CallInst::Create(Int, Op, CI->getName(), CI); 10104 10105 CI->replaceAllUsesWith(Op); 10106 CI->eraseFromParent(); 10107 return true; 10108} 10109 10110bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 10111 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 10112 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 10113 10114 std::string AsmStr = IA->getAsmString(); 10115 10116 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 10117 SmallVector<StringRef, 4> AsmPieces; 10118 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 10119 10120 switch (AsmPieces.size()) { 10121 default: return false; 10122 case 1: 10123 AsmStr = AsmPieces[0]; 10124 AsmPieces.clear(); 10125 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 10126 10127 // bswap $0 10128 if (AsmPieces.size() == 2 && 10129 (AsmPieces[0] == "bswap" || 10130 AsmPieces[0] == "bswapq" || 10131 AsmPieces[0] == "bswapl") && 10132 (AsmPieces[1] == "$0" || 10133 AsmPieces[1] == "${0:q}")) { 10134 // No need to check constraints, nothing other than the equivalent of 10135 // "=r,0" would be valid here. 10136 return LowerToBSwap(CI); 10137 } 10138 // rorw $$8, ${0:w} --> llvm.bswap.i16 10139 if (CI->getType()->isIntegerTy(16) && 10140 AsmPieces.size() == 3 && 10141 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 10142 AsmPieces[1] == "$$8," && 10143 AsmPieces[2] == "${0:w}" && 10144 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 10145 AsmPieces.clear(); 10146 const std::string &Constraints = IA->getConstraintString(); 10147 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 10148 std::sort(AsmPieces.begin(), AsmPieces.end()); 10149 if (AsmPieces.size() == 4 && 10150 AsmPieces[0] == "~{cc}" && 10151 AsmPieces[1] == "~{dirflag}" && 10152 AsmPieces[2] == "~{flags}" && 10153 AsmPieces[3] == "~{fpsr}") { 10154 return LowerToBSwap(CI); 10155 } 10156 } 10157 break; 10158 case 3: 10159 if (CI->getType()->isIntegerTy(64) && 10160 Constraints.size() >= 2 && 10161 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 10162 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 10163 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 10164 SmallVector<StringRef, 4> Words; 10165 SplitString(AsmPieces[0], Words, " \t"); 10166 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 10167 Words.clear(); 10168 SplitString(AsmPieces[1], Words, " \t"); 10169 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 10170 Words.clear(); 10171 SplitString(AsmPieces[2], Words, " \t,"); 10172 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 10173 Words[2] == "%edx") { 10174 return LowerToBSwap(CI); 10175 } 10176 } 10177 } 10178 } 10179 break; 10180 } 10181 return false; 10182} 10183 10184 10185 10186/// getConstraintType - Given a constraint letter, return the type of 10187/// constraint it is for this target. 10188X86TargetLowering::ConstraintType 10189X86TargetLowering::getConstraintType(const std::string &Constraint) const { 10190 if (Constraint.size() == 1) { 10191 switch (Constraint[0]) { 10192 case 'A': 10193 return C_Register; 10194 case 'f': 10195 case 'r': 10196 case 'R': 10197 case 'l': 10198 case 'q': 10199 case 'Q': 10200 case 'x': 10201 case 'y': 10202 case 'Y': 10203 return C_RegisterClass; 10204 case 'e': 10205 case 'Z': 10206 return C_Other; 10207 default: 10208 break; 10209 } 10210 } 10211 return TargetLowering::getConstraintType(Constraint); 10212} 10213 10214/// LowerXConstraint - try to replace an X constraint, which matches anything, 10215/// with another that has more specific requirements based on the type of the 10216/// corresponding operand. 10217const char *X86TargetLowering:: 10218LowerXConstraint(EVT ConstraintVT) const { 10219 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10220 // 'f' like normal targets. 10221 if (ConstraintVT.isFloatingPoint()) { 10222 if (Subtarget->hasSSE2()) 10223 return "Y"; 10224 if (Subtarget->hasSSE1()) 10225 return "x"; 10226 } 10227 10228 return TargetLowering::LowerXConstraint(ConstraintVT); 10229} 10230 10231/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10232/// vector. If it is invalid, don't add anything to Ops. 10233void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10234 char Constraint, 10235 std::vector<SDValue>&Ops, 10236 SelectionDAG &DAG) const { 10237 SDValue Result(0, 0); 10238 10239 switch (Constraint) { 10240 default: break; 10241 case 'I': 10242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10243 if (C->getZExtValue() <= 31) { 10244 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10245 break; 10246 } 10247 } 10248 return; 10249 case 'J': 10250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10251 if (C->getZExtValue() <= 63) { 10252 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10253 break; 10254 } 10255 } 10256 return; 10257 case 'K': 10258 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10259 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10260 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10261 break; 10262 } 10263 } 10264 return; 10265 case 'N': 10266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10267 if (C->getZExtValue() <= 255) { 10268 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10269 break; 10270 } 10271 } 10272 return; 10273 case 'e': { 10274 // 32-bit signed value 10275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10276 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10277 C->getSExtValue())) { 10278 // Widen to 64 bits here to get it sign extended. 10279 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10280 break; 10281 } 10282 // FIXME gcc accepts some relocatable values here too, but only in certain 10283 // memory models; it's complicated. 10284 } 10285 return; 10286 } 10287 case 'Z': { 10288 // 32-bit unsigned value 10289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10290 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10291 C->getZExtValue())) { 10292 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10293 break; 10294 } 10295 } 10296 // FIXME gcc accepts some relocatable values here too, but only in certain 10297 // memory models; it's complicated. 10298 return; 10299 } 10300 case 'i': { 10301 // Literal immediates are always ok. 10302 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10303 // Widen to 64 bits here to get it sign extended. 10304 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10305 break; 10306 } 10307 10308 // In any sort of PIC mode addresses need to be computed at runtime by 10309 // adding in a register or some sort of table lookup. These can't 10310 // be used as immediates. 10311 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 10312 return; 10313 10314 // If we are in non-pic codegen mode, we allow the address of a global (with 10315 // an optional displacement) to be used with 'i'. 10316 GlobalAddressSDNode *GA = 0; 10317 int64_t Offset = 0; 10318 10319 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10320 while (1) { 10321 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10322 Offset += GA->getOffset(); 10323 break; 10324 } else if (Op.getOpcode() == ISD::ADD) { 10325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10326 Offset += C->getZExtValue(); 10327 Op = Op.getOperand(0); 10328 continue; 10329 } 10330 } else if (Op.getOpcode() == ISD::SUB) { 10331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10332 Offset += -C->getZExtValue(); 10333 Op = Op.getOperand(0); 10334 continue; 10335 } 10336 } 10337 10338 // Otherwise, this isn't something we can handle, reject it. 10339 return; 10340 } 10341 10342 const GlobalValue *GV = GA->getGlobal(); 10343 // If we require an extra load to get this address, as in PIC mode, we 10344 // can't accept it. 10345 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10346 getTargetMachine()))) 10347 return; 10348 10349 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 10350 GA->getValueType(0), Offset); 10351 break; 10352 } 10353 } 10354 10355 if (Result.getNode()) { 10356 Ops.push_back(Result); 10357 return; 10358 } 10359 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 10360} 10361 10362std::vector<unsigned> X86TargetLowering:: 10363getRegClassForInlineAsmConstraint(const std::string &Constraint, 10364 EVT VT) const { 10365 if (Constraint.size() == 1) { 10366 // FIXME: not handling fp-stack yet! 10367 switch (Constraint[0]) { // GCC X86 Constraint Letters 10368 default: break; // Unknown constraint letter 10369 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10370 if (Subtarget->is64Bit()) { 10371 if (VT == MVT::i32) 10372 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10373 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10374 X86::R10D,X86::R11D,X86::R12D, 10375 X86::R13D,X86::R14D,X86::R15D, 10376 X86::EBP, X86::ESP, 0); 10377 else if (VT == MVT::i16) 10378 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10379 X86::SI, X86::DI, X86::R8W,X86::R9W, 10380 X86::R10W,X86::R11W,X86::R12W, 10381 X86::R13W,X86::R14W,X86::R15W, 10382 X86::BP, X86::SP, 0); 10383 else if (VT == MVT::i8) 10384 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10385 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10386 X86::R10B,X86::R11B,X86::R12B, 10387 X86::R13B,X86::R14B,X86::R15B, 10388 X86::BPL, X86::SPL, 0); 10389 10390 else if (VT == MVT::i64) 10391 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10392 X86::RSI, X86::RDI, X86::R8, X86::R9, 10393 X86::R10, X86::R11, X86::R12, 10394 X86::R13, X86::R14, X86::R15, 10395 X86::RBP, X86::RSP, 0); 10396 10397 break; 10398 } 10399 // 32-bit fallthrough 10400 case 'Q': // Q_REGS 10401 if (VT == MVT::i32) 10402 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10403 else if (VT == MVT::i16) 10404 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10405 else if (VT == MVT::i8) 10406 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10407 else if (VT == MVT::i64) 10408 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10409 break; 10410 } 10411 } 10412 10413 return std::vector<unsigned>(); 10414} 10415 10416std::pair<unsigned, const TargetRegisterClass*> 10417X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10418 EVT VT) const { 10419 // First, see if this is a constraint that directly corresponds to an LLVM 10420 // register class. 10421 if (Constraint.size() == 1) { 10422 // GCC Constraint Letters 10423 switch (Constraint[0]) { 10424 default: break; 10425 case 'r': // GENERAL_REGS 10426 case 'l': // INDEX_REGS 10427 if (VT == MVT::i8) 10428 return std::make_pair(0U, X86::GR8RegisterClass); 10429 if (VT == MVT::i16) 10430 return std::make_pair(0U, X86::GR16RegisterClass); 10431 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10432 return std::make_pair(0U, X86::GR32RegisterClass); 10433 return std::make_pair(0U, X86::GR64RegisterClass); 10434 case 'R': // LEGACY_REGS 10435 if (VT == MVT::i8) 10436 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10437 if (VT == MVT::i16) 10438 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10439 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10440 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10441 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10442 case 'f': // FP Stack registers. 10443 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10444 // value to the correct fpstack register class. 10445 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10446 return std::make_pair(0U, X86::RFP32RegisterClass); 10447 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10448 return std::make_pair(0U, X86::RFP64RegisterClass); 10449 return std::make_pair(0U, X86::RFP80RegisterClass); 10450 case 'y': // MMX_REGS if MMX allowed. 10451 if (!Subtarget->hasMMX()) break; 10452 return std::make_pair(0U, X86::VR64RegisterClass); 10453 case 'Y': // SSE_REGS if SSE2 allowed 10454 if (!Subtarget->hasSSE2()) break; 10455 // FALL THROUGH. 10456 case 'x': // SSE_REGS if SSE1 allowed 10457 if (!Subtarget->hasSSE1()) break; 10458 10459 switch (VT.getSimpleVT().SimpleTy) { 10460 default: break; 10461 // Scalar SSE types. 10462 case MVT::f32: 10463 case MVT::i32: 10464 return std::make_pair(0U, X86::FR32RegisterClass); 10465 case MVT::f64: 10466 case MVT::i64: 10467 return std::make_pair(0U, X86::FR64RegisterClass); 10468 // Vector types. 10469 case MVT::v16i8: 10470 case MVT::v8i16: 10471 case MVT::v4i32: 10472 case MVT::v2i64: 10473 case MVT::v4f32: 10474 case MVT::v2f64: 10475 return std::make_pair(0U, X86::VR128RegisterClass); 10476 } 10477 break; 10478 } 10479 } 10480 10481 // Use the default implementation in TargetLowering to convert the register 10482 // constraint into a member of a register class. 10483 std::pair<unsigned, const TargetRegisterClass*> Res; 10484 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10485 10486 // Not found as a standard register? 10487 if (Res.second == 0) { 10488 // Map st(0) -> st(7) -> ST0 10489 if (Constraint.size() == 7 && Constraint[0] == '{' && 10490 tolower(Constraint[1]) == 's' && 10491 tolower(Constraint[2]) == 't' && 10492 Constraint[3] == '(' && 10493 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10494 Constraint[5] == ')' && 10495 Constraint[6] == '}') { 10496 10497 Res.first = X86::ST0+Constraint[4]-'0'; 10498 Res.second = X86::RFP80RegisterClass; 10499 return Res; 10500 } 10501 10502 // GCC allows "st(0)" to be called just plain "st". 10503 if (StringRef("{st}").equals_lower(Constraint)) { 10504 Res.first = X86::ST0; 10505 Res.second = X86::RFP80RegisterClass; 10506 return Res; 10507 } 10508 10509 // flags -> EFLAGS 10510 if (StringRef("{flags}").equals_lower(Constraint)) { 10511 Res.first = X86::EFLAGS; 10512 Res.second = X86::CCRRegisterClass; 10513 return Res; 10514 } 10515 10516 // 'A' means EAX + EDX. 10517 if (Constraint == "A") { 10518 Res.first = X86::EAX; 10519 Res.second = X86::GR32_ADRegisterClass; 10520 return Res; 10521 } 10522 return Res; 10523 } 10524 10525 // Otherwise, check to see if this is a register class of the wrong value 10526 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10527 // turn into {ax},{dx}. 10528 if (Res.second->hasType(VT)) 10529 return Res; // Correct type already, nothing to do. 10530 10531 // All of the single-register GCC register classes map their values onto 10532 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10533 // really want an 8-bit or 32-bit register, map to the appropriate register 10534 // class and return the appropriate register. 10535 if (Res.second == X86::GR16RegisterClass) { 10536 if (VT == MVT::i8) { 10537 unsigned DestReg = 0; 10538 switch (Res.first) { 10539 default: break; 10540 case X86::AX: DestReg = X86::AL; break; 10541 case X86::DX: DestReg = X86::DL; break; 10542 case X86::CX: DestReg = X86::CL; break; 10543 case X86::BX: DestReg = X86::BL; break; 10544 } 10545 if (DestReg) { 10546 Res.first = DestReg; 10547 Res.second = X86::GR8RegisterClass; 10548 } 10549 } else if (VT == MVT::i32) { 10550 unsigned DestReg = 0; 10551 switch (Res.first) { 10552 default: break; 10553 case X86::AX: DestReg = X86::EAX; break; 10554 case X86::DX: DestReg = X86::EDX; break; 10555 case X86::CX: DestReg = X86::ECX; break; 10556 case X86::BX: DestReg = X86::EBX; break; 10557 case X86::SI: DestReg = X86::ESI; break; 10558 case X86::DI: DestReg = X86::EDI; break; 10559 case X86::BP: DestReg = X86::EBP; break; 10560 case X86::SP: DestReg = X86::ESP; break; 10561 } 10562 if (DestReg) { 10563 Res.first = DestReg; 10564 Res.second = X86::GR32RegisterClass; 10565 } 10566 } else if (VT == MVT::i64) { 10567 unsigned DestReg = 0; 10568 switch (Res.first) { 10569 default: break; 10570 case X86::AX: DestReg = X86::RAX; break; 10571 case X86::DX: DestReg = X86::RDX; break; 10572 case X86::CX: DestReg = X86::RCX; break; 10573 case X86::BX: DestReg = X86::RBX; break; 10574 case X86::SI: DestReg = X86::RSI; break; 10575 case X86::DI: DestReg = X86::RDI; break; 10576 case X86::BP: DestReg = X86::RBP; break; 10577 case X86::SP: DestReg = X86::RSP; break; 10578 } 10579 if (DestReg) { 10580 Res.first = DestReg; 10581 Res.second = X86::GR64RegisterClass; 10582 } 10583 } 10584 } else if (Res.second == X86::FR32RegisterClass || 10585 Res.second == X86::FR64RegisterClass || 10586 Res.second == X86::VR128RegisterClass) { 10587 // Handle references to XMM physical registers that got mapped into the 10588 // wrong class. This can happen with constraints like {xmm0} where the 10589 // target independent register mapper will just pick the first match it can 10590 // find, ignoring the required type. 10591 if (VT == MVT::f32) 10592 Res.second = X86::FR32RegisterClass; 10593 else if (VT == MVT::f64) 10594 Res.second = X86::FR64RegisterClass; 10595 else if (X86::VR128RegisterClass->hasType(VT)) 10596 Res.second = X86::VR128RegisterClass; 10597 } 10598 10599 return Res; 10600} 10601