X86ISelLowering.cpp revision ccfea35efb0817267a9b997933207863917a8a85
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86MCTargetExpr.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/PseudoSourceValue.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Support/raw_ostream.h" 51using namespace llvm; 52 53STATISTIC(NumTailCalls, "Number of tail calls"); 54 55static cl::opt<bool> 56DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 57 58// Disable16Bit - 16-bit operations typically have a larger encoding than 59// corresponding 32-bit instructions, and 16-bit code is slow on some 60// processors. This is an experimental flag to disable 16-bit operations 61// (which forces them to be Legalized to 32-bit operations). 62static cl::opt<bool> 63Disable16Bit("disable-16bit", cl::Hidden, 64 cl::desc("Disable use of 16-bit instructions")); 65 66// Forward declarations. 67static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 68 SDValue V2); 69 70static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 71 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 72 default: llvm_unreachable("unknown subtarget type"); 73 case X86Subtarget::isDarwin: 74 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 75 return new X8664_MachoTargetObjectFile(); 76 return new TargetLoweringObjectFileMachO(); 77 case X86Subtarget::isELF: 78 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 79 return new X8664_ELFTargetObjectFile(TM); 80 return new X8632_ELFTargetObjectFile(TM); 81 case X86Subtarget::isMingw: 82 case X86Subtarget::isCygwin: 83 case X86Subtarget::isWindows: 84 return new TargetLoweringObjectFileCOFF(); 85 } 86} 87 88X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 89 : TargetLowering(TM, createTLOF(TM)) { 90 Subtarget = &TM.getSubtarget<X86Subtarget>(); 91 X86ScalarSSEf64 = Subtarget->hasSSE2(); 92 X86ScalarSSEf32 = Subtarget->hasSSE1(); 93 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 94 95 RegInfo = TM.getRegisterInfo(); 96 TD = getTargetData(); 97 98 // Set up the TargetLowering object. 99 100 // X86 is weird, it always uses i8 for shift amounts and setcc results. 101 setShiftAmountType(MVT::i8); 102 setBooleanContents(ZeroOrOneBooleanContent); 103 setSchedulingPreference(SchedulingForRegPressure); 104 setStackPointerRegisterToSaveRestore(X86StackPtr); 105 106 if (Subtarget->isTargetDarwin()) { 107 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 108 setUseUnderscoreSetJmp(false); 109 setUseUnderscoreLongJmp(false); 110 } else if (Subtarget->isTargetMingw()) { 111 // MS runtime is weird: it exports _setjmp, but longjmp! 112 setUseUnderscoreSetJmp(true); 113 setUseUnderscoreLongJmp(false); 114 } else { 115 setUseUnderscoreSetJmp(true); 116 setUseUnderscoreLongJmp(true); 117 } 118 119 // Set up the register classes. 120 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 121 if (!Disable16Bit) 122 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 123 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 124 if (Subtarget->is64Bit()) 125 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 126 127 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 128 129 // We don't accept any truncstore of integer registers. 130 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 131 if (!Disable16Bit) 132 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 133 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 134 if (!Disable16Bit) 135 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 136 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 137 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 138 139 // SETOEQ and SETUNE require checking two conditions. 140 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 141 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 142 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 143 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 144 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 145 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 146 147 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 148 // operation. 149 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 150 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 151 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 152 153 if (Subtarget->is64Bit()) { 154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 155 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 156 } else if (!UseSoftFloat) { 157 if (X86ScalarSSEf64) { 158 // We have an impenetrably clever algorithm for ui64->double only. 159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 160 } 161 // We have an algorithm for SSE2, and we turn this into a 64-bit 162 // FILD for other targets. 163 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 164 } 165 166 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 167 // this operation. 168 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 169 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 170 171 if (!UseSoftFloat) { 172 // SSE has no i16 to fp conversion, only i32 173 if (X86ScalarSSEf32) { 174 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 175 // f32 and f64 cases are Legal, f80 case is not 176 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 177 } else { 178 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 179 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 180 } 181 } else { 182 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 183 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 184 } 185 186 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 187 // are Legal, f80 is custom lowered. 188 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 189 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 190 191 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 192 // this operation. 193 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 194 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 195 196 if (X86ScalarSSEf32) { 197 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 198 // f32 and f64 cases are Legal, f80 case is not 199 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 200 } else { 201 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 202 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 203 } 204 205 // Handle FP_TO_UINT by promoting the destination to a larger signed 206 // conversion. 207 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 208 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 209 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 210 211 if (Subtarget->is64Bit()) { 212 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 213 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 214 } else if (!UseSoftFloat) { 215 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 216 // Expand FP_TO_UINT into a select. 217 // FIXME: We would like to use a Custom expander here eventually to do 218 // the optimal thing for SSE vs. the default expansion in the legalizer. 219 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 220 else 221 // With SSE3 we can use fisttpll to convert to a signed i64; without 222 // SSE, we're stuck with a fistpll. 223 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 224 } 225 226 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 227 if (!X86ScalarSSEf64) { 228 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 229 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 230 } 231 232 // Scalar integer divide and remainder are lowered to use operations that 233 // produce two results, to match the available instructions. This exposes 234 // the two-result form to trivial CSE, which is able to combine x/y and x%y 235 // into a single instruction. 236 // 237 // Scalar integer multiply-high is also lowered to use two-result 238 // operations, to match the available instructions. However, plain multiply 239 // (low) operations are left as Legal, as there are single-result 240 // instructions for this in x86. Using the two-result multiply instructions 241 // when both high and low results are needed must be arranged by dagcombine. 242 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 243 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 244 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 245 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 246 setOperationAction(ISD::SREM , MVT::i8 , Expand); 247 setOperationAction(ISD::UREM , MVT::i8 , Expand); 248 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 249 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 250 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 251 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 252 setOperationAction(ISD::SREM , MVT::i16 , Expand); 253 setOperationAction(ISD::UREM , MVT::i16 , Expand); 254 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 255 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 256 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 257 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 258 setOperationAction(ISD::SREM , MVT::i32 , Expand); 259 setOperationAction(ISD::UREM , MVT::i32 , Expand); 260 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 261 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 262 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 263 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 264 setOperationAction(ISD::SREM , MVT::i64 , Expand); 265 setOperationAction(ISD::UREM , MVT::i64 , Expand); 266 267 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 268 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 269 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 270 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 271 if (Subtarget->is64Bit()) 272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 276 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 277 setOperationAction(ISD::FREM , MVT::f32 , Expand); 278 setOperationAction(ISD::FREM , MVT::f64 , Expand); 279 setOperationAction(ISD::FREM , MVT::f80 , Expand); 280 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 281 282 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 283 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 284 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 285 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 286 if (Disable16Bit) { 287 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 288 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 289 } else { 290 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 291 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 292 } 293 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 294 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 295 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 296 if (Subtarget->is64Bit()) { 297 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 298 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 299 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 300 } 301 302 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 303 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 304 305 // These should be promoted to a larger select which is supported. 306 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 307 // X86 wants to expand cmov itself. 308 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 309 if (Disable16Bit) 310 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 311 else 312 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 313 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 314 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 315 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 316 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 317 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 318 if (Disable16Bit) 319 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 320 else 321 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 322 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 323 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 324 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 325 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 326 if (Subtarget->is64Bit()) { 327 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 328 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 329 } 330 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 331 332 // Darwin ABI issue. 333 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 334 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 335 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 336 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 337 if (Subtarget->is64Bit()) 338 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 339 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 340 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 341 if (Subtarget->is64Bit()) { 342 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 343 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 344 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 345 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 346 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 347 } 348 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 349 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 350 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 351 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 352 if (Subtarget->is64Bit()) { 353 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 354 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 355 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 356 } 357 358 if (Subtarget->hasSSE1()) 359 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 360 361 if (!Subtarget->hasSSE2()) 362 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 363 364 // Expand certain atomics 365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 369 370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 374 375 if (!Subtarget->is64Bit()) { 376 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 377 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 378 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 381 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 382 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 383 } 384 385 // FIXME - use subtarget debug flags 386 if (!Subtarget->isTargetDarwin() && 387 !Subtarget->isTargetELF() && 388 !Subtarget->isTargetCygMing()) { 389 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 390 } 391 392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 393 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 395 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 396 if (Subtarget->is64Bit()) { 397 setExceptionPointerRegister(X86::RAX); 398 setExceptionSelectorRegister(X86::RDX); 399 } else { 400 setExceptionPointerRegister(X86::EAX); 401 setExceptionSelectorRegister(X86::EDX); 402 } 403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 404 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 405 406 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 407 408 setOperationAction(ISD::TRAP, MVT::Other, Legal); 409 410 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 411 setOperationAction(ISD::VASTART , MVT::Other, Custom); 412 setOperationAction(ISD::VAEND , MVT::Other, Expand); 413 if (Subtarget->is64Bit()) { 414 setOperationAction(ISD::VAARG , MVT::Other, Custom); 415 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 416 } else { 417 setOperationAction(ISD::VAARG , MVT::Other, Expand); 418 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 419 } 420 421 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 422 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 423 if (Subtarget->is64Bit()) 424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 425 if (Subtarget->isTargetCygMing()) 426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 427 else 428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 429 430 if (!UseSoftFloat && X86ScalarSSEf64) { 431 // f32 and f64 use SSE. 432 // Set up the FP register classes. 433 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 434 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 435 436 // Use ANDPD to simulate FABS. 437 setOperationAction(ISD::FABS , MVT::f64, Custom); 438 setOperationAction(ISD::FABS , MVT::f32, Custom); 439 440 // Use XORP to simulate FNEG. 441 setOperationAction(ISD::FNEG , MVT::f64, Custom); 442 setOperationAction(ISD::FNEG , MVT::f32, Custom); 443 444 // Use ANDPD and ORPD to simulate FCOPYSIGN. 445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 447 448 // We don't support sin/cos/fmod 449 setOperationAction(ISD::FSIN , MVT::f64, Expand); 450 setOperationAction(ISD::FCOS , MVT::f64, Expand); 451 setOperationAction(ISD::FSIN , MVT::f32, Expand); 452 setOperationAction(ISD::FCOS , MVT::f32, Expand); 453 454 // Expand FP immediates into loads from the stack, except for the special 455 // cases we handle. 456 addLegalFPImmediate(APFloat(+0.0)); // xorpd 457 addLegalFPImmediate(APFloat(+0.0f)); // xorps 458 } else if (!UseSoftFloat && X86ScalarSSEf32) { 459 // Use SSE for f32, x87 for f64. 460 // Set up the FP register classes. 461 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 463 464 // Use ANDPS to simulate FABS. 465 setOperationAction(ISD::FABS , MVT::f32, Custom); 466 467 // Use XORP to simulate FNEG. 468 setOperationAction(ISD::FNEG , MVT::f32, Custom); 469 470 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 471 472 // Use ANDPS and ORPS to simulate FCOPYSIGN. 473 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 474 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 475 476 // We don't support sin/cos/fmod 477 setOperationAction(ISD::FSIN , MVT::f32, Expand); 478 setOperationAction(ISD::FCOS , MVT::f32, Expand); 479 480 // Special cases we handle for FP constants. 481 addLegalFPImmediate(APFloat(+0.0f)); // xorps 482 addLegalFPImmediate(APFloat(+0.0)); // FLD0 483 addLegalFPImmediate(APFloat(+1.0)); // FLD1 484 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 485 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 486 487 if (!UnsafeFPMath) { 488 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 489 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 490 } 491 } else if (!UseSoftFloat) { 492 // f32 and f64 in x87. 493 // Set up the FP register classes. 494 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 495 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 496 497 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 498 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 499 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 500 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 501 502 if (!UnsafeFPMath) { 503 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 504 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 505 } 506 addLegalFPImmediate(APFloat(+0.0)); // FLD0 507 addLegalFPImmediate(APFloat(+1.0)); // FLD1 508 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 509 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 510 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 511 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 512 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 513 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 514 } 515 516 // Long double always uses X87. 517 if (!UseSoftFloat) { 518 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 519 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 520 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 521 { 522 bool ignored; 523 APFloat TmpFlt(+0.0); 524 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 525 &ignored); 526 addLegalFPImmediate(TmpFlt); // FLD0 527 TmpFlt.changeSign(); 528 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 529 APFloat TmpFlt2(+1.0); 530 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 531 &ignored); 532 addLegalFPImmediate(TmpFlt2); // FLD1 533 TmpFlt2.changeSign(); 534 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 535 } 536 537 if (!UnsafeFPMath) { 538 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 539 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 540 } 541 } 542 543 // Always use a library call for pow. 544 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 545 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 546 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 547 548 setOperationAction(ISD::FLOG, MVT::f80, Expand); 549 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 550 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 551 setOperationAction(ISD::FEXP, MVT::f80, Expand); 552 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 553 554 // First set operation action for all vector types to either promote 555 // (for widening) or expand (for scalarization). Then we will selectively 556 // turn on ones that can be effectively codegen'd. 557 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 558 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 559 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 574 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 575 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 607 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 608 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 610 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 611 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 612 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 613 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 614 setTruncStoreAction((MVT::SimpleValueType)VT, 615 (MVT::SimpleValueType)InnerVT, Expand); 616 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 617 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 618 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 619 } 620 621 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 622 // with -msoft-float, disable use of MMX as well. 623 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 624 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 625 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 626 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 627 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 628 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 629 630 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 631 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 632 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 633 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 634 635 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 636 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 637 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 638 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 639 640 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 641 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 642 643 setOperationAction(ISD::AND, MVT::v8i8, Promote); 644 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 645 setOperationAction(ISD::AND, MVT::v4i16, Promote); 646 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 647 setOperationAction(ISD::AND, MVT::v2i32, Promote); 648 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 649 setOperationAction(ISD::AND, MVT::v1i64, Legal); 650 651 setOperationAction(ISD::OR, MVT::v8i8, Promote); 652 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 653 setOperationAction(ISD::OR, MVT::v4i16, Promote); 654 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 655 setOperationAction(ISD::OR, MVT::v2i32, Promote); 656 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 657 setOperationAction(ISD::OR, MVT::v1i64, Legal); 658 659 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 660 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 661 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 662 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 663 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 664 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 665 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 666 667 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 668 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 669 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 670 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 671 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 672 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 673 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 674 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 675 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 676 677 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 678 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 680 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 681 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 682 683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 687 688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 692 693 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 694 695 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 696 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 697 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 698 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 699 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 700 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 701 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 702 } 703 704 if (!UseSoftFloat && Subtarget->hasSSE1()) { 705 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 706 707 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 708 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 709 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 710 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 711 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 712 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 713 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 714 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 715 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 717 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 718 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 719 } 720 721 if (!UseSoftFloat && Subtarget->hasSSE2()) { 722 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 723 724 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 725 // registers cannot be used even for integer operations. 726 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 727 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 728 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 729 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 730 731 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 732 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 733 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 734 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 735 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 736 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 737 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 738 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 739 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 740 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 741 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 742 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 743 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 744 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 745 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 746 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 747 748 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 749 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 750 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 751 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 752 753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 758 759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 764 765 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 766 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 767 EVT VT = (MVT::SimpleValueType)i; 768 // Do not attempt to custom lower non-power-of-2 vectors 769 if (!isPowerOf2_32(VT.getVectorNumElements())) 770 continue; 771 // Do not attempt to custom lower non-128-bit vectors 772 if (!VT.is128BitVector()) 773 continue; 774 setOperationAction(ISD::BUILD_VECTOR, 775 VT.getSimpleVT().SimpleTy, Custom); 776 setOperationAction(ISD::VECTOR_SHUFFLE, 777 VT.getSimpleVT().SimpleTy, Custom); 778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 779 VT.getSimpleVT().SimpleTy, Custom); 780 } 781 782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 783 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 785 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 786 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 788 789 if (Subtarget->is64Bit()) { 790 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 792 } 793 794 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 795 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 796 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 797 EVT VT = SVT; 798 799 // Do not attempt to promote non-128-bit vectors 800 if (!VT.is128BitVector()) { 801 continue; 802 } 803 setOperationAction(ISD::AND, SVT, Promote); 804 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 805 setOperationAction(ISD::OR, SVT, Promote); 806 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 807 setOperationAction(ISD::XOR, SVT, Promote); 808 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 809 setOperationAction(ISD::LOAD, SVT, Promote); 810 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 811 setOperationAction(ISD::SELECT, SVT, Promote); 812 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 813 } 814 815 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 816 817 // Custom lower v2i64 and v2f64 selects. 818 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 819 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 820 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 821 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 822 823 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 824 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 825 if (!DisableMMX && Subtarget->hasMMX()) { 826 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 827 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 828 } 829 } 830 831 if (Subtarget->hasSSE41()) { 832 // FIXME: Do we need to handle scalar-to-vector here? 833 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 834 835 // i8 and i16 vectors are custom , because the source register and source 836 // source memory operand types are not the same width. f32 vectors are 837 // custom since the immediate controlling the insert encodes additional 838 // information. 839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 843 844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 848 849 if (Subtarget->is64Bit()) { 850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 852 } 853 } 854 855 if (Subtarget->hasSSE42()) { 856 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 857 } 858 859 if (!UseSoftFloat && Subtarget->hasAVX()) { 860 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 861 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 862 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 863 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 864 865 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 866 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 867 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 868 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 869 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 870 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 871 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 872 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 873 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 874 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 875 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 876 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 877 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 878 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 879 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 880 881 // Operations to consider commented out -v16i16 v32i8 882 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 883 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 884 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 885 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 886 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 887 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 888 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 889 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 890 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 891 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 892 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 893 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 894 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 895 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 896 897 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 898 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 899 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 900 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 901 902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 903 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 904 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 907 908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 909 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 911 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 913 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 914 915#if 0 916 // Not sure we want to do this since there are no 256-bit integer 917 // operations in AVX 918 919 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 920 // This includes 256-bit vectors 921 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 922 EVT VT = (MVT::SimpleValueType)i; 923 924 // Do not attempt to custom lower non-power-of-2 vectors 925 if (!isPowerOf2_32(VT.getVectorNumElements())) 926 continue; 927 928 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 929 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 930 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 931 } 932 933 if (Subtarget->is64Bit()) { 934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 935 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 936 } 937#endif 938 939#if 0 940 // Not sure we want to do this since there are no 256-bit integer 941 // operations in AVX 942 943 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 944 // Including 256-bit vectors 945 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 946 EVT VT = (MVT::SimpleValueType)i; 947 948 if (!VT.is256BitVector()) { 949 continue; 950 } 951 setOperationAction(ISD::AND, VT, Promote); 952 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 953 setOperationAction(ISD::OR, VT, Promote); 954 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 955 setOperationAction(ISD::XOR, VT, Promote); 956 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 957 setOperationAction(ISD::LOAD, VT, Promote); 958 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 959 setOperationAction(ISD::SELECT, VT, Promote); 960 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 961 } 962 963 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 964#endif 965 } 966 967 // We want to custom lower some of our intrinsics. 968 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 969 970 // Add/Sub/Mul with overflow operations are custom lowered. 971 setOperationAction(ISD::SADDO, MVT::i32, Custom); 972 setOperationAction(ISD::SADDO, MVT::i64, Custom); 973 setOperationAction(ISD::UADDO, MVT::i32, Custom); 974 setOperationAction(ISD::UADDO, MVT::i64, Custom); 975 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 976 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 977 setOperationAction(ISD::USUBO, MVT::i32, Custom); 978 setOperationAction(ISD::USUBO, MVT::i64, Custom); 979 setOperationAction(ISD::SMULO, MVT::i32, Custom); 980 setOperationAction(ISD::SMULO, MVT::i64, Custom); 981 982 if (!Subtarget->is64Bit()) { 983 // These libcalls are not available in 32-bit. 984 setLibcallName(RTLIB::SHL_I128, 0); 985 setLibcallName(RTLIB::SRL_I128, 0); 986 setLibcallName(RTLIB::SRA_I128, 0); 987 } 988 989 // We have target-specific dag combine patterns for the following nodes: 990 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 991 setTargetDAGCombine(ISD::BUILD_VECTOR); 992 setTargetDAGCombine(ISD::SELECT); 993 setTargetDAGCombine(ISD::AND); 994 setTargetDAGCombine(ISD::SHL); 995 setTargetDAGCombine(ISD::SRA); 996 setTargetDAGCombine(ISD::SRL); 997 setTargetDAGCombine(ISD::OR); 998 setTargetDAGCombine(ISD::STORE); 999 setTargetDAGCombine(ISD::MEMBARRIER); 1000 setTargetDAGCombine(ISD::ZERO_EXTEND); 1001 if (Subtarget->is64Bit()) 1002 setTargetDAGCombine(ISD::MUL); 1003 1004 computeRegisterProperties(); 1005 1006 // FIXME: These should be based on subtarget info. Plus, the values should 1007 // be smaller when we are in optimizing for size mode. 1008 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1009 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 1010 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1011 setPrefLoopAlignment(16); 1012 benefitFromCodePlacementOpt = true; 1013} 1014 1015 1016MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1017 return MVT::i8; 1018} 1019 1020 1021/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1022/// the desired ByVal argument alignment. 1023static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1024 if (MaxAlign == 16) 1025 return; 1026 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1027 if (VTy->getBitWidth() == 128) 1028 MaxAlign = 16; 1029 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1030 unsigned EltAlign = 0; 1031 getMaxByValAlign(ATy->getElementType(), EltAlign); 1032 if (EltAlign > MaxAlign) 1033 MaxAlign = EltAlign; 1034 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1035 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1036 unsigned EltAlign = 0; 1037 getMaxByValAlign(STy->getElementType(i), EltAlign); 1038 if (EltAlign > MaxAlign) 1039 MaxAlign = EltAlign; 1040 if (MaxAlign == 16) 1041 break; 1042 } 1043 } 1044 return; 1045} 1046 1047/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1048/// function arguments in the caller parameter area. For X86, aggregates 1049/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1050/// are at 4-byte boundaries. 1051unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1052 if (Subtarget->is64Bit()) { 1053 // Max of 8 and alignment of type. 1054 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1055 if (TyAlign > 8) 1056 return TyAlign; 1057 return 8; 1058 } 1059 1060 unsigned Align = 4; 1061 if (Subtarget->hasSSE1()) 1062 getMaxByValAlign(Ty, Align); 1063 return Align; 1064} 1065 1066/// getOptimalMemOpType - Returns the target specific optimal type for load 1067/// and store operations as a result of memset, memcpy, and memmove 1068/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1069/// determining it. 1070EVT 1071X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1072 bool isSrcConst, bool isSrcStr, 1073 SelectionDAG &DAG) const { 1074 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1075 // linux. This is because the stack realignment code can't handle certain 1076 // cases like PR2962. This should be removed when PR2962 is fixed. 1077 const Function *F = DAG.getMachineFunction().getFunction(); 1078 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1079 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1080 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1081 return MVT::v4i32; 1082 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1083 return MVT::v4f32; 1084 } 1085 if (Subtarget->is64Bit() && Size >= 8) 1086 return MVT::i64; 1087 return MVT::i32; 1088} 1089 1090/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1091/// current function. The returned value is a member of the 1092/// MachineJumpTableInfo::JTEntryKind enum. 1093unsigned X86TargetLowering::getJumpTableEncoding() const { 1094 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1095 // symbol. 1096 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1097 Subtarget->isPICStyleGOT()) 1098 return MachineJumpTableInfo::EK_Custom32; 1099 1100 // Otherwise, use the normal jump table encoding heuristics. 1101 return TargetLowering::getJumpTableEncoding(); 1102} 1103 1104/// getPICBaseSymbol - Return the X86-32 PIC base. 1105MCSymbol * 1106X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1107 MCContext &Ctx) const { 1108 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1109 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1110 Twine(MF->getFunctionNumber())+"$pb"); 1111} 1112 1113 1114const MCExpr * 1115X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1116 const MachineBasicBlock *MBB, 1117 unsigned uid,MCContext &Ctx) const{ 1118 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1119 Subtarget->isPICStyleGOT()); 1120 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1121 // entries. 1122 return X86MCTargetExpr::Create(MBB->getSymbol(Ctx), 1123 X86MCTargetExpr::GOTOFF, Ctx); 1124} 1125 1126/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1127/// jumptable. 1128SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1129 SelectionDAG &DAG) const { 1130 if (!Subtarget->is64Bit()) 1131 // This doesn't have DebugLoc associated with it, but is not really the 1132 // same as a Register. 1133 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1134 getPointerTy()); 1135 return Table; 1136} 1137 1138/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1139/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1140/// MCExpr. 1141const MCExpr *X86TargetLowering:: 1142getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1143 MCContext &Ctx) const { 1144 // X86-64 uses RIP relative addressing based on the jump table label. 1145 if (Subtarget->isPICStyleRIPRel()) 1146 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1147 1148 // Otherwise, the reference is relative to the PIC base. 1149 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1150} 1151 1152/// getFunctionAlignment - Return the Log2 alignment of this function. 1153unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1154 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1155} 1156 1157//===----------------------------------------------------------------------===// 1158// Return Value Calling Convention Implementation 1159//===----------------------------------------------------------------------===// 1160 1161#include "X86GenCallingConv.inc" 1162 1163bool 1164X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1165 const SmallVectorImpl<EVT> &OutTys, 1166 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1167 SelectionDAG &DAG) { 1168 SmallVector<CCValAssign, 16> RVLocs; 1169 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1170 RVLocs, *DAG.getContext()); 1171 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86); 1172} 1173 1174SDValue 1175X86TargetLowering::LowerReturn(SDValue Chain, 1176 CallingConv::ID CallConv, bool isVarArg, 1177 const SmallVectorImpl<ISD::OutputArg> &Outs, 1178 DebugLoc dl, SelectionDAG &DAG) { 1179 1180 SmallVector<CCValAssign, 16> RVLocs; 1181 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1182 RVLocs, *DAG.getContext()); 1183 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1184 1185 // Add the regs to the liveout set for the function. 1186 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1187 for (unsigned i = 0; i != RVLocs.size(); ++i) 1188 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1189 MRI.addLiveOut(RVLocs[i].getLocReg()); 1190 1191 SDValue Flag; 1192 1193 SmallVector<SDValue, 6> RetOps; 1194 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1195 // Operand #1 = Bytes To Pop 1196 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1197 1198 // Copy the result values into the output registers. 1199 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1200 CCValAssign &VA = RVLocs[i]; 1201 assert(VA.isRegLoc() && "Can only return in registers!"); 1202 SDValue ValToCopy = Outs[i].Val; 1203 1204 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1205 // the RET instruction and handled by the FP Stackifier. 1206 if (VA.getLocReg() == X86::ST0 || 1207 VA.getLocReg() == X86::ST1) { 1208 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1209 // change the value to the FP stack register class. 1210 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1211 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1212 RetOps.push_back(ValToCopy); 1213 // Don't emit a copytoreg. 1214 continue; 1215 } 1216 1217 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1218 // which is returned in RAX / RDX. 1219 if (Subtarget->is64Bit()) { 1220 EVT ValVT = ValToCopy.getValueType(); 1221 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1222 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1223 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1224 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1225 } 1226 } 1227 1228 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1229 Flag = Chain.getValue(1); 1230 } 1231 1232 // The x86-64 ABI for returning structs by value requires that we copy 1233 // the sret argument into %rax for the return. We saved the argument into 1234 // a virtual register in the entry block, so now we copy the value out 1235 // and into %rax. 1236 if (Subtarget->is64Bit() && 1237 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1238 MachineFunction &MF = DAG.getMachineFunction(); 1239 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1240 unsigned Reg = FuncInfo->getSRetReturnReg(); 1241 if (!Reg) { 1242 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64)); 1243 FuncInfo->setSRetReturnReg(Reg); 1244 } 1245 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1246 1247 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1248 Flag = Chain.getValue(1); 1249 1250 // RAX now acts like a return value. 1251 MRI.addLiveOut(X86::RAX); 1252 } 1253 1254 RetOps[0] = Chain; // Update chain. 1255 1256 // Add the flag if we have it. 1257 if (Flag.getNode()) 1258 RetOps.push_back(Flag); 1259 1260 return DAG.getNode(X86ISD::RET_FLAG, dl, 1261 MVT::Other, &RetOps[0], RetOps.size()); 1262} 1263 1264/// LowerCallResult - Lower the result values of a call into the 1265/// appropriate copies out of appropriate physical registers. 1266/// 1267SDValue 1268X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1269 CallingConv::ID CallConv, bool isVarArg, 1270 const SmallVectorImpl<ISD::InputArg> &Ins, 1271 DebugLoc dl, SelectionDAG &DAG, 1272 SmallVectorImpl<SDValue> &InVals) { 1273 1274 // Assign locations to each value returned by this call. 1275 SmallVector<CCValAssign, 16> RVLocs; 1276 bool Is64Bit = Subtarget->is64Bit(); 1277 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1278 RVLocs, *DAG.getContext()); 1279 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1280 1281 // Copy all of the result registers out of their specified physreg. 1282 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1283 CCValAssign &VA = RVLocs[i]; 1284 EVT CopyVT = VA.getValVT(); 1285 1286 // If this is x86-64, and we disabled SSE, we can't return FP values 1287 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1288 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1289 llvm_report_error("SSE register return with SSE disabled"); 1290 } 1291 1292 // If this is a call to a function that returns an fp value on the floating 1293 // point stack, but where we prefer to use the value in xmm registers, copy 1294 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1295 if ((VA.getLocReg() == X86::ST0 || 1296 VA.getLocReg() == X86::ST1) && 1297 isScalarFPTypeInSSEReg(VA.getValVT())) { 1298 CopyVT = MVT::f80; 1299 } 1300 1301 SDValue Val; 1302 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1303 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1304 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1305 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1306 MVT::v2i64, InFlag).getValue(1); 1307 Val = Chain.getValue(0); 1308 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1309 Val, DAG.getConstant(0, MVT::i64)); 1310 } else { 1311 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1312 MVT::i64, InFlag).getValue(1); 1313 Val = Chain.getValue(0); 1314 } 1315 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1316 } else { 1317 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1318 CopyVT, InFlag).getValue(1); 1319 Val = Chain.getValue(0); 1320 } 1321 InFlag = Chain.getValue(2); 1322 1323 if (CopyVT != VA.getValVT()) { 1324 // Round the F80 the right size, which also moves to the appropriate xmm 1325 // register. 1326 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1327 // This truncation won't change the value. 1328 DAG.getIntPtrConstant(1)); 1329 } 1330 1331 InVals.push_back(Val); 1332 } 1333 1334 return Chain; 1335} 1336 1337 1338//===----------------------------------------------------------------------===// 1339// C & StdCall & Fast Calling Convention implementation 1340//===----------------------------------------------------------------------===// 1341// StdCall calling convention seems to be standard for many Windows' API 1342// routines and around. It differs from C calling convention just a little: 1343// callee should clean up the stack, not caller. Symbols should be also 1344// decorated in some fancy way :) It doesn't support any vector arguments. 1345// For info on fast calling convention see Fast Calling Convention (tail call) 1346// implementation LowerX86_32FastCCCallTo. 1347 1348/// CallIsStructReturn - Determines whether a call uses struct return 1349/// semantics. 1350static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1351 if (Outs.empty()) 1352 return false; 1353 1354 return Outs[0].Flags.isSRet(); 1355} 1356 1357/// ArgsAreStructReturn - Determines whether a function uses struct 1358/// return semantics. 1359static bool 1360ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1361 if (Ins.empty()) 1362 return false; 1363 1364 return Ins[0].Flags.isSRet(); 1365} 1366 1367/// IsCalleePop - Determines whether the callee is required to pop its 1368/// own arguments. Callee pop is necessary to support tail calls. 1369bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1370 if (IsVarArg) 1371 return false; 1372 1373 switch (CallingConv) { 1374 default: 1375 return false; 1376 case CallingConv::X86_StdCall: 1377 return !Subtarget->is64Bit(); 1378 case CallingConv::X86_FastCall: 1379 return !Subtarget->is64Bit(); 1380 case CallingConv::Fast: 1381 return GuaranteedTailCallOpt; 1382 } 1383} 1384 1385/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1386/// given CallingConvention value. 1387CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1388 if (Subtarget->is64Bit()) { 1389 if (Subtarget->isTargetWin64()) 1390 return CC_X86_Win64_C; 1391 else 1392 return CC_X86_64_C; 1393 } 1394 1395 if (CC == CallingConv::X86_FastCall) 1396 return CC_X86_32_FastCall; 1397 else if (CC == CallingConv::Fast) 1398 return CC_X86_32_FastCC; 1399 else 1400 return CC_X86_32_C; 1401} 1402 1403/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1404/// by "Src" to address "Dst" with size and alignment information specified by 1405/// the specific parameter attribute. The copy will be passed as a byval 1406/// function parameter. 1407static SDValue 1408CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1409 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1410 DebugLoc dl) { 1411 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1412 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1413 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1414} 1415 1416/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1417/// a tailcall target by changing its ABI. 1418static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1419 return GuaranteedTailCallOpt && CC == CallingConv::Fast; 1420} 1421 1422SDValue 1423X86TargetLowering::LowerMemArgument(SDValue Chain, 1424 CallingConv::ID CallConv, 1425 const SmallVectorImpl<ISD::InputArg> &Ins, 1426 DebugLoc dl, SelectionDAG &DAG, 1427 const CCValAssign &VA, 1428 MachineFrameInfo *MFI, 1429 unsigned i) { 1430 // Create the nodes corresponding to a load from this parameter slot. 1431 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1432 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1433 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1434 EVT ValVT; 1435 1436 // If value is passed by pointer we have address passed instead of the value 1437 // itself. 1438 if (VA.getLocInfo() == CCValAssign::Indirect) 1439 ValVT = VA.getLocVT(); 1440 else 1441 ValVT = VA.getValVT(); 1442 1443 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1444 // changed with more analysis. 1445 // In case of tail call optimization mark all arguments mutable. Since they 1446 // could be overwritten by lowering of arguments in case of a tail call. 1447 if (Flags.isByVal()) { 1448 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1449 VA.getLocMemOffset(), isImmutable, false); 1450 return DAG.getFrameIndex(FI, getPointerTy()); 1451 } else { 1452 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1453 VA.getLocMemOffset(), isImmutable, false); 1454 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1455 return DAG.getLoad(ValVT, dl, Chain, FIN, 1456 PseudoSourceValue::getFixedStack(FI), 0, 1457 false, false, 0); 1458 } 1459} 1460 1461SDValue 1462X86TargetLowering::LowerFormalArguments(SDValue Chain, 1463 CallingConv::ID CallConv, 1464 bool isVarArg, 1465 const SmallVectorImpl<ISD::InputArg> &Ins, 1466 DebugLoc dl, 1467 SelectionDAG &DAG, 1468 SmallVectorImpl<SDValue> &InVals) { 1469 1470 MachineFunction &MF = DAG.getMachineFunction(); 1471 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1472 1473 const Function* Fn = MF.getFunction(); 1474 if (Fn->hasExternalLinkage() && 1475 Subtarget->isTargetCygMing() && 1476 Fn->getName() == "main") 1477 FuncInfo->setForceFramePointer(true); 1478 1479 MachineFrameInfo *MFI = MF.getFrameInfo(); 1480 bool Is64Bit = Subtarget->is64Bit(); 1481 bool IsWin64 = Subtarget->isTargetWin64(); 1482 1483 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1484 "Var args not supported with calling convention fastcc"); 1485 1486 // Assign locations to all of the incoming arguments. 1487 SmallVector<CCValAssign, 16> ArgLocs; 1488 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1489 ArgLocs, *DAG.getContext()); 1490 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1491 1492 unsigned LastVal = ~0U; 1493 SDValue ArgValue; 1494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1495 CCValAssign &VA = ArgLocs[i]; 1496 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1497 // places. 1498 assert(VA.getValNo() != LastVal && 1499 "Don't support value assigned to multiple locs yet"); 1500 LastVal = VA.getValNo(); 1501 1502 if (VA.isRegLoc()) { 1503 EVT RegVT = VA.getLocVT(); 1504 TargetRegisterClass *RC = NULL; 1505 if (RegVT == MVT::i32) 1506 RC = X86::GR32RegisterClass; 1507 else if (Is64Bit && RegVT == MVT::i64) 1508 RC = X86::GR64RegisterClass; 1509 else if (RegVT == MVT::f32) 1510 RC = X86::FR32RegisterClass; 1511 else if (RegVT == MVT::f64) 1512 RC = X86::FR64RegisterClass; 1513 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1514 RC = X86::VR128RegisterClass; 1515 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1516 RC = X86::VR64RegisterClass; 1517 else 1518 llvm_unreachable("Unknown argument type!"); 1519 1520 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1521 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1522 1523 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1524 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1525 // right size. 1526 if (VA.getLocInfo() == CCValAssign::SExt) 1527 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1528 DAG.getValueType(VA.getValVT())); 1529 else if (VA.getLocInfo() == CCValAssign::ZExt) 1530 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1531 DAG.getValueType(VA.getValVT())); 1532 else if (VA.getLocInfo() == CCValAssign::BCvt) 1533 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1534 1535 if (VA.isExtInLoc()) { 1536 // Handle MMX values passed in XMM regs. 1537 if (RegVT.isVector()) { 1538 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1539 ArgValue, DAG.getConstant(0, MVT::i64)); 1540 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1541 } else 1542 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1543 } 1544 } else { 1545 assert(VA.isMemLoc()); 1546 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1547 } 1548 1549 // If value is passed via pointer - do a load. 1550 if (VA.getLocInfo() == CCValAssign::Indirect) 1551 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1552 false, false, 0); 1553 1554 InVals.push_back(ArgValue); 1555 } 1556 1557 // The x86-64 ABI for returning structs by value requires that we copy 1558 // the sret argument into %rax for the return. Save the argument into 1559 // a virtual register so that we can access it from the return points. 1560 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1561 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1562 unsigned Reg = FuncInfo->getSRetReturnReg(); 1563 if (!Reg) { 1564 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1565 FuncInfo->setSRetReturnReg(Reg); 1566 } 1567 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1569 } 1570 1571 unsigned StackSize = CCInfo.getNextStackOffset(); 1572 // Align stack specially for tail calls. 1573 if (FuncIsMadeTailCallSafe(CallConv)) 1574 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1575 1576 // If the function takes variable number of arguments, make a frame index for 1577 // the start of the first vararg value... for expansion of llvm.va_start. 1578 if (isVarArg) { 1579 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1580 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false); 1581 } 1582 if (Is64Bit) { 1583 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1584 1585 // FIXME: We should really autogenerate these arrays 1586 static const unsigned GPR64ArgRegsWin64[] = { 1587 X86::RCX, X86::RDX, X86::R8, X86::R9 1588 }; 1589 static const unsigned XMMArgRegsWin64[] = { 1590 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1591 }; 1592 static const unsigned GPR64ArgRegs64Bit[] = { 1593 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1594 }; 1595 static const unsigned XMMArgRegs64Bit[] = { 1596 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1597 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1598 }; 1599 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1600 1601 if (IsWin64) { 1602 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1603 GPR64ArgRegs = GPR64ArgRegsWin64; 1604 XMMArgRegs = XMMArgRegsWin64; 1605 } else { 1606 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1607 GPR64ArgRegs = GPR64ArgRegs64Bit; 1608 XMMArgRegs = XMMArgRegs64Bit; 1609 } 1610 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1611 TotalNumIntRegs); 1612 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1613 TotalNumXMMRegs); 1614 1615 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1616 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1617 "SSE register cannot be used when SSE is disabled!"); 1618 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1619 "SSE register cannot be used when SSE is disabled!"); 1620 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1621 // Kernel mode asks for SSE to be disabled, so don't push them 1622 // on the stack. 1623 TotalNumXMMRegs = 0; 1624 1625 // For X86-64, if there are vararg parameters that are passed via 1626 // registers, then we must store them to their spots on the stack so they 1627 // may be loaded by deferencing the result of va_next. 1628 VarArgsGPOffset = NumIntRegs * 8; 1629 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1630 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1631 TotalNumXMMRegs * 16, 16, 1632 false); 1633 1634 // Store the integer parameter registers. 1635 SmallVector<SDValue, 8> MemOps; 1636 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1637 unsigned Offset = VarArgsGPOffset; 1638 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1639 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1640 DAG.getIntPtrConstant(Offset)); 1641 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1642 X86::GR64RegisterClass); 1643 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1644 SDValue Store = 1645 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1646 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1647 Offset, false, false, 0); 1648 MemOps.push_back(Store); 1649 Offset += 8; 1650 } 1651 1652 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1653 // Now store the XMM (fp + vector) parameter registers. 1654 SmallVector<SDValue, 11> SaveXMMOps; 1655 SaveXMMOps.push_back(Chain); 1656 1657 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1658 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1659 SaveXMMOps.push_back(ALVal); 1660 1661 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1662 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1663 1664 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1665 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1666 X86::VR128RegisterClass); 1667 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1668 SaveXMMOps.push_back(Val); 1669 } 1670 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1671 MVT::Other, 1672 &SaveXMMOps[0], SaveXMMOps.size())); 1673 } 1674 1675 if (!MemOps.empty()) 1676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1677 &MemOps[0], MemOps.size()); 1678 } 1679 } 1680 1681 // Some CCs need callee pop. 1682 if (IsCalleePop(isVarArg, CallConv)) { 1683 BytesToPopOnReturn = StackSize; // Callee pops everything. 1684 } else { 1685 BytesToPopOnReturn = 0; // Callee pops nothing. 1686 // If this is an sret function, the return should pop the hidden pointer. 1687 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins)) 1688 BytesToPopOnReturn = 4; 1689 } 1690 1691 if (!Is64Bit) { 1692 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1693 if (CallConv == CallingConv::X86_FastCall) 1694 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1695 } 1696 1697 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1698 1699 return Chain; 1700} 1701 1702SDValue 1703X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1704 SDValue StackPtr, SDValue Arg, 1705 DebugLoc dl, SelectionDAG &DAG, 1706 const CCValAssign &VA, 1707 ISD::ArgFlagsTy Flags) { 1708 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1709 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1710 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1711 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1712 if (Flags.isByVal()) { 1713 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1714 } 1715 return DAG.getStore(Chain, dl, Arg, PtrOff, 1716 PseudoSourceValue::getStack(), LocMemOffset, 1717 false, false, 0); 1718} 1719 1720/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1721/// optimization is performed and it is required. 1722SDValue 1723X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1724 SDValue &OutRetAddr, SDValue Chain, 1725 bool IsTailCall, bool Is64Bit, 1726 int FPDiff, DebugLoc dl) { 1727 // Adjust the Return address stack slot. 1728 EVT VT = getPointerTy(); 1729 OutRetAddr = getReturnAddressFrameIndex(DAG); 1730 1731 // Load the "old" Return address. 1732 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1733 return SDValue(OutRetAddr.getNode(), 1); 1734} 1735 1736/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1737/// optimization is performed and it is required (FPDiff!=0). 1738static SDValue 1739EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1740 SDValue Chain, SDValue RetAddrFrIdx, 1741 bool Is64Bit, int FPDiff, DebugLoc dl) { 1742 // Store the return address to the appropriate stack slot. 1743 if (!FPDiff) return Chain; 1744 // Calculate the new stack slot for the return address. 1745 int SlotSize = Is64Bit ? 8 : 4; 1746 int NewReturnAddrFI = 1747 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false); 1748 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1749 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1750 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1751 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1752 false, false, 0); 1753 return Chain; 1754} 1755 1756SDValue 1757X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1758 CallingConv::ID CallConv, bool isVarArg, 1759 bool &isTailCall, 1760 const SmallVectorImpl<ISD::OutputArg> &Outs, 1761 const SmallVectorImpl<ISD::InputArg> &Ins, 1762 DebugLoc dl, SelectionDAG &DAG, 1763 SmallVectorImpl<SDValue> &InVals) { 1764 MachineFunction &MF = DAG.getMachineFunction(); 1765 bool Is64Bit = Subtarget->is64Bit(); 1766 bool IsStructRet = CallIsStructReturn(Outs); 1767 bool IsSibcall = false; 1768 1769 if (isTailCall) { 1770 // Check if it's really possible to do a tail call. 1771 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 1772 Outs, Ins, DAG); 1773 1774 // Sibcalls are automatically detected tailcalls which do not require 1775 // ABI changes. 1776 if (!GuaranteedTailCallOpt && isTailCall) 1777 IsSibcall = true; 1778 1779 if (isTailCall) 1780 ++NumTailCalls; 1781 } 1782 1783 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1784 "Var args not supported with calling convention fastcc"); 1785 1786 // Analyze operands of the call, assigning locations to each operand. 1787 SmallVector<CCValAssign, 16> ArgLocs; 1788 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1789 ArgLocs, *DAG.getContext()); 1790 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1791 1792 // Get a count of how many bytes are to be pushed on the stack. 1793 unsigned NumBytes = CCInfo.getNextStackOffset(); 1794 if (IsSibcall) 1795 // This is a sibcall. The memory operands are available in caller's 1796 // own caller's stack. 1797 NumBytes = 0; 1798 else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast) 1799 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1800 1801 int FPDiff = 0; 1802 if (isTailCall && !IsSibcall) { 1803 // Lower arguments at fp - stackoffset + fpdiff. 1804 unsigned NumBytesCallerPushed = 1805 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1806 FPDiff = NumBytesCallerPushed - NumBytes; 1807 1808 // Set the delta of movement of the returnaddr stackslot. 1809 // But only set if delta is greater than previous delta. 1810 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1811 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1812 } 1813 1814 if (!IsSibcall) 1815 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1816 1817 SDValue RetAddrFrIdx; 1818 // Load return adress for tail calls. 1819 if (isTailCall && FPDiff) 1820 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1821 Is64Bit, FPDiff, dl); 1822 1823 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1824 SmallVector<SDValue, 8> MemOpChains; 1825 SDValue StackPtr; 1826 1827 // Walk the register/memloc assignments, inserting copies/loads. In the case 1828 // of tail call optimization arguments are handle later. 1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1830 CCValAssign &VA = ArgLocs[i]; 1831 EVT RegVT = VA.getLocVT(); 1832 SDValue Arg = Outs[i].Val; 1833 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1834 bool isByVal = Flags.isByVal(); 1835 1836 // Promote the value if needed. 1837 switch (VA.getLocInfo()) { 1838 default: llvm_unreachable("Unknown loc info!"); 1839 case CCValAssign::Full: break; 1840 case CCValAssign::SExt: 1841 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1842 break; 1843 case CCValAssign::ZExt: 1844 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1845 break; 1846 case CCValAssign::AExt: 1847 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1848 // Special case: passing MMX values in XMM registers. 1849 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1850 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1851 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1852 } else 1853 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1854 break; 1855 case CCValAssign::BCvt: 1856 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1857 break; 1858 case CCValAssign::Indirect: { 1859 // Store the argument. 1860 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1861 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1862 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1863 PseudoSourceValue::getFixedStack(FI), 0, 1864 false, false, 0); 1865 Arg = SpillSlot; 1866 break; 1867 } 1868 } 1869 1870 if (VA.isRegLoc()) { 1871 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1872 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1873 assert(VA.isMemLoc()); 1874 if (StackPtr.getNode() == 0) 1875 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1876 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1877 dl, DAG, VA, Flags)); 1878 } 1879 } 1880 1881 if (!MemOpChains.empty()) 1882 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1883 &MemOpChains[0], MemOpChains.size()); 1884 1885 // Build a sequence of copy-to-reg nodes chained together with token chain 1886 // and flag operands which copy the outgoing args into registers. 1887 SDValue InFlag; 1888 // Tail call byval lowering might overwrite argument registers so in case of 1889 // tail call optimization the copies to registers are lowered later. 1890 if (!isTailCall) 1891 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1892 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1893 RegsToPass[i].second, InFlag); 1894 InFlag = Chain.getValue(1); 1895 } 1896 1897 if (Subtarget->isPICStyleGOT()) { 1898 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1899 // GOT pointer. 1900 if (!isTailCall) { 1901 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1902 DAG.getNode(X86ISD::GlobalBaseReg, 1903 DebugLoc::getUnknownLoc(), 1904 getPointerTy()), 1905 InFlag); 1906 InFlag = Chain.getValue(1); 1907 } else { 1908 // If we are tail calling and generating PIC/GOT style code load the 1909 // address of the callee into ECX. The value in ecx is used as target of 1910 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1911 // for tail calls on PIC/GOT architectures. Normally we would just put the 1912 // address of GOT into ebx and then call target@PLT. But for tail calls 1913 // ebx would be restored (since ebx is callee saved) before jumping to the 1914 // target@PLT. 1915 1916 // Note: The actual moving to ECX is done further down. 1917 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1918 if (G && !G->getGlobal()->hasHiddenVisibility() && 1919 !G->getGlobal()->hasProtectedVisibility()) 1920 Callee = LowerGlobalAddress(Callee, DAG); 1921 else if (isa<ExternalSymbolSDNode>(Callee)) 1922 Callee = LowerExternalSymbol(Callee, DAG); 1923 } 1924 } 1925 1926 if (Is64Bit && isVarArg) { 1927 // From AMD64 ABI document: 1928 // For calls that may call functions that use varargs or stdargs 1929 // (prototype-less calls or calls to functions containing ellipsis (...) in 1930 // the declaration) %al is used as hidden argument to specify the number 1931 // of SSE registers used. The contents of %al do not need to match exactly 1932 // the number of registers, but must be an ubound on the number of SSE 1933 // registers used and is in the range 0 - 8 inclusive. 1934 1935 // FIXME: Verify this on Win64 1936 // Count the number of XMM registers allocated. 1937 static const unsigned XMMArgRegs[] = { 1938 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1939 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1940 }; 1941 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1942 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1943 && "SSE registers cannot be used when SSE is disabled"); 1944 1945 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1946 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1947 InFlag = Chain.getValue(1); 1948 } 1949 1950 1951 // For tail calls lower the arguments to the 'real' stack slot. 1952 if (isTailCall) { 1953 // Force all the incoming stack arguments to be loaded from the stack 1954 // before any new outgoing arguments are stored to the stack, because the 1955 // outgoing stack slots may alias the incoming argument stack slots, and 1956 // the alias isn't otherwise explicit. This is slightly more conservative 1957 // than necessary, because it means that each store effectively depends 1958 // on every argument instead of just those arguments it would clobber. 1959 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1960 1961 SmallVector<SDValue, 8> MemOpChains2; 1962 SDValue FIN; 1963 int FI = 0; 1964 // Do not flag preceeding copytoreg stuff together with the following stuff. 1965 InFlag = SDValue(); 1966 if (GuaranteedTailCallOpt) { 1967 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1968 CCValAssign &VA = ArgLocs[i]; 1969 if (VA.isRegLoc()) 1970 continue; 1971 assert(VA.isMemLoc()); 1972 SDValue Arg = Outs[i].Val; 1973 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1974 // Create frame index. 1975 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1976 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1977 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false); 1978 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1979 1980 if (Flags.isByVal()) { 1981 // Copy relative to framepointer. 1982 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1983 if (StackPtr.getNode() == 0) 1984 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1985 getPointerTy()); 1986 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1987 1988 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 1989 ArgChain, 1990 Flags, DAG, dl)); 1991 } else { 1992 // Store relative to framepointer. 1993 MemOpChains2.push_back( 1994 DAG.getStore(ArgChain, dl, Arg, FIN, 1995 PseudoSourceValue::getFixedStack(FI), 0, 1996 false, false, 0)); 1997 } 1998 } 1999 } 2000 2001 if (!MemOpChains2.empty()) 2002 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2003 &MemOpChains2[0], MemOpChains2.size()); 2004 2005 // Copy arguments to their registers. 2006 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2007 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2008 RegsToPass[i].second, InFlag); 2009 InFlag = Chain.getValue(1); 2010 } 2011 InFlag =SDValue(); 2012 2013 // Store the return address to the appropriate stack slot. 2014 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2015 FPDiff, dl); 2016 } 2017 2018 bool WasGlobalOrExternal = false; 2019 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2020 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2021 // In the 64-bit large code model, we have to make all calls 2022 // through a register, since the call instruction's 32-bit 2023 // pc-relative offset may not be large enough to hold the whole 2024 // address. 2025 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2026 WasGlobalOrExternal = true; 2027 // If the callee is a GlobalAddress node (quite common, every direct call 2028 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2029 // it. 2030 2031 // We should use extra load for direct calls to dllimported functions in 2032 // non-JIT mode. 2033 GlobalValue *GV = G->getGlobal(); 2034 if (!GV->hasDLLImportLinkage()) { 2035 unsigned char OpFlags = 0; 2036 2037 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2038 // external symbols most go through the PLT in PIC mode. If the symbol 2039 // has hidden or protected visibility, or if it is static or local, then 2040 // we don't need to use the PLT - we can directly call it. 2041 if (Subtarget->isTargetELF() && 2042 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2043 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2044 OpFlags = X86II::MO_PLT; 2045 } else if (Subtarget->isPICStyleStubAny() && 2046 (GV->isDeclaration() || GV->isWeakForLinker()) && 2047 Subtarget->getDarwinVers() < 9) { 2048 // PC-relative references to external symbols should go through $stub, 2049 // unless we're building with the leopard linker or later, which 2050 // automatically synthesizes these stubs. 2051 OpFlags = X86II::MO_DARWIN_STUB; 2052 } 2053 2054 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 2055 G->getOffset(), OpFlags); 2056 } 2057 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2058 WasGlobalOrExternal = true; 2059 unsigned char OpFlags = 0; 2060 2061 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2062 // symbols should go through the PLT. 2063 if (Subtarget->isTargetELF() && 2064 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2065 OpFlags = X86II::MO_PLT; 2066 } else if (Subtarget->isPICStyleStubAny() && 2067 Subtarget->getDarwinVers() < 9) { 2068 // PC-relative references to external symbols should go through $stub, 2069 // unless we're building with the leopard linker or later, which 2070 // automatically synthesizes these stubs. 2071 OpFlags = X86II::MO_DARWIN_STUB; 2072 } 2073 2074 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2075 OpFlags); 2076 } 2077 2078 if (isTailCall && !WasGlobalOrExternal) { 2079 // Force the address into a (call preserved) caller-saved register since 2080 // tailcall must happen after callee-saved registers are poped. 2081 // FIXME: Give it a special register class that contains caller-saved 2082 // register instead? 2083 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX; 2084 Chain = DAG.getCopyToReg(Chain, dl, 2085 DAG.getRegister(TCReg, getPointerTy()), 2086 Callee,InFlag); 2087 Callee = DAG.getRegister(TCReg, getPointerTy()); 2088 } 2089 2090 // Returns a chain & a flag for retval copy to use. 2091 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2092 SmallVector<SDValue, 8> Ops; 2093 2094 if (!IsSibcall && isTailCall) { 2095 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2096 DAG.getIntPtrConstant(0, true), InFlag); 2097 InFlag = Chain.getValue(1); 2098 } 2099 2100 Ops.push_back(Chain); 2101 Ops.push_back(Callee); 2102 2103 if (isTailCall) 2104 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2105 2106 // Add argument registers to the end of the list so that they are known live 2107 // into the call. 2108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2109 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2110 RegsToPass[i].second.getValueType())); 2111 2112 // Add an implicit use GOT pointer in EBX. 2113 if (!isTailCall && Subtarget->isPICStyleGOT()) 2114 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2115 2116 // Add an implicit use of AL for x86 vararg functions. 2117 if (Is64Bit && isVarArg) 2118 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2119 2120 if (InFlag.getNode()) 2121 Ops.push_back(InFlag); 2122 2123 if (isTailCall) { 2124 // If this is the first return lowered for this function, add the regs 2125 // to the liveout set for the function. 2126 if (MF.getRegInfo().liveout_empty()) { 2127 SmallVector<CCValAssign, 16> RVLocs; 2128 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2129 *DAG.getContext()); 2130 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2131 for (unsigned i = 0; i != RVLocs.size(); ++i) 2132 if (RVLocs[i].isRegLoc()) 2133 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2134 } 2135 2136 assert(((Callee.getOpcode() == ISD::Register && 2137 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || 2138 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) || 2139 Callee.getOpcode() == ISD::TargetExternalSymbol || 2140 Callee.getOpcode() == ISD::TargetGlobalAddress) && 2141 "Expecting a global address, external symbol, or scratch register"); 2142 2143 return DAG.getNode(X86ISD::TC_RETURN, dl, 2144 NodeTys, &Ops[0], Ops.size()); 2145 } 2146 2147 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2148 InFlag = Chain.getValue(1); 2149 2150 // Create the CALLSEQ_END node. 2151 unsigned NumBytesForCalleeToPush; 2152 if (IsCalleePop(isVarArg, CallConv)) 2153 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2154 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet) 2155 // If this is a call to a struct-return function, the callee 2156 // pops the hidden struct pointer, so we have to push it back. 2157 // This is common for Darwin/X86, Linux & Mingw32 targets. 2158 NumBytesForCalleeToPush = 4; 2159 else 2160 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2161 2162 // Returns a flag for retval copy to use. 2163 if (!IsSibcall) { 2164 Chain = DAG.getCALLSEQ_END(Chain, 2165 DAG.getIntPtrConstant(NumBytes, true), 2166 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2167 true), 2168 InFlag); 2169 InFlag = Chain.getValue(1); 2170 } 2171 2172 // Handle result values, copying them out of physregs into vregs that we 2173 // return. 2174 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2175 Ins, dl, DAG, InVals); 2176} 2177 2178 2179//===----------------------------------------------------------------------===// 2180// Fast Calling Convention (tail call) implementation 2181//===----------------------------------------------------------------------===// 2182 2183// Like std call, callee cleans arguments, convention except that ECX is 2184// reserved for storing the tail called function address. Only 2 registers are 2185// free for argument passing (inreg). Tail call optimization is performed 2186// provided: 2187// * tailcallopt is enabled 2188// * caller/callee are fastcc 2189// On X86_64 architecture with GOT-style position independent code only local 2190// (within module) calls are supported at the moment. 2191// To keep the stack aligned according to platform abi the function 2192// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2193// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2194// If a tail called function callee has more arguments than the caller the 2195// caller needs to make sure that there is room to move the RETADDR to. This is 2196// achieved by reserving an area the size of the argument delta right after the 2197// original REtADDR, but before the saved framepointer or the spilled registers 2198// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2199// stack layout: 2200// arg1 2201// arg2 2202// RETADDR 2203// [ new RETADDR 2204// move area ] 2205// (possible EBP) 2206// ESI 2207// EDI 2208// local1 .. 2209 2210/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2211/// for a 16 byte align requirement. 2212unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2213 SelectionDAG& DAG) { 2214 MachineFunction &MF = DAG.getMachineFunction(); 2215 const TargetMachine &TM = MF.getTarget(); 2216 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2217 unsigned StackAlignment = TFI.getStackAlignment(); 2218 uint64_t AlignMask = StackAlignment - 1; 2219 int64_t Offset = StackSize; 2220 uint64_t SlotSize = TD->getPointerSize(); 2221 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2222 // Number smaller than 12 so just add the difference. 2223 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2224 } else { 2225 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2226 Offset = ((~AlignMask) & Offset) + StackAlignment + 2227 (StackAlignment-SlotSize); 2228 } 2229 return Offset; 2230} 2231 2232/// MatchingStackOffset - Return true if the given stack call argument is 2233/// already available in the same position (relatively) of the caller's 2234/// incoming argument stack. 2235static 2236bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2237 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2238 const X86InstrInfo *TII) { 2239 int FI; 2240 if (Arg.getOpcode() == ISD::CopyFromReg) { 2241 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2242 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2243 return false; 2244 MachineInstr *Def = MRI->getVRegDef(VR); 2245 if (!Def) 2246 return false; 2247 if (!Flags.isByVal()) { 2248 if (!TII->isLoadFromStackSlot(Def, FI)) 2249 return false; 2250 } else { 2251 unsigned Opcode = Def->getOpcode(); 2252 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2253 Def->getOperand(1).isFI()) { 2254 FI = Def->getOperand(1).getIndex(); 2255 if (MFI->getObjectSize(FI) != Flags.getByValSize()) 2256 return false; 2257 } else 2258 return false; 2259 } 2260 } else { 2261 LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg); 2262 if (!Ld) 2263 return false; 2264 SDValue Ptr = Ld->getBasePtr(); 2265 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2266 if (!FINode) 2267 return false; 2268 FI = FINode->getIndex(); 2269 } 2270 2271 if (!MFI->isFixedObjectIndex(FI)) 2272 return false; 2273 return Offset == MFI->getObjectOffset(FI); 2274} 2275 2276/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2277/// for tail call optimization. Targets which want to do tail call 2278/// optimization should implement this function. 2279bool 2280X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2281 CallingConv::ID CalleeCC, 2282 bool isVarArg, 2283 const SmallVectorImpl<ISD::OutputArg> &Outs, 2284 const SmallVectorImpl<ISD::InputArg> &Ins, 2285 SelectionDAG& DAG) const { 2286 if (CalleeCC != CallingConv::Fast && 2287 CalleeCC != CallingConv::C) 2288 return false; 2289 2290 // If -tailcallopt is specified, make fastcc functions tail-callable. 2291 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2292 if (GuaranteedTailCallOpt) { 2293 if (CalleeCC == CallingConv::Fast && 2294 CallerF->getCallingConv() == CalleeCC) 2295 return true; 2296 return false; 2297 } 2298 2299 // Look for obvious safe cases to perform tail call optimization that does not 2300 // requite ABI changes. This is what gcc calls sibcall. 2301 2302 // Do not tail call optimize vararg calls for now. 2303 if (isVarArg) 2304 return false; 2305 2306 // If the callee takes no arguments then go on to check the results of the 2307 // call. 2308 if (!Outs.empty()) { 2309 // Check if stack adjustment is needed. For now, do not do this if any 2310 // argument is passed on the stack. 2311 SmallVector<CCValAssign, 16> ArgLocs; 2312 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2313 ArgLocs, *DAG.getContext()); 2314 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2315 if (CCInfo.getNextStackOffset()) { 2316 MachineFunction &MF = DAG.getMachineFunction(); 2317 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2318 return false; 2319 if (Subtarget->isTargetWin64()) 2320 // Win64 ABI has additional complications. 2321 return false; 2322 2323 // Check if the arguments are already laid out in the right way as 2324 // the caller's fixed stack objects. 2325 MachineFrameInfo *MFI = MF.getFrameInfo(); 2326 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2327 const X86InstrInfo *TII = 2328 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2329 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2330 CCValAssign &VA = ArgLocs[i]; 2331 EVT RegVT = VA.getLocVT(); 2332 SDValue Arg = Outs[i].Val; 2333 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2334 if (VA.getLocInfo() == CCValAssign::Indirect) 2335 return false; 2336 if (!VA.isRegLoc()) { 2337 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2338 MFI, MRI, TII)) 2339 return false; 2340 } 2341 } 2342 } 2343 } 2344 2345 return true; 2346} 2347 2348FastISel * 2349X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, 2350 DwarfWriter *dw, 2351 DenseMap<const Value *, unsigned> &vm, 2352 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, 2353 DenseMap<const AllocaInst *, int> &am 2354#ifndef NDEBUG 2355 , SmallSet<Instruction*, 8> &cil 2356#endif 2357 ) { 2358 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2359#ifndef NDEBUG 2360 , cil 2361#endif 2362 ); 2363} 2364 2365 2366//===----------------------------------------------------------------------===// 2367// Other Lowering Hooks 2368//===----------------------------------------------------------------------===// 2369 2370 2371SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2372 MachineFunction &MF = DAG.getMachineFunction(); 2373 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2374 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2375 2376 if (ReturnAddrIndex == 0) { 2377 // Set up a frame object for the return address. 2378 uint64_t SlotSize = TD->getPointerSize(); 2379 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2380 true, false); 2381 FuncInfo->setRAIndex(ReturnAddrIndex); 2382 } 2383 2384 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2385} 2386 2387 2388bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2389 bool hasSymbolicDisplacement) { 2390 // Offset should fit into 32 bit immediate field. 2391 if (!isInt32(Offset)) 2392 return false; 2393 2394 // If we don't have a symbolic displacement - we don't have any extra 2395 // restrictions. 2396 if (!hasSymbolicDisplacement) 2397 return true; 2398 2399 // FIXME: Some tweaks might be needed for medium code model. 2400 if (M != CodeModel::Small && M != CodeModel::Kernel) 2401 return false; 2402 2403 // For small code model we assume that latest object is 16MB before end of 31 2404 // bits boundary. We may also accept pretty large negative constants knowing 2405 // that all objects are in the positive half of address space. 2406 if (M == CodeModel::Small && Offset < 16*1024*1024) 2407 return true; 2408 2409 // For kernel code model we know that all object resist in the negative half 2410 // of 32bits address space. We may not accept negative offsets, since they may 2411 // be just off and we may accept pretty large positive ones. 2412 if (M == CodeModel::Kernel && Offset > 0) 2413 return true; 2414 2415 return false; 2416} 2417 2418/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2419/// specific condition code, returning the condition code and the LHS/RHS of the 2420/// comparison to make. 2421static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2422 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2423 if (!isFP) { 2424 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2425 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2426 // X > -1 -> X == 0, jump !sign. 2427 RHS = DAG.getConstant(0, RHS.getValueType()); 2428 return X86::COND_NS; 2429 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2430 // X < 0 -> X == 0, jump on sign. 2431 return X86::COND_S; 2432 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2433 // X < 1 -> X <= 0 2434 RHS = DAG.getConstant(0, RHS.getValueType()); 2435 return X86::COND_LE; 2436 } 2437 } 2438 2439 switch (SetCCOpcode) { 2440 default: llvm_unreachable("Invalid integer condition!"); 2441 case ISD::SETEQ: return X86::COND_E; 2442 case ISD::SETGT: return X86::COND_G; 2443 case ISD::SETGE: return X86::COND_GE; 2444 case ISD::SETLT: return X86::COND_L; 2445 case ISD::SETLE: return X86::COND_LE; 2446 case ISD::SETNE: return X86::COND_NE; 2447 case ISD::SETULT: return X86::COND_B; 2448 case ISD::SETUGT: return X86::COND_A; 2449 case ISD::SETULE: return X86::COND_BE; 2450 case ISD::SETUGE: return X86::COND_AE; 2451 } 2452 } 2453 2454 // First determine if it is required or is profitable to flip the operands. 2455 2456 // If LHS is a foldable load, but RHS is not, flip the condition. 2457 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2458 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2459 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2460 std::swap(LHS, RHS); 2461 } 2462 2463 switch (SetCCOpcode) { 2464 default: break; 2465 case ISD::SETOLT: 2466 case ISD::SETOLE: 2467 case ISD::SETUGT: 2468 case ISD::SETUGE: 2469 std::swap(LHS, RHS); 2470 break; 2471 } 2472 2473 // On a floating point condition, the flags are set as follows: 2474 // ZF PF CF op 2475 // 0 | 0 | 0 | X > Y 2476 // 0 | 0 | 1 | X < Y 2477 // 1 | 0 | 0 | X == Y 2478 // 1 | 1 | 1 | unordered 2479 switch (SetCCOpcode) { 2480 default: llvm_unreachable("Condcode should be pre-legalized away"); 2481 case ISD::SETUEQ: 2482 case ISD::SETEQ: return X86::COND_E; 2483 case ISD::SETOLT: // flipped 2484 case ISD::SETOGT: 2485 case ISD::SETGT: return X86::COND_A; 2486 case ISD::SETOLE: // flipped 2487 case ISD::SETOGE: 2488 case ISD::SETGE: return X86::COND_AE; 2489 case ISD::SETUGT: // flipped 2490 case ISD::SETULT: 2491 case ISD::SETLT: return X86::COND_B; 2492 case ISD::SETUGE: // flipped 2493 case ISD::SETULE: 2494 case ISD::SETLE: return X86::COND_BE; 2495 case ISD::SETONE: 2496 case ISD::SETNE: return X86::COND_NE; 2497 case ISD::SETUO: return X86::COND_P; 2498 case ISD::SETO: return X86::COND_NP; 2499 case ISD::SETOEQ: 2500 case ISD::SETUNE: return X86::COND_INVALID; 2501 } 2502} 2503 2504/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2505/// code. Current x86 isa includes the following FP cmov instructions: 2506/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2507static bool hasFPCMov(unsigned X86CC) { 2508 switch (X86CC) { 2509 default: 2510 return false; 2511 case X86::COND_B: 2512 case X86::COND_BE: 2513 case X86::COND_E: 2514 case X86::COND_P: 2515 case X86::COND_A: 2516 case X86::COND_AE: 2517 case X86::COND_NE: 2518 case X86::COND_NP: 2519 return true; 2520 } 2521} 2522 2523/// isFPImmLegal - Returns true if the target can instruction select the 2524/// specified FP immediate natively. If false, the legalizer will 2525/// materialize the FP immediate as a load from a constant pool. 2526bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2527 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2528 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2529 return true; 2530 } 2531 return false; 2532} 2533 2534/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2535/// the specified range (L, H]. 2536static bool isUndefOrInRange(int Val, int Low, int Hi) { 2537 return (Val < 0) || (Val >= Low && Val < Hi); 2538} 2539 2540/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2541/// specified value. 2542static bool isUndefOrEqual(int Val, int CmpVal) { 2543 if (Val < 0 || Val == CmpVal) 2544 return true; 2545 return false; 2546} 2547 2548/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2549/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2550/// the second operand. 2551static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2552 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2553 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2554 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2555 return (Mask[0] < 2 && Mask[1] < 2); 2556 return false; 2557} 2558 2559bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2560 SmallVector<int, 8> M; 2561 N->getMask(M); 2562 return ::isPSHUFDMask(M, N->getValueType(0)); 2563} 2564 2565/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2566/// is suitable for input to PSHUFHW. 2567static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2568 if (VT != MVT::v8i16) 2569 return false; 2570 2571 // Lower quadword copied in order or undef. 2572 for (int i = 0; i != 4; ++i) 2573 if (Mask[i] >= 0 && Mask[i] != i) 2574 return false; 2575 2576 // Upper quadword shuffled. 2577 for (int i = 4; i != 8; ++i) 2578 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2579 return false; 2580 2581 return true; 2582} 2583 2584bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2585 SmallVector<int, 8> M; 2586 N->getMask(M); 2587 return ::isPSHUFHWMask(M, N->getValueType(0)); 2588} 2589 2590/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2591/// is suitable for input to PSHUFLW. 2592static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2593 if (VT != MVT::v8i16) 2594 return false; 2595 2596 // Upper quadword copied in order. 2597 for (int i = 4; i != 8; ++i) 2598 if (Mask[i] >= 0 && Mask[i] != i) 2599 return false; 2600 2601 // Lower quadword shuffled. 2602 for (int i = 0; i != 4; ++i) 2603 if (Mask[i] >= 4) 2604 return false; 2605 2606 return true; 2607} 2608 2609bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2610 SmallVector<int, 8> M; 2611 N->getMask(M); 2612 return ::isPSHUFLWMask(M, N->getValueType(0)); 2613} 2614 2615/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2616/// is suitable for input to PALIGNR. 2617static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2618 bool hasSSSE3) { 2619 int i, e = VT.getVectorNumElements(); 2620 2621 // Do not handle v2i64 / v2f64 shuffles with palignr. 2622 if (e < 4 || !hasSSSE3) 2623 return false; 2624 2625 for (i = 0; i != e; ++i) 2626 if (Mask[i] >= 0) 2627 break; 2628 2629 // All undef, not a palignr. 2630 if (i == e) 2631 return false; 2632 2633 // Determine if it's ok to perform a palignr with only the LHS, since we 2634 // don't have access to the actual shuffle elements to see if RHS is undef. 2635 bool Unary = Mask[i] < (int)e; 2636 bool NeedsUnary = false; 2637 2638 int s = Mask[i] - i; 2639 2640 // Check the rest of the elements to see if they are consecutive. 2641 for (++i; i != e; ++i) { 2642 int m = Mask[i]; 2643 if (m < 0) 2644 continue; 2645 2646 Unary = Unary && (m < (int)e); 2647 NeedsUnary = NeedsUnary || (m < s); 2648 2649 if (NeedsUnary && !Unary) 2650 return false; 2651 if (Unary && m != ((s+i) & (e-1))) 2652 return false; 2653 if (!Unary && m != (s+i)) 2654 return false; 2655 } 2656 return true; 2657} 2658 2659bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2660 SmallVector<int, 8> M; 2661 N->getMask(M); 2662 return ::isPALIGNRMask(M, N->getValueType(0), true); 2663} 2664 2665/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2666/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2667static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2668 int NumElems = VT.getVectorNumElements(); 2669 if (NumElems != 2 && NumElems != 4) 2670 return false; 2671 2672 int Half = NumElems / 2; 2673 for (int i = 0; i < Half; ++i) 2674 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2675 return false; 2676 for (int i = Half; i < NumElems; ++i) 2677 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2678 return false; 2679 2680 return true; 2681} 2682 2683bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2684 SmallVector<int, 8> M; 2685 N->getMask(M); 2686 return ::isSHUFPMask(M, N->getValueType(0)); 2687} 2688 2689/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2690/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2691/// half elements to come from vector 1 (which would equal the dest.) and 2692/// the upper half to come from vector 2. 2693static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2694 int NumElems = VT.getVectorNumElements(); 2695 2696 if (NumElems != 2 && NumElems != 4) 2697 return false; 2698 2699 int Half = NumElems / 2; 2700 for (int i = 0; i < Half; ++i) 2701 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2702 return false; 2703 for (int i = Half; i < NumElems; ++i) 2704 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2705 return false; 2706 return true; 2707} 2708 2709static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2710 SmallVector<int, 8> M; 2711 N->getMask(M); 2712 return isCommutedSHUFPMask(M, N->getValueType(0)); 2713} 2714 2715/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2716/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2717bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2718 if (N->getValueType(0).getVectorNumElements() != 4) 2719 return false; 2720 2721 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2722 return isUndefOrEqual(N->getMaskElt(0), 6) && 2723 isUndefOrEqual(N->getMaskElt(1), 7) && 2724 isUndefOrEqual(N->getMaskElt(2), 2) && 2725 isUndefOrEqual(N->getMaskElt(3), 3); 2726} 2727 2728/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2729/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2730/// <2, 3, 2, 3> 2731bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2732 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2733 2734 if (NumElems != 4) 2735 return false; 2736 2737 return isUndefOrEqual(N->getMaskElt(0), 2) && 2738 isUndefOrEqual(N->getMaskElt(1), 3) && 2739 isUndefOrEqual(N->getMaskElt(2), 2) && 2740 isUndefOrEqual(N->getMaskElt(3), 3); 2741} 2742 2743/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2744/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2745bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2746 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2747 2748 if (NumElems != 2 && NumElems != 4) 2749 return false; 2750 2751 for (unsigned i = 0; i < NumElems/2; ++i) 2752 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2753 return false; 2754 2755 for (unsigned i = NumElems/2; i < NumElems; ++i) 2756 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2757 return false; 2758 2759 return true; 2760} 2761 2762/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2763/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2764bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2765 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2766 2767 if (NumElems != 2 && NumElems != 4) 2768 return false; 2769 2770 for (unsigned i = 0; i < NumElems/2; ++i) 2771 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2772 return false; 2773 2774 for (unsigned i = 0; i < NumElems/2; ++i) 2775 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2776 return false; 2777 2778 return true; 2779} 2780 2781/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2782/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2783static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2784 bool V2IsSplat = false) { 2785 int NumElts = VT.getVectorNumElements(); 2786 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2787 return false; 2788 2789 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2790 int BitI = Mask[i]; 2791 int BitI1 = Mask[i+1]; 2792 if (!isUndefOrEqual(BitI, j)) 2793 return false; 2794 if (V2IsSplat) { 2795 if (!isUndefOrEqual(BitI1, NumElts)) 2796 return false; 2797 } else { 2798 if (!isUndefOrEqual(BitI1, j + NumElts)) 2799 return false; 2800 } 2801 } 2802 return true; 2803} 2804 2805bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2806 SmallVector<int, 8> M; 2807 N->getMask(M); 2808 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2809} 2810 2811/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2812/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2813static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2814 bool V2IsSplat = false) { 2815 int NumElts = VT.getVectorNumElements(); 2816 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2817 return false; 2818 2819 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2820 int BitI = Mask[i]; 2821 int BitI1 = Mask[i+1]; 2822 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2823 return false; 2824 if (V2IsSplat) { 2825 if (isUndefOrEqual(BitI1, NumElts)) 2826 return false; 2827 } else { 2828 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2829 return false; 2830 } 2831 } 2832 return true; 2833} 2834 2835bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2836 SmallVector<int, 8> M; 2837 N->getMask(M); 2838 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2839} 2840 2841/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2842/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2843/// <0, 0, 1, 1> 2844static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2845 int NumElems = VT.getVectorNumElements(); 2846 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2847 return false; 2848 2849 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2850 int BitI = Mask[i]; 2851 int BitI1 = Mask[i+1]; 2852 if (!isUndefOrEqual(BitI, j)) 2853 return false; 2854 if (!isUndefOrEqual(BitI1, j)) 2855 return false; 2856 } 2857 return true; 2858} 2859 2860bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2861 SmallVector<int, 8> M; 2862 N->getMask(M); 2863 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2864} 2865 2866/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2867/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2868/// <2, 2, 3, 3> 2869static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2870 int NumElems = VT.getVectorNumElements(); 2871 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2872 return false; 2873 2874 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2875 int BitI = Mask[i]; 2876 int BitI1 = Mask[i+1]; 2877 if (!isUndefOrEqual(BitI, j)) 2878 return false; 2879 if (!isUndefOrEqual(BitI1, j)) 2880 return false; 2881 } 2882 return true; 2883} 2884 2885bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2886 SmallVector<int, 8> M; 2887 N->getMask(M); 2888 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2889} 2890 2891/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2892/// specifies a shuffle of elements that is suitable for input to MOVSS, 2893/// MOVSD, and MOVD, i.e. setting the lowest element. 2894static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2895 if (VT.getVectorElementType().getSizeInBits() < 32) 2896 return false; 2897 2898 int NumElts = VT.getVectorNumElements(); 2899 2900 if (!isUndefOrEqual(Mask[0], NumElts)) 2901 return false; 2902 2903 for (int i = 1; i < NumElts; ++i) 2904 if (!isUndefOrEqual(Mask[i], i)) 2905 return false; 2906 2907 return true; 2908} 2909 2910bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2911 SmallVector<int, 8> M; 2912 N->getMask(M); 2913 return ::isMOVLMask(M, N->getValueType(0)); 2914} 2915 2916/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2917/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2918/// element of vector 2 and the other elements to come from vector 1 in order. 2919static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2920 bool V2IsSplat = false, bool V2IsUndef = false) { 2921 int NumOps = VT.getVectorNumElements(); 2922 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2923 return false; 2924 2925 if (!isUndefOrEqual(Mask[0], 0)) 2926 return false; 2927 2928 for (int i = 1; i < NumOps; ++i) 2929 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2930 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2931 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2932 return false; 2933 2934 return true; 2935} 2936 2937static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2938 bool V2IsUndef = false) { 2939 SmallVector<int, 8> M; 2940 N->getMask(M); 2941 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2942} 2943 2944/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2945/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2946bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2947 if (N->getValueType(0).getVectorNumElements() != 4) 2948 return false; 2949 2950 // Expect 1, 1, 3, 3 2951 for (unsigned i = 0; i < 2; ++i) { 2952 int Elt = N->getMaskElt(i); 2953 if (Elt >= 0 && Elt != 1) 2954 return false; 2955 } 2956 2957 bool HasHi = false; 2958 for (unsigned i = 2; i < 4; ++i) { 2959 int Elt = N->getMaskElt(i); 2960 if (Elt >= 0 && Elt != 3) 2961 return false; 2962 if (Elt == 3) 2963 HasHi = true; 2964 } 2965 // Don't use movshdup if it can be done with a shufps. 2966 // FIXME: verify that matching u, u, 3, 3 is what we want. 2967 return HasHi; 2968} 2969 2970/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2971/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2972bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 2973 if (N->getValueType(0).getVectorNumElements() != 4) 2974 return false; 2975 2976 // Expect 0, 0, 2, 2 2977 for (unsigned i = 0; i < 2; ++i) 2978 if (N->getMaskElt(i) > 0) 2979 return false; 2980 2981 bool HasHi = false; 2982 for (unsigned i = 2; i < 4; ++i) { 2983 int Elt = N->getMaskElt(i); 2984 if (Elt >= 0 && Elt != 2) 2985 return false; 2986 if (Elt == 2) 2987 HasHi = true; 2988 } 2989 // Don't use movsldup if it can be done with a shufps. 2990 return HasHi; 2991} 2992 2993/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2994/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2995bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 2996 int e = N->getValueType(0).getVectorNumElements() / 2; 2997 2998 for (int i = 0; i < e; ++i) 2999 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3000 return false; 3001 for (int i = 0; i < e; ++i) 3002 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3003 return false; 3004 return true; 3005} 3006 3007/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3008/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3009unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3011 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3012 3013 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3014 unsigned Mask = 0; 3015 for (int i = 0; i < NumOperands; ++i) { 3016 int Val = SVOp->getMaskElt(NumOperands-i-1); 3017 if (Val < 0) Val = 0; 3018 if (Val >= NumOperands) Val -= NumOperands; 3019 Mask |= Val; 3020 if (i != NumOperands - 1) 3021 Mask <<= Shift; 3022 } 3023 return Mask; 3024} 3025 3026/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3027/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3028unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3030 unsigned Mask = 0; 3031 // 8 nodes, but we only care about the last 4. 3032 for (unsigned i = 7; i >= 4; --i) { 3033 int Val = SVOp->getMaskElt(i); 3034 if (Val >= 0) 3035 Mask |= (Val - 4); 3036 if (i != 4) 3037 Mask <<= 2; 3038 } 3039 return Mask; 3040} 3041 3042/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3043/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3044unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3046 unsigned Mask = 0; 3047 // 8 nodes, but we only care about the first 4. 3048 for (int i = 3; i >= 0; --i) { 3049 int Val = SVOp->getMaskElt(i); 3050 if (Val >= 0) 3051 Mask |= Val; 3052 if (i != 0) 3053 Mask <<= 2; 3054 } 3055 return Mask; 3056} 3057 3058/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3059/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3060unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3061 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3062 EVT VVT = N->getValueType(0); 3063 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3064 int Val = 0; 3065 3066 unsigned i, e; 3067 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3068 Val = SVOp->getMaskElt(i); 3069 if (Val >= 0) 3070 break; 3071 } 3072 return (Val - i) * EltSize; 3073} 3074 3075/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3076/// constant +0.0. 3077bool X86::isZeroNode(SDValue Elt) { 3078 return ((isa<ConstantSDNode>(Elt) && 3079 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 3080 (isa<ConstantFPSDNode>(Elt) && 3081 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3082} 3083 3084/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3085/// their permute mask. 3086static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3087 SelectionDAG &DAG) { 3088 EVT VT = SVOp->getValueType(0); 3089 unsigned NumElems = VT.getVectorNumElements(); 3090 SmallVector<int, 8> MaskVec; 3091 3092 for (unsigned i = 0; i != NumElems; ++i) { 3093 int idx = SVOp->getMaskElt(i); 3094 if (idx < 0) 3095 MaskVec.push_back(idx); 3096 else if (idx < (int)NumElems) 3097 MaskVec.push_back(idx + NumElems); 3098 else 3099 MaskVec.push_back(idx - NumElems); 3100 } 3101 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3102 SVOp->getOperand(0), &MaskVec[0]); 3103} 3104 3105/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3106/// the two vector operands have swapped position. 3107static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3108 unsigned NumElems = VT.getVectorNumElements(); 3109 for (unsigned i = 0; i != NumElems; ++i) { 3110 int idx = Mask[i]; 3111 if (idx < 0) 3112 continue; 3113 else if (idx < (int)NumElems) 3114 Mask[i] = idx + NumElems; 3115 else 3116 Mask[i] = idx - NumElems; 3117 } 3118} 3119 3120/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3121/// match movhlps. The lower half elements should come from upper half of 3122/// V1 (and in order), and the upper half elements should come from the upper 3123/// half of V2 (and in order). 3124static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3125 if (Op->getValueType(0).getVectorNumElements() != 4) 3126 return false; 3127 for (unsigned i = 0, e = 2; i != e; ++i) 3128 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3129 return false; 3130 for (unsigned i = 2; i != 4; ++i) 3131 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3132 return false; 3133 return true; 3134} 3135 3136/// isScalarLoadToVector - Returns true if the node is a scalar load that 3137/// is promoted to a vector. It also returns the LoadSDNode by reference if 3138/// required. 3139static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3140 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3141 return false; 3142 N = N->getOperand(0).getNode(); 3143 if (!ISD::isNON_EXTLoad(N)) 3144 return false; 3145 if (LD) 3146 *LD = cast<LoadSDNode>(N); 3147 return true; 3148} 3149 3150/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3151/// match movlp{s|d}. The lower half elements should come from lower half of 3152/// V1 (and in order), and the upper half elements should come from the upper 3153/// half of V2 (and in order). And since V1 will become the source of the 3154/// MOVLP, it must be either a vector load or a scalar load to vector. 3155static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3156 ShuffleVectorSDNode *Op) { 3157 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3158 return false; 3159 // Is V2 is a vector load, don't do this transformation. We will try to use 3160 // load folding shufps op. 3161 if (ISD::isNON_EXTLoad(V2)) 3162 return false; 3163 3164 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3165 3166 if (NumElems != 2 && NumElems != 4) 3167 return false; 3168 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3169 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3170 return false; 3171 for (unsigned i = NumElems/2; i != NumElems; ++i) 3172 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3173 return false; 3174 return true; 3175} 3176 3177/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3178/// all the same. 3179static bool isSplatVector(SDNode *N) { 3180 if (N->getOpcode() != ISD::BUILD_VECTOR) 3181 return false; 3182 3183 SDValue SplatValue = N->getOperand(0); 3184 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3185 if (N->getOperand(i) != SplatValue) 3186 return false; 3187 return true; 3188} 3189 3190/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3191/// to an zero vector. 3192/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3193static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3194 SDValue V1 = N->getOperand(0); 3195 SDValue V2 = N->getOperand(1); 3196 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3197 for (unsigned i = 0; i != NumElems; ++i) { 3198 int Idx = N->getMaskElt(i); 3199 if (Idx >= (int)NumElems) { 3200 unsigned Opc = V2.getOpcode(); 3201 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3202 continue; 3203 if (Opc != ISD::BUILD_VECTOR || 3204 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3205 return false; 3206 } else if (Idx >= 0) { 3207 unsigned Opc = V1.getOpcode(); 3208 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3209 continue; 3210 if (Opc != ISD::BUILD_VECTOR || 3211 !X86::isZeroNode(V1.getOperand(Idx))) 3212 return false; 3213 } 3214 } 3215 return true; 3216} 3217 3218/// getZeroVector - Returns a vector of specified type with all zero elements. 3219/// 3220static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3221 DebugLoc dl) { 3222 assert(VT.isVector() && "Expected a vector type"); 3223 3224 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3225 // type. This ensures they get CSE'd. 3226 SDValue Vec; 3227 if (VT.getSizeInBits() == 64) { // MMX 3228 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3229 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3230 } else if (HasSSE2) { // SSE2 3231 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3232 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3233 } else { // SSE1 3234 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3235 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3236 } 3237 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3238} 3239 3240/// getOnesVector - Returns a vector of specified type with all bits set. 3241/// 3242static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3243 assert(VT.isVector() && "Expected a vector type"); 3244 3245 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3246 // type. This ensures they get CSE'd. 3247 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3248 SDValue Vec; 3249 if (VT.getSizeInBits() == 64) // MMX 3250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3251 else // SSE 3252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3253 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3254} 3255 3256 3257/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3258/// that point to V2 points to its first element. 3259static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3260 EVT VT = SVOp->getValueType(0); 3261 unsigned NumElems = VT.getVectorNumElements(); 3262 3263 bool Changed = false; 3264 SmallVector<int, 8> MaskVec; 3265 SVOp->getMask(MaskVec); 3266 3267 for (unsigned i = 0; i != NumElems; ++i) { 3268 if (MaskVec[i] > (int)NumElems) { 3269 MaskVec[i] = NumElems; 3270 Changed = true; 3271 } 3272 } 3273 if (Changed) 3274 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3275 SVOp->getOperand(1), &MaskVec[0]); 3276 return SDValue(SVOp, 0); 3277} 3278 3279/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3280/// operation of specified width. 3281static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3282 SDValue V2) { 3283 unsigned NumElems = VT.getVectorNumElements(); 3284 SmallVector<int, 8> Mask; 3285 Mask.push_back(NumElems); 3286 for (unsigned i = 1; i != NumElems; ++i) 3287 Mask.push_back(i); 3288 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3289} 3290 3291/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3292static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3293 SDValue V2) { 3294 unsigned NumElems = VT.getVectorNumElements(); 3295 SmallVector<int, 8> Mask; 3296 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3297 Mask.push_back(i); 3298 Mask.push_back(i + NumElems); 3299 } 3300 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3301} 3302 3303/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3304static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3305 SDValue V2) { 3306 unsigned NumElems = VT.getVectorNumElements(); 3307 unsigned Half = NumElems/2; 3308 SmallVector<int, 8> Mask; 3309 for (unsigned i = 0; i != Half; ++i) { 3310 Mask.push_back(i + Half); 3311 Mask.push_back(i + NumElems + Half); 3312 } 3313 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3314} 3315 3316/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3317static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3318 bool HasSSE2) { 3319 if (SV->getValueType(0).getVectorNumElements() <= 4) 3320 return SDValue(SV, 0); 3321 3322 EVT PVT = MVT::v4f32; 3323 EVT VT = SV->getValueType(0); 3324 DebugLoc dl = SV->getDebugLoc(); 3325 SDValue V1 = SV->getOperand(0); 3326 int NumElems = VT.getVectorNumElements(); 3327 int EltNo = SV->getSplatIndex(); 3328 3329 // unpack elements to the correct location 3330 while (NumElems > 4) { 3331 if (EltNo < NumElems/2) { 3332 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3333 } else { 3334 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3335 EltNo -= NumElems/2; 3336 } 3337 NumElems >>= 1; 3338 } 3339 3340 // Perform the splat. 3341 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3342 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3343 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3344 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3345} 3346 3347/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3348/// vector of zero or undef vector. This produces a shuffle where the low 3349/// element of V2 is swizzled into the zero/undef vector, landing at element 3350/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3351static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3352 bool isZero, bool HasSSE2, 3353 SelectionDAG &DAG) { 3354 EVT VT = V2.getValueType(); 3355 SDValue V1 = isZero 3356 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3357 unsigned NumElems = VT.getVectorNumElements(); 3358 SmallVector<int, 16> MaskVec; 3359 for (unsigned i = 0; i != NumElems; ++i) 3360 // If this is the insertion idx, put the low elt of V2 here. 3361 MaskVec.push_back(i == Idx ? NumElems : i); 3362 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3363} 3364 3365/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3366/// a shuffle that is zero. 3367static 3368unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3369 bool Low, SelectionDAG &DAG) { 3370 unsigned NumZeros = 0; 3371 for (int i = 0; i < NumElems; ++i) { 3372 unsigned Index = Low ? i : NumElems-i-1; 3373 int Idx = SVOp->getMaskElt(Index); 3374 if (Idx < 0) { 3375 ++NumZeros; 3376 continue; 3377 } 3378 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3379 if (Elt.getNode() && X86::isZeroNode(Elt)) 3380 ++NumZeros; 3381 else 3382 break; 3383 } 3384 return NumZeros; 3385} 3386 3387/// isVectorShift - Returns true if the shuffle can be implemented as a 3388/// logical left or right shift of a vector. 3389/// FIXME: split into pslldqi, psrldqi, palignr variants. 3390static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3391 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3392 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3393 3394 isLeft = true; 3395 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3396 if (!NumZeros) { 3397 isLeft = false; 3398 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3399 if (!NumZeros) 3400 return false; 3401 } 3402 bool SeenV1 = false; 3403 bool SeenV2 = false; 3404 for (int i = NumZeros; i < NumElems; ++i) { 3405 int Val = isLeft ? (i - NumZeros) : i; 3406 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3407 if (Idx < 0) 3408 continue; 3409 if (Idx < NumElems) 3410 SeenV1 = true; 3411 else { 3412 Idx -= NumElems; 3413 SeenV2 = true; 3414 } 3415 if (Idx != Val) 3416 return false; 3417 } 3418 if (SeenV1 && SeenV2) 3419 return false; 3420 3421 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3422 ShAmt = NumZeros; 3423 return true; 3424} 3425 3426 3427/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3428/// 3429static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3430 unsigned NumNonZero, unsigned NumZero, 3431 SelectionDAG &DAG, TargetLowering &TLI) { 3432 if (NumNonZero > 8) 3433 return SDValue(); 3434 3435 DebugLoc dl = Op.getDebugLoc(); 3436 SDValue V(0, 0); 3437 bool First = true; 3438 for (unsigned i = 0; i < 16; ++i) { 3439 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3440 if (ThisIsNonZero && First) { 3441 if (NumZero) 3442 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3443 else 3444 V = DAG.getUNDEF(MVT::v8i16); 3445 First = false; 3446 } 3447 3448 if ((i & 1) != 0) { 3449 SDValue ThisElt(0, 0), LastElt(0, 0); 3450 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3451 if (LastIsNonZero) { 3452 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3453 MVT::i16, Op.getOperand(i-1)); 3454 } 3455 if (ThisIsNonZero) { 3456 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3457 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3458 ThisElt, DAG.getConstant(8, MVT::i8)); 3459 if (LastIsNonZero) 3460 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3461 } else 3462 ThisElt = LastElt; 3463 3464 if (ThisElt.getNode()) 3465 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3466 DAG.getIntPtrConstant(i/2)); 3467 } 3468 } 3469 3470 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3471} 3472 3473/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3474/// 3475static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3476 unsigned NumNonZero, unsigned NumZero, 3477 SelectionDAG &DAG, TargetLowering &TLI) { 3478 if (NumNonZero > 4) 3479 return SDValue(); 3480 3481 DebugLoc dl = Op.getDebugLoc(); 3482 SDValue V(0, 0); 3483 bool First = true; 3484 for (unsigned i = 0; i < 8; ++i) { 3485 bool isNonZero = (NonZeros & (1 << i)) != 0; 3486 if (isNonZero) { 3487 if (First) { 3488 if (NumZero) 3489 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3490 else 3491 V = DAG.getUNDEF(MVT::v8i16); 3492 First = false; 3493 } 3494 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3495 MVT::v8i16, V, Op.getOperand(i), 3496 DAG.getIntPtrConstant(i)); 3497 } 3498 } 3499 3500 return V; 3501} 3502 3503/// getVShift - Return a vector logical shift node. 3504/// 3505static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3506 unsigned NumBits, SelectionDAG &DAG, 3507 const TargetLowering &TLI, DebugLoc dl) { 3508 bool isMMX = VT.getSizeInBits() == 64; 3509 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3510 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3511 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3512 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3513 DAG.getNode(Opc, dl, ShVT, SrcOp, 3514 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3515} 3516 3517SDValue 3518X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3519 SelectionDAG &DAG) { 3520 3521 // Check if the scalar load can be widened into a vector load. And if 3522 // the address is "base + cst" see if the cst can be "absorbed" into 3523 // the shuffle mask. 3524 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3525 SDValue Ptr = LD->getBasePtr(); 3526 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3527 return SDValue(); 3528 EVT PVT = LD->getValueType(0); 3529 if (PVT != MVT::i32 && PVT != MVT::f32) 3530 return SDValue(); 3531 3532 int FI = -1; 3533 int64_t Offset = 0; 3534 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3535 FI = FINode->getIndex(); 3536 Offset = 0; 3537 } else if (Ptr.getOpcode() == ISD::ADD && 3538 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3539 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3540 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3541 Offset = Ptr.getConstantOperandVal(1); 3542 Ptr = Ptr.getOperand(0); 3543 } else { 3544 return SDValue(); 3545 } 3546 3547 SDValue Chain = LD->getChain(); 3548 // Make sure the stack object alignment is at least 16. 3549 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3550 if (DAG.InferPtrAlignment(Ptr) < 16) { 3551 if (MFI->isFixedObjectIndex(FI)) { 3552 // Can't change the alignment. FIXME: It's possible to compute 3553 // the exact stack offset and reference FI + adjust offset instead. 3554 // If someone *really* cares about this. That's the way to implement it. 3555 return SDValue(); 3556 } else { 3557 MFI->setObjectAlignment(FI, 16); 3558 } 3559 } 3560 3561 // (Offset % 16) must be multiple of 4. Then address is then 3562 // Ptr + (Offset & ~15). 3563 if (Offset < 0) 3564 return SDValue(); 3565 if ((Offset % 16) & 3) 3566 return SDValue(); 3567 int64_t StartOffset = Offset & ~15; 3568 if (StartOffset) 3569 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3570 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3571 3572 int EltNo = (Offset - StartOffset) >> 2; 3573 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3574 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3575 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3576 false, false, 0); 3577 // Canonicalize it to a v4i32 shuffle. 3578 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3579 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3580 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3581 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3582 } 3583 3584 return SDValue(); 3585} 3586 3587SDValue 3588X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3589 DebugLoc dl = Op.getDebugLoc(); 3590 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3591 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3592 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3593 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3594 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3595 // eliminated on x86-32 hosts. 3596 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3597 return Op; 3598 3599 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3600 return getOnesVector(Op.getValueType(), DAG, dl); 3601 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3602 } 3603 3604 EVT VT = Op.getValueType(); 3605 EVT ExtVT = VT.getVectorElementType(); 3606 unsigned EVTBits = ExtVT.getSizeInBits(); 3607 3608 unsigned NumElems = Op.getNumOperands(); 3609 unsigned NumZero = 0; 3610 unsigned NumNonZero = 0; 3611 unsigned NonZeros = 0; 3612 bool IsAllConstants = true; 3613 SmallSet<SDValue, 8> Values; 3614 for (unsigned i = 0; i < NumElems; ++i) { 3615 SDValue Elt = Op.getOperand(i); 3616 if (Elt.getOpcode() == ISD::UNDEF) 3617 continue; 3618 Values.insert(Elt); 3619 if (Elt.getOpcode() != ISD::Constant && 3620 Elt.getOpcode() != ISD::ConstantFP) 3621 IsAllConstants = false; 3622 if (X86::isZeroNode(Elt)) 3623 NumZero++; 3624 else { 3625 NonZeros |= (1 << i); 3626 NumNonZero++; 3627 } 3628 } 3629 3630 if (NumNonZero == 0) { 3631 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3632 return DAG.getUNDEF(VT); 3633 } 3634 3635 // Special case for single non-zero, non-undef, element. 3636 if (NumNonZero == 1) { 3637 unsigned Idx = CountTrailingZeros_32(NonZeros); 3638 SDValue Item = Op.getOperand(Idx); 3639 3640 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3641 // the value are obviously zero, truncate the value to i32 and do the 3642 // insertion that way. Only do this if the value is non-constant or if the 3643 // value is a constant being inserted into element 0. It is cheaper to do 3644 // a constant pool load than it is to do a movd + shuffle. 3645 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3646 (!IsAllConstants || Idx == 0)) { 3647 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3648 // Handle MMX and SSE both. 3649 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3650 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3651 3652 // Truncate the value (which may itself be a constant) to i32, and 3653 // convert it to a vector with movd (S2V+shuffle to zero extend). 3654 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3655 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3656 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3657 Subtarget->hasSSE2(), DAG); 3658 3659 // Now we have our 32-bit value zero extended in the low element of 3660 // a vector. If Idx != 0, swizzle it into place. 3661 if (Idx != 0) { 3662 SmallVector<int, 4> Mask; 3663 Mask.push_back(Idx); 3664 for (unsigned i = 1; i != VecElts; ++i) 3665 Mask.push_back(i); 3666 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3667 DAG.getUNDEF(Item.getValueType()), 3668 &Mask[0]); 3669 } 3670 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3671 } 3672 } 3673 3674 // If we have a constant or non-constant insertion into the low element of 3675 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3676 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3677 // depending on what the source datatype is. 3678 if (Idx == 0) { 3679 if (NumZero == 0) { 3680 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3681 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3682 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3683 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3684 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3685 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3686 DAG); 3687 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3688 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3689 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3690 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3691 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3692 Subtarget->hasSSE2(), DAG); 3693 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3694 } 3695 } 3696 3697 // Is it a vector logical left shift? 3698 if (NumElems == 2 && Idx == 1 && 3699 X86::isZeroNode(Op.getOperand(0)) && 3700 !X86::isZeroNode(Op.getOperand(1))) { 3701 unsigned NumBits = VT.getSizeInBits(); 3702 return getVShift(true, VT, 3703 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3704 VT, Op.getOperand(1)), 3705 NumBits/2, DAG, *this, dl); 3706 } 3707 3708 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3709 return SDValue(); 3710 3711 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3712 // is a non-constant being inserted into an element other than the low one, 3713 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3714 // movd/movss) to move this into the low element, then shuffle it into 3715 // place. 3716 if (EVTBits == 32) { 3717 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3718 3719 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3720 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3721 Subtarget->hasSSE2(), DAG); 3722 SmallVector<int, 8> MaskVec; 3723 for (unsigned i = 0; i < NumElems; i++) 3724 MaskVec.push_back(i == Idx ? 0 : 1); 3725 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3726 } 3727 } 3728 3729 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3730 if (Values.size() == 1) { 3731 if (EVTBits == 32) { 3732 // Instead of a shuffle like this: 3733 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3734 // Check if it's possible to issue this instead. 3735 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3736 unsigned Idx = CountTrailingZeros_32(NonZeros); 3737 SDValue Item = Op.getOperand(Idx); 3738 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3739 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3740 } 3741 return SDValue(); 3742 } 3743 3744 // A vector full of immediates; various special cases are already 3745 // handled, so this is best done with a single constant-pool load. 3746 if (IsAllConstants) 3747 return SDValue(); 3748 3749 // Let legalizer expand 2-wide build_vectors. 3750 if (EVTBits == 64) { 3751 if (NumNonZero == 1) { 3752 // One half is zero or undef. 3753 unsigned Idx = CountTrailingZeros_32(NonZeros); 3754 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3755 Op.getOperand(Idx)); 3756 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3757 Subtarget->hasSSE2(), DAG); 3758 } 3759 return SDValue(); 3760 } 3761 3762 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3763 if (EVTBits == 8 && NumElems == 16) { 3764 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3765 *this); 3766 if (V.getNode()) return V; 3767 } 3768 3769 if (EVTBits == 16 && NumElems == 8) { 3770 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3771 *this); 3772 if (V.getNode()) return V; 3773 } 3774 3775 // If element VT is == 32 bits, turn it into a number of shuffles. 3776 SmallVector<SDValue, 8> V; 3777 V.resize(NumElems); 3778 if (NumElems == 4 && NumZero > 0) { 3779 for (unsigned i = 0; i < 4; ++i) { 3780 bool isZero = !(NonZeros & (1 << i)); 3781 if (isZero) 3782 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3783 else 3784 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3785 } 3786 3787 for (unsigned i = 0; i < 2; ++i) { 3788 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3789 default: break; 3790 case 0: 3791 V[i] = V[i*2]; // Must be a zero vector. 3792 break; 3793 case 1: 3794 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3795 break; 3796 case 2: 3797 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3798 break; 3799 case 3: 3800 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3801 break; 3802 } 3803 } 3804 3805 SmallVector<int, 8> MaskVec; 3806 bool Reverse = (NonZeros & 0x3) == 2; 3807 for (unsigned i = 0; i < 2; ++i) 3808 MaskVec.push_back(Reverse ? 1-i : i); 3809 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3810 for (unsigned i = 0; i < 2; ++i) 3811 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3812 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3813 } 3814 3815 if (Values.size() > 2) { 3816 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3817 // values to be inserted is equal to the number of elements, in which case 3818 // use the unpack code below in the hopes of matching the consecutive elts 3819 // load merge pattern for shuffles. 3820 // FIXME: We could probably just check that here directly. 3821 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3822 getSubtarget()->hasSSE41()) { 3823 V[0] = DAG.getUNDEF(VT); 3824 for (unsigned i = 0; i < NumElems; ++i) 3825 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3826 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3827 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3828 return V[0]; 3829 } 3830 // Expand into a number of unpckl*. 3831 // e.g. for v4f32 3832 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3833 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3834 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3835 for (unsigned i = 0; i < NumElems; ++i) 3836 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3837 NumElems >>= 1; 3838 while (NumElems != 0) { 3839 for (unsigned i = 0; i < NumElems; ++i) 3840 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3841 NumElems >>= 1; 3842 } 3843 return V[0]; 3844 } 3845 3846 return SDValue(); 3847} 3848 3849SDValue 3850X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3851 // We support concatenate two MMX registers and place them in a MMX 3852 // register. This is better than doing a stack convert. 3853 DebugLoc dl = Op.getDebugLoc(); 3854 EVT ResVT = Op.getValueType(); 3855 assert(Op.getNumOperands() == 2); 3856 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 3857 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 3858 int Mask[2]; 3859 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 3860 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3861 InVec = Op.getOperand(1); 3862 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3863 unsigned NumElts = ResVT.getVectorNumElements(); 3864 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3865 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 3866 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 3867 } else { 3868 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 3869 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3870 Mask[0] = 0; Mask[1] = 2; 3871 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 3872 } 3873 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3874} 3875 3876// v8i16 shuffles - Prefer shuffles in the following order: 3877// 1. [all] pshuflw, pshufhw, optional move 3878// 2. [ssse3] 1 x pshufb 3879// 3. [ssse3] 2 x pshufb + 1 x por 3880// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3881static 3882SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3883 SelectionDAG &DAG, X86TargetLowering &TLI) { 3884 SDValue V1 = SVOp->getOperand(0); 3885 SDValue V2 = SVOp->getOperand(1); 3886 DebugLoc dl = SVOp->getDebugLoc(); 3887 SmallVector<int, 8> MaskVals; 3888 3889 // Determine if more than 1 of the words in each of the low and high quadwords 3890 // of the result come from the same quadword of one of the two inputs. Undef 3891 // mask values count as coming from any quadword, for better codegen. 3892 SmallVector<unsigned, 4> LoQuad(4); 3893 SmallVector<unsigned, 4> HiQuad(4); 3894 BitVector InputQuads(4); 3895 for (unsigned i = 0; i < 8; ++i) { 3896 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3897 int EltIdx = SVOp->getMaskElt(i); 3898 MaskVals.push_back(EltIdx); 3899 if (EltIdx < 0) { 3900 ++Quad[0]; 3901 ++Quad[1]; 3902 ++Quad[2]; 3903 ++Quad[3]; 3904 continue; 3905 } 3906 ++Quad[EltIdx / 4]; 3907 InputQuads.set(EltIdx / 4); 3908 } 3909 3910 int BestLoQuad = -1; 3911 unsigned MaxQuad = 1; 3912 for (unsigned i = 0; i < 4; ++i) { 3913 if (LoQuad[i] > MaxQuad) { 3914 BestLoQuad = i; 3915 MaxQuad = LoQuad[i]; 3916 } 3917 } 3918 3919 int BestHiQuad = -1; 3920 MaxQuad = 1; 3921 for (unsigned i = 0; i < 4; ++i) { 3922 if (HiQuad[i] > MaxQuad) { 3923 BestHiQuad = i; 3924 MaxQuad = HiQuad[i]; 3925 } 3926 } 3927 3928 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3929 // of the two input vectors, shuffle them into one input vector so only a 3930 // single pshufb instruction is necessary. If There are more than 2 input 3931 // quads, disable the next transformation since it does not help SSSE3. 3932 bool V1Used = InputQuads[0] || InputQuads[1]; 3933 bool V2Used = InputQuads[2] || InputQuads[3]; 3934 if (TLI.getSubtarget()->hasSSSE3()) { 3935 if (InputQuads.count() == 2 && V1Used && V2Used) { 3936 BestLoQuad = InputQuads.find_first(); 3937 BestHiQuad = InputQuads.find_next(BestLoQuad); 3938 } 3939 if (InputQuads.count() > 2) { 3940 BestLoQuad = -1; 3941 BestHiQuad = -1; 3942 } 3943 } 3944 3945 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3946 // the shuffle mask. If a quad is scored as -1, that means that it contains 3947 // words from all 4 input quadwords. 3948 SDValue NewV; 3949 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3950 SmallVector<int, 8> MaskV; 3951 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3952 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3953 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3954 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3955 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3956 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3957 3958 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3959 // source words for the shuffle, to aid later transformations. 3960 bool AllWordsInNewV = true; 3961 bool InOrder[2] = { true, true }; 3962 for (unsigned i = 0; i != 8; ++i) { 3963 int idx = MaskVals[i]; 3964 if (idx != (int)i) 3965 InOrder[i/4] = false; 3966 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3967 continue; 3968 AllWordsInNewV = false; 3969 break; 3970 } 3971 3972 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3973 if (AllWordsInNewV) { 3974 for (int i = 0; i != 8; ++i) { 3975 int idx = MaskVals[i]; 3976 if (idx < 0) 3977 continue; 3978 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3979 if ((idx != i) && idx < 4) 3980 pshufhw = false; 3981 if ((idx != i) && idx > 3) 3982 pshuflw = false; 3983 } 3984 V1 = NewV; 3985 V2Used = false; 3986 BestLoQuad = 0; 3987 BestHiQuad = 1; 3988 } 3989 3990 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3991 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3992 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 3993 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 3994 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 3995 } 3996 } 3997 3998 // If we have SSSE3, and all words of the result are from 1 input vector, 3999 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4000 // is present, fall back to case 4. 4001 if (TLI.getSubtarget()->hasSSSE3()) { 4002 SmallVector<SDValue,16> pshufbMask; 4003 4004 // If we have elements from both input vectors, set the high bit of the 4005 // shuffle mask element to zero out elements that come from V2 in the V1 4006 // mask, and elements that come from V1 in the V2 mask, so that the two 4007 // results can be OR'd together. 4008 bool TwoInputs = V1Used && V2Used; 4009 for (unsigned i = 0; i != 8; ++i) { 4010 int EltIdx = MaskVals[i] * 2; 4011 if (TwoInputs && (EltIdx >= 16)) { 4012 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4013 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4014 continue; 4015 } 4016 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4017 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4018 } 4019 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4020 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4021 DAG.getNode(ISD::BUILD_VECTOR, dl, 4022 MVT::v16i8, &pshufbMask[0], 16)); 4023 if (!TwoInputs) 4024 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4025 4026 // Calculate the shuffle mask for the second input, shuffle it, and 4027 // OR it with the first shuffled input. 4028 pshufbMask.clear(); 4029 for (unsigned i = 0; i != 8; ++i) { 4030 int EltIdx = MaskVals[i] * 2; 4031 if (EltIdx < 16) { 4032 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4033 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4034 continue; 4035 } 4036 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4037 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4038 } 4039 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4040 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4041 DAG.getNode(ISD::BUILD_VECTOR, dl, 4042 MVT::v16i8, &pshufbMask[0], 16)); 4043 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4044 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4045 } 4046 4047 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4048 // and update MaskVals with new element order. 4049 BitVector InOrder(8); 4050 if (BestLoQuad >= 0) { 4051 SmallVector<int, 8> MaskV; 4052 for (int i = 0; i != 4; ++i) { 4053 int idx = MaskVals[i]; 4054 if (idx < 0) { 4055 MaskV.push_back(-1); 4056 InOrder.set(i); 4057 } else if ((idx / 4) == BestLoQuad) { 4058 MaskV.push_back(idx & 3); 4059 InOrder.set(i); 4060 } else { 4061 MaskV.push_back(-1); 4062 } 4063 } 4064 for (unsigned i = 4; i != 8; ++i) 4065 MaskV.push_back(i); 4066 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4067 &MaskV[0]); 4068 } 4069 4070 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4071 // and update MaskVals with the new element order. 4072 if (BestHiQuad >= 0) { 4073 SmallVector<int, 8> MaskV; 4074 for (unsigned i = 0; i != 4; ++i) 4075 MaskV.push_back(i); 4076 for (unsigned i = 4; i != 8; ++i) { 4077 int idx = MaskVals[i]; 4078 if (idx < 0) { 4079 MaskV.push_back(-1); 4080 InOrder.set(i); 4081 } else if ((idx / 4) == BestHiQuad) { 4082 MaskV.push_back((idx & 3) + 4); 4083 InOrder.set(i); 4084 } else { 4085 MaskV.push_back(-1); 4086 } 4087 } 4088 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4089 &MaskV[0]); 4090 } 4091 4092 // In case BestHi & BestLo were both -1, which means each quadword has a word 4093 // from each of the four input quadwords, calculate the InOrder bitvector now 4094 // before falling through to the insert/extract cleanup. 4095 if (BestLoQuad == -1 && BestHiQuad == -1) { 4096 NewV = V1; 4097 for (int i = 0; i != 8; ++i) 4098 if (MaskVals[i] < 0 || MaskVals[i] == i) 4099 InOrder.set(i); 4100 } 4101 4102 // The other elements are put in the right place using pextrw and pinsrw. 4103 for (unsigned i = 0; i != 8; ++i) { 4104 if (InOrder[i]) 4105 continue; 4106 int EltIdx = MaskVals[i]; 4107 if (EltIdx < 0) 4108 continue; 4109 SDValue ExtOp = (EltIdx < 8) 4110 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4111 DAG.getIntPtrConstant(EltIdx)) 4112 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4113 DAG.getIntPtrConstant(EltIdx - 8)); 4114 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4115 DAG.getIntPtrConstant(i)); 4116 } 4117 return NewV; 4118} 4119 4120// v16i8 shuffles - Prefer shuffles in the following order: 4121// 1. [ssse3] 1 x pshufb 4122// 2. [ssse3] 2 x pshufb + 1 x por 4123// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4124static 4125SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4126 SelectionDAG &DAG, X86TargetLowering &TLI) { 4127 SDValue V1 = SVOp->getOperand(0); 4128 SDValue V2 = SVOp->getOperand(1); 4129 DebugLoc dl = SVOp->getDebugLoc(); 4130 SmallVector<int, 16> MaskVals; 4131 SVOp->getMask(MaskVals); 4132 4133 // If we have SSSE3, case 1 is generated when all result bytes come from 4134 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4135 // present, fall back to case 3. 4136 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4137 bool V1Only = true; 4138 bool V2Only = true; 4139 for (unsigned i = 0; i < 16; ++i) { 4140 int EltIdx = MaskVals[i]; 4141 if (EltIdx < 0) 4142 continue; 4143 if (EltIdx < 16) 4144 V2Only = false; 4145 else 4146 V1Only = false; 4147 } 4148 4149 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4150 if (TLI.getSubtarget()->hasSSSE3()) { 4151 SmallVector<SDValue,16> pshufbMask; 4152 4153 // If all result elements are from one input vector, then only translate 4154 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4155 // 4156 // Otherwise, we have elements from both input vectors, and must zero out 4157 // elements that come from V2 in the first mask, and V1 in the second mask 4158 // so that we can OR them together. 4159 bool TwoInputs = !(V1Only || V2Only); 4160 for (unsigned i = 0; i != 16; ++i) { 4161 int EltIdx = MaskVals[i]; 4162 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4163 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4164 continue; 4165 } 4166 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4167 } 4168 // If all the elements are from V2, assign it to V1 and return after 4169 // building the first pshufb. 4170 if (V2Only) 4171 V1 = V2; 4172 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4173 DAG.getNode(ISD::BUILD_VECTOR, dl, 4174 MVT::v16i8, &pshufbMask[0], 16)); 4175 if (!TwoInputs) 4176 return V1; 4177 4178 // Calculate the shuffle mask for the second input, shuffle it, and 4179 // OR it with the first shuffled input. 4180 pshufbMask.clear(); 4181 for (unsigned i = 0; i != 16; ++i) { 4182 int EltIdx = MaskVals[i]; 4183 if (EltIdx < 16) { 4184 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4185 continue; 4186 } 4187 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4188 } 4189 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4190 DAG.getNode(ISD::BUILD_VECTOR, dl, 4191 MVT::v16i8, &pshufbMask[0], 16)); 4192 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4193 } 4194 4195 // No SSSE3 - Calculate in place words and then fix all out of place words 4196 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4197 // the 16 different words that comprise the two doublequadword input vectors. 4198 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4199 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4200 SDValue NewV = V2Only ? V2 : V1; 4201 for (int i = 0; i != 8; ++i) { 4202 int Elt0 = MaskVals[i*2]; 4203 int Elt1 = MaskVals[i*2+1]; 4204 4205 // This word of the result is all undef, skip it. 4206 if (Elt0 < 0 && Elt1 < 0) 4207 continue; 4208 4209 // This word of the result is already in the correct place, skip it. 4210 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4211 continue; 4212 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4213 continue; 4214 4215 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4216 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4217 SDValue InsElt; 4218 4219 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4220 // using a single extract together, load it and store it. 4221 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4222 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4223 DAG.getIntPtrConstant(Elt1 / 2)); 4224 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4225 DAG.getIntPtrConstant(i)); 4226 continue; 4227 } 4228 4229 // If Elt1 is defined, extract it from the appropriate source. If the 4230 // source byte is not also odd, shift the extracted word left 8 bits 4231 // otherwise clear the bottom 8 bits if we need to do an or. 4232 if (Elt1 >= 0) { 4233 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4234 DAG.getIntPtrConstant(Elt1 / 2)); 4235 if ((Elt1 & 1) == 0) 4236 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4237 DAG.getConstant(8, TLI.getShiftAmountTy())); 4238 else if (Elt0 >= 0) 4239 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4240 DAG.getConstant(0xFF00, MVT::i16)); 4241 } 4242 // If Elt0 is defined, extract it from the appropriate source. If the 4243 // source byte is not also even, shift the extracted word right 8 bits. If 4244 // Elt1 was also defined, OR the extracted values together before 4245 // inserting them in the result. 4246 if (Elt0 >= 0) { 4247 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4248 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4249 if ((Elt0 & 1) != 0) 4250 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4251 DAG.getConstant(8, TLI.getShiftAmountTy())); 4252 else if (Elt1 >= 0) 4253 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4254 DAG.getConstant(0x00FF, MVT::i16)); 4255 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4256 : InsElt0; 4257 } 4258 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4259 DAG.getIntPtrConstant(i)); 4260 } 4261 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4262} 4263 4264/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4265/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 4266/// done when every pair / quad of shuffle mask elements point to elements in 4267/// the right sequence. e.g. 4268/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4269static 4270SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4271 SelectionDAG &DAG, 4272 TargetLowering &TLI, DebugLoc dl) { 4273 EVT VT = SVOp->getValueType(0); 4274 SDValue V1 = SVOp->getOperand(0); 4275 SDValue V2 = SVOp->getOperand(1); 4276 unsigned NumElems = VT.getVectorNumElements(); 4277 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4278 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4279 EVT MaskEltVT = MaskVT.getVectorElementType(); 4280 EVT NewVT = MaskVT; 4281 switch (VT.getSimpleVT().SimpleTy) { 4282 default: assert(false && "Unexpected!"); 4283 case MVT::v4f32: NewVT = MVT::v2f64; break; 4284 case MVT::v4i32: NewVT = MVT::v2i64; break; 4285 case MVT::v8i16: NewVT = MVT::v4i32; break; 4286 case MVT::v16i8: NewVT = MVT::v4i32; break; 4287 } 4288 4289 if (NewWidth == 2) { 4290 if (VT.isInteger()) 4291 NewVT = MVT::v2i64; 4292 else 4293 NewVT = MVT::v2f64; 4294 } 4295 int Scale = NumElems / NewWidth; 4296 SmallVector<int, 8> MaskVec; 4297 for (unsigned i = 0; i < NumElems; i += Scale) { 4298 int StartIdx = -1; 4299 for (int j = 0; j < Scale; ++j) { 4300 int EltIdx = SVOp->getMaskElt(i+j); 4301 if (EltIdx < 0) 4302 continue; 4303 if (StartIdx == -1) 4304 StartIdx = EltIdx - (EltIdx % Scale); 4305 if (EltIdx != StartIdx + j) 4306 return SDValue(); 4307 } 4308 if (StartIdx == -1) 4309 MaskVec.push_back(-1); 4310 else 4311 MaskVec.push_back(StartIdx / Scale); 4312 } 4313 4314 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4315 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4316 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4317} 4318 4319/// getVZextMovL - Return a zero-extending vector move low node. 4320/// 4321static SDValue getVZextMovL(EVT VT, EVT OpVT, 4322 SDValue SrcOp, SelectionDAG &DAG, 4323 const X86Subtarget *Subtarget, DebugLoc dl) { 4324 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4325 LoadSDNode *LD = NULL; 4326 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4327 LD = dyn_cast<LoadSDNode>(SrcOp); 4328 if (!LD) { 4329 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4330 // instead. 4331 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4332 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4333 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4334 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4335 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4336 // PR2108 4337 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4338 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4339 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4340 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4341 OpVT, 4342 SrcOp.getOperand(0) 4343 .getOperand(0)))); 4344 } 4345 } 4346 } 4347 4348 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4349 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4350 DAG.getNode(ISD::BIT_CONVERT, dl, 4351 OpVT, SrcOp))); 4352} 4353 4354/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4355/// shuffles. 4356static SDValue 4357LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4358 SDValue V1 = SVOp->getOperand(0); 4359 SDValue V2 = SVOp->getOperand(1); 4360 DebugLoc dl = SVOp->getDebugLoc(); 4361 EVT VT = SVOp->getValueType(0); 4362 4363 SmallVector<std::pair<int, int>, 8> Locs; 4364 Locs.resize(4); 4365 SmallVector<int, 8> Mask1(4U, -1); 4366 SmallVector<int, 8> PermMask; 4367 SVOp->getMask(PermMask); 4368 4369 unsigned NumHi = 0; 4370 unsigned NumLo = 0; 4371 for (unsigned i = 0; i != 4; ++i) { 4372 int Idx = PermMask[i]; 4373 if (Idx < 0) { 4374 Locs[i] = std::make_pair(-1, -1); 4375 } else { 4376 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4377 if (Idx < 4) { 4378 Locs[i] = std::make_pair(0, NumLo); 4379 Mask1[NumLo] = Idx; 4380 NumLo++; 4381 } else { 4382 Locs[i] = std::make_pair(1, NumHi); 4383 if (2+NumHi < 4) 4384 Mask1[2+NumHi] = Idx; 4385 NumHi++; 4386 } 4387 } 4388 } 4389 4390 if (NumLo <= 2 && NumHi <= 2) { 4391 // If no more than two elements come from either vector. This can be 4392 // implemented with two shuffles. First shuffle gather the elements. 4393 // The second shuffle, which takes the first shuffle as both of its 4394 // vector operands, put the elements into the right order. 4395 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4396 4397 SmallVector<int, 8> Mask2(4U, -1); 4398 4399 for (unsigned i = 0; i != 4; ++i) { 4400 if (Locs[i].first == -1) 4401 continue; 4402 else { 4403 unsigned Idx = (i < 2) ? 0 : 4; 4404 Idx += Locs[i].first * 2 + Locs[i].second; 4405 Mask2[i] = Idx; 4406 } 4407 } 4408 4409 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4410 } else if (NumLo == 3 || NumHi == 3) { 4411 // Otherwise, we must have three elements from one vector, call it X, and 4412 // one element from the other, call it Y. First, use a shufps to build an 4413 // intermediate vector with the one element from Y and the element from X 4414 // that will be in the same half in the final destination (the indexes don't 4415 // matter). Then, use a shufps to build the final vector, taking the half 4416 // containing the element from Y from the intermediate, and the other half 4417 // from X. 4418 if (NumHi == 3) { 4419 // Normalize it so the 3 elements come from V1. 4420 CommuteVectorShuffleMask(PermMask, VT); 4421 std::swap(V1, V2); 4422 } 4423 4424 // Find the element from V2. 4425 unsigned HiIndex; 4426 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4427 int Val = PermMask[HiIndex]; 4428 if (Val < 0) 4429 continue; 4430 if (Val >= 4) 4431 break; 4432 } 4433 4434 Mask1[0] = PermMask[HiIndex]; 4435 Mask1[1] = -1; 4436 Mask1[2] = PermMask[HiIndex^1]; 4437 Mask1[3] = -1; 4438 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4439 4440 if (HiIndex >= 2) { 4441 Mask1[0] = PermMask[0]; 4442 Mask1[1] = PermMask[1]; 4443 Mask1[2] = HiIndex & 1 ? 6 : 4; 4444 Mask1[3] = HiIndex & 1 ? 4 : 6; 4445 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4446 } else { 4447 Mask1[0] = HiIndex & 1 ? 2 : 0; 4448 Mask1[1] = HiIndex & 1 ? 0 : 2; 4449 Mask1[2] = PermMask[2]; 4450 Mask1[3] = PermMask[3]; 4451 if (Mask1[2] >= 0) 4452 Mask1[2] += 4; 4453 if (Mask1[3] >= 0) 4454 Mask1[3] += 4; 4455 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4456 } 4457 } 4458 4459 // Break it into (shuffle shuffle_hi, shuffle_lo). 4460 Locs.clear(); 4461 SmallVector<int,8> LoMask(4U, -1); 4462 SmallVector<int,8> HiMask(4U, -1); 4463 4464 SmallVector<int,8> *MaskPtr = &LoMask; 4465 unsigned MaskIdx = 0; 4466 unsigned LoIdx = 0; 4467 unsigned HiIdx = 2; 4468 for (unsigned i = 0; i != 4; ++i) { 4469 if (i == 2) { 4470 MaskPtr = &HiMask; 4471 MaskIdx = 1; 4472 LoIdx = 0; 4473 HiIdx = 2; 4474 } 4475 int Idx = PermMask[i]; 4476 if (Idx < 0) { 4477 Locs[i] = std::make_pair(-1, -1); 4478 } else if (Idx < 4) { 4479 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4480 (*MaskPtr)[LoIdx] = Idx; 4481 LoIdx++; 4482 } else { 4483 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4484 (*MaskPtr)[HiIdx] = Idx; 4485 HiIdx++; 4486 } 4487 } 4488 4489 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4490 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4491 SmallVector<int, 8> MaskOps; 4492 for (unsigned i = 0; i != 4; ++i) { 4493 if (Locs[i].first == -1) { 4494 MaskOps.push_back(-1); 4495 } else { 4496 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4497 MaskOps.push_back(Idx); 4498 } 4499 } 4500 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4501} 4502 4503SDValue 4504X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4506 SDValue V1 = Op.getOperand(0); 4507 SDValue V2 = Op.getOperand(1); 4508 EVT VT = Op.getValueType(); 4509 DebugLoc dl = Op.getDebugLoc(); 4510 unsigned NumElems = VT.getVectorNumElements(); 4511 bool isMMX = VT.getSizeInBits() == 64; 4512 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4513 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4514 bool V1IsSplat = false; 4515 bool V2IsSplat = false; 4516 4517 if (isZeroShuffle(SVOp)) 4518 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4519 4520 // Promote splats to v4f32. 4521 if (SVOp->isSplat()) { 4522 if (isMMX || NumElems < 4) 4523 return Op; 4524 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4525 } 4526 4527 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4528 // do it! 4529 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4530 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4531 if (NewOp.getNode()) 4532 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4533 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4534 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4535 // FIXME: Figure out a cleaner way to do this. 4536 // Try to make use of movq to zero out the top part. 4537 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4538 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4539 if (NewOp.getNode()) { 4540 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4541 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4542 DAG, Subtarget, dl); 4543 } 4544 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4545 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4546 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4547 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4548 DAG, Subtarget, dl); 4549 } 4550 } 4551 4552 if (X86::isPSHUFDMask(SVOp)) 4553 return Op; 4554 4555 // Check if this can be converted into a logical shift. 4556 bool isLeft = false; 4557 unsigned ShAmt = 0; 4558 SDValue ShVal; 4559 bool isShift = getSubtarget()->hasSSE2() && 4560 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4561 if (isShift && ShVal.hasOneUse()) { 4562 // If the shifted value has multiple uses, it may be cheaper to use 4563 // v_set0 + movlhps or movhlps, etc. 4564 EVT EltVT = VT.getVectorElementType(); 4565 ShAmt *= EltVT.getSizeInBits(); 4566 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4567 } 4568 4569 if (X86::isMOVLMask(SVOp)) { 4570 if (V1IsUndef) 4571 return V2; 4572 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4573 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4574 if (!isMMX) 4575 return Op; 4576 } 4577 4578 // FIXME: fold these into legal mask. 4579 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4580 X86::isMOVSLDUPMask(SVOp) || 4581 X86::isMOVHLPSMask(SVOp) || 4582 X86::isMOVLHPSMask(SVOp) || 4583 X86::isMOVLPMask(SVOp))) 4584 return Op; 4585 4586 if (ShouldXformToMOVHLPS(SVOp) || 4587 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4588 return CommuteVectorShuffle(SVOp, DAG); 4589 4590 if (isShift) { 4591 // No better options. Use a vshl / vsrl. 4592 EVT EltVT = VT.getVectorElementType(); 4593 ShAmt *= EltVT.getSizeInBits(); 4594 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4595 } 4596 4597 bool Commuted = false; 4598 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4599 // 1,1,1,1 -> v8i16 though. 4600 V1IsSplat = isSplatVector(V1.getNode()); 4601 V2IsSplat = isSplatVector(V2.getNode()); 4602 4603 // Canonicalize the splat or undef, if present, to be on the RHS. 4604 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4605 Op = CommuteVectorShuffle(SVOp, DAG); 4606 SVOp = cast<ShuffleVectorSDNode>(Op); 4607 V1 = SVOp->getOperand(0); 4608 V2 = SVOp->getOperand(1); 4609 std::swap(V1IsSplat, V2IsSplat); 4610 std::swap(V1IsUndef, V2IsUndef); 4611 Commuted = true; 4612 } 4613 4614 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4615 // Shuffling low element of v1 into undef, just return v1. 4616 if (V2IsUndef) 4617 return V1; 4618 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4619 // the instruction selector will not match, so get a canonical MOVL with 4620 // swapped operands to undo the commute. 4621 return getMOVL(DAG, dl, VT, V2, V1); 4622 } 4623 4624 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4625 X86::isUNPCKH_v_undef_Mask(SVOp) || 4626 X86::isUNPCKLMask(SVOp) || 4627 X86::isUNPCKHMask(SVOp)) 4628 return Op; 4629 4630 if (V2IsSplat) { 4631 // Normalize mask so all entries that point to V2 points to its first 4632 // element then try to match unpck{h|l} again. If match, return a 4633 // new vector_shuffle with the corrected mask. 4634 SDValue NewMask = NormalizeMask(SVOp, DAG); 4635 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4636 if (NSVOp != SVOp) { 4637 if (X86::isUNPCKLMask(NSVOp, true)) { 4638 return NewMask; 4639 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4640 return NewMask; 4641 } 4642 } 4643 } 4644 4645 if (Commuted) { 4646 // Commute is back and try unpck* again. 4647 // FIXME: this seems wrong. 4648 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4649 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4650 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4651 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4652 X86::isUNPCKLMask(NewSVOp) || 4653 X86::isUNPCKHMask(NewSVOp)) 4654 return NewOp; 4655 } 4656 4657 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4658 4659 // Normalize the node to match x86 shuffle ops if needed 4660 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4661 return CommuteVectorShuffle(SVOp, DAG); 4662 4663 // Check for legal shuffle and return? 4664 SmallVector<int, 16> PermMask; 4665 SVOp->getMask(PermMask); 4666 if (isShuffleMaskLegal(PermMask, VT)) 4667 return Op; 4668 4669 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4670 if (VT == MVT::v8i16) { 4671 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4672 if (NewOp.getNode()) 4673 return NewOp; 4674 } 4675 4676 if (VT == MVT::v16i8) { 4677 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4678 if (NewOp.getNode()) 4679 return NewOp; 4680 } 4681 4682 // Handle all 4 wide cases with a number of shuffles except for MMX. 4683 if (NumElems == 4 && !isMMX) 4684 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4685 4686 return SDValue(); 4687} 4688 4689SDValue 4690X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4691 SelectionDAG &DAG) { 4692 EVT VT = Op.getValueType(); 4693 DebugLoc dl = Op.getDebugLoc(); 4694 if (VT.getSizeInBits() == 8) { 4695 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4696 Op.getOperand(0), Op.getOperand(1)); 4697 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4698 DAG.getValueType(VT)); 4699 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4700 } else if (VT.getSizeInBits() == 16) { 4701 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4702 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4703 if (Idx == 0) 4704 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4705 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4706 DAG.getNode(ISD::BIT_CONVERT, dl, 4707 MVT::v4i32, 4708 Op.getOperand(0)), 4709 Op.getOperand(1))); 4710 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4711 Op.getOperand(0), Op.getOperand(1)); 4712 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4713 DAG.getValueType(VT)); 4714 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4715 } else if (VT == MVT::f32) { 4716 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4717 // the result back to FR32 register. It's only worth matching if the 4718 // result has a single use which is a store or a bitcast to i32. And in 4719 // the case of a store, it's not worth it if the index is a constant 0, 4720 // because a MOVSSmr can be used instead, which is smaller and faster. 4721 if (!Op.hasOneUse()) 4722 return SDValue(); 4723 SDNode *User = *Op.getNode()->use_begin(); 4724 if ((User->getOpcode() != ISD::STORE || 4725 (isa<ConstantSDNode>(Op.getOperand(1)) && 4726 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4727 (User->getOpcode() != ISD::BIT_CONVERT || 4728 User->getValueType(0) != MVT::i32)) 4729 return SDValue(); 4730 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4731 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4732 Op.getOperand(0)), 4733 Op.getOperand(1)); 4734 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4735 } else if (VT == MVT::i32) { 4736 // ExtractPS works with constant index. 4737 if (isa<ConstantSDNode>(Op.getOperand(1))) 4738 return Op; 4739 } 4740 return SDValue(); 4741} 4742 4743 4744SDValue 4745X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4746 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4747 return SDValue(); 4748 4749 if (Subtarget->hasSSE41()) { 4750 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4751 if (Res.getNode()) 4752 return Res; 4753 } 4754 4755 EVT VT = Op.getValueType(); 4756 DebugLoc dl = Op.getDebugLoc(); 4757 // TODO: handle v16i8. 4758 if (VT.getSizeInBits() == 16) { 4759 SDValue Vec = Op.getOperand(0); 4760 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4761 if (Idx == 0) 4762 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4763 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4764 DAG.getNode(ISD::BIT_CONVERT, dl, 4765 MVT::v4i32, Vec), 4766 Op.getOperand(1))); 4767 // Transform it so it match pextrw which produces a 32-bit result. 4768 EVT EltVT = MVT::i32; 4769 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4770 Op.getOperand(0), Op.getOperand(1)); 4771 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4772 DAG.getValueType(VT)); 4773 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4774 } else if (VT.getSizeInBits() == 32) { 4775 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4776 if (Idx == 0) 4777 return Op; 4778 4779 // SHUFPS the element to the lowest double word, then movss. 4780 int Mask[4] = { Idx, -1, -1, -1 }; 4781 EVT VVT = Op.getOperand(0).getValueType(); 4782 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4783 DAG.getUNDEF(VVT), Mask); 4784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4785 DAG.getIntPtrConstant(0)); 4786 } else if (VT.getSizeInBits() == 64) { 4787 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4788 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4789 // to match extract_elt for f64. 4790 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4791 if (Idx == 0) 4792 return Op; 4793 4794 // UNPCKHPD the element to the lowest double word, then movsd. 4795 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4796 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4797 int Mask[2] = { 1, -1 }; 4798 EVT VVT = Op.getOperand(0).getValueType(); 4799 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4800 DAG.getUNDEF(VVT), Mask); 4801 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4802 DAG.getIntPtrConstant(0)); 4803 } 4804 4805 return SDValue(); 4806} 4807 4808SDValue 4809X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4810 EVT VT = Op.getValueType(); 4811 EVT EltVT = VT.getVectorElementType(); 4812 DebugLoc dl = Op.getDebugLoc(); 4813 4814 SDValue N0 = Op.getOperand(0); 4815 SDValue N1 = Op.getOperand(1); 4816 SDValue N2 = Op.getOperand(2); 4817 4818 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 4819 isa<ConstantSDNode>(N2)) { 4820 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4821 : X86ISD::PINSRW; 4822 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4823 // argument. 4824 if (N1.getValueType() != MVT::i32) 4825 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4826 if (N2.getValueType() != MVT::i32) 4827 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4828 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4829 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4830 // Bits [7:6] of the constant are the source select. This will always be 4831 // zero here. The DAG Combiner may combine an extract_elt index into these 4832 // bits. For example (insert (extract, 3), 2) could be matched by putting 4833 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4834 // Bits [5:4] of the constant are the destination select. This is the 4835 // value of the incoming immediate. 4836 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4837 // combine either bitwise AND or insert of float 0.0 to set these bits. 4838 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4839 // Create this as a scalar to vector.. 4840 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4841 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4842 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4843 // PINSR* works with constant index. 4844 return Op; 4845 } 4846 return SDValue(); 4847} 4848 4849SDValue 4850X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4851 EVT VT = Op.getValueType(); 4852 EVT EltVT = VT.getVectorElementType(); 4853 4854 if (Subtarget->hasSSE41()) 4855 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4856 4857 if (EltVT == MVT::i8) 4858 return SDValue(); 4859 4860 DebugLoc dl = Op.getDebugLoc(); 4861 SDValue N0 = Op.getOperand(0); 4862 SDValue N1 = Op.getOperand(1); 4863 SDValue N2 = Op.getOperand(2); 4864 4865 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4866 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4867 // as its second argument. 4868 if (N1.getValueType() != MVT::i32) 4869 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4870 if (N2.getValueType() != MVT::i32) 4871 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4872 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4873 } 4874 return SDValue(); 4875} 4876 4877SDValue 4878X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4879 DebugLoc dl = Op.getDebugLoc(); 4880 if (Op.getValueType() == MVT::v2f32) 4881 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4882 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4883 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4884 Op.getOperand(0)))); 4885 4886 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4887 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4888 4889 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4890 EVT VT = MVT::v2i32; 4891 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4892 default: break; 4893 case MVT::v16i8: 4894 case MVT::v8i16: 4895 VT = MVT::v4i32; 4896 break; 4897 } 4898 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4899 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4900} 4901 4902// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4903// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4904// one of the above mentioned nodes. It has to be wrapped because otherwise 4905// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4906// be used to form addressing mode. These wrapped nodes will be selected 4907// into MOV32ri. 4908SDValue 4909X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4910 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4911 4912 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4913 // global base reg. 4914 unsigned char OpFlag = 0; 4915 unsigned WrapperKind = X86ISD::Wrapper; 4916 CodeModel::Model M = getTargetMachine().getCodeModel(); 4917 4918 if (Subtarget->isPICStyleRIPRel() && 4919 (M == CodeModel::Small || M == CodeModel::Kernel)) 4920 WrapperKind = X86ISD::WrapperRIP; 4921 else if (Subtarget->isPICStyleGOT()) 4922 OpFlag = X86II::MO_GOTOFF; 4923 else if (Subtarget->isPICStyleStubPIC()) 4924 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4925 4926 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4927 CP->getAlignment(), 4928 CP->getOffset(), OpFlag); 4929 DebugLoc DL = CP->getDebugLoc(); 4930 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4931 // With PIC, the address is actually $g + Offset. 4932 if (OpFlag) { 4933 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4934 DAG.getNode(X86ISD::GlobalBaseReg, 4935 DebugLoc::getUnknownLoc(), getPointerTy()), 4936 Result); 4937 } 4938 4939 return Result; 4940} 4941 4942SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4943 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4944 4945 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4946 // global base reg. 4947 unsigned char OpFlag = 0; 4948 unsigned WrapperKind = X86ISD::Wrapper; 4949 CodeModel::Model M = getTargetMachine().getCodeModel(); 4950 4951 if (Subtarget->isPICStyleRIPRel() && 4952 (M == CodeModel::Small || M == CodeModel::Kernel)) 4953 WrapperKind = X86ISD::WrapperRIP; 4954 else if (Subtarget->isPICStyleGOT()) 4955 OpFlag = X86II::MO_GOTOFF; 4956 else if (Subtarget->isPICStyleStubPIC()) 4957 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4958 4959 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4960 OpFlag); 4961 DebugLoc DL = JT->getDebugLoc(); 4962 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4963 4964 // With PIC, the address is actually $g + Offset. 4965 if (OpFlag) { 4966 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4967 DAG.getNode(X86ISD::GlobalBaseReg, 4968 DebugLoc::getUnknownLoc(), getPointerTy()), 4969 Result); 4970 } 4971 4972 return Result; 4973} 4974 4975SDValue 4976X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4977 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4978 4979 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4980 // global base reg. 4981 unsigned char OpFlag = 0; 4982 unsigned WrapperKind = X86ISD::Wrapper; 4983 CodeModel::Model M = getTargetMachine().getCodeModel(); 4984 4985 if (Subtarget->isPICStyleRIPRel() && 4986 (M == CodeModel::Small || M == CodeModel::Kernel)) 4987 WrapperKind = X86ISD::WrapperRIP; 4988 else if (Subtarget->isPICStyleGOT()) 4989 OpFlag = X86II::MO_GOTOFF; 4990 else if (Subtarget->isPICStyleStubPIC()) 4991 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4992 4993 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 4994 4995 DebugLoc DL = Op.getDebugLoc(); 4996 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4997 4998 4999 // With PIC, the address is actually $g + Offset. 5000 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5001 !Subtarget->is64Bit()) { 5002 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5003 DAG.getNode(X86ISD::GlobalBaseReg, 5004 DebugLoc::getUnknownLoc(), 5005 getPointerTy()), 5006 Result); 5007 } 5008 5009 return Result; 5010} 5011 5012SDValue 5013X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 5014 // Create the TargetBlockAddressAddress node. 5015 unsigned char OpFlags = 5016 Subtarget->ClassifyBlockAddressReference(); 5017 CodeModel::Model M = getTargetMachine().getCodeModel(); 5018 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5019 DebugLoc dl = Op.getDebugLoc(); 5020 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5021 /*isTarget=*/true, OpFlags); 5022 5023 if (Subtarget->isPICStyleRIPRel() && 5024 (M == CodeModel::Small || M == CodeModel::Kernel)) 5025 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5026 else 5027 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5028 5029 // With PIC, the address is actually $g + Offset. 5030 if (isGlobalRelativeToPICBase(OpFlags)) { 5031 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5032 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5033 Result); 5034 } 5035 5036 return Result; 5037} 5038 5039SDValue 5040X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5041 int64_t Offset, 5042 SelectionDAG &DAG) const { 5043 // Create the TargetGlobalAddress node, folding in the constant 5044 // offset if it is legal. 5045 unsigned char OpFlags = 5046 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5047 CodeModel::Model M = getTargetMachine().getCodeModel(); 5048 SDValue Result; 5049 if (OpFlags == X86II::MO_NO_FLAG && 5050 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5051 // A direct static reference to a global. 5052 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 5053 Offset = 0; 5054 } else { 5055 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 5056 } 5057 5058 if (Subtarget->isPICStyleRIPRel() && 5059 (M == CodeModel::Small || M == CodeModel::Kernel)) 5060 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5061 else 5062 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5063 5064 // With PIC, the address is actually $g + Offset. 5065 if (isGlobalRelativeToPICBase(OpFlags)) { 5066 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5067 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5068 Result); 5069 } 5070 5071 // For globals that require a load from a stub to get the address, emit the 5072 // load. 5073 if (isGlobalStubReference(OpFlags)) 5074 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5075 PseudoSourceValue::getGOT(), 0, false, false, 0); 5076 5077 // If there was a non-zero offset that we didn't fold, create an explicit 5078 // addition for it. 5079 if (Offset != 0) 5080 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5081 DAG.getConstant(Offset, getPointerTy())); 5082 5083 return Result; 5084} 5085 5086SDValue 5087X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 5088 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5089 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5090 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5091} 5092 5093static SDValue 5094GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5095 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5096 unsigned char OperandFlags) { 5097 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5098 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5099 DebugLoc dl = GA->getDebugLoc(); 5100 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 5101 GA->getValueType(0), 5102 GA->getOffset(), 5103 OperandFlags); 5104 if (InFlag) { 5105 SDValue Ops[] = { Chain, TGA, *InFlag }; 5106 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5107 } else { 5108 SDValue Ops[] = { Chain, TGA }; 5109 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5110 } 5111 5112 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5113 MFI->setHasCalls(true); 5114 5115 SDValue Flag = Chain.getValue(1); 5116 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5117} 5118 5119// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5120static SDValue 5121LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5122 const EVT PtrVT) { 5123 SDValue InFlag; 5124 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5125 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5126 DAG.getNode(X86ISD::GlobalBaseReg, 5127 DebugLoc::getUnknownLoc(), 5128 PtrVT), InFlag); 5129 InFlag = Chain.getValue(1); 5130 5131 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5132} 5133 5134// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5135static SDValue 5136LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5137 const EVT PtrVT) { 5138 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5139 X86::RAX, X86II::MO_TLSGD); 5140} 5141 5142// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5143// "local exec" model. 5144static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5145 const EVT PtrVT, TLSModel::Model model, 5146 bool is64Bit) { 5147 DebugLoc dl = GA->getDebugLoc(); 5148 // Get the Thread Pointer 5149 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5150 DebugLoc::getUnknownLoc(), PtrVT, 5151 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5152 MVT::i32)); 5153 5154 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5155 NULL, 0, false, false, 0); 5156 5157 unsigned char OperandFlags = 0; 5158 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5159 // initialexec. 5160 unsigned WrapperKind = X86ISD::Wrapper; 5161 if (model == TLSModel::LocalExec) { 5162 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5163 } else if (is64Bit) { 5164 assert(model == TLSModel::InitialExec); 5165 OperandFlags = X86II::MO_GOTTPOFF; 5166 WrapperKind = X86ISD::WrapperRIP; 5167 } else { 5168 assert(model == TLSModel::InitialExec); 5169 OperandFlags = X86II::MO_INDNTPOFF; 5170 } 5171 5172 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5173 // exec) 5174 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5175 GA->getOffset(), OperandFlags); 5176 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5177 5178 if (model == TLSModel::InitialExec) 5179 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5180 PseudoSourceValue::getGOT(), 0, false, false, 0); 5181 5182 // The address of the thread local variable is the add of the thread 5183 // pointer with the offset of the variable. 5184 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5185} 5186 5187SDValue 5188X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 5189 // TODO: implement the "local dynamic" model 5190 // TODO: implement the "initial exec"model for pic executables 5191 assert(Subtarget->isTargetELF() && 5192 "TLS not implemented for non-ELF targets"); 5193 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5194 const GlobalValue *GV = GA->getGlobal(); 5195 5196 // If GV is an alias then use the aliasee for determining 5197 // thread-localness. 5198 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5199 GV = GA->resolveAliasedGlobal(false); 5200 5201 TLSModel::Model model = getTLSModel(GV, 5202 getTargetMachine().getRelocationModel()); 5203 5204 switch (model) { 5205 case TLSModel::GeneralDynamic: 5206 case TLSModel::LocalDynamic: // not implemented 5207 if (Subtarget->is64Bit()) 5208 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5209 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5210 5211 case TLSModel::InitialExec: 5212 case TLSModel::LocalExec: 5213 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5214 Subtarget->is64Bit()); 5215 } 5216 5217 llvm_unreachable("Unreachable"); 5218 return SDValue(); 5219} 5220 5221 5222/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5223/// take a 2 x i32 value to shift plus a shift amount. 5224SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 5225 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5226 EVT VT = Op.getValueType(); 5227 unsigned VTBits = VT.getSizeInBits(); 5228 DebugLoc dl = Op.getDebugLoc(); 5229 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5230 SDValue ShOpLo = Op.getOperand(0); 5231 SDValue ShOpHi = Op.getOperand(1); 5232 SDValue ShAmt = Op.getOperand(2); 5233 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5234 DAG.getConstant(VTBits - 1, MVT::i8)) 5235 : DAG.getConstant(0, VT); 5236 5237 SDValue Tmp2, Tmp3; 5238 if (Op.getOpcode() == ISD::SHL_PARTS) { 5239 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5240 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5241 } else { 5242 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5243 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5244 } 5245 5246 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5247 DAG.getConstant(VTBits, MVT::i8)); 5248 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5249 AndNode, DAG.getConstant(0, MVT::i8)); 5250 5251 SDValue Hi, Lo; 5252 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5253 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5254 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5255 5256 if (Op.getOpcode() == ISD::SHL_PARTS) { 5257 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5258 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5259 } else { 5260 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5261 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5262 } 5263 5264 SDValue Ops[2] = { Lo, Hi }; 5265 return DAG.getMergeValues(Ops, 2, dl); 5266} 5267 5268SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5269 EVT SrcVT = Op.getOperand(0).getValueType(); 5270 5271 if (SrcVT.isVector()) { 5272 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5273 return Op; 5274 } 5275 return SDValue(); 5276 } 5277 5278 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5279 "Unknown SINT_TO_FP to lower!"); 5280 5281 // These are really Legal; return the operand so the caller accepts it as 5282 // Legal. 5283 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5284 return Op; 5285 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5286 Subtarget->is64Bit()) { 5287 return Op; 5288 } 5289 5290 DebugLoc dl = Op.getDebugLoc(); 5291 unsigned Size = SrcVT.getSizeInBits()/8; 5292 MachineFunction &MF = DAG.getMachineFunction(); 5293 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5294 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5295 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5296 StackSlot, 5297 PseudoSourceValue::getFixedStack(SSFI), 0, 5298 false, false, 0); 5299 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5300} 5301 5302SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5303 SDValue StackSlot, 5304 SelectionDAG &DAG) { 5305 // Build the FILD 5306 DebugLoc dl = Op.getDebugLoc(); 5307 SDVTList Tys; 5308 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5309 if (useSSE) 5310 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5311 else 5312 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5313 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5314 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5315 Tys, Ops, array_lengthof(Ops)); 5316 5317 if (useSSE) { 5318 Chain = Result.getValue(1); 5319 SDValue InFlag = Result.getValue(2); 5320 5321 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5322 // shouldn't be necessary except that RFP cannot be live across 5323 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5324 MachineFunction &MF = DAG.getMachineFunction(); 5325 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5326 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5327 Tys = DAG.getVTList(MVT::Other); 5328 SDValue Ops[] = { 5329 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5330 }; 5331 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5332 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5333 PseudoSourceValue::getFixedStack(SSFI), 0, 5334 false, false, 0); 5335 } 5336 5337 return Result; 5338} 5339 5340// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5341SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5342 // This algorithm is not obvious. Here it is in C code, more or less: 5343 /* 5344 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5345 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5346 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5347 5348 // Copy ints to xmm registers. 5349 __m128i xh = _mm_cvtsi32_si128( hi ); 5350 __m128i xl = _mm_cvtsi32_si128( lo ); 5351 5352 // Combine into low half of a single xmm register. 5353 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5354 __m128d d; 5355 double sd; 5356 5357 // Merge in appropriate exponents to give the integer bits the right 5358 // magnitude. 5359 x = _mm_unpacklo_epi32( x, exp ); 5360 5361 // Subtract away the biases to deal with the IEEE-754 double precision 5362 // implicit 1. 5363 d = _mm_sub_pd( (__m128d) x, bias ); 5364 5365 // All conversions up to here are exact. The correctly rounded result is 5366 // calculated using the current rounding mode using the following 5367 // horizontal add. 5368 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5369 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5370 // store doesn't really need to be here (except 5371 // maybe to zero the other double) 5372 return sd; 5373 } 5374 */ 5375 5376 DebugLoc dl = Op.getDebugLoc(); 5377 LLVMContext *Context = DAG.getContext(); 5378 5379 // Build some magic constants. 5380 std::vector<Constant*> CV0; 5381 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5382 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5383 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5384 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5385 Constant *C0 = ConstantVector::get(CV0); 5386 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5387 5388 std::vector<Constant*> CV1; 5389 CV1.push_back( 5390 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5391 CV1.push_back( 5392 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5393 Constant *C1 = ConstantVector::get(CV1); 5394 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5395 5396 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5397 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5398 Op.getOperand(0), 5399 DAG.getIntPtrConstant(1))); 5400 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5401 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5402 Op.getOperand(0), 5403 DAG.getIntPtrConstant(0))); 5404 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5405 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5406 PseudoSourceValue::getConstantPool(), 0, 5407 false, false, 16); 5408 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5409 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5410 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5411 PseudoSourceValue::getConstantPool(), 0, 5412 false, false, 16); 5413 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5414 5415 // Add the halves; easiest way is to swap them into another reg first. 5416 int ShufMask[2] = { 1, -1 }; 5417 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5418 DAG.getUNDEF(MVT::v2f64), ShufMask); 5419 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5420 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5421 DAG.getIntPtrConstant(0)); 5422} 5423 5424// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5425SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5426 DebugLoc dl = Op.getDebugLoc(); 5427 // FP constant to bias correct the final result. 5428 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5429 MVT::f64); 5430 5431 // Load the 32-bit value into an XMM register. 5432 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5433 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5434 Op.getOperand(0), 5435 DAG.getIntPtrConstant(0))); 5436 5437 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5438 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5439 DAG.getIntPtrConstant(0)); 5440 5441 // Or the load with the bias. 5442 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5443 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5444 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5445 MVT::v2f64, Load)), 5446 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5447 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5448 MVT::v2f64, Bias))); 5449 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5450 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5451 DAG.getIntPtrConstant(0)); 5452 5453 // Subtract the bias. 5454 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5455 5456 // Handle final rounding. 5457 EVT DestVT = Op.getValueType(); 5458 5459 if (DestVT.bitsLT(MVT::f64)) { 5460 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5461 DAG.getIntPtrConstant(0)); 5462 } else if (DestVT.bitsGT(MVT::f64)) { 5463 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5464 } 5465 5466 // Handle final rounding. 5467 return Sub; 5468} 5469 5470SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5471 SDValue N0 = Op.getOperand(0); 5472 DebugLoc dl = Op.getDebugLoc(); 5473 5474 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5475 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5476 // the optimization here. 5477 if (DAG.SignBitIsZero(N0)) 5478 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5479 5480 EVT SrcVT = N0.getValueType(); 5481 if (SrcVT == MVT::i64) { 5482 // We only handle SSE2 f64 target here; caller can expand the rest. 5483 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5484 return SDValue(); 5485 5486 return LowerUINT_TO_FP_i64(Op, DAG); 5487 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5488 return LowerUINT_TO_FP_i32(Op, DAG); 5489 } 5490 5491 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5492 5493 // Make a 64-bit buffer, and use it to build an FILD. 5494 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5495 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5496 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5497 getPointerTy(), StackSlot, WordOff); 5498 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5499 StackSlot, NULL, 0, false, false, 0); 5500 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5501 OffsetSlot, NULL, 0, false, false, 0); 5502 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5503} 5504 5505std::pair<SDValue,SDValue> X86TargetLowering:: 5506FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5507 DebugLoc dl = Op.getDebugLoc(); 5508 5509 EVT DstTy = Op.getValueType(); 5510 5511 if (!IsSigned) { 5512 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5513 DstTy = MVT::i64; 5514 } 5515 5516 assert(DstTy.getSimpleVT() <= MVT::i64 && 5517 DstTy.getSimpleVT() >= MVT::i16 && 5518 "Unknown FP_TO_SINT to lower!"); 5519 5520 // These are really Legal. 5521 if (DstTy == MVT::i32 && 5522 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5523 return std::make_pair(SDValue(), SDValue()); 5524 if (Subtarget->is64Bit() && 5525 DstTy == MVT::i64 && 5526 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5527 return std::make_pair(SDValue(), SDValue()); 5528 5529 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5530 // stack slot. 5531 MachineFunction &MF = DAG.getMachineFunction(); 5532 unsigned MemSize = DstTy.getSizeInBits()/8; 5533 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5534 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5535 5536 unsigned Opc; 5537 switch (DstTy.getSimpleVT().SimpleTy) { 5538 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5539 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5540 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5541 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5542 } 5543 5544 SDValue Chain = DAG.getEntryNode(); 5545 SDValue Value = Op.getOperand(0); 5546 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5547 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5548 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5549 PseudoSourceValue::getFixedStack(SSFI), 0, 5550 false, false, 0); 5551 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5552 SDValue Ops[] = { 5553 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5554 }; 5555 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5556 Chain = Value.getValue(1); 5557 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5558 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5559 } 5560 5561 // Build the FP_TO_INT*_IN_MEM 5562 SDValue Ops[] = { Chain, Value, StackSlot }; 5563 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5564 5565 return std::make_pair(FIST, StackSlot); 5566} 5567 5568SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5569 if (Op.getValueType().isVector()) { 5570 if (Op.getValueType() == MVT::v2i32 && 5571 Op.getOperand(0).getValueType() == MVT::v2f64) { 5572 return Op; 5573 } 5574 return SDValue(); 5575 } 5576 5577 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5578 SDValue FIST = Vals.first, StackSlot = Vals.second; 5579 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5580 if (FIST.getNode() == 0) return Op; 5581 5582 // Load the result. 5583 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5584 FIST, StackSlot, NULL, 0, false, false, 0); 5585} 5586 5587SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5588 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5589 SDValue FIST = Vals.first, StackSlot = Vals.second; 5590 assert(FIST.getNode() && "Unexpected failure"); 5591 5592 // Load the result. 5593 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5594 FIST, StackSlot, NULL, 0, false, false, 0); 5595} 5596 5597SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5598 LLVMContext *Context = DAG.getContext(); 5599 DebugLoc dl = Op.getDebugLoc(); 5600 EVT VT = Op.getValueType(); 5601 EVT EltVT = VT; 5602 if (VT.isVector()) 5603 EltVT = VT.getVectorElementType(); 5604 std::vector<Constant*> CV; 5605 if (EltVT == MVT::f64) { 5606 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5607 CV.push_back(C); 5608 CV.push_back(C); 5609 } else { 5610 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5611 CV.push_back(C); 5612 CV.push_back(C); 5613 CV.push_back(C); 5614 CV.push_back(C); 5615 } 5616 Constant *C = ConstantVector::get(CV); 5617 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5618 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5619 PseudoSourceValue::getConstantPool(), 0, 5620 false, false, 16); 5621 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5622} 5623 5624SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5625 LLVMContext *Context = DAG.getContext(); 5626 DebugLoc dl = Op.getDebugLoc(); 5627 EVT VT = Op.getValueType(); 5628 EVT EltVT = VT; 5629 if (VT.isVector()) 5630 EltVT = VT.getVectorElementType(); 5631 std::vector<Constant*> CV; 5632 if (EltVT == MVT::f64) { 5633 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5634 CV.push_back(C); 5635 CV.push_back(C); 5636 } else { 5637 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5638 CV.push_back(C); 5639 CV.push_back(C); 5640 CV.push_back(C); 5641 CV.push_back(C); 5642 } 5643 Constant *C = ConstantVector::get(CV); 5644 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5645 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5646 PseudoSourceValue::getConstantPool(), 0, 5647 false, false, 16); 5648 if (VT.isVector()) { 5649 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5650 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5651 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5652 Op.getOperand(0)), 5653 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5654 } else { 5655 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5656 } 5657} 5658 5659SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5660 LLVMContext *Context = DAG.getContext(); 5661 SDValue Op0 = Op.getOperand(0); 5662 SDValue Op1 = Op.getOperand(1); 5663 DebugLoc dl = Op.getDebugLoc(); 5664 EVT VT = Op.getValueType(); 5665 EVT SrcVT = Op1.getValueType(); 5666 5667 // If second operand is smaller, extend it first. 5668 if (SrcVT.bitsLT(VT)) { 5669 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5670 SrcVT = VT; 5671 } 5672 // And if it is bigger, shrink it first. 5673 if (SrcVT.bitsGT(VT)) { 5674 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5675 SrcVT = VT; 5676 } 5677 5678 // At this point the operands and the result should have the same 5679 // type, and that won't be f80 since that is not custom lowered. 5680 5681 // First get the sign bit of second operand. 5682 std::vector<Constant*> CV; 5683 if (SrcVT == MVT::f64) { 5684 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5685 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5686 } else { 5687 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5688 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5689 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5690 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5691 } 5692 Constant *C = ConstantVector::get(CV); 5693 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5694 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5695 PseudoSourceValue::getConstantPool(), 0, 5696 false, false, 16); 5697 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5698 5699 // Shift sign bit right or left if the two operands have different types. 5700 if (SrcVT.bitsGT(VT)) { 5701 // Op0 is MVT::f32, Op1 is MVT::f64. 5702 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5703 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5704 DAG.getConstant(32, MVT::i32)); 5705 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5706 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5707 DAG.getIntPtrConstant(0)); 5708 } 5709 5710 // Clear first operand sign bit. 5711 CV.clear(); 5712 if (VT == MVT::f64) { 5713 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5714 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5715 } else { 5716 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5717 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5718 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5719 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5720 } 5721 C = ConstantVector::get(CV); 5722 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5723 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5724 PseudoSourceValue::getConstantPool(), 0, 5725 false, false, 16); 5726 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5727 5728 // Or the value with the sign bit. 5729 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5730} 5731 5732/// Emit nodes that will be selected as "test Op0,Op0", or something 5733/// equivalent. 5734SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5735 SelectionDAG &DAG) { 5736 DebugLoc dl = Op.getDebugLoc(); 5737 5738 // CF and OF aren't always set the way we want. Determine which 5739 // of these we need. 5740 bool NeedCF = false; 5741 bool NeedOF = false; 5742 switch (X86CC) { 5743 case X86::COND_A: case X86::COND_AE: 5744 case X86::COND_B: case X86::COND_BE: 5745 NeedCF = true; 5746 break; 5747 case X86::COND_G: case X86::COND_GE: 5748 case X86::COND_L: case X86::COND_LE: 5749 case X86::COND_O: case X86::COND_NO: 5750 NeedOF = true; 5751 break; 5752 default: break; 5753 } 5754 5755 // See if we can use the EFLAGS value from the operand instead of 5756 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5757 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5758 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5759 unsigned Opcode = 0; 5760 unsigned NumOperands = 0; 5761 switch (Op.getNode()->getOpcode()) { 5762 case ISD::ADD: 5763 // Due to an isel shortcoming, be conservative if this add is likely to 5764 // be selected as part of a load-modify-store instruction. When the root 5765 // node in a match is a store, isel doesn't know how to remap non-chain 5766 // non-flag uses of other nodes in the match, such as the ADD in this 5767 // case. This leads to the ADD being left around and reselected, with 5768 // the result being two adds in the output. 5769 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5770 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5771 if (UI->getOpcode() == ISD::STORE) 5772 goto default_case; 5773 if (ConstantSDNode *C = 5774 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5775 // An add of one will be selected as an INC. 5776 if (C->getAPIntValue() == 1) { 5777 Opcode = X86ISD::INC; 5778 NumOperands = 1; 5779 break; 5780 } 5781 // An add of negative one (subtract of one) will be selected as a DEC. 5782 if (C->getAPIntValue().isAllOnesValue()) { 5783 Opcode = X86ISD::DEC; 5784 NumOperands = 1; 5785 break; 5786 } 5787 } 5788 // Otherwise use a regular EFLAGS-setting add. 5789 Opcode = X86ISD::ADD; 5790 NumOperands = 2; 5791 break; 5792 case ISD::AND: { 5793 // If the primary and result isn't used, don't bother using X86ISD::AND, 5794 // because a TEST instruction will be better. 5795 bool NonFlagUse = false; 5796 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5797 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 5798 SDNode *User = *UI; 5799 unsigned UOpNo = UI.getOperandNo(); 5800 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 5801 // Look pass truncate. 5802 UOpNo = User->use_begin().getOperandNo(); 5803 User = *User->use_begin(); 5804 } 5805 if (User->getOpcode() != ISD::BRCOND && 5806 User->getOpcode() != ISD::SETCC && 5807 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 5808 NonFlagUse = true; 5809 break; 5810 } 5811 } 5812 if (!NonFlagUse) 5813 break; 5814 } 5815 // FALL THROUGH 5816 case ISD::SUB: 5817 case ISD::OR: 5818 case ISD::XOR: 5819 // Due to the ISEL shortcoming noted above, be conservative if this op is 5820 // likely to be selected as part of a load-modify-store instruction. 5821 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5822 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5823 if (UI->getOpcode() == ISD::STORE) 5824 goto default_case; 5825 // Otherwise use a regular EFLAGS-setting instruction. 5826 switch (Op.getNode()->getOpcode()) { 5827 case ISD::SUB: Opcode = X86ISD::SUB; break; 5828 case ISD::OR: Opcode = X86ISD::OR; break; 5829 case ISD::XOR: Opcode = X86ISD::XOR; break; 5830 case ISD::AND: Opcode = X86ISD::AND; break; 5831 default: llvm_unreachable("unexpected operator!"); 5832 } 5833 NumOperands = 2; 5834 break; 5835 case X86ISD::ADD: 5836 case X86ISD::SUB: 5837 case X86ISD::INC: 5838 case X86ISD::DEC: 5839 case X86ISD::OR: 5840 case X86ISD::XOR: 5841 case X86ISD::AND: 5842 return SDValue(Op.getNode(), 1); 5843 default: 5844 default_case: 5845 break; 5846 } 5847 if (Opcode != 0) { 5848 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5849 SmallVector<SDValue, 4> Ops; 5850 for (unsigned i = 0; i != NumOperands; ++i) 5851 Ops.push_back(Op.getOperand(i)); 5852 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5853 DAG.ReplaceAllUsesWith(Op, New); 5854 return SDValue(New.getNode(), 1); 5855 } 5856 } 5857 5858 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5859 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5860 DAG.getConstant(0, Op.getValueType())); 5861} 5862 5863/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5864/// equivalent. 5865SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5866 SelectionDAG &DAG) { 5867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5868 if (C->getAPIntValue() == 0) 5869 return EmitTest(Op0, X86CC, DAG); 5870 5871 DebugLoc dl = Op0.getDebugLoc(); 5872 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5873} 5874 5875/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 5876/// if it's possible. 5877static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC, 5878 DebugLoc dl, SelectionDAG &DAG) { 5879 SDValue LHS, RHS; 5880 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5881 if (ConstantSDNode *Op010C = 5882 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5883 if (Op010C->getZExtValue() == 1) { 5884 LHS = Op0.getOperand(0); 5885 RHS = Op0.getOperand(1).getOperand(1); 5886 } 5887 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5888 if (ConstantSDNode *Op000C = 5889 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5890 if (Op000C->getZExtValue() == 1) { 5891 LHS = Op0.getOperand(1); 5892 RHS = Op0.getOperand(0).getOperand(1); 5893 } 5894 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5895 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5896 SDValue AndLHS = Op0.getOperand(0); 5897 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5898 LHS = AndLHS.getOperand(0); 5899 RHS = AndLHS.getOperand(1); 5900 } 5901 } 5902 5903 if (LHS.getNode()) { 5904 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5905 // instruction. Since the shift amount is in-range-or-undefined, we know 5906 // that doing a bittest on the i16 value is ok. We extend to i32 because 5907 // the encoding for the i16 version is larger than the i32 version. 5908 if (LHS.getValueType() == MVT::i8) 5909 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5910 5911 // If the operand types disagree, extend the shift amount to match. Since 5912 // BT ignores high bits (like shifts) we can use anyextend. 5913 if (LHS.getValueType() != RHS.getValueType()) 5914 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5915 5916 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5917 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5918 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5919 DAG.getConstant(Cond, MVT::i8), BT); 5920 } 5921 5922 return SDValue(); 5923} 5924 5925SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5926 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5927 SDValue Op0 = Op.getOperand(0); 5928 SDValue Op1 = Op.getOperand(1); 5929 DebugLoc dl = Op.getDebugLoc(); 5930 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5931 5932 // Optimize to BT if possible. 5933 // Lower (X & (1 << N)) == 0 to BT(X, N). 5934 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5935 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5936 if (Op0.getOpcode() == ISD::AND && 5937 Op0.hasOneUse() && 5938 Op1.getOpcode() == ISD::Constant && 5939 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5940 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5941 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 5942 if (NewSetCC.getNode()) 5943 return NewSetCC; 5944 } 5945 5946 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5947 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5948 if (X86CC == X86::COND_INVALID) 5949 return SDValue(); 5950 5951 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 5952 5953 // Use sbb x, x to materialize carry bit into a GPR. 5954 if (X86CC == X86::COND_B) 5955 return DAG.getNode(ISD::AND, dl, MVT::i8, 5956 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 5957 DAG.getConstant(X86CC, MVT::i8), Cond), 5958 DAG.getConstant(1, MVT::i8)); 5959 5960 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5961 DAG.getConstant(X86CC, MVT::i8), Cond); 5962} 5963 5964SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5965 SDValue Cond; 5966 SDValue Op0 = Op.getOperand(0); 5967 SDValue Op1 = Op.getOperand(1); 5968 SDValue CC = Op.getOperand(2); 5969 EVT VT = Op.getValueType(); 5970 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5971 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5972 DebugLoc dl = Op.getDebugLoc(); 5973 5974 if (isFP) { 5975 unsigned SSECC = 8; 5976 EVT VT0 = Op0.getValueType(); 5977 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5978 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5979 bool Swap = false; 5980 5981 switch (SetCCOpcode) { 5982 default: break; 5983 case ISD::SETOEQ: 5984 case ISD::SETEQ: SSECC = 0; break; 5985 case ISD::SETOGT: 5986 case ISD::SETGT: Swap = true; // Fallthrough 5987 case ISD::SETLT: 5988 case ISD::SETOLT: SSECC = 1; break; 5989 case ISD::SETOGE: 5990 case ISD::SETGE: Swap = true; // Fallthrough 5991 case ISD::SETLE: 5992 case ISD::SETOLE: SSECC = 2; break; 5993 case ISD::SETUO: SSECC = 3; break; 5994 case ISD::SETUNE: 5995 case ISD::SETNE: SSECC = 4; break; 5996 case ISD::SETULE: Swap = true; 5997 case ISD::SETUGE: SSECC = 5; break; 5998 case ISD::SETULT: Swap = true; 5999 case ISD::SETUGT: SSECC = 6; break; 6000 case ISD::SETO: SSECC = 7; break; 6001 } 6002 if (Swap) 6003 std::swap(Op0, Op1); 6004 6005 // In the two special cases we can't handle, emit two comparisons. 6006 if (SSECC == 8) { 6007 if (SetCCOpcode == ISD::SETUEQ) { 6008 SDValue UNORD, EQ; 6009 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6010 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6011 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6012 } 6013 else if (SetCCOpcode == ISD::SETONE) { 6014 SDValue ORD, NEQ; 6015 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6016 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6017 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6018 } 6019 llvm_unreachable("Illegal FP comparison"); 6020 } 6021 // Handle all other FP comparisons here. 6022 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6023 } 6024 6025 // We are handling one of the integer comparisons here. Since SSE only has 6026 // GT and EQ comparisons for integer, swapping operands and multiple 6027 // operations may be required for some comparisons. 6028 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6029 bool Swap = false, Invert = false, FlipSigns = false; 6030 6031 switch (VT.getSimpleVT().SimpleTy) { 6032 default: break; 6033 case MVT::v8i8: 6034 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6035 case MVT::v4i16: 6036 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6037 case MVT::v2i32: 6038 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6039 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6040 } 6041 6042 switch (SetCCOpcode) { 6043 default: break; 6044 case ISD::SETNE: Invert = true; 6045 case ISD::SETEQ: Opc = EQOpc; break; 6046 case ISD::SETLT: Swap = true; 6047 case ISD::SETGT: Opc = GTOpc; break; 6048 case ISD::SETGE: Swap = true; 6049 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6050 case ISD::SETULT: Swap = true; 6051 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6052 case ISD::SETUGE: Swap = true; 6053 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6054 } 6055 if (Swap) 6056 std::swap(Op0, Op1); 6057 6058 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6059 // bits of the inputs before performing those operations. 6060 if (FlipSigns) { 6061 EVT EltVT = VT.getVectorElementType(); 6062 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6063 EltVT); 6064 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6065 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6066 SignBits.size()); 6067 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6068 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6069 } 6070 6071 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6072 6073 // If the logical-not of the result is required, perform that now. 6074 if (Invert) 6075 Result = DAG.getNOT(dl, Result, VT); 6076 6077 return Result; 6078} 6079 6080// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6081static bool isX86LogicalCmp(SDValue Op) { 6082 unsigned Opc = Op.getNode()->getOpcode(); 6083 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6084 return true; 6085 if (Op.getResNo() == 1 && 6086 (Opc == X86ISD::ADD || 6087 Opc == X86ISD::SUB || 6088 Opc == X86ISD::SMUL || 6089 Opc == X86ISD::UMUL || 6090 Opc == X86ISD::INC || 6091 Opc == X86ISD::DEC || 6092 Opc == X86ISD::OR || 6093 Opc == X86ISD::XOR || 6094 Opc == X86ISD::AND)) 6095 return true; 6096 6097 return false; 6098} 6099 6100SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 6101 bool addTest = true; 6102 SDValue Cond = Op.getOperand(0); 6103 DebugLoc dl = Op.getDebugLoc(); 6104 SDValue CC; 6105 6106 if (Cond.getOpcode() == ISD::SETCC) { 6107 SDValue NewCond = LowerSETCC(Cond, DAG); 6108 if (NewCond.getNode()) 6109 Cond = NewCond; 6110 } 6111 6112 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6113 SDValue Op1 = Op.getOperand(1); 6114 SDValue Op2 = Op.getOperand(2); 6115 if (Cond.getOpcode() == X86ISD::SETCC && 6116 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6117 SDValue Cmp = Cond.getOperand(1); 6118 if (Cmp.getOpcode() == X86ISD::CMP) { 6119 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6120 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6121 ConstantSDNode *RHSC = 6122 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6123 if (N1C && N1C->isAllOnesValue() && 6124 N2C && N2C->isNullValue() && 6125 RHSC && RHSC->isNullValue()) { 6126 SDValue CmpOp0 = Cmp.getOperand(0); 6127 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(), 6128 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6129 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6130 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6131 } 6132 } 6133 } 6134 6135 // Look pass (and (setcc_carry (cmp ...)), 1). 6136 if (Cond.getOpcode() == ISD::AND && 6137 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6138 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6139 if (C && C->getAPIntValue() == 1) 6140 Cond = Cond.getOperand(0); 6141 } 6142 6143 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6144 // setting operand in place of the X86ISD::SETCC. 6145 if (Cond.getOpcode() == X86ISD::SETCC || 6146 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6147 CC = Cond.getOperand(0); 6148 6149 SDValue Cmp = Cond.getOperand(1); 6150 unsigned Opc = Cmp.getOpcode(); 6151 EVT VT = Op.getValueType(); 6152 6153 bool IllegalFPCMov = false; 6154 if (VT.isFloatingPoint() && !VT.isVector() && 6155 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6156 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6157 6158 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6159 Opc == X86ISD::BT) { // FIXME 6160 Cond = Cmp; 6161 addTest = false; 6162 } 6163 } 6164 6165 if (addTest) { 6166 // Look pass the truncate. 6167 if (Cond.getOpcode() == ISD::TRUNCATE) 6168 Cond = Cond.getOperand(0); 6169 6170 // We know the result of AND is compared against zero. Try to match 6171 // it to BT. 6172 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6173 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6174 if (NewSetCC.getNode()) { 6175 CC = NewSetCC.getOperand(0); 6176 Cond = NewSetCC.getOperand(1); 6177 addTest = false; 6178 } 6179 } 6180 } 6181 6182 if (addTest) { 6183 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6184 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6185 } 6186 6187 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6188 // condition is true. 6189 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6190 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6191 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6192} 6193 6194// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6195// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6196// from the AND / OR. 6197static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6198 Opc = Op.getOpcode(); 6199 if (Opc != ISD::OR && Opc != ISD::AND) 6200 return false; 6201 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6202 Op.getOperand(0).hasOneUse() && 6203 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6204 Op.getOperand(1).hasOneUse()); 6205} 6206 6207// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6208// 1 and that the SETCC node has a single use. 6209static bool isXor1OfSetCC(SDValue Op) { 6210 if (Op.getOpcode() != ISD::XOR) 6211 return false; 6212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6213 if (N1C && N1C->getAPIntValue() == 1) { 6214 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6215 Op.getOperand(0).hasOneUse(); 6216 } 6217 return false; 6218} 6219 6220SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 6221 bool addTest = true; 6222 SDValue Chain = Op.getOperand(0); 6223 SDValue Cond = Op.getOperand(1); 6224 SDValue Dest = Op.getOperand(2); 6225 DebugLoc dl = Op.getDebugLoc(); 6226 SDValue CC; 6227 6228 if (Cond.getOpcode() == ISD::SETCC) { 6229 SDValue NewCond = LowerSETCC(Cond, DAG); 6230 if (NewCond.getNode()) 6231 Cond = NewCond; 6232 } 6233#if 0 6234 // FIXME: LowerXALUO doesn't handle these!! 6235 else if (Cond.getOpcode() == X86ISD::ADD || 6236 Cond.getOpcode() == X86ISD::SUB || 6237 Cond.getOpcode() == X86ISD::SMUL || 6238 Cond.getOpcode() == X86ISD::UMUL) 6239 Cond = LowerXALUO(Cond, DAG); 6240#endif 6241 6242 // Look pass (and (setcc_carry (cmp ...)), 1). 6243 if (Cond.getOpcode() == ISD::AND && 6244 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6245 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6246 if (C && C->getAPIntValue() == 1) 6247 Cond = Cond.getOperand(0); 6248 } 6249 6250 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6251 // setting operand in place of the X86ISD::SETCC. 6252 if (Cond.getOpcode() == X86ISD::SETCC || 6253 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6254 CC = Cond.getOperand(0); 6255 6256 SDValue Cmp = Cond.getOperand(1); 6257 unsigned Opc = Cmp.getOpcode(); 6258 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6259 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6260 Cond = Cmp; 6261 addTest = false; 6262 } else { 6263 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6264 default: break; 6265 case X86::COND_O: 6266 case X86::COND_B: 6267 // These can only come from an arithmetic instruction with overflow, 6268 // e.g. SADDO, UADDO. 6269 Cond = Cond.getNode()->getOperand(1); 6270 addTest = false; 6271 break; 6272 } 6273 } 6274 } else { 6275 unsigned CondOpc; 6276 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6277 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6278 if (CondOpc == ISD::OR) { 6279 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6280 // two branches instead of an explicit OR instruction with a 6281 // separate test. 6282 if (Cmp == Cond.getOperand(1).getOperand(1) && 6283 isX86LogicalCmp(Cmp)) { 6284 CC = Cond.getOperand(0).getOperand(0); 6285 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6286 Chain, Dest, CC, Cmp); 6287 CC = Cond.getOperand(1).getOperand(0); 6288 Cond = Cmp; 6289 addTest = false; 6290 } 6291 } else { // ISD::AND 6292 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6293 // two branches instead of an explicit AND instruction with a 6294 // separate test. However, we only do this if this block doesn't 6295 // have a fall-through edge, because this requires an explicit 6296 // jmp when the condition is false. 6297 if (Cmp == Cond.getOperand(1).getOperand(1) && 6298 isX86LogicalCmp(Cmp) && 6299 Op.getNode()->hasOneUse()) { 6300 X86::CondCode CCode = 6301 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6302 CCode = X86::GetOppositeBranchCondition(CCode); 6303 CC = DAG.getConstant(CCode, MVT::i8); 6304 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 6305 // Look for an unconditional branch following this conditional branch. 6306 // We need this because we need to reverse the successors in order 6307 // to implement FCMP_OEQ. 6308 if (User.getOpcode() == ISD::BR) { 6309 SDValue FalseBB = User.getOperand(1); 6310 SDValue NewBR = 6311 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 6312 assert(NewBR == User); 6313 Dest = FalseBB; 6314 6315 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6316 Chain, Dest, CC, Cmp); 6317 X86::CondCode CCode = 6318 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6319 CCode = X86::GetOppositeBranchCondition(CCode); 6320 CC = DAG.getConstant(CCode, MVT::i8); 6321 Cond = Cmp; 6322 addTest = false; 6323 } 6324 } 6325 } 6326 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6327 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6328 // It should be transformed during dag combiner except when the condition 6329 // is set by a arithmetics with overflow node. 6330 X86::CondCode CCode = 6331 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6332 CCode = X86::GetOppositeBranchCondition(CCode); 6333 CC = DAG.getConstant(CCode, MVT::i8); 6334 Cond = Cond.getOperand(0).getOperand(1); 6335 addTest = false; 6336 } 6337 } 6338 6339 if (addTest) { 6340 // Look pass the truncate. 6341 if (Cond.getOpcode() == ISD::TRUNCATE) 6342 Cond = Cond.getOperand(0); 6343 6344 // We know the result of AND is compared against zero. Try to match 6345 // it to BT. 6346 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6347 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6348 if (NewSetCC.getNode()) { 6349 CC = NewSetCC.getOperand(0); 6350 Cond = NewSetCC.getOperand(1); 6351 addTest = false; 6352 } 6353 } 6354 } 6355 6356 if (addTest) { 6357 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6358 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6359 } 6360 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6361 Chain, Dest, CC, Cond); 6362} 6363 6364 6365// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6366// Calls to _alloca is needed to probe the stack when allocating more than 4k 6367// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6368// that the guard pages used by the OS virtual memory manager are allocated in 6369// correct sequence. 6370SDValue 6371X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6372 SelectionDAG &DAG) { 6373 assert(Subtarget->isTargetCygMing() && 6374 "This should be used only on Cygwin/Mingw targets"); 6375 DebugLoc dl = Op.getDebugLoc(); 6376 6377 // Get the inputs. 6378 SDValue Chain = Op.getOperand(0); 6379 SDValue Size = Op.getOperand(1); 6380 // FIXME: Ensure alignment here 6381 6382 SDValue Flag; 6383 6384 EVT IntPtr = getPointerTy(); 6385 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6386 6387 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 6388 6389 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6390 Flag = Chain.getValue(1); 6391 6392 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6393 SDValue Ops[] = { Chain, 6394 DAG.getTargetExternalSymbol("_alloca", IntPtr), 6395 DAG.getRegister(X86::EAX, IntPtr), 6396 DAG.getRegister(X86StackPtr, SPTy), 6397 Flag }; 6398 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 6399 Flag = Chain.getValue(1); 6400 6401 Chain = DAG.getCALLSEQ_END(Chain, 6402 DAG.getIntPtrConstant(0, true), 6403 DAG.getIntPtrConstant(0, true), 6404 Flag); 6405 6406 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6407 6408 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6409 return DAG.getMergeValues(Ops1, 2, dl); 6410} 6411 6412SDValue 6413X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 6414 SDValue Chain, 6415 SDValue Dst, SDValue Src, 6416 SDValue Size, unsigned Align, 6417 const Value *DstSV, 6418 uint64_t DstSVOff) { 6419 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6420 6421 // If not DWORD aligned or size is more than the threshold, call the library. 6422 // The libc version is likely to be faster for these cases. It can use the 6423 // address value and run time information about the CPU. 6424 if ((Align & 3) != 0 || 6425 !ConstantSize || 6426 ConstantSize->getZExtValue() > 6427 getSubtarget()->getMaxInlineSizeThreshold()) { 6428 SDValue InFlag(0, 0); 6429 6430 // Check to see if there is a specialized entry-point for memory zeroing. 6431 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 6432 6433 if (const char *bzeroEntry = V && 6434 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 6435 EVT IntPtr = getPointerTy(); 6436 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 6437 TargetLowering::ArgListTy Args; 6438 TargetLowering::ArgListEntry Entry; 6439 Entry.Node = Dst; 6440 Entry.Ty = IntPtrTy; 6441 Args.push_back(Entry); 6442 Entry.Node = Size; 6443 Args.push_back(Entry); 6444 std::pair<SDValue,SDValue> CallResult = 6445 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 6446 false, false, false, false, 6447 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 6448 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl, 6449 DAG.GetOrdering(Chain.getNode())); 6450 return CallResult.second; 6451 } 6452 6453 // Otherwise have the target-independent code call memset. 6454 return SDValue(); 6455 } 6456 6457 uint64_t SizeVal = ConstantSize->getZExtValue(); 6458 SDValue InFlag(0, 0); 6459 EVT AVT; 6460 SDValue Count; 6461 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 6462 unsigned BytesLeft = 0; 6463 bool TwoRepStos = false; 6464 if (ValC) { 6465 unsigned ValReg; 6466 uint64_t Val = ValC->getZExtValue() & 255; 6467 6468 // If the value is a constant, then we can potentially use larger sets. 6469 switch (Align & 3) { 6470 case 2: // WORD aligned 6471 AVT = MVT::i16; 6472 ValReg = X86::AX; 6473 Val = (Val << 8) | Val; 6474 break; 6475 case 0: // DWORD aligned 6476 AVT = MVT::i32; 6477 ValReg = X86::EAX; 6478 Val = (Val << 8) | Val; 6479 Val = (Val << 16) | Val; 6480 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 6481 AVT = MVT::i64; 6482 ValReg = X86::RAX; 6483 Val = (Val << 32) | Val; 6484 } 6485 break; 6486 default: // Byte aligned 6487 AVT = MVT::i8; 6488 ValReg = X86::AL; 6489 Count = DAG.getIntPtrConstant(SizeVal); 6490 break; 6491 } 6492 6493 if (AVT.bitsGT(MVT::i8)) { 6494 unsigned UBytes = AVT.getSizeInBits() / 8; 6495 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 6496 BytesLeft = SizeVal % UBytes; 6497 } 6498 6499 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 6500 InFlag); 6501 InFlag = Chain.getValue(1); 6502 } else { 6503 AVT = MVT::i8; 6504 Count = DAG.getIntPtrConstant(SizeVal); 6505 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 6506 InFlag = Chain.getValue(1); 6507 } 6508 6509 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6510 X86::ECX, 6511 Count, InFlag); 6512 InFlag = Chain.getValue(1); 6513 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6514 X86::EDI, 6515 Dst, InFlag); 6516 InFlag = Chain.getValue(1); 6517 6518 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6519 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6520 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6521 6522 if (TwoRepStos) { 6523 InFlag = Chain.getValue(1); 6524 Count = Size; 6525 EVT CVT = Count.getValueType(); 6526 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 6527 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 6528 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 6529 X86::ECX, 6530 Left, InFlag); 6531 InFlag = Chain.getValue(1); 6532 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6533 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; 6534 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6535 } else if (BytesLeft) { 6536 // Handle the last 1 - 7 bytes. 6537 unsigned Offset = SizeVal - BytesLeft; 6538 EVT AddrVT = Dst.getValueType(); 6539 EVT SizeVT = Size.getValueType(); 6540 6541 Chain = DAG.getMemset(Chain, dl, 6542 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6543 DAG.getConstant(Offset, AddrVT)), 6544 Src, 6545 DAG.getConstant(BytesLeft, SizeVT), 6546 Align, DstSV, DstSVOff + Offset); 6547 } 6548 6549 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6550 return Chain; 6551} 6552 6553SDValue 6554X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6555 SDValue Chain, SDValue Dst, SDValue Src, 6556 SDValue Size, unsigned Align, 6557 bool AlwaysInline, 6558 const Value *DstSV, uint64_t DstSVOff, 6559 const Value *SrcSV, uint64_t SrcSVOff) { 6560 // This requires the copy size to be a constant, preferrably 6561 // within a subtarget-specific limit. 6562 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6563 if (!ConstantSize) 6564 return SDValue(); 6565 uint64_t SizeVal = ConstantSize->getZExtValue(); 6566 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6567 return SDValue(); 6568 6569 /// If not DWORD aligned, call the library. 6570 if ((Align & 3) != 0) 6571 return SDValue(); 6572 6573 // DWORD aligned 6574 EVT AVT = MVT::i32; 6575 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6576 AVT = MVT::i64; 6577 6578 unsigned UBytes = AVT.getSizeInBits() / 8; 6579 unsigned CountVal = SizeVal / UBytes; 6580 SDValue Count = DAG.getIntPtrConstant(CountVal); 6581 unsigned BytesLeft = SizeVal % UBytes; 6582 6583 SDValue InFlag(0, 0); 6584 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6585 X86::ECX, 6586 Count, InFlag); 6587 InFlag = Chain.getValue(1); 6588 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6589 X86::EDI, 6590 Dst, InFlag); 6591 InFlag = Chain.getValue(1); 6592 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6593 X86::ESI, 6594 Src, InFlag); 6595 InFlag = Chain.getValue(1); 6596 6597 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6598 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6599 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops, 6600 array_lengthof(Ops)); 6601 6602 SmallVector<SDValue, 4> Results; 6603 Results.push_back(RepMovs); 6604 if (BytesLeft) { 6605 // Handle the last 1 - 7 bytes. 6606 unsigned Offset = SizeVal - BytesLeft; 6607 EVT DstVT = Dst.getValueType(); 6608 EVT SrcVT = Src.getValueType(); 6609 EVT SizeVT = Size.getValueType(); 6610 Results.push_back(DAG.getMemcpy(Chain, dl, 6611 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6612 DAG.getConstant(Offset, DstVT)), 6613 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6614 DAG.getConstant(Offset, SrcVT)), 6615 DAG.getConstant(BytesLeft, SizeVT), 6616 Align, AlwaysInline, 6617 DstSV, DstSVOff + Offset, 6618 SrcSV, SrcSVOff + Offset)); 6619 } 6620 6621 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6622 &Results[0], Results.size()); 6623} 6624 6625SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6626 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6627 DebugLoc dl = Op.getDebugLoc(); 6628 6629 if (!Subtarget->is64Bit()) { 6630 // vastart just stores the address of the VarArgsFrameIndex slot into the 6631 // memory location argument. 6632 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6633 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6634 false, false, 0); 6635 } 6636 6637 // __va_list_tag: 6638 // gp_offset (0 - 6 * 8) 6639 // fp_offset (48 - 48 + 8 * 16) 6640 // overflow_arg_area (point to parameters coming in memory). 6641 // reg_save_area 6642 SmallVector<SDValue, 8> MemOps; 6643 SDValue FIN = Op.getOperand(1); 6644 // Store gp_offset 6645 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6646 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6647 FIN, SV, 0, false, false, 0); 6648 MemOps.push_back(Store); 6649 6650 // Store fp_offset 6651 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6652 FIN, DAG.getIntPtrConstant(4)); 6653 Store = DAG.getStore(Op.getOperand(0), dl, 6654 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6655 FIN, SV, 0, false, false, 0); 6656 MemOps.push_back(Store); 6657 6658 // Store ptr to overflow_arg_area 6659 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6660 FIN, DAG.getIntPtrConstant(4)); 6661 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6662 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0, 6663 false, false, 0); 6664 MemOps.push_back(Store); 6665 6666 // Store ptr to reg_save_area. 6667 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6668 FIN, DAG.getIntPtrConstant(8)); 6669 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6670 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0, 6671 false, false, 0); 6672 MemOps.push_back(Store); 6673 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6674 &MemOps[0], MemOps.size()); 6675} 6676 6677SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6678 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6679 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6680 SDValue Chain = Op.getOperand(0); 6681 SDValue SrcPtr = Op.getOperand(1); 6682 SDValue SrcSV = Op.getOperand(2); 6683 6684 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6685 return SDValue(); 6686} 6687 6688SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6689 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6690 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6691 SDValue Chain = Op.getOperand(0); 6692 SDValue DstPtr = Op.getOperand(1); 6693 SDValue SrcPtr = Op.getOperand(2); 6694 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6695 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6696 DebugLoc dl = Op.getDebugLoc(); 6697 6698 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6699 DAG.getIntPtrConstant(24), 8, false, 6700 DstSV, 0, SrcSV, 0); 6701} 6702 6703SDValue 6704X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6705 DebugLoc dl = Op.getDebugLoc(); 6706 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6707 switch (IntNo) { 6708 default: return SDValue(); // Don't custom lower most intrinsics. 6709 // Comparison intrinsics. 6710 case Intrinsic::x86_sse_comieq_ss: 6711 case Intrinsic::x86_sse_comilt_ss: 6712 case Intrinsic::x86_sse_comile_ss: 6713 case Intrinsic::x86_sse_comigt_ss: 6714 case Intrinsic::x86_sse_comige_ss: 6715 case Intrinsic::x86_sse_comineq_ss: 6716 case Intrinsic::x86_sse_ucomieq_ss: 6717 case Intrinsic::x86_sse_ucomilt_ss: 6718 case Intrinsic::x86_sse_ucomile_ss: 6719 case Intrinsic::x86_sse_ucomigt_ss: 6720 case Intrinsic::x86_sse_ucomige_ss: 6721 case Intrinsic::x86_sse_ucomineq_ss: 6722 case Intrinsic::x86_sse2_comieq_sd: 6723 case Intrinsic::x86_sse2_comilt_sd: 6724 case Intrinsic::x86_sse2_comile_sd: 6725 case Intrinsic::x86_sse2_comigt_sd: 6726 case Intrinsic::x86_sse2_comige_sd: 6727 case Intrinsic::x86_sse2_comineq_sd: 6728 case Intrinsic::x86_sse2_ucomieq_sd: 6729 case Intrinsic::x86_sse2_ucomilt_sd: 6730 case Intrinsic::x86_sse2_ucomile_sd: 6731 case Intrinsic::x86_sse2_ucomigt_sd: 6732 case Intrinsic::x86_sse2_ucomige_sd: 6733 case Intrinsic::x86_sse2_ucomineq_sd: { 6734 unsigned Opc = 0; 6735 ISD::CondCode CC = ISD::SETCC_INVALID; 6736 switch (IntNo) { 6737 default: break; 6738 case Intrinsic::x86_sse_comieq_ss: 6739 case Intrinsic::x86_sse2_comieq_sd: 6740 Opc = X86ISD::COMI; 6741 CC = ISD::SETEQ; 6742 break; 6743 case Intrinsic::x86_sse_comilt_ss: 6744 case Intrinsic::x86_sse2_comilt_sd: 6745 Opc = X86ISD::COMI; 6746 CC = ISD::SETLT; 6747 break; 6748 case Intrinsic::x86_sse_comile_ss: 6749 case Intrinsic::x86_sse2_comile_sd: 6750 Opc = X86ISD::COMI; 6751 CC = ISD::SETLE; 6752 break; 6753 case Intrinsic::x86_sse_comigt_ss: 6754 case Intrinsic::x86_sse2_comigt_sd: 6755 Opc = X86ISD::COMI; 6756 CC = ISD::SETGT; 6757 break; 6758 case Intrinsic::x86_sse_comige_ss: 6759 case Intrinsic::x86_sse2_comige_sd: 6760 Opc = X86ISD::COMI; 6761 CC = ISD::SETGE; 6762 break; 6763 case Intrinsic::x86_sse_comineq_ss: 6764 case Intrinsic::x86_sse2_comineq_sd: 6765 Opc = X86ISD::COMI; 6766 CC = ISD::SETNE; 6767 break; 6768 case Intrinsic::x86_sse_ucomieq_ss: 6769 case Intrinsic::x86_sse2_ucomieq_sd: 6770 Opc = X86ISD::UCOMI; 6771 CC = ISD::SETEQ; 6772 break; 6773 case Intrinsic::x86_sse_ucomilt_ss: 6774 case Intrinsic::x86_sse2_ucomilt_sd: 6775 Opc = X86ISD::UCOMI; 6776 CC = ISD::SETLT; 6777 break; 6778 case Intrinsic::x86_sse_ucomile_ss: 6779 case Intrinsic::x86_sse2_ucomile_sd: 6780 Opc = X86ISD::UCOMI; 6781 CC = ISD::SETLE; 6782 break; 6783 case Intrinsic::x86_sse_ucomigt_ss: 6784 case Intrinsic::x86_sse2_ucomigt_sd: 6785 Opc = X86ISD::UCOMI; 6786 CC = ISD::SETGT; 6787 break; 6788 case Intrinsic::x86_sse_ucomige_ss: 6789 case Intrinsic::x86_sse2_ucomige_sd: 6790 Opc = X86ISD::UCOMI; 6791 CC = ISD::SETGE; 6792 break; 6793 case Intrinsic::x86_sse_ucomineq_ss: 6794 case Intrinsic::x86_sse2_ucomineq_sd: 6795 Opc = X86ISD::UCOMI; 6796 CC = ISD::SETNE; 6797 break; 6798 } 6799 6800 SDValue LHS = Op.getOperand(1); 6801 SDValue RHS = Op.getOperand(2); 6802 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6803 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6804 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6805 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6806 DAG.getConstant(X86CC, MVT::i8), Cond); 6807 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6808 } 6809 // ptest intrinsics. The intrinsic these come from are designed to return 6810 // an integer value, not just an instruction so lower it to the ptest 6811 // pattern and a setcc for the result. 6812 case Intrinsic::x86_sse41_ptestz: 6813 case Intrinsic::x86_sse41_ptestc: 6814 case Intrinsic::x86_sse41_ptestnzc:{ 6815 unsigned X86CC = 0; 6816 switch (IntNo) { 6817 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6818 case Intrinsic::x86_sse41_ptestz: 6819 // ZF = 1 6820 X86CC = X86::COND_E; 6821 break; 6822 case Intrinsic::x86_sse41_ptestc: 6823 // CF = 1 6824 X86CC = X86::COND_B; 6825 break; 6826 case Intrinsic::x86_sse41_ptestnzc: 6827 // ZF and CF = 0 6828 X86CC = X86::COND_A; 6829 break; 6830 } 6831 6832 SDValue LHS = Op.getOperand(1); 6833 SDValue RHS = Op.getOperand(2); 6834 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6835 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6836 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6837 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6838 } 6839 6840 // Fix vector shift instructions where the last operand is a non-immediate 6841 // i32 value. 6842 case Intrinsic::x86_sse2_pslli_w: 6843 case Intrinsic::x86_sse2_pslli_d: 6844 case Intrinsic::x86_sse2_pslli_q: 6845 case Intrinsic::x86_sse2_psrli_w: 6846 case Intrinsic::x86_sse2_psrli_d: 6847 case Intrinsic::x86_sse2_psrli_q: 6848 case Intrinsic::x86_sse2_psrai_w: 6849 case Intrinsic::x86_sse2_psrai_d: 6850 case Intrinsic::x86_mmx_pslli_w: 6851 case Intrinsic::x86_mmx_pslli_d: 6852 case Intrinsic::x86_mmx_pslli_q: 6853 case Intrinsic::x86_mmx_psrli_w: 6854 case Intrinsic::x86_mmx_psrli_d: 6855 case Intrinsic::x86_mmx_psrli_q: 6856 case Intrinsic::x86_mmx_psrai_w: 6857 case Intrinsic::x86_mmx_psrai_d: { 6858 SDValue ShAmt = Op.getOperand(2); 6859 if (isa<ConstantSDNode>(ShAmt)) 6860 return SDValue(); 6861 6862 unsigned NewIntNo = 0; 6863 EVT ShAmtVT = MVT::v4i32; 6864 switch (IntNo) { 6865 case Intrinsic::x86_sse2_pslli_w: 6866 NewIntNo = Intrinsic::x86_sse2_psll_w; 6867 break; 6868 case Intrinsic::x86_sse2_pslli_d: 6869 NewIntNo = Intrinsic::x86_sse2_psll_d; 6870 break; 6871 case Intrinsic::x86_sse2_pslli_q: 6872 NewIntNo = Intrinsic::x86_sse2_psll_q; 6873 break; 6874 case Intrinsic::x86_sse2_psrli_w: 6875 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6876 break; 6877 case Intrinsic::x86_sse2_psrli_d: 6878 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6879 break; 6880 case Intrinsic::x86_sse2_psrli_q: 6881 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6882 break; 6883 case Intrinsic::x86_sse2_psrai_w: 6884 NewIntNo = Intrinsic::x86_sse2_psra_w; 6885 break; 6886 case Intrinsic::x86_sse2_psrai_d: 6887 NewIntNo = Intrinsic::x86_sse2_psra_d; 6888 break; 6889 default: { 6890 ShAmtVT = MVT::v2i32; 6891 switch (IntNo) { 6892 case Intrinsic::x86_mmx_pslli_w: 6893 NewIntNo = Intrinsic::x86_mmx_psll_w; 6894 break; 6895 case Intrinsic::x86_mmx_pslli_d: 6896 NewIntNo = Intrinsic::x86_mmx_psll_d; 6897 break; 6898 case Intrinsic::x86_mmx_pslli_q: 6899 NewIntNo = Intrinsic::x86_mmx_psll_q; 6900 break; 6901 case Intrinsic::x86_mmx_psrli_w: 6902 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6903 break; 6904 case Intrinsic::x86_mmx_psrli_d: 6905 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6906 break; 6907 case Intrinsic::x86_mmx_psrli_q: 6908 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6909 break; 6910 case Intrinsic::x86_mmx_psrai_w: 6911 NewIntNo = Intrinsic::x86_mmx_psra_w; 6912 break; 6913 case Intrinsic::x86_mmx_psrai_d: 6914 NewIntNo = Intrinsic::x86_mmx_psra_d; 6915 break; 6916 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6917 } 6918 break; 6919 } 6920 } 6921 6922 // The vector shift intrinsics with scalars uses 32b shift amounts but 6923 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 6924 // to be zero. 6925 SDValue ShOps[4]; 6926 ShOps[0] = ShAmt; 6927 ShOps[1] = DAG.getConstant(0, MVT::i32); 6928 if (ShAmtVT == MVT::v4i32) { 6929 ShOps[2] = DAG.getUNDEF(MVT::i32); 6930 ShOps[3] = DAG.getUNDEF(MVT::i32); 6931 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 6932 } else { 6933 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 6934 } 6935 6936 EVT VT = Op.getValueType(); 6937 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 6938 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6939 DAG.getConstant(NewIntNo, MVT::i32), 6940 Op.getOperand(1), ShAmt); 6941 } 6942 } 6943} 6944 6945SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6946 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6947 DebugLoc dl = Op.getDebugLoc(); 6948 6949 if (Depth > 0) { 6950 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6951 SDValue Offset = 6952 DAG.getConstant(TD->getPointerSize(), 6953 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6954 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6955 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6956 FrameAddr, Offset), 6957 NULL, 0, false, false, 0); 6958 } 6959 6960 // Just load the return address. 6961 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6962 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6963 RetAddrFI, NULL, 0, false, false, 0); 6964} 6965 6966SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6967 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6968 MFI->setFrameAddressIsTaken(true); 6969 EVT VT = Op.getValueType(); 6970 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6971 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6972 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6973 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6974 while (Depth--) 6975 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 6976 false, false, 0); 6977 return FrameAddr; 6978} 6979 6980SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6981 SelectionDAG &DAG) { 6982 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6983} 6984 6985SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6986{ 6987 MachineFunction &MF = DAG.getMachineFunction(); 6988 SDValue Chain = Op.getOperand(0); 6989 SDValue Offset = Op.getOperand(1); 6990 SDValue Handler = Op.getOperand(2); 6991 DebugLoc dl = Op.getDebugLoc(); 6992 6993 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6994 getPointerTy()); 6995 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6996 6997 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6998 DAG.getIntPtrConstant(-TD->getPointerSize())); 6999 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7000 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7001 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7002 MF.getRegInfo().addLiveOut(StoreAddrReg); 7003 7004 return DAG.getNode(X86ISD::EH_RETURN, dl, 7005 MVT::Other, 7006 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7007} 7008 7009SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7010 SelectionDAG &DAG) { 7011 SDValue Root = Op.getOperand(0); 7012 SDValue Trmp = Op.getOperand(1); // trampoline 7013 SDValue FPtr = Op.getOperand(2); // nested function 7014 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7015 DebugLoc dl = Op.getDebugLoc(); 7016 7017 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7018 7019 if (Subtarget->is64Bit()) { 7020 SDValue OutChains[6]; 7021 7022 // Large code-model. 7023 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7024 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7025 7026 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7027 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7028 7029 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7030 7031 // Load the pointer to the nested function into R11. 7032 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7033 SDValue Addr = Trmp; 7034 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7035 Addr, TrmpAddr, 0, false, false, 0); 7036 7037 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7038 DAG.getConstant(2, MVT::i64)); 7039 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7040 false, false, 2); 7041 7042 // Load the 'nest' parameter value into R10. 7043 // R10 is specified in X86CallingConv.td 7044 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7045 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7046 DAG.getConstant(10, MVT::i64)); 7047 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7048 Addr, TrmpAddr, 10, false, false, 0); 7049 7050 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7051 DAG.getConstant(12, MVT::i64)); 7052 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7053 false, false, 2); 7054 7055 // Jump to the nested function. 7056 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7058 DAG.getConstant(20, MVT::i64)); 7059 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7060 Addr, TrmpAddr, 20, false, false, 0); 7061 7062 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7063 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7064 DAG.getConstant(22, MVT::i64)); 7065 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7066 TrmpAddr, 22, false, false, 0); 7067 7068 SDValue Ops[] = 7069 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7070 return DAG.getMergeValues(Ops, 2, dl); 7071 } else { 7072 const Function *Func = 7073 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7074 CallingConv::ID CC = Func->getCallingConv(); 7075 unsigned NestReg; 7076 7077 switch (CC) { 7078 default: 7079 llvm_unreachable("Unsupported calling convention"); 7080 case CallingConv::C: 7081 case CallingConv::X86_StdCall: { 7082 // Pass 'nest' parameter in ECX. 7083 // Must be kept in sync with X86CallingConv.td 7084 NestReg = X86::ECX; 7085 7086 // Check that ECX wasn't needed by an 'inreg' parameter. 7087 const FunctionType *FTy = Func->getFunctionType(); 7088 const AttrListPtr &Attrs = Func->getAttributes(); 7089 7090 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7091 unsigned InRegCount = 0; 7092 unsigned Idx = 1; 7093 7094 for (FunctionType::param_iterator I = FTy->param_begin(), 7095 E = FTy->param_end(); I != E; ++I, ++Idx) 7096 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7097 // FIXME: should only count parameters that are lowered to integers. 7098 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7099 7100 if (InRegCount > 2) { 7101 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 7102 } 7103 } 7104 break; 7105 } 7106 case CallingConv::X86_FastCall: 7107 case CallingConv::Fast: 7108 // Pass 'nest' parameter in EAX. 7109 // Must be kept in sync with X86CallingConv.td 7110 NestReg = X86::EAX; 7111 break; 7112 } 7113 7114 SDValue OutChains[4]; 7115 SDValue Addr, Disp; 7116 7117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7118 DAG.getConstant(10, MVT::i32)); 7119 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7120 7121 // This is storing the opcode for MOV32ri. 7122 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7123 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7124 OutChains[0] = DAG.getStore(Root, dl, 7125 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7126 Trmp, TrmpAddr, 0, false, false, 0); 7127 7128 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7129 DAG.getConstant(1, MVT::i32)); 7130 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7131 false, false, 1); 7132 7133 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7134 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7135 DAG.getConstant(5, MVT::i32)); 7136 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7137 TrmpAddr, 5, false, false, 1); 7138 7139 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7140 DAG.getConstant(6, MVT::i32)); 7141 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7142 false, false, 1); 7143 7144 SDValue Ops[] = 7145 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7146 return DAG.getMergeValues(Ops, 2, dl); 7147 } 7148} 7149 7150SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 7151 /* 7152 The rounding mode is in bits 11:10 of FPSR, and has the following 7153 settings: 7154 00 Round to nearest 7155 01 Round to -inf 7156 10 Round to +inf 7157 11 Round to 0 7158 7159 FLT_ROUNDS, on the other hand, expects the following: 7160 -1 Undefined 7161 0 Round to 0 7162 1 Round to nearest 7163 2 Round to +inf 7164 3 Round to -inf 7165 7166 To perform the conversion, we do: 7167 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7168 */ 7169 7170 MachineFunction &MF = DAG.getMachineFunction(); 7171 const TargetMachine &TM = MF.getTarget(); 7172 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7173 unsigned StackAlignment = TFI.getStackAlignment(); 7174 EVT VT = Op.getValueType(); 7175 DebugLoc dl = Op.getDebugLoc(); 7176 7177 // Save FP Control Word to stack slot 7178 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7179 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7180 7181 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7182 DAG.getEntryNode(), StackSlot); 7183 7184 // Load FP Control Word from stack slot 7185 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7186 false, false, 0); 7187 7188 // Transform as necessary 7189 SDValue CWD1 = 7190 DAG.getNode(ISD::SRL, dl, MVT::i16, 7191 DAG.getNode(ISD::AND, dl, MVT::i16, 7192 CWD, DAG.getConstant(0x800, MVT::i16)), 7193 DAG.getConstant(11, MVT::i8)); 7194 SDValue CWD2 = 7195 DAG.getNode(ISD::SRL, dl, MVT::i16, 7196 DAG.getNode(ISD::AND, dl, MVT::i16, 7197 CWD, DAG.getConstant(0x400, MVT::i16)), 7198 DAG.getConstant(9, MVT::i8)); 7199 7200 SDValue RetVal = 7201 DAG.getNode(ISD::AND, dl, MVT::i16, 7202 DAG.getNode(ISD::ADD, dl, MVT::i16, 7203 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7204 DAG.getConstant(1, MVT::i16)), 7205 DAG.getConstant(3, MVT::i16)); 7206 7207 7208 return DAG.getNode((VT.getSizeInBits() < 16 ? 7209 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7210} 7211 7212SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 7213 EVT VT = Op.getValueType(); 7214 EVT OpVT = VT; 7215 unsigned NumBits = VT.getSizeInBits(); 7216 DebugLoc dl = Op.getDebugLoc(); 7217 7218 Op = Op.getOperand(0); 7219 if (VT == MVT::i8) { 7220 // Zero extend to i32 since there is not an i8 bsr. 7221 OpVT = MVT::i32; 7222 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7223 } 7224 7225 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7226 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7227 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7228 7229 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7230 SDValue Ops[] = { 7231 Op, 7232 DAG.getConstant(NumBits+NumBits-1, OpVT), 7233 DAG.getConstant(X86::COND_E, MVT::i8), 7234 Op.getValue(1) 7235 }; 7236 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7237 7238 // Finally xor with NumBits-1. 7239 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7240 7241 if (VT == MVT::i8) 7242 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7243 return Op; 7244} 7245 7246SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 7247 EVT VT = Op.getValueType(); 7248 EVT OpVT = VT; 7249 unsigned NumBits = VT.getSizeInBits(); 7250 DebugLoc dl = Op.getDebugLoc(); 7251 7252 Op = Op.getOperand(0); 7253 if (VT == MVT::i8) { 7254 OpVT = MVT::i32; 7255 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7256 } 7257 7258 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7259 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7260 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7261 7262 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7263 SDValue Ops[] = { 7264 Op, 7265 DAG.getConstant(NumBits, OpVT), 7266 DAG.getConstant(X86::COND_E, MVT::i8), 7267 Op.getValue(1) 7268 }; 7269 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7270 7271 if (VT == MVT::i8) 7272 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7273 return Op; 7274} 7275 7276SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 7277 EVT VT = Op.getValueType(); 7278 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7279 DebugLoc dl = Op.getDebugLoc(); 7280 7281 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7282 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7283 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7284 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7285 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7286 // 7287 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7288 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7289 // return AloBlo + AloBhi + AhiBlo; 7290 7291 SDValue A = Op.getOperand(0); 7292 SDValue B = Op.getOperand(1); 7293 7294 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7295 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7296 A, DAG.getConstant(32, MVT::i32)); 7297 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7298 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7299 B, DAG.getConstant(32, MVT::i32)); 7300 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7301 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7302 A, B); 7303 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7304 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7305 A, Bhi); 7306 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7307 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7308 Ahi, B); 7309 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7310 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7311 AloBhi, DAG.getConstant(32, MVT::i32)); 7312 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7313 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7314 AhiBlo, DAG.getConstant(32, MVT::i32)); 7315 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7316 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7317 return Res; 7318} 7319 7320 7321SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 7322 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7323 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7324 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7325 // has only one use. 7326 SDNode *N = Op.getNode(); 7327 SDValue LHS = N->getOperand(0); 7328 SDValue RHS = N->getOperand(1); 7329 unsigned BaseOp = 0; 7330 unsigned Cond = 0; 7331 DebugLoc dl = Op.getDebugLoc(); 7332 7333 switch (Op.getOpcode()) { 7334 default: llvm_unreachable("Unknown ovf instruction!"); 7335 case ISD::SADDO: 7336 // A subtract of one will be selected as a INC. Note that INC doesn't 7337 // set CF, so we can't do this for UADDO. 7338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7339 if (C->getAPIntValue() == 1) { 7340 BaseOp = X86ISD::INC; 7341 Cond = X86::COND_O; 7342 break; 7343 } 7344 BaseOp = X86ISD::ADD; 7345 Cond = X86::COND_O; 7346 break; 7347 case ISD::UADDO: 7348 BaseOp = X86ISD::ADD; 7349 Cond = X86::COND_B; 7350 break; 7351 case ISD::SSUBO: 7352 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7353 // set CF, so we can't do this for USUBO. 7354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7355 if (C->getAPIntValue() == 1) { 7356 BaseOp = X86ISD::DEC; 7357 Cond = X86::COND_O; 7358 break; 7359 } 7360 BaseOp = X86ISD::SUB; 7361 Cond = X86::COND_O; 7362 break; 7363 case ISD::USUBO: 7364 BaseOp = X86ISD::SUB; 7365 Cond = X86::COND_B; 7366 break; 7367 case ISD::SMULO: 7368 BaseOp = X86ISD::SMUL; 7369 Cond = X86::COND_O; 7370 break; 7371 case ISD::UMULO: 7372 BaseOp = X86ISD::UMUL; 7373 Cond = X86::COND_B; 7374 break; 7375 } 7376 7377 // Also sets EFLAGS. 7378 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7379 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7380 7381 SDValue SetCC = 7382 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7383 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7384 7385 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7386 return Sum; 7387} 7388 7389SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 7390 EVT T = Op.getValueType(); 7391 DebugLoc dl = Op.getDebugLoc(); 7392 unsigned Reg = 0; 7393 unsigned size = 0; 7394 switch(T.getSimpleVT().SimpleTy) { 7395 default: 7396 assert(false && "Invalid value type!"); 7397 case MVT::i8: Reg = X86::AL; size = 1; break; 7398 case MVT::i16: Reg = X86::AX; size = 2; break; 7399 case MVT::i32: Reg = X86::EAX; size = 4; break; 7400 case MVT::i64: 7401 assert(Subtarget->is64Bit() && "Node not type legal!"); 7402 Reg = X86::RAX; size = 8; 7403 break; 7404 } 7405 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7406 Op.getOperand(2), SDValue()); 7407 SDValue Ops[] = { cpIn.getValue(0), 7408 Op.getOperand(1), 7409 Op.getOperand(3), 7410 DAG.getTargetConstant(size, MVT::i8), 7411 cpIn.getValue(1) }; 7412 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7413 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7414 SDValue cpOut = 7415 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7416 return cpOut; 7417} 7418 7419SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7420 SelectionDAG &DAG) { 7421 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7422 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7423 SDValue TheChain = Op.getOperand(0); 7424 DebugLoc dl = Op.getDebugLoc(); 7425 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7426 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7427 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7428 rax.getValue(2)); 7429 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7430 DAG.getConstant(32, MVT::i8)); 7431 SDValue Ops[] = { 7432 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7433 rdx.getValue(1) 7434 }; 7435 return DAG.getMergeValues(Ops, 2, dl); 7436} 7437 7438SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 7439 SDNode *Node = Op.getNode(); 7440 DebugLoc dl = Node->getDebugLoc(); 7441 EVT T = Node->getValueType(0); 7442 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7443 DAG.getConstant(0, T), Node->getOperand(2)); 7444 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7445 cast<AtomicSDNode>(Node)->getMemoryVT(), 7446 Node->getOperand(0), 7447 Node->getOperand(1), negOp, 7448 cast<AtomicSDNode>(Node)->getSrcValue(), 7449 cast<AtomicSDNode>(Node)->getAlignment()); 7450} 7451 7452/// LowerOperation - Provide custom lowering hooks for some operations. 7453/// 7454SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 7455 switch (Op.getOpcode()) { 7456 default: llvm_unreachable("Should not custom lower this!"); 7457 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7458 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7459 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7460 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7461 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7462 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7463 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7464 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7465 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7466 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7467 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7468 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7469 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7470 case ISD::SHL_PARTS: 7471 case ISD::SRA_PARTS: 7472 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7473 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7474 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7475 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7476 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7477 case ISD::FABS: return LowerFABS(Op, DAG); 7478 case ISD::FNEG: return LowerFNEG(Op, DAG); 7479 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7480 case ISD::SETCC: return LowerSETCC(Op, DAG); 7481 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7482 case ISD::SELECT: return LowerSELECT(Op, DAG); 7483 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7484 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7485 case ISD::VASTART: return LowerVASTART(Op, DAG); 7486 case ISD::VAARG: return LowerVAARG(Op, DAG); 7487 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7488 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7489 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7490 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7491 case ISD::FRAME_TO_ARGS_OFFSET: 7492 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7493 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7494 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7495 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7496 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7497 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7498 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7499 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7500 case ISD::SADDO: 7501 case ISD::UADDO: 7502 case ISD::SSUBO: 7503 case ISD::USUBO: 7504 case ISD::SMULO: 7505 case ISD::UMULO: return LowerXALUO(Op, DAG); 7506 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7507 } 7508} 7509 7510void X86TargetLowering:: 7511ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7512 SelectionDAG &DAG, unsigned NewOp) { 7513 EVT T = Node->getValueType(0); 7514 DebugLoc dl = Node->getDebugLoc(); 7515 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7516 7517 SDValue Chain = Node->getOperand(0); 7518 SDValue In1 = Node->getOperand(1); 7519 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7520 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7521 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7522 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7523 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7524 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7525 SDValue Result = 7526 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7527 cast<MemSDNode>(Node)->getMemOperand()); 7528 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7530 Results.push_back(Result.getValue(2)); 7531} 7532 7533/// ReplaceNodeResults - Replace a node with an illegal result type 7534/// with a new node built out of custom code. 7535void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7536 SmallVectorImpl<SDValue>&Results, 7537 SelectionDAG &DAG) { 7538 DebugLoc dl = N->getDebugLoc(); 7539 switch (N->getOpcode()) { 7540 default: 7541 assert(false && "Do not know how to custom type legalize this operation!"); 7542 return; 7543 case ISD::FP_TO_SINT: { 7544 std::pair<SDValue,SDValue> Vals = 7545 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7546 SDValue FIST = Vals.first, StackSlot = Vals.second; 7547 if (FIST.getNode() != 0) { 7548 EVT VT = N->getValueType(0); 7549 // Return a load from the stack slot. 7550 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7551 false, false, 0)); 7552 } 7553 return; 7554 } 7555 case ISD::READCYCLECOUNTER: { 7556 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7557 SDValue TheChain = N->getOperand(0); 7558 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7559 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7560 rd.getValue(1)); 7561 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7562 eax.getValue(2)); 7563 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7564 SDValue Ops[] = { eax, edx }; 7565 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7566 Results.push_back(edx.getValue(1)); 7567 return; 7568 } 7569 case ISD::ATOMIC_CMP_SWAP: { 7570 EVT T = N->getValueType(0); 7571 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7572 SDValue cpInL, cpInH; 7573 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7574 DAG.getConstant(0, MVT::i32)); 7575 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7576 DAG.getConstant(1, MVT::i32)); 7577 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7578 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7579 cpInL.getValue(1)); 7580 SDValue swapInL, swapInH; 7581 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7582 DAG.getConstant(0, MVT::i32)); 7583 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7584 DAG.getConstant(1, MVT::i32)); 7585 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7586 cpInH.getValue(1)); 7587 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7588 swapInL.getValue(1)); 7589 SDValue Ops[] = { swapInH.getValue(0), 7590 N->getOperand(1), 7591 swapInH.getValue(1) }; 7592 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7593 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7594 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7595 MVT::i32, Result.getValue(1)); 7596 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7597 MVT::i32, cpOutL.getValue(2)); 7598 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7599 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7600 Results.push_back(cpOutH.getValue(1)); 7601 return; 7602 } 7603 case ISD::ATOMIC_LOAD_ADD: 7604 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7605 return; 7606 case ISD::ATOMIC_LOAD_AND: 7607 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7608 return; 7609 case ISD::ATOMIC_LOAD_NAND: 7610 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7611 return; 7612 case ISD::ATOMIC_LOAD_OR: 7613 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7614 return; 7615 case ISD::ATOMIC_LOAD_SUB: 7616 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7617 return; 7618 case ISD::ATOMIC_LOAD_XOR: 7619 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7620 return; 7621 case ISD::ATOMIC_SWAP: 7622 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7623 return; 7624 } 7625} 7626 7627const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7628 switch (Opcode) { 7629 default: return NULL; 7630 case X86ISD::BSF: return "X86ISD::BSF"; 7631 case X86ISD::BSR: return "X86ISD::BSR"; 7632 case X86ISD::SHLD: return "X86ISD::SHLD"; 7633 case X86ISD::SHRD: return "X86ISD::SHRD"; 7634 case X86ISD::FAND: return "X86ISD::FAND"; 7635 case X86ISD::FOR: return "X86ISD::FOR"; 7636 case X86ISD::FXOR: return "X86ISD::FXOR"; 7637 case X86ISD::FSRL: return "X86ISD::FSRL"; 7638 case X86ISD::FILD: return "X86ISD::FILD"; 7639 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7640 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7641 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7642 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7643 case X86ISD::FLD: return "X86ISD::FLD"; 7644 case X86ISD::FST: return "X86ISD::FST"; 7645 case X86ISD::CALL: return "X86ISD::CALL"; 7646 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7647 case X86ISD::BT: return "X86ISD::BT"; 7648 case X86ISD::CMP: return "X86ISD::CMP"; 7649 case X86ISD::COMI: return "X86ISD::COMI"; 7650 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7651 case X86ISD::SETCC: return "X86ISD::SETCC"; 7652 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7653 case X86ISD::CMOV: return "X86ISD::CMOV"; 7654 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7655 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7656 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7657 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7658 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7659 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7660 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7661 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7662 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7663 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7664 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7665 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7666 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7667 case X86ISD::FMAX: return "X86ISD::FMAX"; 7668 case X86ISD::FMIN: return "X86ISD::FMIN"; 7669 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7670 case X86ISD::FRCP: return "X86ISD::FRCP"; 7671 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7672 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7673 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7674 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7675 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7676 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7677 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7678 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7679 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7680 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7681 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7682 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7683 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7684 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7685 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7686 case X86ISD::VSHL: return "X86ISD::VSHL"; 7687 case X86ISD::VSRL: return "X86ISD::VSRL"; 7688 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7689 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7690 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7691 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7692 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7693 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7694 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7695 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7696 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7697 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7698 case X86ISD::ADD: return "X86ISD::ADD"; 7699 case X86ISD::SUB: return "X86ISD::SUB"; 7700 case X86ISD::SMUL: return "X86ISD::SMUL"; 7701 case X86ISD::UMUL: return "X86ISD::UMUL"; 7702 case X86ISD::INC: return "X86ISD::INC"; 7703 case X86ISD::DEC: return "X86ISD::DEC"; 7704 case X86ISD::OR: return "X86ISD::OR"; 7705 case X86ISD::XOR: return "X86ISD::XOR"; 7706 case X86ISD::AND: return "X86ISD::AND"; 7707 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7708 case X86ISD::PTEST: return "X86ISD::PTEST"; 7709 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7710 } 7711} 7712 7713// isLegalAddressingMode - Return true if the addressing mode represented 7714// by AM is legal for this target, for a load/store of the specified type. 7715bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7716 const Type *Ty) const { 7717 // X86 supports extremely general addressing modes. 7718 CodeModel::Model M = getTargetMachine().getCodeModel(); 7719 7720 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7721 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7722 return false; 7723 7724 if (AM.BaseGV) { 7725 unsigned GVFlags = 7726 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7727 7728 // If a reference to this global requires an extra load, we can't fold it. 7729 if (isGlobalStubReference(GVFlags)) 7730 return false; 7731 7732 // If BaseGV requires a register for the PIC base, we cannot also have a 7733 // BaseReg specified. 7734 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7735 return false; 7736 7737 // If lower 4G is not available, then we must use rip-relative addressing. 7738 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7739 return false; 7740 } 7741 7742 switch (AM.Scale) { 7743 case 0: 7744 case 1: 7745 case 2: 7746 case 4: 7747 case 8: 7748 // These scales always work. 7749 break; 7750 case 3: 7751 case 5: 7752 case 9: 7753 // These scales are formed with basereg+scalereg. Only accept if there is 7754 // no basereg yet. 7755 if (AM.HasBaseReg) 7756 return false; 7757 break; 7758 default: // Other stuff never works. 7759 return false; 7760 } 7761 7762 return true; 7763} 7764 7765 7766bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7767 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7768 return false; 7769 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7770 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7771 if (NumBits1 <= NumBits2) 7772 return false; 7773 return Subtarget->is64Bit() || NumBits1 < 64; 7774} 7775 7776bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7777 if (!VT1.isInteger() || !VT2.isInteger()) 7778 return false; 7779 unsigned NumBits1 = VT1.getSizeInBits(); 7780 unsigned NumBits2 = VT2.getSizeInBits(); 7781 if (NumBits1 <= NumBits2) 7782 return false; 7783 return Subtarget->is64Bit() || NumBits1 < 64; 7784} 7785 7786bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7787 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7788 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7789} 7790 7791bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7792 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7793 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7794} 7795 7796bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7797 // i16 instructions are longer (0x66 prefix) and potentially slower. 7798 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7799} 7800 7801/// isShuffleMaskLegal - Targets can use this to indicate that they only 7802/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7803/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7804/// are assumed to be legal. 7805bool 7806X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7807 EVT VT) const { 7808 // Only do shuffles on 128-bit vector types for now. 7809 if (VT.getSizeInBits() == 64) 7810 return false; 7811 7812 // FIXME: pshufb, blends, shifts. 7813 return (VT.getVectorNumElements() == 2 || 7814 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7815 isMOVLMask(M, VT) || 7816 isSHUFPMask(M, VT) || 7817 isPSHUFDMask(M, VT) || 7818 isPSHUFHWMask(M, VT) || 7819 isPSHUFLWMask(M, VT) || 7820 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 7821 isUNPCKLMask(M, VT) || 7822 isUNPCKHMask(M, VT) || 7823 isUNPCKL_v_undef_Mask(M, VT) || 7824 isUNPCKH_v_undef_Mask(M, VT)); 7825} 7826 7827bool 7828X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7829 EVT VT) const { 7830 unsigned NumElts = VT.getVectorNumElements(); 7831 // FIXME: This collection of masks seems suspect. 7832 if (NumElts == 2) 7833 return true; 7834 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7835 return (isMOVLMask(Mask, VT) || 7836 isCommutedMOVLMask(Mask, VT, true) || 7837 isSHUFPMask(Mask, VT) || 7838 isCommutedSHUFPMask(Mask, VT)); 7839 } 7840 return false; 7841} 7842 7843//===----------------------------------------------------------------------===// 7844// X86 Scheduler Hooks 7845//===----------------------------------------------------------------------===// 7846 7847// private utility function 7848MachineBasicBlock * 7849X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7850 MachineBasicBlock *MBB, 7851 unsigned regOpc, 7852 unsigned immOpc, 7853 unsigned LoadOpc, 7854 unsigned CXchgOpc, 7855 unsigned copyOpc, 7856 unsigned notOpc, 7857 unsigned EAXreg, 7858 TargetRegisterClass *RC, 7859 bool invSrc) const { 7860 // For the atomic bitwise operator, we generate 7861 // thisMBB: 7862 // newMBB: 7863 // ld t1 = [bitinstr.addr] 7864 // op t2 = t1, [bitinstr.val] 7865 // mov EAX = t1 7866 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7867 // bz newMBB 7868 // fallthrough -->nextMBB 7869 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7870 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7871 MachineFunction::iterator MBBIter = MBB; 7872 ++MBBIter; 7873 7874 /// First build the CFG 7875 MachineFunction *F = MBB->getParent(); 7876 MachineBasicBlock *thisMBB = MBB; 7877 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7878 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7879 F->insert(MBBIter, newMBB); 7880 F->insert(MBBIter, nextMBB); 7881 7882 // Move all successors to thisMBB to nextMBB 7883 nextMBB->transferSuccessors(thisMBB); 7884 7885 // Update thisMBB to fall through to newMBB 7886 thisMBB->addSuccessor(newMBB); 7887 7888 // newMBB jumps to itself and fall through to nextMBB 7889 newMBB->addSuccessor(nextMBB); 7890 newMBB->addSuccessor(newMBB); 7891 7892 // Insert instructions into newMBB based on incoming instruction 7893 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7894 "unexpected number of operands"); 7895 DebugLoc dl = bInstr->getDebugLoc(); 7896 MachineOperand& destOper = bInstr->getOperand(0); 7897 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7898 int numArgs = bInstr->getNumOperands() - 1; 7899 for (int i=0; i < numArgs; ++i) 7900 argOpers[i] = &bInstr->getOperand(i+1); 7901 7902 // x86 address has 4 operands: base, index, scale, and displacement 7903 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7904 int valArgIndx = lastAddrIndx + 1; 7905 7906 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7907 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7908 for (int i=0; i <= lastAddrIndx; ++i) 7909 (*MIB).addOperand(*argOpers[i]); 7910 7911 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7912 if (invSrc) { 7913 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7914 } 7915 else 7916 tt = t1; 7917 7918 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7919 assert((argOpers[valArgIndx]->isReg() || 7920 argOpers[valArgIndx]->isImm()) && 7921 "invalid operand"); 7922 if (argOpers[valArgIndx]->isReg()) 7923 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7924 else 7925 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7926 MIB.addReg(tt); 7927 (*MIB).addOperand(*argOpers[valArgIndx]); 7928 7929 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7930 MIB.addReg(t1); 7931 7932 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7933 for (int i=0; i <= lastAddrIndx; ++i) 7934 (*MIB).addOperand(*argOpers[i]); 7935 MIB.addReg(t2); 7936 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7937 (*MIB).setMemRefs(bInstr->memoperands_begin(), 7938 bInstr->memoperands_end()); 7939 7940 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7941 MIB.addReg(EAXreg); 7942 7943 // insert branch 7944 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 7945 7946 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7947 return nextMBB; 7948} 7949 7950// private utility function: 64 bit atomics on 32 bit host. 7951MachineBasicBlock * 7952X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7953 MachineBasicBlock *MBB, 7954 unsigned regOpcL, 7955 unsigned regOpcH, 7956 unsigned immOpcL, 7957 unsigned immOpcH, 7958 bool invSrc) const { 7959 // For the atomic bitwise operator, we generate 7960 // thisMBB (instructions are in pairs, except cmpxchg8b) 7961 // ld t1,t2 = [bitinstr.addr] 7962 // newMBB: 7963 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7964 // op t5, t6 <- out1, out2, [bitinstr.val] 7965 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7966 // mov ECX, EBX <- t5, t6 7967 // mov EAX, EDX <- t1, t2 7968 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7969 // mov t3, t4 <- EAX, EDX 7970 // bz newMBB 7971 // result in out1, out2 7972 // fallthrough -->nextMBB 7973 7974 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7975 const unsigned LoadOpc = X86::MOV32rm; 7976 const unsigned copyOpc = X86::MOV32rr; 7977 const unsigned NotOpc = X86::NOT32r; 7978 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7979 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7980 MachineFunction::iterator MBBIter = MBB; 7981 ++MBBIter; 7982 7983 /// First build the CFG 7984 MachineFunction *F = MBB->getParent(); 7985 MachineBasicBlock *thisMBB = MBB; 7986 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7987 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7988 F->insert(MBBIter, newMBB); 7989 F->insert(MBBIter, nextMBB); 7990 7991 // Move all successors to thisMBB to nextMBB 7992 nextMBB->transferSuccessors(thisMBB); 7993 7994 // Update thisMBB to fall through to newMBB 7995 thisMBB->addSuccessor(newMBB); 7996 7997 // newMBB jumps to itself and fall through to nextMBB 7998 newMBB->addSuccessor(nextMBB); 7999 newMBB->addSuccessor(newMBB); 8000 8001 DebugLoc dl = bInstr->getDebugLoc(); 8002 // Insert instructions into newMBB based on incoming instruction 8003 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8004 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 8005 "unexpected number of operands"); 8006 MachineOperand& dest1Oper = bInstr->getOperand(0); 8007 MachineOperand& dest2Oper = bInstr->getOperand(1); 8008 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8009 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 8010 argOpers[i] = &bInstr->getOperand(i+2); 8011 8012 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8013 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8014 8015 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8016 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8017 for (int i=0; i <= lastAddrIndx; ++i) 8018 (*MIB).addOperand(*argOpers[i]); 8019 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8020 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8021 // add 4 to displacement. 8022 for (int i=0; i <= lastAddrIndx-2; ++i) 8023 (*MIB).addOperand(*argOpers[i]); 8024 MachineOperand newOp3 = *(argOpers[3]); 8025 if (newOp3.isImm()) 8026 newOp3.setImm(newOp3.getImm()+4); 8027 else 8028 newOp3.setOffset(newOp3.getOffset()+4); 8029 (*MIB).addOperand(newOp3); 8030 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8031 8032 // t3/4 are defined later, at the bottom of the loop 8033 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8034 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8035 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8036 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8037 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8038 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8039 8040 // The subsequent operations should be using the destination registers of 8041 //the PHI instructions. 8042 if (invSrc) { 8043 t1 = F->getRegInfo().createVirtualRegister(RC); 8044 t2 = F->getRegInfo().createVirtualRegister(RC); 8045 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8046 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8047 } else { 8048 t1 = dest1Oper.getReg(); 8049 t2 = dest2Oper.getReg(); 8050 } 8051 8052 int valArgIndx = lastAddrIndx + 1; 8053 assert((argOpers[valArgIndx]->isReg() || 8054 argOpers[valArgIndx]->isImm()) && 8055 "invalid operand"); 8056 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8057 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8058 if (argOpers[valArgIndx]->isReg()) 8059 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8060 else 8061 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8062 if (regOpcL != X86::MOV32rr) 8063 MIB.addReg(t1); 8064 (*MIB).addOperand(*argOpers[valArgIndx]); 8065 assert(argOpers[valArgIndx + 1]->isReg() == 8066 argOpers[valArgIndx]->isReg()); 8067 assert(argOpers[valArgIndx + 1]->isImm() == 8068 argOpers[valArgIndx]->isImm()); 8069 if (argOpers[valArgIndx + 1]->isReg()) 8070 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8071 else 8072 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8073 if (regOpcH != X86::MOV32rr) 8074 MIB.addReg(t2); 8075 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8076 8077 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 8078 MIB.addReg(t1); 8079 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 8080 MIB.addReg(t2); 8081 8082 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 8083 MIB.addReg(t5); 8084 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 8085 MIB.addReg(t6); 8086 8087 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8088 for (int i=0; i <= lastAddrIndx; ++i) 8089 (*MIB).addOperand(*argOpers[i]); 8090 8091 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8092 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8093 bInstr->memoperands_end()); 8094 8095 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 8096 MIB.addReg(X86::EAX); 8097 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 8098 MIB.addReg(X86::EDX); 8099 8100 // insert branch 8101 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8102 8103 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8104 return nextMBB; 8105} 8106 8107// private utility function 8108MachineBasicBlock * 8109X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8110 MachineBasicBlock *MBB, 8111 unsigned cmovOpc) const { 8112 // For the atomic min/max operator, we generate 8113 // thisMBB: 8114 // newMBB: 8115 // ld t1 = [min/max.addr] 8116 // mov t2 = [min/max.val] 8117 // cmp t1, t2 8118 // cmov[cond] t2 = t1 8119 // mov EAX = t1 8120 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8121 // bz newMBB 8122 // fallthrough -->nextMBB 8123 // 8124 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8125 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8126 MachineFunction::iterator MBBIter = MBB; 8127 ++MBBIter; 8128 8129 /// First build the CFG 8130 MachineFunction *F = MBB->getParent(); 8131 MachineBasicBlock *thisMBB = MBB; 8132 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8133 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8134 F->insert(MBBIter, newMBB); 8135 F->insert(MBBIter, nextMBB); 8136 8137 // Move all successors of thisMBB to nextMBB 8138 nextMBB->transferSuccessors(thisMBB); 8139 8140 // Update thisMBB to fall through to newMBB 8141 thisMBB->addSuccessor(newMBB); 8142 8143 // newMBB jumps to newMBB and fall through to nextMBB 8144 newMBB->addSuccessor(nextMBB); 8145 newMBB->addSuccessor(newMBB); 8146 8147 DebugLoc dl = mInstr->getDebugLoc(); 8148 // Insert instructions into newMBB based on incoming instruction 8149 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 8150 "unexpected number of operands"); 8151 MachineOperand& destOper = mInstr->getOperand(0); 8152 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8153 int numArgs = mInstr->getNumOperands() - 1; 8154 for (int i=0; i < numArgs; ++i) 8155 argOpers[i] = &mInstr->getOperand(i+1); 8156 8157 // x86 address has 4 operands: base, index, scale, and displacement 8158 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8159 int valArgIndx = lastAddrIndx + 1; 8160 8161 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8162 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8163 for (int i=0; i <= lastAddrIndx; ++i) 8164 (*MIB).addOperand(*argOpers[i]); 8165 8166 // We only support register and immediate values 8167 assert((argOpers[valArgIndx]->isReg() || 8168 argOpers[valArgIndx]->isImm()) && 8169 "invalid operand"); 8170 8171 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8172 if (argOpers[valArgIndx]->isReg()) 8173 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8174 else 8175 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8176 (*MIB).addOperand(*argOpers[valArgIndx]); 8177 8178 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 8179 MIB.addReg(t1); 8180 8181 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8182 MIB.addReg(t1); 8183 MIB.addReg(t2); 8184 8185 // Generate movc 8186 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8187 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8188 MIB.addReg(t2); 8189 MIB.addReg(t1); 8190 8191 // Cmp and exchange if none has modified the memory location 8192 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8193 for (int i=0; i <= lastAddrIndx; ++i) 8194 (*MIB).addOperand(*argOpers[i]); 8195 MIB.addReg(t3); 8196 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8197 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8198 mInstr->memoperands_end()); 8199 8200 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 8201 MIB.addReg(X86::EAX); 8202 8203 // insert branch 8204 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8205 8206 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 8207 return nextMBB; 8208} 8209 8210// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8211// all of this code can be replaced with that in the .td file. 8212MachineBasicBlock * 8213X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8214 unsigned numArgs, bool memArg) const { 8215 8216 MachineFunction *F = BB->getParent(); 8217 DebugLoc dl = MI->getDebugLoc(); 8218 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8219 8220 unsigned Opc; 8221 if (memArg) 8222 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8223 else 8224 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8225 8226 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8227 8228 for (unsigned i = 0; i < numArgs; ++i) { 8229 MachineOperand &Op = MI->getOperand(i+1); 8230 8231 if (!(Op.isReg() && Op.isImplicit())) 8232 MIB.addOperand(Op); 8233 } 8234 8235 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8236 .addReg(X86::XMM0); 8237 8238 F->DeleteMachineInstr(MI); 8239 8240 return BB; 8241} 8242 8243MachineBasicBlock * 8244X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8245 MachineInstr *MI, 8246 MachineBasicBlock *MBB) const { 8247 // Emit code to save XMM registers to the stack. The ABI says that the 8248 // number of registers to save is given in %al, so it's theoretically 8249 // possible to do an indirect jump trick to avoid saving all of them, 8250 // however this code takes a simpler approach and just executes all 8251 // of the stores if %al is non-zero. It's less code, and it's probably 8252 // easier on the hardware branch predictor, and stores aren't all that 8253 // expensive anyway. 8254 8255 // Create the new basic blocks. One block contains all the XMM stores, 8256 // and one block is the final destination regardless of whether any 8257 // stores were performed. 8258 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8259 MachineFunction *F = MBB->getParent(); 8260 MachineFunction::iterator MBBIter = MBB; 8261 ++MBBIter; 8262 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8263 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8264 F->insert(MBBIter, XMMSaveMBB); 8265 F->insert(MBBIter, EndMBB); 8266 8267 // Set up the CFG. 8268 // Move any original successors of MBB to the end block. 8269 EndMBB->transferSuccessors(MBB); 8270 // The original block will now fall through to the XMM save block. 8271 MBB->addSuccessor(XMMSaveMBB); 8272 // The XMMSaveMBB will fall through to the end block. 8273 XMMSaveMBB->addSuccessor(EndMBB); 8274 8275 // Now add the instructions. 8276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8277 DebugLoc DL = MI->getDebugLoc(); 8278 8279 unsigned CountReg = MI->getOperand(0).getReg(); 8280 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8281 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8282 8283 if (!Subtarget->isTargetWin64()) { 8284 // If %al is 0, branch around the XMM save block. 8285 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8286 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8287 MBB->addSuccessor(EndMBB); 8288 } 8289 8290 // In the XMM save block, save all the XMM argument registers. 8291 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8292 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8293 MachineMemOperand *MMO = 8294 F->getMachineMemOperand( 8295 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8296 MachineMemOperand::MOStore, Offset, 8297 /*Size=*/16, /*Align=*/16); 8298 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8299 .addFrameIndex(RegSaveFrameIndex) 8300 .addImm(/*Scale=*/1) 8301 .addReg(/*IndexReg=*/0) 8302 .addImm(/*Disp=*/Offset) 8303 .addReg(/*Segment=*/0) 8304 .addReg(MI->getOperand(i).getReg()) 8305 .addMemOperand(MMO); 8306 } 8307 8308 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8309 8310 return EndMBB; 8311} 8312 8313MachineBasicBlock * 8314X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8315 MachineBasicBlock *BB, 8316 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8317 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8318 DebugLoc DL = MI->getDebugLoc(); 8319 8320 // To "insert" a SELECT_CC instruction, we actually have to insert the 8321 // diamond control-flow pattern. The incoming instruction knows the 8322 // destination vreg to set, the condition code register to branch on, the 8323 // true/false values to select between, and a branch opcode to use. 8324 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8325 MachineFunction::iterator It = BB; 8326 ++It; 8327 8328 // thisMBB: 8329 // ... 8330 // TrueVal = ... 8331 // cmpTY ccX, r1, r2 8332 // bCC copy1MBB 8333 // fallthrough --> copy0MBB 8334 MachineBasicBlock *thisMBB = BB; 8335 MachineFunction *F = BB->getParent(); 8336 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8337 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8338 unsigned Opc = 8339 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8340 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8341 F->insert(It, copy0MBB); 8342 F->insert(It, sinkMBB); 8343 // Update machine-CFG edges by first adding all successors of the current 8344 // block to the new block which will contain the Phi node for the select. 8345 // Also inform sdisel of the edge changes. 8346 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 8347 E = BB->succ_end(); I != E; ++I) { 8348 EM->insert(std::make_pair(*I, sinkMBB)); 8349 sinkMBB->addSuccessor(*I); 8350 } 8351 // Next, remove all successors of the current block, and add the true 8352 // and fallthrough blocks as its successors. 8353 while (!BB->succ_empty()) 8354 BB->removeSuccessor(BB->succ_begin()); 8355 // Add the true and fallthrough blocks as its successors. 8356 BB->addSuccessor(copy0MBB); 8357 BB->addSuccessor(sinkMBB); 8358 8359 // copy0MBB: 8360 // %FalseValue = ... 8361 // # fallthrough to sinkMBB 8362 BB = copy0MBB; 8363 8364 // Update machine-CFG edges 8365 BB->addSuccessor(sinkMBB); 8366 8367 // sinkMBB: 8368 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8369 // ... 8370 BB = sinkMBB; 8371 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 8372 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8373 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8374 8375 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8376 return BB; 8377} 8378 8379 8380MachineBasicBlock * 8381X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8382 MachineBasicBlock *BB, 8383 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8384 switch (MI->getOpcode()) { 8385 default: assert(false && "Unexpected instr type to insert"); 8386 case X86::CMOV_GR8: 8387 case X86::CMOV_V1I64: 8388 case X86::CMOV_FR32: 8389 case X86::CMOV_FR64: 8390 case X86::CMOV_V4F32: 8391 case X86::CMOV_V2F64: 8392 case X86::CMOV_V2I64: 8393 return EmitLoweredSelect(MI, BB, EM); 8394 8395 case X86::FP32_TO_INT16_IN_MEM: 8396 case X86::FP32_TO_INT32_IN_MEM: 8397 case X86::FP32_TO_INT64_IN_MEM: 8398 case X86::FP64_TO_INT16_IN_MEM: 8399 case X86::FP64_TO_INT32_IN_MEM: 8400 case X86::FP64_TO_INT64_IN_MEM: 8401 case X86::FP80_TO_INT16_IN_MEM: 8402 case X86::FP80_TO_INT32_IN_MEM: 8403 case X86::FP80_TO_INT64_IN_MEM: { 8404 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8405 DebugLoc DL = MI->getDebugLoc(); 8406 8407 // Change the floating point control register to use "round towards zero" 8408 // mode when truncating to an integer value. 8409 MachineFunction *F = BB->getParent(); 8410 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8411 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 8412 8413 // Load the old value of the high byte of the control word... 8414 unsigned OldCW = 8415 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8416 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 8417 CWFrameIdx); 8418 8419 // Set the high part to be round to zero... 8420 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8421 .addImm(0xC7F); 8422 8423 // Reload the modified control word now... 8424 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8425 8426 // Restore the memory image of control word to original value 8427 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8428 .addReg(OldCW); 8429 8430 // Get the X86 opcode to use. 8431 unsigned Opc; 8432 switch (MI->getOpcode()) { 8433 default: llvm_unreachable("illegal opcode!"); 8434 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8435 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8436 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8437 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8438 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8439 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8440 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8441 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8442 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8443 } 8444 8445 X86AddressMode AM; 8446 MachineOperand &Op = MI->getOperand(0); 8447 if (Op.isReg()) { 8448 AM.BaseType = X86AddressMode::RegBase; 8449 AM.Base.Reg = Op.getReg(); 8450 } else { 8451 AM.BaseType = X86AddressMode::FrameIndexBase; 8452 AM.Base.FrameIndex = Op.getIndex(); 8453 } 8454 Op = MI->getOperand(1); 8455 if (Op.isImm()) 8456 AM.Scale = Op.getImm(); 8457 Op = MI->getOperand(2); 8458 if (Op.isImm()) 8459 AM.IndexReg = Op.getImm(); 8460 Op = MI->getOperand(3); 8461 if (Op.isGlobal()) { 8462 AM.GV = Op.getGlobal(); 8463 } else { 8464 AM.Disp = Op.getImm(); 8465 } 8466 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 8467 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 8468 8469 // Reload the original control word now. 8470 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8471 8472 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8473 return BB; 8474 } 8475 // String/text processing lowering. 8476 case X86::PCMPISTRM128REG: 8477 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8478 case X86::PCMPISTRM128MEM: 8479 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8480 case X86::PCMPESTRM128REG: 8481 return EmitPCMP(MI, BB, 5, false /* in mem */); 8482 case X86::PCMPESTRM128MEM: 8483 return EmitPCMP(MI, BB, 5, true /* in mem */); 8484 8485 // Atomic Lowering. 8486 case X86::ATOMAND32: 8487 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8488 X86::AND32ri, X86::MOV32rm, 8489 X86::LCMPXCHG32, X86::MOV32rr, 8490 X86::NOT32r, X86::EAX, 8491 X86::GR32RegisterClass); 8492 case X86::ATOMOR32: 8493 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8494 X86::OR32ri, X86::MOV32rm, 8495 X86::LCMPXCHG32, X86::MOV32rr, 8496 X86::NOT32r, X86::EAX, 8497 X86::GR32RegisterClass); 8498 case X86::ATOMXOR32: 8499 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8500 X86::XOR32ri, X86::MOV32rm, 8501 X86::LCMPXCHG32, X86::MOV32rr, 8502 X86::NOT32r, X86::EAX, 8503 X86::GR32RegisterClass); 8504 case X86::ATOMNAND32: 8505 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8506 X86::AND32ri, X86::MOV32rm, 8507 X86::LCMPXCHG32, X86::MOV32rr, 8508 X86::NOT32r, X86::EAX, 8509 X86::GR32RegisterClass, true); 8510 case X86::ATOMMIN32: 8511 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8512 case X86::ATOMMAX32: 8513 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8514 case X86::ATOMUMIN32: 8515 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8516 case X86::ATOMUMAX32: 8517 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8518 8519 case X86::ATOMAND16: 8520 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8521 X86::AND16ri, X86::MOV16rm, 8522 X86::LCMPXCHG16, X86::MOV16rr, 8523 X86::NOT16r, X86::AX, 8524 X86::GR16RegisterClass); 8525 case X86::ATOMOR16: 8526 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8527 X86::OR16ri, X86::MOV16rm, 8528 X86::LCMPXCHG16, X86::MOV16rr, 8529 X86::NOT16r, X86::AX, 8530 X86::GR16RegisterClass); 8531 case X86::ATOMXOR16: 8532 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8533 X86::XOR16ri, X86::MOV16rm, 8534 X86::LCMPXCHG16, X86::MOV16rr, 8535 X86::NOT16r, X86::AX, 8536 X86::GR16RegisterClass); 8537 case X86::ATOMNAND16: 8538 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8539 X86::AND16ri, X86::MOV16rm, 8540 X86::LCMPXCHG16, X86::MOV16rr, 8541 X86::NOT16r, X86::AX, 8542 X86::GR16RegisterClass, true); 8543 case X86::ATOMMIN16: 8544 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8545 case X86::ATOMMAX16: 8546 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8547 case X86::ATOMUMIN16: 8548 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8549 case X86::ATOMUMAX16: 8550 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8551 8552 case X86::ATOMAND8: 8553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8554 X86::AND8ri, X86::MOV8rm, 8555 X86::LCMPXCHG8, X86::MOV8rr, 8556 X86::NOT8r, X86::AL, 8557 X86::GR8RegisterClass); 8558 case X86::ATOMOR8: 8559 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8560 X86::OR8ri, X86::MOV8rm, 8561 X86::LCMPXCHG8, X86::MOV8rr, 8562 X86::NOT8r, X86::AL, 8563 X86::GR8RegisterClass); 8564 case X86::ATOMXOR8: 8565 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8566 X86::XOR8ri, X86::MOV8rm, 8567 X86::LCMPXCHG8, X86::MOV8rr, 8568 X86::NOT8r, X86::AL, 8569 X86::GR8RegisterClass); 8570 case X86::ATOMNAND8: 8571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8572 X86::AND8ri, X86::MOV8rm, 8573 X86::LCMPXCHG8, X86::MOV8rr, 8574 X86::NOT8r, X86::AL, 8575 X86::GR8RegisterClass, true); 8576 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8577 // This group is for 64-bit host. 8578 case X86::ATOMAND64: 8579 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8580 X86::AND64ri32, X86::MOV64rm, 8581 X86::LCMPXCHG64, X86::MOV64rr, 8582 X86::NOT64r, X86::RAX, 8583 X86::GR64RegisterClass); 8584 case X86::ATOMOR64: 8585 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8586 X86::OR64ri32, X86::MOV64rm, 8587 X86::LCMPXCHG64, X86::MOV64rr, 8588 X86::NOT64r, X86::RAX, 8589 X86::GR64RegisterClass); 8590 case X86::ATOMXOR64: 8591 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8592 X86::XOR64ri32, X86::MOV64rm, 8593 X86::LCMPXCHG64, X86::MOV64rr, 8594 X86::NOT64r, X86::RAX, 8595 X86::GR64RegisterClass); 8596 case X86::ATOMNAND64: 8597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8598 X86::AND64ri32, X86::MOV64rm, 8599 X86::LCMPXCHG64, X86::MOV64rr, 8600 X86::NOT64r, X86::RAX, 8601 X86::GR64RegisterClass, true); 8602 case X86::ATOMMIN64: 8603 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8604 case X86::ATOMMAX64: 8605 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8606 case X86::ATOMUMIN64: 8607 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8608 case X86::ATOMUMAX64: 8609 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8610 8611 // This group does 64-bit operations on a 32-bit host. 8612 case X86::ATOMAND6432: 8613 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8614 X86::AND32rr, X86::AND32rr, 8615 X86::AND32ri, X86::AND32ri, 8616 false); 8617 case X86::ATOMOR6432: 8618 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8619 X86::OR32rr, X86::OR32rr, 8620 X86::OR32ri, X86::OR32ri, 8621 false); 8622 case X86::ATOMXOR6432: 8623 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8624 X86::XOR32rr, X86::XOR32rr, 8625 X86::XOR32ri, X86::XOR32ri, 8626 false); 8627 case X86::ATOMNAND6432: 8628 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8629 X86::AND32rr, X86::AND32rr, 8630 X86::AND32ri, X86::AND32ri, 8631 true); 8632 case X86::ATOMADD6432: 8633 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8634 X86::ADD32rr, X86::ADC32rr, 8635 X86::ADD32ri, X86::ADC32ri, 8636 false); 8637 case X86::ATOMSUB6432: 8638 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8639 X86::SUB32rr, X86::SBB32rr, 8640 X86::SUB32ri, X86::SBB32ri, 8641 false); 8642 case X86::ATOMSWAP6432: 8643 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8644 X86::MOV32rr, X86::MOV32rr, 8645 X86::MOV32ri, X86::MOV32ri, 8646 false); 8647 case X86::VASTART_SAVE_XMM_REGS: 8648 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8649 } 8650} 8651 8652//===----------------------------------------------------------------------===// 8653// X86 Optimization Hooks 8654//===----------------------------------------------------------------------===// 8655 8656void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8657 const APInt &Mask, 8658 APInt &KnownZero, 8659 APInt &KnownOne, 8660 const SelectionDAG &DAG, 8661 unsigned Depth) const { 8662 unsigned Opc = Op.getOpcode(); 8663 assert((Opc >= ISD::BUILTIN_OP_END || 8664 Opc == ISD::INTRINSIC_WO_CHAIN || 8665 Opc == ISD::INTRINSIC_W_CHAIN || 8666 Opc == ISD::INTRINSIC_VOID) && 8667 "Should use MaskedValueIsZero if you don't know whether Op" 8668 " is a target node!"); 8669 8670 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8671 switch (Opc) { 8672 default: break; 8673 case X86ISD::ADD: 8674 case X86ISD::SUB: 8675 case X86ISD::SMUL: 8676 case X86ISD::UMUL: 8677 case X86ISD::INC: 8678 case X86ISD::DEC: 8679 case X86ISD::OR: 8680 case X86ISD::XOR: 8681 case X86ISD::AND: 8682 // These nodes' second result is a boolean. 8683 if (Op.getResNo() == 0) 8684 break; 8685 // Fallthrough 8686 case X86ISD::SETCC: 8687 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8688 Mask.getBitWidth() - 1); 8689 break; 8690 } 8691} 8692 8693/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8694/// node is a GlobalAddress + offset. 8695bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8696 GlobalValue* &GA, int64_t &Offset) const{ 8697 if (N->getOpcode() == X86ISD::Wrapper) { 8698 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8699 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8700 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8701 return true; 8702 } 8703 } 8704 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8705} 8706 8707static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 8708 EVT EltVT, LoadSDNode *&LDBase, 8709 unsigned &LastLoadedElt, 8710 SelectionDAG &DAG, MachineFrameInfo *MFI, 8711 const TargetLowering &TLI) { 8712 LDBase = NULL; 8713 LastLoadedElt = -1U; 8714 for (unsigned i = 0; i < NumElems; ++i) { 8715 if (N->getMaskElt(i) < 0) { 8716 if (!LDBase) 8717 return false; 8718 continue; 8719 } 8720 8721 SDValue Elt = DAG.getShuffleScalarElt(N, i); 8722 if (!Elt.getNode() || 8723 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 8724 return false; 8725 if (!LDBase) { 8726 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 8727 return false; 8728 LDBase = cast<LoadSDNode>(Elt.getNode()); 8729 LastLoadedElt = i; 8730 continue; 8731 } 8732 if (Elt.getOpcode() == ISD::UNDEF) 8733 continue; 8734 8735 LoadSDNode *LD = cast<LoadSDNode>(Elt); 8736 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 8737 return false; 8738 LastLoadedElt = i; 8739 } 8740 return true; 8741} 8742 8743/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8744/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8745/// if the load addresses are consecutive, non-overlapping, and in the right 8746/// order. In the case of v2i64, it will see if it can rewrite the 8747/// shuffle to be an appropriate build vector so it can take advantage of 8748// performBuildVectorCombine. 8749static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8750 const TargetLowering &TLI) { 8751 DebugLoc dl = N->getDebugLoc(); 8752 EVT VT = N->getValueType(0); 8753 EVT EltVT = VT.getVectorElementType(); 8754 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8755 unsigned NumElems = VT.getVectorNumElements(); 8756 8757 if (VT.getSizeInBits() != 128) 8758 return SDValue(); 8759 8760 // Try to combine a vector_shuffle into a 128-bit load. 8761 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8762 LoadSDNode *LD = NULL; 8763 unsigned LastLoadedElt; 8764 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG, 8765 MFI, TLI)) 8766 return SDValue(); 8767 8768 if (LastLoadedElt == NumElems - 1) { 8769 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16) 8770 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8771 LD->getSrcValue(), LD->getSrcValueOffset(), 8772 LD->isVolatile(), LD->isNonTemporal(), 0); 8773 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8774 LD->getSrcValue(), LD->getSrcValueOffset(), 8775 LD->isVolatile(), LD->isNonTemporal(), 8776 LD->getAlignment()); 8777 } else if (NumElems == 4 && LastLoadedElt == 1) { 8778 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 8779 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 8780 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 8781 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 8782 } 8783 return SDValue(); 8784} 8785 8786/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8787static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8788 const X86Subtarget *Subtarget) { 8789 DebugLoc DL = N->getDebugLoc(); 8790 SDValue Cond = N->getOperand(0); 8791 // Get the LHS/RHS of the select. 8792 SDValue LHS = N->getOperand(1); 8793 SDValue RHS = N->getOperand(2); 8794 8795 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 8796 // instructions have the peculiarity that if either operand is a NaN, 8797 // they chose what we call the RHS operand (and as such are not symmetric). 8798 // It happens that this matches the semantics of the common C idiom 8799 // x<y?x:y and related forms, so we can recognize these cases. 8800 if (Subtarget->hasSSE2() && 8801 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8802 Cond.getOpcode() == ISD::SETCC) { 8803 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8804 8805 unsigned Opcode = 0; 8806 // Check for x CC y ? x : y. 8807 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 8808 switch (CC) { 8809 default: break; 8810 case ISD::SETULT: 8811 // This can be a min if we can prove that at least one of the operands 8812 // is not a nan. 8813 if (!FiniteOnlyFPMath()) { 8814 if (DAG.isKnownNeverNaN(RHS)) { 8815 // Put the potential NaN in the RHS so that SSE will preserve it. 8816 std::swap(LHS, RHS); 8817 } else if (!DAG.isKnownNeverNaN(LHS)) 8818 break; 8819 } 8820 Opcode = X86ISD::FMIN; 8821 break; 8822 case ISD::SETOLE: 8823 // This can be a min if we can prove that at least one of the operands 8824 // is not a nan. 8825 if (!FiniteOnlyFPMath()) { 8826 if (DAG.isKnownNeverNaN(LHS)) { 8827 // Put the potential NaN in the RHS so that SSE will preserve it. 8828 std::swap(LHS, RHS); 8829 } else if (!DAG.isKnownNeverNaN(RHS)) 8830 break; 8831 } 8832 Opcode = X86ISD::FMIN; 8833 break; 8834 case ISD::SETULE: 8835 // This can be a min, but if either operand is a NaN we need it to 8836 // preserve the original LHS. 8837 std::swap(LHS, RHS); 8838 case ISD::SETOLT: 8839 case ISD::SETLT: 8840 case ISD::SETLE: 8841 Opcode = X86ISD::FMIN; 8842 break; 8843 8844 case ISD::SETOGE: 8845 // This can be a max if we can prove that at least one of the operands 8846 // is not a nan. 8847 if (!FiniteOnlyFPMath()) { 8848 if (DAG.isKnownNeverNaN(LHS)) { 8849 // Put the potential NaN in the RHS so that SSE will preserve it. 8850 std::swap(LHS, RHS); 8851 } else if (!DAG.isKnownNeverNaN(RHS)) 8852 break; 8853 } 8854 Opcode = X86ISD::FMAX; 8855 break; 8856 case ISD::SETUGT: 8857 // This can be a max if we can prove that at least one of the operands 8858 // is not a nan. 8859 if (!FiniteOnlyFPMath()) { 8860 if (DAG.isKnownNeverNaN(RHS)) { 8861 // Put the potential NaN in the RHS so that SSE will preserve it. 8862 std::swap(LHS, RHS); 8863 } else if (!DAG.isKnownNeverNaN(LHS)) 8864 break; 8865 } 8866 Opcode = X86ISD::FMAX; 8867 break; 8868 case ISD::SETUGE: 8869 // This can be a max, but if either operand is a NaN we need it to 8870 // preserve the original LHS. 8871 std::swap(LHS, RHS); 8872 case ISD::SETOGT: 8873 case ISD::SETGT: 8874 case ISD::SETGE: 8875 Opcode = X86ISD::FMAX; 8876 break; 8877 } 8878 // Check for x CC y ? y : x -- a min/max with reversed arms. 8879 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8880 switch (CC) { 8881 default: break; 8882 case ISD::SETOGE: 8883 // This can be a min if we can prove that at least one of the operands 8884 // is not a nan. 8885 if (!FiniteOnlyFPMath()) { 8886 if (DAG.isKnownNeverNaN(RHS)) { 8887 // Put the potential NaN in the RHS so that SSE will preserve it. 8888 std::swap(LHS, RHS); 8889 } else if (!DAG.isKnownNeverNaN(LHS)) 8890 break; 8891 } 8892 Opcode = X86ISD::FMIN; 8893 break; 8894 case ISD::SETUGT: 8895 // This can be a min if we can prove that at least one of the operands 8896 // is not a nan. 8897 if (!FiniteOnlyFPMath()) { 8898 if (DAG.isKnownNeverNaN(LHS)) { 8899 // Put the potential NaN in the RHS so that SSE will preserve it. 8900 std::swap(LHS, RHS); 8901 } else if (!DAG.isKnownNeverNaN(RHS)) 8902 break; 8903 } 8904 Opcode = X86ISD::FMIN; 8905 break; 8906 case ISD::SETUGE: 8907 // This can be a min, but if either operand is a NaN we need it to 8908 // preserve the original LHS. 8909 std::swap(LHS, RHS); 8910 case ISD::SETOGT: 8911 case ISD::SETGT: 8912 case ISD::SETGE: 8913 Opcode = X86ISD::FMIN; 8914 break; 8915 8916 case ISD::SETULT: 8917 // This can be a max if we can prove that at least one of the operands 8918 // is not a nan. 8919 if (!FiniteOnlyFPMath()) { 8920 if (DAG.isKnownNeverNaN(LHS)) { 8921 // Put the potential NaN in the RHS so that SSE will preserve it. 8922 std::swap(LHS, RHS); 8923 } else if (!DAG.isKnownNeverNaN(RHS)) 8924 break; 8925 } 8926 Opcode = X86ISD::FMAX; 8927 break; 8928 case ISD::SETOLE: 8929 // This can be a max if we can prove that at least one of the operands 8930 // is not a nan. 8931 if (!FiniteOnlyFPMath()) { 8932 if (DAG.isKnownNeverNaN(RHS)) { 8933 // Put the potential NaN in the RHS so that SSE will preserve it. 8934 std::swap(LHS, RHS); 8935 } else if (!DAG.isKnownNeverNaN(LHS)) 8936 break; 8937 } 8938 Opcode = X86ISD::FMAX; 8939 break; 8940 case ISD::SETULE: 8941 // This can be a max, but if either operand is a NaN we need it to 8942 // preserve the original LHS. 8943 std::swap(LHS, RHS); 8944 case ISD::SETOLT: 8945 case ISD::SETLT: 8946 case ISD::SETLE: 8947 Opcode = X86ISD::FMAX; 8948 break; 8949 } 8950 } 8951 8952 if (Opcode) 8953 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 8954 } 8955 8956 // If this is a select between two integer constants, try to do some 8957 // optimizations. 8958 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 8959 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 8960 // Don't do this for crazy integer types. 8961 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 8962 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 8963 // so that TrueC (the true value) is larger than FalseC. 8964 bool NeedsCondInvert = false; 8965 8966 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 8967 // Efficiently invertible. 8968 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 8969 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 8970 isa<ConstantSDNode>(Cond.getOperand(1))))) { 8971 NeedsCondInvert = true; 8972 std::swap(TrueC, FalseC); 8973 } 8974 8975 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 8976 if (FalseC->getAPIntValue() == 0 && 8977 TrueC->getAPIntValue().isPowerOf2()) { 8978 if (NeedsCondInvert) // Invert the condition if needed. 8979 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8980 DAG.getConstant(1, Cond.getValueType())); 8981 8982 // Zero extend the condition if needed. 8983 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 8984 8985 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8986 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 8987 DAG.getConstant(ShAmt, MVT::i8)); 8988 } 8989 8990 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 8991 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8992 if (NeedsCondInvert) // Invert the condition if needed. 8993 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8994 DAG.getConstant(1, Cond.getValueType())); 8995 8996 // Zero extend the condition if needed. 8997 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8998 FalseC->getValueType(0), Cond); 8999 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9000 SDValue(FalseC, 0)); 9001 } 9002 9003 // Optimize cases that will turn into an LEA instruction. This requires 9004 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9005 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9006 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9007 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9008 9009 bool isFastMultiplier = false; 9010 if (Diff < 10) { 9011 switch ((unsigned char)Diff) { 9012 default: break; 9013 case 1: // result = add base, cond 9014 case 2: // result = lea base( , cond*2) 9015 case 3: // result = lea base(cond, cond*2) 9016 case 4: // result = lea base( , cond*4) 9017 case 5: // result = lea base(cond, cond*4) 9018 case 8: // result = lea base( , cond*8) 9019 case 9: // result = lea base(cond, cond*8) 9020 isFastMultiplier = true; 9021 break; 9022 } 9023 } 9024 9025 if (isFastMultiplier) { 9026 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9027 if (NeedsCondInvert) // Invert the condition if needed. 9028 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9029 DAG.getConstant(1, Cond.getValueType())); 9030 9031 // Zero extend the condition if needed. 9032 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9033 Cond); 9034 // Scale the condition by the difference. 9035 if (Diff != 1) 9036 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9037 DAG.getConstant(Diff, Cond.getValueType())); 9038 9039 // Add the base if non-zero. 9040 if (FalseC->getAPIntValue() != 0) 9041 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9042 SDValue(FalseC, 0)); 9043 return Cond; 9044 } 9045 } 9046 } 9047 } 9048 9049 return SDValue(); 9050} 9051 9052/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9053static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9054 TargetLowering::DAGCombinerInfo &DCI) { 9055 DebugLoc DL = N->getDebugLoc(); 9056 9057 // If the flag operand isn't dead, don't touch this CMOV. 9058 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9059 return SDValue(); 9060 9061 // If this is a select between two integer constants, try to do some 9062 // optimizations. Note that the operands are ordered the opposite of SELECT 9063 // operands. 9064 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9065 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9066 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9067 // larger than FalseC (the false value). 9068 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9069 9070 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9071 CC = X86::GetOppositeBranchCondition(CC); 9072 std::swap(TrueC, FalseC); 9073 } 9074 9075 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9076 // This is efficient for any integer data type (including i8/i16) and 9077 // shift amount. 9078 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9079 SDValue Cond = N->getOperand(3); 9080 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9081 DAG.getConstant(CC, MVT::i8), Cond); 9082 9083 // Zero extend the condition if needed. 9084 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9085 9086 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9087 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9088 DAG.getConstant(ShAmt, MVT::i8)); 9089 if (N->getNumValues() == 2) // Dead flag value? 9090 return DCI.CombineTo(N, Cond, SDValue()); 9091 return Cond; 9092 } 9093 9094 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9095 // for any integer data type, including i8/i16. 9096 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9097 SDValue Cond = N->getOperand(3); 9098 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9099 DAG.getConstant(CC, MVT::i8), Cond); 9100 9101 // Zero extend the condition if needed. 9102 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9103 FalseC->getValueType(0), Cond); 9104 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9105 SDValue(FalseC, 0)); 9106 9107 if (N->getNumValues() == 2) // Dead flag value? 9108 return DCI.CombineTo(N, Cond, SDValue()); 9109 return Cond; 9110 } 9111 9112 // Optimize cases that will turn into an LEA instruction. This requires 9113 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9114 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9115 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9116 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9117 9118 bool isFastMultiplier = false; 9119 if (Diff < 10) { 9120 switch ((unsigned char)Diff) { 9121 default: break; 9122 case 1: // result = add base, cond 9123 case 2: // result = lea base( , cond*2) 9124 case 3: // result = lea base(cond, cond*2) 9125 case 4: // result = lea base( , cond*4) 9126 case 5: // result = lea base(cond, cond*4) 9127 case 8: // result = lea base( , cond*8) 9128 case 9: // result = lea base(cond, cond*8) 9129 isFastMultiplier = true; 9130 break; 9131 } 9132 } 9133 9134 if (isFastMultiplier) { 9135 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9136 SDValue Cond = N->getOperand(3); 9137 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9138 DAG.getConstant(CC, MVT::i8), Cond); 9139 // Zero extend the condition if needed. 9140 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9141 Cond); 9142 // Scale the condition by the difference. 9143 if (Diff != 1) 9144 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9145 DAG.getConstant(Diff, Cond.getValueType())); 9146 9147 // Add the base if non-zero. 9148 if (FalseC->getAPIntValue() != 0) 9149 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9150 SDValue(FalseC, 0)); 9151 if (N->getNumValues() == 2) // Dead flag value? 9152 return DCI.CombineTo(N, Cond, SDValue()); 9153 return Cond; 9154 } 9155 } 9156 } 9157 } 9158 return SDValue(); 9159} 9160 9161/// PerformANDCombine - Look for SSE and instructions of this form: 9162/// (and x, (build_vector c1,c2,c3,c4)). If there exists a use of a build_vector 9163/// that's the bitwise complement of the mask, then transform the node to 9164/// (and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)). 9165static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 9166 TargetLowering::DAGCombinerInfo &DCI) { 9167 EVT VT = N->getValueType(0); 9168 if (!VT.isVector() || !VT.isInteger()) 9169 return SDValue(); 9170 9171 SDValue N0 = N->getOperand(0); 9172 SDValue N1 = N->getOperand(1); 9173 if (N0.getOpcode() == ISD::XOR || !N1.hasOneUse()) 9174 return SDValue(); 9175 9176 if (N1.getOpcode() == ISD::BUILD_VECTOR) { 9177 unsigned NumElts = VT.getVectorNumElements(); 9178 EVT EltVT = VT.getVectorElementType(); 9179 SmallVector<SDValue, 8> Mask; 9180 Mask.reserve(NumElts); 9181 for (unsigned i = 0; i != NumElts; ++i) { 9182 SDValue Arg = N1.getOperand(i); 9183 if (Arg.getOpcode() == ISD::UNDEF) { 9184 Mask.push_back(Arg); 9185 continue; 9186 } 9187 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Arg); 9188 if (!C) return SDValue(); 9189 Mask.push_back(DAG.getConstant(~C->getAPIntValue(), EltVT)); 9190 } 9191 N1 = DAG.getNode(ISD::BUILD_VECTOR, N1.getDebugLoc(), VT, 9192 &Mask[0], NumElts); 9193 if (!N1.use_empty()) { 9194 unsigned Bits = EltVT.getSizeInBits(); 9195 Mask.clear(); 9196 for (unsigned i = 0; i != NumElts; ++i) 9197 Mask.push_back(DAG.getConstant(APInt::getAllOnesValue(Bits), EltVT)); 9198 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9199 VT, &Mask[0], NumElts); 9200 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9201 DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 9202 N0, NewMask), N1); 9203 } 9204 } 9205 9206 return SDValue(); 9207} 9208 9209/// PerformMulCombine - Optimize a single multiply with constant into two 9210/// in order to implement it with two cheaper instructions, e.g. 9211/// LEA + SHL, LEA + LEA. 9212static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9213 TargetLowering::DAGCombinerInfo &DCI) { 9214 if (DAG.getMachineFunction(). 9215 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 9216 return SDValue(); 9217 9218 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9219 return SDValue(); 9220 9221 EVT VT = N->getValueType(0); 9222 if (VT != MVT::i64) 9223 return SDValue(); 9224 9225 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9226 if (!C) 9227 return SDValue(); 9228 uint64_t MulAmt = C->getZExtValue(); 9229 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9230 return SDValue(); 9231 9232 uint64_t MulAmt1 = 0; 9233 uint64_t MulAmt2 = 0; 9234 if ((MulAmt % 9) == 0) { 9235 MulAmt1 = 9; 9236 MulAmt2 = MulAmt / 9; 9237 } else if ((MulAmt % 5) == 0) { 9238 MulAmt1 = 5; 9239 MulAmt2 = MulAmt / 5; 9240 } else if ((MulAmt % 3) == 0) { 9241 MulAmt1 = 3; 9242 MulAmt2 = MulAmt / 3; 9243 } 9244 if (MulAmt2 && 9245 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9246 DebugLoc DL = N->getDebugLoc(); 9247 9248 if (isPowerOf2_64(MulAmt2) && 9249 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9250 // If second multiplifer is pow2, issue it first. We want the multiply by 9251 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9252 // is an add. 9253 std::swap(MulAmt1, MulAmt2); 9254 9255 SDValue NewMul; 9256 if (isPowerOf2_64(MulAmt1)) 9257 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9258 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9259 else 9260 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9261 DAG.getConstant(MulAmt1, VT)); 9262 9263 if (isPowerOf2_64(MulAmt2)) 9264 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9265 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9266 else 9267 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9268 DAG.getConstant(MulAmt2, VT)); 9269 9270 // Do not add new nodes to DAG combiner worklist. 9271 DCI.CombineTo(N, NewMul, false); 9272 } 9273 return SDValue(); 9274} 9275 9276static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9277 SDValue N0 = N->getOperand(0); 9278 SDValue N1 = N->getOperand(1); 9279 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9280 EVT VT = N0.getValueType(); 9281 9282 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9283 // since the result of setcc_c is all zero's or all ones. 9284 if (N1C && N0.getOpcode() == ISD::AND && 9285 N0.getOperand(1).getOpcode() == ISD::Constant) { 9286 SDValue N00 = N0.getOperand(0); 9287 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9288 ((N00.getOpcode() == ISD::ANY_EXTEND || 9289 N00.getOpcode() == ISD::ZERO_EXTEND) && 9290 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9291 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9292 APInt ShAmt = N1C->getAPIntValue(); 9293 Mask = Mask.shl(ShAmt); 9294 if (Mask != 0) 9295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9296 N00, DAG.getConstant(Mask, VT)); 9297 } 9298 } 9299 9300 return SDValue(); 9301} 9302 9303/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9304/// when possible. 9305static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9306 const X86Subtarget *Subtarget) { 9307 EVT VT = N->getValueType(0); 9308 if (!VT.isVector() && VT.isInteger() && 9309 N->getOpcode() == ISD::SHL) 9310 return PerformSHLCombine(N, DAG); 9311 9312 // On X86 with SSE2 support, we can transform this to a vector shift if 9313 // all elements are shifted by the same amount. We can't do this in legalize 9314 // because the a constant vector is typically transformed to a constant pool 9315 // so we have no knowledge of the shift amount. 9316 if (!Subtarget->hasSSE2()) 9317 return SDValue(); 9318 9319 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9320 return SDValue(); 9321 9322 SDValue ShAmtOp = N->getOperand(1); 9323 EVT EltVT = VT.getVectorElementType(); 9324 DebugLoc DL = N->getDebugLoc(); 9325 SDValue BaseShAmt = SDValue(); 9326 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9327 unsigned NumElts = VT.getVectorNumElements(); 9328 unsigned i = 0; 9329 for (; i != NumElts; ++i) { 9330 SDValue Arg = ShAmtOp.getOperand(i); 9331 if (Arg.getOpcode() == ISD::UNDEF) continue; 9332 BaseShAmt = Arg; 9333 break; 9334 } 9335 for (; i != NumElts; ++i) { 9336 SDValue Arg = ShAmtOp.getOperand(i); 9337 if (Arg.getOpcode() == ISD::UNDEF) continue; 9338 if (Arg != BaseShAmt) { 9339 return SDValue(); 9340 } 9341 } 9342 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9343 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9344 SDValue InVec = ShAmtOp.getOperand(0); 9345 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9346 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9347 unsigned i = 0; 9348 for (; i != NumElts; ++i) { 9349 SDValue Arg = InVec.getOperand(i); 9350 if (Arg.getOpcode() == ISD::UNDEF) continue; 9351 BaseShAmt = Arg; 9352 break; 9353 } 9354 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9356 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9357 if (C->getZExtValue() == SplatIdx) 9358 BaseShAmt = InVec.getOperand(1); 9359 } 9360 } 9361 if (BaseShAmt.getNode() == 0) 9362 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9363 DAG.getIntPtrConstant(0)); 9364 } else 9365 return SDValue(); 9366 9367 // The shift amount is an i32. 9368 if (EltVT.bitsGT(MVT::i32)) 9369 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9370 else if (EltVT.bitsLT(MVT::i32)) 9371 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9372 9373 // The shift amount is identical so we can do a vector shift. 9374 SDValue ValOp = N->getOperand(0); 9375 switch (N->getOpcode()) { 9376 default: 9377 llvm_unreachable("Unknown shift opcode!"); 9378 break; 9379 case ISD::SHL: 9380 if (VT == MVT::v2i64) 9381 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9382 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9383 ValOp, BaseShAmt); 9384 if (VT == MVT::v4i32) 9385 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9386 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9387 ValOp, BaseShAmt); 9388 if (VT == MVT::v8i16) 9389 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9390 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9391 ValOp, BaseShAmt); 9392 break; 9393 case ISD::SRA: 9394 if (VT == MVT::v4i32) 9395 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9396 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9397 ValOp, BaseShAmt); 9398 if (VT == MVT::v8i16) 9399 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9400 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9401 ValOp, BaseShAmt); 9402 break; 9403 case ISD::SRL: 9404 if (VT == MVT::v2i64) 9405 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9406 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9407 ValOp, BaseShAmt); 9408 if (VT == MVT::v4i32) 9409 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9410 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9411 ValOp, BaseShAmt); 9412 if (VT == MVT::v8i16) 9413 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9414 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9415 ValOp, BaseShAmt); 9416 break; 9417 } 9418 return SDValue(); 9419} 9420 9421static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9422 const X86Subtarget *Subtarget) { 9423 EVT VT = N->getValueType(0); 9424 if (VT != MVT::i64 || !Subtarget->is64Bit()) 9425 return SDValue(); 9426 9427 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9428 SDValue N0 = N->getOperand(0); 9429 SDValue N1 = N->getOperand(1); 9430 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9431 std::swap(N0, N1); 9432 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9433 return SDValue(); 9434 9435 SDValue ShAmt0 = N0.getOperand(1); 9436 if (ShAmt0.getValueType() != MVT::i8) 9437 return SDValue(); 9438 SDValue ShAmt1 = N1.getOperand(1); 9439 if (ShAmt1.getValueType() != MVT::i8) 9440 return SDValue(); 9441 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9442 ShAmt0 = ShAmt0.getOperand(0); 9443 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9444 ShAmt1 = ShAmt1.getOperand(0); 9445 9446 DebugLoc DL = N->getDebugLoc(); 9447 unsigned Opc = X86ISD::SHLD; 9448 SDValue Op0 = N0.getOperand(0); 9449 SDValue Op1 = N1.getOperand(0); 9450 if (ShAmt0.getOpcode() == ISD::SUB) { 9451 Opc = X86ISD::SHRD; 9452 std::swap(Op0, Op1); 9453 std::swap(ShAmt0, ShAmt1); 9454 } 9455 9456 if (ShAmt1.getOpcode() == ISD::SUB) { 9457 SDValue Sum = ShAmt1.getOperand(0); 9458 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9459 if (SumC->getSExtValue() == 64 && 9460 ShAmt1.getOperand(1) == ShAmt0) 9461 return DAG.getNode(Opc, DL, VT, 9462 Op0, Op1, 9463 DAG.getNode(ISD::TRUNCATE, DL, 9464 MVT::i8, ShAmt0)); 9465 } 9466 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9467 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9468 if (ShAmt0C && 9469 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64) 9470 return DAG.getNode(Opc, DL, VT, 9471 N0.getOperand(0), N1.getOperand(0), 9472 DAG.getNode(ISD::TRUNCATE, DL, 9473 MVT::i8, ShAmt0)); 9474 } 9475 9476 return SDValue(); 9477} 9478 9479/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9480static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9481 const X86Subtarget *Subtarget) { 9482 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9483 // the FP state in cases where an emms may be missing. 9484 // A preferable solution to the general problem is to figure out the right 9485 // places to insert EMMS. This qualifies as a quick hack. 9486 9487 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9488 StoreSDNode *St = cast<StoreSDNode>(N); 9489 EVT VT = St->getValue().getValueType(); 9490 if (VT.getSizeInBits() != 64) 9491 return SDValue(); 9492 9493 const Function *F = DAG.getMachineFunction().getFunction(); 9494 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9495 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9496 && Subtarget->hasSSE2(); 9497 if ((VT.isVector() || 9498 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9499 isa<LoadSDNode>(St->getValue()) && 9500 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9501 St->getChain().hasOneUse() && !St->isVolatile()) { 9502 SDNode* LdVal = St->getValue().getNode(); 9503 LoadSDNode *Ld = 0; 9504 int TokenFactorIndex = -1; 9505 SmallVector<SDValue, 8> Ops; 9506 SDNode* ChainVal = St->getChain().getNode(); 9507 // Must be a store of a load. We currently handle two cases: the load 9508 // is a direct child, and it's under an intervening TokenFactor. It is 9509 // possible to dig deeper under nested TokenFactors. 9510 if (ChainVal == LdVal) 9511 Ld = cast<LoadSDNode>(St->getChain()); 9512 else if (St->getValue().hasOneUse() && 9513 ChainVal->getOpcode() == ISD::TokenFactor) { 9514 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9515 if (ChainVal->getOperand(i).getNode() == LdVal) { 9516 TokenFactorIndex = i; 9517 Ld = cast<LoadSDNode>(St->getValue()); 9518 } else 9519 Ops.push_back(ChainVal->getOperand(i)); 9520 } 9521 } 9522 9523 if (!Ld || !ISD::isNormalLoad(Ld)) 9524 return SDValue(); 9525 9526 // If this is not the MMX case, i.e. we are just turning i64 load/store 9527 // into f64 load/store, avoid the transformation if there are multiple 9528 // uses of the loaded value. 9529 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9530 return SDValue(); 9531 9532 DebugLoc LdDL = Ld->getDebugLoc(); 9533 DebugLoc StDL = N->getDebugLoc(); 9534 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9535 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9536 // pair instead. 9537 if (Subtarget->is64Bit() || F64IsLegal) { 9538 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9539 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9540 Ld->getBasePtr(), Ld->getSrcValue(), 9541 Ld->getSrcValueOffset(), Ld->isVolatile(), 9542 Ld->isNonTemporal(), Ld->getAlignment()); 9543 SDValue NewChain = NewLd.getValue(1); 9544 if (TokenFactorIndex != -1) { 9545 Ops.push_back(NewChain); 9546 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9547 Ops.size()); 9548 } 9549 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9550 St->getSrcValue(), St->getSrcValueOffset(), 9551 St->isVolatile(), St->isNonTemporal(), 9552 St->getAlignment()); 9553 } 9554 9555 // Otherwise, lower to two pairs of 32-bit loads / stores. 9556 SDValue LoAddr = Ld->getBasePtr(); 9557 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9558 DAG.getConstant(4, MVT::i32)); 9559 9560 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9561 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9562 Ld->isVolatile(), Ld->isNonTemporal(), 9563 Ld->getAlignment()); 9564 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9565 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9566 Ld->isVolatile(), Ld->isNonTemporal(), 9567 MinAlign(Ld->getAlignment(), 4)); 9568 9569 SDValue NewChain = LoLd.getValue(1); 9570 if (TokenFactorIndex != -1) { 9571 Ops.push_back(LoLd); 9572 Ops.push_back(HiLd); 9573 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9574 Ops.size()); 9575 } 9576 9577 LoAddr = St->getBasePtr(); 9578 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9579 DAG.getConstant(4, MVT::i32)); 9580 9581 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9582 St->getSrcValue(), St->getSrcValueOffset(), 9583 St->isVolatile(), St->isNonTemporal(), 9584 St->getAlignment()); 9585 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9586 St->getSrcValue(), 9587 St->getSrcValueOffset() + 4, 9588 St->isVolatile(), 9589 St->isNonTemporal(), 9590 MinAlign(St->getAlignment(), 4)); 9591 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9592 } 9593 return SDValue(); 9594} 9595 9596/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9597/// X86ISD::FXOR nodes. 9598static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9599 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9600 // F[X]OR(0.0, x) -> x 9601 // F[X]OR(x, 0.0) -> x 9602 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9603 if (C->getValueAPF().isPosZero()) 9604 return N->getOperand(1); 9605 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9606 if (C->getValueAPF().isPosZero()) 9607 return N->getOperand(0); 9608 return SDValue(); 9609} 9610 9611/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9612static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9613 // FAND(0.0, x) -> 0.0 9614 // FAND(x, 0.0) -> 0.0 9615 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9616 if (C->getValueAPF().isPosZero()) 9617 return N->getOperand(0); 9618 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9619 if (C->getValueAPF().isPosZero()) 9620 return N->getOperand(1); 9621 return SDValue(); 9622} 9623 9624static SDValue PerformBTCombine(SDNode *N, 9625 SelectionDAG &DAG, 9626 TargetLowering::DAGCombinerInfo &DCI) { 9627 // BT ignores high bits in the bit index operand. 9628 SDValue Op1 = N->getOperand(1); 9629 if (Op1.hasOneUse()) { 9630 unsigned BitWidth = Op1.getValueSizeInBits(); 9631 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9632 APInt KnownZero, KnownOne; 9633 TargetLowering::TargetLoweringOpt TLO(DAG); 9634 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9635 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9636 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9637 DCI.CommitTargetLoweringOpt(TLO); 9638 } 9639 return SDValue(); 9640} 9641 9642static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9643 SDValue Op = N->getOperand(0); 9644 if (Op.getOpcode() == ISD::BIT_CONVERT) 9645 Op = Op.getOperand(0); 9646 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9647 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9648 VT.getVectorElementType().getSizeInBits() == 9649 OpVT.getVectorElementType().getSizeInBits()) { 9650 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9651 } 9652 return SDValue(); 9653} 9654 9655// On X86 and X86-64, atomic operations are lowered to locked instructions. 9656// Locked instructions, in turn, have implicit fence semantics (all memory 9657// operations are flushed before issuing the locked instruction, and the 9658// are not buffered), so we can fold away the common pattern of 9659// fence-atomic-fence. 9660static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 9661 SDValue atomic = N->getOperand(0); 9662 switch (atomic.getOpcode()) { 9663 case ISD::ATOMIC_CMP_SWAP: 9664 case ISD::ATOMIC_SWAP: 9665 case ISD::ATOMIC_LOAD_ADD: 9666 case ISD::ATOMIC_LOAD_SUB: 9667 case ISD::ATOMIC_LOAD_AND: 9668 case ISD::ATOMIC_LOAD_OR: 9669 case ISD::ATOMIC_LOAD_XOR: 9670 case ISD::ATOMIC_LOAD_NAND: 9671 case ISD::ATOMIC_LOAD_MIN: 9672 case ISD::ATOMIC_LOAD_MAX: 9673 case ISD::ATOMIC_LOAD_UMIN: 9674 case ISD::ATOMIC_LOAD_UMAX: 9675 break; 9676 default: 9677 return SDValue(); 9678 } 9679 9680 SDValue fence = atomic.getOperand(0); 9681 if (fence.getOpcode() != ISD::MEMBARRIER) 9682 return SDValue(); 9683 9684 switch (atomic.getOpcode()) { 9685 case ISD::ATOMIC_CMP_SWAP: 9686 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9687 atomic.getOperand(1), atomic.getOperand(2), 9688 atomic.getOperand(3)); 9689 case ISD::ATOMIC_SWAP: 9690 case ISD::ATOMIC_LOAD_ADD: 9691 case ISD::ATOMIC_LOAD_SUB: 9692 case ISD::ATOMIC_LOAD_AND: 9693 case ISD::ATOMIC_LOAD_OR: 9694 case ISD::ATOMIC_LOAD_XOR: 9695 case ISD::ATOMIC_LOAD_NAND: 9696 case ISD::ATOMIC_LOAD_MIN: 9697 case ISD::ATOMIC_LOAD_MAX: 9698 case ISD::ATOMIC_LOAD_UMIN: 9699 case ISD::ATOMIC_LOAD_UMAX: 9700 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9701 atomic.getOperand(1), atomic.getOperand(2)); 9702 default: 9703 return SDValue(); 9704 } 9705} 9706 9707static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9708 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9709 // (and (i32 x86isd::setcc_carry), 1) 9710 // This eliminates the zext. This transformation is necessary because 9711 // ISD::SETCC is always legalized to i8. 9712 DebugLoc dl = N->getDebugLoc(); 9713 SDValue N0 = N->getOperand(0); 9714 EVT VT = N->getValueType(0); 9715 if (N0.getOpcode() == ISD::AND && 9716 N0.hasOneUse() && 9717 N0.getOperand(0).hasOneUse()) { 9718 SDValue N00 = N0.getOperand(0); 9719 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9720 return SDValue(); 9721 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9722 if (!C || C->getZExtValue() != 1) 9723 return SDValue(); 9724 return DAG.getNode(ISD::AND, dl, VT, 9725 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9726 N00.getOperand(0), N00.getOperand(1)), 9727 DAG.getConstant(1, VT)); 9728 } 9729 9730 return SDValue(); 9731} 9732 9733SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9734 DAGCombinerInfo &DCI) const { 9735 SelectionDAG &DAG = DCI.DAG; 9736 switch (N->getOpcode()) { 9737 default: break; 9738 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9739 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9740 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9741 case ISD::AND: return PerformANDCombine(N, DAG, DCI); 9742 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9743 case ISD::SHL: 9744 case ISD::SRA: 9745 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9746 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget); 9747 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9748 case X86ISD::FXOR: 9749 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9750 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9751 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9752 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9753 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9754 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9755 } 9756 9757 return SDValue(); 9758} 9759 9760//===----------------------------------------------------------------------===// 9761// X86 Inline Assembly Support 9762//===----------------------------------------------------------------------===// 9763 9764static bool LowerToBSwap(CallInst *CI) { 9765 // FIXME: this should verify that we are targetting a 486 or better. If not, 9766 // we will turn this bswap into something that will be lowered to logical ops 9767 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9768 // so don't worry about this. 9769 9770 // Verify this is a simple bswap. 9771 if (CI->getNumOperands() != 2 || 9772 CI->getType() != CI->getOperand(1)->getType() || 9773 !CI->getType()->isIntegerTy()) 9774 return false; 9775 9776 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9777 if (!Ty || Ty->getBitWidth() % 16 != 0) 9778 return false; 9779 9780 // Okay, we can do this xform, do so now. 9781 const Type *Tys[] = { Ty }; 9782 Module *M = CI->getParent()->getParent()->getParent(); 9783 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9784 9785 Value *Op = CI->getOperand(1); 9786 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9787 9788 CI->replaceAllUsesWith(Op); 9789 CI->eraseFromParent(); 9790 return true; 9791} 9792 9793bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9794 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9795 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9796 9797 std::string AsmStr = IA->getAsmString(); 9798 9799 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9800 SmallVector<StringRef, 4> AsmPieces; 9801 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9802 9803 switch (AsmPieces.size()) { 9804 default: return false; 9805 case 1: 9806 AsmStr = AsmPieces[0]; 9807 AsmPieces.clear(); 9808 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9809 9810 // bswap $0 9811 if (AsmPieces.size() == 2 && 9812 (AsmPieces[0] == "bswap" || 9813 AsmPieces[0] == "bswapq" || 9814 AsmPieces[0] == "bswapl") && 9815 (AsmPieces[1] == "$0" || 9816 AsmPieces[1] == "${0:q}")) { 9817 // No need to check constraints, nothing other than the equivalent of 9818 // "=r,0" would be valid here. 9819 return LowerToBSwap(CI); 9820 } 9821 // rorw $$8, ${0:w} --> llvm.bswap.i16 9822 if (CI->getType()->isIntegerTy(16) && 9823 AsmPieces.size() == 3 && 9824 AsmPieces[0] == "rorw" && 9825 AsmPieces[1] == "$$8," && 9826 AsmPieces[2] == "${0:w}" && 9827 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") { 9828 return LowerToBSwap(CI); 9829 } 9830 break; 9831 case 3: 9832 if (CI->getType()->isIntegerTy(64) && 9833 Constraints.size() >= 2 && 9834 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9835 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9836 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9837 SmallVector<StringRef, 4> Words; 9838 SplitString(AsmPieces[0], Words, " \t"); 9839 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9840 Words.clear(); 9841 SplitString(AsmPieces[1], Words, " \t"); 9842 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9843 Words.clear(); 9844 SplitString(AsmPieces[2], Words, " \t,"); 9845 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 9846 Words[2] == "%edx") { 9847 return LowerToBSwap(CI); 9848 } 9849 } 9850 } 9851 } 9852 break; 9853 } 9854 return false; 9855} 9856 9857 9858 9859/// getConstraintType - Given a constraint letter, return the type of 9860/// constraint it is for this target. 9861X86TargetLowering::ConstraintType 9862X86TargetLowering::getConstraintType(const std::string &Constraint) const { 9863 if (Constraint.size() == 1) { 9864 switch (Constraint[0]) { 9865 case 'A': 9866 return C_Register; 9867 case 'f': 9868 case 'r': 9869 case 'R': 9870 case 'l': 9871 case 'q': 9872 case 'Q': 9873 case 'x': 9874 case 'y': 9875 case 'Y': 9876 return C_RegisterClass; 9877 case 'e': 9878 case 'Z': 9879 return C_Other; 9880 default: 9881 break; 9882 } 9883 } 9884 return TargetLowering::getConstraintType(Constraint); 9885} 9886 9887/// LowerXConstraint - try to replace an X constraint, which matches anything, 9888/// with another that has more specific requirements based on the type of the 9889/// corresponding operand. 9890const char *X86TargetLowering:: 9891LowerXConstraint(EVT ConstraintVT) const { 9892 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 9893 // 'f' like normal targets. 9894 if (ConstraintVT.isFloatingPoint()) { 9895 if (Subtarget->hasSSE2()) 9896 return "Y"; 9897 if (Subtarget->hasSSE1()) 9898 return "x"; 9899 } 9900 9901 return TargetLowering::LowerXConstraint(ConstraintVT); 9902} 9903 9904/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 9905/// vector. If it is invalid, don't add anything to Ops. 9906void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 9907 char Constraint, 9908 bool hasMemory, 9909 std::vector<SDValue>&Ops, 9910 SelectionDAG &DAG) const { 9911 SDValue Result(0, 0); 9912 9913 switch (Constraint) { 9914 default: break; 9915 case 'I': 9916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9917 if (C->getZExtValue() <= 31) { 9918 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9919 break; 9920 } 9921 } 9922 return; 9923 case 'J': 9924 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9925 if (C->getZExtValue() <= 63) { 9926 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9927 break; 9928 } 9929 } 9930 return; 9931 case 'K': 9932 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9933 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 9934 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9935 break; 9936 } 9937 } 9938 return; 9939 case 'N': 9940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9941 if (C->getZExtValue() <= 255) { 9942 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9943 break; 9944 } 9945 } 9946 return; 9947 case 'e': { 9948 // 32-bit signed value 9949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9950 const ConstantInt *CI = C->getConstantIntValue(); 9951 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9952 C->getSExtValue())) { 9953 // Widen to 64 bits here to get it sign extended. 9954 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 9955 break; 9956 } 9957 // FIXME gcc accepts some relocatable values here too, but only in certain 9958 // memory models; it's complicated. 9959 } 9960 return; 9961 } 9962 case 'Z': { 9963 // 32-bit unsigned value 9964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9965 const ConstantInt *CI = C->getConstantIntValue(); 9966 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9967 C->getZExtValue())) { 9968 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9969 break; 9970 } 9971 } 9972 // FIXME gcc accepts some relocatable values here too, but only in certain 9973 // memory models; it's complicated. 9974 return; 9975 } 9976 case 'i': { 9977 // Literal immediates are always ok. 9978 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 9979 // Widen to 64 bits here to get it sign extended. 9980 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 9981 break; 9982 } 9983 9984 // If we are in non-pic codegen mode, we allow the address of a global (with 9985 // an optional displacement) to be used with 'i'. 9986 GlobalAddressSDNode *GA = 0; 9987 int64_t Offset = 0; 9988 9989 // Match either (GA), (GA+C), (GA+C1+C2), etc. 9990 while (1) { 9991 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 9992 Offset += GA->getOffset(); 9993 break; 9994 } else if (Op.getOpcode() == ISD::ADD) { 9995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9996 Offset += C->getZExtValue(); 9997 Op = Op.getOperand(0); 9998 continue; 9999 } 10000 } else if (Op.getOpcode() == ISD::SUB) { 10001 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10002 Offset += -C->getZExtValue(); 10003 Op = Op.getOperand(0); 10004 continue; 10005 } 10006 } 10007 10008 // Otherwise, this isn't something we can handle, reject it. 10009 return; 10010 } 10011 10012 GlobalValue *GV = GA->getGlobal(); 10013 // If we require an extra load to get this address, as in PIC mode, we 10014 // can't accept it. 10015 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10016 getTargetMachine()))) 10017 return; 10018 10019 if (hasMemory) 10020 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 10021 else 10022 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 10023 Result = Op; 10024 break; 10025 } 10026 } 10027 10028 if (Result.getNode()) { 10029 Ops.push_back(Result); 10030 return; 10031 } 10032 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 10033 Ops, DAG); 10034} 10035 10036std::vector<unsigned> X86TargetLowering:: 10037getRegClassForInlineAsmConstraint(const std::string &Constraint, 10038 EVT VT) const { 10039 if (Constraint.size() == 1) { 10040 // FIXME: not handling fp-stack yet! 10041 switch (Constraint[0]) { // GCC X86 Constraint Letters 10042 default: break; // Unknown constraint letter 10043 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10044 if (Subtarget->is64Bit()) { 10045 if (VT == MVT::i32) 10046 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10047 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10048 X86::R10D,X86::R11D,X86::R12D, 10049 X86::R13D,X86::R14D,X86::R15D, 10050 X86::EBP, X86::ESP, 0); 10051 else if (VT == MVT::i16) 10052 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10053 X86::SI, X86::DI, X86::R8W,X86::R9W, 10054 X86::R10W,X86::R11W,X86::R12W, 10055 X86::R13W,X86::R14W,X86::R15W, 10056 X86::BP, X86::SP, 0); 10057 else if (VT == MVT::i8) 10058 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10059 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10060 X86::R10B,X86::R11B,X86::R12B, 10061 X86::R13B,X86::R14B,X86::R15B, 10062 X86::BPL, X86::SPL, 0); 10063 10064 else if (VT == MVT::i64) 10065 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10066 X86::RSI, X86::RDI, X86::R8, X86::R9, 10067 X86::R10, X86::R11, X86::R12, 10068 X86::R13, X86::R14, X86::R15, 10069 X86::RBP, X86::RSP, 0); 10070 10071 break; 10072 } 10073 // 32-bit fallthrough 10074 case 'Q': // Q_REGS 10075 if (VT == MVT::i32) 10076 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10077 else if (VT == MVT::i16) 10078 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10079 else if (VT == MVT::i8) 10080 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10081 else if (VT == MVT::i64) 10082 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10083 break; 10084 } 10085 } 10086 10087 return std::vector<unsigned>(); 10088} 10089 10090std::pair<unsigned, const TargetRegisterClass*> 10091X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10092 EVT VT) const { 10093 // First, see if this is a constraint that directly corresponds to an LLVM 10094 // register class. 10095 if (Constraint.size() == 1) { 10096 // GCC Constraint Letters 10097 switch (Constraint[0]) { 10098 default: break; 10099 case 'r': // GENERAL_REGS 10100 case 'l': // INDEX_REGS 10101 if (VT == MVT::i8) 10102 return std::make_pair(0U, X86::GR8RegisterClass); 10103 if (VT == MVT::i16) 10104 return std::make_pair(0U, X86::GR16RegisterClass); 10105 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10106 return std::make_pair(0U, X86::GR32RegisterClass); 10107 return std::make_pair(0U, X86::GR64RegisterClass); 10108 case 'R': // LEGACY_REGS 10109 if (VT == MVT::i8) 10110 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10111 if (VT == MVT::i16) 10112 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10113 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10114 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10115 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10116 case 'f': // FP Stack registers. 10117 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10118 // value to the correct fpstack register class. 10119 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10120 return std::make_pair(0U, X86::RFP32RegisterClass); 10121 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10122 return std::make_pair(0U, X86::RFP64RegisterClass); 10123 return std::make_pair(0U, X86::RFP80RegisterClass); 10124 case 'y': // MMX_REGS if MMX allowed. 10125 if (!Subtarget->hasMMX()) break; 10126 return std::make_pair(0U, X86::VR64RegisterClass); 10127 case 'Y': // SSE_REGS if SSE2 allowed 10128 if (!Subtarget->hasSSE2()) break; 10129 // FALL THROUGH. 10130 case 'x': // SSE_REGS if SSE1 allowed 10131 if (!Subtarget->hasSSE1()) break; 10132 10133 switch (VT.getSimpleVT().SimpleTy) { 10134 default: break; 10135 // Scalar SSE types. 10136 case MVT::f32: 10137 case MVT::i32: 10138 return std::make_pair(0U, X86::FR32RegisterClass); 10139 case MVT::f64: 10140 case MVT::i64: 10141 return std::make_pair(0U, X86::FR64RegisterClass); 10142 // Vector types. 10143 case MVT::v16i8: 10144 case MVT::v8i16: 10145 case MVT::v4i32: 10146 case MVT::v2i64: 10147 case MVT::v4f32: 10148 case MVT::v2f64: 10149 return std::make_pair(0U, X86::VR128RegisterClass); 10150 } 10151 break; 10152 } 10153 } 10154 10155 // Use the default implementation in TargetLowering to convert the register 10156 // constraint into a member of a register class. 10157 std::pair<unsigned, const TargetRegisterClass*> Res; 10158 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10159 10160 // Not found as a standard register? 10161 if (Res.second == 0) { 10162 // Map st(0) -> st(7) -> ST0 10163 if (Constraint.size() == 7 && Constraint[0] == '{' && 10164 tolower(Constraint[1]) == 's' && 10165 tolower(Constraint[2]) == 't' && 10166 Constraint[3] == '(' && 10167 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10168 Constraint[5] == ')' && 10169 Constraint[6] == '}') { 10170 10171 Res.first = X86::ST0+Constraint[4]-'0'; 10172 Res.second = X86::RFP80RegisterClass; 10173 return Res; 10174 } 10175 10176 // GCC allows "st(0)" to be called just plain "st". 10177 if (StringRef("{st}").equals_lower(Constraint)) { 10178 Res.first = X86::ST0; 10179 Res.second = X86::RFP80RegisterClass; 10180 return Res; 10181 } 10182 10183 // flags -> EFLAGS 10184 if (StringRef("{flags}").equals_lower(Constraint)) { 10185 Res.first = X86::EFLAGS; 10186 Res.second = X86::CCRRegisterClass; 10187 return Res; 10188 } 10189 10190 // 'A' means EAX + EDX. 10191 if (Constraint == "A") { 10192 Res.first = X86::EAX; 10193 Res.second = X86::GR32_ADRegisterClass; 10194 return Res; 10195 } 10196 return Res; 10197 } 10198 10199 // Otherwise, check to see if this is a register class of the wrong value 10200 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10201 // turn into {ax},{dx}. 10202 if (Res.second->hasType(VT)) 10203 return Res; // Correct type already, nothing to do. 10204 10205 // All of the single-register GCC register classes map their values onto 10206 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10207 // really want an 8-bit or 32-bit register, map to the appropriate register 10208 // class and return the appropriate register. 10209 if (Res.second == X86::GR16RegisterClass) { 10210 if (VT == MVT::i8) { 10211 unsigned DestReg = 0; 10212 switch (Res.first) { 10213 default: break; 10214 case X86::AX: DestReg = X86::AL; break; 10215 case X86::DX: DestReg = X86::DL; break; 10216 case X86::CX: DestReg = X86::CL; break; 10217 case X86::BX: DestReg = X86::BL; break; 10218 } 10219 if (DestReg) { 10220 Res.first = DestReg; 10221 Res.second = X86::GR8RegisterClass; 10222 } 10223 } else if (VT == MVT::i32) { 10224 unsigned DestReg = 0; 10225 switch (Res.first) { 10226 default: break; 10227 case X86::AX: DestReg = X86::EAX; break; 10228 case X86::DX: DestReg = X86::EDX; break; 10229 case X86::CX: DestReg = X86::ECX; break; 10230 case X86::BX: DestReg = X86::EBX; break; 10231 case X86::SI: DestReg = X86::ESI; break; 10232 case X86::DI: DestReg = X86::EDI; break; 10233 case X86::BP: DestReg = X86::EBP; break; 10234 case X86::SP: DestReg = X86::ESP; break; 10235 } 10236 if (DestReg) { 10237 Res.first = DestReg; 10238 Res.second = X86::GR32RegisterClass; 10239 } 10240 } else if (VT == MVT::i64) { 10241 unsigned DestReg = 0; 10242 switch (Res.first) { 10243 default: break; 10244 case X86::AX: DestReg = X86::RAX; break; 10245 case X86::DX: DestReg = X86::RDX; break; 10246 case X86::CX: DestReg = X86::RCX; break; 10247 case X86::BX: DestReg = X86::RBX; break; 10248 case X86::SI: DestReg = X86::RSI; break; 10249 case X86::DI: DestReg = X86::RDI; break; 10250 case X86::BP: DestReg = X86::RBP; break; 10251 case X86::SP: DestReg = X86::RSP; break; 10252 } 10253 if (DestReg) { 10254 Res.first = DestReg; 10255 Res.second = X86::GR64RegisterClass; 10256 } 10257 } 10258 } else if (Res.second == X86::FR32RegisterClass || 10259 Res.second == X86::FR64RegisterClass || 10260 Res.second == X86::VR128RegisterClass) { 10261 // Handle references to XMM physical registers that got mapped into the 10262 // wrong class. This can happen with constraints like {xmm0} where the 10263 // target independent register mapper will just pick the first match it can 10264 // find, ignoring the required type. 10265 if (VT == MVT::f32) 10266 Res.second = X86::FR32RegisterClass; 10267 else if (VT == MVT::f64) 10268 Res.second = X86::FR64RegisterClass; 10269 else if (X86::VR128RegisterClass->hasType(VT)) 10270 Res.second = X86::VR128RegisterClass; 10271 } 10272 10273 return Res; 10274} 10275 10276//===----------------------------------------------------------------------===// 10277// X86 Widen vector type 10278//===----------------------------------------------------------------------===// 10279 10280/// getWidenVectorType: given a vector type, returns the type to widen 10281/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 10282/// If there is no vector type that we want to widen to, returns MVT::Other 10283/// When and where to widen is target dependent based on the cost of 10284/// scalarizing vs using the wider vector type. 10285 10286EVT X86TargetLowering::getWidenVectorType(EVT VT) const { 10287 assert(VT.isVector()); 10288 if (isTypeLegal(VT)) 10289 return VT; 10290 10291 // TODO: In computeRegisterProperty, we can compute the list of legal vector 10292 // type based on element type. This would speed up our search (though 10293 // it may not be worth it since the size of the list is relatively 10294 // small). 10295 EVT EltVT = VT.getVectorElementType(); 10296 unsigned NElts = VT.getVectorNumElements(); 10297 10298 // On X86, it make sense to widen any vector wider than 1 10299 if (NElts <= 1) 10300 return MVT::Other; 10301 10302 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 10303 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 10304 EVT SVT = (MVT::SimpleValueType)nVT; 10305 10306 if (isTypeLegal(SVT) && 10307 SVT.getVectorElementType() == EltVT && 10308 SVT.getVectorNumElements() > NElts) 10309 return SVT; 10310 } 10311 return MVT::Other; 10312} 10313