X86ISelLowering.cpp revision d00bfe1f8dded563fa32a045d6d74ec1c25427dd
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Forward declarations. 61static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 65 66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 67 68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) { 69 if (is64Bit) return new X8664_MachoTargetObjectFile(); 70 return new TargetLoweringObjectFileMachO(); 71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){ 72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM); 73 return new X8632_ELFTargetObjectFile(TM); 74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) { 75 return new TargetLoweringObjectFileCOFF(); 76 } 77 llvm_unreachable("unknown subtarget type"); 78} 79 80X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 81 : TargetLowering(TM, createTLOF(TM)) { 82 Subtarget = &TM.getSubtarget<X86Subtarget>(); 83 X86ScalarSSEf64 = Subtarget->hasSSE2(); 84 X86ScalarSSEf32 = Subtarget->hasSSE1(); 85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 86 87 RegInfo = TM.getRegisterInfo(); 88 TD = getTargetData(); 89 90 // Set up the TargetLowering object. 91 92 // X86 is weird, it always uses i8 for shift amounts and setcc results. 93 setShiftAmountType(MVT::i8); 94 setBooleanContents(ZeroOrOneBooleanContent); 95 setSchedulingPreference(Sched::RegPressure); 96 setStackPointerRegisterToSaveRestore(X86StackPtr); 97 98 if (Subtarget->isTargetDarwin()) { 99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 100 setUseUnderscoreSetJmp(false); 101 setUseUnderscoreLongJmp(false); 102 } else if (Subtarget->isTargetMingw()) { 103 // MS runtime is weird: it exports _setjmp, but longjmp! 104 setUseUnderscoreSetJmp(true); 105 setUseUnderscoreLongJmp(false); 106 } else { 107 setUseUnderscoreSetJmp(true); 108 setUseUnderscoreLongJmp(true); 109 } 110 111 // Set up the register classes. 112 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 113 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 114 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 115 if (Subtarget->is64Bit()) 116 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 117 118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 119 120 // We don't accept any truncstore of integer registers. 121 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 122 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 124 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 126 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 127 128 // SETOEQ and SETUNE require checking two conditions. 129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 135 136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 137 // operation. 138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 141 142 if (Subtarget->is64Bit()) { 143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 145 } else if (!UseSoftFloat) { 146 // We have an algorithm for SSE2->double, and we turn this into a 147 // 64-bit FILD followed by conditional FADD for other targets. 148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 149 // We have an algorithm for SSE2, and we turn this into a 64-bit 150 // FILD for other targets. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 152 } 153 154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 155 // this operation. 156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 158 159 if (!UseSoftFloat) { 160 // SSE has no i16 to fp conversion, only i32 161 if (X86ScalarSSEf32) { 162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 163 // f32 and f64 cases are Legal, f80 case is not 164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 165 } else { 166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 168 } 169 } else { 170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 172 } 173 174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 175 // are Legal, f80 is custom lowered. 176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 178 179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 180 // this operation. 181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 183 184 if (X86ScalarSSEf32) { 185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 186 // f32 and f64 cases are Legal, f80 case is not 187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 188 } else { 189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 191 } 192 193 // Handle FP_TO_UINT by promoting the destination to a larger signed 194 // conversion. 195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 198 199 if (Subtarget->is64Bit()) { 200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 202 } else if (!UseSoftFloat) { 203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 204 // Expand FP_TO_UINT into a select. 205 // FIXME: We would like to use a Custom expander here eventually to do 206 // the optimal thing for SSE vs. the default expansion in the legalizer. 207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 208 else 209 // With SSE3 we can use fisttpll to convert to a signed i64; without 210 // SSE, we're stuck with a fistpll. 211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 212 } 213 214 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 215 if (!X86ScalarSSEf64) { 216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 218 if (Subtarget->is64Bit()) { 219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand); 220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal. 221 if (Subtarget->hasMMX() && !DisableMMX) 222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom); 223 else 224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand); 225 } 226 } 227 228 // Scalar integer divide and remainder are lowered to use operations that 229 // produce two results, to match the available instructions. This exposes 230 // the two-result form to trivial CSE, which is able to combine x/y and x%y 231 // into a single instruction. 232 // 233 // Scalar integer multiply-high is also lowered to use two-result 234 // operations, to match the available instructions. However, plain multiply 235 // (low) operations are left as Legal, as there are single-result 236 // instructions for this in x86. Using the two-result multiply instructions 237 // when both high and low results are needed must be arranged by dagcombine. 238 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 239 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 240 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 241 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 242 setOperationAction(ISD::SREM , MVT::i8 , Expand); 243 setOperationAction(ISD::UREM , MVT::i8 , Expand); 244 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 248 setOperationAction(ISD::SREM , MVT::i16 , Expand); 249 setOperationAction(ISD::UREM , MVT::i16 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 254 setOperationAction(ISD::SREM , MVT::i32 , Expand); 255 setOperationAction(ISD::UREM , MVT::i32 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 260 setOperationAction(ISD::SREM , MVT::i64 , Expand); 261 setOperationAction(ISD::UREM , MVT::i64 , Expand); 262 263 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 264 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 265 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 267 if (Subtarget->is64Bit()) 268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 273 setOperationAction(ISD::FREM , MVT::f32 , Expand); 274 setOperationAction(ISD::FREM , MVT::f64 , Expand); 275 setOperationAction(ISD::FREM , MVT::f80 , Expand); 276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 277 278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 291 } 292 293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 295 296 // These should be promoted to a larger select which is supported. 297 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 298 // X86 wants to expand cmov itself. 299 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 300 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 301 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 302 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 303 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 304 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 305 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 306 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 307 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 308 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 309 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 310 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 313 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 314 } 315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 316 317 // Darwin ABI issue. 318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 322 if (Subtarget->is64Bit()) 323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 326 if (Subtarget->is64Bit()) { 327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 332 } 333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 341 } 342 343 if (Subtarget->hasSSE1()) 344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 345 346 // We may not have a libcall for MEMBARRIER so we should lower this. 347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 348 349 // On X86 and X86-64, atomic operations are lowered to locked instructions. 350 // Locked instructions, in turn, have implicit fence semantics (all memory 351 // operations are flushed before issuing the locked instruction, and they 352 // are not buffered), so we can fold away the common pattern of 353 // fence-atomic-fence. 354 setShouldFoldAtomicFences(true); 355 356 // Expand certain atomics 357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 361 362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 366 367 if (!Subtarget->is64Bit()) { 368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 375 } 376 377 // FIXME - use subtarget debug flags 378 if (!Subtarget->isTargetDarwin() && 379 !Subtarget->isTargetELF() && 380 !Subtarget->isTargetCygMing()) { 381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 382 } 383 384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 388 if (Subtarget->is64Bit()) { 389 setExceptionPointerRegister(X86::RAX); 390 setExceptionSelectorRegister(X86::RDX); 391 } else { 392 setExceptionPointerRegister(X86::EAX); 393 setExceptionSelectorRegister(X86::EDX); 394 } 395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 397 398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 399 400 setOperationAction(ISD::TRAP, MVT::Other, Legal); 401 402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 403 setOperationAction(ISD::VASTART , MVT::Other, Custom); 404 setOperationAction(ISD::VAEND , MVT::Other, Expand); 405 if (Subtarget->is64Bit()) { 406 setOperationAction(ISD::VAARG , MVT::Other, Custom); 407 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 408 } else { 409 setOperationAction(ISD::VAARG , MVT::Other, Expand); 410 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 411 } 412 413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 415 if (Subtarget->is64Bit()) 416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 417 if (Subtarget->isTargetCygMing()) 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 419 else 420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 421 422 if (!UseSoftFloat && X86ScalarSSEf64) { 423 // f32 and f64 use SSE. 424 // Set up the FP register classes. 425 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 426 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 427 428 // Use ANDPD to simulate FABS. 429 setOperationAction(ISD::FABS , MVT::f64, Custom); 430 setOperationAction(ISD::FABS , MVT::f32, Custom); 431 432 // Use XORP to simulate FNEG. 433 setOperationAction(ISD::FNEG , MVT::f64, Custom); 434 setOperationAction(ISD::FNEG , MVT::f32, Custom); 435 436 // Use ANDPD and ORPD to simulate FCOPYSIGN. 437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 439 440 // We don't support sin/cos/fmod 441 setOperationAction(ISD::FSIN , MVT::f64, Expand); 442 setOperationAction(ISD::FCOS , MVT::f64, Expand); 443 setOperationAction(ISD::FSIN , MVT::f32, Expand); 444 setOperationAction(ISD::FCOS , MVT::f32, Expand); 445 446 // Expand FP immediates into loads from the stack, except for the special 447 // cases we handle. 448 addLegalFPImmediate(APFloat(+0.0)); // xorpd 449 addLegalFPImmediate(APFloat(+0.0f)); // xorps 450 } else if (!UseSoftFloat && X86ScalarSSEf32) { 451 // Use SSE for f32, x87 for f64. 452 // Set up the FP register classes. 453 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 455 456 // Use ANDPS to simulate FABS. 457 setOperationAction(ISD::FABS , MVT::f32, Custom); 458 459 // Use XORP to simulate FNEG. 460 setOperationAction(ISD::FNEG , MVT::f32, Custom); 461 462 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 463 464 // Use ANDPS and ORPS to simulate FCOPYSIGN. 465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 467 468 // We don't support sin/cos/fmod 469 setOperationAction(ISD::FSIN , MVT::f32, Expand); 470 setOperationAction(ISD::FCOS , MVT::f32, Expand); 471 472 // Special cases we handle for FP constants. 473 addLegalFPImmediate(APFloat(+0.0f)); // xorps 474 addLegalFPImmediate(APFloat(+0.0)); // FLD0 475 addLegalFPImmediate(APFloat(+1.0)); // FLD1 476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 478 479 if (!UnsafeFPMath) { 480 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 481 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 482 } 483 } else if (!UseSoftFloat) { 484 // f32 and f64 in x87. 485 // Set up the FP register classes. 486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 488 489 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 490 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 493 494 if (!UnsafeFPMath) { 495 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 496 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 497 } 498 addLegalFPImmediate(APFloat(+0.0)); // FLD0 499 addLegalFPImmediate(APFloat(+1.0)); // FLD1 500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 506 } 507 508 // Long double always uses X87. 509 if (!UseSoftFloat) { 510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 511 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 513 { 514 bool ignored; 515 APFloat TmpFlt(+0.0); 516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 517 &ignored); 518 addLegalFPImmediate(TmpFlt); // FLD0 519 TmpFlt.changeSign(); 520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 521 APFloat TmpFlt2(+1.0); 522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 523 &ignored); 524 addLegalFPImmediate(TmpFlt2); // FLD1 525 TmpFlt2.changeSign(); 526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 527 } 528 529 if (!UnsafeFPMath) { 530 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 531 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 532 } 533 } 534 535 // Always use a library call for pow. 536 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 537 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 538 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 539 540 setOperationAction(ISD::FLOG, MVT::f80, Expand); 541 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 542 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 543 setOperationAction(ISD::FEXP, MVT::f80, Expand); 544 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 545 546 // First set operation action for all vector types to either promote 547 // (for widening) or expand (for scalarization). Then we will selectively 548 // turn on ones that can be effectively codegen'd. 549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 606 setTruncStoreAction((MVT::SimpleValueType)VT, 607 (MVT::SimpleValueType)InnerVT, Expand); 608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 611 } 612 613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 614 // with -msoft-float, disable use of MMX as well. 615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false); 617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false); 618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false); 619 620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false); 621 622 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 623 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 624 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 625 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 626 627 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 628 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 629 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 630 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 631 632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 633 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 634 635 setOperationAction(ISD::AND, MVT::v8i8, Promote); 636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 637 setOperationAction(ISD::AND, MVT::v4i16, Promote); 638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 639 setOperationAction(ISD::AND, MVT::v2i32, Promote); 640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 641 setOperationAction(ISD::AND, MVT::v1i64, Legal); 642 643 setOperationAction(ISD::OR, MVT::v8i8, Promote); 644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 645 setOperationAction(ISD::OR, MVT::v4i16, Promote); 646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 647 setOperationAction(ISD::OR, MVT::v2i32, Promote); 648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 649 setOperationAction(ISD::OR, MVT::v1i64, Legal); 650 651 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 653 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 655 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 657 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 658 659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 666 667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 671 672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 676 677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 680 681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 682 683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 690 691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) { 692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom); 693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom); 694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom); 695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom); 696 } 697 } 698 699 if (!UseSoftFloat && Subtarget->hasSSE1()) { 700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 701 702 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 714 } 715 716 if (!UseSoftFloat && Subtarget->hasSSE2()) { 717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 718 719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 720 // registers cannot be used even for integer operations. 721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 725 726 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 727 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 728 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 729 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 730 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 731 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 732 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 733 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 734 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 735 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 736 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 742 743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 747 748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 753 754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 759 760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 762 EVT VT = (MVT::SimpleValueType)i; 763 // Do not attempt to custom lower non-power-of-2 vectors 764 if (!isPowerOf2_32(VT.getVectorNumElements())) 765 continue; 766 // Do not attempt to custom lower non-128-bit vectors 767 if (!VT.is128BitVector()) 768 continue; 769 setOperationAction(ISD::BUILD_VECTOR, 770 VT.getSimpleVT().SimpleTy, Custom); 771 setOperationAction(ISD::VECTOR_SHUFFLE, 772 VT.getSimpleVT().SimpleTy, Custom); 773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 774 VT.getSimpleVT().SimpleTy, Custom); 775 } 776 777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 783 784 if (Subtarget->is64Bit()) { 785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 787 } 788 789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 792 EVT VT = SVT; 793 794 // Do not attempt to promote non-128-bit vectors 795 if (!VT.is128BitVector()) 796 continue; 797 798 setOperationAction(ISD::AND, SVT, Promote); 799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 800 setOperationAction(ISD::OR, SVT, Promote); 801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 802 setOperationAction(ISD::XOR, SVT, Promote); 803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 804 setOperationAction(ISD::LOAD, SVT, Promote); 805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 806 setOperationAction(ISD::SELECT, SVT, Promote); 807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 808 } 809 810 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 811 812 // Custom lower v2i64 and v2f64 selects. 813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 817 818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 820 if (!DisableMMX && Subtarget->hasMMX()) { 821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 823 } 824 } 825 826 if (Subtarget->hasSSE41()) { 827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 828 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 830 setOperationAction(ISD::FRINT, MVT::f32, Legal); 831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 833 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 835 setOperationAction(ISD::FRINT, MVT::f64, Legal); 836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 837 838 // FIXME: Do we need to handle scalar-to-vector here? 839 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 840 841 // Can turn SHL into an integer multiply. 842 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 843 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 844 845 // i8 and i16 vectors are custom , because the source register and source 846 // source memory operand types are not the same width. f32 vectors are 847 // custom since the immediate controlling the insert encodes additional 848 // information. 849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 853 854 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 858 859 if (Subtarget->is64Bit()) { 860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 862 } 863 } 864 865 if (Subtarget->hasSSE42()) { 866 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 867 } 868 869 if (!UseSoftFloat && Subtarget->hasAVX()) { 870 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 871 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 872 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 873 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 874 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 875 876 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 877 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 878 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 879 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 880 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 881 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 882 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 883 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 884 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 885 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 886 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 887 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 888 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 889 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 890 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 891 892 // Operations to consider commented out -v16i16 v32i8 893 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 894 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 895 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 896 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 897 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 898 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 899 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 900 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 901 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 902 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 903 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 904 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 905 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 906 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 907 908 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 909 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 910 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 911 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 912 913 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 914 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 915 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 918 919 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 920 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 921 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 925 926#if 0 927 // Not sure we want to do this since there are no 256-bit integer 928 // operations in AVX 929 930 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 931 // This includes 256-bit vectors 932 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 933 EVT VT = (MVT::SimpleValueType)i; 934 935 // Do not attempt to custom lower non-power-of-2 vectors 936 if (!isPowerOf2_32(VT.getVectorNumElements())) 937 continue; 938 939 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 940 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 942 } 943 944 if (Subtarget->is64Bit()) { 945 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 947 } 948#endif 949 950#if 0 951 // Not sure we want to do this since there are no 256-bit integer 952 // operations in AVX 953 954 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 955 // Including 256-bit vectors 956 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 957 EVT VT = (MVT::SimpleValueType)i; 958 959 if (!VT.is256BitVector()) { 960 continue; 961 } 962 setOperationAction(ISD::AND, VT, Promote); 963 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 964 setOperationAction(ISD::OR, VT, Promote); 965 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 966 setOperationAction(ISD::XOR, VT, Promote); 967 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 968 setOperationAction(ISD::LOAD, VT, Promote); 969 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 970 setOperationAction(ISD::SELECT, VT, Promote); 971 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 972 } 973 974 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 975#endif 976 } 977 978 // We want to custom lower some of our intrinsics. 979 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 980 981 // Add/Sub/Mul with overflow operations are custom lowered. 982 setOperationAction(ISD::SADDO, MVT::i32, Custom); 983 setOperationAction(ISD::UADDO, MVT::i32, Custom); 984 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 985 setOperationAction(ISD::USUBO, MVT::i32, Custom); 986 setOperationAction(ISD::SMULO, MVT::i32, Custom); 987 988 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 989 // handle type legalization for these operations here. 990 // 991 // FIXME: We really should do custom legalization for addition and 992 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 993 // than generic legalization for 64-bit multiplication-with-overflow, though. 994 if (Subtarget->is64Bit()) { 995 setOperationAction(ISD::SADDO, MVT::i64, Custom); 996 setOperationAction(ISD::UADDO, MVT::i64, Custom); 997 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 998 setOperationAction(ISD::USUBO, MVT::i64, Custom); 999 setOperationAction(ISD::SMULO, MVT::i64, Custom); 1000 } 1001 1002 if (!Subtarget->is64Bit()) { 1003 // These libcalls are not available in 32-bit. 1004 setLibcallName(RTLIB::SHL_I128, 0); 1005 setLibcallName(RTLIB::SRL_I128, 0); 1006 setLibcallName(RTLIB::SRA_I128, 0); 1007 } 1008 1009 // We have target-specific dag combine patterns for the following nodes: 1010 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1011 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1012 setTargetDAGCombine(ISD::BUILD_VECTOR); 1013 setTargetDAGCombine(ISD::SELECT); 1014 setTargetDAGCombine(ISD::SHL); 1015 setTargetDAGCombine(ISD::SRA); 1016 setTargetDAGCombine(ISD::SRL); 1017 setTargetDAGCombine(ISD::OR); 1018 setTargetDAGCombine(ISD::STORE); 1019 setTargetDAGCombine(ISD::ZERO_EXTEND); 1020 if (Subtarget->is64Bit()) 1021 setTargetDAGCombine(ISD::MUL); 1022 1023 computeRegisterProperties(); 1024 1025 // FIXME: These should be based on subtarget info. Plus, the values should 1026 // be smaller when we are in optimizing for size mode. 1027 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1028 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1029 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1030 setPrefLoopAlignment(16); 1031 benefitFromCodePlacementOpt = true; 1032} 1033 1034 1035MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1036 return MVT::i8; 1037} 1038 1039 1040/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1041/// the desired ByVal argument alignment. 1042static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1043 if (MaxAlign == 16) 1044 return; 1045 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1046 if (VTy->getBitWidth() == 128) 1047 MaxAlign = 16; 1048 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1049 unsigned EltAlign = 0; 1050 getMaxByValAlign(ATy->getElementType(), EltAlign); 1051 if (EltAlign > MaxAlign) 1052 MaxAlign = EltAlign; 1053 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1054 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1055 unsigned EltAlign = 0; 1056 getMaxByValAlign(STy->getElementType(i), EltAlign); 1057 if (EltAlign > MaxAlign) 1058 MaxAlign = EltAlign; 1059 if (MaxAlign == 16) 1060 break; 1061 } 1062 } 1063 return; 1064} 1065 1066/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1067/// function arguments in the caller parameter area. For X86, aggregates 1068/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1069/// are at 4-byte boundaries. 1070unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1071 if (Subtarget->is64Bit()) { 1072 // Max of 8 and alignment of type. 1073 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1074 if (TyAlign > 8) 1075 return TyAlign; 1076 return 8; 1077 } 1078 1079 unsigned Align = 4; 1080 if (Subtarget->hasSSE1()) 1081 getMaxByValAlign(Ty, Align); 1082 return Align; 1083} 1084 1085/// getOptimalMemOpType - Returns the target specific optimal type for load 1086/// and store operations as a result of memset, memcpy, and memmove 1087/// lowering. If DstAlign is zero that means it's safe to destination 1088/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1089/// means there isn't a need to check it against alignment requirement, 1090/// probably because the source does not need to be loaded. If 1091/// 'NonScalarIntSafe' is true, that means it's safe to return a 1092/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1093/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1094/// constant so it does not need to be loaded. 1095/// It returns EVT::Other if the type should be determined using generic 1096/// target-independent logic. 1097EVT 1098X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1099 unsigned DstAlign, unsigned SrcAlign, 1100 bool NonScalarIntSafe, 1101 bool MemcpyStrSrc, 1102 MachineFunction &MF) const { 1103 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1104 // linux. This is because the stack realignment code can't handle certain 1105 // cases like PR2962. This should be removed when PR2962 is fixed. 1106 const Function *F = MF.getFunction(); 1107 if (NonScalarIntSafe && 1108 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1109 if (Size >= 16 && 1110 (Subtarget->isUnalignedMemAccessFast() || 1111 ((DstAlign == 0 || DstAlign >= 16) && 1112 (SrcAlign == 0 || SrcAlign >= 16))) && 1113 Subtarget->getStackAlignment() >= 16) { 1114 if (Subtarget->hasSSE2()) 1115 return MVT::v4i32; 1116 if (Subtarget->hasSSE1()) 1117 return MVT::v4f32; 1118 } else if (!MemcpyStrSrc && Size >= 8 && 1119 !Subtarget->is64Bit() && 1120 Subtarget->getStackAlignment() >= 8 && 1121 Subtarget->hasSSE2()) { 1122 // Do not use f64 to lower memcpy if source is string constant. It's 1123 // better to use i32 to avoid the loads. 1124 return MVT::f64; 1125 } 1126 } 1127 if (Subtarget->is64Bit() && Size >= 8) 1128 return MVT::i64; 1129 return MVT::i32; 1130} 1131 1132/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1133/// current function. The returned value is a member of the 1134/// MachineJumpTableInfo::JTEntryKind enum. 1135unsigned X86TargetLowering::getJumpTableEncoding() const { 1136 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1137 // symbol. 1138 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1139 Subtarget->isPICStyleGOT()) 1140 return MachineJumpTableInfo::EK_Custom32; 1141 1142 // Otherwise, use the normal jump table encoding heuristics. 1143 return TargetLowering::getJumpTableEncoding(); 1144} 1145 1146/// getPICBaseSymbol - Return the X86-32 PIC base. 1147MCSymbol * 1148X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1149 MCContext &Ctx) const { 1150 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1151 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1152 Twine(MF->getFunctionNumber())+"$pb"); 1153} 1154 1155 1156const MCExpr * 1157X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1158 const MachineBasicBlock *MBB, 1159 unsigned uid,MCContext &Ctx) const{ 1160 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1161 Subtarget->isPICStyleGOT()); 1162 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1163 // entries. 1164 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1165 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1166} 1167 1168/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1169/// jumptable. 1170SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1171 SelectionDAG &DAG) const { 1172 if (!Subtarget->is64Bit()) 1173 // This doesn't have DebugLoc associated with it, but is not really the 1174 // same as a Register. 1175 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1176 return Table; 1177} 1178 1179/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1180/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1181/// MCExpr. 1182const MCExpr *X86TargetLowering:: 1183getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1184 MCContext &Ctx) const { 1185 // X86-64 uses RIP relative addressing based on the jump table label. 1186 if (Subtarget->isPICStyleRIPRel()) 1187 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1188 1189 // Otherwise, the reference is relative to the PIC base. 1190 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1191} 1192 1193/// getFunctionAlignment - Return the Log2 alignment of this function. 1194unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1195 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1196} 1197 1198std::pair<const TargetRegisterClass*, uint8_t> 1199X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1200 const TargetRegisterClass *RRC = 0; 1201 uint8_t Cost = 1; 1202 switch (VT.getSimpleVT().SimpleTy) { 1203 default: 1204 return TargetLowering::findRepresentativeClass(VT); 1205 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1206 RRC = (Subtarget->is64Bit() 1207 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1208 break; 1209 case MVT::v8i8: case MVT::v4i16: 1210 case MVT::v2i32: case MVT::v1i64: 1211 RRC = X86::VR64RegisterClass; 1212 break; 1213 case MVT::f32: case MVT::f64: 1214 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1215 case MVT::v4f32: case MVT::v2f64: 1216 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1217 case MVT::v4f64: 1218 RRC = X86::VR128RegisterClass; 1219 break; 1220 } 1221 return std::make_pair(RRC, Cost); 1222} 1223 1224unsigned 1225X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, 1226 MachineFunction &MF) const { 1227 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0; 1228 switch (RC->getID()) { 1229 default: 1230 return 0; 1231 case X86::GR32RegClassID: 1232 return 4 - FPDiff; 1233 case X86::GR64RegClassID: 1234 return 8 - FPDiff; 1235 case X86::VR128RegClassID: 1236 return Subtarget->is64Bit() ? 10 : 4; 1237 case X86::VR64RegClassID: 1238 return 4; 1239 } 1240} 1241 1242bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1243 unsigned &Offset) const { 1244 if (!Subtarget->isTargetLinux()) 1245 return false; 1246 1247 if (Subtarget->is64Bit()) { 1248 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1249 Offset = 0x28; 1250 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1251 AddressSpace = 256; 1252 else 1253 AddressSpace = 257; 1254 } else { 1255 // %gs:0x14 on i386 1256 Offset = 0x14; 1257 AddressSpace = 256; 1258 } 1259 return true; 1260} 1261 1262 1263//===----------------------------------------------------------------------===// 1264// Return Value Calling Convention Implementation 1265//===----------------------------------------------------------------------===// 1266 1267#include "X86GenCallingConv.inc" 1268 1269bool 1270X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1271 const SmallVectorImpl<ISD::OutputArg> &Outs, 1272 LLVMContext &Context) const { 1273 SmallVector<CCValAssign, 16> RVLocs; 1274 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1275 RVLocs, Context); 1276 return CCInfo.CheckReturn(Outs, RetCC_X86); 1277} 1278 1279SDValue 1280X86TargetLowering::LowerReturn(SDValue Chain, 1281 CallingConv::ID CallConv, bool isVarArg, 1282 const SmallVectorImpl<ISD::OutputArg> &Outs, 1283 const SmallVectorImpl<SDValue> &OutVals, 1284 DebugLoc dl, SelectionDAG &DAG) const { 1285 MachineFunction &MF = DAG.getMachineFunction(); 1286 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1287 1288 SmallVector<CCValAssign, 16> RVLocs; 1289 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1290 RVLocs, *DAG.getContext()); 1291 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1292 1293 // Add the regs to the liveout set for the function. 1294 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1295 for (unsigned i = 0; i != RVLocs.size(); ++i) 1296 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1297 MRI.addLiveOut(RVLocs[i].getLocReg()); 1298 1299 SDValue Flag; 1300 1301 SmallVector<SDValue, 6> RetOps; 1302 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1303 // Operand #1 = Bytes To Pop 1304 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1305 MVT::i16)); 1306 1307 // Copy the result values into the output registers. 1308 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1309 CCValAssign &VA = RVLocs[i]; 1310 assert(VA.isRegLoc() && "Can only return in registers!"); 1311 SDValue ValToCopy = OutVals[i]; 1312 EVT ValVT = ValToCopy.getValueType(); 1313 1314 // If this is x86-64, and we disabled SSE, we can't return FP values 1315 if ((ValVT == MVT::f32 || ValVT == MVT::f64) && 1316 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1317 report_fatal_error("SSE register return with SSE disabled"); 1318 } 1319 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1320 // llvm-gcc has never done it right and no one has noticed, so this 1321 // should be OK for now. 1322 if (ValVT == MVT::f64 && 1323 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1324 report_fatal_error("SSE2 register return with SSE2 disabled"); 1325 1326 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1327 // the RET instruction and handled by the FP Stackifier. 1328 if (VA.getLocReg() == X86::ST0 || 1329 VA.getLocReg() == X86::ST1) { 1330 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1331 // change the value to the FP stack register class. 1332 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1333 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1334 RetOps.push_back(ValToCopy); 1335 // Don't emit a copytoreg. 1336 continue; 1337 } 1338 1339 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1340 // which is returned in RAX / RDX. 1341 if (Subtarget->is64Bit()) { 1342 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1343 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1344 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1345 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1346 ValToCopy); 1347 1348 // If we don't have SSE2 available, convert to v4f32 so the generated 1349 // register is legal. 1350 if (!Subtarget->hasSSE2()) 1351 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy); 1352 } 1353 } 1354 } 1355 1356 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1357 Flag = Chain.getValue(1); 1358 } 1359 1360 // The x86-64 ABI for returning structs by value requires that we copy 1361 // the sret argument into %rax for the return. We saved the argument into 1362 // a virtual register in the entry block, so now we copy the value out 1363 // and into %rax. 1364 if (Subtarget->is64Bit() && 1365 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1366 MachineFunction &MF = DAG.getMachineFunction(); 1367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1368 unsigned Reg = FuncInfo->getSRetReturnReg(); 1369 assert(Reg && 1370 "SRetReturnReg should have been set in LowerFormalArguments()."); 1371 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1372 1373 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1374 Flag = Chain.getValue(1); 1375 1376 // RAX now acts like a return value. 1377 MRI.addLiveOut(X86::RAX); 1378 } 1379 1380 RetOps[0] = Chain; // Update chain. 1381 1382 // Add the flag if we have it. 1383 if (Flag.getNode()) 1384 RetOps.push_back(Flag); 1385 1386 return DAG.getNode(X86ISD::RET_FLAG, dl, 1387 MVT::Other, &RetOps[0], RetOps.size()); 1388} 1389 1390/// LowerCallResult - Lower the result values of a call into the 1391/// appropriate copies out of appropriate physical registers. 1392/// 1393SDValue 1394X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1395 CallingConv::ID CallConv, bool isVarArg, 1396 const SmallVectorImpl<ISD::InputArg> &Ins, 1397 DebugLoc dl, SelectionDAG &DAG, 1398 SmallVectorImpl<SDValue> &InVals) const { 1399 1400 // Assign locations to each value returned by this call. 1401 SmallVector<CCValAssign, 16> RVLocs; 1402 bool Is64Bit = Subtarget->is64Bit(); 1403 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1404 RVLocs, *DAG.getContext()); 1405 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1406 1407 // Copy all of the result registers out of their specified physreg. 1408 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1409 CCValAssign &VA = RVLocs[i]; 1410 EVT CopyVT = VA.getValVT(); 1411 1412 // If this is x86-64, and we disabled SSE, we can't return FP values 1413 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1414 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1415 report_fatal_error("SSE register return with SSE disabled"); 1416 } 1417 1418 SDValue Val; 1419 1420 // If this is a call to a function that returns an fp value on the floating 1421 // point stack, we must guarantee the the value is popped from the stack, so 1422 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1423 // if the return value is not used. We use the FpGET_ST0 instructions 1424 // instead. 1425 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1426 // If we prefer to use the value in xmm registers, copy it out as f80 and 1427 // use a truncate to move it from fp stack reg to xmm reg. 1428 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1429 bool isST0 = VA.getLocReg() == X86::ST0; 1430 unsigned Opc = 0; 1431 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; 1432 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; 1433 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; 1434 SDValue Ops[] = { Chain, InFlag }; 1435 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag, 1436 Ops, 2), 1); 1437 Val = Chain.getValue(0); 1438 1439 // Round the f80 to the right size, which also moves it to the appropriate 1440 // xmm register. 1441 if (CopyVT != VA.getValVT()) 1442 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1443 // This truncation won't change the value. 1444 DAG.getIntPtrConstant(1)); 1445 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1446 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1447 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1448 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1449 MVT::v2i64, InFlag).getValue(1); 1450 Val = Chain.getValue(0); 1451 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1452 Val, DAG.getConstant(0, MVT::i64)); 1453 } else { 1454 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1455 MVT::i64, InFlag).getValue(1); 1456 Val = Chain.getValue(0); 1457 } 1458 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1459 } else { 1460 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1461 CopyVT, InFlag).getValue(1); 1462 Val = Chain.getValue(0); 1463 } 1464 InFlag = Chain.getValue(2); 1465 InVals.push_back(Val); 1466 } 1467 1468 return Chain; 1469} 1470 1471 1472//===----------------------------------------------------------------------===// 1473// C & StdCall & Fast Calling Convention implementation 1474//===----------------------------------------------------------------------===// 1475// StdCall calling convention seems to be standard for many Windows' API 1476// routines and around. It differs from C calling convention just a little: 1477// callee should clean up the stack, not caller. Symbols should be also 1478// decorated in some fancy way :) It doesn't support any vector arguments. 1479// For info on fast calling convention see Fast Calling Convention (tail call) 1480// implementation LowerX86_32FastCCCallTo. 1481 1482/// CallIsStructReturn - Determines whether a call uses struct return 1483/// semantics. 1484static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1485 if (Outs.empty()) 1486 return false; 1487 1488 return Outs[0].Flags.isSRet(); 1489} 1490 1491/// ArgsAreStructReturn - Determines whether a function uses struct 1492/// return semantics. 1493static bool 1494ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1495 if (Ins.empty()) 1496 return false; 1497 1498 return Ins[0].Flags.isSRet(); 1499} 1500 1501/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1502/// given CallingConvention value. 1503CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1504 if (Subtarget->is64Bit()) { 1505 if (CC == CallingConv::GHC) 1506 return CC_X86_64_GHC; 1507 else if (Subtarget->isTargetWin64()) 1508 return CC_X86_Win64_C; 1509 else 1510 return CC_X86_64_C; 1511 } 1512 1513 if (CC == CallingConv::X86_FastCall) 1514 return CC_X86_32_FastCall; 1515 else if (CC == CallingConv::X86_ThisCall) 1516 return CC_X86_32_ThisCall; 1517 else if (CC == CallingConv::Fast) 1518 return CC_X86_32_FastCC; 1519 else if (CC == CallingConv::GHC) 1520 return CC_X86_32_GHC; 1521 else 1522 return CC_X86_32_C; 1523} 1524 1525/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1526/// by "Src" to address "Dst" with size and alignment information specified by 1527/// the specific parameter attribute. The copy will be passed as a byval 1528/// function parameter. 1529static SDValue 1530CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1531 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1532 DebugLoc dl) { 1533 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1534 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1535 /*isVolatile*/false, /*AlwaysInline=*/true, 1536 NULL, 0, NULL, 0); 1537} 1538 1539/// IsTailCallConvention - Return true if the calling convention is one that 1540/// supports tail call optimization. 1541static bool IsTailCallConvention(CallingConv::ID CC) { 1542 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1543} 1544 1545/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1546/// a tailcall target by changing its ABI. 1547static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1548 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1549} 1550 1551SDValue 1552X86TargetLowering::LowerMemArgument(SDValue Chain, 1553 CallingConv::ID CallConv, 1554 const SmallVectorImpl<ISD::InputArg> &Ins, 1555 DebugLoc dl, SelectionDAG &DAG, 1556 const CCValAssign &VA, 1557 MachineFrameInfo *MFI, 1558 unsigned i) const { 1559 // Create the nodes corresponding to a load from this parameter slot. 1560 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1561 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1562 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1563 EVT ValVT; 1564 1565 // If value is passed by pointer we have address passed instead of the value 1566 // itself. 1567 if (VA.getLocInfo() == CCValAssign::Indirect) 1568 ValVT = VA.getLocVT(); 1569 else 1570 ValVT = VA.getValVT(); 1571 1572 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1573 // changed with more analysis. 1574 // In case of tail call optimization mark all arguments mutable. Since they 1575 // could be overwritten by lowering of arguments in case of a tail call. 1576 if (Flags.isByVal()) { 1577 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1578 VA.getLocMemOffset(), isImmutable); 1579 return DAG.getFrameIndex(FI, getPointerTy()); 1580 } else { 1581 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1582 VA.getLocMemOffset(), isImmutable); 1583 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1584 return DAG.getLoad(ValVT, dl, Chain, FIN, 1585 PseudoSourceValue::getFixedStack(FI), 0, 1586 false, false, 0); 1587 } 1588} 1589 1590SDValue 1591X86TargetLowering::LowerFormalArguments(SDValue Chain, 1592 CallingConv::ID CallConv, 1593 bool isVarArg, 1594 const SmallVectorImpl<ISD::InputArg> &Ins, 1595 DebugLoc dl, 1596 SelectionDAG &DAG, 1597 SmallVectorImpl<SDValue> &InVals) 1598 const { 1599 MachineFunction &MF = DAG.getMachineFunction(); 1600 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1601 1602 const Function* Fn = MF.getFunction(); 1603 if (Fn->hasExternalLinkage() && 1604 Subtarget->isTargetCygMing() && 1605 Fn->getName() == "main") 1606 FuncInfo->setForceFramePointer(true); 1607 1608 MachineFrameInfo *MFI = MF.getFrameInfo(); 1609 bool Is64Bit = Subtarget->is64Bit(); 1610 bool IsWin64 = Subtarget->isTargetWin64(); 1611 1612 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1613 "Var args not supported with calling convention fastcc or ghc"); 1614 1615 // Assign locations to all of the incoming arguments. 1616 SmallVector<CCValAssign, 16> ArgLocs; 1617 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1618 ArgLocs, *DAG.getContext()); 1619 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1620 1621 unsigned LastVal = ~0U; 1622 SDValue ArgValue; 1623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1624 CCValAssign &VA = ArgLocs[i]; 1625 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1626 // places. 1627 assert(VA.getValNo() != LastVal && 1628 "Don't support value assigned to multiple locs yet"); 1629 LastVal = VA.getValNo(); 1630 1631 if (VA.isRegLoc()) { 1632 EVT RegVT = VA.getLocVT(); 1633 TargetRegisterClass *RC = NULL; 1634 if (RegVT == MVT::i32) 1635 RC = X86::GR32RegisterClass; 1636 else if (Is64Bit && RegVT == MVT::i64) 1637 RC = X86::GR64RegisterClass; 1638 else if (RegVT == MVT::f32) 1639 RC = X86::FR32RegisterClass; 1640 else if (RegVT == MVT::f64) 1641 RC = X86::FR64RegisterClass; 1642 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1643 RC = X86::VR256RegisterClass; 1644 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1645 RC = X86::VR128RegisterClass; 1646 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1647 RC = X86::VR64RegisterClass; 1648 else 1649 llvm_unreachable("Unknown argument type!"); 1650 1651 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1652 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1653 1654 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1655 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1656 // right size. 1657 if (VA.getLocInfo() == CCValAssign::SExt) 1658 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1659 DAG.getValueType(VA.getValVT())); 1660 else if (VA.getLocInfo() == CCValAssign::ZExt) 1661 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1662 DAG.getValueType(VA.getValVT())); 1663 else if (VA.getLocInfo() == CCValAssign::BCvt) 1664 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1665 1666 if (VA.isExtInLoc()) { 1667 // Handle MMX values passed in XMM regs. 1668 if (RegVT.isVector()) { 1669 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1670 ArgValue, DAG.getConstant(0, MVT::i64)); 1671 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1672 } else 1673 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1674 } 1675 } else { 1676 assert(VA.isMemLoc()); 1677 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1678 } 1679 1680 // If value is passed via pointer - do a load. 1681 if (VA.getLocInfo() == CCValAssign::Indirect) 1682 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1683 false, false, 0); 1684 1685 InVals.push_back(ArgValue); 1686 } 1687 1688 // The x86-64 ABI for returning structs by value requires that we copy 1689 // the sret argument into %rax for the return. Save the argument into 1690 // a virtual register so that we can access it from the return points. 1691 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1692 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1693 unsigned Reg = FuncInfo->getSRetReturnReg(); 1694 if (!Reg) { 1695 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1696 FuncInfo->setSRetReturnReg(Reg); 1697 } 1698 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1699 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1700 } 1701 1702 unsigned StackSize = CCInfo.getNextStackOffset(); 1703 // Align stack specially for tail calls. 1704 if (FuncIsMadeTailCallSafe(CallConv)) 1705 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1706 1707 // If the function takes variable number of arguments, make a frame index for 1708 // the start of the first vararg value... for expansion of llvm.va_start. 1709 if (isVarArg) { 1710 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1711 CallConv != CallingConv::X86_ThisCall)) { 1712 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1713 } 1714 if (Is64Bit) { 1715 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1716 1717 // FIXME: We should really autogenerate these arrays 1718 static const unsigned GPR64ArgRegsWin64[] = { 1719 X86::RCX, X86::RDX, X86::R8, X86::R9 1720 }; 1721 static const unsigned XMMArgRegsWin64[] = { 1722 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1723 }; 1724 static const unsigned GPR64ArgRegs64Bit[] = { 1725 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1726 }; 1727 static const unsigned XMMArgRegs64Bit[] = { 1728 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1729 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1730 }; 1731 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1732 1733 if (IsWin64) { 1734 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1735 GPR64ArgRegs = GPR64ArgRegsWin64; 1736 XMMArgRegs = XMMArgRegsWin64; 1737 } else { 1738 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1739 GPR64ArgRegs = GPR64ArgRegs64Bit; 1740 XMMArgRegs = XMMArgRegs64Bit; 1741 } 1742 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1743 TotalNumIntRegs); 1744 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1745 TotalNumXMMRegs); 1746 1747 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1748 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1749 "SSE register cannot be used when SSE is disabled!"); 1750 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1751 "SSE register cannot be used when SSE is disabled!"); 1752 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1753 // Kernel mode asks for SSE to be disabled, so don't push them 1754 // on the stack. 1755 TotalNumXMMRegs = 0; 1756 1757 // For X86-64, if there are vararg parameters that are passed via 1758 // registers, then we must store them to their spots on the stack so they 1759 // may be loaded by deferencing the result of va_next. 1760 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1761 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1762 FuncInfo->setRegSaveFrameIndex( 1763 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1764 false)); 1765 1766 // Store the integer parameter registers. 1767 SmallVector<SDValue, 8> MemOps; 1768 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1769 getPointerTy()); 1770 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1771 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1772 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1773 DAG.getIntPtrConstant(Offset)); 1774 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1775 X86::GR64RegisterClass); 1776 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1777 SDValue Store = 1778 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1779 PseudoSourceValue::getFixedStack( 1780 FuncInfo->getRegSaveFrameIndex()), 1781 Offset, false, false, 0); 1782 MemOps.push_back(Store); 1783 Offset += 8; 1784 } 1785 1786 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1787 // Now store the XMM (fp + vector) parameter registers. 1788 SmallVector<SDValue, 11> SaveXMMOps; 1789 SaveXMMOps.push_back(Chain); 1790 1791 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1792 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1793 SaveXMMOps.push_back(ALVal); 1794 1795 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1796 FuncInfo->getRegSaveFrameIndex())); 1797 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1798 FuncInfo->getVarArgsFPOffset())); 1799 1800 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1801 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1802 X86::VR128RegisterClass); 1803 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1804 SaveXMMOps.push_back(Val); 1805 } 1806 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1807 MVT::Other, 1808 &SaveXMMOps[0], SaveXMMOps.size())); 1809 } 1810 1811 if (!MemOps.empty()) 1812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1813 &MemOps[0], MemOps.size()); 1814 } 1815 } 1816 1817 // Some CCs need callee pop. 1818 if (Subtarget->IsCalleePop(isVarArg, CallConv)) { 1819 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1820 } else { 1821 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1822 // If this is an sret function, the return should pop the hidden pointer. 1823 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1824 FuncInfo->setBytesToPopOnReturn(4); 1825 } 1826 1827 if (!Is64Bit) { 1828 // RegSaveFrameIndex is X86-64 only. 1829 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1830 if (CallConv == CallingConv::X86_FastCall || 1831 CallConv == CallingConv::X86_ThisCall) 1832 // fastcc functions can't have varargs. 1833 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1834 } 1835 1836 return Chain; 1837} 1838 1839SDValue 1840X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1841 SDValue StackPtr, SDValue Arg, 1842 DebugLoc dl, SelectionDAG &DAG, 1843 const CCValAssign &VA, 1844 ISD::ArgFlagsTy Flags) const { 1845 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1846 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1847 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1848 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1849 if (Flags.isByVal()) { 1850 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1851 } 1852 return DAG.getStore(Chain, dl, Arg, PtrOff, 1853 PseudoSourceValue::getStack(), LocMemOffset, 1854 false, false, 0); 1855} 1856 1857/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1858/// optimization is performed and it is required. 1859SDValue 1860X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1861 SDValue &OutRetAddr, SDValue Chain, 1862 bool IsTailCall, bool Is64Bit, 1863 int FPDiff, DebugLoc dl) const { 1864 // Adjust the Return address stack slot. 1865 EVT VT = getPointerTy(); 1866 OutRetAddr = getReturnAddressFrameIndex(DAG); 1867 1868 // Load the "old" Return address. 1869 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1870 return SDValue(OutRetAddr.getNode(), 1); 1871} 1872 1873/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1874/// optimization is performed and it is required (FPDiff!=0). 1875static SDValue 1876EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1877 SDValue Chain, SDValue RetAddrFrIdx, 1878 bool Is64Bit, int FPDiff, DebugLoc dl) { 1879 // Store the return address to the appropriate stack slot. 1880 if (!FPDiff) return Chain; 1881 // Calculate the new stack slot for the return address. 1882 int SlotSize = Is64Bit ? 8 : 4; 1883 int NewReturnAddrFI = 1884 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1885 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1886 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1887 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1888 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1889 false, false, 0); 1890 return Chain; 1891} 1892 1893SDValue 1894X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1895 CallingConv::ID CallConv, bool isVarArg, 1896 bool &isTailCall, 1897 const SmallVectorImpl<ISD::OutputArg> &Outs, 1898 const SmallVectorImpl<SDValue> &OutVals, 1899 const SmallVectorImpl<ISD::InputArg> &Ins, 1900 DebugLoc dl, SelectionDAG &DAG, 1901 SmallVectorImpl<SDValue> &InVals) const { 1902 MachineFunction &MF = DAG.getMachineFunction(); 1903 bool Is64Bit = Subtarget->is64Bit(); 1904 bool IsStructRet = CallIsStructReturn(Outs); 1905 bool IsSibcall = false; 1906 1907 if (isTailCall) { 1908 // Check if it's really possible to do a tail call. 1909 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1910 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1911 Outs, OutVals, Ins, DAG); 1912 1913 // Sibcalls are automatically detected tailcalls which do not require 1914 // ABI changes. 1915 if (!GuaranteedTailCallOpt && isTailCall) 1916 IsSibcall = true; 1917 1918 if (isTailCall) 1919 ++NumTailCalls; 1920 } 1921 1922 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1923 "Var args not supported with calling convention fastcc or ghc"); 1924 1925 // Analyze operands of the call, assigning locations to each operand. 1926 SmallVector<CCValAssign, 16> ArgLocs; 1927 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1928 ArgLocs, *DAG.getContext()); 1929 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1930 1931 // Get a count of how many bytes are to be pushed on the stack. 1932 unsigned NumBytes = CCInfo.getNextStackOffset(); 1933 if (IsSibcall) 1934 // This is a sibcall. The memory operands are available in caller's 1935 // own caller's stack. 1936 NumBytes = 0; 1937 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1938 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1939 1940 int FPDiff = 0; 1941 if (isTailCall && !IsSibcall) { 1942 // Lower arguments at fp - stackoffset + fpdiff. 1943 unsigned NumBytesCallerPushed = 1944 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1945 FPDiff = NumBytesCallerPushed - NumBytes; 1946 1947 // Set the delta of movement of the returnaddr stackslot. 1948 // But only set if delta is greater than previous delta. 1949 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1950 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1951 } 1952 1953 if (!IsSibcall) 1954 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1955 1956 SDValue RetAddrFrIdx; 1957 // Load return adress for tail calls. 1958 if (isTailCall && FPDiff) 1959 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1960 Is64Bit, FPDiff, dl); 1961 1962 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1963 SmallVector<SDValue, 8> MemOpChains; 1964 SDValue StackPtr; 1965 1966 // Walk the register/memloc assignments, inserting copies/loads. In the case 1967 // of tail call optimization arguments are handle later. 1968 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1969 CCValAssign &VA = ArgLocs[i]; 1970 EVT RegVT = VA.getLocVT(); 1971 SDValue Arg = OutVals[i]; 1972 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1973 bool isByVal = Flags.isByVal(); 1974 1975 // Promote the value if needed. 1976 switch (VA.getLocInfo()) { 1977 default: llvm_unreachable("Unknown loc info!"); 1978 case CCValAssign::Full: break; 1979 case CCValAssign::SExt: 1980 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1981 break; 1982 case CCValAssign::ZExt: 1983 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1984 break; 1985 case CCValAssign::AExt: 1986 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1987 // Special case: passing MMX values in XMM registers. 1988 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1989 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1990 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1991 } else 1992 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1993 break; 1994 case CCValAssign::BCvt: 1995 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1996 break; 1997 case CCValAssign::Indirect: { 1998 // Store the argument. 1999 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2000 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2001 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2002 PseudoSourceValue::getFixedStack(FI), 0, 2003 false, false, 0); 2004 Arg = SpillSlot; 2005 break; 2006 } 2007 } 2008 2009 if (VA.isRegLoc()) { 2010 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2011 if (isVarArg && Subtarget->isTargetWin64()) { 2012 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2013 // shadow reg if callee is a varargs function. 2014 unsigned ShadowReg = 0; 2015 switch (VA.getLocReg()) { 2016 case X86::XMM0: ShadowReg = X86::RCX; break; 2017 case X86::XMM1: ShadowReg = X86::RDX; break; 2018 case X86::XMM2: ShadowReg = X86::R8; break; 2019 case X86::XMM3: ShadowReg = X86::R9; break; 2020 } 2021 if (ShadowReg) 2022 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2023 } 2024 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2025 assert(VA.isMemLoc()); 2026 if (StackPtr.getNode() == 0) 2027 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2028 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2029 dl, DAG, VA, Flags)); 2030 } 2031 } 2032 2033 if (!MemOpChains.empty()) 2034 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2035 &MemOpChains[0], MemOpChains.size()); 2036 2037 // Build a sequence of copy-to-reg nodes chained together with token chain 2038 // and flag operands which copy the outgoing args into registers. 2039 SDValue InFlag; 2040 // Tail call byval lowering might overwrite argument registers so in case of 2041 // tail call optimization the copies to registers are lowered later. 2042 if (!isTailCall) 2043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2045 RegsToPass[i].second, InFlag); 2046 InFlag = Chain.getValue(1); 2047 } 2048 2049 if (Subtarget->isPICStyleGOT()) { 2050 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2051 // GOT pointer. 2052 if (!isTailCall) { 2053 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2054 DAG.getNode(X86ISD::GlobalBaseReg, 2055 DebugLoc(), getPointerTy()), 2056 InFlag); 2057 InFlag = Chain.getValue(1); 2058 } else { 2059 // If we are tail calling and generating PIC/GOT style code load the 2060 // address of the callee into ECX. The value in ecx is used as target of 2061 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2062 // for tail calls on PIC/GOT architectures. Normally we would just put the 2063 // address of GOT into ebx and then call target@PLT. But for tail calls 2064 // ebx would be restored (since ebx is callee saved) before jumping to the 2065 // target@PLT. 2066 2067 // Note: The actual moving to ECX is done further down. 2068 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2069 if (G && !G->getGlobal()->hasHiddenVisibility() && 2070 !G->getGlobal()->hasProtectedVisibility()) 2071 Callee = LowerGlobalAddress(Callee, DAG); 2072 else if (isa<ExternalSymbolSDNode>(Callee)) 2073 Callee = LowerExternalSymbol(Callee, DAG); 2074 } 2075 } 2076 2077 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { 2078 // From AMD64 ABI document: 2079 // For calls that may call functions that use varargs or stdargs 2080 // (prototype-less calls or calls to functions containing ellipsis (...) in 2081 // the declaration) %al is used as hidden argument to specify the number 2082 // of SSE registers used. The contents of %al do not need to match exactly 2083 // the number of registers, but must be an ubound on the number of SSE 2084 // registers used and is in the range 0 - 8 inclusive. 2085 2086 // Count the number of XMM registers allocated. 2087 static const unsigned XMMArgRegs[] = { 2088 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2089 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2090 }; 2091 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2092 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2093 && "SSE registers cannot be used when SSE is disabled"); 2094 2095 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2096 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2097 InFlag = Chain.getValue(1); 2098 } 2099 2100 2101 // For tail calls lower the arguments to the 'real' stack slot. 2102 if (isTailCall) { 2103 // Force all the incoming stack arguments to be loaded from the stack 2104 // before any new outgoing arguments are stored to the stack, because the 2105 // outgoing stack slots may alias the incoming argument stack slots, and 2106 // the alias isn't otherwise explicit. This is slightly more conservative 2107 // than necessary, because it means that each store effectively depends 2108 // on every argument instead of just those arguments it would clobber. 2109 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2110 2111 SmallVector<SDValue, 8> MemOpChains2; 2112 SDValue FIN; 2113 int FI = 0; 2114 // Do not flag preceeding copytoreg stuff together with the following stuff. 2115 InFlag = SDValue(); 2116 if (GuaranteedTailCallOpt) { 2117 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2118 CCValAssign &VA = ArgLocs[i]; 2119 if (VA.isRegLoc()) 2120 continue; 2121 assert(VA.isMemLoc()); 2122 SDValue Arg = OutVals[i]; 2123 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2124 // Create frame index. 2125 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2126 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2127 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2128 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2129 2130 if (Flags.isByVal()) { 2131 // Copy relative to framepointer. 2132 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2133 if (StackPtr.getNode() == 0) 2134 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2135 getPointerTy()); 2136 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2137 2138 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2139 ArgChain, 2140 Flags, DAG, dl)); 2141 } else { 2142 // Store relative to framepointer. 2143 MemOpChains2.push_back( 2144 DAG.getStore(ArgChain, dl, Arg, FIN, 2145 PseudoSourceValue::getFixedStack(FI), 0, 2146 false, false, 0)); 2147 } 2148 } 2149 } 2150 2151 if (!MemOpChains2.empty()) 2152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2153 &MemOpChains2[0], MemOpChains2.size()); 2154 2155 // Copy arguments to their registers. 2156 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2157 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2158 RegsToPass[i].second, InFlag); 2159 InFlag = Chain.getValue(1); 2160 } 2161 InFlag =SDValue(); 2162 2163 // Store the return address to the appropriate stack slot. 2164 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2165 FPDiff, dl); 2166 } 2167 2168 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2169 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2170 // In the 64-bit large code model, we have to make all calls 2171 // through a register, since the call instruction's 32-bit 2172 // pc-relative offset may not be large enough to hold the whole 2173 // address. 2174 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2175 // If the callee is a GlobalAddress node (quite common, every direct call 2176 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2177 // it. 2178 2179 // We should use extra load for direct calls to dllimported functions in 2180 // non-JIT mode. 2181 const GlobalValue *GV = G->getGlobal(); 2182 if (!GV->hasDLLImportLinkage()) { 2183 unsigned char OpFlags = 0; 2184 2185 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2186 // external symbols most go through the PLT in PIC mode. If the symbol 2187 // has hidden or protected visibility, or if it is static or local, then 2188 // we don't need to use the PLT - we can directly call it. 2189 if (Subtarget->isTargetELF() && 2190 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2191 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2192 OpFlags = X86II::MO_PLT; 2193 } else if (Subtarget->isPICStyleStubAny() && 2194 (GV->isDeclaration() || GV->isWeakForLinker()) && 2195 Subtarget->getDarwinVers() < 9) { 2196 // PC-relative references to external symbols should go through $stub, 2197 // unless we're building with the leopard linker or later, which 2198 // automatically synthesizes these stubs. 2199 OpFlags = X86II::MO_DARWIN_STUB; 2200 } 2201 2202 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2203 G->getOffset(), OpFlags); 2204 } 2205 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2206 unsigned char OpFlags = 0; 2207 2208 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2209 // symbols should go through the PLT. 2210 if (Subtarget->isTargetELF() && 2211 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2212 OpFlags = X86II::MO_PLT; 2213 } else if (Subtarget->isPICStyleStubAny() && 2214 Subtarget->getDarwinVers() < 9) { 2215 // PC-relative references to external symbols should go through $stub, 2216 // unless we're building with the leopard linker or later, which 2217 // automatically synthesizes these stubs. 2218 OpFlags = X86II::MO_DARWIN_STUB; 2219 } 2220 2221 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2222 OpFlags); 2223 } 2224 2225 // Returns a chain & a flag for retval copy to use. 2226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2227 SmallVector<SDValue, 8> Ops; 2228 2229 if (!IsSibcall && isTailCall) { 2230 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2231 DAG.getIntPtrConstant(0, true), InFlag); 2232 InFlag = Chain.getValue(1); 2233 } 2234 2235 Ops.push_back(Chain); 2236 Ops.push_back(Callee); 2237 2238 if (isTailCall) 2239 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2240 2241 // Add argument registers to the end of the list so that they are known live 2242 // into the call. 2243 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2244 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2245 RegsToPass[i].second.getValueType())); 2246 2247 // Add an implicit use GOT pointer in EBX. 2248 if (!isTailCall && Subtarget->isPICStyleGOT()) 2249 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2250 2251 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2252 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) 2253 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2254 2255 if (InFlag.getNode()) 2256 Ops.push_back(InFlag); 2257 2258 if (isTailCall) { 2259 // We used to do: 2260 //// If this is the first return lowered for this function, add the regs 2261 //// to the liveout set for the function. 2262 // This isn't right, although it's probably harmless on x86; liveouts 2263 // should be computed from returns not tail calls. Consider a void 2264 // function making a tail call to a function returning int. 2265 return DAG.getNode(X86ISD::TC_RETURN, dl, 2266 NodeTys, &Ops[0], Ops.size()); 2267 } 2268 2269 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2270 InFlag = Chain.getValue(1); 2271 2272 // Create the CALLSEQ_END node. 2273 unsigned NumBytesForCalleeToPush; 2274 if (Subtarget->IsCalleePop(isVarArg, CallConv)) 2275 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2276 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2277 // If this is a call to a struct-return function, the callee 2278 // pops the hidden struct pointer, so we have to push it back. 2279 // This is common for Darwin/X86, Linux & Mingw32 targets. 2280 NumBytesForCalleeToPush = 4; 2281 else 2282 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2283 2284 // Returns a flag for retval copy to use. 2285 if (!IsSibcall) { 2286 Chain = DAG.getCALLSEQ_END(Chain, 2287 DAG.getIntPtrConstant(NumBytes, true), 2288 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2289 true), 2290 InFlag); 2291 InFlag = Chain.getValue(1); 2292 } 2293 2294 // Handle result values, copying them out of physregs into vregs that we 2295 // return. 2296 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2297 Ins, dl, DAG, InVals); 2298} 2299 2300 2301//===----------------------------------------------------------------------===// 2302// Fast Calling Convention (tail call) implementation 2303//===----------------------------------------------------------------------===// 2304 2305// Like std call, callee cleans arguments, convention except that ECX is 2306// reserved for storing the tail called function address. Only 2 registers are 2307// free for argument passing (inreg). Tail call optimization is performed 2308// provided: 2309// * tailcallopt is enabled 2310// * caller/callee are fastcc 2311// On X86_64 architecture with GOT-style position independent code only local 2312// (within module) calls are supported at the moment. 2313// To keep the stack aligned according to platform abi the function 2314// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2315// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2316// If a tail called function callee has more arguments than the caller the 2317// caller needs to make sure that there is room to move the RETADDR to. This is 2318// achieved by reserving an area the size of the argument delta right after the 2319// original REtADDR, but before the saved framepointer or the spilled registers 2320// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2321// stack layout: 2322// arg1 2323// arg2 2324// RETADDR 2325// [ new RETADDR 2326// move area ] 2327// (possible EBP) 2328// ESI 2329// EDI 2330// local1 .. 2331 2332/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2333/// for a 16 byte align requirement. 2334unsigned 2335X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2336 SelectionDAG& DAG) const { 2337 MachineFunction &MF = DAG.getMachineFunction(); 2338 const TargetMachine &TM = MF.getTarget(); 2339 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2340 unsigned StackAlignment = TFI.getStackAlignment(); 2341 uint64_t AlignMask = StackAlignment - 1; 2342 int64_t Offset = StackSize; 2343 uint64_t SlotSize = TD->getPointerSize(); 2344 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2345 // Number smaller than 12 so just add the difference. 2346 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2347 } else { 2348 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2349 Offset = ((~AlignMask) & Offset) + StackAlignment + 2350 (StackAlignment-SlotSize); 2351 } 2352 return Offset; 2353} 2354 2355/// MatchingStackOffset - Return true if the given stack call argument is 2356/// already available in the same position (relatively) of the caller's 2357/// incoming argument stack. 2358static 2359bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2360 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2361 const X86InstrInfo *TII) { 2362 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2363 int FI = INT_MAX; 2364 if (Arg.getOpcode() == ISD::CopyFromReg) { 2365 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2366 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2367 return false; 2368 MachineInstr *Def = MRI->getVRegDef(VR); 2369 if (!Def) 2370 return false; 2371 if (!Flags.isByVal()) { 2372 if (!TII->isLoadFromStackSlot(Def, FI)) 2373 return false; 2374 } else { 2375 unsigned Opcode = Def->getOpcode(); 2376 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2377 Def->getOperand(1).isFI()) { 2378 FI = Def->getOperand(1).getIndex(); 2379 Bytes = Flags.getByValSize(); 2380 } else 2381 return false; 2382 } 2383 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2384 if (Flags.isByVal()) 2385 // ByVal argument is passed in as a pointer but it's now being 2386 // dereferenced. e.g. 2387 // define @foo(%struct.X* %A) { 2388 // tail call @bar(%struct.X* byval %A) 2389 // } 2390 return false; 2391 SDValue Ptr = Ld->getBasePtr(); 2392 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2393 if (!FINode) 2394 return false; 2395 FI = FINode->getIndex(); 2396 } else 2397 return false; 2398 2399 assert(FI != INT_MAX); 2400 if (!MFI->isFixedObjectIndex(FI)) 2401 return false; 2402 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2403} 2404 2405/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2406/// for tail call optimization. Targets which want to do tail call 2407/// optimization should implement this function. 2408bool 2409X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2410 CallingConv::ID CalleeCC, 2411 bool isVarArg, 2412 bool isCalleeStructRet, 2413 bool isCallerStructRet, 2414 const SmallVectorImpl<ISD::OutputArg> &Outs, 2415 const SmallVectorImpl<SDValue> &OutVals, 2416 const SmallVectorImpl<ISD::InputArg> &Ins, 2417 SelectionDAG& DAG) const { 2418 if (!IsTailCallConvention(CalleeCC) && 2419 CalleeCC != CallingConv::C) 2420 return false; 2421 2422 // If -tailcallopt is specified, make fastcc functions tail-callable. 2423 const MachineFunction &MF = DAG.getMachineFunction(); 2424 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2425 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2426 bool CCMatch = CallerCC == CalleeCC; 2427 2428 if (GuaranteedTailCallOpt) { 2429 if (IsTailCallConvention(CalleeCC) && CCMatch) 2430 return true; 2431 return false; 2432 } 2433 2434 // Look for obvious safe cases to perform tail call optimization that do not 2435 // require ABI changes. This is what gcc calls sibcall. 2436 2437 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2438 // emit a special epilogue. 2439 if (RegInfo->needsStackRealignment(MF)) 2440 return false; 2441 2442 // Do not sibcall optimize vararg calls unless the call site is not passing 2443 // any arguments. 2444 if (isVarArg && !Outs.empty()) 2445 return false; 2446 2447 // Also avoid sibcall optimization if either caller or callee uses struct 2448 // return semantics. 2449 if (isCalleeStructRet || isCallerStructRet) 2450 return false; 2451 2452 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2453 // Therefore if it's not used by the call it is not safe to optimize this into 2454 // a sibcall. 2455 bool Unused = false; 2456 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2457 if (!Ins[i].Used) { 2458 Unused = true; 2459 break; 2460 } 2461 } 2462 if (Unused) { 2463 SmallVector<CCValAssign, 16> RVLocs; 2464 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2465 RVLocs, *DAG.getContext()); 2466 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2467 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2468 CCValAssign &VA = RVLocs[i]; 2469 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2470 return false; 2471 } 2472 } 2473 2474 // If the calling conventions do not match, then we'd better make sure the 2475 // results are returned in the same way as what the caller expects. 2476 if (!CCMatch) { 2477 SmallVector<CCValAssign, 16> RVLocs1; 2478 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 2479 RVLocs1, *DAG.getContext()); 2480 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2481 2482 SmallVector<CCValAssign, 16> RVLocs2; 2483 CCState CCInfo2(CallerCC, false, getTargetMachine(), 2484 RVLocs2, *DAG.getContext()); 2485 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2486 2487 if (RVLocs1.size() != RVLocs2.size()) 2488 return false; 2489 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2490 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2491 return false; 2492 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2493 return false; 2494 if (RVLocs1[i].isRegLoc()) { 2495 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2496 return false; 2497 } else { 2498 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2499 return false; 2500 } 2501 } 2502 } 2503 2504 // If the callee takes no arguments then go on to check the results of the 2505 // call. 2506 if (!Outs.empty()) { 2507 // Check if stack adjustment is needed. For now, do not do this if any 2508 // argument is passed on the stack. 2509 SmallVector<CCValAssign, 16> ArgLocs; 2510 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2511 ArgLocs, *DAG.getContext()); 2512 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2513 if (CCInfo.getNextStackOffset()) { 2514 MachineFunction &MF = DAG.getMachineFunction(); 2515 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2516 return false; 2517 if (Subtarget->isTargetWin64()) 2518 // Win64 ABI has additional complications. 2519 return false; 2520 2521 // Check if the arguments are already laid out in the right way as 2522 // the caller's fixed stack objects. 2523 MachineFrameInfo *MFI = MF.getFrameInfo(); 2524 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2525 const X86InstrInfo *TII = 2526 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2527 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2528 CCValAssign &VA = ArgLocs[i]; 2529 SDValue Arg = OutVals[i]; 2530 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2531 if (VA.getLocInfo() == CCValAssign::Indirect) 2532 return false; 2533 if (!VA.isRegLoc()) { 2534 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2535 MFI, MRI, TII)) 2536 return false; 2537 } 2538 } 2539 } 2540 2541 // If the tailcall address may be in a register, then make sure it's 2542 // possible to register allocate for it. In 32-bit, the call address can 2543 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2544 // callee-saved registers are restored. These happen to be the same 2545 // registers used to pass 'inreg' arguments so watch out for those. 2546 if (!Subtarget->is64Bit() && 2547 !isa<GlobalAddressSDNode>(Callee) && 2548 !isa<ExternalSymbolSDNode>(Callee)) { 2549 unsigned NumInRegs = 0; 2550 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2551 CCValAssign &VA = ArgLocs[i]; 2552 if (!VA.isRegLoc()) 2553 continue; 2554 unsigned Reg = VA.getLocReg(); 2555 switch (Reg) { 2556 default: break; 2557 case X86::EAX: case X86::EDX: case X86::ECX: 2558 if (++NumInRegs == 3) 2559 return false; 2560 break; 2561 } 2562 } 2563 } 2564 } 2565 2566 return true; 2567} 2568 2569FastISel * 2570X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2571 return X86::createFastISel(funcInfo); 2572} 2573 2574 2575//===----------------------------------------------------------------------===// 2576// Other Lowering Hooks 2577//===----------------------------------------------------------------------===// 2578 2579static bool MayFoldLoad(SDValue Op) { 2580 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2581} 2582 2583static bool MayFoldIntoStore(SDValue Op) { 2584 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2585} 2586 2587static bool isTargetShuffle(unsigned Opcode) { 2588 switch(Opcode) { 2589 default: return false; 2590 case X86ISD::PSHUFD: 2591 case X86ISD::PSHUFHW: 2592 case X86ISD::PSHUFLW: 2593 case X86ISD::SHUFPD: 2594 case X86ISD::SHUFPS: 2595 case X86ISD::MOVLHPS: 2596 case X86ISD::MOVLHPD: 2597 case X86ISD::MOVHLPS: 2598 case X86ISD::MOVLPS: 2599 case X86ISD::MOVLPD: 2600 case X86ISD::MOVSHDUP: 2601 case X86ISD::MOVSLDUP: 2602 case X86ISD::MOVSS: 2603 case X86ISD::MOVSD: 2604 case X86ISD::PUNPCKLDQ: 2605 return true; 2606 } 2607 return false; 2608} 2609 2610static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2611 SDValue V1, SelectionDAG &DAG) { 2612 switch(Opc) { 2613 default: llvm_unreachable("Unknown x86 shuffle node"); 2614 case X86ISD::MOVSHDUP: 2615 case X86ISD::MOVSLDUP: 2616 return DAG.getNode(Opc, dl, VT, V1); 2617 } 2618 2619 return SDValue(); 2620} 2621 2622static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2623 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2624 switch(Opc) { 2625 default: llvm_unreachable("Unknown x86 shuffle node"); 2626 case X86ISD::PSHUFD: 2627 case X86ISD::PSHUFHW: 2628 case X86ISD::PSHUFLW: 2629 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2630 } 2631 2632 return SDValue(); 2633} 2634 2635static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2636 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2637 switch(Opc) { 2638 default: llvm_unreachable("Unknown x86 shuffle node"); 2639 case X86ISD::SHUFPD: 2640 case X86ISD::SHUFPS: 2641 return DAG.getNode(Opc, dl, VT, V1, V2, 2642 DAG.getConstant(TargetMask, MVT::i8)); 2643 } 2644 return SDValue(); 2645} 2646 2647static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2648 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2649 switch(Opc) { 2650 default: llvm_unreachable("Unknown x86 shuffle node"); 2651 case X86ISD::MOVLHPS: 2652 case X86ISD::MOVLHPD: 2653 case X86ISD::MOVHLPS: 2654 case X86ISD::MOVLPS: 2655 case X86ISD::MOVLPD: 2656 case X86ISD::MOVSS: 2657 case X86ISD::MOVSD: 2658 case X86ISD::PUNPCKLDQ: 2659 return DAG.getNode(Opc, dl, VT, V1, V2); 2660 } 2661 return SDValue(); 2662} 2663 2664SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2665 MachineFunction &MF = DAG.getMachineFunction(); 2666 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2667 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2668 2669 if (ReturnAddrIndex == 0) { 2670 // Set up a frame object for the return address. 2671 uint64_t SlotSize = TD->getPointerSize(); 2672 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2673 false); 2674 FuncInfo->setRAIndex(ReturnAddrIndex); 2675 } 2676 2677 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2678} 2679 2680 2681bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2682 bool hasSymbolicDisplacement) { 2683 // Offset should fit into 32 bit immediate field. 2684 if (!isInt<32>(Offset)) 2685 return false; 2686 2687 // If we don't have a symbolic displacement - we don't have any extra 2688 // restrictions. 2689 if (!hasSymbolicDisplacement) 2690 return true; 2691 2692 // FIXME: Some tweaks might be needed for medium code model. 2693 if (M != CodeModel::Small && M != CodeModel::Kernel) 2694 return false; 2695 2696 // For small code model we assume that latest object is 16MB before end of 31 2697 // bits boundary. We may also accept pretty large negative constants knowing 2698 // that all objects are in the positive half of address space. 2699 if (M == CodeModel::Small && Offset < 16*1024*1024) 2700 return true; 2701 2702 // For kernel code model we know that all object resist in the negative half 2703 // of 32bits address space. We may not accept negative offsets, since they may 2704 // be just off and we may accept pretty large positive ones. 2705 if (M == CodeModel::Kernel && Offset > 0) 2706 return true; 2707 2708 return false; 2709} 2710 2711/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2712/// specific condition code, returning the condition code and the LHS/RHS of the 2713/// comparison to make. 2714static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2716 if (!isFP) { 2717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2719 // X > -1 -> X == 0, jump !sign. 2720 RHS = DAG.getConstant(0, RHS.getValueType()); 2721 return X86::COND_NS; 2722 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2723 // X < 0 -> X == 0, jump on sign. 2724 return X86::COND_S; 2725 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2726 // X < 1 -> X <= 0 2727 RHS = DAG.getConstant(0, RHS.getValueType()); 2728 return X86::COND_LE; 2729 } 2730 } 2731 2732 switch (SetCCOpcode) { 2733 default: llvm_unreachable("Invalid integer condition!"); 2734 case ISD::SETEQ: return X86::COND_E; 2735 case ISD::SETGT: return X86::COND_G; 2736 case ISD::SETGE: return X86::COND_GE; 2737 case ISD::SETLT: return X86::COND_L; 2738 case ISD::SETLE: return X86::COND_LE; 2739 case ISD::SETNE: return X86::COND_NE; 2740 case ISD::SETULT: return X86::COND_B; 2741 case ISD::SETUGT: return X86::COND_A; 2742 case ISD::SETULE: return X86::COND_BE; 2743 case ISD::SETUGE: return X86::COND_AE; 2744 } 2745 } 2746 2747 // First determine if it is required or is profitable to flip the operands. 2748 2749 // If LHS is a foldable load, but RHS is not, flip the condition. 2750 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2751 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2752 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2753 std::swap(LHS, RHS); 2754 } 2755 2756 switch (SetCCOpcode) { 2757 default: break; 2758 case ISD::SETOLT: 2759 case ISD::SETOLE: 2760 case ISD::SETUGT: 2761 case ISD::SETUGE: 2762 std::swap(LHS, RHS); 2763 break; 2764 } 2765 2766 // On a floating point condition, the flags are set as follows: 2767 // ZF PF CF op 2768 // 0 | 0 | 0 | X > Y 2769 // 0 | 0 | 1 | X < Y 2770 // 1 | 0 | 0 | X == Y 2771 // 1 | 1 | 1 | unordered 2772 switch (SetCCOpcode) { 2773 default: llvm_unreachable("Condcode should be pre-legalized away"); 2774 case ISD::SETUEQ: 2775 case ISD::SETEQ: return X86::COND_E; 2776 case ISD::SETOLT: // flipped 2777 case ISD::SETOGT: 2778 case ISD::SETGT: return X86::COND_A; 2779 case ISD::SETOLE: // flipped 2780 case ISD::SETOGE: 2781 case ISD::SETGE: return X86::COND_AE; 2782 case ISD::SETUGT: // flipped 2783 case ISD::SETULT: 2784 case ISD::SETLT: return X86::COND_B; 2785 case ISD::SETUGE: // flipped 2786 case ISD::SETULE: 2787 case ISD::SETLE: return X86::COND_BE; 2788 case ISD::SETONE: 2789 case ISD::SETNE: return X86::COND_NE; 2790 case ISD::SETUO: return X86::COND_P; 2791 case ISD::SETO: return X86::COND_NP; 2792 case ISD::SETOEQ: 2793 case ISD::SETUNE: return X86::COND_INVALID; 2794 } 2795} 2796 2797/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2798/// code. Current x86 isa includes the following FP cmov instructions: 2799/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2800static bool hasFPCMov(unsigned X86CC) { 2801 switch (X86CC) { 2802 default: 2803 return false; 2804 case X86::COND_B: 2805 case X86::COND_BE: 2806 case X86::COND_E: 2807 case X86::COND_P: 2808 case X86::COND_A: 2809 case X86::COND_AE: 2810 case X86::COND_NE: 2811 case X86::COND_NP: 2812 return true; 2813 } 2814} 2815 2816/// isFPImmLegal - Returns true if the target can instruction select the 2817/// specified FP immediate natively. If false, the legalizer will 2818/// materialize the FP immediate as a load from a constant pool. 2819bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2820 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2821 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2822 return true; 2823 } 2824 return false; 2825} 2826 2827/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2828/// the specified range (L, H]. 2829static bool isUndefOrInRange(int Val, int Low, int Hi) { 2830 return (Val < 0) || (Val >= Low && Val < Hi); 2831} 2832 2833/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2834/// specified value. 2835static bool isUndefOrEqual(int Val, int CmpVal) { 2836 if (Val < 0 || Val == CmpVal) 2837 return true; 2838 return false; 2839} 2840 2841/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2842/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2843/// the second operand. 2844static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2845 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2846 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2847 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2848 return (Mask[0] < 2 && Mask[1] < 2); 2849 return false; 2850} 2851 2852bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2853 SmallVector<int, 8> M; 2854 N->getMask(M); 2855 return ::isPSHUFDMask(M, N->getValueType(0)); 2856} 2857 2858/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2859/// is suitable for input to PSHUFHW. 2860static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2861 if (VT != MVT::v8i16) 2862 return false; 2863 2864 // Lower quadword copied in order or undef. 2865 for (int i = 0; i != 4; ++i) 2866 if (Mask[i] >= 0 && Mask[i] != i) 2867 return false; 2868 2869 // Upper quadword shuffled. 2870 for (int i = 4; i != 8; ++i) 2871 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2872 return false; 2873 2874 return true; 2875} 2876 2877bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2878 SmallVector<int, 8> M; 2879 N->getMask(M); 2880 return ::isPSHUFHWMask(M, N->getValueType(0)); 2881} 2882 2883/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2884/// is suitable for input to PSHUFLW. 2885static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2886 if (VT != MVT::v8i16) 2887 return false; 2888 2889 // Upper quadword copied in order. 2890 for (int i = 4; i != 8; ++i) 2891 if (Mask[i] >= 0 && Mask[i] != i) 2892 return false; 2893 2894 // Lower quadword shuffled. 2895 for (int i = 0; i != 4; ++i) 2896 if (Mask[i] >= 4) 2897 return false; 2898 2899 return true; 2900} 2901 2902bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2903 SmallVector<int, 8> M; 2904 N->getMask(M); 2905 return ::isPSHUFLWMask(M, N->getValueType(0)); 2906} 2907 2908/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2909/// is suitable for input to PALIGNR. 2910static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2911 bool hasSSSE3) { 2912 int i, e = VT.getVectorNumElements(); 2913 2914 // Do not handle v2i64 / v2f64 shuffles with palignr. 2915 if (e < 4 || !hasSSSE3) 2916 return false; 2917 2918 for (i = 0; i != e; ++i) 2919 if (Mask[i] >= 0) 2920 break; 2921 2922 // All undef, not a palignr. 2923 if (i == e) 2924 return false; 2925 2926 // Determine if it's ok to perform a palignr with only the LHS, since we 2927 // don't have access to the actual shuffle elements to see if RHS is undef. 2928 bool Unary = Mask[i] < (int)e; 2929 bool NeedsUnary = false; 2930 2931 int s = Mask[i] - i; 2932 2933 // Check the rest of the elements to see if they are consecutive. 2934 for (++i; i != e; ++i) { 2935 int m = Mask[i]; 2936 if (m < 0) 2937 continue; 2938 2939 Unary = Unary && (m < (int)e); 2940 NeedsUnary = NeedsUnary || (m < s); 2941 2942 if (NeedsUnary && !Unary) 2943 return false; 2944 if (Unary && m != ((s+i) & (e-1))) 2945 return false; 2946 if (!Unary && m != (s+i)) 2947 return false; 2948 } 2949 return true; 2950} 2951 2952bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2953 SmallVector<int, 8> M; 2954 N->getMask(M); 2955 return ::isPALIGNRMask(M, N->getValueType(0), true); 2956} 2957 2958/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2959/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2960static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2961 int NumElems = VT.getVectorNumElements(); 2962 if (NumElems != 2 && NumElems != 4) 2963 return false; 2964 2965 int Half = NumElems / 2; 2966 for (int i = 0; i < Half; ++i) 2967 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2968 return false; 2969 for (int i = Half; i < NumElems; ++i) 2970 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2971 return false; 2972 2973 return true; 2974} 2975 2976bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2977 SmallVector<int, 8> M; 2978 N->getMask(M); 2979 return ::isSHUFPMask(M, N->getValueType(0)); 2980} 2981 2982/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2983/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2984/// half elements to come from vector 1 (which would equal the dest.) and 2985/// the upper half to come from vector 2. 2986static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2987 int NumElems = VT.getVectorNumElements(); 2988 2989 if (NumElems != 2 && NumElems != 4) 2990 return false; 2991 2992 int Half = NumElems / 2; 2993 for (int i = 0; i < Half; ++i) 2994 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2995 return false; 2996 for (int i = Half; i < NumElems; ++i) 2997 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2998 return false; 2999 return true; 3000} 3001 3002static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3003 SmallVector<int, 8> M; 3004 N->getMask(M); 3005 return isCommutedSHUFPMask(M, N->getValueType(0)); 3006} 3007 3008/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3009/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3010bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3011 if (N->getValueType(0).getVectorNumElements() != 4) 3012 return false; 3013 3014 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3015 return isUndefOrEqual(N->getMaskElt(0), 6) && 3016 isUndefOrEqual(N->getMaskElt(1), 7) && 3017 isUndefOrEqual(N->getMaskElt(2), 2) && 3018 isUndefOrEqual(N->getMaskElt(3), 3); 3019} 3020 3021/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3022/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3023/// <2, 3, 2, 3> 3024bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3025 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3026 3027 if (NumElems != 4) 3028 return false; 3029 3030 return isUndefOrEqual(N->getMaskElt(0), 2) && 3031 isUndefOrEqual(N->getMaskElt(1), 3) && 3032 isUndefOrEqual(N->getMaskElt(2), 2) && 3033 isUndefOrEqual(N->getMaskElt(3), 3); 3034} 3035 3036/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3037/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3038bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3039 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3040 3041 if (NumElems != 2 && NumElems != 4) 3042 return false; 3043 3044 for (unsigned i = 0; i < NumElems/2; ++i) 3045 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3046 return false; 3047 3048 for (unsigned i = NumElems/2; i < NumElems; ++i) 3049 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3050 return false; 3051 3052 return true; 3053} 3054 3055/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3056/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3057bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3058 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3059 3060 if (NumElems != 2 && NumElems != 4) 3061 return false; 3062 3063 for (unsigned i = 0; i < NumElems/2; ++i) 3064 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3065 return false; 3066 3067 for (unsigned i = 0; i < NumElems/2; ++i) 3068 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3069 return false; 3070 3071 return true; 3072} 3073 3074/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3075/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3076static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3077 bool V2IsSplat = false) { 3078 int NumElts = VT.getVectorNumElements(); 3079 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3080 return false; 3081 3082 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3083 int BitI = Mask[i]; 3084 int BitI1 = Mask[i+1]; 3085 if (!isUndefOrEqual(BitI, j)) 3086 return false; 3087 if (V2IsSplat) { 3088 if (!isUndefOrEqual(BitI1, NumElts)) 3089 return false; 3090 } else { 3091 if (!isUndefOrEqual(BitI1, j + NumElts)) 3092 return false; 3093 } 3094 } 3095 return true; 3096} 3097 3098bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3099 SmallVector<int, 8> M; 3100 N->getMask(M); 3101 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3102} 3103 3104/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3105/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3106static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3107 bool V2IsSplat = false) { 3108 int NumElts = VT.getVectorNumElements(); 3109 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3110 return false; 3111 3112 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3113 int BitI = Mask[i]; 3114 int BitI1 = Mask[i+1]; 3115 if (!isUndefOrEqual(BitI, j + NumElts/2)) 3116 return false; 3117 if (V2IsSplat) { 3118 if (isUndefOrEqual(BitI1, NumElts)) 3119 return false; 3120 } else { 3121 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 3122 return false; 3123 } 3124 } 3125 return true; 3126} 3127 3128bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3129 SmallVector<int, 8> M; 3130 N->getMask(M); 3131 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3132} 3133 3134/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3135/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3136/// <0, 0, 1, 1> 3137static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3138 int NumElems = VT.getVectorNumElements(); 3139 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3140 return false; 3141 3142 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 3143 int BitI = Mask[i]; 3144 int BitI1 = Mask[i+1]; 3145 if (!isUndefOrEqual(BitI, j)) 3146 return false; 3147 if (!isUndefOrEqual(BitI1, j)) 3148 return false; 3149 } 3150 return true; 3151} 3152 3153bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3154 SmallVector<int, 8> M; 3155 N->getMask(M); 3156 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3157} 3158 3159/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3160/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3161/// <2, 2, 3, 3> 3162static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3163 int NumElems = VT.getVectorNumElements(); 3164 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3165 return false; 3166 3167 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3168 int BitI = Mask[i]; 3169 int BitI1 = Mask[i+1]; 3170 if (!isUndefOrEqual(BitI, j)) 3171 return false; 3172 if (!isUndefOrEqual(BitI1, j)) 3173 return false; 3174 } 3175 return true; 3176} 3177 3178bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3179 SmallVector<int, 8> M; 3180 N->getMask(M); 3181 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3182} 3183 3184/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3185/// specifies a shuffle of elements that is suitable for input to MOVSS, 3186/// MOVSD, and MOVD, i.e. setting the lowest element. 3187static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3188 if (VT.getVectorElementType().getSizeInBits() < 32) 3189 return false; 3190 3191 int NumElts = VT.getVectorNumElements(); 3192 3193 if (!isUndefOrEqual(Mask[0], NumElts)) 3194 return false; 3195 3196 for (int i = 1; i < NumElts; ++i) 3197 if (!isUndefOrEqual(Mask[i], i)) 3198 return false; 3199 3200 return true; 3201} 3202 3203bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3204 SmallVector<int, 8> M; 3205 N->getMask(M); 3206 return ::isMOVLMask(M, N->getValueType(0)); 3207} 3208 3209/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3210/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3211/// element of vector 2 and the other elements to come from vector 1 in order. 3212static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3213 bool V2IsSplat = false, bool V2IsUndef = false) { 3214 int NumOps = VT.getVectorNumElements(); 3215 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3216 return false; 3217 3218 if (!isUndefOrEqual(Mask[0], 0)) 3219 return false; 3220 3221 for (int i = 1; i < NumOps; ++i) 3222 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3223 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3224 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3225 return false; 3226 3227 return true; 3228} 3229 3230static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3231 bool V2IsUndef = false) { 3232 SmallVector<int, 8> M; 3233 N->getMask(M); 3234 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3235} 3236 3237/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3238/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3239bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3240 if (N->getValueType(0).getVectorNumElements() != 4) 3241 return false; 3242 3243 // Expect 1, 1, 3, 3 3244 for (unsigned i = 0; i < 2; ++i) { 3245 int Elt = N->getMaskElt(i); 3246 if (Elt >= 0 && Elt != 1) 3247 return false; 3248 } 3249 3250 bool HasHi = false; 3251 for (unsigned i = 2; i < 4; ++i) { 3252 int Elt = N->getMaskElt(i); 3253 if (Elt >= 0 && Elt != 3) 3254 return false; 3255 if (Elt == 3) 3256 HasHi = true; 3257 } 3258 // Don't use movshdup if it can be done with a shufps. 3259 // FIXME: verify that matching u, u, 3, 3 is what we want. 3260 return HasHi; 3261} 3262 3263/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3264/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3265bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3266 if (N->getValueType(0).getVectorNumElements() != 4) 3267 return false; 3268 3269 // Expect 0, 0, 2, 2 3270 for (unsigned i = 0; i < 2; ++i) 3271 if (N->getMaskElt(i) > 0) 3272 return false; 3273 3274 bool HasHi = false; 3275 for (unsigned i = 2; i < 4; ++i) { 3276 int Elt = N->getMaskElt(i); 3277 if (Elt >= 0 && Elt != 2) 3278 return false; 3279 if (Elt == 2) 3280 HasHi = true; 3281 } 3282 // Don't use movsldup if it can be done with a shufps. 3283 return HasHi; 3284} 3285 3286/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3287/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3288bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3289 int e = N->getValueType(0).getVectorNumElements() / 2; 3290 3291 for (int i = 0; i < e; ++i) 3292 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3293 return false; 3294 for (int i = 0; i < e; ++i) 3295 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3296 return false; 3297 return true; 3298} 3299 3300/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3301/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3302unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3303 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3304 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3305 3306 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3307 unsigned Mask = 0; 3308 for (int i = 0; i < NumOperands; ++i) { 3309 int Val = SVOp->getMaskElt(NumOperands-i-1); 3310 if (Val < 0) Val = 0; 3311 if (Val >= NumOperands) Val -= NumOperands; 3312 Mask |= Val; 3313 if (i != NumOperands - 1) 3314 Mask <<= Shift; 3315 } 3316 return Mask; 3317} 3318 3319/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3320/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3321unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3323 unsigned Mask = 0; 3324 // 8 nodes, but we only care about the last 4. 3325 for (unsigned i = 7; i >= 4; --i) { 3326 int Val = SVOp->getMaskElt(i); 3327 if (Val >= 0) 3328 Mask |= (Val - 4); 3329 if (i != 4) 3330 Mask <<= 2; 3331 } 3332 return Mask; 3333} 3334 3335/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3336/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3337unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3338 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3339 unsigned Mask = 0; 3340 // 8 nodes, but we only care about the first 4. 3341 for (int i = 3; i >= 0; --i) { 3342 int Val = SVOp->getMaskElt(i); 3343 if (Val >= 0) 3344 Mask |= Val; 3345 if (i != 0) 3346 Mask <<= 2; 3347 } 3348 return Mask; 3349} 3350 3351/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3352/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3353unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3355 EVT VVT = N->getValueType(0); 3356 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3357 int Val = 0; 3358 3359 unsigned i, e; 3360 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3361 Val = SVOp->getMaskElt(i); 3362 if (Val >= 0) 3363 break; 3364 } 3365 return (Val - i) * EltSize; 3366} 3367 3368/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3369/// constant +0.0. 3370bool X86::isZeroNode(SDValue Elt) { 3371 return ((isa<ConstantSDNode>(Elt) && 3372 cast<ConstantSDNode>(Elt)->isNullValue()) || 3373 (isa<ConstantFPSDNode>(Elt) && 3374 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3375} 3376 3377/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3378/// their permute mask. 3379static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3380 SelectionDAG &DAG) { 3381 EVT VT = SVOp->getValueType(0); 3382 unsigned NumElems = VT.getVectorNumElements(); 3383 SmallVector<int, 8> MaskVec; 3384 3385 for (unsigned i = 0; i != NumElems; ++i) { 3386 int idx = SVOp->getMaskElt(i); 3387 if (idx < 0) 3388 MaskVec.push_back(idx); 3389 else if (idx < (int)NumElems) 3390 MaskVec.push_back(idx + NumElems); 3391 else 3392 MaskVec.push_back(idx - NumElems); 3393 } 3394 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3395 SVOp->getOperand(0), &MaskVec[0]); 3396} 3397 3398/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3399/// the two vector operands have swapped position. 3400static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3401 unsigned NumElems = VT.getVectorNumElements(); 3402 for (unsigned i = 0; i != NumElems; ++i) { 3403 int idx = Mask[i]; 3404 if (idx < 0) 3405 continue; 3406 else if (idx < (int)NumElems) 3407 Mask[i] = idx + NumElems; 3408 else 3409 Mask[i] = idx - NumElems; 3410 } 3411} 3412 3413/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3414/// match movhlps. The lower half elements should come from upper half of 3415/// V1 (and in order), and the upper half elements should come from the upper 3416/// half of V2 (and in order). 3417static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3418 if (Op->getValueType(0).getVectorNumElements() != 4) 3419 return false; 3420 for (unsigned i = 0, e = 2; i != e; ++i) 3421 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3422 return false; 3423 for (unsigned i = 2; i != 4; ++i) 3424 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3425 return false; 3426 return true; 3427} 3428 3429/// isScalarLoadToVector - Returns true if the node is a scalar load that 3430/// is promoted to a vector. It also returns the LoadSDNode by reference if 3431/// required. 3432static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3433 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3434 return false; 3435 N = N->getOperand(0).getNode(); 3436 if (!ISD::isNON_EXTLoad(N)) 3437 return false; 3438 if (LD) 3439 *LD = cast<LoadSDNode>(N); 3440 return true; 3441} 3442 3443/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3444/// match movlp{s|d}. The lower half elements should come from lower half of 3445/// V1 (and in order), and the upper half elements should come from the upper 3446/// half of V2 (and in order). And since V1 will become the source of the 3447/// MOVLP, it must be either a vector load or a scalar load to vector. 3448static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3449 ShuffleVectorSDNode *Op) { 3450 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3451 return false; 3452 // Is V2 is a vector load, don't do this transformation. We will try to use 3453 // load folding shufps op. 3454 if (ISD::isNON_EXTLoad(V2)) 3455 return false; 3456 3457 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3458 3459 if (NumElems != 2 && NumElems != 4) 3460 return false; 3461 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3462 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3463 return false; 3464 for (unsigned i = NumElems/2; i != NumElems; ++i) 3465 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3466 return false; 3467 return true; 3468} 3469 3470/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3471/// all the same. 3472static bool isSplatVector(SDNode *N) { 3473 if (N->getOpcode() != ISD::BUILD_VECTOR) 3474 return false; 3475 3476 SDValue SplatValue = N->getOperand(0); 3477 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3478 if (N->getOperand(i) != SplatValue) 3479 return false; 3480 return true; 3481} 3482 3483/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3484/// to an zero vector. 3485/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3486static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3487 SDValue V1 = N->getOperand(0); 3488 SDValue V2 = N->getOperand(1); 3489 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3490 for (unsigned i = 0; i != NumElems; ++i) { 3491 int Idx = N->getMaskElt(i); 3492 if (Idx >= (int)NumElems) { 3493 unsigned Opc = V2.getOpcode(); 3494 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3495 continue; 3496 if (Opc != ISD::BUILD_VECTOR || 3497 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3498 return false; 3499 } else if (Idx >= 0) { 3500 unsigned Opc = V1.getOpcode(); 3501 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3502 continue; 3503 if (Opc != ISD::BUILD_VECTOR || 3504 !X86::isZeroNode(V1.getOperand(Idx))) 3505 return false; 3506 } 3507 } 3508 return true; 3509} 3510 3511/// getZeroVector - Returns a vector of specified type with all zero elements. 3512/// 3513static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3514 DebugLoc dl) { 3515 assert(VT.isVector() && "Expected a vector type"); 3516 3517 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted 3518 // to their dest type. This ensures they get CSE'd. 3519 SDValue Vec; 3520 if (VT.getSizeInBits() == 64) { // MMX 3521 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3522 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3523 } else if (VT.getSizeInBits() == 128) { 3524 if (HasSSE2) { // SSE2 3525 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3526 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3527 } else { // SSE1 3528 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3529 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3530 } 3531 } else if (VT.getSizeInBits() == 256) { // AVX 3532 // 256-bit logic and arithmetic instructions in AVX are 3533 // all floating-point, no support for integer ops. Default 3534 // to emitting fp zeroed vectors then. 3535 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3536 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3537 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3538 } 3539 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3540} 3541 3542/// getOnesVector - Returns a vector of specified type with all bits set. 3543/// 3544static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3545 assert(VT.isVector() && "Expected a vector type"); 3546 3547 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3548 // type. This ensures they get CSE'd. 3549 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3550 SDValue Vec; 3551 if (VT.getSizeInBits() == 64) // MMX 3552 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3553 else // SSE 3554 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3555 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3556} 3557 3558 3559/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3560/// that point to V2 points to its first element. 3561static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3562 EVT VT = SVOp->getValueType(0); 3563 unsigned NumElems = VT.getVectorNumElements(); 3564 3565 bool Changed = false; 3566 SmallVector<int, 8> MaskVec; 3567 SVOp->getMask(MaskVec); 3568 3569 for (unsigned i = 0; i != NumElems; ++i) { 3570 if (MaskVec[i] > (int)NumElems) { 3571 MaskVec[i] = NumElems; 3572 Changed = true; 3573 } 3574 } 3575 if (Changed) 3576 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3577 SVOp->getOperand(1), &MaskVec[0]); 3578 return SDValue(SVOp, 0); 3579} 3580 3581/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3582/// operation of specified width. 3583static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3584 SDValue V2) { 3585 unsigned NumElems = VT.getVectorNumElements(); 3586 SmallVector<int, 8> Mask; 3587 Mask.push_back(NumElems); 3588 for (unsigned i = 1; i != NumElems; ++i) 3589 Mask.push_back(i); 3590 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3591} 3592 3593/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3594static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3595 SDValue V2) { 3596 unsigned NumElems = VT.getVectorNumElements(); 3597 SmallVector<int, 8> Mask; 3598 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3599 Mask.push_back(i); 3600 Mask.push_back(i + NumElems); 3601 } 3602 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3603} 3604 3605/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3606static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3607 SDValue V2) { 3608 unsigned NumElems = VT.getVectorNumElements(); 3609 unsigned Half = NumElems/2; 3610 SmallVector<int, 8> Mask; 3611 for (unsigned i = 0; i != Half; ++i) { 3612 Mask.push_back(i + Half); 3613 Mask.push_back(i + NumElems + Half); 3614 } 3615 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3616} 3617 3618/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32. 3619static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 3620 if (SV->getValueType(0).getVectorNumElements() <= 4) 3621 return SDValue(SV, 0); 3622 3623 EVT PVT = MVT::v4f32; 3624 EVT VT = SV->getValueType(0); 3625 DebugLoc dl = SV->getDebugLoc(); 3626 SDValue V1 = SV->getOperand(0); 3627 int NumElems = VT.getVectorNumElements(); 3628 int EltNo = SV->getSplatIndex(); 3629 3630 // unpack elements to the correct location 3631 while (NumElems > 4) { 3632 if (EltNo < NumElems/2) { 3633 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3634 } else { 3635 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3636 EltNo -= NumElems/2; 3637 } 3638 NumElems >>= 1; 3639 } 3640 3641 // Perform the splat. 3642 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3643 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3644 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3645 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3646} 3647 3648/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3649/// vector of zero or undef vector. This produces a shuffle where the low 3650/// element of V2 is swizzled into the zero/undef vector, landing at element 3651/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3652static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3653 bool isZero, bool HasSSE2, 3654 SelectionDAG &DAG) { 3655 EVT VT = V2.getValueType(); 3656 SDValue V1 = isZero 3657 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3658 unsigned NumElems = VT.getVectorNumElements(); 3659 SmallVector<int, 16> MaskVec; 3660 for (unsigned i = 0; i != NumElems; ++i) 3661 // If this is the insertion idx, put the low elt of V2 here. 3662 MaskVec.push_back(i == Idx ? NumElems : i); 3663 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3664} 3665 3666/// getShuffleScalarElt - Returns the scalar element that will make up the ith 3667/// element of the result of the vector shuffle. 3668SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) { 3669 SDValue V = SDValue(N, 0); 3670 EVT VT = V.getValueType(); 3671 unsigned Opcode = V.getOpcode(); 3672 3673 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 3674 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 3675 Index = SV->getMaskElt(Index); 3676 3677 if (Index < 0) 3678 return DAG.getUNDEF(VT.getVectorElementType()); 3679 3680 int NumElems = VT.getVectorNumElements(); 3681 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 3682 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); 3683 } 3684 3685 // Recurse into target specific vector shuffles to find scalars. 3686 if (isTargetShuffle(Opcode)) { 3687 switch(Opcode) { 3688 case X86ISD::MOVSS: 3689 case X86ISD::MOVSD: { 3690 // The index 0 always comes from the first element of the second source, 3691 // this is why MOVSS and MOVSD are used in the first place. The other 3692 // elements come from the other positions of the first source vector. 3693 unsigned OpNum = (Index == 0) ? 1 : 0; 3694 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG); 3695 } 3696 default: 3697 assert("not implemented for target shuffle node"); 3698 return SDValue(); 3699 } 3700 } 3701 3702 // Actual nodes that may contain scalar elements 3703 if (Opcode == ISD::BIT_CONVERT) { 3704 V = V.getOperand(0); 3705 EVT SrcVT = V.getValueType(); 3706 unsigned NumElems = VT.getVectorNumElements(); 3707 3708 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 3709 return SDValue(); 3710 } 3711 3712 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 3713 return (Index == 0) ? V.getOperand(0) 3714 : DAG.getUNDEF(VT.getVectorElementType()); 3715 3716 if (V.getOpcode() == ISD::BUILD_VECTOR) 3717 return V.getOperand(Index); 3718 3719 return SDValue(); 3720} 3721 3722/// getNumOfConsecutiveZeros - Return the number of elements of a vector 3723/// shuffle operation which come from a consecutively from a zero. The 3724/// search can start in two diferent directions, from left or right. 3725static 3726unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 3727 bool ZerosFromLeft, SelectionDAG &DAG) { 3728 int i = 0; 3729 3730 while (i < NumElems) { 3731 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 3732 SDValue Elt = getShuffleScalarElt(N, Index, DAG); 3733 if (!(Elt.getNode() && 3734 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 3735 break; 3736 ++i; 3737 } 3738 3739 return i; 3740} 3741 3742/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 3743/// MaskE correspond consecutively to elements from one of the vector operands, 3744/// starting from its index OpIdx. Also tell OpNum which source vector operand. 3745static 3746bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 3747 int OpIdx, int NumElems, unsigned &OpNum) { 3748 bool SeenV1 = false; 3749 bool SeenV2 = false; 3750 3751 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 3752 int Idx = SVOp->getMaskElt(i); 3753 // Ignore undef indicies 3754 if (Idx < 0) 3755 continue; 3756 3757 if (Idx < NumElems) 3758 SeenV1 = true; 3759 else 3760 SeenV2 = true; 3761 3762 // Only accept consecutive elements from the same vector 3763 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 3764 return false; 3765 } 3766 3767 OpNum = SeenV1 ? 0 : 1; 3768 return true; 3769} 3770 3771/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 3772/// logical left shift of a vector. 3773static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3774 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3775 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3776 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3777 false /* check zeros from right */, DAG); 3778 unsigned OpSrc; 3779 3780 if (!NumZeros) 3781 return false; 3782 3783 // Considering the elements in the mask that are not consecutive zeros, 3784 // check if they consecutively come from only one of the source vectors. 3785 // 3786 // V1 = {X, A, B, C} 0 3787 // \ \ \ / 3788 // vector_shuffle V1, V2 <1, 2, 3, X> 3789 // 3790 if (!isShuffleMaskConsecutive(SVOp, 3791 0, // Mask Start Index 3792 NumElems-NumZeros-1, // Mask End Index 3793 NumZeros, // Where to start looking in the src vector 3794 NumElems, // Number of elements in vector 3795 OpSrc)) // Which source operand ? 3796 return false; 3797 3798 isLeft = false; 3799 ShAmt = NumZeros; 3800 ShVal = SVOp->getOperand(OpSrc); 3801 return true; 3802} 3803 3804/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 3805/// logical left shift of a vector. 3806static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3807 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3808 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3809 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3810 true /* check zeros from left */, DAG); 3811 unsigned OpSrc; 3812 3813 if (!NumZeros) 3814 return false; 3815 3816 // Considering the elements in the mask that are not consecutive zeros, 3817 // check if they consecutively come from only one of the source vectors. 3818 // 3819 // 0 { A, B, X, X } = V2 3820 // / \ / / 3821 // vector_shuffle V1, V2 <X, X, 4, 5> 3822 // 3823 if (!isShuffleMaskConsecutive(SVOp, 3824 NumZeros, // Mask Start Index 3825 NumElems-1, // Mask End Index 3826 0, // Where to start looking in the src vector 3827 NumElems, // Number of elements in vector 3828 OpSrc)) // Which source operand ? 3829 return false; 3830 3831 isLeft = true; 3832 ShAmt = NumZeros; 3833 ShVal = SVOp->getOperand(OpSrc); 3834 return true; 3835} 3836 3837/// isVectorShift - Returns true if the shuffle can be implemented as a 3838/// logical left or right shift of a vector. 3839static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3840 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3841 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 3842 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 3843 return true; 3844 3845 return false; 3846} 3847 3848/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3849/// 3850static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3851 unsigned NumNonZero, unsigned NumZero, 3852 SelectionDAG &DAG, 3853 const TargetLowering &TLI) { 3854 if (NumNonZero > 8) 3855 return SDValue(); 3856 3857 DebugLoc dl = Op.getDebugLoc(); 3858 SDValue V(0, 0); 3859 bool First = true; 3860 for (unsigned i = 0; i < 16; ++i) { 3861 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3862 if (ThisIsNonZero && First) { 3863 if (NumZero) 3864 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3865 else 3866 V = DAG.getUNDEF(MVT::v8i16); 3867 First = false; 3868 } 3869 3870 if ((i & 1) != 0) { 3871 SDValue ThisElt(0, 0), LastElt(0, 0); 3872 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3873 if (LastIsNonZero) { 3874 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3875 MVT::i16, Op.getOperand(i-1)); 3876 } 3877 if (ThisIsNonZero) { 3878 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3879 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3880 ThisElt, DAG.getConstant(8, MVT::i8)); 3881 if (LastIsNonZero) 3882 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3883 } else 3884 ThisElt = LastElt; 3885 3886 if (ThisElt.getNode()) 3887 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3888 DAG.getIntPtrConstant(i/2)); 3889 } 3890 } 3891 3892 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3893} 3894 3895/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3896/// 3897static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3898 unsigned NumNonZero, unsigned NumZero, 3899 SelectionDAG &DAG, 3900 const TargetLowering &TLI) { 3901 if (NumNonZero > 4) 3902 return SDValue(); 3903 3904 DebugLoc dl = Op.getDebugLoc(); 3905 SDValue V(0, 0); 3906 bool First = true; 3907 for (unsigned i = 0; i < 8; ++i) { 3908 bool isNonZero = (NonZeros & (1 << i)) != 0; 3909 if (isNonZero) { 3910 if (First) { 3911 if (NumZero) 3912 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3913 else 3914 V = DAG.getUNDEF(MVT::v8i16); 3915 First = false; 3916 } 3917 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3918 MVT::v8i16, V, Op.getOperand(i), 3919 DAG.getIntPtrConstant(i)); 3920 } 3921 } 3922 3923 return V; 3924} 3925 3926/// getVShift - Return a vector logical shift node. 3927/// 3928static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3929 unsigned NumBits, SelectionDAG &DAG, 3930 const TargetLowering &TLI, DebugLoc dl) { 3931 bool isMMX = VT.getSizeInBits() == 64; 3932 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3933 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3934 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3935 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3936 DAG.getNode(Opc, dl, ShVT, SrcOp, 3937 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3938} 3939 3940SDValue 3941X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3942 SelectionDAG &DAG) const { 3943 3944 // Check if the scalar load can be widened into a vector load. And if 3945 // the address is "base + cst" see if the cst can be "absorbed" into 3946 // the shuffle mask. 3947 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3948 SDValue Ptr = LD->getBasePtr(); 3949 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3950 return SDValue(); 3951 EVT PVT = LD->getValueType(0); 3952 if (PVT != MVT::i32 && PVT != MVT::f32) 3953 return SDValue(); 3954 3955 int FI = -1; 3956 int64_t Offset = 0; 3957 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3958 FI = FINode->getIndex(); 3959 Offset = 0; 3960 } else if (Ptr.getOpcode() == ISD::ADD && 3961 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3962 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3963 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3964 Offset = Ptr.getConstantOperandVal(1); 3965 Ptr = Ptr.getOperand(0); 3966 } else { 3967 return SDValue(); 3968 } 3969 3970 SDValue Chain = LD->getChain(); 3971 // Make sure the stack object alignment is at least 16. 3972 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3973 if (DAG.InferPtrAlignment(Ptr) < 16) { 3974 if (MFI->isFixedObjectIndex(FI)) { 3975 // Can't change the alignment. FIXME: It's possible to compute 3976 // the exact stack offset and reference FI + adjust offset instead. 3977 // If someone *really* cares about this. That's the way to implement it. 3978 return SDValue(); 3979 } else { 3980 MFI->setObjectAlignment(FI, 16); 3981 } 3982 } 3983 3984 // (Offset % 16) must be multiple of 4. Then address is then 3985 // Ptr + (Offset & ~15). 3986 if (Offset < 0) 3987 return SDValue(); 3988 if ((Offset % 16) & 3) 3989 return SDValue(); 3990 int64_t StartOffset = Offset & ~15; 3991 if (StartOffset) 3992 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3993 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3994 3995 int EltNo = (Offset - StartOffset) >> 2; 3996 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3997 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3998 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3999 false, false, 0); 4000 // Canonicalize it to a v4i32 shuffle. 4001 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 4002 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4003 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 4004 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 4005 } 4006 4007 return SDValue(); 4008} 4009 4010/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4011/// vector of type 'VT', see if the elements can be replaced by a single large 4012/// load which has the same value as a build_vector whose operands are 'elts'. 4013/// 4014/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4015/// 4016/// FIXME: we'd also like to handle the case where the last elements are zero 4017/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4018/// There's even a handy isZeroNode for that purpose. 4019static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4020 DebugLoc &dl, SelectionDAG &DAG) { 4021 EVT EltVT = VT.getVectorElementType(); 4022 unsigned NumElems = Elts.size(); 4023 4024 LoadSDNode *LDBase = NULL; 4025 unsigned LastLoadedElt = -1U; 4026 4027 // For each element in the initializer, see if we've found a load or an undef. 4028 // If we don't find an initial load element, or later load elements are 4029 // non-consecutive, bail out. 4030 for (unsigned i = 0; i < NumElems; ++i) { 4031 SDValue Elt = Elts[i]; 4032 4033 if (!Elt.getNode() || 4034 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4035 return SDValue(); 4036 if (!LDBase) { 4037 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4038 return SDValue(); 4039 LDBase = cast<LoadSDNode>(Elt.getNode()); 4040 LastLoadedElt = i; 4041 continue; 4042 } 4043 if (Elt.getOpcode() == ISD::UNDEF) 4044 continue; 4045 4046 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4047 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4048 return SDValue(); 4049 LastLoadedElt = i; 4050 } 4051 4052 // If we have found an entire vector of loads and undefs, then return a large 4053 // load of the entire vector width starting at the base pointer. If we found 4054 // consecutive loads for the low half, generate a vzext_load node. 4055 if (LastLoadedElt == NumElems - 1) { 4056 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4057 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 4058 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 4059 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4060 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 4061 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 4062 LDBase->isVolatile(), LDBase->isNonTemporal(), 4063 LDBase->getAlignment()); 4064 } else if (NumElems == 4 && LastLoadedElt == 1) { 4065 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4066 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4067 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 4068 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 4069 } 4070 return SDValue(); 4071} 4072 4073SDValue 4074X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4075 DebugLoc dl = Op.getDebugLoc(); 4076 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1. 4077 // All one's are handled with pcmpeqd. In AVX, zero's are handled with 4078 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd 4079 // is present, so AllOnes is ignored. 4080 if (ISD::isBuildVectorAllZeros(Op.getNode()) || 4081 (Op.getValueType().getSizeInBits() != 256 && 4082 ISD::isBuildVectorAllOnes(Op.getNode()))) { 4083 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 4084 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 4085 // eliminated on x86-32 hosts. 4086 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 4087 return Op; 4088 4089 if (ISD::isBuildVectorAllOnes(Op.getNode())) 4090 return getOnesVector(Op.getValueType(), DAG, dl); 4091 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4092 } 4093 4094 EVT VT = Op.getValueType(); 4095 EVT ExtVT = VT.getVectorElementType(); 4096 unsigned EVTBits = ExtVT.getSizeInBits(); 4097 4098 unsigned NumElems = Op.getNumOperands(); 4099 unsigned NumZero = 0; 4100 unsigned NumNonZero = 0; 4101 unsigned NonZeros = 0; 4102 bool IsAllConstants = true; 4103 SmallSet<SDValue, 8> Values; 4104 for (unsigned i = 0; i < NumElems; ++i) { 4105 SDValue Elt = Op.getOperand(i); 4106 if (Elt.getOpcode() == ISD::UNDEF) 4107 continue; 4108 Values.insert(Elt); 4109 if (Elt.getOpcode() != ISD::Constant && 4110 Elt.getOpcode() != ISD::ConstantFP) 4111 IsAllConstants = false; 4112 if (X86::isZeroNode(Elt)) 4113 NumZero++; 4114 else { 4115 NonZeros |= (1 << i); 4116 NumNonZero++; 4117 } 4118 } 4119 4120 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4121 if (NumNonZero == 0) 4122 return DAG.getUNDEF(VT); 4123 4124 // Special case for single non-zero, non-undef, element. 4125 if (NumNonZero == 1) { 4126 unsigned Idx = CountTrailingZeros_32(NonZeros); 4127 SDValue Item = Op.getOperand(Idx); 4128 4129 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4130 // the value are obviously zero, truncate the value to i32 and do the 4131 // insertion that way. Only do this if the value is non-constant or if the 4132 // value is a constant being inserted into element 0. It is cheaper to do 4133 // a constant pool load than it is to do a movd + shuffle. 4134 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4135 (!IsAllConstants || Idx == 0)) { 4136 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4137 // Handle MMX and SSE both. 4138 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 4139 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 4140 4141 // Truncate the value (which may itself be a constant) to i32, and 4142 // convert it to a vector with movd (S2V+shuffle to zero extend). 4143 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4144 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4145 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4146 Subtarget->hasSSE2(), DAG); 4147 4148 // Now we have our 32-bit value zero extended in the low element of 4149 // a vector. If Idx != 0, swizzle it into place. 4150 if (Idx != 0) { 4151 SmallVector<int, 4> Mask; 4152 Mask.push_back(Idx); 4153 for (unsigned i = 1; i != VecElts; ++i) 4154 Mask.push_back(i); 4155 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4156 DAG.getUNDEF(Item.getValueType()), 4157 &Mask[0]); 4158 } 4159 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 4160 } 4161 } 4162 4163 // If we have a constant or non-constant insertion into the low element of 4164 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4165 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4166 // depending on what the source datatype is. 4167 if (Idx == 0) { 4168 if (NumZero == 0) { 4169 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4170 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4171 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4172 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4173 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4174 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4175 DAG); 4176 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4177 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4178 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 4179 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4180 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4181 Subtarget->hasSSE2(), DAG); 4182 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 4183 } 4184 } 4185 4186 // Is it a vector logical left shift? 4187 if (NumElems == 2 && Idx == 1 && 4188 X86::isZeroNode(Op.getOperand(0)) && 4189 !X86::isZeroNode(Op.getOperand(1))) { 4190 unsigned NumBits = VT.getSizeInBits(); 4191 return getVShift(true, VT, 4192 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4193 VT, Op.getOperand(1)), 4194 NumBits/2, DAG, *this, dl); 4195 } 4196 4197 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4198 return SDValue(); 4199 4200 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4201 // is a non-constant being inserted into an element other than the low one, 4202 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4203 // movd/movss) to move this into the low element, then shuffle it into 4204 // place. 4205 if (EVTBits == 32) { 4206 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4207 4208 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4209 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4210 Subtarget->hasSSE2(), DAG); 4211 SmallVector<int, 8> MaskVec; 4212 for (unsigned i = 0; i < NumElems; i++) 4213 MaskVec.push_back(i == Idx ? 0 : 1); 4214 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4215 } 4216 } 4217 4218 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4219 if (Values.size() == 1) { 4220 if (EVTBits == 32) { 4221 // Instead of a shuffle like this: 4222 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4223 // Check if it's possible to issue this instead. 4224 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4225 unsigned Idx = CountTrailingZeros_32(NonZeros); 4226 SDValue Item = Op.getOperand(Idx); 4227 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4228 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4229 } 4230 return SDValue(); 4231 } 4232 4233 // A vector full of immediates; various special cases are already 4234 // handled, so this is best done with a single constant-pool load. 4235 if (IsAllConstants) 4236 return SDValue(); 4237 4238 // Let legalizer expand 2-wide build_vectors. 4239 if (EVTBits == 64) { 4240 if (NumNonZero == 1) { 4241 // One half is zero or undef. 4242 unsigned Idx = CountTrailingZeros_32(NonZeros); 4243 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4244 Op.getOperand(Idx)); 4245 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4246 Subtarget->hasSSE2(), DAG); 4247 } 4248 return SDValue(); 4249 } 4250 4251 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4252 if (EVTBits == 8 && NumElems == 16) { 4253 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4254 *this); 4255 if (V.getNode()) return V; 4256 } 4257 4258 if (EVTBits == 16 && NumElems == 8) { 4259 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4260 *this); 4261 if (V.getNode()) return V; 4262 } 4263 4264 // If element VT is == 32 bits, turn it into a number of shuffles. 4265 SmallVector<SDValue, 8> V; 4266 V.resize(NumElems); 4267 if (NumElems == 4 && NumZero > 0) { 4268 for (unsigned i = 0; i < 4; ++i) { 4269 bool isZero = !(NonZeros & (1 << i)); 4270 if (isZero) 4271 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4272 else 4273 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4274 } 4275 4276 for (unsigned i = 0; i < 2; ++i) { 4277 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4278 default: break; 4279 case 0: 4280 V[i] = V[i*2]; // Must be a zero vector. 4281 break; 4282 case 1: 4283 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4284 break; 4285 case 2: 4286 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4287 break; 4288 case 3: 4289 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4290 break; 4291 } 4292 } 4293 4294 SmallVector<int, 8> MaskVec; 4295 bool Reverse = (NonZeros & 0x3) == 2; 4296 for (unsigned i = 0; i < 2; ++i) 4297 MaskVec.push_back(Reverse ? 1-i : i); 4298 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4299 for (unsigned i = 0; i < 2; ++i) 4300 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4301 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4302 } 4303 4304 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4305 // Check for a build vector of consecutive loads. 4306 for (unsigned i = 0; i < NumElems; ++i) 4307 V[i] = Op.getOperand(i); 4308 4309 // Check for elements which are consecutive loads. 4310 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4311 if (LD.getNode()) 4312 return LD; 4313 4314 // For SSE 4.1, use insertps to put the high elements into the low element. 4315 if (getSubtarget()->hasSSE41()) { 4316 SDValue Result; 4317 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4318 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4319 else 4320 Result = DAG.getUNDEF(VT); 4321 4322 for (unsigned i = 1; i < NumElems; ++i) { 4323 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4324 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4325 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4326 } 4327 return Result; 4328 } 4329 4330 // Otherwise, expand into a number of unpckl*, start by extending each of 4331 // our (non-undef) elements to the full vector width with the element in the 4332 // bottom slot of the vector (which generates no code for SSE). 4333 for (unsigned i = 0; i < NumElems; ++i) { 4334 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4335 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4336 else 4337 V[i] = DAG.getUNDEF(VT); 4338 } 4339 4340 // Next, we iteratively mix elements, e.g. for v4f32: 4341 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 4342 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 4343 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 4344 unsigned EltStride = NumElems >> 1; 4345 while (EltStride != 0) { 4346 for (unsigned i = 0; i < EltStride; ++i) { 4347 // If V[i+EltStride] is undef and this is the first round of mixing, 4348 // then it is safe to just drop this shuffle: V[i] is already in the 4349 // right place, the one element (since it's the first round) being 4350 // inserted as undef can be dropped. This isn't safe for successive 4351 // rounds because they will permute elements within both vectors. 4352 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 4353 EltStride == NumElems/2) 4354 continue; 4355 4356 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 4357 } 4358 EltStride >>= 1; 4359 } 4360 return V[0]; 4361 } 4362 return SDValue(); 4363} 4364 4365SDValue 4366X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 4367 // We support concatenate two MMX registers and place them in a MMX 4368 // register. This is better than doing a stack convert. 4369 DebugLoc dl = Op.getDebugLoc(); 4370 EVT ResVT = Op.getValueType(); 4371 assert(Op.getNumOperands() == 2); 4372 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 4373 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 4374 int Mask[2]; 4375 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 4376 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4377 InVec = Op.getOperand(1); 4378 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4379 unsigned NumElts = ResVT.getVectorNumElements(); 4380 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4381 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 4382 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 4383 } else { 4384 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 4385 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4386 Mask[0] = 0; Mask[1] = 2; 4387 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 4388 } 4389 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4390} 4391 4392// v8i16 shuffles - Prefer shuffles in the following order: 4393// 1. [all] pshuflw, pshufhw, optional move 4394// 2. [ssse3] 1 x pshufb 4395// 3. [ssse3] 2 x pshufb + 1 x por 4396// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4397SDValue 4398X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 4399 SelectionDAG &DAG) const { 4400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4401 SDValue V1 = SVOp->getOperand(0); 4402 SDValue V2 = SVOp->getOperand(1); 4403 DebugLoc dl = SVOp->getDebugLoc(); 4404 SmallVector<int, 8> MaskVals; 4405 4406 // Determine if more than 1 of the words in each of the low and high quadwords 4407 // of the result come from the same quadword of one of the two inputs. Undef 4408 // mask values count as coming from any quadword, for better codegen. 4409 SmallVector<unsigned, 4> LoQuad(4); 4410 SmallVector<unsigned, 4> HiQuad(4); 4411 BitVector InputQuads(4); 4412 for (unsigned i = 0; i < 8; ++i) { 4413 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4414 int EltIdx = SVOp->getMaskElt(i); 4415 MaskVals.push_back(EltIdx); 4416 if (EltIdx < 0) { 4417 ++Quad[0]; 4418 ++Quad[1]; 4419 ++Quad[2]; 4420 ++Quad[3]; 4421 continue; 4422 } 4423 ++Quad[EltIdx / 4]; 4424 InputQuads.set(EltIdx / 4); 4425 } 4426 4427 int BestLoQuad = -1; 4428 unsigned MaxQuad = 1; 4429 for (unsigned i = 0; i < 4; ++i) { 4430 if (LoQuad[i] > MaxQuad) { 4431 BestLoQuad = i; 4432 MaxQuad = LoQuad[i]; 4433 } 4434 } 4435 4436 int BestHiQuad = -1; 4437 MaxQuad = 1; 4438 for (unsigned i = 0; i < 4; ++i) { 4439 if (HiQuad[i] > MaxQuad) { 4440 BestHiQuad = i; 4441 MaxQuad = HiQuad[i]; 4442 } 4443 } 4444 4445 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4446 // of the two input vectors, shuffle them into one input vector so only a 4447 // single pshufb instruction is necessary. If There are more than 2 input 4448 // quads, disable the next transformation since it does not help SSSE3. 4449 bool V1Used = InputQuads[0] || InputQuads[1]; 4450 bool V2Used = InputQuads[2] || InputQuads[3]; 4451 if (Subtarget->hasSSSE3()) { 4452 if (InputQuads.count() == 2 && V1Used && V2Used) { 4453 BestLoQuad = InputQuads.find_first(); 4454 BestHiQuad = InputQuads.find_next(BestLoQuad); 4455 } 4456 if (InputQuads.count() > 2) { 4457 BestLoQuad = -1; 4458 BestHiQuad = -1; 4459 } 4460 } 4461 4462 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4463 // the shuffle mask. If a quad is scored as -1, that means that it contains 4464 // words from all 4 input quadwords. 4465 SDValue NewV; 4466 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4467 SmallVector<int, 8> MaskV; 4468 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4469 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4470 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4471 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 4472 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 4473 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 4474 4475 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4476 // source words for the shuffle, to aid later transformations. 4477 bool AllWordsInNewV = true; 4478 bool InOrder[2] = { true, true }; 4479 for (unsigned i = 0; i != 8; ++i) { 4480 int idx = MaskVals[i]; 4481 if (idx != (int)i) 4482 InOrder[i/4] = false; 4483 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4484 continue; 4485 AllWordsInNewV = false; 4486 break; 4487 } 4488 4489 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4490 if (AllWordsInNewV) { 4491 for (int i = 0; i != 8; ++i) { 4492 int idx = MaskVals[i]; 4493 if (idx < 0) 4494 continue; 4495 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4496 if ((idx != i) && idx < 4) 4497 pshufhw = false; 4498 if ((idx != i) && idx > 3) 4499 pshuflw = false; 4500 } 4501 V1 = NewV; 4502 V2Used = false; 4503 BestLoQuad = 0; 4504 BestHiQuad = 1; 4505 } 4506 4507 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4508 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4509 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4510 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 4511 unsigned TargetMask = 0; 4512 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4513 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4514 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 4515 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 4516 V1 = NewV.getOperand(0); 4517 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 4518 } 4519 } 4520 4521 // If we have SSSE3, and all words of the result are from 1 input vector, 4522 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4523 // is present, fall back to case 4. 4524 if (Subtarget->hasSSSE3()) { 4525 SmallVector<SDValue,16> pshufbMask; 4526 4527 // If we have elements from both input vectors, set the high bit of the 4528 // shuffle mask element to zero out elements that come from V2 in the V1 4529 // mask, and elements that come from V1 in the V2 mask, so that the two 4530 // results can be OR'd together. 4531 bool TwoInputs = V1Used && V2Used; 4532 for (unsigned i = 0; i != 8; ++i) { 4533 int EltIdx = MaskVals[i] * 2; 4534 if (TwoInputs && (EltIdx >= 16)) { 4535 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4536 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4537 continue; 4538 } 4539 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4540 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4541 } 4542 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4543 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4544 DAG.getNode(ISD::BUILD_VECTOR, dl, 4545 MVT::v16i8, &pshufbMask[0], 16)); 4546 if (!TwoInputs) 4547 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4548 4549 // Calculate the shuffle mask for the second input, shuffle it, and 4550 // OR it with the first shuffled input. 4551 pshufbMask.clear(); 4552 for (unsigned i = 0; i != 8; ++i) { 4553 int EltIdx = MaskVals[i] * 2; 4554 if (EltIdx < 16) { 4555 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4556 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4557 continue; 4558 } 4559 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4560 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4561 } 4562 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4563 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4564 DAG.getNode(ISD::BUILD_VECTOR, dl, 4565 MVT::v16i8, &pshufbMask[0], 16)); 4566 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4567 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4568 } 4569 4570 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4571 // and update MaskVals with new element order. 4572 BitVector InOrder(8); 4573 if (BestLoQuad >= 0) { 4574 SmallVector<int, 8> MaskV; 4575 for (int i = 0; i != 4; ++i) { 4576 int idx = MaskVals[i]; 4577 if (idx < 0) { 4578 MaskV.push_back(-1); 4579 InOrder.set(i); 4580 } else if ((idx / 4) == BestLoQuad) { 4581 MaskV.push_back(idx & 3); 4582 InOrder.set(i); 4583 } else { 4584 MaskV.push_back(-1); 4585 } 4586 } 4587 for (unsigned i = 4; i != 8; ++i) 4588 MaskV.push_back(i); 4589 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4590 &MaskV[0]); 4591 4592 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4593 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 4594 NewV.getOperand(0), 4595 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 4596 DAG); 4597 } 4598 4599 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4600 // and update MaskVals with the new element order. 4601 if (BestHiQuad >= 0) { 4602 SmallVector<int, 8> MaskV; 4603 for (unsigned i = 0; i != 4; ++i) 4604 MaskV.push_back(i); 4605 for (unsigned i = 4; i != 8; ++i) { 4606 int idx = MaskVals[i]; 4607 if (idx < 0) { 4608 MaskV.push_back(-1); 4609 InOrder.set(i); 4610 } else if ((idx / 4) == BestHiQuad) { 4611 MaskV.push_back((idx & 3) + 4); 4612 InOrder.set(i); 4613 } else { 4614 MaskV.push_back(-1); 4615 } 4616 } 4617 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4618 &MaskV[0]); 4619 4620 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4621 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 4622 NewV.getOperand(0), 4623 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 4624 DAG); 4625 } 4626 4627 // In case BestHi & BestLo were both -1, which means each quadword has a word 4628 // from each of the four input quadwords, calculate the InOrder bitvector now 4629 // before falling through to the insert/extract cleanup. 4630 if (BestLoQuad == -1 && BestHiQuad == -1) { 4631 NewV = V1; 4632 for (int i = 0; i != 8; ++i) 4633 if (MaskVals[i] < 0 || MaskVals[i] == i) 4634 InOrder.set(i); 4635 } 4636 4637 // The other elements are put in the right place using pextrw and pinsrw. 4638 for (unsigned i = 0; i != 8; ++i) { 4639 if (InOrder[i]) 4640 continue; 4641 int EltIdx = MaskVals[i]; 4642 if (EltIdx < 0) 4643 continue; 4644 SDValue ExtOp = (EltIdx < 8) 4645 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4646 DAG.getIntPtrConstant(EltIdx)) 4647 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4648 DAG.getIntPtrConstant(EltIdx - 8)); 4649 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4650 DAG.getIntPtrConstant(i)); 4651 } 4652 return NewV; 4653} 4654 4655// v16i8 shuffles - Prefer shuffles in the following order: 4656// 1. [ssse3] 1 x pshufb 4657// 2. [ssse3] 2 x pshufb + 1 x por 4658// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4659static 4660SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4661 SelectionDAG &DAG, 4662 const X86TargetLowering &TLI) { 4663 SDValue V1 = SVOp->getOperand(0); 4664 SDValue V2 = SVOp->getOperand(1); 4665 DebugLoc dl = SVOp->getDebugLoc(); 4666 SmallVector<int, 16> MaskVals; 4667 SVOp->getMask(MaskVals); 4668 4669 // If we have SSSE3, case 1 is generated when all result bytes come from 4670 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4671 // present, fall back to case 3. 4672 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4673 bool V1Only = true; 4674 bool V2Only = true; 4675 for (unsigned i = 0; i < 16; ++i) { 4676 int EltIdx = MaskVals[i]; 4677 if (EltIdx < 0) 4678 continue; 4679 if (EltIdx < 16) 4680 V2Only = false; 4681 else 4682 V1Only = false; 4683 } 4684 4685 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4686 if (TLI.getSubtarget()->hasSSSE3()) { 4687 SmallVector<SDValue,16> pshufbMask; 4688 4689 // If all result elements are from one input vector, then only translate 4690 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4691 // 4692 // Otherwise, we have elements from both input vectors, and must zero out 4693 // elements that come from V2 in the first mask, and V1 in the second mask 4694 // so that we can OR them together. 4695 bool TwoInputs = !(V1Only || V2Only); 4696 for (unsigned i = 0; i != 16; ++i) { 4697 int EltIdx = MaskVals[i]; 4698 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4699 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4700 continue; 4701 } 4702 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4703 } 4704 // If all the elements are from V2, assign it to V1 and return after 4705 // building the first pshufb. 4706 if (V2Only) 4707 V1 = V2; 4708 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4709 DAG.getNode(ISD::BUILD_VECTOR, dl, 4710 MVT::v16i8, &pshufbMask[0], 16)); 4711 if (!TwoInputs) 4712 return V1; 4713 4714 // Calculate the shuffle mask for the second input, shuffle it, and 4715 // OR it with the first shuffled input. 4716 pshufbMask.clear(); 4717 for (unsigned i = 0; i != 16; ++i) { 4718 int EltIdx = MaskVals[i]; 4719 if (EltIdx < 16) { 4720 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4721 continue; 4722 } 4723 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4724 } 4725 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4726 DAG.getNode(ISD::BUILD_VECTOR, dl, 4727 MVT::v16i8, &pshufbMask[0], 16)); 4728 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4729 } 4730 4731 // No SSSE3 - Calculate in place words and then fix all out of place words 4732 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4733 // the 16 different words that comprise the two doublequadword input vectors. 4734 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4735 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4736 SDValue NewV = V2Only ? V2 : V1; 4737 for (int i = 0; i != 8; ++i) { 4738 int Elt0 = MaskVals[i*2]; 4739 int Elt1 = MaskVals[i*2+1]; 4740 4741 // This word of the result is all undef, skip it. 4742 if (Elt0 < 0 && Elt1 < 0) 4743 continue; 4744 4745 // This word of the result is already in the correct place, skip it. 4746 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4747 continue; 4748 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4749 continue; 4750 4751 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4752 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4753 SDValue InsElt; 4754 4755 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4756 // using a single extract together, load it and store it. 4757 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4758 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4759 DAG.getIntPtrConstant(Elt1 / 2)); 4760 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4761 DAG.getIntPtrConstant(i)); 4762 continue; 4763 } 4764 4765 // If Elt1 is defined, extract it from the appropriate source. If the 4766 // source byte is not also odd, shift the extracted word left 8 bits 4767 // otherwise clear the bottom 8 bits if we need to do an or. 4768 if (Elt1 >= 0) { 4769 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4770 DAG.getIntPtrConstant(Elt1 / 2)); 4771 if ((Elt1 & 1) == 0) 4772 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4773 DAG.getConstant(8, TLI.getShiftAmountTy())); 4774 else if (Elt0 >= 0) 4775 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4776 DAG.getConstant(0xFF00, MVT::i16)); 4777 } 4778 // If Elt0 is defined, extract it from the appropriate source. If the 4779 // source byte is not also even, shift the extracted word right 8 bits. If 4780 // Elt1 was also defined, OR the extracted values together before 4781 // inserting them in the result. 4782 if (Elt0 >= 0) { 4783 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4784 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4785 if ((Elt0 & 1) != 0) 4786 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4787 DAG.getConstant(8, TLI.getShiftAmountTy())); 4788 else if (Elt1 >= 0) 4789 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4790 DAG.getConstant(0x00FF, MVT::i16)); 4791 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4792 : InsElt0; 4793 } 4794 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4795 DAG.getIntPtrConstant(i)); 4796 } 4797 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4798} 4799 4800/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4801/// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be 4802/// done when every pair / quad of shuffle mask elements point to elements in 4803/// the right sequence. e.g. 4804/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4805static 4806SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4807 SelectionDAG &DAG, 4808 const TargetLowering &TLI, DebugLoc dl) { 4809 EVT VT = SVOp->getValueType(0); 4810 SDValue V1 = SVOp->getOperand(0); 4811 SDValue V2 = SVOp->getOperand(1); 4812 unsigned NumElems = VT.getVectorNumElements(); 4813 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4814 EVT MaskVT = (NewWidth == 4) ? MVT::v4i16 : MVT::v2i32; 4815 EVT NewVT = MaskVT; 4816 switch (VT.getSimpleVT().SimpleTy) { 4817 default: assert(false && "Unexpected!"); 4818 case MVT::v4f32: NewVT = MVT::v2f64; break; 4819 case MVT::v4i32: NewVT = MVT::v2i64; break; 4820 case MVT::v8i16: NewVT = MVT::v4i32; break; 4821 case MVT::v16i8: NewVT = MVT::v4i32; break; 4822 } 4823 4824 if (NewWidth == 2) { 4825 if (VT.isInteger()) 4826 NewVT = MVT::v2i64; 4827 else 4828 NewVT = MVT::v2f64; 4829 } 4830 int Scale = NumElems / NewWidth; 4831 SmallVector<int, 8> MaskVec; 4832 for (unsigned i = 0; i < NumElems; i += Scale) { 4833 int StartIdx = -1; 4834 for (int j = 0; j < Scale; ++j) { 4835 int EltIdx = SVOp->getMaskElt(i+j); 4836 if (EltIdx < 0) 4837 continue; 4838 if (StartIdx == -1) 4839 StartIdx = EltIdx - (EltIdx % Scale); 4840 if (EltIdx != StartIdx + j) 4841 return SDValue(); 4842 } 4843 if (StartIdx == -1) 4844 MaskVec.push_back(-1); 4845 else 4846 MaskVec.push_back(StartIdx / Scale); 4847 } 4848 4849 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4850 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4851 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4852} 4853 4854/// getVZextMovL - Return a zero-extending vector move low node. 4855/// 4856static SDValue getVZextMovL(EVT VT, EVT OpVT, 4857 SDValue SrcOp, SelectionDAG &DAG, 4858 const X86Subtarget *Subtarget, DebugLoc dl) { 4859 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4860 LoadSDNode *LD = NULL; 4861 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4862 LD = dyn_cast<LoadSDNode>(SrcOp); 4863 if (!LD) { 4864 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4865 // instead. 4866 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4867 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4868 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4869 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4870 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4871 // PR2108 4872 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4873 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4874 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4875 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4876 OpVT, 4877 SrcOp.getOperand(0) 4878 .getOperand(0)))); 4879 } 4880 } 4881 } 4882 4883 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4884 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4885 DAG.getNode(ISD::BIT_CONVERT, dl, 4886 OpVT, SrcOp))); 4887} 4888 4889/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4890/// shuffles. 4891static SDValue 4892LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4893 SDValue V1 = SVOp->getOperand(0); 4894 SDValue V2 = SVOp->getOperand(1); 4895 DebugLoc dl = SVOp->getDebugLoc(); 4896 EVT VT = SVOp->getValueType(0); 4897 4898 SmallVector<std::pair<int, int>, 8> Locs; 4899 Locs.resize(4); 4900 SmallVector<int, 8> Mask1(4U, -1); 4901 SmallVector<int, 8> PermMask; 4902 SVOp->getMask(PermMask); 4903 4904 unsigned NumHi = 0; 4905 unsigned NumLo = 0; 4906 for (unsigned i = 0; i != 4; ++i) { 4907 int Idx = PermMask[i]; 4908 if (Idx < 0) { 4909 Locs[i] = std::make_pair(-1, -1); 4910 } else { 4911 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4912 if (Idx < 4) { 4913 Locs[i] = std::make_pair(0, NumLo); 4914 Mask1[NumLo] = Idx; 4915 NumLo++; 4916 } else { 4917 Locs[i] = std::make_pair(1, NumHi); 4918 if (2+NumHi < 4) 4919 Mask1[2+NumHi] = Idx; 4920 NumHi++; 4921 } 4922 } 4923 } 4924 4925 if (NumLo <= 2 && NumHi <= 2) { 4926 // If no more than two elements come from either vector. This can be 4927 // implemented with two shuffles. First shuffle gather the elements. 4928 // The second shuffle, which takes the first shuffle as both of its 4929 // vector operands, put the elements into the right order. 4930 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4931 4932 SmallVector<int, 8> Mask2(4U, -1); 4933 4934 for (unsigned i = 0; i != 4; ++i) { 4935 if (Locs[i].first == -1) 4936 continue; 4937 else { 4938 unsigned Idx = (i < 2) ? 0 : 4; 4939 Idx += Locs[i].first * 2 + Locs[i].second; 4940 Mask2[i] = Idx; 4941 } 4942 } 4943 4944 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4945 } else if (NumLo == 3 || NumHi == 3) { 4946 // Otherwise, we must have three elements from one vector, call it X, and 4947 // one element from the other, call it Y. First, use a shufps to build an 4948 // intermediate vector with the one element from Y and the element from X 4949 // that will be in the same half in the final destination (the indexes don't 4950 // matter). Then, use a shufps to build the final vector, taking the half 4951 // containing the element from Y from the intermediate, and the other half 4952 // from X. 4953 if (NumHi == 3) { 4954 // Normalize it so the 3 elements come from V1. 4955 CommuteVectorShuffleMask(PermMask, VT); 4956 std::swap(V1, V2); 4957 } 4958 4959 // Find the element from V2. 4960 unsigned HiIndex; 4961 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4962 int Val = PermMask[HiIndex]; 4963 if (Val < 0) 4964 continue; 4965 if (Val >= 4) 4966 break; 4967 } 4968 4969 Mask1[0] = PermMask[HiIndex]; 4970 Mask1[1] = -1; 4971 Mask1[2] = PermMask[HiIndex^1]; 4972 Mask1[3] = -1; 4973 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4974 4975 if (HiIndex >= 2) { 4976 Mask1[0] = PermMask[0]; 4977 Mask1[1] = PermMask[1]; 4978 Mask1[2] = HiIndex & 1 ? 6 : 4; 4979 Mask1[3] = HiIndex & 1 ? 4 : 6; 4980 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4981 } else { 4982 Mask1[0] = HiIndex & 1 ? 2 : 0; 4983 Mask1[1] = HiIndex & 1 ? 0 : 2; 4984 Mask1[2] = PermMask[2]; 4985 Mask1[3] = PermMask[3]; 4986 if (Mask1[2] >= 0) 4987 Mask1[2] += 4; 4988 if (Mask1[3] >= 0) 4989 Mask1[3] += 4; 4990 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4991 } 4992 } 4993 4994 // Break it into (shuffle shuffle_hi, shuffle_lo). 4995 Locs.clear(); 4996 SmallVector<int,8> LoMask(4U, -1); 4997 SmallVector<int,8> HiMask(4U, -1); 4998 4999 SmallVector<int,8> *MaskPtr = &LoMask; 5000 unsigned MaskIdx = 0; 5001 unsigned LoIdx = 0; 5002 unsigned HiIdx = 2; 5003 for (unsigned i = 0; i != 4; ++i) { 5004 if (i == 2) { 5005 MaskPtr = &HiMask; 5006 MaskIdx = 1; 5007 LoIdx = 0; 5008 HiIdx = 2; 5009 } 5010 int Idx = PermMask[i]; 5011 if (Idx < 0) { 5012 Locs[i] = std::make_pair(-1, -1); 5013 } else if (Idx < 4) { 5014 Locs[i] = std::make_pair(MaskIdx, LoIdx); 5015 (*MaskPtr)[LoIdx] = Idx; 5016 LoIdx++; 5017 } else { 5018 Locs[i] = std::make_pair(MaskIdx, HiIdx); 5019 (*MaskPtr)[HiIdx] = Idx; 5020 HiIdx++; 5021 } 5022 } 5023 5024 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 5025 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 5026 SmallVector<int, 8> MaskOps; 5027 for (unsigned i = 0; i != 4; ++i) { 5028 if (Locs[i].first == -1) { 5029 MaskOps.push_back(-1); 5030 } else { 5031 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5032 MaskOps.push_back(Idx); 5033 } 5034 } 5035 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5036} 5037 5038static 5039SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5040 bool HasSSE2) { 5041 SDValue V1 = Op.getOperand(0); 5042 SDValue V2 = Op.getOperand(1); 5043 EVT VT = Op.getValueType(); 5044 5045 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5046 5047 if (HasSSE2 && VT == MVT::v2f64) 5048 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5049 5050 // v4f32 or v4i32 5051 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5052} 5053 5054static 5055SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 5056 SDValue V1 = Op.getOperand(0); 5057 SDValue V2 = Op.getOperand(1); 5058 EVT VT = Op.getValueType(); 5059 5060 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 5061 "unsupported shuffle type"); 5062 5063 if (V2.getOpcode() == ISD::UNDEF) 5064 V2 = V1; 5065 5066 // v4i32 or v4f32 5067 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 5068} 5069 5070static 5071SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 5072 SDValue V1 = Op.getOperand(0); 5073 SDValue V2 = Op.getOperand(1); 5074 EVT VT = Op.getValueType(); 5075 unsigned NumElems = VT.getVectorNumElements(); 5076 5077 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 5078 // operand of these instructions is only memory, so check if there's a 5079 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 5080 // same masks. 5081 bool CanFoldLoad = false; 5082 SDValue TmpV1 = V1; 5083 SDValue TmpV2 = V2; 5084 5085 // Trivial case, when V2 comes from a load. 5086 if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT) 5087 TmpV2 = TmpV2.getOperand(0); 5088 if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) 5089 TmpV2 = TmpV2.getOperand(0); 5090 if (MayFoldLoad(TmpV2)) 5091 CanFoldLoad = true; 5092 5093 // When V1 is a load, it can be folded later into a store in isel, example: 5094 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 5095 // turns into: 5096 // (MOVLPSmr addr:$src1, VR128:$src2) 5097 // So, recognize this potential and also use MOVLPS or MOVLPD 5098 if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT) 5099 TmpV1 = TmpV1.getOperand(0); 5100 if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op)) 5101 CanFoldLoad = true; 5102 5103 if (CanFoldLoad) { 5104 if (HasSSE2 && NumElems == 2) 5105 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 5106 5107 if (NumElems == 4) 5108 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 5109 } 5110 5111 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5112 // movl and movlp will both match v2i64, but v2i64 is never matched by 5113 // movl earlier because we make it strict to avoid messing with the movlp load 5114 // folding logic (see the code above getMOVLP call). Match it here then, 5115 // this is horrible, but will stay like this until we move all shuffle 5116 // matching to x86 specific nodes. Note that for the 1st condition all 5117 // types are matched with movsd. 5118 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) 5119 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5120 else if (HasSSE2) 5121 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5122 5123 5124 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 5125 5126 // Invert the operand order and use SHUFPS to match it. 5127 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, 5128 X86::getShuffleSHUFImmediate(SVOp), DAG); 5129} 5130 5131SDValue 5132X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 5133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5134 SDValue V1 = Op.getOperand(0); 5135 SDValue V2 = Op.getOperand(1); 5136 EVT VT = Op.getValueType(); 5137 DebugLoc dl = Op.getDebugLoc(); 5138 unsigned NumElems = VT.getVectorNumElements(); 5139 bool isMMX = VT.getSizeInBits() == 64; 5140 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 5141 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 5142 bool V1IsSplat = false; 5143 bool V2IsSplat = false; 5144 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 5145 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 5146 MachineFunction &MF = DAG.getMachineFunction(); 5147 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 5148 5149 if (isZeroShuffle(SVOp)) 5150 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5151 5152 // Promote splats to v4f32. 5153 if (SVOp->isSplat()) { 5154 if (isMMX || NumElems < 4) 5155 return Op; 5156 return PromoteSplat(SVOp, DAG); 5157 } 5158 5159 // If the shuffle can be profitably rewritten as a narrower shuffle, then 5160 // do it! 5161 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 5162 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5163 if (NewOp.getNode()) 5164 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5165 LowerVECTOR_SHUFFLE(NewOp, DAG)); 5166 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 5167 // FIXME: Figure out a cleaner way to do this. 5168 // Try to make use of movq to zero out the top part. 5169 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 5170 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5171 if (NewOp.getNode()) { 5172 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 5173 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 5174 DAG, Subtarget, dl); 5175 } 5176 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 5177 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5178 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 5179 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 5180 DAG, Subtarget, dl); 5181 } 5182 } 5183 5184 if (X86::isPSHUFDMask(SVOp)) { 5185 // The actual implementation will match the mask in the if above and then 5186 // during isel it can match several different instructions, not only pshufd 5187 // as its name says, sad but true, emulate the behavior for now... 5188 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 5189 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 5190 5191 if (OptForSize && HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && 5192 VT == MVT::v4i32) 5193 return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); 5194 5195 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5196 5197 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 5198 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 5199 5200 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5201 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 5202 TargetMask, DAG); 5203 5204 if (VT == MVT::v4f32) 5205 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 5206 TargetMask, DAG); 5207 } 5208 5209 // Check if this can be converted into a logical shift. 5210 bool isLeft = false; 5211 unsigned ShAmt = 0; 5212 SDValue ShVal; 5213 bool isShift = getSubtarget()->hasSSE2() && 5214 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 5215 if (isShift && ShVal.hasOneUse()) { 5216 // If the shifted value has multiple uses, it may be cheaper to use 5217 // v_set0 + movlhps or movhlps, etc. 5218 EVT EltVT = VT.getVectorElementType(); 5219 ShAmt *= EltVT.getSizeInBits(); 5220 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5221 } 5222 5223 if (X86::isMOVLMask(SVOp)) { 5224 if (V1IsUndef) 5225 return V2; 5226 if (ISD::isBuildVectorAllZeros(V1.getNode())) 5227 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 5228 if (!isMMX && !X86::isMOVLPMask(SVOp)) { 5229 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5230 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5231 5232 if (VT == MVT::v4i32 || VT == MVT::v4f32) 5233 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5234 } 5235 } 5236 5237 // FIXME: fold these into legal mask. 5238 if (!isMMX) { 5239 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 5240 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 5241 5242 if (X86::isMOVHLPSMask(SVOp)) 5243 return getMOVHighToLow(Op, dl, DAG); 5244 5245 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5246 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 5247 5248 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) 5249 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 5250 5251 if (X86::isMOVLPMask(SVOp)) 5252 return getMOVLP(Op, dl, DAG, HasSSE2); 5253 } 5254 5255 if (ShouldXformToMOVHLPS(SVOp) || 5256 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 5257 return CommuteVectorShuffle(SVOp, DAG); 5258 5259 if (isShift) { 5260 // No better options. Use a vshl / vsrl. 5261 EVT EltVT = VT.getVectorElementType(); 5262 ShAmt *= EltVT.getSizeInBits(); 5263 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5264 } 5265 5266 bool Commuted = false; 5267 // FIXME: This should also accept a bitcast of a splat? Be careful, not 5268 // 1,1,1,1 -> v8i16 though. 5269 V1IsSplat = isSplatVector(V1.getNode()); 5270 V2IsSplat = isSplatVector(V2.getNode()); 5271 5272 // Canonicalize the splat or undef, if present, to be on the RHS. 5273 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 5274 Op = CommuteVectorShuffle(SVOp, DAG); 5275 SVOp = cast<ShuffleVectorSDNode>(Op); 5276 V1 = SVOp->getOperand(0); 5277 V2 = SVOp->getOperand(1); 5278 std::swap(V1IsSplat, V2IsSplat); 5279 std::swap(V1IsUndef, V2IsUndef); 5280 Commuted = true; 5281 } 5282 5283 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 5284 // Shuffling low element of v1 into undef, just return v1. 5285 if (V2IsUndef) 5286 return V1; 5287 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 5288 // the instruction selector will not match, so get a canonical MOVL with 5289 // swapped operands to undo the commute. 5290 return getMOVL(DAG, dl, VT, V2, V1); 5291 } 5292 5293 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 5294 X86::isUNPCKH_v_undef_Mask(SVOp) || 5295 X86::isUNPCKLMask(SVOp) || 5296 X86::isUNPCKHMask(SVOp)) 5297 return Op; 5298 5299 if (V2IsSplat) { 5300 // Normalize mask so all entries that point to V2 points to its first 5301 // element then try to match unpck{h|l} again. If match, return a 5302 // new vector_shuffle with the corrected mask. 5303 SDValue NewMask = NormalizeMask(SVOp, DAG); 5304 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 5305 if (NSVOp != SVOp) { 5306 if (X86::isUNPCKLMask(NSVOp, true)) { 5307 return NewMask; 5308 } else if (X86::isUNPCKHMask(NSVOp, true)) { 5309 return NewMask; 5310 } 5311 } 5312 } 5313 5314 if (Commuted) { 5315 // Commute is back and try unpck* again. 5316 // FIXME: this seems wrong. 5317 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 5318 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 5319 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 5320 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 5321 X86::isUNPCKLMask(NewSVOp) || 5322 X86::isUNPCKHMask(NewSVOp)) 5323 return NewOp; 5324 } 5325 5326 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 5327 5328 // Normalize the node to match x86 shuffle ops if needed 5329 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 5330 return CommuteVectorShuffle(SVOp, DAG); 5331 5332 // Check for legal shuffle and return? 5333 SmallVector<int, 16> PermMask; 5334 SVOp->getMask(PermMask); 5335 if (isShuffleMaskLegal(PermMask, VT)) 5336 return Op; 5337 5338 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 5339 if (VT == MVT::v8i16) { 5340 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 5341 if (NewOp.getNode()) 5342 return NewOp; 5343 } 5344 5345 if (VT == MVT::v16i8) { 5346 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 5347 if (NewOp.getNode()) 5348 return NewOp; 5349 } 5350 5351 // Handle all 4 wide cases with a number of shuffles except for MMX. 5352 if (NumElems == 4 && !isMMX) 5353 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 5354 5355 return SDValue(); 5356} 5357 5358SDValue 5359X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 5360 SelectionDAG &DAG) const { 5361 EVT VT = Op.getValueType(); 5362 DebugLoc dl = Op.getDebugLoc(); 5363 if (VT.getSizeInBits() == 8) { 5364 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 5365 Op.getOperand(0), Op.getOperand(1)); 5366 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5367 DAG.getValueType(VT)); 5368 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5369 } else if (VT.getSizeInBits() == 16) { 5370 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5371 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 5372 if (Idx == 0) 5373 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5374 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5375 DAG.getNode(ISD::BIT_CONVERT, dl, 5376 MVT::v4i32, 5377 Op.getOperand(0)), 5378 Op.getOperand(1))); 5379 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 5380 Op.getOperand(0), Op.getOperand(1)); 5381 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5382 DAG.getValueType(VT)); 5383 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5384 } else if (VT == MVT::f32) { 5385 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 5386 // the result back to FR32 register. It's only worth matching if the 5387 // result has a single use which is a store or a bitcast to i32. And in 5388 // the case of a store, it's not worth it if the index is a constant 0, 5389 // because a MOVSSmr can be used instead, which is smaller and faster. 5390 if (!Op.hasOneUse()) 5391 return SDValue(); 5392 SDNode *User = *Op.getNode()->use_begin(); 5393 if ((User->getOpcode() != ISD::STORE || 5394 (isa<ConstantSDNode>(Op.getOperand(1)) && 5395 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 5396 (User->getOpcode() != ISD::BIT_CONVERT || 5397 User->getValueType(0) != MVT::i32)) 5398 return SDValue(); 5399 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5400 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 5401 Op.getOperand(0)), 5402 Op.getOperand(1)); 5403 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 5404 } else if (VT == MVT::i32) { 5405 // ExtractPS works with constant index. 5406 if (isa<ConstantSDNode>(Op.getOperand(1))) 5407 return Op; 5408 } 5409 return SDValue(); 5410} 5411 5412 5413SDValue 5414X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5415 SelectionDAG &DAG) const { 5416 if (!isa<ConstantSDNode>(Op.getOperand(1))) 5417 return SDValue(); 5418 5419 if (Subtarget->hasSSE41()) { 5420 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 5421 if (Res.getNode()) 5422 return Res; 5423 } 5424 5425 EVT VT = Op.getValueType(); 5426 DebugLoc dl = Op.getDebugLoc(); 5427 // TODO: handle v16i8. 5428 if (VT.getSizeInBits() == 16) { 5429 SDValue Vec = Op.getOperand(0); 5430 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5431 if (Idx == 0) 5432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5434 DAG.getNode(ISD::BIT_CONVERT, dl, 5435 MVT::v4i32, Vec), 5436 Op.getOperand(1))); 5437 // Transform it so it match pextrw which produces a 32-bit result. 5438 EVT EltVT = MVT::i32; 5439 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 5440 Op.getOperand(0), Op.getOperand(1)); 5441 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 5442 DAG.getValueType(VT)); 5443 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5444 } else if (VT.getSizeInBits() == 32) { 5445 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5446 if (Idx == 0) 5447 return Op; 5448 5449 // SHUFPS the element to the lowest double word, then movss. 5450 int Mask[4] = { Idx, -1, -1, -1 }; 5451 EVT VVT = Op.getOperand(0).getValueType(); 5452 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5453 DAG.getUNDEF(VVT), Mask); 5454 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5455 DAG.getIntPtrConstant(0)); 5456 } else if (VT.getSizeInBits() == 64) { 5457 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 5458 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 5459 // to match extract_elt for f64. 5460 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5461 if (Idx == 0) 5462 return Op; 5463 5464 // UNPCKHPD the element to the lowest double word, then movsd. 5465 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 5466 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 5467 int Mask[2] = { 1, -1 }; 5468 EVT VVT = Op.getOperand(0).getValueType(); 5469 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5470 DAG.getUNDEF(VVT), Mask); 5471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5472 DAG.getIntPtrConstant(0)); 5473 } 5474 5475 return SDValue(); 5476} 5477 5478SDValue 5479X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 5480 SelectionDAG &DAG) const { 5481 EVT VT = Op.getValueType(); 5482 EVT EltVT = VT.getVectorElementType(); 5483 DebugLoc dl = Op.getDebugLoc(); 5484 5485 SDValue N0 = Op.getOperand(0); 5486 SDValue N1 = Op.getOperand(1); 5487 SDValue N2 = Op.getOperand(2); 5488 5489 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 5490 isa<ConstantSDNode>(N2)) { 5491 unsigned Opc; 5492 if (VT == MVT::v8i16) 5493 Opc = X86ISD::PINSRW; 5494 else if (VT == MVT::v4i16) 5495 Opc = X86ISD::MMX_PINSRW; 5496 else if (VT == MVT::v16i8) 5497 Opc = X86ISD::PINSRB; 5498 else 5499 Opc = X86ISD::PINSRB; 5500 5501 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 5502 // argument. 5503 if (N1.getValueType() != MVT::i32) 5504 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5505 if (N2.getValueType() != MVT::i32) 5506 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5507 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 5508 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 5509 // Bits [7:6] of the constant are the source select. This will always be 5510 // zero here. The DAG Combiner may combine an extract_elt index into these 5511 // bits. For example (insert (extract, 3), 2) could be matched by putting 5512 // the '3' into bits [7:6] of X86ISD::INSERTPS. 5513 // Bits [5:4] of the constant are the destination select. This is the 5514 // value of the incoming immediate. 5515 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 5516 // combine either bitwise AND or insert of float 0.0 to set these bits. 5517 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 5518 // Create this as a scalar to vector.. 5519 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 5520 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 5521 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 5522 // PINSR* works with constant index. 5523 return Op; 5524 } 5525 return SDValue(); 5526} 5527 5528SDValue 5529X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 5530 EVT VT = Op.getValueType(); 5531 EVT EltVT = VT.getVectorElementType(); 5532 5533 if (Subtarget->hasSSE41()) 5534 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 5535 5536 if (EltVT == MVT::i8) 5537 return SDValue(); 5538 5539 DebugLoc dl = Op.getDebugLoc(); 5540 SDValue N0 = Op.getOperand(0); 5541 SDValue N1 = Op.getOperand(1); 5542 SDValue N2 = Op.getOperand(2); 5543 5544 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 5545 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 5546 // as its second argument. 5547 if (N1.getValueType() != MVT::i32) 5548 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5549 if (N2.getValueType() != MVT::i32) 5550 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5551 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 5552 dl, VT, N0, N1, N2); 5553 } 5554 return SDValue(); 5555} 5556 5557SDValue 5558X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5559 DebugLoc dl = Op.getDebugLoc(); 5560 5561 if (Op.getValueType() == MVT::v1i64 && 5562 Op.getOperand(0).getValueType() == MVT::i64) 5563 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 5564 5565 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 5566 EVT VT = MVT::v2i32; 5567 switch (Op.getValueType().getSimpleVT().SimpleTy) { 5568 default: break; 5569 case MVT::v16i8: 5570 case MVT::v8i16: 5571 VT = MVT::v4i32; 5572 break; 5573 } 5574 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 5575 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 5576} 5577 5578// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5579// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5580// one of the above mentioned nodes. It has to be wrapped because otherwise 5581// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5582// be used to form addressing mode. These wrapped nodes will be selected 5583// into MOV32ri. 5584SDValue 5585X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 5586 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5587 5588 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5589 // global base reg. 5590 unsigned char OpFlag = 0; 5591 unsigned WrapperKind = X86ISD::Wrapper; 5592 CodeModel::Model M = getTargetMachine().getCodeModel(); 5593 5594 if (Subtarget->isPICStyleRIPRel() && 5595 (M == CodeModel::Small || M == CodeModel::Kernel)) 5596 WrapperKind = X86ISD::WrapperRIP; 5597 else if (Subtarget->isPICStyleGOT()) 5598 OpFlag = X86II::MO_GOTOFF; 5599 else if (Subtarget->isPICStyleStubPIC()) 5600 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5601 5602 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5603 CP->getAlignment(), 5604 CP->getOffset(), OpFlag); 5605 DebugLoc DL = CP->getDebugLoc(); 5606 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5607 // With PIC, the address is actually $g + Offset. 5608 if (OpFlag) { 5609 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5610 DAG.getNode(X86ISD::GlobalBaseReg, 5611 DebugLoc(), getPointerTy()), 5612 Result); 5613 } 5614 5615 return Result; 5616} 5617 5618SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 5619 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5620 5621 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5622 // global base reg. 5623 unsigned char OpFlag = 0; 5624 unsigned WrapperKind = X86ISD::Wrapper; 5625 CodeModel::Model M = getTargetMachine().getCodeModel(); 5626 5627 if (Subtarget->isPICStyleRIPRel() && 5628 (M == CodeModel::Small || M == CodeModel::Kernel)) 5629 WrapperKind = X86ISD::WrapperRIP; 5630 else if (Subtarget->isPICStyleGOT()) 5631 OpFlag = X86II::MO_GOTOFF; 5632 else if (Subtarget->isPICStyleStubPIC()) 5633 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5634 5635 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5636 OpFlag); 5637 DebugLoc DL = JT->getDebugLoc(); 5638 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5639 5640 // With PIC, the address is actually $g + Offset. 5641 if (OpFlag) { 5642 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5643 DAG.getNode(X86ISD::GlobalBaseReg, 5644 DebugLoc(), getPointerTy()), 5645 Result); 5646 } 5647 5648 return Result; 5649} 5650 5651SDValue 5652X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 5653 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5654 5655 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5656 // global base reg. 5657 unsigned char OpFlag = 0; 5658 unsigned WrapperKind = X86ISD::Wrapper; 5659 CodeModel::Model M = getTargetMachine().getCodeModel(); 5660 5661 if (Subtarget->isPICStyleRIPRel() && 5662 (M == CodeModel::Small || M == CodeModel::Kernel)) 5663 WrapperKind = X86ISD::WrapperRIP; 5664 else if (Subtarget->isPICStyleGOT()) 5665 OpFlag = X86II::MO_GOTOFF; 5666 else if (Subtarget->isPICStyleStubPIC()) 5667 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5668 5669 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5670 5671 DebugLoc DL = Op.getDebugLoc(); 5672 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5673 5674 5675 // With PIC, the address is actually $g + Offset. 5676 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5677 !Subtarget->is64Bit()) { 5678 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5679 DAG.getNode(X86ISD::GlobalBaseReg, 5680 DebugLoc(), getPointerTy()), 5681 Result); 5682 } 5683 5684 return Result; 5685} 5686 5687SDValue 5688X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 5689 // Create the TargetBlockAddressAddress node. 5690 unsigned char OpFlags = 5691 Subtarget->ClassifyBlockAddressReference(); 5692 CodeModel::Model M = getTargetMachine().getCodeModel(); 5693 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5694 DebugLoc dl = Op.getDebugLoc(); 5695 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5696 /*isTarget=*/true, OpFlags); 5697 5698 if (Subtarget->isPICStyleRIPRel() && 5699 (M == CodeModel::Small || M == CodeModel::Kernel)) 5700 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5701 else 5702 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5703 5704 // With PIC, the address is actually $g + Offset. 5705 if (isGlobalRelativeToPICBase(OpFlags)) { 5706 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5707 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5708 Result); 5709 } 5710 5711 return Result; 5712} 5713 5714SDValue 5715X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5716 int64_t Offset, 5717 SelectionDAG &DAG) const { 5718 // Create the TargetGlobalAddress node, folding in the constant 5719 // offset if it is legal. 5720 unsigned char OpFlags = 5721 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5722 CodeModel::Model M = getTargetMachine().getCodeModel(); 5723 SDValue Result; 5724 if (OpFlags == X86II::MO_NO_FLAG && 5725 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5726 // A direct static reference to a global. 5727 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 5728 Offset = 0; 5729 } else { 5730 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 5731 } 5732 5733 if (Subtarget->isPICStyleRIPRel() && 5734 (M == CodeModel::Small || M == CodeModel::Kernel)) 5735 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5736 else 5737 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5738 5739 // With PIC, the address is actually $g + Offset. 5740 if (isGlobalRelativeToPICBase(OpFlags)) { 5741 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5742 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5743 Result); 5744 } 5745 5746 // For globals that require a load from a stub to get the address, emit the 5747 // load. 5748 if (isGlobalStubReference(OpFlags)) 5749 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5750 PseudoSourceValue::getGOT(), 0, false, false, 0); 5751 5752 // If there was a non-zero offset that we didn't fold, create an explicit 5753 // addition for it. 5754 if (Offset != 0) 5755 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5756 DAG.getConstant(Offset, getPointerTy())); 5757 5758 return Result; 5759} 5760 5761SDValue 5762X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 5763 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5764 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5765 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5766} 5767 5768static SDValue 5769GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5770 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5771 unsigned char OperandFlags) { 5772 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5773 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5774 DebugLoc dl = GA->getDebugLoc(); 5775 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5776 GA->getValueType(0), 5777 GA->getOffset(), 5778 OperandFlags); 5779 if (InFlag) { 5780 SDValue Ops[] = { Chain, TGA, *InFlag }; 5781 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5782 } else { 5783 SDValue Ops[] = { Chain, TGA }; 5784 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5785 } 5786 5787 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5788 MFI->setAdjustsStack(true); 5789 5790 SDValue Flag = Chain.getValue(1); 5791 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5792} 5793 5794// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5795static SDValue 5796LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5797 const EVT PtrVT) { 5798 SDValue InFlag; 5799 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5800 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5801 DAG.getNode(X86ISD::GlobalBaseReg, 5802 DebugLoc(), PtrVT), InFlag); 5803 InFlag = Chain.getValue(1); 5804 5805 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5806} 5807 5808// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5809static SDValue 5810LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5811 const EVT PtrVT) { 5812 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5813 X86::RAX, X86II::MO_TLSGD); 5814} 5815 5816// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5817// "local exec" model. 5818static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5819 const EVT PtrVT, TLSModel::Model model, 5820 bool is64Bit) { 5821 DebugLoc dl = GA->getDebugLoc(); 5822 // Get the Thread Pointer 5823 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5824 DebugLoc(), PtrVT, 5825 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5826 MVT::i32)); 5827 5828 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5829 NULL, 0, false, false, 0); 5830 5831 unsigned char OperandFlags = 0; 5832 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5833 // initialexec. 5834 unsigned WrapperKind = X86ISD::Wrapper; 5835 if (model == TLSModel::LocalExec) { 5836 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5837 } else if (is64Bit) { 5838 assert(model == TLSModel::InitialExec); 5839 OperandFlags = X86II::MO_GOTTPOFF; 5840 WrapperKind = X86ISD::WrapperRIP; 5841 } else { 5842 assert(model == TLSModel::InitialExec); 5843 OperandFlags = X86II::MO_INDNTPOFF; 5844 } 5845 5846 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5847 // exec) 5848 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5849 GA->getValueType(0), 5850 GA->getOffset(), OperandFlags); 5851 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5852 5853 if (model == TLSModel::InitialExec) 5854 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5855 PseudoSourceValue::getGOT(), 0, false, false, 0); 5856 5857 // The address of the thread local variable is the add of the thread 5858 // pointer with the offset of the variable. 5859 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5860} 5861 5862SDValue 5863X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 5864 5865 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5866 const GlobalValue *GV = GA->getGlobal(); 5867 5868 if (Subtarget->isTargetELF()) { 5869 // TODO: implement the "local dynamic" model 5870 // TODO: implement the "initial exec"model for pic executables 5871 5872 // If GV is an alias then use the aliasee for determining 5873 // thread-localness. 5874 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5875 GV = GA->resolveAliasedGlobal(false); 5876 5877 TLSModel::Model model 5878 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 5879 5880 switch (model) { 5881 case TLSModel::GeneralDynamic: 5882 case TLSModel::LocalDynamic: // not implemented 5883 if (Subtarget->is64Bit()) 5884 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5885 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5886 5887 case TLSModel::InitialExec: 5888 case TLSModel::LocalExec: 5889 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5890 Subtarget->is64Bit()); 5891 } 5892 } else if (Subtarget->isTargetDarwin()) { 5893 // Darwin only has one model of TLS. Lower to that. 5894 unsigned char OpFlag = 0; 5895 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 5896 X86ISD::WrapperRIP : X86ISD::Wrapper; 5897 5898 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5899 // global base reg. 5900 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 5901 !Subtarget->is64Bit(); 5902 if (PIC32) 5903 OpFlag = X86II::MO_TLVP_PIC_BASE; 5904 else 5905 OpFlag = X86II::MO_TLVP; 5906 DebugLoc DL = Op.getDebugLoc(); 5907 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 5908 getPointerTy(), 5909 GA->getOffset(), OpFlag); 5910 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5911 5912 // With PIC32, the address is actually $g + Offset. 5913 if (PIC32) 5914 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5915 DAG.getNode(X86ISD::GlobalBaseReg, 5916 DebugLoc(), getPointerTy()), 5917 Offset); 5918 5919 // Lowering the machine isd will make sure everything is in the right 5920 // location. 5921 SDValue Args[] = { Offset }; 5922 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1); 5923 5924 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 5925 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5926 MFI->setAdjustsStack(true); 5927 5928 // And our return value (tls address) is in the standard call return value 5929 // location. 5930 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 5931 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 5932 } 5933 5934 assert(false && 5935 "TLS not implemented for this target."); 5936 5937 llvm_unreachable("Unreachable"); 5938 return SDValue(); 5939} 5940 5941 5942/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5943/// take a 2 x i32 value to shift plus a shift amount. 5944SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 5945 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5946 EVT VT = Op.getValueType(); 5947 unsigned VTBits = VT.getSizeInBits(); 5948 DebugLoc dl = Op.getDebugLoc(); 5949 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5950 SDValue ShOpLo = Op.getOperand(0); 5951 SDValue ShOpHi = Op.getOperand(1); 5952 SDValue ShAmt = Op.getOperand(2); 5953 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5954 DAG.getConstant(VTBits - 1, MVT::i8)) 5955 : DAG.getConstant(0, VT); 5956 5957 SDValue Tmp2, Tmp3; 5958 if (Op.getOpcode() == ISD::SHL_PARTS) { 5959 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5960 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5961 } else { 5962 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5963 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5964 } 5965 5966 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5967 DAG.getConstant(VTBits, MVT::i8)); 5968 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5969 AndNode, DAG.getConstant(0, MVT::i8)); 5970 5971 SDValue Hi, Lo; 5972 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5973 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5974 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5975 5976 if (Op.getOpcode() == ISD::SHL_PARTS) { 5977 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5978 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5979 } else { 5980 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5981 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5982 } 5983 5984 SDValue Ops[2] = { Lo, Hi }; 5985 return DAG.getMergeValues(Ops, 2, dl); 5986} 5987 5988SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 5989 SelectionDAG &DAG) const { 5990 EVT SrcVT = Op.getOperand(0).getValueType(); 5991 5992 if (SrcVT.isVector()) { 5993 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5994 return Op; 5995 } 5996 return SDValue(); 5997 } 5998 5999 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 6000 "Unknown SINT_TO_FP to lower!"); 6001 6002 // These are really Legal; return the operand so the caller accepts it as 6003 // Legal. 6004 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 6005 return Op; 6006 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 6007 Subtarget->is64Bit()) { 6008 return Op; 6009 } 6010 6011 DebugLoc dl = Op.getDebugLoc(); 6012 unsigned Size = SrcVT.getSizeInBits()/8; 6013 MachineFunction &MF = DAG.getMachineFunction(); 6014 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 6015 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6016 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6017 StackSlot, 6018 PseudoSourceValue::getFixedStack(SSFI), 0, 6019 false, false, 0); 6020 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 6021} 6022 6023SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 6024 SDValue StackSlot, 6025 SelectionDAG &DAG) const { 6026 // Build the FILD 6027 DebugLoc dl = Op.getDebugLoc(); 6028 SDVTList Tys; 6029 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 6030 if (useSSE) 6031 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 6032 else 6033 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 6034 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 6035 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 6036 Tys, Ops, array_lengthof(Ops)); 6037 6038 if (useSSE) { 6039 Chain = Result.getValue(1); 6040 SDValue InFlag = Result.getValue(2); 6041 6042 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 6043 // shouldn't be necessary except that RFP cannot be live across 6044 // multiple blocks. When stackifier is fixed, they can be uncoupled. 6045 MachineFunction &MF = DAG.getMachineFunction(); 6046 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 6047 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6048 Tys = DAG.getVTList(MVT::Other); 6049 SDValue Ops[] = { 6050 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 6051 }; 6052 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 6053 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 6054 PseudoSourceValue::getFixedStack(SSFI), 0, 6055 false, false, 0); 6056 } 6057 6058 return Result; 6059} 6060 6061// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 6062SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 6063 SelectionDAG &DAG) const { 6064 // This algorithm is not obvious. Here it is in C code, more or less: 6065 /* 6066 double uint64_to_double( uint32_t hi, uint32_t lo ) { 6067 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 6068 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 6069 6070 // Copy ints to xmm registers. 6071 __m128i xh = _mm_cvtsi32_si128( hi ); 6072 __m128i xl = _mm_cvtsi32_si128( lo ); 6073 6074 // Combine into low half of a single xmm register. 6075 __m128i x = _mm_unpacklo_epi32( xh, xl ); 6076 __m128d d; 6077 double sd; 6078 6079 // Merge in appropriate exponents to give the integer bits the right 6080 // magnitude. 6081 x = _mm_unpacklo_epi32( x, exp ); 6082 6083 // Subtract away the biases to deal with the IEEE-754 double precision 6084 // implicit 1. 6085 d = _mm_sub_pd( (__m128d) x, bias ); 6086 6087 // All conversions up to here are exact. The correctly rounded result is 6088 // calculated using the current rounding mode using the following 6089 // horizontal add. 6090 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 6091 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 6092 // store doesn't really need to be here (except 6093 // maybe to zero the other double) 6094 return sd; 6095 } 6096 */ 6097 6098 DebugLoc dl = Op.getDebugLoc(); 6099 LLVMContext *Context = DAG.getContext(); 6100 6101 // Build some magic constants. 6102 std::vector<Constant*> CV0; 6103 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 6104 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 6105 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6106 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 6107 Constant *C0 = ConstantVector::get(CV0); 6108 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 6109 6110 std::vector<Constant*> CV1; 6111 CV1.push_back( 6112 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 6113 CV1.push_back( 6114 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 6115 Constant *C1 = ConstantVector::get(CV1); 6116 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 6117 6118 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6119 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6120 Op.getOperand(0), 6121 DAG.getIntPtrConstant(1))); 6122 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6123 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6124 Op.getOperand(0), 6125 DAG.getIntPtrConstant(0))); 6126 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 6127 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 6128 PseudoSourceValue::getConstantPool(), 0, 6129 false, false, 16); 6130 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 6131 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 6132 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 6133 PseudoSourceValue::getConstantPool(), 0, 6134 false, false, 16); 6135 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 6136 6137 // Add the halves; easiest way is to swap them into another reg first. 6138 int ShufMask[2] = { 1, -1 }; 6139 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 6140 DAG.getUNDEF(MVT::v2f64), ShufMask); 6141 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 6142 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 6143 DAG.getIntPtrConstant(0)); 6144} 6145 6146// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 6147SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 6148 SelectionDAG &DAG) const { 6149 DebugLoc dl = Op.getDebugLoc(); 6150 // FP constant to bias correct the final result. 6151 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 6152 MVT::f64); 6153 6154 // Load the 32-bit value into an XMM register. 6155 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6156 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6157 Op.getOperand(0), 6158 DAG.getIntPtrConstant(0))); 6159 6160 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6161 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 6162 DAG.getIntPtrConstant(0)); 6163 6164 // Or the load with the bias. 6165 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 6166 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6167 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6168 MVT::v2f64, Load)), 6169 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6170 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6171 MVT::v2f64, Bias))); 6172 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6173 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 6174 DAG.getIntPtrConstant(0)); 6175 6176 // Subtract the bias. 6177 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 6178 6179 // Handle final rounding. 6180 EVT DestVT = Op.getValueType(); 6181 6182 if (DestVT.bitsLT(MVT::f64)) { 6183 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6184 DAG.getIntPtrConstant(0)); 6185 } else if (DestVT.bitsGT(MVT::f64)) { 6186 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6187 } 6188 6189 // Handle final rounding. 6190 return Sub; 6191} 6192 6193SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 6194 SelectionDAG &DAG) const { 6195 SDValue N0 = Op.getOperand(0); 6196 DebugLoc dl = Op.getDebugLoc(); 6197 6198 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 6199 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 6200 // the optimization here. 6201 if (DAG.SignBitIsZero(N0)) 6202 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 6203 6204 EVT SrcVT = N0.getValueType(); 6205 EVT DstVT = Op.getValueType(); 6206 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 6207 return LowerUINT_TO_FP_i64(Op, DAG); 6208 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 6209 return LowerUINT_TO_FP_i32(Op, DAG); 6210 6211 // Make a 64-bit buffer, and use it to build an FILD. 6212 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 6213 if (SrcVT == MVT::i32) { 6214 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 6215 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 6216 getPointerTy(), StackSlot, WordOff); 6217 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6218 StackSlot, NULL, 0, false, false, 0); 6219 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 6220 OffsetSlot, NULL, 0, false, false, 0); 6221 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 6222 return Fild; 6223 } 6224 6225 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 6226 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6227 StackSlot, NULL, 0, false, false, 0); 6228 // For i64 source, we need to add the appropriate power of 2 if the input 6229 // was negative. This is the same as the optimization in 6230 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 6231 // we must be careful to do the computation in x87 extended precision, not 6232 // in SSE. (The generic code can't know it's OK to do this, or how to.) 6233 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 6234 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 6235 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3); 6236 6237 APInt FF(32, 0x5F800000ULL); 6238 6239 // Check whether the sign bit is set. 6240 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 6241 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 6242 ISD::SETLT); 6243 6244 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 6245 SDValue FudgePtr = DAG.getConstantPool( 6246 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 6247 getPointerTy()); 6248 6249 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 6250 SDValue Zero = DAG.getIntPtrConstant(0); 6251 SDValue Four = DAG.getIntPtrConstant(4); 6252 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 6253 Zero, Four); 6254 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 6255 6256 // Load the value out, extending it from f32 to f80. 6257 // FIXME: Avoid the extend by constructing the right constant pool? 6258 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(), 6259 FudgePtr, PseudoSourceValue::getConstantPool(), 6260 0, MVT::f32, false, false, 4); 6261 // Extend everything to 80 bits to force it to be done on x87. 6262 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 6263 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 6264} 6265 6266std::pair<SDValue,SDValue> X86TargetLowering:: 6267FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 6268 DebugLoc dl = Op.getDebugLoc(); 6269 6270 EVT DstTy = Op.getValueType(); 6271 6272 if (!IsSigned) { 6273 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 6274 DstTy = MVT::i64; 6275 } 6276 6277 assert(DstTy.getSimpleVT() <= MVT::i64 && 6278 DstTy.getSimpleVT() >= MVT::i16 && 6279 "Unknown FP_TO_SINT to lower!"); 6280 6281 // These are really Legal. 6282 if (DstTy == MVT::i32 && 6283 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6284 return std::make_pair(SDValue(), SDValue()); 6285 if (Subtarget->is64Bit() && 6286 DstTy == MVT::i64 && 6287 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6288 return std::make_pair(SDValue(), SDValue()); 6289 6290 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 6291 // stack slot. 6292 MachineFunction &MF = DAG.getMachineFunction(); 6293 unsigned MemSize = DstTy.getSizeInBits()/8; 6294 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6295 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6296 6297 unsigned Opc; 6298 switch (DstTy.getSimpleVT().SimpleTy) { 6299 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 6300 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 6301 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 6302 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 6303 } 6304 6305 SDValue Chain = DAG.getEntryNode(); 6306 SDValue Value = Op.getOperand(0); 6307 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 6308 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 6309 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 6310 PseudoSourceValue::getFixedStack(SSFI), 0, 6311 false, false, 0); 6312 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 6313 SDValue Ops[] = { 6314 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 6315 }; 6316 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 6317 Chain = Value.getValue(1); 6318 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6319 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6320 } 6321 6322 // Build the FP_TO_INT*_IN_MEM 6323 SDValue Ops[] = { Chain, Value, StackSlot }; 6324 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 6325 6326 return std::make_pair(FIST, StackSlot); 6327} 6328 6329SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 6330 SelectionDAG &DAG) const { 6331 if (Op.getValueType().isVector()) { 6332 if (Op.getValueType() == MVT::v2i32 && 6333 Op.getOperand(0).getValueType() == MVT::v2f64) { 6334 return Op; 6335 } 6336 return SDValue(); 6337 } 6338 6339 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 6340 SDValue FIST = Vals.first, StackSlot = Vals.second; 6341 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 6342 if (FIST.getNode() == 0) return Op; 6343 6344 // Load the result. 6345 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6346 FIST, StackSlot, NULL, 0, false, false, 0); 6347} 6348 6349SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 6350 SelectionDAG &DAG) const { 6351 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 6352 SDValue FIST = Vals.first, StackSlot = Vals.second; 6353 assert(FIST.getNode() && "Unexpected failure"); 6354 6355 // Load the result. 6356 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6357 FIST, StackSlot, NULL, 0, false, false, 0); 6358} 6359 6360SDValue X86TargetLowering::LowerFABS(SDValue Op, 6361 SelectionDAG &DAG) const { 6362 LLVMContext *Context = DAG.getContext(); 6363 DebugLoc dl = Op.getDebugLoc(); 6364 EVT VT = Op.getValueType(); 6365 EVT EltVT = VT; 6366 if (VT.isVector()) 6367 EltVT = VT.getVectorElementType(); 6368 std::vector<Constant*> CV; 6369 if (EltVT == MVT::f64) { 6370 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 6371 CV.push_back(C); 6372 CV.push_back(C); 6373 } else { 6374 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 6375 CV.push_back(C); 6376 CV.push_back(C); 6377 CV.push_back(C); 6378 CV.push_back(C); 6379 } 6380 Constant *C = ConstantVector::get(CV); 6381 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6382 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6383 PseudoSourceValue::getConstantPool(), 0, 6384 false, false, 16); 6385 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 6386} 6387 6388SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 6389 LLVMContext *Context = DAG.getContext(); 6390 DebugLoc dl = Op.getDebugLoc(); 6391 EVT VT = Op.getValueType(); 6392 EVT EltVT = VT; 6393 if (VT.isVector()) 6394 EltVT = VT.getVectorElementType(); 6395 std::vector<Constant*> CV; 6396 if (EltVT == MVT::f64) { 6397 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 6398 CV.push_back(C); 6399 CV.push_back(C); 6400 } else { 6401 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 6402 CV.push_back(C); 6403 CV.push_back(C); 6404 CV.push_back(C); 6405 CV.push_back(C); 6406 } 6407 Constant *C = ConstantVector::get(CV); 6408 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6409 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6410 PseudoSourceValue::getConstantPool(), 0, 6411 false, false, 16); 6412 if (VT.isVector()) { 6413 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 6414 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 6415 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6416 Op.getOperand(0)), 6417 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 6418 } else { 6419 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 6420 } 6421} 6422 6423SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 6424 LLVMContext *Context = DAG.getContext(); 6425 SDValue Op0 = Op.getOperand(0); 6426 SDValue Op1 = Op.getOperand(1); 6427 DebugLoc dl = Op.getDebugLoc(); 6428 EVT VT = Op.getValueType(); 6429 EVT SrcVT = Op1.getValueType(); 6430 6431 // If second operand is smaller, extend it first. 6432 if (SrcVT.bitsLT(VT)) { 6433 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 6434 SrcVT = VT; 6435 } 6436 // And if it is bigger, shrink it first. 6437 if (SrcVT.bitsGT(VT)) { 6438 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 6439 SrcVT = VT; 6440 } 6441 6442 // At this point the operands and the result should have the same 6443 // type, and that won't be f80 since that is not custom lowered. 6444 6445 // First get the sign bit of second operand. 6446 std::vector<Constant*> CV; 6447 if (SrcVT == MVT::f64) { 6448 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 6449 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6450 } else { 6451 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 6452 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6453 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6454 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6455 } 6456 Constant *C = ConstantVector::get(CV); 6457 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6458 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 6459 PseudoSourceValue::getConstantPool(), 0, 6460 false, false, 16); 6461 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 6462 6463 // Shift sign bit right or left if the two operands have different types. 6464 if (SrcVT.bitsGT(VT)) { 6465 // Op0 is MVT::f32, Op1 is MVT::f64. 6466 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 6467 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 6468 DAG.getConstant(32, MVT::i32)); 6469 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 6470 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 6471 DAG.getIntPtrConstant(0)); 6472 } 6473 6474 // Clear first operand sign bit. 6475 CV.clear(); 6476 if (VT == MVT::f64) { 6477 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 6478 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6479 } else { 6480 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 6481 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6482 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6483 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6484 } 6485 C = ConstantVector::get(CV); 6486 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6487 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6488 PseudoSourceValue::getConstantPool(), 0, 6489 false, false, 16); 6490 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 6491 6492 // Or the value with the sign bit. 6493 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 6494} 6495 6496/// Emit nodes that will be selected as "test Op0,Op0", or something 6497/// equivalent. 6498SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 6499 SelectionDAG &DAG) const { 6500 DebugLoc dl = Op.getDebugLoc(); 6501 6502 // CF and OF aren't always set the way we want. Determine which 6503 // of these we need. 6504 bool NeedCF = false; 6505 bool NeedOF = false; 6506 switch (X86CC) { 6507 default: break; 6508 case X86::COND_A: case X86::COND_AE: 6509 case X86::COND_B: case X86::COND_BE: 6510 NeedCF = true; 6511 break; 6512 case X86::COND_G: case X86::COND_GE: 6513 case X86::COND_L: case X86::COND_LE: 6514 case X86::COND_O: case X86::COND_NO: 6515 NeedOF = true; 6516 break; 6517 } 6518 6519 // See if we can use the EFLAGS value from the operand instead of 6520 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 6521 // we prove that the arithmetic won't overflow, we can't use OF or CF. 6522 if (Op.getResNo() != 0 || NeedOF || NeedCF) 6523 // Emit a CMP with 0, which is the TEST pattern. 6524 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6525 DAG.getConstant(0, Op.getValueType())); 6526 6527 unsigned Opcode = 0; 6528 unsigned NumOperands = 0; 6529 switch (Op.getNode()->getOpcode()) { 6530 case ISD::ADD: 6531 // Due to an isel shortcoming, be conservative if this add is likely to be 6532 // selected as part of a load-modify-store instruction. When the root node 6533 // in a match is a store, isel doesn't know how to remap non-chain non-flag 6534 // uses of other nodes in the match, such as the ADD in this case. This 6535 // leads to the ADD being left around and reselected, with the result being 6536 // two adds in the output. Alas, even if none our users are stores, that 6537 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 6538 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 6539 // climbing the DAG back to the root, and it doesn't seem to be worth the 6540 // effort. 6541 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6542 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6543 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 6544 goto default_case; 6545 6546 if (ConstantSDNode *C = 6547 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 6548 // An add of one will be selected as an INC. 6549 if (C->getAPIntValue() == 1) { 6550 Opcode = X86ISD::INC; 6551 NumOperands = 1; 6552 break; 6553 } 6554 6555 // An add of negative one (subtract of one) will be selected as a DEC. 6556 if (C->getAPIntValue().isAllOnesValue()) { 6557 Opcode = X86ISD::DEC; 6558 NumOperands = 1; 6559 break; 6560 } 6561 } 6562 6563 // Otherwise use a regular EFLAGS-setting add. 6564 Opcode = X86ISD::ADD; 6565 NumOperands = 2; 6566 break; 6567 case ISD::AND: { 6568 // If the primary and result isn't used, don't bother using X86ISD::AND, 6569 // because a TEST instruction will be better. 6570 bool NonFlagUse = false; 6571 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6572 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 6573 SDNode *User = *UI; 6574 unsigned UOpNo = UI.getOperandNo(); 6575 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 6576 // Look pass truncate. 6577 UOpNo = User->use_begin().getOperandNo(); 6578 User = *User->use_begin(); 6579 } 6580 6581 if (User->getOpcode() != ISD::BRCOND && 6582 User->getOpcode() != ISD::SETCC && 6583 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 6584 NonFlagUse = true; 6585 break; 6586 } 6587 } 6588 6589 if (!NonFlagUse) 6590 break; 6591 } 6592 // FALL THROUGH 6593 case ISD::SUB: 6594 case ISD::OR: 6595 case ISD::XOR: 6596 // Due to the ISEL shortcoming noted above, be conservative if this op is 6597 // likely to be selected as part of a load-modify-store instruction. 6598 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6599 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6600 if (UI->getOpcode() == ISD::STORE) 6601 goto default_case; 6602 6603 // Otherwise use a regular EFLAGS-setting instruction. 6604 switch (Op.getNode()->getOpcode()) { 6605 default: llvm_unreachable("unexpected operator!"); 6606 case ISD::SUB: Opcode = X86ISD::SUB; break; 6607 case ISD::OR: Opcode = X86ISD::OR; break; 6608 case ISD::XOR: Opcode = X86ISD::XOR; break; 6609 case ISD::AND: Opcode = X86ISD::AND; break; 6610 } 6611 6612 NumOperands = 2; 6613 break; 6614 case X86ISD::ADD: 6615 case X86ISD::SUB: 6616 case X86ISD::INC: 6617 case X86ISD::DEC: 6618 case X86ISD::OR: 6619 case X86ISD::XOR: 6620 case X86ISD::AND: 6621 return SDValue(Op.getNode(), 1); 6622 default: 6623 default_case: 6624 break; 6625 } 6626 6627 if (Opcode == 0) 6628 // Emit a CMP with 0, which is the TEST pattern. 6629 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6630 DAG.getConstant(0, Op.getValueType())); 6631 6632 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 6633 SmallVector<SDValue, 4> Ops; 6634 for (unsigned i = 0; i != NumOperands; ++i) 6635 Ops.push_back(Op.getOperand(i)); 6636 6637 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 6638 DAG.ReplaceAllUsesWith(Op, New); 6639 return SDValue(New.getNode(), 1); 6640} 6641 6642/// Emit nodes that will be selected as "cmp Op0,Op1", or something 6643/// equivalent. 6644SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 6645 SelectionDAG &DAG) const { 6646 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 6647 if (C->getAPIntValue() == 0) 6648 return EmitTest(Op0, X86CC, DAG); 6649 6650 DebugLoc dl = Op0.getDebugLoc(); 6651 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 6652} 6653 6654/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 6655/// if it's possible. 6656SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 6657 DebugLoc dl, SelectionDAG &DAG) const { 6658 SDValue Op0 = And.getOperand(0); 6659 SDValue Op1 = And.getOperand(1); 6660 if (Op0.getOpcode() == ISD::TRUNCATE) 6661 Op0 = Op0.getOperand(0); 6662 if (Op1.getOpcode() == ISD::TRUNCATE) 6663 Op1 = Op1.getOperand(0); 6664 6665 SDValue LHS, RHS; 6666 if (Op1.getOpcode() == ISD::SHL) 6667 std::swap(Op0, Op1); 6668 if (Op0.getOpcode() == ISD::SHL) { 6669 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6670 if (And00C->getZExtValue() == 1) { 6671 // If we looked past a truncate, check that it's only truncating away 6672 // known zeros. 6673 unsigned BitWidth = Op0.getValueSizeInBits(); 6674 unsigned AndBitWidth = And.getValueSizeInBits(); 6675 if (BitWidth > AndBitWidth) { 6676 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 6677 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 6678 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 6679 return SDValue(); 6680 } 6681 LHS = Op1; 6682 RHS = Op0.getOperand(1); 6683 } 6684 } else if (Op1.getOpcode() == ISD::Constant) { 6685 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6686 SDValue AndLHS = Op0; 6687 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6688 LHS = AndLHS.getOperand(0); 6689 RHS = AndLHS.getOperand(1); 6690 } 6691 } 6692 6693 if (LHS.getNode()) { 6694 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 6695 // instruction. Since the shift amount is in-range-or-undefined, we know 6696 // that doing a bittest on the i32 value is ok. We extend to i32 because 6697 // the encoding for the i16 version is larger than the i32 version. 6698 // Also promote i16 to i32 for performance / code size reason. 6699 if (LHS.getValueType() == MVT::i8 || 6700 LHS.getValueType() == MVT::i16) 6701 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 6702 6703 // If the operand types disagree, extend the shift amount to match. Since 6704 // BT ignores high bits (like shifts) we can use anyextend. 6705 if (LHS.getValueType() != RHS.getValueType()) 6706 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 6707 6708 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 6709 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 6710 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6711 DAG.getConstant(Cond, MVT::i8), BT); 6712 } 6713 6714 return SDValue(); 6715} 6716 6717SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 6718 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 6719 SDValue Op0 = Op.getOperand(0); 6720 SDValue Op1 = Op.getOperand(1); 6721 DebugLoc dl = Op.getDebugLoc(); 6722 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6723 6724 // Optimize to BT if possible. 6725 // Lower (X & (1 << N)) == 0 to BT(X, N). 6726 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 6727 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 6728 if (Op0.getOpcode() == ISD::AND && 6729 Op0.hasOneUse() && 6730 Op1.getOpcode() == ISD::Constant && 6731 cast<ConstantSDNode>(Op1)->isNullValue() && 6732 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6733 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 6734 if (NewSetCC.getNode()) 6735 return NewSetCC; 6736 } 6737 6738 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 6739 if (Op0.getOpcode() == X86ISD::SETCC && 6740 Op1.getOpcode() == ISD::Constant && 6741 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 6742 cast<ConstantSDNode>(Op1)->isNullValue()) && 6743 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6744 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 6745 bool Invert = (CC == ISD::SETNE) ^ 6746 cast<ConstantSDNode>(Op1)->isNullValue(); 6747 if (Invert) 6748 CCode = X86::GetOppositeBranchCondition(CCode); 6749 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6750 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6751 } 6752 6753 bool isFP = Op1.getValueType().isFloatingPoint(); 6754 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6755 if (X86CC == X86::COND_INVALID) 6756 return SDValue(); 6757 6758 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6759 6760 // Use sbb x, x to materialize carry bit into a GPR. 6761 if (X86CC == X86::COND_B) 6762 return DAG.getNode(ISD::AND, dl, MVT::i8, 6763 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6764 DAG.getConstant(X86CC, MVT::i8), Cond), 6765 DAG.getConstant(1, MVT::i8)); 6766 6767 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6768 DAG.getConstant(X86CC, MVT::i8), Cond); 6769} 6770 6771SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 6772 SDValue Cond; 6773 SDValue Op0 = Op.getOperand(0); 6774 SDValue Op1 = Op.getOperand(1); 6775 SDValue CC = Op.getOperand(2); 6776 EVT VT = Op.getValueType(); 6777 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6778 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6779 DebugLoc dl = Op.getDebugLoc(); 6780 6781 if (isFP) { 6782 unsigned SSECC = 8; 6783 EVT VT0 = Op0.getValueType(); 6784 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6785 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6786 bool Swap = false; 6787 6788 switch (SetCCOpcode) { 6789 default: break; 6790 case ISD::SETOEQ: 6791 case ISD::SETEQ: SSECC = 0; break; 6792 case ISD::SETOGT: 6793 case ISD::SETGT: Swap = true; // Fallthrough 6794 case ISD::SETLT: 6795 case ISD::SETOLT: SSECC = 1; break; 6796 case ISD::SETOGE: 6797 case ISD::SETGE: Swap = true; // Fallthrough 6798 case ISD::SETLE: 6799 case ISD::SETOLE: SSECC = 2; break; 6800 case ISD::SETUO: SSECC = 3; break; 6801 case ISD::SETUNE: 6802 case ISD::SETNE: SSECC = 4; break; 6803 case ISD::SETULE: Swap = true; 6804 case ISD::SETUGE: SSECC = 5; break; 6805 case ISD::SETULT: Swap = true; 6806 case ISD::SETUGT: SSECC = 6; break; 6807 case ISD::SETO: SSECC = 7; break; 6808 } 6809 if (Swap) 6810 std::swap(Op0, Op1); 6811 6812 // In the two special cases we can't handle, emit two comparisons. 6813 if (SSECC == 8) { 6814 if (SetCCOpcode == ISD::SETUEQ) { 6815 SDValue UNORD, EQ; 6816 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6817 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6818 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6819 } 6820 else if (SetCCOpcode == ISD::SETONE) { 6821 SDValue ORD, NEQ; 6822 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6823 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6824 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6825 } 6826 llvm_unreachable("Illegal FP comparison"); 6827 } 6828 // Handle all other FP comparisons here. 6829 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6830 } 6831 6832 // We are handling one of the integer comparisons here. Since SSE only has 6833 // GT and EQ comparisons for integer, swapping operands and multiple 6834 // operations may be required for some comparisons. 6835 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6836 bool Swap = false, Invert = false, FlipSigns = false; 6837 6838 switch (VT.getSimpleVT().SimpleTy) { 6839 default: break; 6840 case MVT::v8i8: 6841 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6842 case MVT::v4i16: 6843 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6844 case MVT::v2i32: 6845 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6846 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6847 } 6848 6849 switch (SetCCOpcode) { 6850 default: break; 6851 case ISD::SETNE: Invert = true; 6852 case ISD::SETEQ: Opc = EQOpc; break; 6853 case ISD::SETLT: Swap = true; 6854 case ISD::SETGT: Opc = GTOpc; break; 6855 case ISD::SETGE: Swap = true; 6856 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6857 case ISD::SETULT: Swap = true; 6858 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6859 case ISD::SETUGE: Swap = true; 6860 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6861 } 6862 if (Swap) 6863 std::swap(Op0, Op1); 6864 6865 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6866 // bits of the inputs before performing those operations. 6867 if (FlipSigns) { 6868 EVT EltVT = VT.getVectorElementType(); 6869 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6870 EltVT); 6871 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6872 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6873 SignBits.size()); 6874 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6875 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6876 } 6877 6878 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6879 6880 // If the logical-not of the result is required, perform that now. 6881 if (Invert) 6882 Result = DAG.getNOT(dl, Result, VT); 6883 6884 return Result; 6885} 6886 6887// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6888static bool isX86LogicalCmp(SDValue Op) { 6889 unsigned Opc = Op.getNode()->getOpcode(); 6890 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6891 return true; 6892 if (Op.getResNo() == 1 && 6893 (Opc == X86ISD::ADD || 6894 Opc == X86ISD::SUB || 6895 Opc == X86ISD::SMUL || 6896 Opc == X86ISD::UMUL || 6897 Opc == X86ISD::INC || 6898 Opc == X86ISD::DEC || 6899 Opc == X86ISD::OR || 6900 Opc == X86ISD::XOR || 6901 Opc == X86ISD::AND)) 6902 return true; 6903 6904 return false; 6905} 6906 6907SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 6908 bool addTest = true; 6909 SDValue Cond = Op.getOperand(0); 6910 DebugLoc dl = Op.getDebugLoc(); 6911 SDValue CC; 6912 6913 if (Cond.getOpcode() == ISD::SETCC) { 6914 SDValue NewCond = LowerSETCC(Cond, DAG); 6915 if (NewCond.getNode()) 6916 Cond = NewCond; 6917 } 6918 6919 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6920 SDValue Op1 = Op.getOperand(1); 6921 SDValue Op2 = Op.getOperand(2); 6922 if (Cond.getOpcode() == X86ISD::SETCC && 6923 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6924 SDValue Cmp = Cond.getOperand(1); 6925 if (Cmp.getOpcode() == X86ISD::CMP) { 6926 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6927 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6928 ConstantSDNode *RHSC = 6929 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6930 if (N1C && N1C->isAllOnesValue() && 6931 N2C && N2C->isNullValue() && 6932 RHSC && RHSC->isNullValue()) { 6933 SDValue CmpOp0 = Cmp.getOperand(0); 6934 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6935 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6936 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6937 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6938 } 6939 } 6940 } 6941 6942 // Look pass (and (setcc_carry (cmp ...)), 1). 6943 if (Cond.getOpcode() == ISD::AND && 6944 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6945 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6946 if (C && C->getAPIntValue() == 1) 6947 Cond = Cond.getOperand(0); 6948 } 6949 6950 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6951 // setting operand in place of the X86ISD::SETCC. 6952 if (Cond.getOpcode() == X86ISD::SETCC || 6953 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6954 CC = Cond.getOperand(0); 6955 6956 SDValue Cmp = Cond.getOperand(1); 6957 unsigned Opc = Cmp.getOpcode(); 6958 EVT VT = Op.getValueType(); 6959 6960 bool IllegalFPCMov = false; 6961 if (VT.isFloatingPoint() && !VT.isVector() && 6962 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6963 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6964 6965 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6966 Opc == X86ISD::BT) { // FIXME 6967 Cond = Cmp; 6968 addTest = false; 6969 } 6970 } 6971 6972 if (addTest) { 6973 // Look pass the truncate. 6974 if (Cond.getOpcode() == ISD::TRUNCATE) 6975 Cond = Cond.getOperand(0); 6976 6977 // We know the result of AND is compared against zero. Try to match 6978 // it to BT. 6979 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6980 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6981 if (NewSetCC.getNode()) { 6982 CC = NewSetCC.getOperand(0); 6983 Cond = NewSetCC.getOperand(1); 6984 addTest = false; 6985 } 6986 } 6987 } 6988 6989 if (addTest) { 6990 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6991 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6992 } 6993 6994 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6995 // condition is true. 6996 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6997 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6998 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6999} 7000 7001// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 7002// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 7003// from the AND / OR. 7004static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 7005 Opc = Op.getOpcode(); 7006 if (Opc != ISD::OR && Opc != ISD::AND) 7007 return false; 7008 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7009 Op.getOperand(0).hasOneUse() && 7010 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 7011 Op.getOperand(1).hasOneUse()); 7012} 7013 7014// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 7015// 1 and that the SETCC node has a single use. 7016static bool isXor1OfSetCC(SDValue Op) { 7017 if (Op.getOpcode() != ISD::XOR) 7018 return false; 7019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7020 if (N1C && N1C->getAPIntValue() == 1) { 7021 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 7022 Op.getOperand(0).hasOneUse(); 7023 } 7024 return false; 7025} 7026 7027SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 7028 bool addTest = true; 7029 SDValue Chain = Op.getOperand(0); 7030 SDValue Cond = Op.getOperand(1); 7031 SDValue Dest = Op.getOperand(2); 7032 DebugLoc dl = Op.getDebugLoc(); 7033 SDValue CC; 7034 7035 if (Cond.getOpcode() == ISD::SETCC) { 7036 SDValue NewCond = LowerSETCC(Cond, DAG); 7037 if (NewCond.getNode()) 7038 Cond = NewCond; 7039 } 7040#if 0 7041 // FIXME: LowerXALUO doesn't handle these!! 7042 else if (Cond.getOpcode() == X86ISD::ADD || 7043 Cond.getOpcode() == X86ISD::SUB || 7044 Cond.getOpcode() == X86ISD::SMUL || 7045 Cond.getOpcode() == X86ISD::UMUL) 7046 Cond = LowerXALUO(Cond, DAG); 7047#endif 7048 7049 // Look pass (and (setcc_carry (cmp ...)), 1). 7050 if (Cond.getOpcode() == ISD::AND && 7051 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 7052 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 7053 if (C && C->getAPIntValue() == 1) 7054 Cond = Cond.getOperand(0); 7055 } 7056 7057 // If condition flag is set by a X86ISD::CMP, then use it as the condition 7058 // setting operand in place of the X86ISD::SETCC. 7059 if (Cond.getOpcode() == X86ISD::SETCC || 7060 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 7061 CC = Cond.getOperand(0); 7062 7063 SDValue Cmp = Cond.getOperand(1); 7064 unsigned Opc = Cmp.getOpcode(); 7065 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 7066 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 7067 Cond = Cmp; 7068 addTest = false; 7069 } else { 7070 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 7071 default: break; 7072 case X86::COND_O: 7073 case X86::COND_B: 7074 // These can only come from an arithmetic instruction with overflow, 7075 // e.g. SADDO, UADDO. 7076 Cond = Cond.getNode()->getOperand(1); 7077 addTest = false; 7078 break; 7079 } 7080 } 7081 } else { 7082 unsigned CondOpc; 7083 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 7084 SDValue Cmp = Cond.getOperand(0).getOperand(1); 7085 if (CondOpc == ISD::OR) { 7086 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 7087 // two branches instead of an explicit OR instruction with a 7088 // separate test. 7089 if (Cmp == Cond.getOperand(1).getOperand(1) && 7090 isX86LogicalCmp(Cmp)) { 7091 CC = Cond.getOperand(0).getOperand(0); 7092 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7093 Chain, Dest, CC, Cmp); 7094 CC = Cond.getOperand(1).getOperand(0); 7095 Cond = Cmp; 7096 addTest = false; 7097 } 7098 } else { // ISD::AND 7099 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 7100 // two branches instead of an explicit AND instruction with a 7101 // separate test. However, we only do this if this block doesn't 7102 // have a fall-through edge, because this requires an explicit 7103 // jmp when the condition is false. 7104 if (Cmp == Cond.getOperand(1).getOperand(1) && 7105 isX86LogicalCmp(Cmp) && 7106 Op.getNode()->hasOneUse()) { 7107 X86::CondCode CCode = 7108 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7109 CCode = X86::GetOppositeBranchCondition(CCode); 7110 CC = DAG.getConstant(CCode, MVT::i8); 7111 SDNode *User = *Op.getNode()->use_begin(); 7112 // Look for an unconditional branch following this conditional branch. 7113 // We need this because we need to reverse the successors in order 7114 // to implement FCMP_OEQ. 7115 if (User->getOpcode() == ISD::BR) { 7116 SDValue FalseBB = User->getOperand(1); 7117 SDNode *NewBR = 7118 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 7119 assert(NewBR == User); 7120 (void)NewBR; 7121 Dest = FalseBB; 7122 7123 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7124 Chain, Dest, CC, Cmp); 7125 X86::CondCode CCode = 7126 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 7127 CCode = X86::GetOppositeBranchCondition(CCode); 7128 CC = DAG.getConstant(CCode, MVT::i8); 7129 Cond = Cmp; 7130 addTest = false; 7131 } 7132 } 7133 } 7134 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 7135 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 7136 // It should be transformed during dag combiner except when the condition 7137 // is set by a arithmetics with overflow node. 7138 X86::CondCode CCode = 7139 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7140 CCode = X86::GetOppositeBranchCondition(CCode); 7141 CC = DAG.getConstant(CCode, MVT::i8); 7142 Cond = Cond.getOperand(0).getOperand(1); 7143 addTest = false; 7144 } 7145 } 7146 7147 if (addTest) { 7148 // Look pass the truncate. 7149 if (Cond.getOpcode() == ISD::TRUNCATE) 7150 Cond = Cond.getOperand(0); 7151 7152 // We know the result of AND is compared against zero. Try to match 7153 // it to BT. 7154 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7155 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 7156 if (NewSetCC.getNode()) { 7157 CC = NewSetCC.getOperand(0); 7158 Cond = NewSetCC.getOperand(1); 7159 addTest = false; 7160 } 7161 } 7162 } 7163 7164 if (addTest) { 7165 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7166 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7167 } 7168 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7169 Chain, Dest, CC, Cond); 7170} 7171 7172 7173// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 7174// Calls to _alloca is needed to probe the stack when allocating more than 4k 7175// bytes in one go. Touching the stack at 4K increments is necessary to ensure 7176// that the guard pages used by the OS virtual memory manager are allocated in 7177// correct sequence. 7178SDValue 7179X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 7180 SelectionDAG &DAG) const { 7181 assert(Subtarget->isTargetCygMing() && 7182 "This should be used only on Cygwin/Mingw targets"); 7183 DebugLoc dl = Op.getDebugLoc(); 7184 7185 // Get the inputs. 7186 SDValue Chain = Op.getOperand(0); 7187 SDValue Size = Op.getOperand(1); 7188 // FIXME: Ensure alignment here 7189 7190 SDValue Flag; 7191 7192 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 7193 7194 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 7195 Flag = Chain.getValue(1); 7196 7197 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 7198 7199 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 7200 Flag = Chain.getValue(1); 7201 7202 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 7203 7204 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 7205 return DAG.getMergeValues(Ops1, 2, dl); 7206} 7207 7208SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 7209 MachineFunction &MF = DAG.getMachineFunction(); 7210 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 7211 7212 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 7213 DebugLoc dl = Op.getDebugLoc(); 7214 7215 if (!Subtarget->is64Bit()) { 7216 // vastart just stores the address of the VarArgsFrameIndex slot into the 7217 // memory location argument. 7218 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7219 getPointerTy()); 7220 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 7221 false, false, 0); 7222 } 7223 7224 // __va_list_tag: 7225 // gp_offset (0 - 6 * 8) 7226 // fp_offset (48 - 48 + 8 * 16) 7227 // overflow_arg_area (point to parameters coming in memory). 7228 // reg_save_area 7229 SmallVector<SDValue, 8> MemOps; 7230 SDValue FIN = Op.getOperand(1); 7231 // Store gp_offset 7232 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 7233 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 7234 MVT::i32), 7235 FIN, SV, 0, false, false, 0); 7236 MemOps.push_back(Store); 7237 7238 // Store fp_offset 7239 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7240 FIN, DAG.getIntPtrConstant(4)); 7241 Store = DAG.getStore(Op.getOperand(0), dl, 7242 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 7243 MVT::i32), 7244 FIN, SV, 4, false, false, 0); 7245 MemOps.push_back(Store); 7246 7247 // Store ptr to overflow_arg_area 7248 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7249 FIN, DAG.getIntPtrConstant(4)); 7250 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7251 getPointerTy()); 7252 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8, 7253 false, false, 0); 7254 MemOps.push_back(Store); 7255 7256 // Store ptr to reg_save_area. 7257 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7258 FIN, DAG.getIntPtrConstant(8)); 7259 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 7260 getPointerTy()); 7261 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16, 7262 false, false, 0); 7263 MemOps.push_back(Store); 7264 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 7265 &MemOps[0], MemOps.size()); 7266} 7267 7268SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 7269 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 7270 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 7271 7272 report_fatal_error("VAArgInst is not yet implemented for x86-64!"); 7273 return SDValue(); 7274} 7275 7276SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 7277 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 7278 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 7279 SDValue Chain = Op.getOperand(0); 7280 SDValue DstPtr = Op.getOperand(1); 7281 SDValue SrcPtr = Op.getOperand(2); 7282 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 7283 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7284 DebugLoc dl = Op.getDebugLoc(); 7285 7286 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 7287 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 7288 false, DstSV, 0, SrcSV, 0); 7289} 7290 7291SDValue 7292X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 7293 DebugLoc dl = Op.getDebugLoc(); 7294 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7295 switch (IntNo) { 7296 default: return SDValue(); // Don't custom lower most intrinsics. 7297 // Comparison intrinsics. 7298 case Intrinsic::x86_sse_comieq_ss: 7299 case Intrinsic::x86_sse_comilt_ss: 7300 case Intrinsic::x86_sse_comile_ss: 7301 case Intrinsic::x86_sse_comigt_ss: 7302 case Intrinsic::x86_sse_comige_ss: 7303 case Intrinsic::x86_sse_comineq_ss: 7304 case Intrinsic::x86_sse_ucomieq_ss: 7305 case Intrinsic::x86_sse_ucomilt_ss: 7306 case Intrinsic::x86_sse_ucomile_ss: 7307 case Intrinsic::x86_sse_ucomigt_ss: 7308 case Intrinsic::x86_sse_ucomige_ss: 7309 case Intrinsic::x86_sse_ucomineq_ss: 7310 case Intrinsic::x86_sse2_comieq_sd: 7311 case Intrinsic::x86_sse2_comilt_sd: 7312 case Intrinsic::x86_sse2_comile_sd: 7313 case Intrinsic::x86_sse2_comigt_sd: 7314 case Intrinsic::x86_sse2_comige_sd: 7315 case Intrinsic::x86_sse2_comineq_sd: 7316 case Intrinsic::x86_sse2_ucomieq_sd: 7317 case Intrinsic::x86_sse2_ucomilt_sd: 7318 case Intrinsic::x86_sse2_ucomile_sd: 7319 case Intrinsic::x86_sse2_ucomigt_sd: 7320 case Intrinsic::x86_sse2_ucomige_sd: 7321 case Intrinsic::x86_sse2_ucomineq_sd: { 7322 unsigned Opc = 0; 7323 ISD::CondCode CC = ISD::SETCC_INVALID; 7324 switch (IntNo) { 7325 default: break; 7326 case Intrinsic::x86_sse_comieq_ss: 7327 case Intrinsic::x86_sse2_comieq_sd: 7328 Opc = X86ISD::COMI; 7329 CC = ISD::SETEQ; 7330 break; 7331 case Intrinsic::x86_sse_comilt_ss: 7332 case Intrinsic::x86_sse2_comilt_sd: 7333 Opc = X86ISD::COMI; 7334 CC = ISD::SETLT; 7335 break; 7336 case Intrinsic::x86_sse_comile_ss: 7337 case Intrinsic::x86_sse2_comile_sd: 7338 Opc = X86ISD::COMI; 7339 CC = ISD::SETLE; 7340 break; 7341 case Intrinsic::x86_sse_comigt_ss: 7342 case Intrinsic::x86_sse2_comigt_sd: 7343 Opc = X86ISD::COMI; 7344 CC = ISD::SETGT; 7345 break; 7346 case Intrinsic::x86_sse_comige_ss: 7347 case Intrinsic::x86_sse2_comige_sd: 7348 Opc = X86ISD::COMI; 7349 CC = ISD::SETGE; 7350 break; 7351 case Intrinsic::x86_sse_comineq_ss: 7352 case Intrinsic::x86_sse2_comineq_sd: 7353 Opc = X86ISD::COMI; 7354 CC = ISD::SETNE; 7355 break; 7356 case Intrinsic::x86_sse_ucomieq_ss: 7357 case Intrinsic::x86_sse2_ucomieq_sd: 7358 Opc = X86ISD::UCOMI; 7359 CC = ISD::SETEQ; 7360 break; 7361 case Intrinsic::x86_sse_ucomilt_ss: 7362 case Intrinsic::x86_sse2_ucomilt_sd: 7363 Opc = X86ISD::UCOMI; 7364 CC = ISD::SETLT; 7365 break; 7366 case Intrinsic::x86_sse_ucomile_ss: 7367 case Intrinsic::x86_sse2_ucomile_sd: 7368 Opc = X86ISD::UCOMI; 7369 CC = ISD::SETLE; 7370 break; 7371 case Intrinsic::x86_sse_ucomigt_ss: 7372 case Intrinsic::x86_sse2_ucomigt_sd: 7373 Opc = X86ISD::UCOMI; 7374 CC = ISD::SETGT; 7375 break; 7376 case Intrinsic::x86_sse_ucomige_ss: 7377 case Intrinsic::x86_sse2_ucomige_sd: 7378 Opc = X86ISD::UCOMI; 7379 CC = ISD::SETGE; 7380 break; 7381 case Intrinsic::x86_sse_ucomineq_ss: 7382 case Intrinsic::x86_sse2_ucomineq_sd: 7383 Opc = X86ISD::UCOMI; 7384 CC = ISD::SETNE; 7385 break; 7386 } 7387 7388 SDValue LHS = Op.getOperand(1); 7389 SDValue RHS = Op.getOperand(2); 7390 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 7391 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 7392 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 7393 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7394 DAG.getConstant(X86CC, MVT::i8), Cond); 7395 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7396 } 7397 // ptest and testp intrinsics. The intrinsic these come from are designed to 7398 // return an integer value, not just an instruction so lower it to the ptest 7399 // or testp pattern and a setcc for the result. 7400 case Intrinsic::x86_sse41_ptestz: 7401 case Intrinsic::x86_sse41_ptestc: 7402 case Intrinsic::x86_sse41_ptestnzc: 7403 case Intrinsic::x86_avx_ptestz_256: 7404 case Intrinsic::x86_avx_ptestc_256: 7405 case Intrinsic::x86_avx_ptestnzc_256: 7406 case Intrinsic::x86_avx_vtestz_ps: 7407 case Intrinsic::x86_avx_vtestc_ps: 7408 case Intrinsic::x86_avx_vtestnzc_ps: 7409 case Intrinsic::x86_avx_vtestz_pd: 7410 case Intrinsic::x86_avx_vtestc_pd: 7411 case Intrinsic::x86_avx_vtestnzc_pd: 7412 case Intrinsic::x86_avx_vtestz_ps_256: 7413 case Intrinsic::x86_avx_vtestc_ps_256: 7414 case Intrinsic::x86_avx_vtestnzc_ps_256: 7415 case Intrinsic::x86_avx_vtestz_pd_256: 7416 case Intrinsic::x86_avx_vtestc_pd_256: 7417 case Intrinsic::x86_avx_vtestnzc_pd_256: { 7418 bool IsTestPacked = false; 7419 unsigned X86CC = 0; 7420 switch (IntNo) { 7421 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 7422 case Intrinsic::x86_avx_vtestz_ps: 7423 case Intrinsic::x86_avx_vtestz_pd: 7424 case Intrinsic::x86_avx_vtestz_ps_256: 7425 case Intrinsic::x86_avx_vtestz_pd_256: 7426 IsTestPacked = true; // Fallthrough 7427 case Intrinsic::x86_sse41_ptestz: 7428 case Intrinsic::x86_avx_ptestz_256: 7429 // ZF = 1 7430 X86CC = X86::COND_E; 7431 break; 7432 case Intrinsic::x86_avx_vtestc_ps: 7433 case Intrinsic::x86_avx_vtestc_pd: 7434 case Intrinsic::x86_avx_vtestc_ps_256: 7435 case Intrinsic::x86_avx_vtestc_pd_256: 7436 IsTestPacked = true; // Fallthrough 7437 case Intrinsic::x86_sse41_ptestc: 7438 case Intrinsic::x86_avx_ptestc_256: 7439 // CF = 1 7440 X86CC = X86::COND_B; 7441 break; 7442 case Intrinsic::x86_avx_vtestnzc_ps: 7443 case Intrinsic::x86_avx_vtestnzc_pd: 7444 case Intrinsic::x86_avx_vtestnzc_ps_256: 7445 case Intrinsic::x86_avx_vtestnzc_pd_256: 7446 IsTestPacked = true; // Fallthrough 7447 case Intrinsic::x86_sse41_ptestnzc: 7448 case Intrinsic::x86_avx_ptestnzc_256: 7449 // ZF and CF = 0 7450 X86CC = X86::COND_A; 7451 break; 7452 } 7453 7454 SDValue LHS = Op.getOperand(1); 7455 SDValue RHS = Op.getOperand(2); 7456 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 7457 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 7458 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 7459 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 7460 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7461 } 7462 7463 // Fix vector shift instructions where the last operand is a non-immediate 7464 // i32 value. 7465 case Intrinsic::x86_sse2_pslli_w: 7466 case Intrinsic::x86_sse2_pslli_d: 7467 case Intrinsic::x86_sse2_pslli_q: 7468 case Intrinsic::x86_sse2_psrli_w: 7469 case Intrinsic::x86_sse2_psrli_d: 7470 case Intrinsic::x86_sse2_psrli_q: 7471 case Intrinsic::x86_sse2_psrai_w: 7472 case Intrinsic::x86_sse2_psrai_d: 7473 case Intrinsic::x86_mmx_pslli_w: 7474 case Intrinsic::x86_mmx_pslli_d: 7475 case Intrinsic::x86_mmx_pslli_q: 7476 case Intrinsic::x86_mmx_psrli_w: 7477 case Intrinsic::x86_mmx_psrli_d: 7478 case Intrinsic::x86_mmx_psrli_q: 7479 case Intrinsic::x86_mmx_psrai_w: 7480 case Intrinsic::x86_mmx_psrai_d: { 7481 SDValue ShAmt = Op.getOperand(2); 7482 if (isa<ConstantSDNode>(ShAmt)) 7483 return SDValue(); 7484 7485 unsigned NewIntNo = 0; 7486 EVT ShAmtVT = MVT::v4i32; 7487 switch (IntNo) { 7488 case Intrinsic::x86_sse2_pslli_w: 7489 NewIntNo = Intrinsic::x86_sse2_psll_w; 7490 break; 7491 case Intrinsic::x86_sse2_pslli_d: 7492 NewIntNo = Intrinsic::x86_sse2_psll_d; 7493 break; 7494 case Intrinsic::x86_sse2_pslli_q: 7495 NewIntNo = Intrinsic::x86_sse2_psll_q; 7496 break; 7497 case Intrinsic::x86_sse2_psrli_w: 7498 NewIntNo = Intrinsic::x86_sse2_psrl_w; 7499 break; 7500 case Intrinsic::x86_sse2_psrli_d: 7501 NewIntNo = Intrinsic::x86_sse2_psrl_d; 7502 break; 7503 case Intrinsic::x86_sse2_psrli_q: 7504 NewIntNo = Intrinsic::x86_sse2_psrl_q; 7505 break; 7506 case Intrinsic::x86_sse2_psrai_w: 7507 NewIntNo = Intrinsic::x86_sse2_psra_w; 7508 break; 7509 case Intrinsic::x86_sse2_psrai_d: 7510 NewIntNo = Intrinsic::x86_sse2_psra_d; 7511 break; 7512 default: { 7513 ShAmtVT = MVT::v2i32; 7514 switch (IntNo) { 7515 case Intrinsic::x86_mmx_pslli_w: 7516 NewIntNo = Intrinsic::x86_mmx_psll_w; 7517 break; 7518 case Intrinsic::x86_mmx_pslli_d: 7519 NewIntNo = Intrinsic::x86_mmx_psll_d; 7520 break; 7521 case Intrinsic::x86_mmx_pslli_q: 7522 NewIntNo = Intrinsic::x86_mmx_psll_q; 7523 break; 7524 case Intrinsic::x86_mmx_psrli_w: 7525 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7526 break; 7527 case Intrinsic::x86_mmx_psrli_d: 7528 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7529 break; 7530 case Intrinsic::x86_mmx_psrli_q: 7531 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7532 break; 7533 case Intrinsic::x86_mmx_psrai_w: 7534 NewIntNo = Intrinsic::x86_mmx_psra_w; 7535 break; 7536 case Intrinsic::x86_mmx_psrai_d: 7537 NewIntNo = Intrinsic::x86_mmx_psra_d; 7538 break; 7539 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7540 } 7541 break; 7542 } 7543 } 7544 7545 // The vector shift intrinsics with scalars uses 32b shift amounts but 7546 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7547 // to be zero. 7548 SDValue ShOps[4]; 7549 ShOps[0] = ShAmt; 7550 ShOps[1] = DAG.getConstant(0, MVT::i32); 7551 if (ShAmtVT == MVT::v4i32) { 7552 ShOps[2] = DAG.getUNDEF(MVT::i32); 7553 ShOps[3] = DAG.getUNDEF(MVT::i32); 7554 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7555 } else { 7556 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7557 } 7558 7559 EVT VT = Op.getValueType(); 7560 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 7561 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7562 DAG.getConstant(NewIntNo, MVT::i32), 7563 Op.getOperand(1), ShAmt); 7564 } 7565 } 7566} 7567 7568SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 7569 SelectionDAG &DAG) const { 7570 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7571 MFI->setReturnAddressIsTaken(true); 7572 7573 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7574 DebugLoc dl = Op.getDebugLoc(); 7575 7576 if (Depth > 0) { 7577 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7578 SDValue Offset = 7579 DAG.getConstant(TD->getPointerSize(), 7580 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7581 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7582 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7583 FrameAddr, Offset), 7584 NULL, 0, false, false, 0); 7585 } 7586 7587 // Just load the return address. 7588 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7589 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7590 RetAddrFI, NULL, 0, false, false, 0); 7591} 7592 7593SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 7594 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7595 MFI->setFrameAddressIsTaken(true); 7596 7597 EVT VT = Op.getValueType(); 7598 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7599 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7600 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7601 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7602 while (Depth--) 7603 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7604 false, false, 0); 7605 return FrameAddr; 7606} 7607 7608SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7609 SelectionDAG &DAG) const { 7610 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7611} 7612 7613SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 7614 MachineFunction &MF = DAG.getMachineFunction(); 7615 SDValue Chain = Op.getOperand(0); 7616 SDValue Offset = Op.getOperand(1); 7617 SDValue Handler = Op.getOperand(2); 7618 DebugLoc dl = Op.getDebugLoc(); 7619 7620 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 7621 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7622 getPointerTy()); 7623 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7624 7625 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 7626 DAG.getIntPtrConstant(TD->getPointerSize())); 7627 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7628 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7629 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7630 MF.getRegInfo().addLiveOut(StoreAddrReg); 7631 7632 return DAG.getNode(X86ISD::EH_RETURN, dl, 7633 MVT::Other, 7634 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7635} 7636 7637SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7638 SelectionDAG &DAG) const { 7639 SDValue Root = Op.getOperand(0); 7640 SDValue Trmp = Op.getOperand(1); // trampoline 7641 SDValue FPtr = Op.getOperand(2); // nested function 7642 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7643 DebugLoc dl = Op.getDebugLoc(); 7644 7645 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7646 7647 if (Subtarget->is64Bit()) { 7648 SDValue OutChains[6]; 7649 7650 // Large code-model. 7651 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7652 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7653 7654 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7655 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7656 7657 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7658 7659 // Load the pointer to the nested function into R11. 7660 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7661 SDValue Addr = Trmp; 7662 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7663 Addr, TrmpAddr, 0, false, false, 0); 7664 7665 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7666 DAG.getConstant(2, MVT::i64)); 7667 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7668 false, false, 2); 7669 7670 // Load the 'nest' parameter value into R10. 7671 // R10 is specified in X86CallingConv.td 7672 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7673 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7674 DAG.getConstant(10, MVT::i64)); 7675 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7676 Addr, TrmpAddr, 10, false, false, 0); 7677 7678 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7679 DAG.getConstant(12, MVT::i64)); 7680 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7681 false, false, 2); 7682 7683 // Jump to the nested function. 7684 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7685 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7686 DAG.getConstant(20, MVT::i64)); 7687 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7688 Addr, TrmpAddr, 20, false, false, 0); 7689 7690 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7691 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7692 DAG.getConstant(22, MVT::i64)); 7693 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7694 TrmpAddr, 22, false, false, 0); 7695 7696 SDValue Ops[] = 7697 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7698 return DAG.getMergeValues(Ops, 2, dl); 7699 } else { 7700 const Function *Func = 7701 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7702 CallingConv::ID CC = Func->getCallingConv(); 7703 unsigned NestReg; 7704 7705 switch (CC) { 7706 default: 7707 llvm_unreachable("Unsupported calling convention"); 7708 case CallingConv::C: 7709 case CallingConv::X86_StdCall: { 7710 // Pass 'nest' parameter in ECX. 7711 // Must be kept in sync with X86CallingConv.td 7712 NestReg = X86::ECX; 7713 7714 // Check that ECX wasn't needed by an 'inreg' parameter. 7715 const FunctionType *FTy = Func->getFunctionType(); 7716 const AttrListPtr &Attrs = Func->getAttributes(); 7717 7718 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7719 unsigned InRegCount = 0; 7720 unsigned Idx = 1; 7721 7722 for (FunctionType::param_iterator I = FTy->param_begin(), 7723 E = FTy->param_end(); I != E; ++I, ++Idx) 7724 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7725 // FIXME: should only count parameters that are lowered to integers. 7726 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7727 7728 if (InRegCount > 2) { 7729 report_fatal_error("Nest register in use - reduce number of inreg" 7730 " parameters!"); 7731 } 7732 } 7733 break; 7734 } 7735 case CallingConv::X86_FastCall: 7736 case CallingConv::X86_ThisCall: 7737 case CallingConv::Fast: 7738 // Pass 'nest' parameter in EAX. 7739 // Must be kept in sync with X86CallingConv.td 7740 NestReg = X86::EAX; 7741 break; 7742 } 7743 7744 SDValue OutChains[4]; 7745 SDValue Addr, Disp; 7746 7747 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7748 DAG.getConstant(10, MVT::i32)); 7749 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7750 7751 // This is storing the opcode for MOV32ri. 7752 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7753 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7754 OutChains[0] = DAG.getStore(Root, dl, 7755 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7756 Trmp, TrmpAddr, 0, false, false, 0); 7757 7758 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7759 DAG.getConstant(1, MVT::i32)); 7760 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7761 false, false, 1); 7762 7763 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7765 DAG.getConstant(5, MVT::i32)); 7766 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7767 TrmpAddr, 5, false, false, 1); 7768 7769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7770 DAG.getConstant(6, MVT::i32)); 7771 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7772 false, false, 1); 7773 7774 SDValue Ops[] = 7775 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7776 return DAG.getMergeValues(Ops, 2, dl); 7777 } 7778} 7779 7780SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 7781 SelectionDAG &DAG) const { 7782 /* 7783 The rounding mode is in bits 11:10 of FPSR, and has the following 7784 settings: 7785 00 Round to nearest 7786 01 Round to -inf 7787 10 Round to +inf 7788 11 Round to 0 7789 7790 FLT_ROUNDS, on the other hand, expects the following: 7791 -1 Undefined 7792 0 Round to 0 7793 1 Round to nearest 7794 2 Round to +inf 7795 3 Round to -inf 7796 7797 To perform the conversion, we do: 7798 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7799 */ 7800 7801 MachineFunction &MF = DAG.getMachineFunction(); 7802 const TargetMachine &TM = MF.getTarget(); 7803 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7804 unsigned StackAlignment = TFI.getStackAlignment(); 7805 EVT VT = Op.getValueType(); 7806 DebugLoc dl = Op.getDebugLoc(); 7807 7808 // Save FP Control Word to stack slot 7809 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7810 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7811 7812 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7813 DAG.getEntryNode(), StackSlot); 7814 7815 // Load FP Control Word from stack slot 7816 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7817 false, false, 0); 7818 7819 // Transform as necessary 7820 SDValue CWD1 = 7821 DAG.getNode(ISD::SRL, dl, MVT::i16, 7822 DAG.getNode(ISD::AND, dl, MVT::i16, 7823 CWD, DAG.getConstant(0x800, MVT::i16)), 7824 DAG.getConstant(11, MVT::i8)); 7825 SDValue CWD2 = 7826 DAG.getNode(ISD::SRL, dl, MVT::i16, 7827 DAG.getNode(ISD::AND, dl, MVT::i16, 7828 CWD, DAG.getConstant(0x400, MVT::i16)), 7829 DAG.getConstant(9, MVT::i8)); 7830 7831 SDValue RetVal = 7832 DAG.getNode(ISD::AND, dl, MVT::i16, 7833 DAG.getNode(ISD::ADD, dl, MVT::i16, 7834 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7835 DAG.getConstant(1, MVT::i16)), 7836 DAG.getConstant(3, MVT::i16)); 7837 7838 7839 return DAG.getNode((VT.getSizeInBits() < 16 ? 7840 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7841} 7842 7843SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 7844 EVT VT = Op.getValueType(); 7845 EVT OpVT = VT; 7846 unsigned NumBits = VT.getSizeInBits(); 7847 DebugLoc dl = Op.getDebugLoc(); 7848 7849 Op = Op.getOperand(0); 7850 if (VT == MVT::i8) { 7851 // Zero extend to i32 since there is not an i8 bsr. 7852 OpVT = MVT::i32; 7853 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7854 } 7855 7856 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7857 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7858 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7859 7860 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7861 SDValue Ops[] = { 7862 Op, 7863 DAG.getConstant(NumBits+NumBits-1, OpVT), 7864 DAG.getConstant(X86::COND_E, MVT::i8), 7865 Op.getValue(1) 7866 }; 7867 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7868 7869 // Finally xor with NumBits-1. 7870 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7871 7872 if (VT == MVT::i8) 7873 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7874 return Op; 7875} 7876 7877SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 7878 EVT VT = Op.getValueType(); 7879 EVT OpVT = VT; 7880 unsigned NumBits = VT.getSizeInBits(); 7881 DebugLoc dl = Op.getDebugLoc(); 7882 7883 Op = Op.getOperand(0); 7884 if (VT == MVT::i8) { 7885 OpVT = MVT::i32; 7886 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7887 } 7888 7889 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7890 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7891 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7892 7893 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7894 SDValue Ops[] = { 7895 Op, 7896 DAG.getConstant(NumBits, OpVT), 7897 DAG.getConstant(X86::COND_E, MVT::i8), 7898 Op.getValue(1) 7899 }; 7900 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7901 7902 if (VT == MVT::i8) 7903 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7904 return Op; 7905} 7906 7907SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 7908 EVT VT = Op.getValueType(); 7909 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7910 DebugLoc dl = Op.getDebugLoc(); 7911 7912 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7913 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7914 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7915 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7916 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7917 // 7918 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7919 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7920 // return AloBlo + AloBhi + AhiBlo; 7921 7922 SDValue A = Op.getOperand(0); 7923 SDValue B = Op.getOperand(1); 7924 7925 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7926 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7927 A, DAG.getConstant(32, MVT::i32)); 7928 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7929 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7930 B, DAG.getConstant(32, MVT::i32)); 7931 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7932 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7933 A, B); 7934 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7935 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7936 A, Bhi); 7937 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7938 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7939 Ahi, B); 7940 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7941 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7942 AloBhi, DAG.getConstant(32, MVT::i32)); 7943 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7944 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7945 AhiBlo, DAG.getConstant(32, MVT::i32)); 7946 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7947 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7948 return Res; 7949} 7950 7951SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { 7952 EVT VT = Op.getValueType(); 7953 DebugLoc dl = Op.getDebugLoc(); 7954 SDValue R = Op.getOperand(0); 7955 7956 LLVMContext *Context = DAG.getContext(); 7957 7958 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later"); 7959 7960 if (VT == MVT::v4i32) { 7961 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7962 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 7963 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 7964 7965 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 7966 7967 std::vector<Constant*> CV(4, CI); 7968 Constant *C = ConstantVector::get(CV); 7969 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7970 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7971 PseudoSourceValue::getConstantPool(), 0, 7972 false, false, 16); 7973 7974 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 7975 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op); 7976 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 7977 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 7978 } 7979 if (VT == MVT::v16i8) { 7980 // a = a << 5; 7981 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7982 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 7983 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 7984 7985 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 7986 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 7987 7988 std::vector<Constant*> CVM1(16, CM1); 7989 std::vector<Constant*> CVM2(16, CM2); 7990 Constant *C = ConstantVector::get(CVM1); 7991 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7992 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7993 PseudoSourceValue::getConstantPool(), 0, 7994 false, false, 16); 7995 7996 // r = pblendv(r, psllw(r & (char16)15, 4), a); 7997 M = DAG.getNode(ISD::AND, dl, VT, R, M); 7998 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7999 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8000 DAG.getConstant(4, MVT::i32)); 8001 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8002 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8003 R, M, Op); 8004 // a += a 8005 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8006 8007 C = ConstantVector::get(CVM2); 8008 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8009 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8010 PseudoSourceValue::getConstantPool(), 0, false, false, 16); 8011 8012 // r = pblendv(r, psllw(r & (char16)63, 2), a); 8013 M = DAG.getNode(ISD::AND, dl, VT, R, M); 8014 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8015 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 8016 DAG.getConstant(2, MVT::i32)); 8017 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8018 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8019 R, M, Op); 8020 // a += a 8021 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 8022 8023 // return pblendv(r, r+r, a); 8024 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8025 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 8026 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 8027 return R; 8028 } 8029 return SDValue(); 8030} 8031 8032SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 8033 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 8034 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 8035 // looks for this combo and may remove the "setcc" instruction if the "setcc" 8036 // has only one use. 8037 SDNode *N = Op.getNode(); 8038 SDValue LHS = N->getOperand(0); 8039 SDValue RHS = N->getOperand(1); 8040 unsigned BaseOp = 0; 8041 unsigned Cond = 0; 8042 DebugLoc dl = Op.getDebugLoc(); 8043 8044 switch (Op.getOpcode()) { 8045 default: llvm_unreachable("Unknown ovf instruction!"); 8046 case ISD::SADDO: 8047 // A subtract of one will be selected as a INC. Note that INC doesn't 8048 // set CF, so we can't do this for UADDO. 8049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 8050 if (C->getAPIntValue() == 1) { 8051 BaseOp = X86ISD::INC; 8052 Cond = X86::COND_O; 8053 break; 8054 } 8055 BaseOp = X86ISD::ADD; 8056 Cond = X86::COND_O; 8057 break; 8058 case ISD::UADDO: 8059 BaseOp = X86ISD::ADD; 8060 Cond = X86::COND_B; 8061 break; 8062 case ISD::SSUBO: 8063 // A subtract of one will be selected as a DEC. Note that DEC doesn't 8064 // set CF, so we can't do this for USUBO. 8065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 8066 if (C->getAPIntValue() == 1) { 8067 BaseOp = X86ISD::DEC; 8068 Cond = X86::COND_O; 8069 break; 8070 } 8071 BaseOp = X86ISD::SUB; 8072 Cond = X86::COND_O; 8073 break; 8074 case ISD::USUBO: 8075 BaseOp = X86ISD::SUB; 8076 Cond = X86::COND_B; 8077 break; 8078 case ISD::SMULO: 8079 BaseOp = X86ISD::SMUL; 8080 Cond = X86::COND_O; 8081 break; 8082 case ISD::UMULO: 8083 BaseOp = X86ISD::UMUL; 8084 Cond = X86::COND_B; 8085 break; 8086 } 8087 8088 // Also sets EFLAGS. 8089 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 8090 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 8091 8092 SDValue SetCC = 8093 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 8094 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 8095 8096 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 8097 return Sum; 8098} 8099 8100SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 8101 DebugLoc dl = Op.getDebugLoc(); 8102 8103 if (!Subtarget->hasSSE2()) { 8104 SDValue Chain = Op.getOperand(0); 8105 SDValue Zero = DAG.getConstant(0, 8106 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8107 SDValue Ops[] = { 8108 DAG.getRegister(X86::ESP, MVT::i32), // Base 8109 DAG.getTargetConstant(1, MVT::i8), // Scale 8110 DAG.getRegister(0, MVT::i32), // Index 8111 DAG.getTargetConstant(0, MVT::i32), // Disp 8112 DAG.getRegister(0, MVT::i32), // Segment. 8113 Zero, 8114 Chain 8115 }; 8116 SDNode *Res = 8117 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 8118 array_lengthof(Ops)); 8119 return SDValue(Res, 0); 8120 } 8121 8122 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 8123 if (!isDev) 8124 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 8125 8126 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 8127 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 8128 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 8129 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 8130 8131 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 8132 if (!Op1 && !Op2 && !Op3 && Op4) 8133 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 8134 8135 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 8136 if (Op1 && !Op2 && !Op3 && !Op4) 8137 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 8138 8139 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 8140 // (MFENCE)>; 8141 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 8142} 8143 8144SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 8145 EVT T = Op.getValueType(); 8146 DebugLoc dl = Op.getDebugLoc(); 8147 unsigned Reg = 0; 8148 unsigned size = 0; 8149 switch(T.getSimpleVT().SimpleTy) { 8150 default: 8151 assert(false && "Invalid value type!"); 8152 case MVT::i8: Reg = X86::AL; size = 1; break; 8153 case MVT::i16: Reg = X86::AX; size = 2; break; 8154 case MVT::i32: Reg = X86::EAX; size = 4; break; 8155 case MVT::i64: 8156 assert(Subtarget->is64Bit() && "Node not type legal!"); 8157 Reg = X86::RAX; size = 8; 8158 break; 8159 } 8160 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 8161 Op.getOperand(2), SDValue()); 8162 SDValue Ops[] = { cpIn.getValue(0), 8163 Op.getOperand(1), 8164 Op.getOperand(3), 8165 DAG.getTargetConstant(size, MVT::i8), 8166 cpIn.getValue(1) }; 8167 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8168 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 8169 SDValue cpOut = 8170 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 8171 return cpOut; 8172} 8173 8174SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 8175 SelectionDAG &DAG) const { 8176 assert(Subtarget->is64Bit() && "Result not type legalized?"); 8177 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8178 SDValue TheChain = Op.getOperand(0); 8179 DebugLoc dl = Op.getDebugLoc(); 8180 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8181 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 8182 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 8183 rax.getValue(2)); 8184 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 8185 DAG.getConstant(32, MVT::i8)); 8186 SDValue Ops[] = { 8187 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 8188 rdx.getValue(1) 8189 }; 8190 return DAG.getMergeValues(Ops, 2, dl); 8191} 8192 8193SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op, 8194 SelectionDAG &DAG) const { 8195 EVT SrcVT = Op.getOperand(0).getValueType(); 8196 EVT DstVT = Op.getValueType(); 8197 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && 8198 Subtarget->hasMMX() && !DisableMMX) && 8199 "Unexpected custom BIT_CONVERT"); 8200 assert((DstVT == MVT::i64 || 8201 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 8202 "Unexpected custom BIT_CONVERT"); 8203 // i64 <=> MMX conversions are Legal. 8204 if (SrcVT==MVT::i64 && DstVT.isVector()) 8205 return Op; 8206 if (DstVT==MVT::i64 && SrcVT.isVector()) 8207 return Op; 8208 // MMX <=> MMX conversions are Legal. 8209 if (SrcVT.isVector() && DstVT.isVector()) 8210 return Op; 8211 // All other conversions need to be expanded. 8212 return SDValue(); 8213} 8214SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 8215 SDNode *Node = Op.getNode(); 8216 DebugLoc dl = Node->getDebugLoc(); 8217 EVT T = Node->getValueType(0); 8218 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 8219 DAG.getConstant(0, T), Node->getOperand(2)); 8220 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 8221 cast<AtomicSDNode>(Node)->getMemoryVT(), 8222 Node->getOperand(0), 8223 Node->getOperand(1), negOp, 8224 cast<AtomicSDNode>(Node)->getSrcValue(), 8225 cast<AtomicSDNode>(Node)->getAlignment()); 8226} 8227 8228/// LowerOperation - Provide custom lowering hooks for some operations. 8229/// 8230SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 8231 switch (Op.getOpcode()) { 8232 default: llvm_unreachable("Should not custom lower this!"); 8233 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 8234 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 8235 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 8236 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 8237 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 8238 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 8239 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 8240 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 8241 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 8242 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 8243 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 8244 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 8245 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 8246 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 8247 case ISD::SHL_PARTS: 8248 case ISD::SRA_PARTS: 8249 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 8250 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 8251 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 8252 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 8253 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 8254 case ISD::FABS: return LowerFABS(Op, DAG); 8255 case ISD::FNEG: return LowerFNEG(Op, DAG); 8256 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 8257 case ISD::SETCC: return LowerSETCC(Op, DAG); 8258 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 8259 case ISD::SELECT: return LowerSELECT(Op, DAG); 8260 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 8261 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 8262 case ISD::VASTART: return LowerVASTART(Op, DAG); 8263 case ISD::VAARG: return LowerVAARG(Op, DAG); 8264 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 8265 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 8266 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 8267 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 8268 case ISD::FRAME_TO_ARGS_OFFSET: 8269 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 8270 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 8271 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 8272 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 8273 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 8274 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 8275 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 8276 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 8277 case ISD::SHL: return LowerSHL(Op, DAG); 8278 case ISD::SADDO: 8279 case ISD::UADDO: 8280 case ISD::SSUBO: 8281 case ISD::USUBO: 8282 case ISD::SMULO: 8283 case ISD::UMULO: return LowerXALUO(Op, DAG); 8284 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 8285 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 8286 } 8287} 8288 8289void X86TargetLowering:: 8290ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 8291 SelectionDAG &DAG, unsigned NewOp) const { 8292 EVT T = Node->getValueType(0); 8293 DebugLoc dl = Node->getDebugLoc(); 8294 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 8295 8296 SDValue Chain = Node->getOperand(0); 8297 SDValue In1 = Node->getOperand(1); 8298 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8299 Node->getOperand(2), DAG.getIntPtrConstant(0)); 8300 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8301 Node->getOperand(2), DAG.getIntPtrConstant(1)); 8302 SDValue Ops[] = { Chain, In1, In2L, In2H }; 8303 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 8304 SDValue Result = 8305 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 8306 cast<MemSDNode>(Node)->getMemOperand()); 8307 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 8308 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8309 Results.push_back(Result.getValue(2)); 8310} 8311 8312/// ReplaceNodeResults - Replace a node with an illegal result type 8313/// with a new node built out of custom code. 8314void X86TargetLowering::ReplaceNodeResults(SDNode *N, 8315 SmallVectorImpl<SDValue>&Results, 8316 SelectionDAG &DAG) const { 8317 DebugLoc dl = N->getDebugLoc(); 8318 switch (N->getOpcode()) { 8319 default: 8320 assert(false && "Do not know how to custom type legalize this operation!"); 8321 return; 8322 case ISD::FP_TO_SINT: { 8323 std::pair<SDValue,SDValue> Vals = 8324 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 8325 SDValue FIST = Vals.first, StackSlot = Vals.second; 8326 if (FIST.getNode() != 0) { 8327 EVT VT = N->getValueType(0); 8328 // Return a load from the stack slot. 8329 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 8330 false, false, 0)); 8331 } 8332 return; 8333 } 8334 case ISD::READCYCLECOUNTER: { 8335 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8336 SDValue TheChain = N->getOperand(0); 8337 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8338 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 8339 rd.getValue(1)); 8340 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 8341 eax.getValue(2)); 8342 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 8343 SDValue Ops[] = { eax, edx }; 8344 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 8345 Results.push_back(edx.getValue(1)); 8346 return; 8347 } 8348 case ISD::ATOMIC_CMP_SWAP: { 8349 EVT T = N->getValueType(0); 8350 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 8351 SDValue cpInL, cpInH; 8352 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8353 DAG.getConstant(0, MVT::i32)); 8354 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8355 DAG.getConstant(1, MVT::i32)); 8356 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 8357 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 8358 cpInL.getValue(1)); 8359 SDValue swapInL, swapInH; 8360 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8361 DAG.getConstant(0, MVT::i32)); 8362 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8363 DAG.getConstant(1, MVT::i32)); 8364 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 8365 cpInH.getValue(1)); 8366 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 8367 swapInL.getValue(1)); 8368 SDValue Ops[] = { swapInH.getValue(0), 8369 N->getOperand(1), 8370 swapInH.getValue(1) }; 8371 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8372 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 8373 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 8374 MVT::i32, Result.getValue(1)); 8375 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 8376 MVT::i32, cpOutL.getValue(2)); 8377 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 8378 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8379 Results.push_back(cpOutH.getValue(1)); 8380 return; 8381 } 8382 case ISD::ATOMIC_LOAD_ADD: 8383 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 8384 return; 8385 case ISD::ATOMIC_LOAD_AND: 8386 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 8387 return; 8388 case ISD::ATOMIC_LOAD_NAND: 8389 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 8390 return; 8391 case ISD::ATOMIC_LOAD_OR: 8392 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 8393 return; 8394 case ISD::ATOMIC_LOAD_SUB: 8395 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 8396 return; 8397 case ISD::ATOMIC_LOAD_XOR: 8398 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 8399 return; 8400 case ISD::ATOMIC_SWAP: 8401 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 8402 return; 8403 } 8404} 8405 8406const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 8407 switch (Opcode) { 8408 default: return NULL; 8409 case X86ISD::BSF: return "X86ISD::BSF"; 8410 case X86ISD::BSR: return "X86ISD::BSR"; 8411 case X86ISD::SHLD: return "X86ISD::SHLD"; 8412 case X86ISD::SHRD: return "X86ISD::SHRD"; 8413 case X86ISD::FAND: return "X86ISD::FAND"; 8414 case X86ISD::FOR: return "X86ISD::FOR"; 8415 case X86ISD::FXOR: return "X86ISD::FXOR"; 8416 case X86ISD::FSRL: return "X86ISD::FSRL"; 8417 case X86ISD::FILD: return "X86ISD::FILD"; 8418 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 8419 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 8420 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 8421 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 8422 case X86ISD::FLD: return "X86ISD::FLD"; 8423 case X86ISD::FST: return "X86ISD::FST"; 8424 case X86ISD::CALL: return "X86ISD::CALL"; 8425 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 8426 case X86ISD::BT: return "X86ISD::BT"; 8427 case X86ISD::CMP: return "X86ISD::CMP"; 8428 case X86ISD::COMI: return "X86ISD::COMI"; 8429 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 8430 case X86ISD::SETCC: return "X86ISD::SETCC"; 8431 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 8432 case X86ISD::CMOV: return "X86ISD::CMOV"; 8433 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 8434 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 8435 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 8436 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 8437 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 8438 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 8439 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 8440 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 8441 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 8442 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 8443 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 8444 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 8445 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 8446 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 8447 case X86ISD::FMAX: return "X86ISD::FMAX"; 8448 case X86ISD::FMIN: return "X86ISD::FMIN"; 8449 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 8450 case X86ISD::FRCP: return "X86ISD::FRCP"; 8451 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 8452 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 8453 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 8454 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 8455 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 8456 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 8457 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 8458 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 8459 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 8460 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 8461 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 8462 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 8463 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 8464 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 8465 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 8466 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 8467 case X86ISD::VSHL: return "X86ISD::VSHL"; 8468 case X86ISD::VSRL: return "X86ISD::VSRL"; 8469 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 8470 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 8471 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 8472 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 8473 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 8474 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 8475 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 8476 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 8477 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 8478 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 8479 case X86ISD::ADD: return "X86ISD::ADD"; 8480 case X86ISD::SUB: return "X86ISD::SUB"; 8481 case X86ISD::SMUL: return "X86ISD::SMUL"; 8482 case X86ISD::UMUL: return "X86ISD::UMUL"; 8483 case X86ISD::INC: return "X86ISD::INC"; 8484 case X86ISD::DEC: return "X86ISD::DEC"; 8485 case X86ISD::OR: return "X86ISD::OR"; 8486 case X86ISD::XOR: return "X86ISD::XOR"; 8487 case X86ISD::AND: return "X86ISD::AND"; 8488 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 8489 case X86ISD::PTEST: return "X86ISD::PTEST"; 8490 case X86ISD::TESTP: return "X86ISD::TESTP"; 8491 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 8492 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 8493 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 8494 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 8495 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 8496 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 8497 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 8498 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 8499 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 8500 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 8501 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 8502 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 8503 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 8504 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 8505 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 8506 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 8507 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 8508 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 8509 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 8510 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 8511 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 8512 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 8513 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 8514 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 8515 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 8516 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 8517 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 8518 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 8519 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 8520 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 8521 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 8522 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 8523 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 8524 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 8525 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 8526 } 8527} 8528 8529// isLegalAddressingMode - Return true if the addressing mode represented 8530// by AM is legal for this target, for a load/store of the specified type. 8531bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 8532 const Type *Ty) const { 8533 // X86 supports extremely general addressing modes. 8534 CodeModel::Model M = getTargetMachine().getCodeModel(); 8535 Reloc::Model R = getTargetMachine().getRelocationModel(); 8536 8537 // X86 allows a sign-extended 32-bit immediate field as a displacement. 8538 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 8539 return false; 8540 8541 if (AM.BaseGV) { 8542 unsigned GVFlags = 8543 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 8544 8545 // If a reference to this global requires an extra load, we can't fold it. 8546 if (isGlobalStubReference(GVFlags)) 8547 return false; 8548 8549 // If BaseGV requires a register for the PIC base, we cannot also have a 8550 // BaseReg specified. 8551 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 8552 return false; 8553 8554 // If lower 4G is not available, then we must use rip-relative addressing. 8555 if ((M != CodeModel::Small || R != Reloc::Static) && 8556 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 8557 return false; 8558 } 8559 8560 switch (AM.Scale) { 8561 case 0: 8562 case 1: 8563 case 2: 8564 case 4: 8565 case 8: 8566 // These scales always work. 8567 break; 8568 case 3: 8569 case 5: 8570 case 9: 8571 // These scales are formed with basereg+scalereg. Only accept if there is 8572 // no basereg yet. 8573 if (AM.HasBaseReg) 8574 return false; 8575 break; 8576 default: // Other stuff never works. 8577 return false; 8578 } 8579 8580 return true; 8581} 8582 8583 8584bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 8585 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 8586 return false; 8587 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 8588 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 8589 if (NumBits1 <= NumBits2) 8590 return false; 8591 return true; 8592} 8593 8594bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 8595 if (!VT1.isInteger() || !VT2.isInteger()) 8596 return false; 8597 unsigned NumBits1 = VT1.getSizeInBits(); 8598 unsigned NumBits2 = VT2.getSizeInBits(); 8599 if (NumBits1 <= NumBits2) 8600 return false; 8601 return true; 8602} 8603 8604bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 8605 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 8606 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 8607} 8608 8609bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 8610 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 8611 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 8612} 8613 8614bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 8615 // i16 instructions are longer (0x66 prefix) and potentially slower. 8616 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 8617} 8618 8619/// isShuffleMaskLegal - Targets can use this to indicate that they only 8620/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 8621/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 8622/// are assumed to be legal. 8623bool 8624X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 8625 EVT VT) const { 8626 // Very little shuffling can be done for 64-bit vectors right now. 8627 if (VT.getSizeInBits() == 64) 8628 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 8629 8630 // FIXME: pshufb, blends, shifts. 8631 return (VT.getVectorNumElements() == 2 || 8632 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 8633 isMOVLMask(M, VT) || 8634 isSHUFPMask(M, VT) || 8635 isPSHUFDMask(M, VT) || 8636 isPSHUFHWMask(M, VT) || 8637 isPSHUFLWMask(M, VT) || 8638 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 8639 isUNPCKLMask(M, VT) || 8640 isUNPCKHMask(M, VT) || 8641 isUNPCKL_v_undef_Mask(M, VT) || 8642 isUNPCKH_v_undef_Mask(M, VT)); 8643} 8644 8645bool 8646X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 8647 EVT VT) const { 8648 unsigned NumElts = VT.getVectorNumElements(); 8649 // FIXME: This collection of masks seems suspect. 8650 if (NumElts == 2) 8651 return true; 8652 if (NumElts == 4 && VT.getSizeInBits() == 128) { 8653 return (isMOVLMask(Mask, VT) || 8654 isCommutedMOVLMask(Mask, VT, true) || 8655 isSHUFPMask(Mask, VT) || 8656 isCommutedSHUFPMask(Mask, VT)); 8657 } 8658 return false; 8659} 8660 8661//===----------------------------------------------------------------------===// 8662// X86 Scheduler Hooks 8663//===----------------------------------------------------------------------===// 8664 8665// private utility function 8666MachineBasicBlock * 8667X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 8668 MachineBasicBlock *MBB, 8669 unsigned regOpc, 8670 unsigned immOpc, 8671 unsigned LoadOpc, 8672 unsigned CXchgOpc, 8673 unsigned notOpc, 8674 unsigned EAXreg, 8675 TargetRegisterClass *RC, 8676 bool invSrc) const { 8677 // For the atomic bitwise operator, we generate 8678 // thisMBB: 8679 // newMBB: 8680 // ld t1 = [bitinstr.addr] 8681 // op t2 = t1, [bitinstr.val] 8682 // mov EAX = t1 8683 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8684 // bz newMBB 8685 // fallthrough -->nextMBB 8686 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8687 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8688 MachineFunction::iterator MBBIter = MBB; 8689 ++MBBIter; 8690 8691 /// First build the CFG 8692 MachineFunction *F = MBB->getParent(); 8693 MachineBasicBlock *thisMBB = MBB; 8694 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8695 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8696 F->insert(MBBIter, newMBB); 8697 F->insert(MBBIter, nextMBB); 8698 8699 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8700 nextMBB->splice(nextMBB->begin(), thisMBB, 8701 llvm::next(MachineBasicBlock::iterator(bInstr)), 8702 thisMBB->end()); 8703 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8704 8705 // Update thisMBB to fall through to newMBB 8706 thisMBB->addSuccessor(newMBB); 8707 8708 // newMBB jumps to itself and fall through to nextMBB 8709 newMBB->addSuccessor(nextMBB); 8710 newMBB->addSuccessor(newMBB); 8711 8712 // Insert instructions into newMBB based on incoming instruction 8713 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8714 "unexpected number of operands"); 8715 DebugLoc dl = bInstr->getDebugLoc(); 8716 MachineOperand& destOper = bInstr->getOperand(0); 8717 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8718 int numArgs = bInstr->getNumOperands() - 1; 8719 for (int i=0; i < numArgs; ++i) 8720 argOpers[i] = &bInstr->getOperand(i+1); 8721 8722 // x86 address has 4 operands: base, index, scale, and displacement 8723 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8724 int valArgIndx = lastAddrIndx + 1; 8725 8726 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8727 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 8728 for (int i=0; i <= lastAddrIndx; ++i) 8729 (*MIB).addOperand(*argOpers[i]); 8730 8731 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 8732 if (invSrc) { 8733 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 8734 } 8735 else 8736 tt = t1; 8737 8738 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8739 assert((argOpers[valArgIndx]->isReg() || 8740 argOpers[valArgIndx]->isImm()) && 8741 "invalid operand"); 8742 if (argOpers[valArgIndx]->isReg()) 8743 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 8744 else 8745 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 8746 MIB.addReg(tt); 8747 (*MIB).addOperand(*argOpers[valArgIndx]); 8748 8749 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 8750 MIB.addReg(t1); 8751 8752 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 8753 for (int i=0; i <= lastAddrIndx; ++i) 8754 (*MIB).addOperand(*argOpers[i]); 8755 MIB.addReg(t2); 8756 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8757 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8758 bInstr->memoperands_end()); 8759 8760 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 8761 MIB.addReg(EAXreg); 8762 8763 // insert branch 8764 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8765 8766 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8767 return nextMBB; 8768} 8769 8770// private utility function: 64 bit atomics on 32 bit host. 8771MachineBasicBlock * 8772X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8773 MachineBasicBlock *MBB, 8774 unsigned regOpcL, 8775 unsigned regOpcH, 8776 unsigned immOpcL, 8777 unsigned immOpcH, 8778 bool invSrc) const { 8779 // For the atomic bitwise operator, we generate 8780 // thisMBB (instructions are in pairs, except cmpxchg8b) 8781 // ld t1,t2 = [bitinstr.addr] 8782 // newMBB: 8783 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8784 // op t5, t6 <- out1, out2, [bitinstr.val] 8785 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8786 // mov ECX, EBX <- t5, t6 8787 // mov EAX, EDX <- t1, t2 8788 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8789 // mov t3, t4 <- EAX, EDX 8790 // bz newMBB 8791 // result in out1, out2 8792 // fallthrough -->nextMBB 8793 8794 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8795 const unsigned LoadOpc = X86::MOV32rm; 8796 const unsigned NotOpc = X86::NOT32r; 8797 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8798 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8799 MachineFunction::iterator MBBIter = MBB; 8800 ++MBBIter; 8801 8802 /// First build the CFG 8803 MachineFunction *F = MBB->getParent(); 8804 MachineBasicBlock *thisMBB = MBB; 8805 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8806 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8807 F->insert(MBBIter, newMBB); 8808 F->insert(MBBIter, nextMBB); 8809 8810 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8811 nextMBB->splice(nextMBB->begin(), thisMBB, 8812 llvm::next(MachineBasicBlock::iterator(bInstr)), 8813 thisMBB->end()); 8814 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8815 8816 // Update thisMBB to fall through to newMBB 8817 thisMBB->addSuccessor(newMBB); 8818 8819 // newMBB jumps to itself and fall through to nextMBB 8820 newMBB->addSuccessor(nextMBB); 8821 newMBB->addSuccessor(newMBB); 8822 8823 DebugLoc dl = bInstr->getDebugLoc(); 8824 // Insert instructions into newMBB based on incoming instruction 8825 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8826 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 8827 "unexpected number of operands"); 8828 MachineOperand& dest1Oper = bInstr->getOperand(0); 8829 MachineOperand& dest2Oper = bInstr->getOperand(1); 8830 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8831 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 8832 argOpers[i] = &bInstr->getOperand(i+2); 8833 8834 // We use some of the operands multiple times, so conservatively just 8835 // clear any kill flags that might be present. 8836 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 8837 argOpers[i]->setIsKill(false); 8838 } 8839 8840 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8841 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8842 8843 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8844 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8845 for (int i=0; i <= lastAddrIndx; ++i) 8846 (*MIB).addOperand(*argOpers[i]); 8847 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8848 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8849 // add 4 to displacement. 8850 for (int i=0; i <= lastAddrIndx-2; ++i) 8851 (*MIB).addOperand(*argOpers[i]); 8852 MachineOperand newOp3 = *(argOpers[3]); 8853 if (newOp3.isImm()) 8854 newOp3.setImm(newOp3.getImm()+4); 8855 else 8856 newOp3.setOffset(newOp3.getOffset()+4); 8857 (*MIB).addOperand(newOp3); 8858 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8859 8860 // t3/4 are defined later, at the bottom of the loop 8861 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8862 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8863 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8864 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8865 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8866 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8867 8868 // The subsequent operations should be using the destination registers of 8869 //the PHI instructions. 8870 if (invSrc) { 8871 t1 = F->getRegInfo().createVirtualRegister(RC); 8872 t2 = F->getRegInfo().createVirtualRegister(RC); 8873 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8874 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8875 } else { 8876 t1 = dest1Oper.getReg(); 8877 t2 = dest2Oper.getReg(); 8878 } 8879 8880 int valArgIndx = lastAddrIndx + 1; 8881 assert((argOpers[valArgIndx]->isReg() || 8882 argOpers[valArgIndx]->isImm()) && 8883 "invalid operand"); 8884 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8885 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8886 if (argOpers[valArgIndx]->isReg()) 8887 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8888 else 8889 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8890 if (regOpcL != X86::MOV32rr) 8891 MIB.addReg(t1); 8892 (*MIB).addOperand(*argOpers[valArgIndx]); 8893 assert(argOpers[valArgIndx + 1]->isReg() == 8894 argOpers[valArgIndx]->isReg()); 8895 assert(argOpers[valArgIndx + 1]->isImm() == 8896 argOpers[valArgIndx]->isImm()); 8897 if (argOpers[valArgIndx + 1]->isReg()) 8898 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8899 else 8900 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8901 if (regOpcH != X86::MOV32rr) 8902 MIB.addReg(t2); 8903 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8904 8905 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 8906 MIB.addReg(t1); 8907 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 8908 MIB.addReg(t2); 8909 8910 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 8911 MIB.addReg(t5); 8912 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 8913 MIB.addReg(t6); 8914 8915 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8916 for (int i=0; i <= lastAddrIndx; ++i) 8917 (*MIB).addOperand(*argOpers[i]); 8918 8919 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8920 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8921 bInstr->memoperands_end()); 8922 8923 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 8924 MIB.addReg(X86::EAX); 8925 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 8926 MIB.addReg(X86::EDX); 8927 8928 // insert branch 8929 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8930 8931 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8932 return nextMBB; 8933} 8934 8935// private utility function 8936MachineBasicBlock * 8937X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8938 MachineBasicBlock *MBB, 8939 unsigned cmovOpc) const { 8940 // For the atomic min/max operator, we generate 8941 // thisMBB: 8942 // newMBB: 8943 // ld t1 = [min/max.addr] 8944 // mov t2 = [min/max.val] 8945 // cmp t1, t2 8946 // cmov[cond] t2 = t1 8947 // mov EAX = t1 8948 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8949 // bz newMBB 8950 // fallthrough -->nextMBB 8951 // 8952 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8953 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8954 MachineFunction::iterator MBBIter = MBB; 8955 ++MBBIter; 8956 8957 /// First build the CFG 8958 MachineFunction *F = MBB->getParent(); 8959 MachineBasicBlock *thisMBB = MBB; 8960 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8961 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8962 F->insert(MBBIter, newMBB); 8963 F->insert(MBBIter, nextMBB); 8964 8965 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8966 nextMBB->splice(nextMBB->begin(), thisMBB, 8967 llvm::next(MachineBasicBlock::iterator(mInstr)), 8968 thisMBB->end()); 8969 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8970 8971 // Update thisMBB to fall through to newMBB 8972 thisMBB->addSuccessor(newMBB); 8973 8974 // newMBB jumps to newMBB and fall through to nextMBB 8975 newMBB->addSuccessor(nextMBB); 8976 newMBB->addSuccessor(newMBB); 8977 8978 DebugLoc dl = mInstr->getDebugLoc(); 8979 // Insert instructions into newMBB based on incoming instruction 8980 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8981 "unexpected number of operands"); 8982 MachineOperand& destOper = mInstr->getOperand(0); 8983 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8984 int numArgs = mInstr->getNumOperands() - 1; 8985 for (int i=0; i < numArgs; ++i) 8986 argOpers[i] = &mInstr->getOperand(i+1); 8987 8988 // x86 address has 4 operands: base, index, scale, and displacement 8989 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8990 int valArgIndx = lastAddrIndx + 1; 8991 8992 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8993 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8994 for (int i=0; i <= lastAddrIndx; ++i) 8995 (*MIB).addOperand(*argOpers[i]); 8996 8997 // We only support register and immediate values 8998 assert((argOpers[valArgIndx]->isReg() || 8999 argOpers[valArgIndx]->isImm()) && 9000 "invalid operand"); 9001 9002 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9003 if (argOpers[valArgIndx]->isReg()) 9004 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 9005 else 9006 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 9007 (*MIB).addOperand(*argOpers[valArgIndx]); 9008 9009 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 9010 MIB.addReg(t1); 9011 9012 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 9013 MIB.addReg(t1); 9014 MIB.addReg(t2); 9015 9016 // Generate movc 9017 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 9018 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 9019 MIB.addReg(t2); 9020 MIB.addReg(t1); 9021 9022 // Cmp and exchange if none has modified the memory location 9023 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 9024 for (int i=0; i <= lastAddrIndx; ++i) 9025 (*MIB).addOperand(*argOpers[i]); 9026 MIB.addReg(t3); 9027 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 9028 (*MIB).setMemRefs(mInstr->memoperands_begin(), 9029 mInstr->memoperands_end()); 9030 9031 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 9032 MIB.addReg(X86::EAX); 9033 9034 // insert branch 9035 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 9036 9037 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 9038 return nextMBB; 9039} 9040 9041// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 9042// or XMM0_V32I8 in AVX all of this code can be replaced with that 9043// in the .td file. 9044MachineBasicBlock * 9045X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 9046 unsigned numArgs, bool memArg) const { 9047 9048 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 9049 "Target must have SSE4.2 or AVX features enabled"); 9050 9051 DebugLoc dl = MI->getDebugLoc(); 9052 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9053 9054 unsigned Opc; 9055 9056 if (!Subtarget->hasAVX()) { 9057 if (memArg) 9058 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 9059 else 9060 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 9061 } else { 9062 if (memArg) 9063 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 9064 else 9065 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 9066 } 9067 9068 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 9069 9070 for (unsigned i = 0; i < numArgs; ++i) { 9071 MachineOperand &Op = MI->getOperand(i+1); 9072 9073 if (!(Op.isReg() && Op.isImplicit())) 9074 MIB.addOperand(Op); 9075 } 9076 9077 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 9078 .addReg(X86::XMM0); 9079 9080 MI->eraseFromParent(); 9081 9082 return BB; 9083} 9084 9085MachineBasicBlock * 9086X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 9087 MachineInstr *MI, 9088 MachineBasicBlock *MBB) const { 9089 // Emit code to save XMM registers to the stack. The ABI says that the 9090 // number of registers to save is given in %al, so it's theoretically 9091 // possible to do an indirect jump trick to avoid saving all of them, 9092 // however this code takes a simpler approach and just executes all 9093 // of the stores if %al is non-zero. It's less code, and it's probably 9094 // easier on the hardware branch predictor, and stores aren't all that 9095 // expensive anyway. 9096 9097 // Create the new basic blocks. One block contains all the XMM stores, 9098 // and one block is the final destination regardless of whether any 9099 // stores were performed. 9100 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 9101 MachineFunction *F = MBB->getParent(); 9102 MachineFunction::iterator MBBIter = MBB; 9103 ++MBBIter; 9104 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 9105 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 9106 F->insert(MBBIter, XMMSaveMBB); 9107 F->insert(MBBIter, EndMBB); 9108 9109 // Transfer the remainder of MBB and its successor edges to EndMBB. 9110 EndMBB->splice(EndMBB->begin(), MBB, 9111 llvm::next(MachineBasicBlock::iterator(MI)), 9112 MBB->end()); 9113 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 9114 9115 // The original block will now fall through to the XMM save block. 9116 MBB->addSuccessor(XMMSaveMBB); 9117 // The XMMSaveMBB will fall through to the end block. 9118 XMMSaveMBB->addSuccessor(EndMBB); 9119 9120 // Now add the instructions. 9121 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9122 DebugLoc DL = MI->getDebugLoc(); 9123 9124 unsigned CountReg = MI->getOperand(0).getReg(); 9125 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 9126 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 9127 9128 if (!Subtarget->isTargetWin64()) { 9129 // If %al is 0, branch around the XMM save block. 9130 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 9131 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 9132 MBB->addSuccessor(EndMBB); 9133 } 9134 9135 // In the XMM save block, save all the XMM argument registers. 9136 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 9137 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 9138 MachineMemOperand *MMO = 9139 F->getMachineMemOperand( 9140 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 9141 MachineMemOperand::MOStore, Offset, 9142 /*Size=*/16, /*Align=*/16); 9143 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 9144 .addFrameIndex(RegSaveFrameIndex) 9145 .addImm(/*Scale=*/1) 9146 .addReg(/*IndexReg=*/0) 9147 .addImm(/*Disp=*/Offset) 9148 .addReg(/*Segment=*/0) 9149 .addReg(MI->getOperand(i).getReg()) 9150 .addMemOperand(MMO); 9151 } 9152 9153 MI->eraseFromParent(); // The pseudo instruction is gone now. 9154 9155 return EndMBB; 9156} 9157 9158MachineBasicBlock * 9159X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 9160 MachineBasicBlock *BB) const { 9161 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9162 DebugLoc DL = MI->getDebugLoc(); 9163 9164 // To "insert" a SELECT_CC instruction, we actually have to insert the 9165 // diamond control-flow pattern. The incoming instruction knows the 9166 // destination vreg to set, the condition code register to branch on, the 9167 // true/false values to select between, and a branch opcode to use. 9168 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 9169 MachineFunction::iterator It = BB; 9170 ++It; 9171 9172 // thisMBB: 9173 // ... 9174 // TrueVal = ... 9175 // cmpTY ccX, r1, r2 9176 // bCC copy1MBB 9177 // fallthrough --> copy0MBB 9178 MachineBasicBlock *thisMBB = BB; 9179 MachineFunction *F = BB->getParent(); 9180 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 9181 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 9182 F->insert(It, copy0MBB); 9183 F->insert(It, sinkMBB); 9184 9185 // If the EFLAGS register isn't dead in the terminator, then claim that it's 9186 // live into the sink and copy blocks. 9187 const MachineFunction *MF = BB->getParent(); 9188 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 9189 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 9190 9191 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 9192 const MachineOperand &MO = MI->getOperand(I); 9193 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 9194 unsigned Reg = MO.getReg(); 9195 if (Reg != X86::EFLAGS) continue; 9196 copy0MBB->addLiveIn(Reg); 9197 sinkMBB->addLiveIn(Reg); 9198 } 9199 9200 // Transfer the remainder of BB and its successor edges to sinkMBB. 9201 sinkMBB->splice(sinkMBB->begin(), BB, 9202 llvm::next(MachineBasicBlock::iterator(MI)), 9203 BB->end()); 9204 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 9205 9206 // Add the true and fallthrough blocks as its successors. 9207 BB->addSuccessor(copy0MBB); 9208 BB->addSuccessor(sinkMBB); 9209 9210 // Create the conditional branch instruction. 9211 unsigned Opc = 9212 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 9213 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 9214 9215 // copy0MBB: 9216 // %FalseValue = ... 9217 // # fallthrough to sinkMBB 9218 copy0MBB->addSuccessor(sinkMBB); 9219 9220 // sinkMBB: 9221 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 9222 // ... 9223 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 9224 TII->get(X86::PHI), MI->getOperand(0).getReg()) 9225 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 9226 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 9227 9228 MI->eraseFromParent(); // The pseudo instruction is gone now. 9229 return sinkMBB; 9230} 9231 9232MachineBasicBlock * 9233X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 9234 MachineBasicBlock *BB) const { 9235 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9236 DebugLoc DL = MI->getDebugLoc(); 9237 9238 // The lowering is pretty easy: we're just emitting the call to _alloca. The 9239 // non-trivial part is impdef of ESP. 9240 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 9241 // mingw-w64. 9242 9243 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 9244 .addExternalSymbol("_alloca") 9245 .addReg(X86::EAX, RegState::Implicit) 9246 .addReg(X86::ESP, RegState::Implicit) 9247 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 9248 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 9249 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 9250 9251 MI->eraseFromParent(); // The pseudo instruction is gone now. 9252 return BB; 9253} 9254 9255MachineBasicBlock * 9256X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 9257 MachineBasicBlock *BB) const { 9258 // This is pretty easy. We're taking the value that we received from 9259 // our load from the relocation, sticking it in either RDI (x86-64) 9260 // or EAX and doing an indirect call. The return value will then 9261 // be in the normal return register. 9262 const X86InstrInfo *TII 9263 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 9264 DebugLoc DL = MI->getDebugLoc(); 9265 MachineFunction *F = BB->getParent(); 9266 bool IsWin64 = Subtarget->isTargetWin64(); 9267 9268 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 9269 9270 if (Subtarget->is64Bit()) { 9271 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9272 TII->get(X86::MOV64rm), X86::RDI) 9273 .addReg(X86::RIP) 9274 .addImm(0).addReg(0) 9275 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9276 MI->getOperand(3).getTargetFlags()) 9277 .addReg(0); 9278 MIB = BuildMI(*BB, MI, DL, TII->get(IsWin64 ? X86::WINCALL64m : X86::CALL64m)); 9279 addDirectMem(MIB, X86::RDI); 9280 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 9281 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9282 TII->get(X86::MOV32rm), X86::EAX) 9283 .addReg(0) 9284 .addImm(0).addReg(0) 9285 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9286 MI->getOperand(3).getTargetFlags()) 9287 .addReg(0); 9288 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 9289 addDirectMem(MIB, X86::EAX); 9290 } else { 9291 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9292 TII->get(X86::MOV32rm), X86::EAX) 9293 .addReg(TII->getGlobalBaseReg(F)) 9294 .addImm(0).addReg(0) 9295 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9296 MI->getOperand(3).getTargetFlags()) 9297 .addReg(0); 9298 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 9299 addDirectMem(MIB, X86::EAX); 9300 } 9301 9302 MI->eraseFromParent(); // The pseudo instruction is gone now. 9303 return BB; 9304} 9305 9306MachineBasicBlock * 9307X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 9308 MachineBasicBlock *BB) const { 9309 switch (MI->getOpcode()) { 9310 default: assert(false && "Unexpected instr type to insert"); 9311 case X86::MINGW_ALLOCA: 9312 return EmitLoweredMingwAlloca(MI, BB); 9313 case X86::TLSCall_32: 9314 case X86::TLSCall_64: 9315 return EmitLoweredTLSCall(MI, BB); 9316 case X86::CMOV_GR8: 9317 case X86::CMOV_V1I64: 9318 case X86::CMOV_FR32: 9319 case X86::CMOV_FR64: 9320 case X86::CMOV_V4F32: 9321 case X86::CMOV_V2F64: 9322 case X86::CMOV_V2I64: 9323 case X86::CMOV_GR16: 9324 case X86::CMOV_GR32: 9325 case X86::CMOV_RFP32: 9326 case X86::CMOV_RFP64: 9327 case X86::CMOV_RFP80: 9328 return EmitLoweredSelect(MI, BB); 9329 9330 case X86::FP32_TO_INT16_IN_MEM: 9331 case X86::FP32_TO_INT32_IN_MEM: 9332 case X86::FP32_TO_INT64_IN_MEM: 9333 case X86::FP64_TO_INT16_IN_MEM: 9334 case X86::FP64_TO_INT32_IN_MEM: 9335 case X86::FP64_TO_INT64_IN_MEM: 9336 case X86::FP80_TO_INT16_IN_MEM: 9337 case X86::FP80_TO_INT32_IN_MEM: 9338 case X86::FP80_TO_INT64_IN_MEM: { 9339 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9340 DebugLoc DL = MI->getDebugLoc(); 9341 9342 // Change the floating point control register to use "round towards zero" 9343 // mode when truncating to an integer value. 9344 MachineFunction *F = BB->getParent(); 9345 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 9346 addFrameReference(BuildMI(*BB, MI, DL, 9347 TII->get(X86::FNSTCW16m)), CWFrameIdx); 9348 9349 // Load the old value of the high byte of the control word... 9350 unsigned OldCW = 9351 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 9352 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 9353 CWFrameIdx); 9354 9355 // Set the high part to be round to zero... 9356 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 9357 .addImm(0xC7F); 9358 9359 // Reload the modified control word now... 9360 addFrameReference(BuildMI(*BB, MI, DL, 9361 TII->get(X86::FLDCW16m)), CWFrameIdx); 9362 9363 // Restore the memory image of control word to original value 9364 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 9365 .addReg(OldCW); 9366 9367 // Get the X86 opcode to use. 9368 unsigned Opc; 9369 switch (MI->getOpcode()) { 9370 default: llvm_unreachable("illegal opcode!"); 9371 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 9372 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 9373 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 9374 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 9375 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 9376 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 9377 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 9378 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 9379 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 9380 } 9381 9382 X86AddressMode AM; 9383 MachineOperand &Op = MI->getOperand(0); 9384 if (Op.isReg()) { 9385 AM.BaseType = X86AddressMode::RegBase; 9386 AM.Base.Reg = Op.getReg(); 9387 } else { 9388 AM.BaseType = X86AddressMode::FrameIndexBase; 9389 AM.Base.FrameIndex = Op.getIndex(); 9390 } 9391 Op = MI->getOperand(1); 9392 if (Op.isImm()) 9393 AM.Scale = Op.getImm(); 9394 Op = MI->getOperand(2); 9395 if (Op.isImm()) 9396 AM.IndexReg = Op.getImm(); 9397 Op = MI->getOperand(3); 9398 if (Op.isGlobal()) { 9399 AM.GV = Op.getGlobal(); 9400 } else { 9401 AM.Disp = Op.getImm(); 9402 } 9403 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 9404 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 9405 9406 // Reload the original control word now. 9407 addFrameReference(BuildMI(*BB, MI, DL, 9408 TII->get(X86::FLDCW16m)), CWFrameIdx); 9409 9410 MI->eraseFromParent(); // The pseudo instruction is gone now. 9411 return BB; 9412 } 9413 // String/text processing lowering. 9414 case X86::PCMPISTRM128REG: 9415 case X86::VPCMPISTRM128REG: 9416 return EmitPCMP(MI, BB, 3, false /* in-mem */); 9417 case X86::PCMPISTRM128MEM: 9418 case X86::VPCMPISTRM128MEM: 9419 return EmitPCMP(MI, BB, 3, true /* in-mem */); 9420 case X86::PCMPESTRM128REG: 9421 case X86::VPCMPESTRM128REG: 9422 return EmitPCMP(MI, BB, 5, false /* in mem */); 9423 case X86::PCMPESTRM128MEM: 9424 case X86::VPCMPESTRM128MEM: 9425 return EmitPCMP(MI, BB, 5, true /* in mem */); 9426 9427 // Atomic Lowering. 9428 case X86::ATOMAND32: 9429 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 9430 X86::AND32ri, X86::MOV32rm, 9431 X86::LCMPXCHG32, 9432 X86::NOT32r, X86::EAX, 9433 X86::GR32RegisterClass); 9434 case X86::ATOMOR32: 9435 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 9436 X86::OR32ri, X86::MOV32rm, 9437 X86::LCMPXCHG32, 9438 X86::NOT32r, X86::EAX, 9439 X86::GR32RegisterClass); 9440 case X86::ATOMXOR32: 9441 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 9442 X86::XOR32ri, X86::MOV32rm, 9443 X86::LCMPXCHG32, 9444 X86::NOT32r, X86::EAX, 9445 X86::GR32RegisterClass); 9446 case X86::ATOMNAND32: 9447 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 9448 X86::AND32ri, X86::MOV32rm, 9449 X86::LCMPXCHG32, 9450 X86::NOT32r, X86::EAX, 9451 X86::GR32RegisterClass, true); 9452 case X86::ATOMMIN32: 9453 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 9454 case X86::ATOMMAX32: 9455 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 9456 case X86::ATOMUMIN32: 9457 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 9458 case X86::ATOMUMAX32: 9459 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 9460 9461 case X86::ATOMAND16: 9462 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 9463 X86::AND16ri, X86::MOV16rm, 9464 X86::LCMPXCHG16, 9465 X86::NOT16r, X86::AX, 9466 X86::GR16RegisterClass); 9467 case X86::ATOMOR16: 9468 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 9469 X86::OR16ri, X86::MOV16rm, 9470 X86::LCMPXCHG16, 9471 X86::NOT16r, X86::AX, 9472 X86::GR16RegisterClass); 9473 case X86::ATOMXOR16: 9474 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 9475 X86::XOR16ri, X86::MOV16rm, 9476 X86::LCMPXCHG16, 9477 X86::NOT16r, X86::AX, 9478 X86::GR16RegisterClass); 9479 case X86::ATOMNAND16: 9480 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 9481 X86::AND16ri, X86::MOV16rm, 9482 X86::LCMPXCHG16, 9483 X86::NOT16r, X86::AX, 9484 X86::GR16RegisterClass, true); 9485 case X86::ATOMMIN16: 9486 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 9487 case X86::ATOMMAX16: 9488 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 9489 case X86::ATOMUMIN16: 9490 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 9491 case X86::ATOMUMAX16: 9492 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 9493 9494 case X86::ATOMAND8: 9495 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 9496 X86::AND8ri, X86::MOV8rm, 9497 X86::LCMPXCHG8, 9498 X86::NOT8r, X86::AL, 9499 X86::GR8RegisterClass); 9500 case X86::ATOMOR8: 9501 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 9502 X86::OR8ri, X86::MOV8rm, 9503 X86::LCMPXCHG8, 9504 X86::NOT8r, X86::AL, 9505 X86::GR8RegisterClass); 9506 case X86::ATOMXOR8: 9507 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 9508 X86::XOR8ri, X86::MOV8rm, 9509 X86::LCMPXCHG8, 9510 X86::NOT8r, X86::AL, 9511 X86::GR8RegisterClass); 9512 case X86::ATOMNAND8: 9513 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 9514 X86::AND8ri, X86::MOV8rm, 9515 X86::LCMPXCHG8, 9516 X86::NOT8r, X86::AL, 9517 X86::GR8RegisterClass, true); 9518 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 9519 // This group is for 64-bit host. 9520 case X86::ATOMAND64: 9521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 9522 X86::AND64ri32, X86::MOV64rm, 9523 X86::LCMPXCHG64, 9524 X86::NOT64r, X86::RAX, 9525 X86::GR64RegisterClass); 9526 case X86::ATOMOR64: 9527 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 9528 X86::OR64ri32, X86::MOV64rm, 9529 X86::LCMPXCHG64, 9530 X86::NOT64r, X86::RAX, 9531 X86::GR64RegisterClass); 9532 case X86::ATOMXOR64: 9533 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 9534 X86::XOR64ri32, X86::MOV64rm, 9535 X86::LCMPXCHG64, 9536 X86::NOT64r, X86::RAX, 9537 X86::GR64RegisterClass); 9538 case X86::ATOMNAND64: 9539 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 9540 X86::AND64ri32, X86::MOV64rm, 9541 X86::LCMPXCHG64, 9542 X86::NOT64r, X86::RAX, 9543 X86::GR64RegisterClass, true); 9544 case X86::ATOMMIN64: 9545 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 9546 case X86::ATOMMAX64: 9547 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 9548 case X86::ATOMUMIN64: 9549 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 9550 case X86::ATOMUMAX64: 9551 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 9552 9553 // This group does 64-bit operations on a 32-bit host. 9554 case X86::ATOMAND6432: 9555 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9556 X86::AND32rr, X86::AND32rr, 9557 X86::AND32ri, X86::AND32ri, 9558 false); 9559 case X86::ATOMOR6432: 9560 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9561 X86::OR32rr, X86::OR32rr, 9562 X86::OR32ri, X86::OR32ri, 9563 false); 9564 case X86::ATOMXOR6432: 9565 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9566 X86::XOR32rr, X86::XOR32rr, 9567 X86::XOR32ri, X86::XOR32ri, 9568 false); 9569 case X86::ATOMNAND6432: 9570 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9571 X86::AND32rr, X86::AND32rr, 9572 X86::AND32ri, X86::AND32ri, 9573 true); 9574 case X86::ATOMADD6432: 9575 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9576 X86::ADD32rr, X86::ADC32rr, 9577 X86::ADD32ri, X86::ADC32ri, 9578 false); 9579 case X86::ATOMSUB6432: 9580 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9581 X86::SUB32rr, X86::SBB32rr, 9582 X86::SUB32ri, X86::SBB32ri, 9583 false); 9584 case X86::ATOMSWAP6432: 9585 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9586 X86::MOV32rr, X86::MOV32rr, 9587 X86::MOV32ri, X86::MOV32ri, 9588 false); 9589 case X86::VASTART_SAVE_XMM_REGS: 9590 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 9591 } 9592} 9593 9594//===----------------------------------------------------------------------===// 9595// X86 Optimization Hooks 9596//===----------------------------------------------------------------------===// 9597 9598void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 9599 const APInt &Mask, 9600 APInt &KnownZero, 9601 APInt &KnownOne, 9602 const SelectionDAG &DAG, 9603 unsigned Depth) const { 9604 unsigned Opc = Op.getOpcode(); 9605 assert((Opc >= ISD::BUILTIN_OP_END || 9606 Opc == ISD::INTRINSIC_WO_CHAIN || 9607 Opc == ISD::INTRINSIC_W_CHAIN || 9608 Opc == ISD::INTRINSIC_VOID) && 9609 "Should use MaskedValueIsZero if you don't know whether Op" 9610 " is a target node!"); 9611 9612 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 9613 switch (Opc) { 9614 default: break; 9615 case X86ISD::ADD: 9616 case X86ISD::SUB: 9617 case X86ISD::SMUL: 9618 case X86ISD::UMUL: 9619 case X86ISD::INC: 9620 case X86ISD::DEC: 9621 case X86ISD::OR: 9622 case X86ISD::XOR: 9623 case X86ISD::AND: 9624 // These nodes' second result is a boolean. 9625 if (Op.getResNo() == 0) 9626 break; 9627 // Fallthrough 9628 case X86ISD::SETCC: 9629 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 9630 Mask.getBitWidth() - 1); 9631 break; 9632 } 9633} 9634 9635/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 9636/// node is a GlobalAddress + offset. 9637bool X86TargetLowering::isGAPlusOffset(SDNode *N, 9638 const GlobalValue* &GA, 9639 int64_t &Offset) const { 9640 if (N->getOpcode() == X86ISD::Wrapper) { 9641 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 9642 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 9643 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 9644 return true; 9645 } 9646 } 9647 return TargetLowering::isGAPlusOffset(N, GA, Offset); 9648} 9649 9650/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 9651/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 9652/// if the load addresses are consecutive, non-overlapping, and in the right 9653/// order. 9654static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 9655 const TargetLowering &TLI) { 9656 DebugLoc dl = N->getDebugLoc(); 9657 EVT VT = N->getValueType(0); 9658 9659 if (VT.getSizeInBits() != 128) 9660 return SDValue(); 9661 9662 SmallVector<SDValue, 16> Elts; 9663 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 9664 Elts.push_back(getShuffleScalarElt(N, i, DAG)); 9665 9666 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 9667} 9668 9669/// PerformShuffleCombine - Detect vector gather/scatter index generation 9670/// and convert it from being a bunch of shuffles and extracts to a simple 9671/// store and scalar loads to extract the elements. 9672static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 9673 const TargetLowering &TLI) { 9674 SDValue InputVector = N->getOperand(0); 9675 9676 // Only operate on vectors of 4 elements, where the alternative shuffling 9677 // gets to be more expensive. 9678 if (InputVector.getValueType() != MVT::v4i32) 9679 return SDValue(); 9680 9681 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 9682 // single use which is a sign-extend or zero-extend, and all elements are 9683 // used. 9684 SmallVector<SDNode *, 4> Uses; 9685 unsigned ExtractedElements = 0; 9686 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 9687 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 9688 if (UI.getUse().getResNo() != InputVector.getResNo()) 9689 return SDValue(); 9690 9691 SDNode *Extract = *UI; 9692 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 9693 return SDValue(); 9694 9695 if (Extract->getValueType(0) != MVT::i32) 9696 return SDValue(); 9697 if (!Extract->hasOneUse()) 9698 return SDValue(); 9699 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 9700 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 9701 return SDValue(); 9702 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 9703 return SDValue(); 9704 9705 // Record which element was extracted. 9706 ExtractedElements |= 9707 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 9708 9709 Uses.push_back(Extract); 9710 } 9711 9712 // If not all the elements were used, this may not be worthwhile. 9713 if (ExtractedElements != 15) 9714 return SDValue(); 9715 9716 // Ok, we've now decided to do the transformation. 9717 DebugLoc dl = InputVector.getDebugLoc(); 9718 9719 // Store the value to a temporary stack slot. 9720 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 9721 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 9722 0, false, false, 0); 9723 9724 // Replace each use (extract) with a load of the appropriate element. 9725 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 9726 UE = Uses.end(); UI != UE; ++UI) { 9727 SDNode *Extract = *UI; 9728 9729 // Compute the element's address. 9730 SDValue Idx = Extract->getOperand(1); 9731 unsigned EltSize = 9732 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 9733 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 9734 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 9735 9736 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), 9737 OffsetVal, StackPtr); 9738 9739 // Load the scalar. 9740 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 9741 ScalarAddr, NULL, 0, false, false, 0); 9742 9743 // Replace the exact with the load. 9744 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 9745 } 9746 9747 // The replacement was made in place; don't return anything. 9748 return SDValue(); 9749} 9750 9751/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 9752static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 9753 const X86Subtarget *Subtarget) { 9754 DebugLoc DL = N->getDebugLoc(); 9755 SDValue Cond = N->getOperand(0); 9756 // Get the LHS/RHS of the select. 9757 SDValue LHS = N->getOperand(1); 9758 SDValue RHS = N->getOperand(2); 9759 9760 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 9761 // instructions match the semantics of the common C idiom x<y?x:y but not 9762 // x<=y?x:y, because of how they handle negative zero (which can be 9763 // ignored in unsafe-math mode). 9764 if (Subtarget->hasSSE2() && 9765 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 9766 Cond.getOpcode() == ISD::SETCC) { 9767 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 9768 9769 unsigned Opcode = 0; 9770 // Check for x CC y ? x : y. 9771 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 9772 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 9773 switch (CC) { 9774 default: break; 9775 case ISD::SETULT: 9776 // Converting this to a min would handle NaNs incorrectly, and swapping 9777 // the operands would cause it to handle comparisons between positive 9778 // and negative zero incorrectly. 9779 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9780 if (!UnsafeFPMath && 9781 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9782 break; 9783 std::swap(LHS, RHS); 9784 } 9785 Opcode = X86ISD::FMIN; 9786 break; 9787 case ISD::SETOLE: 9788 // Converting this to a min would handle comparisons between positive 9789 // and negative zero incorrectly. 9790 if (!UnsafeFPMath && 9791 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9792 break; 9793 Opcode = X86ISD::FMIN; 9794 break; 9795 case ISD::SETULE: 9796 // Converting this to a min would handle both negative zeros and NaNs 9797 // incorrectly, but we can swap the operands to fix both. 9798 std::swap(LHS, RHS); 9799 case ISD::SETOLT: 9800 case ISD::SETLT: 9801 case ISD::SETLE: 9802 Opcode = X86ISD::FMIN; 9803 break; 9804 9805 case ISD::SETOGE: 9806 // Converting this to a max would handle comparisons between positive 9807 // and negative zero incorrectly. 9808 if (!UnsafeFPMath && 9809 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9810 break; 9811 Opcode = X86ISD::FMAX; 9812 break; 9813 case ISD::SETUGT: 9814 // Converting this to a max would handle NaNs incorrectly, and swapping 9815 // the operands would cause it to handle comparisons between positive 9816 // and negative zero incorrectly. 9817 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9818 if (!UnsafeFPMath && 9819 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9820 break; 9821 std::swap(LHS, RHS); 9822 } 9823 Opcode = X86ISD::FMAX; 9824 break; 9825 case ISD::SETUGE: 9826 // Converting this to a max would handle both negative zeros and NaNs 9827 // incorrectly, but we can swap the operands to fix both. 9828 std::swap(LHS, RHS); 9829 case ISD::SETOGT: 9830 case ISD::SETGT: 9831 case ISD::SETGE: 9832 Opcode = X86ISD::FMAX; 9833 break; 9834 } 9835 // Check for x CC y ? y : x -- a min/max with reversed arms. 9836 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9837 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9838 switch (CC) { 9839 default: break; 9840 case ISD::SETOGE: 9841 // Converting this to a min would handle comparisons between positive 9842 // and negative zero incorrectly, and swapping the operands would 9843 // cause it to handle NaNs incorrectly. 9844 if (!UnsafeFPMath && 9845 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9846 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9847 break; 9848 std::swap(LHS, RHS); 9849 } 9850 Opcode = X86ISD::FMIN; 9851 break; 9852 case ISD::SETUGT: 9853 // Converting this to a min would handle NaNs incorrectly. 9854 if (!UnsafeFPMath && 9855 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9856 break; 9857 Opcode = X86ISD::FMIN; 9858 break; 9859 case ISD::SETUGE: 9860 // Converting this to a min would handle both negative zeros and NaNs 9861 // incorrectly, but we can swap the operands to fix both. 9862 std::swap(LHS, RHS); 9863 case ISD::SETOGT: 9864 case ISD::SETGT: 9865 case ISD::SETGE: 9866 Opcode = X86ISD::FMIN; 9867 break; 9868 9869 case ISD::SETULT: 9870 // Converting this to a max would handle NaNs incorrectly. 9871 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9872 break; 9873 Opcode = X86ISD::FMAX; 9874 break; 9875 case ISD::SETOLE: 9876 // Converting this to a max would handle comparisons between positive 9877 // and negative zero incorrectly, and swapping the operands would 9878 // cause it to handle NaNs incorrectly. 9879 if (!UnsafeFPMath && 9880 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9881 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9882 break; 9883 std::swap(LHS, RHS); 9884 } 9885 Opcode = X86ISD::FMAX; 9886 break; 9887 case ISD::SETULE: 9888 // Converting this to a max would handle both negative zeros and NaNs 9889 // incorrectly, but we can swap the operands to fix both. 9890 std::swap(LHS, RHS); 9891 case ISD::SETOLT: 9892 case ISD::SETLT: 9893 case ISD::SETLE: 9894 Opcode = X86ISD::FMAX; 9895 break; 9896 } 9897 } 9898 9899 if (Opcode) 9900 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9901 } 9902 9903 // If this is a select between two integer constants, try to do some 9904 // optimizations. 9905 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9906 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9907 // Don't do this for crazy integer types. 9908 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9909 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9910 // so that TrueC (the true value) is larger than FalseC. 9911 bool NeedsCondInvert = false; 9912 9913 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9914 // Efficiently invertible. 9915 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9916 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9917 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9918 NeedsCondInvert = true; 9919 std::swap(TrueC, FalseC); 9920 } 9921 9922 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9923 if (FalseC->getAPIntValue() == 0 && 9924 TrueC->getAPIntValue().isPowerOf2()) { 9925 if (NeedsCondInvert) // Invert the condition if needed. 9926 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9927 DAG.getConstant(1, Cond.getValueType())); 9928 9929 // Zero extend the condition if needed. 9930 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9931 9932 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9933 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9934 DAG.getConstant(ShAmt, MVT::i8)); 9935 } 9936 9937 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9938 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9939 if (NeedsCondInvert) // Invert the condition if needed. 9940 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9941 DAG.getConstant(1, Cond.getValueType())); 9942 9943 // Zero extend the condition if needed. 9944 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9945 FalseC->getValueType(0), Cond); 9946 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9947 SDValue(FalseC, 0)); 9948 } 9949 9950 // Optimize cases that will turn into an LEA instruction. This requires 9951 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9952 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9953 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9954 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9955 9956 bool isFastMultiplier = false; 9957 if (Diff < 10) { 9958 switch ((unsigned char)Diff) { 9959 default: break; 9960 case 1: // result = add base, cond 9961 case 2: // result = lea base( , cond*2) 9962 case 3: // result = lea base(cond, cond*2) 9963 case 4: // result = lea base( , cond*4) 9964 case 5: // result = lea base(cond, cond*4) 9965 case 8: // result = lea base( , cond*8) 9966 case 9: // result = lea base(cond, cond*8) 9967 isFastMultiplier = true; 9968 break; 9969 } 9970 } 9971 9972 if (isFastMultiplier) { 9973 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9974 if (NeedsCondInvert) // Invert the condition if needed. 9975 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9976 DAG.getConstant(1, Cond.getValueType())); 9977 9978 // Zero extend the condition if needed. 9979 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9980 Cond); 9981 // Scale the condition by the difference. 9982 if (Diff != 1) 9983 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9984 DAG.getConstant(Diff, Cond.getValueType())); 9985 9986 // Add the base if non-zero. 9987 if (FalseC->getAPIntValue() != 0) 9988 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9989 SDValue(FalseC, 0)); 9990 return Cond; 9991 } 9992 } 9993 } 9994 } 9995 9996 return SDValue(); 9997} 9998 9999/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 10000static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 10001 TargetLowering::DAGCombinerInfo &DCI) { 10002 DebugLoc DL = N->getDebugLoc(); 10003 10004 // If the flag operand isn't dead, don't touch this CMOV. 10005 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 10006 return SDValue(); 10007 10008 // If this is a select between two integer constants, try to do some 10009 // optimizations. Note that the operands are ordered the opposite of SELECT 10010 // operands. 10011 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 10012 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 10013 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 10014 // larger than FalseC (the false value). 10015 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 10016 10017 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 10018 CC = X86::GetOppositeBranchCondition(CC); 10019 std::swap(TrueC, FalseC); 10020 } 10021 10022 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 10023 // This is efficient for any integer data type (including i8/i16) and 10024 // shift amount. 10025 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 10026 SDValue Cond = N->getOperand(3); 10027 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10028 DAG.getConstant(CC, MVT::i8), Cond); 10029 10030 // Zero extend the condition if needed. 10031 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 10032 10033 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 10034 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 10035 DAG.getConstant(ShAmt, MVT::i8)); 10036 if (N->getNumValues() == 2) // Dead flag value? 10037 return DCI.CombineTo(N, Cond, SDValue()); 10038 return Cond; 10039 } 10040 10041 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 10042 // for any integer data type, including i8/i16. 10043 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 10044 SDValue Cond = N->getOperand(3); 10045 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10046 DAG.getConstant(CC, MVT::i8), Cond); 10047 10048 // Zero extend the condition if needed. 10049 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 10050 FalseC->getValueType(0), Cond); 10051 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10052 SDValue(FalseC, 0)); 10053 10054 if (N->getNumValues() == 2) // Dead flag value? 10055 return DCI.CombineTo(N, Cond, SDValue()); 10056 return Cond; 10057 } 10058 10059 // Optimize cases that will turn into an LEA instruction. This requires 10060 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 10061 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 10062 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 10063 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 10064 10065 bool isFastMultiplier = false; 10066 if (Diff < 10) { 10067 switch ((unsigned char)Diff) { 10068 default: break; 10069 case 1: // result = add base, cond 10070 case 2: // result = lea base( , cond*2) 10071 case 3: // result = lea base(cond, cond*2) 10072 case 4: // result = lea base( , cond*4) 10073 case 5: // result = lea base(cond, cond*4) 10074 case 8: // result = lea base( , cond*8) 10075 case 9: // result = lea base(cond, cond*8) 10076 isFastMultiplier = true; 10077 break; 10078 } 10079 } 10080 10081 if (isFastMultiplier) { 10082 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 10083 SDValue Cond = N->getOperand(3); 10084 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10085 DAG.getConstant(CC, MVT::i8), Cond); 10086 // Zero extend the condition if needed. 10087 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 10088 Cond); 10089 // Scale the condition by the difference. 10090 if (Diff != 1) 10091 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 10092 DAG.getConstant(Diff, Cond.getValueType())); 10093 10094 // Add the base if non-zero. 10095 if (FalseC->getAPIntValue() != 0) 10096 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 10097 SDValue(FalseC, 0)); 10098 if (N->getNumValues() == 2) // Dead flag value? 10099 return DCI.CombineTo(N, Cond, SDValue()); 10100 return Cond; 10101 } 10102 } 10103 } 10104 } 10105 return SDValue(); 10106} 10107 10108 10109/// PerformMulCombine - Optimize a single multiply with constant into two 10110/// in order to implement it with two cheaper instructions, e.g. 10111/// LEA + SHL, LEA + LEA. 10112static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 10113 TargetLowering::DAGCombinerInfo &DCI) { 10114 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 10115 return SDValue(); 10116 10117 EVT VT = N->getValueType(0); 10118 if (VT != MVT::i64) 10119 return SDValue(); 10120 10121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 10122 if (!C) 10123 return SDValue(); 10124 uint64_t MulAmt = C->getZExtValue(); 10125 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 10126 return SDValue(); 10127 10128 uint64_t MulAmt1 = 0; 10129 uint64_t MulAmt2 = 0; 10130 if ((MulAmt % 9) == 0) { 10131 MulAmt1 = 9; 10132 MulAmt2 = MulAmt / 9; 10133 } else if ((MulAmt % 5) == 0) { 10134 MulAmt1 = 5; 10135 MulAmt2 = MulAmt / 5; 10136 } else if ((MulAmt % 3) == 0) { 10137 MulAmt1 = 3; 10138 MulAmt2 = MulAmt / 3; 10139 } 10140 if (MulAmt2 && 10141 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 10142 DebugLoc DL = N->getDebugLoc(); 10143 10144 if (isPowerOf2_64(MulAmt2) && 10145 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 10146 // If second multiplifer is pow2, issue it first. We want the multiply by 10147 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 10148 // is an add. 10149 std::swap(MulAmt1, MulAmt2); 10150 10151 SDValue NewMul; 10152 if (isPowerOf2_64(MulAmt1)) 10153 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 10154 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 10155 else 10156 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 10157 DAG.getConstant(MulAmt1, VT)); 10158 10159 if (isPowerOf2_64(MulAmt2)) 10160 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 10161 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 10162 else 10163 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 10164 DAG.getConstant(MulAmt2, VT)); 10165 10166 // Do not add new nodes to DAG combiner worklist. 10167 DCI.CombineTo(N, NewMul, false); 10168 } 10169 return SDValue(); 10170} 10171 10172static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 10173 SDValue N0 = N->getOperand(0); 10174 SDValue N1 = N->getOperand(1); 10175 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 10176 EVT VT = N0.getValueType(); 10177 10178 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 10179 // since the result of setcc_c is all zero's or all ones. 10180 if (N1C && N0.getOpcode() == ISD::AND && 10181 N0.getOperand(1).getOpcode() == ISD::Constant) { 10182 SDValue N00 = N0.getOperand(0); 10183 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 10184 ((N00.getOpcode() == ISD::ANY_EXTEND || 10185 N00.getOpcode() == ISD::ZERO_EXTEND) && 10186 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 10187 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 10188 APInt ShAmt = N1C->getAPIntValue(); 10189 Mask = Mask.shl(ShAmt); 10190 if (Mask != 0) 10191 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 10192 N00, DAG.getConstant(Mask, VT)); 10193 } 10194 } 10195 10196 return SDValue(); 10197} 10198 10199/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 10200/// when possible. 10201static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 10202 const X86Subtarget *Subtarget) { 10203 EVT VT = N->getValueType(0); 10204 if (!VT.isVector() && VT.isInteger() && 10205 N->getOpcode() == ISD::SHL) 10206 return PerformSHLCombine(N, DAG); 10207 10208 // On X86 with SSE2 support, we can transform this to a vector shift if 10209 // all elements are shifted by the same amount. We can't do this in legalize 10210 // because the a constant vector is typically transformed to a constant pool 10211 // so we have no knowledge of the shift amount. 10212 if (!Subtarget->hasSSE2()) 10213 return SDValue(); 10214 10215 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 10216 return SDValue(); 10217 10218 SDValue ShAmtOp = N->getOperand(1); 10219 EVT EltVT = VT.getVectorElementType(); 10220 DebugLoc DL = N->getDebugLoc(); 10221 SDValue BaseShAmt = SDValue(); 10222 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 10223 unsigned NumElts = VT.getVectorNumElements(); 10224 unsigned i = 0; 10225 for (; i != NumElts; ++i) { 10226 SDValue Arg = ShAmtOp.getOperand(i); 10227 if (Arg.getOpcode() == ISD::UNDEF) continue; 10228 BaseShAmt = Arg; 10229 break; 10230 } 10231 for (; i != NumElts; ++i) { 10232 SDValue Arg = ShAmtOp.getOperand(i); 10233 if (Arg.getOpcode() == ISD::UNDEF) continue; 10234 if (Arg != BaseShAmt) { 10235 return SDValue(); 10236 } 10237 } 10238 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 10239 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 10240 SDValue InVec = ShAmtOp.getOperand(0); 10241 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 10242 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 10243 unsigned i = 0; 10244 for (; i != NumElts; ++i) { 10245 SDValue Arg = InVec.getOperand(i); 10246 if (Arg.getOpcode() == ISD::UNDEF) continue; 10247 BaseShAmt = Arg; 10248 break; 10249 } 10250 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 10251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 10252 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 10253 if (C->getZExtValue() == SplatIdx) 10254 BaseShAmt = InVec.getOperand(1); 10255 } 10256 } 10257 if (BaseShAmt.getNode() == 0) 10258 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 10259 DAG.getIntPtrConstant(0)); 10260 } else 10261 return SDValue(); 10262 10263 // The shift amount is an i32. 10264 if (EltVT.bitsGT(MVT::i32)) 10265 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 10266 else if (EltVT.bitsLT(MVT::i32)) 10267 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 10268 10269 // The shift amount is identical so we can do a vector shift. 10270 SDValue ValOp = N->getOperand(0); 10271 switch (N->getOpcode()) { 10272 default: 10273 llvm_unreachable("Unknown shift opcode!"); 10274 break; 10275 case ISD::SHL: 10276 if (VT == MVT::v2i64) 10277 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10278 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10279 ValOp, BaseShAmt); 10280 if (VT == MVT::v4i32) 10281 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10282 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10283 ValOp, BaseShAmt); 10284 if (VT == MVT::v8i16) 10285 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10286 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10287 ValOp, BaseShAmt); 10288 break; 10289 case ISD::SRA: 10290 if (VT == MVT::v4i32) 10291 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10292 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10293 ValOp, BaseShAmt); 10294 if (VT == MVT::v8i16) 10295 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10296 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10297 ValOp, BaseShAmt); 10298 break; 10299 case ISD::SRL: 10300 if (VT == MVT::v2i64) 10301 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10302 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10303 ValOp, BaseShAmt); 10304 if (VT == MVT::v4i32) 10305 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10306 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10307 ValOp, BaseShAmt); 10308 if (VT == MVT::v8i16) 10309 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10310 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10311 ValOp, BaseShAmt); 10312 break; 10313 } 10314 return SDValue(); 10315} 10316 10317static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 10318 TargetLowering::DAGCombinerInfo &DCI, 10319 const X86Subtarget *Subtarget) { 10320 if (DCI.isBeforeLegalizeOps()) 10321 return SDValue(); 10322 10323 EVT VT = N->getValueType(0); 10324 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 10325 return SDValue(); 10326 10327 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 10328 SDValue N0 = N->getOperand(0); 10329 SDValue N1 = N->getOperand(1); 10330 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 10331 std::swap(N0, N1); 10332 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 10333 return SDValue(); 10334 if (!N0.hasOneUse() || !N1.hasOneUse()) 10335 return SDValue(); 10336 10337 SDValue ShAmt0 = N0.getOperand(1); 10338 if (ShAmt0.getValueType() != MVT::i8) 10339 return SDValue(); 10340 SDValue ShAmt1 = N1.getOperand(1); 10341 if (ShAmt1.getValueType() != MVT::i8) 10342 return SDValue(); 10343 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 10344 ShAmt0 = ShAmt0.getOperand(0); 10345 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 10346 ShAmt1 = ShAmt1.getOperand(0); 10347 10348 DebugLoc DL = N->getDebugLoc(); 10349 unsigned Opc = X86ISD::SHLD; 10350 SDValue Op0 = N0.getOperand(0); 10351 SDValue Op1 = N1.getOperand(0); 10352 if (ShAmt0.getOpcode() == ISD::SUB) { 10353 Opc = X86ISD::SHRD; 10354 std::swap(Op0, Op1); 10355 std::swap(ShAmt0, ShAmt1); 10356 } 10357 10358 unsigned Bits = VT.getSizeInBits(); 10359 if (ShAmt1.getOpcode() == ISD::SUB) { 10360 SDValue Sum = ShAmt1.getOperand(0); 10361 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 10362 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 10363 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 10364 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 10365 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 10366 return DAG.getNode(Opc, DL, VT, 10367 Op0, Op1, 10368 DAG.getNode(ISD::TRUNCATE, DL, 10369 MVT::i8, ShAmt0)); 10370 } 10371 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 10372 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 10373 if (ShAmt0C && 10374 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 10375 return DAG.getNode(Opc, DL, VT, 10376 N0.getOperand(0), N1.getOperand(0), 10377 DAG.getNode(ISD::TRUNCATE, DL, 10378 MVT::i8, ShAmt0)); 10379 } 10380 10381 return SDValue(); 10382} 10383 10384/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 10385static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 10386 const X86Subtarget *Subtarget) { 10387 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 10388 // the FP state in cases where an emms may be missing. 10389 // A preferable solution to the general problem is to figure out the right 10390 // places to insert EMMS. This qualifies as a quick hack. 10391 10392 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 10393 StoreSDNode *St = cast<StoreSDNode>(N); 10394 EVT VT = St->getValue().getValueType(); 10395 if (VT.getSizeInBits() != 64) 10396 return SDValue(); 10397 10398 const Function *F = DAG.getMachineFunction().getFunction(); 10399 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 10400 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 10401 && Subtarget->hasSSE2(); 10402 if ((VT.isVector() || 10403 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 10404 isa<LoadSDNode>(St->getValue()) && 10405 !cast<LoadSDNode>(St->getValue())->isVolatile() && 10406 St->getChain().hasOneUse() && !St->isVolatile()) { 10407 SDNode* LdVal = St->getValue().getNode(); 10408 LoadSDNode *Ld = 0; 10409 int TokenFactorIndex = -1; 10410 SmallVector<SDValue, 8> Ops; 10411 SDNode* ChainVal = St->getChain().getNode(); 10412 // Must be a store of a load. We currently handle two cases: the load 10413 // is a direct child, and it's under an intervening TokenFactor. It is 10414 // possible to dig deeper under nested TokenFactors. 10415 if (ChainVal == LdVal) 10416 Ld = cast<LoadSDNode>(St->getChain()); 10417 else if (St->getValue().hasOneUse() && 10418 ChainVal->getOpcode() == ISD::TokenFactor) { 10419 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 10420 if (ChainVal->getOperand(i).getNode() == LdVal) { 10421 TokenFactorIndex = i; 10422 Ld = cast<LoadSDNode>(St->getValue()); 10423 } else 10424 Ops.push_back(ChainVal->getOperand(i)); 10425 } 10426 } 10427 10428 if (!Ld || !ISD::isNormalLoad(Ld)) 10429 return SDValue(); 10430 10431 // If this is not the MMX case, i.e. we are just turning i64 load/store 10432 // into f64 load/store, avoid the transformation if there are multiple 10433 // uses of the loaded value. 10434 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 10435 return SDValue(); 10436 10437 DebugLoc LdDL = Ld->getDebugLoc(); 10438 DebugLoc StDL = N->getDebugLoc(); 10439 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 10440 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 10441 // pair instead. 10442 if (Subtarget->is64Bit() || F64IsLegal) { 10443 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 10444 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 10445 Ld->getBasePtr(), Ld->getSrcValue(), 10446 Ld->getSrcValueOffset(), Ld->isVolatile(), 10447 Ld->isNonTemporal(), Ld->getAlignment()); 10448 SDValue NewChain = NewLd.getValue(1); 10449 if (TokenFactorIndex != -1) { 10450 Ops.push_back(NewChain); 10451 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 10452 Ops.size()); 10453 } 10454 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 10455 St->getSrcValue(), St->getSrcValueOffset(), 10456 St->isVolatile(), St->isNonTemporal(), 10457 St->getAlignment()); 10458 } 10459 10460 // Otherwise, lower to two pairs of 32-bit loads / stores. 10461 SDValue LoAddr = Ld->getBasePtr(); 10462 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 10463 DAG.getConstant(4, MVT::i32)); 10464 10465 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 10466 Ld->getSrcValue(), Ld->getSrcValueOffset(), 10467 Ld->isVolatile(), Ld->isNonTemporal(), 10468 Ld->getAlignment()); 10469 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 10470 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 10471 Ld->isVolatile(), Ld->isNonTemporal(), 10472 MinAlign(Ld->getAlignment(), 4)); 10473 10474 SDValue NewChain = LoLd.getValue(1); 10475 if (TokenFactorIndex != -1) { 10476 Ops.push_back(LoLd); 10477 Ops.push_back(HiLd); 10478 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 10479 Ops.size()); 10480 } 10481 10482 LoAddr = St->getBasePtr(); 10483 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 10484 DAG.getConstant(4, MVT::i32)); 10485 10486 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 10487 St->getSrcValue(), St->getSrcValueOffset(), 10488 St->isVolatile(), St->isNonTemporal(), 10489 St->getAlignment()); 10490 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 10491 St->getSrcValue(), 10492 St->getSrcValueOffset() + 4, 10493 St->isVolatile(), 10494 St->isNonTemporal(), 10495 MinAlign(St->getAlignment(), 4)); 10496 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 10497 } 10498 return SDValue(); 10499} 10500 10501/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 10502/// X86ISD::FXOR nodes. 10503static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 10504 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 10505 // F[X]OR(0.0, x) -> x 10506 // F[X]OR(x, 0.0) -> x 10507 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 10508 if (C->getValueAPF().isPosZero()) 10509 return N->getOperand(1); 10510 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 10511 if (C->getValueAPF().isPosZero()) 10512 return N->getOperand(0); 10513 return SDValue(); 10514} 10515 10516/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 10517static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 10518 // FAND(0.0, x) -> 0.0 10519 // FAND(x, 0.0) -> 0.0 10520 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 10521 if (C->getValueAPF().isPosZero()) 10522 return N->getOperand(0); 10523 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 10524 if (C->getValueAPF().isPosZero()) 10525 return N->getOperand(1); 10526 return SDValue(); 10527} 10528 10529static SDValue PerformBTCombine(SDNode *N, 10530 SelectionDAG &DAG, 10531 TargetLowering::DAGCombinerInfo &DCI) { 10532 // BT ignores high bits in the bit index operand. 10533 SDValue Op1 = N->getOperand(1); 10534 if (Op1.hasOneUse()) { 10535 unsigned BitWidth = Op1.getValueSizeInBits(); 10536 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 10537 APInt KnownZero, KnownOne; 10538 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 10539 !DCI.isBeforeLegalizeOps()); 10540 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10541 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 10542 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 10543 DCI.CommitTargetLoweringOpt(TLO); 10544 } 10545 return SDValue(); 10546} 10547 10548static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 10549 SDValue Op = N->getOperand(0); 10550 if (Op.getOpcode() == ISD::BIT_CONVERT) 10551 Op = Op.getOperand(0); 10552 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 10553 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 10554 VT.getVectorElementType().getSizeInBits() == 10555 OpVT.getVectorElementType().getSizeInBits()) { 10556 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 10557 } 10558 return SDValue(); 10559} 10560 10561static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 10562 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 10563 // (and (i32 x86isd::setcc_carry), 1) 10564 // This eliminates the zext. This transformation is necessary because 10565 // ISD::SETCC is always legalized to i8. 10566 DebugLoc dl = N->getDebugLoc(); 10567 SDValue N0 = N->getOperand(0); 10568 EVT VT = N->getValueType(0); 10569 if (N0.getOpcode() == ISD::AND && 10570 N0.hasOneUse() && 10571 N0.getOperand(0).hasOneUse()) { 10572 SDValue N00 = N0.getOperand(0); 10573 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 10574 return SDValue(); 10575 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 10576 if (!C || C->getZExtValue() != 1) 10577 return SDValue(); 10578 return DAG.getNode(ISD::AND, dl, VT, 10579 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 10580 N00.getOperand(0), N00.getOperand(1)), 10581 DAG.getConstant(1, VT)); 10582 } 10583 10584 return SDValue(); 10585} 10586 10587SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 10588 DAGCombinerInfo &DCI) const { 10589 SelectionDAG &DAG = DCI.DAG; 10590 switch (N->getOpcode()) { 10591 default: break; 10592 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 10593 case ISD::EXTRACT_VECTOR_ELT: 10594 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 10595 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 10596 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 10597 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 10598 case ISD::SHL: 10599 case ISD::SRA: 10600 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 10601 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 10602 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 10603 case X86ISD::FXOR: 10604 case X86ISD::FOR: return PerformFORCombine(N, DAG); 10605 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 10606 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 10607 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 10608 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 10609 } 10610 10611 return SDValue(); 10612} 10613 10614/// isTypeDesirableForOp - Return true if the target has native support for 10615/// the specified value type and it is 'desirable' to use the type for the 10616/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 10617/// instruction encodings are longer and some i16 instructions are slow. 10618bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 10619 if (!isTypeLegal(VT)) 10620 return false; 10621 if (VT != MVT::i16) 10622 return true; 10623 10624 switch (Opc) { 10625 default: 10626 return true; 10627 case ISD::LOAD: 10628 case ISD::SIGN_EXTEND: 10629 case ISD::ZERO_EXTEND: 10630 case ISD::ANY_EXTEND: 10631 case ISD::SHL: 10632 case ISD::SRL: 10633 case ISD::SUB: 10634 case ISD::ADD: 10635 case ISD::MUL: 10636 case ISD::AND: 10637 case ISD::OR: 10638 case ISD::XOR: 10639 return false; 10640 } 10641} 10642 10643/// IsDesirableToPromoteOp - This method query the target whether it is 10644/// beneficial for dag combiner to promote the specified node. If true, it 10645/// should return the desired promotion type by reference. 10646bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 10647 EVT VT = Op.getValueType(); 10648 if (VT != MVT::i16) 10649 return false; 10650 10651 bool Promote = false; 10652 bool Commute = false; 10653 switch (Op.getOpcode()) { 10654 default: break; 10655 case ISD::LOAD: { 10656 LoadSDNode *LD = cast<LoadSDNode>(Op); 10657 // If the non-extending load has a single use and it's not live out, then it 10658 // might be folded. 10659 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 10660 Op.hasOneUse()*/) { 10661 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 10662 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 10663 // The only case where we'd want to promote LOAD (rather then it being 10664 // promoted as an operand is when it's only use is liveout. 10665 if (UI->getOpcode() != ISD::CopyToReg) 10666 return false; 10667 } 10668 } 10669 Promote = true; 10670 break; 10671 } 10672 case ISD::SIGN_EXTEND: 10673 case ISD::ZERO_EXTEND: 10674 case ISD::ANY_EXTEND: 10675 Promote = true; 10676 break; 10677 case ISD::SHL: 10678 case ISD::SRL: { 10679 SDValue N0 = Op.getOperand(0); 10680 // Look out for (store (shl (load), x)). 10681 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 10682 return false; 10683 Promote = true; 10684 break; 10685 } 10686 case ISD::ADD: 10687 case ISD::MUL: 10688 case ISD::AND: 10689 case ISD::OR: 10690 case ISD::XOR: 10691 Commute = true; 10692 // fallthrough 10693 case ISD::SUB: { 10694 SDValue N0 = Op.getOperand(0); 10695 SDValue N1 = Op.getOperand(1); 10696 if (!Commute && MayFoldLoad(N1)) 10697 return false; 10698 // Avoid disabling potential load folding opportunities. 10699 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 10700 return false; 10701 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 10702 return false; 10703 Promote = true; 10704 } 10705 } 10706 10707 PVT = MVT::i32; 10708 return Promote; 10709} 10710 10711//===----------------------------------------------------------------------===// 10712// X86 Inline Assembly Support 10713//===----------------------------------------------------------------------===// 10714 10715static bool LowerToBSwap(CallInst *CI) { 10716 // FIXME: this should verify that we are targetting a 486 or better. If not, 10717 // we will turn this bswap into something that will be lowered to logical ops 10718 // instead of emitting the bswap asm. For now, we don't support 486 or lower 10719 // so don't worry about this. 10720 10721 // Verify this is a simple bswap. 10722 if (CI->getNumArgOperands() != 1 || 10723 CI->getType() != CI->getArgOperand(0)->getType() || 10724 !CI->getType()->isIntegerTy()) 10725 return false; 10726 10727 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 10728 if (!Ty || Ty->getBitWidth() % 16 != 0) 10729 return false; 10730 10731 // Okay, we can do this xform, do so now. 10732 const Type *Tys[] = { Ty }; 10733 Module *M = CI->getParent()->getParent()->getParent(); 10734 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 10735 10736 Value *Op = CI->getArgOperand(0); 10737 Op = CallInst::Create(Int, Op, CI->getName(), CI); 10738 10739 CI->replaceAllUsesWith(Op); 10740 CI->eraseFromParent(); 10741 return true; 10742} 10743 10744bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 10745 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 10746 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 10747 10748 std::string AsmStr = IA->getAsmString(); 10749 10750 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 10751 SmallVector<StringRef, 4> AsmPieces; 10752 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 10753 10754 switch (AsmPieces.size()) { 10755 default: return false; 10756 case 1: 10757 AsmStr = AsmPieces[0]; 10758 AsmPieces.clear(); 10759 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 10760 10761 // bswap $0 10762 if (AsmPieces.size() == 2 && 10763 (AsmPieces[0] == "bswap" || 10764 AsmPieces[0] == "bswapq" || 10765 AsmPieces[0] == "bswapl") && 10766 (AsmPieces[1] == "$0" || 10767 AsmPieces[1] == "${0:q}")) { 10768 // No need to check constraints, nothing other than the equivalent of 10769 // "=r,0" would be valid here. 10770 return LowerToBSwap(CI); 10771 } 10772 // rorw $$8, ${0:w} --> llvm.bswap.i16 10773 if (CI->getType()->isIntegerTy(16) && 10774 AsmPieces.size() == 3 && 10775 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 10776 AsmPieces[1] == "$$8," && 10777 AsmPieces[2] == "${0:w}" && 10778 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 10779 AsmPieces.clear(); 10780 const std::string &Constraints = IA->getConstraintString(); 10781 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 10782 std::sort(AsmPieces.begin(), AsmPieces.end()); 10783 if (AsmPieces.size() == 4 && 10784 AsmPieces[0] == "~{cc}" && 10785 AsmPieces[1] == "~{dirflag}" && 10786 AsmPieces[2] == "~{flags}" && 10787 AsmPieces[3] == "~{fpsr}") { 10788 return LowerToBSwap(CI); 10789 } 10790 } 10791 break; 10792 case 3: 10793 if (CI->getType()->isIntegerTy(64) && 10794 Constraints.size() >= 2 && 10795 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 10796 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 10797 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 10798 SmallVector<StringRef, 4> Words; 10799 SplitString(AsmPieces[0], Words, " \t"); 10800 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 10801 Words.clear(); 10802 SplitString(AsmPieces[1], Words, " \t"); 10803 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 10804 Words.clear(); 10805 SplitString(AsmPieces[2], Words, " \t,"); 10806 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 10807 Words[2] == "%edx") { 10808 return LowerToBSwap(CI); 10809 } 10810 } 10811 } 10812 } 10813 break; 10814 } 10815 return false; 10816} 10817 10818 10819 10820/// getConstraintType - Given a constraint letter, return the type of 10821/// constraint it is for this target. 10822X86TargetLowering::ConstraintType 10823X86TargetLowering::getConstraintType(const std::string &Constraint) const { 10824 if (Constraint.size() == 1) { 10825 switch (Constraint[0]) { 10826 case 'A': 10827 return C_Register; 10828 case 'f': 10829 case 'r': 10830 case 'R': 10831 case 'l': 10832 case 'q': 10833 case 'Q': 10834 case 'x': 10835 case 'y': 10836 case 'Y': 10837 return C_RegisterClass; 10838 case 'e': 10839 case 'Z': 10840 return C_Other; 10841 default: 10842 break; 10843 } 10844 } 10845 return TargetLowering::getConstraintType(Constraint); 10846} 10847 10848/// LowerXConstraint - try to replace an X constraint, which matches anything, 10849/// with another that has more specific requirements based on the type of the 10850/// corresponding operand. 10851const char *X86TargetLowering:: 10852LowerXConstraint(EVT ConstraintVT) const { 10853 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10854 // 'f' like normal targets. 10855 if (ConstraintVT.isFloatingPoint()) { 10856 if (Subtarget->hasSSE2()) 10857 return "Y"; 10858 if (Subtarget->hasSSE1()) 10859 return "x"; 10860 } 10861 10862 return TargetLowering::LowerXConstraint(ConstraintVT); 10863} 10864 10865/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10866/// vector. If it is invalid, don't add anything to Ops. 10867void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10868 char Constraint, 10869 std::vector<SDValue>&Ops, 10870 SelectionDAG &DAG) const { 10871 SDValue Result(0, 0); 10872 10873 switch (Constraint) { 10874 default: break; 10875 case 'I': 10876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10877 if (C->getZExtValue() <= 31) { 10878 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10879 break; 10880 } 10881 } 10882 return; 10883 case 'J': 10884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10885 if (C->getZExtValue() <= 63) { 10886 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10887 break; 10888 } 10889 } 10890 return; 10891 case 'K': 10892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10893 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10894 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10895 break; 10896 } 10897 } 10898 return; 10899 case 'N': 10900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10901 if (C->getZExtValue() <= 255) { 10902 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10903 break; 10904 } 10905 } 10906 return; 10907 case 'e': { 10908 // 32-bit signed value 10909 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10910 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10911 C->getSExtValue())) { 10912 // Widen to 64 bits here to get it sign extended. 10913 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10914 break; 10915 } 10916 // FIXME gcc accepts some relocatable values here too, but only in certain 10917 // memory models; it's complicated. 10918 } 10919 return; 10920 } 10921 case 'Z': { 10922 // 32-bit unsigned value 10923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10924 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10925 C->getZExtValue())) { 10926 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10927 break; 10928 } 10929 } 10930 // FIXME gcc accepts some relocatable values here too, but only in certain 10931 // memory models; it's complicated. 10932 return; 10933 } 10934 case 'i': { 10935 // Literal immediates are always ok. 10936 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10937 // Widen to 64 bits here to get it sign extended. 10938 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10939 break; 10940 } 10941 10942 // In any sort of PIC mode addresses need to be computed at runtime by 10943 // adding in a register or some sort of table lookup. These can't 10944 // be used as immediates. 10945 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 10946 return; 10947 10948 // If we are in non-pic codegen mode, we allow the address of a global (with 10949 // an optional displacement) to be used with 'i'. 10950 GlobalAddressSDNode *GA = 0; 10951 int64_t Offset = 0; 10952 10953 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10954 while (1) { 10955 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10956 Offset += GA->getOffset(); 10957 break; 10958 } else if (Op.getOpcode() == ISD::ADD) { 10959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10960 Offset += C->getZExtValue(); 10961 Op = Op.getOperand(0); 10962 continue; 10963 } 10964 } else if (Op.getOpcode() == ISD::SUB) { 10965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10966 Offset += -C->getZExtValue(); 10967 Op = Op.getOperand(0); 10968 continue; 10969 } 10970 } 10971 10972 // Otherwise, this isn't something we can handle, reject it. 10973 return; 10974 } 10975 10976 const GlobalValue *GV = GA->getGlobal(); 10977 // If we require an extra load to get this address, as in PIC mode, we 10978 // can't accept it. 10979 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10980 getTargetMachine()))) 10981 return; 10982 10983 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 10984 GA->getValueType(0), Offset); 10985 break; 10986 } 10987 } 10988 10989 if (Result.getNode()) { 10990 Ops.push_back(Result); 10991 return; 10992 } 10993 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 10994} 10995 10996std::vector<unsigned> X86TargetLowering:: 10997getRegClassForInlineAsmConstraint(const std::string &Constraint, 10998 EVT VT) const { 10999 if (Constraint.size() == 1) { 11000 // FIXME: not handling fp-stack yet! 11001 switch (Constraint[0]) { // GCC X86 Constraint Letters 11002 default: break; // Unknown constraint letter 11003 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 11004 if (Subtarget->is64Bit()) { 11005 if (VT == MVT::i32) 11006 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 11007 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 11008 X86::R10D,X86::R11D,X86::R12D, 11009 X86::R13D,X86::R14D,X86::R15D, 11010 X86::EBP, X86::ESP, 0); 11011 else if (VT == MVT::i16) 11012 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 11013 X86::SI, X86::DI, X86::R8W,X86::R9W, 11014 X86::R10W,X86::R11W,X86::R12W, 11015 X86::R13W,X86::R14W,X86::R15W, 11016 X86::BP, X86::SP, 0); 11017 else if (VT == MVT::i8) 11018 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 11019 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 11020 X86::R10B,X86::R11B,X86::R12B, 11021 X86::R13B,X86::R14B,X86::R15B, 11022 X86::BPL, X86::SPL, 0); 11023 11024 else if (VT == MVT::i64) 11025 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 11026 X86::RSI, X86::RDI, X86::R8, X86::R9, 11027 X86::R10, X86::R11, X86::R12, 11028 X86::R13, X86::R14, X86::R15, 11029 X86::RBP, X86::RSP, 0); 11030 11031 break; 11032 } 11033 // 32-bit fallthrough 11034 case 'Q': // Q_REGS 11035 if (VT == MVT::i32) 11036 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 11037 else if (VT == MVT::i16) 11038 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 11039 else if (VT == MVT::i8) 11040 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 11041 else if (VT == MVT::i64) 11042 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 11043 break; 11044 } 11045 } 11046 11047 return std::vector<unsigned>(); 11048} 11049 11050std::pair<unsigned, const TargetRegisterClass*> 11051X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 11052 EVT VT) const { 11053 // First, see if this is a constraint that directly corresponds to an LLVM 11054 // register class. 11055 if (Constraint.size() == 1) { 11056 // GCC Constraint Letters 11057 switch (Constraint[0]) { 11058 default: break; 11059 case 'r': // GENERAL_REGS 11060 case 'l': // INDEX_REGS 11061 if (VT == MVT::i8) 11062 return std::make_pair(0U, X86::GR8RegisterClass); 11063 if (VT == MVT::i16) 11064 return std::make_pair(0U, X86::GR16RegisterClass); 11065 if (VT == MVT::i32 || !Subtarget->is64Bit()) 11066 return std::make_pair(0U, X86::GR32RegisterClass); 11067 return std::make_pair(0U, X86::GR64RegisterClass); 11068 case 'R': // LEGACY_REGS 11069 if (VT == MVT::i8) 11070 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 11071 if (VT == MVT::i16) 11072 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 11073 if (VT == MVT::i32 || !Subtarget->is64Bit()) 11074 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 11075 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 11076 case 'f': // FP Stack registers. 11077 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 11078 // value to the correct fpstack register class. 11079 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 11080 return std::make_pair(0U, X86::RFP32RegisterClass); 11081 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 11082 return std::make_pair(0U, X86::RFP64RegisterClass); 11083 return std::make_pair(0U, X86::RFP80RegisterClass); 11084 case 'y': // MMX_REGS if MMX allowed. 11085 if (!Subtarget->hasMMX()) break; 11086 return std::make_pair(0U, X86::VR64RegisterClass); 11087 case 'Y': // SSE_REGS if SSE2 allowed 11088 if (!Subtarget->hasSSE2()) break; 11089 // FALL THROUGH. 11090 case 'x': // SSE_REGS if SSE1 allowed 11091 if (!Subtarget->hasSSE1()) break; 11092 11093 switch (VT.getSimpleVT().SimpleTy) { 11094 default: break; 11095 // Scalar SSE types. 11096 case MVT::f32: 11097 case MVT::i32: 11098 return std::make_pair(0U, X86::FR32RegisterClass); 11099 case MVT::f64: 11100 case MVT::i64: 11101 return std::make_pair(0U, X86::FR64RegisterClass); 11102 // Vector types. 11103 case MVT::v16i8: 11104 case MVT::v8i16: 11105 case MVT::v4i32: 11106 case MVT::v2i64: 11107 case MVT::v4f32: 11108 case MVT::v2f64: 11109 return std::make_pair(0U, X86::VR128RegisterClass); 11110 } 11111 break; 11112 } 11113 } 11114 11115 // Use the default implementation in TargetLowering to convert the register 11116 // constraint into a member of a register class. 11117 std::pair<unsigned, const TargetRegisterClass*> Res; 11118 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 11119 11120 // Not found as a standard register? 11121 if (Res.second == 0) { 11122 // Map st(0) -> st(7) -> ST0 11123 if (Constraint.size() == 7 && Constraint[0] == '{' && 11124 tolower(Constraint[1]) == 's' && 11125 tolower(Constraint[2]) == 't' && 11126 Constraint[3] == '(' && 11127 (Constraint[4] >= '0' && Constraint[4] <= '7') && 11128 Constraint[5] == ')' && 11129 Constraint[6] == '}') { 11130 11131 Res.first = X86::ST0+Constraint[4]-'0'; 11132 Res.second = X86::RFP80RegisterClass; 11133 return Res; 11134 } 11135 11136 // GCC allows "st(0)" to be called just plain "st". 11137 if (StringRef("{st}").equals_lower(Constraint)) { 11138 Res.first = X86::ST0; 11139 Res.second = X86::RFP80RegisterClass; 11140 return Res; 11141 } 11142 11143 // flags -> EFLAGS 11144 if (StringRef("{flags}").equals_lower(Constraint)) { 11145 Res.first = X86::EFLAGS; 11146 Res.second = X86::CCRRegisterClass; 11147 return Res; 11148 } 11149 11150 // 'A' means EAX + EDX. 11151 if (Constraint == "A") { 11152 Res.first = X86::EAX; 11153 Res.second = X86::GR32_ADRegisterClass; 11154 return Res; 11155 } 11156 return Res; 11157 } 11158 11159 // Otherwise, check to see if this is a register class of the wrong value 11160 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 11161 // turn into {ax},{dx}. 11162 if (Res.second->hasType(VT)) 11163 return Res; // Correct type already, nothing to do. 11164 11165 // All of the single-register GCC register classes map their values onto 11166 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 11167 // really want an 8-bit or 32-bit register, map to the appropriate register 11168 // class and return the appropriate register. 11169 if (Res.second == X86::GR16RegisterClass) { 11170 if (VT == MVT::i8) { 11171 unsigned DestReg = 0; 11172 switch (Res.first) { 11173 default: break; 11174 case X86::AX: DestReg = X86::AL; break; 11175 case X86::DX: DestReg = X86::DL; break; 11176 case X86::CX: DestReg = X86::CL; break; 11177 case X86::BX: DestReg = X86::BL; break; 11178 } 11179 if (DestReg) { 11180 Res.first = DestReg; 11181 Res.second = X86::GR8RegisterClass; 11182 } 11183 } else if (VT == MVT::i32) { 11184 unsigned DestReg = 0; 11185 switch (Res.first) { 11186 default: break; 11187 case X86::AX: DestReg = X86::EAX; break; 11188 case X86::DX: DestReg = X86::EDX; break; 11189 case X86::CX: DestReg = X86::ECX; break; 11190 case X86::BX: DestReg = X86::EBX; break; 11191 case X86::SI: DestReg = X86::ESI; break; 11192 case X86::DI: DestReg = X86::EDI; break; 11193 case X86::BP: DestReg = X86::EBP; break; 11194 case X86::SP: DestReg = X86::ESP; break; 11195 } 11196 if (DestReg) { 11197 Res.first = DestReg; 11198 Res.second = X86::GR32RegisterClass; 11199 } 11200 } else if (VT == MVT::i64) { 11201 unsigned DestReg = 0; 11202 switch (Res.first) { 11203 default: break; 11204 case X86::AX: DestReg = X86::RAX; break; 11205 case X86::DX: DestReg = X86::RDX; break; 11206 case X86::CX: DestReg = X86::RCX; break; 11207 case X86::BX: DestReg = X86::RBX; break; 11208 case X86::SI: DestReg = X86::RSI; break; 11209 case X86::DI: DestReg = X86::RDI; break; 11210 case X86::BP: DestReg = X86::RBP; break; 11211 case X86::SP: DestReg = X86::RSP; break; 11212 } 11213 if (DestReg) { 11214 Res.first = DestReg; 11215 Res.second = X86::GR64RegisterClass; 11216 } 11217 } 11218 } else if (Res.second == X86::FR32RegisterClass || 11219 Res.second == X86::FR64RegisterClass || 11220 Res.second == X86::VR128RegisterClass) { 11221 // Handle references to XMM physical registers that got mapped into the 11222 // wrong class. This can happen with constraints like {xmm0} where the 11223 // target independent register mapper will just pick the first match it can 11224 // find, ignoring the required type. 11225 if (VT == MVT::f32) 11226 Res.second = X86::FR32RegisterClass; 11227 else if (VT == MVT::f64) 11228 Res.second = X86::FR64RegisterClass; 11229 else if (X86::VR128RegisterClass->hasType(VT)) 11230 Res.second = X86::VR128RegisterClass; 11231 } 11232 11233 return Res; 11234} 11235