X86ISelLowering.cpp revision d2070b00efb97ee32e360d53edfd7bf6de88d62c
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VariadicFunction.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetOptions.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasSSE2(); 172 X86ScalarSSEf32 = Subtarget->hasSSE1(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 185 186 // For 64-bit since we have so many registers use the ILP scheduler, for 187 // 32-bit code use the register pressure specific scheduling. 188 if (Subtarget->is64Bit()) 189 setSchedulingPreference(Sched::ILP); 190 else 191 setSchedulingPreference(Sched::RegPressure); 192 setStackPointerRegisterToSaveRestore(X86StackPtr); 193 194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 195 // Setup Windows compiler runtime calls. 196 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 198 setLibcallName(RTLIB::SREM_I64, "_allrem"); 199 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 200 setLibcallName(RTLIB::MUL_I64, "_allmul"); 201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 210 } 211 212 if (Subtarget->isTargetDarwin()) { 213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 214 setUseUnderscoreSetJmp(false); 215 setUseUnderscoreLongJmp(false); 216 } else if (Subtarget->isTargetMingw()) { 217 // MS runtime is weird: it exports _setjmp, but longjmp! 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(false); 220 } else { 221 setUseUnderscoreSetJmp(true); 222 setUseUnderscoreLongJmp(true); 223 } 224 225 // Set up the register classes. 226 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 227 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 228 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 229 if (Subtarget->is64Bit()) 230 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 231 232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 234 // We don't accept any truncstore of integer registers. 235 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 240 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 241 242 // SETOEQ and SETUNE require checking two conditions. 243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 249 250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 251 // operation. 252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 259 } else if (!TM.Options.UseSoftFloat) { 260 // We have an algorithm for SSE2->double, and we turn this into a 261 // 64-bit FILD followed by conditional FADD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 // We have an algorithm for SSE2, and we turn this into a 64-bit 264 // FILD for other targets. 265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 266 } 267 268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 269 // this operation. 270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 272 273 if (!TM.Options.UseSoftFloat) { 274 // SSE has no i16 to fp conversion, only i32 275 if (X86ScalarSSEf32) { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 // f32 and f64 cases are Legal, f80 case is not 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } else { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 282 } 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 286 } 287 288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 289 // are Legal, f80 is custom lowered. 290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 292 293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 294 // this operation. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 297 298 if (X86ScalarSSEf32) { 299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 300 // f32 and f64 cases are Legal, f80 case is not 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } else { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 305 } 306 307 // Handle FP_TO_UINT by promoting the destination to a larger signed 308 // conversion. 309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 312 313 if (Subtarget->is64Bit()) { 314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 316 } else if (!TM.Options.UseSoftFloat) { 317 // Since AVX is a superset of SSE3, only check for SSE here. 318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 319 // Expand FP_TO_UINT into a select. 320 // FIXME: We would like to use a Custom expander here eventually to do 321 // the optimal thing for SSE vs. the default expansion in the legalizer. 322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 323 else 324 // With SSE3 we can use fisttpll to convert to a signed i64; without 325 // SSE, we're stuck with a fistpll. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 327 } 328 329 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 330 if (!X86ScalarSSEf64) { 331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 333 if (Subtarget->is64Bit()) { 334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 335 // Without SSE, i64->f64 goes through memory. 336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 337 } 338 } 339 340 // Scalar integer divide and remainder are lowered to use operations that 341 // produce two results, to match the available instructions. This exposes 342 // the two-result form to trivial CSE, which is able to combine x/y and x%y 343 // into a single instruction. 344 // 345 // Scalar integer multiply-high is also lowered to use two-result 346 // operations, to match the available instructions. However, plain multiply 347 // (low) operations are left as Legal, as there are single-result 348 // instructions for this in x86. Using the two-result multiply instructions 349 // when both high and low results are needed must be arranged by dagcombine. 350 for (unsigned i = 0, e = 4; i != e; ++i) { 351 MVT VT = IntVTs[i]; 352 setOperationAction(ISD::MULHS, VT, Expand); 353 setOperationAction(ISD::MULHU, VT, Expand); 354 setOperationAction(ISD::SDIV, VT, Expand); 355 setOperationAction(ISD::UDIV, VT, Expand); 356 setOperationAction(ISD::SREM, VT, Expand); 357 setOperationAction(ISD::UREM, VT, Expand); 358 359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 360 setOperationAction(ISD::ADDC, VT, Custom); 361 setOperationAction(ISD::ADDE, VT, Custom); 362 setOperationAction(ISD::SUBC, VT, Custom); 363 setOperationAction(ISD::SUBE, VT, Custom); 364 } 365 366 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 367 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 368 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f64 , Expand); 378 setOperationAction(ISD::FREM , MVT::f80 , Expand); 379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 380 381 // Promote the i8 variants and force them on up to i32 which has a shorter 382 // encoding. 383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 387 if (Subtarget->hasBMI()) { 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 390 if (Subtarget->is64Bit()) 391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 392 } else { 393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 395 if (Subtarget->is64Bit()) 396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 397 } 398 399 if (Subtarget->hasLZCNT()) { 400 // When promoting the i8 variants, force them to i32 for a shorter 401 // encoding. 402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 408 if (Subtarget->is64Bit()) 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 410 } else { 411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 417 if (Subtarget->is64Bit()) { 418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 420 } 421 } 422 423 if (Subtarget->hasPOPCNT()) { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 425 } else { 426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 429 if (Subtarget->is64Bit()) 430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 431 } 432 433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 435 436 // These should be promoted to a larger select which is supported. 437 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 438 // X86 wants to expand cmov itself. 439 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 440 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 441 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 443 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 444 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 446 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 449 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 450 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 451 if (Subtarget->is64Bit()) { 452 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 453 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 454 } 455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 456 457 // Darwin ABI issue. 458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 462 if (Subtarget->is64Bit()) 463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 466 if (Subtarget->is64Bit()) { 467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 472 } 473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 477 if (Subtarget->is64Bit()) { 478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 481 } 482 483 if (Subtarget->hasSSE1()) 484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 485 486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 488 489 // On X86 and X86-64, atomic operations are lowered to locked instructions. 490 // Locked instructions, in turn, have implicit fence semantics (all memory 491 // operations are flushed before issuing the locked instruction, and they 492 // are not buffered), so we can fold away the common pattern of 493 // fence-atomic-fence. 494 setShouldFoldAtomicFences(true); 495 496 // Expand certain atomics 497 for (unsigned i = 0, e = 4; i != e; ++i) { 498 MVT VT = IntVTs[i]; 499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 502 } 503 504 if (!Subtarget->is64Bit()) { 505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 513 } 514 515 if (Subtarget->hasCmpxchg16b()) { 516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 517 } 518 519 // FIXME - use subtarget debug flags 520 if (!Subtarget->isTargetDarwin() && 521 !Subtarget->isTargetELF() && 522 !Subtarget->isTargetCygMing()) { 523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 524 } 525 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 530 if (Subtarget->is64Bit()) { 531 setExceptionPointerRegister(X86::RAX); 532 setExceptionSelectorRegister(X86::RDX); 533 } else { 534 setExceptionPointerRegister(X86::EAX); 535 setExceptionSelectorRegister(X86::EDX); 536 } 537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 539 540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 542 543 setOperationAction(ISD::TRAP, MVT::Other, Legal); 544 545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 546 setOperationAction(ISD::VASTART , MVT::Other, Custom); 547 setOperationAction(ISD::VAEND , MVT::Other, Expand); 548 if (Subtarget->is64Bit()) { 549 setOperationAction(ISD::VAARG , MVT::Other, Custom); 550 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 551 } else { 552 setOperationAction(ISD::VAARG , MVT::Other, Expand); 553 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 554 } 555 556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 558 559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Custom); 562 else if (TM.Options.EnableSegmentedStacks) 563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 564 MVT::i64 : MVT::i32, Custom); 565 else 566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 567 MVT::i64 : MVT::i32, Expand); 568 569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 570 // f32 and f64 use SSE. 571 // Set up the FP register classes. 572 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 573 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 574 575 // Use ANDPD to simulate FABS. 576 setOperationAction(ISD::FABS , MVT::f64, Custom); 577 setOperationAction(ISD::FABS , MVT::f32, Custom); 578 579 // Use XORP to simulate FNEG. 580 setOperationAction(ISD::FNEG , MVT::f64, Custom); 581 setOperationAction(ISD::FNEG , MVT::f32, Custom); 582 583 // Use ANDPD and ORPD to simulate FCOPYSIGN. 584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 586 587 // Lower this to FGETSIGNx86 plus an AND. 588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 590 591 // We don't support sin/cos/fmod 592 setOperationAction(ISD::FSIN , MVT::f64, Expand); 593 setOperationAction(ISD::FCOS , MVT::f64, Expand); 594 setOperationAction(ISD::FSIN , MVT::f32, Expand); 595 setOperationAction(ISD::FCOS , MVT::f32, Expand); 596 597 // Expand FP immediates into loads from the stack, except for the special 598 // cases we handle. 599 addLegalFPImmediate(APFloat(+0.0)); // xorpd 600 addLegalFPImmediate(APFloat(+0.0f)); // xorps 601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 602 // Use SSE for f32, x87 for f64. 603 // Set up the FP register classes. 604 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 605 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 606 607 // Use ANDPS to simulate FABS. 608 setOperationAction(ISD::FABS , MVT::f32, Custom); 609 610 // Use XORP to simulate FNEG. 611 setOperationAction(ISD::FNEG , MVT::f32, Custom); 612 613 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 614 615 // Use ANDPS and ORPS to simulate FCOPYSIGN. 616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 618 619 // We don't support sin/cos/fmod 620 setOperationAction(ISD::FSIN , MVT::f32, Expand); 621 setOperationAction(ISD::FCOS , MVT::f32, Expand); 622 623 // Special cases we handle for FP constants. 624 addLegalFPImmediate(APFloat(+0.0f)); // xorps 625 addLegalFPImmediate(APFloat(+0.0)); // FLD0 626 addLegalFPImmediate(APFloat(+1.0)); // FLD1 627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 629 630 if (!TM.Options.UnsafeFPMath) { 631 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 632 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 633 } 634 } else if (!TM.Options.UseSoftFloat) { 635 // f32 and f64 in x87. 636 // Set up the FP register classes. 637 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 638 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 639 640 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 641 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 644 645 if (!TM.Options.UnsafeFPMath) { 646 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 647 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 648 } 649 addLegalFPImmediate(APFloat(+0.0)); // FLD0 650 addLegalFPImmediate(APFloat(+1.0)); // FLD1 651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 657 } 658 659 // We don't support FMA. 660 setOperationAction(ISD::FMA, MVT::f64, Expand); 661 setOperationAction(ISD::FMA, MVT::f32, Expand); 662 663 // Long double always uses X87. 664 if (!TM.Options.UseSoftFloat) { 665 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 666 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 668 { 669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 670 addLegalFPImmediate(TmpFlt); // FLD0 671 TmpFlt.changeSign(); 672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 673 674 bool ignored; 675 APFloat TmpFlt2(+1.0); 676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 677 &ignored); 678 addLegalFPImmediate(TmpFlt2); // FLD1 679 TmpFlt2.changeSign(); 680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 681 } 682 683 if (!TM.Options.UnsafeFPMath) { 684 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 685 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 686 } 687 688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 689 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 691 setOperationAction(ISD::FRINT, MVT::f80, Expand); 692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 693 setOperationAction(ISD::FMA, MVT::f80, Expand); 694 } 695 696 // Always use a library call for pow. 697 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 698 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 699 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 700 701 setOperationAction(ISD::FLOG, MVT::f80, Expand); 702 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 703 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 704 setOperationAction(ISD::FEXP, MVT::f80, Expand); 705 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 706 707 // First set operation action for all vector types to either promote 708 // (for widening) or expand (for scalarization). Then we will selectively 709 // turn on ones that can be effectively codegen'd. 710 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 711 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 764 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 769 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 770 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 771 setTruncStoreAction((MVT::SimpleValueType)VT, 772 (MVT::SimpleValueType)InnerVT, Expand); 773 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 775 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 776 } 777 778 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 779 // with -msoft-float, disable use of MMX as well. 780 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 781 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 782 // No operations on x86mmx supported, everything uses intrinsics. 783 } 784 785 // MMX-sized vectors (other than x86mmx) are expected to be expanded 786 // into smaller operations. 787 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 788 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 789 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 790 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 791 setOperationAction(ISD::AND, MVT::v8i8, Expand); 792 setOperationAction(ISD::AND, MVT::v4i16, Expand); 793 setOperationAction(ISD::AND, MVT::v2i32, Expand); 794 setOperationAction(ISD::AND, MVT::v1i64, Expand); 795 setOperationAction(ISD::OR, MVT::v8i8, Expand); 796 setOperationAction(ISD::OR, MVT::v4i16, Expand); 797 setOperationAction(ISD::OR, MVT::v2i32, Expand); 798 setOperationAction(ISD::OR, MVT::v1i64, Expand); 799 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 800 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 801 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 802 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 808 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 809 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 810 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 811 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 814 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 815 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 816 817 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 818 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 819 820 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 821 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 822 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 823 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 824 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 825 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 826 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 827 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 830 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 831 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 832 } 833 834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 835 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 836 837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 838 // registers cannot be used even for integer operations. 839 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 841 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 842 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 843 844 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 845 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 846 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 847 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 848 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 849 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 850 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 851 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 852 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 853 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 854 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 860 861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 865 866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 871 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 877 878 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 880 EVT VT = (MVT::SimpleValueType)i; 881 // Do not attempt to custom lower non-power-of-2 vectors 882 if (!isPowerOf2_32(VT.getVectorNumElements())) 883 continue; 884 // Do not attempt to custom lower non-128-bit vectors 885 if (!VT.is128BitVector()) 886 continue; 887 setOperationAction(ISD::BUILD_VECTOR, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::VECTOR_SHUFFLE, 890 VT.getSimpleVT().SimpleTy, Custom); 891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 892 VT.getSimpleVT().SimpleTy, Custom); 893 } 894 895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 901 902 if (Subtarget->is64Bit()) { 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 905 } 906 907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 909 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 910 EVT VT = SVT; 911 912 // Do not attempt to promote non-128-bit vectors 913 if (!VT.is128BitVector()) 914 continue; 915 916 setOperationAction(ISD::AND, SVT, Promote); 917 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 918 setOperationAction(ISD::OR, SVT, Promote); 919 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 920 setOperationAction(ISD::XOR, SVT, Promote); 921 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 922 setOperationAction(ISD::LOAD, SVT, Promote); 923 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 924 setOperationAction(ISD::SELECT, SVT, Promote); 925 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 926 } 927 928 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 929 930 // Custom lower v2i64 and v2f64 selects. 931 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 932 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 933 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 934 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 935 936 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 937 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 938 } 939 940 if (Subtarget->hasSSE41()) { 941 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 942 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 944 setOperationAction(ISD::FRINT, MVT::f32, Legal); 945 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 946 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 947 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 948 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 949 setOperationAction(ISD::FRINT, MVT::f64, Legal); 950 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 951 952 // FIXME: Do we need to handle scalar-to-vector here? 953 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 954 955 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 958 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 959 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 960 961 // i8 and i16 vectors are custom , because the source register and source 962 // source memory operand types are not the same width. f32 vectors are 963 // custom since the immediate controlling the insert encodes additional 964 // information. 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 969 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 974 975 // FIXME: these should be Legal but thats only for the case where 976 // the index is constant. For now custom expand to deal with that. 977 if (Subtarget->is64Bit()) { 978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 980 } 981 } 982 983 if (Subtarget->hasSSE2()) { 984 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 986 987 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 988 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 989 990 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 991 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 992 993 if (Subtarget->hasAVX2()) { 994 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 995 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 996 997 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 998 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 999 1000 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1001 } else { 1002 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1003 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1004 1005 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1006 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1007 1008 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1009 } 1010 } 1011 1012 if (Subtarget->hasSSE42()) 1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1014 1015 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1016 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1020 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1021 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1022 1023 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1024 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1025 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1026 1027 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1031 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1033 1034 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1038 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1040 1041 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1042 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1043 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1044 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1051 1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1060 1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1065 1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1069 1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1074 1075 if (Subtarget->hasAVX2()) { 1076 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1077 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1078 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1079 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1080 1081 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1082 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1083 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1084 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1085 1086 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1087 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1088 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1089 // Don't lower v32i8 because there is no 128-bit byte mul 1090 1091 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1092 1093 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1094 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1095 1096 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1097 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1098 1099 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1100 } else { 1101 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1102 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1103 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1104 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1105 1106 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1107 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1108 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1109 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1110 1111 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1112 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1113 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1114 // Don't lower v32i8 because there is no 128-bit byte mul 1115 1116 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1117 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1118 1119 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1120 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1121 1122 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1123 } 1124 1125 // Custom lower several nodes for 256-bit types. 1126 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1127 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1128 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1129 EVT VT = SVT; 1130 1131 // Extract subvector is special because the value type 1132 // (result) is 128-bit but the source is 256-bit wide. 1133 if (VT.is128BitVector()) 1134 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1135 1136 // Do not attempt to custom lower other non-256-bit vectors 1137 if (!VT.is256BitVector()) 1138 continue; 1139 1140 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1141 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1142 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1144 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1145 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1146 } 1147 1148 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1149 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1150 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1151 EVT VT = SVT; 1152 1153 // Do not attempt to promote non-256-bit vectors 1154 if (!VT.is256BitVector()) 1155 continue; 1156 1157 setOperationAction(ISD::AND, SVT, Promote); 1158 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1159 setOperationAction(ISD::OR, SVT, Promote); 1160 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::XOR, SVT, Promote); 1162 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1163 setOperationAction(ISD::LOAD, SVT, Promote); 1164 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1165 setOperationAction(ISD::SELECT, SVT, Promote); 1166 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1167 } 1168 } 1169 1170 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1171 // of this type with custom code. 1172 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1173 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1174 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1175 Custom); 1176 } 1177 1178 // We want to custom lower some of our intrinsics. 1179 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1180 1181 1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1183 // handle type legalization for these operations here. 1184 // 1185 // FIXME: We really should do custom legalization for addition and 1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1187 // than generic legalization for 64-bit multiplication-with-overflow, though. 1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1189 // Add/Sub/Mul with overflow operations are custom lowered. 1190 MVT VT = IntVTs[i]; 1191 setOperationAction(ISD::SADDO, VT, Custom); 1192 setOperationAction(ISD::UADDO, VT, Custom); 1193 setOperationAction(ISD::SSUBO, VT, Custom); 1194 setOperationAction(ISD::USUBO, VT, Custom); 1195 setOperationAction(ISD::SMULO, VT, Custom); 1196 setOperationAction(ISD::UMULO, VT, Custom); 1197 } 1198 1199 // There are no 8-bit 3-address imul/mul instructions 1200 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1201 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1202 1203 if (!Subtarget->is64Bit()) { 1204 // These libcalls are not available in 32-bit. 1205 setLibcallName(RTLIB::SHL_I128, 0); 1206 setLibcallName(RTLIB::SRL_I128, 0); 1207 setLibcallName(RTLIB::SRA_I128, 0); 1208 } 1209 1210 // We have target-specific dag combine patterns for the following nodes: 1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1213 setTargetDAGCombine(ISD::VSELECT); 1214 setTargetDAGCombine(ISD::SELECT); 1215 setTargetDAGCombine(ISD::SHL); 1216 setTargetDAGCombine(ISD::SRA); 1217 setTargetDAGCombine(ISD::SRL); 1218 setTargetDAGCombine(ISD::OR); 1219 setTargetDAGCombine(ISD::AND); 1220 setTargetDAGCombine(ISD::ADD); 1221 setTargetDAGCombine(ISD::FADD); 1222 setTargetDAGCombine(ISD::FSUB); 1223 setTargetDAGCombine(ISD::SUB); 1224 setTargetDAGCombine(ISD::LOAD); 1225 setTargetDAGCombine(ISD::STORE); 1226 setTargetDAGCombine(ISD::ZERO_EXTEND); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->hasAVX() && 1331 Subtarget->getStackAlignment() >= 32) 1332 return MVT::v8f32; 1333 if (Subtarget->hasSSE2()) 1334 return MVT::v4i32; 1335 if (Subtarget->hasSSE1()) 1336 return MVT::v4f32; 1337 } else if (!MemcpyStrSrc && Size >= 8 && 1338 !Subtarget->is64Bit() && 1339 Subtarget->getStackAlignment() >= 8 && 1340 Subtarget->hasSSE2()) { 1341 // Do not use f64 to lower memcpy if source is string constant. It's 1342 // better to use i32 to avoid the loads. 1343 return MVT::f64; 1344 } 1345 } 1346 if (Subtarget->is64Bit() && Size >= 8) 1347 return MVT::i64; 1348 return MVT::i32; 1349} 1350 1351/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1352/// current function. The returned value is a member of the 1353/// MachineJumpTableInfo::JTEntryKind enum. 1354unsigned X86TargetLowering::getJumpTableEncoding() const { 1355 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1356 // symbol. 1357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1358 Subtarget->isPICStyleGOT()) 1359 return MachineJumpTableInfo::EK_Custom32; 1360 1361 // Otherwise, use the normal jump table encoding heuristics. 1362 return TargetLowering::getJumpTableEncoding(); 1363} 1364 1365const MCExpr * 1366X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1367 const MachineBasicBlock *MBB, 1368 unsigned uid,MCContext &Ctx) const{ 1369 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1370 Subtarget->isPICStyleGOT()); 1371 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1372 // entries. 1373 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1374 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1375} 1376 1377/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1378/// jumptable. 1379SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1380 SelectionDAG &DAG) const { 1381 if (!Subtarget->is64Bit()) 1382 // This doesn't have DebugLoc associated with it, but is not really the 1383 // same as a Register. 1384 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1385 return Table; 1386} 1387 1388/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1389/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1390/// MCExpr. 1391const MCExpr *X86TargetLowering:: 1392getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1393 MCContext &Ctx) const { 1394 // X86-64 uses RIP relative addressing based on the jump table label. 1395 if (Subtarget->isPICStyleRIPRel()) 1396 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1397 1398 // Otherwise, the reference is relative to the PIC base. 1399 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1400} 1401 1402// FIXME: Why this routine is here? Move to RegInfo! 1403std::pair<const TargetRegisterClass*, uint8_t> 1404X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1405 const TargetRegisterClass *RRC = 0; 1406 uint8_t Cost = 1; 1407 switch (VT.getSimpleVT().SimpleTy) { 1408 default: 1409 return TargetLowering::findRepresentativeClass(VT); 1410 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1411 RRC = (Subtarget->is64Bit() 1412 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1413 break; 1414 case MVT::x86mmx: 1415 RRC = X86::VR64RegisterClass; 1416 break; 1417 case MVT::f32: case MVT::f64: 1418 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1419 case MVT::v4f32: case MVT::v2f64: 1420 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1421 case MVT::v4f64: 1422 RRC = X86::VR128RegisterClass; 1423 break; 1424 } 1425 return std::make_pair(RRC, Cost); 1426} 1427 1428bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1429 unsigned &Offset) const { 1430 if (!Subtarget->isTargetLinux()) 1431 return false; 1432 1433 if (Subtarget->is64Bit()) { 1434 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1435 Offset = 0x28; 1436 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1437 AddressSpace = 256; 1438 else 1439 AddressSpace = 257; 1440 } else { 1441 // %gs:0x14 on i386 1442 Offset = 0x14; 1443 AddressSpace = 256; 1444 } 1445 return true; 1446} 1447 1448 1449//===----------------------------------------------------------------------===// 1450// Return Value Calling Convention Implementation 1451//===----------------------------------------------------------------------===// 1452 1453#include "X86GenCallingConv.inc" 1454 1455bool 1456X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1457 MachineFunction &MF, bool isVarArg, 1458 const SmallVectorImpl<ISD::OutputArg> &Outs, 1459 LLVMContext &Context) const { 1460 SmallVector<CCValAssign, 16> RVLocs; 1461 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1462 RVLocs, Context); 1463 return CCInfo.CheckReturn(Outs, RetCC_X86); 1464} 1465 1466SDValue 1467X86TargetLowering::LowerReturn(SDValue Chain, 1468 CallingConv::ID CallConv, bool isVarArg, 1469 const SmallVectorImpl<ISD::OutputArg> &Outs, 1470 const SmallVectorImpl<SDValue> &OutVals, 1471 DebugLoc dl, SelectionDAG &DAG) const { 1472 MachineFunction &MF = DAG.getMachineFunction(); 1473 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1474 1475 SmallVector<CCValAssign, 16> RVLocs; 1476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1477 RVLocs, *DAG.getContext()); 1478 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1479 1480 // Add the regs to the liveout set for the function. 1481 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1482 for (unsigned i = 0; i != RVLocs.size(); ++i) 1483 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1484 MRI.addLiveOut(RVLocs[i].getLocReg()); 1485 1486 SDValue Flag; 1487 1488 SmallVector<SDValue, 6> RetOps; 1489 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1490 // Operand #1 = Bytes To Pop 1491 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1492 MVT::i16)); 1493 1494 // Copy the result values into the output registers. 1495 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1496 CCValAssign &VA = RVLocs[i]; 1497 assert(VA.isRegLoc() && "Can only return in registers!"); 1498 SDValue ValToCopy = OutVals[i]; 1499 EVT ValVT = ValToCopy.getValueType(); 1500 1501 // If this is x86-64, and we disabled SSE, we can't return FP values, 1502 // or SSE or MMX vectors. 1503 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1504 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1505 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1506 report_fatal_error("SSE register return with SSE disabled"); 1507 } 1508 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1509 // llvm-gcc has never done it right and no one has noticed, so this 1510 // should be OK for now. 1511 if (ValVT == MVT::f64 && 1512 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1513 report_fatal_error("SSE2 register return with SSE2 disabled"); 1514 1515 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1516 // the RET instruction and handled by the FP Stackifier. 1517 if (VA.getLocReg() == X86::ST0 || 1518 VA.getLocReg() == X86::ST1) { 1519 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1520 // change the value to the FP stack register class. 1521 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1522 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1523 RetOps.push_back(ValToCopy); 1524 // Don't emit a copytoreg. 1525 continue; 1526 } 1527 1528 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1529 // which is returned in RAX / RDX. 1530 if (Subtarget->is64Bit()) { 1531 if (ValVT == MVT::x86mmx) { 1532 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1533 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1534 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1535 ValToCopy); 1536 // If we don't have SSE2 available, convert to v4f32 so the generated 1537 // register is legal. 1538 if (!Subtarget->hasSSE2()) 1539 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1540 } 1541 } 1542 } 1543 1544 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1545 Flag = Chain.getValue(1); 1546 } 1547 1548 // The x86-64 ABI for returning structs by value requires that we copy 1549 // the sret argument into %rax for the return. We saved the argument into 1550 // a virtual register in the entry block, so now we copy the value out 1551 // and into %rax. 1552 if (Subtarget->is64Bit() && 1553 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1554 MachineFunction &MF = DAG.getMachineFunction(); 1555 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1556 unsigned Reg = FuncInfo->getSRetReturnReg(); 1557 assert(Reg && 1558 "SRetReturnReg should have been set in LowerFormalArguments()."); 1559 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1560 1561 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1562 Flag = Chain.getValue(1); 1563 1564 // RAX now acts like a return value. 1565 MRI.addLiveOut(X86::RAX); 1566 } 1567 1568 RetOps[0] = Chain; // Update chain. 1569 1570 // Add the flag if we have it. 1571 if (Flag.getNode()) 1572 RetOps.push_back(Flag); 1573 1574 return DAG.getNode(X86ISD::RET_FLAG, dl, 1575 MVT::Other, &RetOps[0], RetOps.size()); 1576} 1577 1578bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1579 if (N->getNumValues() != 1) 1580 return false; 1581 if (!N->hasNUsesOfValue(1, 0)) 1582 return false; 1583 1584 SDNode *Copy = *N->use_begin(); 1585 if (Copy->getOpcode() != ISD::CopyToReg && 1586 Copy->getOpcode() != ISD::FP_EXTEND) 1587 return false; 1588 1589 bool HasRet = false; 1590 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1591 UI != UE; ++UI) { 1592 if (UI->getOpcode() != X86ISD::RET_FLAG) 1593 return false; 1594 HasRet = true; 1595 } 1596 1597 return HasRet; 1598} 1599 1600EVT 1601X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1602 ISD::NodeType ExtendKind) const { 1603 MVT ReturnMVT; 1604 // TODO: Is this also valid on 32-bit? 1605 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1606 ReturnMVT = MVT::i8; 1607 else 1608 ReturnMVT = MVT::i32; 1609 1610 EVT MinVT = getRegisterType(Context, ReturnMVT); 1611 return VT.bitsLT(MinVT) ? MinVT : VT; 1612} 1613 1614/// LowerCallResult - Lower the result values of a call into the 1615/// appropriate copies out of appropriate physical registers. 1616/// 1617SDValue 1618X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1619 CallingConv::ID CallConv, bool isVarArg, 1620 const SmallVectorImpl<ISD::InputArg> &Ins, 1621 DebugLoc dl, SelectionDAG &DAG, 1622 SmallVectorImpl<SDValue> &InVals) const { 1623 1624 // Assign locations to each value returned by this call. 1625 SmallVector<CCValAssign, 16> RVLocs; 1626 bool Is64Bit = Subtarget->is64Bit(); 1627 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1628 getTargetMachine(), RVLocs, *DAG.getContext()); 1629 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1630 1631 // Copy all of the result registers out of their specified physreg. 1632 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1633 CCValAssign &VA = RVLocs[i]; 1634 EVT CopyVT = VA.getValVT(); 1635 1636 // If this is x86-64, and we disabled SSE, we can't return FP values 1637 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1638 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1639 report_fatal_error("SSE register return with SSE disabled"); 1640 } 1641 1642 SDValue Val; 1643 1644 // If this is a call to a function that returns an fp value on the floating 1645 // point stack, we must guarantee the the value is popped from the stack, so 1646 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1647 // if the return value is not used. We use the FpPOP_RETVAL instruction 1648 // instead. 1649 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1650 // If we prefer to use the value in xmm registers, copy it out as f80 and 1651 // use a truncate to move it from fp stack reg to xmm reg. 1652 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1653 SDValue Ops[] = { Chain, InFlag }; 1654 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1655 MVT::Other, MVT::Glue, Ops, 2), 1); 1656 Val = Chain.getValue(0); 1657 1658 // Round the f80 to the right size, which also moves it to the appropriate 1659 // xmm register. 1660 if (CopyVT != VA.getValVT()) 1661 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1662 // This truncation won't change the value. 1663 DAG.getIntPtrConstant(1)); 1664 } else { 1665 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1666 CopyVT, InFlag).getValue(1); 1667 Val = Chain.getValue(0); 1668 } 1669 InFlag = Chain.getValue(2); 1670 InVals.push_back(Val); 1671 } 1672 1673 return Chain; 1674} 1675 1676 1677//===----------------------------------------------------------------------===// 1678// C & StdCall & Fast Calling Convention implementation 1679//===----------------------------------------------------------------------===// 1680// StdCall calling convention seems to be standard for many Windows' API 1681// routines and around. It differs from C calling convention just a little: 1682// callee should clean up the stack, not caller. Symbols should be also 1683// decorated in some fancy way :) It doesn't support any vector arguments. 1684// For info on fast calling convention see Fast Calling Convention (tail call) 1685// implementation LowerX86_32FastCCCallTo. 1686 1687/// CallIsStructReturn - Determines whether a call uses struct return 1688/// semantics. 1689static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1690 if (Outs.empty()) 1691 return false; 1692 1693 return Outs[0].Flags.isSRet(); 1694} 1695 1696/// ArgsAreStructReturn - Determines whether a function uses struct 1697/// return semantics. 1698static bool 1699ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1700 if (Ins.empty()) 1701 return false; 1702 1703 return Ins[0].Flags.isSRet(); 1704} 1705 1706/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1707/// by "Src" to address "Dst" with size and alignment information specified by 1708/// the specific parameter attribute. The copy will be passed as a byval 1709/// function parameter. 1710static SDValue 1711CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1712 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1713 DebugLoc dl) { 1714 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1715 1716 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1717 /*isVolatile*/false, /*AlwaysInline=*/true, 1718 MachinePointerInfo(), MachinePointerInfo()); 1719} 1720 1721/// IsTailCallConvention - Return true if the calling convention is one that 1722/// supports tail call optimization. 1723static bool IsTailCallConvention(CallingConv::ID CC) { 1724 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1725} 1726 1727bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1728 if (!CI->isTailCall()) 1729 return false; 1730 1731 CallSite CS(CI); 1732 CallingConv::ID CalleeCC = CS.getCallingConv(); 1733 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1734 return false; 1735 1736 return true; 1737} 1738 1739/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1740/// a tailcall target by changing its ABI. 1741static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1742 bool GuaranteedTailCallOpt) { 1743 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1744} 1745 1746SDValue 1747X86TargetLowering::LowerMemArgument(SDValue Chain, 1748 CallingConv::ID CallConv, 1749 const SmallVectorImpl<ISD::InputArg> &Ins, 1750 DebugLoc dl, SelectionDAG &DAG, 1751 const CCValAssign &VA, 1752 MachineFrameInfo *MFI, 1753 unsigned i) const { 1754 // Create the nodes corresponding to a load from this parameter slot. 1755 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1756 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1757 getTargetMachine().Options.GuaranteedTailCallOpt); 1758 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1759 EVT ValVT; 1760 1761 // If value is passed by pointer we have address passed instead of the value 1762 // itself. 1763 if (VA.getLocInfo() == CCValAssign::Indirect) 1764 ValVT = VA.getLocVT(); 1765 else 1766 ValVT = VA.getValVT(); 1767 1768 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1769 // changed with more analysis. 1770 // In case of tail call optimization mark all arguments mutable. Since they 1771 // could be overwritten by lowering of arguments in case of a tail call. 1772 if (Flags.isByVal()) { 1773 unsigned Bytes = Flags.getByValSize(); 1774 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1775 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1776 return DAG.getFrameIndex(FI, getPointerTy()); 1777 } else { 1778 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1779 VA.getLocMemOffset(), isImmutable); 1780 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1781 return DAG.getLoad(ValVT, dl, Chain, FIN, 1782 MachinePointerInfo::getFixedStack(FI), 1783 false, false, false, 0); 1784 } 1785} 1786 1787SDValue 1788X86TargetLowering::LowerFormalArguments(SDValue Chain, 1789 CallingConv::ID CallConv, 1790 bool isVarArg, 1791 const SmallVectorImpl<ISD::InputArg> &Ins, 1792 DebugLoc dl, 1793 SelectionDAG &DAG, 1794 SmallVectorImpl<SDValue> &InVals) 1795 const { 1796 MachineFunction &MF = DAG.getMachineFunction(); 1797 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1798 1799 const Function* Fn = MF.getFunction(); 1800 if (Fn->hasExternalLinkage() && 1801 Subtarget->isTargetCygMing() && 1802 Fn->getName() == "main") 1803 FuncInfo->setForceFramePointer(true); 1804 1805 MachineFrameInfo *MFI = MF.getFrameInfo(); 1806 bool Is64Bit = Subtarget->is64Bit(); 1807 bool IsWin64 = Subtarget->isTargetWin64(); 1808 1809 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1810 "Var args not supported with calling convention fastcc or ghc"); 1811 1812 // Assign locations to all of the incoming arguments. 1813 SmallVector<CCValAssign, 16> ArgLocs; 1814 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1815 ArgLocs, *DAG.getContext()); 1816 1817 // Allocate shadow area for Win64 1818 if (IsWin64) { 1819 CCInfo.AllocateStack(32, 8); 1820 } 1821 1822 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1823 1824 unsigned LastVal = ~0U; 1825 SDValue ArgValue; 1826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1827 CCValAssign &VA = ArgLocs[i]; 1828 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1829 // places. 1830 assert(VA.getValNo() != LastVal && 1831 "Don't support value assigned to multiple locs yet"); 1832 (void)LastVal; 1833 LastVal = VA.getValNo(); 1834 1835 if (VA.isRegLoc()) { 1836 EVT RegVT = VA.getLocVT(); 1837 TargetRegisterClass *RC = NULL; 1838 if (RegVT == MVT::i32) 1839 RC = X86::GR32RegisterClass; 1840 else if (Is64Bit && RegVT == MVT::i64) 1841 RC = X86::GR64RegisterClass; 1842 else if (RegVT == MVT::f32) 1843 RC = X86::FR32RegisterClass; 1844 else if (RegVT == MVT::f64) 1845 RC = X86::FR64RegisterClass; 1846 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1847 RC = X86::VR256RegisterClass; 1848 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1849 RC = X86::VR128RegisterClass; 1850 else if (RegVT == MVT::x86mmx) 1851 RC = X86::VR64RegisterClass; 1852 else 1853 llvm_unreachable("Unknown argument type!"); 1854 1855 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1856 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1857 1858 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1859 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1860 // right size. 1861 if (VA.getLocInfo() == CCValAssign::SExt) 1862 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1863 DAG.getValueType(VA.getValVT())); 1864 else if (VA.getLocInfo() == CCValAssign::ZExt) 1865 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1866 DAG.getValueType(VA.getValVT())); 1867 else if (VA.getLocInfo() == CCValAssign::BCvt) 1868 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1869 1870 if (VA.isExtInLoc()) { 1871 // Handle MMX values passed in XMM regs. 1872 if (RegVT.isVector()) { 1873 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1874 ArgValue); 1875 } else 1876 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1877 } 1878 } else { 1879 assert(VA.isMemLoc()); 1880 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1881 } 1882 1883 // If value is passed via pointer - do a load. 1884 if (VA.getLocInfo() == CCValAssign::Indirect) 1885 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1886 MachinePointerInfo(), false, false, false, 0); 1887 1888 InVals.push_back(ArgValue); 1889 } 1890 1891 // The x86-64 ABI for returning structs by value requires that we copy 1892 // the sret argument into %rax for the return. Save the argument into 1893 // a virtual register so that we can access it from the return points. 1894 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1895 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1896 unsigned Reg = FuncInfo->getSRetReturnReg(); 1897 if (!Reg) { 1898 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1899 FuncInfo->setSRetReturnReg(Reg); 1900 } 1901 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1902 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1903 } 1904 1905 unsigned StackSize = CCInfo.getNextStackOffset(); 1906 // Align stack specially for tail calls. 1907 if (FuncIsMadeTailCallSafe(CallConv, 1908 MF.getTarget().Options.GuaranteedTailCallOpt)) 1909 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1910 1911 // If the function takes variable number of arguments, make a frame index for 1912 // the start of the first vararg value... for expansion of llvm.va_start. 1913 if (isVarArg) { 1914 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1915 CallConv != CallingConv::X86_ThisCall)) { 1916 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1917 } 1918 if (Is64Bit) { 1919 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1920 1921 // FIXME: We should really autogenerate these arrays 1922 static const unsigned GPR64ArgRegsWin64[] = { 1923 X86::RCX, X86::RDX, X86::R8, X86::R9 1924 }; 1925 static const unsigned GPR64ArgRegs64Bit[] = { 1926 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1927 }; 1928 static const unsigned XMMArgRegs64Bit[] = { 1929 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1930 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1931 }; 1932 const unsigned *GPR64ArgRegs; 1933 unsigned NumXMMRegs = 0; 1934 1935 if (IsWin64) { 1936 // The XMM registers which might contain var arg parameters are shadowed 1937 // in their paired GPR. So we only need to save the GPR to their home 1938 // slots. 1939 TotalNumIntRegs = 4; 1940 GPR64ArgRegs = GPR64ArgRegsWin64; 1941 } else { 1942 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1943 GPR64ArgRegs = GPR64ArgRegs64Bit; 1944 1945 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1946 TotalNumXMMRegs); 1947 } 1948 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1949 TotalNumIntRegs); 1950 1951 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1952 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1953 "SSE register cannot be used when SSE is disabled!"); 1954 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1955 NoImplicitFloatOps) && 1956 "SSE register cannot be used when SSE is disabled!"); 1957 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1958 !Subtarget->hasSSE1()) 1959 // Kernel mode asks for SSE to be disabled, so don't push them 1960 // on the stack. 1961 TotalNumXMMRegs = 0; 1962 1963 if (IsWin64) { 1964 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1965 // Get to the caller-allocated home save location. Add 8 to account 1966 // for the return address. 1967 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1968 FuncInfo->setRegSaveFrameIndex( 1969 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1970 // Fixup to set vararg frame on shadow area (4 x i64). 1971 if (NumIntRegs < 4) 1972 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1973 } else { 1974 // For X86-64, if there are vararg parameters that are passed via 1975 // registers, then we must store them to their spots on the stack so 1976 // they may be loaded by deferencing the result of va_next. 1977 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1978 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1979 FuncInfo->setRegSaveFrameIndex( 1980 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1981 false)); 1982 } 1983 1984 // Store the integer parameter registers. 1985 SmallVector<SDValue, 8> MemOps; 1986 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1987 getPointerTy()); 1988 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1989 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1990 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1991 DAG.getIntPtrConstant(Offset)); 1992 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1993 X86::GR64RegisterClass); 1994 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1995 SDValue Store = 1996 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1997 MachinePointerInfo::getFixedStack( 1998 FuncInfo->getRegSaveFrameIndex(), Offset), 1999 false, false, 0); 2000 MemOps.push_back(Store); 2001 Offset += 8; 2002 } 2003 2004 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2005 // Now store the XMM (fp + vector) parameter registers. 2006 SmallVector<SDValue, 11> SaveXMMOps; 2007 SaveXMMOps.push_back(Chain); 2008 2009 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2010 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2011 SaveXMMOps.push_back(ALVal); 2012 2013 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2014 FuncInfo->getRegSaveFrameIndex())); 2015 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2016 FuncInfo->getVarArgsFPOffset())); 2017 2018 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2019 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2020 X86::VR128RegisterClass); 2021 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2022 SaveXMMOps.push_back(Val); 2023 } 2024 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2025 MVT::Other, 2026 &SaveXMMOps[0], SaveXMMOps.size())); 2027 } 2028 2029 if (!MemOps.empty()) 2030 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2031 &MemOps[0], MemOps.size()); 2032 } 2033 } 2034 2035 // Some CCs need callee pop. 2036 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2037 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2038 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2039 } else { 2040 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2041 // If this is an sret function, the return should pop the hidden pointer. 2042 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 2043 FuncInfo->setBytesToPopOnReturn(4); 2044 } 2045 2046 if (!Is64Bit) { 2047 // RegSaveFrameIndex is X86-64 only. 2048 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2049 if (CallConv == CallingConv::X86_FastCall || 2050 CallConv == CallingConv::X86_ThisCall) 2051 // fastcc functions can't have varargs. 2052 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2053 } 2054 2055 FuncInfo->setArgumentStackSize(StackSize); 2056 2057 return Chain; 2058} 2059 2060SDValue 2061X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2062 SDValue StackPtr, SDValue Arg, 2063 DebugLoc dl, SelectionDAG &DAG, 2064 const CCValAssign &VA, 2065 ISD::ArgFlagsTy Flags) const { 2066 unsigned LocMemOffset = VA.getLocMemOffset(); 2067 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2068 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2069 if (Flags.isByVal()) 2070 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2071 2072 return DAG.getStore(Chain, dl, Arg, PtrOff, 2073 MachinePointerInfo::getStack(LocMemOffset), 2074 false, false, 0); 2075} 2076 2077/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2078/// optimization is performed and it is required. 2079SDValue 2080X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2081 SDValue &OutRetAddr, SDValue Chain, 2082 bool IsTailCall, bool Is64Bit, 2083 int FPDiff, DebugLoc dl) const { 2084 // Adjust the Return address stack slot. 2085 EVT VT = getPointerTy(); 2086 OutRetAddr = getReturnAddressFrameIndex(DAG); 2087 2088 // Load the "old" Return address. 2089 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2090 false, false, false, 0); 2091 return SDValue(OutRetAddr.getNode(), 1); 2092} 2093 2094/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2095/// optimization is performed and it is required (FPDiff!=0). 2096static SDValue 2097EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2098 SDValue Chain, SDValue RetAddrFrIdx, 2099 bool Is64Bit, int FPDiff, DebugLoc dl) { 2100 // Store the return address to the appropriate stack slot. 2101 if (!FPDiff) return Chain; 2102 // Calculate the new stack slot for the return address. 2103 int SlotSize = Is64Bit ? 8 : 4; 2104 int NewReturnAddrFI = 2105 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2106 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2107 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2108 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2109 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2110 false, false, 0); 2111 return Chain; 2112} 2113 2114SDValue 2115X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2116 CallingConv::ID CallConv, bool isVarArg, 2117 bool &isTailCall, 2118 const SmallVectorImpl<ISD::OutputArg> &Outs, 2119 const SmallVectorImpl<SDValue> &OutVals, 2120 const SmallVectorImpl<ISD::InputArg> &Ins, 2121 DebugLoc dl, SelectionDAG &DAG, 2122 SmallVectorImpl<SDValue> &InVals) const { 2123 MachineFunction &MF = DAG.getMachineFunction(); 2124 bool Is64Bit = Subtarget->is64Bit(); 2125 bool IsWin64 = Subtarget->isTargetWin64(); 2126 bool IsStructRet = CallIsStructReturn(Outs); 2127 bool IsSibcall = false; 2128 2129 if (isTailCall) { 2130 // Check if it's really possible to do a tail call. 2131 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2132 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2133 Outs, OutVals, Ins, DAG); 2134 2135 // Sibcalls are automatically detected tailcalls which do not require 2136 // ABI changes. 2137 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2138 IsSibcall = true; 2139 2140 if (isTailCall) 2141 ++NumTailCalls; 2142 } 2143 2144 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2145 "Var args not supported with calling convention fastcc or ghc"); 2146 2147 // Analyze operands of the call, assigning locations to each operand. 2148 SmallVector<CCValAssign, 16> ArgLocs; 2149 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2150 ArgLocs, *DAG.getContext()); 2151 2152 // Allocate shadow area for Win64 2153 if (IsWin64) { 2154 CCInfo.AllocateStack(32, 8); 2155 } 2156 2157 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2158 2159 // Get a count of how many bytes are to be pushed on the stack. 2160 unsigned NumBytes = CCInfo.getNextStackOffset(); 2161 if (IsSibcall) 2162 // This is a sibcall. The memory operands are available in caller's 2163 // own caller's stack. 2164 NumBytes = 0; 2165 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2166 IsTailCallConvention(CallConv)) 2167 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2168 2169 int FPDiff = 0; 2170 if (isTailCall && !IsSibcall) { 2171 // Lower arguments at fp - stackoffset + fpdiff. 2172 unsigned NumBytesCallerPushed = 2173 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2174 FPDiff = NumBytesCallerPushed - NumBytes; 2175 2176 // Set the delta of movement of the returnaddr stackslot. 2177 // But only set if delta is greater than previous delta. 2178 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2179 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2180 } 2181 2182 if (!IsSibcall) 2183 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2184 2185 SDValue RetAddrFrIdx; 2186 // Load return address for tail calls. 2187 if (isTailCall && FPDiff) 2188 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2189 Is64Bit, FPDiff, dl); 2190 2191 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2192 SmallVector<SDValue, 8> MemOpChains; 2193 SDValue StackPtr; 2194 2195 // Walk the register/memloc assignments, inserting copies/loads. In the case 2196 // of tail call optimization arguments are handle later. 2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2198 CCValAssign &VA = ArgLocs[i]; 2199 EVT RegVT = VA.getLocVT(); 2200 SDValue Arg = OutVals[i]; 2201 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2202 bool isByVal = Flags.isByVal(); 2203 2204 // Promote the value if needed. 2205 switch (VA.getLocInfo()) { 2206 default: llvm_unreachable("Unknown loc info!"); 2207 case CCValAssign::Full: break; 2208 case CCValAssign::SExt: 2209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2210 break; 2211 case CCValAssign::ZExt: 2212 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2213 break; 2214 case CCValAssign::AExt: 2215 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2216 // Special case: passing MMX values in XMM registers. 2217 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2218 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2219 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2220 } else 2221 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2222 break; 2223 case CCValAssign::BCvt: 2224 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2225 break; 2226 case CCValAssign::Indirect: { 2227 // Store the argument. 2228 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2229 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2230 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2231 MachinePointerInfo::getFixedStack(FI), 2232 false, false, 0); 2233 Arg = SpillSlot; 2234 break; 2235 } 2236 } 2237 2238 if (VA.isRegLoc()) { 2239 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2240 if (isVarArg && IsWin64) { 2241 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2242 // shadow reg if callee is a varargs function. 2243 unsigned ShadowReg = 0; 2244 switch (VA.getLocReg()) { 2245 case X86::XMM0: ShadowReg = X86::RCX; break; 2246 case X86::XMM1: ShadowReg = X86::RDX; break; 2247 case X86::XMM2: ShadowReg = X86::R8; break; 2248 case X86::XMM3: ShadowReg = X86::R9; break; 2249 } 2250 if (ShadowReg) 2251 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2252 } 2253 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2254 assert(VA.isMemLoc()); 2255 if (StackPtr.getNode() == 0) 2256 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2257 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2258 dl, DAG, VA, Flags)); 2259 } 2260 } 2261 2262 if (!MemOpChains.empty()) 2263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2264 &MemOpChains[0], MemOpChains.size()); 2265 2266 // Build a sequence of copy-to-reg nodes chained together with token chain 2267 // and flag operands which copy the outgoing args into registers. 2268 SDValue InFlag; 2269 // Tail call byval lowering might overwrite argument registers so in case of 2270 // tail call optimization the copies to registers are lowered later. 2271 if (!isTailCall) 2272 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2273 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2274 RegsToPass[i].second, InFlag); 2275 InFlag = Chain.getValue(1); 2276 } 2277 2278 if (Subtarget->isPICStyleGOT()) { 2279 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2280 // GOT pointer. 2281 if (!isTailCall) { 2282 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2283 DAG.getNode(X86ISD::GlobalBaseReg, 2284 DebugLoc(), getPointerTy()), 2285 InFlag); 2286 InFlag = Chain.getValue(1); 2287 } else { 2288 // If we are tail calling and generating PIC/GOT style code load the 2289 // address of the callee into ECX. The value in ecx is used as target of 2290 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2291 // for tail calls on PIC/GOT architectures. Normally we would just put the 2292 // address of GOT into ebx and then call target@PLT. But for tail calls 2293 // ebx would be restored (since ebx is callee saved) before jumping to the 2294 // target@PLT. 2295 2296 // Note: The actual moving to ECX is done further down. 2297 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2298 if (G && !G->getGlobal()->hasHiddenVisibility() && 2299 !G->getGlobal()->hasProtectedVisibility()) 2300 Callee = LowerGlobalAddress(Callee, DAG); 2301 else if (isa<ExternalSymbolSDNode>(Callee)) 2302 Callee = LowerExternalSymbol(Callee, DAG); 2303 } 2304 } 2305 2306 if (Is64Bit && isVarArg && !IsWin64) { 2307 // From AMD64 ABI document: 2308 // For calls that may call functions that use varargs or stdargs 2309 // (prototype-less calls or calls to functions containing ellipsis (...) in 2310 // the declaration) %al is used as hidden argument to specify the number 2311 // of SSE registers used. The contents of %al do not need to match exactly 2312 // the number of registers, but must be an ubound on the number of SSE 2313 // registers used and is in the range 0 - 8 inclusive. 2314 2315 // Count the number of XMM registers allocated. 2316 static const unsigned XMMArgRegs[] = { 2317 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2318 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2319 }; 2320 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2321 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2322 && "SSE registers cannot be used when SSE is disabled"); 2323 2324 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2325 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2326 InFlag = Chain.getValue(1); 2327 } 2328 2329 2330 // For tail calls lower the arguments to the 'real' stack slot. 2331 if (isTailCall) { 2332 // Force all the incoming stack arguments to be loaded from the stack 2333 // before any new outgoing arguments are stored to the stack, because the 2334 // outgoing stack slots may alias the incoming argument stack slots, and 2335 // the alias isn't otherwise explicit. This is slightly more conservative 2336 // than necessary, because it means that each store effectively depends 2337 // on every argument instead of just those arguments it would clobber. 2338 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2339 2340 SmallVector<SDValue, 8> MemOpChains2; 2341 SDValue FIN; 2342 int FI = 0; 2343 // Do not flag preceding copytoreg stuff together with the following stuff. 2344 InFlag = SDValue(); 2345 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2346 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2347 CCValAssign &VA = ArgLocs[i]; 2348 if (VA.isRegLoc()) 2349 continue; 2350 assert(VA.isMemLoc()); 2351 SDValue Arg = OutVals[i]; 2352 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2353 // Create frame index. 2354 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2355 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2356 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2357 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2358 2359 if (Flags.isByVal()) { 2360 // Copy relative to framepointer. 2361 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2362 if (StackPtr.getNode() == 0) 2363 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2364 getPointerTy()); 2365 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2366 2367 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2368 ArgChain, 2369 Flags, DAG, dl)); 2370 } else { 2371 // Store relative to framepointer. 2372 MemOpChains2.push_back( 2373 DAG.getStore(ArgChain, dl, Arg, FIN, 2374 MachinePointerInfo::getFixedStack(FI), 2375 false, false, 0)); 2376 } 2377 } 2378 } 2379 2380 if (!MemOpChains2.empty()) 2381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2382 &MemOpChains2[0], MemOpChains2.size()); 2383 2384 // Copy arguments to their registers. 2385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2386 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2387 RegsToPass[i].second, InFlag); 2388 InFlag = Chain.getValue(1); 2389 } 2390 InFlag =SDValue(); 2391 2392 // Store the return address to the appropriate stack slot. 2393 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2394 FPDiff, dl); 2395 } 2396 2397 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2398 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2399 // In the 64-bit large code model, we have to make all calls 2400 // through a register, since the call instruction's 32-bit 2401 // pc-relative offset may not be large enough to hold the whole 2402 // address. 2403 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2404 // If the callee is a GlobalAddress node (quite common, every direct call 2405 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2406 // it. 2407 2408 // We should use extra load for direct calls to dllimported functions in 2409 // non-JIT mode. 2410 const GlobalValue *GV = G->getGlobal(); 2411 if (!GV->hasDLLImportLinkage()) { 2412 unsigned char OpFlags = 0; 2413 bool ExtraLoad = false; 2414 unsigned WrapperKind = ISD::DELETED_NODE; 2415 2416 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2417 // external symbols most go through the PLT in PIC mode. If the symbol 2418 // has hidden or protected visibility, or if it is static or local, then 2419 // we don't need to use the PLT - we can directly call it. 2420 if (Subtarget->isTargetELF() && 2421 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2422 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2423 OpFlags = X86II::MO_PLT; 2424 } else if (Subtarget->isPICStyleStubAny() && 2425 (GV->isDeclaration() || GV->isWeakForLinker()) && 2426 (!Subtarget->getTargetTriple().isMacOSX() || 2427 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2428 // PC-relative references to external symbols should go through $stub, 2429 // unless we're building with the leopard linker or later, which 2430 // automatically synthesizes these stubs. 2431 OpFlags = X86II::MO_DARWIN_STUB; 2432 } else if (Subtarget->isPICStyleRIPRel() && 2433 isa<Function>(GV) && 2434 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2435 // If the function is marked as non-lazy, generate an indirect call 2436 // which loads from the GOT directly. This avoids runtime overhead 2437 // at the cost of eager binding (and one extra byte of encoding). 2438 OpFlags = X86II::MO_GOTPCREL; 2439 WrapperKind = X86ISD::WrapperRIP; 2440 ExtraLoad = true; 2441 } 2442 2443 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2444 G->getOffset(), OpFlags); 2445 2446 // Add a wrapper if needed. 2447 if (WrapperKind != ISD::DELETED_NODE) 2448 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2449 // Add extra indirection if needed. 2450 if (ExtraLoad) 2451 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2452 MachinePointerInfo::getGOT(), 2453 false, false, false, 0); 2454 } 2455 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2456 unsigned char OpFlags = 0; 2457 2458 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2459 // external symbols should go through the PLT. 2460 if (Subtarget->isTargetELF() && 2461 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2462 OpFlags = X86II::MO_PLT; 2463 } else if (Subtarget->isPICStyleStubAny() && 2464 (!Subtarget->getTargetTriple().isMacOSX() || 2465 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2466 // PC-relative references to external symbols should go through $stub, 2467 // unless we're building with the leopard linker or later, which 2468 // automatically synthesizes these stubs. 2469 OpFlags = X86II::MO_DARWIN_STUB; 2470 } 2471 2472 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2473 OpFlags); 2474 } 2475 2476 // Returns a chain & a flag for retval copy to use. 2477 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2478 SmallVector<SDValue, 8> Ops; 2479 2480 if (!IsSibcall && isTailCall) { 2481 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2482 DAG.getIntPtrConstant(0, true), InFlag); 2483 InFlag = Chain.getValue(1); 2484 } 2485 2486 Ops.push_back(Chain); 2487 Ops.push_back(Callee); 2488 2489 if (isTailCall) 2490 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2491 2492 // Add argument registers to the end of the list so that they are known live 2493 // into the call. 2494 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2495 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2496 RegsToPass[i].second.getValueType())); 2497 2498 // Add an implicit use GOT pointer in EBX. 2499 if (!isTailCall && Subtarget->isPICStyleGOT()) 2500 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2501 2502 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2503 if (Is64Bit && isVarArg && !IsWin64) 2504 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2505 2506 if (InFlag.getNode()) 2507 Ops.push_back(InFlag); 2508 2509 if (isTailCall) { 2510 // We used to do: 2511 //// If this is the first return lowered for this function, add the regs 2512 //// to the liveout set for the function. 2513 // This isn't right, although it's probably harmless on x86; liveouts 2514 // should be computed from returns not tail calls. Consider a void 2515 // function making a tail call to a function returning int. 2516 return DAG.getNode(X86ISD::TC_RETURN, dl, 2517 NodeTys, &Ops[0], Ops.size()); 2518 } 2519 2520 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2521 InFlag = Chain.getValue(1); 2522 2523 // Create the CALLSEQ_END node. 2524 unsigned NumBytesForCalleeToPush; 2525 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2526 getTargetMachine().Options.GuaranteedTailCallOpt)) 2527 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2528 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2529 // If this is a call to a struct-return function, the callee 2530 // pops the hidden struct pointer, so we have to push it back. 2531 // This is common for Darwin/X86, Linux & Mingw32 targets. 2532 NumBytesForCalleeToPush = 4; 2533 else 2534 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2535 2536 // Returns a flag for retval copy to use. 2537 if (!IsSibcall) { 2538 Chain = DAG.getCALLSEQ_END(Chain, 2539 DAG.getIntPtrConstant(NumBytes, true), 2540 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2541 true), 2542 InFlag); 2543 InFlag = Chain.getValue(1); 2544 } 2545 2546 // Handle result values, copying them out of physregs into vregs that we 2547 // return. 2548 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2549 Ins, dl, DAG, InVals); 2550} 2551 2552 2553//===----------------------------------------------------------------------===// 2554// Fast Calling Convention (tail call) implementation 2555//===----------------------------------------------------------------------===// 2556 2557// Like std call, callee cleans arguments, convention except that ECX is 2558// reserved for storing the tail called function address. Only 2 registers are 2559// free for argument passing (inreg). Tail call optimization is performed 2560// provided: 2561// * tailcallopt is enabled 2562// * caller/callee are fastcc 2563// On X86_64 architecture with GOT-style position independent code only local 2564// (within module) calls are supported at the moment. 2565// To keep the stack aligned according to platform abi the function 2566// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2567// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2568// If a tail called function callee has more arguments than the caller the 2569// caller needs to make sure that there is room to move the RETADDR to. This is 2570// achieved by reserving an area the size of the argument delta right after the 2571// original REtADDR, but before the saved framepointer or the spilled registers 2572// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2573// stack layout: 2574// arg1 2575// arg2 2576// RETADDR 2577// [ new RETADDR 2578// move area ] 2579// (possible EBP) 2580// ESI 2581// EDI 2582// local1 .. 2583 2584/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2585/// for a 16 byte align requirement. 2586unsigned 2587X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2588 SelectionDAG& DAG) const { 2589 MachineFunction &MF = DAG.getMachineFunction(); 2590 const TargetMachine &TM = MF.getTarget(); 2591 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2592 unsigned StackAlignment = TFI.getStackAlignment(); 2593 uint64_t AlignMask = StackAlignment - 1; 2594 int64_t Offset = StackSize; 2595 uint64_t SlotSize = TD->getPointerSize(); 2596 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2597 // Number smaller than 12 so just add the difference. 2598 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2599 } else { 2600 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2601 Offset = ((~AlignMask) & Offset) + StackAlignment + 2602 (StackAlignment-SlotSize); 2603 } 2604 return Offset; 2605} 2606 2607/// MatchingStackOffset - Return true if the given stack call argument is 2608/// already available in the same position (relatively) of the caller's 2609/// incoming argument stack. 2610static 2611bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2612 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2613 const X86InstrInfo *TII) { 2614 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2615 int FI = INT_MAX; 2616 if (Arg.getOpcode() == ISD::CopyFromReg) { 2617 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2618 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2619 return false; 2620 MachineInstr *Def = MRI->getVRegDef(VR); 2621 if (!Def) 2622 return false; 2623 if (!Flags.isByVal()) { 2624 if (!TII->isLoadFromStackSlot(Def, FI)) 2625 return false; 2626 } else { 2627 unsigned Opcode = Def->getOpcode(); 2628 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2629 Def->getOperand(1).isFI()) { 2630 FI = Def->getOperand(1).getIndex(); 2631 Bytes = Flags.getByValSize(); 2632 } else 2633 return false; 2634 } 2635 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2636 if (Flags.isByVal()) 2637 // ByVal argument is passed in as a pointer but it's now being 2638 // dereferenced. e.g. 2639 // define @foo(%struct.X* %A) { 2640 // tail call @bar(%struct.X* byval %A) 2641 // } 2642 return false; 2643 SDValue Ptr = Ld->getBasePtr(); 2644 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2645 if (!FINode) 2646 return false; 2647 FI = FINode->getIndex(); 2648 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2649 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2650 FI = FINode->getIndex(); 2651 Bytes = Flags.getByValSize(); 2652 } else 2653 return false; 2654 2655 assert(FI != INT_MAX); 2656 if (!MFI->isFixedObjectIndex(FI)) 2657 return false; 2658 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2659} 2660 2661/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2662/// for tail call optimization. Targets which want to do tail call 2663/// optimization should implement this function. 2664bool 2665X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2666 CallingConv::ID CalleeCC, 2667 bool isVarArg, 2668 bool isCalleeStructRet, 2669 bool isCallerStructRet, 2670 const SmallVectorImpl<ISD::OutputArg> &Outs, 2671 const SmallVectorImpl<SDValue> &OutVals, 2672 const SmallVectorImpl<ISD::InputArg> &Ins, 2673 SelectionDAG& DAG) const { 2674 if (!IsTailCallConvention(CalleeCC) && 2675 CalleeCC != CallingConv::C) 2676 return false; 2677 2678 // If -tailcallopt is specified, make fastcc functions tail-callable. 2679 const MachineFunction &MF = DAG.getMachineFunction(); 2680 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2681 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2682 bool CCMatch = CallerCC == CalleeCC; 2683 2684 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2685 if (IsTailCallConvention(CalleeCC) && CCMatch) 2686 return true; 2687 return false; 2688 } 2689 2690 // Look for obvious safe cases to perform tail call optimization that do not 2691 // require ABI changes. This is what gcc calls sibcall. 2692 2693 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2694 // emit a special epilogue. 2695 if (RegInfo->needsStackRealignment(MF)) 2696 return false; 2697 2698 // Also avoid sibcall optimization if either caller or callee uses struct 2699 // return semantics. 2700 if (isCalleeStructRet || isCallerStructRet) 2701 return false; 2702 2703 // An stdcall caller is expected to clean up its arguments; the callee 2704 // isn't going to do that. 2705 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2706 return false; 2707 2708 // Do not sibcall optimize vararg calls unless all arguments are passed via 2709 // registers. 2710 if (isVarArg && !Outs.empty()) { 2711 2712 // Optimizing for varargs on Win64 is unlikely to be safe without 2713 // additional testing. 2714 if (Subtarget->isTargetWin64()) 2715 return false; 2716 2717 SmallVector<CCValAssign, 16> ArgLocs; 2718 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2719 getTargetMachine(), ArgLocs, *DAG.getContext()); 2720 2721 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2723 if (!ArgLocs[i].isRegLoc()) 2724 return false; 2725 } 2726 2727 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2728 // stack. Therefore, if it's not used by the call it is not safe to optimize 2729 // this into a sibcall. 2730 bool Unused = false; 2731 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2732 if (!Ins[i].Used) { 2733 Unused = true; 2734 break; 2735 } 2736 } 2737 if (Unused) { 2738 SmallVector<CCValAssign, 16> RVLocs; 2739 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2740 getTargetMachine(), RVLocs, *DAG.getContext()); 2741 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2742 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2743 CCValAssign &VA = RVLocs[i]; 2744 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2745 return false; 2746 } 2747 } 2748 2749 // If the calling conventions do not match, then we'd better make sure the 2750 // results are returned in the same way as what the caller expects. 2751 if (!CCMatch) { 2752 SmallVector<CCValAssign, 16> RVLocs1; 2753 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2754 getTargetMachine(), RVLocs1, *DAG.getContext()); 2755 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2756 2757 SmallVector<CCValAssign, 16> RVLocs2; 2758 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2759 getTargetMachine(), RVLocs2, *DAG.getContext()); 2760 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2761 2762 if (RVLocs1.size() != RVLocs2.size()) 2763 return false; 2764 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2765 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2766 return false; 2767 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2768 return false; 2769 if (RVLocs1[i].isRegLoc()) { 2770 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2771 return false; 2772 } else { 2773 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2774 return false; 2775 } 2776 } 2777 } 2778 2779 // If the callee takes no arguments then go on to check the results of the 2780 // call. 2781 if (!Outs.empty()) { 2782 // Check if stack adjustment is needed. For now, do not do this if any 2783 // argument is passed on the stack. 2784 SmallVector<CCValAssign, 16> ArgLocs; 2785 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2786 getTargetMachine(), ArgLocs, *DAG.getContext()); 2787 2788 // Allocate shadow area for Win64 2789 if (Subtarget->isTargetWin64()) { 2790 CCInfo.AllocateStack(32, 8); 2791 } 2792 2793 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2794 if (CCInfo.getNextStackOffset()) { 2795 MachineFunction &MF = DAG.getMachineFunction(); 2796 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2797 return false; 2798 2799 // Check if the arguments are already laid out in the right way as 2800 // the caller's fixed stack objects. 2801 MachineFrameInfo *MFI = MF.getFrameInfo(); 2802 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2803 const X86InstrInfo *TII = 2804 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2805 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2806 CCValAssign &VA = ArgLocs[i]; 2807 SDValue Arg = OutVals[i]; 2808 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2809 if (VA.getLocInfo() == CCValAssign::Indirect) 2810 return false; 2811 if (!VA.isRegLoc()) { 2812 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2813 MFI, MRI, TII)) 2814 return false; 2815 } 2816 } 2817 } 2818 2819 // If the tailcall address may be in a register, then make sure it's 2820 // possible to register allocate for it. In 32-bit, the call address can 2821 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2822 // callee-saved registers are restored. These happen to be the same 2823 // registers used to pass 'inreg' arguments so watch out for those. 2824 if (!Subtarget->is64Bit() && 2825 !isa<GlobalAddressSDNode>(Callee) && 2826 !isa<ExternalSymbolSDNode>(Callee)) { 2827 unsigned NumInRegs = 0; 2828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2829 CCValAssign &VA = ArgLocs[i]; 2830 if (!VA.isRegLoc()) 2831 continue; 2832 unsigned Reg = VA.getLocReg(); 2833 switch (Reg) { 2834 default: break; 2835 case X86::EAX: case X86::EDX: case X86::ECX: 2836 if (++NumInRegs == 3) 2837 return false; 2838 break; 2839 } 2840 } 2841 } 2842 } 2843 2844 return true; 2845} 2846 2847FastISel * 2848X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2849 return X86::createFastISel(funcInfo); 2850} 2851 2852 2853//===----------------------------------------------------------------------===// 2854// Other Lowering Hooks 2855//===----------------------------------------------------------------------===// 2856 2857static bool MayFoldLoad(SDValue Op) { 2858 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2859} 2860 2861static bool MayFoldIntoStore(SDValue Op) { 2862 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2863} 2864 2865static bool isTargetShuffle(unsigned Opcode) { 2866 switch(Opcode) { 2867 default: return false; 2868 case X86ISD::PSHUFD: 2869 case X86ISD::PSHUFHW: 2870 case X86ISD::PSHUFLW: 2871 case X86ISD::SHUFP: 2872 case X86ISD::PALIGN: 2873 case X86ISD::MOVLHPS: 2874 case X86ISD::MOVLHPD: 2875 case X86ISD::MOVHLPS: 2876 case X86ISD::MOVLPS: 2877 case X86ISD::MOVLPD: 2878 case X86ISD::MOVSHDUP: 2879 case X86ISD::MOVSLDUP: 2880 case X86ISD::MOVDDUP: 2881 case X86ISD::MOVSS: 2882 case X86ISD::MOVSD: 2883 case X86ISD::UNPCKL: 2884 case X86ISD::UNPCKH: 2885 case X86ISD::VPERMILP: 2886 case X86ISD::VPERM2X128: 2887 return true; 2888 } 2889 return false; 2890} 2891 2892static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2893 SDValue V1, SelectionDAG &DAG) { 2894 switch(Opc) { 2895 default: llvm_unreachable("Unknown x86 shuffle node"); 2896 case X86ISD::MOVSHDUP: 2897 case X86ISD::MOVSLDUP: 2898 case X86ISD::MOVDDUP: 2899 return DAG.getNode(Opc, dl, VT, V1); 2900 } 2901 2902 return SDValue(); 2903} 2904 2905static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2906 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2907 switch(Opc) { 2908 default: llvm_unreachable("Unknown x86 shuffle node"); 2909 case X86ISD::PSHUFD: 2910 case X86ISD::PSHUFHW: 2911 case X86ISD::PSHUFLW: 2912 case X86ISD::VPERMILP: 2913 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2914 } 2915 2916 return SDValue(); 2917} 2918 2919static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2920 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2921 switch(Opc) { 2922 default: llvm_unreachable("Unknown x86 shuffle node"); 2923 case X86ISD::PALIGN: 2924 case X86ISD::SHUFP: 2925 case X86ISD::VPERM2X128: 2926 return DAG.getNode(Opc, dl, VT, V1, V2, 2927 DAG.getConstant(TargetMask, MVT::i8)); 2928 } 2929 return SDValue(); 2930} 2931 2932static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2933 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2934 switch(Opc) { 2935 default: llvm_unreachable("Unknown x86 shuffle node"); 2936 case X86ISD::MOVLHPS: 2937 case X86ISD::MOVLHPD: 2938 case X86ISD::MOVHLPS: 2939 case X86ISD::MOVLPS: 2940 case X86ISD::MOVLPD: 2941 case X86ISD::MOVSS: 2942 case X86ISD::MOVSD: 2943 case X86ISD::UNPCKL: 2944 case X86ISD::UNPCKH: 2945 return DAG.getNode(Opc, dl, VT, V1, V2); 2946 } 2947 return SDValue(); 2948} 2949 2950SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2951 MachineFunction &MF = DAG.getMachineFunction(); 2952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2953 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2954 2955 if (ReturnAddrIndex == 0) { 2956 // Set up a frame object for the return address. 2957 uint64_t SlotSize = TD->getPointerSize(); 2958 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2959 false); 2960 FuncInfo->setRAIndex(ReturnAddrIndex); 2961 } 2962 2963 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2964} 2965 2966 2967bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2968 bool hasSymbolicDisplacement) { 2969 // Offset should fit into 32 bit immediate field. 2970 if (!isInt<32>(Offset)) 2971 return false; 2972 2973 // If we don't have a symbolic displacement - we don't have any extra 2974 // restrictions. 2975 if (!hasSymbolicDisplacement) 2976 return true; 2977 2978 // FIXME: Some tweaks might be needed for medium code model. 2979 if (M != CodeModel::Small && M != CodeModel::Kernel) 2980 return false; 2981 2982 // For small code model we assume that latest object is 16MB before end of 31 2983 // bits boundary. We may also accept pretty large negative constants knowing 2984 // that all objects are in the positive half of address space. 2985 if (M == CodeModel::Small && Offset < 16*1024*1024) 2986 return true; 2987 2988 // For kernel code model we know that all object resist in the negative half 2989 // of 32bits address space. We may not accept negative offsets, since they may 2990 // be just off and we may accept pretty large positive ones. 2991 if (M == CodeModel::Kernel && Offset > 0) 2992 return true; 2993 2994 return false; 2995} 2996 2997/// isCalleePop - Determines whether the callee is required to pop its 2998/// own arguments. Callee pop is necessary to support tail calls. 2999bool X86::isCalleePop(CallingConv::ID CallingConv, 3000 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3001 if (IsVarArg) 3002 return false; 3003 3004 switch (CallingConv) { 3005 default: 3006 return false; 3007 case CallingConv::X86_StdCall: 3008 return !is64Bit; 3009 case CallingConv::X86_FastCall: 3010 return !is64Bit; 3011 case CallingConv::X86_ThisCall: 3012 return !is64Bit; 3013 case CallingConv::Fast: 3014 return TailCallOpt; 3015 case CallingConv::GHC: 3016 return TailCallOpt; 3017 } 3018} 3019 3020/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3021/// specific condition code, returning the condition code and the LHS/RHS of the 3022/// comparison to make. 3023static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3024 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3025 if (!isFP) { 3026 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3027 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3028 // X > -1 -> X == 0, jump !sign. 3029 RHS = DAG.getConstant(0, RHS.getValueType()); 3030 return X86::COND_NS; 3031 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3032 // X < 0 -> X == 0, jump on sign. 3033 return X86::COND_S; 3034 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3035 // X < 1 -> X <= 0 3036 RHS = DAG.getConstant(0, RHS.getValueType()); 3037 return X86::COND_LE; 3038 } 3039 } 3040 3041 switch (SetCCOpcode) { 3042 default: llvm_unreachable("Invalid integer condition!"); 3043 case ISD::SETEQ: return X86::COND_E; 3044 case ISD::SETGT: return X86::COND_G; 3045 case ISD::SETGE: return X86::COND_GE; 3046 case ISD::SETLT: return X86::COND_L; 3047 case ISD::SETLE: return X86::COND_LE; 3048 case ISD::SETNE: return X86::COND_NE; 3049 case ISD::SETULT: return X86::COND_B; 3050 case ISD::SETUGT: return X86::COND_A; 3051 case ISD::SETULE: return X86::COND_BE; 3052 case ISD::SETUGE: return X86::COND_AE; 3053 } 3054 } 3055 3056 // First determine if it is required or is profitable to flip the operands. 3057 3058 // If LHS is a foldable load, but RHS is not, flip the condition. 3059 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3060 !ISD::isNON_EXTLoad(RHS.getNode())) { 3061 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3062 std::swap(LHS, RHS); 3063 } 3064 3065 switch (SetCCOpcode) { 3066 default: break; 3067 case ISD::SETOLT: 3068 case ISD::SETOLE: 3069 case ISD::SETUGT: 3070 case ISD::SETUGE: 3071 std::swap(LHS, RHS); 3072 break; 3073 } 3074 3075 // On a floating point condition, the flags are set as follows: 3076 // ZF PF CF op 3077 // 0 | 0 | 0 | X > Y 3078 // 0 | 0 | 1 | X < Y 3079 // 1 | 0 | 0 | X == Y 3080 // 1 | 1 | 1 | unordered 3081 switch (SetCCOpcode) { 3082 default: llvm_unreachable("Condcode should be pre-legalized away"); 3083 case ISD::SETUEQ: 3084 case ISD::SETEQ: return X86::COND_E; 3085 case ISD::SETOLT: // flipped 3086 case ISD::SETOGT: 3087 case ISD::SETGT: return X86::COND_A; 3088 case ISD::SETOLE: // flipped 3089 case ISD::SETOGE: 3090 case ISD::SETGE: return X86::COND_AE; 3091 case ISD::SETUGT: // flipped 3092 case ISD::SETULT: 3093 case ISD::SETLT: return X86::COND_B; 3094 case ISD::SETUGE: // flipped 3095 case ISD::SETULE: 3096 case ISD::SETLE: return X86::COND_BE; 3097 case ISD::SETONE: 3098 case ISD::SETNE: return X86::COND_NE; 3099 case ISD::SETUO: return X86::COND_P; 3100 case ISD::SETO: return X86::COND_NP; 3101 case ISD::SETOEQ: 3102 case ISD::SETUNE: return X86::COND_INVALID; 3103 } 3104} 3105 3106/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3107/// code. Current x86 isa includes the following FP cmov instructions: 3108/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3109static bool hasFPCMov(unsigned X86CC) { 3110 switch (X86CC) { 3111 default: 3112 return false; 3113 case X86::COND_B: 3114 case X86::COND_BE: 3115 case X86::COND_E: 3116 case X86::COND_P: 3117 case X86::COND_A: 3118 case X86::COND_AE: 3119 case X86::COND_NE: 3120 case X86::COND_NP: 3121 return true; 3122 } 3123} 3124 3125/// isFPImmLegal - Returns true if the target can instruction select the 3126/// specified FP immediate natively. If false, the legalizer will 3127/// materialize the FP immediate as a load from a constant pool. 3128bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3129 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3130 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3131 return true; 3132 } 3133 return false; 3134} 3135 3136/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3137/// the specified range (L, H]. 3138static bool isUndefOrInRange(int Val, int Low, int Hi) { 3139 return (Val < 0) || (Val >= Low && Val < Hi); 3140} 3141 3142/// isUndefOrInRange - Return true if every element in Mask, begining 3143/// from position Pos and ending in Pos+Size, falls within the specified 3144/// range (L, L+Pos]. or is undef. 3145static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3146 int Pos, int Size, int Low, int Hi) { 3147 for (int i = Pos, e = Pos+Size; i != e; ++i) 3148 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3149 return false; 3150 return true; 3151} 3152 3153/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3154/// specified value. 3155static bool isUndefOrEqual(int Val, int CmpVal) { 3156 if (Val < 0 || Val == CmpVal) 3157 return true; 3158 return false; 3159} 3160 3161/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3162/// from position Pos and ending in Pos+Size, falls within the specified 3163/// sequential range (L, L+Pos]. or is undef. 3164static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3165 int Pos, int Size, int Low) { 3166 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3167 if (!isUndefOrEqual(Mask[i], Low)) 3168 return false; 3169 return true; 3170} 3171 3172/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3173/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3174/// the second operand. 3175static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3176 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3177 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3178 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3179 return (Mask[0] < 2 && Mask[1] < 2); 3180 return false; 3181} 3182 3183bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3184 SmallVector<int, 8> M; 3185 N->getMask(M); 3186 return ::isPSHUFDMask(M, N->getValueType(0)); 3187} 3188 3189/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3190/// is suitable for input to PSHUFHW. 3191static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3192 if (VT != MVT::v8i16) 3193 return false; 3194 3195 // Lower quadword copied in order or undef. 3196 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3197 return false; 3198 3199 // Upper quadword shuffled. 3200 for (unsigned i = 4; i != 8; ++i) 3201 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3202 return false; 3203 3204 return true; 3205} 3206 3207bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3208 SmallVector<int, 8> M; 3209 N->getMask(M); 3210 return ::isPSHUFHWMask(M, N->getValueType(0)); 3211} 3212 3213/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3214/// is suitable for input to PSHUFLW. 3215static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3216 if (VT != MVT::v8i16) 3217 return false; 3218 3219 // Upper quadword copied in order. 3220 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3221 return false; 3222 3223 // Lower quadword shuffled. 3224 for (unsigned i = 0; i != 4; ++i) 3225 if (Mask[i] >= 4) 3226 return false; 3227 3228 return true; 3229} 3230 3231bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3232 SmallVector<int, 8> M; 3233 N->getMask(M); 3234 return ::isPSHUFLWMask(M, N->getValueType(0)); 3235} 3236 3237/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3238/// is suitable for input to PALIGNR. 3239static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3240 bool hasSSSE3) { 3241 int i, e = VT.getVectorNumElements(); 3242 if (VT.getSizeInBits() != 128) 3243 return false; 3244 3245 // Do not handle v2i64 / v2f64 shuffles with palignr. 3246 if (e < 4 || !hasSSSE3) 3247 return false; 3248 3249 for (i = 0; i != e; ++i) 3250 if (Mask[i] >= 0) 3251 break; 3252 3253 // All undef, not a palignr. 3254 if (i == e) 3255 return false; 3256 3257 // Make sure we're shifting in the right direction. 3258 if (Mask[i] <= i) 3259 return false; 3260 3261 int s = Mask[i] - i; 3262 3263 // Check the rest of the elements to see if they are consecutive. 3264 for (++i; i != e; ++i) { 3265 int m = Mask[i]; 3266 if (m >= 0 && m != s+i) 3267 return false; 3268 } 3269 return true; 3270} 3271 3272/// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand 3273/// specifies a shuffle of elements that is suitable for input to 256-bit 3274/// VSHUFPSY. 3275static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3276 bool HasAVX, bool Commuted = false) { 3277 int NumElems = VT.getVectorNumElements(); 3278 3279 if (!HasAVX || VT.getSizeInBits() != 256) 3280 return false; 3281 3282 if (NumElems != 4 && NumElems != 8) 3283 return false; 3284 3285 // VSHUFPSY divides the resulting vector into 4 chunks. 3286 // The sources are also splitted into 4 chunks, and each destination 3287 // chunk must come from a different source chunk. 3288 // 3289 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3290 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3291 // 3292 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3293 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3294 // 3295 // VSHUFPDY divides the resulting vector into 4 chunks. 3296 // The sources are also splitted into 4 chunks, and each destination 3297 // chunk must come from a different source chunk. 3298 // 3299 // SRC1 => X3 X2 X1 X0 3300 // SRC2 => Y3 Y2 Y1 Y0 3301 // 3302 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3303 // 3304 unsigned QuarterSize = NumElems/4; 3305 unsigned HalfSize = QuarterSize*2; 3306 for (unsigned l = 0; l != 2; ++l) { 3307 unsigned LaneStart = l*HalfSize; 3308 for (unsigned s = 0; s != 2; ++s) { 3309 unsigned QuarterStart = s*QuarterSize; 3310 unsigned Src = (Commuted) ? (1-s) : s; 3311 unsigned SrcStart = Src*NumElems + LaneStart; 3312 for (unsigned i = 0; i != QuarterSize; ++i) { 3313 int Idx = Mask[i+QuarterStart+LaneStart]; 3314 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize)) 3315 return false; 3316 // For VSHUFPSY, the mask of the second half must be the same as the 3317 // first but with the appropriate offsets. This works in the same way as 3318 // VPERMILPS works with masks. 3319 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0) 3320 continue; 3321 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart)) 3322 return false; 3323 } 3324 } 3325 } 3326 3327 return true; 3328} 3329 3330/// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle 3331/// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions. 3332static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) { 3333 EVT VT = SVOp->getValueType(0); 3334 unsigned NumElems = VT.getVectorNumElements(); 3335 3336 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types"); 3337 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types"); 3338 3339 unsigned HalfSize = NumElems/2; 3340 unsigned Mul = (NumElems == 8) ? 2 : 1; 3341 unsigned Mask = 0; 3342 for (unsigned i = 0; i != NumElems; ++i) { 3343 int Elt = SVOp->getMaskElt(i); 3344 if (Elt < 0) 3345 continue; 3346 Elt %= HalfSize; 3347 unsigned Shamt = i; 3348 // For VSHUFPSY, the mask of the first half must be equal to the second one. 3349 if (NumElems == 8) Shamt %= HalfSize; 3350 Mask |= Elt << (Shamt*Mul); 3351 } 3352 3353 return Mask; 3354} 3355 3356/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3357/// the two vector operands have swapped position. 3358static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3359 unsigned NumElems) { 3360 for (unsigned i = 0; i != NumElems; ++i) { 3361 int idx = Mask[i]; 3362 if (idx < 0) 3363 continue; 3364 else if (idx < (int)NumElems) 3365 Mask[i] = idx + NumElems; 3366 else 3367 Mask[i] = idx - NumElems; 3368 } 3369} 3370 3371/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3372/// specifies a shuffle of elements that is suitable for input to 128-bit 3373/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3374/// reverse of what x86 shuffles want. 3375static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT, 3376 bool Commuted = false) { 3377 unsigned NumElems = VT.getVectorNumElements(); 3378 3379 if (VT.getSizeInBits() != 128) 3380 return false; 3381 3382 if (NumElems != 2 && NumElems != 4) 3383 return false; 3384 3385 unsigned Half = NumElems / 2; 3386 unsigned SrcStart = Commuted ? NumElems : 0; 3387 for (unsigned i = 0; i != Half; ++i) 3388 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3389 return false; 3390 SrcStart = Commuted ? 0 : NumElems; 3391 for (unsigned i = Half; i != NumElems; ++i) 3392 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3393 return false; 3394 3395 return true; 3396} 3397 3398bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3399 SmallVector<int, 8> M; 3400 N->getMask(M); 3401 return ::isSHUFPMask(M, N->getValueType(0)); 3402} 3403 3404/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3405/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3406bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3407 EVT VT = N->getValueType(0); 3408 unsigned NumElems = VT.getVectorNumElements(); 3409 3410 if (VT.getSizeInBits() != 128) 3411 return false; 3412 3413 if (NumElems != 4) 3414 return false; 3415 3416 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3417 return isUndefOrEqual(N->getMaskElt(0), 6) && 3418 isUndefOrEqual(N->getMaskElt(1), 7) && 3419 isUndefOrEqual(N->getMaskElt(2), 2) && 3420 isUndefOrEqual(N->getMaskElt(3), 3); 3421} 3422 3423/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3424/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3425/// <2, 3, 2, 3> 3426bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3427 EVT VT = N->getValueType(0); 3428 unsigned NumElems = VT.getVectorNumElements(); 3429 3430 if (VT.getSizeInBits() != 128) 3431 return false; 3432 3433 if (NumElems != 4) 3434 return false; 3435 3436 return isUndefOrEqual(N->getMaskElt(0), 2) && 3437 isUndefOrEqual(N->getMaskElt(1), 3) && 3438 isUndefOrEqual(N->getMaskElt(2), 2) && 3439 isUndefOrEqual(N->getMaskElt(3), 3); 3440} 3441 3442/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3443/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3444bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3445 EVT VT = N->getValueType(0); 3446 3447 if (VT.getSizeInBits() != 128) 3448 return false; 3449 3450 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3451 3452 if (NumElems != 2 && NumElems != 4) 3453 return false; 3454 3455 for (unsigned i = 0; i < NumElems/2; ++i) 3456 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3457 return false; 3458 3459 for (unsigned i = NumElems/2; i < NumElems; ++i) 3460 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3461 return false; 3462 3463 return true; 3464} 3465 3466/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3467/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3468bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3469 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3470 3471 if ((NumElems != 2 && NumElems != 4) 3472 || N->getValueType(0).getSizeInBits() > 128) 3473 return false; 3474 3475 for (unsigned i = 0; i < NumElems/2; ++i) 3476 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3477 return false; 3478 3479 for (unsigned i = 0; i < NumElems/2; ++i) 3480 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3481 return false; 3482 3483 return true; 3484} 3485 3486/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3487/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3488static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3489 bool HasAVX2, bool V2IsSplat = false) { 3490 unsigned NumElts = VT.getVectorNumElements(); 3491 3492 assert((VT.is128BitVector() || VT.is256BitVector()) && 3493 "Unsupported vector type for unpckh"); 3494 3495 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3496 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3497 return false; 3498 3499 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3500 // independently on 128-bit lanes. 3501 unsigned NumLanes = VT.getSizeInBits()/128; 3502 unsigned NumLaneElts = NumElts/NumLanes; 3503 3504 for (unsigned l = 0; l != NumLanes; ++l) { 3505 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3506 i != (l+1)*NumLaneElts; 3507 i += 2, ++j) { 3508 int BitI = Mask[i]; 3509 int BitI1 = Mask[i+1]; 3510 if (!isUndefOrEqual(BitI, j)) 3511 return false; 3512 if (V2IsSplat) { 3513 if (!isUndefOrEqual(BitI1, NumElts)) 3514 return false; 3515 } else { 3516 if (!isUndefOrEqual(BitI1, j + NumElts)) 3517 return false; 3518 } 3519 } 3520 } 3521 3522 return true; 3523} 3524 3525bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3526 SmallVector<int, 8> M; 3527 N->getMask(M); 3528 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3529} 3530 3531/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3532/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3533static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3534 bool HasAVX2, bool V2IsSplat = false) { 3535 unsigned NumElts = VT.getVectorNumElements(); 3536 3537 assert((VT.is128BitVector() || VT.is256BitVector()) && 3538 "Unsupported vector type for unpckh"); 3539 3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3542 return false; 3543 3544 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3545 // independently on 128-bit lanes. 3546 unsigned NumLanes = VT.getSizeInBits()/128; 3547 unsigned NumLaneElts = NumElts/NumLanes; 3548 3549 for (unsigned l = 0; l != NumLanes; ++l) { 3550 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3551 i != (l+1)*NumLaneElts; i += 2, ++j) { 3552 int BitI = Mask[i]; 3553 int BitI1 = Mask[i+1]; 3554 if (!isUndefOrEqual(BitI, j)) 3555 return false; 3556 if (V2IsSplat) { 3557 if (isUndefOrEqual(BitI1, NumElts)) 3558 return false; 3559 } else { 3560 if (!isUndefOrEqual(BitI1, j+NumElts)) 3561 return false; 3562 } 3563 } 3564 } 3565 return true; 3566} 3567 3568bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3569 SmallVector<int, 8> M; 3570 N->getMask(M); 3571 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3572} 3573 3574/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3575/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3576/// <0, 0, 1, 1> 3577static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3578 bool HasAVX2) { 3579 unsigned NumElts = VT.getVectorNumElements(); 3580 3581 assert((VT.is128BitVector() || VT.is256BitVector()) && 3582 "Unsupported vector type for unpckh"); 3583 3584 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3585 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3586 return false; 3587 3588 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3589 // FIXME: Need a better way to get rid of this, there's no latency difference 3590 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3591 // the former later. We should also remove the "_undef" special mask. 3592 if (NumElts == 4 && VT.getSizeInBits() == 256) 3593 return false; 3594 3595 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3596 // independently on 128-bit lanes. 3597 unsigned NumLanes = VT.getSizeInBits()/128; 3598 unsigned NumLaneElts = NumElts/NumLanes; 3599 3600 for (unsigned l = 0; l != NumLanes; ++l) { 3601 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3602 i != (l+1)*NumLaneElts; 3603 i += 2, ++j) { 3604 int BitI = Mask[i]; 3605 int BitI1 = Mask[i+1]; 3606 3607 if (!isUndefOrEqual(BitI, j)) 3608 return false; 3609 if (!isUndefOrEqual(BitI1, j)) 3610 return false; 3611 } 3612 } 3613 3614 return true; 3615} 3616 3617bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3618 SmallVector<int, 8> M; 3619 N->getMask(M); 3620 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0), HasAVX2); 3621} 3622 3623/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3624/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3625/// <2, 2, 3, 3> 3626static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3627 bool HasAVX2) { 3628 unsigned NumElts = VT.getVectorNumElements(); 3629 3630 assert((VT.is128BitVector() || VT.is256BitVector()) && 3631 "Unsupported vector type for unpckh"); 3632 3633 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3634 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3635 return false; 3636 3637 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3638 // independently on 128-bit lanes. 3639 unsigned NumLanes = VT.getSizeInBits()/128; 3640 unsigned NumLaneElts = NumElts/NumLanes; 3641 3642 for (unsigned l = 0; l != NumLanes; ++l) { 3643 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3644 i != (l+1)*NumLaneElts; i += 2, ++j) { 3645 int BitI = Mask[i]; 3646 int BitI1 = Mask[i+1]; 3647 if (!isUndefOrEqual(BitI, j)) 3648 return false; 3649 if (!isUndefOrEqual(BitI1, j)) 3650 return false; 3651 } 3652 } 3653 return true; 3654} 3655 3656bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3657 SmallVector<int, 8> M; 3658 N->getMask(M); 3659 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0), HasAVX2); 3660} 3661 3662/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3663/// specifies a shuffle of elements that is suitable for input to MOVSS, 3664/// MOVSD, and MOVD, i.e. setting the lowest element. 3665static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3666 if (VT.getVectorElementType().getSizeInBits() < 32) 3667 return false; 3668 if (VT.getSizeInBits() == 256) 3669 return false; 3670 3671 unsigned NumElts = VT.getVectorNumElements(); 3672 3673 if (!isUndefOrEqual(Mask[0], NumElts)) 3674 return false; 3675 3676 for (unsigned i = 1; i != NumElts; ++i) 3677 if (!isUndefOrEqual(Mask[i], i)) 3678 return false; 3679 3680 return true; 3681} 3682 3683bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3684 SmallVector<int, 8> M; 3685 N->getMask(M); 3686 return ::isMOVLMask(M, N->getValueType(0)); 3687} 3688 3689/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3690/// as permutations between 128-bit chunks or halves. As an example: this 3691/// shuffle bellow: 3692/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3693/// The first half comes from the second half of V1 and the second half from the 3694/// the second half of V2. 3695static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3696 bool HasAVX) { 3697 if (!HasAVX || VT.getSizeInBits() != 256) 3698 return false; 3699 3700 // The shuffle result is divided into half A and half B. In total the two 3701 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3702 // B must come from C, D, E or F. 3703 unsigned HalfSize = VT.getVectorNumElements()/2; 3704 bool MatchA = false, MatchB = false; 3705 3706 // Check if A comes from one of C, D, E, F. 3707 for (unsigned Half = 0; Half != 4; ++Half) { 3708 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3709 MatchA = true; 3710 break; 3711 } 3712 } 3713 3714 // Check if B comes from one of C, D, E, F. 3715 for (unsigned Half = 0; Half != 4; ++Half) { 3716 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3717 MatchB = true; 3718 break; 3719 } 3720 } 3721 3722 return MatchA && MatchB; 3723} 3724 3725/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3726/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3727static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3728 EVT VT = SVOp->getValueType(0); 3729 3730 unsigned HalfSize = VT.getVectorNumElements()/2; 3731 3732 unsigned FstHalf = 0, SndHalf = 0; 3733 for (unsigned i = 0; i < HalfSize; ++i) { 3734 if (SVOp->getMaskElt(i) > 0) { 3735 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3736 break; 3737 } 3738 } 3739 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3740 if (SVOp->getMaskElt(i) > 0) { 3741 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3742 break; 3743 } 3744 } 3745 3746 return (FstHalf | (SndHalf << 4)); 3747} 3748 3749/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3750/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3751/// Note that VPERMIL mask matching is different depending whether theunderlying 3752/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3753/// to the same elements of the low, but to the higher half of the source. 3754/// In VPERMILPD the two lanes could be shuffled independently of each other 3755/// with the same restriction that lanes can't be crossed. 3756static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT, 3757 bool HasAVX) { 3758 if (!HasAVX) 3759 return false; 3760 3761 unsigned NumElts = VT.getVectorNumElements(); 3762 // Only match 256-bit with 32/64-bit types 3763 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3764 return false; 3765 3766 unsigned NumLanes = VT.getSizeInBits()/128; 3767 unsigned LaneSize = NumElts/NumLanes; 3768 for (unsigned l = 0; l != NumLanes; ++l) { 3769 unsigned LaneStart = l*LaneSize; 3770 for (unsigned i = 0; i != LaneSize; ++i) { 3771 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize)) 3772 return false; 3773 if (NumElts == 4 || l == 0) 3774 continue; 3775 // VPERMILPS handling 3776 if (Mask[i] < 0) 3777 continue; 3778 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart)) 3779 return false; 3780 } 3781 } 3782 3783 return true; 3784} 3785 3786/// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle 3787/// the specified VECTOR_MASK mask with VPERMILPS/D* instructions. 3788static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) { 3789 EVT VT = SVOp->getValueType(0); 3790 3791 unsigned NumElts = VT.getVectorNumElements(); 3792 unsigned NumLanes = VT.getSizeInBits()/128; 3793 unsigned LaneSize = NumElts/NumLanes; 3794 3795 // Although the mask is equal for both lanes do it twice to get the cases 3796 // where a mask will match because the same mask element is undef on the 3797 // first half but valid on the second. This would get pathological cases 3798 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3799 unsigned Shift = (LaneSize == 4) ? 2 : 1; 3800 unsigned Mask = 0; 3801 for (unsigned i = 0; i != NumElts; ++i) { 3802 int MaskElt = SVOp->getMaskElt(i); 3803 if (MaskElt < 0) 3804 continue; 3805 MaskElt %= LaneSize; 3806 unsigned Shamt = i; 3807 // VPERMILPSY, the mask of the first half must be equal to the second one 3808 if (NumElts == 8) Shamt %= LaneSize; 3809 Mask |= MaskElt << (Shamt*Shift); 3810 } 3811 3812 return Mask; 3813} 3814 3815/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3816/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3817/// element of vector 2 and the other elements to come from vector 1 in order. 3818static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3819 bool V2IsSplat = false, bool V2IsUndef = false) { 3820 unsigned NumOps = VT.getVectorNumElements(); 3821 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3822 return false; 3823 3824 if (!isUndefOrEqual(Mask[0], 0)) 3825 return false; 3826 3827 for (unsigned i = 1; i != NumOps; ++i) 3828 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3829 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3830 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3831 return false; 3832 3833 return true; 3834} 3835 3836static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3837 bool V2IsUndef = false) { 3838 SmallVector<int, 8> M; 3839 N->getMask(M); 3840 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3841} 3842 3843/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3844/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3845/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3846bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3847 const X86Subtarget *Subtarget) { 3848 if (!Subtarget->hasSSE3()) 3849 return false; 3850 3851 // The second vector must be undef 3852 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3853 return false; 3854 3855 EVT VT = N->getValueType(0); 3856 unsigned NumElems = VT.getVectorNumElements(); 3857 3858 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3859 (VT.getSizeInBits() == 256 && NumElems != 8)) 3860 return false; 3861 3862 // "i+1" is the value the indexed mask element must have 3863 for (unsigned i = 0; i < NumElems; i += 2) 3864 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3865 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3866 return false; 3867 3868 return true; 3869} 3870 3871/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3872/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3873/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3874bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3875 const X86Subtarget *Subtarget) { 3876 if (!Subtarget->hasSSE3()) 3877 return false; 3878 3879 // The second vector must be undef 3880 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3881 return false; 3882 3883 EVT VT = N->getValueType(0); 3884 unsigned NumElems = VT.getVectorNumElements(); 3885 3886 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3887 (VT.getSizeInBits() == 256 && NumElems != 8)) 3888 return false; 3889 3890 // "i" is the value the indexed mask element must have 3891 for (unsigned i = 0; i != NumElems; i += 2) 3892 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3893 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3894 return false; 3895 3896 return true; 3897} 3898 3899/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3900/// specifies a shuffle of elements that is suitable for input to 256-bit 3901/// version of MOVDDUP. 3902static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3903 bool HasAVX) { 3904 unsigned NumElts = VT.getVectorNumElements(); 3905 3906 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3907 return false; 3908 3909 for (unsigned i = 0; i != NumElts/2; ++i) 3910 if (!isUndefOrEqual(Mask[i], 0)) 3911 return false; 3912 for (unsigned i = NumElts/2; i != NumElts; ++i) 3913 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3914 return false; 3915 return true; 3916} 3917 3918/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3919/// specifies a shuffle of elements that is suitable for input to 128-bit 3920/// version of MOVDDUP. 3921bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3922 EVT VT = N->getValueType(0); 3923 3924 if (VT.getSizeInBits() != 128) 3925 return false; 3926 3927 unsigned e = VT.getVectorNumElements() / 2; 3928 for (unsigned i = 0; i != e; ++i) 3929 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3930 return false; 3931 for (unsigned i = 0; i != e; ++i) 3932 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3933 return false; 3934 return true; 3935} 3936 3937/// isVEXTRACTF128Index - Return true if the specified 3938/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3939/// suitable for input to VEXTRACTF128. 3940bool X86::isVEXTRACTF128Index(SDNode *N) { 3941 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3942 return false; 3943 3944 // The index should be aligned on a 128-bit boundary. 3945 uint64_t Index = 3946 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3947 3948 unsigned VL = N->getValueType(0).getVectorNumElements(); 3949 unsigned VBits = N->getValueType(0).getSizeInBits(); 3950 unsigned ElSize = VBits / VL; 3951 bool Result = (Index * ElSize) % 128 == 0; 3952 3953 return Result; 3954} 3955 3956/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3957/// operand specifies a subvector insert that is suitable for input to 3958/// VINSERTF128. 3959bool X86::isVINSERTF128Index(SDNode *N) { 3960 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3961 return false; 3962 3963 // The index should be aligned on a 128-bit boundary. 3964 uint64_t Index = 3965 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3966 3967 unsigned VL = N->getValueType(0).getVectorNumElements(); 3968 unsigned VBits = N->getValueType(0).getSizeInBits(); 3969 unsigned ElSize = VBits / VL; 3970 bool Result = (Index * ElSize) % 128 == 0; 3971 3972 return Result; 3973} 3974 3975/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3976/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3977unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3979 unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3980 3981 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3982 unsigned Mask = 0; 3983 for (unsigned i = 0; i != NumOperands; ++i) { 3984 int Val = SVOp->getMaskElt(NumOperands-i-1); 3985 if (Val < 0) Val = 0; 3986 if (Val >= (int)NumOperands) Val -= NumOperands; 3987 Mask |= Val; 3988 if (i != NumOperands - 1) 3989 Mask <<= Shift; 3990 } 3991 return Mask; 3992} 3993 3994/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3995/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3996unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3998 unsigned Mask = 0; 3999 // 8 nodes, but we only care about the last 4. 4000 for (unsigned i = 7; i >= 4; --i) { 4001 int Val = SVOp->getMaskElt(i); 4002 if (Val >= 0) 4003 Mask |= (Val - 4); 4004 if (i != 4) 4005 Mask <<= 2; 4006 } 4007 return Mask; 4008} 4009 4010/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4011/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4012unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4014 unsigned Mask = 0; 4015 // 8 nodes, but we only care about the first 4. 4016 for (int i = 3; i >= 0; --i) { 4017 int Val = SVOp->getMaskElt(i); 4018 if (Val >= 0) 4019 Mask |= Val; 4020 if (i != 0) 4021 Mask <<= 2; 4022 } 4023 return Mask; 4024} 4025 4026/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4027/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4028static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4029 EVT VT = SVOp->getValueType(0); 4030 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4031 int Val = 0; 4032 4033 unsigned i, e; 4034 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4035 Val = SVOp->getMaskElt(i); 4036 if (Val >= 0) 4037 break; 4038 } 4039 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4040 return (Val - i) * EltSize; 4041} 4042 4043/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4044/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4045/// instructions. 4046unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4047 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4048 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4049 4050 uint64_t Index = 4051 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4052 4053 EVT VecVT = N->getOperand(0).getValueType(); 4054 EVT ElVT = VecVT.getVectorElementType(); 4055 4056 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4057 return Index / NumElemsPerChunk; 4058} 4059 4060/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4061/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4062/// instructions. 4063unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4064 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4065 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4066 4067 uint64_t Index = 4068 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4069 4070 EVT VecVT = N->getValueType(0); 4071 EVT ElVT = VecVT.getVectorElementType(); 4072 4073 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4074 return Index / NumElemsPerChunk; 4075} 4076 4077/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4078/// constant +0.0. 4079bool X86::isZeroNode(SDValue Elt) { 4080 return ((isa<ConstantSDNode>(Elt) && 4081 cast<ConstantSDNode>(Elt)->isNullValue()) || 4082 (isa<ConstantFPSDNode>(Elt) && 4083 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4084} 4085 4086/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4087/// their permute mask. 4088static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4089 SelectionDAG &DAG) { 4090 EVT VT = SVOp->getValueType(0); 4091 unsigned NumElems = VT.getVectorNumElements(); 4092 SmallVector<int, 8> MaskVec; 4093 4094 for (unsigned i = 0; i != NumElems; ++i) { 4095 int idx = SVOp->getMaskElt(i); 4096 if (idx < 0) 4097 MaskVec.push_back(idx); 4098 else if (idx < (int)NumElems) 4099 MaskVec.push_back(idx + NumElems); 4100 else 4101 MaskVec.push_back(idx - NumElems); 4102 } 4103 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4104 SVOp->getOperand(0), &MaskVec[0]); 4105} 4106 4107/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4108/// match movhlps. The lower half elements should come from upper half of 4109/// V1 (and in order), and the upper half elements should come from the upper 4110/// half of V2 (and in order). 4111static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4112 EVT VT = Op->getValueType(0); 4113 if (VT.getSizeInBits() != 128) 4114 return false; 4115 if (VT.getVectorNumElements() != 4) 4116 return false; 4117 for (unsigned i = 0, e = 2; i != e; ++i) 4118 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4119 return false; 4120 for (unsigned i = 2; i != 4; ++i) 4121 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4122 return false; 4123 return true; 4124} 4125 4126/// isScalarLoadToVector - Returns true if the node is a scalar load that 4127/// is promoted to a vector. It also returns the LoadSDNode by reference if 4128/// required. 4129static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4130 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4131 return false; 4132 N = N->getOperand(0).getNode(); 4133 if (!ISD::isNON_EXTLoad(N)) 4134 return false; 4135 if (LD) 4136 *LD = cast<LoadSDNode>(N); 4137 return true; 4138} 4139 4140// Test whether the given value is a vector value which will be legalized 4141// into a load. 4142static bool WillBeConstantPoolLoad(SDNode *N) { 4143 if (N->getOpcode() != ISD::BUILD_VECTOR) 4144 return false; 4145 4146 // Check for any non-constant elements. 4147 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4148 switch (N->getOperand(i).getNode()->getOpcode()) { 4149 case ISD::UNDEF: 4150 case ISD::ConstantFP: 4151 case ISD::Constant: 4152 break; 4153 default: 4154 return false; 4155 } 4156 4157 // Vectors of all-zeros and all-ones are materialized with special 4158 // instructions rather than being loaded. 4159 return !ISD::isBuildVectorAllZeros(N) && 4160 !ISD::isBuildVectorAllOnes(N); 4161} 4162 4163/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4164/// match movlp{s|d}. The lower half elements should come from lower half of 4165/// V1 (and in order), and the upper half elements should come from the upper 4166/// half of V2 (and in order). And since V1 will become the source of the 4167/// MOVLP, it must be either a vector load or a scalar load to vector. 4168static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4169 ShuffleVectorSDNode *Op) { 4170 EVT VT = Op->getValueType(0); 4171 if (VT.getSizeInBits() != 128) 4172 return false; 4173 4174 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4175 return false; 4176 // Is V2 is a vector load, don't do this transformation. We will try to use 4177 // load folding shufps op. 4178 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4179 return false; 4180 4181 unsigned NumElems = VT.getVectorNumElements(); 4182 4183 if (NumElems != 2 && NumElems != 4) 4184 return false; 4185 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4186 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4187 return false; 4188 for (unsigned i = NumElems/2; i != NumElems; ++i) 4189 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4190 return false; 4191 return true; 4192} 4193 4194/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4195/// all the same. 4196static bool isSplatVector(SDNode *N) { 4197 if (N->getOpcode() != ISD::BUILD_VECTOR) 4198 return false; 4199 4200 SDValue SplatValue = N->getOperand(0); 4201 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4202 if (N->getOperand(i) != SplatValue) 4203 return false; 4204 return true; 4205} 4206 4207/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4208/// to an zero vector. 4209/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4210static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4211 SDValue V1 = N->getOperand(0); 4212 SDValue V2 = N->getOperand(1); 4213 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4214 for (unsigned i = 0; i != NumElems; ++i) { 4215 int Idx = N->getMaskElt(i); 4216 if (Idx >= (int)NumElems) { 4217 unsigned Opc = V2.getOpcode(); 4218 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4219 continue; 4220 if (Opc != ISD::BUILD_VECTOR || 4221 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4222 return false; 4223 } else if (Idx >= 0) { 4224 unsigned Opc = V1.getOpcode(); 4225 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4226 continue; 4227 if (Opc != ISD::BUILD_VECTOR || 4228 !X86::isZeroNode(V1.getOperand(Idx))) 4229 return false; 4230 } 4231 } 4232 return true; 4233} 4234 4235/// getZeroVector - Returns a vector of specified type with all zero elements. 4236/// 4237static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 4238 DebugLoc dl) { 4239 assert(VT.isVector() && "Expected a vector type"); 4240 4241 // Always build SSE zero vectors as <4 x i32> bitcasted 4242 // to their dest type. This ensures they get CSE'd. 4243 SDValue Vec; 4244 if (VT.getSizeInBits() == 128) { // SSE 4245 if (HasSSE2) { // SSE2 4246 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4247 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4248 } else { // SSE1 4249 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4251 } 4252 } else if (VT.getSizeInBits() == 256) { // AVX 4253 // 256-bit logic and arithmetic instructions in AVX are 4254 // all floating-point, no support for integer ops. Default 4255 // to emitting fp zeroed vectors then. 4256 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4257 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4259 } 4260 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4261} 4262 4263/// getOnesVector - Returns a vector of specified type with all bits set. 4264/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4265/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4266/// Then bitcast to their original type, ensuring they get CSE'd. 4267static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4268 DebugLoc dl) { 4269 assert(VT.isVector() && "Expected a vector type"); 4270 assert((VT.is128BitVector() || VT.is256BitVector()) 4271 && "Expected a 128-bit or 256-bit vector type"); 4272 4273 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4274 SDValue Vec; 4275 if (VT.getSizeInBits() == 256) { 4276 if (HasAVX2) { // AVX2 4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4279 } else { // AVX 4280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4281 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4282 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4283 Vec = Insert128BitVector(InsV, Vec, 4284 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4285 } 4286 } else { 4287 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4288 } 4289 4290 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4291} 4292 4293/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4294/// that point to V2 points to its first element. 4295static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4296 EVT VT = SVOp->getValueType(0); 4297 unsigned NumElems = VT.getVectorNumElements(); 4298 4299 bool Changed = false; 4300 SmallVector<int, 8> MaskVec; 4301 SVOp->getMask(MaskVec); 4302 4303 for (unsigned i = 0; i != NumElems; ++i) { 4304 if (MaskVec[i] > (int)NumElems) { 4305 MaskVec[i] = NumElems; 4306 Changed = true; 4307 } 4308 } 4309 if (Changed) 4310 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4311 SVOp->getOperand(1), &MaskVec[0]); 4312 return SDValue(SVOp, 0); 4313} 4314 4315/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4316/// operation of specified width. 4317static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4318 SDValue V2) { 4319 unsigned NumElems = VT.getVectorNumElements(); 4320 SmallVector<int, 8> Mask; 4321 Mask.push_back(NumElems); 4322 for (unsigned i = 1; i != NumElems; ++i) 4323 Mask.push_back(i); 4324 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4325} 4326 4327/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4328static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4329 SDValue V2) { 4330 unsigned NumElems = VT.getVectorNumElements(); 4331 SmallVector<int, 8> Mask; 4332 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4333 Mask.push_back(i); 4334 Mask.push_back(i + NumElems); 4335 } 4336 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4337} 4338 4339/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4340static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4341 SDValue V2) { 4342 unsigned NumElems = VT.getVectorNumElements(); 4343 unsigned Half = NumElems/2; 4344 SmallVector<int, 8> Mask; 4345 for (unsigned i = 0; i != Half; ++i) { 4346 Mask.push_back(i + Half); 4347 Mask.push_back(i + NumElems + Half); 4348 } 4349 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4350} 4351 4352// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4353// a generic shuffle instruction because the target has no such instructions. 4354// Generate shuffles which repeat i16 and i8 several times until they can be 4355// represented by v4f32 and then be manipulated by target suported shuffles. 4356static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4357 EVT VT = V.getValueType(); 4358 int NumElems = VT.getVectorNumElements(); 4359 DebugLoc dl = V.getDebugLoc(); 4360 4361 while (NumElems > 4) { 4362 if (EltNo < NumElems/2) { 4363 V = getUnpackl(DAG, dl, VT, V, V); 4364 } else { 4365 V = getUnpackh(DAG, dl, VT, V, V); 4366 EltNo -= NumElems/2; 4367 } 4368 NumElems >>= 1; 4369 } 4370 return V; 4371} 4372 4373/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4374static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4375 EVT VT = V.getValueType(); 4376 DebugLoc dl = V.getDebugLoc(); 4377 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4378 && "Vector size not supported"); 4379 4380 if (VT.getSizeInBits() == 128) { 4381 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4382 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4383 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4384 &SplatMask[0]); 4385 } else { 4386 // To use VPERMILPS to splat scalars, the second half of indicies must 4387 // refer to the higher part, which is a duplication of the lower one, 4388 // because VPERMILPS can only handle in-lane permutations. 4389 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4390 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4391 4392 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4393 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4394 &SplatMask[0]); 4395 } 4396 4397 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4398} 4399 4400/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4401static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4402 EVT SrcVT = SV->getValueType(0); 4403 SDValue V1 = SV->getOperand(0); 4404 DebugLoc dl = SV->getDebugLoc(); 4405 4406 int EltNo = SV->getSplatIndex(); 4407 int NumElems = SrcVT.getVectorNumElements(); 4408 unsigned Size = SrcVT.getSizeInBits(); 4409 4410 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4411 "Unknown how to promote splat for type"); 4412 4413 // Extract the 128-bit part containing the splat element and update 4414 // the splat element index when it refers to the higher register. 4415 if (Size == 256) { 4416 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4417 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4418 if (Idx > 0) 4419 EltNo -= NumElems/2; 4420 } 4421 4422 // All i16 and i8 vector types can't be used directly by a generic shuffle 4423 // instruction because the target has no such instruction. Generate shuffles 4424 // which repeat i16 and i8 several times until they fit in i32, and then can 4425 // be manipulated by target suported shuffles. 4426 EVT EltVT = SrcVT.getVectorElementType(); 4427 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4428 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4429 4430 // Recreate the 256-bit vector and place the same 128-bit vector 4431 // into the low and high part. This is necessary because we want 4432 // to use VPERM* to shuffle the vectors 4433 if (Size == 256) { 4434 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4435 DAG.getConstant(0, MVT::i32), DAG, dl); 4436 V1 = Insert128BitVector(InsV, V1, 4437 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4438 } 4439 4440 return getLegalSplat(DAG, V1, EltNo); 4441} 4442 4443/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4444/// vector of zero or undef vector. This produces a shuffle where the low 4445/// element of V2 is swizzled into the zero/undef vector, landing at element 4446/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4447static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4448 bool isZero, bool HasSSE2, 4449 SelectionDAG &DAG) { 4450 EVT VT = V2.getValueType(); 4451 SDValue V1 = isZero 4452 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4453 unsigned NumElems = VT.getVectorNumElements(); 4454 SmallVector<int, 16> MaskVec; 4455 for (unsigned i = 0; i != NumElems; ++i) 4456 // If this is the insertion idx, put the low elt of V2 here. 4457 MaskVec.push_back(i == Idx ? NumElems : i); 4458 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4459} 4460 4461/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4462/// element of the result of the vector shuffle. 4463static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4464 unsigned Depth) { 4465 if (Depth == 6) 4466 return SDValue(); // Limit search depth. 4467 4468 SDValue V = SDValue(N, 0); 4469 EVT VT = V.getValueType(); 4470 unsigned Opcode = V.getOpcode(); 4471 4472 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4473 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4474 Index = SV->getMaskElt(Index); 4475 4476 if (Index < 0) 4477 return DAG.getUNDEF(VT.getVectorElementType()); 4478 4479 int NumElems = VT.getVectorNumElements(); 4480 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4481 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4482 } 4483 4484 // Recurse into target specific vector shuffles to find scalars. 4485 if (isTargetShuffle(Opcode)) { 4486 int NumElems = VT.getVectorNumElements(); 4487 SmallVector<unsigned, 16> ShuffleMask; 4488 SDValue ImmN; 4489 4490 switch(Opcode) { 4491 case X86ISD::SHUFP: 4492 ImmN = N->getOperand(N->getNumOperands()-1); 4493 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4494 ShuffleMask); 4495 break; 4496 case X86ISD::UNPCKH: 4497 DecodeUNPCKHMask(VT, ShuffleMask); 4498 break; 4499 case X86ISD::UNPCKL: 4500 DecodeUNPCKLMask(VT, ShuffleMask); 4501 break; 4502 case X86ISD::MOVHLPS: 4503 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4504 break; 4505 case X86ISD::MOVLHPS: 4506 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4507 break; 4508 case X86ISD::PSHUFD: 4509 ImmN = N->getOperand(N->getNumOperands()-1); 4510 DecodePSHUFMask(NumElems, 4511 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4512 ShuffleMask); 4513 break; 4514 case X86ISD::PSHUFHW: 4515 ImmN = N->getOperand(N->getNumOperands()-1); 4516 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4517 ShuffleMask); 4518 break; 4519 case X86ISD::PSHUFLW: 4520 ImmN = N->getOperand(N->getNumOperands()-1); 4521 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4522 ShuffleMask); 4523 break; 4524 case X86ISD::MOVSS: 4525 case X86ISD::MOVSD: { 4526 // The index 0 always comes from the first element of the second source, 4527 // this is why MOVSS and MOVSD are used in the first place. The other 4528 // elements come from the other positions of the first source vector. 4529 unsigned OpNum = (Index == 0) ? 1 : 0; 4530 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4531 Depth+1); 4532 } 4533 case X86ISD::VPERMILP: 4534 ImmN = N->getOperand(N->getNumOperands()-1); 4535 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4536 ShuffleMask); 4537 break; 4538 case X86ISD::VPERM2X128: 4539 ImmN = N->getOperand(N->getNumOperands()-1); 4540 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4541 ShuffleMask); 4542 break; 4543 case X86ISD::MOVDDUP: 4544 case X86ISD::MOVLHPD: 4545 case X86ISD::MOVLPD: 4546 case X86ISD::MOVLPS: 4547 case X86ISD::MOVSHDUP: 4548 case X86ISD::MOVSLDUP: 4549 case X86ISD::PALIGN: 4550 return SDValue(); // Not yet implemented. 4551 default: 4552 assert(0 && "unknown target shuffle node"); 4553 return SDValue(); 4554 } 4555 4556 Index = ShuffleMask[Index]; 4557 if (Index < 0) 4558 return DAG.getUNDEF(VT.getVectorElementType()); 4559 4560 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4561 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4562 Depth+1); 4563 } 4564 4565 // Actual nodes that may contain scalar elements 4566 if (Opcode == ISD::BITCAST) { 4567 V = V.getOperand(0); 4568 EVT SrcVT = V.getValueType(); 4569 unsigned NumElems = VT.getVectorNumElements(); 4570 4571 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4572 return SDValue(); 4573 } 4574 4575 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4576 return (Index == 0) ? V.getOperand(0) 4577 : DAG.getUNDEF(VT.getVectorElementType()); 4578 4579 if (V.getOpcode() == ISD::BUILD_VECTOR) 4580 return V.getOperand(Index); 4581 4582 return SDValue(); 4583} 4584 4585/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4586/// shuffle operation which come from a consecutively from a zero. The 4587/// search can start in two different directions, from left or right. 4588static 4589unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4590 bool ZerosFromLeft, SelectionDAG &DAG) { 4591 int i = 0; 4592 4593 while (i < NumElems) { 4594 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4595 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4596 if (!(Elt.getNode() && 4597 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4598 break; 4599 ++i; 4600 } 4601 4602 return i; 4603} 4604 4605/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4606/// MaskE correspond consecutively to elements from one of the vector operands, 4607/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4608static 4609bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4610 int OpIdx, int NumElems, unsigned &OpNum) { 4611 bool SeenV1 = false; 4612 bool SeenV2 = false; 4613 4614 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4615 int Idx = SVOp->getMaskElt(i); 4616 // Ignore undef indicies 4617 if (Idx < 0) 4618 continue; 4619 4620 if (Idx < NumElems) 4621 SeenV1 = true; 4622 else 4623 SeenV2 = true; 4624 4625 // Only accept consecutive elements from the same vector 4626 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4627 return false; 4628 } 4629 4630 OpNum = SeenV1 ? 0 : 1; 4631 return true; 4632} 4633 4634/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4635/// logical left shift of a vector. 4636static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4637 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4638 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4639 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4640 false /* check zeros from right */, DAG); 4641 unsigned OpSrc; 4642 4643 if (!NumZeros) 4644 return false; 4645 4646 // Considering the elements in the mask that are not consecutive zeros, 4647 // check if they consecutively come from only one of the source vectors. 4648 // 4649 // V1 = {X, A, B, C} 0 4650 // \ \ \ / 4651 // vector_shuffle V1, V2 <1, 2, 3, X> 4652 // 4653 if (!isShuffleMaskConsecutive(SVOp, 4654 0, // Mask Start Index 4655 NumElems-NumZeros-1, // Mask End Index 4656 NumZeros, // Where to start looking in the src vector 4657 NumElems, // Number of elements in vector 4658 OpSrc)) // Which source operand ? 4659 return false; 4660 4661 isLeft = false; 4662 ShAmt = NumZeros; 4663 ShVal = SVOp->getOperand(OpSrc); 4664 return true; 4665} 4666 4667/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4668/// logical left shift of a vector. 4669static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4670 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4671 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4672 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4673 true /* check zeros from left */, DAG); 4674 unsigned OpSrc; 4675 4676 if (!NumZeros) 4677 return false; 4678 4679 // Considering the elements in the mask that are not consecutive zeros, 4680 // check if they consecutively come from only one of the source vectors. 4681 // 4682 // 0 { A, B, X, X } = V2 4683 // / \ / / 4684 // vector_shuffle V1, V2 <X, X, 4, 5> 4685 // 4686 if (!isShuffleMaskConsecutive(SVOp, 4687 NumZeros, // Mask Start Index 4688 NumElems-1, // Mask End Index 4689 0, // Where to start looking in the src vector 4690 NumElems, // Number of elements in vector 4691 OpSrc)) // Which source operand ? 4692 return false; 4693 4694 isLeft = true; 4695 ShAmt = NumZeros; 4696 ShVal = SVOp->getOperand(OpSrc); 4697 return true; 4698} 4699 4700/// isVectorShift - Returns true if the shuffle can be implemented as a 4701/// logical left or right shift of a vector. 4702static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4703 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4704 // Although the logic below support any bitwidth size, there are no 4705 // shift instructions which handle more than 128-bit vectors. 4706 if (SVOp->getValueType(0).getSizeInBits() > 128) 4707 return false; 4708 4709 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4710 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4711 return true; 4712 4713 return false; 4714} 4715 4716/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4717/// 4718static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4719 unsigned NumNonZero, unsigned NumZero, 4720 SelectionDAG &DAG, 4721 const TargetLowering &TLI) { 4722 if (NumNonZero > 8) 4723 return SDValue(); 4724 4725 DebugLoc dl = Op.getDebugLoc(); 4726 SDValue V(0, 0); 4727 bool First = true; 4728 for (unsigned i = 0; i < 16; ++i) { 4729 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4730 if (ThisIsNonZero && First) { 4731 if (NumZero) 4732 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4733 else 4734 V = DAG.getUNDEF(MVT::v8i16); 4735 First = false; 4736 } 4737 4738 if ((i & 1) != 0) { 4739 SDValue ThisElt(0, 0), LastElt(0, 0); 4740 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4741 if (LastIsNonZero) { 4742 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4743 MVT::i16, Op.getOperand(i-1)); 4744 } 4745 if (ThisIsNonZero) { 4746 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4747 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4748 ThisElt, DAG.getConstant(8, MVT::i8)); 4749 if (LastIsNonZero) 4750 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4751 } else 4752 ThisElt = LastElt; 4753 4754 if (ThisElt.getNode()) 4755 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4756 DAG.getIntPtrConstant(i/2)); 4757 } 4758 } 4759 4760 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4761} 4762 4763/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4764/// 4765static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4766 unsigned NumNonZero, unsigned NumZero, 4767 SelectionDAG &DAG, 4768 const TargetLowering &TLI) { 4769 if (NumNonZero > 4) 4770 return SDValue(); 4771 4772 DebugLoc dl = Op.getDebugLoc(); 4773 SDValue V(0, 0); 4774 bool First = true; 4775 for (unsigned i = 0; i < 8; ++i) { 4776 bool isNonZero = (NonZeros & (1 << i)) != 0; 4777 if (isNonZero) { 4778 if (First) { 4779 if (NumZero) 4780 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4781 else 4782 V = DAG.getUNDEF(MVT::v8i16); 4783 First = false; 4784 } 4785 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4786 MVT::v8i16, V, Op.getOperand(i), 4787 DAG.getIntPtrConstant(i)); 4788 } 4789 } 4790 4791 return V; 4792} 4793 4794/// getVShift - Return a vector logical shift node. 4795/// 4796static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4797 unsigned NumBits, SelectionDAG &DAG, 4798 const TargetLowering &TLI, DebugLoc dl) { 4799 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4800 EVT ShVT = MVT::v2i64; 4801 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4802 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4803 return DAG.getNode(ISD::BITCAST, dl, VT, 4804 DAG.getNode(Opc, dl, ShVT, SrcOp, 4805 DAG.getConstant(NumBits, 4806 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4807} 4808 4809SDValue 4810X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4811 SelectionDAG &DAG) const { 4812 4813 // Check if the scalar load can be widened into a vector load. And if 4814 // the address is "base + cst" see if the cst can be "absorbed" into 4815 // the shuffle mask. 4816 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4817 SDValue Ptr = LD->getBasePtr(); 4818 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4819 return SDValue(); 4820 EVT PVT = LD->getValueType(0); 4821 if (PVT != MVT::i32 && PVT != MVT::f32) 4822 return SDValue(); 4823 4824 int FI = -1; 4825 int64_t Offset = 0; 4826 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4827 FI = FINode->getIndex(); 4828 Offset = 0; 4829 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4830 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4831 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4832 Offset = Ptr.getConstantOperandVal(1); 4833 Ptr = Ptr.getOperand(0); 4834 } else { 4835 return SDValue(); 4836 } 4837 4838 // FIXME: 256-bit vector instructions don't require a strict alignment, 4839 // improve this code to support it better. 4840 unsigned RequiredAlign = VT.getSizeInBits()/8; 4841 SDValue Chain = LD->getChain(); 4842 // Make sure the stack object alignment is at least 16 or 32. 4843 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4844 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4845 if (MFI->isFixedObjectIndex(FI)) { 4846 // Can't change the alignment. FIXME: It's possible to compute 4847 // the exact stack offset and reference FI + adjust offset instead. 4848 // If someone *really* cares about this. That's the way to implement it. 4849 return SDValue(); 4850 } else { 4851 MFI->setObjectAlignment(FI, RequiredAlign); 4852 } 4853 } 4854 4855 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4856 // Ptr + (Offset & ~15). 4857 if (Offset < 0) 4858 return SDValue(); 4859 if ((Offset % RequiredAlign) & 3) 4860 return SDValue(); 4861 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4862 if (StartOffset) 4863 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4864 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4865 4866 int EltNo = (Offset - StartOffset) >> 2; 4867 int NumElems = VT.getVectorNumElements(); 4868 4869 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4870 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4871 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4872 LD->getPointerInfo().getWithOffset(StartOffset), 4873 false, false, false, 0); 4874 4875 // Canonicalize it to a v4i32 or v8i32 shuffle. 4876 SmallVector<int, 8> Mask; 4877 for (int i = 0; i < NumElems; ++i) 4878 Mask.push_back(EltNo); 4879 4880 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4881 return DAG.getNode(ISD::BITCAST, dl, NVT, 4882 DAG.getVectorShuffle(CanonVT, dl, V1, 4883 DAG.getUNDEF(CanonVT),&Mask[0])); 4884 } 4885 4886 return SDValue(); 4887} 4888 4889/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4890/// vector of type 'VT', see if the elements can be replaced by a single large 4891/// load which has the same value as a build_vector whose operands are 'elts'. 4892/// 4893/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4894/// 4895/// FIXME: we'd also like to handle the case where the last elements are zero 4896/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4897/// There's even a handy isZeroNode for that purpose. 4898static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4899 DebugLoc &DL, SelectionDAG &DAG) { 4900 EVT EltVT = VT.getVectorElementType(); 4901 unsigned NumElems = Elts.size(); 4902 4903 LoadSDNode *LDBase = NULL; 4904 unsigned LastLoadedElt = -1U; 4905 4906 // For each element in the initializer, see if we've found a load or an undef. 4907 // If we don't find an initial load element, or later load elements are 4908 // non-consecutive, bail out. 4909 for (unsigned i = 0; i < NumElems; ++i) { 4910 SDValue Elt = Elts[i]; 4911 4912 if (!Elt.getNode() || 4913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4914 return SDValue(); 4915 if (!LDBase) { 4916 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4917 return SDValue(); 4918 LDBase = cast<LoadSDNode>(Elt.getNode()); 4919 LastLoadedElt = i; 4920 continue; 4921 } 4922 if (Elt.getOpcode() == ISD::UNDEF) 4923 continue; 4924 4925 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4927 return SDValue(); 4928 LastLoadedElt = i; 4929 } 4930 4931 // If we have found an entire vector of loads and undefs, then return a large 4932 // load of the entire vector width starting at the base pointer. If we found 4933 // consecutive loads for the low half, generate a vzext_load node. 4934 if (LastLoadedElt == NumElems - 1) { 4935 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4936 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4937 LDBase->getPointerInfo(), 4938 LDBase->isVolatile(), LDBase->isNonTemporal(), 4939 LDBase->isInvariant(), 0); 4940 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4941 LDBase->getPointerInfo(), 4942 LDBase->isVolatile(), LDBase->isNonTemporal(), 4943 LDBase->isInvariant(), LDBase->getAlignment()); 4944 } else if (NumElems == 4 && LastLoadedElt == 1 && 4945 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4946 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4947 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4948 SDValue ResNode = 4949 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4950 LDBase->getPointerInfo(), 4951 LDBase->getAlignment(), 4952 false/*isVolatile*/, true/*ReadMem*/, 4953 false/*WriteMem*/); 4954 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4955 } 4956 return SDValue(); 4957} 4958 4959/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4960/// a vbroadcast node. We support two patterns: 4961/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4962/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4963/// a scalar load. 4964/// The scalar load node is returned when a pattern is found, 4965/// or SDValue() otherwise. 4966static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4967 if (!Subtarget->hasAVX()) 4968 return SDValue(); 4969 4970 EVT VT = Op.getValueType(); 4971 SDValue V = Op; 4972 4973 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4974 V = V.getOperand(0); 4975 4976 //A suspected load to be broadcasted. 4977 SDValue Ld; 4978 4979 switch (V.getOpcode()) { 4980 default: 4981 // Unknown pattern found. 4982 return SDValue(); 4983 4984 case ISD::BUILD_VECTOR: { 4985 // The BUILD_VECTOR node must be a splat. 4986 if (!isSplatVector(V.getNode())) 4987 return SDValue(); 4988 4989 Ld = V.getOperand(0); 4990 4991 // The suspected load node has several users. Make sure that all 4992 // of its users are from the BUILD_VECTOR node. 4993 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4994 return SDValue(); 4995 break; 4996 } 4997 4998 case ISD::VECTOR_SHUFFLE: { 4999 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5000 5001 // Shuffles must have a splat mask where the first element is 5002 // broadcasted. 5003 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5004 return SDValue(); 5005 5006 SDValue Sc = Op.getOperand(0); 5007 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 5008 return SDValue(); 5009 5010 Ld = Sc.getOperand(0); 5011 5012 // The scalar_to_vector node and the suspected 5013 // load node must have exactly one user. 5014 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 5015 return SDValue(); 5016 break; 5017 } 5018 } 5019 5020 // The scalar source must be a normal load. 5021 if (!ISD::isNormalLoad(Ld.getNode())) 5022 return SDValue(); 5023 5024 bool Is256 = VT.getSizeInBits() == 256; 5025 bool Is128 = VT.getSizeInBits() == 128; 5026 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5027 5028 // VBroadcast to YMM 5029 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5030 return Ld; 5031 5032 // VBroadcast to XMM 5033 if (Is128 && (ScalarSize == 32)) 5034 return Ld; 5035 5036 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5037 // double since there is vbroadcastsd xmm 5038 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5039 // VBroadcast to YMM 5040 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5041 return Ld; 5042 5043 // VBroadcast to XMM 5044 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5045 return Ld; 5046 } 5047 5048 // Unsupported broadcast. 5049 return SDValue(); 5050} 5051 5052SDValue 5053X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5054 DebugLoc dl = Op.getDebugLoc(); 5055 5056 EVT VT = Op.getValueType(); 5057 EVT ExtVT = VT.getVectorElementType(); 5058 unsigned NumElems = Op.getNumOperands(); 5059 5060 // Vectors containing all zeros can be matched by pxor and xorps later 5061 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5062 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5063 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5064 if (Op.getValueType() == MVT::v4i32 || 5065 Op.getValueType() == MVT::v8i32) 5066 return Op; 5067 5068 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 5069 } 5070 5071 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5072 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5073 // vpcmpeqd on 256-bit vectors. 5074 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5075 if (Op.getValueType() == MVT::v4i32 || 5076 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2())) 5077 return Op; 5078 5079 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); 5080 } 5081 5082 SDValue LD = isVectorBroadcast(Op, Subtarget); 5083 if (LD.getNode()) 5084 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5085 5086 unsigned EVTBits = ExtVT.getSizeInBits(); 5087 5088 unsigned NumZero = 0; 5089 unsigned NumNonZero = 0; 5090 unsigned NonZeros = 0; 5091 bool IsAllConstants = true; 5092 SmallSet<SDValue, 8> Values; 5093 for (unsigned i = 0; i < NumElems; ++i) { 5094 SDValue Elt = Op.getOperand(i); 5095 if (Elt.getOpcode() == ISD::UNDEF) 5096 continue; 5097 Values.insert(Elt); 5098 if (Elt.getOpcode() != ISD::Constant && 5099 Elt.getOpcode() != ISD::ConstantFP) 5100 IsAllConstants = false; 5101 if (X86::isZeroNode(Elt)) 5102 NumZero++; 5103 else { 5104 NonZeros |= (1 << i); 5105 NumNonZero++; 5106 } 5107 } 5108 5109 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5110 if (NumNonZero == 0) 5111 return DAG.getUNDEF(VT); 5112 5113 // Special case for single non-zero, non-undef, element. 5114 if (NumNonZero == 1) { 5115 unsigned Idx = CountTrailingZeros_32(NonZeros); 5116 SDValue Item = Op.getOperand(Idx); 5117 5118 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5119 // the value are obviously zero, truncate the value to i32 and do the 5120 // insertion that way. Only do this if the value is non-constant or if the 5121 // value is a constant being inserted into element 0. It is cheaper to do 5122 // a constant pool load than it is to do a movd + shuffle. 5123 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5124 (!IsAllConstants || Idx == 0)) { 5125 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5126 // Handle SSE only. 5127 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5128 EVT VecVT = MVT::v4i32; 5129 unsigned VecElts = 4; 5130 5131 // Truncate the value (which may itself be a constant) to i32, and 5132 // convert it to a vector with movd (S2V+shuffle to zero extend). 5133 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5134 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5135 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5136 Subtarget->hasSSE2(), DAG); 5137 5138 // Now we have our 32-bit value zero extended in the low element of 5139 // a vector. If Idx != 0, swizzle it into place. 5140 if (Idx != 0) { 5141 SmallVector<int, 4> Mask; 5142 Mask.push_back(Idx); 5143 for (unsigned i = 1; i != VecElts; ++i) 5144 Mask.push_back(i); 5145 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5146 DAG.getUNDEF(Item.getValueType()), 5147 &Mask[0]); 5148 } 5149 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5150 } 5151 } 5152 5153 // If we have a constant or non-constant insertion into the low element of 5154 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5155 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5156 // depending on what the source datatype is. 5157 if (Idx == 0) { 5158 if (NumZero == 0) 5159 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5160 5161 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5162 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5163 if (VT.getSizeInBits() == 256) { 5164 SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); 5165 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5166 Item, DAG.getIntPtrConstant(0)); 5167 } 5168 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5169 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5170 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5171 return getShuffleVectorZeroOrUndef(Item, 0, true, 5172 Subtarget->hasSSE2(), DAG); 5173 } 5174 5175 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5176 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5177 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5178 if (VT.getSizeInBits() == 256) { 5179 SDValue ZeroVec = getZeroVector(MVT::v8i32, true, DAG, dl); 5180 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5181 DAG, dl); 5182 } else { 5183 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5184 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5185 Subtarget->hasSSE2(), DAG); 5186 } 5187 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5188 } 5189 } 5190 5191 // Is it a vector logical left shift? 5192 if (NumElems == 2 && Idx == 1 && 5193 X86::isZeroNode(Op.getOperand(0)) && 5194 !X86::isZeroNode(Op.getOperand(1))) { 5195 unsigned NumBits = VT.getSizeInBits(); 5196 return getVShift(true, VT, 5197 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5198 VT, Op.getOperand(1)), 5199 NumBits/2, DAG, *this, dl); 5200 } 5201 5202 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5203 return SDValue(); 5204 5205 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5206 // is a non-constant being inserted into an element other than the low one, 5207 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5208 // movd/movss) to move this into the low element, then shuffle it into 5209 // place. 5210 if (EVTBits == 32) { 5211 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5212 5213 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5214 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5215 Subtarget->hasSSE2(), DAG); 5216 SmallVector<int, 8> MaskVec; 5217 for (unsigned i = 0; i < NumElems; i++) 5218 MaskVec.push_back(i == Idx ? 0 : 1); 5219 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5220 } 5221 } 5222 5223 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5224 if (Values.size() == 1) { 5225 if (EVTBits == 32) { 5226 // Instead of a shuffle like this: 5227 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5228 // Check if it's possible to issue this instead. 5229 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5230 unsigned Idx = CountTrailingZeros_32(NonZeros); 5231 SDValue Item = Op.getOperand(Idx); 5232 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5233 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5234 } 5235 return SDValue(); 5236 } 5237 5238 // A vector full of immediates; various special cases are already 5239 // handled, so this is best done with a single constant-pool load. 5240 if (IsAllConstants) 5241 return SDValue(); 5242 5243 // For AVX-length vectors, build the individual 128-bit pieces and use 5244 // shuffles to put them in place. 5245 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5246 SmallVector<SDValue, 32> V; 5247 for (unsigned i = 0; i < NumElems; ++i) 5248 V.push_back(Op.getOperand(i)); 5249 5250 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5251 5252 // Build both the lower and upper subvector. 5253 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5254 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5255 NumElems/2); 5256 5257 // Recreate the wider vector with the lower and upper part. 5258 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5259 DAG.getConstant(0, MVT::i32), DAG, dl); 5260 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5261 DAG, dl); 5262 } 5263 5264 // Let legalizer expand 2-wide build_vectors. 5265 if (EVTBits == 64) { 5266 if (NumNonZero == 1) { 5267 // One half is zero or undef. 5268 unsigned Idx = CountTrailingZeros_32(NonZeros); 5269 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5270 Op.getOperand(Idx)); 5271 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5272 Subtarget->hasSSE2(), DAG); 5273 } 5274 return SDValue(); 5275 } 5276 5277 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5278 if (EVTBits == 8 && NumElems == 16) { 5279 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5280 *this); 5281 if (V.getNode()) return V; 5282 } 5283 5284 if (EVTBits == 16 && NumElems == 8) { 5285 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5286 *this); 5287 if (V.getNode()) return V; 5288 } 5289 5290 // If element VT is == 32 bits, turn it into a number of shuffles. 5291 SmallVector<SDValue, 8> V; 5292 V.resize(NumElems); 5293 if (NumElems == 4 && NumZero > 0) { 5294 for (unsigned i = 0; i < 4; ++i) { 5295 bool isZero = !(NonZeros & (1 << i)); 5296 if (isZero) 5297 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5298 else 5299 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5300 } 5301 5302 for (unsigned i = 0; i < 2; ++i) { 5303 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5304 default: break; 5305 case 0: 5306 V[i] = V[i*2]; // Must be a zero vector. 5307 break; 5308 case 1: 5309 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5310 break; 5311 case 2: 5312 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5313 break; 5314 case 3: 5315 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5316 break; 5317 } 5318 } 5319 5320 SmallVector<int, 8> MaskVec; 5321 bool Reverse = (NonZeros & 0x3) == 2; 5322 for (unsigned i = 0; i < 2; ++i) 5323 MaskVec.push_back(Reverse ? 1-i : i); 5324 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5325 for (unsigned i = 0; i < 2; ++i) 5326 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5327 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5328 } 5329 5330 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5331 // Check for a build vector of consecutive loads. 5332 for (unsigned i = 0; i < NumElems; ++i) 5333 V[i] = Op.getOperand(i); 5334 5335 // Check for elements which are consecutive loads. 5336 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5337 if (LD.getNode()) 5338 return LD; 5339 5340 // For SSE 4.1, use insertps to put the high elements into the low element. 5341 if (getSubtarget()->hasSSE41()) { 5342 SDValue Result; 5343 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5344 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5345 else 5346 Result = DAG.getUNDEF(VT); 5347 5348 for (unsigned i = 1; i < NumElems; ++i) { 5349 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5350 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5351 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5352 } 5353 return Result; 5354 } 5355 5356 // Otherwise, expand into a number of unpckl*, start by extending each of 5357 // our (non-undef) elements to the full vector width with the element in the 5358 // bottom slot of the vector (which generates no code for SSE). 5359 for (unsigned i = 0; i < NumElems; ++i) { 5360 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5362 else 5363 V[i] = DAG.getUNDEF(VT); 5364 } 5365 5366 // Next, we iteratively mix elements, e.g. for v4f32: 5367 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5368 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5369 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5370 unsigned EltStride = NumElems >> 1; 5371 while (EltStride != 0) { 5372 for (unsigned i = 0; i < EltStride; ++i) { 5373 // If V[i+EltStride] is undef and this is the first round of mixing, 5374 // then it is safe to just drop this shuffle: V[i] is already in the 5375 // right place, the one element (since it's the first round) being 5376 // inserted as undef can be dropped. This isn't safe for successive 5377 // rounds because they will permute elements within both vectors. 5378 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5379 EltStride == NumElems/2) 5380 continue; 5381 5382 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5383 } 5384 EltStride >>= 1; 5385 } 5386 return V[0]; 5387 } 5388 return SDValue(); 5389} 5390 5391// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5392// them in a MMX register. This is better than doing a stack convert. 5393static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5394 DebugLoc dl = Op.getDebugLoc(); 5395 EVT ResVT = Op.getValueType(); 5396 5397 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5398 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5399 int Mask[2]; 5400 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5401 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5402 InVec = Op.getOperand(1); 5403 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5404 unsigned NumElts = ResVT.getVectorNumElements(); 5405 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5406 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5407 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5408 } else { 5409 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5410 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5411 Mask[0] = 0; Mask[1] = 2; 5412 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5413 } 5414 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5415} 5416 5417// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5418// to create 256-bit vectors from two other 128-bit ones. 5419static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5420 DebugLoc dl = Op.getDebugLoc(); 5421 EVT ResVT = Op.getValueType(); 5422 5423 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5424 5425 SDValue V1 = Op.getOperand(0); 5426 SDValue V2 = Op.getOperand(1); 5427 unsigned NumElems = ResVT.getVectorNumElements(); 5428 5429 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5430 DAG.getConstant(0, MVT::i32), DAG, dl); 5431 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5432 DAG, dl); 5433} 5434 5435SDValue 5436X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5437 EVT ResVT = Op.getValueType(); 5438 5439 assert(Op.getNumOperands() == 2); 5440 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5441 "Unsupported CONCAT_VECTORS for value type"); 5442 5443 // We support concatenate two MMX registers and place them in a MMX register. 5444 // This is better than doing a stack convert. 5445 if (ResVT.is128BitVector()) 5446 return LowerMMXCONCAT_VECTORS(Op, DAG); 5447 5448 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5449 // from two other 128-bit ones. 5450 return LowerAVXCONCAT_VECTORS(Op, DAG); 5451} 5452 5453// v8i16 shuffles - Prefer shuffles in the following order: 5454// 1. [all] pshuflw, pshufhw, optional move 5455// 2. [ssse3] 1 x pshufb 5456// 3. [ssse3] 2 x pshufb + 1 x por 5457// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5458SDValue 5459X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5460 SelectionDAG &DAG) const { 5461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5462 SDValue V1 = SVOp->getOperand(0); 5463 SDValue V2 = SVOp->getOperand(1); 5464 DebugLoc dl = SVOp->getDebugLoc(); 5465 SmallVector<int, 8> MaskVals; 5466 5467 // Determine if more than 1 of the words in each of the low and high quadwords 5468 // of the result come from the same quadword of one of the two inputs. Undef 5469 // mask values count as coming from any quadword, for better codegen. 5470 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5471 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5472 BitVector InputQuads(4); 5473 for (unsigned i = 0; i < 8; ++i) { 5474 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5475 int EltIdx = SVOp->getMaskElt(i); 5476 MaskVals.push_back(EltIdx); 5477 if (EltIdx < 0) { 5478 ++Quad[0]; 5479 ++Quad[1]; 5480 ++Quad[2]; 5481 ++Quad[3]; 5482 continue; 5483 } 5484 ++Quad[EltIdx / 4]; 5485 InputQuads.set(EltIdx / 4); 5486 } 5487 5488 int BestLoQuad = -1; 5489 unsigned MaxQuad = 1; 5490 for (unsigned i = 0; i < 4; ++i) { 5491 if (LoQuad[i] > MaxQuad) { 5492 BestLoQuad = i; 5493 MaxQuad = LoQuad[i]; 5494 } 5495 } 5496 5497 int BestHiQuad = -1; 5498 MaxQuad = 1; 5499 for (unsigned i = 0; i < 4; ++i) { 5500 if (HiQuad[i] > MaxQuad) { 5501 BestHiQuad = i; 5502 MaxQuad = HiQuad[i]; 5503 } 5504 } 5505 5506 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5507 // of the two input vectors, shuffle them into one input vector so only a 5508 // single pshufb instruction is necessary. If There are more than 2 input 5509 // quads, disable the next transformation since it does not help SSSE3. 5510 bool V1Used = InputQuads[0] || InputQuads[1]; 5511 bool V2Used = InputQuads[2] || InputQuads[3]; 5512 if (Subtarget->hasSSSE3()) { 5513 if (InputQuads.count() == 2 && V1Used && V2Used) { 5514 BestLoQuad = InputQuads.find_first(); 5515 BestHiQuad = InputQuads.find_next(BestLoQuad); 5516 } 5517 if (InputQuads.count() > 2) { 5518 BestLoQuad = -1; 5519 BestHiQuad = -1; 5520 } 5521 } 5522 5523 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5524 // the shuffle mask. If a quad is scored as -1, that means that it contains 5525 // words from all 4 input quadwords. 5526 SDValue NewV; 5527 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5528 SmallVector<int, 8> MaskV; 5529 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5530 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5531 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5532 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5533 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5534 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5535 5536 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5537 // source words for the shuffle, to aid later transformations. 5538 bool AllWordsInNewV = true; 5539 bool InOrder[2] = { true, true }; 5540 for (unsigned i = 0; i != 8; ++i) { 5541 int idx = MaskVals[i]; 5542 if (idx != (int)i) 5543 InOrder[i/4] = false; 5544 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5545 continue; 5546 AllWordsInNewV = false; 5547 break; 5548 } 5549 5550 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5551 if (AllWordsInNewV) { 5552 for (int i = 0; i != 8; ++i) { 5553 int idx = MaskVals[i]; 5554 if (idx < 0) 5555 continue; 5556 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5557 if ((idx != i) && idx < 4) 5558 pshufhw = false; 5559 if ((idx != i) && idx > 3) 5560 pshuflw = false; 5561 } 5562 V1 = NewV; 5563 V2Used = false; 5564 BestLoQuad = 0; 5565 BestHiQuad = 1; 5566 } 5567 5568 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5569 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5570 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5571 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5572 unsigned TargetMask = 0; 5573 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5574 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5575 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5576 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5577 V1 = NewV.getOperand(0); 5578 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5579 } 5580 } 5581 5582 // If we have SSSE3, and all words of the result are from 1 input vector, 5583 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5584 // is present, fall back to case 4. 5585 if (Subtarget->hasSSSE3()) { 5586 SmallVector<SDValue,16> pshufbMask; 5587 5588 // If we have elements from both input vectors, set the high bit of the 5589 // shuffle mask element to zero out elements that come from V2 in the V1 5590 // mask, and elements that come from V1 in the V2 mask, so that the two 5591 // results can be OR'd together. 5592 bool TwoInputs = V1Used && V2Used; 5593 for (unsigned i = 0; i != 8; ++i) { 5594 int EltIdx = MaskVals[i] * 2; 5595 if (TwoInputs && (EltIdx >= 16)) { 5596 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5597 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5598 continue; 5599 } 5600 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5601 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5602 } 5603 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5604 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5605 DAG.getNode(ISD::BUILD_VECTOR, dl, 5606 MVT::v16i8, &pshufbMask[0], 16)); 5607 if (!TwoInputs) 5608 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5609 5610 // Calculate the shuffle mask for the second input, shuffle it, and 5611 // OR it with the first shuffled input. 5612 pshufbMask.clear(); 5613 for (unsigned i = 0; i != 8; ++i) { 5614 int EltIdx = MaskVals[i] * 2; 5615 if (EltIdx < 16) { 5616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5617 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5618 continue; 5619 } 5620 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5621 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5622 } 5623 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5624 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5625 DAG.getNode(ISD::BUILD_VECTOR, dl, 5626 MVT::v16i8, &pshufbMask[0], 16)); 5627 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5628 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5629 } 5630 5631 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5632 // and update MaskVals with new element order. 5633 BitVector InOrder(8); 5634 if (BestLoQuad >= 0) { 5635 SmallVector<int, 8> MaskV; 5636 for (int i = 0; i != 4; ++i) { 5637 int idx = MaskVals[i]; 5638 if (idx < 0) { 5639 MaskV.push_back(-1); 5640 InOrder.set(i); 5641 } else if ((idx / 4) == BestLoQuad) { 5642 MaskV.push_back(idx & 3); 5643 InOrder.set(i); 5644 } else { 5645 MaskV.push_back(-1); 5646 } 5647 } 5648 for (unsigned i = 4; i != 8; ++i) 5649 MaskV.push_back(i); 5650 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5651 &MaskV[0]); 5652 5653 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5654 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5655 NewV.getOperand(0), 5656 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5657 DAG); 5658 } 5659 5660 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5661 // and update MaskVals with the new element order. 5662 if (BestHiQuad >= 0) { 5663 SmallVector<int, 8> MaskV; 5664 for (unsigned i = 0; i != 4; ++i) 5665 MaskV.push_back(i); 5666 for (unsigned i = 4; i != 8; ++i) { 5667 int idx = MaskVals[i]; 5668 if (idx < 0) { 5669 MaskV.push_back(-1); 5670 InOrder.set(i); 5671 } else if ((idx / 4) == BestHiQuad) { 5672 MaskV.push_back((idx & 3) + 4); 5673 InOrder.set(i); 5674 } else { 5675 MaskV.push_back(-1); 5676 } 5677 } 5678 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5679 &MaskV[0]); 5680 5681 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5682 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5683 NewV.getOperand(0), 5684 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5685 DAG); 5686 } 5687 5688 // In case BestHi & BestLo were both -1, which means each quadword has a word 5689 // from each of the four input quadwords, calculate the InOrder bitvector now 5690 // before falling through to the insert/extract cleanup. 5691 if (BestLoQuad == -1 && BestHiQuad == -1) { 5692 NewV = V1; 5693 for (int i = 0; i != 8; ++i) 5694 if (MaskVals[i] < 0 || MaskVals[i] == i) 5695 InOrder.set(i); 5696 } 5697 5698 // The other elements are put in the right place using pextrw and pinsrw. 5699 for (unsigned i = 0; i != 8; ++i) { 5700 if (InOrder[i]) 5701 continue; 5702 int EltIdx = MaskVals[i]; 5703 if (EltIdx < 0) 5704 continue; 5705 SDValue ExtOp = (EltIdx < 8) 5706 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5707 DAG.getIntPtrConstant(EltIdx)) 5708 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5709 DAG.getIntPtrConstant(EltIdx - 8)); 5710 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5711 DAG.getIntPtrConstant(i)); 5712 } 5713 return NewV; 5714} 5715 5716// v16i8 shuffles - Prefer shuffles in the following order: 5717// 1. [ssse3] 1 x pshufb 5718// 2. [ssse3] 2 x pshufb + 1 x por 5719// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5720static 5721SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5722 SelectionDAG &DAG, 5723 const X86TargetLowering &TLI) { 5724 SDValue V1 = SVOp->getOperand(0); 5725 SDValue V2 = SVOp->getOperand(1); 5726 DebugLoc dl = SVOp->getDebugLoc(); 5727 SmallVector<int, 16> MaskVals; 5728 SVOp->getMask(MaskVals); 5729 5730 // If we have SSSE3, case 1 is generated when all result bytes come from 5731 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5732 // present, fall back to case 3. 5733 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5734 bool V1Only = true; 5735 bool V2Only = true; 5736 for (unsigned i = 0; i < 16; ++i) { 5737 int EltIdx = MaskVals[i]; 5738 if (EltIdx < 0) 5739 continue; 5740 if (EltIdx < 16) 5741 V2Only = false; 5742 else 5743 V1Only = false; 5744 } 5745 5746 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5747 if (TLI.getSubtarget()->hasSSSE3()) { 5748 SmallVector<SDValue,16> pshufbMask; 5749 5750 // If all result elements are from one input vector, then only translate 5751 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5752 // 5753 // Otherwise, we have elements from both input vectors, and must zero out 5754 // elements that come from V2 in the first mask, and V1 in the second mask 5755 // so that we can OR them together. 5756 bool TwoInputs = !(V1Only || V2Only); 5757 for (unsigned i = 0; i != 16; ++i) { 5758 int EltIdx = MaskVals[i]; 5759 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5760 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5761 continue; 5762 } 5763 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5764 } 5765 // If all the elements are from V2, assign it to V1 and return after 5766 // building the first pshufb. 5767 if (V2Only) 5768 V1 = V2; 5769 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5770 DAG.getNode(ISD::BUILD_VECTOR, dl, 5771 MVT::v16i8, &pshufbMask[0], 16)); 5772 if (!TwoInputs) 5773 return V1; 5774 5775 // Calculate the shuffle mask for the second input, shuffle it, and 5776 // OR it with the first shuffled input. 5777 pshufbMask.clear(); 5778 for (unsigned i = 0; i != 16; ++i) { 5779 int EltIdx = MaskVals[i]; 5780 if (EltIdx < 16) { 5781 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5782 continue; 5783 } 5784 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5785 } 5786 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5787 DAG.getNode(ISD::BUILD_VECTOR, dl, 5788 MVT::v16i8, &pshufbMask[0], 16)); 5789 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5790 } 5791 5792 // No SSSE3 - Calculate in place words and then fix all out of place words 5793 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5794 // the 16 different words that comprise the two doublequadword input vectors. 5795 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5796 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5797 SDValue NewV = V2Only ? V2 : V1; 5798 for (int i = 0; i != 8; ++i) { 5799 int Elt0 = MaskVals[i*2]; 5800 int Elt1 = MaskVals[i*2+1]; 5801 5802 // This word of the result is all undef, skip it. 5803 if (Elt0 < 0 && Elt1 < 0) 5804 continue; 5805 5806 // This word of the result is already in the correct place, skip it. 5807 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5808 continue; 5809 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5810 continue; 5811 5812 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5813 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5814 SDValue InsElt; 5815 5816 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5817 // using a single extract together, load it and store it. 5818 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5819 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5820 DAG.getIntPtrConstant(Elt1 / 2)); 5821 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5822 DAG.getIntPtrConstant(i)); 5823 continue; 5824 } 5825 5826 // If Elt1 is defined, extract it from the appropriate source. If the 5827 // source byte is not also odd, shift the extracted word left 8 bits 5828 // otherwise clear the bottom 8 bits if we need to do an or. 5829 if (Elt1 >= 0) { 5830 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5831 DAG.getIntPtrConstant(Elt1 / 2)); 5832 if ((Elt1 & 1) == 0) 5833 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5834 DAG.getConstant(8, 5835 TLI.getShiftAmountTy(InsElt.getValueType()))); 5836 else if (Elt0 >= 0) 5837 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5838 DAG.getConstant(0xFF00, MVT::i16)); 5839 } 5840 // If Elt0 is defined, extract it from the appropriate source. If the 5841 // source byte is not also even, shift the extracted word right 8 bits. If 5842 // Elt1 was also defined, OR the extracted values together before 5843 // inserting them in the result. 5844 if (Elt0 >= 0) { 5845 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5846 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5847 if ((Elt0 & 1) != 0) 5848 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5849 DAG.getConstant(8, 5850 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5851 else if (Elt1 >= 0) 5852 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5853 DAG.getConstant(0x00FF, MVT::i16)); 5854 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5855 : InsElt0; 5856 } 5857 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5858 DAG.getIntPtrConstant(i)); 5859 } 5860 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5861} 5862 5863/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5864/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5865/// done when every pair / quad of shuffle mask elements point to elements in 5866/// the right sequence. e.g. 5867/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5868static 5869SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5870 SelectionDAG &DAG, DebugLoc dl) { 5871 EVT VT = SVOp->getValueType(0); 5872 SDValue V1 = SVOp->getOperand(0); 5873 SDValue V2 = SVOp->getOperand(1); 5874 unsigned NumElems = VT.getVectorNumElements(); 5875 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5876 EVT NewVT; 5877 switch (VT.getSimpleVT().SimpleTy) { 5878 default: assert(false && "Unexpected!"); 5879 case MVT::v4f32: NewVT = MVT::v2f64; break; 5880 case MVT::v4i32: NewVT = MVT::v2i64; break; 5881 case MVT::v8i16: NewVT = MVT::v4i32; break; 5882 case MVT::v16i8: NewVT = MVT::v4i32; break; 5883 } 5884 5885 int Scale = NumElems / NewWidth; 5886 SmallVector<int, 8> MaskVec; 5887 for (unsigned i = 0; i < NumElems; i += Scale) { 5888 int StartIdx = -1; 5889 for (int j = 0; j < Scale; ++j) { 5890 int EltIdx = SVOp->getMaskElt(i+j); 5891 if (EltIdx < 0) 5892 continue; 5893 if (StartIdx == -1) 5894 StartIdx = EltIdx - (EltIdx % Scale); 5895 if (EltIdx != StartIdx + j) 5896 return SDValue(); 5897 } 5898 if (StartIdx == -1) 5899 MaskVec.push_back(-1); 5900 else 5901 MaskVec.push_back(StartIdx / Scale); 5902 } 5903 5904 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5905 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5906 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5907} 5908 5909/// getVZextMovL - Return a zero-extending vector move low node. 5910/// 5911static SDValue getVZextMovL(EVT VT, EVT OpVT, 5912 SDValue SrcOp, SelectionDAG &DAG, 5913 const X86Subtarget *Subtarget, DebugLoc dl) { 5914 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5915 LoadSDNode *LD = NULL; 5916 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5917 LD = dyn_cast<LoadSDNode>(SrcOp); 5918 if (!LD) { 5919 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5920 // instead. 5921 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5922 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5923 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5924 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5925 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5926 // PR2108 5927 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5928 return DAG.getNode(ISD::BITCAST, dl, VT, 5929 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5930 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5931 OpVT, 5932 SrcOp.getOperand(0) 5933 .getOperand(0)))); 5934 } 5935 } 5936 } 5937 5938 return DAG.getNode(ISD::BITCAST, dl, VT, 5939 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5940 DAG.getNode(ISD::BITCAST, dl, 5941 OpVT, SrcOp))); 5942} 5943 5944/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5945/// shuffle node referes to only one lane in the sources. 5946static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5947 EVT VT = SVOp->getValueType(0); 5948 int NumElems = VT.getVectorNumElements(); 5949 int HalfSize = NumElems/2; 5950 SmallVector<int, 16> M; 5951 SVOp->getMask(M); 5952 bool MatchA = false, MatchB = false; 5953 5954 for (int l = 0; l < NumElems*2; l += HalfSize) { 5955 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5956 MatchA = true; 5957 break; 5958 } 5959 } 5960 5961 for (int l = 0; l < NumElems*2; l += HalfSize) { 5962 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5963 MatchB = true; 5964 break; 5965 } 5966 } 5967 5968 return MatchA && MatchB; 5969} 5970 5971/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5972/// which could not be matched by any known target speficic shuffle 5973static SDValue 5974LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5975 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5976 // If each half of a vector shuffle node referes to only one lane in the 5977 // source vectors, extract each used 128-bit lane and shuffle them using 5978 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5979 // the work to the legalizer. 5980 DebugLoc dl = SVOp->getDebugLoc(); 5981 EVT VT = SVOp->getValueType(0); 5982 int NumElems = VT.getVectorNumElements(); 5983 int HalfSize = NumElems/2; 5984 5985 // Extract the reference for each half 5986 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5987 int FstVecOpNum = 0, SndVecOpNum = 0; 5988 for (int i = 0; i < HalfSize; ++i) { 5989 int Elt = SVOp->getMaskElt(i); 5990 if (SVOp->getMaskElt(i) < 0) 5991 continue; 5992 FstVecOpNum = Elt/NumElems; 5993 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5994 break; 5995 } 5996 for (int i = HalfSize; i < NumElems; ++i) { 5997 int Elt = SVOp->getMaskElt(i); 5998 if (SVOp->getMaskElt(i) < 0) 5999 continue; 6000 SndVecOpNum = Elt/NumElems; 6001 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6002 break; 6003 } 6004 6005 // Extract the subvectors 6006 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 6007 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 6008 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 6009 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 6010 6011 // Generate 128-bit shuffles 6012 SmallVector<int, 16> MaskV1, MaskV2; 6013 for (int i = 0; i < HalfSize; ++i) { 6014 int Elt = SVOp->getMaskElt(i); 6015 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6016 } 6017 for (int i = HalfSize; i < NumElems; ++i) { 6018 int Elt = SVOp->getMaskElt(i); 6019 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6020 } 6021 6022 EVT NVT = V1.getValueType(); 6023 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 6024 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 6025 6026 // Concatenate the result back 6027 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6028 DAG.getConstant(0, MVT::i32), DAG, dl); 6029 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6030 DAG, dl); 6031 } 6032 6033 return SDValue(); 6034} 6035 6036/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6037/// 4 elements, and match them with several different shuffle types. 6038static SDValue 6039LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6040 SDValue V1 = SVOp->getOperand(0); 6041 SDValue V2 = SVOp->getOperand(1); 6042 DebugLoc dl = SVOp->getDebugLoc(); 6043 EVT VT = SVOp->getValueType(0); 6044 6045 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6046 6047 SmallVector<std::pair<int, int>, 8> Locs; 6048 Locs.resize(4); 6049 SmallVector<int, 8> Mask1(4U, -1); 6050 SmallVector<int, 8> PermMask; 6051 SVOp->getMask(PermMask); 6052 6053 unsigned NumHi = 0; 6054 unsigned NumLo = 0; 6055 for (unsigned i = 0; i != 4; ++i) { 6056 int Idx = PermMask[i]; 6057 if (Idx < 0) { 6058 Locs[i] = std::make_pair(-1, -1); 6059 } else { 6060 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6061 if (Idx < 4) { 6062 Locs[i] = std::make_pair(0, NumLo); 6063 Mask1[NumLo] = Idx; 6064 NumLo++; 6065 } else { 6066 Locs[i] = std::make_pair(1, NumHi); 6067 if (2+NumHi < 4) 6068 Mask1[2+NumHi] = Idx; 6069 NumHi++; 6070 } 6071 } 6072 } 6073 6074 if (NumLo <= 2 && NumHi <= 2) { 6075 // If no more than two elements come from either vector. This can be 6076 // implemented with two shuffles. First shuffle gather the elements. 6077 // The second shuffle, which takes the first shuffle as both of its 6078 // vector operands, put the elements into the right order. 6079 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6080 6081 SmallVector<int, 8> Mask2(4U, -1); 6082 6083 for (unsigned i = 0; i != 4; ++i) { 6084 if (Locs[i].first == -1) 6085 continue; 6086 else { 6087 unsigned Idx = (i < 2) ? 0 : 4; 6088 Idx += Locs[i].first * 2 + Locs[i].second; 6089 Mask2[i] = Idx; 6090 } 6091 } 6092 6093 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6094 } else if (NumLo == 3 || NumHi == 3) { 6095 // Otherwise, we must have three elements from one vector, call it X, and 6096 // one element from the other, call it Y. First, use a shufps to build an 6097 // intermediate vector with the one element from Y and the element from X 6098 // that will be in the same half in the final destination (the indexes don't 6099 // matter). Then, use a shufps to build the final vector, taking the half 6100 // containing the element from Y from the intermediate, and the other half 6101 // from X. 6102 if (NumHi == 3) { 6103 // Normalize it so the 3 elements come from V1. 6104 CommuteVectorShuffleMask(PermMask, 4); 6105 std::swap(V1, V2); 6106 } 6107 6108 // Find the element from V2. 6109 unsigned HiIndex; 6110 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6111 int Val = PermMask[HiIndex]; 6112 if (Val < 0) 6113 continue; 6114 if (Val >= 4) 6115 break; 6116 } 6117 6118 Mask1[0] = PermMask[HiIndex]; 6119 Mask1[1] = -1; 6120 Mask1[2] = PermMask[HiIndex^1]; 6121 Mask1[3] = -1; 6122 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6123 6124 if (HiIndex >= 2) { 6125 Mask1[0] = PermMask[0]; 6126 Mask1[1] = PermMask[1]; 6127 Mask1[2] = HiIndex & 1 ? 6 : 4; 6128 Mask1[3] = HiIndex & 1 ? 4 : 6; 6129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6130 } else { 6131 Mask1[0] = HiIndex & 1 ? 2 : 0; 6132 Mask1[1] = HiIndex & 1 ? 0 : 2; 6133 Mask1[2] = PermMask[2]; 6134 Mask1[3] = PermMask[3]; 6135 if (Mask1[2] >= 0) 6136 Mask1[2] += 4; 6137 if (Mask1[3] >= 0) 6138 Mask1[3] += 4; 6139 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6140 } 6141 } 6142 6143 // Break it into (shuffle shuffle_hi, shuffle_lo). 6144 Locs.clear(); 6145 Locs.resize(4); 6146 SmallVector<int,8> LoMask(4U, -1); 6147 SmallVector<int,8> HiMask(4U, -1); 6148 6149 SmallVector<int,8> *MaskPtr = &LoMask; 6150 unsigned MaskIdx = 0; 6151 unsigned LoIdx = 0; 6152 unsigned HiIdx = 2; 6153 for (unsigned i = 0; i != 4; ++i) { 6154 if (i == 2) { 6155 MaskPtr = &HiMask; 6156 MaskIdx = 1; 6157 LoIdx = 0; 6158 HiIdx = 2; 6159 } 6160 int Idx = PermMask[i]; 6161 if (Idx < 0) { 6162 Locs[i] = std::make_pair(-1, -1); 6163 } else if (Idx < 4) { 6164 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6165 (*MaskPtr)[LoIdx] = Idx; 6166 LoIdx++; 6167 } else { 6168 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6169 (*MaskPtr)[HiIdx] = Idx; 6170 HiIdx++; 6171 } 6172 } 6173 6174 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6175 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6176 SmallVector<int, 8> MaskOps; 6177 for (unsigned i = 0; i != 4; ++i) { 6178 if (Locs[i].first == -1) { 6179 MaskOps.push_back(-1); 6180 } else { 6181 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6182 MaskOps.push_back(Idx); 6183 } 6184 } 6185 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6186} 6187 6188static bool MayFoldVectorLoad(SDValue V) { 6189 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6190 V = V.getOperand(0); 6191 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6192 V = V.getOperand(0); 6193 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6194 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6195 // BUILD_VECTOR (load), undef 6196 V = V.getOperand(0); 6197 if (MayFoldLoad(V)) 6198 return true; 6199 return false; 6200} 6201 6202// FIXME: the version above should always be used. Since there's 6203// a bug where several vector shuffles can't be folded because the 6204// DAG is not updated during lowering and a node claims to have two 6205// uses while it only has one, use this version, and let isel match 6206// another instruction if the load really happens to have more than 6207// one use. Remove this version after this bug get fixed. 6208// rdar://8434668, PR8156 6209static bool RelaxedMayFoldVectorLoad(SDValue V) { 6210 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6211 V = V.getOperand(0); 6212 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6213 V = V.getOperand(0); 6214 if (ISD::isNormalLoad(V.getNode())) 6215 return true; 6216 return false; 6217} 6218 6219/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6220/// a vector extract, and if both can be later optimized into a single load. 6221/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6222/// here because otherwise a target specific shuffle node is going to be 6223/// emitted for this shuffle, and the optimization not done. 6224/// FIXME: This is probably not the best approach, but fix the problem 6225/// until the right path is decided. 6226static 6227bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6228 const TargetLowering &TLI) { 6229 EVT VT = V.getValueType(); 6230 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6231 6232 // Be sure that the vector shuffle is present in a pattern like this: 6233 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6234 if (!V.hasOneUse()) 6235 return false; 6236 6237 SDNode *N = *V.getNode()->use_begin(); 6238 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6239 return false; 6240 6241 SDValue EltNo = N->getOperand(1); 6242 if (!isa<ConstantSDNode>(EltNo)) 6243 return false; 6244 6245 // If the bit convert changed the number of elements, it is unsafe 6246 // to examine the mask. 6247 bool HasShuffleIntoBitcast = false; 6248 if (V.getOpcode() == ISD::BITCAST) { 6249 EVT SrcVT = V.getOperand(0).getValueType(); 6250 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6251 return false; 6252 V = V.getOperand(0); 6253 HasShuffleIntoBitcast = true; 6254 } 6255 6256 // Select the input vector, guarding against out of range extract vector. 6257 unsigned NumElems = VT.getVectorNumElements(); 6258 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6259 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6260 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6261 6262 // Skip one more bit_convert if necessary 6263 if (V.getOpcode() == ISD::BITCAST) 6264 V = V.getOperand(0); 6265 6266 if (!ISD::isNormalLoad(V.getNode())) 6267 return false; 6268 6269 // Is the original load suitable? 6270 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6271 6272 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6273 return false; 6274 6275 if (!HasShuffleIntoBitcast) 6276 return true; 6277 6278 // If there's a bitcast before the shuffle, check if the load type and 6279 // alignment is valid. 6280 unsigned Align = LN0->getAlignment(); 6281 unsigned NewAlign = 6282 TLI.getTargetData()->getABITypeAlignment( 6283 VT.getTypeForEVT(*DAG.getContext())); 6284 6285 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6286 return false; 6287 6288 return true; 6289} 6290 6291static 6292SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6293 EVT VT = Op.getValueType(); 6294 6295 // Canonizalize to v2f64. 6296 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6297 return DAG.getNode(ISD::BITCAST, dl, VT, 6298 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6299 V1, DAG)); 6300} 6301 6302static 6303SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6304 bool HasSSE2) { 6305 SDValue V1 = Op.getOperand(0); 6306 SDValue V2 = Op.getOperand(1); 6307 EVT VT = Op.getValueType(); 6308 6309 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6310 6311 if (HasSSE2 && VT == MVT::v2f64) 6312 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6313 6314 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6315 return DAG.getNode(ISD::BITCAST, dl, VT, 6316 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6317 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6318 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6319} 6320 6321static 6322SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6323 SDValue V1 = Op.getOperand(0); 6324 SDValue V2 = Op.getOperand(1); 6325 EVT VT = Op.getValueType(); 6326 6327 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6328 "unsupported shuffle type"); 6329 6330 if (V2.getOpcode() == ISD::UNDEF) 6331 V2 = V1; 6332 6333 // v4i32 or v4f32 6334 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6335} 6336 6337static 6338SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6339 SDValue V1 = Op.getOperand(0); 6340 SDValue V2 = Op.getOperand(1); 6341 EVT VT = Op.getValueType(); 6342 unsigned NumElems = VT.getVectorNumElements(); 6343 6344 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6345 // operand of these instructions is only memory, so check if there's a 6346 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6347 // same masks. 6348 bool CanFoldLoad = false; 6349 6350 // Trivial case, when V2 comes from a load. 6351 if (MayFoldVectorLoad(V2)) 6352 CanFoldLoad = true; 6353 6354 // When V1 is a load, it can be folded later into a store in isel, example: 6355 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6356 // turns into: 6357 // (MOVLPSmr addr:$src1, VR128:$src2) 6358 // So, recognize this potential and also use MOVLPS or MOVLPD 6359 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6360 CanFoldLoad = true; 6361 6362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6363 if (CanFoldLoad) { 6364 if (HasSSE2 && NumElems == 2) 6365 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6366 6367 if (NumElems == 4) 6368 // If we don't care about the second element, procede to use movss. 6369 if (SVOp->getMaskElt(1) != -1) 6370 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6371 } 6372 6373 // movl and movlp will both match v2i64, but v2i64 is never matched by 6374 // movl earlier because we make it strict to avoid messing with the movlp load 6375 // folding logic (see the code above getMOVLP call). Match it here then, 6376 // this is horrible, but will stay like this until we move all shuffle 6377 // matching to x86 specific nodes. Note that for the 1st condition all 6378 // types are matched with movsd. 6379 if (HasSSE2) { 6380 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6381 // as to remove this logic from here, as much as possible 6382 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6383 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6384 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6385 } 6386 6387 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6388 6389 // Invert the operand order and use SHUFPS to match it. 6390 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6391 X86::getShuffleSHUFImmediate(SVOp), DAG); 6392} 6393 6394static 6395SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6396 const TargetLowering &TLI, 6397 const X86Subtarget *Subtarget) { 6398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6399 EVT VT = Op.getValueType(); 6400 DebugLoc dl = Op.getDebugLoc(); 6401 SDValue V1 = Op.getOperand(0); 6402 SDValue V2 = Op.getOperand(1); 6403 6404 if (isZeroShuffle(SVOp)) 6405 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 6406 6407 // Handle splat operations 6408 if (SVOp->isSplat()) { 6409 unsigned NumElem = VT.getVectorNumElements(); 6410 int Size = VT.getSizeInBits(); 6411 // Special case, this is the only place now where it's allowed to return 6412 // a vector_shuffle operation without using a target specific node, because 6413 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6414 // this be moved to DAGCombine instead? 6415 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6416 return Op; 6417 6418 // Use vbroadcast whenever the splat comes from a foldable load 6419 SDValue LD = isVectorBroadcast(Op, Subtarget); 6420 if (LD.getNode()) 6421 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6422 6423 // Handle splats by matching through known shuffle masks 6424 if ((Size == 128 && NumElem <= 4) || 6425 (Size == 256 && NumElem < 8)) 6426 return SDValue(); 6427 6428 // All remaning splats are promoted to target supported vector shuffles. 6429 return PromoteSplat(SVOp, DAG); 6430 } 6431 6432 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6433 // do it! 6434 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6435 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6436 if (NewOp.getNode()) 6437 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6438 } else if ((VT == MVT::v4i32 || 6439 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6440 // FIXME: Figure out a cleaner way to do this. 6441 // Try to make use of movq to zero out the top part. 6442 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6443 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6444 if (NewOp.getNode()) { 6445 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6446 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6447 DAG, Subtarget, dl); 6448 } 6449 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6450 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6451 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6452 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6453 DAG, Subtarget, dl); 6454 } 6455 } 6456 return SDValue(); 6457} 6458 6459SDValue 6460X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6462 SDValue V1 = Op.getOperand(0); 6463 SDValue V2 = Op.getOperand(1); 6464 EVT VT = Op.getValueType(); 6465 DebugLoc dl = Op.getDebugLoc(); 6466 unsigned NumElems = VT.getVectorNumElements(); 6467 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6468 bool V1IsSplat = false; 6469 bool V2IsSplat = false; 6470 bool HasSSE2 = Subtarget->hasSSE2(); 6471 bool HasAVX = Subtarget->hasAVX(); 6472 bool HasAVX2 = Subtarget->hasAVX2(); 6473 MachineFunction &MF = DAG.getMachineFunction(); 6474 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6475 6476 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6477 6478 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef"); 6479 6480 // Vector shuffle lowering takes 3 steps: 6481 // 6482 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6483 // narrowing and commutation of operands should be handled. 6484 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6485 // shuffle nodes. 6486 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6487 // so the shuffle can be broken into other shuffles and the legalizer can 6488 // try the lowering again. 6489 // 6490 // The general idea is that no vector_shuffle operation should be left to 6491 // be matched during isel, all of them must be converted to a target specific 6492 // node here. 6493 6494 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6495 // narrowing and commutation of operands should be handled. The actual code 6496 // doesn't include all of those, work in progress... 6497 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6498 if (NewOp.getNode()) 6499 return NewOp; 6500 6501 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6502 // unpckh_undef). Only use pshufd if speed is more important than size. 6503 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2)) 6504 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6505 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2)) 6506 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6507 6508 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() && 6509 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6510 return getMOVDDup(Op, dl, V1, DAG); 6511 6512 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6513 return getMOVHighToLow(Op, dl, DAG); 6514 6515 // Use to match splats 6516 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6517 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6518 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6519 6520 if (X86::isPSHUFDMask(SVOp)) { 6521 // The actual implementation will match the mask in the if above and then 6522 // during isel it can match several different instructions, not only pshufd 6523 // as its name says, sad but true, emulate the behavior for now... 6524 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6525 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6526 6527 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6528 6529 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6530 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6531 6532 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6533 TargetMask, DAG); 6534 } 6535 6536 // Check if this can be converted into a logical shift. 6537 bool isLeft = false; 6538 unsigned ShAmt = 0; 6539 SDValue ShVal; 6540 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6541 if (isShift && ShVal.hasOneUse()) { 6542 // If the shifted value has multiple uses, it may be cheaper to use 6543 // v_set0 + movlhps or movhlps, etc. 6544 EVT EltVT = VT.getVectorElementType(); 6545 ShAmt *= EltVT.getSizeInBits(); 6546 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6547 } 6548 6549 if (X86::isMOVLMask(SVOp)) { 6550 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6551 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6552 if (!X86::isMOVLPMask(SVOp)) { 6553 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6554 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6555 6556 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6557 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6558 } 6559 } 6560 6561 // FIXME: fold these into legal mask. 6562 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6563 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6564 6565 if (X86::isMOVHLPSMask(SVOp)) 6566 return getMOVHighToLow(Op, dl, DAG); 6567 6568 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6569 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6570 6571 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6572 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6573 6574 if (X86::isMOVLPMask(SVOp)) 6575 return getMOVLP(Op, dl, DAG, HasSSE2); 6576 6577 if (ShouldXformToMOVHLPS(SVOp) || 6578 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6579 return CommuteVectorShuffle(SVOp, DAG); 6580 6581 if (isShift) { 6582 // No better options. Use a vshl / vsrl. 6583 EVT EltVT = VT.getVectorElementType(); 6584 ShAmt *= EltVT.getSizeInBits(); 6585 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6586 } 6587 6588 bool Commuted = false; 6589 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6590 // 1,1,1,1 -> v8i16 though. 6591 V1IsSplat = isSplatVector(V1.getNode()); 6592 V2IsSplat = isSplatVector(V2.getNode()); 6593 6594 // Canonicalize the splat or undef, if present, to be on the RHS. 6595 if (V1IsSplat && !V2IsSplat) { 6596 Op = CommuteVectorShuffle(SVOp, DAG); 6597 SVOp = cast<ShuffleVectorSDNode>(Op); 6598 V1 = SVOp->getOperand(0); 6599 V2 = SVOp->getOperand(1); 6600 std::swap(V1IsSplat, V2IsSplat); 6601 Commuted = true; 6602 } 6603 6604 SmallVector<int, 32> M; 6605 SVOp->getMask(M); 6606 6607 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6608 // Shuffling low element of v1 into undef, just return v1. 6609 if (V2IsUndef) 6610 return V1; 6611 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6612 // the instruction selector will not match, so get a canonical MOVL with 6613 // swapped operands to undo the commute. 6614 return getMOVL(DAG, dl, VT, V2, V1); 6615 } 6616 6617 if (isUNPCKLMask(M, VT, HasAVX2)) 6618 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6619 6620 if (isUNPCKHMask(M, VT, HasAVX2)) 6621 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6622 6623 if (V2IsSplat) { 6624 // Normalize mask so all entries that point to V2 points to its first 6625 // element then try to match unpck{h|l} again. If match, return a 6626 // new vector_shuffle with the corrected mask. 6627 SDValue NewMask = NormalizeMask(SVOp, DAG); 6628 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6629 if (NSVOp != SVOp) { 6630 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6631 return NewMask; 6632 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6633 return NewMask; 6634 } 6635 } 6636 } 6637 6638 if (Commuted) { 6639 // Commute is back and try unpck* again. 6640 // FIXME: this seems wrong. 6641 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6642 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6643 6644 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6645 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); 6646 6647 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6648 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); 6649 } 6650 6651 // Normalize the node to match x86 shuffle ops if needed 6652 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) || 6653 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true))) 6654 return CommuteVectorShuffle(SVOp, DAG); 6655 6656 // The checks below are all present in isShuffleMaskLegal, but they are 6657 // inlined here right now to enable us to directly emit target specific 6658 // nodes, and remove one by one until they don't return Op anymore. 6659 6660 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) 6661 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6662 getShufflePALIGNRImmediate(SVOp), 6663 DAG); 6664 6665 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6666 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6667 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6668 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6669 } 6670 6671 if (isPSHUFHWMask(M, VT)) 6672 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6673 X86::getShufflePSHUFHWImmediate(SVOp), 6674 DAG); 6675 6676 if (isPSHUFLWMask(M, VT)) 6677 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6678 X86::getShufflePSHUFLWImmediate(SVOp), 6679 DAG); 6680 6681 if (isSHUFPMask(M, VT)) 6682 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6683 X86::getShuffleSHUFImmediate(SVOp), DAG); 6684 6685 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6686 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6687 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6688 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6689 6690 //===--------------------------------------------------------------------===// 6691 // Generate target specific nodes for 128 or 256-bit shuffles only 6692 // supported in the AVX instruction set. 6693 // 6694 6695 // Handle VMOVDDUPY permutations 6696 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6697 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6698 6699 // Handle VPERMILPS/D* permutations 6700 if (isVPERMILPMask(M, VT, HasAVX)) 6701 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6702 getShuffleVPERMILPImmediate(SVOp), DAG); 6703 6704 // Handle VPERM2F128/VPERM2I128 permutations 6705 if (isVPERM2X128Mask(M, VT, HasAVX)) 6706 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6707 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6708 6709 // Handle VSHUFPS/DY permutations 6710 if (isVSHUFPYMask(M, VT, HasAVX)) 6711 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6712 getShuffleVSHUFPYImmediate(SVOp), DAG); 6713 6714 //===--------------------------------------------------------------------===// 6715 // Since no target specific shuffle was selected for this generic one, 6716 // lower it into other known shuffles. FIXME: this isn't true yet, but 6717 // this is the plan. 6718 // 6719 6720 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6721 if (VT == MVT::v8i16) { 6722 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6723 if (NewOp.getNode()) 6724 return NewOp; 6725 } 6726 6727 if (VT == MVT::v16i8) { 6728 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6729 if (NewOp.getNode()) 6730 return NewOp; 6731 } 6732 6733 // Handle all 128-bit wide vectors with 4 elements, and match them with 6734 // several different shuffle types. 6735 if (NumElems == 4 && VT.getSizeInBits() == 128) 6736 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6737 6738 // Handle general 256-bit shuffles 6739 if (VT.is256BitVector()) 6740 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6741 6742 return SDValue(); 6743} 6744 6745SDValue 6746X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6747 SelectionDAG &DAG) const { 6748 EVT VT = Op.getValueType(); 6749 DebugLoc dl = Op.getDebugLoc(); 6750 6751 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6752 return SDValue(); 6753 6754 if (VT.getSizeInBits() == 8) { 6755 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6756 Op.getOperand(0), Op.getOperand(1)); 6757 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6758 DAG.getValueType(VT)); 6759 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6760 } else if (VT.getSizeInBits() == 16) { 6761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6762 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6763 if (Idx == 0) 6764 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6765 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6766 DAG.getNode(ISD::BITCAST, dl, 6767 MVT::v4i32, 6768 Op.getOperand(0)), 6769 Op.getOperand(1))); 6770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6771 Op.getOperand(0), Op.getOperand(1)); 6772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6773 DAG.getValueType(VT)); 6774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6775 } else if (VT == MVT::f32) { 6776 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6777 // the result back to FR32 register. It's only worth matching if the 6778 // result has a single use which is a store or a bitcast to i32. And in 6779 // the case of a store, it's not worth it if the index is a constant 0, 6780 // because a MOVSSmr can be used instead, which is smaller and faster. 6781 if (!Op.hasOneUse()) 6782 return SDValue(); 6783 SDNode *User = *Op.getNode()->use_begin(); 6784 if ((User->getOpcode() != ISD::STORE || 6785 (isa<ConstantSDNode>(Op.getOperand(1)) && 6786 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6787 (User->getOpcode() != ISD::BITCAST || 6788 User->getValueType(0) != MVT::i32)) 6789 return SDValue(); 6790 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6791 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6792 Op.getOperand(0)), 6793 Op.getOperand(1)); 6794 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6795 } else if (VT == MVT::i32 || VT == MVT::i64) { 6796 // ExtractPS/pextrq works with constant index. 6797 if (isa<ConstantSDNode>(Op.getOperand(1))) 6798 return Op; 6799 } 6800 return SDValue(); 6801} 6802 6803 6804SDValue 6805X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6806 SelectionDAG &DAG) const { 6807 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6808 return SDValue(); 6809 6810 SDValue Vec = Op.getOperand(0); 6811 EVT VecVT = Vec.getValueType(); 6812 6813 // If this is a 256-bit vector result, first extract the 128-bit vector and 6814 // then extract the element from the 128-bit vector. 6815 if (VecVT.getSizeInBits() == 256) { 6816 DebugLoc dl = Op.getNode()->getDebugLoc(); 6817 unsigned NumElems = VecVT.getVectorNumElements(); 6818 SDValue Idx = Op.getOperand(1); 6819 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6820 6821 // Get the 128-bit vector. 6822 bool Upper = IdxVal >= NumElems/2; 6823 Vec = Extract128BitVector(Vec, 6824 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6825 6826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6827 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6828 } 6829 6830 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6831 6832 if (Subtarget->hasSSE41()) { 6833 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6834 if (Res.getNode()) 6835 return Res; 6836 } 6837 6838 EVT VT = Op.getValueType(); 6839 DebugLoc dl = Op.getDebugLoc(); 6840 // TODO: handle v16i8. 6841 if (VT.getSizeInBits() == 16) { 6842 SDValue Vec = Op.getOperand(0); 6843 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6844 if (Idx == 0) 6845 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6846 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6847 DAG.getNode(ISD::BITCAST, dl, 6848 MVT::v4i32, Vec), 6849 Op.getOperand(1))); 6850 // Transform it so it match pextrw which produces a 32-bit result. 6851 EVT EltVT = MVT::i32; 6852 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6853 Op.getOperand(0), Op.getOperand(1)); 6854 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6855 DAG.getValueType(VT)); 6856 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6857 } else if (VT.getSizeInBits() == 32) { 6858 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6859 if (Idx == 0) 6860 return Op; 6861 6862 // SHUFPS the element to the lowest double word, then movss. 6863 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6864 EVT VVT = Op.getOperand(0).getValueType(); 6865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6866 DAG.getUNDEF(VVT), Mask); 6867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6868 DAG.getIntPtrConstant(0)); 6869 } else if (VT.getSizeInBits() == 64) { 6870 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6871 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6872 // to match extract_elt for f64. 6873 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6874 if (Idx == 0) 6875 return Op; 6876 6877 // UNPCKHPD the element to the lowest double word, then movsd. 6878 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6879 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6880 int Mask[2] = { 1, -1 }; 6881 EVT VVT = Op.getOperand(0).getValueType(); 6882 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6883 DAG.getUNDEF(VVT), Mask); 6884 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6885 DAG.getIntPtrConstant(0)); 6886 } 6887 6888 return SDValue(); 6889} 6890 6891SDValue 6892X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6893 SelectionDAG &DAG) const { 6894 EVT VT = Op.getValueType(); 6895 EVT EltVT = VT.getVectorElementType(); 6896 DebugLoc dl = Op.getDebugLoc(); 6897 6898 SDValue N0 = Op.getOperand(0); 6899 SDValue N1 = Op.getOperand(1); 6900 SDValue N2 = Op.getOperand(2); 6901 6902 if (VT.getSizeInBits() == 256) 6903 return SDValue(); 6904 6905 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6906 isa<ConstantSDNode>(N2)) { 6907 unsigned Opc; 6908 if (VT == MVT::v8i16) 6909 Opc = X86ISD::PINSRW; 6910 else if (VT == MVT::v16i8) 6911 Opc = X86ISD::PINSRB; 6912 else 6913 Opc = X86ISD::PINSRB; 6914 6915 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6916 // argument. 6917 if (N1.getValueType() != MVT::i32) 6918 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6919 if (N2.getValueType() != MVT::i32) 6920 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6921 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6922 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6923 // Bits [7:6] of the constant are the source select. This will always be 6924 // zero here. The DAG Combiner may combine an extract_elt index into these 6925 // bits. For example (insert (extract, 3), 2) could be matched by putting 6926 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6927 // Bits [5:4] of the constant are the destination select. This is the 6928 // value of the incoming immediate. 6929 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6930 // combine either bitwise AND or insert of float 0.0 to set these bits. 6931 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6932 // Create this as a scalar to vector.. 6933 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6934 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6935 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6936 isa<ConstantSDNode>(N2)) { 6937 // PINSR* works with constant index. 6938 return Op; 6939 } 6940 return SDValue(); 6941} 6942 6943SDValue 6944X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6945 EVT VT = Op.getValueType(); 6946 EVT EltVT = VT.getVectorElementType(); 6947 6948 DebugLoc dl = Op.getDebugLoc(); 6949 SDValue N0 = Op.getOperand(0); 6950 SDValue N1 = Op.getOperand(1); 6951 SDValue N2 = Op.getOperand(2); 6952 6953 // If this is a 256-bit vector result, first extract the 128-bit vector, 6954 // insert the element into the extracted half and then place it back. 6955 if (VT.getSizeInBits() == 256) { 6956 if (!isa<ConstantSDNode>(N2)) 6957 return SDValue(); 6958 6959 // Get the desired 128-bit vector half. 6960 unsigned NumElems = VT.getVectorNumElements(); 6961 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6962 bool Upper = IdxVal >= NumElems/2; 6963 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6964 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6965 6966 // Insert the element into the desired half. 6967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6968 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6969 6970 // Insert the changed part back to the 256-bit vector 6971 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6972 } 6973 6974 if (Subtarget->hasSSE41()) 6975 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6976 6977 if (EltVT == MVT::i8) 6978 return SDValue(); 6979 6980 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6981 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6982 // as its second argument. 6983 if (N1.getValueType() != MVT::i32) 6984 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6985 if (N2.getValueType() != MVT::i32) 6986 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6987 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6988 } 6989 return SDValue(); 6990} 6991 6992SDValue 6993X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6994 LLVMContext *Context = DAG.getContext(); 6995 DebugLoc dl = Op.getDebugLoc(); 6996 EVT OpVT = Op.getValueType(); 6997 6998 // If this is a 256-bit vector result, first insert into a 128-bit 6999 // vector and then insert into the 256-bit vector. 7000 if (OpVT.getSizeInBits() > 128) { 7001 // Insert into a 128-bit vector. 7002 EVT VT128 = EVT::getVectorVT(*Context, 7003 OpVT.getVectorElementType(), 7004 OpVT.getVectorNumElements() / 2); 7005 7006 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7007 7008 // Insert the 128-bit vector. 7009 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7010 DAG.getConstant(0, MVT::i32), 7011 DAG, dl); 7012 } 7013 7014 if (Op.getValueType() == MVT::v1i64 && 7015 Op.getOperand(0).getValueType() == MVT::i64) 7016 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7017 7018 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7019 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7020 "Expected an SSE type!"); 7021 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7022 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7023} 7024 7025// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7026// a simple subregister reference or explicit instructions to grab 7027// upper bits of a vector. 7028SDValue 7029X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7030 if (Subtarget->hasAVX()) { 7031 DebugLoc dl = Op.getNode()->getDebugLoc(); 7032 SDValue Vec = Op.getNode()->getOperand(0); 7033 SDValue Idx = Op.getNode()->getOperand(1); 7034 7035 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7036 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7037 return Extract128BitVector(Vec, Idx, DAG, dl); 7038 } 7039 } 7040 return SDValue(); 7041} 7042 7043// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7044// simple superregister reference or explicit instructions to insert 7045// the upper bits of a vector. 7046SDValue 7047X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7048 if (Subtarget->hasAVX()) { 7049 DebugLoc dl = Op.getNode()->getDebugLoc(); 7050 SDValue Vec = Op.getNode()->getOperand(0); 7051 SDValue SubVec = Op.getNode()->getOperand(1); 7052 SDValue Idx = Op.getNode()->getOperand(2); 7053 7054 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7055 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7056 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7057 } 7058 } 7059 return SDValue(); 7060} 7061 7062// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7063// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7064// one of the above mentioned nodes. It has to be wrapped because otherwise 7065// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7066// be used to form addressing mode. These wrapped nodes will be selected 7067// into MOV32ri. 7068SDValue 7069X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7070 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7071 7072 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7073 // global base reg. 7074 unsigned char OpFlag = 0; 7075 unsigned WrapperKind = X86ISD::Wrapper; 7076 CodeModel::Model M = getTargetMachine().getCodeModel(); 7077 7078 if (Subtarget->isPICStyleRIPRel() && 7079 (M == CodeModel::Small || M == CodeModel::Kernel)) 7080 WrapperKind = X86ISD::WrapperRIP; 7081 else if (Subtarget->isPICStyleGOT()) 7082 OpFlag = X86II::MO_GOTOFF; 7083 else if (Subtarget->isPICStyleStubPIC()) 7084 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7085 7086 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7087 CP->getAlignment(), 7088 CP->getOffset(), OpFlag); 7089 DebugLoc DL = CP->getDebugLoc(); 7090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7091 // With PIC, the address is actually $g + Offset. 7092 if (OpFlag) { 7093 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7094 DAG.getNode(X86ISD::GlobalBaseReg, 7095 DebugLoc(), getPointerTy()), 7096 Result); 7097 } 7098 7099 return Result; 7100} 7101 7102SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7103 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7104 7105 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7106 // global base reg. 7107 unsigned char OpFlag = 0; 7108 unsigned WrapperKind = X86ISD::Wrapper; 7109 CodeModel::Model M = getTargetMachine().getCodeModel(); 7110 7111 if (Subtarget->isPICStyleRIPRel() && 7112 (M == CodeModel::Small || M == CodeModel::Kernel)) 7113 WrapperKind = X86ISD::WrapperRIP; 7114 else if (Subtarget->isPICStyleGOT()) 7115 OpFlag = X86II::MO_GOTOFF; 7116 else if (Subtarget->isPICStyleStubPIC()) 7117 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7118 7119 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7120 OpFlag); 7121 DebugLoc DL = JT->getDebugLoc(); 7122 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7123 7124 // With PIC, the address is actually $g + Offset. 7125 if (OpFlag) 7126 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7127 DAG.getNode(X86ISD::GlobalBaseReg, 7128 DebugLoc(), getPointerTy()), 7129 Result); 7130 7131 return Result; 7132} 7133 7134SDValue 7135X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7136 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7137 7138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7139 // global base reg. 7140 unsigned char OpFlag = 0; 7141 unsigned WrapperKind = X86ISD::Wrapper; 7142 CodeModel::Model M = getTargetMachine().getCodeModel(); 7143 7144 if (Subtarget->isPICStyleRIPRel() && 7145 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7146 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7147 OpFlag = X86II::MO_GOTPCREL; 7148 WrapperKind = X86ISD::WrapperRIP; 7149 } else if (Subtarget->isPICStyleGOT()) { 7150 OpFlag = X86II::MO_GOT; 7151 } else if (Subtarget->isPICStyleStubPIC()) { 7152 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7153 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7154 OpFlag = X86II::MO_DARWIN_NONLAZY; 7155 } 7156 7157 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7158 7159 DebugLoc DL = Op.getDebugLoc(); 7160 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7161 7162 7163 // With PIC, the address is actually $g + Offset. 7164 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7165 !Subtarget->is64Bit()) { 7166 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7167 DAG.getNode(X86ISD::GlobalBaseReg, 7168 DebugLoc(), getPointerTy()), 7169 Result); 7170 } 7171 7172 // For symbols that require a load from a stub to get the address, emit the 7173 // load. 7174 if (isGlobalStubReference(OpFlag)) 7175 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7176 MachinePointerInfo::getGOT(), false, false, false, 0); 7177 7178 return Result; 7179} 7180 7181SDValue 7182X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7183 // Create the TargetBlockAddressAddress node. 7184 unsigned char OpFlags = 7185 Subtarget->ClassifyBlockAddressReference(); 7186 CodeModel::Model M = getTargetMachine().getCodeModel(); 7187 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7188 DebugLoc dl = Op.getDebugLoc(); 7189 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7190 /*isTarget=*/true, OpFlags); 7191 7192 if (Subtarget->isPICStyleRIPRel() && 7193 (M == CodeModel::Small || M == CodeModel::Kernel)) 7194 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7195 else 7196 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7197 7198 // With PIC, the address is actually $g + Offset. 7199 if (isGlobalRelativeToPICBase(OpFlags)) { 7200 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7201 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7202 Result); 7203 } 7204 7205 return Result; 7206} 7207 7208SDValue 7209X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7210 int64_t Offset, 7211 SelectionDAG &DAG) const { 7212 // Create the TargetGlobalAddress node, folding in the constant 7213 // offset if it is legal. 7214 unsigned char OpFlags = 7215 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7216 CodeModel::Model M = getTargetMachine().getCodeModel(); 7217 SDValue Result; 7218 if (OpFlags == X86II::MO_NO_FLAG && 7219 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7220 // A direct static reference to a global. 7221 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7222 Offset = 0; 7223 } else { 7224 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7225 } 7226 7227 if (Subtarget->isPICStyleRIPRel() && 7228 (M == CodeModel::Small || M == CodeModel::Kernel)) 7229 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7230 else 7231 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7232 7233 // With PIC, the address is actually $g + Offset. 7234 if (isGlobalRelativeToPICBase(OpFlags)) { 7235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7236 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7237 Result); 7238 } 7239 7240 // For globals that require a load from a stub to get the address, emit the 7241 // load. 7242 if (isGlobalStubReference(OpFlags)) 7243 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7244 MachinePointerInfo::getGOT(), false, false, false, 0); 7245 7246 // If there was a non-zero offset that we didn't fold, create an explicit 7247 // addition for it. 7248 if (Offset != 0) 7249 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7250 DAG.getConstant(Offset, getPointerTy())); 7251 7252 return Result; 7253} 7254 7255SDValue 7256X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7257 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7258 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7259 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7260} 7261 7262static SDValue 7263GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7264 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7265 unsigned char OperandFlags) { 7266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7267 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7268 DebugLoc dl = GA->getDebugLoc(); 7269 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7270 GA->getValueType(0), 7271 GA->getOffset(), 7272 OperandFlags); 7273 if (InFlag) { 7274 SDValue Ops[] = { Chain, TGA, *InFlag }; 7275 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7276 } else { 7277 SDValue Ops[] = { Chain, TGA }; 7278 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7279 } 7280 7281 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7282 MFI->setAdjustsStack(true); 7283 7284 SDValue Flag = Chain.getValue(1); 7285 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7286} 7287 7288// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7289static SDValue 7290LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7291 const EVT PtrVT) { 7292 SDValue InFlag; 7293 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7294 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7295 DAG.getNode(X86ISD::GlobalBaseReg, 7296 DebugLoc(), PtrVT), InFlag); 7297 InFlag = Chain.getValue(1); 7298 7299 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7300} 7301 7302// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7303static SDValue 7304LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7305 const EVT PtrVT) { 7306 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7307 X86::RAX, X86II::MO_TLSGD); 7308} 7309 7310// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7311// "local exec" model. 7312static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7313 const EVT PtrVT, TLSModel::Model model, 7314 bool is64Bit) { 7315 DebugLoc dl = GA->getDebugLoc(); 7316 7317 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7318 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7319 is64Bit ? 257 : 256)); 7320 7321 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7322 DAG.getIntPtrConstant(0), 7323 MachinePointerInfo(Ptr), 7324 false, false, false, 0); 7325 7326 unsigned char OperandFlags = 0; 7327 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7328 // initialexec. 7329 unsigned WrapperKind = X86ISD::Wrapper; 7330 if (model == TLSModel::LocalExec) { 7331 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7332 } else if (is64Bit) { 7333 assert(model == TLSModel::InitialExec); 7334 OperandFlags = X86II::MO_GOTTPOFF; 7335 WrapperKind = X86ISD::WrapperRIP; 7336 } else { 7337 assert(model == TLSModel::InitialExec); 7338 OperandFlags = X86II::MO_INDNTPOFF; 7339 } 7340 7341 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7342 // exec) 7343 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7344 GA->getValueType(0), 7345 GA->getOffset(), OperandFlags); 7346 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7347 7348 if (model == TLSModel::InitialExec) 7349 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7350 MachinePointerInfo::getGOT(), false, false, false, 0); 7351 7352 // The address of the thread local variable is the add of the thread 7353 // pointer with the offset of the variable. 7354 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7355} 7356 7357SDValue 7358X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7359 7360 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7361 const GlobalValue *GV = GA->getGlobal(); 7362 7363 if (Subtarget->isTargetELF()) { 7364 // TODO: implement the "local dynamic" model 7365 // TODO: implement the "initial exec"model for pic executables 7366 7367 // If GV is an alias then use the aliasee for determining 7368 // thread-localness. 7369 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7370 GV = GA->resolveAliasedGlobal(false); 7371 7372 TLSModel::Model model 7373 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7374 7375 switch (model) { 7376 case TLSModel::GeneralDynamic: 7377 case TLSModel::LocalDynamic: // not implemented 7378 if (Subtarget->is64Bit()) 7379 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7380 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7381 7382 case TLSModel::InitialExec: 7383 case TLSModel::LocalExec: 7384 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7385 Subtarget->is64Bit()); 7386 } 7387 } else if (Subtarget->isTargetDarwin()) { 7388 // Darwin only has one model of TLS. Lower to that. 7389 unsigned char OpFlag = 0; 7390 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7391 X86ISD::WrapperRIP : X86ISD::Wrapper; 7392 7393 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7394 // global base reg. 7395 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7396 !Subtarget->is64Bit(); 7397 if (PIC32) 7398 OpFlag = X86II::MO_TLVP_PIC_BASE; 7399 else 7400 OpFlag = X86II::MO_TLVP; 7401 DebugLoc DL = Op.getDebugLoc(); 7402 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7403 GA->getValueType(0), 7404 GA->getOffset(), OpFlag); 7405 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7406 7407 // With PIC32, the address is actually $g + Offset. 7408 if (PIC32) 7409 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7410 DAG.getNode(X86ISD::GlobalBaseReg, 7411 DebugLoc(), getPointerTy()), 7412 Offset); 7413 7414 // Lowering the machine isd will make sure everything is in the right 7415 // location. 7416 SDValue Chain = DAG.getEntryNode(); 7417 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7418 SDValue Args[] = { Chain, Offset }; 7419 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7420 7421 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7423 MFI->setAdjustsStack(true); 7424 7425 // And our return value (tls address) is in the standard call return value 7426 // location. 7427 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7428 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7429 Chain.getValue(1)); 7430 } 7431 7432 assert(false && 7433 "TLS not implemented for this target."); 7434 7435 llvm_unreachable("Unreachable"); 7436 return SDValue(); 7437} 7438 7439 7440/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7441/// and take a 2 x i32 value to shift plus a shift amount. 7442SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7443 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7444 EVT VT = Op.getValueType(); 7445 unsigned VTBits = VT.getSizeInBits(); 7446 DebugLoc dl = Op.getDebugLoc(); 7447 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7448 SDValue ShOpLo = Op.getOperand(0); 7449 SDValue ShOpHi = Op.getOperand(1); 7450 SDValue ShAmt = Op.getOperand(2); 7451 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7452 DAG.getConstant(VTBits - 1, MVT::i8)) 7453 : DAG.getConstant(0, VT); 7454 7455 SDValue Tmp2, Tmp3; 7456 if (Op.getOpcode() == ISD::SHL_PARTS) { 7457 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7458 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7459 } else { 7460 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7461 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7462 } 7463 7464 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7465 DAG.getConstant(VTBits, MVT::i8)); 7466 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7467 AndNode, DAG.getConstant(0, MVT::i8)); 7468 7469 SDValue Hi, Lo; 7470 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7471 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7472 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7473 7474 if (Op.getOpcode() == ISD::SHL_PARTS) { 7475 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7476 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7477 } else { 7478 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7479 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7480 } 7481 7482 SDValue Ops[2] = { Lo, Hi }; 7483 return DAG.getMergeValues(Ops, 2, dl); 7484} 7485 7486SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7487 SelectionDAG &DAG) const { 7488 EVT SrcVT = Op.getOperand(0).getValueType(); 7489 7490 if (SrcVT.isVector()) 7491 return SDValue(); 7492 7493 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7494 "Unknown SINT_TO_FP to lower!"); 7495 7496 // These are really Legal; return the operand so the caller accepts it as 7497 // Legal. 7498 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7499 return Op; 7500 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7501 Subtarget->is64Bit()) { 7502 return Op; 7503 } 7504 7505 DebugLoc dl = Op.getDebugLoc(); 7506 unsigned Size = SrcVT.getSizeInBits()/8; 7507 MachineFunction &MF = DAG.getMachineFunction(); 7508 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7509 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7510 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7511 StackSlot, 7512 MachinePointerInfo::getFixedStack(SSFI), 7513 false, false, 0); 7514 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7515} 7516 7517SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7518 SDValue StackSlot, 7519 SelectionDAG &DAG) const { 7520 // Build the FILD 7521 DebugLoc DL = Op.getDebugLoc(); 7522 SDVTList Tys; 7523 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7524 if (useSSE) 7525 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7526 else 7527 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7528 7529 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7530 7531 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7532 MachineMemOperand *MMO; 7533 if (FI) { 7534 int SSFI = FI->getIndex(); 7535 MMO = 7536 DAG.getMachineFunction() 7537 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7538 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7539 } else { 7540 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7541 StackSlot = StackSlot.getOperand(1); 7542 } 7543 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7544 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7545 X86ISD::FILD, DL, 7546 Tys, Ops, array_lengthof(Ops), 7547 SrcVT, MMO); 7548 7549 if (useSSE) { 7550 Chain = Result.getValue(1); 7551 SDValue InFlag = Result.getValue(2); 7552 7553 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7554 // shouldn't be necessary except that RFP cannot be live across 7555 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7556 MachineFunction &MF = DAG.getMachineFunction(); 7557 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7558 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7559 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7560 Tys = DAG.getVTList(MVT::Other); 7561 SDValue Ops[] = { 7562 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7563 }; 7564 MachineMemOperand *MMO = 7565 DAG.getMachineFunction() 7566 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7567 MachineMemOperand::MOStore, SSFISize, SSFISize); 7568 7569 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7570 Ops, array_lengthof(Ops), 7571 Op.getValueType(), MMO); 7572 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7573 MachinePointerInfo::getFixedStack(SSFI), 7574 false, false, false, 0); 7575 } 7576 7577 return Result; 7578} 7579 7580// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7581SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7582 SelectionDAG &DAG) const { 7583 // This algorithm is not obvious. Here it is what we're trying to output: 7584 /* 7585 movq %rax, %xmm0 7586 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7587 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7588 #ifdef __SSE3__ 7589 haddpd %xmm0, %xmm0 7590 #else 7591 pshufd $0x4e, %xmm0, %xmm1 7592 addpd %xmm1, %xmm0 7593 #endif 7594 */ 7595 7596 DebugLoc dl = Op.getDebugLoc(); 7597 LLVMContext *Context = DAG.getContext(); 7598 7599 // Build some magic constants. 7600 SmallVector<Constant*,4> CV0; 7601 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7602 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7603 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7604 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7605 Constant *C0 = ConstantVector::get(CV0); 7606 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7607 7608 SmallVector<Constant*,2> CV1; 7609 CV1.push_back( 7610 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7611 CV1.push_back( 7612 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7613 Constant *C1 = ConstantVector::get(CV1); 7614 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7615 7616 // Load the 64-bit value into an XMM register. 7617 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7618 Op.getOperand(0)); 7619 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7620 MachinePointerInfo::getConstantPool(), 7621 false, false, false, 16); 7622 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7623 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7624 CLod0); 7625 7626 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7627 MachinePointerInfo::getConstantPool(), 7628 false, false, false, 16); 7629 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7630 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7631 SDValue Result; 7632 7633 if (Subtarget->hasSSE3()) { 7634 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7635 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7636 } else { 7637 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7638 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7639 S2F, 0x4E, DAG); 7640 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7641 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7642 Sub); 7643 } 7644 7645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7646 DAG.getIntPtrConstant(0)); 7647} 7648 7649// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7650SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7651 SelectionDAG &DAG) const { 7652 DebugLoc dl = Op.getDebugLoc(); 7653 // FP constant to bias correct the final result. 7654 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7655 MVT::f64); 7656 7657 // Load the 32-bit value into an XMM register. 7658 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7659 Op.getOperand(0)); 7660 7661 // Zero out the upper parts of the register. 7662 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), 7663 DAG); 7664 7665 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7666 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7667 DAG.getIntPtrConstant(0)); 7668 7669 // Or the load with the bias. 7670 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7671 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7672 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7673 MVT::v2f64, Load)), 7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7675 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7676 MVT::v2f64, Bias))); 7677 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7678 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7679 DAG.getIntPtrConstant(0)); 7680 7681 // Subtract the bias. 7682 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7683 7684 // Handle final rounding. 7685 EVT DestVT = Op.getValueType(); 7686 7687 if (DestVT.bitsLT(MVT::f64)) { 7688 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7689 DAG.getIntPtrConstant(0)); 7690 } else if (DestVT.bitsGT(MVT::f64)) { 7691 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7692 } 7693 7694 // Handle final rounding. 7695 return Sub; 7696} 7697 7698SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7699 SelectionDAG &DAG) const { 7700 SDValue N0 = Op.getOperand(0); 7701 DebugLoc dl = Op.getDebugLoc(); 7702 7703 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7704 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7705 // the optimization here. 7706 if (DAG.SignBitIsZero(N0)) 7707 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7708 7709 EVT SrcVT = N0.getValueType(); 7710 EVT DstVT = Op.getValueType(); 7711 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7712 return LowerUINT_TO_FP_i64(Op, DAG); 7713 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7714 return LowerUINT_TO_FP_i32(Op, DAG); 7715 else if (Subtarget->is64Bit() && 7716 SrcVT == MVT::i64 && DstVT == MVT::f32) 7717 return SDValue(); 7718 7719 // Make a 64-bit buffer, and use it to build an FILD. 7720 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7721 if (SrcVT == MVT::i32) { 7722 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7723 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7724 getPointerTy(), StackSlot, WordOff); 7725 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7726 StackSlot, MachinePointerInfo(), 7727 false, false, 0); 7728 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7729 OffsetSlot, MachinePointerInfo(), 7730 false, false, 0); 7731 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7732 return Fild; 7733 } 7734 7735 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7736 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7737 StackSlot, MachinePointerInfo(), 7738 false, false, 0); 7739 // For i64 source, we need to add the appropriate power of 2 if the input 7740 // was negative. This is the same as the optimization in 7741 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7742 // we must be careful to do the computation in x87 extended precision, not 7743 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7744 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7745 MachineMemOperand *MMO = 7746 DAG.getMachineFunction() 7747 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7748 MachineMemOperand::MOLoad, 8, 8); 7749 7750 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7751 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7752 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7753 MVT::i64, MMO); 7754 7755 APInt FF(32, 0x5F800000ULL); 7756 7757 // Check whether the sign bit is set. 7758 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7759 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7760 ISD::SETLT); 7761 7762 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7763 SDValue FudgePtr = DAG.getConstantPool( 7764 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7765 getPointerTy()); 7766 7767 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7768 SDValue Zero = DAG.getIntPtrConstant(0); 7769 SDValue Four = DAG.getIntPtrConstant(4); 7770 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7771 Zero, Four); 7772 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7773 7774 // Load the value out, extending it from f32 to f80. 7775 // FIXME: Avoid the extend by constructing the right constant pool? 7776 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7777 FudgePtr, MachinePointerInfo::getConstantPool(), 7778 MVT::f32, false, false, 4); 7779 // Extend everything to 80 bits to force it to be done on x87. 7780 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7781 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7782} 7783 7784std::pair<SDValue,SDValue> X86TargetLowering:: 7785FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7786 DebugLoc DL = Op.getDebugLoc(); 7787 7788 EVT DstTy = Op.getValueType(); 7789 7790 if (!IsSigned) { 7791 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7792 DstTy = MVT::i64; 7793 } 7794 7795 assert(DstTy.getSimpleVT() <= MVT::i64 && 7796 DstTy.getSimpleVT() >= MVT::i16 && 7797 "Unknown FP_TO_SINT to lower!"); 7798 7799 // These are really Legal. 7800 if (DstTy == MVT::i32 && 7801 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7802 return std::make_pair(SDValue(), SDValue()); 7803 if (Subtarget->is64Bit() && 7804 DstTy == MVT::i64 && 7805 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7806 return std::make_pair(SDValue(), SDValue()); 7807 7808 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7809 // stack slot. 7810 MachineFunction &MF = DAG.getMachineFunction(); 7811 unsigned MemSize = DstTy.getSizeInBits()/8; 7812 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7813 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7814 7815 7816 7817 unsigned Opc; 7818 switch (DstTy.getSimpleVT().SimpleTy) { 7819 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7820 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7821 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7822 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7823 } 7824 7825 SDValue Chain = DAG.getEntryNode(); 7826 SDValue Value = Op.getOperand(0); 7827 EVT TheVT = Op.getOperand(0).getValueType(); 7828 if (isScalarFPTypeInSSEReg(TheVT)) { 7829 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7830 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7831 MachinePointerInfo::getFixedStack(SSFI), 7832 false, false, 0); 7833 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7834 SDValue Ops[] = { 7835 Chain, StackSlot, DAG.getValueType(TheVT) 7836 }; 7837 7838 MachineMemOperand *MMO = 7839 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7840 MachineMemOperand::MOLoad, MemSize, MemSize); 7841 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7842 DstTy, MMO); 7843 Chain = Value.getValue(1); 7844 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7845 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7846 } 7847 7848 MachineMemOperand *MMO = 7849 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7850 MachineMemOperand::MOStore, MemSize, MemSize); 7851 7852 // Build the FP_TO_INT*_IN_MEM 7853 SDValue Ops[] = { Chain, Value, StackSlot }; 7854 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7855 Ops, 3, DstTy, MMO); 7856 7857 return std::make_pair(FIST, StackSlot); 7858} 7859 7860SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7861 SelectionDAG &DAG) const { 7862 if (Op.getValueType().isVector()) 7863 return SDValue(); 7864 7865 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7866 SDValue FIST = Vals.first, StackSlot = Vals.second; 7867 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7868 if (FIST.getNode() == 0) return Op; 7869 7870 // Load the result. 7871 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7872 FIST, StackSlot, MachinePointerInfo(), 7873 false, false, false, 0); 7874} 7875 7876SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7877 SelectionDAG &DAG) const { 7878 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7879 SDValue FIST = Vals.first, StackSlot = Vals.second; 7880 assert(FIST.getNode() && "Unexpected failure"); 7881 7882 // Load the result. 7883 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7884 FIST, StackSlot, MachinePointerInfo(), 7885 false, false, false, 0); 7886} 7887 7888SDValue X86TargetLowering::LowerFABS(SDValue Op, 7889 SelectionDAG &DAG) const { 7890 LLVMContext *Context = DAG.getContext(); 7891 DebugLoc dl = Op.getDebugLoc(); 7892 EVT VT = Op.getValueType(); 7893 EVT EltVT = VT; 7894 if (VT.isVector()) 7895 EltVT = VT.getVectorElementType(); 7896 SmallVector<Constant*,4> CV; 7897 if (EltVT == MVT::f64) { 7898 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7899 CV.assign(2, C); 7900 } else { 7901 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7902 CV.assign(4, C); 7903 } 7904 Constant *C = ConstantVector::get(CV); 7905 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7906 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7907 MachinePointerInfo::getConstantPool(), 7908 false, false, false, 16); 7909 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7910} 7911 7912SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7913 LLVMContext *Context = DAG.getContext(); 7914 DebugLoc dl = Op.getDebugLoc(); 7915 EVT VT = Op.getValueType(); 7916 EVT EltVT = VT; 7917 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7918 if (VT.isVector()) { 7919 EltVT = VT.getVectorElementType(); 7920 NumElts = VT.getVectorNumElements(); 7921 } 7922 SmallVector<Constant*,8> CV; 7923 if (EltVT == MVT::f64) { 7924 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7925 CV.assign(NumElts, C); 7926 } else { 7927 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7928 CV.assign(NumElts, C); 7929 } 7930 Constant *C = ConstantVector::get(CV); 7931 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7932 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7933 MachinePointerInfo::getConstantPool(), 7934 false, false, false, 16); 7935 if (VT.isVector()) { 7936 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7937 return DAG.getNode(ISD::BITCAST, dl, VT, 7938 DAG.getNode(ISD::XOR, dl, XORVT, 7939 DAG.getNode(ISD::BITCAST, dl, XORVT, 7940 Op.getOperand(0)), 7941 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7942 } else { 7943 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7944 } 7945} 7946 7947SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7948 LLVMContext *Context = DAG.getContext(); 7949 SDValue Op0 = Op.getOperand(0); 7950 SDValue Op1 = Op.getOperand(1); 7951 DebugLoc dl = Op.getDebugLoc(); 7952 EVT VT = Op.getValueType(); 7953 EVT SrcVT = Op1.getValueType(); 7954 7955 // If second operand is smaller, extend it first. 7956 if (SrcVT.bitsLT(VT)) { 7957 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7958 SrcVT = VT; 7959 } 7960 // And if it is bigger, shrink it first. 7961 if (SrcVT.bitsGT(VT)) { 7962 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7963 SrcVT = VT; 7964 } 7965 7966 // At this point the operands and the result should have the same 7967 // type, and that won't be f80 since that is not custom lowered. 7968 7969 // First get the sign bit of second operand. 7970 SmallVector<Constant*,4> CV; 7971 if (SrcVT == MVT::f64) { 7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7973 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7974 } else { 7975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7978 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7979 } 7980 Constant *C = ConstantVector::get(CV); 7981 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7982 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7983 MachinePointerInfo::getConstantPool(), 7984 false, false, false, 16); 7985 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7986 7987 // Shift sign bit right or left if the two operands have different types. 7988 if (SrcVT.bitsGT(VT)) { 7989 // Op0 is MVT::f32, Op1 is MVT::f64. 7990 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7991 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7992 DAG.getConstant(32, MVT::i32)); 7993 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7994 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7995 DAG.getIntPtrConstant(0)); 7996 } 7997 7998 // Clear first operand sign bit. 7999 CV.clear(); 8000 if (VT == MVT::f64) { 8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8003 } else { 8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8008 } 8009 C = ConstantVector::get(CV); 8010 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8011 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8012 MachinePointerInfo::getConstantPool(), 8013 false, false, false, 16); 8014 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8015 8016 // Or the value with the sign bit. 8017 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8018} 8019 8020SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8021 SDValue N0 = Op.getOperand(0); 8022 DebugLoc dl = Op.getDebugLoc(); 8023 EVT VT = Op.getValueType(); 8024 8025 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8026 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8027 DAG.getConstant(1, VT)); 8028 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8029} 8030 8031/// Emit nodes that will be selected as "test Op0,Op0", or something 8032/// equivalent. 8033SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8034 SelectionDAG &DAG) const { 8035 DebugLoc dl = Op.getDebugLoc(); 8036 8037 // CF and OF aren't always set the way we want. Determine which 8038 // of these we need. 8039 bool NeedCF = false; 8040 bool NeedOF = false; 8041 switch (X86CC) { 8042 default: break; 8043 case X86::COND_A: case X86::COND_AE: 8044 case X86::COND_B: case X86::COND_BE: 8045 NeedCF = true; 8046 break; 8047 case X86::COND_G: case X86::COND_GE: 8048 case X86::COND_L: case X86::COND_LE: 8049 case X86::COND_O: case X86::COND_NO: 8050 NeedOF = true; 8051 break; 8052 } 8053 8054 // See if we can use the EFLAGS value from the operand instead of 8055 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8056 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8057 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8058 // Emit a CMP with 0, which is the TEST pattern. 8059 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8060 DAG.getConstant(0, Op.getValueType())); 8061 8062 unsigned Opcode = 0; 8063 unsigned NumOperands = 0; 8064 switch (Op.getNode()->getOpcode()) { 8065 case ISD::ADD: 8066 // Due to an isel shortcoming, be conservative if this add is likely to be 8067 // selected as part of a load-modify-store instruction. When the root node 8068 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8069 // uses of other nodes in the match, such as the ADD in this case. This 8070 // leads to the ADD being left around and reselected, with the result being 8071 // two adds in the output. Alas, even if none our users are stores, that 8072 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8073 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8074 // climbing the DAG back to the root, and it doesn't seem to be worth the 8075 // effort. 8076 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8077 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8078 if (UI->getOpcode() != ISD::CopyToReg && 8079 UI->getOpcode() != ISD::SETCC && 8080 UI->getOpcode() != ISD::STORE) 8081 goto default_case; 8082 8083 if (ConstantSDNode *C = 8084 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8085 // An add of one will be selected as an INC. 8086 if (C->getAPIntValue() == 1) { 8087 Opcode = X86ISD::INC; 8088 NumOperands = 1; 8089 break; 8090 } 8091 8092 // An add of negative one (subtract of one) will be selected as a DEC. 8093 if (C->getAPIntValue().isAllOnesValue()) { 8094 Opcode = X86ISD::DEC; 8095 NumOperands = 1; 8096 break; 8097 } 8098 } 8099 8100 // Otherwise use a regular EFLAGS-setting add. 8101 Opcode = X86ISD::ADD; 8102 NumOperands = 2; 8103 break; 8104 case ISD::AND: { 8105 // If the primary and result isn't used, don't bother using X86ISD::AND, 8106 // because a TEST instruction will be better. 8107 bool NonFlagUse = false; 8108 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8109 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8110 SDNode *User = *UI; 8111 unsigned UOpNo = UI.getOperandNo(); 8112 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8113 // Look pass truncate. 8114 UOpNo = User->use_begin().getOperandNo(); 8115 User = *User->use_begin(); 8116 } 8117 8118 if (User->getOpcode() != ISD::BRCOND && 8119 User->getOpcode() != ISD::SETCC && 8120 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8121 NonFlagUse = true; 8122 break; 8123 } 8124 } 8125 8126 if (!NonFlagUse) 8127 break; 8128 } 8129 // FALL THROUGH 8130 case ISD::SUB: 8131 case ISD::OR: 8132 case ISD::XOR: 8133 // Due to the ISEL shortcoming noted above, be conservative if this op is 8134 // likely to be selected as part of a load-modify-store instruction. 8135 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8136 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8137 if (UI->getOpcode() == ISD::STORE) 8138 goto default_case; 8139 8140 // Otherwise use a regular EFLAGS-setting instruction. 8141 switch (Op.getNode()->getOpcode()) { 8142 default: llvm_unreachable("unexpected operator!"); 8143 case ISD::SUB: Opcode = X86ISD::SUB; break; 8144 case ISD::OR: Opcode = X86ISD::OR; break; 8145 case ISD::XOR: Opcode = X86ISD::XOR; break; 8146 case ISD::AND: Opcode = X86ISD::AND; break; 8147 } 8148 8149 NumOperands = 2; 8150 break; 8151 case X86ISD::ADD: 8152 case X86ISD::SUB: 8153 case X86ISD::INC: 8154 case X86ISD::DEC: 8155 case X86ISD::OR: 8156 case X86ISD::XOR: 8157 case X86ISD::AND: 8158 return SDValue(Op.getNode(), 1); 8159 default: 8160 default_case: 8161 break; 8162 } 8163 8164 if (Opcode == 0) 8165 // Emit a CMP with 0, which is the TEST pattern. 8166 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8167 DAG.getConstant(0, Op.getValueType())); 8168 8169 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8170 SmallVector<SDValue, 4> Ops; 8171 for (unsigned i = 0; i != NumOperands; ++i) 8172 Ops.push_back(Op.getOperand(i)); 8173 8174 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8175 DAG.ReplaceAllUsesWith(Op, New); 8176 return SDValue(New.getNode(), 1); 8177} 8178 8179/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8180/// equivalent. 8181SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8182 SelectionDAG &DAG) const { 8183 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8184 if (C->getAPIntValue() == 0) 8185 return EmitTest(Op0, X86CC, DAG); 8186 8187 DebugLoc dl = Op0.getDebugLoc(); 8188 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8189} 8190 8191/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8192/// if it's possible. 8193SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8194 DebugLoc dl, SelectionDAG &DAG) const { 8195 SDValue Op0 = And.getOperand(0); 8196 SDValue Op1 = And.getOperand(1); 8197 if (Op0.getOpcode() == ISD::TRUNCATE) 8198 Op0 = Op0.getOperand(0); 8199 if (Op1.getOpcode() == ISD::TRUNCATE) 8200 Op1 = Op1.getOperand(0); 8201 8202 SDValue LHS, RHS; 8203 if (Op1.getOpcode() == ISD::SHL) 8204 std::swap(Op0, Op1); 8205 if (Op0.getOpcode() == ISD::SHL) { 8206 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8207 if (And00C->getZExtValue() == 1) { 8208 // If we looked past a truncate, check that it's only truncating away 8209 // known zeros. 8210 unsigned BitWidth = Op0.getValueSizeInBits(); 8211 unsigned AndBitWidth = And.getValueSizeInBits(); 8212 if (BitWidth > AndBitWidth) { 8213 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8214 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8215 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8216 return SDValue(); 8217 } 8218 LHS = Op1; 8219 RHS = Op0.getOperand(1); 8220 } 8221 } else if (Op1.getOpcode() == ISD::Constant) { 8222 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8223 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8224 SDValue AndLHS = Op0; 8225 8226 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8227 LHS = AndLHS.getOperand(0); 8228 RHS = AndLHS.getOperand(1); 8229 } 8230 8231 // Use BT if the immediate can't be encoded in a TEST instruction. 8232 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8233 LHS = AndLHS; 8234 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8235 } 8236 } 8237 8238 if (LHS.getNode()) { 8239 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8240 // instruction. Since the shift amount is in-range-or-undefined, we know 8241 // that doing a bittest on the i32 value is ok. We extend to i32 because 8242 // the encoding for the i16 version is larger than the i32 version. 8243 // Also promote i16 to i32 for performance / code size reason. 8244 if (LHS.getValueType() == MVT::i8 || 8245 LHS.getValueType() == MVT::i16) 8246 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8247 8248 // If the operand types disagree, extend the shift amount to match. Since 8249 // BT ignores high bits (like shifts) we can use anyextend. 8250 if (LHS.getValueType() != RHS.getValueType()) 8251 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8252 8253 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8254 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8255 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8256 DAG.getConstant(Cond, MVT::i8), BT); 8257 } 8258 8259 return SDValue(); 8260} 8261 8262SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8263 8264 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8265 8266 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8267 SDValue Op0 = Op.getOperand(0); 8268 SDValue Op1 = Op.getOperand(1); 8269 DebugLoc dl = Op.getDebugLoc(); 8270 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8271 8272 // Optimize to BT if possible. 8273 // Lower (X & (1 << N)) == 0 to BT(X, N). 8274 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8275 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8276 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8277 Op1.getOpcode() == ISD::Constant && 8278 cast<ConstantSDNode>(Op1)->isNullValue() && 8279 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8280 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8281 if (NewSetCC.getNode()) 8282 return NewSetCC; 8283 } 8284 8285 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8286 // these. 8287 if (Op1.getOpcode() == ISD::Constant && 8288 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8289 cast<ConstantSDNode>(Op1)->isNullValue()) && 8290 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8291 8292 // If the input is a setcc, then reuse the input setcc or use a new one with 8293 // the inverted condition. 8294 if (Op0.getOpcode() == X86ISD::SETCC) { 8295 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8296 bool Invert = (CC == ISD::SETNE) ^ 8297 cast<ConstantSDNode>(Op1)->isNullValue(); 8298 if (!Invert) return Op0; 8299 8300 CCode = X86::GetOppositeBranchCondition(CCode); 8301 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8302 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8303 } 8304 } 8305 8306 bool isFP = Op1.getValueType().isFloatingPoint(); 8307 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8308 if (X86CC == X86::COND_INVALID) 8309 return SDValue(); 8310 8311 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8312 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8313 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8314} 8315 8316// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8317// ones, and then concatenate the result back. 8318static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8319 EVT VT = Op.getValueType(); 8320 8321 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8322 "Unsupported value type for operation"); 8323 8324 int NumElems = VT.getVectorNumElements(); 8325 DebugLoc dl = Op.getDebugLoc(); 8326 SDValue CC = Op.getOperand(2); 8327 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8328 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8329 8330 // Extract the LHS vectors 8331 SDValue LHS = Op.getOperand(0); 8332 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8333 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8334 8335 // Extract the RHS vectors 8336 SDValue RHS = Op.getOperand(1); 8337 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8338 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8339 8340 // Issue the operation on the smaller types and concatenate the result back 8341 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8342 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8343 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8344 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8345 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8346} 8347 8348 8349SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8350 SDValue Cond; 8351 SDValue Op0 = Op.getOperand(0); 8352 SDValue Op1 = Op.getOperand(1); 8353 SDValue CC = Op.getOperand(2); 8354 EVT VT = Op.getValueType(); 8355 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8356 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8357 DebugLoc dl = Op.getDebugLoc(); 8358 8359 if (isFP) { 8360 unsigned SSECC = 8; 8361 EVT EltVT = Op0.getValueType().getVectorElementType(); 8362 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8363 8364 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8365 bool Swap = false; 8366 8367 // SSE Condition code mapping: 8368 // 0 - EQ 8369 // 1 - LT 8370 // 2 - LE 8371 // 3 - UNORD 8372 // 4 - NEQ 8373 // 5 - NLT 8374 // 6 - NLE 8375 // 7 - ORD 8376 switch (SetCCOpcode) { 8377 default: break; 8378 case ISD::SETOEQ: 8379 case ISD::SETEQ: SSECC = 0; break; 8380 case ISD::SETOGT: 8381 case ISD::SETGT: Swap = true; // Fallthrough 8382 case ISD::SETLT: 8383 case ISD::SETOLT: SSECC = 1; break; 8384 case ISD::SETOGE: 8385 case ISD::SETGE: Swap = true; // Fallthrough 8386 case ISD::SETLE: 8387 case ISD::SETOLE: SSECC = 2; break; 8388 case ISD::SETUO: SSECC = 3; break; 8389 case ISD::SETUNE: 8390 case ISD::SETNE: SSECC = 4; break; 8391 case ISD::SETULE: Swap = true; 8392 case ISD::SETUGE: SSECC = 5; break; 8393 case ISD::SETULT: Swap = true; 8394 case ISD::SETUGT: SSECC = 6; break; 8395 case ISD::SETO: SSECC = 7; break; 8396 } 8397 if (Swap) 8398 std::swap(Op0, Op1); 8399 8400 // In the two special cases we can't handle, emit two comparisons. 8401 if (SSECC == 8) { 8402 if (SetCCOpcode == ISD::SETUEQ) { 8403 SDValue UNORD, EQ; 8404 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8405 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8406 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8407 } else if (SetCCOpcode == ISD::SETONE) { 8408 SDValue ORD, NEQ; 8409 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8410 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8411 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8412 } 8413 llvm_unreachable("Illegal FP comparison"); 8414 } 8415 // Handle all other FP comparisons here. 8416 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8417 } 8418 8419 // Break 256-bit integer vector compare into smaller ones. 8420 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8421 return Lower256IntVSETCC(Op, DAG); 8422 8423 // We are handling one of the integer comparisons here. Since SSE only has 8424 // GT and EQ comparisons for integer, swapping operands and multiple 8425 // operations may be required for some comparisons. 8426 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8427 bool Swap = false, Invert = false, FlipSigns = false; 8428 8429 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 8430 default: break; 8431 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8432 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8433 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8434 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8435 } 8436 8437 switch (SetCCOpcode) { 8438 default: break; 8439 case ISD::SETNE: Invert = true; 8440 case ISD::SETEQ: Opc = EQOpc; break; 8441 case ISD::SETLT: Swap = true; 8442 case ISD::SETGT: Opc = GTOpc; break; 8443 case ISD::SETGE: Swap = true; 8444 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8445 case ISD::SETULT: Swap = true; 8446 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8447 case ISD::SETUGE: Swap = true; 8448 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8449 } 8450 if (Swap) 8451 std::swap(Op0, Op1); 8452 8453 // Check that the operation in question is available (most are plain SSE2, 8454 // but PCMPGTQ and PCMPEQQ have different requirements). 8455 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42()) 8456 return SDValue(); 8457 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41()) 8458 return SDValue(); 8459 8460 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8461 // bits of the inputs before performing those operations. 8462 if (FlipSigns) { 8463 EVT EltVT = VT.getVectorElementType(); 8464 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8465 EltVT); 8466 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8467 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8468 SignBits.size()); 8469 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8470 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8471 } 8472 8473 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8474 8475 // If the logical-not of the result is required, perform that now. 8476 if (Invert) 8477 Result = DAG.getNOT(dl, Result, VT); 8478 8479 return Result; 8480} 8481 8482// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8483static bool isX86LogicalCmp(SDValue Op) { 8484 unsigned Opc = Op.getNode()->getOpcode(); 8485 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8486 return true; 8487 if (Op.getResNo() == 1 && 8488 (Opc == X86ISD::ADD || 8489 Opc == X86ISD::SUB || 8490 Opc == X86ISD::ADC || 8491 Opc == X86ISD::SBB || 8492 Opc == X86ISD::SMUL || 8493 Opc == X86ISD::UMUL || 8494 Opc == X86ISD::INC || 8495 Opc == X86ISD::DEC || 8496 Opc == X86ISD::OR || 8497 Opc == X86ISD::XOR || 8498 Opc == X86ISD::AND)) 8499 return true; 8500 8501 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8502 return true; 8503 8504 return false; 8505} 8506 8507static bool isZero(SDValue V) { 8508 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8509 return C && C->isNullValue(); 8510} 8511 8512static bool isAllOnes(SDValue V) { 8513 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8514 return C && C->isAllOnesValue(); 8515} 8516 8517SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8518 bool addTest = true; 8519 SDValue Cond = Op.getOperand(0); 8520 SDValue Op1 = Op.getOperand(1); 8521 SDValue Op2 = Op.getOperand(2); 8522 DebugLoc DL = Op.getDebugLoc(); 8523 SDValue CC; 8524 8525 if (Cond.getOpcode() == ISD::SETCC) { 8526 SDValue NewCond = LowerSETCC(Cond, DAG); 8527 if (NewCond.getNode()) 8528 Cond = NewCond; 8529 } 8530 8531 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8532 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8533 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8534 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8535 if (Cond.getOpcode() == X86ISD::SETCC && 8536 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8537 isZero(Cond.getOperand(1).getOperand(1))) { 8538 SDValue Cmp = Cond.getOperand(1); 8539 8540 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8541 8542 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8543 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8544 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8545 8546 SDValue CmpOp0 = Cmp.getOperand(0); 8547 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8548 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8549 8550 SDValue Res = // Res = 0 or -1. 8551 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8552 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8553 8554 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8555 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8556 8557 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8558 if (N2C == 0 || !N2C->isNullValue()) 8559 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8560 return Res; 8561 } 8562 } 8563 8564 // Look past (and (setcc_carry (cmp ...)), 1). 8565 if (Cond.getOpcode() == ISD::AND && 8566 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8568 if (C && C->getAPIntValue() == 1) 8569 Cond = Cond.getOperand(0); 8570 } 8571 8572 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8573 // setting operand in place of the X86ISD::SETCC. 8574 unsigned CondOpcode = Cond.getOpcode(); 8575 if (CondOpcode == X86ISD::SETCC || 8576 CondOpcode == X86ISD::SETCC_CARRY) { 8577 CC = Cond.getOperand(0); 8578 8579 SDValue Cmp = Cond.getOperand(1); 8580 unsigned Opc = Cmp.getOpcode(); 8581 EVT VT = Op.getValueType(); 8582 8583 bool IllegalFPCMov = false; 8584 if (VT.isFloatingPoint() && !VT.isVector() && 8585 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8586 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8587 8588 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8589 Opc == X86ISD::BT) { // FIXME 8590 Cond = Cmp; 8591 addTest = false; 8592 } 8593 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8594 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8595 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8596 Cond.getOperand(0).getValueType() != MVT::i8)) { 8597 SDValue LHS = Cond.getOperand(0); 8598 SDValue RHS = Cond.getOperand(1); 8599 unsigned X86Opcode; 8600 unsigned X86Cond; 8601 SDVTList VTs; 8602 switch (CondOpcode) { 8603 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8604 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8605 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8606 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8607 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8608 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8609 default: llvm_unreachable("unexpected overflowing operator"); 8610 } 8611 if (CondOpcode == ISD::UMULO) 8612 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8613 MVT::i32); 8614 else 8615 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8616 8617 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8618 8619 if (CondOpcode == ISD::UMULO) 8620 Cond = X86Op.getValue(2); 8621 else 8622 Cond = X86Op.getValue(1); 8623 8624 CC = DAG.getConstant(X86Cond, MVT::i8); 8625 addTest = false; 8626 } 8627 8628 if (addTest) { 8629 // Look pass the truncate. 8630 if (Cond.getOpcode() == ISD::TRUNCATE) 8631 Cond = Cond.getOperand(0); 8632 8633 // We know the result of AND is compared against zero. Try to match 8634 // it to BT. 8635 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8636 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8637 if (NewSetCC.getNode()) { 8638 CC = NewSetCC.getOperand(0); 8639 Cond = NewSetCC.getOperand(1); 8640 addTest = false; 8641 } 8642 } 8643 } 8644 8645 if (addTest) { 8646 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8647 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8648 } 8649 8650 // a < b ? -1 : 0 -> RES = ~setcc_carry 8651 // a < b ? 0 : -1 -> RES = setcc_carry 8652 // a >= b ? -1 : 0 -> RES = setcc_carry 8653 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8654 if (Cond.getOpcode() == X86ISD::CMP) { 8655 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8656 8657 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8658 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8659 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8660 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8661 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8662 return DAG.getNOT(DL, Res, Res.getValueType()); 8663 return Res; 8664 } 8665 } 8666 8667 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8668 // condition is true. 8669 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8670 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8671 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8672} 8673 8674// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8675// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8676// from the AND / OR. 8677static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8678 Opc = Op.getOpcode(); 8679 if (Opc != ISD::OR && Opc != ISD::AND) 8680 return false; 8681 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8682 Op.getOperand(0).hasOneUse() && 8683 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8684 Op.getOperand(1).hasOneUse()); 8685} 8686 8687// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8688// 1 and that the SETCC node has a single use. 8689static bool isXor1OfSetCC(SDValue Op) { 8690 if (Op.getOpcode() != ISD::XOR) 8691 return false; 8692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8693 if (N1C && N1C->getAPIntValue() == 1) { 8694 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8695 Op.getOperand(0).hasOneUse(); 8696 } 8697 return false; 8698} 8699 8700SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8701 bool addTest = true; 8702 SDValue Chain = Op.getOperand(0); 8703 SDValue Cond = Op.getOperand(1); 8704 SDValue Dest = Op.getOperand(2); 8705 DebugLoc dl = Op.getDebugLoc(); 8706 SDValue CC; 8707 bool Inverted = false; 8708 8709 if (Cond.getOpcode() == ISD::SETCC) { 8710 // Check for setcc([su]{add,sub,mul}o == 0). 8711 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8712 isa<ConstantSDNode>(Cond.getOperand(1)) && 8713 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8714 Cond.getOperand(0).getResNo() == 1 && 8715 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8716 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8717 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8718 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8719 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8720 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8721 Inverted = true; 8722 Cond = Cond.getOperand(0); 8723 } else { 8724 SDValue NewCond = LowerSETCC(Cond, DAG); 8725 if (NewCond.getNode()) 8726 Cond = NewCond; 8727 } 8728 } 8729#if 0 8730 // FIXME: LowerXALUO doesn't handle these!! 8731 else if (Cond.getOpcode() == X86ISD::ADD || 8732 Cond.getOpcode() == X86ISD::SUB || 8733 Cond.getOpcode() == X86ISD::SMUL || 8734 Cond.getOpcode() == X86ISD::UMUL) 8735 Cond = LowerXALUO(Cond, DAG); 8736#endif 8737 8738 // Look pass (and (setcc_carry (cmp ...)), 1). 8739 if (Cond.getOpcode() == ISD::AND && 8740 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8742 if (C && C->getAPIntValue() == 1) 8743 Cond = Cond.getOperand(0); 8744 } 8745 8746 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8747 // setting operand in place of the X86ISD::SETCC. 8748 unsigned CondOpcode = Cond.getOpcode(); 8749 if (CondOpcode == X86ISD::SETCC || 8750 CondOpcode == X86ISD::SETCC_CARRY) { 8751 CC = Cond.getOperand(0); 8752 8753 SDValue Cmp = Cond.getOperand(1); 8754 unsigned Opc = Cmp.getOpcode(); 8755 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8756 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8757 Cond = Cmp; 8758 addTest = false; 8759 } else { 8760 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8761 default: break; 8762 case X86::COND_O: 8763 case X86::COND_B: 8764 // These can only come from an arithmetic instruction with overflow, 8765 // e.g. SADDO, UADDO. 8766 Cond = Cond.getNode()->getOperand(1); 8767 addTest = false; 8768 break; 8769 } 8770 } 8771 } 8772 CondOpcode = Cond.getOpcode(); 8773 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8774 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8775 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8776 Cond.getOperand(0).getValueType() != MVT::i8)) { 8777 SDValue LHS = Cond.getOperand(0); 8778 SDValue RHS = Cond.getOperand(1); 8779 unsigned X86Opcode; 8780 unsigned X86Cond; 8781 SDVTList VTs; 8782 switch (CondOpcode) { 8783 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8784 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8785 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8786 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8787 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8788 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8789 default: llvm_unreachable("unexpected overflowing operator"); 8790 } 8791 if (Inverted) 8792 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8793 if (CondOpcode == ISD::UMULO) 8794 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8795 MVT::i32); 8796 else 8797 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8798 8799 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8800 8801 if (CondOpcode == ISD::UMULO) 8802 Cond = X86Op.getValue(2); 8803 else 8804 Cond = X86Op.getValue(1); 8805 8806 CC = DAG.getConstant(X86Cond, MVT::i8); 8807 addTest = false; 8808 } else { 8809 unsigned CondOpc; 8810 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8811 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8812 if (CondOpc == ISD::OR) { 8813 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8814 // two branches instead of an explicit OR instruction with a 8815 // separate test. 8816 if (Cmp == Cond.getOperand(1).getOperand(1) && 8817 isX86LogicalCmp(Cmp)) { 8818 CC = Cond.getOperand(0).getOperand(0); 8819 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8820 Chain, Dest, CC, Cmp); 8821 CC = Cond.getOperand(1).getOperand(0); 8822 Cond = Cmp; 8823 addTest = false; 8824 } 8825 } else { // ISD::AND 8826 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8827 // two branches instead of an explicit AND instruction with a 8828 // separate test. However, we only do this if this block doesn't 8829 // have a fall-through edge, because this requires an explicit 8830 // jmp when the condition is false. 8831 if (Cmp == Cond.getOperand(1).getOperand(1) && 8832 isX86LogicalCmp(Cmp) && 8833 Op.getNode()->hasOneUse()) { 8834 X86::CondCode CCode = 8835 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8836 CCode = X86::GetOppositeBranchCondition(CCode); 8837 CC = DAG.getConstant(CCode, MVT::i8); 8838 SDNode *User = *Op.getNode()->use_begin(); 8839 // Look for an unconditional branch following this conditional branch. 8840 // We need this because we need to reverse the successors in order 8841 // to implement FCMP_OEQ. 8842 if (User->getOpcode() == ISD::BR) { 8843 SDValue FalseBB = User->getOperand(1); 8844 SDNode *NewBR = 8845 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8846 assert(NewBR == User); 8847 (void)NewBR; 8848 Dest = FalseBB; 8849 8850 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8851 Chain, Dest, CC, Cmp); 8852 X86::CondCode CCode = 8853 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8854 CCode = X86::GetOppositeBranchCondition(CCode); 8855 CC = DAG.getConstant(CCode, MVT::i8); 8856 Cond = Cmp; 8857 addTest = false; 8858 } 8859 } 8860 } 8861 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8862 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8863 // It should be transformed during dag combiner except when the condition 8864 // is set by a arithmetics with overflow node. 8865 X86::CondCode CCode = 8866 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8867 CCode = X86::GetOppositeBranchCondition(CCode); 8868 CC = DAG.getConstant(CCode, MVT::i8); 8869 Cond = Cond.getOperand(0).getOperand(1); 8870 addTest = false; 8871 } else if (Cond.getOpcode() == ISD::SETCC && 8872 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8873 // For FCMP_OEQ, we can emit 8874 // two branches instead of an explicit AND instruction with a 8875 // separate test. However, we only do this if this block doesn't 8876 // have a fall-through edge, because this requires an explicit 8877 // jmp when the condition is false. 8878 if (Op.getNode()->hasOneUse()) { 8879 SDNode *User = *Op.getNode()->use_begin(); 8880 // Look for an unconditional branch following this conditional branch. 8881 // We need this because we need to reverse the successors in order 8882 // to implement FCMP_OEQ. 8883 if (User->getOpcode() == ISD::BR) { 8884 SDValue FalseBB = User->getOperand(1); 8885 SDNode *NewBR = 8886 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8887 assert(NewBR == User); 8888 (void)NewBR; 8889 Dest = FalseBB; 8890 8891 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8892 Cond.getOperand(0), Cond.getOperand(1)); 8893 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8894 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8895 Chain, Dest, CC, Cmp); 8896 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8897 Cond = Cmp; 8898 addTest = false; 8899 } 8900 } 8901 } else if (Cond.getOpcode() == ISD::SETCC && 8902 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8903 // For FCMP_UNE, we can emit 8904 // two branches instead of an explicit AND instruction with a 8905 // separate test. However, we only do this if this block doesn't 8906 // have a fall-through edge, because this requires an explicit 8907 // jmp when the condition is false. 8908 if (Op.getNode()->hasOneUse()) { 8909 SDNode *User = *Op.getNode()->use_begin(); 8910 // Look for an unconditional branch following this conditional branch. 8911 // We need this because we need to reverse the successors in order 8912 // to implement FCMP_UNE. 8913 if (User->getOpcode() == ISD::BR) { 8914 SDValue FalseBB = User->getOperand(1); 8915 SDNode *NewBR = 8916 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8917 assert(NewBR == User); 8918 (void)NewBR; 8919 8920 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8921 Cond.getOperand(0), Cond.getOperand(1)); 8922 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8923 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8924 Chain, Dest, CC, Cmp); 8925 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8926 Cond = Cmp; 8927 addTest = false; 8928 Dest = FalseBB; 8929 } 8930 } 8931 } 8932 } 8933 8934 if (addTest) { 8935 // Look pass the truncate. 8936 if (Cond.getOpcode() == ISD::TRUNCATE) 8937 Cond = Cond.getOperand(0); 8938 8939 // We know the result of AND is compared against zero. Try to match 8940 // it to BT. 8941 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8942 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8943 if (NewSetCC.getNode()) { 8944 CC = NewSetCC.getOperand(0); 8945 Cond = NewSetCC.getOperand(1); 8946 addTest = false; 8947 } 8948 } 8949 } 8950 8951 if (addTest) { 8952 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8953 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8954 } 8955 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8956 Chain, Dest, CC, Cond); 8957} 8958 8959 8960// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8961// Calls to _alloca is needed to probe the stack when allocating more than 4k 8962// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8963// that the guard pages used by the OS virtual memory manager are allocated in 8964// correct sequence. 8965SDValue 8966X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8967 SelectionDAG &DAG) const { 8968 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8969 getTargetMachine().Options.EnableSegmentedStacks) && 8970 "This should be used only on Windows targets or when segmented stacks " 8971 "are being used"); 8972 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8973 DebugLoc dl = Op.getDebugLoc(); 8974 8975 // Get the inputs. 8976 SDValue Chain = Op.getOperand(0); 8977 SDValue Size = Op.getOperand(1); 8978 // FIXME: Ensure alignment here 8979 8980 bool Is64Bit = Subtarget->is64Bit(); 8981 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8982 8983 if (getTargetMachine().Options.EnableSegmentedStacks) { 8984 MachineFunction &MF = DAG.getMachineFunction(); 8985 MachineRegisterInfo &MRI = MF.getRegInfo(); 8986 8987 if (Is64Bit) { 8988 // The 64 bit implementation of segmented stacks needs to clobber both r10 8989 // r11. This makes it impossible to use it along with nested parameters. 8990 const Function *F = MF.getFunction(); 8991 8992 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8993 I != E; I++) 8994 if (I->hasNestAttr()) 8995 report_fatal_error("Cannot use segmented stacks with functions that " 8996 "have nested arguments."); 8997 } 8998 8999 const TargetRegisterClass *AddrRegClass = 9000 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9001 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9002 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9003 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9004 DAG.getRegister(Vreg, SPTy)); 9005 SDValue Ops1[2] = { Value, Chain }; 9006 return DAG.getMergeValues(Ops1, 2, dl); 9007 } else { 9008 SDValue Flag; 9009 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9010 9011 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9012 Flag = Chain.getValue(1); 9013 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9014 9015 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9016 Flag = Chain.getValue(1); 9017 9018 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9019 9020 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9021 return DAG.getMergeValues(Ops1, 2, dl); 9022 } 9023} 9024 9025SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9026 MachineFunction &MF = DAG.getMachineFunction(); 9027 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9028 9029 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9030 DebugLoc DL = Op.getDebugLoc(); 9031 9032 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9033 // vastart just stores the address of the VarArgsFrameIndex slot into the 9034 // memory location argument. 9035 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9036 getPointerTy()); 9037 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9038 MachinePointerInfo(SV), false, false, 0); 9039 } 9040 9041 // __va_list_tag: 9042 // gp_offset (0 - 6 * 8) 9043 // fp_offset (48 - 48 + 8 * 16) 9044 // overflow_arg_area (point to parameters coming in memory). 9045 // reg_save_area 9046 SmallVector<SDValue, 8> MemOps; 9047 SDValue FIN = Op.getOperand(1); 9048 // Store gp_offset 9049 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9050 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9051 MVT::i32), 9052 FIN, MachinePointerInfo(SV), false, false, 0); 9053 MemOps.push_back(Store); 9054 9055 // Store fp_offset 9056 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9057 FIN, DAG.getIntPtrConstant(4)); 9058 Store = DAG.getStore(Op.getOperand(0), DL, 9059 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9060 MVT::i32), 9061 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9062 MemOps.push_back(Store); 9063 9064 // Store ptr to overflow_arg_area 9065 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9066 FIN, DAG.getIntPtrConstant(4)); 9067 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9068 getPointerTy()); 9069 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9070 MachinePointerInfo(SV, 8), 9071 false, false, 0); 9072 MemOps.push_back(Store); 9073 9074 // Store ptr to reg_save_area. 9075 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9076 FIN, DAG.getIntPtrConstant(8)); 9077 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9078 getPointerTy()); 9079 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9080 MachinePointerInfo(SV, 16), false, false, 0); 9081 MemOps.push_back(Store); 9082 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9083 &MemOps[0], MemOps.size()); 9084} 9085 9086SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9087 assert(Subtarget->is64Bit() && 9088 "LowerVAARG only handles 64-bit va_arg!"); 9089 assert((Subtarget->isTargetLinux() || 9090 Subtarget->isTargetDarwin()) && 9091 "Unhandled target in LowerVAARG"); 9092 assert(Op.getNode()->getNumOperands() == 4); 9093 SDValue Chain = Op.getOperand(0); 9094 SDValue SrcPtr = Op.getOperand(1); 9095 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9096 unsigned Align = Op.getConstantOperandVal(3); 9097 DebugLoc dl = Op.getDebugLoc(); 9098 9099 EVT ArgVT = Op.getNode()->getValueType(0); 9100 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9101 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9102 uint8_t ArgMode; 9103 9104 // Decide which area this value should be read from. 9105 // TODO: Implement the AMD64 ABI in its entirety. This simple 9106 // selection mechanism works only for the basic types. 9107 if (ArgVT == MVT::f80) { 9108 llvm_unreachable("va_arg for f80 not yet implemented"); 9109 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9110 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9111 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9112 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9113 } else { 9114 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9115 } 9116 9117 if (ArgMode == 2) { 9118 // Sanity Check: Make sure using fp_offset makes sense. 9119 assert(!getTargetMachine().Options.UseSoftFloat && 9120 !(DAG.getMachineFunction() 9121 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9122 Subtarget->hasSSE1()); 9123 } 9124 9125 // Insert VAARG_64 node into the DAG 9126 // VAARG_64 returns two values: Variable Argument Address, Chain 9127 SmallVector<SDValue, 11> InstOps; 9128 InstOps.push_back(Chain); 9129 InstOps.push_back(SrcPtr); 9130 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9131 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9132 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9133 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9134 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9135 VTs, &InstOps[0], InstOps.size(), 9136 MVT::i64, 9137 MachinePointerInfo(SV), 9138 /*Align=*/0, 9139 /*Volatile=*/false, 9140 /*ReadMem=*/true, 9141 /*WriteMem=*/true); 9142 Chain = VAARG.getValue(1); 9143 9144 // Load the next argument and return it 9145 return DAG.getLoad(ArgVT, dl, 9146 Chain, 9147 VAARG, 9148 MachinePointerInfo(), 9149 false, false, false, 0); 9150} 9151 9152SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9153 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9154 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9155 SDValue Chain = Op.getOperand(0); 9156 SDValue DstPtr = Op.getOperand(1); 9157 SDValue SrcPtr = Op.getOperand(2); 9158 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9159 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9160 DebugLoc DL = Op.getDebugLoc(); 9161 9162 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9163 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9164 false, 9165 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9166} 9167 9168SDValue 9169X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9170 DebugLoc dl = Op.getDebugLoc(); 9171 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9172 switch (IntNo) { 9173 default: return SDValue(); // Don't custom lower most intrinsics. 9174 // Comparison intrinsics. 9175 case Intrinsic::x86_sse_comieq_ss: 9176 case Intrinsic::x86_sse_comilt_ss: 9177 case Intrinsic::x86_sse_comile_ss: 9178 case Intrinsic::x86_sse_comigt_ss: 9179 case Intrinsic::x86_sse_comige_ss: 9180 case Intrinsic::x86_sse_comineq_ss: 9181 case Intrinsic::x86_sse_ucomieq_ss: 9182 case Intrinsic::x86_sse_ucomilt_ss: 9183 case Intrinsic::x86_sse_ucomile_ss: 9184 case Intrinsic::x86_sse_ucomigt_ss: 9185 case Intrinsic::x86_sse_ucomige_ss: 9186 case Intrinsic::x86_sse_ucomineq_ss: 9187 case Intrinsic::x86_sse2_comieq_sd: 9188 case Intrinsic::x86_sse2_comilt_sd: 9189 case Intrinsic::x86_sse2_comile_sd: 9190 case Intrinsic::x86_sse2_comigt_sd: 9191 case Intrinsic::x86_sse2_comige_sd: 9192 case Intrinsic::x86_sse2_comineq_sd: 9193 case Intrinsic::x86_sse2_ucomieq_sd: 9194 case Intrinsic::x86_sse2_ucomilt_sd: 9195 case Intrinsic::x86_sse2_ucomile_sd: 9196 case Intrinsic::x86_sse2_ucomigt_sd: 9197 case Intrinsic::x86_sse2_ucomige_sd: 9198 case Intrinsic::x86_sse2_ucomineq_sd: { 9199 unsigned Opc = 0; 9200 ISD::CondCode CC = ISD::SETCC_INVALID; 9201 switch (IntNo) { 9202 default: break; 9203 case Intrinsic::x86_sse_comieq_ss: 9204 case Intrinsic::x86_sse2_comieq_sd: 9205 Opc = X86ISD::COMI; 9206 CC = ISD::SETEQ; 9207 break; 9208 case Intrinsic::x86_sse_comilt_ss: 9209 case Intrinsic::x86_sse2_comilt_sd: 9210 Opc = X86ISD::COMI; 9211 CC = ISD::SETLT; 9212 break; 9213 case Intrinsic::x86_sse_comile_ss: 9214 case Intrinsic::x86_sse2_comile_sd: 9215 Opc = X86ISD::COMI; 9216 CC = ISD::SETLE; 9217 break; 9218 case Intrinsic::x86_sse_comigt_ss: 9219 case Intrinsic::x86_sse2_comigt_sd: 9220 Opc = X86ISD::COMI; 9221 CC = ISD::SETGT; 9222 break; 9223 case Intrinsic::x86_sse_comige_ss: 9224 case Intrinsic::x86_sse2_comige_sd: 9225 Opc = X86ISD::COMI; 9226 CC = ISD::SETGE; 9227 break; 9228 case Intrinsic::x86_sse_comineq_ss: 9229 case Intrinsic::x86_sse2_comineq_sd: 9230 Opc = X86ISD::COMI; 9231 CC = ISD::SETNE; 9232 break; 9233 case Intrinsic::x86_sse_ucomieq_ss: 9234 case Intrinsic::x86_sse2_ucomieq_sd: 9235 Opc = X86ISD::UCOMI; 9236 CC = ISD::SETEQ; 9237 break; 9238 case Intrinsic::x86_sse_ucomilt_ss: 9239 case Intrinsic::x86_sse2_ucomilt_sd: 9240 Opc = X86ISD::UCOMI; 9241 CC = ISD::SETLT; 9242 break; 9243 case Intrinsic::x86_sse_ucomile_ss: 9244 case Intrinsic::x86_sse2_ucomile_sd: 9245 Opc = X86ISD::UCOMI; 9246 CC = ISD::SETLE; 9247 break; 9248 case Intrinsic::x86_sse_ucomigt_ss: 9249 case Intrinsic::x86_sse2_ucomigt_sd: 9250 Opc = X86ISD::UCOMI; 9251 CC = ISD::SETGT; 9252 break; 9253 case Intrinsic::x86_sse_ucomige_ss: 9254 case Intrinsic::x86_sse2_ucomige_sd: 9255 Opc = X86ISD::UCOMI; 9256 CC = ISD::SETGE; 9257 break; 9258 case Intrinsic::x86_sse_ucomineq_ss: 9259 case Intrinsic::x86_sse2_ucomineq_sd: 9260 Opc = X86ISD::UCOMI; 9261 CC = ISD::SETNE; 9262 break; 9263 } 9264 9265 SDValue LHS = Op.getOperand(1); 9266 SDValue RHS = Op.getOperand(2); 9267 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9268 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9269 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9270 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9271 DAG.getConstant(X86CC, MVT::i8), Cond); 9272 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9273 } 9274 // Arithmetic intrinsics. 9275 case Intrinsic::x86_sse3_hadd_ps: 9276 case Intrinsic::x86_sse3_hadd_pd: 9277 case Intrinsic::x86_avx_hadd_ps_256: 9278 case Intrinsic::x86_avx_hadd_pd_256: 9279 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9280 Op.getOperand(1), Op.getOperand(2)); 9281 case Intrinsic::x86_sse3_hsub_ps: 9282 case Intrinsic::x86_sse3_hsub_pd: 9283 case Intrinsic::x86_avx_hsub_ps_256: 9284 case Intrinsic::x86_avx_hsub_pd_256: 9285 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9286 Op.getOperand(1), Op.getOperand(2)); 9287 case Intrinsic::x86_avx2_psllv_d: 9288 case Intrinsic::x86_avx2_psllv_q: 9289 case Intrinsic::x86_avx2_psllv_d_256: 9290 case Intrinsic::x86_avx2_psllv_q_256: 9291 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9292 Op.getOperand(1), Op.getOperand(2)); 9293 case Intrinsic::x86_avx2_psrlv_d: 9294 case Intrinsic::x86_avx2_psrlv_q: 9295 case Intrinsic::x86_avx2_psrlv_d_256: 9296 case Intrinsic::x86_avx2_psrlv_q_256: 9297 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9298 Op.getOperand(1), Op.getOperand(2)); 9299 case Intrinsic::x86_avx2_psrav_d: 9300 case Intrinsic::x86_avx2_psrav_d_256: 9301 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9302 Op.getOperand(1), Op.getOperand(2)); 9303 9304 // ptest and testp intrinsics. The intrinsic these come from are designed to 9305 // return an integer value, not just an instruction so lower it to the ptest 9306 // or testp pattern and a setcc for the result. 9307 case Intrinsic::x86_sse41_ptestz: 9308 case Intrinsic::x86_sse41_ptestc: 9309 case Intrinsic::x86_sse41_ptestnzc: 9310 case Intrinsic::x86_avx_ptestz_256: 9311 case Intrinsic::x86_avx_ptestc_256: 9312 case Intrinsic::x86_avx_ptestnzc_256: 9313 case Intrinsic::x86_avx_vtestz_ps: 9314 case Intrinsic::x86_avx_vtestc_ps: 9315 case Intrinsic::x86_avx_vtestnzc_ps: 9316 case Intrinsic::x86_avx_vtestz_pd: 9317 case Intrinsic::x86_avx_vtestc_pd: 9318 case Intrinsic::x86_avx_vtestnzc_pd: 9319 case Intrinsic::x86_avx_vtestz_ps_256: 9320 case Intrinsic::x86_avx_vtestc_ps_256: 9321 case Intrinsic::x86_avx_vtestnzc_ps_256: 9322 case Intrinsic::x86_avx_vtestz_pd_256: 9323 case Intrinsic::x86_avx_vtestc_pd_256: 9324 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9325 bool IsTestPacked = false; 9326 unsigned X86CC = 0; 9327 switch (IntNo) { 9328 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9329 case Intrinsic::x86_avx_vtestz_ps: 9330 case Intrinsic::x86_avx_vtestz_pd: 9331 case Intrinsic::x86_avx_vtestz_ps_256: 9332 case Intrinsic::x86_avx_vtestz_pd_256: 9333 IsTestPacked = true; // Fallthrough 9334 case Intrinsic::x86_sse41_ptestz: 9335 case Intrinsic::x86_avx_ptestz_256: 9336 // ZF = 1 9337 X86CC = X86::COND_E; 9338 break; 9339 case Intrinsic::x86_avx_vtestc_ps: 9340 case Intrinsic::x86_avx_vtestc_pd: 9341 case Intrinsic::x86_avx_vtestc_ps_256: 9342 case Intrinsic::x86_avx_vtestc_pd_256: 9343 IsTestPacked = true; // Fallthrough 9344 case Intrinsic::x86_sse41_ptestc: 9345 case Intrinsic::x86_avx_ptestc_256: 9346 // CF = 1 9347 X86CC = X86::COND_B; 9348 break; 9349 case Intrinsic::x86_avx_vtestnzc_ps: 9350 case Intrinsic::x86_avx_vtestnzc_pd: 9351 case Intrinsic::x86_avx_vtestnzc_ps_256: 9352 case Intrinsic::x86_avx_vtestnzc_pd_256: 9353 IsTestPacked = true; // Fallthrough 9354 case Intrinsic::x86_sse41_ptestnzc: 9355 case Intrinsic::x86_avx_ptestnzc_256: 9356 // ZF and CF = 0 9357 X86CC = X86::COND_A; 9358 break; 9359 } 9360 9361 SDValue LHS = Op.getOperand(1); 9362 SDValue RHS = Op.getOperand(2); 9363 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9364 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9365 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9366 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9367 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9368 } 9369 9370 // Fix vector shift instructions where the last operand is a non-immediate 9371 // i32 value. 9372 case Intrinsic::x86_avx2_pslli_w: 9373 case Intrinsic::x86_avx2_pslli_d: 9374 case Intrinsic::x86_avx2_pslli_q: 9375 case Intrinsic::x86_avx2_psrli_w: 9376 case Intrinsic::x86_avx2_psrli_d: 9377 case Intrinsic::x86_avx2_psrli_q: 9378 case Intrinsic::x86_avx2_psrai_w: 9379 case Intrinsic::x86_avx2_psrai_d: 9380 case Intrinsic::x86_sse2_pslli_w: 9381 case Intrinsic::x86_sse2_pslli_d: 9382 case Intrinsic::x86_sse2_pslli_q: 9383 case Intrinsic::x86_sse2_psrli_w: 9384 case Intrinsic::x86_sse2_psrli_d: 9385 case Intrinsic::x86_sse2_psrli_q: 9386 case Intrinsic::x86_sse2_psrai_w: 9387 case Intrinsic::x86_sse2_psrai_d: 9388 case Intrinsic::x86_mmx_pslli_w: 9389 case Intrinsic::x86_mmx_pslli_d: 9390 case Intrinsic::x86_mmx_pslli_q: 9391 case Intrinsic::x86_mmx_psrli_w: 9392 case Intrinsic::x86_mmx_psrli_d: 9393 case Intrinsic::x86_mmx_psrli_q: 9394 case Intrinsic::x86_mmx_psrai_w: 9395 case Intrinsic::x86_mmx_psrai_d: { 9396 SDValue ShAmt = Op.getOperand(2); 9397 if (isa<ConstantSDNode>(ShAmt)) 9398 return SDValue(); 9399 9400 unsigned NewIntNo = 0; 9401 EVT ShAmtVT = MVT::v4i32; 9402 switch (IntNo) { 9403 case Intrinsic::x86_sse2_pslli_w: 9404 NewIntNo = Intrinsic::x86_sse2_psll_w; 9405 break; 9406 case Intrinsic::x86_sse2_pslli_d: 9407 NewIntNo = Intrinsic::x86_sse2_psll_d; 9408 break; 9409 case Intrinsic::x86_sse2_pslli_q: 9410 NewIntNo = Intrinsic::x86_sse2_psll_q; 9411 break; 9412 case Intrinsic::x86_sse2_psrli_w: 9413 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9414 break; 9415 case Intrinsic::x86_sse2_psrli_d: 9416 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9417 break; 9418 case Intrinsic::x86_sse2_psrli_q: 9419 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9420 break; 9421 case Intrinsic::x86_sse2_psrai_w: 9422 NewIntNo = Intrinsic::x86_sse2_psra_w; 9423 break; 9424 case Intrinsic::x86_sse2_psrai_d: 9425 NewIntNo = Intrinsic::x86_sse2_psra_d; 9426 break; 9427 case Intrinsic::x86_avx2_pslli_w: 9428 NewIntNo = Intrinsic::x86_avx2_psll_w; 9429 break; 9430 case Intrinsic::x86_avx2_pslli_d: 9431 NewIntNo = Intrinsic::x86_avx2_psll_d; 9432 break; 9433 case Intrinsic::x86_avx2_pslli_q: 9434 NewIntNo = Intrinsic::x86_avx2_psll_q; 9435 break; 9436 case Intrinsic::x86_avx2_psrli_w: 9437 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9438 break; 9439 case Intrinsic::x86_avx2_psrli_d: 9440 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9441 break; 9442 case Intrinsic::x86_avx2_psrli_q: 9443 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9444 break; 9445 case Intrinsic::x86_avx2_psrai_w: 9446 NewIntNo = Intrinsic::x86_avx2_psra_w; 9447 break; 9448 case Intrinsic::x86_avx2_psrai_d: 9449 NewIntNo = Intrinsic::x86_avx2_psra_d; 9450 break; 9451 default: { 9452 ShAmtVT = MVT::v2i32; 9453 switch (IntNo) { 9454 case Intrinsic::x86_mmx_pslli_w: 9455 NewIntNo = Intrinsic::x86_mmx_psll_w; 9456 break; 9457 case Intrinsic::x86_mmx_pslli_d: 9458 NewIntNo = Intrinsic::x86_mmx_psll_d; 9459 break; 9460 case Intrinsic::x86_mmx_pslli_q: 9461 NewIntNo = Intrinsic::x86_mmx_psll_q; 9462 break; 9463 case Intrinsic::x86_mmx_psrli_w: 9464 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9465 break; 9466 case Intrinsic::x86_mmx_psrli_d: 9467 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9468 break; 9469 case Intrinsic::x86_mmx_psrli_q: 9470 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9471 break; 9472 case Intrinsic::x86_mmx_psrai_w: 9473 NewIntNo = Intrinsic::x86_mmx_psra_w; 9474 break; 9475 case Intrinsic::x86_mmx_psrai_d: 9476 NewIntNo = Intrinsic::x86_mmx_psra_d; 9477 break; 9478 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9479 } 9480 break; 9481 } 9482 } 9483 9484 // The vector shift intrinsics with scalars uses 32b shift amounts but 9485 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9486 // to be zero. 9487 SDValue ShOps[4]; 9488 ShOps[0] = ShAmt; 9489 ShOps[1] = DAG.getConstant(0, MVT::i32); 9490 if (ShAmtVT == MVT::v4i32) { 9491 ShOps[2] = DAG.getUNDEF(MVT::i32); 9492 ShOps[3] = DAG.getUNDEF(MVT::i32); 9493 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9494 } else { 9495 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9496// FIXME this must be lowered to get rid of the invalid type. 9497 } 9498 9499 EVT VT = Op.getValueType(); 9500 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9501 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9502 DAG.getConstant(NewIntNo, MVT::i32), 9503 Op.getOperand(1), ShAmt); 9504 } 9505 } 9506} 9507 9508SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9509 SelectionDAG &DAG) const { 9510 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9511 MFI->setReturnAddressIsTaken(true); 9512 9513 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9514 DebugLoc dl = Op.getDebugLoc(); 9515 9516 if (Depth > 0) { 9517 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9518 SDValue Offset = 9519 DAG.getConstant(TD->getPointerSize(), 9520 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9521 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9522 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9523 FrameAddr, Offset), 9524 MachinePointerInfo(), false, false, false, 0); 9525 } 9526 9527 // Just load the return address. 9528 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9529 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9530 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9531} 9532 9533SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9534 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9535 MFI->setFrameAddressIsTaken(true); 9536 9537 EVT VT = Op.getValueType(); 9538 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9539 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9540 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9541 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9542 while (Depth--) 9543 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9544 MachinePointerInfo(), 9545 false, false, false, 0); 9546 return FrameAddr; 9547} 9548 9549SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9550 SelectionDAG &DAG) const { 9551 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9552} 9553 9554SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9555 MachineFunction &MF = DAG.getMachineFunction(); 9556 SDValue Chain = Op.getOperand(0); 9557 SDValue Offset = Op.getOperand(1); 9558 SDValue Handler = Op.getOperand(2); 9559 DebugLoc dl = Op.getDebugLoc(); 9560 9561 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9562 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9563 getPointerTy()); 9564 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9565 9566 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9567 DAG.getIntPtrConstant(TD->getPointerSize())); 9568 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9569 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9570 false, false, 0); 9571 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9572 MF.getRegInfo().addLiveOut(StoreAddrReg); 9573 9574 return DAG.getNode(X86ISD::EH_RETURN, dl, 9575 MVT::Other, 9576 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9577} 9578 9579SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9580 SelectionDAG &DAG) const { 9581 return Op.getOperand(0); 9582} 9583 9584SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9585 SelectionDAG &DAG) const { 9586 SDValue Root = Op.getOperand(0); 9587 SDValue Trmp = Op.getOperand(1); // trampoline 9588 SDValue FPtr = Op.getOperand(2); // nested function 9589 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9590 DebugLoc dl = Op.getDebugLoc(); 9591 9592 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9593 9594 if (Subtarget->is64Bit()) { 9595 SDValue OutChains[6]; 9596 9597 // Large code-model. 9598 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9599 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9600 9601 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9602 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9603 9604 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9605 9606 // Load the pointer to the nested function into R11. 9607 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9608 SDValue Addr = Trmp; 9609 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9610 Addr, MachinePointerInfo(TrmpAddr), 9611 false, false, 0); 9612 9613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9614 DAG.getConstant(2, MVT::i64)); 9615 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9616 MachinePointerInfo(TrmpAddr, 2), 9617 false, false, 2); 9618 9619 // Load the 'nest' parameter value into R10. 9620 // R10 is specified in X86CallingConv.td 9621 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9622 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9623 DAG.getConstant(10, MVT::i64)); 9624 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9625 Addr, MachinePointerInfo(TrmpAddr, 10), 9626 false, false, 0); 9627 9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9629 DAG.getConstant(12, MVT::i64)); 9630 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9631 MachinePointerInfo(TrmpAddr, 12), 9632 false, false, 2); 9633 9634 // Jump to the nested function. 9635 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9636 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9637 DAG.getConstant(20, MVT::i64)); 9638 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9639 Addr, MachinePointerInfo(TrmpAddr, 20), 9640 false, false, 0); 9641 9642 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9643 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9644 DAG.getConstant(22, MVT::i64)); 9645 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9646 MachinePointerInfo(TrmpAddr, 22), 9647 false, false, 0); 9648 9649 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9650 } else { 9651 const Function *Func = 9652 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9653 CallingConv::ID CC = Func->getCallingConv(); 9654 unsigned NestReg; 9655 9656 switch (CC) { 9657 default: 9658 llvm_unreachable("Unsupported calling convention"); 9659 case CallingConv::C: 9660 case CallingConv::X86_StdCall: { 9661 // Pass 'nest' parameter in ECX. 9662 // Must be kept in sync with X86CallingConv.td 9663 NestReg = X86::ECX; 9664 9665 // Check that ECX wasn't needed by an 'inreg' parameter. 9666 FunctionType *FTy = Func->getFunctionType(); 9667 const AttrListPtr &Attrs = Func->getAttributes(); 9668 9669 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9670 unsigned InRegCount = 0; 9671 unsigned Idx = 1; 9672 9673 for (FunctionType::param_iterator I = FTy->param_begin(), 9674 E = FTy->param_end(); I != E; ++I, ++Idx) 9675 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9676 // FIXME: should only count parameters that are lowered to integers. 9677 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9678 9679 if (InRegCount > 2) { 9680 report_fatal_error("Nest register in use - reduce number of inreg" 9681 " parameters!"); 9682 } 9683 } 9684 break; 9685 } 9686 case CallingConv::X86_FastCall: 9687 case CallingConv::X86_ThisCall: 9688 case CallingConv::Fast: 9689 // Pass 'nest' parameter in EAX. 9690 // Must be kept in sync with X86CallingConv.td 9691 NestReg = X86::EAX; 9692 break; 9693 } 9694 9695 SDValue OutChains[4]; 9696 SDValue Addr, Disp; 9697 9698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9699 DAG.getConstant(10, MVT::i32)); 9700 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9701 9702 // This is storing the opcode for MOV32ri. 9703 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9704 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9705 OutChains[0] = DAG.getStore(Root, dl, 9706 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9707 Trmp, MachinePointerInfo(TrmpAddr), 9708 false, false, 0); 9709 9710 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9711 DAG.getConstant(1, MVT::i32)); 9712 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9713 MachinePointerInfo(TrmpAddr, 1), 9714 false, false, 1); 9715 9716 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9718 DAG.getConstant(5, MVT::i32)); 9719 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9720 MachinePointerInfo(TrmpAddr, 5), 9721 false, false, 1); 9722 9723 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9724 DAG.getConstant(6, MVT::i32)); 9725 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9726 MachinePointerInfo(TrmpAddr, 6), 9727 false, false, 1); 9728 9729 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9730 } 9731} 9732 9733SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9734 SelectionDAG &DAG) const { 9735 /* 9736 The rounding mode is in bits 11:10 of FPSR, and has the following 9737 settings: 9738 00 Round to nearest 9739 01 Round to -inf 9740 10 Round to +inf 9741 11 Round to 0 9742 9743 FLT_ROUNDS, on the other hand, expects the following: 9744 -1 Undefined 9745 0 Round to 0 9746 1 Round to nearest 9747 2 Round to +inf 9748 3 Round to -inf 9749 9750 To perform the conversion, we do: 9751 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9752 */ 9753 9754 MachineFunction &MF = DAG.getMachineFunction(); 9755 const TargetMachine &TM = MF.getTarget(); 9756 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9757 unsigned StackAlignment = TFI.getStackAlignment(); 9758 EVT VT = Op.getValueType(); 9759 DebugLoc DL = Op.getDebugLoc(); 9760 9761 // Save FP Control Word to stack slot 9762 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9763 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9764 9765 9766 MachineMemOperand *MMO = 9767 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9768 MachineMemOperand::MOStore, 2, 2); 9769 9770 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9771 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9772 DAG.getVTList(MVT::Other), 9773 Ops, 2, MVT::i16, MMO); 9774 9775 // Load FP Control Word from stack slot 9776 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9777 MachinePointerInfo(), false, false, false, 0); 9778 9779 // Transform as necessary 9780 SDValue CWD1 = 9781 DAG.getNode(ISD::SRL, DL, MVT::i16, 9782 DAG.getNode(ISD::AND, DL, MVT::i16, 9783 CWD, DAG.getConstant(0x800, MVT::i16)), 9784 DAG.getConstant(11, MVT::i8)); 9785 SDValue CWD2 = 9786 DAG.getNode(ISD::SRL, DL, MVT::i16, 9787 DAG.getNode(ISD::AND, DL, MVT::i16, 9788 CWD, DAG.getConstant(0x400, MVT::i16)), 9789 DAG.getConstant(9, MVT::i8)); 9790 9791 SDValue RetVal = 9792 DAG.getNode(ISD::AND, DL, MVT::i16, 9793 DAG.getNode(ISD::ADD, DL, MVT::i16, 9794 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9795 DAG.getConstant(1, MVT::i16)), 9796 DAG.getConstant(3, MVT::i16)); 9797 9798 9799 return DAG.getNode((VT.getSizeInBits() < 16 ? 9800 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9801} 9802 9803SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9804 EVT VT = Op.getValueType(); 9805 EVT OpVT = VT; 9806 unsigned NumBits = VT.getSizeInBits(); 9807 DebugLoc dl = Op.getDebugLoc(); 9808 9809 Op = Op.getOperand(0); 9810 if (VT == MVT::i8) { 9811 // Zero extend to i32 since there is not an i8 bsr. 9812 OpVT = MVT::i32; 9813 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9814 } 9815 9816 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9817 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9818 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9819 9820 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9821 SDValue Ops[] = { 9822 Op, 9823 DAG.getConstant(NumBits+NumBits-1, OpVT), 9824 DAG.getConstant(X86::COND_E, MVT::i8), 9825 Op.getValue(1) 9826 }; 9827 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9828 9829 // Finally xor with NumBits-1. 9830 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9831 9832 if (VT == MVT::i8) 9833 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9834 return Op; 9835} 9836 9837SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9838 SelectionDAG &DAG) const { 9839 EVT VT = Op.getValueType(); 9840 EVT OpVT = VT; 9841 unsigned NumBits = VT.getSizeInBits(); 9842 DebugLoc dl = Op.getDebugLoc(); 9843 9844 Op = Op.getOperand(0); 9845 if (VT == MVT::i8) { 9846 // Zero extend to i32 since there is not an i8 bsr. 9847 OpVT = MVT::i32; 9848 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9849 } 9850 9851 // Issue a bsr (scan bits in reverse). 9852 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9853 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9854 9855 // And xor with NumBits-1. 9856 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9857 9858 if (VT == MVT::i8) 9859 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9860 return Op; 9861} 9862 9863SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9864 EVT VT = Op.getValueType(); 9865 unsigned NumBits = VT.getSizeInBits(); 9866 DebugLoc dl = Op.getDebugLoc(); 9867 Op = Op.getOperand(0); 9868 9869 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9870 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9871 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9872 9873 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9874 SDValue Ops[] = { 9875 Op, 9876 DAG.getConstant(NumBits, VT), 9877 DAG.getConstant(X86::COND_E, MVT::i8), 9878 Op.getValue(1) 9879 }; 9880 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 9881} 9882 9883// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9884// ones, and then concatenate the result back. 9885static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9886 EVT VT = Op.getValueType(); 9887 9888 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9889 "Unsupported value type for operation"); 9890 9891 int NumElems = VT.getVectorNumElements(); 9892 DebugLoc dl = Op.getDebugLoc(); 9893 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9894 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9895 9896 // Extract the LHS vectors 9897 SDValue LHS = Op.getOperand(0); 9898 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9899 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9900 9901 // Extract the RHS vectors 9902 SDValue RHS = Op.getOperand(1); 9903 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9904 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9905 9906 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9907 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9908 9909 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9910 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9911 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9912} 9913 9914SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9915 assert(Op.getValueType().getSizeInBits() == 256 && 9916 Op.getValueType().isInteger() && 9917 "Only handle AVX 256-bit vector integer operation"); 9918 return Lower256IntArith(Op, DAG); 9919} 9920 9921SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9922 assert(Op.getValueType().getSizeInBits() == 256 && 9923 Op.getValueType().isInteger() && 9924 "Only handle AVX 256-bit vector integer operation"); 9925 return Lower256IntArith(Op, DAG); 9926} 9927 9928SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9929 EVT VT = Op.getValueType(); 9930 9931 // Decompose 256-bit ops into smaller 128-bit ops. 9932 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 9933 return Lower256IntArith(Op, DAG); 9934 9935 DebugLoc dl = Op.getDebugLoc(); 9936 9937 SDValue A = Op.getOperand(0); 9938 SDValue B = Op.getOperand(1); 9939 9940 if (VT == MVT::v4i64) { 9941 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 9942 9943 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 9944 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 9945 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 9946 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 9947 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 9948 // 9949 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 9950 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 9951 // return AloBlo + AloBhi + AhiBlo; 9952 9953 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9954 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9955 A, DAG.getConstant(32, MVT::i32)); 9956 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9957 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9958 B, DAG.getConstant(32, MVT::i32)); 9959 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9960 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9961 A, B); 9962 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9963 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9964 A, Bhi); 9965 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9966 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9967 Ahi, B); 9968 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9969 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9970 AloBhi, DAG.getConstant(32, MVT::i32)); 9971 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9972 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9973 AhiBlo, DAG.getConstant(32, MVT::i32)); 9974 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9975 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9976 return Res; 9977 } 9978 9979 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9980 9981 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9982 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9983 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9984 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9985 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9986 // 9987 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9988 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9989 // return AloBlo + AloBhi + AhiBlo; 9990 9991 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9992 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9993 A, DAG.getConstant(32, MVT::i32)); 9994 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9995 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9996 B, DAG.getConstant(32, MVT::i32)); 9997 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9998 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9999 A, B); 10000 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10001 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10002 A, Bhi); 10003 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10004 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10005 Ahi, B); 10006 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10007 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10008 AloBhi, DAG.getConstant(32, MVT::i32)); 10009 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10010 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10011 AhiBlo, DAG.getConstant(32, MVT::i32)); 10012 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10013 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10014 return Res; 10015} 10016 10017SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10018 10019 EVT VT = Op.getValueType(); 10020 DebugLoc dl = Op.getDebugLoc(); 10021 SDValue R = Op.getOperand(0); 10022 SDValue Amt = Op.getOperand(1); 10023 LLVMContext *Context = DAG.getContext(); 10024 10025 if (!Subtarget->hasSSE2()) 10026 return SDValue(); 10027 10028 // Optimize shl/srl/sra with constant shift amount. 10029 if (isSplatVector(Amt.getNode())) { 10030 SDValue SclrAmt = Amt->getOperand(0); 10031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10032 uint64_t ShiftAmt = C->getZExtValue(); 10033 10034 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) { 10035 // Make a large shift. 10036 SDValue SHL = 10037 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10038 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10039 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10040 // Zero out the rightmost bits. 10041 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10042 MVT::i8)); 10043 return DAG.getNode(ISD::AND, dl, VT, SHL, 10044 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10045 } 10046 10047 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 10048 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10049 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10050 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10051 10052 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 10053 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10054 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10055 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10056 10057 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 10058 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10059 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10060 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10061 10062 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) { 10063 // Make a large shift. 10064 SDValue SRL = 10065 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10066 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10067 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10068 // Zero out the leftmost bits. 10069 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10070 MVT::i8)); 10071 return DAG.getNode(ISD::AND, dl, VT, SRL, 10072 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10073 } 10074 10075 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 10076 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10077 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10078 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10079 10080 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 10081 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10082 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10083 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10084 10085 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 10086 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10087 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10088 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10089 10090 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 10091 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10092 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10093 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10094 10095 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 10096 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10097 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10098 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10099 10100 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) { 10101 if (ShiftAmt == 7) { 10102 // R s>> 7 === R s< 0 10103 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 10104 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10105 } 10106 10107 // R s>> a === ((R u>> a) ^ m) - m 10108 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10109 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10110 MVT::i8)); 10111 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10112 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10113 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10114 return Res; 10115 } 10116 10117 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10118 if (Op.getOpcode() == ISD::SHL) { 10119 // Make a large shift. 10120 SDValue SHL = 10121 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10122 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 10123 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10124 // Zero out the rightmost bits. 10125 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10126 MVT::i8)); 10127 return DAG.getNode(ISD::AND, dl, VT, SHL, 10128 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10129 } 10130 if (Op.getOpcode() == ISD::SRL) { 10131 // Make a large shift. 10132 SDValue SRL = 10133 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10134 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 10135 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10136 // Zero out the leftmost bits. 10137 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10138 MVT::i8)); 10139 return DAG.getNode(ISD::AND, dl, VT, SRL, 10140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10141 } 10142 if (Op.getOpcode() == ISD::SRA) { 10143 if (ShiftAmt == 7) { 10144 // R s>> 7 === R s< 0 10145 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 10146 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10147 } 10148 10149 // R s>> a === ((R u>> a) ^ m) - m 10150 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10151 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10152 MVT::i8)); 10153 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10154 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10155 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10156 return Res; 10157 } 10158 } 10159 } 10160 } 10161 10162 // Lower SHL with variable shift amount. 10163 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10164 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10165 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10166 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 10167 10168 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10169 10170 std::vector<Constant*> CV(4, CI); 10171 Constant *C = ConstantVector::get(CV); 10172 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10173 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10174 MachinePointerInfo::getConstantPool(), 10175 false, false, false, 16); 10176 10177 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10178 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10179 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10180 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10181 } 10182 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10183 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) && 10184 "Need SSE2 for pslli/pcmpeq."); 10185 10186 // a = a << 5; 10187 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10188 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10189 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 10190 10191 // Turn 'a' into a mask suitable for VSELECT 10192 SDValue VSelM = DAG.getConstant(0x80, VT); 10193 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10194 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10195 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10196 OpVSel, VSelM); 10197 10198 SDValue CM1 = DAG.getConstant(0x0f, VT); 10199 SDValue CM2 = DAG.getConstant(0x3f, VT); 10200 10201 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10202 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10203 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10204 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10205 DAG.getConstant(4, MVT::i32)); 10206 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10207 10208 // a += a 10209 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10210 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10211 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10212 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10213 OpVSel, VSelM); 10214 10215 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10216 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10217 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10218 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10219 DAG.getConstant(2, MVT::i32)); 10220 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10221 10222 // a += a 10223 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10224 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10225 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10226 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10227 OpVSel, VSelM); 10228 10229 // return VSELECT(r, r+r, a); 10230 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10231 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10232 return R; 10233 } 10234 10235 // Decompose 256-bit shifts into smaller 128-bit shifts. 10236 if (VT.getSizeInBits() == 256) { 10237 int NumElems = VT.getVectorNumElements(); 10238 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10239 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10240 10241 // Extract the two vectors 10242 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10243 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10244 DAG, dl); 10245 10246 // Recreate the shift amount vectors 10247 SDValue Amt1, Amt2; 10248 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10249 // Constant shift amount 10250 SmallVector<SDValue, 4> Amt1Csts; 10251 SmallVector<SDValue, 4> Amt2Csts; 10252 for (int i = 0; i < NumElems/2; ++i) 10253 Amt1Csts.push_back(Amt->getOperand(i)); 10254 for (int i = NumElems/2; i < NumElems; ++i) 10255 Amt2Csts.push_back(Amt->getOperand(i)); 10256 10257 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10258 &Amt1Csts[0], NumElems/2); 10259 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10260 &Amt2Csts[0], NumElems/2); 10261 } else { 10262 // Variable shift amount 10263 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10264 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10265 DAG, dl); 10266 } 10267 10268 // Issue new vector shifts for the smaller types 10269 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10270 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10271 10272 // Concatenate the result back 10273 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10274 } 10275 10276 return SDValue(); 10277} 10278 10279SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10280 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10281 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10282 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10283 // has only one use. 10284 SDNode *N = Op.getNode(); 10285 SDValue LHS = N->getOperand(0); 10286 SDValue RHS = N->getOperand(1); 10287 unsigned BaseOp = 0; 10288 unsigned Cond = 0; 10289 DebugLoc DL = Op.getDebugLoc(); 10290 switch (Op.getOpcode()) { 10291 default: llvm_unreachable("Unknown ovf instruction!"); 10292 case ISD::SADDO: 10293 // A subtract of one will be selected as a INC. Note that INC doesn't 10294 // set CF, so we can't do this for UADDO. 10295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10296 if (C->isOne()) { 10297 BaseOp = X86ISD::INC; 10298 Cond = X86::COND_O; 10299 break; 10300 } 10301 BaseOp = X86ISD::ADD; 10302 Cond = X86::COND_O; 10303 break; 10304 case ISD::UADDO: 10305 BaseOp = X86ISD::ADD; 10306 Cond = X86::COND_B; 10307 break; 10308 case ISD::SSUBO: 10309 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10310 // set CF, so we can't do this for USUBO. 10311 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10312 if (C->isOne()) { 10313 BaseOp = X86ISD::DEC; 10314 Cond = X86::COND_O; 10315 break; 10316 } 10317 BaseOp = X86ISD::SUB; 10318 Cond = X86::COND_O; 10319 break; 10320 case ISD::USUBO: 10321 BaseOp = X86ISD::SUB; 10322 Cond = X86::COND_B; 10323 break; 10324 case ISD::SMULO: 10325 BaseOp = X86ISD::SMUL; 10326 Cond = X86::COND_O; 10327 break; 10328 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10329 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10330 MVT::i32); 10331 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10332 10333 SDValue SetCC = 10334 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10335 DAG.getConstant(X86::COND_O, MVT::i32), 10336 SDValue(Sum.getNode(), 2)); 10337 10338 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10339 } 10340 } 10341 10342 // Also sets EFLAGS. 10343 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10344 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10345 10346 SDValue SetCC = 10347 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10348 DAG.getConstant(Cond, MVT::i32), 10349 SDValue(Sum.getNode(), 1)); 10350 10351 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10352} 10353 10354SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10355 SelectionDAG &DAG) const { 10356 DebugLoc dl = Op.getDebugLoc(); 10357 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10358 EVT VT = Op.getValueType(); 10359 10360 if (Subtarget->hasSSE2() && VT.isVector()) { 10361 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10362 ExtraVT.getScalarType().getSizeInBits(); 10363 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10364 10365 unsigned SHLIntrinsicsID = 0; 10366 unsigned SRAIntrinsicsID = 0; 10367 switch (VT.getSimpleVT().SimpleTy) { 10368 default: 10369 return SDValue(); 10370 case MVT::v4i32: 10371 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10372 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10373 break; 10374 case MVT::v8i16: 10375 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10376 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10377 break; 10378 case MVT::v8i32: 10379 case MVT::v16i16: 10380 if (!Subtarget->hasAVX()) 10381 return SDValue(); 10382 if (!Subtarget->hasAVX2()) { 10383 // needs to be split 10384 int NumElems = VT.getVectorNumElements(); 10385 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10386 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10387 10388 // Extract the LHS vectors 10389 SDValue LHS = Op.getOperand(0); 10390 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10391 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10392 10393 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10394 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10395 10396 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10397 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10398 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10399 ExtraNumElems/2); 10400 SDValue Extra = DAG.getValueType(ExtraVT); 10401 10402 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10403 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10404 10405 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10406 } 10407 if (VT == MVT::v8i32) { 10408 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d; 10409 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d; 10410 } else { 10411 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w; 10412 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w; 10413 } 10414 } 10415 10416 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10417 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10418 Op.getOperand(0), ShAmt); 10419 10420 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10421 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10422 Tmp1, ShAmt); 10423 } 10424 10425 return SDValue(); 10426} 10427 10428 10429SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10430 DebugLoc dl = Op.getDebugLoc(); 10431 10432 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10433 // There isn't any reason to disable it if the target processor supports it. 10434 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10435 SDValue Chain = Op.getOperand(0); 10436 SDValue Zero = DAG.getConstant(0, MVT::i32); 10437 SDValue Ops[] = { 10438 DAG.getRegister(X86::ESP, MVT::i32), // Base 10439 DAG.getTargetConstant(1, MVT::i8), // Scale 10440 DAG.getRegister(0, MVT::i32), // Index 10441 DAG.getTargetConstant(0, MVT::i32), // Disp 10442 DAG.getRegister(0, MVT::i32), // Segment. 10443 Zero, 10444 Chain 10445 }; 10446 SDNode *Res = 10447 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10448 array_lengthof(Ops)); 10449 return SDValue(Res, 0); 10450 } 10451 10452 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10453 if (!isDev) 10454 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10455 10456 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10457 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10458 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10459 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10460 10461 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10462 if (!Op1 && !Op2 && !Op3 && Op4) 10463 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10464 10465 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10466 if (Op1 && !Op2 && !Op3 && !Op4) 10467 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10468 10469 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10470 // (MFENCE)>; 10471 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10472} 10473 10474SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10475 SelectionDAG &DAG) const { 10476 DebugLoc dl = Op.getDebugLoc(); 10477 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10478 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10479 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10480 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10481 10482 // The only fence that needs an instruction is a sequentially-consistent 10483 // cross-thread fence. 10484 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10485 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10486 // no-sse2). There isn't any reason to disable it if the target processor 10487 // supports it. 10488 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10489 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10490 10491 SDValue Chain = Op.getOperand(0); 10492 SDValue Zero = DAG.getConstant(0, MVT::i32); 10493 SDValue Ops[] = { 10494 DAG.getRegister(X86::ESP, MVT::i32), // Base 10495 DAG.getTargetConstant(1, MVT::i8), // Scale 10496 DAG.getRegister(0, MVT::i32), // Index 10497 DAG.getTargetConstant(0, MVT::i32), // Disp 10498 DAG.getRegister(0, MVT::i32), // Segment. 10499 Zero, 10500 Chain 10501 }; 10502 SDNode *Res = 10503 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10504 array_lengthof(Ops)); 10505 return SDValue(Res, 0); 10506 } 10507 10508 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10509 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10510} 10511 10512 10513SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10514 EVT T = Op.getValueType(); 10515 DebugLoc DL = Op.getDebugLoc(); 10516 unsigned Reg = 0; 10517 unsigned size = 0; 10518 switch(T.getSimpleVT().SimpleTy) { 10519 default: 10520 assert(false && "Invalid value type!"); 10521 case MVT::i8: Reg = X86::AL; size = 1; break; 10522 case MVT::i16: Reg = X86::AX; size = 2; break; 10523 case MVT::i32: Reg = X86::EAX; size = 4; break; 10524 case MVT::i64: 10525 assert(Subtarget->is64Bit() && "Node not type legal!"); 10526 Reg = X86::RAX; size = 8; 10527 break; 10528 } 10529 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10530 Op.getOperand(2), SDValue()); 10531 SDValue Ops[] = { cpIn.getValue(0), 10532 Op.getOperand(1), 10533 Op.getOperand(3), 10534 DAG.getTargetConstant(size, MVT::i8), 10535 cpIn.getValue(1) }; 10536 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10537 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10538 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10539 Ops, 5, T, MMO); 10540 SDValue cpOut = 10541 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10542 return cpOut; 10543} 10544 10545SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10546 SelectionDAG &DAG) const { 10547 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10548 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10549 SDValue TheChain = Op.getOperand(0); 10550 DebugLoc dl = Op.getDebugLoc(); 10551 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10552 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10553 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10554 rax.getValue(2)); 10555 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10556 DAG.getConstant(32, MVT::i8)); 10557 SDValue Ops[] = { 10558 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10559 rdx.getValue(1) 10560 }; 10561 return DAG.getMergeValues(Ops, 2, dl); 10562} 10563 10564SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10565 SelectionDAG &DAG) const { 10566 EVT SrcVT = Op.getOperand(0).getValueType(); 10567 EVT DstVT = Op.getValueType(); 10568 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10569 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10570 assert((DstVT == MVT::i64 || 10571 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10572 "Unexpected custom BITCAST"); 10573 // i64 <=> MMX conversions are Legal. 10574 if (SrcVT==MVT::i64 && DstVT.isVector()) 10575 return Op; 10576 if (DstVT==MVT::i64 && SrcVT.isVector()) 10577 return Op; 10578 // MMX <=> MMX conversions are Legal. 10579 if (SrcVT.isVector() && DstVT.isVector()) 10580 return Op; 10581 // All other conversions need to be expanded. 10582 return SDValue(); 10583} 10584 10585SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10586 SDNode *Node = Op.getNode(); 10587 DebugLoc dl = Node->getDebugLoc(); 10588 EVT T = Node->getValueType(0); 10589 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10590 DAG.getConstant(0, T), Node->getOperand(2)); 10591 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10592 cast<AtomicSDNode>(Node)->getMemoryVT(), 10593 Node->getOperand(0), 10594 Node->getOperand(1), negOp, 10595 cast<AtomicSDNode>(Node)->getSrcValue(), 10596 cast<AtomicSDNode>(Node)->getAlignment(), 10597 cast<AtomicSDNode>(Node)->getOrdering(), 10598 cast<AtomicSDNode>(Node)->getSynchScope()); 10599} 10600 10601static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10602 SDNode *Node = Op.getNode(); 10603 DebugLoc dl = Node->getDebugLoc(); 10604 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10605 10606 // Convert seq_cst store -> xchg 10607 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10608 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10609 // (The only way to get a 16-byte store is cmpxchg16b) 10610 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10611 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10612 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10613 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10614 cast<AtomicSDNode>(Node)->getMemoryVT(), 10615 Node->getOperand(0), 10616 Node->getOperand(1), Node->getOperand(2), 10617 cast<AtomicSDNode>(Node)->getMemOperand(), 10618 cast<AtomicSDNode>(Node)->getOrdering(), 10619 cast<AtomicSDNode>(Node)->getSynchScope()); 10620 return Swap.getValue(1); 10621 } 10622 // Other atomic stores have a simple pattern. 10623 return Op; 10624} 10625 10626static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10627 EVT VT = Op.getNode()->getValueType(0); 10628 10629 // Let legalize expand this if it isn't a legal type yet. 10630 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10631 return SDValue(); 10632 10633 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10634 10635 unsigned Opc; 10636 bool ExtraOp = false; 10637 switch (Op.getOpcode()) { 10638 default: assert(0 && "Invalid code"); 10639 case ISD::ADDC: Opc = X86ISD::ADD; break; 10640 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10641 case ISD::SUBC: Opc = X86ISD::SUB; break; 10642 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10643 } 10644 10645 if (!ExtraOp) 10646 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10647 Op.getOperand(1)); 10648 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10649 Op.getOperand(1), Op.getOperand(2)); 10650} 10651 10652/// LowerOperation - Provide custom lowering hooks for some operations. 10653/// 10654SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10655 switch (Op.getOpcode()) { 10656 default: llvm_unreachable("Should not custom lower this!"); 10657 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10658 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10659 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10660 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10661 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10662 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10663 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10664 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10665 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10666 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10667 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10668 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10669 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10670 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10671 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10672 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10673 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10674 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10675 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10676 case ISD::SHL_PARTS: 10677 case ISD::SRA_PARTS: 10678 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10679 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10680 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10681 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10682 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10683 case ISD::FABS: return LowerFABS(Op, DAG); 10684 case ISD::FNEG: return LowerFNEG(Op, DAG); 10685 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10686 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10687 case ISD::SETCC: return LowerSETCC(Op, DAG); 10688 case ISD::SELECT: return LowerSELECT(Op, DAG); 10689 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10690 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10691 case ISD::VASTART: return LowerVASTART(Op, DAG); 10692 case ISD::VAARG: return LowerVAARG(Op, DAG); 10693 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10694 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10695 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10696 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10697 case ISD::FRAME_TO_ARGS_OFFSET: 10698 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10699 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10700 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10701 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10702 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10703 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10704 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10705 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10706 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10707 case ISD::MUL: return LowerMUL(Op, DAG); 10708 case ISD::SRA: 10709 case ISD::SRL: 10710 case ISD::SHL: return LowerShift(Op, DAG); 10711 case ISD::SADDO: 10712 case ISD::UADDO: 10713 case ISD::SSUBO: 10714 case ISD::USUBO: 10715 case ISD::SMULO: 10716 case ISD::UMULO: return LowerXALUO(Op, DAG); 10717 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10718 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10719 case ISD::ADDC: 10720 case ISD::ADDE: 10721 case ISD::SUBC: 10722 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10723 case ISD::ADD: return LowerADD(Op, DAG); 10724 case ISD::SUB: return LowerSUB(Op, DAG); 10725 } 10726} 10727 10728static void ReplaceATOMIC_LOAD(SDNode *Node, 10729 SmallVectorImpl<SDValue> &Results, 10730 SelectionDAG &DAG) { 10731 DebugLoc dl = Node->getDebugLoc(); 10732 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10733 10734 // Convert wide load -> cmpxchg8b/cmpxchg16b 10735 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10736 // (The only way to get a 16-byte load is cmpxchg16b) 10737 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10738 SDValue Zero = DAG.getConstant(0, VT); 10739 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10740 Node->getOperand(0), 10741 Node->getOperand(1), Zero, Zero, 10742 cast<AtomicSDNode>(Node)->getMemOperand(), 10743 cast<AtomicSDNode>(Node)->getOrdering(), 10744 cast<AtomicSDNode>(Node)->getSynchScope()); 10745 Results.push_back(Swap.getValue(0)); 10746 Results.push_back(Swap.getValue(1)); 10747} 10748 10749void X86TargetLowering:: 10750ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10751 SelectionDAG &DAG, unsigned NewOp) const { 10752 DebugLoc dl = Node->getDebugLoc(); 10753 assert (Node->getValueType(0) == MVT::i64 && 10754 "Only know how to expand i64 atomics"); 10755 10756 SDValue Chain = Node->getOperand(0); 10757 SDValue In1 = Node->getOperand(1); 10758 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10759 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10760 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10761 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10762 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10763 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10764 SDValue Result = 10765 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10766 cast<MemSDNode>(Node)->getMemOperand()); 10767 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10768 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10769 Results.push_back(Result.getValue(2)); 10770} 10771 10772/// ReplaceNodeResults - Replace a node with an illegal result type 10773/// with a new node built out of custom code. 10774void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10775 SmallVectorImpl<SDValue>&Results, 10776 SelectionDAG &DAG) const { 10777 DebugLoc dl = N->getDebugLoc(); 10778 switch (N->getOpcode()) { 10779 default: 10780 assert(false && "Do not know how to custom type legalize this operation!"); 10781 return; 10782 case ISD::SIGN_EXTEND_INREG: 10783 case ISD::ADDC: 10784 case ISD::ADDE: 10785 case ISD::SUBC: 10786 case ISD::SUBE: 10787 // We don't want to expand or promote these. 10788 return; 10789 case ISD::FP_TO_SINT: { 10790 std::pair<SDValue,SDValue> Vals = 10791 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10792 SDValue FIST = Vals.first, StackSlot = Vals.second; 10793 if (FIST.getNode() != 0) { 10794 EVT VT = N->getValueType(0); 10795 // Return a load from the stack slot. 10796 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10797 MachinePointerInfo(), 10798 false, false, false, 0)); 10799 } 10800 return; 10801 } 10802 case ISD::READCYCLECOUNTER: { 10803 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10804 SDValue TheChain = N->getOperand(0); 10805 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10806 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10807 rd.getValue(1)); 10808 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10809 eax.getValue(2)); 10810 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10811 SDValue Ops[] = { eax, edx }; 10812 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10813 Results.push_back(edx.getValue(1)); 10814 return; 10815 } 10816 case ISD::ATOMIC_CMP_SWAP: { 10817 EVT T = N->getValueType(0); 10818 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10819 bool Regs64bit = T == MVT::i128; 10820 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10821 SDValue cpInL, cpInH; 10822 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10823 DAG.getConstant(0, HalfT)); 10824 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10825 DAG.getConstant(1, HalfT)); 10826 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10827 Regs64bit ? X86::RAX : X86::EAX, 10828 cpInL, SDValue()); 10829 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10830 Regs64bit ? X86::RDX : X86::EDX, 10831 cpInH, cpInL.getValue(1)); 10832 SDValue swapInL, swapInH; 10833 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10834 DAG.getConstant(0, HalfT)); 10835 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10836 DAG.getConstant(1, HalfT)); 10837 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10838 Regs64bit ? X86::RBX : X86::EBX, 10839 swapInL, cpInH.getValue(1)); 10840 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10841 Regs64bit ? X86::RCX : X86::ECX, 10842 swapInH, swapInL.getValue(1)); 10843 SDValue Ops[] = { swapInH.getValue(0), 10844 N->getOperand(1), 10845 swapInH.getValue(1) }; 10846 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10847 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10848 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10849 X86ISD::LCMPXCHG8_DAG; 10850 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10851 Ops, 3, T, MMO); 10852 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10853 Regs64bit ? X86::RAX : X86::EAX, 10854 HalfT, Result.getValue(1)); 10855 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10856 Regs64bit ? X86::RDX : X86::EDX, 10857 HalfT, cpOutL.getValue(2)); 10858 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10859 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10860 Results.push_back(cpOutH.getValue(1)); 10861 return; 10862 } 10863 case ISD::ATOMIC_LOAD_ADD: 10864 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10865 return; 10866 case ISD::ATOMIC_LOAD_AND: 10867 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10868 return; 10869 case ISD::ATOMIC_LOAD_NAND: 10870 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10871 return; 10872 case ISD::ATOMIC_LOAD_OR: 10873 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10874 return; 10875 case ISD::ATOMIC_LOAD_SUB: 10876 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10877 return; 10878 case ISD::ATOMIC_LOAD_XOR: 10879 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10880 return; 10881 case ISD::ATOMIC_SWAP: 10882 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10883 return; 10884 case ISD::ATOMIC_LOAD: 10885 ReplaceATOMIC_LOAD(N, Results, DAG); 10886 } 10887} 10888 10889const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10890 switch (Opcode) { 10891 default: return NULL; 10892 case X86ISD::BSF: return "X86ISD::BSF"; 10893 case X86ISD::BSR: return "X86ISD::BSR"; 10894 case X86ISD::SHLD: return "X86ISD::SHLD"; 10895 case X86ISD::SHRD: return "X86ISD::SHRD"; 10896 case X86ISD::FAND: return "X86ISD::FAND"; 10897 case X86ISD::FOR: return "X86ISD::FOR"; 10898 case X86ISD::FXOR: return "X86ISD::FXOR"; 10899 case X86ISD::FSRL: return "X86ISD::FSRL"; 10900 case X86ISD::FILD: return "X86ISD::FILD"; 10901 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10902 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10903 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10904 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10905 case X86ISD::FLD: return "X86ISD::FLD"; 10906 case X86ISD::FST: return "X86ISD::FST"; 10907 case X86ISD::CALL: return "X86ISD::CALL"; 10908 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10909 case X86ISD::BT: return "X86ISD::BT"; 10910 case X86ISD::CMP: return "X86ISD::CMP"; 10911 case X86ISD::COMI: return "X86ISD::COMI"; 10912 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10913 case X86ISD::SETCC: return "X86ISD::SETCC"; 10914 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10915 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10916 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10917 case X86ISD::CMOV: return "X86ISD::CMOV"; 10918 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10919 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10920 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10921 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10922 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10923 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10924 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10925 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10926 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10927 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10928 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10929 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10930 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10931 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10932 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10933 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10934 case X86ISD::HADD: return "X86ISD::HADD"; 10935 case X86ISD::HSUB: return "X86ISD::HSUB"; 10936 case X86ISD::FHADD: return "X86ISD::FHADD"; 10937 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10938 case X86ISD::FMAX: return "X86ISD::FMAX"; 10939 case X86ISD::FMIN: return "X86ISD::FMIN"; 10940 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10941 case X86ISD::FRCP: return "X86ISD::FRCP"; 10942 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10943 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10944 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10945 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10946 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10947 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10948 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10949 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10950 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10951 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10952 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10953 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10954 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10955 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10956 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10957 case X86ISD::VSHL: return "X86ISD::VSHL"; 10958 case X86ISD::VSRL: return "X86ISD::VSRL"; 10959 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10960 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10961 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10962 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10963 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10964 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10965 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10966 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10967 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10968 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10969 case X86ISD::ADD: return "X86ISD::ADD"; 10970 case X86ISD::SUB: return "X86ISD::SUB"; 10971 case X86ISD::ADC: return "X86ISD::ADC"; 10972 case X86ISD::SBB: return "X86ISD::SBB"; 10973 case X86ISD::SMUL: return "X86ISD::SMUL"; 10974 case X86ISD::UMUL: return "X86ISD::UMUL"; 10975 case X86ISD::INC: return "X86ISD::INC"; 10976 case X86ISD::DEC: return "X86ISD::DEC"; 10977 case X86ISD::OR: return "X86ISD::OR"; 10978 case X86ISD::XOR: return "X86ISD::XOR"; 10979 case X86ISD::AND: return "X86ISD::AND"; 10980 case X86ISD::ANDN: return "X86ISD::ANDN"; 10981 case X86ISD::BLSI: return "X86ISD::BLSI"; 10982 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 10983 case X86ISD::BLSR: return "X86ISD::BLSR"; 10984 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10985 case X86ISD::PTEST: return "X86ISD::PTEST"; 10986 case X86ISD::TESTP: return "X86ISD::TESTP"; 10987 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10988 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10989 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10990 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10991 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10992 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10993 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 10994 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10995 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10996 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10997 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10998 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10999 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11000 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11001 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11002 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 11003 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 11004 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11005 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11006 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11007 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11008 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11009 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11010 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11011 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11012 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11013 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11014 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11015 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11016 } 11017} 11018 11019// isLegalAddressingMode - Return true if the addressing mode represented 11020// by AM is legal for this target, for a load/store of the specified type. 11021bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11022 Type *Ty) const { 11023 // X86 supports extremely general addressing modes. 11024 CodeModel::Model M = getTargetMachine().getCodeModel(); 11025 Reloc::Model R = getTargetMachine().getRelocationModel(); 11026 11027 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11028 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11029 return false; 11030 11031 if (AM.BaseGV) { 11032 unsigned GVFlags = 11033 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11034 11035 // If a reference to this global requires an extra load, we can't fold it. 11036 if (isGlobalStubReference(GVFlags)) 11037 return false; 11038 11039 // If BaseGV requires a register for the PIC base, we cannot also have a 11040 // BaseReg specified. 11041 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11042 return false; 11043 11044 // If lower 4G is not available, then we must use rip-relative addressing. 11045 if ((M != CodeModel::Small || R != Reloc::Static) && 11046 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11047 return false; 11048 } 11049 11050 switch (AM.Scale) { 11051 case 0: 11052 case 1: 11053 case 2: 11054 case 4: 11055 case 8: 11056 // These scales always work. 11057 break; 11058 case 3: 11059 case 5: 11060 case 9: 11061 // These scales are formed with basereg+scalereg. Only accept if there is 11062 // no basereg yet. 11063 if (AM.HasBaseReg) 11064 return false; 11065 break; 11066 default: // Other stuff never works. 11067 return false; 11068 } 11069 11070 return true; 11071} 11072 11073 11074bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11075 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11076 return false; 11077 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11078 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11079 if (NumBits1 <= NumBits2) 11080 return false; 11081 return true; 11082} 11083 11084bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11085 if (!VT1.isInteger() || !VT2.isInteger()) 11086 return false; 11087 unsigned NumBits1 = VT1.getSizeInBits(); 11088 unsigned NumBits2 = VT2.getSizeInBits(); 11089 if (NumBits1 <= NumBits2) 11090 return false; 11091 return true; 11092} 11093 11094bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11095 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11096 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11097} 11098 11099bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11100 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11101 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11102} 11103 11104bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11105 // i16 instructions are longer (0x66 prefix) and potentially slower. 11106 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11107} 11108 11109/// isShuffleMaskLegal - Targets can use this to indicate that they only 11110/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11111/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11112/// are assumed to be legal. 11113bool 11114X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11115 EVT VT) const { 11116 // Very little shuffling can be done for 64-bit vectors right now. 11117 if (VT.getSizeInBits() == 64) 11118 return false; 11119 11120 // FIXME: pshufb, blends, shifts. 11121 return (VT.getVectorNumElements() == 2 || 11122 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11123 isMOVLMask(M, VT) || 11124 isSHUFPMask(M, VT) || 11125 isPSHUFDMask(M, VT) || 11126 isPSHUFHWMask(M, VT) || 11127 isPSHUFLWMask(M, VT) || 11128 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 11129 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11130 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11131 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11132 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11133} 11134 11135bool 11136X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11137 EVT VT) const { 11138 unsigned NumElts = VT.getVectorNumElements(); 11139 // FIXME: This collection of masks seems suspect. 11140 if (NumElts == 2) 11141 return true; 11142 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11143 return (isMOVLMask(Mask, VT) || 11144 isCommutedMOVLMask(Mask, VT, true) || 11145 isSHUFPMask(Mask, VT) || 11146 isSHUFPMask(Mask, VT, /* Commuted */ true)); 11147 } 11148 return false; 11149} 11150 11151//===----------------------------------------------------------------------===// 11152// X86 Scheduler Hooks 11153//===----------------------------------------------------------------------===// 11154 11155// private utility function 11156MachineBasicBlock * 11157X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11158 MachineBasicBlock *MBB, 11159 unsigned regOpc, 11160 unsigned immOpc, 11161 unsigned LoadOpc, 11162 unsigned CXchgOpc, 11163 unsigned notOpc, 11164 unsigned EAXreg, 11165 TargetRegisterClass *RC, 11166 bool invSrc) const { 11167 // For the atomic bitwise operator, we generate 11168 // thisMBB: 11169 // newMBB: 11170 // ld t1 = [bitinstr.addr] 11171 // op t2 = t1, [bitinstr.val] 11172 // mov EAX = t1 11173 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11174 // bz newMBB 11175 // fallthrough -->nextMBB 11176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11177 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11178 MachineFunction::iterator MBBIter = MBB; 11179 ++MBBIter; 11180 11181 /// First build the CFG 11182 MachineFunction *F = MBB->getParent(); 11183 MachineBasicBlock *thisMBB = MBB; 11184 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11185 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11186 F->insert(MBBIter, newMBB); 11187 F->insert(MBBIter, nextMBB); 11188 11189 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11190 nextMBB->splice(nextMBB->begin(), thisMBB, 11191 llvm::next(MachineBasicBlock::iterator(bInstr)), 11192 thisMBB->end()); 11193 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11194 11195 // Update thisMBB to fall through to newMBB 11196 thisMBB->addSuccessor(newMBB); 11197 11198 // newMBB jumps to itself and fall through to nextMBB 11199 newMBB->addSuccessor(nextMBB); 11200 newMBB->addSuccessor(newMBB); 11201 11202 // Insert instructions into newMBB based on incoming instruction 11203 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11204 "unexpected number of operands"); 11205 DebugLoc dl = bInstr->getDebugLoc(); 11206 MachineOperand& destOper = bInstr->getOperand(0); 11207 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11208 int numArgs = bInstr->getNumOperands() - 1; 11209 for (int i=0; i < numArgs; ++i) 11210 argOpers[i] = &bInstr->getOperand(i+1); 11211 11212 // x86 address has 4 operands: base, index, scale, and displacement 11213 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11214 int valArgIndx = lastAddrIndx + 1; 11215 11216 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11217 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11218 for (int i=0; i <= lastAddrIndx; ++i) 11219 (*MIB).addOperand(*argOpers[i]); 11220 11221 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11222 if (invSrc) { 11223 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11224 } 11225 else 11226 tt = t1; 11227 11228 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11229 assert((argOpers[valArgIndx]->isReg() || 11230 argOpers[valArgIndx]->isImm()) && 11231 "invalid operand"); 11232 if (argOpers[valArgIndx]->isReg()) 11233 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11234 else 11235 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11236 MIB.addReg(tt); 11237 (*MIB).addOperand(*argOpers[valArgIndx]); 11238 11239 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11240 MIB.addReg(t1); 11241 11242 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11243 for (int i=0; i <= lastAddrIndx; ++i) 11244 (*MIB).addOperand(*argOpers[i]); 11245 MIB.addReg(t2); 11246 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11247 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11248 bInstr->memoperands_end()); 11249 11250 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11251 MIB.addReg(EAXreg); 11252 11253 // insert branch 11254 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11255 11256 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11257 return nextMBB; 11258} 11259 11260// private utility function: 64 bit atomics on 32 bit host. 11261MachineBasicBlock * 11262X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11263 MachineBasicBlock *MBB, 11264 unsigned regOpcL, 11265 unsigned regOpcH, 11266 unsigned immOpcL, 11267 unsigned immOpcH, 11268 bool invSrc) const { 11269 // For the atomic bitwise operator, we generate 11270 // thisMBB (instructions are in pairs, except cmpxchg8b) 11271 // ld t1,t2 = [bitinstr.addr] 11272 // newMBB: 11273 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11274 // op t5, t6 <- out1, out2, [bitinstr.val] 11275 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11276 // mov ECX, EBX <- t5, t6 11277 // mov EAX, EDX <- t1, t2 11278 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11279 // mov t3, t4 <- EAX, EDX 11280 // bz newMBB 11281 // result in out1, out2 11282 // fallthrough -->nextMBB 11283 11284 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11285 const unsigned LoadOpc = X86::MOV32rm; 11286 const unsigned NotOpc = X86::NOT32r; 11287 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11288 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11289 MachineFunction::iterator MBBIter = MBB; 11290 ++MBBIter; 11291 11292 /// First build the CFG 11293 MachineFunction *F = MBB->getParent(); 11294 MachineBasicBlock *thisMBB = MBB; 11295 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11296 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11297 F->insert(MBBIter, newMBB); 11298 F->insert(MBBIter, nextMBB); 11299 11300 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11301 nextMBB->splice(nextMBB->begin(), thisMBB, 11302 llvm::next(MachineBasicBlock::iterator(bInstr)), 11303 thisMBB->end()); 11304 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11305 11306 // Update thisMBB to fall through to newMBB 11307 thisMBB->addSuccessor(newMBB); 11308 11309 // newMBB jumps to itself and fall through to nextMBB 11310 newMBB->addSuccessor(nextMBB); 11311 newMBB->addSuccessor(newMBB); 11312 11313 DebugLoc dl = bInstr->getDebugLoc(); 11314 // Insert instructions into newMBB based on incoming instruction 11315 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11316 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11317 "unexpected number of operands"); 11318 MachineOperand& dest1Oper = bInstr->getOperand(0); 11319 MachineOperand& dest2Oper = bInstr->getOperand(1); 11320 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11321 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11322 argOpers[i] = &bInstr->getOperand(i+2); 11323 11324 // We use some of the operands multiple times, so conservatively just 11325 // clear any kill flags that might be present. 11326 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11327 argOpers[i]->setIsKill(false); 11328 } 11329 11330 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11331 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11332 11333 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11334 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11335 for (int i=0; i <= lastAddrIndx; ++i) 11336 (*MIB).addOperand(*argOpers[i]); 11337 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11338 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11339 // add 4 to displacement. 11340 for (int i=0; i <= lastAddrIndx-2; ++i) 11341 (*MIB).addOperand(*argOpers[i]); 11342 MachineOperand newOp3 = *(argOpers[3]); 11343 if (newOp3.isImm()) 11344 newOp3.setImm(newOp3.getImm()+4); 11345 else 11346 newOp3.setOffset(newOp3.getOffset()+4); 11347 (*MIB).addOperand(newOp3); 11348 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11349 11350 // t3/4 are defined later, at the bottom of the loop 11351 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11352 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11353 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11354 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11355 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11356 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11357 11358 // The subsequent operations should be using the destination registers of 11359 //the PHI instructions. 11360 if (invSrc) { 11361 t1 = F->getRegInfo().createVirtualRegister(RC); 11362 t2 = F->getRegInfo().createVirtualRegister(RC); 11363 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11364 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11365 } else { 11366 t1 = dest1Oper.getReg(); 11367 t2 = dest2Oper.getReg(); 11368 } 11369 11370 int valArgIndx = lastAddrIndx + 1; 11371 assert((argOpers[valArgIndx]->isReg() || 11372 argOpers[valArgIndx]->isImm()) && 11373 "invalid operand"); 11374 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11375 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11376 if (argOpers[valArgIndx]->isReg()) 11377 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11378 else 11379 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11380 if (regOpcL != X86::MOV32rr) 11381 MIB.addReg(t1); 11382 (*MIB).addOperand(*argOpers[valArgIndx]); 11383 assert(argOpers[valArgIndx + 1]->isReg() == 11384 argOpers[valArgIndx]->isReg()); 11385 assert(argOpers[valArgIndx + 1]->isImm() == 11386 argOpers[valArgIndx]->isImm()); 11387 if (argOpers[valArgIndx + 1]->isReg()) 11388 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11389 else 11390 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11391 if (regOpcH != X86::MOV32rr) 11392 MIB.addReg(t2); 11393 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11394 11395 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11396 MIB.addReg(t1); 11397 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11398 MIB.addReg(t2); 11399 11400 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11401 MIB.addReg(t5); 11402 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11403 MIB.addReg(t6); 11404 11405 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11406 for (int i=0; i <= lastAddrIndx; ++i) 11407 (*MIB).addOperand(*argOpers[i]); 11408 11409 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11410 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11411 bInstr->memoperands_end()); 11412 11413 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11414 MIB.addReg(X86::EAX); 11415 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11416 MIB.addReg(X86::EDX); 11417 11418 // insert branch 11419 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11420 11421 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11422 return nextMBB; 11423} 11424 11425// private utility function 11426MachineBasicBlock * 11427X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11428 MachineBasicBlock *MBB, 11429 unsigned cmovOpc) const { 11430 // For the atomic min/max operator, we generate 11431 // thisMBB: 11432 // newMBB: 11433 // ld t1 = [min/max.addr] 11434 // mov t2 = [min/max.val] 11435 // cmp t1, t2 11436 // cmov[cond] t2 = t1 11437 // mov EAX = t1 11438 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11439 // bz newMBB 11440 // fallthrough -->nextMBB 11441 // 11442 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11443 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11444 MachineFunction::iterator MBBIter = MBB; 11445 ++MBBIter; 11446 11447 /// First build the CFG 11448 MachineFunction *F = MBB->getParent(); 11449 MachineBasicBlock *thisMBB = MBB; 11450 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11451 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11452 F->insert(MBBIter, newMBB); 11453 F->insert(MBBIter, nextMBB); 11454 11455 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11456 nextMBB->splice(nextMBB->begin(), thisMBB, 11457 llvm::next(MachineBasicBlock::iterator(mInstr)), 11458 thisMBB->end()); 11459 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11460 11461 // Update thisMBB to fall through to newMBB 11462 thisMBB->addSuccessor(newMBB); 11463 11464 // newMBB jumps to newMBB and fall through to nextMBB 11465 newMBB->addSuccessor(nextMBB); 11466 newMBB->addSuccessor(newMBB); 11467 11468 DebugLoc dl = mInstr->getDebugLoc(); 11469 // Insert instructions into newMBB based on incoming instruction 11470 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11471 "unexpected number of operands"); 11472 MachineOperand& destOper = mInstr->getOperand(0); 11473 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11474 int numArgs = mInstr->getNumOperands() - 1; 11475 for (int i=0; i < numArgs; ++i) 11476 argOpers[i] = &mInstr->getOperand(i+1); 11477 11478 // x86 address has 4 operands: base, index, scale, and displacement 11479 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11480 int valArgIndx = lastAddrIndx + 1; 11481 11482 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11483 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11484 for (int i=0; i <= lastAddrIndx; ++i) 11485 (*MIB).addOperand(*argOpers[i]); 11486 11487 // We only support register and immediate values 11488 assert((argOpers[valArgIndx]->isReg() || 11489 argOpers[valArgIndx]->isImm()) && 11490 "invalid operand"); 11491 11492 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11493 if (argOpers[valArgIndx]->isReg()) 11494 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11495 else 11496 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11497 (*MIB).addOperand(*argOpers[valArgIndx]); 11498 11499 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11500 MIB.addReg(t1); 11501 11502 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11503 MIB.addReg(t1); 11504 MIB.addReg(t2); 11505 11506 // Generate movc 11507 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11508 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11509 MIB.addReg(t2); 11510 MIB.addReg(t1); 11511 11512 // Cmp and exchange if none has modified the memory location 11513 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11514 for (int i=0; i <= lastAddrIndx; ++i) 11515 (*MIB).addOperand(*argOpers[i]); 11516 MIB.addReg(t3); 11517 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11518 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11519 mInstr->memoperands_end()); 11520 11521 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11522 MIB.addReg(X86::EAX); 11523 11524 // insert branch 11525 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11526 11527 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11528 return nextMBB; 11529} 11530 11531// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11532// or XMM0_V32I8 in AVX all of this code can be replaced with that 11533// in the .td file. 11534MachineBasicBlock * 11535X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11536 unsigned numArgs, bool memArg) const { 11537 assert(Subtarget->hasSSE42() && 11538 "Target must have SSE4.2 or AVX features enabled"); 11539 11540 DebugLoc dl = MI->getDebugLoc(); 11541 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11542 unsigned Opc; 11543 if (!Subtarget->hasAVX()) { 11544 if (memArg) 11545 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11546 else 11547 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11548 } else { 11549 if (memArg) 11550 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11551 else 11552 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11553 } 11554 11555 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11556 for (unsigned i = 0; i < numArgs; ++i) { 11557 MachineOperand &Op = MI->getOperand(i+1); 11558 if (!(Op.isReg() && Op.isImplicit())) 11559 MIB.addOperand(Op); 11560 } 11561 BuildMI(*BB, MI, dl, 11562 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11563 MI->getOperand(0).getReg()) 11564 .addReg(X86::XMM0); 11565 11566 MI->eraseFromParent(); 11567 return BB; 11568} 11569 11570MachineBasicBlock * 11571X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11572 DebugLoc dl = MI->getDebugLoc(); 11573 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11574 11575 // Address into RAX/EAX, other two args into ECX, EDX. 11576 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11577 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11578 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11579 for (int i = 0; i < X86::AddrNumOperands; ++i) 11580 MIB.addOperand(MI->getOperand(i)); 11581 11582 unsigned ValOps = X86::AddrNumOperands; 11583 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11584 .addReg(MI->getOperand(ValOps).getReg()); 11585 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11586 .addReg(MI->getOperand(ValOps+1).getReg()); 11587 11588 // The instruction doesn't actually take any operands though. 11589 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11590 11591 MI->eraseFromParent(); // The pseudo is gone now. 11592 return BB; 11593} 11594 11595MachineBasicBlock * 11596X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11597 DebugLoc dl = MI->getDebugLoc(); 11598 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11599 11600 // First arg in ECX, the second in EAX. 11601 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11602 .addReg(MI->getOperand(0).getReg()); 11603 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11604 .addReg(MI->getOperand(1).getReg()); 11605 11606 // The instruction doesn't actually take any operands though. 11607 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11608 11609 MI->eraseFromParent(); // The pseudo is gone now. 11610 return BB; 11611} 11612 11613MachineBasicBlock * 11614X86TargetLowering::EmitVAARG64WithCustomInserter( 11615 MachineInstr *MI, 11616 MachineBasicBlock *MBB) const { 11617 // Emit va_arg instruction on X86-64. 11618 11619 // Operands to this pseudo-instruction: 11620 // 0 ) Output : destination address (reg) 11621 // 1-5) Input : va_list address (addr, i64mem) 11622 // 6 ) ArgSize : Size (in bytes) of vararg type 11623 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11624 // 8 ) Align : Alignment of type 11625 // 9 ) EFLAGS (implicit-def) 11626 11627 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11628 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11629 11630 unsigned DestReg = MI->getOperand(0).getReg(); 11631 MachineOperand &Base = MI->getOperand(1); 11632 MachineOperand &Scale = MI->getOperand(2); 11633 MachineOperand &Index = MI->getOperand(3); 11634 MachineOperand &Disp = MI->getOperand(4); 11635 MachineOperand &Segment = MI->getOperand(5); 11636 unsigned ArgSize = MI->getOperand(6).getImm(); 11637 unsigned ArgMode = MI->getOperand(7).getImm(); 11638 unsigned Align = MI->getOperand(8).getImm(); 11639 11640 // Memory Reference 11641 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11642 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11643 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11644 11645 // Machine Information 11646 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11647 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11648 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11649 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11650 DebugLoc DL = MI->getDebugLoc(); 11651 11652 // struct va_list { 11653 // i32 gp_offset 11654 // i32 fp_offset 11655 // i64 overflow_area (address) 11656 // i64 reg_save_area (address) 11657 // } 11658 // sizeof(va_list) = 24 11659 // alignment(va_list) = 8 11660 11661 unsigned TotalNumIntRegs = 6; 11662 unsigned TotalNumXMMRegs = 8; 11663 bool UseGPOffset = (ArgMode == 1); 11664 bool UseFPOffset = (ArgMode == 2); 11665 unsigned MaxOffset = TotalNumIntRegs * 8 + 11666 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11667 11668 /* Align ArgSize to a multiple of 8 */ 11669 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11670 bool NeedsAlign = (Align > 8); 11671 11672 MachineBasicBlock *thisMBB = MBB; 11673 MachineBasicBlock *overflowMBB; 11674 MachineBasicBlock *offsetMBB; 11675 MachineBasicBlock *endMBB; 11676 11677 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11678 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11679 unsigned OffsetReg = 0; 11680 11681 if (!UseGPOffset && !UseFPOffset) { 11682 // If we only pull from the overflow region, we don't create a branch. 11683 // We don't need to alter control flow. 11684 OffsetDestReg = 0; // unused 11685 OverflowDestReg = DestReg; 11686 11687 offsetMBB = NULL; 11688 overflowMBB = thisMBB; 11689 endMBB = thisMBB; 11690 } else { 11691 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11692 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11693 // If not, pull from overflow_area. (branch to overflowMBB) 11694 // 11695 // thisMBB 11696 // | . 11697 // | . 11698 // offsetMBB overflowMBB 11699 // | . 11700 // | . 11701 // endMBB 11702 11703 // Registers for the PHI in endMBB 11704 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11705 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11706 11707 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11708 MachineFunction *MF = MBB->getParent(); 11709 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11710 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11711 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11712 11713 MachineFunction::iterator MBBIter = MBB; 11714 ++MBBIter; 11715 11716 // Insert the new basic blocks 11717 MF->insert(MBBIter, offsetMBB); 11718 MF->insert(MBBIter, overflowMBB); 11719 MF->insert(MBBIter, endMBB); 11720 11721 // Transfer the remainder of MBB and its successor edges to endMBB. 11722 endMBB->splice(endMBB->begin(), thisMBB, 11723 llvm::next(MachineBasicBlock::iterator(MI)), 11724 thisMBB->end()); 11725 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11726 11727 // Make offsetMBB and overflowMBB successors of thisMBB 11728 thisMBB->addSuccessor(offsetMBB); 11729 thisMBB->addSuccessor(overflowMBB); 11730 11731 // endMBB is a successor of both offsetMBB and overflowMBB 11732 offsetMBB->addSuccessor(endMBB); 11733 overflowMBB->addSuccessor(endMBB); 11734 11735 // Load the offset value into a register 11736 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11737 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11738 .addOperand(Base) 11739 .addOperand(Scale) 11740 .addOperand(Index) 11741 .addDisp(Disp, UseFPOffset ? 4 : 0) 11742 .addOperand(Segment) 11743 .setMemRefs(MMOBegin, MMOEnd); 11744 11745 // Check if there is enough room left to pull this argument. 11746 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11747 .addReg(OffsetReg) 11748 .addImm(MaxOffset + 8 - ArgSizeA8); 11749 11750 // Branch to "overflowMBB" if offset >= max 11751 // Fall through to "offsetMBB" otherwise 11752 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11753 .addMBB(overflowMBB); 11754 } 11755 11756 // In offsetMBB, emit code to use the reg_save_area. 11757 if (offsetMBB) { 11758 assert(OffsetReg != 0); 11759 11760 // Read the reg_save_area address. 11761 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11762 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11763 .addOperand(Base) 11764 .addOperand(Scale) 11765 .addOperand(Index) 11766 .addDisp(Disp, 16) 11767 .addOperand(Segment) 11768 .setMemRefs(MMOBegin, MMOEnd); 11769 11770 // Zero-extend the offset 11771 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11772 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11773 .addImm(0) 11774 .addReg(OffsetReg) 11775 .addImm(X86::sub_32bit); 11776 11777 // Add the offset to the reg_save_area to get the final address. 11778 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11779 .addReg(OffsetReg64) 11780 .addReg(RegSaveReg); 11781 11782 // Compute the offset for the next argument 11783 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11784 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11785 .addReg(OffsetReg) 11786 .addImm(UseFPOffset ? 16 : 8); 11787 11788 // Store it back into the va_list. 11789 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11790 .addOperand(Base) 11791 .addOperand(Scale) 11792 .addOperand(Index) 11793 .addDisp(Disp, UseFPOffset ? 4 : 0) 11794 .addOperand(Segment) 11795 .addReg(NextOffsetReg) 11796 .setMemRefs(MMOBegin, MMOEnd); 11797 11798 // Jump to endMBB 11799 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11800 .addMBB(endMBB); 11801 } 11802 11803 // 11804 // Emit code to use overflow area 11805 // 11806 11807 // Load the overflow_area address into a register. 11808 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11809 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11810 .addOperand(Base) 11811 .addOperand(Scale) 11812 .addOperand(Index) 11813 .addDisp(Disp, 8) 11814 .addOperand(Segment) 11815 .setMemRefs(MMOBegin, MMOEnd); 11816 11817 // If we need to align it, do so. Otherwise, just copy the address 11818 // to OverflowDestReg. 11819 if (NeedsAlign) { 11820 // Align the overflow address 11821 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11822 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11823 11824 // aligned_addr = (addr + (align-1)) & ~(align-1) 11825 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11826 .addReg(OverflowAddrReg) 11827 .addImm(Align-1); 11828 11829 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11830 .addReg(TmpReg) 11831 .addImm(~(uint64_t)(Align-1)); 11832 } else { 11833 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11834 .addReg(OverflowAddrReg); 11835 } 11836 11837 // Compute the next overflow address after this argument. 11838 // (the overflow address should be kept 8-byte aligned) 11839 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11840 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11841 .addReg(OverflowDestReg) 11842 .addImm(ArgSizeA8); 11843 11844 // Store the new overflow address. 11845 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11846 .addOperand(Base) 11847 .addOperand(Scale) 11848 .addOperand(Index) 11849 .addDisp(Disp, 8) 11850 .addOperand(Segment) 11851 .addReg(NextAddrReg) 11852 .setMemRefs(MMOBegin, MMOEnd); 11853 11854 // If we branched, emit the PHI to the front of endMBB. 11855 if (offsetMBB) { 11856 BuildMI(*endMBB, endMBB->begin(), DL, 11857 TII->get(X86::PHI), DestReg) 11858 .addReg(OffsetDestReg).addMBB(offsetMBB) 11859 .addReg(OverflowDestReg).addMBB(overflowMBB); 11860 } 11861 11862 // Erase the pseudo instruction 11863 MI->eraseFromParent(); 11864 11865 return endMBB; 11866} 11867 11868MachineBasicBlock * 11869X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11870 MachineInstr *MI, 11871 MachineBasicBlock *MBB) const { 11872 // Emit code to save XMM registers to the stack. The ABI says that the 11873 // number of registers to save is given in %al, so it's theoretically 11874 // possible to do an indirect jump trick to avoid saving all of them, 11875 // however this code takes a simpler approach and just executes all 11876 // of the stores if %al is non-zero. It's less code, and it's probably 11877 // easier on the hardware branch predictor, and stores aren't all that 11878 // expensive anyway. 11879 11880 // Create the new basic blocks. One block contains all the XMM stores, 11881 // and one block is the final destination regardless of whether any 11882 // stores were performed. 11883 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11884 MachineFunction *F = MBB->getParent(); 11885 MachineFunction::iterator MBBIter = MBB; 11886 ++MBBIter; 11887 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11888 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11889 F->insert(MBBIter, XMMSaveMBB); 11890 F->insert(MBBIter, EndMBB); 11891 11892 // Transfer the remainder of MBB and its successor edges to EndMBB. 11893 EndMBB->splice(EndMBB->begin(), MBB, 11894 llvm::next(MachineBasicBlock::iterator(MI)), 11895 MBB->end()); 11896 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11897 11898 // The original block will now fall through to the XMM save block. 11899 MBB->addSuccessor(XMMSaveMBB); 11900 // The XMMSaveMBB will fall through to the end block. 11901 XMMSaveMBB->addSuccessor(EndMBB); 11902 11903 // Now add the instructions. 11904 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11905 DebugLoc DL = MI->getDebugLoc(); 11906 11907 unsigned CountReg = MI->getOperand(0).getReg(); 11908 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11909 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11910 11911 if (!Subtarget->isTargetWin64()) { 11912 // If %al is 0, branch around the XMM save block. 11913 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11914 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11915 MBB->addSuccessor(EndMBB); 11916 } 11917 11918 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11919 // In the XMM save block, save all the XMM argument registers. 11920 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11921 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11922 MachineMemOperand *MMO = 11923 F->getMachineMemOperand( 11924 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11925 MachineMemOperand::MOStore, 11926 /*Size=*/16, /*Align=*/16); 11927 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11928 .addFrameIndex(RegSaveFrameIndex) 11929 .addImm(/*Scale=*/1) 11930 .addReg(/*IndexReg=*/0) 11931 .addImm(/*Disp=*/Offset) 11932 .addReg(/*Segment=*/0) 11933 .addReg(MI->getOperand(i).getReg()) 11934 .addMemOperand(MMO); 11935 } 11936 11937 MI->eraseFromParent(); // The pseudo instruction is gone now. 11938 11939 return EndMBB; 11940} 11941 11942MachineBasicBlock * 11943X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11944 MachineBasicBlock *BB) const { 11945 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11946 DebugLoc DL = MI->getDebugLoc(); 11947 11948 // To "insert" a SELECT_CC instruction, we actually have to insert the 11949 // diamond control-flow pattern. The incoming instruction knows the 11950 // destination vreg to set, the condition code register to branch on, the 11951 // true/false values to select between, and a branch opcode to use. 11952 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11953 MachineFunction::iterator It = BB; 11954 ++It; 11955 11956 // thisMBB: 11957 // ... 11958 // TrueVal = ... 11959 // cmpTY ccX, r1, r2 11960 // bCC copy1MBB 11961 // fallthrough --> copy0MBB 11962 MachineBasicBlock *thisMBB = BB; 11963 MachineFunction *F = BB->getParent(); 11964 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11965 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11966 F->insert(It, copy0MBB); 11967 F->insert(It, sinkMBB); 11968 11969 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11970 // live into the sink and copy blocks. 11971 if (!MI->killsRegister(X86::EFLAGS)) { 11972 copy0MBB->addLiveIn(X86::EFLAGS); 11973 sinkMBB->addLiveIn(X86::EFLAGS); 11974 } 11975 11976 // Transfer the remainder of BB and its successor edges to sinkMBB. 11977 sinkMBB->splice(sinkMBB->begin(), BB, 11978 llvm::next(MachineBasicBlock::iterator(MI)), 11979 BB->end()); 11980 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11981 11982 // Add the true and fallthrough blocks as its successors. 11983 BB->addSuccessor(copy0MBB); 11984 BB->addSuccessor(sinkMBB); 11985 11986 // Create the conditional branch instruction. 11987 unsigned Opc = 11988 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11989 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11990 11991 // copy0MBB: 11992 // %FalseValue = ... 11993 // # fallthrough to sinkMBB 11994 copy0MBB->addSuccessor(sinkMBB); 11995 11996 // sinkMBB: 11997 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11998 // ... 11999 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12000 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12001 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12002 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12003 12004 MI->eraseFromParent(); // The pseudo instruction is gone now. 12005 return sinkMBB; 12006} 12007 12008MachineBasicBlock * 12009X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12010 bool Is64Bit) const { 12011 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12012 DebugLoc DL = MI->getDebugLoc(); 12013 MachineFunction *MF = BB->getParent(); 12014 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12015 12016 assert(getTargetMachine().Options.EnableSegmentedStacks); 12017 12018 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12019 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12020 12021 // BB: 12022 // ... [Till the alloca] 12023 // If stacklet is not large enough, jump to mallocMBB 12024 // 12025 // bumpMBB: 12026 // Allocate by subtracting from RSP 12027 // Jump to continueMBB 12028 // 12029 // mallocMBB: 12030 // Allocate by call to runtime 12031 // 12032 // continueMBB: 12033 // ... 12034 // [rest of original BB] 12035 // 12036 12037 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12038 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12039 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12040 12041 MachineRegisterInfo &MRI = MF->getRegInfo(); 12042 const TargetRegisterClass *AddrRegClass = 12043 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12044 12045 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12046 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12047 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12048 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12049 sizeVReg = MI->getOperand(1).getReg(), 12050 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12051 12052 MachineFunction::iterator MBBIter = BB; 12053 ++MBBIter; 12054 12055 MF->insert(MBBIter, bumpMBB); 12056 MF->insert(MBBIter, mallocMBB); 12057 MF->insert(MBBIter, continueMBB); 12058 12059 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12060 (MachineBasicBlock::iterator(MI)), BB->end()); 12061 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12062 12063 // Add code to the main basic block to check if the stack limit has been hit, 12064 // and if so, jump to mallocMBB otherwise to bumpMBB. 12065 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12066 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12067 .addReg(tmpSPVReg).addReg(sizeVReg); 12068 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12069 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12070 .addReg(SPLimitVReg); 12071 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12072 12073 // bumpMBB simply decreases the stack pointer, since we know the current 12074 // stacklet has enough space. 12075 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12076 .addReg(SPLimitVReg); 12077 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12078 .addReg(SPLimitVReg); 12079 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12080 12081 // Calls into a routine in libgcc to allocate more space from the heap. 12082 if (Is64Bit) { 12083 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12084 .addReg(sizeVReg); 12085 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12086 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12087 } else { 12088 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12089 .addImm(12); 12090 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12091 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12092 .addExternalSymbol("__morestack_allocate_stack_space"); 12093 } 12094 12095 if (!Is64Bit) 12096 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12097 .addImm(16); 12098 12099 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12100 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12101 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12102 12103 // Set up the CFG correctly. 12104 BB->addSuccessor(bumpMBB); 12105 BB->addSuccessor(mallocMBB); 12106 mallocMBB->addSuccessor(continueMBB); 12107 bumpMBB->addSuccessor(continueMBB); 12108 12109 // Take care of the PHI nodes. 12110 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12111 MI->getOperand(0).getReg()) 12112 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12113 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12114 12115 // Delete the original pseudo instruction. 12116 MI->eraseFromParent(); 12117 12118 // And we're done. 12119 return continueMBB; 12120} 12121 12122MachineBasicBlock * 12123X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12124 MachineBasicBlock *BB) const { 12125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12126 DebugLoc DL = MI->getDebugLoc(); 12127 12128 assert(!Subtarget->isTargetEnvMacho()); 12129 12130 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12131 // non-trivial part is impdef of ESP. 12132 12133 if (Subtarget->isTargetWin64()) { 12134 if (Subtarget->isTargetCygMing()) { 12135 // ___chkstk(Mingw64): 12136 // Clobbers R10, R11, RAX and EFLAGS. 12137 // Updates RSP. 12138 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12139 .addExternalSymbol("___chkstk") 12140 .addReg(X86::RAX, RegState::Implicit) 12141 .addReg(X86::RSP, RegState::Implicit) 12142 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12143 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12144 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12145 } else { 12146 // __chkstk(MSVCRT): does not update stack pointer. 12147 // Clobbers R10, R11 and EFLAGS. 12148 // FIXME: RAX(allocated size) might be reused and not killed. 12149 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12150 .addExternalSymbol("__chkstk") 12151 .addReg(X86::RAX, RegState::Implicit) 12152 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12153 // RAX has the offset to subtracted from RSP. 12154 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12155 .addReg(X86::RSP) 12156 .addReg(X86::RAX); 12157 } 12158 } else { 12159 const char *StackProbeSymbol = 12160 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12161 12162 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12163 .addExternalSymbol(StackProbeSymbol) 12164 .addReg(X86::EAX, RegState::Implicit) 12165 .addReg(X86::ESP, RegState::Implicit) 12166 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12167 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12168 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12169 } 12170 12171 MI->eraseFromParent(); // The pseudo instruction is gone now. 12172 return BB; 12173} 12174 12175MachineBasicBlock * 12176X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12177 MachineBasicBlock *BB) const { 12178 // This is pretty easy. We're taking the value that we received from 12179 // our load from the relocation, sticking it in either RDI (x86-64) 12180 // or EAX and doing an indirect call. The return value will then 12181 // be in the normal return register. 12182 const X86InstrInfo *TII 12183 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12184 DebugLoc DL = MI->getDebugLoc(); 12185 MachineFunction *F = BB->getParent(); 12186 12187 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12188 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12189 12190 if (Subtarget->is64Bit()) { 12191 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12192 TII->get(X86::MOV64rm), X86::RDI) 12193 .addReg(X86::RIP) 12194 .addImm(0).addReg(0) 12195 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12196 MI->getOperand(3).getTargetFlags()) 12197 .addReg(0); 12198 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12199 addDirectMem(MIB, X86::RDI); 12200 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12201 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12202 TII->get(X86::MOV32rm), X86::EAX) 12203 .addReg(0) 12204 .addImm(0).addReg(0) 12205 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12206 MI->getOperand(3).getTargetFlags()) 12207 .addReg(0); 12208 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12209 addDirectMem(MIB, X86::EAX); 12210 } else { 12211 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12212 TII->get(X86::MOV32rm), X86::EAX) 12213 .addReg(TII->getGlobalBaseReg(F)) 12214 .addImm(0).addReg(0) 12215 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12216 MI->getOperand(3).getTargetFlags()) 12217 .addReg(0); 12218 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12219 addDirectMem(MIB, X86::EAX); 12220 } 12221 12222 MI->eraseFromParent(); // The pseudo instruction is gone now. 12223 return BB; 12224} 12225 12226MachineBasicBlock * 12227X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12228 MachineBasicBlock *BB) const { 12229 switch (MI->getOpcode()) { 12230 default: assert(0 && "Unexpected instr type to insert"); 12231 case X86::TAILJMPd64: 12232 case X86::TAILJMPr64: 12233 case X86::TAILJMPm64: 12234 assert(0 && "TAILJMP64 would not be touched here."); 12235 case X86::TCRETURNdi64: 12236 case X86::TCRETURNri64: 12237 case X86::TCRETURNmi64: 12238 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12239 // On AMD64, additional defs should be added before register allocation. 12240 if (!Subtarget->isTargetWin64()) { 12241 MI->addRegisterDefined(X86::RSI); 12242 MI->addRegisterDefined(X86::RDI); 12243 MI->addRegisterDefined(X86::XMM6); 12244 MI->addRegisterDefined(X86::XMM7); 12245 MI->addRegisterDefined(X86::XMM8); 12246 MI->addRegisterDefined(X86::XMM9); 12247 MI->addRegisterDefined(X86::XMM10); 12248 MI->addRegisterDefined(X86::XMM11); 12249 MI->addRegisterDefined(X86::XMM12); 12250 MI->addRegisterDefined(X86::XMM13); 12251 MI->addRegisterDefined(X86::XMM14); 12252 MI->addRegisterDefined(X86::XMM15); 12253 } 12254 return BB; 12255 case X86::WIN_ALLOCA: 12256 return EmitLoweredWinAlloca(MI, BB); 12257 case X86::SEG_ALLOCA_32: 12258 return EmitLoweredSegAlloca(MI, BB, false); 12259 case X86::SEG_ALLOCA_64: 12260 return EmitLoweredSegAlloca(MI, BB, true); 12261 case X86::TLSCall_32: 12262 case X86::TLSCall_64: 12263 return EmitLoweredTLSCall(MI, BB); 12264 case X86::CMOV_GR8: 12265 case X86::CMOV_FR32: 12266 case X86::CMOV_FR64: 12267 case X86::CMOV_V4F32: 12268 case X86::CMOV_V2F64: 12269 case X86::CMOV_V2I64: 12270 case X86::CMOV_V8F32: 12271 case X86::CMOV_V4F64: 12272 case X86::CMOV_V4I64: 12273 case X86::CMOV_GR16: 12274 case X86::CMOV_GR32: 12275 case X86::CMOV_RFP32: 12276 case X86::CMOV_RFP64: 12277 case X86::CMOV_RFP80: 12278 return EmitLoweredSelect(MI, BB); 12279 12280 case X86::FP32_TO_INT16_IN_MEM: 12281 case X86::FP32_TO_INT32_IN_MEM: 12282 case X86::FP32_TO_INT64_IN_MEM: 12283 case X86::FP64_TO_INT16_IN_MEM: 12284 case X86::FP64_TO_INT32_IN_MEM: 12285 case X86::FP64_TO_INT64_IN_MEM: 12286 case X86::FP80_TO_INT16_IN_MEM: 12287 case X86::FP80_TO_INT32_IN_MEM: 12288 case X86::FP80_TO_INT64_IN_MEM: { 12289 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12290 DebugLoc DL = MI->getDebugLoc(); 12291 12292 // Change the floating point control register to use "round towards zero" 12293 // mode when truncating to an integer value. 12294 MachineFunction *F = BB->getParent(); 12295 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12296 addFrameReference(BuildMI(*BB, MI, DL, 12297 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12298 12299 // Load the old value of the high byte of the control word... 12300 unsigned OldCW = 12301 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12302 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12303 CWFrameIdx); 12304 12305 // Set the high part to be round to zero... 12306 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12307 .addImm(0xC7F); 12308 12309 // Reload the modified control word now... 12310 addFrameReference(BuildMI(*BB, MI, DL, 12311 TII->get(X86::FLDCW16m)), CWFrameIdx); 12312 12313 // Restore the memory image of control word to original value 12314 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12315 .addReg(OldCW); 12316 12317 // Get the X86 opcode to use. 12318 unsigned Opc; 12319 switch (MI->getOpcode()) { 12320 default: llvm_unreachable("illegal opcode!"); 12321 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12322 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12323 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12324 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12325 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12326 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12327 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12328 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12329 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12330 } 12331 12332 X86AddressMode AM; 12333 MachineOperand &Op = MI->getOperand(0); 12334 if (Op.isReg()) { 12335 AM.BaseType = X86AddressMode::RegBase; 12336 AM.Base.Reg = Op.getReg(); 12337 } else { 12338 AM.BaseType = X86AddressMode::FrameIndexBase; 12339 AM.Base.FrameIndex = Op.getIndex(); 12340 } 12341 Op = MI->getOperand(1); 12342 if (Op.isImm()) 12343 AM.Scale = Op.getImm(); 12344 Op = MI->getOperand(2); 12345 if (Op.isImm()) 12346 AM.IndexReg = Op.getImm(); 12347 Op = MI->getOperand(3); 12348 if (Op.isGlobal()) { 12349 AM.GV = Op.getGlobal(); 12350 } else { 12351 AM.Disp = Op.getImm(); 12352 } 12353 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12354 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12355 12356 // Reload the original control word now. 12357 addFrameReference(BuildMI(*BB, MI, DL, 12358 TII->get(X86::FLDCW16m)), CWFrameIdx); 12359 12360 MI->eraseFromParent(); // The pseudo instruction is gone now. 12361 return BB; 12362 } 12363 // String/text processing lowering. 12364 case X86::PCMPISTRM128REG: 12365 case X86::VPCMPISTRM128REG: 12366 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12367 case X86::PCMPISTRM128MEM: 12368 case X86::VPCMPISTRM128MEM: 12369 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12370 case X86::PCMPESTRM128REG: 12371 case X86::VPCMPESTRM128REG: 12372 return EmitPCMP(MI, BB, 5, false /* in mem */); 12373 case X86::PCMPESTRM128MEM: 12374 case X86::VPCMPESTRM128MEM: 12375 return EmitPCMP(MI, BB, 5, true /* in mem */); 12376 12377 // Thread synchronization. 12378 case X86::MONITOR: 12379 return EmitMonitor(MI, BB); 12380 case X86::MWAIT: 12381 return EmitMwait(MI, BB); 12382 12383 // Atomic Lowering. 12384 case X86::ATOMAND32: 12385 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12386 X86::AND32ri, X86::MOV32rm, 12387 X86::LCMPXCHG32, 12388 X86::NOT32r, X86::EAX, 12389 X86::GR32RegisterClass); 12390 case X86::ATOMOR32: 12391 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12392 X86::OR32ri, X86::MOV32rm, 12393 X86::LCMPXCHG32, 12394 X86::NOT32r, X86::EAX, 12395 X86::GR32RegisterClass); 12396 case X86::ATOMXOR32: 12397 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12398 X86::XOR32ri, X86::MOV32rm, 12399 X86::LCMPXCHG32, 12400 X86::NOT32r, X86::EAX, 12401 X86::GR32RegisterClass); 12402 case X86::ATOMNAND32: 12403 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12404 X86::AND32ri, X86::MOV32rm, 12405 X86::LCMPXCHG32, 12406 X86::NOT32r, X86::EAX, 12407 X86::GR32RegisterClass, true); 12408 case X86::ATOMMIN32: 12409 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12410 case X86::ATOMMAX32: 12411 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12412 case X86::ATOMUMIN32: 12413 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12414 case X86::ATOMUMAX32: 12415 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12416 12417 case X86::ATOMAND16: 12418 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12419 X86::AND16ri, X86::MOV16rm, 12420 X86::LCMPXCHG16, 12421 X86::NOT16r, X86::AX, 12422 X86::GR16RegisterClass); 12423 case X86::ATOMOR16: 12424 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12425 X86::OR16ri, X86::MOV16rm, 12426 X86::LCMPXCHG16, 12427 X86::NOT16r, X86::AX, 12428 X86::GR16RegisterClass); 12429 case X86::ATOMXOR16: 12430 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12431 X86::XOR16ri, X86::MOV16rm, 12432 X86::LCMPXCHG16, 12433 X86::NOT16r, X86::AX, 12434 X86::GR16RegisterClass); 12435 case X86::ATOMNAND16: 12436 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12437 X86::AND16ri, X86::MOV16rm, 12438 X86::LCMPXCHG16, 12439 X86::NOT16r, X86::AX, 12440 X86::GR16RegisterClass, true); 12441 case X86::ATOMMIN16: 12442 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12443 case X86::ATOMMAX16: 12444 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12445 case X86::ATOMUMIN16: 12446 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12447 case X86::ATOMUMAX16: 12448 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12449 12450 case X86::ATOMAND8: 12451 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12452 X86::AND8ri, X86::MOV8rm, 12453 X86::LCMPXCHG8, 12454 X86::NOT8r, X86::AL, 12455 X86::GR8RegisterClass); 12456 case X86::ATOMOR8: 12457 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12458 X86::OR8ri, X86::MOV8rm, 12459 X86::LCMPXCHG8, 12460 X86::NOT8r, X86::AL, 12461 X86::GR8RegisterClass); 12462 case X86::ATOMXOR8: 12463 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12464 X86::XOR8ri, X86::MOV8rm, 12465 X86::LCMPXCHG8, 12466 X86::NOT8r, X86::AL, 12467 X86::GR8RegisterClass); 12468 case X86::ATOMNAND8: 12469 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12470 X86::AND8ri, X86::MOV8rm, 12471 X86::LCMPXCHG8, 12472 X86::NOT8r, X86::AL, 12473 X86::GR8RegisterClass, true); 12474 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12475 // This group is for 64-bit host. 12476 case X86::ATOMAND64: 12477 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12478 X86::AND64ri32, X86::MOV64rm, 12479 X86::LCMPXCHG64, 12480 X86::NOT64r, X86::RAX, 12481 X86::GR64RegisterClass); 12482 case X86::ATOMOR64: 12483 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12484 X86::OR64ri32, X86::MOV64rm, 12485 X86::LCMPXCHG64, 12486 X86::NOT64r, X86::RAX, 12487 X86::GR64RegisterClass); 12488 case X86::ATOMXOR64: 12489 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12490 X86::XOR64ri32, X86::MOV64rm, 12491 X86::LCMPXCHG64, 12492 X86::NOT64r, X86::RAX, 12493 X86::GR64RegisterClass); 12494 case X86::ATOMNAND64: 12495 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12496 X86::AND64ri32, X86::MOV64rm, 12497 X86::LCMPXCHG64, 12498 X86::NOT64r, X86::RAX, 12499 X86::GR64RegisterClass, true); 12500 case X86::ATOMMIN64: 12501 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12502 case X86::ATOMMAX64: 12503 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12504 case X86::ATOMUMIN64: 12505 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12506 case X86::ATOMUMAX64: 12507 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12508 12509 // This group does 64-bit operations on a 32-bit host. 12510 case X86::ATOMAND6432: 12511 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12512 X86::AND32rr, X86::AND32rr, 12513 X86::AND32ri, X86::AND32ri, 12514 false); 12515 case X86::ATOMOR6432: 12516 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12517 X86::OR32rr, X86::OR32rr, 12518 X86::OR32ri, X86::OR32ri, 12519 false); 12520 case X86::ATOMXOR6432: 12521 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12522 X86::XOR32rr, X86::XOR32rr, 12523 X86::XOR32ri, X86::XOR32ri, 12524 false); 12525 case X86::ATOMNAND6432: 12526 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12527 X86::AND32rr, X86::AND32rr, 12528 X86::AND32ri, X86::AND32ri, 12529 true); 12530 case X86::ATOMADD6432: 12531 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12532 X86::ADD32rr, X86::ADC32rr, 12533 X86::ADD32ri, X86::ADC32ri, 12534 false); 12535 case X86::ATOMSUB6432: 12536 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12537 X86::SUB32rr, X86::SBB32rr, 12538 X86::SUB32ri, X86::SBB32ri, 12539 false); 12540 case X86::ATOMSWAP6432: 12541 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12542 X86::MOV32rr, X86::MOV32rr, 12543 X86::MOV32ri, X86::MOV32ri, 12544 false); 12545 case X86::VASTART_SAVE_XMM_REGS: 12546 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12547 12548 case X86::VAARG_64: 12549 return EmitVAARG64WithCustomInserter(MI, BB); 12550 } 12551} 12552 12553//===----------------------------------------------------------------------===// 12554// X86 Optimization Hooks 12555//===----------------------------------------------------------------------===// 12556 12557void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12558 const APInt &Mask, 12559 APInt &KnownZero, 12560 APInt &KnownOne, 12561 const SelectionDAG &DAG, 12562 unsigned Depth) const { 12563 unsigned Opc = Op.getOpcode(); 12564 assert((Opc >= ISD::BUILTIN_OP_END || 12565 Opc == ISD::INTRINSIC_WO_CHAIN || 12566 Opc == ISD::INTRINSIC_W_CHAIN || 12567 Opc == ISD::INTRINSIC_VOID) && 12568 "Should use MaskedValueIsZero if you don't know whether Op" 12569 " is a target node!"); 12570 12571 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12572 switch (Opc) { 12573 default: break; 12574 case X86ISD::ADD: 12575 case X86ISD::SUB: 12576 case X86ISD::ADC: 12577 case X86ISD::SBB: 12578 case X86ISD::SMUL: 12579 case X86ISD::UMUL: 12580 case X86ISD::INC: 12581 case X86ISD::DEC: 12582 case X86ISD::OR: 12583 case X86ISD::XOR: 12584 case X86ISD::AND: 12585 // These nodes' second result is a boolean. 12586 if (Op.getResNo() == 0) 12587 break; 12588 // Fallthrough 12589 case X86ISD::SETCC: 12590 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12591 Mask.getBitWidth() - 1); 12592 break; 12593 case ISD::INTRINSIC_WO_CHAIN: { 12594 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12595 unsigned NumLoBits = 0; 12596 switch (IntId) { 12597 default: break; 12598 case Intrinsic::x86_sse_movmsk_ps: 12599 case Intrinsic::x86_avx_movmsk_ps_256: 12600 case Intrinsic::x86_sse2_movmsk_pd: 12601 case Intrinsic::x86_avx_movmsk_pd_256: 12602 case Intrinsic::x86_mmx_pmovmskb: 12603 case Intrinsic::x86_sse2_pmovmskb_128: 12604 case Intrinsic::x86_avx2_pmovmskb: { 12605 // High bits of movmskp{s|d}, pmovmskb are known zero. 12606 switch (IntId) { 12607 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12608 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12609 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12610 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12611 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12612 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12613 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12614 } 12615 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12616 Mask.getBitWidth() - NumLoBits); 12617 break; 12618 } 12619 } 12620 break; 12621 } 12622 } 12623} 12624 12625unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12626 unsigned Depth) const { 12627 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12628 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12629 return Op.getValueType().getScalarType().getSizeInBits(); 12630 12631 // Fallback case. 12632 return 1; 12633} 12634 12635/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12636/// node is a GlobalAddress + offset. 12637bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12638 const GlobalValue* &GA, 12639 int64_t &Offset) const { 12640 if (N->getOpcode() == X86ISD::Wrapper) { 12641 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12642 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12643 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12644 return true; 12645 } 12646 } 12647 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12648} 12649 12650/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12651/// same as extracting the high 128-bit part of 256-bit vector and then 12652/// inserting the result into the low part of a new 256-bit vector 12653static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12654 EVT VT = SVOp->getValueType(0); 12655 int NumElems = VT.getVectorNumElements(); 12656 12657 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12658 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12659 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12660 SVOp->getMaskElt(j) >= 0) 12661 return false; 12662 12663 return true; 12664} 12665 12666/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12667/// same as extracting the low 128-bit part of 256-bit vector and then 12668/// inserting the result into the high part of a new 256-bit vector 12669static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12670 EVT VT = SVOp->getValueType(0); 12671 int NumElems = VT.getVectorNumElements(); 12672 12673 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12674 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12675 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12676 SVOp->getMaskElt(j) >= 0) 12677 return false; 12678 12679 return true; 12680} 12681 12682/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12683static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12684 TargetLowering::DAGCombinerInfo &DCI) { 12685 DebugLoc dl = N->getDebugLoc(); 12686 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12687 SDValue V1 = SVOp->getOperand(0); 12688 SDValue V2 = SVOp->getOperand(1); 12689 EVT VT = SVOp->getValueType(0); 12690 int NumElems = VT.getVectorNumElements(); 12691 12692 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12693 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12694 // 12695 // 0,0,0,... 12696 // | 12697 // V UNDEF BUILD_VECTOR UNDEF 12698 // \ / \ / 12699 // CONCAT_VECTOR CONCAT_VECTOR 12700 // \ / 12701 // \ / 12702 // RESULT: V + zero extended 12703 // 12704 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12705 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12706 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12707 return SDValue(); 12708 12709 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12710 return SDValue(); 12711 12712 // To match the shuffle mask, the first half of the mask should 12713 // be exactly the first vector, and all the rest a splat with the 12714 // first element of the second one. 12715 for (int i = 0; i < NumElems/2; ++i) 12716 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12717 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12718 return SDValue(); 12719 12720 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12721 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12722 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12723 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12724 SDValue ResNode = 12725 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12726 Ld->getMemoryVT(), 12727 Ld->getPointerInfo(), 12728 Ld->getAlignment(), 12729 false/*isVolatile*/, true/*ReadMem*/, 12730 false/*WriteMem*/); 12731 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12732 } 12733 12734 // Emit a zeroed vector and insert the desired subvector on its 12735 // first half. 12736 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 12737 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12738 DAG.getConstant(0, MVT::i32), DAG, dl); 12739 return DCI.CombineTo(N, InsV); 12740 } 12741 12742 //===--------------------------------------------------------------------===// 12743 // Combine some shuffles into subvector extracts and inserts: 12744 // 12745 12746 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12747 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12748 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12749 DAG, dl); 12750 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12751 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12752 return DCI.CombineTo(N, InsV); 12753 } 12754 12755 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12756 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12757 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12758 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12759 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12760 return DCI.CombineTo(N, InsV); 12761 } 12762 12763 return SDValue(); 12764} 12765 12766/// PerformShuffleCombine - Performs several different shuffle combines. 12767static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12768 TargetLowering::DAGCombinerInfo &DCI, 12769 const X86Subtarget *Subtarget) { 12770 DebugLoc dl = N->getDebugLoc(); 12771 EVT VT = N->getValueType(0); 12772 12773 // Don't create instructions with illegal types after legalize types has run. 12774 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12775 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12776 return SDValue(); 12777 12778 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12779 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12780 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12781 return PerformShuffleCombine256(N, DAG, DCI); 12782 12783 // Only handle 128 wide vector from here on. 12784 if (VT.getSizeInBits() != 128) 12785 return SDValue(); 12786 12787 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12788 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12789 // consecutive, non-overlapping, and in the right order. 12790 SmallVector<SDValue, 16> Elts; 12791 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12792 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12793 12794 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12795} 12796 12797/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12798/// generation and convert it from being a bunch of shuffles and extracts 12799/// to a simple store and scalar loads to extract the elements. 12800static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12801 const TargetLowering &TLI) { 12802 SDValue InputVector = N->getOperand(0); 12803 12804 // Only operate on vectors of 4 elements, where the alternative shuffling 12805 // gets to be more expensive. 12806 if (InputVector.getValueType() != MVT::v4i32) 12807 return SDValue(); 12808 12809 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12810 // single use which is a sign-extend or zero-extend, and all elements are 12811 // used. 12812 SmallVector<SDNode *, 4> Uses; 12813 unsigned ExtractedElements = 0; 12814 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12815 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12816 if (UI.getUse().getResNo() != InputVector.getResNo()) 12817 return SDValue(); 12818 12819 SDNode *Extract = *UI; 12820 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12821 return SDValue(); 12822 12823 if (Extract->getValueType(0) != MVT::i32) 12824 return SDValue(); 12825 if (!Extract->hasOneUse()) 12826 return SDValue(); 12827 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12828 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12829 return SDValue(); 12830 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12831 return SDValue(); 12832 12833 // Record which element was extracted. 12834 ExtractedElements |= 12835 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12836 12837 Uses.push_back(Extract); 12838 } 12839 12840 // If not all the elements were used, this may not be worthwhile. 12841 if (ExtractedElements != 15) 12842 return SDValue(); 12843 12844 // Ok, we've now decided to do the transformation. 12845 DebugLoc dl = InputVector.getDebugLoc(); 12846 12847 // Store the value to a temporary stack slot. 12848 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12849 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12850 MachinePointerInfo(), false, false, 0); 12851 12852 // Replace each use (extract) with a load of the appropriate element. 12853 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12854 UE = Uses.end(); UI != UE; ++UI) { 12855 SDNode *Extract = *UI; 12856 12857 // cOMpute the element's address. 12858 SDValue Idx = Extract->getOperand(1); 12859 unsigned EltSize = 12860 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12861 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12862 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12863 12864 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12865 StackPtr, OffsetVal); 12866 12867 // Load the scalar. 12868 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12869 ScalarAddr, MachinePointerInfo(), 12870 false, false, false, 0); 12871 12872 // Replace the exact with the load. 12873 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12874 } 12875 12876 // The replacement was made in place; don't return anything. 12877 return SDValue(); 12878} 12879 12880/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12881/// nodes. 12882static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12883 const X86Subtarget *Subtarget) { 12884 DebugLoc DL = N->getDebugLoc(); 12885 SDValue Cond = N->getOperand(0); 12886 // Get the LHS/RHS of the select. 12887 SDValue LHS = N->getOperand(1); 12888 SDValue RHS = N->getOperand(2); 12889 EVT VT = LHS.getValueType(); 12890 12891 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12892 // instructions match the semantics of the common C idiom x<y?x:y but not 12893 // x<=y?x:y, because of how they handle negative zero (which can be 12894 // ignored in unsafe-math mode). 12895 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12896 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12897 (Subtarget->hasSSE2() || 12898 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12899 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12900 12901 unsigned Opcode = 0; 12902 // Check for x CC y ? x : y. 12903 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12904 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12905 switch (CC) { 12906 default: break; 12907 case ISD::SETULT: 12908 // Converting this to a min would handle NaNs incorrectly, and swapping 12909 // the operands would cause it to handle comparisons between positive 12910 // and negative zero incorrectly. 12911 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12912 if (!DAG.getTarget().Options.UnsafeFPMath && 12913 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12914 break; 12915 std::swap(LHS, RHS); 12916 } 12917 Opcode = X86ISD::FMIN; 12918 break; 12919 case ISD::SETOLE: 12920 // Converting this to a min would handle comparisons between positive 12921 // and negative zero incorrectly. 12922 if (!DAG.getTarget().Options.UnsafeFPMath && 12923 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12924 break; 12925 Opcode = X86ISD::FMIN; 12926 break; 12927 case ISD::SETULE: 12928 // Converting this to a min would handle both negative zeros and NaNs 12929 // incorrectly, but we can swap the operands to fix both. 12930 std::swap(LHS, RHS); 12931 case ISD::SETOLT: 12932 case ISD::SETLT: 12933 case ISD::SETLE: 12934 Opcode = X86ISD::FMIN; 12935 break; 12936 12937 case ISD::SETOGE: 12938 // Converting this to a max would handle comparisons between positive 12939 // and negative zero incorrectly. 12940 if (!DAG.getTarget().Options.UnsafeFPMath && 12941 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12942 break; 12943 Opcode = X86ISD::FMAX; 12944 break; 12945 case ISD::SETUGT: 12946 // Converting this to a max would handle NaNs incorrectly, and swapping 12947 // the operands would cause it to handle comparisons between positive 12948 // and negative zero incorrectly. 12949 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12950 if (!DAG.getTarget().Options.UnsafeFPMath && 12951 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12952 break; 12953 std::swap(LHS, RHS); 12954 } 12955 Opcode = X86ISD::FMAX; 12956 break; 12957 case ISD::SETUGE: 12958 // Converting this to a max would handle both negative zeros and NaNs 12959 // incorrectly, but we can swap the operands to fix both. 12960 std::swap(LHS, RHS); 12961 case ISD::SETOGT: 12962 case ISD::SETGT: 12963 case ISD::SETGE: 12964 Opcode = X86ISD::FMAX; 12965 break; 12966 } 12967 // Check for x CC y ? y : x -- a min/max with reversed arms. 12968 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12969 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12970 switch (CC) { 12971 default: break; 12972 case ISD::SETOGE: 12973 // Converting this to a min would handle comparisons between positive 12974 // and negative zero incorrectly, and swapping the operands would 12975 // cause it to handle NaNs incorrectly. 12976 if (!DAG.getTarget().Options.UnsafeFPMath && 12977 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12978 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12979 break; 12980 std::swap(LHS, RHS); 12981 } 12982 Opcode = X86ISD::FMIN; 12983 break; 12984 case ISD::SETUGT: 12985 // Converting this to a min would handle NaNs incorrectly. 12986 if (!DAG.getTarget().Options.UnsafeFPMath && 12987 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12988 break; 12989 Opcode = X86ISD::FMIN; 12990 break; 12991 case ISD::SETUGE: 12992 // Converting this to a min would handle both negative zeros and NaNs 12993 // incorrectly, but we can swap the operands to fix both. 12994 std::swap(LHS, RHS); 12995 case ISD::SETOGT: 12996 case ISD::SETGT: 12997 case ISD::SETGE: 12998 Opcode = X86ISD::FMIN; 12999 break; 13000 13001 case ISD::SETULT: 13002 // Converting this to a max would handle NaNs incorrectly. 13003 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13004 break; 13005 Opcode = X86ISD::FMAX; 13006 break; 13007 case ISD::SETOLE: 13008 // Converting this to a max would handle comparisons between positive 13009 // and negative zero incorrectly, and swapping the operands would 13010 // cause it to handle NaNs incorrectly. 13011 if (!DAG.getTarget().Options.UnsafeFPMath && 13012 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13013 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13014 break; 13015 std::swap(LHS, RHS); 13016 } 13017 Opcode = X86ISD::FMAX; 13018 break; 13019 case ISD::SETULE: 13020 // Converting this to a max would handle both negative zeros and NaNs 13021 // incorrectly, but we can swap the operands to fix both. 13022 std::swap(LHS, RHS); 13023 case ISD::SETOLT: 13024 case ISD::SETLT: 13025 case ISD::SETLE: 13026 Opcode = X86ISD::FMAX; 13027 break; 13028 } 13029 } 13030 13031 if (Opcode) 13032 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13033 } 13034 13035 // If this is a select between two integer constants, try to do some 13036 // optimizations. 13037 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13038 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13039 // Don't do this for crazy integer types. 13040 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13041 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13042 // so that TrueC (the true value) is larger than FalseC. 13043 bool NeedsCondInvert = false; 13044 13045 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13046 // Efficiently invertible. 13047 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13048 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13049 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13050 NeedsCondInvert = true; 13051 std::swap(TrueC, FalseC); 13052 } 13053 13054 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13055 if (FalseC->getAPIntValue() == 0 && 13056 TrueC->getAPIntValue().isPowerOf2()) { 13057 if (NeedsCondInvert) // Invert the condition if needed. 13058 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13059 DAG.getConstant(1, Cond.getValueType())); 13060 13061 // Zero extend the condition if needed. 13062 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13063 13064 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13065 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13066 DAG.getConstant(ShAmt, MVT::i8)); 13067 } 13068 13069 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13070 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13071 if (NeedsCondInvert) // Invert the condition if needed. 13072 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13073 DAG.getConstant(1, Cond.getValueType())); 13074 13075 // Zero extend the condition if needed. 13076 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13077 FalseC->getValueType(0), Cond); 13078 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13079 SDValue(FalseC, 0)); 13080 } 13081 13082 // Optimize cases that will turn into an LEA instruction. This requires 13083 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13084 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13085 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13086 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13087 13088 bool isFastMultiplier = false; 13089 if (Diff < 10) { 13090 switch ((unsigned char)Diff) { 13091 default: break; 13092 case 1: // result = add base, cond 13093 case 2: // result = lea base( , cond*2) 13094 case 3: // result = lea base(cond, cond*2) 13095 case 4: // result = lea base( , cond*4) 13096 case 5: // result = lea base(cond, cond*4) 13097 case 8: // result = lea base( , cond*8) 13098 case 9: // result = lea base(cond, cond*8) 13099 isFastMultiplier = true; 13100 break; 13101 } 13102 } 13103 13104 if (isFastMultiplier) { 13105 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13106 if (NeedsCondInvert) // Invert the condition if needed. 13107 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13108 DAG.getConstant(1, Cond.getValueType())); 13109 13110 // Zero extend the condition if needed. 13111 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13112 Cond); 13113 // Scale the condition by the difference. 13114 if (Diff != 1) 13115 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13116 DAG.getConstant(Diff, Cond.getValueType())); 13117 13118 // Add the base if non-zero. 13119 if (FalseC->getAPIntValue() != 0) 13120 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13121 SDValue(FalseC, 0)); 13122 return Cond; 13123 } 13124 } 13125 } 13126 } 13127 13128 // Canonicalize max and min: 13129 // (x > y) ? x : y -> (x >= y) ? x : y 13130 // (x < y) ? x : y -> (x <= y) ? x : y 13131 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13132 // the need for an extra compare 13133 // against zero. e.g. 13134 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13135 // subl %esi, %edi 13136 // testl %edi, %edi 13137 // movl $0, %eax 13138 // cmovgl %edi, %eax 13139 // => 13140 // xorl %eax, %eax 13141 // subl %esi, $edi 13142 // cmovsl %eax, %edi 13143 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13144 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13145 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13146 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13147 switch (CC) { 13148 default: break; 13149 case ISD::SETLT: 13150 case ISD::SETGT: { 13151 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13152 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13153 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13154 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13155 } 13156 } 13157 } 13158 13159 return SDValue(); 13160} 13161 13162/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13163static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13164 TargetLowering::DAGCombinerInfo &DCI) { 13165 DebugLoc DL = N->getDebugLoc(); 13166 13167 // If the flag operand isn't dead, don't touch this CMOV. 13168 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13169 return SDValue(); 13170 13171 SDValue FalseOp = N->getOperand(0); 13172 SDValue TrueOp = N->getOperand(1); 13173 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13174 SDValue Cond = N->getOperand(3); 13175 if (CC == X86::COND_E || CC == X86::COND_NE) { 13176 switch (Cond.getOpcode()) { 13177 default: break; 13178 case X86ISD::BSR: 13179 case X86ISD::BSF: 13180 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13181 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13182 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13183 } 13184 } 13185 13186 // If this is a select between two integer constants, try to do some 13187 // optimizations. Note that the operands are ordered the opposite of SELECT 13188 // operands. 13189 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13190 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13191 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13192 // larger than FalseC (the false value). 13193 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13194 CC = X86::GetOppositeBranchCondition(CC); 13195 std::swap(TrueC, FalseC); 13196 } 13197 13198 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13199 // This is efficient for any integer data type (including i8/i16) and 13200 // shift amount. 13201 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13202 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13203 DAG.getConstant(CC, MVT::i8), Cond); 13204 13205 // Zero extend the condition if needed. 13206 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13207 13208 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13209 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13210 DAG.getConstant(ShAmt, MVT::i8)); 13211 if (N->getNumValues() == 2) // Dead flag value? 13212 return DCI.CombineTo(N, Cond, SDValue()); 13213 return Cond; 13214 } 13215 13216 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13217 // for any integer data type, including i8/i16. 13218 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13219 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13220 DAG.getConstant(CC, MVT::i8), Cond); 13221 13222 // Zero extend the condition if needed. 13223 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13224 FalseC->getValueType(0), Cond); 13225 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13226 SDValue(FalseC, 0)); 13227 13228 if (N->getNumValues() == 2) // Dead flag value? 13229 return DCI.CombineTo(N, Cond, SDValue()); 13230 return Cond; 13231 } 13232 13233 // Optimize cases that will turn into an LEA instruction. This requires 13234 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13235 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13236 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13237 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13238 13239 bool isFastMultiplier = false; 13240 if (Diff < 10) { 13241 switch ((unsigned char)Diff) { 13242 default: break; 13243 case 1: // result = add base, cond 13244 case 2: // result = lea base( , cond*2) 13245 case 3: // result = lea base(cond, cond*2) 13246 case 4: // result = lea base( , cond*4) 13247 case 5: // result = lea base(cond, cond*4) 13248 case 8: // result = lea base( , cond*8) 13249 case 9: // result = lea base(cond, cond*8) 13250 isFastMultiplier = true; 13251 break; 13252 } 13253 } 13254 13255 if (isFastMultiplier) { 13256 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13257 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13258 DAG.getConstant(CC, MVT::i8), Cond); 13259 // Zero extend the condition if needed. 13260 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13261 Cond); 13262 // Scale the condition by the difference. 13263 if (Diff != 1) 13264 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13265 DAG.getConstant(Diff, Cond.getValueType())); 13266 13267 // Add the base if non-zero. 13268 if (FalseC->getAPIntValue() != 0) 13269 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13270 SDValue(FalseC, 0)); 13271 if (N->getNumValues() == 2) // Dead flag value? 13272 return DCI.CombineTo(N, Cond, SDValue()); 13273 return Cond; 13274 } 13275 } 13276 } 13277 } 13278 return SDValue(); 13279} 13280 13281 13282/// PerformMulCombine - Optimize a single multiply with constant into two 13283/// in order to implement it with two cheaper instructions, e.g. 13284/// LEA + SHL, LEA + LEA. 13285static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13286 TargetLowering::DAGCombinerInfo &DCI) { 13287 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13288 return SDValue(); 13289 13290 EVT VT = N->getValueType(0); 13291 if (VT != MVT::i64) 13292 return SDValue(); 13293 13294 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13295 if (!C) 13296 return SDValue(); 13297 uint64_t MulAmt = C->getZExtValue(); 13298 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13299 return SDValue(); 13300 13301 uint64_t MulAmt1 = 0; 13302 uint64_t MulAmt2 = 0; 13303 if ((MulAmt % 9) == 0) { 13304 MulAmt1 = 9; 13305 MulAmt2 = MulAmt / 9; 13306 } else if ((MulAmt % 5) == 0) { 13307 MulAmt1 = 5; 13308 MulAmt2 = MulAmt / 5; 13309 } else if ((MulAmt % 3) == 0) { 13310 MulAmt1 = 3; 13311 MulAmt2 = MulAmt / 3; 13312 } 13313 if (MulAmt2 && 13314 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13315 DebugLoc DL = N->getDebugLoc(); 13316 13317 if (isPowerOf2_64(MulAmt2) && 13318 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13319 // If second multiplifer is pow2, issue it first. We want the multiply by 13320 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13321 // is an add. 13322 std::swap(MulAmt1, MulAmt2); 13323 13324 SDValue NewMul; 13325 if (isPowerOf2_64(MulAmt1)) 13326 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13327 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13328 else 13329 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13330 DAG.getConstant(MulAmt1, VT)); 13331 13332 if (isPowerOf2_64(MulAmt2)) 13333 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13334 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13335 else 13336 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13337 DAG.getConstant(MulAmt2, VT)); 13338 13339 // Do not add new nodes to DAG combiner worklist. 13340 DCI.CombineTo(N, NewMul, false); 13341 } 13342 return SDValue(); 13343} 13344 13345static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13346 SDValue N0 = N->getOperand(0); 13347 SDValue N1 = N->getOperand(1); 13348 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13349 EVT VT = N0.getValueType(); 13350 13351 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13352 // since the result of setcc_c is all zero's or all ones. 13353 if (VT.isInteger() && !VT.isVector() && 13354 N1C && N0.getOpcode() == ISD::AND && 13355 N0.getOperand(1).getOpcode() == ISD::Constant) { 13356 SDValue N00 = N0.getOperand(0); 13357 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13358 ((N00.getOpcode() == ISD::ANY_EXTEND || 13359 N00.getOpcode() == ISD::ZERO_EXTEND) && 13360 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13361 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13362 APInt ShAmt = N1C->getAPIntValue(); 13363 Mask = Mask.shl(ShAmt); 13364 if (Mask != 0) 13365 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13366 N00, DAG.getConstant(Mask, VT)); 13367 } 13368 } 13369 13370 13371 // Hardware support for vector shifts is sparse which makes us scalarize the 13372 // vector operations in many cases. Also, on sandybridge ADD is faster than 13373 // shl. 13374 // (shl V, 1) -> add V,V 13375 if (isSplatVector(N1.getNode())) { 13376 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13378 // We shift all of the values by one. In many cases we do not have 13379 // hardware support for this operation. This is better expressed as an ADD 13380 // of two values. 13381 if (N1C && (1 == N1C->getZExtValue())) { 13382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13383 } 13384 } 13385 13386 return SDValue(); 13387} 13388 13389/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13390/// when possible. 13391static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13392 const X86Subtarget *Subtarget) { 13393 EVT VT = N->getValueType(0); 13394 if (N->getOpcode() == ISD::SHL) { 13395 SDValue V = PerformSHLCombine(N, DAG); 13396 if (V.getNode()) return V; 13397 } 13398 13399 // On X86 with SSE2 support, we can transform this to a vector shift if 13400 // all elements are shifted by the same amount. We can't do this in legalize 13401 // because the a constant vector is typically transformed to a constant pool 13402 // so we have no knowledge of the shift amount. 13403 if (!Subtarget->hasSSE2()) 13404 return SDValue(); 13405 13406 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13407 (!Subtarget->hasAVX2() || 13408 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13409 return SDValue(); 13410 13411 SDValue ShAmtOp = N->getOperand(1); 13412 EVT EltVT = VT.getVectorElementType(); 13413 DebugLoc DL = N->getDebugLoc(); 13414 SDValue BaseShAmt = SDValue(); 13415 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13416 unsigned NumElts = VT.getVectorNumElements(); 13417 unsigned i = 0; 13418 for (; i != NumElts; ++i) { 13419 SDValue Arg = ShAmtOp.getOperand(i); 13420 if (Arg.getOpcode() == ISD::UNDEF) continue; 13421 BaseShAmt = Arg; 13422 break; 13423 } 13424 for (; i != NumElts; ++i) { 13425 SDValue Arg = ShAmtOp.getOperand(i); 13426 if (Arg.getOpcode() == ISD::UNDEF) continue; 13427 if (Arg != BaseShAmt) { 13428 return SDValue(); 13429 } 13430 } 13431 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13432 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13433 SDValue InVec = ShAmtOp.getOperand(0); 13434 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13435 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13436 unsigned i = 0; 13437 for (; i != NumElts; ++i) { 13438 SDValue Arg = InVec.getOperand(i); 13439 if (Arg.getOpcode() == ISD::UNDEF) continue; 13440 BaseShAmt = Arg; 13441 break; 13442 } 13443 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13445 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13446 if (C->getZExtValue() == SplatIdx) 13447 BaseShAmt = InVec.getOperand(1); 13448 } 13449 } 13450 if (BaseShAmt.getNode() == 0) 13451 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13452 DAG.getIntPtrConstant(0)); 13453 } else 13454 return SDValue(); 13455 13456 // The shift amount is an i32. 13457 if (EltVT.bitsGT(MVT::i32)) 13458 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13459 else if (EltVT.bitsLT(MVT::i32)) 13460 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13461 13462 // The shift amount is identical so we can do a vector shift. 13463 SDValue ValOp = N->getOperand(0); 13464 switch (N->getOpcode()) { 13465 default: 13466 llvm_unreachable("Unknown shift opcode!"); 13467 break; 13468 case ISD::SHL: 13469 if (VT == MVT::v2i64) 13470 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13471 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13472 ValOp, BaseShAmt); 13473 if (VT == MVT::v4i32) 13474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13475 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13476 ValOp, BaseShAmt); 13477 if (VT == MVT::v8i16) 13478 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13479 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13480 ValOp, BaseShAmt); 13481 if (VT == MVT::v4i64) 13482 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13483 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 13484 ValOp, BaseShAmt); 13485 if (VT == MVT::v8i32) 13486 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13487 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 13488 ValOp, BaseShAmt); 13489 if (VT == MVT::v16i16) 13490 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13491 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 13492 ValOp, BaseShAmt); 13493 break; 13494 case ISD::SRA: 13495 if (VT == MVT::v4i32) 13496 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13497 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13498 ValOp, BaseShAmt); 13499 if (VT == MVT::v8i16) 13500 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13501 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13502 ValOp, BaseShAmt); 13503 if (VT == MVT::v8i32) 13504 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13505 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 13506 ValOp, BaseShAmt); 13507 if (VT == MVT::v16i16) 13508 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13509 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 13510 ValOp, BaseShAmt); 13511 break; 13512 case ISD::SRL: 13513 if (VT == MVT::v2i64) 13514 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13515 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13516 ValOp, BaseShAmt); 13517 if (VT == MVT::v4i32) 13518 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13519 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13520 ValOp, BaseShAmt); 13521 if (VT == MVT::v8i16) 13522 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13523 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13524 ValOp, BaseShAmt); 13525 if (VT == MVT::v4i64) 13526 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13527 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 13528 ValOp, BaseShAmt); 13529 if (VT == MVT::v8i32) 13530 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13531 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 13532 ValOp, BaseShAmt); 13533 if (VT == MVT::v16i16) 13534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13535 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 13536 ValOp, BaseShAmt); 13537 break; 13538 } 13539 return SDValue(); 13540} 13541 13542 13543// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13544// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13545// and friends. Likewise for OR -> CMPNEQSS. 13546static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13547 TargetLowering::DAGCombinerInfo &DCI, 13548 const X86Subtarget *Subtarget) { 13549 unsigned opcode; 13550 13551 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13552 // we're requiring SSE2 for both. 13553 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13554 SDValue N0 = N->getOperand(0); 13555 SDValue N1 = N->getOperand(1); 13556 SDValue CMP0 = N0->getOperand(1); 13557 SDValue CMP1 = N1->getOperand(1); 13558 DebugLoc DL = N->getDebugLoc(); 13559 13560 // The SETCCs should both refer to the same CMP. 13561 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13562 return SDValue(); 13563 13564 SDValue CMP00 = CMP0->getOperand(0); 13565 SDValue CMP01 = CMP0->getOperand(1); 13566 EVT VT = CMP00.getValueType(); 13567 13568 if (VT == MVT::f32 || VT == MVT::f64) { 13569 bool ExpectingFlags = false; 13570 // Check for any users that want flags: 13571 for (SDNode::use_iterator UI = N->use_begin(), 13572 UE = N->use_end(); 13573 !ExpectingFlags && UI != UE; ++UI) 13574 switch (UI->getOpcode()) { 13575 default: 13576 case ISD::BR_CC: 13577 case ISD::BRCOND: 13578 case ISD::SELECT: 13579 ExpectingFlags = true; 13580 break; 13581 case ISD::CopyToReg: 13582 case ISD::SIGN_EXTEND: 13583 case ISD::ZERO_EXTEND: 13584 case ISD::ANY_EXTEND: 13585 break; 13586 } 13587 13588 if (!ExpectingFlags) { 13589 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13590 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13591 13592 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13593 X86::CondCode tmp = cc0; 13594 cc0 = cc1; 13595 cc1 = tmp; 13596 } 13597 13598 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13599 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13600 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13601 X86ISD::NodeType NTOperator = is64BitFP ? 13602 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13603 // FIXME: need symbolic constants for these magic numbers. 13604 // See X86ATTInstPrinter.cpp:printSSECC(). 13605 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13606 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13607 DAG.getConstant(x86cc, MVT::i8)); 13608 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13609 OnesOrZeroesF); 13610 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13611 DAG.getConstant(1, MVT::i32)); 13612 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13613 return OneBitOfTruth; 13614 } 13615 } 13616 } 13617 } 13618 return SDValue(); 13619} 13620 13621/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13622/// so it can be folded inside ANDNP. 13623static bool CanFoldXORWithAllOnes(const SDNode *N) { 13624 EVT VT = N->getValueType(0); 13625 13626 // Match direct AllOnes for 128 and 256-bit vectors 13627 if (ISD::isBuildVectorAllOnes(N)) 13628 return true; 13629 13630 // Look through a bit convert. 13631 if (N->getOpcode() == ISD::BITCAST) 13632 N = N->getOperand(0).getNode(); 13633 13634 // Sometimes the operand may come from a insert_subvector building a 256-bit 13635 // allones vector 13636 if (VT.getSizeInBits() == 256 && 13637 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13638 SDValue V1 = N->getOperand(0); 13639 SDValue V2 = N->getOperand(1); 13640 13641 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13642 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13643 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13644 ISD::isBuildVectorAllOnes(V2.getNode())) 13645 return true; 13646 } 13647 13648 return false; 13649} 13650 13651static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13652 TargetLowering::DAGCombinerInfo &DCI, 13653 const X86Subtarget *Subtarget) { 13654 if (DCI.isBeforeLegalizeOps()) 13655 return SDValue(); 13656 13657 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13658 if (R.getNode()) 13659 return R; 13660 13661 EVT VT = N->getValueType(0); 13662 13663 // Create ANDN, BLSI, and BLSR instructions 13664 // BLSI is X & (-X) 13665 // BLSR is X & (X-1) 13666 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13667 SDValue N0 = N->getOperand(0); 13668 SDValue N1 = N->getOperand(1); 13669 DebugLoc DL = N->getDebugLoc(); 13670 13671 // Check LHS for not 13672 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13673 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13674 // Check RHS for not 13675 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13676 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13677 13678 // Check LHS for neg 13679 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13680 isZero(N0.getOperand(0))) 13681 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13682 13683 // Check RHS for neg 13684 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13685 isZero(N1.getOperand(0))) 13686 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13687 13688 // Check LHS for X-1 13689 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13690 isAllOnes(N0.getOperand(1))) 13691 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13692 13693 // Check RHS for X-1 13694 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13695 isAllOnes(N1.getOperand(1))) 13696 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13697 13698 return SDValue(); 13699 } 13700 13701 // Want to form ANDNP nodes: 13702 // 1) In the hopes of then easily combining them with OR and AND nodes 13703 // to form PBLEND/PSIGN. 13704 // 2) To match ANDN packed intrinsics 13705 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13706 return SDValue(); 13707 13708 SDValue N0 = N->getOperand(0); 13709 SDValue N1 = N->getOperand(1); 13710 DebugLoc DL = N->getDebugLoc(); 13711 13712 // Check LHS for vnot 13713 if (N0.getOpcode() == ISD::XOR && 13714 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13715 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13716 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13717 13718 // Check RHS for vnot 13719 if (N1.getOpcode() == ISD::XOR && 13720 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13721 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13722 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13723 13724 return SDValue(); 13725} 13726 13727static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13728 TargetLowering::DAGCombinerInfo &DCI, 13729 const X86Subtarget *Subtarget) { 13730 if (DCI.isBeforeLegalizeOps()) 13731 return SDValue(); 13732 13733 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13734 if (R.getNode()) 13735 return R; 13736 13737 EVT VT = N->getValueType(0); 13738 13739 SDValue N0 = N->getOperand(0); 13740 SDValue N1 = N->getOperand(1); 13741 13742 // look for psign/blend 13743 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13744 if (!Subtarget->hasSSSE3() || 13745 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13746 return SDValue(); 13747 13748 // Canonicalize pandn to RHS 13749 if (N0.getOpcode() == X86ISD::ANDNP) 13750 std::swap(N0, N1); 13751 // or (and (m, y), (pandn m, x)) 13752 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13753 SDValue Mask = N1.getOperand(0); 13754 SDValue X = N1.getOperand(1); 13755 SDValue Y; 13756 if (N0.getOperand(0) == Mask) 13757 Y = N0.getOperand(1); 13758 if (N0.getOperand(1) == Mask) 13759 Y = N0.getOperand(0); 13760 13761 // Check to see if the mask appeared in both the AND and ANDNP and 13762 if (!Y.getNode()) 13763 return SDValue(); 13764 13765 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13766 if (Mask.getOpcode() != ISD::BITCAST || 13767 X.getOpcode() != ISD::BITCAST || 13768 Y.getOpcode() != ISD::BITCAST) 13769 return SDValue(); 13770 13771 // Look through mask bitcast. 13772 Mask = Mask.getOperand(0); 13773 EVT MaskVT = Mask.getValueType(); 13774 13775 // Validate that the Mask operand is a vector sra node. The sra node 13776 // will be an intrinsic. 13777 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13778 return SDValue(); 13779 13780 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13781 // there is no psrai.b 13782 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13783 case Intrinsic::x86_sse2_psrai_w: 13784 case Intrinsic::x86_sse2_psrai_d: 13785 case Intrinsic::x86_avx2_psrai_w: 13786 case Intrinsic::x86_avx2_psrai_d: 13787 break; 13788 default: return SDValue(); 13789 } 13790 13791 // Check that the SRA is all signbits. 13792 SDValue SraC = Mask.getOperand(2); 13793 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13794 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13795 if ((SraAmt + 1) != EltBits) 13796 return SDValue(); 13797 13798 DebugLoc DL = N->getDebugLoc(); 13799 13800 // Now we know we at least have a plendvb with the mask val. See if 13801 // we can form a psignb/w/d. 13802 // psign = x.type == y.type == mask.type && y = sub(0, x); 13803 X = X.getOperand(0); 13804 Y = Y.getOperand(0); 13805 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13806 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13807 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() && 13808 (EltBits == 8 || EltBits == 16 || EltBits == 32)) { 13809 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, 13810 Mask.getOperand(1)); 13811 return DAG.getNode(ISD::BITCAST, DL, VT, Sign); 13812 } 13813 // PBLENDVB only available on SSE 4.1 13814 if (!Subtarget->hasSSE41()) 13815 return SDValue(); 13816 13817 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13818 13819 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13820 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13821 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13822 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13823 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13824 } 13825 } 13826 13827 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13828 return SDValue(); 13829 13830 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13831 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13832 std::swap(N0, N1); 13833 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13834 return SDValue(); 13835 if (!N0.hasOneUse() || !N1.hasOneUse()) 13836 return SDValue(); 13837 13838 SDValue ShAmt0 = N0.getOperand(1); 13839 if (ShAmt0.getValueType() != MVT::i8) 13840 return SDValue(); 13841 SDValue ShAmt1 = N1.getOperand(1); 13842 if (ShAmt1.getValueType() != MVT::i8) 13843 return SDValue(); 13844 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13845 ShAmt0 = ShAmt0.getOperand(0); 13846 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13847 ShAmt1 = ShAmt1.getOperand(0); 13848 13849 DebugLoc DL = N->getDebugLoc(); 13850 unsigned Opc = X86ISD::SHLD; 13851 SDValue Op0 = N0.getOperand(0); 13852 SDValue Op1 = N1.getOperand(0); 13853 if (ShAmt0.getOpcode() == ISD::SUB) { 13854 Opc = X86ISD::SHRD; 13855 std::swap(Op0, Op1); 13856 std::swap(ShAmt0, ShAmt1); 13857 } 13858 13859 unsigned Bits = VT.getSizeInBits(); 13860 if (ShAmt1.getOpcode() == ISD::SUB) { 13861 SDValue Sum = ShAmt1.getOperand(0); 13862 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13863 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13864 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13865 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13866 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13867 return DAG.getNode(Opc, DL, VT, 13868 Op0, Op1, 13869 DAG.getNode(ISD::TRUNCATE, DL, 13870 MVT::i8, ShAmt0)); 13871 } 13872 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13873 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13874 if (ShAmt0C && 13875 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13876 return DAG.getNode(Opc, DL, VT, 13877 N0.getOperand(0), N1.getOperand(0), 13878 DAG.getNode(ISD::TRUNCATE, DL, 13879 MVT::i8, ShAmt0)); 13880 } 13881 13882 return SDValue(); 13883} 13884 13885// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 13886static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 13887 TargetLowering::DAGCombinerInfo &DCI, 13888 const X86Subtarget *Subtarget) { 13889 if (DCI.isBeforeLegalizeOps()) 13890 return SDValue(); 13891 13892 EVT VT = N->getValueType(0); 13893 13894 if (VT != MVT::i32 && VT != MVT::i64) 13895 return SDValue(); 13896 13897 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 13898 13899 // Create BLSMSK instructions by finding X ^ (X-1) 13900 SDValue N0 = N->getOperand(0); 13901 SDValue N1 = N->getOperand(1); 13902 DebugLoc DL = N->getDebugLoc(); 13903 13904 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13905 isAllOnes(N0.getOperand(1))) 13906 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 13907 13908 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13909 isAllOnes(N1.getOperand(1))) 13910 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 13911 13912 return SDValue(); 13913} 13914 13915/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13916static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13917 const X86Subtarget *Subtarget) { 13918 LoadSDNode *Ld = cast<LoadSDNode>(N); 13919 EVT RegVT = Ld->getValueType(0); 13920 EVT MemVT = Ld->getMemoryVT(); 13921 DebugLoc dl = Ld->getDebugLoc(); 13922 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13923 13924 ISD::LoadExtType Ext = Ld->getExtensionType(); 13925 13926 // If this is a vector EXT Load then attempt to optimize it using a 13927 // shuffle. We need SSE4 for the shuffles. 13928 // TODO: It is possible to support ZExt by zeroing the undef values 13929 // during the shuffle phase or after the shuffle. 13930 if (RegVT.isVector() && RegVT.isInteger() && 13931 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13932 assert(MemVT != RegVT && "Cannot extend to the same type"); 13933 assert(MemVT.isVector() && "Must load a vector from memory"); 13934 13935 unsigned NumElems = RegVT.getVectorNumElements(); 13936 unsigned RegSz = RegVT.getSizeInBits(); 13937 unsigned MemSz = MemVT.getSizeInBits(); 13938 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13939 // All sizes must be a power of two 13940 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13941 13942 // Attempt to load the original value using a single load op. 13943 // Find a scalar type which is equal to the loaded word size. 13944 MVT SclrLoadTy = MVT::i8; 13945 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13946 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13947 MVT Tp = (MVT::SimpleValueType)tp; 13948 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13949 SclrLoadTy = Tp; 13950 break; 13951 } 13952 } 13953 13954 // Proceed if a load word is found. 13955 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13956 13957 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13958 RegSz/SclrLoadTy.getSizeInBits()); 13959 13960 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13961 RegSz/MemVT.getScalarType().getSizeInBits()); 13962 // Can't shuffle using an illegal type. 13963 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13964 13965 // Perform a single load. 13966 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13967 Ld->getBasePtr(), 13968 Ld->getPointerInfo(), Ld->isVolatile(), 13969 Ld->isNonTemporal(), Ld->isInvariant(), 13970 Ld->getAlignment()); 13971 13972 // Insert the word loaded into a vector. 13973 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13974 LoadUnitVecVT, ScalarLoad); 13975 13976 // Bitcast the loaded value to a vector of the original element type, in 13977 // the size of the target vector type. 13978 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 13979 ScalarInVector); 13980 unsigned SizeRatio = RegSz/MemSz; 13981 13982 // Redistribute the loaded elements into the different locations. 13983 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13984 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 13985 13986 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 13987 DAG.getUNDEF(SlicedVec.getValueType()), 13988 ShuffleVec.data()); 13989 13990 // Bitcast to the requested type. 13991 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 13992 // Replace the original load with the new sequence 13993 // and return the new chain. 13994 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 13995 return SDValue(ScalarLoad.getNode(), 1); 13996 } 13997 13998 return SDValue(); 13999} 14000 14001/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14002static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14003 const X86Subtarget *Subtarget) { 14004 StoreSDNode *St = cast<StoreSDNode>(N); 14005 EVT VT = St->getValue().getValueType(); 14006 EVT StVT = St->getMemoryVT(); 14007 DebugLoc dl = St->getDebugLoc(); 14008 SDValue StoredVal = St->getOperand(1); 14009 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14010 14011 // If we are saving a concatenation of two XMM registers, perform two stores. 14012 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14013 // 128-bit ones. If in the future the cost becomes only one memory access the 14014 // first version would be better. 14015 if (VT.getSizeInBits() == 256 && 14016 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14017 StoredVal.getNumOperands() == 2) { 14018 14019 SDValue Value0 = StoredVal.getOperand(0); 14020 SDValue Value1 = StoredVal.getOperand(1); 14021 14022 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14023 SDValue Ptr0 = St->getBasePtr(); 14024 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14025 14026 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14027 St->getPointerInfo(), St->isVolatile(), 14028 St->isNonTemporal(), St->getAlignment()); 14029 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14030 St->getPointerInfo(), St->isVolatile(), 14031 St->isNonTemporal(), St->getAlignment()); 14032 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14033 } 14034 14035 // Optimize trunc store (of multiple scalars) to shuffle and store. 14036 // First, pack all of the elements in one place. Next, store to memory 14037 // in fewer chunks. 14038 if (St->isTruncatingStore() && VT.isVector()) { 14039 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14040 unsigned NumElems = VT.getVectorNumElements(); 14041 assert(StVT != VT && "Cannot truncate to the same type"); 14042 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14043 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14044 14045 // From, To sizes and ElemCount must be pow of two 14046 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14047 // We are going to use the original vector elt for storing. 14048 // Accumulated smaller vector elements must be a multiple of the store size. 14049 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14050 14051 unsigned SizeRatio = FromSz / ToSz; 14052 14053 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14054 14055 // Create a type on which we perform the shuffle 14056 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14057 StVT.getScalarType(), NumElems*SizeRatio); 14058 14059 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14060 14061 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14062 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14063 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14064 14065 // Can't shuffle using an illegal type 14066 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14067 14068 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14069 DAG.getUNDEF(WideVec.getValueType()), 14070 ShuffleVec.data()); 14071 // At this point all of the data is stored at the bottom of the 14072 // register. We now need to save it to mem. 14073 14074 // Find the largest store unit 14075 MVT StoreType = MVT::i8; 14076 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14077 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14078 MVT Tp = (MVT::SimpleValueType)tp; 14079 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14080 StoreType = Tp; 14081 } 14082 14083 // Bitcast the original vector into a vector of store-size units 14084 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14085 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14086 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14087 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14088 SmallVector<SDValue, 8> Chains; 14089 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14090 TLI.getPointerTy()); 14091 SDValue Ptr = St->getBasePtr(); 14092 14093 // Perform one or more big stores into memory. 14094 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14095 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14096 StoreType, ShuffWide, 14097 DAG.getIntPtrConstant(i)); 14098 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14099 St->getPointerInfo(), St->isVolatile(), 14100 St->isNonTemporal(), St->getAlignment()); 14101 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14102 Chains.push_back(Ch); 14103 } 14104 14105 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14106 Chains.size()); 14107 } 14108 14109 14110 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14111 // the FP state in cases where an emms may be missing. 14112 // A preferable solution to the general problem is to figure out the right 14113 // places to insert EMMS. This qualifies as a quick hack. 14114 14115 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14116 if (VT.getSizeInBits() != 64) 14117 return SDValue(); 14118 14119 const Function *F = DAG.getMachineFunction().getFunction(); 14120 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14121 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14122 && Subtarget->hasSSE2(); 14123 if ((VT.isVector() || 14124 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14125 isa<LoadSDNode>(St->getValue()) && 14126 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14127 St->getChain().hasOneUse() && !St->isVolatile()) { 14128 SDNode* LdVal = St->getValue().getNode(); 14129 LoadSDNode *Ld = 0; 14130 int TokenFactorIndex = -1; 14131 SmallVector<SDValue, 8> Ops; 14132 SDNode* ChainVal = St->getChain().getNode(); 14133 // Must be a store of a load. We currently handle two cases: the load 14134 // is a direct child, and it's under an intervening TokenFactor. It is 14135 // possible to dig deeper under nested TokenFactors. 14136 if (ChainVal == LdVal) 14137 Ld = cast<LoadSDNode>(St->getChain()); 14138 else if (St->getValue().hasOneUse() && 14139 ChainVal->getOpcode() == ISD::TokenFactor) { 14140 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14141 if (ChainVal->getOperand(i).getNode() == LdVal) { 14142 TokenFactorIndex = i; 14143 Ld = cast<LoadSDNode>(St->getValue()); 14144 } else 14145 Ops.push_back(ChainVal->getOperand(i)); 14146 } 14147 } 14148 14149 if (!Ld || !ISD::isNormalLoad(Ld)) 14150 return SDValue(); 14151 14152 // If this is not the MMX case, i.e. we are just turning i64 load/store 14153 // into f64 load/store, avoid the transformation if there are multiple 14154 // uses of the loaded value. 14155 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14156 return SDValue(); 14157 14158 DebugLoc LdDL = Ld->getDebugLoc(); 14159 DebugLoc StDL = N->getDebugLoc(); 14160 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14161 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14162 // pair instead. 14163 if (Subtarget->is64Bit() || F64IsLegal) { 14164 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14165 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14166 Ld->getPointerInfo(), Ld->isVolatile(), 14167 Ld->isNonTemporal(), Ld->isInvariant(), 14168 Ld->getAlignment()); 14169 SDValue NewChain = NewLd.getValue(1); 14170 if (TokenFactorIndex != -1) { 14171 Ops.push_back(NewChain); 14172 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14173 Ops.size()); 14174 } 14175 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14176 St->getPointerInfo(), 14177 St->isVolatile(), St->isNonTemporal(), 14178 St->getAlignment()); 14179 } 14180 14181 // Otherwise, lower to two pairs of 32-bit loads / stores. 14182 SDValue LoAddr = Ld->getBasePtr(); 14183 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14184 DAG.getConstant(4, MVT::i32)); 14185 14186 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14187 Ld->getPointerInfo(), 14188 Ld->isVolatile(), Ld->isNonTemporal(), 14189 Ld->isInvariant(), Ld->getAlignment()); 14190 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14191 Ld->getPointerInfo().getWithOffset(4), 14192 Ld->isVolatile(), Ld->isNonTemporal(), 14193 Ld->isInvariant(), 14194 MinAlign(Ld->getAlignment(), 4)); 14195 14196 SDValue NewChain = LoLd.getValue(1); 14197 if (TokenFactorIndex != -1) { 14198 Ops.push_back(LoLd); 14199 Ops.push_back(HiLd); 14200 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14201 Ops.size()); 14202 } 14203 14204 LoAddr = St->getBasePtr(); 14205 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14206 DAG.getConstant(4, MVT::i32)); 14207 14208 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14209 St->getPointerInfo(), 14210 St->isVolatile(), St->isNonTemporal(), 14211 St->getAlignment()); 14212 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14213 St->getPointerInfo().getWithOffset(4), 14214 St->isVolatile(), 14215 St->isNonTemporal(), 14216 MinAlign(St->getAlignment(), 4)); 14217 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14218 } 14219 return SDValue(); 14220} 14221 14222/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14223/// and return the operands for the horizontal operation in LHS and RHS. A 14224/// horizontal operation performs the binary operation on successive elements 14225/// of its first operand, then on successive elements of its second operand, 14226/// returning the resulting values in a vector. For example, if 14227/// A = < float a0, float a1, float a2, float a3 > 14228/// and 14229/// B = < float b0, float b1, float b2, float b3 > 14230/// then the result of doing a horizontal operation on A and B is 14231/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14232/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14233/// A horizontal-op B, for some already available A and B, and if so then LHS is 14234/// set to A, RHS to B, and the routine returns 'true'. 14235/// Note that the binary operation should have the property that if one of the 14236/// operands is UNDEF then the result is UNDEF. 14237static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14238 // Look for the following pattern: if 14239 // A = < float a0, float a1, float a2, float a3 > 14240 // B = < float b0, float b1, float b2, float b3 > 14241 // and 14242 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14243 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14244 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14245 // which is A horizontal-op B. 14246 14247 // At least one of the operands should be a vector shuffle. 14248 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14249 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14250 return false; 14251 14252 EVT VT = LHS.getValueType(); 14253 14254 assert((VT.is128BitVector() || VT.is256BitVector()) && 14255 "Unsupported vector type for horizontal add/sub"); 14256 14257 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14258 // operate independently on 128-bit lanes. 14259 unsigned NumElts = VT.getVectorNumElements(); 14260 unsigned NumLanes = VT.getSizeInBits()/128; 14261 unsigned NumLaneElts = NumElts / NumLanes; 14262 assert((NumLaneElts % 2 == 0) && 14263 "Vector type should have an even number of elements in each lane"); 14264 unsigned HalfLaneElts = NumLaneElts/2; 14265 14266 // View LHS in the form 14267 // LHS = VECTOR_SHUFFLE A, B, LMask 14268 // If LHS is not a shuffle then pretend it is the shuffle 14269 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14270 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14271 // type VT. 14272 SDValue A, B; 14273 SmallVector<int, 16> LMask(NumElts); 14274 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14275 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14276 A = LHS.getOperand(0); 14277 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14278 B = LHS.getOperand(1); 14279 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 14280 } else { 14281 if (LHS.getOpcode() != ISD::UNDEF) 14282 A = LHS; 14283 for (unsigned i = 0; i != NumElts; ++i) 14284 LMask[i] = i; 14285 } 14286 14287 // Likewise, view RHS in the form 14288 // RHS = VECTOR_SHUFFLE C, D, RMask 14289 SDValue C, D; 14290 SmallVector<int, 16> RMask(NumElts); 14291 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14292 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14293 C = RHS.getOperand(0); 14294 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14295 D = RHS.getOperand(1); 14296 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 14297 } else { 14298 if (RHS.getOpcode() != ISD::UNDEF) 14299 C = RHS; 14300 for (unsigned i = 0; i != NumElts; ++i) 14301 RMask[i] = i; 14302 } 14303 14304 // Check that the shuffles are both shuffling the same vectors. 14305 if (!(A == C && B == D) && !(A == D && B == C)) 14306 return false; 14307 14308 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14309 if (!A.getNode() && !B.getNode()) 14310 return false; 14311 14312 // If A and B occur in reverse order in RHS, then "swap" them (which means 14313 // rewriting the mask). 14314 if (A != C) 14315 CommuteVectorShuffleMask(RMask, NumElts); 14316 14317 // At this point LHS and RHS are equivalent to 14318 // LHS = VECTOR_SHUFFLE A, B, LMask 14319 // RHS = VECTOR_SHUFFLE A, B, RMask 14320 // Check that the masks correspond to performing a horizontal operation. 14321 for (unsigned i = 0; i != NumElts; ++i) { 14322 int LIdx = LMask[i], RIdx = RMask[i]; 14323 14324 // Ignore any UNDEF components. 14325 if (LIdx < 0 || RIdx < 0 || 14326 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14327 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14328 continue; 14329 14330 // Check that successive elements are being operated on. If not, this is 14331 // not a horizontal operation. 14332 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14333 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14334 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14335 if (!(LIdx == Index && RIdx == Index + 1) && 14336 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14337 return false; 14338 } 14339 14340 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14341 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14342 return true; 14343} 14344 14345/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14346static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14347 const X86Subtarget *Subtarget) { 14348 EVT VT = N->getValueType(0); 14349 SDValue LHS = N->getOperand(0); 14350 SDValue RHS = N->getOperand(1); 14351 14352 // Try to synthesize horizontal adds from adds of shuffles. 14353 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14354 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14355 isHorizontalBinOp(LHS, RHS, true)) 14356 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14357 return SDValue(); 14358} 14359 14360/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14361static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14362 const X86Subtarget *Subtarget) { 14363 EVT VT = N->getValueType(0); 14364 SDValue LHS = N->getOperand(0); 14365 SDValue RHS = N->getOperand(1); 14366 14367 // Try to synthesize horizontal subs from subs of shuffles. 14368 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14369 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14370 isHorizontalBinOp(LHS, RHS, false)) 14371 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14372 return SDValue(); 14373} 14374 14375/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14376/// X86ISD::FXOR nodes. 14377static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14378 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14379 // F[X]OR(0.0, x) -> x 14380 // F[X]OR(x, 0.0) -> x 14381 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14382 if (C->getValueAPF().isPosZero()) 14383 return N->getOperand(1); 14384 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14385 if (C->getValueAPF().isPosZero()) 14386 return N->getOperand(0); 14387 return SDValue(); 14388} 14389 14390/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14391static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14392 // FAND(0.0, x) -> 0.0 14393 // FAND(x, 0.0) -> 0.0 14394 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14395 if (C->getValueAPF().isPosZero()) 14396 return N->getOperand(0); 14397 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14398 if (C->getValueAPF().isPosZero()) 14399 return N->getOperand(1); 14400 return SDValue(); 14401} 14402 14403static SDValue PerformBTCombine(SDNode *N, 14404 SelectionDAG &DAG, 14405 TargetLowering::DAGCombinerInfo &DCI) { 14406 // BT ignores high bits in the bit index operand. 14407 SDValue Op1 = N->getOperand(1); 14408 if (Op1.hasOneUse()) { 14409 unsigned BitWidth = Op1.getValueSizeInBits(); 14410 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14411 APInt KnownZero, KnownOne; 14412 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14413 !DCI.isBeforeLegalizeOps()); 14414 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14415 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14416 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14417 DCI.CommitTargetLoweringOpt(TLO); 14418 } 14419 return SDValue(); 14420} 14421 14422static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14423 SDValue Op = N->getOperand(0); 14424 if (Op.getOpcode() == ISD::BITCAST) 14425 Op = Op.getOperand(0); 14426 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14427 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14428 VT.getVectorElementType().getSizeInBits() == 14429 OpVT.getVectorElementType().getSizeInBits()) { 14430 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14431 } 14432 return SDValue(); 14433} 14434 14435static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14436 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14437 // (and (i32 x86isd::setcc_carry), 1) 14438 // This eliminates the zext. This transformation is necessary because 14439 // ISD::SETCC is always legalized to i8. 14440 DebugLoc dl = N->getDebugLoc(); 14441 SDValue N0 = N->getOperand(0); 14442 EVT VT = N->getValueType(0); 14443 if (N0.getOpcode() == ISD::AND && 14444 N0.hasOneUse() && 14445 N0.getOperand(0).hasOneUse()) { 14446 SDValue N00 = N0.getOperand(0); 14447 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14448 return SDValue(); 14449 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14450 if (!C || C->getZExtValue() != 1) 14451 return SDValue(); 14452 return DAG.getNode(ISD::AND, dl, VT, 14453 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14454 N00.getOperand(0), N00.getOperand(1)), 14455 DAG.getConstant(1, VT)); 14456 } 14457 14458 return SDValue(); 14459} 14460 14461// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14462static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14463 unsigned X86CC = N->getConstantOperandVal(0); 14464 SDValue EFLAG = N->getOperand(1); 14465 DebugLoc DL = N->getDebugLoc(); 14466 14467 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14468 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14469 // cases. 14470 if (X86CC == X86::COND_B) 14471 return DAG.getNode(ISD::AND, DL, MVT::i8, 14472 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14473 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14474 DAG.getConstant(1, MVT::i8)); 14475 14476 return SDValue(); 14477} 14478 14479static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14480 const X86TargetLowering *XTLI) { 14481 SDValue Op0 = N->getOperand(0); 14482 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14483 // a 32-bit target where SSE doesn't support i64->FP operations. 14484 if (Op0.getOpcode() == ISD::LOAD) { 14485 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14486 EVT VT = Ld->getValueType(0); 14487 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14488 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14489 !XTLI->getSubtarget()->is64Bit() && 14490 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14491 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14492 Ld->getChain(), Op0, DAG); 14493 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14494 return FILDChain; 14495 } 14496 } 14497 return SDValue(); 14498} 14499 14500// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14501static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14502 X86TargetLowering::DAGCombinerInfo &DCI) { 14503 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14504 // the result is either zero or one (depending on the input carry bit). 14505 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14506 if (X86::isZeroNode(N->getOperand(0)) && 14507 X86::isZeroNode(N->getOperand(1)) && 14508 // We don't have a good way to replace an EFLAGS use, so only do this when 14509 // dead right now. 14510 SDValue(N, 1).use_empty()) { 14511 DebugLoc DL = N->getDebugLoc(); 14512 EVT VT = N->getValueType(0); 14513 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14514 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14515 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14516 DAG.getConstant(X86::COND_B,MVT::i8), 14517 N->getOperand(2)), 14518 DAG.getConstant(1, VT)); 14519 return DCI.CombineTo(N, Res1, CarryOut); 14520 } 14521 14522 return SDValue(); 14523} 14524 14525// fold (add Y, (sete X, 0)) -> adc 0, Y 14526// (add Y, (setne X, 0)) -> sbb -1, Y 14527// (sub (sete X, 0), Y) -> sbb 0, Y 14528// (sub (setne X, 0), Y) -> adc -1, Y 14529static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14530 DebugLoc DL = N->getDebugLoc(); 14531 14532 // Look through ZExts. 14533 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14534 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14535 return SDValue(); 14536 14537 SDValue SetCC = Ext.getOperand(0); 14538 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14539 return SDValue(); 14540 14541 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14542 if (CC != X86::COND_E && CC != X86::COND_NE) 14543 return SDValue(); 14544 14545 SDValue Cmp = SetCC.getOperand(1); 14546 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14547 !X86::isZeroNode(Cmp.getOperand(1)) || 14548 !Cmp.getOperand(0).getValueType().isInteger()) 14549 return SDValue(); 14550 14551 SDValue CmpOp0 = Cmp.getOperand(0); 14552 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14553 DAG.getConstant(1, CmpOp0.getValueType())); 14554 14555 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14556 if (CC == X86::COND_NE) 14557 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14558 DL, OtherVal.getValueType(), OtherVal, 14559 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14560 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14561 DL, OtherVal.getValueType(), OtherVal, 14562 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14563} 14564 14565/// PerformADDCombine - Do target-specific dag combines on integer adds. 14566static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14567 const X86Subtarget *Subtarget) { 14568 EVT VT = N->getValueType(0); 14569 SDValue Op0 = N->getOperand(0); 14570 SDValue Op1 = N->getOperand(1); 14571 14572 // Try to synthesize horizontal adds from adds of shuffles. 14573 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14574 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) && 14575 isHorizontalBinOp(Op0, Op1, true)) 14576 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14577 14578 return OptimizeConditionalInDecrement(N, DAG); 14579} 14580 14581static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14582 const X86Subtarget *Subtarget) { 14583 SDValue Op0 = N->getOperand(0); 14584 SDValue Op1 = N->getOperand(1); 14585 14586 // X86 can't encode an immediate LHS of a sub. See if we can push the 14587 // negation into a preceding instruction. 14588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14589 // If the RHS of the sub is a XOR with one use and a constant, invert the 14590 // immediate. Then add one to the LHS of the sub so we can turn 14591 // X-Y -> X+~Y+1, saving one register. 14592 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14593 isa<ConstantSDNode>(Op1.getOperand(1))) { 14594 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14595 EVT VT = Op0.getValueType(); 14596 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14597 Op1.getOperand(0), 14598 DAG.getConstant(~XorC, VT)); 14599 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14600 DAG.getConstant(C->getAPIntValue()+1, VT)); 14601 } 14602 } 14603 14604 // Try to synthesize horizontal adds from adds of shuffles. 14605 EVT VT = N->getValueType(0); 14606 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14607 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14608 isHorizontalBinOp(Op0, Op1, true)) 14609 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14610 14611 return OptimizeConditionalInDecrement(N, DAG); 14612} 14613 14614SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14615 DAGCombinerInfo &DCI) const { 14616 SelectionDAG &DAG = DCI.DAG; 14617 switch (N->getOpcode()) { 14618 default: break; 14619 case ISD::EXTRACT_VECTOR_ELT: 14620 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14621 case ISD::VSELECT: 14622 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14623 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14624 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14625 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14626 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14627 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14628 case ISD::SHL: 14629 case ISD::SRA: 14630 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14631 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14632 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14633 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14634 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14635 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14636 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14637 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14638 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14639 case X86ISD::FXOR: 14640 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14641 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14642 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14643 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14644 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14645 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14646 case X86ISD::SHUFP: // Handle all target specific shuffles 14647 case X86ISD::PALIGN: 14648 case X86ISD::UNPCKH: 14649 case X86ISD::UNPCKL: 14650 case X86ISD::MOVHLPS: 14651 case X86ISD::MOVLHPS: 14652 case X86ISD::PSHUFD: 14653 case X86ISD::PSHUFHW: 14654 case X86ISD::PSHUFLW: 14655 case X86ISD::MOVSS: 14656 case X86ISD::MOVSD: 14657 case X86ISD::VPERMILP: 14658 case X86ISD::VPERM2X128: 14659 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14660 } 14661 14662 return SDValue(); 14663} 14664 14665/// isTypeDesirableForOp - Return true if the target has native support for 14666/// the specified value type and it is 'desirable' to use the type for the 14667/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14668/// instruction encodings are longer and some i16 instructions are slow. 14669bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14670 if (!isTypeLegal(VT)) 14671 return false; 14672 if (VT != MVT::i16) 14673 return true; 14674 14675 switch (Opc) { 14676 default: 14677 return true; 14678 case ISD::LOAD: 14679 case ISD::SIGN_EXTEND: 14680 case ISD::ZERO_EXTEND: 14681 case ISD::ANY_EXTEND: 14682 case ISD::SHL: 14683 case ISD::SRL: 14684 case ISD::SUB: 14685 case ISD::ADD: 14686 case ISD::MUL: 14687 case ISD::AND: 14688 case ISD::OR: 14689 case ISD::XOR: 14690 return false; 14691 } 14692} 14693 14694/// IsDesirableToPromoteOp - This method query the target whether it is 14695/// beneficial for dag combiner to promote the specified node. If true, it 14696/// should return the desired promotion type by reference. 14697bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14698 EVT VT = Op.getValueType(); 14699 if (VT != MVT::i16) 14700 return false; 14701 14702 bool Promote = false; 14703 bool Commute = false; 14704 switch (Op.getOpcode()) { 14705 default: break; 14706 case ISD::LOAD: { 14707 LoadSDNode *LD = cast<LoadSDNode>(Op); 14708 // If the non-extending load has a single use and it's not live out, then it 14709 // might be folded. 14710 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14711 Op.hasOneUse()*/) { 14712 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14713 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14714 // The only case where we'd want to promote LOAD (rather then it being 14715 // promoted as an operand is when it's only use is liveout. 14716 if (UI->getOpcode() != ISD::CopyToReg) 14717 return false; 14718 } 14719 } 14720 Promote = true; 14721 break; 14722 } 14723 case ISD::SIGN_EXTEND: 14724 case ISD::ZERO_EXTEND: 14725 case ISD::ANY_EXTEND: 14726 Promote = true; 14727 break; 14728 case ISD::SHL: 14729 case ISD::SRL: { 14730 SDValue N0 = Op.getOperand(0); 14731 // Look out for (store (shl (load), x)). 14732 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14733 return false; 14734 Promote = true; 14735 break; 14736 } 14737 case ISD::ADD: 14738 case ISD::MUL: 14739 case ISD::AND: 14740 case ISD::OR: 14741 case ISD::XOR: 14742 Commute = true; 14743 // fallthrough 14744 case ISD::SUB: { 14745 SDValue N0 = Op.getOperand(0); 14746 SDValue N1 = Op.getOperand(1); 14747 if (!Commute && MayFoldLoad(N1)) 14748 return false; 14749 // Avoid disabling potential load folding opportunities. 14750 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14751 return false; 14752 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14753 return false; 14754 Promote = true; 14755 } 14756 } 14757 14758 PVT = MVT::i32; 14759 return Promote; 14760} 14761 14762//===----------------------------------------------------------------------===// 14763// X86 Inline Assembly Support 14764//===----------------------------------------------------------------------===// 14765 14766namespace { 14767 // Helper to match a string separated by whitespace. 14768 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 14769 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 14770 14771 for (unsigned i = 0, e = args.size(); i != e; ++i) { 14772 StringRef piece(*args[i]); 14773 if (!s.startswith(piece)) // Check if the piece matches. 14774 return false; 14775 14776 s = s.substr(piece.size()); 14777 StringRef::size_type pos = s.find_first_not_of(" \t"); 14778 if (pos == 0) // We matched a prefix. 14779 return false; 14780 14781 s = s.substr(pos); 14782 } 14783 14784 return s.empty(); 14785 } 14786 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 14787} 14788 14789bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14790 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14791 14792 std::string AsmStr = IA->getAsmString(); 14793 14794 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14795 if (!Ty || Ty->getBitWidth() % 16 != 0) 14796 return false; 14797 14798 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14799 SmallVector<StringRef, 4> AsmPieces; 14800 SplitString(AsmStr, AsmPieces, ";\n"); 14801 14802 switch (AsmPieces.size()) { 14803 default: return false; 14804 case 1: 14805 // FIXME: this should verify that we are targeting a 486 or better. If not, 14806 // we will turn this bswap into something that will be lowered to logical 14807 // ops instead of emitting the bswap asm. For now, we don't support 486 or 14808 // lower so don't worry about this. 14809 // bswap $0 14810 if (matchAsm(AsmPieces[0], "bswap", "$0") || 14811 matchAsm(AsmPieces[0], "bswapl", "$0") || 14812 matchAsm(AsmPieces[0], "bswapq", "$0") || 14813 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 14814 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 14815 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 14816 // No need to check constraints, nothing other than the equivalent of 14817 // "=r,0" would be valid here. 14818 return IntrinsicLowering::LowerToByteSwap(CI); 14819 } 14820 14821 // rorw $$8, ${0:w} --> llvm.bswap.i16 14822 if (CI->getType()->isIntegerTy(16) && 14823 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14824 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 14825 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 14826 AsmPieces.clear(); 14827 const std::string &ConstraintsStr = IA->getConstraintString(); 14828 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14829 std::sort(AsmPieces.begin(), AsmPieces.end()); 14830 if (AsmPieces.size() == 4 && 14831 AsmPieces[0] == "~{cc}" && 14832 AsmPieces[1] == "~{dirflag}" && 14833 AsmPieces[2] == "~{flags}" && 14834 AsmPieces[3] == "~{fpsr}") 14835 return IntrinsicLowering::LowerToByteSwap(CI); 14836 } 14837 break; 14838 case 3: 14839 if (CI->getType()->isIntegerTy(32) && 14840 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14841 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 14842 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 14843 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 14844 AsmPieces.clear(); 14845 const std::string &ConstraintsStr = IA->getConstraintString(); 14846 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14847 std::sort(AsmPieces.begin(), AsmPieces.end()); 14848 if (AsmPieces.size() == 4 && 14849 AsmPieces[0] == "~{cc}" && 14850 AsmPieces[1] == "~{dirflag}" && 14851 AsmPieces[2] == "~{flags}" && 14852 AsmPieces[3] == "~{fpsr}") 14853 return IntrinsicLowering::LowerToByteSwap(CI); 14854 } 14855 14856 if (CI->getType()->isIntegerTy(64)) { 14857 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14858 if (Constraints.size() >= 2 && 14859 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14860 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14861 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14862 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 14863 matchAsm(AsmPieces[1], "bswap", "%edx") && 14864 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 14865 return IntrinsicLowering::LowerToByteSwap(CI); 14866 } 14867 } 14868 break; 14869 } 14870 return false; 14871} 14872 14873 14874 14875/// getConstraintType - Given a constraint letter, return the type of 14876/// constraint it is for this target. 14877X86TargetLowering::ConstraintType 14878X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14879 if (Constraint.size() == 1) { 14880 switch (Constraint[0]) { 14881 case 'R': 14882 case 'q': 14883 case 'Q': 14884 case 'f': 14885 case 't': 14886 case 'u': 14887 case 'y': 14888 case 'x': 14889 case 'Y': 14890 case 'l': 14891 return C_RegisterClass; 14892 case 'a': 14893 case 'b': 14894 case 'c': 14895 case 'd': 14896 case 'S': 14897 case 'D': 14898 case 'A': 14899 return C_Register; 14900 case 'I': 14901 case 'J': 14902 case 'K': 14903 case 'L': 14904 case 'M': 14905 case 'N': 14906 case 'G': 14907 case 'C': 14908 case 'e': 14909 case 'Z': 14910 return C_Other; 14911 default: 14912 break; 14913 } 14914 } 14915 return TargetLowering::getConstraintType(Constraint); 14916} 14917 14918/// Examine constraint type and operand type and determine a weight value. 14919/// This object must already have been set up with the operand type 14920/// and the current alternative constraint selected. 14921TargetLowering::ConstraintWeight 14922 X86TargetLowering::getSingleConstraintMatchWeight( 14923 AsmOperandInfo &info, const char *constraint) const { 14924 ConstraintWeight weight = CW_Invalid; 14925 Value *CallOperandVal = info.CallOperandVal; 14926 // If we don't have a value, we can't do a match, 14927 // but allow it at the lowest weight. 14928 if (CallOperandVal == NULL) 14929 return CW_Default; 14930 Type *type = CallOperandVal->getType(); 14931 // Look at the constraint type. 14932 switch (*constraint) { 14933 default: 14934 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14935 case 'R': 14936 case 'q': 14937 case 'Q': 14938 case 'a': 14939 case 'b': 14940 case 'c': 14941 case 'd': 14942 case 'S': 14943 case 'D': 14944 case 'A': 14945 if (CallOperandVal->getType()->isIntegerTy()) 14946 weight = CW_SpecificReg; 14947 break; 14948 case 'f': 14949 case 't': 14950 case 'u': 14951 if (type->isFloatingPointTy()) 14952 weight = CW_SpecificReg; 14953 break; 14954 case 'y': 14955 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14956 weight = CW_SpecificReg; 14957 break; 14958 case 'x': 14959 case 'Y': 14960 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 14961 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 14962 weight = CW_Register; 14963 break; 14964 case 'I': 14965 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14966 if (C->getZExtValue() <= 31) 14967 weight = CW_Constant; 14968 } 14969 break; 14970 case 'J': 14971 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14972 if (C->getZExtValue() <= 63) 14973 weight = CW_Constant; 14974 } 14975 break; 14976 case 'K': 14977 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14978 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 14979 weight = CW_Constant; 14980 } 14981 break; 14982 case 'L': 14983 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14984 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 14985 weight = CW_Constant; 14986 } 14987 break; 14988 case 'M': 14989 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14990 if (C->getZExtValue() <= 3) 14991 weight = CW_Constant; 14992 } 14993 break; 14994 case 'N': 14995 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14996 if (C->getZExtValue() <= 0xff) 14997 weight = CW_Constant; 14998 } 14999 break; 15000 case 'G': 15001 case 'C': 15002 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15003 weight = CW_Constant; 15004 } 15005 break; 15006 case 'e': 15007 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15008 if ((C->getSExtValue() >= -0x80000000LL) && 15009 (C->getSExtValue() <= 0x7fffffffLL)) 15010 weight = CW_Constant; 15011 } 15012 break; 15013 case 'Z': 15014 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15015 if (C->getZExtValue() <= 0xffffffff) 15016 weight = CW_Constant; 15017 } 15018 break; 15019 } 15020 return weight; 15021} 15022 15023/// LowerXConstraint - try to replace an X constraint, which matches anything, 15024/// with another that has more specific requirements based on the type of the 15025/// corresponding operand. 15026const char *X86TargetLowering:: 15027LowerXConstraint(EVT ConstraintVT) const { 15028 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15029 // 'f' like normal targets. 15030 if (ConstraintVT.isFloatingPoint()) { 15031 if (Subtarget->hasSSE2()) 15032 return "Y"; 15033 if (Subtarget->hasSSE1()) 15034 return "x"; 15035 } 15036 15037 return TargetLowering::LowerXConstraint(ConstraintVT); 15038} 15039 15040/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15041/// vector. If it is invalid, don't add anything to Ops. 15042void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15043 std::string &Constraint, 15044 std::vector<SDValue>&Ops, 15045 SelectionDAG &DAG) const { 15046 SDValue Result(0, 0); 15047 15048 // Only support length 1 constraints for now. 15049 if (Constraint.length() > 1) return; 15050 15051 char ConstraintLetter = Constraint[0]; 15052 switch (ConstraintLetter) { 15053 default: break; 15054 case 'I': 15055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15056 if (C->getZExtValue() <= 31) { 15057 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15058 break; 15059 } 15060 } 15061 return; 15062 case 'J': 15063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15064 if (C->getZExtValue() <= 63) { 15065 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15066 break; 15067 } 15068 } 15069 return; 15070 case 'K': 15071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15072 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15073 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15074 break; 15075 } 15076 } 15077 return; 15078 case 'N': 15079 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15080 if (C->getZExtValue() <= 255) { 15081 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15082 break; 15083 } 15084 } 15085 return; 15086 case 'e': { 15087 // 32-bit signed value 15088 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15089 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15090 C->getSExtValue())) { 15091 // Widen to 64 bits here to get it sign extended. 15092 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15093 break; 15094 } 15095 // FIXME gcc accepts some relocatable values here too, but only in certain 15096 // memory models; it's complicated. 15097 } 15098 return; 15099 } 15100 case 'Z': { 15101 // 32-bit unsigned value 15102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15103 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15104 C->getZExtValue())) { 15105 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15106 break; 15107 } 15108 } 15109 // FIXME gcc accepts some relocatable values here too, but only in certain 15110 // memory models; it's complicated. 15111 return; 15112 } 15113 case 'i': { 15114 // Literal immediates are always ok. 15115 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15116 // Widen to 64 bits here to get it sign extended. 15117 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15118 break; 15119 } 15120 15121 // In any sort of PIC mode addresses need to be computed at runtime by 15122 // adding in a register or some sort of table lookup. These can't 15123 // be used as immediates. 15124 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15125 return; 15126 15127 // If we are in non-pic codegen mode, we allow the address of a global (with 15128 // an optional displacement) to be used with 'i'. 15129 GlobalAddressSDNode *GA = 0; 15130 int64_t Offset = 0; 15131 15132 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15133 while (1) { 15134 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15135 Offset += GA->getOffset(); 15136 break; 15137 } else if (Op.getOpcode() == ISD::ADD) { 15138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15139 Offset += C->getZExtValue(); 15140 Op = Op.getOperand(0); 15141 continue; 15142 } 15143 } else if (Op.getOpcode() == ISD::SUB) { 15144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15145 Offset += -C->getZExtValue(); 15146 Op = Op.getOperand(0); 15147 continue; 15148 } 15149 } 15150 15151 // Otherwise, this isn't something we can handle, reject it. 15152 return; 15153 } 15154 15155 const GlobalValue *GV = GA->getGlobal(); 15156 // If we require an extra load to get this address, as in PIC mode, we 15157 // can't accept it. 15158 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15159 getTargetMachine()))) 15160 return; 15161 15162 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15163 GA->getValueType(0), Offset); 15164 break; 15165 } 15166 } 15167 15168 if (Result.getNode()) { 15169 Ops.push_back(Result); 15170 return; 15171 } 15172 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15173} 15174 15175std::pair<unsigned, const TargetRegisterClass*> 15176X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15177 EVT VT) const { 15178 // First, see if this is a constraint that directly corresponds to an LLVM 15179 // register class. 15180 if (Constraint.size() == 1) { 15181 // GCC Constraint Letters 15182 switch (Constraint[0]) { 15183 default: break; 15184 // TODO: Slight differences here in allocation order and leaving 15185 // RIP in the class. Do they matter any more here than they do 15186 // in the normal allocation? 15187 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15188 if (Subtarget->is64Bit()) { 15189 if (VT == MVT::i32 || VT == MVT::f32) 15190 return std::make_pair(0U, X86::GR32RegisterClass); 15191 else if (VT == MVT::i16) 15192 return std::make_pair(0U, X86::GR16RegisterClass); 15193 else if (VT == MVT::i8 || VT == MVT::i1) 15194 return std::make_pair(0U, X86::GR8RegisterClass); 15195 else if (VT == MVT::i64 || VT == MVT::f64) 15196 return std::make_pair(0U, X86::GR64RegisterClass); 15197 break; 15198 } 15199 // 32-bit fallthrough 15200 case 'Q': // Q_REGS 15201 if (VT == MVT::i32 || VT == MVT::f32) 15202 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15203 else if (VT == MVT::i16) 15204 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15205 else if (VT == MVT::i8 || VT == MVT::i1) 15206 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15207 else if (VT == MVT::i64) 15208 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15209 break; 15210 case 'r': // GENERAL_REGS 15211 case 'l': // INDEX_REGS 15212 if (VT == MVT::i8 || VT == MVT::i1) 15213 return std::make_pair(0U, X86::GR8RegisterClass); 15214 if (VT == MVT::i16) 15215 return std::make_pair(0U, X86::GR16RegisterClass); 15216 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15217 return std::make_pair(0U, X86::GR32RegisterClass); 15218 return std::make_pair(0U, X86::GR64RegisterClass); 15219 case 'R': // LEGACY_REGS 15220 if (VT == MVT::i8 || VT == MVT::i1) 15221 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15222 if (VT == MVT::i16) 15223 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15224 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15225 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15226 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15227 case 'f': // FP Stack registers. 15228 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15229 // value to the correct fpstack register class. 15230 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15231 return std::make_pair(0U, X86::RFP32RegisterClass); 15232 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15233 return std::make_pair(0U, X86::RFP64RegisterClass); 15234 return std::make_pair(0U, X86::RFP80RegisterClass); 15235 case 'y': // MMX_REGS if MMX allowed. 15236 if (!Subtarget->hasMMX()) break; 15237 return std::make_pair(0U, X86::VR64RegisterClass); 15238 case 'Y': // SSE_REGS if SSE2 allowed 15239 if (!Subtarget->hasSSE2()) break; 15240 // FALL THROUGH. 15241 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15242 if (!Subtarget->hasSSE1()) break; 15243 15244 switch (VT.getSimpleVT().SimpleTy) { 15245 default: break; 15246 // Scalar SSE types. 15247 case MVT::f32: 15248 case MVT::i32: 15249 return std::make_pair(0U, X86::FR32RegisterClass); 15250 case MVT::f64: 15251 case MVT::i64: 15252 return std::make_pair(0U, X86::FR64RegisterClass); 15253 // Vector types. 15254 case MVT::v16i8: 15255 case MVT::v8i16: 15256 case MVT::v4i32: 15257 case MVT::v2i64: 15258 case MVT::v4f32: 15259 case MVT::v2f64: 15260 return std::make_pair(0U, X86::VR128RegisterClass); 15261 // AVX types. 15262 case MVT::v32i8: 15263 case MVT::v16i16: 15264 case MVT::v8i32: 15265 case MVT::v4i64: 15266 case MVT::v8f32: 15267 case MVT::v4f64: 15268 return std::make_pair(0U, X86::VR256RegisterClass); 15269 15270 } 15271 break; 15272 } 15273 } 15274 15275 // Use the default implementation in TargetLowering to convert the register 15276 // constraint into a member of a register class. 15277 std::pair<unsigned, const TargetRegisterClass*> Res; 15278 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15279 15280 // Not found as a standard register? 15281 if (Res.second == 0) { 15282 // Map st(0) -> st(7) -> ST0 15283 if (Constraint.size() == 7 && Constraint[0] == '{' && 15284 tolower(Constraint[1]) == 's' && 15285 tolower(Constraint[2]) == 't' && 15286 Constraint[3] == '(' && 15287 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15288 Constraint[5] == ')' && 15289 Constraint[6] == '}') { 15290 15291 Res.first = X86::ST0+Constraint[4]-'0'; 15292 Res.second = X86::RFP80RegisterClass; 15293 return Res; 15294 } 15295 15296 // GCC allows "st(0)" to be called just plain "st". 15297 if (StringRef("{st}").equals_lower(Constraint)) { 15298 Res.first = X86::ST0; 15299 Res.second = X86::RFP80RegisterClass; 15300 return Res; 15301 } 15302 15303 // flags -> EFLAGS 15304 if (StringRef("{flags}").equals_lower(Constraint)) { 15305 Res.first = X86::EFLAGS; 15306 Res.second = X86::CCRRegisterClass; 15307 return Res; 15308 } 15309 15310 // 'A' means EAX + EDX. 15311 if (Constraint == "A") { 15312 Res.first = X86::EAX; 15313 Res.second = X86::GR32_ADRegisterClass; 15314 return Res; 15315 } 15316 return Res; 15317 } 15318 15319 // Otherwise, check to see if this is a register class of the wrong value 15320 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15321 // turn into {ax},{dx}. 15322 if (Res.second->hasType(VT)) 15323 return Res; // Correct type already, nothing to do. 15324 15325 // All of the single-register GCC register classes map their values onto 15326 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15327 // really want an 8-bit or 32-bit register, map to the appropriate register 15328 // class and return the appropriate register. 15329 if (Res.second == X86::GR16RegisterClass) { 15330 if (VT == MVT::i8) { 15331 unsigned DestReg = 0; 15332 switch (Res.first) { 15333 default: break; 15334 case X86::AX: DestReg = X86::AL; break; 15335 case X86::DX: DestReg = X86::DL; break; 15336 case X86::CX: DestReg = X86::CL; break; 15337 case X86::BX: DestReg = X86::BL; break; 15338 } 15339 if (DestReg) { 15340 Res.first = DestReg; 15341 Res.second = X86::GR8RegisterClass; 15342 } 15343 } else if (VT == MVT::i32) { 15344 unsigned DestReg = 0; 15345 switch (Res.first) { 15346 default: break; 15347 case X86::AX: DestReg = X86::EAX; break; 15348 case X86::DX: DestReg = X86::EDX; break; 15349 case X86::CX: DestReg = X86::ECX; break; 15350 case X86::BX: DestReg = X86::EBX; break; 15351 case X86::SI: DestReg = X86::ESI; break; 15352 case X86::DI: DestReg = X86::EDI; break; 15353 case X86::BP: DestReg = X86::EBP; break; 15354 case X86::SP: DestReg = X86::ESP; break; 15355 } 15356 if (DestReg) { 15357 Res.first = DestReg; 15358 Res.second = X86::GR32RegisterClass; 15359 } 15360 } else if (VT == MVT::i64) { 15361 unsigned DestReg = 0; 15362 switch (Res.first) { 15363 default: break; 15364 case X86::AX: DestReg = X86::RAX; break; 15365 case X86::DX: DestReg = X86::RDX; break; 15366 case X86::CX: DestReg = X86::RCX; break; 15367 case X86::BX: DestReg = X86::RBX; break; 15368 case X86::SI: DestReg = X86::RSI; break; 15369 case X86::DI: DestReg = X86::RDI; break; 15370 case X86::BP: DestReg = X86::RBP; break; 15371 case X86::SP: DestReg = X86::RSP; break; 15372 } 15373 if (DestReg) { 15374 Res.first = DestReg; 15375 Res.second = X86::GR64RegisterClass; 15376 } 15377 } 15378 } else if (Res.second == X86::FR32RegisterClass || 15379 Res.second == X86::FR64RegisterClass || 15380 Res.second == X86::VR128RegisterClass) { 15381 // Handle references to XMM physical registers that got mapped into the 15382 // wrong class. This can happen with constraints like {xmm0} where the 15383 // target independent register mapper will just pick the first match it can 15384 // find, ignoring the required type. 15385 if (VT == MVT::f32) 15386 Res.second = X86::FR32RegisterClass; 15387 else if (VT == MVT::f64) 15388 Res.second = X86::FR64RegisterClass; 15389 else if (X86::VR128RegisterClass->hasType(VT)) 15390 Res.second = X86::VR128RegisterClass; 15391 } 15392 15393 return Res; 15394} 15395