X86ISelLowering.cpp revision d40aa24ebf2e67ae0802d15e1ff20373c1e9dc2f
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/MC/MCAsmInfo.h" 40#include "llvm/MC/MCContext.h" 41#include "llvm/MC/MCExpr.h" 42#include "llvm/MC/MCSymbol.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/Support/CallSite.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX(); 172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 184 // For 64-bit since we have so many registers use the ILP scheduler, for 185 // 32-bit code use the register pressure specific scheduling. 186 if (Subtarget->is64Bit()) 187 setSchedulingPreference(Sched::ILP); 188 else 189 setSchedulingPreference(Sched::RegPressure); 190 setStackPointerRegisterToSaveRestore(X86StackPtr); 191 192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 193 // Setup Windows compiler runtime calls. 194 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 196 setLibcallName(RTLIB::SREM_I64, "_allrem"); 197 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 198 setLibcallName(RTLIB::MUL_I64, "_allmul"); 199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 208 } 209 210 if (Subtarget->isTargetDarwin()) { 211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 212 setUseUnderscoreSetJmp(false); 213 setUseUnderscoreLongJmp(false); 214 } else if (Subtarget->isTargetMingw()) { 215 // MS runtime is weird: it exports _setjmp, but longjmp! 216 setUseUnderscoreSetJmp(true); 217 setUseUnderscoreLongJmp(false); 218 } else { 219 setUseUnderscoreSetJmp(true); 220 setUseUnderscoreLongJmp(true); 221 } 222 223 // Set up the register classes. 224 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 225 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 226 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 227 if (Subtarget->is64Bit()) 228 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 229 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 231 232 // We don't accept any truncstore of integer registers. 233 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 234 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 236 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 239 240 // SETOEQ and SETUNE require checking two conditions. 241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 247 248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 249 // operation. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 253 254 if (Subtarget->is64Bit()) { 255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 257 } else if (!UseSoftFloat) { 258 // We have an algorithm for SSE2->double, and we turn this into a 259 // 64-bit FILD followed by conditional FADD for other targets. 260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 261 // We have an algorithm for SSE2, and we turn this into a 64-bit 262 // FILD for other targets. 263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 264 } 265 266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 267 // this operation. 268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 270 271 if (!UseSoftFloat) { 272 // SSE has no i16 to fp conversion, only i32 273 if (X86ScalarSSEf32) { 274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 275 // f32 and f64 cases are Legal, f80 case is not 276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 277 } else { 278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 280 } 281 } else { 282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 284 } 285 286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 287 // are Legal, f80 is custom lowered. 288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 290 291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 292 // this operation. 293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 295 296 if (X86ScalarSSEf32) { 297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 298 // f32 and f64 cases are Legal, f80 case is not 299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 300 } else { 301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 303 } 304 305 // Handle FP_TO_UINT by promoting the destination to a larger signed 306 // conversion. 307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 310 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 314 } else if (!UseSoftFloat) { 315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 316 // Expand FP_TO_UINT into a select. 317 // FIXME: We would like to use a Custom expander here eventually to do 318 // the optimal thing for SSE vs. the default expansion in the legalizer. 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 320 else 321 // With SSE3 we can use fisttpll to convert to a signed i64; without 322 // SSE, we're stuck with a fistpll. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 324 } 325 326 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 327 if (!X86ScalarSSEf64) { 328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 330 if (Subtarget->is64Bit()) { 331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 332 // Without SSE, i64->f64 goes through memory. 333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 334 } 335 } 336 337 // Scalar integer divide and remainder are lowered to use operations that 338 // produce two results, to match the available instructions. This exposes 339 // the two-result form to trivial CSE, which is able to combine x/y and x%y 340 // into a single instruction. 341 // 342 // Scalar integer multiply-high is also lowered to use two-result 343 // operations, to match the available instructions. However, plain multiply 344 // (low) operations are left as Legal, as there are single-result 345 // instructions for this in x86. Using the two-result multiply instructions 346 // when both high and low results are needed must be arranged by dagcombine. 347 for (unsigned i = 0, e = 4; i != e; ++i) { 348 MVT VT = IntVTs[i]; 349 setOperationAction(ISD::MULHS, VT, Expand); 350 setOperationAction(ISD::MULHU, VT, Expand); 351 setOperationAction(ISD::SDIV, VT, Expand); 352 setOperationAction(ISD::UDIV, VT, Expand); 353 setOperationAction(ISD::SREM, VT, Expand); 354 setOperationAction(ISD::UREM, VT, Expand); 355 356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 357 setOperationAction(ISD::ADDC, VT, Custom); 358 setOperationAction(ISD::ADDE, VT, Custom); 359 setOperationAction(ISD::SUBC, VT, Custom); 360 setOperationAction(ISD::SUBE, VT, Custom); 361 } 362 363 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 364 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 365 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 367 if (Subtarget->is64Bit()) 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 373 setOperationAction(ISD::FREM , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f64 , Expand); 375 setOperationAction(ISD::FREM , MVT::f80 , Expand); 376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 377 378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 384 if (Subtarget->is64Bit()) { 385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 387 } 388 389 if (Subtarget->hasPOPCNT()) { 390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 391 } else { 392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 395 if (Subtarget->is64Bit()) 396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 397 } 398 399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 401 402 // These should be promoted to a larger select which is supported. 403 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 404 // X86 wants to expand cmov itself. 405 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 406 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 407 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 408 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 409 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 410 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 411 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 412 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 413 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 414 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 415 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 416 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 417 if (Subtarget->is64Bit()) { 418 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 419 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 420 } 421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 422 423 // Darwin ABI issue. 424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 428 if (Subtarget->is64Bit()) 429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 432 if (Subtarget->is64Bit()) { 433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 438 } 439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 443 if (Subtarget->is64Bit()) { 444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 447 } 448 449 if (Subtarget->hasXMM()) 450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 451 452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 454 455 // On X86 and X86-64, atomic operations are lowered to locked instructions. 456 // Locked instructions, in turn, have implicit fence semantics (all memory 457 // operations are flushed before issuing the locked instruction, and they 458 // are not buffered), so we can fold away the common pattern of 459 // fence-atomic-fence. 460 setShouldFoldAtomicFences(true); 461 462 // Expand certain atomics 463 for (unsigned i = 0, e = 4; i != e; ++i) { 464 MVT VT = IntVTs[i]; 465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 467 } 468 469 if (!Subtarget->is64Bit()) { 470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 477 } 478 479 // FIXME - use subtarget debug flags 480 if (!Subtarget->isTargetDarwin() && 481 !Subtarget->isTargetELF() && 482 !Subtarget->isTargetCygMing()) { 483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 484 } 485 486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 490 if (Subtarget->is64Bit()) { 491 setExceptionPointerRegister(X86::RAX); 492 setExceptionSelectorRegister(X86::RDX); 493 } else { 494 setExceptionPointerRegister(X86::EAX); 495 setExceptionSelectorRegister(X86::EDX); 496 } 497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 499 500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 501 502 setOperationAction(ISD::TRAP, MVT::Other, Legal); 503 504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 505 setOperationAction(ISD::VASTART , MVT::Other, Custom); 506 setOperationAction(ISD::VAEND , MVT::Other, Expand); 507 if (Subtarget->is64Bit()) { 508 setOperationAction(ISD::VAARG , MVT::Other, Custom); 509 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 510 } else { 511 setOperationAction(ISD::VAARG , MVT::Other, Expand); 512 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 513 } 514 515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 517 setOperationAction(ISD::DYNAMIC_STACKALLOC, 518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), 519 (Subtarget->isTargetCOFF() 520 && !Subtarget->isTargetEnvMacho() 521 ? Custom : Expand)); 522 523 if (!UseSoftFloat && X86ScalarSSEf64) { 524 // f32 and f64 use SSE. 525 // Set up the FP register classes. 526 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 527 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 528 529 // Use ANDPD to simulate FABS. 530 setOperationAction(ISD::FABS , MVT::f64, Custom); 531 setOperationAction(ISD::FABS , MVT::f32, Custom); 532 533 // Use XORP to simulate FNEG. 534 setOperationAction(ISD::FNEG , MVT::f64, Custom); 535 setOperationAction(ISD::FNEG , MVT::f32, Custom); 536 537 // Use ANDPD and ORPD to simulate FCOPYSIGN. 538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 540 541 // Lower this to FGETSIGNx86 plus an AND. 542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 544 545 // We don't support sin/cos/fmod 546 setOperationAction(ISD::FSIN , MVT::f64, Expand); 547 setOperationAction(ISD::FCOS , MVT::f64, Expand); 548 setOperationAction(ISD::FSIN , MVT::f32, Expand); 549 setOperationAction(ISD::FCOS , MVT::f32, Expand); 550 551 // Expand FP immediates into loads from the stack, except for the special 552 // cases we handle. 553 addLegalFPImmediate(APFloat(+0.0)); // xorpd 554 addLegalFPImmediate(APFloat(+0.0f)); // xorps 555 } else if (!UseSoftFloat && X86ScalarSSEf32) { 556 // Use SSE for f32, x87 for f64. 557 // Set up the FP register classes. 558 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 560 561 // Use ANDPS to simulate FABS. 562 setOperationAction(ISD::FABS , MVT::f32, Custom); 563 564 // Use XORP to simulate FNEG. 565 setOperationAction(ISD::FNEG , MVT::f32, Custom); 566 567 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 568 569 // Use ANDPS and ORPS to simulate FCOPYSIGN. 570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 572 573 // We don't support sin/cos/fmod 574 setOperationAction(ISD::FSIN , MVT::f32, Expand); 575 setOperationAction(ISD::FCOS , MVT::f32, Expand); 576 577 // Special cases we handle for FP constants. 578 addLegalFPImmediate(APFloat(+0.0f)); // xorps 579 addLegalFPImmediate(APFloat(+0.0)); // FLD0 580 addLegalFPImmediate(APFloat(+1.0)); // FLD1 581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 583 584 if (!UnsafeFPMath) { 585 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 586 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 587 } 588 } else if (!UseSoftFloat) { 589 // f32 and f64 in x87. 590 // Set up the FP register classes. 591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 593 594 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 595 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 598 599 if (!UnsafeFPMath) { 600 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 601 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 602 } 603 addLegalFPImmediate(APFloat(+0.0)); // FLD0 604 addLegalFPImmediate(APFloat(+1.0)); // FLD1 605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 611 } 612 613 // We don't support FMA. 614 setOperationAction(ISD::FMA, MVT::f64, Expand); 615 setOperationAction(ISD::FMA, MVT::f32, Expand); 616 617 // Long double always uses X87. 618 if (!UseSoftFloat) { 619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 620 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 622 { 623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 624 addLegalFPImmediate(TmpFlt); // FLD0 625 TmpFlt.changeSign(); 626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 627 628 bool ignored; 629 APFloat TmpFlt2(+1.0); 630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 631 &ignored); 632 addLegalFPImmediate(TmpFlt2); // FLD1 633 TmpFlt2.changeSign(); 634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 635 } 636 637 if (!UnsafeFPMath) { 638 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 639 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 640 } 641 642 setOperationAction(ISD::FMA, MVT::f80, Expand); 643 } 644 645 // Always use a library call for pow. 646 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 647 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 648 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 649 650 setOperationAction(ISD::FLOG, MVT::f80, Expand); 651 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 652 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 653 setOperationAction(ISD::FEXP, MVT::f80, Expand); 654 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 655 656 // First set operation action for all vector types to either promote 657 // (for widening) or expand (for scalarization). Then we will selectively 658 // turn on ones that can be effectively codegen'd. 659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 717 setTruncStoreAction((MVT::SimpleValueType)VT, 718 (MVT::SimpleValueType)InnerVT, Expand); 719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 722 } 723 724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 725 // with -msoft-float, disable use of MMX as well. 726 if (!UseSoftFloat && Subtarget->hasMMX()) { 727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 728 // No operations on x86mmx supported, everything uses intrinsics. 729 } 730 731 // MMX-sized vectors (other than x86mmx) are expected to be expanded 732 // into smaller operations. 733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 737 setOperationAction(ISD::AND, MVT::v8i8, Expand); 738 setOperationAction(ISD::AND, MVT::v4i16, Expand); 739 setOperationAction(ISD::AND, MVT::v2i32, Expand); 740 setOperationAction(ISD::AND, MVT::v1i64, Expand); 741 setOperationAction(ISD::OR, MVT::v8i8, Expand); 742 setOperationAction(ISD::OR, MVT::v4i16, Expand); 743 setOperationAction(ISD::OR, MVT::v2i32, Expand); 744 setOperationAction(ISD::OR, MVT::v1i64, Expand); 745 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 746 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 747 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 748 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 762 763 if (!UseSoftFloat && Subtarget->hasXMM()) { 764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 765 766 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 778 } 779 780 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 782 783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 784 // registers cannot be used even for integer operations. 785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 789 790 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 791 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 792 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 793 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 794 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 795 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 796 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 797 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 798 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 799 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 800 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 806 807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 811 812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 817 818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 823 824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 826 EVT VT = (MVT::SimpleValueType)i; 827 // Do not attempt to custom lower non-power-of-2 vectors 828 if (!isPowerOf2_32(VT.getVectorNumElements())) 829 continue; 830 // Do not attempt to custom lower non-128-bit vectors 831 if (!VT.is128BitVector()) 832 continue; 833 setOperationAction(ISD::BUILD_VECTOR, 834 VT.getSimpleVT().SimpleTy, Custom); 835 setOperationAction(ISD::VECTOR_SHUFFLE, 836 VT.getSimpleVT().SimpleTy, Custom); 837 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 838 VT.getSimpleVT().SimpleTy, Custom); 839 } 840 841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 847 848 if (Subtarget->is64Bit()) { 849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 851 } 852 853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 856 EVT VT = SVT; 857 858 // Do not attempt to promote non-128-bit vectors 859 if (!VT.is128BitVector()) 860 continue; 861 862 setOperationAction(ISD::AND, SVT, Promote); 863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 864 setOperationAction(ISD::OR, SVT, Promote); 865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 866 setOperationAction(ISD::XOR, SVT, Promote); 867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 868 setOperationAction(ISD::LOAD, SVT, Promote); 869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 870 setOperationAction(ISD::SELECT, SVT, Promote); 871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 872 } 873 874 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 875 876 // Custom lower v2i64 and v2f64 selects. 877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 881 882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 884 } 885 886 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 888 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 890 setOperationAction(ISD::FRINT, MVT::f32, Legal); 891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 893 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 895 setOperationAction(ISD::FRINT, MVT::f64, Legal); 896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 897 898 // FIXME: Do we need to handle scalar-to-vector here? 899 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 900 901 // Can turn SHL into an integer multiply. 902 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 903 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 904 905 // i8 and i16 vectors are custom , because the source register and source 906 // source memory operand types are not the same width. f32 vectors are 907 // custom since the immediate controlling the insert encodes additional 908 // information. 909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 913 914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 918 919 if (Subtarget->is64Bit()) { 920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 922 } 923 } 924 925 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) { 926 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 927 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 928 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 929 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 930 931 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 932 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 933 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 934 935 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 936 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 937 } 938 939 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 940 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 941 942 if (!UseSoftFloat && Subtarget->hasAVX()) { 943 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 944 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 945 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 946 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 947 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 948 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 949 950 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 951 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 952 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 953 954 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 955 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 956 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 957 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 958 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 959 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 960 961 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 962 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 963 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 964 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 965 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 966 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 967 968 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 969 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 970 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 971 972 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 973 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 978 979 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 980 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 981 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 982 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 983 984 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 985 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 987 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 988 989 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 990 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 991 992 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 993 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom); 994 995 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 996 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 997 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 998 999 // Custom lower several nodes for 256-bit types. 1000 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1001 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1002 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1003 EVT VT = SVT; 1004 1005 // Extract subvector is special because the value type 1006 // (result) is 128-bit but the source is 256-bit wide. 1007 if (VT.is128BitVector()) 1008 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1009 1010 // Do not attempt to custom lower other non-256-bit vectors 1011 if (!VT.is256BitVector()) 1012 continue; 1013 1014 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1015 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1016 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1018 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1019 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1020 } 1021 1022 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1023 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1024 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1025 EVT VT = SVT; 1026 1027 // Do not attempt to promote non-256-bit vectors 1028 if (!VT.is256BitVector()) 1029 continue; 1030 1031 setOperationAction(ISD::AND, SVT, Promote); 1032 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1033 setOperationAction(ISD::OR, SVT, Promote); 1034 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1035 setOperationAction(ISD::XOR, SVT, Promote); 1036 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1037 setOperationAction(ISD::LOAD, SVT, Promote); 1038 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1039 setOperationAction(ISD::SELECT, SVT, Promote); 1040 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1041 } 1042 } 1043 1044 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1045 // of this type with custom code. 1046 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1047 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1048 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1049 } 1050 1051 // We want to custom lower some of our intrinsics. 1052 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1053 1054 1055 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1056 // handle type legalization for these operations here. 1057 // 1058 // FIXME: We really should do custom legalization for addition and 1059 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1060 // than generic legalization for 64-bit multiplication-with-overflow, though. 1061 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1062 // Add/Sub/Mul with overflow operations are custom lowered. 1063 MVT VT = IntVTs[i]; 1064 setOperationAction(ISD::SADDO, VT, Custom); 1065 setOperationAction(ISD::UADDO, VT, Custom); 1066 setOperationAction(ISD::SSUBO, VT, Custom); 1067 setOperationAction(ISD::USUBO, VT, Custom); 1068 setOperationAction(ISD::SMULO, VT, Custom); 1069 setOperationAction(ISD::UMULO, VT, Custom); 1070 } 1071 1072 // There are no 8-bit 3-address imul/mul instructions 1073 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1074 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1075 1076 if (!Subtarget->is64Bit()) { 1077 // These libcalls are not available in 32-bit. 1078 setLibcallName(RTLIB::SHL_I128, 0); 1079 setLibcallName(RTLIB::SRL_I128, 0); 1080 setLibcallName(RTLIB::SRA_I128, 0); 1081 } 1082 1083 // We have target-specific dag combine patterns for the following nodes: 1084 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1085 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1086 setTargetDAGCombine(ISD::BUILD_VECTOR); 1087 setTargetDAGCombine(ISD::SELECT); 1088 setTargetDAGCombine(ISD::SHL); 1089 setTargetDAGCombine(ISD::SRA); 1090 setTargetDAGCombine(ISD::SRL); 1091 setTargetDAGCombine(ISD::OR); 1092 setTargetDAGCombine(ISD::AND); 1093 setTargetDAGCombine(ISD::ADD); 1094 setTargetDAGCombine(ISD::SUB); 1095 setTargetDAGCombine(ISD::STORE); 1096 setTargetDAGCombine(ISD::ZERO_EXTEND); 1097 setTargetDAGCombine(ISD::SINT_TO_FP); 1098 if (Subtarget->is64Bit()) 1099 setTargetDAGCombine(ISD::MUL); 1100 1101 computeRegisterProperties(); 1102 1103 // On Darwin, -Os means optimize for size without hurting performance, 1104 // do not reduce the limit. 1105 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1106 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1107 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1108 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1109 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1110 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1111 setPrefLoopAlignment(16); 1112 benefitFromCodePlacementOpt = true; 1113 1114 setPrefFunctionAlignment(4); 1115} 1116 1117 1118MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1119 return MVT::i8; 1120} 1121 1122 1123/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1124/// the desired ByVal argument alignment. 1125static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1126 if (MaxAlign == 16) 1127 return; 1128 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1129 if (VTy->getBitWidth() == 128) 1130 MaxAlign = 16; 1131 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1132 unsigned EltAlign = 0; 1133 getMaxByValAlign(ATy->getElementType(), EltAlign); 1134 if (EltAlign > MaxAlign) 1135 MaxAlign = EltAlign; 1136 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1137 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1138 unsigned EltAlign = 0; 1139 getMaxByValAlign(STy->getElementType(i), EltAlign); 1140 if (EltAlign > MaxAlign) 1141 MaxAlign = EltAlign; 1142 if (MaxAlign == 16) 1143 break; 1144 } 1145 } 1146 return; 1147} 1148 1149/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1150/// function arguments in the caller parameter area. For X86, aggregates 1151/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1152/// are at 4-byte boundaries. 1153unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1154 if (Subtarget->is64Bit()) { 1155 // Max of 8 and alignment of type. 1156 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1157 if (TyAlign > 8) 1158 return TyAlign; 1159 return 8; 1160 } 1161 1162 unsigned Align = 4; 1163 if (Subtarget->hasXMM()) 1164 getMaxByValAlign(Ty, Align); 1165 return Align; 1166} 1167 1168/// getOptimalMemOpType - Returns the target specific optimal type for load 1169/// and store operations as a result of memset, memcpy, and memmove 1170/// lowering. If DstAlign is zero that means it's safe to destination 1171/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1172/// means there isn't a need to check it against alignment requirement, 1173/// probably because the source does not need to be loaded. If 1174/// 'NonScalarIntSafe' is true, that means it's safe to return a 1175/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1176/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1177/// constant so it does not need to be loaded. 1178/// It returns EVT::Other if the type should be determined using generic 1179/// target-independent logic. 1180EVT 1181X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1182 unsigned DstAlign, unsigned SrcAlign, 1183 bool NonScalarIntSafe, 1184 bool MemcpyStrSrc, 1185 MachineFunction &MF) const { 1186 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1187 // linux. This is because the stack realignment code can't handle certain 1188 // cases like PR2962. This should be removed when PR2962 is fixed. 1189 const Function *F = MF.getFunction(); 1190 if (NonScalarIntSafe && 1191 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1192 if (Size >= 16 && 1193 (Subtarget->isUnalignedMemAccessFast() || 1194 ((DstAlign == 0 || DstAlign >= 16) && 1195 (SrcAlign == 0 || SrcAlign >= 16))) && 1196 Subtarget->getStackAlignment() >= 16) { 1197 if (Subtarget->hasSSE2()) 1198 return MVT::v4i32; 1199 if (Subtarget->hasSSE1()) 1200 return MVT::v4f32; 1201 } else if (!MemcpyStrSrc && Size >= 8 && 1202 !Subtarget->is64Bit() && 1203 Subtarget->getStackAlignment() >= 8 && 1204 Subtarget->hasXMMInt()) { 1205 // Do not use f64 to lower memcpy if source is string constant. It's 1206 // better to use i32 to avoid the loads. 1207 return MVT::f64; 1208 } 1209 } 1210 if (Subtarget->is64Bit() && Size >= 8) 1211 return MVT::i64; 1212 return MVT::i32; 1213} 1214 1215/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1216/// current function. The returned value is a member of the 1217/// MachineJumpTableInfo::JTEntryKind enum. 1218unsigned X86TargetLowering::getJumpTableEncoding() const { 1219 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1220 // symbol. 1221 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1222 Subtarget->isPICStyleGOT()) 1223 return MachineJumpTableInfo::EK_Custom32; 1224 1225 // Otherwise, use the normal jump table encoding heuristics. 1226 return TargetLowering::getJumpTableEncoding(); 1227} 1228 1229const MCExpr * 1230X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1231 const MachineBasicBlock *MBB, 1232 unsigned uid,MCContext &Ctx) const{ 1233 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1234 Subtarget->isPICStyleGOT()); 1235 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1236 // entries. 1237 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1238 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1239} 1240 1241/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1242/// jumptable. 1243SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1244 SelectionDAG &DAG) const { 1245 if (!Subtarget->is64Bit()) 1246 // This doesn't have DebugLoc associated with it, but is not really the 1247 // same as a Register. 1248 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1249 return Table; 1250} 1251 1252/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1253/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1254/// MCExpr. 1255const MCExpr *X86TargetLowering:: 1256getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1257 MCContext &Ctx) const { 1258 // X86-64 uses RIP relative addressing based on the jump table label. 1259 if (Subtarget->isPICStyleRIPRel()) 1260 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1261 1262 // Otherwise, the reference is relative to the PIC base. 1263 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1264} 1265 1266// FIXME: Why this routine is here? Move to RegInfo! 1267std::pair<const TargetRegisterClass*, uint8_t> 1268X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1269 const TargetRegisterClass *RRC = 0; 1270 uint8_t Cost = 1; 1271 switch (VT.getSimpleVT().SimpleTy) { 1272 default: 1273 return TargetLowering::findRepresentativeClass(VT); 1274 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1275 RRC = (Subtarget->is64Bit() 1276 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1277 break; 1278 case MVT::x86mmx: 1279 RRC = X86::VR64RegisterClass; 1280 break; 1281 case MVT::f32: case MVT::f64: 1282 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1283 case MVT::v4f32: case MVT::v2f64: 1284 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1285 case MVT::v4f64: 1286 RRC = X86::VR128RegisterClass; 1287 break; 1288 } 1289 return std::make_pair(RRC, Cost); 1290} 1291 1292bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1293 unsigned &Offset) const { 1294 if (!Subtarget->isTargetLinux()) 1295 return false; 1296 1297 if (Subtarget->is64Bit()) { 1298 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1299 Offset = 0x28; 1300 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1301 AddressSpace = 256; 1302 else 1303 AddressSpace = 257; 1304 } else { 1305 // %gs:0x14 on i386 1306 Offset = 0x14; 1307 AddressSpace = 256; 1308 } 1309 return true; 1310} 1311 1312 1313//===----------------------------------------------------------------------===// 1314// Return Value Calling Convention Implementation 1315//===----------------------------------------------------------------------===// 1316 1317#include "X86GenCallingConv.inc" 1318 1319bool 1320X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1321 MachineFunction &MF, bool isVarArg, 1322 const SmallVectorImpl<ISD::OutputArg> &Outs, 1323 LLVMContext &Context) const { 1324 SmallVector<CCValAssign, 16> RVLocs; 1325 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1326 RVLocs, Context); 1327 return CCInfo.CheckReturn(Outs, RetCC_X86); 1328} 1329 1330SDValue 1331X86TargetLowering::LowerReturn(SDValue Chain, 1332 CallingConv::ID CallConv, bool isVarArg, 1333 const SmallVectorImpl<ISD::OutputArg> &Outs, 1334 const SmallVectorImpl<SDValue> &OutVals, 1335 DebugLoc dl, SelectionDAG &DAG) const { 1336 MachineFunction &MF = DAG.getMachineFunction(); 1337 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1338 1339 SmallVector<CCValAssign, 16> RVLocs; 1340 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1341 RVLocs, *DAG.getContext()); 1342 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1343 1344 // Add the regs to the liveout set for the function. 1345 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1346 for (unsigned i = 0; i != RVLocs.size(); ++i) 1347 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1348 MRI.addLiveOut(RVLocs[i].getLocReg()); 1349 1350 SDValue Flag; 1351 1352 SmallVector<SDValue, 6> RetOps; 1353 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1354 // Operand #1 = Bytes To Pop 1355 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1356 MVT::i16)); 1357 1358 // Copy the result values into the output registers. 1359 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1360 CCValAssign &VA = RVLocs[i]; 1361 assert(VA.isRegLoc() && "Can only return in registers!"); 1362 SDValue ValToCopy = OutVals[i]; 1363 EVT ValVT = ValToCopy.getValueType(); 1364 1365 // If this is x86-64, and we disabled SSE, we can't return FP values, 1366 // or SSE or MMX vectors. 1367 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1368 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1369 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1370 report_fatal_error("SSE register return with SSE disabled"); 1371 } 1372 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1373 // llvm-gcc has never done it right and no one has noticed, so this 1374 // should be OK for now. 1375 if (ValVT == MVT::f64 && 1376 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1377 report_fatal_error("SSE2 register return with SSE2 disabled"); 1378 1379 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1380 // the RET instruction and handled by the FP Stackifier. 1381 if (VA.getLocReg() == X86::ST0 || 1382 VA.getLocReg() == X86::ST1) { 1383 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1384 // change the value to the FP stack register class. 1385 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1386 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1387 RetOps.push_back(ValToCopy); 1388 // Don't emit a copytoreg. 1389 continue; 1390 } 1391 1392 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1393 // which is returned in RAX / RDX. 1394 if (Subtarget->is64Bit()) { 1395 if (ValVT == MVT::x86mmx) { 1396 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1397 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1398 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1399 ValToCopy); 1400 // If we don't have SSE2 available, convert to v4f32 so the generated 1401 // register is legal. 1402 if (!Subtarget->hasSSE2()) 1403 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1404 } 1405 } 1406 } 1407 1408 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1409 Flag = Chain.getValue(1); 1410 } 1411 1412 // The x86-64 ABI for returning structs by value requires that we copy 1413 // the sret argument into %rax for the return. We saved the argument into 1414 // a virtual register in the entry block, so now we copy the value out 1415 // and into %rax. 1416 if (Subtarget->is64Bit() && 1417 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1418 MachineFunction &MF = DAG.getMachineFunction(); 1419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1420 unsigned Reg = FuncInfo->getSRetReturnReg(); 1421 assert(Reg && 1422 "SRetReturnReg should have been set in LowerFormalArguments()."); 1423 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1424 1425 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1426 Flag = Chain.getValue(1); 1427 1428 // RAX now acts like a return value. 1429 MRI.addLiveOut(X86::RAX); 1430 } 1431 1432 RetOps[0] = Chain; // Update chain. 1433 1434 // Add the flag if we have it. 1435 if (Flag.getNode()) 1436 RetOps.push_back(Flag); 1437 1438 return DAG.getNode(X86ISD::RET_FLAG, dl, 1439 MVT::Other, &RetOps[0], RetOps.size()); 1440} 1441 1442bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1443 if (N->getNumValues() != 1) 1444 return false; 1445 if (!N->hasNUsesOfValue(1, 0)) 1446 return false; 1447 1448 SDNode *Copy = *N->use_begin(); 1449 if (Copy->getOpcode() != ISD::CopyToReg && 1450 Copy->getOpcode() != ISD::FP_EXTEND) 1451 return false; 1452 1453 bool HasRet = false; 1454 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1455 UI != UE; ++UI) { 1456 if (UI->getOpcode() != X86ISD::RET_FLAG) 1457 return false; 1458 HasRet = true; 1459 } 1460 1461 return HasRet; 1462} 1463 1464EVT 1465X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1466 ISD::NodeType ExtendKind) const { 1467 MVT ReturnMVT; 1468 // TODO: Is this also valid on 32-bit? 1469 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1470 ReturnMVT = MVT::i8; 1471 else 1472 ReturnMVT = MVT::i32; 1473 1474 EVT MinVT = getRegisterType(Context, ReturnMVT); 1475 return VT.bitsLT(MinVT) ? MinVT : VT; 1476} 1477 1478/// LowerCallResult - Lower the result values of a call into the 1479/// appropriate copies out of appropriate physical registers. 1480/// 1481SDValue 1482X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1483 CallingConv::ID CallConv, bool isVarArg, 1484 const SmallVectorImpl<ISD::InputArg> &Ins, 1485 DebugLoc dl, SelectionDAG &DAG, 1486 SmallVectorImpl<SDValue> &InVals) const { 1487 1488 // Assign locations to each value returned by this call. 1489 SmallVector<CCValAssign, 16> RVLocs; 1490 bool Is64Bit = Subtarget->is64Bit(); 1491 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1492 getTargetMachine(), RVLocs, *DAG.getContext()); 1493 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1494 1495 // Copy all of the result registers out of their specified physreg. 1496 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1497 CCValAssign &VA = RVLocs[i]; 1498 EVT CopyVT = VA.getValVT(); 1499 1500 // If this is x86-64, and we disabled SSE, we can't return FP values 1501 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1502 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1503 report_fatal_error("SSE register return with SSE disabled"); 1504 } 1505 1506 SDValue Val; 1507 1508 // If this is a call to a function that returns an fp value on the floating 1509 // point stack, we must guarantee the the value is popped from the stack, so 1510 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1511 // if the return value is not used. We use the FpPOP_RETVAL instruction 1512 // instead. 1513 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1514 // If we prefer to use the value in xmm registers, copy it out as f80 and 1515 // use a truncate to move it from fp stack reg to xmm reg. 1516 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1517 SDValue Ops[] = { Chain, InFlag }; 1518 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1519 MVT::Other, MVT::Glue, Ops, 2), 1); 1520 Val = Chain.getValue(0); 1521 1522 // Round the f80 to the right size, which also moves it to the appropriate 1523 // xmm register. 1524 if (CopyVT != VA.getValVT()) 1525 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1526 // This truncation won't change the value. 1527 DAG.getIntPtrConstant(1)); 1528 } else { 1529 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1530 CopyVT, InFlag).getValue(1); 1531 Val = Chain.getValue(0); 1532 } 1533 InFlag = Chain.getValue(2); 1534 InVals.push_back(Val); 1535 } 1536 1537 return Chain; 1538} 1539 1540 1541//===----------------------------------------------------------------------===// 1542// C & StdCall & Fast Calling Convention implementation 1543//===----------------------------------------------------------------------===// 1544// StdCall calling convention seems to be standard for many Windows' API 1545// routines and around. It differs from C calling convention just a little: 1546// callee should clean up the stack, not caller. Symbols should be also 1547// decorated in some fancy way :) It doesn't support any vector arguments. 1548// For info on fast calling convention see Fast Calling Convention (tail call) 1549// implementation LowerX86_32FastCCCallTo. 1550 1551/// CallIsStructReturn - Determines whether a call uses struct return 1552/// semantics. 1553static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1554 if (Outs.empty()) 1555 return false; 1556 1557 return Outs[0].Flags.isSRet(); 1558} 1559 1560/// ArgsAreStructReturn - Determines whether a function uses struct 1561/// return semantics. 1562static bool 1563ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1564 if (Ins.empty()) 1565 return false; 1566 1567 return Ins[0].Flags.isSRet(); 1568} 1569 1570/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1571/// by "Src" to address "Dst" with size and alignment information specified by 1572/// the specific parameter attribute. The copy will be passed as a byval 1573/// function parameter. 1574static SDValue 1575CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1576 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1577 DebugLoc dl) { 1578 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1579 1580 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1581 /*isVolatile*/false, /*AlwaysInline=*/true, 1582 MachinePointerInfo(), MachinePointerInfo()); 1583} 1584 1585/// IsTailCallConvention - Return true if the calling convention is one that 1586/// supports tail call optimization. 1587static bool IsTailCallConvention(CallingConv::ID CC) { 1588 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1589} 1590 1591bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1592 if (!CI->isTailCall()) 1593 return false; 1594 1595 CallSite CS(CI); 1596 CallingConv::ID CalleeCC = CS.getCallingConv(); 1597 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1598 return false; 1599 1600 return true; 1601} 1602 1603/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1604/// a tailcall target by changing its ABI. 1605static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1606 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1607} 1608 1609SDValue 1610X86TargetLowering::LowerMemArgument(SDValue Chain, 1611 CallingConv::ID CallConv, 1612 const SmallVectorImpl<ISD::InputArg> &Ins, 1613 DebugLoc dl, SelectionDAG &DAG, 1614 const CCValAssign &VA, 1615 MachineFrameInfo *MFI, 1616 unsigned i) const { 1617 // Create the nodes corresponding to a load from this parameter slot. 1618 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1619 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1620 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1621 EVT ValVT; 1622 1623 // If value is passed by pointer we have address passed instead of the value 1624 // itself. 1625 if (VA.getLocInfo() == CCValAssign::Indirect) 1626 ValVT = VA.getLocVT(); 1627 else 1628 ValVT = VA.getValVT(); 1629 1630 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1631 // changed with more analysis. 1632 // In case of tail call optimization mark all arguments mutable. Since they 1633 // could be overwritten by lowering of arguments in case of a tail call. 1634 if (Flags.isByVal()) { 1635 unsigned Bytes = Flags.getByValSize(); 1636 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1637 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1638 return DAG.getFrameIndex(FI, getPointerTy()); 1639 } else { 1640 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1641 VA.getLocMemOffset(), isImmutable); 1642 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1643 return DAG.getLoad(ValVT, dl, Chain, FIN, 1644 MachinePointerInfo::getFixedStack(FI), 1645 false, false, 0); 1646 } 1647} 1648 1649SDValue 1650X86TargetLowering::LowerFormalArguments(SDValue Chain, 1651 CallingConv::ID CallConv, 1652 bool isVarArg, 1653 const SmallVectorImpl<ISD::InputArg> &Ins, 1654 DebugLoc dl, 1655 SelectionDAG &DAG, 1656 SmallVectorImpl<SDValue> &InVals) 1657 const { 1658 MachineFunction &MF = DAG.getMachineFunction(); 1659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1660 1661 const Function* Fn = MF.getFunction(); 1662 if (Fn->hasExternalLinkage() && 1663 Subtarget->isTargetCygMing() && 1664 Fn->getName() == "main") 1665 FuncInfo->setForceFramePointer(true); 1666 1667 MachineFrameInfo *MFI = MF.getFrameInfo(); 1668 bool Is64Bit = Subtarget->is64Bit(); 1669 bool IsWin64 = Subtarget->isTargetWin64(); 1670 1671 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1672 "Var args not supported with calling convention fastcc or ghc"); 1673 1674 // Assign locations to all of the incoming arguments. 1675 SmallVector<CCValAssign, 16> ArgLocs; 1676 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1677 ArgLocs, *DAG.getContext()); 1678 1679 // Allocate shadow area for Win64 1680 if (IsWin64) { 1681 CCInfo.AllocateStack(32, 8); 1682 } 1683 1684 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1685 1686 unsigned LastVal = ~0U; 1687 SDValue ArgValue; 1688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1689 CCValAssign &VA = ArgLocs[i]; 1690 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1691 // places. 1692 assert(VA.getValNo() != LastVal && 1693 "Don't support value assigned to multiple locs yet"); 1694 LastVal = VA.getValNo(); 1695 1696 if (VA.isRegLoc()) { 1697 EVT RegVT = VA.getLocVT(); 1698 TargetRegisterClass *RC = NULL; 1699 if (RegVT == MVT::i32) 1700 RC = X86::GR32RegisterClass; 1701 else if (Is64Bit && RegVT == MVT::i64) 1702 RC = X86::GR64RegisterClass; 1703 else if (RegVT == MVT::f32) 1704 RC = X86::FR32RegisterClass; 1705 else if (RegVT == MVT::f64) 1706 RC = X86::FR64RegisterClass; 1707 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1708 RC = X86::VR256RegisterClass; 1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1710 RC = X86::VR128RegisterClass; 1711 else if (RegVT == MVT::x86mmx) 1712 RC = X86::VR64RegisterClass; 1713 else 1714 llvm_unreachable("Unknown argument type!"); 1715 1716 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1717 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1718 1719 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1720 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1721 // right size. 1722 if (VA.getLocInfo() == CCValAssign::SExt) 1723 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1724 DAG.getValueType(VA.getValVT())); 1725 else if (VA.getLocInfo() == CCValAssign::ZExt) 1726 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1727 DAG.getValueType(VA.getValVT())); 1728 else if (VA.getLocInfo() == CCValAssign::BCvt) 1729 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1730 1731 if (VA.isExtInLoc()) { 1732 // Handle MMX values passed in XMM regs. 1733 if (RegVT.isVector()) { 1734 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1735 ArgValue); 1736 } else 1737 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1738 } 1739 } else { 1740 assert(VA.isMemLoc()); 1741 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1742 } 1743 1744 // If value is passed via pointer - do a load. 1745 if (VA.getLocInfo() == CCValAssign::Indirect) 1746 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1747 MachinePointerInfo(), false, false, 0); 1748 1749 InVals.push_back(ArgValue); 1750 } 1751 1752 // The x86-64 ABI for returning structs by value requires that we copy 1753 // the sret argument into %rax for the return. Save the argument into 1754 // a virtual register so that we can access it from the return points. 1755 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1756 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1757 unsigned Reg = FuncInfo->getSRetReturnReg(); 1758 if (!Reg) { 1759 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1760 FuncInfo->setSRetReturnReg(Reg); 1761 } 1762 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1763 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1764 } 1765 1766 unsigned StackSize = CCInfo.getNextStackOffset(); 1767 // Align stack specially for tail calls. 1768 if (FuncIsMadeTailCallSafe(CallConv)) 1769 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1770 1771 // If the function takes variable number of arguments, make a frame index for 1772 // the start of the first vararg value... for expansion of llvm.va_start. 1773 if (isVarArg) { 1774 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1775 CallConv != CallingConv::X86_ThisCall)) { 1776 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1777 } 1778 if (Is64Bit) { 1779 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1780 1781 // FIXME: We should really autogenerate these arrays 1782 static const unsigned GPR64ArgRegsWin64[] = { 1783 X86::RCX, X86::RDX, X86::R8, X86::R9 1784 }; 1785 static const unsigned GPR64ArgRegs64Bit[] = { 1786 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1787 }; 1788 static const unsigned XMMArgRegs64Bit[] = { 1789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1791 }; 1792 const unsigned *GPR64ArgRegs; 1793 unsigned NumXMMRegs = 0; 1794 1795 if (IsWin64) { 1796 // The XMM registers which might contain var arg parameters are shadowed 1797 // in their paired GPR. So we only need to save the GPR to their home 1798 // slots. 1799 TotalNumIntRegs = 4; 1800 GPR64ArgRegs = GPR64ArgRegsWin64; 1801 } else { 1802 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1803 GPR64ArgRegs = GPR64ArgRegs64Bit; 1804 1805 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1806 } 1807 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1808 TotalNumIntRegs); 1809 1810 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1811 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1812 "SSE register cannot be used when SSE is disabled!"); 1813 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1814 "SSE register cannot be used when SSE is disabled!"); 1815 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1816 // Kernel mode asks for SSE to be disabled, so don't push them 1817 // on the stack. 1818 TotalNumXMMRegs = 0; 1819 1820 if (IsWin64) { 1821 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1822 // Get to the caller-allocated home save location. Add 8 to account 1823 // for the return address. 1824 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1825 FuncInfo->setRegSaveFrameIndex( 1826 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1827 // Fixup to set vararg frame on shadow area (4 x i64). 1828 if (NumIntRegs < 4) 1829 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1830 } else { 1831 // For X86-64, if there are vararg parameters that are passed via 1832 // registers, then we must store them to their spots on the stack so they 1833 // may be loaded by deferencing the result of va_next. 1834 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1835 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1836 FuncInfo->setRegSaveFrameIndex( 1837 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1838 false)); 1839 } 1840 1841 // Store the integer parameter registers. 1842 SmallVector<SDValue, 8> MemOps; 1843 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1844 getPointerTy()); 1845 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1846 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1847 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1848 DAG.getIntPtrConstant(Offset)); 1849 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1850 X86::GR64RegisterClass); 1851 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1852 SDValue Store = 1853 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1854 MachinePointerInfo::getFixedStack( 1855 FuncInfo->getRegSaveFrameIndex(), Offset), 1856 false, false, 0); 1857 MemOps.push_back(Store); 1858 Offset += 8; 1859 } 1860 1861 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1862 // Now store the XMM (fp + vector) parameter registers. 1863 SmallVector<SDValue, 11> SaveXMMOps; 1864 SaveXMMOps.push_back(Chain); 1865 1866 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1867 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1868 SaveXMMOps.push_back(ALVal); 1869 1870 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1871 FuncInfo->getRegSaveFrameIndex())); 1872 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1873 FuncInfo->getVarArgsFPOffset())); 1874 1875 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1876 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1877 X86::VR128RegisterClass); 1878 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1879 SaveXMMOps.push_back(Val); 1880 } 1881 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1882 MVT::Other, 1883 &SaveXMMOps[0], SaveXMMOps.size())); 1884 } 1885 1886 if (!MemOps.empty()) 1887 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1888 &MemOps[0], MemOps.size()); 1889 } 1890 } 1891 1892 // Some CCs need callee pop. 1893 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 1894 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1895 } else { 1896 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1897 // If this is an sret function, the return should pop the hidden pointer. 1898 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1899 FuncInfo->setBytesToPopOnReturn(4); 1900 } 1901 1902 if (!Is64Bit) { 1903 // RegSaveFrameIndex is X86-64 only. 1904 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1905 if (CallConv == CallingConv::X86_FastCall || 1906 CallConv == CallingConv::X86_ThisCall) 1907 // fastcc functions can't have varargs. 1908 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1909 } 1910 1911 return Chain; 1912} 1913 1914SDValue 1915X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1916 SDValue StackPtr, SDValue Arg, 1917 DebugLoc dl, SelectionDAG &DAG, 1918 const CCValAssign &VA, 1919 ISD::ArgFlagsTy Flags) const { 1920 unsigned LocMemOffset = VA.getLocMemOffset(); 1921 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1922 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1923 if (Flags.isByVal()) 1924 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1925 1926 return DAG.getStore(Chain, dl, Arg, PtrOff, 1927 MachinePointerInfo::getStack(LocMemOffset), 1928 false, false, 0); 1929} 1930 1931/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1932/// optimization is performed and it is required. 1933SDValue 1934X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1935 SDValue &OutRetAddr, SDValue Chain, 1936 bool IsTailCall, bool Is64Bit, 1937 int FPDiff, DebugLoc dl) const { 1938 // Adjust the Return address stack slot. 1939 EVT VT = getPointerTy(); 1940 OutRetAddr = getReturnAddressFrameIndex(DAG); 1941 1942 // Load the "old" Return address. 1943 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1944 false, false, 0); 1945 return SDValue(OutRetAddr.getNode(), 1); 1946} 1947 1948/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 1949/// optimization is performed and it is required (FPDiff!=0). 1950static SDValue 1951EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1952 SDValue Chain, SDValue RetAddrFrIdx, 1953 bool Is64Bit, int FPDiff, DebugLoc dl) { 1954 // Store the return address to the appropriate stack slot. 1955 if (!FPDiff) return Chain; 1956 // Calculate the new stack slot for the return address. 1957 int SlotSize = Is64Bit ? 8 : 4; 1958 int NewReturnAddrFI = 1959 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1960 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1961 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1962 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1963 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 1964 false, false, 0); 1965 return Chain; 1966} 1967 1968SDValue 1969X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1970 CallingConv::ID CallConv, bool isVarArg, 1971 bool &isTailCall, 1972 const SmallVectorImpl<ISD::OutputArg> &Outs, 1973 const SmallVectorImpl<SDValue> &OutVals, 1974 const SmallVectorImpl<ISD::InputArg> &Ins, 1975 DebugLoc dl, SelectionDAG &DAG, 1976 SmallVectorImpl<SDValue> &InVals) const { 1977 MachineFunction &MF = DAG.getMachineFunction(); 1978 bool Is64Bit = Subtarget->is64Bit(); 1979 bool IsWin64 = Subtarget->isTargetWin64(); 1980 bool IsStructRet = CallIsStructReturn(Outs); 1981 bool IsSibcall = false; 1982 1983 if (isTailCall) { 1984 // Check if it's really possible to do a tail call. 1985 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1986 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1987 Outs, OutVals, Ins, DAG); 1988 1989 // Sibcalls are automatically detected tailcalls which do not require 1990 // ABI changes. 1991 if (!GuaranteedTailCallOpt && isTailCall) 1992 IsSibcall = true; 1993 1994 if (isTailCall) 1995 ++NumTailCalls; 1996 } 1997 1998 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1999 "Var args not supported with calling convention fastcc or ghc"); 2000 2001 // Analyze operands of the call, assigning locations to each operand. 2002 SmallVector<CCValAssign, 16> ArgLocs; 2003 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2004 ArgLocs, *DAG.getContext()); 2005 2006 // Allocate shadow area for Win64 2007 if (IsWin64) { 2008 CCInfo.AllocateStack(32, 8); 2009 } 2010 2011 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2012 2013 // Get a count of how many bytes are to be pushed on the stack. 2014 unsigned NumBytes = CCInfo.getNextStackOffset(); 2015 if (IsSibcall) 2016 // This is a sibcall. The memory operands are available in caller's 2017 // own caller's stack. 2018 NumBytes = 0; 2019 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2020 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2021 2022 int FPDiff = 0; 2023 if (isTailCall && !IsSibcall) { 2024 // Lower arguments at fp - stackoffset + fpdiff. 2025 unsigned NumBytesCallerPushed = 2026 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2027 FPDiff = NumBytesCallerPushed - NumBytes; 2028 2029 // Set the delta of movement of the returnaddr stackslot. 2030 // But only set if delta is greater than previous delta. 2031 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2032 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2033 } 2034 2035 if (!IsSibcall) 2036 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2037 2038 SDValue RetAddrFrIdx; 2039 // Load return address for tail calls. 2040 if (isTailCall && FPDiff) 2041 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2042 Is64Bit, FPDiff, dl); 2043 2044 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2045 SmallVector<SDValue, 8> MemOpChains; 2046 SDValue StackPtr; 2047 2048 // Walk the register/memloc assignments, inserting copies/loads. In the case 2049 // of tail call optimization arguments are handle later. 2050 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2051 CCValAssign &VA = ArgLocs[i]; 2052 EVT RegVT = VA.getLocVT(); 2053 SDValue Arg = OutVals[i]; 2054 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2055 bool isByVal = Flags.isByVal(); 2056 2057 // Promote the value if needed. 2058 switch (VA.getLocInfo()) { 2059 default: llvm_unreachable("Unknown loc info!"); 2060 case CCValAssign::Full: break; 2061 case CCValAssign::SExt: 2062 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2063 break; 2064 case CCValAssign::ZExt: 2065 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2066 break; 2067 case CCValAssign::AExt: 2068 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2069 // Special case: passing MMX values in XMM registers. 2070 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2071 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2072 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2073 } else 2074 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2075 break; 2076 case CCValAssign::BCvt: 2077 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2078 break; 2079 case CCValAssign::Indirect: { 2080 // Store the argument. 2081 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2082 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2083 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2084 MachinePointerInfo::getFixedStack(FI), 2085 false, false, 0); 2086 Arg = SpillSlot; 2087 break; 2088 } 2089 } 2090 2091 if (VA.isRegLoc()) { 2092 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2093 if (isVarArg && IsWin64) { 2094 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2095 // shadow reg if callee is a varargs function. 2096 unsigned ShadowReg = 0; 2097 switch (VA.getLocReg()) { 2098 case X86::XMM0: ShadowReg = X86::RCX; break; 2099 case X86::XMM1: ShadowReg = X86::RDX; break; 2100 case X86::XMM2: ShadowReg = X86::R8; break; 2101 case X86::XMM3: ShadowReg = X86::R9; break; 2102 } 2103 if (ShadowReg) 2104 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2105 } 2106 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2107 assert(VA.isMemLoc()); 2108 if (StackPtr.getNode() == 0) 2109 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2110 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2111 dl, DAG, VA, Flags)); 2112 } 2113 } 2114 2115 if (!MemOpChains.empty()) 2116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2117 &MemOpChains[0], MemOpChains.size()); 2118 2119 // Build a sequence of copy-to-reg nodes chained together with token chain 2120 // and flag operands which copy the outgoing args into registers. 2121 SDValue InFlag; 2122 // Tail call byval lowering might overwrite argument registers so in case of 2123 // tail call optimization the copies to registers are lowered later. 2124 if (!isTailCall) 2125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2127 RegsToPass[i].second, InFlag); 2128 InFlag = Chain.getValue(1); 2129 } 2130 2131 if (Subtarget->isPICStyleGOT()) { 2132 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2133 // GOT pointer. 2134 if (!isTailCall) { 2135 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2136 DAG.getNode(X86ISD::GlobalBaseReg, 2137 DebugLoc(), getPointerTy()), 2138 InFlag); 2139 InFlag = Chain.getValue(1); 2140 } else { 2141 // If we are tail calling and generating PIC/GOT style code load the 2142 // address of the callee into ECX. The value in ecx is used as target of 2143 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2144 // for tail calls on PIC/GOT architectures. Normally we would just put the 2145 // address of GOT into ebx and then call target@PLT. But for tail calls 2146 // ebx would be restored (since ebx is callee saved) before jumping to the 2147 // target@PLT. 2148 2149 // Note: The actual moving to ECX is done further down. 2150 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2151 if (G && !G->getGlobal()->hasHiddenVisibility() && 2152 !G->getGlobal()->hasProtectedVisibility()) 2153 Callee = LowerGlobalAddress(Callee, DAG); 2154 else if (isa<ExternalSymbolSDNode>(Callee)) 2155 Callee = LowerExternalSymbol(Callee, DAG); 2156 } 2157 } 2158 2159 if (Is64Bit && isVarArg && !IsWin64) { 2160 // From AMD64 ABI document: 2161 // For calls that may call functions that use varargs or stdargs 2162 // (prototype-less calls or calls to functions containing ellipsis (...) in 2163 // the declaration) %al is used as hidden argument to specify the number 2164 // of SSE registers used. The contents of %al do not need to match exactly 2165 // the number of registers, but must be an ubound on the number of SSE 2166 // registers used and is in the range 0 - 8 inclusive. 2167 2168 // Count the number of XMM registers allocated. 2169 static const unsigned XMMArgRegs[] = { 2170 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2171 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2172 }; 2173 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2174 assert((Subtarget->hasXMM() || !NumXMMRegs) 2175 && "SSE registers cannot be used when SSE is disabled"); 2176 2177 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2178 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2179 InFlag = Chain.getValue(1); 2180 } 2181 2182 2183 // For tail calls lower the arguments to the 'real' stack slot. 2184 if (isTailCall) { 2185 // Force all the incoming stack arguments to be loaded from the stack 2186 // before any new outgoing arguments are stored to the stack, because the 2187 // outgoing stack slots may alias the incoming argument stack slots, and 2188 // the alias isn't otherwise explicit. This is slightly more conservative 2189 // than necessary, because it means that each store effectively depends 2190 // on every argument instead of just those arguments it would clobber. 2191 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2192 2193 SmallVector<SDValue, 8> MemOpChains2; 2194 SDValue FIN; 2195 int FI = 0; 2196 // Do not flag preceding copytoreg stuff together with the following stuff. 2197 InFlag = SDValue(); 2198 if (GuaranteedTailCallOpt) { 2199 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2200 CCValAssign &VA = ArgLocs[i]; 2201 if (VA.isRegLoc()) 2202 continue; 2203 assert(VA.isMemLoc()); 2204 SDValue Arg = OutVals[i]; 2205 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2206 // Create frame index. 2207 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2208 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2209 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2210 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2211 2212 if (Flags.isByVal()) { 2213 // Copy relative to framepointer. 2214 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2215 if (StackPtr.getNode() == 0) 2216 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2217 getPointerTy()); 2218 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2219 2220 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2221 ArgChain, 2222 Flags, DAG, dl)); 2223 } else { 2224 // Store relative to framepointer. 2225 MemOpChains2.push_back( 2226 DAG.getStore(ArgChain, dl, Arg, FIN, 2227 MachinePointerInfo::getFixedStack(FI), 2228 false, false, 0)); 2229 } 2230 } 2231 } 2232 2233 if (!MemOpChains2.empty()) 2234 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2235 &MemOpChains2[0], MemOpChains2.size()); 2236 2237 // Copy arguments to their registers. 2238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2239 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2240 RegsToPass[i].second, InFlag); 2241 InFlag = Chain.getValue(1); 2242 } 2243 InFlag =SDValue(); 2244 2245 // Store the return address to the appropriate stack slot. 2246 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2247 FPDiff, dl); 2248 } 2249 2250 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2251 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2252 // In the 64-bit large code model, we have to make all calls 2253 // through a register, since the call instruction's 32-bit 2254 // pc-relative offset may not be large enough to hold the whole 2255 // address. 2256 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2257 // If the callee is a GlobalAddress node (quite common, every direct call 2258 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2259 // it. 2260 2261 // We should use extra load for direct calls to dllimported functions in 2262 // non-JIT mode. 2263 const GlobalValue *GV = G->getGlobal(); 2264 if (!GV->hasDLLImportLinkage()) { 2265 unsigned char OpFlags = 0; 2266 bool ExtraLoad = false; 2267 unsigned WrapperKind = ISD::DELETED_NODE; 2268 2269 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2270 // external symbols most go through the PLT in PIC mode. If the symbol 2271 // has hidden or protected visibility, or if it is static or local, then 2272 // we don't need to use the PLT - we can directly call it. 2273 if (Subtarget->isTargetELF() && 2274 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2275 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2276 OpFlags = X86II::MO_PLT; 2277 } else if (Subtarget->isPICStyleStubAny() && 2278 (GV->isDeclaration() || GV->isWeakForLinker()) && 2279 (!Subtarget->getTargetTriple().isMacOSX() || 2280 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2281 // PC-relative references to external symbols should go through $stub, 2282 // unless we're building with the leopard linker or later, which 2283 // automatically synthesizes these stubs. 2284 OpFlags = X86II::MO_DARWIN_STUB; 2285 } else if (Subtarget->isPICStyleRIPRel() && 2286 isa<Function>(GV) && 2287 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2288 // If the function is marked as non-lazy, generate an indirect call 2289 // which loads from the GOT directly. This avoids runtime overhead 2290 // at the cost of eager binding (and one extra byte of encoding). 2291 OpFlags = X86II::MO_GOTPCREL; 2292 WrapperKind = X86ISD::WrapperRIP; 2293 ExtraLoad = true; 2294 } 2295 2296 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2297 G->getOffset(), OpFlags); 2298 2299 // Add a wrapper if needed. 2300 if (WrapperKind != ISD::DELETED_NODE) 2301 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2302 // Add extra indirection if needed. 2303 if (ExtraLoad) 2304 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2305 MachinePointerInfo::getGOT(), 2306 false, false, 0); 2307 } 2308 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2309 unsigned char OpFlags = 0; 2310 2311 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2312 // external symbols should go through the PLT. 2313 if (Subtarget->isTargetELF() && 2314 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2315 OpFlags = X86II::MO_PLT; 2316 } else if (Subtarget->isPICStyleStubAny() && 2317 (!Subtarget->getTargetTriple().isMacOSX() || 2318 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2319 // PC-relative references to external symbols should go through $stub, 2320 // unless we're building with the leopard linker or later, which 2321 // automatically synthesizes these stubs. 2322 OpFlags = X86II::MO_DARWIN_STUB; 2323 } 2324 2325 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2326 OpFlags); 2327 } 2328 2329 // Returns a chain & a flag for retval copy to use. 2330 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2331 SmallVector<SDValue, 8> Ops; 2332 2333 if (!IsSibcall && isTailCall) { 2334 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2335 DAG.getIntPtrConstant(0, true), InFlag); 2336 InFlag = Chain.getValue(1); 2337 } 2338 2339 Ops.push_back(Chain); 2340 Ops.push_back(Callee); 2341 2342 if (isTailCall) 2343 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2344 2345 // Add argument registers to the end of the list so that they are known live 2346 // into the call. 2347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2348 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2349 RegsToPass[i].second.getValueType())); 2350 2351 // Add an implicit use GOT pointer in EBX. 2352 if (!isTailCall && Subtarget->isPICStyleGOT()) 2353 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2354 2355 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2356 if (Is64Bit && isVarArg && !IsWin64) 2357 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2358 2359 if (InFlag.getNode()) 2360 Ops.push_back(InFlag); 2361 2362 if (isTailCall) { 2363 // We used to do: 2364 //// If this is the first return lowered for this function, add the regs 2365 //// to the liveout set for the function. 2366 // This isn't right, although it's probably harmless on x86; liveouts 2367 // should be computed from returns not tail calls. Consider a void 2368 // function making a tail call to a function returning int. 2369 return DAG.getNode(X86ISD::TC_RETURN, dl, 2370 NodeTys, &Ops[0], Ops.size()); 2371 } 2372 2373 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2374 InFlag = Chain.getValue(1); 2375 2376 // Create the CALLSEQ_END node. 2377 unsigned NumBytesForCalleeToPush; 2378 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2379 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2380 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2381 // If this is a call to a struct-return function, the callee 2382 // pops the hidden struct pointer, so we have to push it back. 2383 // This is common for Darwin/X86, Linux & Mingw32 targets. 2384 NumBytesForCalleeToPush = 4; 2385 else 2386 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2387 2388 // Returns a flag for retval copy to use. 2389 if (!IsSibcall) { 2390 Chain = DAG.getCALLSEQ_END(Chain, 2391 DAG.getIntPtrConstant(NumBytes, true), 2392 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2393 true), 2394 InFlag); 2395 InFlag = Chain.getValue(1); 2396 } 2397 2398 // Handle result values, copying them out of physregs into vregs that we 2399 // return. 2400 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2401 Ins, dl, DAG, InVals); 2402} 2403 2404 2405//===----------------------------------------------------------------------===// 2406// Fast Calling Convention (tail call) implementation 2407//===----------------------------------------------------------------------===// 2408 2409// Like std call, callee cleans arguments, convention except that ECX is 2410// reserved for storing the tail called function address. Only 2 registers are 2411// free for argument passing (inreg). Tail call optimization is performed 2412// provided: 2413// * tailcallopt is enabled 2414// * caller/callee are fastcc 2415// On X86_64 architecture with GOT-style position independent code only local 2416// (within module) calls are supported at the moment. 2417// To keep the stack aligned according to platform abi the function 2418// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2419// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2420// If a tail called function callee has more arguments than the caller the 2421// caller needs to make sure that there is room to move the RETADDR to. This is 2422// achieved by reserving an area the size of the argument delta right after the 2423// original REtADDR, but before the saved framepointer or the spilled registers 2424// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2425// stack layout: 2426// arg1 2427// arg2 2428// RETADDR 2429// [ new RETADDR 2430// move area ] 2431// (possible EBP) 2432// ESI 2433// EDI 2434// local1 .. 2435 2436/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2437/// for a 16 byte align requirement. 2438unsigned 2439X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2440 SelectionDAG& DAG) const { 2441 MachineFunction &MF = DAG.getMachineFunction(); 2442 const TargetMachine &TM = MF.getTarget(); 2443 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2444 unsigned StackAlignment = TFI.getStackAlignment(); 2445 uint64_t AlignMask = StackAlignment - 1; 2446 int64_t Offset = StackSize; 2447 uint64_t SlotSize = TD->getPointerSize(); 2448 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2449 // Number smaller than 12 so just add the difference. 2450 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2451 } else { 2452 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2453 Offset = ((~AlignMask) & Offset) + StackAlignment + 2454 (StackAlignment-SlotSize); 2455 } 2456 return Offset; 2457} 2458 2459/// MatchingStackOffset - Return true if the given stack call argument is 2460/// already available in the same position (relatively) of the caller's 2461/// incoming argument stack. 2462static 2463bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2464 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2465 const X86InstrInfo *TII) { 2466 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2467 int FI = INT_MAX; 2468 if (Arg.getOpcode() == ISD::CopyFromReg) { 2469 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2470 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2471 return false; 2472 MachineInstr *Def = MRI->getVRegDef(VR); 2473 if (!Def) 2474 return false; 2475 if (!Flags.isByVal()) { 2476 if (!TII->isLoadFromStackSlot(Def, FI)) 2477 return false; 2478 } else { 2479 unsigned Opcode = Def->getOpcode(); 2480 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2481 Def->getOperand(1).isFI()) { 2482 FI = Def->getOperand(1).getIndex(); 2483 Bytes = Flags.getByValSize(); 2484 } else 2485 return false; 2486 } 2487 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2488 if (Flags.isByVal()) 2489 // ByVal argument is passed in as a pointer but it's now being 2490 // dereferenced. e.g. 2491 // define @foo(%struct.X* %A) { 2492 // tail call @bar(%struct.X* byval %A) 2493 // } 2494 return false; 2495 SDValue Ptr = Ld->getBasePtr(); 2496 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2497 if (!FINode) 2498 return false; 2499 FI = FINode->getIndex(); 2500 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2501 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2502 FI = FINode->getIndex(); 2503 Bytes = Flags.getByValSize(); 2504 } else 2505 return false; 2506 2507 assert(FI != INT_MAX); 2508 if (!MFI->isFixedObjectIndex(FI)) 2509 return false; 2510 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2511} 2512 2513/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2514/// for tail call optimization. Targets which want to do tail call 2515/// optimization should implement this function. 2516bool 2517X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2518 CallingConv::ID CalleeCC, 2519 bool isVarArg, 2520 bool isCalleeStructRet, 2521 bool isCallerStructRet, 2522 const SmallVectorImpl<ISD::OutputArg> &Outs, 2523 const SmallVectorImpl<SDValue> &OutVals, 2524 const SmallVectorImpl<ISD::InputArg> &Ins, 2525 SelectionDAG& DAG) const { 2526 if (!IsTailCallConvention(CalleeCC) && 2527 CalleeCC != CallingConv::C) 2528 return false; 2529 2530 // If -tailcallopt is specified, make fastcc functions tail-callable. 2531 const MachineFunction &MF = DAG.getMachineFunction(); 2532 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2533 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2534 bool CCMatch = CallerCC == CalleeCC; 2535 2536 if (GuaranteedTailCallOpt) { 2537 if (IsTailCallConvention(CalleeCC) && CCMatch) 2538 return true; 2539 return false; 2540 } 2541 2542 // Look for obvious safe cases to perform tail call optimization that do not 2543 // require ABI changes. This is what gcc calls sibcall. 2544 2545 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2546 // emit a special epilogue. 2547 if (RegInfo->needsStackRealignment(MF)) 2548 return false; 2549 2550 // Also avoid sibcall optimization if either caller or callee uses struct 2551 // return semantics. 2552 if (isCalleeStructRet || isCallerStructRet) 2553 return false; 2554 2555 // An stdcall caller is expected to clean up its arguments; the callee 2556 // isn't going to do that. 2557 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2558 return false; 2559 2560 // Do not sibcall optimize vararg calls unless all arguments are passed via 2561 // registers. 2562 if (isVarArg && !Outs.empty()) { 2563 2564 // Optimizing for varargs on Win64 is unlikely to be safe without 2565 // additional testing. 2566 if (Subtarget->isTargetWin64()) 2567 return false; 2568 2569 SmallVector<CCValAssign, 16> ArgLocs; 2570 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2571 getTargetMachine(), ArgLocs, *DAG.getContext()); 2572 2573 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2575 if (!ArgLocs[i].isRegLoc()) 2576 return false; 2577 } 2578 2579 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2580 // Therefore if it's not used by the call it is not safe to optimize this into 2581 // a sibcall. 2582 bool Unused = false; 2583 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2584 if (!Ins[i].Used) { 2585 Unused = true; 2586 break; 2587 } 2588 } 2589 if (Unused) { 2590 SmallVector<CCValAssign, 16> RVLocs; 2591 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2592 getTargetMachine(), RVLocs, *DAG.getContext()); 2593 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2594 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2595 CCValAssign &VA = RVLocs[i]; 2596 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2597 return false; 2598 } 2599 } 2600 2601 // If the calling conventions do not match, then we'd better make sure the 2602 // results are returned in the same way as what the caller expects. 2603 if (!CCMatch) { 2604 SmallVector<CCValAssign, 16> RVLocs1; 2605 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2606 getTargetMachine(), RVLocs1, *DAG.getContext()); 2607 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2608 2609 SmallVector<CCValAssign, 16> RVLocs2; 2610 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2611 getTargetMachine(), RVLocs2, *DAG.getContext()); 2612 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2613 2614 if (RVLocs1.size() != RVLocs2.size()) 2615 return false; 2616 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2617 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2618 return false; 2619 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2620 return false; 2621 if (RVLocs1[i].isRegLoc()) { 2622 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2623 return false; 2624 } else { 2625 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2626 return false; 2627 } 2628 } 2629 } 2630 2631 // If the callee takes no arguments then go on to check the results of the 2632 // call. 2633 if (!Outs.empty()) { 2634 // Check if stack adjustment is needed. For now, do not do this if any 2635 // argument is passed on the stack. 2636 SmallVector<CCValAssign, 16> ArgLocs; 2637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2638 getTargetMachine(), ArgLocs, *DAG.getContext()); 2639 2640 // Allocate shadow area for Win64 2641 if (Subtarget->isTargetWin64()) { 2642 CCInfo.AllocateStack(32, 8); 2643 } 2644 2645 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2646 if (CCInfo.getNextStackOffset()) { 2647 MachineFunction &MF = DAG.getMachineFunction(); 2648 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2649 return false; 2650 2651 // Check if the arguments are already laid out in the right way as 2652 // the caller's fixed stack objects. 2653 MachineFrameInfo *MFI = MF.getFrameInfo(); 2654 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2655 const X86InstrInfo *TII = 2656 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2657 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2658 CCValAssign &VA = ArgLocs[i]; 2659 SDValue Arg = OutVals[i]; 2660 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2661 if (VA.getLocInfo() == CCValAssign::Indirect) 2662 return false; 2663 if (!VA.isRegLoc()) { 2664 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2665 MFI, MRI, TII)) 2666 return false; 2667 } 2668 } 2669 } 2670 2671 // If the tailcall address may be in a register, then make sure it's 2672 // possible to register allocate for it. In 32-bit, the call address can 2673 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2674 // callee-saved registers are restored. These happen to be the same 2675 // registers used to pass 'inreg' arguments so watch out for those. 2676 if (!Subtarget->is64Bit() && 2677 !isa<GlobalAddressSDNode>(Callee) && 2678 !isa<ExternalSymbolSDNode>(Callee)) { 2679 unsigned NumInRegs = 0; 2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2681 CCValAssign &VA = ArgLocs[i]; 2682 if (!VA.isRegLoc()) 2683 continue; 2684 unsigned Reg = VA.getLocReg(); 2685 switch (Reg) { 2686 default: break; 2687 case X86::EAX: case X86::EDX: case X86::ECX: 2688 if (++NumInRegs == 3) 2689 return false; 2690 break; 2691 } 2692 } 2693 } 2694 } 2695 2696 return true; 2697} 2698 2699FastISel * 2700X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2701 return X86::createFastISel(funcInfo); 2702} 2703 2704 2705//===----------------------------------------------------------------------===// 2706// Other Lowering Hooks 2707//===----------------------------------------------------------------------===// 2708 2709static bool MayFoldLoad(SDValue Op) { 2710 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2711} 2712 2713static bool MayFoldIntoStore(SDValue Op) { 2714 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2715} 2716 2717static bool isTargetShuffle(unsigned Opcode) { 2718 switch(Opcode) { 2719 default: return false; 2720 case X86ISD::PSHUFD: 2721 case X86ISD::PSHUFHW: 2722 case X86ISD::PSHUFLW: 2723 case X86ISD::SHUFPD: 2724 case X86ISD::PALIGN: 2725 case X86ISD::SHUFPS: 2726 case X86ISD::MOVLHPS: 2727 case X86ISD::MOVLHPD: 2728 case X86ISD::MOVHLPS: 2729 case X86ISD::MOVLPS: 2730 case X86ISD::MOVLPD: 2731 case X86ISD::MOVSHDUP: 2732 case X86ISD::MOVSLDUP: 2733 case X86ISD::MOVDDUP: 2734 case X86ISD::MOVSS: 2735 case X86ISD::MOVSD: 2736 case X86ISD::UNPCKLPS: 2737 case X86ISD::UNPCKLPD: 2738 case X86ISD::VUNPCKLPSY: 2739 case X86ISD::VUNPCKLPDY: 2740 case X86ISD::PUNPCKLWD: 2741 case X86ISD::PUNPCKLBW: 2742 case X86ISD::PUNPCKLDQ: 2743 case X86ISD::PUNPCKLQDQ: 2744 case X86ISD::UNPCKHPS: 2745 case X86ISD::UNPCKHPD: 2746 case X86ISD::VUNPCKHPSY: 2747 case X86ISD::VUNPCKHPDY: 2748 case X86ISD::PUNPCKHWD: 2749 case X86ISD::PUNPCKHBW: 2750 case X86ISD::PUNPCKHDQ: 2751 case X86ISD::PUNPCKHQDQ: 2752 case X86ISD::VPERMILPS: 2753 case X86ISD::VPERMILPSY: 2754 case X86ISD::VPERMILPD: 2755 case X86ISD::VPERMILPDY: 2756 return true; 2757 } 2758 return false; 2759} 2760 2761static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2762 SDValue V1, SelectionDAG &DAG) { 2763 switch(Opc) { 2764 default: llvm_unreachable("Unknown x86 shuffle node"); 2765 case X86ISD::MOVSHDUP: 2766 case X86ISD::MOVSLDUP: 2767 case X86ISD::MOVDDUP: 2768 return DAG.getNode(Opc, dl, VT, V1); 2769 } 2770 2771 return SDValue(); 2772} 2773 2774static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2775 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2776 switch(Opc) { 2777 default: llvm_unreachable("Unknown x86 shuffle node"); 2778 case X86ISD::PSHUFD: 2779 case X86ISD::PSHUFHW: 2780 case X86ISD::PSHUFLW: 2781 case X86ISD::VPERMILPS: 2782 case X86ISD::VPERMILPSY: 2783 case X86ISD::VPERMILPD: 2784 case X86ISD::VPERMILPDY: 2785 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2786 } 2787 2788 return SDValue(); 2789} 2790 2791static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2792 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2793 switch(Opc) { 2794 default: llvm_unreachable("Unknown x86 shuffle node"); 2795 case X86ISD::PALIGN: 2796 case X86ISD::SHUFPD: 2797 case X86ISD::SHUFPS: 2798 return DAG.getNode(Opc, dl, VT, V1, V2, 2799 DAG.getConstant(TargetMask, MVT::i8)); 2800 } 2801 return SDValue(); 2802} 2803 2804static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2805 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2806 switch(Opc) { 2807 default: llvm_unreachable("Unknown x86 shuffle node"); 2808 case X86ISD::MOVLHPS: 2809 case X86ISD::MOVLHPD: 2810 case X86ISD::MOVHLPS: 2811 case X86ISD::MOVLPS: 2812 case X86ISD::MOVLPD: 2813 case X86ISD::MOVSS: 2814 case X86ISD::MOVSD: 2815 case X86ISD::UNPCKLPS: 2816 case X86ISD::UNPCKLPD: 2817 case X86ISD::VUNPCKLPSY: 2818 case X86ISD::VUNPCKLPDY: 2819 case X86ISD::PUNPCKLWD: 2820 case X86ISD::PUNPCKLBW: 2821 case X86ISD::PUNPCKLDQ: 2822 case X86ISD::PUNPCKLQDQ: 2823 case X86ISD::UNPCKHPS: 2824 case X86ISD::UNPCKHPD: 2825 case X86ISD::VUNPCKHPSY: 2826 case X86ISD::VUNPCKHPDY: 2827 case X86ISD::PUNPCKHWD: 2828 case X86ISD::PUNPCKHBW: 2829 case X86ISD::PUNPCKHDQ: 2830 case X86ISD::PUNPCKHQDQ: 2831 return DAG.getNode(Opc, dl, VT, V1, V2); 2832 } 2833 return SDValue(); 2834} 2835 2836SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2837 MachineFunction &MF = DAG.getMachineFunction(); 2838 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2839 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2840 2841 if (ReturnAddrIndex == 0) { 2842 // Set up a frame object for the return address. 2843 uint64_t SlotSize = TD->getPointerSize(); 2844 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2845 false); 2846 FuncInfo->setRAIndex(ReturnAddrIndex); 2847 } 2848 2849 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2850} 2851 2852 2853bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2854 bool hasSymbolicDisplacement) { 2855 // Offset should fit into 32 bit immediate field. 2856 if (!isInt<32>(Offset)) 2857 return false; 2858 2859 // If we don't have a symbolic displacement - we don't have any extra 2860 // restrictions. 2861 if (!hasSymbolicDisplacement) 2862 return true; 2863 2864 // FIXME: Some tweaks might be needed for medium code model. 2865 if (M != CodeModel::Small && M != CodeModel::Kernel) 2866 return false; 2867 2868 // For small code model we assume that latest object is 16MB before end of 31 2869 // bits boundary. We may also accept pretty large negative constants knowing 2870 // that all objects are in the positive half of address space. 2871 if (M == CodeModel::Small && Offset < 16*1024*1024) 2872 return true; 2873 2874 // For kernel code model we know that all object resist in the negative half 2875 // of 32bits address space. We may not accept negative offsets, since they may 2876 // be just off and we may accept pretty large positive ones. 2877 if (M == CodeModel::Kernel && Offset > 0) 2878 return true; 2879 2880 return false; 2881} 2882 2883/// isCalleePop - Determines whether the callee is required to pop its 2884/// own arguments. Callee pop is necessary to support tail calls. 2885bool X86::isCalleePop(CallingConv::ID CallingConv, 2886 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2887 if (IsVarArg) 2888 return false; 2889 2890 switch (CallingConv) { 2891 default: 2892 return false; 2893 case CallingConv::X86_StdCall: 2894 return !is64Bit; 2895 case CallingConv::X86_FastCall: 2896 return !is64Bit; 2897 case CallingConv::X86_ThisCall: 2898 return !is64Bit; 2899 case CallingConv::Fast: 2900 return TailCallOpt; 2901 case CallingConv::GHC: 2902 return TailCallOpt; 2903 } 2904} 2905 2906/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2907/// specific condition code, returning the condition code and the LHS/RHS of the 2908/// comparison to make. 2909static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2910 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2911 if (!isFP) { 2912 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2913 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2914 // X > -1 -> X == 0, jump !sign. 2915 RHS = DAG.getConstant(0, RHS.getValueType()); 2916 return X86::COND_NS; 2917 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2918 // X < 0 -> X == 0, jump on sign. 2919 return X86::COND_S; 2920 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2921 // X < 1 -> X <= 0 2922 RHS = DAG.getConstant(0, RHS.getValueType()); 2923 return X86::COND_LE; 2924 } 2925 } 2926 2927 switch (SetCCOpcode) { 2928 default: llvm_unreachable("Invalid integer condition!"); 2929 case ISD::SETEQ: return X86::COND_E; 2930 case ISD::SETGT: return X86::COND_G; 2931 case ISD::SETGE: return X86::COND_GE; 2932 case ISD::SETLT: return X86::COND_L; 2933 case ISD::SETLE: return X86::COND_LE; 2934 case ISD::SETNE: return X86::COND_NE; 2935 case ISD::SETULT: return X86::COND_B; 2936 case ISD::SETUGT: return X86::COND_A; 2937 case ISD::SETULE: return X86::COND_BE; 2938 case ISD::SETUGE: return X86::COND_AE; 2939 } 2940 } 2941 2942 // First determine if it is required or is profitable to flip the operands. 2943 2944 // If LHS is a foldable load, but RHS is not, flip the condition. 2945 if (ISD::isNON_EXTLoad(LHS.getNode()) && 2946 !ISD::isNON_EXTLoad(RHS.getNode())) { 2947 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2948 std::swap(LHS, RHS); 2949 } 2950 2951 switch (SetCCOpcode) { 2952 default: break; 2953 case ISD::SETOLT: 2954 case ISD::SETOLE: 2955 case ISD::SETUGT: 2956 case ISD::SETUGE: 2957 std::swap(LHS, RHS); 2958 break; 2959 } 2960 2961 // On a floating point condition, the flags are set as follows: 2962 // ZF PF CF op 2963 // 0 | 0 | 0 | X > Y 2964 // 0 | 0 | 1 | X < Y 2965 // 1 | 0 | 0 | X == Y 2966 // 1 | 1 | 1 | unordered 2967 switch (SetCCOpcode) { 2968 default: llvm_unreachable("Condcode should be pre-legalized away"); 2969 case ISD::SETUEQ: 2970 case ISD::SETEQ: return X86::COND_E; 2971 case ISD::SETOLT: // flipped 2972 case ISD::SETOGT: 2973 case ISD::SETGT: return X86::COND_A; 2974 case ISD::SETOLE: // flipped 2975 case ISD::SETOGE: 2976 case ISD::SETGE: return X86::COND_AE; 2977 case ISD::SETUGT: // flipped 2978 case ISD::SETULT: 2979 case ISD::SETLT: return X86::COND_B; 2980 case ISD::SETUGE: // flipped 2981 case ISD::SETULE: 2982 case ISD::SETLE: return X86::COND_BE; 2983 case ISD::SETONE: 2984 case ISD::SETNE: return X86::COND_NE; 2985 case ISD::SETUO: return X86::COND_P; 2986 case ISD::SETO: return X86::COND_NP; 2987 case ISD::SETOEQ: 2988 case ISD::SETUNE: return X86::COND_INVALID; 2989 } 2990} 2991 2992/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2993/// code. Current x86 isa includes the following FP cmov instructions: 2994/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2995static bool hasFPCMov(unsigned X86CC) { 2996 switch (X86CC) { 2997 default: 2998 return false; 2999 case X86::COND_B: 3000 case X86::COND_BE: 3001 case X86::COND_E: 3002 case X86::COND_P: 3003 case X86::COND_A: 3004 case X86::COND_AE: 3005 case X86::COND_NE: 3006 case X86::COND_NP: 3007 return true; 3008 } 3009} 3010 3011/// isFPImmLegal - Returns true if the target can instruction select the 3012/// specified FP immediate natively. If false, the legalizer will 3013/// materialize the FP immediate as a load from a constant pool. 3014bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3015 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3016 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3017 return true; 3018 } 3019 return false; 3020} 3021 3022/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3023/// the specified range (L, H]. 3024static bool isUndefOrInRange(int Val, int Low, int Hi) { 3025 return (Val < 0) || (Val >= Low && Val < Hi); 3026} 3027 3028/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3029/// specified value. 3030static bool isUndefOrEqual(int Val, int CmpVal) { 3031 if (Val < 0 || Val == CmpVal) 3032 return true; 3033 return false; 3034} 3035 3036/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3037/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3038/// the second operand. 3039static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3040 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3041 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3042 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3043 return (Mask[0] < 2 && Mask[1] < 2); 3044 return false; 3045} 3046 3047bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3048 SmallVector<int, 8> M; 3049 N->getMask(M); 3050 return ::isPSHUFDMask(M, N->getValueType(0)); 3051} 3052 3053/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3054/// is suitable for input to PSHUFHW. 3055static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3056 if (VT != MVT::v8i16) 3057 return false; 3058 3059 // Lower quadword copied in order or undef. 3060 for (int i = 0; i != 4; ++i) 3061 if (Mask[i] >= 0 && Mask[i] != i) 3062 return false; 3063 3064 // Upper quadword shuffled. 3065 for (int i = 4; i != 8; ++i) 3066 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3067 return false; 3068 3069 return true; 3070} 3071 3072bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3073 SmallVector<int, 8> M; 3074 N->getMask(M); 3075 return ::isPSHUFHWMask(M, N->getValueType(0)); 3076} 3077 3078/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3079/// is suitable for input to PSHUFLW. 3080static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3081 if (VT != MVT::v8i16) 3082 return false; 3083 3084 // Upper quadword copied in order. 3085 for (int i = 4; i != 8; ++i) 3086 if (Mask[i] >= 0 && Mask[i] != i) 3087 return false; 3088 3089 // Lower quadword shuffled. 3090 for (int i = 0; i != 4; ++i) 3091 if (Mask[i] >= 4) 3092 return false; 3093 3094 return true; 3095} 3096 3097bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3098 SmallVector<int, 8> M; 3099 N->getMask(M); 3100 return ::isPSHUFLWMask(M, N->getValueType(0)); 3101} 3102 3103/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3104/// is suitable for input to PALIGNR. 3105static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3106 bool hasSSSE3) { 3107 int i, e = VT.getVectorNumElements(); 3108 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3109 return false; 3110 3111 // Do not handle v2i64 / v2f64 shuffles with palignr. 3112 if (e < 4 || !hasSSSE3) 3113 return false; 3114 3115 for (i = 0; i != e; ++i) 3116 if (Mask[i] >= 0) 3117 break; 3118 3119 // All undef, not a palignr. 3120 if (i == e) 3121 return false; 3122 3123 // Make sure we're shifting in the right direction. 3124 if (Mask[i] <= i) 3125 return false; 3126 3127 int s = Mask[i] - i; 3128 3129 // Check the rest of the elements to see if they are consecutive. 3130 for (++i; i != e; ++i) { 3131 int m = Mask[i]; 3132 if (m >= 0 && m != s+i) 3133 return false; 3134 } 3135 return true; 3136} 3137 3138/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3139/// specifies a shuffle of elements that is suitable for input to SHUFP*. 3140static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3141 int NumElems = VT.getVectorNumElements(); 3142 if (NumElems != 2 && NumElems != 4) 3143 return false; 3144 3145 int Half = NumElems / 2; 3146 for (int i = 0; i < Half; ++i) 3147 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3148 return false; 3149 for (int i = Half; i < NumElems; ++i) 3150 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3151 return false; 3152 3153 return true; 3154} 3155 3156bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3157 SmallVector<int, 8> M; 3158 N->getMask(M); 3159 return ::isSHUFPMask(M, N->getValueType(0)); 3160} 3161 3162/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3163/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3164/// half elements to come from vector 1 (which would equal the dest.) and 3165/// the upper half to come from vector 2. 3166static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3167 int NumElems = VT.getVectorNumElements(); 3168 3169 if (NumElems != 2 && NumElems != 4) 3170 return false; 3171 3172 int Half = NumElems / 2; 3173 for (int i = 0; i < Half; ++i) 3174 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3175 return false; 3176 for (int i = Half; i < NumElems; ++i) 3177 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3178 return false; 3179 return true; 3180} 3181 3182static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3183 SmallVector<int, 8> M; 3184 N->getMask(M); 3185 return isCommutedSHUFPMask(M, N->getValueType(0)); 3186} 3187 3188/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3189/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3190bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3191 EVT VT = N->getValueType(0); 3192 unsigned NumElems = VT.getVectorNumElements(); 3193 3194 if (VT.getSizeInBits() != 128) 3195 return false; 3196 3197 if (NumElems != 4) 3198 return false; 3199 3200 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3201 return isUndefOrEqual(N->getMaskElt(0), 6) && 3202 isUndefOrEqual(N->getMaskElt(1), 7) && 3203 isUndefOrEqual(N->getMaskElt(2), 2) && 3204 isUndefOrEqual(N->getMaskElt(3), 3); 3205} 3206 3207/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3208/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3209/// <2, 3, 2, 3> 3210bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3211 EVT VT = N->getValueType(0); 3212 unsigned NumElems = VT.getVectorNumElements(); 3213 3214 if (VT.getSizeInBits() != 128) 3215 return false; 3216 3217 if (NumElems != 4) 3218 return false; 3219 3220 return isUndefOrEqual(N->getMaskElt(0), 2) && 3221 isUndefOrEqual(N->getMaskElt(1), 3) && 3222 isUndefOrEqual(N->getMaskElt(2), 2) && 3223 isUndefOrEqual(N->getMaskElt(3), 3); 3224} 3225 3226/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3227/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3228bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3229 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3230 3231 if (NumElems != 2 && NumElems != 4) 3232 return false; 3233 3234 for (unsigned i = 0; i < NumElems/2; ++i) 3235 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3236 return false; 3237 3238 for (unsigned i = NumElems/2; i < NumElems; ++i) 3239 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3240 return false; 3241 3242 return true; 3243} 3244 3245/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3246/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3247bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3248 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3249 3250 if ((NumElems != 2 && NumElems != 4) 3251 || N->getValueType(0).getSizeInBits() > 128) 3252 return false; 3253 3254 for (unsigned i = 0; i < NumElems/2; ++i) 3255 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3256 return false; 3257 3258 for (unsigned i = 0; i < NumElems/2; ++i) 3259 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3260 return false; 3261 3262 return true; 3263} 3264 3265/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3266/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3267static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3268 bool V2IsSplat = false) { 3269 int NumElts = VT.getVectorNumElements(); 3270 3271 assert((VT.is128BitVector() || VT.is256BitVector()) && 3272 "Unsupported vector type for unpckh"); 3273 3274 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3275 return false; 3276 3277 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3278 // independently on 128-bit lanes. 3279 unsigned NumLanes = VT.getSizeInBits()/128; 3280 unsigned NumLaneElts = NumElts/NumLanes; 3281 3282 unsigned Start = 0; 3283 unsigned End = NumLaneElts; 3284 for (unsigned s = 0; s < NumLanes; ++s) { 3285 for (unsigned i = Start, j = s * NumLaneElts; 3286 i != End; 3287 i += 2, ++j) { 3288 int BitI = Mask[i]; 3289 int BitI1 = Mask[i+1]; 3290 if (!isUndefOrEqual(BitI, j)) 3291 return false; 3292 if (V2IsSplat) { 3293 if (!isUndefOrEqual(BitI1, NumElts)) 3294 return false; 3295 } else { 3296 if (!isUndefOrEqual(BitI1, j + NumElts)) 3297 return false; 3298 } 3299 } 3300 // Process the next 128 bits. 3301 Start += NumLaneElts; 3302 End += NumLaneElts; 3303 } 3304 3305 return true; 3306} 3307 3308bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3309 SmallVector<int, 8> M; 3310 N->getMask(M); 3311 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3312} 3313 3314/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3315/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3316static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3317 bool V2IsSplat = false) { 3318 int NumElts = VT.getVectorNumElements(); 3319 3320 assert((VT.is128BitVector() || VT.is256BitVector()) && 3321 "Unsupported vector type for unpckh"); 3322 3323 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3324 return false; 3325 3326 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3327 // independently on 128-bit lanes. 3328 unsigned NumLanes = VT.getSizeInBits()/128; 3329 unsigned NumLaneElts = NumElts/NumLanes; 3330 3331 unsigned Start = 0; 3332 unsigned End = NumLaneElts; 3333 for (unsigned l = 0; l != NumLanes; ++l) { 3334 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3335 i != End; i += 2, ++j) { 3336 int BitI = Mask[i]; 3337 int BitI1 = Mask[i+1]; 3338 if (!isUndefOrEqual(BitI, j)) 3339 return false; 3340 if (V2IsSplat) { 3341 if (isUndefOrEqual(BitI1, NumElts)) 3342 return false; 3343 } else { 3344 if (!isUndefOrEqual(BitI1, j+NumElts)) 3345 return false; 3346 } 3347 } 3348 // Process the next 128 bits. 3349 Start += NumLaneElts; 3350 End += NumLaneElts; 3351 } 3352 return true; 3353} 3354 3355bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3356 SmallVector<int, 8> M; 3357 N->getMask(M); 3358 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3359} 3360 3361/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3362/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3363/// <0, 0, 1, 1> 3364static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3365 int NumElems = VT.getVectorNumElements(); 3366 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3367 return false; 3368 3369 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3370 // independently on 128-bit lanes. 3371 unsigned NumLanes = VT.getSizeInBits() / 128; 3372 unsigned NumLaneElts = NumElems / NumLanes; 3373 3374 for (unsigned s = 0; s < NumLanes; ++s) { 3375 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3376 i != NumLaneElts * (s + 1); 3377 i += 2, ++j) { 3378 int BitI = Mask[i]; 3379 int BitI1 = Mask[i+1]; 3380 3381 if (!isUndefOrEqual(BitI, j)) 3382 return false; 3383 if (!isUndefOrEqual(BitI1, j)) 3384 return false; 3385 } 3386 } 3387 3388 return true; 3389} 3390 3391bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3392 SmallVector<int, 8> M; 3393 N->getMask(M); 3394 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3395} 3396 3397/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3398/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3399/// <2, 2, 3, 3> 3400static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3401 int NumElems = VT.getVectorNumElements(); 3402 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3403 return false; 3404 3405 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3406 int BitI = Mask[i]; 3407 int BitI1 = Mask[i+1]; 3408 if (!isUndefOrEqual(BitI, j)) 3409 return false; 3410 if (!isUndefOrEqual(BitI1, j)) 3411 return false; 3412 } 3413 return true; 3414} 3415 3416bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3417 SmallVector<int, 8> M; 3418 N->getMask(M); 3419 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3420} 3421 3422/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3423/// specifies a shuffle of elements that is suitable for input to MOVSS, 3424/// MOVSD, and MOVD, i.e. setting the lowest element. 3425static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3426 if (VT.getVectorElementType().getSizeInBits() < 32) 3427 return false; 3428 3429 int NumElts = VT.getVectorNumElements(); 3430 3431 if (!isUndefOrEqual(Mask[0], NumElts)) 3432 return false; 3433 3434 for (int i = 1; i < NumElts; ++i) 3435 if (!isUndefOrEqual(Mask[i], i)) 3436 return false; 3437 3438 return true; 3439} 3440 3441bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3442 SmallVector<int, 8> M; 3443 N->getMask(M); 3444 return ::isMOVLMask(M, N->getValueType(0)); 3445} 3446 3447/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3448/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3449/// Note that VPERMIL mask matching is different depending whether theunderlying 3450/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3451/// to the same elements of the low, but to the higher half of the source. 3452/// In VPERMILPD the two lanes could be shuffled independently of each other 3453/// with the same restriction that lanes can't be crossed. 3454static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3455 const X86Subtarget *Subtarget) { 3456 int NumElts = VT.getVectorNumElements(); 3457 int NumLanes = VT.getSizeInBits()/128; 3458 3459 if (!Subtarget->hasAVX()) 3460 return false; 3461 3462 // Match any permutation of 128-bit vector with 64-bit types 3463 if (NumLanes == 1 && NumElts != 2) 3464 return false; 3465 3466 // Only match 256-bit with 32 types 3467 if (VT.getSizeInBits() == 256 && NumElts != 4) 3468 return false; 3469 3470 // The mask on the high lane is independent of the low. Both can match 3471 // any element in inside its own lane, but can't cross. 3472 int LaneSize = NumElts/NumLanes; 3473 for (int l = 0; l < NumLanes; ++l) 3474 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3475 int LaneStart = l*LaneSize; 3476 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3477 return false; 3478 } 3479 3480 return true; 3481} 3482 3483/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3484/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3485/// Note that VPERMIL mask matching is different depending whether theunderlying 3486/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3487/// to the same elements of the low, but to the higher half of the source. 3488/// In VPERMILPD the two lanes could be shuffled independently of each other 3489/// with the same restriction that lanes can't be crossed. 3490static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3491 const X86Subtarget *Subtarget) { 3492 unsigned NumElts = VT.getVectorNumElements(); 3493 unsigned NumLanes = VT.getSizeInBits()/128; 3494 3495 if (!Subtarget->hasAVX()) 3496 return false; 3497 3498 // Match any permutation of 128-bit vector with 32-bit types 3499 if (NumLanes == 1 && NumElts != 4) 3500 return false; 3501 3502 // Only match 256-bit with 32 types 3503 if (VT.getSizeInBits() == 256 && NumElts != 8) 3504 return false; 3505 3506 // The mask on the high lane should be the same as the low. Actually, 3507 // they can differ if any of the corresponding index in a lane is undef 3508 // and the other stays in range. 3509 int LaneSize = NumElts/NumLanes; 3510 for (int i = 0; i < LaneSize; ++i) { 3511 int HighElt = i+LaneSize; 3512 if (Mask[i] < 0 && (isUndefOrInRange(Mask[HighElt], LaneSize, NumElts))) 3513 continue; 3514 if (Mask[HighElt] < 0 && (isUndefOrInRange(Mask[i], 0, LaneSize))) 3515 continue; 3516 if (Mask[HighElt]-Mask[i] != LaneSize) 3517 return false; 3518 } 3519 3520 return true; 3521} 3522 3523/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3524/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3525static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3526 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3527 EVT VT = SVOp->getValueType(0); 3528 3529 int NumElts = VT.getVectorNumElements(); 3530 int NumLanes = VT.getSizeInBits()/128; 3531 int LaneSize = NumElts/NumLanes; 3532 3533 // Although the mask is equal for both lanes do it twice to get the cases 3534 // where a mask will match because the same mask element is undef on the 3535 // first half but valid on the second. This would get pathological cases 3536 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3537 unsigned Mask = 0; 3538 for (int l = 0; l < NumLanes; ++l) { 3539 for (int i = 0; i < LaneSize; ++i) { 3540 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3541 if (MaskElt < 0) 3542 continue; 3543 if (MaskElt >= LaneSize) 3544 MaskElt -= LaneSize; 3545 Mask |= MaskElt << (i*2); 3546 } 3547 } 3548 3549 return Mask; 3550} 3551 3552/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3553/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3554static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3555 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3556 EVT VT = SVOp->getValueType(0); 3557 3558 int NumElts = VT.getVectorNumElements(); 3559 int NumLanes = VT.getSizeInBits()/128; 3560 3561 unsigned Mask = 0; 3562 int LaneSize = NumElts/NumLanes; 3563 for (int l = 0; l < NumLanes; ++l) 3564 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3565 int MaskElt = SVOp->getMaskElt(i); 3566 if (MaskElt < 0) 3567 continue; 3568 Mask |= (MaskElt-l*LaneSize) << i; 3569 } 3570 3571 return Mask; 3572} 3573 3574/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3575/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3576/// element of vector 2 and the other elements to come from vector 1 in order. 3577static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3578 bool V2IsSplat = false, bool V2IsUndef = false) { 3579 int NumOps = VT.getVectorNumElements(); 3580 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3581 return false; 3582 3583 if (!isUndefOrEqual(Mask[0], 0)) 3584 return false; 3585 3586 for (int i = 1; i < NumOps; ++i) 3587 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3588 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3589 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3590 return false; 3591 3592 return true; 3593} 3594 3595static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3596 bool V2IsUndef = false) { 3597 SmallVector<int, 8> M; 3598 N->getMask(M); 3599 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3600} 3601 3602/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3603/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3604/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3605bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3606 const X86Subtarget *Subtarget) { 3607 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3608 return false; 3609 3610 // The second vector must be undef 3611 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3612 return false; 3613 3614 EVT VT = N->getValueType(0); 3615 unsigned NumElems = VT.getVectorNumElements(); 3616 3617 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3618 (VT.getSizeInBits() == 256 && NumElems != 8)) 3619 return false; 3620 3621 // "i+1" is the value the indexed mask element must have 3622 for (unsigned i = 0; i < NumElems; i += 2) 3623 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3624 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3625 return false; 3626 3627 return true; 3628} 3629 3630/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3631/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3632/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3633bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3634 const X86Subtarget *Subtarget) { 3635 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3636 return false; 3637 3638 // The second vector must be undef 3639 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3640 return false; 3641 3642 EVT VT = N->getValueType(0); 3643 unsigned NumElems = VT.getVectorNumElements(); 3644 3645 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3646 (VT.getSizeInBits() == 256 && NumElems != 8)) 3647 return false; 3648 3649 // "i" is the value the indexed mask element must have 3650 for (unsigned i = 0; i < NumElems; i += 2) 3651 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3652 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3653 return false; 3654 3655 return true; 3656} 3657 3658/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3659/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3660bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3661 int e = N->getValueType(0).getVectorNumElements() / 2; 3662 3663 for (int i = 0; i < e; ++i) 3664 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3665 return false; 3666 for (int i = 0; i < e; ++i) 3667 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3668 return false; 3669 return true; 3670} 3671 3672/// isVEXTRACTF128Index - Return true if the specified 3673/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3674/// suitable for input to VEXTRACTF128. 3675bool X86::isVEXTRACTF128Index(SDNode *N) { 3676 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3677 return false; 3678 3679 // The index should be aligned on a 128-bit boundary. 3680 uint64_t Index = 3681 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3682 3683 unsigned VL = N->getValueType(0).getVectorNumElements(); 3684 unsigned VBits = N->getValueType(0).getSizeInBits(); 3685 unsigned ElSize = VBits / VL; 3686 bool Result = (Index * ElSize) % 128 == 0; 3687 3688 return Result; 3689} 3690 3691/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3692/// operand specifies a subvector insert that is suitable for input to 3693/// VINSERTF128. 3694bool X86::isVINSERTF128Index(SDNode *N) { 3695 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3696 return false; 3697 3698 // The index should be aligned on a 128-bit boundary. 3699 uint64_t Index = 3700 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3701 3702 unsigned VL = N->getValueType(0).getVectorNumElements(); 3703 unsigned VBits = N->getValueType(0).getSizeInBits(); 3704 unsigned ElSize = VBits / VL; 3705 bool Result = (Index * ElSize) % 128 == 0; 3706 3707 return Result; 3708} 3709 3710/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3711/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3712unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3714 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3715 3716 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3717 unsigned Mask = 0; 3718 for (int i = 0; i < NumOperands; ++i) { 3719 int Val = SVOp->getMaskElt(NumOperands-i-1); 3720 if (Val < 0) Val = 0; 3721 if (Val >= NumOperands) Val -= NumOperands; 3722 Mask |= Val; 3723 if (i != NumOperands - 1) 3724 Mask <<= Shift; 3725 } 3726 return Mask; 3727} 3728 3729/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3730/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3731unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3732 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3733 unsigned Mask = 0; 3734 // 8 nodes, but we only care about the last 4. 3735 for (unsigned i = 7; i >= 4; --i) { 3736 int Val = SVOp->getMaskElt(i); 3737 if (Val >= 0) 3738 Mask |= (Val - 4); 3739 if (i != 4) 3740 Mask <<= 2; 3741 } 3742 return Mask; 3743} 3744 3745/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3746/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3747unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3748 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3749 unsigned Mask = 0; 3750 // 8 nodes, but we only care about the first 4. 3751 for (int i = 3; i >= 0; --i) { 3752 int Val = SVOp->getMaskElt(i); 3753 if (Val >= 0) 3754 Mask |= Val; 3755 if (i != 0) 3756 Mask <<= 2; 3757 } 3758 return Mask; 3759} 3760 3761/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3762/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3763unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3765 EVT VVT = N->getValueType(0); 3766 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3767 int Val = 0; 3768 3769 unsigned i, e; 3770 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3771 Val = SVOp->getMaskElt(i); 3772 if (Val >= 0) 3773 break; 3774 } 3775 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3776 return (Val - i) * EltSize; 3777} 3778 3779/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3780/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3781/// instructions. 3782unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3783 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3784 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3785 3786 uint64_t Index = 3787 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3788 3789 EVT VecVT = N->getOperand(0).getValueType(); 3790 EVT ElVT = VecVT.getVectorElementType(); 3791 3792 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3793 return Index / NumElemsPerChunk; 3794} 3795 3796/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3797/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3798/// instructions. 3799unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3800 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3801 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3802 3803 uint64_t Index = 3804 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3805 3806 EVT VecVT = N->getValueType(0); 3807 EVT ElVT = VecVT.getVectorElementType(); 3808 3809 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3810 return Index / NumElemsPerChunk; 3811} 3812 3813/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3814/// constant +0.0. 3815bool X86::isZeroNode(SDValue Elt) { 3816 return ((isa<ConstantSDNode>(Elt) && 3817 cast<ConstantSDNode>(Elt)->isNullValue()) || 3818 (isa<ConstantFPSDNode>(Elt) && 3819 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3820} 3821 3822/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3823/// their permute mask. 3824static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3825 SelectionDAG &DAG) { 3826 EVT VT = SVOp->getValueType(0); 3827 unsigned NumElems = VT.getVectorNumElements(); 3828 SmallVector<int, 8> MaskVec; 3829 3830 for (unsigned i = 0; i != NumElems; ++i) { 3831 int idx = SVOp->getMaskElt(i); 3832 if (idx < 0) 3833 MaskVec.push_back(idx); 3834 else if (idx < (int)NumElems) 3835 MaskVec.push_back(idx + NumElems); 3836 else 3837 MaskVec.push_back(idx - NumElems); 3838 } 3839 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3840 SVOp->getOperand(0), &MaskVec[0]); 3841} 3842 3843/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3844/// the two vector operands have swapped position. 3845static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3846 unsigned NumElems = VT.getVectorNumElements(); 3847 for (unsigned i = 0; i != NumElems; ++i) { 3848 int idx = Mask[i]; 3849 if (idx < 0) 3850 continue; 3851 else if (idx < (int)NumElems) 3852 Mask[i] = idx + NumElems; 3853 else 3854 Mask[i] = idx - NumElems; 3855 } 3856} 3857 3858/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3859/// match movhlps. The lower half elements should come from upper half of 3860/// V1 (and in order), and the upper half elements should come from the upper 3861/// half of V2 (and in order). 3862static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3863 if (Op->getValueType(0).getVectorNumElements() != 4) 3864 return false; 3865 for (unsigned i = 0, e = 2; i != e; ++i) 3866 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3867 return false; 3868 for (unsigned i = 2; i != 4; ++i) 3869 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3870 return false; 3871 return true; 3872} 3873 3874/// isScalarLoadToVector - Returns true if the node is a scalar load that 3875/// is promoted to a vector. It also returns the LoadSDNode by reference if 3876/// required. 3877static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3878 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3879 return false; 3880 N = N->getOperand(0).getNode(); 3881 if (!ISD::isNON_EXTLoad(N)) 3882 return false; 3883 if (LD) 3884 *LD = cast<LoadSDNode>(N); 3885 return true; 3886} 3887 3888/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3889/// match movlp{s|d}. The lower half elements should come from lower half of 3890/// V1 (and in order), and the upper half elements should come from the upper 3891/// half of V2 (and in order). And since V1 will become the source of the 3892/// MOVLP, it must be either a vector load or a scalar load to vector. 3893static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3894 ShuffleVectorSDNode *Op) { 3895 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3896 return false; 3897 // Is V2 is a vector load, don't do this transformation. We will try to use 3898 // load folding shufps op. 3899 if (ISD::isNON_EXTLoad(V2)) 3900 return false; 3901 3902 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3903 3904 if (NumElems != 2 && NumElems != 4) 3905 return false; 3906 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3907 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3908 return false; 3909 for (unsigned i = NumElems/2; i != NumElems; ++i) 3910 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3911 return false; 3912 return true; 3913} 3914 3915/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3916/// all the same. 3917static bool isSplatVector(SDNode *N) { 3918 if (N->getOpcode() != ISD::BUILD_VECTOR) 3919 return false; 3920 3921 SDValue SplatValue = N->getOperand(0); 3922 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3923 if (N->getOperand(i) != SplatValue) 3924 return false; 3925 return true; 3926} 3927 3928/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3929/// to an zero vector. 3930/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3931static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3932 SDValue V1 = N->getOperand(0); 3933 SDValue V2 = N->getOperand(1); 3934 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3935 for (unsigned i = 0; i != NumElems; ++i) { 3936 int Idx = N->getMaskElt(i); 3937 if (Idx >= (int)NumElems) { 3938 unsigned Opc = V2.getOpcode(); 3939 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3940 continue; 3941 if (Opc != ISD::BUILD_VECTOR || 3942 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3943 return false; 3944 } else if (Idx >= 0) { 3945 unsigned Opc = V1.getOpcode(); 3946 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3947 continue; 3948 if (Opc != ISD::BUILD_VECTOR || 3949 !X86::isZeroNode(V1.getOperand(Idx))) 3950 return false; 3951 } 3952 } 3953 return true; 3954} 3955 3956/// getZeroVector - Returns a vector of specified type with all zero elements. 3957/// 3958static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3959 DebugLoc dl) { 3960 assert(VT.isVector() && "Expected a vector type"); 3961 3962 // Always build SSE zero vectors as <4 x i32> bitcasted 3963 // to their dest type. This ensures they get CSE'd. 3964 SDValue Vec; 3965 if (VT.getSizeInBits() == 128) { // SSE 3966 if (HasSSE2) { // SSE2 3967 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3968 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3969 } else { // SSE1 3970 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3972 } 3973 } else if (VT.getSizeInBits() == 256) { // AVX 3974 // 256-bit logic and arithmetic instructions in AVX are 3975 // all floating-point, no support for integer ops. Default 3976 // to emitting fp zeroed vectors then. 3977 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3978 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3979 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3980 } 3981 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3982} 3983 3984/// getOnesVector - Returns a vector of specified type with all bits set. 3985/// Always build ones vectors as <4 x i32>. For 256-bit types, use two 3986/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 3987/// original type, ensuring they get CSE'd. 3988static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3989 assert(VT.isVector() && "Expected a vector type"); 3990 assert((VT.is128BitVector() || VT.is256BitVector()) 3991 && "Expected a 128-bit or 256-bit vector type"); 3992 3993 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3994 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 3995 Cst, Cst, Cst, Cst); 3996 3997 if (VT.is256BitVector()) { 3998 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 3999 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4000 Vec = Insert128BitVector(InsV, Vec, 4001 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4002 } 4003 4004 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4005} 4006 4007/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4008/// that point to V2 points to its first element. 4009static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4010 EVT VT = SVOp->getValueType(0); 4011 unsigned NumElems = VT.getVectorNumElements(); 4012 4013 bool Changed = false; 4014 SmallVector<int, 8> MaskVec; 4015 SVOp->getMask(MaskVec); 4016 4017 for (unsigned i = 0; i != NumElems; ++i) { 4018 if (MaskVec[i] > (int)NumElems) { 4019 MaskVec[i] = NumElems; 4020 Changed = true; 4021 } 4022 } 4023 if (Changed) 4024 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4025 SVOp->getOperand(1), &MaskVec[0]); 4026 return SDValue(SVOp, 0); 4027} 4028 4029/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4030/// operation of specified width. 4031static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4032 SDValue V2) { 4033 unsigned NumElems = VT.getVectorNumElements(); 4034 SmallVector<int, 8> Mask; 4035 Mask.push_back(NumElems); 4036 for (unsigned i = 1; i != NumElems; ++i) 4037 Mask.push_back(i); 4038 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4039} 4040 4041/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4042static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4043 SDValue V2) { 4044 unsigned NumElems = VT.getVectorNumElements(); 4045 SmallVector<int, 8> Mask; 4046 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4047 Mask.push_back(i); 4048 Mask.push_back(i + NumElems); 4049 } 4050 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4051} 4052 4053/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4054static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4055 SDValue V2) { 4056 unsigned NumElems = VT.getVectorNumElements(); 4057 unsigned Half = NumElems/2; 4058 SmallVector<int, 8> Mask; 4059 for (unsigned i = 0; i != Half; ++i) { 4060 Mask.push_back(i + Half); 4061 Mask.push_back(i + NumElems + Half); 4062 } 4063 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4064} 4065 4066// PromoteSplatv8v16 - All i16 and i8 vector types can't be used directly by 4067// a generic shuffle instruction because the target has no such instructions. 4068// Generate shuffles which repeat i16 and i8 several times until they can be 4069// represented by v4f32 and then be manipulated by target suported shuffles. 4070static SDValue PromoteSplatv8v16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4071 EVT VT = V.getValueType(); 4072 int NumElems = VT.getVectorNumElements(); 4073 DebugLoc dl = V.getDebugLoc(); 4074 4075 while (NumElems > 4) { 4076 if (EltNo < NumElems/2) { 4077 V = getUnpackl(DAG, dl, VT, V, V); 4078 } else { 4079 V = getUnpackh(DAG, dl, VT, V, V); 4080 EltNo -= NumElems/2; 4081 } 4082 NumElems >>= 1; 4083 } 4084 return V; 4085} 4086 4087/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4088static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4089 EVT VT = V.getValueType(); 4090 DebugLoc dl = V.getDebugLoc(); 4091 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4092 && "Vector size not supported"); 4093 4094 bool Is128 = VT.getSizeInBits() == 128; 4095 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32; 4096 V = DAG.getNode(ISD::BITCAST, dl, NVT, V); 4097 4098 if (Is128) { 4099 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4100 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); 4101 } else { 4102 // The second half of indicies refer to the higher part, which is a 4103 // duplication of the lower one. This makes this shuffle a perfect match 4104 // for the VPERM instruction. 4105 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4106 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4107 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); 4108 } 4109 4110 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4111} 4112 4113/// PromoteVectorToScalarSplat - Since there's no native support for 4114/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector + 4115/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the 4116/// shuffle before the insertion, this yields less instructions in the end. 4117static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV, 4118 SelectionDAG &DAG) { 4119 EVT SrcVT = SV->getValueType(0); 4120 SDValue V1 = SV->getOperand(0); 4121 DebugLoc dl = SV->getDebugLoc(); 4122 int NumElems = SrcVT.getVectorNumElements(); 4123 4124 assert(SrcVT.is256BitVector() && "unknown howto handle vector type"); 4125 4126 SmallVector<int, 4> Mask; 4127 for (int i = 0; i < NumElems/2; ++i) 4128 Mask.push_back(SV->getMaskElt(i)); 4129 4130 EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(), 4131 NumElems/2); 4132 SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1), 4133 DAG.getUNDEF(SVT), &Mask[0]); 4134 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1, 4135 DAG.getConstant(0, MVT::i32), DAG, dl); 4136 4137 return Insert128BitVector(InsV, SV1, 4138 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4139} 4140 4141/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and 4142/// v8i32, v16i16 or v32i8 to v8f32. 4143static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4144 EVT SrcVT = SV->getValueType(0); 4145 SDValue V1 = SV->getOperand(0); 4146 DebugLoc dl = SV->getDebugLoc(); 4147 4148 int EltNo = SV->getSplatIndex(); 4149 int NumElems = SrcVT.getVectorNumElements(); 4150 unsigned Size = SrcVT.getSizeInBits(); 4151 4152 // Extract the 128-bit part containing the splat element and update 4153 // the splat element index when it refers to the higher register. 4154 if (Size == 256) { 4155 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4156 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4157 if (Idx > 0) 4158 EltNo -= NumElems/2; 4159 } 4160 4161 // Make this 128-bit vector duplicate i8 and i16 elements 4162 if (NumElems > 4) 4163 V1 = PromoteSplatv8v16(V1, DAG, EltNo); 4164 4165 // Recreate the 256-bit vector and place the same 128-bit vector 4166 // into the low and high part. This is necessary because we want 4167 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles 4168 // inside each separate v4f32 lane. 4169 if (Size == 256) { 4170 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4171 DAG.getConstant(0, MVT::i32), DAG, dl); 4172 V1 = Insert128BitVector(InsV, V1, 4173 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4174 } 4175 4176 return getLegalSplat(DAG, V1, EltNo); 4177} 4178 4179/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4180/// vector of zero or undef vector. This produces a shuffle where the low 4181/// element of V2 is swizzled into the zero/undef vector, landing at element 4182/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4183static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4184 bool isZero, bool HasSSE2, 4185 SelectionDAG &DAG) { 4186 EVT VT = V2.getValueType(); 4187 SDValue V1 = isZero 4188 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4189 unsigned NumElems = VT.getVectorNumElements(); 4190 SmallVector<int, 16> MaskVec; 4191 for (unsigned i = 0; i != NumElems; ++i) 4192 // If this is the insertion idx, put the low elt of V2 here. 4193 MaskVec.push_back(i == Idx ? NumElems : i); 4194 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4195} 4196 4197/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4198/// element of the result of the vector shuffle. 4199static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4200 unsigned Depth) { 4201 if (Depth == 6) 4202 return SDValue(); // Limit search depth. 4203 4204 SDValue V = SDValue(N, 0); 4205 EVT VT = V.getValueType(); 4206 unsigned Opcode = V.getOpcode(); 4207 4208 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4209 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4210 Index = SV->getMaskElt(Index); 4211 4212 if (Index < 0) 4213 return DAG.getUNDEF(VT.getVectorElementType()); 4214 4215 int NumElems = VT.getVectorNumElements(); 4216 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4217 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4218 } 4219 4220 // Recurse into target specific vector shuffles to find scalars. 4221 if (isTargetShuffle(Opcode)) { 4222 int NumElems = VT.getVectorNumElements(); 4223 SmallVector<unsigned, 16> ShuffleMask; 4224 SDValue ImmN; 4225 4226 switch(Opcode) { 4227 case X86ISD::SHUFPS: 4228 case X86ISD::SHUFPD: 4229 ImmN = N->getOperand(N->getNumOperands()-1); 4230 DecodeSHUFPSMask(NumElems, 4231 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4232 ShuffleMask); 4233 break; 4234 case X86ISD::PUNPCKHBW: 4235 case X86ISD::PUNPCKHWD: 4236 case X86ISD::PUNPCKHDQ: 4237 case X86ISD::PUNPCKHQDQ: 4238 DecodePUNPCKHMask(NumElems, ShuffleMask); 4239 break; 4240 case X86ISD::UNPCKHPS: 4241 case X86ISD::UNPCKHPD: 4242 case X86ISD::VUNPCKHPSY: 4243 case X86ISD::VUNPCKHPDY: 4244 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4245 break; 4246 case X86ISD::PUNPCKLBW: 4247 case X86ISD::PUNPCKLWD: 4248 case X86ISD::PUNPCKLDQ: 4249 case X86ISD::PUNPCKLQDQ: 4250 DecodePUNPCKLMask(VT, ShuffleMask); 4251 break; 4252 case X86ISD::UNPCKLPS: 4253 case X86ISD::UNPCKLPD: 4254 case X86ISD::VUNPCKLPSY: 4255 case X86ISD::VUNPCKLPDY: 4256 DecodeUNPCKLPMask(VT, ShuffleMask); 4257 break; 4258 case X86ISD::MOVHLPS: 4259 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4260 break; 4261 case X86ISD::MOVLHPS: 4262 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4263 break; 4264 case X86ISD::PSHUFD: 4265 ImmN = N->getOperand(N->getNumOperands()-1); 4266 DecodePSHUFMask(NumElems, 4267 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4268 ShuffleMask); 4269 break; 4270 case X86ISD::PSHUFHW: 4271 ImmN = N->getOperand(N->getNumOperands()-1); 4272 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4273 ShuffleMask); 4274 break; 4275 case X86ISD::PSHUFLW: 4276 ImmN = N->getOperand(N->getNumOperands()-1); 4277 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4278 ShuffleMask); 4279 break; 4280 case X86ISD::MOVSS: 4281 case X86ISD::MOVSD: { 4282 // The index 0 always comes from the first element of the second source, 4283 // this is why MOVSS and MOVSD are used in the first place. The other 4284 // elements come from the other positions of the first source vector. 4285 unsigned OpNum = (Index == 0) ? 1 : 0; 4286 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4287 Depth+1); 4288 } 4289 case X86ISD::VPERMILPS: 4290 ImmN = N->getOperand(N->getNumOperands()-1); 4291 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4292 ShuffleMask); 4293 break; 4294 case X86ISD::VPERMILPSY: 4295 ImmN = N->getOperand(N->getNumOperands()-1); 4296 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4297 ShuffleMask); 4298 break; 4299 case X86ISD::VPERMILPD: 4300 ImmN = N->getOperand(N->getNumOperands()-1); 4301 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4302 ShuffleMask); 4303 break; 4304 case X86ISD::VPERMILPDY: 4305 ImmN = N->getOperand(N->getNumOperands()-1); 4306 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4307 ShuffleMask); 4308 break; 4309 default: 4310 assert("not implemented for target shuffle node"); 4311 return SDValue(); 4312 } 4313 4314 Index = ShuffleMask[Index]; 4315 if (Index < 0) 4316 return DAG.getUNDEF(VT.getVectorElementType()); 4317 4318 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4319 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4320 Depth+1); 4321 } 4322 4323 // Actual nodes that may contain scalar elements 4324 if (Opcode == ISD::BITCAST) { 4325 V = V.getOperand(0); 4326 EVT SrcVT = V.getValueType(); 4327 unsigned NumElems = VT.getVectorNumElements(); 4328 4329 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4330 return SDValue(); 4331 } 4332 4333 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4334 return (Index == 0) ? V.getOperand(0) 4335 : DAG.getUNDEF(VT.getVectorElementType()); 4336 4337 if (V.getOpcode() == ISD::BUILD_VECTOR) 4338 return V.getOperand(Index); 4339 4340 return SDValue(); 4341} 4342 4343/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4344/// shuffle operation which come from a consecutively from a zero. The 4345/// search can start in two different directions, from left or right. 4346static 4347unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4348 bool ZerosFromLeft, SelectionDAG &DAG) { 4349 int i = 0; 4350 4351 while (i < NumElems) { 4352 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4353 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4354 if (!(Elt.getNode() && 4355 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4356 break; 4357 ++i; 4358 } 4359 4360 return i; 4361} 4362 4363/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4364/// MaskE correspond consecutively to elements from one of the vector operands, 4365/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4366static 4367bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4368 int OpIdx, int NumElems, unsigned &OpNum) { 4369 bool SeenV1 = false; 4370 bool SeenV2 = false; 4371 4372 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4373 int Idx = SVOp->getMaskElt(i); 4374 // Ignore undef indicies 4375 if (Idx < 0) 4376 continue; 4377 4378 if (Idx < NumElems) 4379 SeenV1 = true; 4380 else 4381 SeenV2 = true; 4382 4383 // Only accept consecutive elements from the same vector 4384 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4385 return false; 4386 } 4387 4388 OpNum = SeenV1 ? 0 : 1; 4389 return true; 4390} 4391 4392/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4393/// logical left shift of a vector. 4394static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4395 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4396 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4397 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4398 false /* check zeros from right */, DAG); 4399 unsigned OpSrc; 4400 4401 if (!NumZeros) 4402 return false; 4403 4404 // Considering the elements in the mask that are not consecutive zeros, 4405 // check if they consecutively come from only one of the source vectors. 4406 // 4407 // V1 = {X, A, B, C} 0 4408 // \ \ \ / 4409 // vector_shuffle V1, V2 <1, 2, 3, X> 4410 // 4411 if (!isShuffleMaskConsecutive(SVOp, 4412 0, // Mask Start Index 4413 NumElems-NumZeros-1, // Mask End Index 4414 NumZeros, // Where to start looking in the src vector 4415 NumElems, // Number of elements in vector 4416 OpSrc)) // Which source operand ? 4417 return false; 4418 4419 isLeft = false; 4420 ShAmt = NumZeros; 4421 ShVal = SVOp->getOperand(OpSrc); 4422 return true; 4423} 4424 4425/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4426/// logical left shift of a vector. 4427static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4428 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4429 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4430 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4431 true /* check zeros from left */, DAG); 4432 unsigned OpSrc; 4433 4434 if (!NumZeros) 4435 return false; 4436 4437 // Considering the elements in the mask that are not consecutive zeros, 4438 // check if they consecutively come from only one of the source vectors. 4439 // 4440 // 0 { A, B, X, X } = V2 4441 // / \ / / 4442 // vector_shuffle V1, V2 <X, X, 4, 5> 4443 // 4444 if (!isShuffleMaskConsecutive(SVOp, 4445 NumZeros, // Mask Start Index 4446 NumElems-1, // Mask End Index 4447 0, // Where to start looking in the src vector 4448 NumElems, // Number of elements in vector 4449 OpSrc)) // Which source operand ? 4450 return false; 4451 4452 isLeft = true; 4453 ShAmt = NumZeros; 4454 ShVal = SVOp->getOperand(OpSrc); 4455 return true; 4456} 4457 4458/// isVectorShift - Returns true if the shuffle can be implemented as a 4459/// logical left or right shift of a vector. 4460static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4461 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4462 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4463 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4464 return true; 4465 4466 return false; 4467} 4468 4469/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4470/// 4471static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4472 unsigned NumNonZero, unsigned NumZero, 4473 SelectionDAG &DAG, 4474 const TargetLowering &TLI) { 4475 if (NumNonZero > 8) 4476 return SDValue(); 4477 4478 DebugLoc dl = Op.getDebugLoc(); 4479 SDValue V(0, 0); 4480 bool First = true; 4481 for (unsigned i = 0; i < 16; ++i) { 4482 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4483 if (ThisIsNonZero && First) { 4484 if (NumZero) 4485 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4486 else 4487 V = DAG.getUNDEF(MVT::v8i16); 4488 First = false; 4489 } 4490 4491 if ((i & 1) != 0) { 4492 SDValue ThisElt(0, 0), LastElt(0, 0); 4493 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4494 if (LastIsNonZero) { 4495 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4496 MVT::i16, Op.getOperand(i-1)); 4497 } 4498 if (ThisIsNonZero) { 4499 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4500 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4501 ThisElt, DAG.getConstant(8, MVT::i8)); 4502 if (LastIsNonZero) 4503 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4504 } else 4505 ThisElt = LastElt; 4506 4507 if (ThisElt.getNode()) 4508 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4509 DAG.getIntPtrConstant(i/2)); 4510 } 4511 } 4512 4513 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4514} 4515 4516/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4517/// 4518static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4519 unsigned NumNonZero, unsigned NumZero, 4520 SelectionDAG &DAG, 4521 const TargetLowering &TLI) { 4522 if (NumNonZero > 4) 4523 return SDValue(); 4524 4525 DebugLoc dl = Op.getDebugLoc(); 4526 SDValue V(0, 0); 4527 bool First = true; 4528 for (unsigned i = 0; i < 8; ++i) { 4529 bool isNonZero = (NonZeros & (1 << i)) != 0; 4530 if (isNonZero) { 4531 if (First) { 4532 if (NumZero) 4533 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4534 else 4535 V = DAG.getUNDEF(MVT::v8i16); 4536 First = false; 4537 } 4538 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4539 MVT::v8i16, V, Op.getOperand(i), 4540 DAG.getIntPtrConstant(i)); 4541 } 4542 } 4543 4544 return V; 4545} 4546 4547/// getVShift - Return a vector logical shift node. 4548/// 4549static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4550 unsigned NumBits, SelectionDAG &DAG, 4551 const TargetLowering &TLI, DebugLoc dl) { 4552 EVT ShVT = MVT::v2i64; 4553 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4554 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4555 return DAG.getNode(ISD::BITCAST, dl, VT, 4556 DAG.getNode(Opc, dl, ShVT, SrcOp, 4557 DAG.getConstant(NumBits, 4558 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4559} 4560 4561SDValue 4562X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4563 SelectionDAG &DAG) const { 4564 4565 // Check if the scalar load can be widened into a vector load. And if 4566 // the address is "base + cst" see if the cst can be "absorbed" into 4567 // the shuffle mask. 4568 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4569 SDValue Ptr = LD->getBasePtr(); 4570 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4571 return SDValue(); 4572 EVT PVT = LD->getValueType(0); 4573 if (PVT != MVT::i32 && PVT != MVT::f32) 4574 return SDValue(); 4575 4576 int FI = -1; 4577 int64_t Offset = 0; 4578 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4579 FI = FINode->getIndex(); 4580 Offset = 0; 4581 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4582 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4583 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4584 Offset = Ptr.getConstantOperandVal(1); 4585 Ptr = Ptr.getOperand(0); 4586 } else { 4587 return SDValue(); 4588 } 4589 4590 // FIXME: 256-bit vector instructions don't require a strict alignment, 4591 // improve this code to support it better. 4592 unsigned RequiredAlign = VT.getSizeInBits()/8; 4593 SDValue Chain = LD->getChain(); 4594 // Make sure the stack object alignment is at least 16 or 32. 4595 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4596 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4597 if (MFI->isFixedObjectIndex(FI)) { 4598 // Can't change the alignment. FIXME: It's possible to compute 4599 // the exact stack offset and reference FI + adjust offset instead. 4600 // If someone *really* cares about this. That's the way to implement it. 4601 return SDValue(); 4602 } else { 4603 MFI->setObjectAlignment(FI, RequiredAlign); 4604 } 4605 } 4606 4607 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4608 // Ptr + (Offset & ~15). 4609 if (Offset < 0) 4610 return SDValue(); 4611 if ((Offset % RequiredAlign) & 3) 4612 return SDValue(); 4613 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4614 if (StartOffset) 4615 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4616 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4617 4618 int EltNo = (Offset - StartOffset) >> 2; 4619 int NumElems = VT.getVectorNumElements(); 4620 4621 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4622 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4623 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4624 LD->getPointerInfo().getWithOffset(StartOffset), 4625 false, false, 0); 4626 4627 // Canonicalize it to a v4i32 or v8i32 shuffle. 4628 SmallVector<int, 8> Mask; 4629 for (int i = 0; i < NumElems; ++i) 4630 Mask.push_back(EltNo); 4631 4632 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4633 return DAG.getNode(ISD::BITCAST, dl, NVT, 4634 DAG.getVectorShuffle(CanonVT, dl, V1, 4635 DAG.getUNDEF(CanonVT),&Mask[0])); 4636 } 4637 4638 return SDValue(); 4639} 4640 4641/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4642/// vector of type 'VT', see if the elements can be replaced by a single large 4643/// load which has the same value as a build_vector whose operands are 'elts'. 4644/// 4645/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4646/// 4647/// FIXME: we'd also like to handle the case where the last elements are zero 4648/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4649/// There's even a handy isZeroNode for that purpose. 4650static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4651 DebugLoc &DL, SelectionDAG &DAG) { 4652 EVT EltVT = VT.getVectorElementType(); 4653 unsigned NumElems = Elts.size(); 4654 4655 LoadSDNode *LDBase = NULL; 4656 unsigned LastLoadedElt = -1U; 4657 4658 // For each element in the initializer, see if we've found a load or an undef. 4659 // If we don't find an initial load element, or later load elements are 4660 // non-consecutive, bail out. 4661 for (unsigned i = 0; i < NumElems; ++i) { 4662 SDValue Elt = Elts[i]; 4663 4664 if (!Elt.getNode() || 4665 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4666 return SDValue(); 4667 if (!LDBase) { 4668 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4669 return SDValue(); 4670 LDBase = cast<LoadSDNode>(Elt.getNode()); 4671 LastLoadedElt = i; 4672 continue; 4673 } 4674 if (Elt.getOpcode() == ISD::UNDEF) 4675 continue; 4676 4677 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4678 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4679 return SDValue(); 4680 LastLoadedElt = i; 4681 } 4682 4683 // If we have found an entire vector of loads and undefs, then return a large 4684 // load of the entire vector width starting at the base pointer. If we found 4685 // consecutive loads for the low half, generate a vzext_load node. 4686 if (LastLoadedElt == NumElems - 1) { 4687 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4688 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4689 LDBase->getPointerInfo(), 4690 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4691 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4692 LDBase->getPointerInfo(), 4693 LDBase->isVolatile(), LDBase->isNonTemporal(), 4694 LDBase->getAlignment()); 4695 } else if (NumElems == 4 && LastLoadedElt == 1 && 4696 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4697 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4698 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4699 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, 4700 Ops, 2, MVT::i32, 4701 LDBase->getMemOperand()); 4702 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4703 } 4704 return SDValue(); 4705} 4706 4707SDValue 4708X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4709 DebugLoc dl = Op.getDebugLoc(); 4710 4711 EVT VT = Op.getValueType(); 4712 EVT ExtVT = VT.getVectorElementType(); 4713 unsigned NumElems = Op.getNumOperands(); 4714 4715 // Vectors containing all zeros can be matched by pxor and xorps later 4716 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 4717 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 4718 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 4719 if (Op.getValueType() == MVT::v4i32 || 4720 Op.getValueType() == MVT::v8i32) 4721 return Op; 4722 4723 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4724 } 4725 4726 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 4727 // vectors or broken into v4i32 operations on 256-bit vectors. 4728 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 4729 if (Op.getValueType() == MVT::v4i32) 4730 return Op; 4731 4732 return getOnesVector(Op.getValueType(), DAG, dl); 4733 } 4734 4735 unsigned EVTBits = ExtVT.getSizeInBits(); 4736 4737 unsigned NumZero = 0; 4738 unsigned NumNonZero = 0; 4739 unsigned NonZeros = 0; 4740 bool IsAllConstants = true; 4741 SmallSet<SDValue, 8> Values; 4742 for (unsigned i = 0; i < NumElems; ++i) { 4743 SDValue Elt = Op.getOperand(i); 4744 if (Elt.getOpcode() == ISD::UNDEF) 4745 continue; 4746 Values.insert(Elt); 4747 if (Elt.getOpcode() != ISD::Constant && 4748 Elt.getOpcode() != ISD::ConstantFP) 4749 IsAllConstants = false; 4750 if (X86::isZeroNode(Elt)) 4751 NumZero++; 4752 else { 4753 NonZeros |= (1 << i); 4754 NumNonZero++; 4755 } 4756 } 4757 4758 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4759 if (NumNonZero == 0) 4760 return DAG.getUNDEF(VT); 4761 4762 // Special case for single non-zero, non-undef, element. 4763 if (NumNonZero == 1) { 4764 unsigned Idx = CountTrailingZeros_32(NonZeros); 4765 SDValue Item = Op.getOperand(Idx); 4766 4767 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4768 // the value are obviously zero, truncate the value to i32 and do the 4769 // insertion that way. Only do this if the value is non-constant or if the 4770 // value is a constant being inserted into element 0. It is cheaper to do 4771 // a constant pool load than it is to do a movd + shuffle. 4772 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4773 (!IsAllConstants || Idx == 0)) { 4774 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4775 // Handle SSE only. 4776 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 4777 EVT VecVT = MVT::v4i32; 4778 unsigned VecElts = 4; 4779 4780 // Truncate the value (which may itself be a constant) to i32, and 4781 // convert it to a vector with movd (S2V+shuffle to zero extend). 4782 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4783 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4784 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4785 Subtarget->hasSSE2(), DAG); 4786 4787 // Now we have our 32-bit value zero extended in the low element of 4788 // a vector. If Idx != 0, swizzle it into place. 4789 if (Idx != 0) { 4790 SmallVector<int, 4> Mask; 4791 Mask.push_back(Idx); 4792 for (unsigned i = 1; i != VecElts; ++i) 4793 Mask.push_back(i); 4794 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4795 DAG.getUNDEF(Item.getValueType()), 4796 &Mask[0]); 4797 } 4798 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 4799 } 4800 } 4801 4802 // If we have a constant or non-constant insertion into the low element of 4803 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4804 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4805 // depending on what the source datatype is. 4806 if (Idx == 0) { 4807 if (NumZero == 0) { 4808 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4809 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4810 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4811 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4812 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4813 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4814 DAG); 4815 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4816 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4817 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 4818 EVT MiddleVT = MVT::v4i32; 4819 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4820 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4821 Subtarget->hasSSE2(), DAG); 4822 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 4823 } 4824 } 4825 4826 // Is it a vector logical left shift? 4827 if (NumElems == 2 && Idx == 1 && 4828 X86::isZeroNode(Op.getOperand(0)) && 4829 !X86::isZeroNode(Op.getOperand(1))) { 4830 unsigned NumBits = VT.getSizeInBits(); 4831 return getVShift(true, VT, 4832 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4833 VT, Op.getOperand(1)), 4834 NumBits/2, DAG, *this, dl); 4835 } 4836 4837 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4838 return SDValue(); 4839 4840 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4841 // is a non-constant being inserted into an element other than the low one, 4842 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4843 // movd/movss) to move this into the low element, then shuffle it into 4844 // place. 4845 if (EVTBits == 32) { 4846 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4847 4848 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4849 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4850 Subtarget->hasSSE2(), DAG); 4851 SmallVector<int, 8> MaskVec; 4852 for (unsigned i = 0; i < NumElems; i++) 4853 MaskVec.push_back(i == Idx ? 0 : 1); 4854 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4855 } 4856 } 4857 4858 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4859 if (Values.size() == 1) { 4860 if (EVTBits == 32) { 4861 // Instead of a shuffle like this: 4862 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4863 // Check if it's possible to issue this instead. 4864 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4865 unsigned Idx = CountTrailingZeros_32(NonZeros); 4866 SDValue Item = Op.getOperand(Idx); 4867 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4868 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4869 } 4870 return SDValue(); 4871 } 4872 4873 // A vector full of immediates; various special cases are already 4874 // handled, so this is best done with a single constant-pool load. 4875 if (IsAllConstants) 4876 return SDValue(); 4877 4878 // For AVX-length vectors, build the individual 128-bit pieces and use 4879 // shuffles to put them in place. 4880 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 4881 SmallVector<SDValue, 32> V; 4882 for (unsigned i = 0; i < NumElems; ++i) 4883 V.push_back(Op.getOperand(i)); 4884 4885 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 4886 4887 // Build both the lower and upper subvector. 4888 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 4889 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 4890 NumElems/2); 4891 4892 // Recreate the wider vector with the lower and upper part. 4893 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 4894 DAG.getConstant(0, MVT::i32), DAG, dl); 4895 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 4896 DAG, dl); 4897 } 4898 4899 // Let legalizer expand 2-wide build_vectors. 4900 if (EVTBits == 64) { 4901 if (NumNonZero == 1) { 4902 // One half is zero or undef. 4903 unsigned Idx = CountTrailingZeros_32(NonZeros); 4904 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4905 Op.getOperand(Idx)); 4906 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4907 Subtarget->hasSSE2(), DAG); 4908 } 4909 return SDValue(); 4910 } 4911 4912 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4913 if (EVTBits == 8 && NumElems == 16) { 4914 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4915 *this); 4916 if (V.getNode()) return V; 4917 } 4918 4919 if (EVTBits == 16 && NumElems == 8) { 4920 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4921 *this); 4922 if (V.getNode()) return V; 4923 } 4924 4925 // If element VT is == 32 bits, turn it into a number of shuffles. 4926 SmallVector<SDValue, 8> V; 4927 V.resize(NumElems); 4928 if (NumElems == 4 && NumZero > 0) { 4929 for (unsigned i = 0; i < 4; ++i) { 4930 bool isZero = !(NonZeros & (1 << i)); 4931 if (isZero) 4932 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4933 else 4934 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4935 } 4936 4937 for (unsigned i = 0; i < 2; ++i) { 4938 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4939 default: break; 4940 case 0: 4941 V[i] = V[i*2]; // Must be a zero vector. 4942 break; 4943 case 1: 4944 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4945 break; 4946 case 2: 4947 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4948 break; 4949 case 3: 4950 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4951 break; 4952 } 4953 } 4954 4955 SmallVector<int, 8> MaskVec; 4956 bool Reverse = (NonZeros & 0x3) == 2; 4957 for (unsigned i = 0; i < 2; ++i) 4958 MaskVec.push_back(Reverse ? 1-i : i); 4959 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4960 for (unsigned i = 0; i < 2; ++i) 4961 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4962 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4963 } 4964 4965 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4966 // Check for a build vector of consecutive loads. 4967 for (unsigned i = 0; i < NumElems; ++i) 4968 V[i] = Op.getOperand(i); 4969 4970 // Check for elements which are consecutive loads. 4971 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4972 if (LD.getNode()) 4973 return LD; 4974 4975 // For SSE 4.1, use insertps to put the high elements into the low element. 4976 if (getSubtarget()->hasSSE41()) { 4977 SDValue Result; 4978 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4979 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4980 else 4981 Result = DAG.getUNDEF(VT); 4982 4983 for (unsigned i = 1; i < NumElems; ++i) { 4984 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4985 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4986 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4987 } 4988 return Result; 4989 } 4990 4991 // Otherwise, expand into a number of unpckl*, start by extending each of 4992 // our (non-undef) elements to the full vector width with the element in the 4993 // bottom slot of the vector (which generates no code for SSE). 4994 for (unsigned i = 0; i < NumElems; ++i) { 4995 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4996 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4997 else 4998 V[i] = DAG.getUNDEF(VT); 4999 } 5000 5001 // Next, we iteratively mix elements, e.g. for v4f32: 5002 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5003 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5004 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5005 unsigned EltStride = NumElems >> 1; 5006 while (EltStride != 0) { 5007 for (unsigned i = 0; i < EltStride; ++i) { 5008 // If V[i+EltStride] is undef and this is the first round of mixing, 5009 // then it is safe to just drop this shuffle: V[i] is already in the 5010 // right place, the one element (since it's the first round) being 5011 // inserted as undef can be dropped. This isn't safe for successive 5012 // rounds because they will permute elements within both vectors. 5013 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5014 EltStride == NumElems/2) 5015 continue; 5016 5017 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5018 } 5019 EltStride >>= 1; 5020 } 5021 return V[0]; 5022 } 5023 return SDValue(); 5024} 5025 5026// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5027// them in a MMX register. This is better than doing a stack convert. 5028static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5029 DebugLoc dl = Op.getDebugLoc(); 5030 EVT ResVT = Op.getValueType(); 5031 5032 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5033 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5034 int Mask[2]; 5035 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5036 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5037 InVec = Op.getOperand(1); 5038 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5039 unsigned NumElts = ResVT.getVectorNumElements(); 5040 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5041 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5042 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5043 } else { 5044 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5045 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5046 Mask[0] = 0; Mask[1] = 2; 5047 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5048 } 5049 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5050} 5051 5052// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5053// to create 256-bit vectors from two other 128-bit ones. 5054static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5055 DebugLoc dl = Op.getDebugLoc(); 5056 EVT ResVT = Op.getValueType(); 5057 5058 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5059 5060 SDValue V1 = Op.getOperand(0); 5061 SDValue V2 = Op.getOperand(1); 5062 unsigned NumElems = ResVT.getVectorNumElements(); 5063 5064 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5065 DAG.getConstant(0, MVT::i32), DAG, dl); 5066 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5067 DAG, dl); 5068} 5069 5070SDValue 5071X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5072 EVT ResVT = Op.getValueType(); 5073 5074 assert(Op.getNumOperands() == 2); 5075 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5076 "Unsupported CONCAT_VECTORS for value type"); 5077 5078 // We support concatenate two MMX registers and place them in a MMX register. 5079 // This is better than doing a stack convert. 5080 if (ResVT.is128BitVector()) 5081 return LowerMMXCONCAT_VECTORS(Op, DAG); 5082 5083 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5084 // from two other 128-bit ones. 5085 return LowerAVXCONCAT_VECTORS(Op, DAG); 5086} 5087 5088// v8i16 shuffles - Prefer shuffles in the following order: 5089// 1. [all] pshuflw, pshufhw, optional move 5090// 2. [ssse3] 1 x pshufb 5091// 3. [ssse3] 2 x pshufb + 1 x por 5092// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5093SDValue 5094X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5095 SelectionDAG &DAG) const { 5096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5097 SDValue V1 = SVOp->getOperand(0); 5098 SDValue V2 = SVOp->getOperand(1); 5099 DebugLoc dl = SVOp->getDebugLoc(); 5100 SmallVector<int, 8> MaskVals; 5101 5102 // Determine if more than 1 of the words in each of the low and high quadwords 5103 // of the result come from the same quadword of one of the two inputs. Undef 5104 // mask values count as coming from any quadword, for better codegen. 5105 SmallVector<unsigned, 4> LoQuad(4); 5106 SmallVector<unsigned, 4> HiQuad(4); 5107 BitVector InputQuads(4); 5108 for (unsigned i = 0; i < 8; ++i) { 5109 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 5110 int EltIdx = SVOp->getMaskElt(i); 5111 MaskVals.push_back(EltIdx); 5112 if (EltIdx < 0) { 5113 ++Quad[0]; 5114 ++Quad[1]; 5115 ++Quad[2]; 5116 ++Quad[3]; 5117 continue; 5118 } 5119 ++Quad[EltIdx / 4]; 5120 InputQuads.set(EltIdx / 4); 5121 } 5122 5123 int BestLoQuad = -1; 5124 unsigned MaxQuad = 1; 5125 for (unsigned i = 0; i < 4; ++i) { 5126 if (LoQuad[i] > MaxQuad) { 5127 BestLoQuad = i; 5128 MaxQuad = LoQuad[i]; 5129 } 5130 } 5131 5132 int BestHiQuad = -1; 5133 MaxQuad = 1; 5134 for (unsigned i = 0; i < 4; ++i) { 5135 if (HiQuad[i] > MaxQuad) { 5136 BestHiQuad = i; 5137 MaxQuad = HiQuad[i]; 5138 } 5139 } 5140 5141 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5142 // of the two input vectors, shuffle them into one input vector so only a 5143 // single pshufb instruction is necessary. If There are more than 2 input 5144 // quads, disable the next transformation since it does not help SSSE3. 5145 bool V1Used = InputQuads[0] || InputQuads[1]; 5146 bool V2Used = InputQuads[2] || InputQuads[3]; 5147 if (Subtarget->hasSSSE3()) { 5148 if (InputQuads.count() == 2 && V1Used && V2Used) { 5149 BestLoQuad = InputQuads.find_first(); 5150 BestHiQuad = InputQuads.find_next(BestLoQuad); 5151 } 5152 if (InputQuads.count() > 2) { 5153 BestLoQuad = -1; 5154 BestHiQuad = -1; 5155 } 5156 } 5157 5158 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5159 // the shuffle mask. If a quad is scored as -1, that means that it contains 5160 // words from all 4 input quadwords. 5161 SDValue NewV; 5162 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5163 SmallVector<int, 8> MaskV; 5164 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5165 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5166 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5167 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5168 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5169 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5170 5171 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5172 // source words for the shuffle, to aid later transformations. 5173 bool AllWordsInNewV = true; 5174 bool InOrder[2] = { true, true }; 5175 for (unsigned i = 0; i != 8; ++i) { 5176 int idx = MaskVals[i]; 5177 if (idx != (int)i) 5178 InOrder[i/4] = false; 5179 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5180 continue; 5181 AllWordsInNewV = false; 5182 break; 5183 } 5184 5185 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5186 if (AllWordsInNewV) { 5187 for (int i = 0; i != 8; ++i) { 5188 int idx = MaskVals[i]; 5189 if (idx < 0) 5190 continue; 5191 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5192 if ((idx != i) && idx < 4) 5193 pshufhw = false; 5194 if ((idx != i) && idx > 3) 5195 pshuflw = false; 5196 } 5197 V1 = NewV; 5198 V2Used = false; 5199 BestLoQuad = 0; 5200 BestHiQuad = 1; 5201 } 5202 5203 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5204 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5205 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5206 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5207 unsigned TargetMask = 0; 5208 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5209 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5210 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5211 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5212 V1 = NewV.getOperand(0); 5213 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5214 } 5215 } 5216 5217 // If we have SSSE3, and all words of the result are from 1 input vector, 5218 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5219 // is present, fall back to case 4. 5220 if (Subtarget->hasSSSE3()) { 5221 SmallVector<SDValue,16> pshufbMask; 5222 5223 // If we have elements from both input vectors, set the high bit of the 5224 // shuffle mask element to zero out elements that come from V2 in the V1 5225 // mask, and elements that come from V1 in the V2 mask, so that the two 5226 // results can be OR'd together. 5227 bool TwoInputs = V1Used && V2Used; 5228 for (unsigned i = 0; i != 8; ++i) { 5229 int EltIdx = MaskVals[i] * 2; 5230 if (TwoInputs && (EltIdx >= 16)) { 5231 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5232 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5233 continue; 5234 } 5235 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5236 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5237 } 5238 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5239 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5240 DAG.getNode(ISD::BUILD_VECTOR, dl, 5241 MVT::v16i8, &pshufbMask[0], 16)); 5242 if (!TwoInputs) 5243 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5244 5245 // Calculate the shuffle mask for the second input, shuffle it, and 5246 // OR it with the first shuffled input. 5247 pshufbMask.clear(); 5248 for (unsigned i = 0; i != 8; ++i) { 5249 int EltIdx = MaskVals[i] * 2; 5250 if (EltIdx < 16) { 5251 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5252 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5253 continue; 5254 } 5255 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5256 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5257 } 5258 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5259 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5260 DAG.getNode(ISD::BUILD_VECTOR, dl, 5261 MVT::v16i8, &pshufbMask[0], 16)); 5262 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5263 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5264 } 5265 5266 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5267 // and update MaskVals with new element order. 5268 BitVector InOrder(8); 5269 if (BestLoQuad >= 0) { 5270 SmallVector<int, 8> MaskV; 5271 for (int i = 0; i != 4; ++i) { 5272 int idx = MaskVals[i]; 5273 if (idx < 0) { 5274 MaskV.push_back(-1); 5275 InOrder.set(i); 5276 } else if ((idx / 4) == BestLoQuad) { 5277 MaskV.push_back(idx & 3); 5278 InOrder.set(i); 5279 } else { 5280 MaskV.push_back(-1); 5281 } 5282 } 5283 for (unsigned i = 4; i != 8; ++i) 5284 MaskV.push_back(i); 5285 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5286 &MaskV[0]); 5287 5288 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5289 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5290 NewV.getOperand(0), 5291 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5292 DAG); 5293 } 5294 5295 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5296 // and update MaskVals with the new element order. 5297 if (BestHiQuad >= 0) { 5298 SmallVector<int, 8> MaskV; 5299 for (unsigned i = 0; i != 4; ++i) 5300 MaskV.push_back(i); 5301 for (unsigned i = 4; i != 8; ++i) { 5302 int idx = MaskVals[i]; 5303 if (idx < 0) { 5304 MaskV.push_back(-1); 5305 InOrder.set(i); 5306 } else if ((idx / 4) == BestHiQuad) { 5307 MaskV.push_back((idx & 3) + 4); 5308 InOrder.set(i); 5309 } else { 5310 MaskV.push_back(-1); 5311 } 5312 } 5313 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5314 &MaskV[0]); 5315 5316 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5317 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5318 NewV.getOperand(0), 5319 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5320 DAG); 5321 } 5322 5323 // In case BestHi & BestLo were both -1, which means each quadword has a word 5324 // from each of the four input quadwords, calculate the InOrder bitvector now 5325 // before falling through to the insert/extract cleanup. 5326 if (BestLoQuad == -1 && BestHiQuad == -1) { 5327 NewV = V1; 5328 for (int i = 0; i != 8; ++i) 5329 if (MaskVals[i] < 0 || MaskVals[i] == i) 5330 InOrder.set(i); 5331 } 5332 5333 // The other elements are put in the right place using pextrw and pinsrw. 5334 for (unsigned i = 0; i != 8; ++i) { 5335 if (InOrder[i]) 5336 continue; 5337 int EltIdx = MaskVals[i]; 5338 if (EltIdx < 0) 5339 continue; 5340 SDValue ExtOp = (EltIdx < 8) 5341 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5342 DAG.getIntPtrConstant(EltIdx)) 5343 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5344 DAG.getIntPtrConstant(EltIdx - 8)); 5345 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5346 DAG.getIntPtrConstant(i)); 5347 } 5348 return NewV; 5349} 5350 5351// v16i8 shuffles - Prefer shuffles in the following order: 5352// 1. [ssse3] 1 x pshufb 5353// 2. [ssse3] 2 x pshufb + 1 x por 5354// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5355static 5356SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5357 SelectionDAG &DAG, 5358 const X86TargetLowering &TLI) { 5359 SDValue V1 = SVOp->getOperand(0); 5360 SDValue V2 = SVOp->getOperand(1); 5361 DebugLoc dl = SVOp->getDebugLoc(); 5362 SmallVector<int, 16> MaskVals; 5363 SVOp->getMask(MaskVals); 5364 5365 // If we have SSSE3, case 1 is generated when all result bytes come from 5366 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5367 // present, fall back to case 3. 5368 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5369 bool V1Only = true; 5370 bool V2Only = true; 5371 for (unsigned i = 0; i < 16; ++i) { 5372 int EltIdx = MaskVals[i]; 5373 if (EltIdx < 0) 5374 continue; 5375 if (EltIdx < 16) 5376 V2Only = false; 5377 else 5378 V1Only = false; 5379 } 5380 5381 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5382 if (TLI.getSubtarget()->hasSSSE3()) { 5383 SmallVector<SDValue,16> pshufbMask; 5384 5385 // If all result elements are from one input vector, then only translate 5386 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5387 // 5388 // Otherwise, we have elements from both input vectors, and must zero out 5389 // elements that come from V2 in the first mask, and V1 in the second mask 5390 // so that we can OR them together. 5391 bool TwoInputs = !(V1Only || V2Only); 5392 for (unsigned i = 0; i != 16; ++i) { 5393 int EltIdx = MaskVals[i]; 5394 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5395 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5396 continue; 5397 } 5398 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5399 } 5400 // If all the elements are from V2, assign it to V1 and return after 5401 // building the first pshufb. 5402 if (V2Only) 5403 V1 = V2; 5404 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5405 DAG.getNode(ISD::BUILD_VECTOR, dl, 5406 MVT::v16i8, &pshufbMask[0], 16)); 5407 if (!TwoInputs) 5408 return V1; 5409 5410 // Calculate the shuffle mask for the second input, shuffle it, and 5411 // OR it with the first shuffled input. 5412 pshufbMask.clear(); 5413 for (unsigned i = 0; i != 16; ++i) { 5414 int EltIdx = MaskVals[i]; 5415 if (EltIdx < 16) { 5416 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5417 continue; 5418 } 5419 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5420 } 5421 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5422 DAG.getNode(ISD::BUILD_VECTOR, dl, 5423 MVT::v16i8, &pshufbMask[0], 16)); 5424 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5425 } 5426 5427 // No SSSE3 - Calculate in place words and then fix all out of place words 5428 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5429 // the 16 different words that comprise the two doublequadword input vectors. 5430 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5431 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5432 SDValue NewV = V2Only ? V2 : V1; 5433 for (int i = 0; i != 8; ++i) { 5434 int Elt0 = MaskVals[i*2]; 5435 int Elt1 = MaskVals[i*2+1]; 5436 5437 // This word of the result is all undef, skip it. 5438 if (Elt0 < 0 && Elt1 < 0) 5439 continue; 5440 5441 // This word of the result is already in the correct place, skip it. 5442 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5443 continue; 5444 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5445 continue; 5446 5447 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5448 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5449 SDValue InsElt; 5450 5451 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5452 // using a single extract together, load it and store it. 5453 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5454 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5455 DAG.getIntPtrConstant(Elt1 / 2)); 5456 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5457 DAG.getIntPtrConstant(i)); 5458 continue; 5459 } 5460 5461 // If Elt1 is defined, extract it from the appropriate source. If the 5462 // source byte is not also odd, shift the extracted word left 8 bits 5463 // otherwise clear the bottom 8 bits if we need to do an or. 5464 if (Elt1 >= 0) { 5465 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5466 DAG.getIntPtrConstant(Elt1 / 2)); 5467 if ((Elt1 & 1) == 0) 5468 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5469 DAG.getConstant(8, 5470 TLI.getShiftAmountTy(InsElt.getValueType()))); 5471 else if (Elt0 >= 0) 5472 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5473 DAG.getConstant(0xFF00, MVT::i16)); 5474 } 5475 // If Elt0 is defined, extract it from the appropriate source. If the 5476 // source byte is not also even, shift the extracted word right 8 bits. If 5477 // Elt1 was also defined, OR the extracted values together before 5478 // inserting them in the result. 5479 if (Elt0 >= 0) { 5480 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5481 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5482 if ((Elt0 & 1) != 0) 5483 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5484 DAG.getConstant(8, 5485 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5486 else if (Elt1 >= 0) 5487 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5488 DAG.getConstant(0x00FF, MVT::i16)); 5489 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5490 : InsElt0; 5491 } 5492 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5493 DAG.getIntPtrConstant(i)); 5494 } 5495 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5496} 5497 5498/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5499/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5500/// done when every pair / quad of shuffle mask elements point to elements in 5501/// the right sequence. e.g. 5502/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5503static 5504SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5505 SelectionDAG &DAG, DebugLoc dl) { 5506 EVT VT = SVOp->getValueType(0); 5507 SDValue V1 = SVOp->getOperand(0); 5508 SDValue V2 = SVOp->getOperand(1); 5509 unsigned NumElems = VT.getVectorNumElements(); 5510 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5511 EVT NewVT; 5512 switch (VT.getSimpleVT().SimpleTy) { 5513 default: assert(false && "Unexpected!"); 5514 case MVT::v4f32: NewVT = MVT::v2f64; break; 5515 case MVT::v4i32: NewVT = MVT::v2i64; break; 5516 case MVT::v8i16: NewVT = MVT::v4i32; break; 5517 case MVT::v16i8: NewVT = MVT::v4i32; break; 5518 } 5519 5520 int Scale = NumElems / NewWidth; 5521 SmallVector<int, 8> MaskVec; 5522 for (unsigned i = 0; i < NumElems; i += Scale) { 5523 int StartIdx = -1; 5524 for (int j = 0; j < Scale; ++j) { 5525 int EltIdx = SVOp->getMaskElt(i+j); 5526 if (EltIdx < 0) 5527 continue; 5528 if (StartIdx == -1) 5529 StartIdx = EltIdx - (EltIdx % Scale); 5530 if (EltIdx != StartIdx + j) 5531 return SDValue(); 5532 } 5533 if (StartIdx == -1) 5534 MaskVec.push_back(-1); 5535 else 5536 MaskVec.push_back(StartIdx / Scale); 5537 } 5538 5539 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5540 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5541 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5542} 5543 5544/// getVZextMovL - Return a zero-extending vector move low node. 5545/// 5546static SDValue getVZextMovL(EVT VT, EVT OpVT, 5547 SDValue SrcOp, SelectionDAG &DAG, 5548 const X86Subtarget *Subtarget, DebugLoc dl) { 5549 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5550 LoadSDNode *LD = NULL; 5551 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5552 LD = dyn_cast<LoadSDNode>(SrcOp); 5553 if (!LD) { 5554 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5555 // instead. 5556 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5557 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5558 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5559 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5560 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5561 // PR2108 5562 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5563 return DAG.getNode(ISD::BITCAST, dl, VT, 5564 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5565 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5566 OpVT, 5567 SrcOp.getOperand(0) 5568 .getOperand(0)))); 5569 } 5570 } 5571 } 5572 5573 return DAG.getNode(ISD::BITCAST, dl, VT, 5574 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5575 DAG.getNode(ISD::BITCAST, dl, 5576 OpVT, SrcOp))); 5577} 5578 5579/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5580/// which could not be matched by any known target speficic shuffle 5581static SDValue 5582LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5583 return SDValue(); 5584} 5585 5586/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5587/// 4 elements, and match them with several different shuffle types. 5588static SDValue 5589LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5590 SDValue V1 = SVOp->getOperand(0); 5591 SDValue V2 = SVOp->getOperand(1); 5592 DebugLoc dl = SVOp->getDebugLoc(); 5593 EVT VT = SVOp->getValueType(0); 5594 5595 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5596 5597 SmallVector<std::pair<int, int>, 8> Locs; 5598 Locs.resize(4); 5599 SmallVector<int, 8> Mask1(4U, -1); 5600 SmallVector<int, 8> PermMask; 5601 SVOp->getMask(PermMask); 5602 5603 unsigned NumHi = 0; 5604 unsigned NumLo = 0; 5605 for (unsigned i = 0; i != 4; ++i) { 5606 int Idx = PermMask[i]; 5607 if (Idx < 0) { 5608 Locs[i] = std::make_pair(-1, -1); 5609 } else { 5610 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5611 if (Idx < 4) { 5612 Locs[i] = std::make_pair(0, NumLo); 5613 Mask1[NumLo] = Idx; 5614 NumLo++; 5615 } else { 5616 Locs[i] = std::make_pair(1, NumHi); 5617 if (2+NumHi < 4) 5618 Mask1[2+NumHi] = Idx; 5619 NumHi++; 5620 } 5621 } 5622 } 5623 5624 if (NumLo <= 2 && NumHi <= 2) { 5625 // If no more than two elements come from either vector. This can be 5626 // implemented with two shuffles. First shuffle gather the elements. 5627 // The second shuffle, which takes the first shuffle as both of its 5628 // vector operands, put the elements into the right order. 5629 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5630 5631 SmallVector<int, 8> Mask2(4U, -1); 5632 5633 for (unsigned i = 0; i != 4; ++i) { 5634 if (Locs[i].first == -1) 5635 continue; 5636 else { 5637 unsigned Idx = (i < 2) ? 0 : 4; 5638 Idx += Locs[i].first * 2 + Locs[i].second; 5639 Mask2[i] = Idx; 5640 } 5641 } 5642 5643 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 5644 } else if (NumLo == 3 || NumHi == 3) { 5645 // Otherwise, we must have three elements from one vector, call it X, and 5646 // one element from the other, call it Y. First, use a shufps to build an 5647 // intermediate vector with the one element from Y and the element from X 5648 // that will be in the same half in the final destination (the indexes don't 5649 // matter). Then, use a shufps to build the final vector, taking the half 5650 // containing the element from Y from the intermediate, and the other half 5651 // from X. 5652 if (NumHi == 3) { 5653 // Normalize it so the 3 elements come from V1. 5654 CommuteVectorShuffleMask(PermMask, VT); 5655 std::swap(V1, V2); 5656 } 5657 5658 // Find the element from V2. 5659 unsigned HiIndex; 5660 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 5661 int Val = PermMask[HiIndex]; 5662 if (Val < 0) 5663 continue; 5664 if (Val >= 4) 5665 break; 5666 } 5667 5668 Mask1[0] = PermMask[HiIndex]; 5669 Mask1[1] = -1; 5670 Mask1[2] = PermMask[HiIndex^1]; 5671 Mask1[3] = -1; 5672 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5673 5674 if (HiIndex >= 2) { 5675 Mask1[0] = PermMask[0]; 5676 Mask1[1] = PermMask[1]; 5677 Mask1[2] = HiIndex & 1 ? 6 : 4; 5678 Mask1[3] = HiIndex & 1 ? 4 : 6; 5679 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5680 } else { 5681 Mask1[0] = HiIndex & 1 ? 2 : 0; 5682 Mask1[1] = HiIndex & 1 ? 0 : 2; 5683 Mask1[2] = PermMask[2]; 5684 Mask1[3] = PermMask[3]; 5685 if (Mask1[2] >= 0) 5686 Mask1[2] += 4; 5687 if (Mask1[3] >= 0) 5688 Mask1[3] += 4; 5689 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 5690 } 5691 } 5692 5693 // Break it into (shuffle shuffle_hi, shuffle_lo). 5694 Locs.clear(); 5695 Locs.resize(4); 5696 SmallVector<int,8> LoMask(4U, -1); 5697 SmallVector<int,8> HiMask(4U, -1); 5698 5699 SmallVector<int,8> *MaskPtr = &LoMask; 5700 unsigned MaskIdx = 0; 5701 unsigned LoIdx = 0; 5702 unsigned HiIdx = 2; 5703 for (unsigned i = 0; i != 4; ++i) { 5704 if (i == 2) { 5705 MaskPtr = &HiMask; 5706 MaskIdx = 1; 5707 LoIdx = 0; 5708 HiIdx = 2; 5709 } 5710 int Idx = PermMask[i]; 5711 if (Idx < 0) { 5712 Locs[i] = std::make_pair(-1, -1); 5713 } else if (Idx < 4) { 5714 Locs[i] = std::make_pair(MaskIdx, LoIdx); 5715 (*MaskPtr)[LoIdx] = Idx; 5716 LoIdx++; 5717 } else { 5718 Locs[i] = std::make_pair(MaskIdx, HiIdx); 5719 (*MaskPtr)[HiIdx] = Idx; 5720 HiIdx++; 5721 } 5722 } 5723 5724 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 5725 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 5726 SmallVector<int, 8> MaskOps; 5727 for (unsigned i = 0; i != 4; ++i) { 5728 if (Locs[i].first == -1) { 5729 MaskOps.push_back(-1); 5730 } else { 5731 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5732 MaskOps.push_back(Idx); 5733 } 5734 } 5735 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5736} 5737 5738static bool MayFoldVectorLoad(SDValue V) { 5739 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5740 V = V.getOperand(0); 5741 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5742 V = V.getOperand(0); 5743 if (MayFoldLoad(V)) 5744 return true; 5745 return false; 5746} 5747 5748// FIXME: the version above should always be used. Since there's 5749// a bug where several vector shuffles can't be folded because the 5750// DAG is not updated during lowering and a node claims to have two 5751// uses while it only has one, use this version, and let isel match 5752// another instruction if the load really happens to have more than 5753// one use. Remove this version after this bug get fixed. 5754// rdar://8434668, PR8156 5755static bool RelaxedMayFoldVectorLoad(SDValue V) { 5756 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5757 V = V.getOperand(0); 5758 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5759 V = V.getOperand(0); 5760 if (ISD::isNormalLoad(V.getNode())) 5761 return true; 5762 return false; 5763} 5764 5765/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 5766/// a vector extract, and if both can be later optimized into a single load. 5767/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 5768/// here because otherwise a target specific shuffle node is going to be 5769/// emitted for this shuffle, and the optimization not done. 5770/// FIXME: This is probably not the best approach, but fix the problem 5771/// until the right path is decided. 5772static 5773bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 5774 const TargetLowering &TLI) { 5775 EVT VT = V.getValueType(); 5776 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 5777 5778 // Be sure that the vector shuffle is present in a pattern like this: 5779 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 5780 if (!V.hasOneUse()) 5781 return false; 5782 5783 SDNode *N = *V.getNode()->use_begin(); 5784 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 5785 return false; 5786 5787 SDValue EltNo = N->getOperand(1); 5788 if (!isa<ConstantSDNode>(EltNo)) 5789 return false; 5790 5791 // If the bit convert changed the number of elements, it is unsafe 5792 // to examine the mask. 5793 bool HasShuffleIntoBitcast = false; 5794 if (V.getOpcode() == ISD::BITCAST) { 5795 EVT SrcVT = V.getOperand(0).getValueType(); 5796 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 5797 return false; 5798 V = V.getOperand(0); 5799 HasShuffleIntoBitcast = true; 5800 } 5801 5802 // Select the input vector, guarding against out of range extract vector. 5803 unsigned NumElems = VT.getVectorNumElements(); 5804 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5805 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 5806 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 5807 5808 // Skip one more bit_convert if necessary 5809 if (V.getOpcode() == ISD::BITCAST) 5810 V = V.getOperand(0); 5811 5812 if (ISD::isNormalLoad(V.getNode())) { 5813 // Is the original load suitable? 5814 LoadSDNode *LN0 = cast<LoadSDNode>(V); 5815 5816 // FIXME: avoid the multi-use bug that is preventing lots of 5817 // of foldings to be detected, this is still wrong of course, but 5818 // give the temporary desired behavior, and if it happens that 5819 // the load has real more uses, during isel it will not fold, and 5820 // will generate poor code. 5821 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 5822 return false; 5823 5824 if (!HasShuffleIntoBitcast) 5825 return true; 5826 5827 // If there's a bitcast before the shuffle, check if the load type and 5828 // alignment is valid. 5829 unsigned Align = LN0->getAlignment(); 5830 unsigned NewAlign = 5831 TLI.getTargetData()->getABITypeAlignment( 5832 VT.getTypeForEVT(*DAG.getContext())); 5833 5834 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 5835 return false; 5836 } 5837 5838 return true; 5839} 5840 5841static 5842SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 5843 EVT VT = Op.getValueType(); 5844 5845 // Canonizalize to v2f64. 5846 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 5847 return DAG.getNode(ISD::BITCAST, dl, VT, 5848 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 5849 V1, DAG)); 5850} 5851 5852static 5853SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5854 bool HasSSE2) { 5855 SDValue V1 = Op.getOperand(0); 5856 SDValue V2 = Op.getOperand(1); 5857 EVT VT = Op.getValueType(); 5858 5859 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5860 5861 if (HasSSE2 && VT == MVT::v2f64) 5862 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5863 5864 // v4f32 or v4i32 5865 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5866} 5867 5868static 5869SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 5870 SDValue V1 = Op.getOperand(0); 5871 SDValue V2 = Op.getOperand(1); 5872 EVT VT = Op.getValueType(); 5873 5874 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 5875 "unsupported shuffle type"); 5876 5877 if (V2.getOpcode() == ISD::UNDEF) 5878 V2 = V1; 5879 5880 // v4i32 or v4f32 5881 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 5882} 5883 5884static 5885SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 5886 SDValue V1 = Op.getOperand(0); 5887 SDValue V2 = Op.getOperand(1); 5888 EVT VT = Op.getValueType(); 5889 unsigned NumElems = VT.getVectorNumElements(); 5890 5891 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 5892 // operand of these instructions is only memory, so check if there's a 5893 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 5894 // same masks. 5895 bool CanFoldLoad = false; 5896 5897 // Trivial case, when V2 comes from a load. 5898 if (MayFoldVectorLoad(V2)) 5899 CanFoldLoad = true; 5900 5901 // When V1 is a load, it can be folded later into a store in isel, example: 5902 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 5903 // turns into: 5904 // (MOVLPSmr addr:$src1, VR128:$src2) 5905 // So, recognize this potential and also use MOVLPS or MOVLPD 5906 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 5907 CanFoldLoad = true; 5908 5909 // Both of them can't be memory operations though. 5910 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 5911 CanFoldLoad = false; 5912 5913 if (CanFoldLoad) { 5914 if (HasSSE2 && NumElems == 2) 5915 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 5916 5917 if (NumElems == 4) 5918 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 5919 } 5920 5921 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5922 // movl and movlp will both match v2i64, but v2i64 is never matched by 5923 // movl earlier because we make it strict to avoid messing with the movlp load 5924 // folding logic (see the code above getMOVLP call). Match it here then, 5925 // this is horrible, but will stay like this until we move all shuffle 5926 // matching to x86 specific nodes. Note that for the 1st condition all 5927 // types are matched with movsd. 5928 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) 5929 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5930 else if (HasSSE2) 5931 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5932 5933 5934 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 5935 5936 // Invert the operand order and use SHUFPS to match it. 5937 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, 5938 X86::getShuffleSHUFImmediate(SVOp), DAG); 5939} 5940 5941static inline unsigned getUNPCKLOpcode(EVT VT) { 5942 switch(VT.getSimpleVT().SimpleTy) { 5943 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 5944 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 5945 case MVT::v4f32: return X86ISD::UNPCKLPS; 5946 case MVT::v2f64: return X86ISD::UNPCKLPD; 5947 case MVT::v8i32: // Use fp unit for int unpack. 5948 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 5949 case MVT::v4i64: // Use fp unit for int unpack. 5950 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 5951 case MVT::v16i8: return X86ISD::PUNPCKLBW; 5952 case MVT::v8i16: return X86ISD::PUNPCKLWD; 5953 default: 5954 llvm_unreachable("Unknown type for unpckl"); 5955 } 5956 return 0; 5957} 5958 5959static inline unsigned getUNPCKHOpcode(EVT VT) { 5960 switch(VT.getSimpleVT().SimpleTy) { 5961 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 5962 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 5963 case MVT::v4f32: return X86ISD::UNPCKHPS; 5964 case MVT::v2f64: return X86ISD::UNPCKHPD; 5965 case MVT::v8i32: // Use fp unit for int unpack. 5966 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 5967 case MVT::v4i64: // Use fp unit for int unpack. 5968 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 5969 case MVT::v16i8: return X86ISD::PUNPCKHBW; 5970 case MVT::v8i16: return X86ISD::PUNPCKHWD; 5971 default: 5972 llvm_unreachable("Unknown type for unpckh"); 5973 } 5974 return 0; 5975} 5976 5977static inline unsigned getVPERMILOpcode(EVT VT) { 5978 switch(VT.getSimpleVT().SimpleTy) { 5979 case MVT::v4i32: 5980 case MVT::v4f32: return X86ISD::VPERMILPS; 5981 case MVT::v2i64: 5982 case MVT::v2f64: return X86ISD::VPERMILPD; 5983 case MVT::v8i32: 5984 case MVT::v8f32: return X86ISD::VPERMILPSY; 5985 case MVT::v4i64: 5986 case MVT::v4f64: return X86ISD::VPERMILPDY; 5987 default: 5988 llvm_unreachable("Unknown type for vpermil"); 5989 } 5990 return 0; 5991} 5992 5993static 5994SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 5995 const TargetLowering &TLI, 5996 const X86Subtarget *Subtarget) { 5997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5998 EVT VT = Op.getValueType(); 5999 DebugLoc dl = Op.getDebugLoc(); 6000 SDValue V1 = Op.getOperand(0); 6001 SDValue V2 = Op.getOperand(1); 6002 6003 if (isZeroShuffle(SVOp)) 6004 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 6005 6006 // Handle splat operations 6007 if (SVOp->isSplat()) { 6008 unsigned NumElem = VT.getVectorNumElements(); 6009 // Special case, this is the only place now where it's allowed to return 6010 // a vector_shuffle operation without using a target specific node, because 6011 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6012 // this be moved to DAGCombine instead? 6013 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6014 return Op; 6015 6016 // Since there's no native support for scalar_to_vector for 256-bit AVX, a 6017 // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this 6018 // idiom and do the shuffle before the insertion, this yields less 6019 // instructions in the end. 6020 if (VT.is256BitVector() && 6021 V1.getOpcode() == ISD::INSERT_SUBVECTOR && 6022 V1.getOperand(0).getOpcode() == ISD::UNDEF && 6023 V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR) 6024 return PromoteVectorToScalarSplat(SVOp, DAG); 6025 6026 // Handle splats by matching through known shuffle masks 6027 if ((VT.is128BitVector() && NumElem <= 4) || 6028 (VT.is256BitVector() && NumElem <= 8)) 6029 return SDValue(); 6030 6031 // All i16 and i8 vector types can't be used directly by a generic shuffle 6032 // instruction because the target has no such instruction. Generate shuffles 6033 // which repeat i16 and i8 several times until they fit in i32, and then can 6034 // be manipulated by target suported shuffles. After the insertion of the 6035 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32. 6036 return PromoteSplat(SVOp, DAG); 6037 } 6038 6039 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6040 // do it! 6041 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6042 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6043 if (NewOp.getNode()) 6044 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6045 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6046 // FIXME: Figure out a cleaner way to do this. 6047 // Try to make use of movq to zero out the top part. 6048 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6049 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6050 if (NewOp.getNode()) { 6051 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6052 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6053 DAG, Subtarget, dl); 6054 } 6055 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6056 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6057 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6058 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6059 DAG, Subtarget, dl); 6060 } 6061 } 6062 return SDValue(); 6063} 6064 6065SDValue 6066X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6068 SDValue V1 = Op.getOperand(0); 6069 SDValue V2 = Op.getOperand(1); 6070 EVT VT = Op.getValueType(); 6071 DebugLoc dl = Op.getDebugLoc(); 6072 unsigned NumElems = VT.getVectorNumElements(); 6073 bool isMMX = VT.getSizeInBits() == 64; 6074 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6075 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6076 bool V1IsSplat = false; 6077 bool V2IsSplat = false; 6078 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 6079 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 6080 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); 6081 MachineFunction &MF = DAG.getMachineFunction(); 6082 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6083 6084 // Shuffle operations on MMX not supported. 6085 if (isMMX) 6086 return Op; 6087 6088 // Vector shuffle lowering takes 3 steps: 6089 // 6090 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6091 // narrowing and commutation of operands should be handled. 6092 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6093 // shuffle nodes. 6094 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6095 // so the shuffle can be broken into other shuffles and the legalizer can 6096 // try the lowering again. 6097 // 6098 // The general ideia is that no vector_shuffle operation should be left to 6099 // be matched during isel, all of them must be converted to a target specific 6100 // node here. 6101 6102 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6103 // narrowing and commutation of operands should be handled. The actual code 6104 // doesn't include all of those, work in progress... 6105 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6106 if (NewOp.getNode()) 6107 return NewOp; 6108 6109 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6110 // unpckh_undef). Only use pshufd if speed is more important than size. 6111 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6112 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6113 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6114 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6115 6116 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && 6117 RelaxedMayFoldVectorLoad(V1)) 6118 return getMOVDDup(Op, dl, V1, DAG); 6119 6120 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6121 return getMOVHighToLow(Op, dl, DAG); 6122 6123 // Use to match splats 6124 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6125 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6126 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6127 6128 if (X86::isPSHUFDMask(SVOp)) { 6129 // The actual implementation will match the mask in the if above and then 6130 // during isel it can match several different instructions, not only pshufd 6131 // as its name says, sad but true, emulate the behavior for now... 6132 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6133 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6134 6135 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6136 6137 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6138 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6139 6140 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6141 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 6142 TargetMask, DAG); 6143 6144 if (VT == MVT::v4f32) 6145 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 6146 TargetMask, DAG); 6147 } 6148 6149 // Check if this can be converted into a logical shift. 6150 bool isLeft = false; 6151 unsigned ShAmt = 0; 6152 SDValue ShVal; 6153 bool isShift = getSubtarget()->hasSSE2() && 6154 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6155 if (isShift && ShVal.hasOneUse()) { 6156 // If the shifted value has multiple uses, it may be cheaper to use 6157 // v_set0 + movlhps or movhlps, etc. 6158 EVT EltVT = VT.getVectorElementType(); 6159 ShAmt *= EltVT.getSizeInBits(); 6160 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6161 } 6162 6163 if (X86::isMOVLMask(SVOp)) { 6164 if (V1IsUndef) 6165 return V2; 6166 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6167 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6168 if (!X86::isMOVLPMask(SVOp)) { 6169 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6170 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6171 6172 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6173 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6174 } 6175 } 6176 6177 // FIXME: fold these into legal mask. 6178 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6179 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6180 6181 if (X86::isMOVHLPSMask(SVOp)) 6182 return getMOVHighToLow(Op, dl, DAG); 6183 6184 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6185 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6186 6187 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6188 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6189 6190 if (X86::isMOVLPMask(SVOp)) 6191 return getMOVLP(Op, dl, DAG, HasSSE2); 6192 6193 if (ShouldXformToMOVHLPS(SVOp) || 6194 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6195 return CommuteVectorShuffle(SVOp, DAG); 6196 6197 if (isShift) { 6198 // No better options. Use a vshl / vsrl. 6199 EVT EltVT = VT.getVectorElementType(); 6200 ShAmt *= EltVT.getSizeInBits(); 6201 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6202 } 6203 6204 bool Commuted = false; 6205 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6206 // 1,1,1,1 -> v8i16 though. 6207 V1IsSplat = isSplatVector(V1.getNode()); 6208 V2IsSplat = isSplatVector(V2.getNode()); 6209 6210 // Canonicalize the splat or undef, if present, to be on the RHS. 6211 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6212 Op = CommuteVectorShuffle(SVOp, DAG); 6213 SVOp = cast<ShuffleVectorSDNode>(Op); 6214 V1 = SVOp->getOperand(0); 6215 V2 = SVOp->getOperand(1); 6216 std::swap(V1IsSplat, V2IsSplat); 6217 std::swap(V1IsUndef, V2IsUndef); 6218 Commuted = true; 6219 } 6220 6221 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6222 // Shuffling low element of v1 into undef, just return v1. 6223 if (V2IsUndef) 6224 return V1; 6225 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6226 // the instruction selector will not match, so get a canonical MOVL with 6227 // swapped operands to undo the commute. 6228 return getMOVL(DAG, dl, VT, V2, V1); 6229 } 6230 6231 if (X86::isUNPCKLMask(SVOp)) 6232 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6233 6234 if (X86::isUNPCKHMask(SVOp)) 6235 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6236 6237 if (V2IsSplat) { 6238 // Normalize mask so all entries that point to V2 points to its first 6239 // element then try to match unpck{h|l} again. If match, return a 6240 // new vector_shuffle with the corrected mask. 6241 SDValue NewMask = NormalizeMask(SVOp, DAG); 6242 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6243 if (NSVOp != SVOp) { 6244 if (X86::isUNPCKLMask(NSVOp, true)) { 6245 return NewMask; 6246 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6247 return NewMask; 6248 } 6249 } 6250 } 6251 6252 if (Commuted) { 6253 // Commute is back and try unpck* again. 6254 // FIXME: this seems wrong. 6255 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6256 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6257 6258 if (X86::isUNPCKLMask(NewSVOp)) 6259 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6260 6261 if (X86::isUNPCKHMask(NewSVOp)) 6262 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6263 } 6264 6265 // Normalize the node to match x86 shuffle ops if needed 6266 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6267 return CommuteVectorShuffle(SVOp, DAG); 6268 6269 // The checks below are all present in isShuffleMaskLegal, but they are 6270 // inlined here right now to enable us to directly emit target specific 6271 // nodes, and remove one by one until they don't return Op anymore. 6272 SmallVector<int, 16> M; 6273 SVOp->getMask(M); 6274 6275 if (isPALIGNRMask(M, VT, HasSSSE3)) 6276 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6277 X86::getShufflePALIGNRImmediate(SVOp), 6278 DAG); 6279 6280 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6281 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6282 if (VT == MVT::v2f64) 6283 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6284 if (VT == MVT::v2i64) 6285 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6286 } 6287 6288 if (isPSHUFHWMask(M, VT)) 6289 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6290 X86::getShufflePSHUFHWImmediate(SVOp), 6291 DAG); 6292 6293 if (isPSHUFLWMask(M, VT)) 6294 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6295 X86::getShufflePSHUFLWImmediate(SVOp), 6296 DAG); 6297 6298 if (isSHUFPMask(M, VT)) { 6299 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6300 if (VT == MVT::v4f32 || VT == MVT::v4i32) 6301 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, 6302 TargetMask, DAG); 6303 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6304 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, 6305 TargetMask, DAG); 6306 } 6307 6308 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6309 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6310 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6311 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6312 6313 //===--------------------------------------------------------------------===// 6314 // Generate target specific nodes for 128 or 256-bit shuffles only 6315 // supported in the AVX instruction set. 6316 // 6317 6318 // Handle VPERMILPS* permutations 6319 if (isVPERMILPSMask(M, VT, Subtarget)) 6320 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6321 getShuffleVPERMILPSImmediate(SVOp), DAG); 6322 6323 // Handle VPERMILPD* permutations 6324 if (isVPERMILPDMask(M, VT, Subtarget)) 6325 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6326 getShuffleVPERMILPDImmediate(SVOp), DAG); 6327 6328 //===--------------------------------------------------------------------===// 6329 // Since no target specific shuffle was selected for this generic one, 6330 // lower it into other known shuffles. FIXME: this isn't true yet, but 6331 // this is the plan. 6332 // 6333 6334 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6335 if (VT == MVT::v8i16) { 6336 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6337 if (NewOp.getNode()) 6338 return NewOp; 6339 } 6340 6341 if (VT == MVT::v16i8) { 6342 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6343 if (NewOp.getNode()) 6344 return NewOp; 6345 } 6346 6347 // Handle all 128-bit wide vectors with 4 elements, and match them with 6348 // several different shuffle types. 6349 if (NumElems == 4 && VT.getSizeInBits() == 128) 6350 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6351 6352 // Handle general 256-bit shuffles 6353 if (VT.is256BitVector()) 6354 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6355 6356 return SDValue(); 6357} 6358 6359SDValue 6360X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6361 SelectionDAG &DAG) const { 6362 EVT VT = Op.getValueType(); 6363 DebugLoc dl = Op.getDebugLoc(); 6364 6365 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6366 return SDValue(); 6367 6368 if (VT.getSizeInBits() == 8) { 6369 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6370 Op.getOperand(0), Op.getOperand(1)); 6371 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6372 DAG.getValueType(VT)); 6373 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6374 } else if (VT.getSizeInBits() == 16) { 6375 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6376 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6377 if (Idx == 0) 6378 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6379 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6380 DAG.getNode(ISD::BITCAST, dl, 6381 MVT::v4i32, 6382 Op.getOperand(0)), 6383 Op.getOperand(1))); 6384 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6385 Op.getOperand(0), Op.getOperand(1)); 6386 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6387 DAG.getValueType(VT)); 6388 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6389 } else if (VT == MVT::f32) { 6390 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6391 // the result back to FR32 register. It's only worth matching if the 6392 // result has a single use which is a store or a bitcast to i32. And in 6393 // the case of a store, it's not worth it if the index is a constant 0, 6394 // because a MOVSSmr can be used instead, which is smaller and faster. 6395 if (!Op.hasOneUse()) 6396 return SDValue(); 6397 SDNode *User = *Op.getNode()->use_begin(); 6398 if ((User->getOpcode() != ISD::STORE || 6399 (isa<ConstantSDNode>(Op.getOperand(1)) && 6400 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6401 (User->getOpcode() != ISD::BITCAST || 6402 User->getValueType(0) != MVT::i32)) 6403 return SDValue(); 6404 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6405 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6406 Op.getOperand(0)), 6407 Op.getOperand(1)); 6408 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6409 } else if (VT == MVT::i32) { 6410 // ExtractPS works with constant index. 6411 if (isa<ConstantSDNode>(Op.getOperand(1))) 6412 return Op; 6413 } 6414 return SDValue(); 6415} 6416 6417 6418SDValue 6419X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6420 SelectionDAG &DAG) const { 6421 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6422 return SDValue(); 6423 6424 SDValue Vec = Op.getOperand(0); 6425 EVT VecVT = Vec.getValueType(); 6426 6427 // If this is a 256-bit vector result, first extract the 128-bit vector and 6428 // then extract the element from the 128-bit vector. 6429 if (VecVT.getSizeInBits() == 256) { 6430 DebugLoc dl = Op.getNode()->getDebugLoc(); 6431 unsigned NumElems = VecVT.getVectorNumElements(); 6432 SDValue Idx = Op.getOperand(1); 6433 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6434 6435 // Get the 128-bit vector. 6436 bool Upper = IdxVal >= NumElems/2; 6437 Vec = Extract128BitVector(Vec, 6438 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6439 6440 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6441 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6442 } 6443 6444 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6445 6446 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 6447 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6448 if (Res.getNode()) 6449 return Res; 6450 } 6451 6452 EVT VT = Op.getValueType(); 6453 DebugLoc dl = Op.getDebugLoc(); 6454 // TODO: handle v16i8. 6455 if (VT.getSizeInBits() == 16) { 6456 SDValue Vec = Op.getOperand(0); 6457 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6458 if (Idx == 0) 6459 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6460 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6461 DAG.getNode(ISD::BITCAST, dl, 6462 MVT::v4i32, Vec), 6463 Op.getOperand(1))); 6464 // Transform it so it match pextrw which produces a 32-bit result. 6465 EVT EltVT = MVT::i32; 6466 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6467 Op.getOperand(0), Op.getOperand(1)); 6468 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6469 DAG.getValueType(VT)); 6470 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6471 } else if (VT.getSizeInBits() == 32) { 6472 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6473 if (Idx == 0) 6474 return Op; 6475 6476 // SHUFPS the element to the lowest double word, then movss. 6477 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6478 EVT VVT = Op.getOperand(0).getValueType(); 6479 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6480 DAG.getUNDEF(VVT), Mask); 6481 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6482 DAG.getIntPtrConstant(0)); 6483 } else if (VT.getSizeInBits() == 64) { 6484 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6485 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6486 // to match extract_elt for f64. 6487 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6488 if (Idx == 0) 6489 return Op; 6490 6491 // UNPCKHPD the element to the lowest double word, then movsd. 6492 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6493 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6494 int Mask[2] = { 1, -1 }; 6495 EVT VVT = Op.getOperand(0).getValueType(); 6496 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6497 DAG.getUNDEF(VVT), Mask); 6498 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6499 DAG.getIntPtrConstant(0)); 6500 } 6501 6502 return SDValue(); 6503} 6504 6505SDValue 6506X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6507 SelectionDAG &DAG) const { 6508 EVT VT = Op.getValueType(); 6509 EVT EltVT = VT.getVectorElementType(); 6510 DebugLoc dl = Op.getDebugLoc(); 6511 6512 SDValue N0 = Op.getOperand(0); 6513 SDValue N1 = Op.getOperand(1); 6514 SDValue N2 = Op.getOperand(2); 6515 6516 if (VT.getSizeInBits() == 256) 6517 return SDValue(); 6518 6519 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6520 isa<ConstantSDNode>(N2)) { 6521 unsigned Opc; 6522 if (VT == MVT::v8i16) 6523 Opc = X86ISD::PINSRW; 6524 else if (VT == MVT::v16i8) 6525 Opc = X86ISD::PINSRB; 6526 else 6527 Opc = X86ISD::PINSRB; 6528 6529 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6530 // argument. 6531 if (N1.getValueType() != MVT::i32) 6532 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6533 if (N2.getValueType() != MVT::i32) 6534 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6535 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6536 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6537 // Bits [7:6] of the constant are the source select. This will always be 6538 // zero here. The DAG Combiner may combine an extract_elt index into these 6539 // bits. For example (insert (extract, 3), 2) could be matched by putting 6540 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6541 // Bits [5:4] of the constant are the destination select. This is the 6542 // value of the incoming immediate. 6543 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6544 // combine either bitwise AND or insert of float 0.0 to set these bits. 6545 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6546 // Create this as a scalar to vector.. 6547 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6548 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6549 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 6550 // PINSR* works with constant index. 6551 return Op; 6552 } 6553 return SDValue(); 6554} 6555 6556SDValue 6557X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6558 EVT VT = Op.getValueType(); 6559 EVT EltVT = VT.getVectorElementType(); 6560 6561 DebugLoc dl = Op.getDebugLoc(); 6562 SDValue N0 = Op.getOperand(0); 6563 SDValue N1 = Op.getOperand(1); 6564 SDValue N2 = Op.getOperand(2); 6565 6566 // If this is a 256-bit vector result, first extract the 128-bit vector, 6567 // insert the element into the extracted half and then place it back. 6568 if (VT.getSizeInBits() == 256) { 6569 if (!isa<ConstantSDNode>(N2)) 6570 return SDValue(); 6571 6572 // Get the desired 128-bit vector half. 6573 unsigned NumElems = VT.getVectorNumElements(); 6574 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6575 bool Upper = IdxVal >= NumElems/2; 6576 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6577 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6578 6579 // Insert the element into the desired half. 6580 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6581 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6582 6583 // Insert the changed part back to the 256-bit vector 6584 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6585 } 6586 6587 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 6588 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6589 6590 if (EltVT == MVT::i8) 6591 return SDValue(); 6592 6593 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6594 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6595 // as its second argument. 6596 if (N1.getValueType() != MVT::i32) 6597 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6598 if (N2.getValueType() != MVT::i32) 6599 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6600 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6601 } 6602 return SDValue(); 6603} 6604 6605SDValue 6606X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6607 LLVMContext *Context = DAG.getContext(); 6608 DebugLoc dl = Op.getDebugLoc(); 6609 EVT OpVT = Op.getValueType(); 6610 6611 // If this is a 256-bit vector result, first insert into a 128-bit 6612 // vector and then insert into the 256-bit vector. 6613 if (OpVT.getSizeInBits() > 128) { 6614 // Insert into a 128-bit vector. 6615 EVT VT128 = EVT::getVectorVT(*Context, 6616 OpVT.getVectorElementType(), 6617 OpVT.getVectorNumElements() / 2); 6618 6619 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6620 6621 // Insert the 128-bit vector. 6622 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6623 DAG.getConstant(0, MVT::i32), 6624 DAG, dl); 6625 } 6626 6627 if (Op.getValueType() == MVT::v1i64 && 6628 Op.getOperand(0).getValueType() == MVT::i64) 6629 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6630 6631 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6632 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6633 "Expected an SSE type!"); 6634 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6635 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6636} 6637 6638// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6639// a simple subregister reference or explicit instructions to grab 6640// upper bits of a vector. 6641SDValue 6642X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6643 if (Subtarget->hasAVX()) { 6644 DebugLoc dl = Op.getNode()->getDebugLoc(); 6645 SDValue Vec = Op.getNode()->getOperand(0); 6646 SDValue Idx = Op.getNode()->getOperand(1); 6647 6648 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6649 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6650 return Extract128BitVector(Vec, Idx, DAG, dl); 6651 } 6652 } 6653 return SDValue(); 6654} 6655 6656// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6657// simple superregister reference or explicit instructions to insert 6658// the upper bits of a vector. 6659SDValue 6660X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6661 if (Subtarget->hasAVX()) { 6662 DebugLoc dl = Op.getNode()->getDebugLoc(); 6663 SDValue Vec = Op.getNode()->getOperand(0); 6664 SDValue SubVec = Op.getNode()->getOperand(1); 6665 SDValue Idx = Op.getNode()->getOperand(2); 6666 6667 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6668 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6669 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6670 } 6671 } 6672 return SDValue(); 6673} 6674 6675// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6676// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6677// one of the above mentioned nodes. It has to be wrapped because otherwise 6678// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6679// be used to form addressing mode. These wrapped nodes will be selected 6680// into MOV32ri. 6681SDValue 6682X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6683 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6684 6685 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6686 // global base reg. 6687 unsigned char OpFlag = 0; 6688 unsigned WrapperKind = X86ISD::Wrapper; 6689 CodeModel::Model M = getTargetMachine().getCodeModel(); 6690 6691 if (Subtarget->isPICStyleRIPRel() && 6692 (M == CodeModel::Small || M == CodeModel::Kernel)) 6693 WrapperKind = X86ISD::WrapperRIP; 6694 else if (Subtarget->isPICStyleGOT()) 6695 OpFlag = X86II::MO_GOTOFF; 6696 else if (Subtarget->isPICStyleStubPIC()) 6697 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6698 6699 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6700 CP->getAlignment(), 6701 CP->getOffset(), OpFlag); 6702 DebugLoc DL = CP->getDebugLoc(); 6703 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6704 // With PIC, the address is actually $g + Offset. 6705 if (OpFlag) { 6706 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6707 DAG.getNode(X86ISD::GlobalBaseReg, 6708 DebugLoc(), getPointerTy()), 6709 Result); 6710 } 6711 6712 return Result; 6713} 6714 6715SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6716 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6717 6718 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6719 // global base reg. 6720 unsigned char OpFlag = 0; 6721 unsigned WrapperKind = X86ISD::Wrapper; 6722 CodeModel::Model M = getTargetMachine().getCodeModel(); 6723 6724 if (Subtarget->isPICStyleRIPRel() && 6725 (M == CodeModel::Small || M == CodeModel::Kernel)) 6726 WrapperKind = X86ISD::WrapperRIP; 6727 else if (Subtarget->isPICStyleGOT()) 6728 OpFlag = X86II::MO_GOTOFF; 6729 else if (Subtarget->isPICStyleStubPIC()) 6730 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6731 6732 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 6733 OpFlag); 6734 DebugLoc DL = JT->getDebugLoc(); 6735 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6736 6737 // With PIC, the address is actually $g + Offset. 6738 if (OpFlag) 6739 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6740 DAG.getNode(X86ISD::GlobalBaseReg, 6741 DebugLoc(), getPointerTy()), 6742 Result); 6743 6744 return Result; 6745} 6746 6747SDValue 6748X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 6749 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 6750 6751 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6752 // global base reg. 6753 unsigned char OpFlag = 0; 6754 unsigned WrapperKind = X86ISD::Wrapper; 6755 CodeModel::Model M = getTargetMachine().getCodeModel(); 6756 6757 if (Subtarget->isPICStyleRIPRel() && 6758 (M == CodeModel::Small || M == CodeModel::Kernel)) 6759 WrapperKind = X86ISD::WrapperRIP; 6760 else if (Subtarget->isPICStyleGOT()) 6761 OpFlag = X86II::MO_GOTOFF; 6762 else if (Subtarget->isPICStyleStubPIC()) 6763 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6764 6765 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 6766 6767 DebugLoc DL = Op.getDebugLoc(); 6768 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6769 6770 6771 // With PIC, the address is actually $g + Offset. 6772 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 6773 !Subtarget->is64Bit()) { 6774 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6775 DAG.getNode(X86ISD::GlobalBaseReg, 6776 DebugLoc(), getPointerTy()), 6777 Result); 6778 } 6779 6780 return Result; 6781} 6782 6783SDValue 6784X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 6785 // Create the TargetBlockAddressAddress node. 6786 unsigned char OpFlags = 6787 Subtarget->ClassifyBlockAddressReference(); 6788 CodeModel::Model M = getTargetMachine().getCodeModel(); 6789 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 6790 DebugLoc dl = Op.getDebugLoc(); 6791 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 6792 /*isTarget=*/true, OpFlags); 6793 6794 if (Subtarget->isPICStyleRIPRel() && 6795 (M == CodeModel::Small || M == CodeModel::Kernel)) 6796 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6797 else 6798 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6799 6800 // With PIC, the address is actually $g + Offset. 6801 if (isGlobalRelativeToPICBase(OpFlags)) { 6802 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6803 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6804 Result); 6805 } 6806 6807 return Result; 6808} 6809 6810SDValue 6811X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 6812 int64_t Offset, 6813 SelectionDAG &DAG) const { 6814 // Create the TargetGlobalAddress node, folding in the constant 6815 // offset if it is legal. 6816 unsigned char OpFlags = 6817 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 6818 CodeModel::Model M = getTargetMachine().getCodeModel(); 6819 SDValue Result; 6820 if (OpFlags == X86II::MO_NO_FLAG && 6821 X86::isOffsetSuitableForCodeModel(Offset, M)) { 6822 // A direct static reference to a global. 6823 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 6824 Offset = 0; 6825 } else { 6826 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 6827 } 6828 6829 if (Subtarget->isPICStyleRIPRel() && 6830 (M == CodeModel::Small || M == CodeModel::Kernel)) 6831 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6832 else 6833 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6834 6835 // With PIC, the address is actually $g + Offset. 6836 if (isGlobalRelativeToPICBase(OpFlags)) { 6837 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6838 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6839 Result); 6840 } 6841 6842 // For globals that require a load from a stub to get the address, emit the 6843 // load. 6844 if (isGlobalStubReference(OpFlags)) 6845 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 6846 MachinePointerInfo::getGOT(), false, false, 0); 6847 6848 // If there was a non-zero offset that we didn't fold, create an explicit 6849 // addition for it. 6850 if (Offset != 0) 6851 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 6852 DAG.getConstant(Offset, getPointerTy())); 6853 6854 return Result; 6855} 6856 6857SDValue 6858X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 6859 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 6860 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 6861 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 6862} 6863 6864static SDValue 6865GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 6866 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 6867 unsigned char OperandFlags) { 6868 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6869 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6870 DebugLoc dl = GA->getDebugLoc(); 6871 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6872 GA->getValueType(0), 6873 GA->getOffset(), 6874 OperandFlags); 6875 if (InFlag) { 6876 SDValue Ops[] = { Chain, TGA, *InFlag }; 6877 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 6878 } else { 6879 SDValue Ops[] = { Chain, TGA }; 6880 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 6881 } 6882 6883 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 6884 MFI->setAdjustsStack(true); 6885 6886 SDValue Flag = Chain.getValue(1); 6887 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 6888} 6889 6890// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 6891static SDValue 6892LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6893 const EVT PtrVT) { 6894 SDValue InFlag; 6895 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 6896 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 6897 DAG.getNode(X86ISD::GlobalBaseReg, 6898 DebugLoc(), PtrVT), InFlag); 6899 InFlag = Chain.getValue(1); 6900 6901 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 6902} 6903 6904// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 6905static SDValue 6906LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6907 const EVT PtrVT) { 6908 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 6909 X86::RAX, X86II::MO_TLSGD); 6910} 6911 6912// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 6913// "local exec" model. 6914static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6915 const EVT PtrVT, TLSModel::Model model, 6916 bool is64Bit) { 6917 DebugLoc dl = GA->getDebugLoc(); 6918 6919 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 6920 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 6921 is64Bit ? 257 : 256)); 6922 6923 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 6924 DAG.getIntPtrConstant(0), 6925 MachinePointerInfo(Ptr), false, false, 0); 6926 6927 unsigned char OperandFlags = 0; 6928 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 6929 // initialexec. 6930 unsigned WrapperKind = X86ISD::Wrapper; 6931 if (model == TLSModel::LocalExec) { 6932 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 6933 } else if (is64Bit) { 6934 assert(model == TLSModel::InitialExec); 6935 OperandFlags = X86II::MO_GOTTPOFF; 6936 WrapperKind = X86ISD::WrapperRIP; 6937 } else { 6938 assert(model == TLSModel::InitialExec); 6939 OperandFlags = X86II::MO_INDNTPOFF; 6940 } 6941 6942 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 6943 // exec) 6944 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6945 GA->getValueType(0), 6946 GA->getOffset(), OperandFlags); 6947 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 6948 6949 if (model == TLSModel::InitialExec) 6950 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 6951 MachinePointerInfo::getGOT(), false, false, 0); 6952 6953 // The address of the thread local variable is the add of the thread 6954 // pointer with the offset of the variable. 6955 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 6956} 6957 6958SDValue 6959X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 6960 6961 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 6962 const GlobalValue *GV = GA->getGlobal(); 6963 6964 if (Subtarget->isTargetELF()) { 6965 // TODO: implement the "local dynamic" model 6966 // TODO: implement the "initial exec"model for pic executables 6967 6968 // If GV is an alias then use the aliasee for determining 6969 // thread-localness. 6970 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 6971 GV = GA->resolveAliasedGlobal(false); 6972 6973 TLSModel::Model model 6974 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 6975 6976 switch (model) { 6977 case TLSModel::GeneralDynamic: 6978 case TLSModel::LocalDynamic: // not implemented 6979 if (Subtarget->is64Bit()) 6980 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 6981 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 6982 6983 case TLSModel::InitialExec: 6984 case TLSModel::LocalExec: 6985 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 6986 Subtarget->is64Bit()); 6987 } 6988 } else if (Subtarget->isTargetDarwin()) { 6989 // Darwin only has one model of TLS. Lower to that. 6990 unsigned char OpFlag = 0; 6991 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 6992 X86ISD::WrapperRIP : X86ISD::Wrapper; 6993 6994 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6995 // global base reg. 6996 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 6997 !Subtarget->is64Bit(); 6998 if (PIC32) 6999 OpFlag = X86II::MO_TLVP_PIC_BASE; 7000 else 7001 OpFlag = X86II::MO_TLVP; 7002 DebugLoc DL = Op.getDebugLoc(); 7003 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7004 GA->getValueType(0), 7005 GA->getOffset(), OpFlag); 7006 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7007 7008 // With PIC32, the address is actually $g + Offset. 7009 if (PIC32) 7010 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7011 DAG.getNode(X86ISD::GlobalBaseReg, 7012 DebugLoc(), getPointerTy()), 7013 Offset); 7014 7015 // Lowering the machine isd will make sure everything is in the right 7016 // location. 7017 SDValue Chain = DAG.getEntryNode(); 7018 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7019 SDValue Args[] = { Chain, Offset }; 7020 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7021 7022 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7023 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7024 MFI->setAdjustsStack(true); 7025 7026 // And our return value (tls address) is in the standard call return value 7027 // location. 7028 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7029 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 7030 } 7031 7032 assert(false && 7033 "TLS not implemented for this target."); 7034 7035 llvm_unreachable("Unreachable"); 7036 return SDValue(); 7037} 7038 7039 7040/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7041/// take a 2 x i32 value to shift plus a shift amount. 7042SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7043 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7044 EVT VT = Op.getValueType(); 7045 unsigned VTBits = VT.getSizeInBits(); 7046 DebugLoc dl = Op.getDebugLoc(); 7047 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7048 SDValue ShOpLo = Op.getOperand(0); 7049 SDValue ShOpHi = Op.getOperand(1); 7050 SDValue ShAmt = Op.getOperand(2); 7051 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7052 DAG.getConstant(VTBits - 1, MVT::i8)) 7053 : DAG.getConstant(0, VT); 7054 7055 SDValue Tmp2, Tmp3; 7056 if (Op.getOpcode() == ISD::SHL_PARTS) { 7057 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7058 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7059 } else { 7060 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7061 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7062 } 7063 7064 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7065 DAG.getConstant(VTBits, MVT::i8)); 7066 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7067 AndNode, DAG.getConstant(0, MVT::i8)); 7068 7069 SDValue Hi, Lo; 7070 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7071 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7072 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7073 7074 if (Op.getOpcode() == ISD::SHL_PARTS) { 7075 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7076 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7077 } else { 7078 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7079 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7080 } 7081 7082 SDValue Ops[2] = { Lo, Hi }; 7083 return DAG.getMergeValues(Ops, 2, dl); 7084} 7085 7086SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7087 SelectionDAG &DAG) const { 7088 EVT SrcVT = Op.getOperand(0).getValueType(); 7089 7090 if (SrcVT.isVector()) 7091 return SDValue(); 7092 7093 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7094 "Unknown SINT_TO_FP to lower!"); 7095 7096 // These are really Legal; return the operand so the caller accepts it as 7097 // Legal. 7098 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7099 return Op; 7100 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7101 Subtarget->is64Bit()) { 7102 return Op; 7103 } 7104 7105 DebugLoc dl = Op.getDebugLoc(); 7106 unsigned Size = SrcVT.getSizeInBits()/8; 7107 MachineFunction &MF = DAG.getMachineFunction(); 7108 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7109 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7110 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7111 StackSlot, 7112 MachinePointerInfo::getFixedStack(SSFI), 7113 false, false, 0); 7114 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7115} 7116 7117SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7118 SDValue StackSlot, 7119 SelectionDAG &DAG) const { 7120 // Build the FILD 7121 DebugLoc DL = Op.getDebugLoc(); 7122 SDVTList Tys; 7123 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7124 if (useSSE) 7125 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7126 else 7127 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7128 7129 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7130 7131 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7132 MachineMemOperand *MMO; 7133 if (FI) { 7134 int SSFI = FI->getIndex(); 7135 MMO = 7136 DAG.getMachineFunction() 7137 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7138 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7139 } else { 7140 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7141 StackSlot = StackSlot.getOperand(1); 7142 } 7143 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7144 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7145 X86ISD::FILD, DL, 7146 Tys, Ops, array_lengthof(Ops), 7147 SrcVT, MMO); 7148 7149 if (useSSE) { 7150 Chain = Result.getValue(1); 7151 SDValue InFlag = Result.getValue(2); 7152 7153 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7154 // shouldn't be necessary except that RFP cannot be live across 7155 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7156 MachineFunction &MF = DAG.getMachineFunction(); 7157 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7158 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7159 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7160 Tys = DAG.getVTList(MVT::Other); 7161 SDValue Ops[] = { 7162 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7163 }; 7164 MachineMemOperand *MMO = 7165 DAG.getMachineFunction() 7166 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7167 MachineMemOperand::MOStore, SSFISize, SSFISize); 7168 7169 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7170 Ops, array_lengthof(Ops), 7171 Op.getValueType(), MMO); 7172 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7173 MachinePointerInfo::getFixedStack(SSFI), 7174 false, false, 0); 7175 } 7176 7177 return Result; 7178} 7179 7180// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7181SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7182 SelectionDAG &DAG) const { 7183 // This algorithm is not obvious. Here it is in C code, more or less: 7184 /* 7185 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7186 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7187 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7188 7189 // Copy ints to xmm registers. 7190 __m128i xh = _mm_cvtsi32_si128( hi ); 7191 __m128i xl = _mm_cvtsi32_si128( lo ); 7192 7193 // Combine into low half of a single xmm register. 7194 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7195 __m128d d; 7196 double sd; 7197 7198 // Merge in appropriate exponents to give the integer bits the right 7199 // magnitude. 7200 x = _mm_unpacklo_epi32( x, exp ); 7201 7202 // Subtract away the biases to deal with the IEEE-754 double precision 7203 // implicit 1. 7204 d = _mm_sub_pd( (__m128d) x, bias ); 7205 7206 // All conversions up to here are exact. The correctly rounded result is 7207 // calculated using the current rounding mode using the following 7208 // horizontal add. 7209 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7210 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7211 // store doesn't really need to be here (except 7212 // maybe to zero the other double) 7213 return sd; 7214 } 7215 */ 7216 7217 DebugLoc dl = Op.getDebugLoc(); 7218 LLVMContext *Context = DAG.getContext(); 7219 7220 // Build some magic constants. 7221 std::vector<Constant*> CV0; 7222 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7223 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7224 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7225 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7226 Constant *C0 = ConstantVector::get(CV0); 7227 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7228 7229 std::vector<Constant*> CV1; 7230 CV1.push_back( 7231 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7232 CV1.push_back( 7233 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7234 Constant *C1 = ConstantVector::get(CV1); 7235 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7236 7237 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7238 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7239 Op.getOperand(0), 7240 DAG.getIntPtrConstant(1))); 7241 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7242 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7243 Op.getOperand(0), 7244 DAG.getIntPtrConstant(0))); 7245 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7246 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7247 MachinePointerInfo::getConstantPool(), 7248 false, false, 16); 7249 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7250 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7251 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7252 MachinePointerInfo::getConstantPool(), 7253 false, false, 16); 7254 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7255 7256 // Add the halves; easiest way is to swap them into another reg first. 7257 int ShufMask[2] = { 1, -1 }; 7258 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7259 DAG.getUNDEF(MVT::v2f64), ShufMask); 7260 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7261 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7262 DAG.getIntPtrConstant(0)); 7263} 7264 7265// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7266SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7267 SelectionDAG &DAG) const { 7268 DebugLoc dl = Op.getDebugLoc(); 7269 // FP constant to bias correct the final result. 7270 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7271 MVT::f64); 7272 7273 // Load the 32-bit value into an XMM register. 7274 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7275 Op.getOperand(0)); 7276 7277 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7278 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7279 DAG.getIntPtrConstant(0)); 7280 7281 // Or the load with the bias. 7282 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7283 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7284 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7285 MVT::v2f64, Load)), 7286 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7287 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7288 MVT::v2f64, Bias))); 7289 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7290 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7291 DAG.getIntPtrConstant(0)); 7292 7293 // Subtract the bias. 7294 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7295 7296 // Handle final rounding. 7297 EVT DestVT = Op.getValueType(); 7298 7299 if (DestVT.bitsLT(MVT::f64)) { 7300 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7301 DAG.getIntPtrConstant(0)); 7302 } else if (DestVT.bitsGT(MVT::f64)) { 7303 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7304 } 7305 7306 // Handle final rounding. 7307 return Sub; 7308} 7309 7310SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7311 SelectionDAG &DAG) const { 7312 SDValue N0 = Op.getOperand(0); 7313 DebugLoc dl = Op.getDebugLoc(); 7314 7315 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7316 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7317 // the optimization here. 7318 if (DAG.SignBitIsZero(N0)) 7319 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7320 7321 EVT SrcVT = N0.getValueType(); 7322 EVT DstVT = Op.getValueType(); 7323 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7324 return LowerUINT_TO_FP_i64(Op, DAG); 7325 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7326 return LowerUINT_TO_FP_i32(Op, DAG); 7327 7328 // Make a 64-bit buffer, and use it to build an FILD. 7329 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7330 if (SrcVT == MVT::i32) { 7331 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7332 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7333 getPointerTy(), StackSlot, WordOff); 7334 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7335 StackSlot, MachinePointerInfo(), 7336 false, false, 0); 7337 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7338 OffsetSlot, MachinePointerInfo(), 7339 false, false, 0); 7340 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7341 return Fild; 7342 } 7343 7344 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7345 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7346 StackSlot, MachinePointerInfo(), 7347 false, false, 0); 7348 // For i64 source, we need to add the appropriate power of 2 if the input 7349 // was negative. This is the same as the optimization in 7350 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7351 // we must be careful to do the computation in x87 extended precision, not 7352 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7353 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7354 MachineMemOperand *MMO = 7355 DAG.getMachineFunction() 7356 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7357 MachineMemOperand::MOLoad, 8, 8); 7358 7359 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7360 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7361 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7362 MVT::i64, MMO); 7363 7364 APInt FF(32, 0x5F800000ULL); 7365 7366 // Check whether the sign bit is set. 7367 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7368 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7369 ISD::SETLT); 7370 7371 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7372 SDValue FudgePtr = DAG.getConstantPool( 7373 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7374 getPointerTy()); 7375 7376 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7377 SDValue Zero = DAG.getIntPtrConstant(0); 7378 SDValue Four = DAG.getIntPtrConstant(4); 7379 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7380 Zero, Four); 7381 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7382 7383 // Load the value out, extending it from f32 to f80. 7384 // FIXME: Avoid the extend by constructing the right constant pool? 7385 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7386 FudgePtr, MachinePointerInfo::getConstantPool(), 7387 MVT::f32, false, false, 4); 7388 // Extend everything to 80 bits to force it to be done on x87. 7389 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7390 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7391} 7392 7393std::pair<SDValue,SDValue> X86TargetLowering:: 7394FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7395 DebugLoc DL = Op.getDebugLoc(); 7396 7397 EVT DstTy = Op.getValueType(); 7398 7399 if (!IsSigned) { 7400 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7401 DstTy = MVT::i64; 7402 } 7403 7404 assert(DstTy.getSimpleVT() <= MVT::i64 && 7405 DstTy.getSimpleVT() >= MVT::i16 && 7406 "Unknown FP_TO_SINT to lower!"); 7407 7408 // These are really Legal. 7409 if (DstTy == MVT::i32 && 7410 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7411 return std::make_pair(SDValue(), SDValue()); 7412 if (Subtarget->is64Bit() && 7413 DstTy == MVT::i64 && 7414 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7415 return std::make_pair(SDValue(), SDValue()); 7416 7417 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7418 // stack slot. 7419 MachineFunction &MF = DAG.getMachineFunction(); 7420 unsigned MemSize = DstTy.getSizeInBits()/8; 7421 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7422 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7423 7424 7425 7426 unsigned Opc; 7427 switch (DstTy.getSimpleVT().SimpleTy) { 7428 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7429 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7430 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7431 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7432 } 7433 7434 SDValue Chain = DAG.getEntryNode(); 7435 SDValue Value = Op.getOperand(0); 7436 EVT TheVT = Op.getOperand(0).getValueType(); 7437 if (isScalarFPTypeInSSEReg(TheVT)) { 7438 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7439 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7440 MachinePointerInfo::getFixedStack(SSFI), 7441 false, false, 0); 7442 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7443 SDValue Ops[] = { 7444 Chain, StackSlot, DAG.getValueType(TheVT) 7445 }; 7446 7447 MachineMemOperand *MMO = 7448 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7449 MachineMemOperand::MOLoad, MemSize, MemSize); 7450 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7451 DstTy, MMO); 7452 Chain = Value.getValue(1); 7453 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7454 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7455 } 7456 7457 MachineMemOperand *MMO = 7458 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7459 MachineMemOperand::MOStore, MemSize, MemSize); 7460 7461 // Build the FP_TO_INT*_IN_MEM 7462 SDValue Ops[] = { Chain, Value, StackSlot }; 7463 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7464 Ops, 3, DstTy, MMO); 7465 7466 return std::make_pair(FIST, StackSlot); 7467} 7468 7469SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7470 SelectionDAG &DAG) const { 7471 if (Op.getValueType().isVector()) 7472 return SDValue(); 7473 7474 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7475 SDValue FIST = Vals.first, StackSlot = Vals.second; 7476 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7477 if (FIST.getNode() == 0) return Op; 7478 7479 // Load the result. 7480 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7481 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7482} 7483 7484SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7485 SelectionDAG &DAG) const { 7486 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7487 SDValue FIST = Vals.first, StackSlot = Vals.second; 7488 assert(FIST.getNode() && "Unexpected failure"); 7489 7490 // Load the result. 7491 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7492 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7493} 7494 7495SDValue X86TargetLowering::LowerFABS(SDValue Op, 7496 SelectionDAG &DAG) const { 7497 LLVMContext *Context = DAG.getContext(); 7498 DebugLoc dl = Op.getDebugLoc(); 7499 EVT VT = Op.getValueType(); 7500 EVT EltVT = VT; 7501 if (VT.isVector()) 7502 EltVT = VT.getVectorElementType(); 7503 std::vector<Constant*> CV; 7504 if (EltVT == MVT::f64) { 7505 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7506 CV.push_back(C); 7507 CV.push_back(C); 7508 } else { 7509 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7510 CV.push_back(C); 7511 CV.push_back(C); 7512 CV.push_back(C); 7513 CV.push_back(C); 7514 } 7515 Constant *C = ConstantVector::get(CV); 7516 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7517 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7518 MachinePointerInfo::getConstantPool(), 7519 false, false, 16); 7520 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7521} 7522 7523SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7524 LLVMContext *Context = DAG.getContext(); 7525 DebugLoc dl = Op.getDebugLoc(); 7526 EVT VT = Op.getValueType(); 7527 EVT EltVT = VT; 7528 if (VT.isVector()) 7529 EltVT = VT.getVectorElementType(); 7530 std::vector<Constant*> CV; 7531 if (EltVT == MVT::f64) { 7532 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7533 CV.push_back(C); 7534 CV.push_back(C); 7535 } else { 7536 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7537 CV.push_back(C); 7538 CV.push_back(C); 7539 CV.push_back(C); 7540 CV.push_back(C); 7541 } 7542 Constant *C = ConstantVector::get(CV); 7543 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7544 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7545 MachinePointerInfo::getConstantPool(), 7546 false, false, 16); 7547 if (VT.isVector()) { 7548 return DAG.getNode(ISD::BITCAST, dl, VT, 7549 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 7550 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7551 Op.getOperand(0)), 7552 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 7553 } else { 7554 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7555 } 7556} 7557 7558SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7559 LLVMContext *Context = DAG.getContext(); 7560 SDValue Op0 = Op.getOperand(0); 7561 SDValue Op1 = Op.getOperand(1); 7562 DebugLoc dl = Op.getDebugLoc(); 7563 EVT VT = Op.getValueType(); 7564 EVT SrcVT = Op1.getValueType(); 7565 7566 // If second operand is smaller, extend it first. 7567 if (SrcVT.bitsLT(VT)) { 7568 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7569 SrcVT = VT; 7570 } 7571 // And if it is bigger, shrink it first. 7572 if (SrcVT.bitsGT(VT)) { 7573 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7574 SrcVT = VT; 7575 } 7576 7577 // At this point the operands and the result should have the same 7578 // type, and that won't be f80 since that is not custom lowered. 7579 7580 // First get the sign bit of second operand. 7581 std::vector<Constant*> CV; 7582 if (SrcVT == MVT::f64) { 7583 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7584 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7585 } else { 7586 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7587 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7588 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7589 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7590 } 7591 Constant *C = ConstantVector::get(CV); 7592 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7593 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7594 MachinePointerInfo::getConstantPool(), 7595 false, false, 16); 7596 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7597 7598 // Shift sign bit right or left if the two operands have different types. 7599 if (SrcVT.bitsGT(VT)) { 7600 // Op0 is MVT::f32, Op1 is MVT::f64. 7601 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7602 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7603 DAG.getConstant(32, MVT::i32)); 7604 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7605 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7606 DAG.getIntPtrConstant(0)); 7607 } 7608 7609 // Clear first operand sign bit. 7610 CV.clear(); 7611 if (VT == MVT::f64) { 7612 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7613 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7614 } else { 7615 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7616 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7617 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7618 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7619 } 7620 C = ConstantVector::get(CV); 7621 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7622 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7623 MachinePointerInfo::getConstantPool(), 7624 false, false, 16); 7625 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7626 7627 // Or the value with the sign bit. 7628 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7629} 7630 7631SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7632 SDValue N0 = Op.getOperand(0); 7633 DebugLoc dl = Op.getDebugLoc(); 7634 EVT VT = Op.getValueType(); 7635 7636 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7637 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7638 DAG.getConstant(1, VT)); 7639 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7640} 7641 7642/// Emit nodes that will be selected as "test Op0,Op0", or something 7643/// equivalent. 7644SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7645 SelectionDAG &DAG) const { 7646 DebugLoc dl = Op.getDebugLoc(); 7647 7648 // CF and OF aren't always set the way we want. Determine which 7649 // of these we need. 7650 bool NeedCF = false; 7651 bool NeedOF = false; 7652 switch (X86CC) { 7653 default: break; 7654 case X86::COND_A: case X86::COND_AE: 7655 case X86::COND_B: case X86::COND_BE: 7656 NeedCF = true; 7657 break; 7658 case X86::COND_G: case X86::COND_GE: 7659 case X86::COND_L: case X86::COND_LE: 7660 case X86::COND_O: case X86::COND_NO: 7661 NeedOF = true; 7662 break; 7663 } 7664 7665 // See if we can use the EFLAGS value from the operand instead of 7666 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7667 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7668 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7669 // Emit a CMP with 0, which is the TEST pattern. 7670 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7671 DAG.getConstant(0, Op.getValueType())); 7672 7673 unsigned Opcode = 0; 7674 unsigned NumOperands = 0; 7675 switch (Op.getNode()->getOpcode()) { 7676 case ISD::ADD: 7677 // Due to an isel shortcoming, be conservative if this add is likely to be 7678 // selected as part of a load-modify-store instruction. When the root node 7679 // in a match is a store, isel doesn't know how to remap non-chain non-flag 7680 // uses of other nodes in the match, such as the ADD in this case. This 7681 // leads to the ADD being left around and reselected, with the result being 7682 // two adds in the output. Alas, even if none our users are stores, that 7683 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 7684 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 7685 // climbing the DAG back to the root, and it doesn't seem to be worth the 7686 // effort. 7687 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7688 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7689 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 7690 goto default_case; 7691 7692 if (ConstantSDNode *C = 7693 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 7694 // An add of one will be selected as an INC. 7695 if (C->getAPIntValue() == 1) { 7696 Opcode = X86ISD::INC; 7697 NumOperands = 1; 7698 break; 7699 } 7700 7701 // An add of negative one (subtract of one) will be selected as a DEC. 7702 if (C->getAPIntValue().isAllOnesValue()) { 7703 Opcode = X86ISD::DEC; 7704 NumOperands = 1; 7705 break; 7706 } 7707 } 7708 7709 // Otherwise use a regular EFLAGS-setting add. 7710 Opcode = X86ISD::ADD; 7711 NumOperands = 2; 7712 break; 7713 case ISD::AND: { 7714 // If the primary and result isn't used, don't bother using X86ISD::AND, 7715 // because a TEST instruction will be better. 7716 bool NonFlagUse = false; 7717 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7718 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 7719 SDNode *User = *UI; 7720 unsigned UOpNo = UI.getOperandNo(); 7721 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 7722 // Look pass truncate. 7723 UOpNo = User->use_begin().getOperandNo(); 7724 User = *User->use_begin(); 7725 } 7726 7727 if (User->getOpcode() != ISD::BRCOND && 7728 User->getOpcode() != ISD::SETCC && 7729 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 7730 NonFlagUse = true; 7731 break; 7732 } 7733 } 7734 7735 if (!NonFlagUse) 7736 break; 7737 } 7738 // FALL THROUGH 7739 case ISD::SUB: 7740 case ISD::OR: 7741 case ISD::XOR: 7742 // Due to the ISEL shortcoming noted above, be conservative if this op is 7743 // likely to be selected as part of a load-modify-store instruction. 7744 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7745 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7746 if (UI->getOpcode() == ISD::STORE) 7747 goto default_case; 7748 7749 // Otherwise use a regular EFLAGS-setting instruction. 7750 switch (Op.getNode()->getOpcode()) { 7751 default: llvm_unreachable("unexpected operator!"); 7752 case ISD::SUB: Opcode = X86ISD::SUB; break; 7753 case ISD::OR: Opcode = X86ISD::OR; break; 7754 case ISD::XOR: Opcode = X86ISD::XOR; break; 7755 case ISD::AND: Opcode = X86ISD::AND; break; 7756 } 7757 7758 NumOperands = 2; 7759 break; 7760 case X86ISD::ADD: 7761 case X86ISD::SUB: 7762 case X86ISD::INC: 7763 case X86ISD::DEC: 7764 case X86ISD::OR: 7765 case X86ISD::XOR: 7766 case X86ISD::AND: 7767 return SDValue(Op.getNode(), 1); 7768 default: 7769 default_case: 7770 break; 7771 } 7772 7773 if (Opcode == 0) 7774 // Emit a CMP with 0, which is the TEST pattern. 7775 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7776 DAG.getConstant(0, Op.getValueType())); 7777 7778 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 7779 SmallVector<SDValue, 4> Ops; 7780 for (unsigned i = 0; i != NumOperands; ++i) 7781 Ops.push_back(Op.getOperand(i)); 7782 7783 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 7784 DAG.ReplaceAllUsesWith(Op, New); 7785 return SDValue(New.getNode(), 1); 7786} 7787 7788/// Emit nodes that will be selected as "cmp Op0,Op1", or something 7789/// equivalent. 7790SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 7791 SelectionDAG &DAG) const { 7792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 7793 if (C->getAPIntValue() == 0) 7794 return EmitTest(Op0, X86CC, DAG); 7795 7796 DebugLoc dl = Op0.getDebugLoc(); 7797 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 7798} 7799 7800/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 7801/// if it's possible. 7802SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 7803 DebugLoc dl, SelectionDAG &DAG) const { 7804 SDValue Op0 = And.getOperand(0); 7805 SDValue Op1 = And.getOperand(1); 7806 if (Op0.getOpcode() == ISD::TRUNCATE) 7807 Op0 = Op0.getOperand(0); 7808 if (Op1.getOpcode() == ISD::TRUNCATE) 7809 Op1 = Op1.getOperand(0); 7810 7811 SDValue LHS, RHS; 7812 if (Op1.getOpcode() == ISD::SHL) 7813 std::swap(Op0, Op1); 7814 if (Op0.getOpcode() == ISD::SHL) { 7815 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 7816 if (And00C->getZExtValue() == 1) { 7817 // If we looked past a truncate, check that it's only truncating away 7818 // known zeros. 7819 unsigned BitWidth = Op0.getValueSizeInBits(); 7820 unsigned AndBitWidth = And.getValueSizeInBits(); 7821 if (BitWidth > AndBitWidth) { 7822 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 7823 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 7824 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 7825 return SDValue(); 7826 } 7827 LHS = Op1; 7828 RHS = Op0.getOperand(1); 7829 } 7830 } else if (Op1.getOpcode() == ISD::Constant) { 7831 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 7832 SDValue AndLHS = Op0; 7833 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 7834 LHS = AndLHS.getOperand(0); 7835 RHS = AndLHS.getOperand(1); 7836 } 7837 } 7838 7839 if (LHS.getNode()) { 7840 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 7841 // instruction. Since the shift amount is in-range-or-undefined, we know 7842 // that doing a bittest on the i32 value is ok. We extend to i32 because 7843 // the encoding for the i16 version is larger than the i32 version. 7844 // Also promote i16 to i32 for performance / code size reason. 7845 if (LHS.getValueType() == MVT::i8 || 7846 LHS.getValueType() == MVT::i16) 7847 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 7848 7849 // If the operand types disagree, extend the shift amount to match. Since 7850 // BT ignores high bits (like shifts) we can use anyextend. 7851 if (LHS.getValueType() != RHS.getValueType()) 7852 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 7853 7854 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 7855 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 7856 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7857 DAG.getConstant(Cond, MVT::i8), BT); 7858 } 7859 7860 return SDValue(); 7861} 7862 7863SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 7864 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 7865 SDValue Op0 = Op.getOperand(0); 7866 SDValue Op1 = Op.getOperand(1); 7867 DebugLoc dl = Op.getDebugLoc(); 7868 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 7869 7870 // Optimize to BT if possible. 7871 // Lower (X & (1 << N)) == 0 to BT(X, N). 7872 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 7873 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 7874 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 7875 Op1.getOpcode() == ISD::Constant && 7876 cast<ConstantSDNode>(Op1)->isNullValue() && 7877 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7878 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 7879 if (NewSetCC.getNode()) 7880 return NewSetCC; 7881 } 7882 7883 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 7884 // these. 7885 if (Op1.getOpcode() == ISD::Constant && 7886 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 7887 cast<ConstantSDNode>(Op1)->isNullValue()) && 7888 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7889 7890 // If the input is a setcc, then reuse the input setcc or use a new one with 7891 // the inverted condition. 7892 if (Op0.getOpcode() == X86ISD::SETCC) { 7893 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 7894 bool Invert = (CC == ISD::SETNE) ^ 7895 cast<ConstantSDNode>(Op1)->isNullValue(); 7896 if (!Invert) return Op0; 7897 7898 CCode = X86::GetOppositeBranchCondition(CCode); 7899 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7900 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 7901 } 7902 } 7903 7904 bool isFP = Op1.getValueType().isFloatingPoint(); 7905 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 7906 if (X86CC == X86::COND_INVALID) 7907 return SDValue(); 7908 7909 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 7910 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7911 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 7912} 7913 7914SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 7915 SDValue Cond; 7916 SDValue Op0 = Op.getOperand(0); 7917 SDValue Op1 = Op.getOperand(1); 7918 SDValue CC = Op.getOperand(2); 7919 EVT VT = Op.getValueType(); 7920 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 7921 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 7922 DebugLoc dl = Op.getDebugLoc(); 7923 7924 if (isFP) { 7925 unsigned SSECC = 8; 7926 EVT EltVT = Op0.getValueType().getVectorElementType(); 7927 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 7928 7929 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 7930 bool Swap = false; 7931 7932 switch (SetCCOpcode) { 7933 default: break; 7934 case ISD::SETOEQ: 7935 case ISD::SETEQ: SSECC = 0; break; 7936 case ISD::SETOGT: 7937 case ISD::SETGT: Swap = true; // Fallthrough 7938 case ISD::SETLT: 7939 case ISD::SETOLT: SSECC = 1; break; 7940 case ISD::SETOGE: 7941 case ISD::SETGE: Swap = true; // Fallthrough 7942 case ISD::SETLE: 7943 case ISD::SETOLE: SSECC = 2; break; 7944 case ISD::SETUO: SSECC = 3; break; 7945 case ISD::SETUNE: 7946 case ISD::SETNE: SSECC = 4; break; 7947 case ISD::SETULE: Swap = true; 7948 case ISD::SETUGE: SSECC = 5; break; 7949 case ISD::SETULT: Swap = true; 7950 case ISD::SETUGT: SSECC = 6; break; 7951 case ISD::SETO: SSECC = 7; break; 7952 } 7953 if (Swap) 7954 std::swap(Op0, Op1); 7955 7956 // In the two special cases we can't handle, emit two comparisons. 7957 if (SSECC == 8) { 7958 if (SetCCOpcode == ISD::SETUEQ) { 7959 SDValue UNORD, EQ; 7960 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 7961 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 7962 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 7963 } 7964 else if (SetCCOpcode == ISD::SETONE) { 7965 SDValue ORD, NEQ; 7966 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 7967 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 7968 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 7969 } 7970 llvm_unreachable("Illegal FP comparison"); 7971 } 7972 // Handle all other FP comparisons here. 7973 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 7974 } 7975 7976 if (!isFP && VT.getSizeInBits() == 256) 7977 return SDValue(); 7978 7979 // We are handling one of the integer comparisons here. Since SSE only has 7980 // GT and EQ comparisons for integer, swapping operands and multiple 7981 // operations may be required for some comparisons. 7982 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 7983 bool Swap = false, Invert = false, FlipSigns = false; 7984 7985 switch (VT.getSimpleVT().SimpleTy) { 7986 default: break; 7987 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 7988 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 7989 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 7990 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 7991 } 7992 7993 switch (SetCCOpcode) { 7994 default: break; 7995 case ISD::SETNE: Invert = true; 7996 case ISD::SETEQ: Opc = EQOpc; break; 7997 case ISD::SETLT: Swap = true; 7998 case ISD::SETGT: Opc = GTOpc; break; 7999 case ISD::SETGE: Swap = true; 8000 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8001 case ISD::SETULT: Swap = true; 8002 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8003 case ISD::SETUGE: Swap = true; 8004 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8005 } 8006 if (Swap) 8007 std::swap(Op0, Op1); 8008 8009 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8010 // bits of the inputs before performing those operations. 8011 if (FlipSigns) { 8012 EVT EltVT = VT.getVectorElementType(); 8013 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8014 EltVT); 8015 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8016 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8017 SignBits.size()); 8018 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8019 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8020 } 8021 8022 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8023 8024 // If the logical-not of the result is required, perform that now. 8025 if (Invert) 8026 Result = DAG.getNOT(dl, Result, VT); 8027 8028 return Result; 8029} 8030 8031// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8032static bool isX86LogicalCmp(SDValue Op) { 8033 unsigned Opc = Op.getNode()->getOpcode(); 8034 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8035 return true; 8036 if (Op.getResNo() == 1 && 8037 (Opc == X86ISD::ADD || 8038 Opc == X86ISD::SUB || 8039 Opc == X86ISD::ADC || 8040 Opc == X86ISD::SBB || 8041 Opc == X86ISD::SMUL || 8042 Opc == X86ISD::UMUL || 8043 Opc == X86ISD::INC || 8044 Opc == X86ISD::DEC || 8045 Opc == X86ISD::OR || 8046 Opc == X86ISD::XOR || 8047 Opc == X86ISD::AND)) 8048 return true; 8049 8050 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8051 return true; 8052 8053 return false; 8054} 8055 8056static bool isZero(SDValue V) { 8057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8058 return C && C->isNullValue(); 8059} 8060 8061static bool isAllOnes(SDValue V) { 8062 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8063 return C && C->isAllOnesValue(); 8064} 8065 8066SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8067 bool addTest = true; 8068 SDValue Cond = Op.getOperand(0); 8069 SDValue Op1 = Op.getOperand(1); 8070 SDValue Op2 = Op.getOperand(2); 8071 DebugLoc DL = Op.getDebugLoc(); 8072 SDValue CC; 8073 8074 if (Cond.getOpcode() == ISD::SETCC) { 8075 SDValue NewCond = LowerSETCC(Cond, DAG); 8076 if (NewCond.getNode()) 8077 Cond = NewCond; 8078 } 8079 8080 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8081 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8082 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8083 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8084 if (Cond.getOpcode() == X86ISD::SETCC && 8085 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8086 isZero(Cond.getOperand(1).getOperand(1))) { 8087 SDValue Cmp = Cond.getOperand(1); 8088 8089 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8090 8091 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8092 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8093 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8094 8095 SDValue CmpOp0 = Cmp.getOperand(0); 8096 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8097 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8098 8099 SDValue Res = // Res = 0 or -1. 8100 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8101 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8102 8103 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8104 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8105 8106 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8107 if (N2C == 0 || !N2C->isNullValue()) 8108 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8109 return Res; 8110 } 8111 } 8112 8113 // Look past (and (setcc_carry (cmp ...)), 1). 8114 if (Cond.getOpcode() == ISD::AND && 8115 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8116 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8117 if (C && C->getAPIntValue() == 1) 8118 Cond = Cond.getOperand(0); 8119 } 8120 8121 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8122 // setting operand in place of the X86ISD::SETCC. 8123 if (Cond.getOpcode() == X86ISD::SETCC || 8124 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8125 CC = Cond.getOperand(0); 8126 8127 SDValue Cmp = Cond.getOperand(1); 8128 unsigned Opc = Cmp.getOpcode(); 8129 EVT VT = Op.getValueType(); 8130 8131 bool IllegalFPCMov = false; 8132 if (VT.isFloatingPoint() && !VT.isVector() && 8133 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8134 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8135 8136 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8137 Opc == X86ISD::BT) { // FIXME 8138 Cond = Cmp; 8139 addTest = false; 8140 } 8141 } 8142 8143 if (addTest) { 8144 // Look pass the truncate. 8145 if (Cond.getOpcode() == ISD::TRUNCATE) 8146 Cond = Cond.getOperand(0); 8147 8148 // We know the result of AND is compared against zero. Try to match 8149 // it to BT. 8150 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8151 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8152 if (NewSetCC.getNode()) { 8153 CC = NewSetCC.getOperand(0); 8154 Cond = NewSetCC.getOperand(1); 8155 addTest = false; 8156 } 8157 } 8158 } 8159 8160 if (addTest) { 8161 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8162 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8163 } 8164 8165 // a < b ? -1 : 0 -> RES = ~setcc_carry 8166 // a < b ? 0 : -1 -> RES = setcc_carry 8167 // a >= b ? -1 : 0 -> RES = setcc_carry 8168 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8169 if (Cond.getOpcode() == X86ISD::CMP) { 8170 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8171 8172 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8173 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8174 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8175 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8176 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8177 return DAG.getNOT(DL, Res, Res.getValueType()); 8178 return Res; 8179 } 8180 } 8181 8182 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8183 // condition is true. 8184 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8185 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8186 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8187} 8188 8189// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8190// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8191// from the AND / OR. 8192static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8193 Opc = Op.getOpcode(); 8194 if (Opc != ISD::OR && Opc != ISD::AND) 8195 return false; 8196 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8197 Op.getOperand(0).hasOneUse() && 8198 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8199 Op.getOperand(1).hasOneUse()); 8200} 8201 8202// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8203// 1 and that the SETCC node has a single use. 8204static bool isXor1OfSetCC(SDValue Op) { 8205 if (Op.getOpcode() != ISD::XOR) 8206 return false; 8207 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8208 if (N1C && N1C->getAPIntValue() == 1) { 8209 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8210 Op.getOperand(0).hasOneUse(); 8211 } 8212 return false; 8213} 8214 8215SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8216 bool addTest = true; 8217 SDValue Chain = Op.getOperand(0); 8218 SDValue Cond = Op.getOperand(1); 8219 SDValue Dest = Op.getOperand(2); 8220 DebugLoc dl = Op.getDebugLoc(); 8221 SDValue CC; 8222 8223 if (Cond.getOpcode() == ISD::SETCC) { 8224 SDValue NewCond = LowerSETCC(Cond, DAG); 8225 if (NewCond.getNode()) 8226 Cond = NewCond; 8227 } 8228#if 0 8229 // FIXME: LowerXALUO doesn't handle these!! 8230 else if (Cond.getOpcode() == X86ISD::ADD || 8231 Cond.getOpcode() == X86ISD::SUB || 8232 Cond.getOpcode() == X86ISD::SMUL || 8233 Cond.getOpcode() == X86ISD::UMUL) 8234 Cond = LowerXALUO(Cond, DAG); 8235#endif 8236 8237 // Look pass (and (setcc_carry (cmp ...)), 1). 8238 if (Cond.getOpcode() == ISD::AND && 8239 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8241 if (C && C->getAPIntValue() == 1) 8242 Cond = Cond.getOperand(0); 8243 } 8244 8245 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8246 // setting operand in place of the X86ISD::SETCC. 8247 if (Cond.getOpcode() == X86ISD::SETCC || 8248 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8249 CC = Cond.getOperand(0); 8250 8251 SDValue Cmp = Cond.getOperand(1); 8252 unsigned Opc = Cmp.getOpcode(); 8253 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8254 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8255 Cond = Cmp; 8256 addTest = false; 8257 } else { 8258 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8259 default: break; 8260 case X86::COND_O: 8261 case X86::COND_B: 8262 // These can only come from an arithmetic instruction with overflow, 8263 // e.g. SADDO, UADDO. 8264 Cond = Cond.getNode()->getOperand(1); 8265 addTest = false; 8266 break; 8267 } 8268 } 8269 } else { 8270 unsigned CondOpc; 8271 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8272 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8273 if (CondOpc == ISD::OR) { 8274 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8275 // two branches instead of an explicit OR instruction with a 8276 // separate test. 8277 if (Cmp == Cond.getOperand(1).getOperand(1) && 8278 isX86LogicalCmp(Cmp)) { 8279 CC = Cond.getOperand(0).getOperand(0); 8280 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8281 Chain, Dest, CC, Cmp); 8282 CC = Cond.getOperand(1).getOperand(0); 8283 Cond = Cmp; 8284 addTest = false; 8285 } 8286 } else { // ISD::AND 8287 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8288 // two branches instead of an explicit AND instruction with a 8289 // separate test. However, we only do this if this block doesn't 8290 // have a fall-through edge, because this requires an explicit 8291 // jmp when the condition is false. 8292 if (Cmp == Cond.getOperand(1).getOperand(1) && 8293 isX86LogicalCmp(Cmp) && 8294 Op.getNode()->hasOneUse()) { 8295 X86::CondCode CCode = 8296 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8297 CCode = X86::GetOppositeBranchCondition(CCode); 8298 CC = DAG.getConstant(CCode, MVT::i8); 8299 SDNode *User = *Op.getNode()->use_begin(); 8300 // Look for an unconditional branch following this conditional branch. 8301 // We need this because we need to reverse the successors in order 8302 // to implement FCMP_OEQ. 8303 if (User->getOpcode() == ISD::BR) { 8304 SDValue FalseBB = User->getOperand(1); 8305 SDNode *NewBR = 8306 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8307 assert(NewBR == User); 8308 (void)NewBR; 8309 Dest = FalseBB; 8310 8311 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8312 Chain, Dest, CC, Cmp); 8313 X86::CondCode CCode = 8314 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8315 CCode = X86::GetOppositeBranchCondition(CCode); 8316 CC = DAG.getConstant(CCode, MVT::i8); 8317 Cond = Cmp; 8318 addTest = false; 8319 } 8320 } 8321 } 8322 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8323 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8324 // It should be transformed during dag combiner except when the condition 8325 // is set by a arithmetics with overflow node. 8326 X86::CondCode CCode = 8327 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8328 CCode = X86::GetOppositeBranchCondition(CCode); 8329 CC = DAG.getConstant(CCode, MVT::i8); 8330 Cond = Cond.getOperand(0).getOperand(1); 8331 addTest = false; 8332 } 8333 } 8334 8335 if (addTest) { 8336 // Look pass the truncate. 8337 if (Cond.getOpcode() == ISD::TRUNCATE) 8338 Cond = Cond.getOperand(0); 8339 8340 // We know the result of AND is compared against zero. Try to match 8341 // it to BT. 8342 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8343 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8344 if (NewSetCC.getNode()) { 8345 CC = NewSetCC.getOperand(0); 8346 Cond = NewSetCC.getOperand(1); 8347 addTest = false; 8348 } 8349 } 8350 } 8351 8352 if (addTest) { 8353 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8354 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8355 } 8356 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8357 Chain, Dest, CC, Cond); 8358} 8359 8360 8361// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8362// Calls to _alloca is needed to probe the stack when allocating more than 4k 8363// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8364// that the guard pages used by the OS virtual memory manager are allocated in 8365// correct sequence. 8366SDValue 8367X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8368 SelectionDAG &DAG) const { 8369 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && 8370 "This should be used only on Windows targets"); 8371 assert(!Subtarget->isTargetEnvMacho()); 8372 DebugLoc dl = Op.getDebugLoc(); 8373 8374 // Get the inputs. 8375 SDValue Chain = Op.getOperand(0); 8376 SDValue Size = Op.getOperand(1); 8377 // FIXME: Ensure alignment here 8378 8379 SDValue Flag; 8380 8381 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 8382 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8383 8384 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8385 Flag = Chain.getValue(1); 8386 8387 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8388 8389 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8390 Flag = Chain.getValue(1); 8391 8392 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8393 8394 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8395 return DAG.getMergeValues(Ops1, 2, dl); 8396} 8397 8398SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8399 MachineFunction &MF = DAG.getMachineFunction(); 8400 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8401 8402 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8403 DebugLoc DL = Op.getDebugLoc(); 8404 8405 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8406 // vastart just stores the address of the VarArgsFrameIndex slot into the 8407 // memory location argument. 8408 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8409 getPointerTy()); 8410 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8411 MachinePointerInfo(SV), false, false, 0); 8412 } 8413 8414 // __va_list_tag: 8415 // gp_offset (0 - 6 * 8) 8416 // fp_offset (48 - 48 + 8 * 16) 8417 // overflow_arg_area (point to parameters coming in memory). 8418 // reg_save_area 8419 SmallVector<SDValue, 8> MemOps; 8420 SDValue FIN = Op.getOperand(1); 8421 // Store gp_offset 8422 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8423 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8424 MVT::i32), 8425 FIN, MachinePointerInfo(SV), false, false, 0); 8426 MemOps.push_back(Store); 8427 8428 // Store fp_offset 8429 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8430 FIN, DAG.getIntPtrConstant(4)); 8431 Store = DAG.getStore(Op.getOperand(0), DL, 8432 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8433 MVT::i32), 8434 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8435 MemOps.push_back(Store); 8436 8437 // Store ptr to overflow_arg_area 8438 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8439 FIN, DAG.getIntPtrConstant(4)); 8440 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8441 getPointerTy()); 8442 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8443 MachinePointerInfo(SV, 8), 8444 false, false, 0); 8445 MemOps.push_back(Store); 8446 8447 // Store ptr to reg_save_area. 8448 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8449 FIN, DAG.getIntPtrConstant(8)); 8450 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 8451 getPointerTy()); 8452 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 8453 MachinePointerInfo(SV, 16), false, false, 0); 8454 MemOps.push_back(Store); 8455 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 8456 &MemOps[0], MemOps.size()); 8457} 8458 8459SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 8460 assert(Subtarget->is64Bit() && 8461 "LowerVAARG only handles 64-bit va_arg!"); 8462 assert((Subtarget->isTargetLinux() || 8463 Subtarget->isTargetDarwin()) && 8464 "Unhandled target in LowerVAARG"); 8465 assert(Op.getNode()->getNumOperands() == 4); 8466 SDValue Chain = Op.getOperand(0); 8467 SDValue SrcPtr = Op.getOperand(1); 8468 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8469 unsigned Align = Op.getConstantOperandVal(3); 8470 DebugLoc dl = Op.getDebugLoc(); 8471 8472 EVT ArgVT = Op.getNode()->getValueType(0); 8473 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 8474 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 8475 uint8_t ArgMode; 8476 8477 // Decide which area this value should be read from. 8478 // TODO: Implement the AMD64 ABI in its entirety. This simple 8479 // selection mechanism works only for the basic types. 8480 if (ArgVT == MVT::f80) { 8481 llvm_unreachable("va_arg for f80 not yet implemented"); 8482 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 8483 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 8484 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 8485 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 8486 } else { 8487 llvm_unreachable("Unhandled argument type in LowerVAARG"); 8488 } 8489 8490 if (ArgMode == 2) { 8491 // Sanity Check: Make sure using fp_offset makes sense. 8492 assert(!UseSoftFloat && 8493 !(DAG.getMachineFunction() 8494 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 8495 Subtarget->hasXMM()); 8496 } 8497 8498 // Insert VAARG_64 node into the DAG 8499 // VAARG_64 returns two values: Variable Argument Address, Chain 8500 SmallVector<SDValue, 11> InstOps; 8501 InstOps.push_back(Chain); 8502 InstOps.push_back(SrcPtr); 8503 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 8504 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 8505 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 8506 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 8507 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 8508 VTs, &InstOps[0], InstOps.size(), 8509 MVT::i64, 8510 MachinePointerInfo(SV), 8511 /*Align=*/0, 8512 /*Volatile=*/false, 8513 /*ReadMem=*/true, 8514 /*WriteMem=*/true); 8515 Chain = VAARG.getValue(1); 8516 8517 // Load the next argument and return it 8518 return DAG.getLoad(ArgVT, dl, 8519 Chain, 8520 VAARG, 8521 MachinePointerInfo(), 8522 false, false, 0); 8523} 8524 8525SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 8526 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 8527 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 8528 SDValue Chain = Op.getOperand(0); 8529 SDValue DstPtr = Op.getOperand(1); 8530 SDValue SrcPtr = Op.getOperand(2); 8531 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 8532 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8533 DebugLoc DL = Op.getDebugLoc(); 8534 8535 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 8536 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 8537 false, 8538 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 8539} 8540 8541SDValue 8542X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 8543 DebugLoc dl = Op.getDebugLoc(); 8544 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8545 switch (IntNo) { 8546 default: return SDValue(); // Don't custom lower most intrinsics. 8547 // Comparison intrinsics. 8548 case Intrinsic::x86_sse_comieq_ss: 8549 case Intrinsic::x86_sse_comilt_ss: 8550 case Intrinsic::x86_sse_comile_ss: 8551 case Intrinsic::x86_sse_comigt_ss: 8552 case Intrinsic::x86_sse_comige_ss: 8553 case Intrinsic::x86_sse_comineq_ss: 8554 case Intrinsic::x86_sse_ucomieq_ss: 8555 case Intrinsic::x86_sse_ucomilt_ss: 8556 case Intrinsic::x86_sse_ucomile_ss: 8557 case Intrinsic::x86_sse_ucomigt_ss: 8558 case Intrinsic::x86_sse_ucomige_ss: 8559 case Intrinsic::x86_sse_ucomineq_ss: 8560 case Intrinsic::x86_sse2_comieq_sd: 8561 case Intrinsic::x86_sse2_comilt_sd: 8562 case Intrinsic::x86_sse2_comile_sd: 8563 case Intrinsic::x86_sse2_comigt_sd: 8564 case Intrinsic::x86_sse2_comige_sd: 8565 case Intrinsic::x86_sse2_comineq_sd: 8566 case Intrinsic::x86_sse2_ucomieq_sd: 8567 case Intrinsic::x86_sse2_ucomilt_sd: 8568 case Intrinsic::x86_sse2_ucomile_sd: 8569 case Intrinsic::x86_sse2_ucomigt_sd: 8570 case Intrinsic::x86_sse2_ucomige_sd: 8571 case Intrinsic::x86_sse2_ucomineq_sd: { 8572 unsigned Opc = 0; 8573 ISD::CondCode CC = ISD::SETCC_INVALID; 8574 switch (IntNo) { 8575 default: break; 8576 case Intrinsic::x86_sse_comieq_ss: 8577 case Intrinsic::x86_sse2_comieq_sd: 8578 Opc = X86ISD::COMI; 8579 CC = ISD::SETEQ; 8580 break; 8581 case Intrinsic::x86_sse_comilt_ss: 8582 case Intrinsic::x86_sse2_comilt_sd: 8583 Opc = X86ISD::COMI; 8584 CC = ISD::SETLT; 8585 break; 8586 case Intrinsic::x86_sse_comile_ss: 8587 case Intrinsic::x86_sse2_comile_sd: 8588 Opc = X86ISD::COMI; 8589 CC = ISD::SETLE; 8590 break; 8591 case Intrinsic::x86_sse_comigt_ss: 8592 case Intrinsic::x86_sse2_comigt_sd: 8593 Opc = X86ISD::COMI; 8594 CC = ISD::SETGT; 8595 break; 8596 case Intrinsic::x86_sse_comige_ss: 8597 case Intrinsic::x86_sse2_comige_sd: 8598 Opc = X86ISD::COMI; 8599 CC = ISD::SETGE; 8600 break; 8601 case Intrinsic::x86_sse_comineq_ss: 8602 case Intrinsic::x86_sse2_comineq_sd: 8603 Opc = X86ISD::COMI; 8604 CC = ISD::SETNE; 8605 break; 8606 case Intrinsic::x86_sse_ucomieq_ss: 8607 case Intrinsic::x86_sse2_ucomieq_sd: 8608 Opc = X86ISD::UCOMI; 8609 CC = ISD::SETEQ; 8610 break; 8611 case Intrinsic::x86_sse_ucomilt_ss: 8612 case Intrinsic::x86_sse2_ucomilt_sd: 8613 Opc = X86ISD::UCOMI; 8614 CC = ISD::SETLT; 8615 break; 8616 case Intrinsic::x86_sse_ucomile_ss: 8617 case Intrinsic::x86_sse2_ucomile_sd: 8618 Opc = X86ISD::UCOMI; 8619 CC = ISD::SETLE; 8620 break; 8621 case Intrinsic::x86_sse_ucomigt_ss: 8622 case Intrinsic::x86_sse2_ucomigt_sd: 8623 Opc = X86ISD::UCOMI; 8624 CC = ISD::SETGT; 8625 break; 8626 case Intrinsic::x86_sse_ucomige_ss: 8627 case Intrinsic::x86_sse2_ucomige_sd: 8628 Opc = X86ISD::UCOMI; 8629 CC = ISD::SETGE; 8630 break; 8631 case Intrinsic::x86_sse_ucomineq_ss: 8632 case Intrinsic::x86_sse2_ucomineq_sd: 8633 Opc = X86ISD::UCOMI; 8634 CC = ISD::SETNE; 8635 break; 8636 } 8637 8638 SDValue LHS = Op.getOperand(1); 8639 SDValue RHS = Op.getOperand(2); 8640 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 8641 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 8642 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 8643 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8644 DAG.getConstant(X86CC, MVT::i8), Cond); 8645 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8646 } 8647 // ptest and testp intrinsics. The intrinsic these come from are designed to 8648 // return an integer value, not just an instruction so lower it to the ptest 8649 // or testp pattern and a setcc for the result. 8650 case Intrinsic::x86_sse41_ptestz: 8651 case Intrinsic::x86_sse41_ptestc: 8652 case Intrinsic::x86_sse41_ptestnzc: 8653 case Intrinsic::x86_avx_ptestz_256: 8654 case Intrinsic::x86_avx_ptestc_256: 8655 case Intrinsic::x86_avx_ptestnzc_256: 8656 case Intrinsic::x86_avx_vtestz_ps: 8657 case Intrinsic::x86_avx_vtestc_ps: 8658 case Intrinsic::x86_avx_vtestnzc_ps: 8659 case Intrinsic::x86_avx_vtestz_pd: 8660 case Intrinsic::x86_avx_vtestc_pd: 8661 case Intrinsic::x86_avx_vtestnzc_pd: 8662 case Intrinsic::x86_avx_vtestz_ps_256: 8663 case Intrinsic::x86_avx_vtestc_ps_256: 8664 case Intrinsic::x86_avx_vtestnzc_ps_256: 8665 case Intrinsic::x86_avx_vtestz_pd_256: 8666 case Intrinsic::x86_avx_vtestc_pd_256: 8667 case Intrinsic::x86_avx_vtestnzc_pd_256: { 8668 bool IsTestPacked = false; 8669 unsigned X86CC = 0; 8670 switch (IntNo) { 8671 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 8672 case Intrinsic::x86_avx_vtestz_ps: 8673 case Intrinsic::x86_avx_vtestz_pd: 8674 case Intrinsic::x86_avx_vtestz_ps_256: 8675 case Intrinsic::x86_avx_vtestz_pd_256: 8676 IsTestPacked = true; // Fallthrough 8677 case Intrinsic::x86_sse41_ptestz: 8678 case Intrinsic::x86_avx_ptestz_256: 8679 // ZF = 1 8680 X86CC = X86::COND_E; 8681 break; 8682 case Intrinsic::x86_avx_vtestc_ps: 8683 case Intrinsic::x86_avx_vtestc_pd: 8684 case Intrinsic::x86_avx_vtestc_ps_256: 8685 case Intrinsic::x86_avx_vtestc_pd_256: 8686 IsTestPacked = true; // Fallthrough 8687 case Intrinsic::x86_sse41_ptestc: 8688 case Intrinsic::x86_avx_ptestc_256: 8689 // CF = 1 8690 X86CC = X86::COND_B; 8691 break; 8692 case Intrinsic::x86_avx_vtestnzc_ps: 8693 case Intrinsic::x86_avx_vtestnzc_pd: 8694 case Intrinsic::x86_avx_vtestnzc_ps_256: 8695 case Intrinsic::x86_avx_vtestnzc_pd_256: 8696 IsTestPacked = true; // Fallthrough 8697 case Intrinsic::x86_sse41_ptestnzc: 8698 case Intrinsic::x86_avx_ptestnzc_256: 8699 // ZF and CF = 0 8700 X86CC = X86::COND_A; 8701 break; 8702 } 8703 8704 SDValue LHS = Op.getOperand(1); 8705 SDValue RHS = Op.getOperand(2); 8706 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 8707 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 8708 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 8709 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 8710 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8711 } 8712 8713 // Fix vector shift instructions where the last operand is a non-immediate 8714 // i32 value. 8715 case Intrinsic::x86_sse2_pslli_w: 8716 case Intrinsic::x86_sse2_pslli_d: 8717 case Intrinsic::x86_sse2_pslli_q: 8718 case Intrinsic::x86_sse2_psrli_w: 8719 case Intrinsic::x86_sse2_psrli_d: 8720 case Intrinsic::x86_sse2_psrli_q: 8721 case Intrinsic::x86_sse2_psrai_w: 8722 case Intrinsic::x86_sse2_psrai_d: 8723 case Intrinsic::x86_mmx_pslli_w: 8724 case Intrinsic::x86_mmx_pslli_d: 8725 case Intrinsic::x86_mmx_pslli_q: 8726 case Intrinsic::x86_mmx_psrli_w: 8727 case Intrinsic::x86_mmx_psrli_d: 8728 case Intrinsic::x86_mmx_psrli_q: 8729 case Intrinsic::x86_mmx_psrai_w: 8730 case Intrinsic::x86_mmx_psrai_d: { 8731 SDValue ShAmt = Op.getOperand(2); 8732 if (isa<ConstantSDNode>(ShAmt)) 8733 return SDValue(); 8734 8735 unsigned NewIntNo = 0; 8736 EVT ShAmtVT = MVT::v4i32; 8737 switch (IntNo) { 8738 case Intrinsic::x86_sse2_pslli_w: 8739 NewIntNo = Intrinsic::x86_sse2_psll_w; 8740 break; 8741 case Intrinsic::x86_sse2_pslli_d: 8742 NewIntNo = Intrinsic::x86_sse2_psll_d; 8743 break; 8744 case Intrinsic::x86_sse2_pslli_q: 8745 NewIntNo = Intrinsic::x86_sse2_psll_q; 8746 break; 8747 case Intrinsic::x86_sse2_psrli_w: 8748 NewIntNo = Intrinsic::x86_sse2_psrl_w; 8749 break; 8750 case Intrinsic::x86_sse2_psrli_d: 8751 NewIntNo = Intrinsic::x86_sse2_psrl_d; 8752 break; 8753 case Intrinsic::x86_sse2_psrli_q: 8754 NewIntNo = Intrinsic::x86_sse2_psrl_q; 8755 break; 8756 case Intrinsic::x86_sse2_psrai_w: 8757 NewIntNo = Intrinsic::x86_sse2_psra_w; 8758 break; 8759 case Intrinsic::x86_sse2_psrai_d: 8760 NewIntNo = Intrinsic::x86_sse2_psra_d; 8761 break; 8762 default: { 8763 ShAmtVT = MVT::v2i32; 8764 switch (IntNo) { 8765 case Intrinsic::x86_mmx_pslli_w: 8766 NewIntNo = Intrinsic::x86_mmx_psll_w; 8767 break; 8768 case Intrinsic::x86_mmx_pslli_d: 8769 NewIntNo = Intrinsic::x86_mmx_psll_d; 8770 break; 8771 case Intrinsic::x86_mmx_pslli_q: 8772 NewIntNo = Intrinsic::x86_mmx_psll_q; 8773 break; 8774 case Intrinsic::x86_mmx_psrli_w: 8775 NewIntNo = Intrinsic::x86_mmx_psrl_w; 8776 break; 8777 case Intrinsic::x86_mmx_psrli_d: 8778 NewIntNo = Intrinsic::x86_mmx_psrl_d; 8779 break; 8780 case Intrinsic::x86_mmx_psrli_q: 8781 NewIntNo = Intrinsic::x86_mmx_psrl_q; 8782 break; 8783 case Intrinsic::x86_mmx_psrai_w: 8784 NewIntNo = Intrinsic::x86_mmx_psra_w; 8785 break; 8786 case Intrinsic::x86_mmx_psrai_d: 8787 NewIntNo = Intrinsic::x86_mmx_psra_d; 8788 break; 8789 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 8790 } 8791 break; 8792 } 8793 } 8794 8795 // The vector shift intrinsics with scalars uses 32b shift amounts but 8796 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 8797 // to be zero. 8798 SDValue ShOps[4]; 8799 ShOps[0] = ShAmt; 8800 ShOps[1] = DAG.getConstant(0, MVT::i32); 8801 if (ShAmtVT == MVT::v4i32) { 8802 ShOps[2] = DAG.getUNDEF(MVT::i32); 8803 ShOps[3] = DAG.getUNDEF(MVT::i32); 8804 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 8805 } else { 8806 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 8807// FIXME this must be lowered to get rid of the invalid type. 8808 } 8809 8810 EVT VT = Op.getValueType(); 8811 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 8812 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8813 DAG.getConstant(NewIntNo, MVT::i32), 8814 Op.getOperand(1), ShAmt); 8815 } 8816 } 8817} 8818 8819SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 8820 SelectionDAG &DAG) const { 8821 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8822 MFI->setReturnAddressIsTaken(true); 8823 8824 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8825 DebugLoc dl = Op.getDebugLoc(); 8826 8827 if (Depth > 0) { 8828 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 8829 SDValue Offset = 8830 DAG.getConstant(TD->getPointerSize(), 8831 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8832 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8833 DAG.getNode(ISD::ADD, dl, getPointerTy(), 8834 FrameAddr, Offset), 8835 MachinePointerInfo(), false, false, 0); 8836 } 8837 8838 // Just load the return address. 8839 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 8840 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8841 RetAddrFI, MachinePointerInfo(), false, false, 0); 8842} 8843 8844SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 8845 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8846 MFI->setFrameAddressIsTaken(true); 8847 8848 EVT VT = Op.getValueType(); 8849 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 8850 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8851 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 8852 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 8853 while (Depth--) 8854 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 8855 MachinePointerInfo(), 8856 false, false, 0); 8857 return FrameAddr; 8858} 8859 8860SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 8861 SelectionDAG &DAG) const { 8862 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 8863} 8864 8865SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 8866 MachineFunction &MF = DAG.getMachineFunction(); 8867 SDValue Chain = Op.getOperand(0); 8868 SDValue Offset = Op.getOperand(1); 8869 SDValue Handler = Op.getOperand(2); 8870 DebugLoc dl = Op.getDebugLoc(); 8871 8872 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 8873 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 8874 getPointerTy()); 8875 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 8876 8877 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 8878 DAG.getIntPtrConstant(TD->getPointerSize())); 8879 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 8880 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 8881 false, false, 0); 8882 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 8883 MF.getRegInfo().addLiveOut(StoreAddrReg); 8884 8885 return DAG.getNode(X86ISD::EH_RETURN, dl, 8886 MVT::Other, 8887 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 8888} 8889 8890SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 8891 SelectionDAG &DAG) const { 8892 SDValue Root = Op.getOperand(0); 8893 SDValue Trmp = Op.getOperand(1); // trampoline 8894 SDValue FPtr = Op.getOperand(2); // nested function 8895 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 8896 DebugLoc dl = Op.getDebugLoc(); 8897 8898 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8899 8900 if (Subtarget->is64Bit()) { 8901 SDValue OutChains[6]; 8902 8903 // Large code-model. 8904 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 8905 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 8906 8907 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 8908 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 8909 8910 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 8911 8912 // Load the pointer to the nested function into R11. 8913 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 8914 SDValue Addr = Trmp; 8915 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8916 Addr, MachinePointerInfo(TrmpAddr), 8917 false, false, 0); 8918 8919 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8920 DAG.getConstant(2, MVT::i64)); 8921 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 8922 MachinePointerInfo(TrmpAddr, 2), 8923 false, false, 2); 8924 8925 // Load the 'nest' parameter value into R10. 8926 // R10 is specified in X86CallingConv.td 8927 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 8928 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8929 DAG.getConstant(10, MVT::i64)); 8930 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8931 Addr, MachinePointerInfo(TrmpAddr, 10), 8932 false, false, 0); 8933 8934 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8935 DAG.getConstant(12, MVT::i64)); 8936 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 8937 MachinePointerInfo(TrmpAddr, 12), 8938 false, false, 2); 8939 8940 // Jump to the nested function. 8941 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 8942 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8943 DAG.getConstant(20, MVT::i64)); 8944 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8945 Addr, MachinePointerInfo(TrmpAddr, 20), 8946 false, false, 0); 8947 8948 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 8949 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8950 DAG.getConstant(22, MVT::i64)); 8951 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 8952 MachinePointerInfo(TrmpAddr, 22), 8953 false, false, 0); 8954 8955 SDValue Ops[] = 8956 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 8957 return DAG.getMergeValues(Ops, 2, dl); 8958 } else { 8959 const Function *Func = 8960 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 8961 CallingConv::ID CC = Func->getCallingConv(); 8962 unsigned NestReg; 8963 8964 switch (CC) { 8965 default: 8966 llvm_unreachable("Unsupported calling convention"); 8967 case CallingConv::C: 8968 case CallingConv::X86_StdCall: { 8969 // Pass 'nest' parameter in ECX. 8970 // Must be kept in sync with X86CallingConv.td 8971 NestReg = X86::ECX; 8972 8973 // Check that ECX wasn't needed by an 'inreg' parameter. 8974 FunctionType *FTy = Func->getFunctionType(); 8975 const AttrListPtr &Attrs = Func->getAttributes(); 8976 8977 if (!Attrs.isEmpty() && !Func->isVarArg()) { 8978 unsigned InRegCount = 0; 8979 unsigned Idx = 1; 8980 8981 for (FunctionType::param_iterator I = FTy->param_begin(), 8982 E = FTy->param_end(); I != E; ++I, ++Idx) 8983 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 8984 // FIXME: should only count parameters that are lowered to integers. 8985 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 8986 8987 if (InRegCount > 2) { 8988 report_fatal_error("Nest register in use - reduce number of inreg" 8989 " parameters!"); 8990 } 8991 } 8992 break; 8993 } 8994 case CallingConv::X86_FastCall: 8995 case CallingConv::X86_ThisCall: 8996 case CallingConv::Fast: 8997 // Pass 'nest' parameter in EAX. 8998 // Must be kept in sync with X86CallingConv.td 8999 NestReg = X86::EAX; 9000 break; 9001 } 9002 9003 SDValue OutChains[4]; 9004 SDValue Addr, Disp; 9005 9006 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9007 DAG.getConstant(10, MVT::i32)); 9008 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9009 9010 // This is storing the opcode for MOV32ri. 9011 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9012 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9013 OutChains[0] = DAG.getStore(Root, dl, 9014 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9015 Trmp, MachinePointerInfo(TrmpAddr), 9016 false, false, 0); 9017 9018 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9019 DAG.getConstant(1, MVT::i32)); 9020 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9021 MachinePointerInfo(TrmpAddr, 1), 9022 false, false, 1); 9023 9024 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9025 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9026 DAG.getConstant(5, MVT::i32)); 9027 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9028 MachinePointerInfo(TrmpAddr, 5), 9029 false, false, 1); 9030 9031 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9032 DAG.getConstant(6, MVT::i32)); 9033 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9034 MachinePointerInfo(TrmpAddr, 6), 9035 false, false, 1); 9036 9037 SDValue Ops[] = 9038 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 9039 return DAG.getMergeValues(Ops, 2, dl); 9040 } 9041} 9042 9043SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9044 SelectionDAG &DAG) const { 9045 /* 9046 The rounding mode is in bits 11:10 of FPSR, and has the following 9047 settings: 9048 00 Round to nearest 9049 01 Round to -inf 9050 10 Round to +inf 9051 11 Round to 0 9052 9053 FLT_ROUNDS, on the other hand, expects the following: 9054 -1 Undefined 9055 0 Round to 0 9056 1 Round to nearest 9057 2 Round to +inf 9058 3 Round to -inf 9059 9060 To perform the conversion, we do: 9061 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9062 */ 9063 9064 MachineFunction &MF = DAG.getMachineFunction(); 9065 const TargetMachine &TM = MF.getTarget(); 9066 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9067 unsigned StackAlignment = TFI.getStackAlignment(); 9068 EVT VT = Op.getValueType(); 9069 DebugLoc DL = Op.getDebugLoc(); 9070 9071 // Save FP Control Word to stack slot 9072 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9073 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9074 9075 9076 MachineMemOperand *MMO = 9077 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9078 MachineMemOperand::MOStore, 2, 2); 9079 9080 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9081 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9082 DAG.getVTList(MVT::Other), 9083 Ops, 2, MVT::i16, MMO); 9084 9085 // Load FP Control Word from stack slot 9086 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9087 MachinePointerInfo(), false, false, 0); 9088 9089 // Transform as necessary 9090 SDValue CWD1 = 9091 DAG.getNode(ISD::SRL, DL, MVT::i16, 9092 DAG.getNode(ISD::AND, DL, MVT::i16, 9093 CWD, DAG.getConstant(0x800, MVT::i16)), 9094 DAG.getConstant(11, MVT::i8)); 9095 SDValue CWD2 = 9096 DAG.getNode(ISD::SRL, DL, MVT::i16, 9097 DAG.getNode(ISD::AND, DL, MVT::i16, 9098 CWD, DAG.getConstant(0x400, MVT::i16)), 9099 DAG.getConstant(9, MVT::i8)); 9100 9101 SDValue RetVal = 9102 DAG.getNode(ISD::AND, DL, MVT::i16, 9103 DAG.getNode(ISD::ADD, DL, MVT::i16, 9104 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9105 DAG.getConstant(1, MVT::i16)), 9106 DAG.getConstant(3, MVT::i16)); 9107 9108 9109 return DAG.getNode((VT.getSizeInBits() < 16 ? 9110 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9111} 9112 9113SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9114 EVT VT = Op.getValueType(); 9115 EVT OpVT = VT; 9116 unsigned NumBits = VT.getSizeInBits(); 9117 DebugLoc dl = Op.getDebugLoc(); 9118 9119 Op = Op.getOperand(0); 9120 if (VT == MVT::i8) { 9121 // Zero extend to i32 since there is not an i8 bsr. 9122 OpVT = MVT::i32; 9123 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9124 } 9125 9126 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9127 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9128 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9129 9130 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9131 SDValue Ops[] = { 9132 Op, 9133 DAG.getConstant(NumBits+NumBits-1, OpVT), 9134 DAG.getConstant(X86::COND_E, MVT::i8), 9135 Op.getValue(1) 9136 }; 9137 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9138 9139 // Finally xor with NumBits-1. 9140 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9141 9142 if (VT == MVT::i8) 9143 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9144 return Op; 9145} 9146 9147SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9148 EVT VT = Op.getValueType(); 9149 EVT OpVT = VT; 9150 unsigned NumBits = VT.getSizeInBits(); 9151 DebugLoc dl = Op.getDebugLoc(); 9152 9153 Op = Op.getOperand(0); 9154 if (VT == MVT::i8) { 9155 OpVT = MVT::i32; 9156 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9157 } 9158 9159 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9160 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9161 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9162 9163 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9164 SDValue Ops[] = { 9165 Op, 9166 DAG.getConstant(NumBits, OpVT), 9167 DAG.getConstant(X86::COND_E, MVT::i8), 9168 Op.getValue(1) 9169 }; 9170 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9171 9172 if (VT == MVT::i8) 9173 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9174 return Op; 9175} 9176 9177SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 9178 EVT VT = Op.getValueType(); 9179 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9180 DebugLoc dl = Op.getDebugLoc(); 9181 9182 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9183 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9184 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9185 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9186 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9187 // 9188 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9189 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9190 // return AloBlo + AloBhi + AhiBlo; 9191 9192 SDValue A = Op.getOperand(0); 9193 SDValue B = Op.getOperand(1); 9194 9195 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9196 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9197 A, DAG.getConstant(32, MVT::i32)); 9198 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9199 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9200 B, DAG.getConstant(32, MVT::i32)); 9201 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9202 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9203 A, B); 9204 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9205 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9206 A, Bhi); 9207 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9208 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9209 Ahi, B); 9210 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9211 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9212 AloBhi, DAG.getConstant(32, MVT::i32)); 9213 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9214 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9215 AhiBlo, DAG.getConstant(32, MVT::i32)); 9216 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9217 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9218 return Res; 9219} 9220 9221SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 9222 9223 EVT VT = Op.getValueType(); 9224 DebugLoc dl = Op.getDebugLoc(); 9225 SDValue R = Op.getOperand(0); 9226 SDValue Amt = Op.getOperand(1); 9227 LLVMContext *Context = DAG.getContext(); 9228 9229 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 9230 return SDValue(); 9231 9232 // Decompose 256-bit shifts into smaller 128-bit shifts. 9233 if (VT.getSizeInBits() == 256) { 9234 int NumElems = VT.getVectorNumElements(); 9235 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9236 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9237 9238 // Extract the two vectors 9239 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 9240 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 9241 DAG, dl); 9242 9243 // Recreate the shift amount vectors 9244 SmallVector<SDValue, 4> Amt1Csts; 9245 SmallVector<SDValue, 4> Amt2Csts; 9246 for (int i = 0; i < NumElems/2; ++i) 9247 Amt1Csts.push_back(Amt->getOperand(i)); 9248 for (int i = NumElems/2; i < NumElems; ++i) 9249 Amt2Csts.push_back(Amt->getOperand(i)); 9250 9251 SDValue Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9252 &Amt1Csts[0], NumElems/2); 9253 SDValue Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9254 &Amt2Csts[0], NumElems/2); 9255 9256 // Issue new vector shifts for the smaller types 9257 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 9258 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 9259 9260 // Concatenate the result back 9261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 9262 } 9263 9264 // Optimize shl/srl/sra with constant shift amount. 9265 if (isSplatVector(Amt.getNode())) { 9266 SDValue SclrAmt = Amt->getOperand(0); 9267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 9268 uint64_t ShiftAmt = C->getZExtValue(); 9269 9270 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 9271 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9272 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9273 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9274 9275 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 9276 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9277 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9278 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9279 9280 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 9281 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9282 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9283 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9284 9285 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 9286 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9287 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9288 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9289 9290 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 9291 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9292 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9293 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9294 9295 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 9296 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9297 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9298 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9299 9300 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 9301 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9302 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9303 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9304 9305 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 9306 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9307 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9308 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9309 } 9310 } 9311 9312 // Lower SHL with variable shift amount. 9313 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 9314 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9315 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9316 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 9317 9318 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 9319 9320 std::vector<Constant*> CV(4, CI); 9321 Constant *C = ConstantVector::get(CV); 9322 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9323 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9324 MachinePointerInfo::getConstantPool(), 9325 false, false, 16); 9326 9327 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 9328 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 9329 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 9330 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 9331 } 9332 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 9333 // a = a << 5; 9334 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9335 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9336 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 9337 9338 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 9339 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 9340 9341 std::vector<Constant*> CVM1(16, CM1); 9342 std::vector<Constant*> CVM2(16, CM2); 9343 Constant *C = ConstantVector::get(CVM1); 9344 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9345 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9346 MachinePointerInfo::getConstantPool(), 9347 false, false, 16); 9348 9349 // r = pblendv(r, psllw(r & (char16)15, 4), a); 9350 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9351 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9352 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9353 DAG.getConstant(4, MVT::i32)); 9354 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9355 // a += a 9356 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9357 9358 C = ConstantVector::get(CVM2); 9359 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9360 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9361 MachinePointerInfo::getConstantPool(), 9362 false, false, 16); 9363 9364 // r = pblendv(r, psllw(r & (char16)63, 2), a); 9365 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9366 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9367 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9368 DAG.getConstant(2, MVT::i32)); 9369 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9370 // a += a 9371 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9372 9373 // return pblendv(r, r+r, a); 9374 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, 9375 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 9376 return R; 9377 } 9378 return SDValue(); 9379} 9380 9381SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 9382 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 9383 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 9384 // looks for this combo and may remove the "setcc" instruction if the "setcc" 9385 // has only one use. 9386 SDNode *N = Op.getNode(); 9387 SDValue LHS = N->getOperand(0); 9388 SDValue RHS = N->getOperand(1); 9389 unsigned BaseOp = 0; 9390 unsigned Cond = 0; 9391 DebugLoc DL = Op.getDebugLoc(); 9392 switch (Op.getOpcode()) { 9393 default: llvm_unreachable("Unknown ovf instruction!"); 9394 case ISD::SADDO: 9395 // A subtract of one will be selected as a INC. Note that INC doesn't 9396 // set CF, so we can't do this for UADDO. 9397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9398 if (C->isOne()) { 9399 BaseOp = X86ISD::INC; 9400 Cond = X86::COND_O; 9401 break; 9402 } 9403 BaseOp = X86ISD::ADD; 9404 Cond = X86::COND_O; 9405 break; 9406 case ISD::UADDO: 9407 BaseOp = X86ISD::ADD; 9408 Cond = X86::COND_B; 9409 break; 9410 case ISD::SSUBO: 9411 // A subtract of one will be selected as a DEC. Note that DEC doesn't 9412 // set CF, so we can't do this for USUBO. 9413 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9414 if (C->isOne()) { 9415 BaseOp = X86ISD::DEC; 9416 Cond = X86::COND_O; 9417 break; 9418 } 9419 BaseOp = X86ISD::SUB; 9420 Cond = X86::COND_O; 9421 break; 9422 case ISD::USUBO: 9423 BaseOp = X86ISD::SUB; 9424 Cond = X86::COND_B; 9425 break; 9426 case ISD::SMULO: 9427 BaseOp = X86ISD::SMUL; 9428 Cond = X86::COND_O; 9429 break; 9430 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 9431 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 9432 MVT::i32); 9433 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 9434 9435 SDValue SetCC = 9436 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9437 DAG.getConstant(X86::COND_O, MVT::i32), 9438 SDValue(Sum.getNode(), 2)); 9439 9440 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 9441 } 9442 } 9443 9444 // Also sets EFLAGS. 9445 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 9446 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 9447 9448 SDValue SetCC = 9449 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 9450 DAG.getConstant(Cond, MVT::i32), 9451 SDValue(Sum.getNode(), 1)); 9452 9453 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 9454} 9455 9456SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 9457 DebugLoc dl = Op.getDebugLoc(); 9458 SDNode* Node = Op.getNode(); 9459 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 9460 EVT VT = Node->getValueType(0); 9461 9462 if (Subtarget->hasSSE2() && VT.isVector()) { 9463 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 9464 ExtraVT.getScalarType().getSizeInBits(); 9465 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 9466 9467 unsigned SHLIntrinsicsID = 0; 9468 unsigned SRAIntrinsicsID = 0; 9469 switch (VT.getSimpleVT().SimpleTy) { 9470 default: 9471 return SDValue(); 9472 case MVT::v2i64: { 9473 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q; 9474 SRAIntrinsicsID = 0; 9475 break; 9476 } 9477 case MVT::v4i32: { 9478 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 9479 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 9480 break; 9481 } 9482 case MVT::v8i16: { 9483 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 9484 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 9485 break; 9486 } 9487 } 9488 9489 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9490 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 9491 Node->getOperand(0), ShAmt); 9492 9493 // In case of 1 bit sext, no need to shr 9494 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; 9495 9496 if (SRAIntrinsicsID) { 9497 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9498 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 9499 Tmp1, ShAmt); 9500 } 9501 return Tmp1; 9502 } 9503 9504 return SDValue(); 9505} 9506 9507 9508SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 9509 DebugLoc dl = Op.getDebugLoc(); 9510 9511 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 9512 // There isn't any reason to disable it if the target processor supports it. 9513 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 9514 SDValue Chain = Op.getOperand(0); 9515 SDValue Zero = DAG.getConstant(0, MVT::i32); 9516 SDValue Ops[] = { 9517 DAG.getRegister(X86::ESP, MVT::i32), // Base 9518 DAG.getTargetConstant(1, MVT::i8), // Scale 9519 DAG.getRegister(0, MVT::i32), // Index 9520 DAG.getTargetConstant(0, MVT::i32), // Disp 9521 DAG.getRegister(0, MVT::i32), // Segment. 9522 Zero, 9523 Chain 9524 }; 9525 SDNode *Res = 9526 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 9527 array_lengthof(Ops)); 9528 return SDValue(Res, 0); 9529 } 9530 9531 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 9532 if (!isDev) 9533 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 9534 9535 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 9536 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 9537 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 9538 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 9539 9540 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 9541 if (!Op1 && !Op2 && !Op3 && Op4) 9542 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 9543 9544 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 9545 if (Op1 && !Op2 && !Op3 && !Op4) 9546 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 9547 9548 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 9549 // (MFENCE)>; 9550 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 9551} 9552 9553SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 9554 SelectionDAG &DAG) const { 9555 DebugLoc dl = Op.getDebugLoc(); 9556 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 9557 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 9558 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 9559 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 9560 9561 // The only fence that needs an instruction is a sequentially-consistent 9562 // cross-thread fence. 9563 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 9564 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 9565 // no-sse2). There isn't any reason to disable it if the target processor 9566 // supports it. 9567 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 9568 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 9569 9570 SDValue Chain = Op.getOperand(0); 9571 SDValue Zero = DAG.getConstant(0, MVT::i32); 9572 SDValue Ops[] = { 9573 DAG.getRegister(X86::ESP, MVT::i32), // Base 9574 DAG.getTargetConstant(1, MVT::i8), // Scale 9575 DAG.getRegister(0, MVT::i32), // Index 9576 DAG.getTargetConstant(0, MVT::i32), // Disp 9577 DAG.getRegister(0, MVT::i32), // Segment. 9578 Zero, 9579 Chain 9580 }; 9581 SDNode *Res = 9582 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 9583 array_lengthof(Ops)); 9584 return SDValue(Res, 0); 9585 } 9586 9587 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 9588 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 9589} 9590 9591 9592SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 9593 EVT T = Op.getValueType(); 9594 DebugLoc DL = Op.getDebugLoc(); 9595 unsigned Reg = 0; 9596 unsigned size = 0; 9597 switch(T.getSimpleVT().SimpleTy) { 9598 default: 9599 assert(false && "Invalid value type!"); 9600 case MVT::i8: Reg = X86::AL; size = 1; break; 9601 case MVT::i16: Reg = X86::AX; size = 2; break; 9602 case MVT::i32: Reg = X86::EAX; size = 4; break; 9603 case MVT::i64: 9604 assert(Subtarget->is64Bit() && "Node not type legal!"); 9605 Reg = X86::RAX; size = 8; 9606 break; 9607 } 9608 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 9609 Op.getOperand(2), SDValue()); 9610 SDValue Ops[] = { cpIn.getValue(0), 9611 Op.getOperand(1), 9612 Op.getOperand(3), 9613 DAG.getTargetConstant(size, MVT::i8), 9614 cpIn.getValue(1) }; 9615 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9616 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 9617 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 9618 Ops, 5, T, MMO); 9619 SDValue cpOut = 9620 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 9621 return cpOut; 9622} 9623 9624SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 9625 SelectionDAG &DAG) const { 9626 assert(Subtarget->is64Bit() && "Result not type legalized?"); 9627 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9628 SDValue TheChain = Op.getOperand(0); 9629 DebugLoc dl = Op.getDebugLoc(); 9630 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9631 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 9632 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 9633 rax.getValue(2)); 9634 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 9635 DAG.getConstant(32, MVT::i8)); 9636 SDValue Ops[] = { 9637 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 9638 rdx.getValue(1) 9639 }; 9640 return DAG.getMergeValues(Ops, 2, dl); 9641} 9642 9643SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 9644 SelectionDAG &DAG) const { 9645 EVT SrcVT = Op.getOperand(0).getValueType(); 9646 EVT DstVT = Op.getValueType(); 9647 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 9648 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 9649 assert((DstVT == MVT::i64 || 9650 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 9651 "Unexpected custom BITCAST"); 9652 // i64 <=> MMX conversions are Legal. 9653 if (SrcVT==MVT::i64 && DstVT.isVector()) 9654 return Op; 9655 if (DstVT==MVT::i64 && SrcVT.isVector()) 9656 return Op; 9657 // MMX <=> MMX conversions are Legal. 9658 if (SrcVT.isVector() && DstVT.isVector()) 9659 return Op; 9660 // All other conversions need to be expanded. 9661 return SDValue(); 9662} 9663 9664SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 9665 SDNode *Node = Op.getNode(); 9666 DebugLoc dl = Node->getDebugLoc(); 9667 EVT T = Node->getValueType(0); 9668 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 9669 DAG.getConstant(0, T), Node->getOperand(2)); 9670 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 9671 cast<AtomicSDNode>(Node)->getMemoryVT(), 9672 Node->getOperand(0), 9673 Node->getOperand(1), negOp, 9674 cast<AtomicSDNode>(Node)->getSrcValue(), 9675 cast<AtomicSDNode>(Node)->getAlignment(), 9676 cast<AtomicSDNode>(Node)->getOrdering(), 9677 cast<AtomicSDNode>(Node)->getSynchScope()); 9678} 9679 9680static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 9681 EVT VT = Op.getNode()->getValueType(0); 9682 9683 // Let legalize expand this if it isn't a legal type yet. 9684 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 9685 return SDValue(); 9686 9687 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9688 9689 unsigned Opc; 9690 bool ExtraOp = false; 9691 switch (Op.getOpcode()) { 9692 default: assert(0 && "Invalid code"); 9693 case ISD::ADDC: Opc = X86ISD::ADD; break; 9694 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 9695 case ISD::SUBC: Opc = X86ISD::SUB; break; 9696 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 9697 } 9698 9699 if (!ExtraOp) 9700 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9701 Op.getOperand(1)); 9702 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9703 Op.getOperand(1), Op.getOperand(2)); 9704} 9705 9706/// LowerOperation - Provide custom lowering hooks for some operations. 9707/// 9708SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 9709 switch (Op.getOpcode()) { 9710 default: llvm_unreachable("Should not custom lower this!"); 9711 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 9712 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 9713 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 9714 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 9715 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 9716 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 9717 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 9718 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 9719 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 9720 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 9721 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 9722 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 9723 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 9724 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 9725 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 9726 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 9727 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 9728 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 9729 case ISD::SHL_PARTS: 9730 case ISD::SRA_PARTS: 9731 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 9732 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 9733 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 9734 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 9735 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 9736 case ISD::FABS: return LowerFABS(Op, DAG); 9737 case ISD::FNEG: return LowerFNEG(Op, DAG); 9738 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 9739 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 9740 case ISD::SETCC: return LowerSETCC(Op, DAG); 9741 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 9742 case ISD::SELECT: return LowerSELECT(Op, DAG); 9743 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 9744 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 9745 case ISD::VASTART: return LowerVASTART(Op, DAG); 9746 case ISD::VAARG: return LowerVAARG(Op, DAG); 9747 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 9748 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 9749 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 9750 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 9751 case ISD::FRAME_TO_ARGS_OFFSET: 9752 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 9753 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 9754 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 9755 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 9756 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 9757 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 9758 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 9759 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 9760 case ISD::SRA: 9761 case ISD::SRL: 9762 case ISD::SHL: return LowerShift(Op, DAG); 9763 case ISD::SADDO: 9764 case ISD::UADDO: 9765 case ISD::SSUBO: 9766 case ISD::USUBO: 9767 case ISD::SMULO: 9768 case ISD::UMULO: return LowerXALUO(Op, DAG); 9769 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 9770 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 9771 case ISD::ADDC: 9772 case ISD::ADDE: 9773 case ISD::SUBC: 9774 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 9775 } 9776} 9777 9778void X86TargetLowering:: 9779ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 9780 SelectionDAG &DAG, unsigned NewOp) const { 9781 EVT T = Node->getValueType(0); 9782 DebugLoc dl = Node->getDebugLoc(); 9783 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 9784 9785 SDValue Chain = Node->getOperand(0); 9786 SDValue In1 = Node->getOperand(1); 9787 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9788 Node->getOperand(2), DAG.getIntPtrConstant(0)); 9789 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9790 Node->getOperand(2), DAG.getIntPtrConstant(1)); 9791 SDValue Ops[] = { Chain, In1, In2L, In2H }; 9792 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 9793 SDValue Result = 9794 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 9795 cast<MemSDNode>(Node)->getMemOperand()); 9796 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 9797 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9798 Results.push_back(Result.getValue(2)); 9799} 9800 9801/// ReplaceNodeResults - Replace a node with an illegal result type 9802/// with a new node built out of custom code. 9803void X86TargetLowering::ReplaceNodeResults(SDNode *N, 9804 SmallVectorImpl<SDValue>&Results, 9805 SelectionDAG &DAG) const { 9806 DebugLoc dl = N->getDebugLoc(); 9807 switch (N->getOpcode()) { 9808 default: 9809 assert(false && "Do not know how to custom type legalize this operation!"); 9810 return; 9811 case ISD::SIGN_EXTEND_INREG: 9812 case ISD::ADDC: 9813 case ISD::ADDE: 9814 case ISD::SUBC: 9815 case ISD::SUBE: 9816 // We don't want to expand or promote these. 9817 return; 9818 case ISD::FP_TO_SINT: { 9819 std::pair<SDValue,SDValue> Vals = 9820 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 9821 SDValue FIST = Vals.first, StackSlot = Vals.second; 9822 if (FIST.getNode() != 0) { 9823 EVT VT = N->getValueType(0); 9824 // Return a load from the stack slot. 9825 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 9826 MachinePointerInfo(), false, false, 0)); 9827 } 9828 return; 9829 } 9830 case ISD::READCYCLECOUNTER: { 9831 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9832 SDValue TheChain = N->getOperand(0); 9833 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9834 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 9835 rd.getValue(1)); 9836 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 9837 eax.getValue(2)); 9838 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 9839 SDValue Ops[] = { eax, edx }; 9840 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 9841 Results.push_back(edx.getValue(1)); 9842 return; 9843 } 9844 case ISD::ATOMIC_CMP_SWAP: { 9845 EVT T = N->getValueType(0); 9846 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 9847 SDValue cpInL, cpInH; 9848 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9849 DAG.getConstant(0, MVT::i32)); 9850 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9851 DAG.getConstant(1, MVT::i32)); 9852 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 9853 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 9854 cpInL.getValue(1)); 9855 SDValue swapInL, swapInH; 9856 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9857 DAG.getConstant(0, MVT::i32)); 9858 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9859 DAG.getConstant(1, MVT::i32)); 9860 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 9861 cpInH.getValue(1)); 9862 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 9863 swapInL.getValue(1)); 9864 SDValue Ops[] = { swapInH.getValue(0), 9865 N->getOperand(1), 9866 swapInH.getValue(1) }; 9867 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9868 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 9869 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, 9870 Ops, 3, T, MMO); 9871 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 9872 MVT::i32, Result.getValue(1)); 9873 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 9874 MVT::i32, cpOutL.getValue(2)); 9875 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 9876 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9877 Results.push_back(cpOutH.getValue(1)); 9878 return; 9879 } 9880 case ISD::ATOMIC_LOAD_ADD: 9881 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 9882 return; 9883 case ISD::ATOMIC_LOAD_AND: 9884 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 9885 return; 9886 case ISD::ATOMIC_LOAD_NAND: 9887 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 9888 return; 9889 case ISD::ATOMIC_LOAD_OR: 9890 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 9891 return; 9892 case ISD::ATOMIC_LOAD_SUB: 9893 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 9894 return; 9895 case ISD::ATOMIC_LOAD_XOR: 9896 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 9897 return; 9898 case ISD::ATOMIC_SWAP: 9899 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 9900 return; 9901 } 9902} 9903 9904const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 9905 switch (Opcode) { 9906 default: return NULL; 9907 case X86ISD::BSF: return "X86ISD::BSF"; 9908 case X86ISD::BSR: return "X86ISD::BSR"; 9909 case X86ISD::SHLD: return "X86ISD::SHLD"; 9910 case X86ISD::SHRD: return "X86ISD::SHRD"; 9911 case X86ISD::FAND: return "X86ISD::FAND"; 9912 case X86ISD::FOR: return "X86ISD::FOR"; 9913 case X86ISD::FXOR: return "X86ISD::FXOR"; 9914 case X86ISD::FSRL: return "X86ISD::FSRL"; 9915 case X86ISD::FILD: return "X86ISD::FILD"; 9916 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 9917 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 9918 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 9919 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 9920 case X86ISD::FLD: return "X86ISD::FLD"; 9921 case X86ISD::FST: return "X86ISD::FST"; 9922 case X86ISD::CALL: return "X86ISD::CALL"; 9923 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 9924 case X86ISD::BT: return "X86ISD::BT"; 9925 case X86ISD::CMP: return "X86ISD::CMP"; 9926 case X86ISD::COMI: return "X86ISD::COMI"; 9927 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 9928 case X86ISD::SETCC: return "X86ISD::SETCC"; 9929 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 9930 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 9931 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 9932 case X86ISD::CMOV: return "X86ISD::CMOV"; 9933 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 9934 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 9935 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 9936 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 9937 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 9938 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 9939 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 9940 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 9941 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 9942 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 9943 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 9944 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 9945 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 9946 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 9947 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 9948 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 9949 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 9950 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB"; 9951 case X86ISD::FMAX: return "X86ISD::FMAX"; 9952 case X86ISD::FMIN: return "X86ISD::FMIN"; 9953 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 9954 case X86ISD::FRCP: return "X86ISD::FRCP"; 9955 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 9956 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 9957 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 9958 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 9959 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 9960 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 9961 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 9962 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 9963 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 9964 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 9965 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 9966 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 9967 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 9968 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 9969 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 9970 case X86ISD::VSHL: return "X86ISD::VSHL"; 9971 case X86ISD::VSRL: return "X86ISD::VSRL"; 9972 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 9973 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 9974 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 9975 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 9976 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 9977 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 9978 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 9979 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 9980 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 9981 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 9982 case X86ISD::ADD: return "X86ISD::ADD"; 9983 case X86ISD::SUB: return "X86ISD::SUB"; 9984 case X86ISD::ADC: return "X86ISD::ADC"; 9985 case X86ISD::SBB: return "X86ISD::SBB"; 9986 case X86ISD::SMUL: return "X86ISD::SMUL"; 9987 case X86ISD::UMUL: return "X86ISD::UMUL"; 9988 case X86ISD::INC: return "X86ISD::INC"; 9989 case X86ISD::DEC: return "X86ISD::DEC"; 9990 case X86ISD::OR: return "X86ISD::OR"; 9991 case X86ISD::XOR: return "X86ISD::XOR"; 9992 case X86ISD::AND: return "X86ISD::AND"; 9993 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 9994 case X86ISD::PTEST: return "X86ISD::PTEST"; 9995 case X86ISD::TESTP: return "X86ISD::TESTP"; 9996 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 9997 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 9998 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 9999 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10000 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10001 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10002 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 10003 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 10004 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10005 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10006 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10007 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 10008 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10009 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10010 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10011 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10012 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10013 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10014 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10015 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10016 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10017 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 10018 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 10019 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 10020 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 10021 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 10022 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 10023 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 10024 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 10025 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 10026 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 10027 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 10028 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 10029 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 10030 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 10031 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 10032 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 10033 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 10034 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10035 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10036 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10037 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10038 } 10039} 10040 10041// isLegalAddressingMode - Return true if the addressing mode represented 10042// by AM is legal for this target, for a load/store of the specified type. 10043bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10044 Type *Ty) const { 10045 // X86 supports extremely general addressing modes. 10046 CodeModel::Model M = getTargetMachine().getCodeModel(); 10047 Reloc::Model R = getTargetMachine().getRelocationModel(); 10048 10049 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10050 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10051 return false; 10052 10053 if (AM.BaseGV) { 10054 unsigned GVFlags = 10055 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 10056 10057 // If a reference to this global requires an extra load, we can't fold it. 10058 if (isGlobalStubReference(GVFlags)) 10059 return false; 10060 10061 // If BaseGV requires a register for the PIC base, we cannot also have a 10062 // BaseReg specified. 10063 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 10064 return false; 10065 10066 // If lower 4G is not available, then we must use rip-relative addressing. 10067 if ((M != CodeModel::Small || R != Reloc::Static) && 10068 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 10069 return false; 10070 } 10071 10072 switch (AM.Scale) { 10073 case 0: 10074 case 1: 10075 case 2: 10076 case 4: 10077 case 8: 10078 // These scales always work. 10079 break; 10080 case 3: 10081 case 5: 10082 case 9: 10083 // These scales are formed with basereg+scalereg. Only accept if there is 10084 // no basereg yet. 10085 if (AM.HasBaseReg) 10086 return false; 10087 break; 10088 default: // Other stuff never works. 10089 return false; 10090 } 10091 10092 return true; 10093} 10094 10095 10096bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 10097 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 10098 return false; 10099 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 10100 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 10101 if (NumBits1 <= NumBits2) 10102 return false; 10103 return true; 10104} 10105 10106bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 10107 if (!VT1.isInteger() || !VT2.isInteger()) 10108 return false; 10109 unsigned NumBits1 = VT1.getSizeInBits(); 10110 unsigned NumBits2 = VT2.getSizeInBits(); 10111 if (NumBits1 <= NumBits2) 10112 return false; 10113 return true; 10114} 10115 10116bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 10117 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10118 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 10119} 10120 10121bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 10122 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10123 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 10124} 10125 10126bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 10127 // i16 instructions are longer (0x66 prefix) and potentially slower. 10128 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 10129} 10130 10131/// isShuffleMaskLegal - Targets can use this to indicate that they only 10132/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 10133/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 10134/// are assumed to be legal. 10135bool 10136X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 10137 EVT VT) const { 10138 // Very little shuffling can be done for 64-bit vectors right now. 10139 if (VT.getSizeInBits() == 64) 10140 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 10141 10142 // FIXME: pshufb, blends, shifts. 10143 return (VT.getVectorNumElements() == 2 || 10144 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 10145 isMOVLMask(M, VT) || 10146 isSHUFPMask(M, VT) || 10147 isPSHUFDMask(M, VT) || 10148 isPSHUFHWMask(M, VT) || 10149 isPSHUFLWMask(M, VT) || 10150 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 10151 isUNPCKLMask(M, VT) || 10152 isUNPCKHMask(M, VT) || 10153 isUNPCKL_v_undef_Mask(M, VT) || 10154 isUNPCKH_v_undef_Mask(M, VT)); 10155} 10156 10157bool 10158X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 10159 EVT VT) const { 10160 unsigned NumElts = VT.getVectorNumElements(); 10161 // FIXME: This collection of masks seems suspect. 10162 if (NumElts == 2) 10163 return true; 10164 if (NumElts == 4 && VT.getSizeInBits() == 128) { 10165 return (isMOVLMask(Mask, VT) || 10166 isCommutedMOVLMask(Mask, VT, true) || 10167 isSHUFPMask(Mask, VT) || 10168 isCommutedSHUFPMask(Mask, VT)); 10169 } 10170 return false; 10171} 10172 10173//===----------------------------------------------------------------------===// 10174// X86 Scheduler Hooks 10175//===----------------------------------------------------------------------===// 10176 10177// private utility function 10178MachineBasicBlock * 10179X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 10180 MachineBasicBlock *MBB, 10181 unsigned regOpc, 10182 unsigned immOpc, 10183 unsigned LoadOpc, 10184 unsigned CXchgOpc, 10185 unsigned notOpc, 10186 unsigned EAXreg, 10187 TargetRegisterClass *RC, 10188 bool invSrc) const { 10189 // For the atomic bitwise operator, we generate 10190 // thisMBB: 10191 // newMBB: 10192 // ld t1 = [bitinstr.addr] 10193 // op t2 = t1, [bitinstr.val] 10194 // mov EAX = t1 10195 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10196 // bz newMBB 10197 // fallthrough -->nextMBB 10198 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10199 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10200 MachineFunction::iterator MBBIter = MBB; 10201 ++MBBIter; 10202 10203 /// First build the CFG 10204 MachineFunction *F = MBB->getParent(); 10205 MachineBasicBlock *thisMBB = MBB; 10206 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10207 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10208 F->insert(MBBIter, newMBB); 10209 F->insert(MBBIter, nextMBB); 10210 10211 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10212 nextMBB->splice(nextMBB->begin(), thisMBB, 10213 llvm::next(MachineBasicBlock::iterator(bInstr)), 10214 thisMBB->end()); 10215 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10216 10217 // Update thisMBB to fall through to newMBB 10218 thisMBB->addSuccessor(newMBB); 10219 10220 // newMBB jumps to itself and fall through to nextMBB 10221 newMBB->addSuccessor(nextMBB); 10222 newMBB->addSuccessor(newMBB); 10223 10224 // Insert instructions into newMBB based on incoming instruction 10225 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10226 "unexpected number of operands"); 10227 DebugLoc dl = bInstr->getDebugLoc(); 10228 MachineOperand& destOper = bInstr->getOperand(0); 10229 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10230 int numArgs = bInstr->getNumOperands() - 1; 10231 for (int i=0; i < numArgs; ++i) 10232 argOpers[i] = &bInstr->getOperand(i+1); 10233 10234 // x86 address has 4 operands: base, index, scale, and displacement 10235 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10236 int valArgIndx = lastAddrIndx + 1; 10237 10238 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10239 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 10240 for (int i=0; i <= lastAddrIndx; ++i) 10241 (*MIB).addOperand(*argOpers[i]); 10242 10243 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 10244 if (invSrc) { 10245 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 10246 } 10247 else 10248 tt = t1; 10249 10250 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10251 assert((argOpers[valArgIndx]->isReg() || 10252 argOpers[valArgIndx]->isImm()) && 10253 "invalid operand"); 10254 if (argOpers[valArgIndx]->isReg()) 10255 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 10256 else 10257 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 10258 MIB.addReg(tt); 10259 (*MIB).addOperand(*argOpers[valArgIndx]); 10260 10261 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 10262 MIB.addReg(t1); 10263 10264 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 10265 for (int i=0; i <= lastAddrIndx; ++i) 10266 (*MIB).addOperand(*argOpers[i]); 10267 MIB.addReg(t2); 10268 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10269 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10270 bInstr->memoperands_end()); 10271 10272 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10273 MIB.addReg(EAXreg); 10274 10275 // insert branch 10276 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10277 10278 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10279 return nextMBB; 10280} 10281 10282// private utility function: 64 bit atomics on 32 bit host. 10283MachineBasicBlock * 10284X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 10285 MachineBasicBlock *MBB, 10286 unsigned regOpcL, 10287 unsigned regOpcH, 10288 unsigned immOpcL, 10289 unsigned immOpcH, 10290 bool invSrc) const { 10291 // For the atomic bitwise operator, we generate 10292 // thisMBB (instructions are in pairs, except cmpxchg8b) 10293 // ld t1,t2 = [bitinstr.addr] 10294 // newMBB: 10295 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 10296 // op t5, t6 <- out1, out2, [bitinstr.val] 10297 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 10298 // mov ECX, EBX <- t5, t6 10299 // mov EAX, EDX <- t1, t2 10300 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 10301 // mov t3, t4 <- EAX, EDX 10302 // bz newMBB 10303 // result in out1, out2 10304 // fallthrough -->nextMBB 10305 10306 const TargetRegisterClass *RC = X86::GR32RegisterClass; 10307 const unsigned LoadOpc = X86::MOV32rm; 10308 const unsigned NotOpc = X86::NOT32r; 10309 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10310 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10311 MachineFunction::iterator MBBIter = MBB; 10312 ++MBBIter; 10313 10314 /// First build the CFG 10315 MachineFunction *F = MBB->getParent(); 10316 MachineBasicBlock *thisMBB = MBB; 10317 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10318 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10319 F->insert(MBBIter, newMBB); 10320 F->insert(MBBIter, nextMBB); 10321 10322 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10323 nextMBB->splice(nextMBB->begin(), thisMBB, 10324 llvm::next(MachineBasicBlock::iterator(bInstr)), 10325 thisMBB->end()); 10326 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10327 10328 // Update thisMBB to fall through to newMBB 10329 thisMBB->addSuccessor(newMBB); 10330 10331 // newMBB jumps to itself and fall through to nextMBB 10332 newMBB->addSuccessor(nextMBB); 10333 newMBB->addSuccessor(newMBB); 10334 10335 DebugLoc dl = bInstr->getDebugLoc(); 10336 // Insert instructions into newMBB based on incoming instruction 10337 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 10338 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 10339 "unexpected number of operands"); 10340 MachineOperand& dest1Oper = bInstr->getOperand(0); 10341 MachineOperand& dest2Oper = bInstr->getOperand(1); 10342 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10343 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 10344 argOpers[i] = &bInstr->getOperand(i+2); 10345 10346 // We use some of the operands multiple times, so conservatively just 10347 // clear any kill flags that might be present. 10348 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 10349 argOpers[i]->setIsKill(false); 10350 } 10351 10352 // x86 address has 5 operands: base, index, scale, displacement, and segment. 10353 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10354 10355 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10356 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 10357 for (int i=0; i <= lastAddrIndx; ++i) 10358 (*MIB).addOperand(*argOpers[i]); 10359 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10360 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 10361 // add 4 to displacement. 10362 for (int i=0; i <= lastAddrIndx-2; ++i) 10363 (*MIB).addOperand(*argOpers[i]); 10364 MachineOperand newOp3 = *(argOpers[3]); 10365 if (newOp3.isImm()) 10366 newOp3.setImm(newOp3.getImm()+4); 10367 else 10368 newOp3.setOffset(newOp3.getOffset()+4); 10369 (*MIB).addOperand(newOp3); 10370 (*MIB).addOperand(*argOpers[lastAddrIndx]); 10371 10372 // t3/4 are defined later, at the bottom of the loop 10373 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 10374 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 10375 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 10376 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 10377 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 10378 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 10379 10380 // The subsequent operations should be using the destination registers of 10381 //the PHI instructions. 10382 if (invSrc) { 10383 t1 = F->getRegInfo().createVirtualRegister(RC); 10384 t2 = F->getRegInfo().createVirtualRegister(RC); 10385 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 10386 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 10387 } else { 10388 t1 = dest1Oper.getReg(); 10389 t2 = dest2Oper.getReg(); 10390 } 10391 10392 int valArgIndx = lastAddrIndx + 1; 10393 assert((argOpers[valArgIndx]->isReg() || 10394 argOpers[valArgIndx]->isImm()) && 10395 "invalid operand"); 10396 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 10397 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 10398 if (argOpers[valArgIndx]->isReg()) 10399 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 10400 else 10401 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 10402 if (regOpcL != X86::MOV32rr) 10403 MIB.addReg(t1); 10404 (*MIB).addOperand(*argOpers[valArgIndx]); 10405 assert(argOpers[valArgIndx + 1]->isReg() == 10406 argOpers[valArgIndx]->isReg()); 10407 assert(argOpers[valArgIndx + 1]->isImm() == 10408 argOpers[valArgIndx]->isImm()); 10409 if (argOpers[valArgIndx + 1]->isReg()) 10410 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 10411 else 10412 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 10413 if (regOpcH != X86::MOV32rr) 10414 MIB.addReg(t2); 10415 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 10416 10417 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 10418 MIB.addReg(t1); 10419 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 10420 MIB.addReg(t2); 10421 10422 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 10423 MIB.addReg(t5); 10424 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 10425 MIB.addReg(t6); 10426 10427 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 10428 for (int i=0; i <= lastAddrIndx; ++i) 10429 (*MIB).addOperand(*argOpers[i]); 10430 10431 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10432 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10433 bInstr->memoperands_end()); 10434 10435 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 10436 MIB.addReg(X86::EAX); 10437 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 10438 MIB.addReg(X86::EDX); 10439 10440 // insert branch 10441 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10442 10443 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10444 return nextMBB; 10445} 10446 10447// private utility function 10448MachineBasicBlock * 10449X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 10450 MachineBasicBlock *MBB, 10451 unsigned cmovOpc) const { 10452 // For the atomic min/max operator, we generate 10453 // thisMBB: 10454 // newMBB: 10455 // ld t1 = [min/max.addr] 10456 // mov t2 = [min/max.val] 10457 // cmp t1, t2 10458 // cmov[cond] t2 = t1 10459 // mov EAX = t1 10460 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10461 // bz newMBB 10462 // fallthrough -->nextMBB 10463 // 10464 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10465 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10466 MachineFunction::iterator MBBIter = MBB; 10467 ++MBBIter; 10468 10469 /// First build the CFG 10470 MachineFunction *F = MBB->getParent(); 10471 MachineBasicBlock *thisMBB = MBB; 10472 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10473 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10474 F->insert(MBBIter, newMBB); 10475 F->insert(MBBIter, nextMBB); 10476 10477 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10478 nextMBB->splice(nextMBB->begin(), thisMBB, 10479 llvm::next(MachineBasicBlock::iterator(mInstr)), 10480 thisMBB->end()); 10481 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10482 10483 // Update thisMBB to fall through to newMBB 10484 thisMBB->addSuccessor(newMBB); 10485 10486 // newMBB jumps to newMBB and fall through to nextMBB 10487 newMBB->addSuccessor(nextMBB); 10488 newMBB->addSuccessor(newMBB); 10489 10490 DebugLoc dl = mInstr->getDebugLoc(); 10491 // Insert instructions into newMBB based on incoming instruction 10492 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10493 "unexpected number of operands"); 10494 MachineOperand& destOper = mInstr->getOperand(0); 10495 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10496 int numArgs = mInstr->getNumOperands() - 1; 10497 for (int i=0; i < numArgs; ++i) 10498 argOpers[i] = &mInstr->getOperand(i+1); 10499 10500 // x86 address has 4 operands: base, index, scale, and displacement 10501 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10502 int valArgIndx = lastAddrIndx + 1; 10503 10504 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10505 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 10506 for (int i=0; i <= lastAddrIndx; ++i) 10507 (*MIB).addOperand(*argOpers[i]); 10508 10509 // We only support register and immediate values 10510 assert((argOpers[valArgIndx]->isReg() || 10511 argOpers[valArgIndx]->isImm()) && 10512 "invalid operand"); 10513 10514 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10515 if (argOpers[valArgIndx]->isReg()) 10516 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 10517 else 10518 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 10519 (*MIB).addOperand(*argOpers[valArgIndx]); 10520 10521 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 10522 MIB.addReg(t1); 10523 10524 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 10525 MIB.addReg(t1); 10526 MIB.addReg(t2); 10527 10528 // Generate movc 10529 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10530 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 10531 MIB.addReg(t2); 10532 MIB.addReg(t1); 10533 10534 // Cmp and exchange if none has modified the memory location 10535 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 10536 for (int i=0; i <= lastAddrIndx; ++i) 10537 (*MIB).addOperand(*argOpers[i]); 10538 MIB.addReg(t3); 10539 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10540 (*MIB).setMemRefs(mInstr->memoperands_begin(), 10541 mInstr->memoperands_end()); 10542 10543 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10544 MIB.addReg(X86::EAX); 10545 10546 // insert branch 10547 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10548 10549 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 10550 return nextMBB; 10551} 10552 10553// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 10554// or XMM0_V32I8 in AVX all of this code can be replaced with that 10555// in the .td file. 10556MachineBasicBlock * 10557X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 10558 unsigned numArgs, bool memArg) const { 10559 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 10560 "Target must have SSE4.2 or AVX features enabled"); 10561 10562 DebugLoc dl = MI->getDebugLoc(); 10563 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10564 unsigned Opc; 10565 if (!Subtarget->hasAVX()) { 10566 if (memArg) 10567 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 10568 else 10569 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 10570 } else { 10571 if (memArg) 10572 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 10573 else 10574 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 10575 } 10576 10577 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 10578 for (unsigned i = 0; i < numArgs; ++i) { 10579 MachineOperand &Op = MI->getOperand(i+1); 10580 if (!(Op.isReg() && Op.isImplicit())) 10581 MIB.addOperand(Op); 10582 } 10583 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 10584 .addReg(X86::XMM0); 10585 10586 MI->eraseFromParent(); 10587 return BB; 10588} 10589 10590MachineBasicBlock * 10591X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 10592 DebugLoc dl = MI->getDebugLoc(); 10593 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10594 10595 // Address into RAX/EAX, other two args into ECX, EDX. 10596 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 10597 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 10598 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 10599 for (int i = 0; i < X86::AddrNumOperands; ++i) 10600 MIB.addOperand(MI->getOperand(i)); 10601 10602 unsigned ValOps = X86::AddrNumOperands; 10603 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 10604 .addReg(MI->getOperand(ValOps).getReg()); 10605 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 10606 .addReg(MI->getOperand(ValOps+1).getReg()); 10607 10608 // The instruction doesn't actually take any operands though. 10609 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 10610 10611 MI->eraseFromParent(); // The pseudo is gone now. 10612 return BB; 10613} 10614 10615MachineBasicBlock * 10616X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 10617 DebugLoc dl = MI->getDebugLoc(); 10618 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10619 10620 // First arg in ECX, the second in EAX. 10621 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 10622 .addReg(MI->getOperand(0).getReg()); 10623 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 10624 .addReg(MI->getOperand(1).getReg()); 10625 10626 // The instruction doesn't actually take any operands though. 10627 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 10628 10629 MI->eraseFromParent(); // The pseudo is gone now. 10630 return BB; 10631} 10632 10633MachineBasicBlock * 10634X86TargetLowering::EmitVAARG64WithCustomInserter( 10635 MachineInstr *MI, 10636 MachineBasicBlock *MBB) const { 10637 // Emit va_arg instruction on X86-64. 10638 10639 // Operands to this pseudo-instruction: 10640 // 0 ) Output : destination address (reg) 10641 // 1-5) Input : va_list address (addr, i64mem) 10642 // 6 ) ArgSize : Size (in bytes) of vararg type 10643 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 10644 // 8 ) Align : Alignment of type 10645 // 9 ) EFLAGS (implicit-def) 10646 10647 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 10648 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 10649 10650 unsigned DestReg = MI->getOperand(0).getReg(); 10651 MachineOperand &Base = MI->getOperand(1); 10652 MachineOperand &Scale = MI->getOperand(2); 10653 MachineOperand &Index = MI->getOperand(3); 10654 MachineOperand &Disp = MI->getOperand(4); 10655 MachineOperand &Segment = MI->getOperand(5); 10656 unsigned ArgSize = MI->getOperand(6).getImm(); 10657 unsigned ArgMode = MI->getOperand(7).getImm(); 10658 unsigned Align = MI->getOperand(8).getImm(); 10659 10660 // Memory Reference 10661 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 10662 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 10663 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 10664 10665 // Machine Information 10666 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10667 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 10668 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 10669 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 10670 DebugLoc DL = MI->getDebugLoc(); 10671 10672 // struct va_list { 10673 // i32 gp_offset 10674 // i32 fp_offset 10675 // i64 overflow_area (address) 10676 // i64 reg_save_area (address) 10677 // } 10678 // sizeof(va_list) = 24 10679 // alignment(va_list) = 8 10680 10681 unsigned TotalNumIntRegs = 6; 10682 unsigned TotalNumXMMRegs = 8; 10683 bool UseGPOffset = (ArgMode == 1); 10684 bool UseFPOffset = (ArgMode == 2); 10685 unsigned MaxOffset = TotalNumIntRegs * 8 + 10686 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 10687 10688 /* Align ArgSize to a multiple of 8 */ 10689 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 10690 bool NeedsAlign = (Align > 8); 10691 10692 MachineBasicBlock *thisMBB = MBB; 10693 MachineBasicBlock *overflowMBB; 10694 MachineBasicBlock *offsetMBB; 10695 MachineBasicBlock *endMBB; 10696 10697 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 10698 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 10699 unsigned OffsetReg = 0; 10700 10701 if (!UseGPOffset && !UseFPOffset) { 10702 // If we only pull from the overflow region, we don't create a branch. 10703 // We don't need to alter control flow. 10704 OffsetDestReg = 0; // unused 10705 OverflowDestReg = DestReg; 10706 10707 offsetMBB = NULL; 10708 overflowMBB = thisMBB; 10709 endMBB = thisMBB; 10710 } else { 10711 // First emit code to check if gp_offset (or fp_offset) is below the bound. 10712 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 10713 // If not, pull from overflow_area. (branch to overflowMBB) 10714 // 10715 // thisMBB 10716 // | . 10717 // | . 10718 // offsetMBB overflowMBB 10719 // | . 10720 // | . 10721 // endMBB 10722 10723 // Registers for the PHI in endMBB 10724 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 10725 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 10726 10727 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10728 MachineFunction *MF = MBB->getParent(); 10729 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10730 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10731 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10732 10733 MachineFunction::iterator MBBIter = MBB; 10734 ++MBBIter; 10735 10736 // Insert the new basic blocks 10737 MF->insert(MBBIter, offsetMBB); 10738 MF->insert(MBBIter, overflowMBB); 10739 MF->insert(MBBIter, endMBB); 10740 10741 // Transfer the remainder of MBB and its successor edges to endMBB. 10742 endMBB->splice(endMBB->begin(), thisMBB, 10743 llvm::next(MachineBasicBlock::iterator(MI)), 10744 thisMBB->end()); 10745 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10746 10747 // Make offsetMBB and overflowMBB successors of thisMBB 10748 thisMBB->addSuccessor(offsetMBB); 10749 thisMBB->addSuccessor(overflowMBB); 10750 10751 // endMBB is a successor of both offsetMBB and overflowMBB 10752 offsetMBB->addSuccessor(endMBB); 10753 overflowMBB->addSuccessor(endMBB); 10754 10755 // Load the offset value into a register 10756 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10757 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 10758 .addOperand(Base) 10759 .addOperand(Scale) 10760 .addOperand(Index) 10761 .addDisp(Disp, UseFPOffset ? 4 : 0) 10762 .addOperand(Segment) 10763 .setMemRefs(MMOBegin, MMOEnd); 10764 10765 // Check if there is enough room left to pull this argument. 10766 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 10767 .addReg(OffsetReg) 10768 .addImm(MaxOffset + 8 - ArgSizeA8); 10769 10770 // Branch to "overflowMBB" if offset >= max 10771 // Fall through to "offsetMBB" otherwise 10772 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 10773 .addMBB(overflowMBB); 10774 } 10775 10776 // In offsetMBB, emit code to use the reg_save_area. 10777 if (offsetMBB) { 10778 assert(OffsetReg != 0); 10779 10780 // Read the reg_save_area address. 10781 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 10782 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 10783 .addOperand(Base) 10784 .addOperand(Scale) 10785 .addOperand(Index) 10786 .addDisp(Disp, 16) 10787 .addOperand(Segment) 10788 .setMemRefs(MMOBegin, MMOEnd); 10789 10790 // Zero-extend the offset 10791 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 10792 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 10793 .addImm(0) 10794 .addReg(OffsetReg) 10795 .addImm(X86::sub_32bit); 10796 10797 // Add the offset to the reg_save_area to get the final address. 10798 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 10799 .addReg(OffsetReg64) 10800 .addReg(RegSaveReg); 10801 10802 // Compute the offset for the next argument 10803 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10804 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 10805 .addReg(OffsetReg) 10806 .addImm(UseFPOffset ? 16 : 8); 10807 10808 // Store it back into the va_list. 10809 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 10810 .addOperand(Base) 10811 .addOperand(Scale) 10812 .addOperand(Index) 10813 .addDisp(Disp, UseFPOffset ? 4 : 0) 10814 .addOperand(Segment) 10815 .addReg(NextOffsetReg) 10816 .setMemRefs(MMOBegin, MMOEnd); 10817 10818 // Jump to endMBB 10819 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 10820 .addMBB(endMBB); 10821 } 10822 10823 // 10824 // Emit code to use overflow area 10825 // 10826 10827 // Load the overflow_area address into a register. 10828 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 10829 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 10830 .addOperand(Base) 10831 .addOperand(Scale) 10832 .addOperand(Index) 10833 .addDisp(Disp, 8) 10834 .addOperand(Segment) 10835 .setMemRefs(MMOBegin, MMOEnd); 10836 10837 // If we need to align it, do so. Otherwise, just copy the address 10838 // to OverflowDestReg. 10839 if (NeedsAlign) { 10840 // Align the overflow address 10841 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 10842 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 10843 10844 // aligned_addr = (addr + (align-1)) & ~(align-1) 10845 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 10846 .addReg(OverflowAddrReg) 10847 .addImm(Align-1); 10848 10849 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 10850 .addReg(TmpReg) 10851 .addImm(~(uint64_t)(Align-1)); 10852 } else { 10853 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 10854 .addReg(OverflowAddrReg); 10855 } 10856 10857 // Compute the next overflow address after this argument. 10858 // (the overflow address should be kept 8-byte aligned) 10859 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 10860 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 10861 .addReg(OverflowDestReg) 10862 .addImm(ArgSizeA8); 10863 10864 // Store the new overflow address. 10865 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 10866 .addOperand(Base) 10867 .addOperand(Scale) 10868 .addOperand(Index) 10869 .addDisp(Disp, 8) 10870 .addOperand(Segment) 10871 .addReg(NextAddrReg) 10872 .setMemRefs(MMOBegin, MMOEnd); 10873 10874 // If we branched, emit the PHI to the front of endMBB. 10875 if (offsetMBB) { 10876 BuildMI(*endMBB, endMBB->begin(), DL, 10877 TII->get(X86::PHI), DestReg) 10878 .addReg(OffsetDestReg).addMBB(offsetMBB) 10879 .addReg(OverflowDestReg).addMBB(overflowMBB); 10880 } 10881 10882 // Erase the pseudo instruction 10883 MI->eraseFromParent(); 10884 10885 return endMBB; 10886} 10887 10888MachineBasicBlock * 10889X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 10890 MachineInstr *MI, 10891 MachineBasicBlock *MBB) const { 10892 // Emit code to save XMM registers to the stack. The ABI says that the 10893 // number of registers to save is given in %al, so it's theoretically 10894 // possible to do an indirect jump trick to avoid saving all of them, 10895 // however this code takes a simpler approach and just executes all 10896 // of the stores if %al is non-zero. It's less code, and it's probably 10897 // easier on the hardware branch predictor, and stores aren't all that 10898 // expensive anyway. 10899 10900 // Create the new basic blocks. One block contains all the XMM stores, 10901 // and one block is the final destination regardless of whether any 10902 // stores were performed. 10903 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10904 MachineFunction *F = MBB->getParent(); 10905 MachineFunction::iterator MBBIter = MBB; 10906 ++MBBIter; 10907 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 10908 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 10909 F->insert(MBBIter, XMMSaveMBB); 10910 F->insert(MBBIter, EndMBB); 10911 10912 // Transfer the remainder of MBB and its successor edges to EndMBB. 10913 EndMBB->splice(EndMBB->begin(), MBB, 10914 llvm::next(MachineBasicBlock::iterator(MI)), 10915 MBB->end()); 10916 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 10917 10918 // The original block will now fall through to the XMM save block. 10919 MBB->addSuccessor(XMMSaveMBB); 10920 // The XMMSaveMBB will fall through to the end block. 10921 XMMSaveMBB->addSuccessor(EndMBB); 10922 10923 // Now add the instructions. 10924 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10925 DebugLoc DL = MI->getDebugLoc(); 10926 10927 unsigned CountReg = MI->getOperand(0).getReg(); 10928 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 10929 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 10930 10931 if (!Subtarget->isTargetWin64()) { 10932 // If %al is 0, branch around the XMM save block. 10933 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 10934 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 10935 MBB->addSuccessor(EndMBB); 10936 } 10937 10938 // In the XMM save block, save all the XMM argument registers. 10939 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 10940 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 10941 MachineMemOperand *MMO = 10942 F->getMachineMemOperand( 10943 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 10944 MachineMemOperand::MOStore, 10945 /*Size=*/16, /*Align=*/16); 10946 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 10947 .addFrameIndex(RegSaveFrameIndex) 10948 .addImm(/*Scale=*/1) 10949 .addReg(/*IndexReg=*/0) 10950 .addImm(/*Disp=*/Offset) 10951 .addReg(/*Segment=*/0) 10952 .addReg(MI->getOperand(i).getReg()) 10953 .addMemOperand(MMO); 10954 } 10955 10956 MI->eraseFromParent(); // The pseudo instruction is gone now. 10957 10958 return EndMBB; 10959} 10960 10961MachineBasicBlock * 10962X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 10963 MachineBasicBlock *BB) const { 10964 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10965 DebugLoc DL = MI->getDebugLoc(); 10966 10967 // To "insert" a SELECT_CC instruction, we actually have to insert the 10968 // diamond control-flow pattern. The incoming instruction knows the 10969 // destination vreg to set, the condition code register to branch on, the 10970 // true/false values to select between, and a branch opcode to use. 10971 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 10972 MachineFunction::iterator It = BB; 10973 ++It; 10974 10975 // thisMBB: 10976 // ... 10977 // TrueVal = ... 10978 // cmpTY ccX, r1, r2 10979 // bCC copy1MBB 10980 // fallthrough --> copy0MBB 10981 MachineBasicBlock *thisMBB = BB; 10982 MachineFunction *F = BB->getParent(); 10983 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 10984 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 10985 F->insert(It, copy0MBB); 10986 F->insert(It, sinkMBB); 10987 10988 // If the EFLAGS register isn't dead in the terminator, then claim that it's 10989 // live into the sink and copy blocks. 10990 const MachineFunction *MF = BB->getParent(); 10991 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 10992 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 10993 10994 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 10995 const MachineOperand &MO = MI->getOperand(I); 10996 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 10997 unsigned Reg = MO.getReg(); 10998 if (Reg != X86::EFLAGS) continue; 10999 copy0MBB->addLiveIn(Reg); 11000 sinkMBB->addLiveIn(Reg); 11001 } 11002 11003 // Transfer the remainder of BB and its successor edges to sinkMBB. 11004 sinkMBB->splice(sinkMBB->begin(), BB, 11005 llvm::next(MachineBasicBlock::iterator(MI)), 11006 BB->end()); 11007 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11008 11009 // Add the true and fallthrough blocks as its successors. 11010 BB->addSuccessor(copy0MBB); 11011 BB->addSuccessor(sinkMBB); 11012 11013 // Create the conditional branch instruction. 11014 unsigned Opc = 11015 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11016 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11017 11018 // copy0MBB: 11019 // %FalseValue = ... 11020 // # fallthrough to sinkMBB 11021 copy0MBB->addSuccessor(sinkMBB); 11022 11023 // sinkMBB: 11024 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11025 // ... 11026 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11027 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11028 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11029 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11030 11031 MI->eraseFromParent(); // The pseudo instruction is gone now. 11032 return sinkMBB; 11033} 11034 11035MachineBasicBlock * 11036X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 11037 MachineBasicBlock *BB) const { 11038 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11039 DebugLoc DL = MI->getDebugLoc(); 11040 11041 assert(!Subtarget->isTargetEnvMacho()); 11042 11043 // The lowering is pretty easy: we're just emitting the call to _alloca. The 11044 // non-trivial part is impdef of ESP. 11045 11046 if (Subtarget->isTargetWin64()) { 11047 if (Subtarget->isTargetCygMing()) { 11048 // ___chkstk(Mingw64): 11049 // Clobbers R10, R11, RAX and EFLAGS. 11050 // Updates RSP. 11051 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11052 .addExternalSymbol("___chkstk") 11053 .addReg(X86::RAX, RegState::Implicit) 11054 .addReg(X86::RSP, RegState::Implicit) 11055 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 11056 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 11057 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11058 } else { 11059 // __chkstk(MSVCRT): does not update stack pointer. 11060 // Clobbers R10, R11 and EFLAGS. 11061 // FIXME: RAX(allocated size) might be reused and not killed. 11062 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11063 .addExternalSymbol("__chkstk") 11064 .addReg(X86::RAX, RegState::Implicit) 11065 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11066 // RAX has the offset to subtracted from RSP. 11067 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 11068 .addReg(X86::RSP) 11069 .addReg(X86::RAX); 11070 } 11071 } else { 11072 const char *StackProbeSymbol = 11073 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 11074 11075 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 11076 .addExternalSymbol(StackProbeSymbol) 11077 .addReg(X86::EAX, RegState::Implicit) 11078 .addReg(X86::ESP, RegState::Implicit) 11079 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 11080 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 11081 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11082 } 11083 11084 MI->eraseFromParent(); // The pseudo instruction is gone now. 11085 return BB; 11086} 11087 11088MachineBasicBlock * 11089X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 11090 MachineBasicBlock *BB) const { 11091 // This is pretty easy. We're taking the value that we received from 11092 // our load from the relocation, sticking it in either RDI (x86-64) 11093 // or EAX and doing an indirect call. The return value will then 11094 // be in the normal return register. 11095 const X86InstrInfo *TII 11096 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 11097 DebugLoc DL = MI->getDebugLoc(); 11098 MachineFunction *F = BB->getParent(); 11099 11100 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 11101 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 11102 11103 if (Subtarget->is64Bit()) { 11104 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11105 TII->get(X86::MOV64rm), X86::RDI) 11106 .addReg(X86::RIP) 11107 .addImm(0).addReg(0) 11108 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11109 MI->getOperand(3).getTargetFlags()) 11110 .addReg(0); 11111 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 11112 addDirectMem(MIB, X86::RDI); 11113 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 11114 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11115 TII->get(X86::MOV32rm), X86::EAX) 11116 .addReg(0) 11117 .addImm(0).addReg(0) 11118 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11119 MI->getOperand(3).getTargetFlags()) 11120 .addReg(0); 11121 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11122 addDirectMem(MIB, X86::EAX); 11123 } else { 11124 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11125 TII->get(X86::MOV32rm), X86::EAX) 11126 .addReg(TII->getGlobalBaseReg(F)) 11127 .addImm(0).addReg(0) 11128 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11129 MI->getOperand(3).getTargetFlags()) 11130 .addReg(0); 11131 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11132 addDirectMem(MIB, X86::EAX); 11133 } 11134 11135 MI->eraseFromParent(); // The pseudo instruction is gone now. 11136 return BB; 11137} 11138 11139MachineBasicBlock * 11140X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 11141 MachineBasicBlock *BB) const { 11142 switch (MI->getOpcode()) { 11143 default: assert(false && "Unexpected instr type to insert"); 11144 case X86::TAILJMPd64: 11145 case X86::TAILJMPr64: 11146 case X86::TAILJMPm64: 11147 assert(!"TAILJMP64 would not be touched here."); 11148 case X86::TCRETURNdi64: 11149 case X86::TCRETURNri64: 11150 case X86::TCRETURNmi64: 11151 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 11152 // On AMD64, additional defs should be added before register allocation. 11153 if (!Subtarget->isTargetWin64()) { 11154 MI->addRegisterDefined(X86::RSI); 11155 MI->addRegisterDefined(X86::RDI); 11156 MI->addRegisterDefined(X86::XMM6); 11157 MI->addRegisterDefined(X86::XMM7); 11158 MI->addRegisterDefined(X86::XMM8); 11159 MI->addRegisterDefined(X86::XMM9); 11160 MI->addRegisterDefined(X86::XMM10); 11161 MI->addRegisterDefined(X86::XMM11); 11162 MI->addRegisterDefined(X86::XMM12); 11163 MI->addRegisterDefined(X86::XMM13); 11164 MI->addRegisterDefined(X86::XMM14); 11165 MI->addRegisterDefined(X86::XMM15); 11166 } 11167 return BB; 11168 case X86::WIN_ALLOCA: 11169 return EmitLoweredWinAlloca(MI, BB); 11170 case X86::TLSCall_32: 11171 case X86::TLSCall_64: 11172 return EmitLoweredTLSCall(MI, BB); 11173 case X86::CMOV_GR8: 11174 case X86::CMOV_FR32: 11175 case X86::CMOV_FR64: 11176 case X86::CMOV_V4F32: 11177 case X86::CMOV_V2F64: 11178 case X86::CMOV_V2I64: 11179 case X86::CMOV_V8F32: 11180 case X86::CMOV_V4F64: 11181 case X86::CMOV_V4I64: 11182 case X86::CMOV_GR16: 11183 case X86::CMOV_GR32: 11184 case X86::CMOV_RFP32: 11185 case X86::CMOV_RFP64: 11186 case X86::CMOV_RFP80: 11187 return EmitLoweredSelect(MI, BB); 11188 11189 case X86::FP32_TO_INT16_IN_MEM: 11190 case X86::FP32_TO_INT32_IN_MEM: 11191 case X86::FP32_TO_INT64_IN_MEM: 11192 case X86::FP64_TO_INT16_IN_MEM: 11193 case X86::FP64_TO_INT32_IN_MEM: 11194 case X86::FP64_TO_INT64_IN_MEM: 11195 case X86::FP80_TO_INT16_IN_MEM: 11196 case X86::FP80_TO_INT32_IN_MEM: 11197 case X86::FP80_TO_INT64_IN_MEM: { 11198 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11199 DebugLoc DL = MI->getDebugLoc(); 11200 11201 // Change the floating point control register to use "round towards zero" 11202 // mode when truncating to an integer value. 11203 MachineFunction *F = BB->getParent(); 11204 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 11205 addFrameReference(BuildMI(*BB, MI, DL, 11206 TII->get(X86::FNSTCW16m)), CWFrameIdx); 11207 11208 // Load the old value of the high byte of the control word... 11209 unsigned OldCW = 11210 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 11211 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 11212 CWFrameIdx); 11213 11214 // Set the high part to be round to zero... 11215 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 11216 .addImm(0xC7F); 11217 11218 // Reload the modified control word now... 11219 addFrameReference(BuildMI(*BB, MI, DL, 11220 TII->get(X86::FLDCW16m)), CWFrameIdx); 11221 11222 // Restore the memory image of control word to original value 11223 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 11224 .addReg(OldCW); 11225 11226 // Get the X86 opcode to use. 11227 unsigned Opc; 11228 switch (MI->getOpcode()) { 11229 default: llvm_unreachable("illegal opcode!"); 11230 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 11231 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 11232 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 11233 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 11234 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 11235 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 11236 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 11237 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 11238 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 11239 } 11240 11241 X86AddressMode AM; 11242 MachineOperand &Op = MI->getOperand(0); 11243 if (Op.isReg()) { 11244 AM.BaseType = X86AddressMode::RegBase; 11245 AM.Base.Reg = Op.getReg(); 11246 } else { 11247 AM.BaseType = X86AddressMode::FrameIndexBase; 11248 AM.Base.FrameIndex = Op.getIndex(); 11249 } 11250 Op = MI->getOperand(1); 11251 if (Op.isImm()) 11252 AM.Scale = Op.getImm(); 11253 Op = MI->getOperand(2); 11254 if (Op.isImm()) 11255 AM.IndexReg = Op.getImm(); 11256 Op = MI->getOperand(3); 11257 if (Op.isGlobal()) { 11258 AM.GV = Op.getGlobal(); 11259 } else { 11260 AM.Disp = Op.getImm(); 11261 } 11262 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 11263 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 11264 11265 // Reload the original control word now. 11266 addFrameReference(BuildMI(*BB, MI, DL, 11267 TII->get(X86::FLDCW16m)), CWFrameIdx); 11268 11269 MI->eraseFromParent(); // The pseudo instruction is gone now. 11270 return BB; 11271 } 11272 // String/text processing lowering. 11273 case X86::PCMPISTRM128REG: 11274 case X86::VPCMPISTRM128REG: 11275 return EmitPCMP(MI, BB, 3, false /* in-mem */); 11276 case X86::PCMPISTRM128MEM: 11277 case X86::VPCMPISTRM128MEM: 11278 return EmitPCMP(MI, BB, 3, true /* in-mem */); 11279 case X86::PCMPESTRM128REG: 11280 case X86::VPCMPESTRM128REG: 11281 return EmitPCMP(MI, BB, 5, false /* in mem */); 11282 case X86::PCMPESTRM128MEM: 11283 case X86::VPCMPESTRM128MEM: 11284 return EmitPCMP(MI, BB, 5, true /* in mem */); 11285 11286 // Thread synchronization. 11287 case X86::MONITOR: 11288 return EmitMonitor(MI, BB); 11289 case X86::MWAIT: 11290 return EmitMwait(MI, BB); 11291 11292 // Atomic Lowering. 11293 case X86::ATOMAND32: 11294 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 11295 X86::AND32ri, X86::MOV32rm, 11296 X86::LCMPXCHG32, 11297 X86::NOT32r, X86::EAX, 11298 X86::GR32RegisterClass); 11299 case X86::ATOMOR32: 11300 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 11301 X86::OR32ri, X86::MOV32rm, 11302 X86::LCMPXCHG32, 11303 X86::NOT32r, X86::EAX, 11304 X86::GR32RegisterClass); 11305 case X86::ATOMXOR32: 11306 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 11307 X86::XOR32ri, X86::MOV32rm, 11308 X86::LCMPXCHG32, 11309 X86::NOT32r, X86::EAX, 11310 X86::GR32RegisterClass); 11311 case X86::ATOMNAND32: 11312 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 11313 X86::AND32ri, X86::MOV32rm, 11314 X86::LCMPXCHG32, 11315 X86::NOT32r, X86::EAX, 11316 X86::GR32RegisterClass, true); 11317 case X86::ATOMMIN32: 11318 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 11319 case X86::ATOMMAX32: 11320 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 11321 case X86::ATOMUMIN32: 11322 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 11323 case X86::ATOMUMAX32: 11324 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 11325 11326 case X86::ATOMAND16: 11327 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 11328 X86::AND16ri, X86::MOV16rm, 11329 X86::LCMPXCHG16, 11330 X86::NOT16r, X86::AX, 11331 X86::GR16RegisterClass); 11332 case X86::ATOMOR16: 11333 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 11334 X86::OR16ri, X86::MOV16rm, 11335 X86::LCMPXCHG16, 11336 X86::NOT16r, X86::AX, 11337 X86::GR16RegisterClass); 11338 case X86::ATOMXOR16: 11339 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 11340 X86::XOR16ri, X86::MOV16rm, 11341 X86::LCMPXCHG16, 11342 X86::NOT16r, X86::AX, 11343 X86::GR16RegisterClass); 11344 case X86::ATOMNAND16: 11345 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 11346 X86::AND16ri, X86::MOV16rm, 11347 X86::LCMPXCHG16, 11348 X86::NOT16r, X86::AX, 11349 X86::GR16RegisterClass, true); 11350 case X86::ATOMMIN16: 11351 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 11352 case X86::ATOMMAX16: 11353 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 11354 case X86::ATOMUMIN16: 11355 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 11356 case X86::ATOMUMAX16: 11357 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 11358 11359 case X86::ATOMAND8: 11360 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 11361 X86::AND8ri, X86::MOV8rm, 11362 X86::LCMPXCHG8, 11363 X86::NOT8r, X86::AL, 11364 X86::GR8RegisterClass); 11365 case X86::ATOMOR8: 11366 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 11367 X86::OR8ri, X86::MOV8rm, 11368 X86::LCMPXCHG8, 11369 X86::NOT8r, X86::AL, 11370 X86::GR8RegisterClass); 11371 case X86::ATOMXOR8: 11372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 11373 X86::XOR8ri, X86::MOV8rm, 11374 X86::LCMPXCHG8, 11375 X86::NOT8r, X86::AL, 11376 X86::GR8RegisterClass); 11377 case X86::ATOMNAND8: 11378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 11379 X86::AND8ri, X86::MOV8rm, 11380 X86::LCMPXCHG8, 11381 X86::NOT8r, X86::AL, 11382 X86::GR8RegisterClass, true); 11383 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 11384 // This group is for 64-bit host. 11385 case X86::ATOMAND64: 11386 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 11387 X86::AND64ri32, X86::MOV64rm, 11388 X86::LCMPXCHG64, 11389 X86::NOT64r, X86::RAX, 11390 X86::GR64RegisterClass); 11391 case X86::ATOMOR64: 11392 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 11393 X86::OR64ri32, X86::MOV64rm, 11394 X86::LCMPXCHG64, 11395 X86::NOT64r, X86::RAX, 11396 X86::GR64RegisterClass); 11397 case X86::ATOMXOR64: 11398 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 11399 X86::XOR64ri32, X86::MOV64rm, 11400 X86::LCMPXCHG64, 11401 X86::NOT64r, X86::RAX, 11402 X86::GR64RegisterClass); 11403 case X86::ATOMNAND64: 11404 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 11405 X86::AND64ri32, X86::MOV64rm, 11406 X86::LCMPXCHG64, 11407 X86::NOT64r, X86::RAX, 11408 X86::GR64RegisterClass, true); 11409 case X86::ATOMMIN64: 11410 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 11411 case X86::ATOMMAX64: 11412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 11413 case X86::ATOMUMIN64: 11414 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 11415 case X86::ATOMUMAX64: 11416 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 11417 11418 // This group does 64-bit operations on a 32-bit host. 11419 case X86::ATOMAND6432: 11420 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11421 X86::AND32rr, X86::AND32rr, 11422 X86::AND32ri, X86::AND32ri, 11423 false); 11424 case X86::ATOMOR6432: 11425 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11426 X86::OR32rr, X86::OR32rr, 11427 X86::OR32ri, X86::OR32ri, 11428 false); 11429 case X86::ATOMXOR6432: 11430 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11431 X86::XOR32rr, X86::XOR32rr, 11432 X86::XOR32ri, X86::XOR32ri, 11433 false); 11434 case X86::ATOMNAND6432: 11435 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11436 X86::AND32rr, X86::AND32rr, 11437 X86::AND32ri, X86::AND32ri, 11438 true); 11439 case X86::ATOMADD6432: 11440 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11441 X86::ADD32rr, X86::ADC32rr, 11442 X86::ADD32ri, X86::ADC32ri, 11443 false); 11444 case X86::ATOMSUB6432: 11445 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11446 X86::SUB32rr, X86::SBB32rr, 11447 X86::SUB32ri, X86::SBB32ri, 11448 false); 11449 case X86::ATOMSWAP6432: 11450 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11451 X86::MOV32rr, X86::MOV32rr, 11452 X86::MOV32ri, X86::MOV32ri, 11453 false); 11454 case X86::VASTART_SAVE_XMM_REGS: 11455 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 11456 11457 case X86::VAARG_64: 11458 return EmitVAARG64WithCustomInserter(MI, BB); 11459 } 11460} 11461 11462//===----------------------------------------------------------------------===// 11463// X86 Optimization Hooks 11464//===----------------------------------------------------------------------===// 11465 11466void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 11467 const APInt &Mask, 11468 APInt &KnownZero, 11469 APInt &KnownOne, 11470 const SelectionDAG &DAG, 11471 unsigned Depth) const { 11472 unsigned Opc = Op.getOpcode(); 11473 assert((Opc >= ISD::BUILTIN_OP_END || 11474 Opc == ISD::INTRINSIC_WO_CHAIN || 11475 Opc == ISD::INTRINSIC_W_CHAIN || 11476 Opc == ISD::INTRINSIC_VOID) && 11477 "Should use MaskedValueIsZero if you don't know whether Op" 11478 " is a target node!"); 11479 11480 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 11481 switch (Opc) { 11482 default: break; 11483 case X86ISD::ADD: 11484 case X86ISD::SUB: 11485 case X86ISD::ADC: 11486 case X86ISD::SBB: 11487 case X86ISD::SMUL: 11488 case X86ISD::UMUL: 11489 case X86ISD::INC: 11490 case X86ISD::DEC: 11491 case X86ISD::OR: 11492 case X86ISD::XOR: 11493 case X86ISD::AND: 11494 // These nodes' second result is a boolean. 11495 if (Op.getResNo() == 0) 11496 break; 11497 // Fallthrough 11498 case X86ISD::SETCC: 11499 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 11500 Mask.getBitWidth() - 1); 11501 break; 11502 } 11503} 11504 11505unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 11506 unsigned Depth) const { 11507 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 11508 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 11509 return Op.getValueType().getScalarType().getSizeInBits(); 11510 11511 // Fallback case. 11512 return 1; 11513} 11514 11515/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 11516/// node is a GlobalAddress + offset. 11517bool X86TargetLowering::isGAPlusOffset(SDNode *N, 11518 const GlobalValue* &GA, 11519 int64_t &Offset) const { 11520 if (N->getOpcode() == X86ISD::Wrapper) { 11521 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 11522 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 11523 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 11524 return true; 11525 } 11526 } 11527 return TargetLowering::isGAPlusOffset(N, GA, Offset); 11528} 11529 11530/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 11531static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 11532 TargetLowering::DAGCombinerInfo &DCI) { 11533 DebugLoc dl = N->getDebugLoc(); 11534 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 11535 SDValue V1 = SVOp->getOperand(0); 11536 SDValue V2 = SVOp->getOperand(1); 11537 EVT VT = SVOp->getValueType(0); 11538 11539 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 11540 V2.getOpcode() == ISD::CONCAT_VECTORS) { 11541 // 11542 // 0,0,0,... 11543 // | 11544 // V UNDEF BUILD_VECTOR UNDEF 11545 // \ / \ / 11546 // CONCAT_VECTOR CONCAT_VECTOR 11547 // \ / 11548 // \ / 11549 // RESULT: V + zero extended 11550 // 11551 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 11552 V2.getOperand(1).getOpcode() != ISD::UNDEF || 11553 V1.getOperand(1).getOpcode() != ISD::UNDEF) 11554 return SDValue(); 11555 11556 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 11557 return SDValue(); 11558 11559 // To match the shuffle mask, the first half of the mask should 11560 // be exactly the first vector, and all the rest a splat with the 11561 // first element of the second one. 11562 int NumElems = VT.getVectorNumElements(); 11563 for (int i = 0; i < NumElems/2; ++i) 11564 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 11565 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 11566 return SDValue(); 11567 11568 // Emit a zeroed vector and insert the desired subvector on its 11569 // first half. 11570 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 11571 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 11572 DAG.getConstant(0, MVT::i32), DAG, dl); 11573 return DCI.CombineTo(N, InsV); 11574 } 11575 11576 return SDValue(); 11577} 11578 11579/// PerformShuffleCombine - Performs several different shuffle combines. 11580static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 11581 TargetLowering::DAGCombinerInfo &DCI) { 11582 DebugLoc dl = N->getDebugLoc(); 11583 EVT VT = N->getValueType(0); 11584 11585 // Don't create instructions with illegal types after legalize types has run. 11586 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11587 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 11588 return SDValue(); 11589 11590 // Only handle pure VECTOR_SHUFFLE nodes. 11591 if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE) 11592 return PerformShuffleCombine256(N, DAG, DCI); 11593 11594 // Only handle 128 wide vector from here on. 11595 if (VT.getSizeInBits() != 128) 11596 return SDValue(); 11597 11598 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 11599 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 11600 // consecutive, non-overlapping, and in the right order. 11601 SmallVector<SDValue, 16> Elts; 11602 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 11603 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 11604 11605 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 11606} 11607 11608/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 11609/// generation and convert it from being a bunch of shuffles and extracts 11610/// to a simple store and scalar loads to extract the elements. 11611static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 11612 const TargetLowering &TLI) { 11613 SDValue InputVector = N->getOperand(0); 11614 11615 // Only operate on vectors of 4 elements, where the alternative shuffling 11616 // gets to be more expensive. 11617 if (InputVector.getValueType() != MVT::v4i32) 11618 return SDValue(); 11619 11620 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 11621 // single use which is a sign-extend or zero-extend, and all elements are 11622 // used. 11623 SmallVector<SDNode *, 4> Uses; 11624 unsigned ExtractedElements = 0; 11625 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 11626 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 11627 if (UI.getUse().getResNo() != InputVector.getResNo()) 11628 return SDValue(); 11629 11630 SDNode *Extract = *UI; 11631 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 11632 return SDValue(); 11633 11634 if (Extract->getValueType(0) != MVT::i32) 11635 return SDValue(); 11636 if (!Extract->hasOneUse()) 11637 return SDValue(); 11638 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 11639 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 11640 return SDValue(); 11641 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 11642 return SDValue(); 11643 11644 // Record which element was extracted. 11645 ExtractedElements |= 11646 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 11647 11648 Uses.push_back(Extract); 11649 } 11650 11651 // If not all the elements were used, this may not be worthwhile. 11652 if (ExtractedElements != 15) 11653 return SDValue(); 11654 11655 // Ok, we've now decided to do the transformation. 11656 DebugLoc dl = InputVector.getDebugLoc(); 11657 11658 // Store the value to a temporary stack slot. 11659 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 11660 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 11661 MachinePointerInfo(), false, false, 0); 11662 11663 // Replace each use (extract) with a load of the appropriate element. 11664 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 11665 UE = Uses.end(); UI != UE; ++UI) { 11666 SDNode *Extract = *UI; 11667 11668 // cOMpute the element's address. 11669 SDValue Idx = Extract->getOperand(1); 11670 unsigned EltSize = 11671 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 11672 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 11673 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 11674 11675 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 11676 StackPtr, OffsetVal); 11677 11678 // Load the scalar. 11679 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 11680 ScalarAddr, MachinePointerInfo(), 11681 false, false, 0); 11682 11683 // Replace the exact with the load. 11684 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 11685 } 11686 11687 // The replacement was made in place; don't return anything. 11688 return SDValue(); 11689} 11690 11691/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 11692static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 11693 const X86Subtarget *Subtarget) { 11694 DebugLoc DL = N->getDebugLoc(); 11695 SDValue Cond = N->getOperand(0); 11696 // Get the LHS/RHS of the select. 11697 SDValue LHS = N->getOperand(1); 11698 SDValue RHS = N->getOperand(2); 11699 11700 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 11701 // instructions match the semantics of the common C idiom x<y?x:y but not 11702 // x<=y?x:y, because of how they handle negative zero (which can be 11703 // ignored in unsafe-math mode). 11704 if (Subtarget->hasSSE2() && 11705 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 11706 Cond.getOpcode() == ISD::SETCC) { 11707 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 11708 11709 unsigned Opcode = 0; 11710 // Check for x CC y ? x : y. 11711 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 11712 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 11713 switch (CC) { 11714 default: break; 11715 case ISD::SETULT: 11716 // Converting this to a min would handle NaNs incorrectly, and swapping 11717 // the operands would cause it to handle comparisons between positive 11718 // and negative zero incorrectly. 11719 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11720 if (!UnsafeFPMath && 11721 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11722 break; 11723 std::swap(LHS, RHS); 11724 } 11725 Opcode = X86ISD::FMIN; 11726 break; 11727 case ISD::SETOLE: 11728 // Converting this to a min would handle comparisons between positive 11729 // and negative zero incorrectly. 11730 if (!UnsafeFPMath && 11731 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 11732 break; 11733 Opcode = X86ISD::FMIN; 11734 break; 11735 case ISD::SETULE: 11736 // Converting this to a min would handle both negative zeros and NaNs 11737 // incorrectly, but we can swap the operands to fix both. 11738 std::swap(LHS, RHS); 11739 case ISD::SETOLT: 11740 case ISD::SETLT: 11741 case ISD::SETLE: 11742 Opcode = X86ISD::FMIN; 11743 break; 11744 11745 case ISD::SETOGE: 11746 // Converting this to a max would handle comparisons between positive 11747 // and negative zero incorrectly. 11748 if (!UnsafeFPMath && 11749 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 11750 break; 11751 Opcode = X86ISD::FMAX; 11752 break; 11753 case ISD::SETUGT: 11754 // Converting this to a max would handle NaNs incorrectly, and swapping 11755 // the operands would cause it to handle comparisons between positive 11756 // and negative zero incorrectly. 11757 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11758 if (!UnsafeFPMath && 11759 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11760 break; 11761 std::swap(LHS, RHS); 11762 } 11763 Opcode = X86ISD::FMAX; 11764 break; 11765 case ISD::SETUGE: 11766 // Converting this to a max would handle both negative zeros and NaNs 11767 // incorrectly, but we can swap the operands to fix both. 11768 std::swap(LHS, RHS); 11769 case ISD::SETOGT: 11770 case ISD::SETGT: 11771 case ISD::SETGE: 11772 Opcode = X86ISD::FMAX; 11773 break; 11774 } 11775 // Check for x CC y ? y : x -- a min/max with reversed arms. 11776 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 11777 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 11778 switch (CC) { 11779 default: break; 11780 case ISD::SETOGE: 11781 // Converting this to a min would handle comparisons between positive 11782 // and negative zero incorrectly, and swapping the operands would 11783 // cause it to handle NaNs incorrectly. 11784 if (!UnsafeFPMath && 11785 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 11786 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11787 break; 11788 std::swap(LHS, RHS); 11789 } 11790 Opcode = X86ISD::FMIN; 11791 break; 11792 case ISD::SETUGT: 11793 // Converting this to a min would handle NaNs incorrectly. 11794 if (!UnsafeFPMath && 11795 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 11796 break; 11797 Opcode = X86ISD::FMIN; 11798 break; 11799 case ISD::SETUGE: 11800 // Converting this to a min would handle both negative zeros and NaNs 11801 // incorrectly, but we can swap the operands to fix both. 11802 std::swap(LHS, RHS); 11803 case ISD::SETOGT: 11804 case ISD::SETGT: 11805 case ISD::SETGE: 11806 Opcode = X86ISD::FMIN; 11807 break; 11808 11809 case ISD::SETULT: 11810 // Converting this to a max would handle NaNs incorrectly. 11811 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11812 break; 11813 Opcode = X86ISD::FMAX; 11814 break; 11815 case ISD::SETOLE: 11816 // Converting this to a max would handle comparisons between positive 11817 // and negative zero incorrectly, and swapping the operands would 11818 // cause it to handle NaNs incorrectly. 11819 if (!UnsafeFPMath && 11820 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 11821 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11822 break; 11823 std::swap(LHS, RHS); 11824 } 11825 Opcode = X86ISD::FMAX; 11826 break; 11827 case ISD::SETULE: 11828 // Converting this to a max would handle both negative zeros and NaNs 11829 // incorrectly, but we can swap the operands to fix both. 11830 std::swap(LHS, RHS); 11831 case ISD::SETOLT: 11832 case ISD::SETLT: 11833 case ISD::SETLE: 11834 Opcode = X86ISD::FMAX; 11835 break; 11836 } 11837 } 11838 11839 if (Opcode) 11840 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 11841 } 11842 11843 // If this is a select between two integer constants, try to do some 11844 // optimizations. 11845 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 11846 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 11847 // Don't do this for crazy integer types. 11848 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 11849 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 11850 // so that TrueC (the true value) is larger than FalseC. 11851 bool NeedsCondInvert = false; 11852 11853 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 11854 // Efficiently invertible. 11855 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 11856 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 11857 isa<ConstantSDNode>(Cond.getOperand(1))))) { 11858 NeedsCondInvert = true; 11859 std::swap(TrueC, FalseC); 11860 } 11861 11862 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 11863 if (FalseC->getAPIntValue() == 0 && 11864 TrueC->getAPIntValue().isPowerOf2()) { 11865 if (NeedsCondInvert) // Invert the condition if needed. 11866 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11867 DAG.getConstant(1, Cond.getValueType())); 11868 11869 // Zero extend the condition if needed. 11870 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 11871 11872 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 11873 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 11874 DAG.getConstant(ShAmt, MVT::i8)); 11875 } 11876 11877 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 11878 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 11879 if (NeedsCondInvert) // Invert the condition if needed. 11880 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11881 DAG.getConstant(1, Cond.getValueType())); 11882 11883 // Zero extend the condition if needed. 11884 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 11885 FalseC->getValueType(0), Cond); 11886 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11887 SDValue(FalseC, 0)); 11888 } 11889 11890 // Optimize cases that will turn into an LEA instruction. This requires 11891 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 11892 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 11893 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 11894 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 11895 11896 bool isFastMultiplier = false; 11897 if (Diff < 10) { 11898 switch ((unsigned char)Diff) { 11899 default: break; 11900 case 1: // result = add base, cond 11901 case 2: // result = lea base( , cond*2) 11902 case 3: // result = lea base(cond, cond*2) 11903 case 4: // result = lea base( , cond*4) 11904 case 5: // result = lea base(cond, cond*4) 11905 case 8: // result = lea base( , cond*8) 11906 case 9: // result = lea base(cond, cond*8) 11907 isFastMultiplier = true; 11908 break; 11909 } 11910 } 11911 11912 if (isFastMultiplier) { 11913 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 11914 if (NeedsCondInvert) // Invert the condition if needed. 11915 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11916 DAG.getConstant(1, Cond.getValueType())); 11917 11918 // Zero extend the condition if needed. 11919 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 11920 Cond); 11921 // Scale the condition by the difference. 11922 if (Diff != 1) 11923 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 11924 DAG.getConstant(Diff, Cond.getValueType())); 11925 11926 // Add the base if non-zero. 11927 if (FalseC->getAPIntValue() != 0) 11928 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11929 SDValue(FalseC, 0)); 11930 return Cond; 11931 } 11932 } 11933 } 11934 } 11935 11936 return SDValue(); 11937} 11938 11939/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 11940static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 11941 TargetLowering::DAGCombinerInfo &DCI) { 11942 DebugLoc DL = N->getDebugLoc(); 11943 11944 // If the flag operand isn't dead, don't touch this CMOV. 11945 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 11946 return SDValue(); 11947 11948 SDValue FalseOp = N->getOperand(0); 11949 SDValue TrueOp = N->getOperand(1); 11950 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 11951 SDValue Cond = N->getOperand(3); 11952 if (CC == X86::COND_E || CC == X86::COND_NE) { 11953 switch (Cond.getOpcode()) { 11954 default: break; 11955 case X86ISD::BSR: 11956 case X86ISD::BSF: 11957 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 11958 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 11959 return (CC == X86::COND_E) ? FalseOp : TrueOp; 11960 } 11961 } 11962 11963 // If this is a select between two integer constants, try to do some 11964 // optimizations. Note that the operands are ordered the opposite of SELECT 11965 // operands. 11966 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 11967 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 11968 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 11969 // larger than FalseC (the false value). 11970 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 11971 CC = X86::GetOppositeBranchCondition(CC); 11972 std::swap(TrueC, FalseC); 11973 } 11974 11975 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 11976 // This is efficient for any integer data type (including i8/i16) and 11977 // shift amount. 11978 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 11979 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11980 DAG.getConstant(CC, MVT::i8), Cond); 11981 11982 // Zero extend the condition if needed. 11983 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 11984 11985 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 11986 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 11987 DAG.getConstant(ShAmt, MVT::i8)); 11988 if (N->getNumValues() == 2) // Dead flag value? 11989 return DCI.CombineTo(N, Cond, SDValue()); 11990 return Cond; 11991 } 11992 11993 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 11994 // for any integer data type, including i8/i16. 11995 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 11996 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11997 DAG.getConstant(CC, MVT::i8), Cond); 11998 11999 // Zero extend the condition if needed. 12000 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12001 FalseC->getValueType(0), Cond); 12002 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12003 SDValue(FalseC, 0)); 12004 12005 if (N->getNumValues() == 2) // Dead flag value? 12006 return DCI.CombineTo(N, Cond, SDValue()); 12007 return Cond; 12008 } 12009 12010 // Optimize cases that will turn into an LEA instruction. This requires 12011 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12012 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12013 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12014 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12015 12016 bool isFastMultiplier = false; 12017 if (Diff < 10) { 12018 switch ((unsigned char)Diff) { 12019 default: break; 12020 case 1: // result = add base, cond 12021 case 2: // result = lea base( , cond*2) 12022 case 3: // result = lea base(cond, cond*2) 12023 case 4: // result = lea base( , cond*4) 12024 case 5: // result = lea base(cond, cond*4) 12025 case 8: // result = lea base( , cond*8) 12026 case 9: // result = lea base(cond, cond*8) 12027 isFastMultiplier = true; 12028 break; 12029 } 12030 } 12031 12032 if (isFastMultiplier) { 12033 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12034 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12035 DAG.getConstant(CC, MVT::i8), Cond); 12036 // Zero extend the condition if needed. 12037 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12038 Cond); 12039 // Scale the condition by the difference. 12040 if (Diff != 1) 12041 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12042 DAG.getConstant(Diff, Cond.getValueType())); 12043 12044 // Add the base if non-zero. 12045 if (FalseC->getAPIntValue() != 0) 12046 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12047 SDValue(FalseC, 0)); 12048 if (N->getNumValues() == 2) // Dead flag value? 12049 return DCI.CombineTo(N, Cond, SDValue()); 12050 return Cond; 12051 } 12052 } 12053 } 12054 } 12055 return SDValue(); 12056} 12057 12058 12059/// PerformMulCombine - Optimize a single multiply with constant into two 12060/// in order to implement it with two cheaper instructions, e.g. 12061/// LEA + SHL, LEA + LEA. 12062static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 12063 TargetLowering::DAGCombinerInfo &DCI) { 12064 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 12065 return SDValue(); 12066 12067 EVT VT = N->getValueType(0); 12068 if (VT != MVT::i64) 12069 return SDValue(); 12070 12071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 12072 if (!C) 12073 return SDValue(); 12074 uint64_t MulAmt = C->getZExtValue(); 12075 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 12076 return SDValue(); 12077 12078 uint64_t MulAmt1 = 0; 12079 uint64_t MulAmt2 = 0; 12080 if ((MulAmt % 9) == 0) { 12081 MulAmt1 = 9; 12082 MulAmt2 = MulAmt / 9; 12083 } else if ((MulAmt % 5) == 0) { 12084 MulAmt1 = 5; 12085 MulAmt2 = MulAmt / 5; 12086 } else if ((MulAmt % 3) == 0) { 12087 MulAmt1 = 3; 12088 MulAmt2 = MulAmt / 3; 12089 } 12090 if (MulAmt2 && 12091 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 12092 DebugLoc DL = N->getDebugLoc(); 12093 12094 if (isPowerOf2_64(MulAmt2) && 12095 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 12096 // If second multiplifer is pow2, issue it first. We want the multiply by 12097 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 12098 // is an add. 12099 std::swap(MulAmt1, MulAmt2); 12100 12101 SDValue NewMul; 12102 if (isPowerOf2_64(MulAmt1)) 12103 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 12104 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 12105 else 12106 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 12107 DAG.getConstant(MulAmt1, VT)); 12108 12109 if (isPowerOf2_64(MulAmt2)) 12110 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 12111 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 12112 else 12113 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 12114 DAG.getConstant(MulAmt2, VT)); 12115 12116 // Do not add new nodes to DAG combiner worklist. 12117 DCI.CombineTo(N, NewMul, false); 12118 } 12119 return SDValue(); 12120} 12121 12122static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 12123 SDValue N0 = N->getOperand(0); 12124 SDValue N1 = N->getOperand(1); 12125 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 12126 EVT VT = N0.getValueType(); 12127 12128 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 12129 // since the result of setcc_c is all zero's or all ones. 12130 if (N1C && N0.getOpcode() == ISD::AND && 12131 N0.getOperand(1).getOpcode() == ISD::Constant) { 12132 SDValue N00 = N0.getOperand(0); 12133 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 12134 ((N00.getOpcode() == ISD::ANY_EXTEND || 12135 N00.getOpcode() == ISD::ZERO_EXTEND) && 12136 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 12137 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 12138 APInt ShAmt = N1C->getAPIntValue(); 12139 Mask = Mask.shl(ShAmt); 12140 if (Mask != 0) 12141 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 12142 N00, DAG.getConstant(Mask, VT)); 12143 } 12144 } 12145 12146 return SDValue(); 12147} 12148 12149/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 12150/// when possible. 12151static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 12152 const X86Subtarget *Subtarget) { 12153 EVT VT = N->getValueType(0); 12154 if (!VT.isVector() && VT.isInteger() && 12155 N->getOpcode() == ISD::SHL) 12156 return PerformSHLCombine(N, DAG); 12157 12158 // On X86 with SSE2 support, we can transform this to a vector shift if 12159 // all elements are shifted by the same amount. We can't do this in legalize 12160 // because the a constant vector is typically transformed to a constant pool 12161 // so we have no knowledge of the shift amount. 12162 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 12163 return SDValue(); 12164 12165 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 12166 return SDValue(); 12167 12168 SDValue ShAmtOp = N->getOperand(1); 12169 EVT EltVT = VT.getVectorElementType(); 12170 DebugLoc DL = N->getDebugLoc(); 12171 SDValue BaseShAmt = SDValue(); 12172 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 12173 unsigned NumElts = VT.getVectorNumElements(); 12174 unsigned i = 0; 12175 for (; i != NumElts; ++i) { 12176 SDValue Arg = ShAmtOp.getOperand(i); 12177 if (Arg.getOpcode() == ISD::UNDEF) continue; 12178 BaseShAmt = Arg; 12179 break; 12180 } 12181 for (; i != NumElts; ++i) { 12182 SDValue Arg = ShAmtOp.getOperand(i); 12183 if (Arg.getOpcode() == ISD::UNDEF) continue; 12184 if (Arg != BaseShAmt) { 12185 return SDValue(); 12186 } 12187 } 12188 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 12189 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 12190 SDValue InVec = ShAmtOp.getOperand(0); 12191 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 12192 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 12193 unsigned i = 0; 12194 for (; i != NumElts; ++i) { 12195 SDValue Arg = InVec.getOperand(i); 12196 if (Arg.getOpcode() == ISD::UNDEF) continue; 12197 BaseShAmt = Arg; 12198 break; 12199 } 12200 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 12201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 12202 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 12203 if (C->getZExtValue() == SplatIdx) 12204 BaseShAmt = InVec.getOperand(1); 12205 } 12206 } 12207 if (BaseShAmt.getNode() == 0) 12208 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 12209 DAG.getIntPtrConstant(0)); 12210 } else 12211 return SDValue(); 12212 12213 // The shift amount is an i32. 12214 if (EltVT.bitsGT(MVT::i32)) 12215 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 12216 else if (EltVT.bitsLT(MVT::i32)) 12217 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 12218 12219 // The shift amount is identical so we can do a vector shift. 12220 SDValue ValOp = N->getOperand(0); 12221 switch (N->getOpcode()) { 12222 default: 12223 llvm_unreachable("Unknown shift opcode!"); 12224 break; 12225 case ISD::SHL: 12226 if (VT == MVT::v2i64) 12227 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12228 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 12229 ValOp, BaseShAmt); 12230 if (VT == MVT::v4i32) 12231 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12232 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 12233 ValOp, BaseShAmt); 12234 if (VT == MVT::v8i16) 12235 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12236 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 12237 ValOp, BaseShAmt); 12238 break; 12239 case ISD::SRA: 12240 if (VT == MVT::v4i32) 12241 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12242 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 12243 ValOp, BaseShAmt); 12244 if (VT == MVT::v8i16) 12245 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12246 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 12247 ValOp, BaseShAmt); 12248 break; 12249 case ISD::SRL: 12250 if (VT == MVT::v2i64) 12251 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12252 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 12253 ValOp, BaseShAmt); 12254 if (VT == MVT::v4i32) 12255 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12256 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 12257 ValOp, BaseShAmt); 12258 if (VT == MVT::v8i16) 12259 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12260 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 12261 ValOp, BaseShAmt); 12262 break; 12263 } 12264 return SDValue(); 12265} 12266 12267 12268// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 12269// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 12270// and friends. Likewise for OR -> CMPNEQSS. 12271static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 12272 TargetLowering::DAGCombinerInfo &DCI, 12273 const X86Subtarget *Subtarget) { 12274 unsigned opcode; 12275 12276 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 12277 // we're requiring SSE2 for both. 12278 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 12279 SDValue N0 = N->getOperand(0); 12280 SDValue N1 = N->getOperand(1); 12281 SDValue CMP0 = N0->getOperand(1); 12282 SDValue CMP1 = N1->getOperand(1); 12283 DebugLoc DL = N->getDebugLoc(); 12284 12285 // The SETCCs should both refer to the same CMP. 12286 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 12287 return SDValue(); 12288 12289 SDValue CMP00 = CMP0->getOperand(0); 12290 SDValue CMP01 = CMP0->getOperand(1); 12291 EVT VT = CMP00.getValueType(); 12292 12293 if (VT == MVT::f32 || VT == MVT::f64) { 12294 bool ExpectingFlags = false; 12295 // Check for any users that want flags: 12296 for (SDNode::use_iterator UI = N->use_begin(), 12297 UE = N->use_end(); 12298 !ExpectingFlags && UI != UE; ++UI) 12299 switch (UI->getOpcode()) { 12300 default: 12301 case ISD::BR_CC: 12302 case ISD::BRCOND: 12303 case ISD::SELECT: 12304 ExpectingFlags = true; 12305 break; 12306 case ISD::CopyToReg: 12307 case ISD::SIGN_EXTEND: 12308 case ISD::ZERO_EXTEND: 12309 case ISD::ANY_EXTEND: 12310 break; 12311 } 12312 12313 if (!ExpectingFlags) { 12314 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 12315 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 12316 12317 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 12318 X86::CondCode tmp = cc0; 12319 cc0 = cc1; 12320 cc1 = tmp; 12321 } 12322 12323 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 12324 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 12325 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 12326 X86ISD::NodeType NTOperator = is64BitFP ? 12327 X86ISD::FSETCCsd : X86ISD::FSETCCss; 12328 // FIXME: need symbolic constants for these magic numbers. 12329 // See X86ATTInstPrinter.cpp:printSSECC(). 12330 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 12331 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 12332 DAG.getConstant(x86cc, MVT::i8)); 12333 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 12334 OnesOrZeroesF); 12335 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 12336 DAG.getConstant(1, MVT::i32)); 12337 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 12338 return OneBitOfTruth; 12339 } 12340 } 12341 } 12342 } 12343 return SDValue(); 12344} 12345 12346/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 12347/// so it can be folded inside ANDNP. 12348static bool CanFoldXORWithAllOnes(const SDNode *N) { 12349 EVT VT = N->getValueType(0); 12350 12351 // Match direct AllOnes for 128 and 256-bit vectors 12352 if (ISD::isBuildVectorAllOnes(N)) 12353 return true; 12354 12355 // Look through a bit convert. 12356 if (N->getOpcode() == ISD::BITCAST) 12357 N = N->getOperand(0).getNode(); 12358 12359 // Sometimes the operand may come from a insert_subvector building a 256-bit 12360 // allones vector 12361 if (VT.getSizeInBits() == 256 && 12362 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 12363 SDValue V1 = N->getOperand(0); 12364 SDValue V2 = N->getOperand(1); 12365 12366 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 12367 V1.getOperand(0).getOpcode() == ISD::UNDEF && 12368 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 12369 ISD::isBuildVectorAllOnes(V2.getNode())) 12370 return true; 12371 } 12372 12373 return false; 12374} 12375 12376static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 12377 TargetLowering::DAGCombinerInfo &DCI, 12378 const X86Subtarget *Subtarget) { 12379 if (DCI.isBeforeLegalizeOps()) 12380 return SDValue(); 12381 12382 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 12383 if (R.getNode()) 12384 return R; 12385 12386 // Want to form ANDNP nodes: 12387 // 1) In the hopes of then easily combining them with OR and AND nodes 12388 // to form PBLEND/PSIGN. 12389 // 2) To match ANDN packed intrinsics 12390 EVT VT = N->getValueType(0); 12391 if (VT != MVT::v2i64 && VT != MVT::v4i64) 12392 return SDValue(); 12393 12394 SDValue N0 = N->getOperand(0); 12395 SDValue N1 = N->getOperand(1); 12396 DebugLoc DL = N->getDebugLoc(); 12397 12398 // Check LHS for vnot 12399 if (N0.getOpcode() == ISD::XOR && 12400 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 12401 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 12402 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 12403 12404 // Check RHS for vnot 12405 if (N1.getOpcode() == ISD::XOR && 12406 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 12407 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 12408 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 12409 12410 return SDValue(); 12411} 12412 12413static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 12414 TargetLowering::DAGCombinerInfo &DCI, 12415 const X86Subtarget *Subtarget) { 12416 if (DCI.isBeforeLegalizeOps()) 12417 return SDValue(); 12418 12419 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 12420 if (R.getNode()) 12421 return R; 12422 12423 EVT VT = N->getValueType(0); 12424 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 12425 return SDValue(); 12426 12427 SDValue N0 = N->getOperand(0); 12428 SDValue N1 = N->getOperand(1); 12429 12430 // look for psign/blend 12431 if (Subtarget->hasSSSE3()) { 12432 if (VT == MVT::v2i64) { 12433 // Canonicalize pandn to RHS 12434 if (N0.getOpcode() == X86ISD::ANDNP) 12435 std::swap(N0, N1); 12436 // or (and (m, x), (pandn m, y)) 12437 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 12438 SDValue Mask = N1.getOperand(0); 12439 SDValue X = N1.getOperand(1); 12440 SDValue Y; 12441 if (N0.getOperand(0) == Mask) 12442 Y = N0.getOperand(1); 12443 if (N0.getOperand(1) == Mask) 12444 Y = N0.getOperand(0); 12445 12446 // Check to see if the mask appeared in both the AND and ANDNP and 12447 if (!Y.getNode()) 12448 return SDValue(); 12449 12450 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 12451 if (Mask.getOpcode() != ISD::BITCAST || 12452 X.getOpcode() != ISD::BITCAST || 12453 Y.getOpcode() != ISD::BITCAST) 12454 return SDValue(); 12455 12456 // Look through mask bitcast. 12457 Mask = Mask.getOperand(0); 12458 EVT MaskVT = Mask.getValueType(); 12459 12460 // Validate that the Mask operand is a vector sra node. The sra node 12461 // will be an intrinsic. 12462 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 12463 return SDValue(); 12464 12465 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 12466 // there is no psrai.b 12467 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 12468 case Intrinsic::x86_sse2_psrai_w: 12469 case Intrinsic::x86_sse2_psrai_d: 12470 break; 12471 default: return SDValue(); 12472 } 12473 12474 // Check that the SRA is all signbits. 12475 SDValue SraC = Mask.getOperand(2); 12476 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 12477 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 12478 if ((SraAmt + 1) != EltBits) 12479 return SDValue(); 12480 12481 DebugLoc DL = N->getDebugLoc(); 12482 12483 // Now we know we at least have a plendvb with the mask val. See if 12484 // we can form a psignb/w/d. 12485 // psign = x.type == y.type == mask.type && y = sub(0, x); 12486 X = X.getOperand(0); 12487 Y = Y.getOperand(0); 12488 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 12489 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 12490 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 12491 unsigned Opc = 0; 12492 switch (EltBits) { 12493 case 8: Opc = X86ISD::PSIGNB; break; 12494 case 16: Opc = X86ISD::PSIGNW; break; 12495 case 32: Opc = X86ISD::PSIGND; break; 12496 default: break; 12497 } 12498 if (Opc) { 12499 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 12500 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 12501 } 12502 } 12503 // PBLENDVB only available on SSE 4.1 12504 if (!Subtarget->hasSSE41()) 12505 return SDValue(); 12506 12507 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 12508 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 12509 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 12510 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask); 12511 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 12512 } 12513 } 12514 } 12515 12516 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 12517 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 12518 std::swap(N0, N1); 12519 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 12520 return SDValue(); 12521 if (!N0.hasOneUse() || !N1.hasOneUse()) 12522 return SDValue(); 12523 12524 SDValue ShAmt0 = N0.getOperand(1); 12525 if (ShAmt0.getValueType() != MVT::i8) 12526 return SDValue(); 12527 SDValue ShAmt1 = N1.getOperand(1); 12528 if (ShAmt1.getValueType() != MVT::i8) 12529 return SDValue(); 12530 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 12531 ShAmt0 = ShAmt0.getOperand(0); 12532 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 12533 ShAmt1 = ShAmt1.getOperand(0); 12534 12535 DebugLoc DL = N->getDebugLoc(); 12536 unsigned Opc = X86ISD::SHLD; 12537 SDValue Op0 = N0.getOperand(0); 12538 SDValue Op1 = N1.getOperand(0); 12539 if (ShAmt0.getOpcode() == ISD::SUB) { 12540 Opc = X86ISD::SHRD; 12541 std::swap(Op0, Op1); 12542 std::swap(ShAmt0, ShAmt1); 12543 } 12544 12545 unsigned Bits = VT.getSizeInBits(); 12546 if (ShAmt1.getOpcode() == ISD::SUB) { 12547 SDValue Sum = ShAmt1.getOperand(0); 12548 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 12549 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 12550 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 12551 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 12552 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 12553 return DAG.getNode(Opc, DL, VT, 12554 Op0, Op1, 12555 DAG.getNode(ISD::TRUNCATE, DL, 12556 MVT::i8, ShAmt0)); 12557 } 12558 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 12559 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 12560 if (ShAmt0C && 12561 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 12562 return DAG.getNode(Opc, DL, VT, 12563 N0.getOperand(0), N1.getOperand(0), 12564 DAG.getNode(ISD::TRUNCATE, DL, 12565 MVT::i8, ShAmt0)); 12566 } 12567 12568 return SDValue(); 12569} 12570 12571/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 12572static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 12573 const X86Subtarget *Subtarget) { 12574 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 12575 // the FP state in cases where an emms may be missing. 12576 // A preferable solution to the general problem is to figure out the right 12577 // places to insert EMMS. This qualifies as a quick hack. 12578 12579 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 12580 StoreSDNode *St = cast<StoreSDNode>(N); 12581 EVT VT = St->getValue().getValueType(); 12582 if (VT.getSizeInBits() != 64) 12583 return SDValue(); 12584 12585 const Function *F = DAG.getMachineFunction().getFunction(); 12586 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 12587 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 12588 && Subtarget->hasSSE2(); 12589 if ((VT.isVector() || 12590 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 12591 isa<LoadSDNode>(St->getValue()) && 12592 !cast<LoadSDNode>(St->getValue())->isVolatile() && 12593 St->getChain().hasOneUse() && !St->isVolatile()) { 12594 SDNode* LdVal = St->getValue().getNode(); 12595 LoadSDNode *Ld = 0; 12596 int TokenFactorIndex = -1; 12597 SmallVector<SDValue, 8> Ops; 12598 SDNode* ChainVal = St->getChain().getNode(); 12599 // Must be a store of a load. We currently handle two cases: the load 12600 // is a direct child, and it's under an intervening TokenFactor. It is 12601 // possible to dig deeper under nested TokenFactors. 12602 if (ChainVal == LdVal) 12603 Ld = cast<LoadSDNode>(St->getChain()); 12604 else if (St->getValue().hasOneUse() && 12605 ChainVal->getOpcode() == ISD::TokenFactor) { 12606 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 12607 if (ChainVal->getOperand(i).getNode() == LdVal) { 12608 TokenFactorIndex = i; 12609 Ld = cast<LoadSDNode>(St->getValue()); 12610 } else 12611 Ops.push_back(ChainVal->getOperand(i)); 12612 } 12613 } 12614 12615 if (!Ld || !ISD::isNormalLoad(Ld)) 12616 return SDValue(); 12617 12618 // If this is not the MMX case, i.e. we are just turning i64 load/store 12619 // into f64 load/store, avoid the transformation if there are multiple 12620 // uses of the loaded value. 12621 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 12622 return SDValue(); 12623 12624 DebugLoc LdDL = Ld->getDebugLoc(); 12625 DebugLoc StDL = N->getDebugLoc(); 12626 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 12627 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 12628 // pair instead. 12629 if (Subtarget->is64Bit() || F64IsLegal) { 12630 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 12631 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 12632 Ld->getPointerInfo(), Ld->isVolatile(), 12633 Ld->isNonTemporal(), Ld->getAlignment()); 12634 SDValue NewChain = NewLd.getValue(1); 12635 if (TokenFactorIndex != -1) { 12636 Ops.push_back(NewChain); 12637 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 12638 Ops.size()); 12639 } 12640 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 12641 St->getPointerInfo(), 12642 St->isVolatile(), St->isNonTemporal(), 12643 St->getAlignment()); 12644 } 12645 12646 // Otherwise, lower to two pairs of 32-bit loads / stores. 12647 SDValue LoAddr = Ld->getBasePtr(); 12648 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 12649 DAG.getConstant(4, MVT::i32)); 12650 12651 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 12652 Ld->getPointerInfo(), 12653 Ld->isVolatile(), Ld->isNonTemporal(), 12654 Ld->getAlignment()); 12655 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 12656 Ld->getPointerInfo().getWithOffset(4), 12657 Ld->isVolatile(), Ld->isNonTemporal(), 12658 MinAlign(Ld->getAlignment(), 4)); 12659 12660 SDValue NewChain = LoLd.getValue(1); 12661 if (TokenFactorIndex != -1) { 12662 Ops.push_back(LoLd); 12663 Ops.push_back(HiLd); 12664 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 12665 Ops.size()); 12666 } 12667 12668 LoAddr = St->getBasePtr(); 12669 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 12670 DAG.getConstant(4, MVT::i32)); 12671 12672 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 12673 St->getPointerInfo(), 12674 St->isVolatile(), St->isNonTemporal(), 12675 St->getAlignment()); 12676 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 12677 St->getPointerInfo().getWithOffset(4), 12678 St->isVolatile(), 12679 St->isNonTemporal(), 12680 MinAlign(St->getAlignment(), 4)); 12681 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 12682 } 12683 return SDValue(); 12684} 12685 12686/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 12687/// X86ISD::FXOR nodes. 12688static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 12689 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 12690 // F[X]OR(0.0, x) -> x 12691 // F[X]OR(x, 0.0) -> x 12692 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 12693 if (C->getValueAPF().isPosZero()) 12694 return N->getOperand(1); 12695 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 12696 if (C->getValueAPF().isPosZero()) 12697 return N->getOperand(0); 12698 return SDValue(); 12699} 12700 12701/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 12702static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 12703 // FAND(0.0, x) -> 0.0 12704 // FAND(x, 0.0) -> 0.0 12705 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 12706 if (C->getValueAPF().isPosZero()) 12707 return N->getOperand(0); 12708 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 12709 if (C->getValueAPF().isPosZero()) 12710 return N->getOperand(1); 12711 return SDValue(); 12712} 12713 12714static SDValue PerformBTCombine(SDNode *N, 12715 SelectionDAG &DAG, 12716 TargetLowering::DAGCombinerInfo &DCI) { 12717 // BT ignores high bits in the bit index operand. 12718 SDValue Op1 = N->getOperand(1); 12719 if (Op1.hasOneUse()) { 12720 unsigned BitWidth = Op1.getValueSizeInBits(); 12721 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 12722 APInt KnownZero, KnownOne; 12723 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 12724 !DCI.isBeforeLegalizeOps()); 12725 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12726 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 12727 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 12728 DCI.CommitTargetLoweringOpt(TLO); 12729 } 12730 return SDValue(); 12731} 12732 12733static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 12734 SDValue Op = N->getOperand(0); 12735 if (Op.getOpcode() == ISD::BITCAST) 12736 Op = Op.getOperand(0); 12737 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 12738 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 12739 VT.getVectorElementType().getSizeInBits() == 12740 OpVT.getVectorElementType().getSizeInBits()) { 12741 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 12742 } 12743 return SDValue(); 12744} 12745 12746static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 12747 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 12748 // (and (i32 x86isd::setcc_carry), 1) 12749 // This eliminates the zext. This transformation is necessary because 12750 // ISD::SETCC is always legalized to i8. 12751 DebugLoc dl = N->getDebugLoc(); 12752 SDValue N0 = N->getOperand(0); 12753 EVT VT = N->getValueType(0); 12754 if (N0.getOpcode() == ISD::AND && 12755 N0.hasOneUse() && 12756 N0.getOperand(0).hasOneUse()) { 12757 SDValue N00 = N0.getOperand(0); 12758 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 12759 return SDValue(); 12760 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 12761 if (!C || C->getZExtValue() != 1) 12762 return SDValue(); 12763 return DAG.getNode(ISD::AND, dl, VT, 12764 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 12765 N00.getOperand(0), N00.getOperand(1)), 12766 DAG.getConstant(1, VT)); 12767 } 12768 12769 return SDValue(); 12770} 12771 12772// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 12773static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 12774 unsigned X86CC = N->getConstantOperandVal(0); 12775 SDValue EFLAG = N->getOperand(1); 12776 DebugLoc DL = N->getDebugLoc(); 12777 12778 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 12779 // a zext and produces an all-ones bit which is more useful than 0/1 in some 12780 // cases. 12781 if (X86CC == X86::COND_B) 12782 return DAG.getNode(ISD::AND, DL, MVT::i8, 12783 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 12784 DAG.getConstant(X86CC, MVT::i8), EFLAG), 12785 DAG.getConstant(1, MVT::i8)); 12786 12787 return SDValue(); 12788} 12789 12790static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 12791 const X86TargetLowering *XTLI) { 12792 SDValue Op0 = N->getOperand(0); 12793 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 12794 // a 32-bit target where SSE doesn't support i64->FP operations. 12795 if (Op0.getOpcode() == ISD::LOAD) { 12796 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 12797 EVT VT = Ld->getValueType(0); 12798 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 12799 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 12800 !XTLI->getSubtarget()->is64Bit() && 12801 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 12802 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 12803 Ld->getChain(), Op0, DAG); 12804 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 12805 return FILDChain; 12806 } 12807 } 12808 return SDValue(); 12809} 12810 12811// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 12812static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 12813 X86TargetLowering::DAGCombinerInfo &DCI) { 12814 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 12815 // the result is either zero or one (depending on the input carry bit). 12816 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 12817 if (X86::isZeroNode(N->getOperand(0)) && 12818 X86::isZeroNode(N->getOperand(1)) && 12819 // We don't have a good way to replace an EFLAGS use, so only do this when 12820 // dead right now. 12821 SDValue(N, 1).use_empty()) { 12822 DebugLoc DL = N->getDebugLoc(); 12823 EVT VT = N->getValueType(0); 12824 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 12825 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 12826 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 12827 DAG.getConstant(X86::COND_B,MVT::i8), 12828 N->getOperand(2)), 12829 DAG.getConstant(1, VT)); 12830 return DCI.CombineTo(N, Res1, CarryOut); 12831 } 12832 12833 return SDValue(); 12834} 12835 12836// fold (add Y, (sete X, 0)) -> adc 0, Y 12837// (add Y, (setne X, 0)) -> sbb -1, Y 12838// (sub (sete X, 0), Y) -> sbb 0, Y 12839// (sub (setne X, 0), Y) -> adc -1, Y 12840static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 12841 DebugLoc DL = N->getDebugLoc(); 12842 12843 // Look through ZExts. 12844 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 12845 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 12846 return SDValue(); 12847 12848 SDValue SetCC = Ext.getOperand(0); 12849 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 12850 return SDValue(); 12851 12852 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 12853 if (CC != X86::COND_E && CC != X86::COND_NE) 12854 return SDValue(); 12855 12856 SDValue Cmp = SetCC.getOperand(1); 12857 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 12858 !X86::isZeroNode(Cmp.getOperand(1)) || 12859 !Cmp.getOperand(0).getValueType().isInteger()) 12860 return SDValue(); 12861 12862 SDValue CmpOp0 = Cmp.getOperand(0); 12863 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 12864 DAG.getConstant(1, CmpOp0.getValueType())); 12865 12866 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 12867 if (CC == X86::COND_NE) 12868 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 12869 DL, OtherVal.getValueType(), OtherVal, 12870 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 12871 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 12872 DL, OtherVal.getValueType(), OtherVal, 12873 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 12874} 12875 12876static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 12877 SDValue Op0 = N->getOperand(0); 12878 SDValue Op1 = N->getOperand(1); 12879 12880 // X86 can't encode an immediate LHS of a sub. See if we can push the 12881 // negation into a preceding instruction. 12882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 12883 uint64_t Op0C = C->getSExtValue(); 12884 12885 // If the RHS of the sub is a XOR with one use and a constant, invert the 12886 // immediate. Then add one to the LHS of the sub so we can turn 12887 // X-Y -> X+~Y+1, saving one register. 12888 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 12889 isa<ConstantSDNode>(Op1.getOperand(1))) { 12890 uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue(); 12891 EVT VT = Op0.getValueType(); 12892 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 12893 Op1.getOperand(0), 12894 DAG.getConstant(~XorC, VT)); 12895 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 12896 DAG.getConstant(Op0C+1, VT)); 12897 } 12898 } 12899 12900 return OptimizeConditionalInDecrement(N, DAG); 12901} 12902 12903SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 12904 DAGCombinerInfo &DCI) const { 12905 SelectionDAG &DAG = DCI.DAG; 12906 switch (N->getOpcode()) { 12907 default: break; 12908 case ISD::EXTRACT_VECTOR_ELT: 12909 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 12910 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 12911 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 12912 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 12913 case ISD::SUB: return PerformSubCombine(N, DAG); 12914 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 12915 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 12916 case ISD::SHL: 12917 case ISD::SRA: 12918 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 12919 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 12920 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 12921 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 12922 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 12923 case X86ISD::FXOR: 12924 case X86ISD::FOR: return PerformFORCombine(N, DAG); 12925 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 12926 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 12927 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 12928 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 12929 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 12930 case X86ISD::SHUFPS: // Handle all target specific shuffles 12931 case X86ISD::SHUFPD: 12932 case X86ISD::PALIGN: 12933 case X86ISD::PUNPCKHBW: 12934 case X86ISD::PUNPCKHWD: 12935 case X86ISD::PUNPCKHDQ: 12936 case X86ISD::PUNPCKHQDQ: 12937 case X86ISD::UNPCKHPS: 12938 case X86ISD::UNPCKHPD: 12939 case X86ISD::VUNPCKHPSY: 12940 case X86ISD::VUNPCKHPDY: 12941 case X86ISD::PUNPCKLBW: 12942 case X86ISD::PUNPCKLWD: 12943 case X86ISD::PUNPCKLDQ: 12944 case X86ISD::PUNPCKLQDQ: 12945 case X86ISD::UNPCKLPS: 12946 case X86ISD::UNPCKLPD: 12947 case X86ISD::VUNPCKLPSY: 12948 case X86ISD::VUNPCKLPDY: 12949 case X86ISD::MOVHLPS: 12950 case X86ISD::MOVLHPS: 12951 case X86ISD::PSHUFD: 12952 case X86ISD::PSHUFHW: 12953 case X86ISD::PSHUFLW: 12954 case X86ISD::MOVSS: 12955 case X86ISD::MOVSD: 12956 case X86ISD::VPERMILPS: 12957 case X86ISD::VPERMILPSY: 12958 case X86ISD::VPERMILPD: 12959 case X86ISD::VPERMILPDY: 12960 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI); 12961 } 12962 12963 return SDValue(); 12964} 12965 12966/// isTypeDesirableForOp - Return true if the target has native support for 12967/// the specified value type and it is 'desirable' to use the type for the 12968/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 12969/// instruction encodings are longer and some i16 instructions are slow. 12970bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 12971 if (!isTypeLegal(VT)) 12972 return false; 12973 if (VT != MVT::i16) 12974 return true; 12975 12976 switch (Opc) { 12977 default: 12978 return true; 12979 case ISD::LOAD: 12980 case ISD::SIGN_EXTEND: 12981 case ISD::ZERO_EXTEND: 12982 case ISD::ANY_EXTEND: 12983 case ISD::SHL: 12984 case ISD::SRL: 12985 case ISD::SUB: 12986 case ISD::ADD: 12987 case ISD::MUL: 12988 case ISD::AND: 12989 case ISD::OR: 12990 case ISD::XOR: 12991 return false; 12992 } 12993} 12994 12995/// IsDesirableToPromoteOp - This method query the target whether it is 12996/// beneficial for dag combiner to promote the specified node. If true, it 12997/// should return the desired promotion type by reference. 12998bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 12999 EVT VT = Op.getValueType(); 13000 if (VT != MVT::i16) 13001 return false; 13002 13003 bool Promote = false; 13004 bool Commute = false; 13005 switch (Op.getOpcode()) { 13006 default: break; 13007 case ISD::LOAD: { 13008 LoadSDNode *LD = cast<LoadSDNode>(Op); 13009 // If the non-extending load has a single use and it's not live out, then it 13010 // might be folded. 13011 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 13012 Op.hasOneUse()*/) { 13013 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 13014 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 13015 // The only case where we'd want to promote LOAD (rather then it being 13016 // promoted as an operand is when it's only use is liveout. 13017 if (UI->getOpcode() != ISD::CopyToReg) 13018 return false; 13019 } 13020 } 13021 Promote = true; 13022 break; 13023 } 13024 case ISD::SIGN_EXTEND: 13025 case ISD::ZERO_EXTEND: 13026 case ISD::ANY_EXTEND: 13027 Promote = true; 13028 break; 13029 case ISD::SHL: 13030 case ISD::SRL: { 13031 SDValue N0 = Op.getOperand(0); 13032 // Look out for (store (shl (load), x)). 13033 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 13034 return false; 13035 Promote = true; 13036 break; 13037 } 13038 case ISD::ADD: 13039 case ISD::MUL: 13040 case ISD::AND: 13041 case ISD::OR: 13042 case ISD::XOR: 13043 Commute = true; 13044 // fallthrough 13045 case ISD::SUB: { 13046 SDValue N0 = Op.getOperand(0); 13047 SDValue N1 = Op.getOperand(1); 13048 if (!Commute && MayFoldLoad(N1)) 13049 return false; 13050 // Avoid disabling potential load folding opportunities. 13051 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 13052 return false; 13053 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 13054 return false; 13055 Promote = true; 13056 } 13057 } 13058 13059 PVT = MVT::i32; 13060 return Promote; 13061} 13062 13063//===----------------------------------------------------------------------===// 13064// X86 Inline Assembly Support 13065//===----------------------------------------------------------------------===// 13066 13067bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 13068 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 13069 13070 std::string AsmStr = IA->getAsmString(); 13071 13072 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 13073 SmallVector<StringRef, 4> AsmPieces; 13074 SplitString(AsmStr, AsmPieces, ";\n"); 13075 13076 switch (AsmPieces.size()) { 13077 default: return false; 13078 case 1: 13079 AsmStr = AsmPieces[0]; 13080 AsmPieces.clear(); 13081 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 13082 13083 // FIXME: this should verify that we are targeting a 486 or better. If not, 13084 // we will turn this bswap into something that will be lowered to logical ops 13085 // instead of emitting the bswap asm. For now, we don't support 486 or lower 13086 // so don't worry about this. 13087 // bswap $0 13088 if (AsmPieces.size() == 2 && 13089 (AsmPieces[0] == "bswap" || 13090 AsmPieces[0] == "bswapq" || 13091 AsmPieces[0] == "bswapl") && 13092 (AsmPieces[1] == "$0" || 13093 AsmPieces[1] == "${0:q}")) { 13094 // No need to check constraints, nothing other than the equivalent of 13095 // "=r,0" would be valid here. 13096 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13097 if (!Ty || Ty->getBitWidth() % 16 != 0) 13098 return false; 13099 return IntrinsicLowering::LowerToByteSwap(CI); 13100 } 13101 // rorw $$8, ${0:w} --> llvm.bswap.i16 13102 if (CI->getType()->isIntegerTy(16) && 13103 AsmPieces.size() == 3 && 13104 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 13105 AsmPieces[1] == "$$8," && 13106 AsmPieces[2] == "${0:w}" && 13107 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 13108 AsmPieces.clear(); 13109 const std::string &ConstraintsStr = IA->getConstraintString(); 13110 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 13111 std::sort(AsmPieces.begin(), AsmPieces.end()); 13112 if (AsmPieces.size() == 4 && 13113 AsmPieces[0] == "~{cc}" && 13114 AsmPieces[1] == "~{dirflag}" && 13115 AsmPieces[2] == "~{flags}" && 13116 AsmPieces[3] == "~{fpsr}") { 13117 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13118 if (!Ty || Ty->getBitWidth() % 16 != 0) 13119 return false; 13120 return IntrinsicLowering::LowerToByteSwap(CI); 13121 } 13122 } 13123 break; 13124 case 3: 13125 if (CI->getType()->isIntegerTy(32) && 13126 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 13127 SmallVector<StringRef, 4> Words; 13128 SplitString(AsmPieces[0], Words, " \t,"); 13129 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 13130 Words[2] == "${0:w}") { 13131 Words.clear(); 13132 SplitString(AsmPieces[1], Words, " \t,"); 13133 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 13134 Words[2] == "$0") { 13135 Words.clear(); 13136 SplitString(AsmPieces[2], Words, " \t,"); 13137 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 13138 Words[2] == "${0:w}") { 13139 AsmPieces.clear(); 13140 const std::string &ConstraintsStr = IA->getConstraintString(); 13141 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 13142 std::sort(AsmPieces.begin(), AsmPieces.end()); 13143 if (AsmPieces.size() == 4 && 13144 AsmPieces[0] == "~{cc}" && 13145 AsmPieces[1] == "~{dirflag}" && 13146 AsmPieces[2] == "~{flags}" && 13147 AsmPieces[3] == "~{fpsr}") { 13148 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13149 if (!Ty || Ty->getBitWidth() % 16 != 0) 13150 return false; 13151 return IntrinsicLowering::LowerToByteSwap(CI); 13152 } 13153 } 13154 } 13155 } 13156 } 13157 13158 if (CI->getType()->isIntegerTy(64)) { 13159 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 13160 if (Constraints.size() >= 2 && 13161 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 13162 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 13163 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 13164 SmallVector<StringRef, 4> Words; 13165 SplitString(AsmPieces[0], Words, " \t"); 13166 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 13167 Words.clear(); 13168 SplitString(AsmPieces[1], Words, " \t"); 13169 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 13170 Words.clear(); 13171 SplitString(AsmPieces[2], Words, " \t,"); 13172 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 13173 Words[2] == "%edx") { 13174 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13175 if (!Ty || Ty->getBitWidth() % 16 != 0) 13176 return false; 13177 return IntrinsicLowering::LowerToByteSwap(CI); 13178 } 13179 } 13180 } 13181 } 13182 } 13183 break; 13184 } 13185 return false; 13186} 13187 13188 13189 13190/// getConstraintType - Given a constraint letter, return the type of 13191/// constraint it is for this target. 13192X86TargetLowering::ConstraintType 13193X86TargetLowering::getConstraintType(const std::string &Constraint) const { 13194 if (Constraint.size() == 1) { 13195 switch (Constraint[0]) { 13196 case 'R': 13197 case 'q': 13198 case 'Q': 13199 case 'f': 13200 case 't': 13201 case 'u': 13202 case 'y': 13203 case 'x': 13204 case 'Y': 13205 case 'l': 13206 return C_RegisterClass; 13207 case 'a': 13208 case 'b': 13209 case 'c': 13210 case 'd': 13211 case 'S': 13212 case 'D': 13213 case 'A': 13214 return C_Register; 13215 case 'I': 13216 case 'J': 13217 case 'K': 13218 case 'L': 13219 case 'M': 13220 case 'N': 13221 case 'G': 13222 case 'C': 13223 case 'e': 13224 case 'Z': 13225 return C_Other; 13226 default: 13227 break; 13228 } 13229 } 13230 return TargetLowering::getConstraintType(Constraint); 13231} 13232 13233/// Examine constraint type and operand type and determine a weight value. 13234/// This object must already have been set up with the operand type 13235/// and the current alternative constraint selected. 13236TargetLowering::ConstraintWeight 13237 X86TargetLowering::getSingleConstraintMatchWeight( 13238 AsmOperandInfo &info, const char *constraint) const { 13239 ConstraintWeight weight = CW_Invalid; 13240 Value *CallOperandVal = info.CallOperandVal; 13241 // If we don't have a value, we can't do a match, 13242 // but allow it at the lowest weight. 13243 if (CallOperandVal == NULL) 13244 return CW_Default; 13245 Type *type = CallOperandVal->getType(); 13246 // Look at the constraint type. 13247 switch (*constraint) { 13248 default: 13249 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 13250 case 'R': 13251 case 'q': 13252 case 'Q': 13253 case 'a': 13254 case 'b': 13255 case 'c': 13256 case 'd': 13257 case 'S': 13258 case 'D': 13259 case 'A': 13260 if (CallOperandVal->getType()->isIntegerTy()) 13261 weight = CW_SpecificReg; 13262 break; 13263 case 'f': 13264 case 't': 13265 case 'u': 13266 if (type->isFloatingPointTy()) 13267 weight = CW_SpecificReg; 13268 break; 13269 case 'y': 13270 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 13271 weight = CW_SpecificReg; 13272 break; 13273 case 'x': 13274 case 'Y': 13275 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 13276 weight = CW_Register; 13277 break; 13278 case 'I': 13279 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 13280 if (C->getZExtValue() <= 31) 13281 weight = CW_Constant; 13282 } 13283 break; 13284 case 'J': 13285 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13286 if (C->getZExtValue() <= 63) 13287 weight = CW_Constant; 13288 } 13289 break; 13290 case 'K': 13291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13292 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 13293 weight = CW_Constant; 13294 } 13295 break; 13296 case 'L': 13297 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13298 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 13299 weight = CW_Constant; 13300 } 13301 break; 13302 case 'M': 13303 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13304 if (C->getZExtValue() <= 3) 13305 weight = CW_Constant; 13306 } 13307 break; 13308 case 'N': 13309 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13310 if (C->getZExtValue() <= 0xff) 13311 weight = CW_Constant; 13312 } 13313 break; 13314 case 'G': 13315 case 'C': 13316 if (dyn_cast<ConstantFP>(CallOperandVal)) { 13317 weight = CW_Constant; 13318 } 13319 break; 13320 case 'e': 13321 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13322 if ((C->getSExtValue() >= -0x80000000LL) && 13323 (C->getSExtValue() <= 0x7fffffffLL)) 13324 weight = CW_Constant; 13325 } 13326 break; 13327 case 'Z': 13328 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13329 if (C->getZExtValue() <= 0xffffffff) 13330 weight = CW_Constant; 13331 } 13332 break; 13333 } 13334 return weight; 13335} 13336 13337/// LowerXConstraint - try to replace an X constraint, which matches anything, 13338/// with another that has more specific requirements based on the type of the 13339/// corresponding operand. 13340const char *X86TargetLowering:: 13341LowerXConstraint(EVT ConstraintVT) const { 13342 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 13343 // 'f' like normal targets. 13344 if (ConstraintVT.isFloatingPoint()) { 13345 if (Subtarget->hasXMMInt()) 13346 return "Y"; 13347 if (Subtarget->hasXMM()) 13348 return "x"; 13349 } 13350 13351 return TargetLowering::LowerXConstraint(ConstraintVT); 13352} 13353 13354/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 13355/// vector. If it is invalid, don't add anything to Ops. 13356void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 13357 std::string &Constraint, 13358 std::vector<SDValue>&Ops, 13359 SelectionDAG &DAG) const { 13360 SDValue Result(0, 0); 13361 13362 // Only support length 1 constraints for now. 13363 if (Constraint.length() > 1) return; 13364 13365 char ConstraintLetter = Constraint[0]; 13366 switch (ConstraintLetter) { 13367 default: break; 13368 case 'I': 13369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13370 if (C->getZExtValue() <= 31) { 13371 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13372 break; 13373 } 13374 } 13375 return; 13376 case 'J': 13377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13378 if (C->getZExtValue() <= 63) { 13379 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13380 break; 13381 } 13382 } 13383 return; 13384 case 'K': 13385 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13386 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 13387 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13388 break; 13389 } 13390 } 13391 return; 13392 case 'N': 13393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13394 if (C->getZExtValue() <= 255) { 13395 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13396 break; 13397 } 13398 } 13399 return; 13400 case 'e': { 13401 // 32-bit signed value 13402 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13403 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 13404 C->getSExtValue())) { 13405 // Widen to 64 bits here to get it sign extended. 13406 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 13407 break; 13408 } 13409 // FIXME gcc accepts some relocatable values here too, but only in certain 13410 // memory models; it's complicated. 13411 } 13412 return; 13413 } 13414 case 'Z': { 13415 // 32-bit unsigned value 13416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13417 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 13418 C->getZExtValue())) { 13419 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13420 break; 13421 } 13422 } 13423 // FIXME gcc accepts some relocatable values here too, but only in certain 13424 // memory models; it's complicated. 13425 return; 13426 } 13427 case 'i': { 13428 // Literal immediates are always ok. 13429 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 13430 // Widen to 64 bits here to get it sign extended. 13431 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 13432 break; 13433 } 13434 13435 // In any sort of PIC mode addresses need to be computed at runtime by 13436 // adding in a register or some sort of table lookup. These can't 13437 // be used as immediates. 13438 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 13439 return; 13440 13441 // If we are in non-pic codegen mode, we allow the address of a global (with 13442 // an optional displacement) to be used with 'i'. 13443 GlobalAddressSDNode *GA = 0; 13444 int64_t Offset = 0; 13445 13446 // Match either (GA), (GA+C), (GA+C1+C2), etc. 13447 while (1) { 13448 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 13449 Offset += GA->getOffset(); 13450 break; 13451 } else if (Op.getOpcode() == ISD::ADD) { 13452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 13453 Offset += C->getZExtValue(); 13454 Op = Op.getOperand(0); 13455 continue; 13456 } 13457 } else if (Op.getOpcode() == ISD::SUB) { 13458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 13459 Offset += -C->getZExtValue(); 13460 Op = Op.getOperand(0); 13461 continue; 13462 } 13463 } 13464 13465 // Otherwise, this isn't something we can handle, reject it. 13466 return; 13467 } 13468 13469 const GlobalValue *GV = GA->getGlobal(); 13470 // If we require an extra load to get this address, as in PIC mode, we 13471 // can't accept it. 13472 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 13473 getTargetMachine()))) 13474 return; 13475 13476 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 13477 GA->getValueType(0), Offset); 13478 break; 13479 } 13480 } 13481 13482 if (Result.getNode()) { 13483 Ops.push_back(Result); 13484 return; 13485 } 13486 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 13487} 13488 13489std::pair<unsigned, const TargetRegisterClass*> 13490X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 13491 EVT VT) const { 13492 // First, see if this is a constraint that directly corresponds to an LLVM 13493 // register class. 13494 if (Constraint.size() == 1) { 13495 // GCC Constraint Letters 13496 switch (Constraint[0]) { 13497 default: break; 13498 // TODO: Slight differences here in allocation order and leaving 13499 // RIP in the class. Do they matter any more here than they do 13500 // in the normal allocation? 13501 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 13502 if (Subtarget->is64Bit()) { 13503 if (VT == MVT::i32 || VT == MVT::f32) 13504 return std::make_pair(0U, X86::GR32RegisterClass); 13505 else if (VT == MVT::i16) 13506 return std::make_pair(0U, X86::GR16RegisterClass); 13507 else if (VT == MVT::i8 || VT == MVT::i1) 13508 return std::make_pair(0U, X86::GR8RegisterClass); 13509 else if (VT == MVT::i64 || VT == MVT::f64) 13510 return std::make_pair(0U, X86::GR64RegisterClass); 13511 break; 13512 } 13513 // 32-bit fallthrough 13514 case 'Q': // Q_REGS 13515 if (VT == MVT::i32 || VT == MVT::f32) 13516 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 13517 else if (VT == MVT::i16) 13518 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 13519 else if (VT == MVT::i8 || VT == MVT::i1) 13520 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 13521 else if (VT == MVT::i64) 13522 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 13523 break; 13524 case 'r': // GENERAL_REGS 13525 case 'l': // INDEX_REGS 13526 if (VT == MVT::i8 || VT == MVT::i1) 13527 return std::make_pair(0U, X86::GR8RegisterClass); 13528 if (VT == MVT::i16) 13529 return std::make_pair(0U, X86::GR16RegisterClass); 13530 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 13531 return std::make_pair(0U, X86::GR32RegisterClass); 13532 return std::make_pair(0U, X86::GR64RegisterClass); 13533 case 'R': // LEGACY_REGS 13534 if (VT == MVT::i8 || VT == MVT::i1) 13535 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 13536 if (VT == MVT::i16) 13537 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 13538 if (VT == MVT::i32 || !Subtarget->is64Bit()) 13539 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 13540 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 13541 case 'f': // FP Stack registers. 13542 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 13543 // value to the correct fpstack register class. 13544 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 13545 return std::make_pair(0U, X86::RFP32RegisterClass); 13546 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 13547 return std::make_pair(0U, X86::RFP64RegisterClass); 13548 return std::make_pair(0U, X86::RFP80RegisterClass); 13549 case 'y': // MMX_REGS if MMX allowed. 13550 if (!Subtarget->hasMMX()) break; 13551 return std::make_pair(0U, X86::VR64RegisterClass); 13552 case 'Y': // SSE_REGS if SSE2 allowed 13553 if (!Subtarget->hasXMMInt()) break; 13554 // FALL THROUGH. 13555 case 'x': // SSE_REGS if SSE1 allowed 13556 if (!Subtarget->hasXMM()) break; 13557 13558 switch (VT.getSimpleVT().SimpleTy) { 13559 default: break; 13560 // Scalar SSE types. 13561 case MVT::f32: 13562 case MVT::i32: 13563 return std::make_pair(0U, X86::FR32RegisterClass); 13564 case MVT::f64: 13565 case MVT::i64: 13566 return std::make_pair(0U, X86::FR64RegisterClass); 13567 // Vector types. 13568 case MVT::v16i8: 13569 case MVT::v8i16: 13570 case MVT::v4i32: 13571 case MVT::v2i64: 13572 case MVT::v4f32: 13573 case MVT::v2f64: 13574 return std::make_pair(0U, X86::VR128RegisterClass); 13575 } 13576 break; 13577 } 13578 } 13579 13580 // Use the default implementation in TargetLowering to convert the register 13581 // constraint into a member of a register class. 13582 std::pair<unsigned, const TargetRegisterClass*> Res; 13583 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 13584 13585 // Not found as a standard register? 13586 if (Res.second == 0) { 13587 // Map st(0) -> st(7) -> ST0 13588 if (Constraint.size() == 7 && Constraint[0] == '{' && 13589 tolower(Constraint[1]) == 's' && 13590 tolower(Constraint[2]) == 't' && 13591 Constraint[3] == '(' && 13592 (Constraint[4] >= '0' && Constraint[4] <= '7') && 13593 Constraint[5] == ')' && 13594 Constraint[6] == '}') { 13595 13596 Res.first = X86::ST0+Constraint[4]-'0'; 13597 Res.second = X86::RFP80RegisterClass; 13598 return Res; 13599 } 13600 13601 // GCC allows "st(0)" to be called just plain "st". 13602 if (StringRef("{st}").equals_lower(Constraint)) { 13603 Res.first = X86::ST0; 13604 Res.second = X86::RFP80RegisterClass; 13605 return Res; 13606 } 13607 13608 // flags -> EFLAGS 13609 if (StringRef("{flags}").equals_lower(Constraint)) { 13610 Res.first = X86::EFLAGS; 13611 Res.second = X86::CCRRegisterClass; 13612 return Res; 13613 } 13614 13615 // 'A' means EAX + EDX. 13616 if (Constraint == "A") { 13617 Res.first = X86::EAX; 13618 Res.second = X86::GR32_ADRegisterClass; 13619 return Res; 13620 } 13621 return Res; 13622 } 13623 13624 // Otherwise, check to see if this is a register class of the wrong value 13625 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 13626 // turn into {ax},{dx}. 13627 if (Res.second->hasType(VT)) 13628 return Res; // Correct type already, nothing to do. 13629 13630 // All of the single-register GCC register classes map their values onto 13631 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 13632 // really want an 8-bit or 32-bit register, map to the appropriate register 13633 // class and return the appropriate register. 13634 if (Res.second == X86::GR16RegisterClass) { 13635 if (VT == MVT::i8) { 13636 unsigned DestReg = 0; 13637 switch (Res.first) { 13638 default: break; 13639 case X86::AX: DestReg = X86::AL; break; 13640 case X86::DX: DestReg = X86::DL; break; 13641 case X86::CX: DestReg = X86::CL; break; 13642 case X86::BX: DestReg = X86::BL; break; 13643 } 13644 if (DestReg) { 13645 Res.first = DestReg; 13646 Res.second = X86::GR8RegisterClass; 13647 } 13648 } else if (VT == MVT::i32) { 13649 unsigned DestReg = 0; 13650 switch (Res.first) { 13651 default: break; 13652 case X86::AX: DestReg = X86::EAX; break; 13653 case X86::DX: DestReg = X86::EDX; break; 13654 case X86::CX: DestReg = X86::ECX; break; 13655 case X86::BX: DestReg = X86::EBX; break; 13656 case X86::SI: DestReg = X86::ESI; break; 13657 case X86::DI: DestReg = X86::EDI; break; 13658 case X86::BP: DestReg = X86::EBP; break; 13659 case X86::SP: DestReg = X86::ESP; break; 13660 } 13661 if (DestReg) { 13662 Res.first = DestReg; 13663 Res.second = X86::GR32RegisterClass; 13664 } 13665 } else if (VT == MVT::i64) { 13666 unsigned DestReg = 0; 13667 switch (Res.first) { 13668 default: break; 13669 case X86::AX: DestReg = X86::RAX; break; 13670 case X86::DX: DestReg = X86::RDX; break; 13671 case X86::CX: DestReg = X86::RCX; break; 13672 case X86::BX: DestReg = X86::RBX; break; 13673 case X86::SI: DestReg = X86::RSI; break; 13674 case X86::DI: DestReg = X86::RDI; break; 13675 case X86::BP: DestReg = X86::RBP; break; 13676 case X86::SP: DestReg = X86::RSP; break; 13677 } 13678 if (DestReg) { 13679 Res.first = DestReg; 13680 Res.second = X86::GR64RegisterClass; 13681 } 13682 } 13683 } else if (Res.second == X86::FR32RegisterClass || 13684 Res.second == X86::FR64RegisterClass || 13685 Res.second == X86::VR128RegisterClass) { 13686 // Handle references to XMM physical registers that got mapped into the 13687 // wrong class. This can happen with constraints like {xmm0} where the 13688 // target independent register mapper will just pick the first match it can 13689 // find, ignoring the required type. 13690 if (VT == MVT::f32) 13691 Res.second = X86::FR32RegisterClass; 13692 else if (VT == MVT::f64) 13693 Res.second = X86::FR64RegisterClass; 13694 else if (X86::VR128RegisterClass->hasType(VT)) 13695 Res.second = X86::VR128RegisterClass; 13696 } 13697 13698 return Res; 13699} 13700