X86ISelLowering.cpp revision d6708eade079c30b0790789a00a8d737d84f52b7
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86TargetMachine.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/GlobalAlias.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Function.h" 25#include "llvm/Instructions.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/LLVMContext.h" 28#include "llvm/ADT/BitVector.h" 29#include "llvm/ADT/VectorExtras.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/PseudoSourceValue.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Target/TargetLoweringObjectFile.h" 40#include "llvm/Target/TargetOptions.h" 41#include "llvm/ADT/SmallSet.h" 42#include "llvm/ADT/StringExtras.h" 43#include "llvm/Support/CommandLine.h" 44#include "llvm/Support/raw_ostream.h" 45using namespace llvm; 46 47static cl::opt<bool> 48DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 49 50// Forward declarations. 51static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 52 SDValue V2); 53 54static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 55 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 56 default: llvm_unreachable("unknown subtarget type"); 57 case X86Subtarget::isDarwin: 58 return new TargetLoweringObjectFileMachO(); 59 case X86Subtarget::isELF: 60 return new TargetLoweringObjectFileELF(); 61 case X86Subtarget::isMingw: 62 case X86Subtarget::isCygwin: 63 case X86Subtarget::isWindows: 64 return new TargetLoweringObjectFileCOFF(); 65 } 66 67} 68 69X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 70 : TargetLowering(TM, createTLOF(TM)) { 71 Subtarget = &TM.getSubtarget<X86Subtarget>(); 72 X86ScalarSSEf64 = Subtarget->hasSSE2(); 73 X86ScalarSSEf32 = Subtarget->hasSSE1(); 74 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 75 76 RegInfo = TM.getRegisterInfo(); 77 TD = getTargetData(); 78 79 // Set up the TargetLowering object. 80 81 // X86 is weird, it always uses i8 for shift amounts and setcc results. 82 setShiftAmountType(MVT::i8); 83 setBooleanContents(ZeroOrOneBooleanContent); 84 setSchedulingPreference(SchedulingForRegPressure); 85 setStackPointerRegisterToSaveRestore(X86StackPtr); 86 87 if (Subtarget->isTargetDarwin()) { 88 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 89 setUseUnderscoreSetJmp(false); 90 setUseUnderscoreLongJmp(false); 91 } else if (Subtarget->isTargetMingw()) { 92 // MS runtime is weird: it exports _setjmp, but longjmp! 93 setUseUnderscoreSetJmp(true); 94 setUseUnderscoreLongJmp(false); 95 } else { 96 setUseUnderscoreSetJmp(true); 97 setUseUnderscoreLongJmp(true); 98 } 99 100 // Set up the register classes. 101 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 102 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 103 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 104 if (Subtarget->is64Bit()) 105 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 106 107 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 108 109 // We don't accept any truncstore of integer registers. 110 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 111 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 112 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 113 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 114 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 115 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 116 117 // SETOEQ and SETUNE require checking two conditions. 118 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 119 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 120 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 121 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 122 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 123 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 124 125 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 126 // operation. 127 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 128 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 129 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 130 131 if (Subtarget->is64Bit()) { 132 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 133 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 134 } else if (!UseSoftFloat) { 135 if (X86ScalarSSEf64) { 136 // We have an impenetrably clever algorithm for ui64->double only. 137 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 138 } 139 // We have an algorithm for SSE2, and we turn this into a 64-bit 140 // FILD for other targets. 141 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 142 } 143 144 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 145 // this operation. 146 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 147 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 148 149 if (!UseSoftFloat) { 150 // SSE has no i16 to fp conversion, only i32 151 if (X86ScalarSSEf32) { 152 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 153 // f32 and f64 cases are Legal, f80 case is not 154 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 155 } else { 156 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 157 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 158 } 159 } else { 160 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 161 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 162 } 163 164 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 165 // are Legal, f80 is custom lowered. 166 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 167 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 168 169 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 170 // this operation. 171 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 172 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 173 174 if (X86ScalarSSEf32) { 175 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 176 // f32 and f64 cases are Legal, f80 case is not 177 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 178 } else { 179 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 180 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 181 } 182 183 // Handle FP_TO_UINT by promoting the destination to a larger signed 184 // conversion. 185 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 186 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 187 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 188 189 if (Subtarget->is64Bit()) { 190 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 191 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 192 } else if (!UseSoftFloat) { 193 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 194 // Expand FP_TO_UINT into a select. 195 // FIXME: We would like to use a Custom expander here eventually to do 196 // the optimal thing for SSE vs. the default expansion in the legalizer. 197 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 198 else 199 // With SSE3 we can use fisttpll to convert to a signed i64; without 200 // SSE, we're stuck with a fistpll. 201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 202 } 203 204 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 205 if (!X86ScalarSSEf64) { 206 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 207 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 208 } 209 210 // Scalar integer divide and remainder are lowered to use operations that 211 // produce two results, to match the available instructions. This exposes 212 // the two-result form to trivial CSE, which is able to combine x/y and x%y 213 // into a single instruction. 214 // 215 // Scalar integer multiply-high is also lowered to use two-result 216 // operations, to match the available instructions. However, plain multiply 217 // (low) operations are left as Legal, as there are single-result 218 // instructions for this in x86. Using the two-result multiply instructions 219 // when both high and low results are needed must be arranged by dagcombine. 220 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 221 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 222 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 223 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 224 setOperationAction(ISD::SREM , MVT::i8 , Expand); 225 setOperationAction(ISD::UREM , MVT::i8 , Expand); 226 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 227 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 228 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 229 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 230 setOperationAction(ISD::SREM , MVT::i16 , Expand); 231 setOperationAction(ISD::UREM , MVT::i16 , Expand); 232 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 233 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 234 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 235 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 236 setOperationAction(ISD::SREM , MVT::i32 , Expand); 237 setOperationAction(ISD::UREM , MVT::i32 , Expand); 238 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 239 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 240 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 241 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 242 setOperationAction(ISD::SREM , MVT::i64 , Expand); 243 setOperationAction(ISD::UREM , MVT::i64 , Expand); 244 245 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 246 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 247 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 248 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 249 if (Subtarget->is64Bit()) 250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 252 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 254 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 255 setOperationAction(ISD::FREM , MVT::f32 , Expand); 256 setOperationAction(ISD::FREM , MVT::f64 , Expand); 257 setOperationAction(ISD::FREM , MVT::f80 , Expand); 258 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 259 260 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 261 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 262 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 263 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 264 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 265 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 266 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 267 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 268 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 269 if (Subtarget->is64Bit()) { 270 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 271 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 272 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 273 } 274 275 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 276 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 277 278 // These should be promoted to a larger select which is supported. 279 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 280 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 281 // X86 wants to expand cmov itself. 282 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 283 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 284 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 285 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 286 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 287 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 288 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 289 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 290 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 291 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 292 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 293 if (Subtarget->is64Bit()) { 294 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 295 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 296 } 297 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 298 299 // Darwin ABI issue. 300 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 301 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 302 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 303 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 304 if (Subtarget->is64Bit()) 305 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 306 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 307 if (Subtarget->is64Bit()) { 308 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 309 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 310 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 311 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 312 } 313 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 314 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 315 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 316 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 317 if (Subtarget->is64Bit()) { 318 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 319 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 320 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 321 } 322 323 if (Subtarget->hasSSE1()) 324 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 325 326 if (!Subtarget->hasSSE2()) 327 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 328 329 // Expand certain atomics 330 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 331 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 332 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 333 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 334 335 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 336 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 337 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 338 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 339 340 if (!Subtarget->is64Bit()) { 341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 347 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 348 } 349 350 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 351 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 352 // FIXME - use subtarget debug flags 353 if (!Subtarget->isTargetDarwin() && 354 !Subtarget->isTargetELF() && 355 !Subtarget->isTargetCygMing()) { 356 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 357 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 358 } 359 360 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 361 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 362 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 363 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 364 if (Subtarget->is64Bit()) { 365 setExceptionPointerRegister(X86::RAX); 366 setExceptionSelectorRegister(X86::RDX); 367 } else { 368 setExceptionPointerRegister(X86::EAX); 369 setExceptionSelectorRegister(X86::EDX); 370 } 371 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 372 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 373 374 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 375 376 setOperationAction(ISD::TRAP, MVT::Other, Legal); 377 378 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 379 setOperationAction(ISD::VASTART , MVT::Other, Custom); 380 setOperationAction(ISD::VAEND , MVT::Other, Expand); 381 if (Subtarget->is64Bit()) { 382 setOperationAction(ISD::VAARG , MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 384 } else { 385 setOperationAction(ISD::VAARG , MVT::Other, Expand); 386 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 387 } 388 389 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 390 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 391 if (Subtarget->is64Bit()) 392 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 393 if (Subtarget->isTargetCygMing()) 394 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 395 else 396 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 397 398 if (!UseSoftFloat && X86ScalarSSEf64) { 399 // f32 and f64 use SSE. 400 // Set up the FP register classes. 401 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 402 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 403 404 // Use ANDPD to simulate FABS. 405 setOperationAction(ISD::FABS , MVT::f64, Custom); 406 setOperationAction(ISD::FABS , MVT::f32, Custom); 407 408 // Use XORP to simulate FNEG. 409 setOperationAction(ISD::FNEG , MVT::f64, Custom); 410 setOperationAction(ISD::FNEG , MVT::f32, Custom); 411 412 // Use ANDPD and ORPD to simulate FCOPYSIGN. 413 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 414 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 415 416 // We don't support sin/cos/fmod 417 setOperationAction(ISD::FSIN , MVT::f64, Expand); 418 setOperationAction(ISD::FCOS , MVT::f64, Expand); 419 setOperationAction(ISD::FSIN , MVT::f32, Expand); 420 setOperationAction(ISD::FCOS , MVT::f32, Expand); 421 422 // Expand FP immediates into loads from the stack, except for the special 423 // cases we handle. 424 addLegalFPImmediate(APFloat(+0.0)); // xorpd 425 addLegalFPImmediate(APFloat(+0.0f)); // xorps 426 } else if (!UseSoftFloat && X86ScalarSSEf32) { 427 // Use SSE for f32, x87 for f64. 428 // Set up the FP register classes. 429 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 430 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 431 432 // Use ANDPS to simulate FABS. 433 setOperationAction(ISD::FABS , MVT::f32, Custom); 434 435 // Use XORP to simulate FNEG. 436 setOperationAction(ISD::FNEG , MVT::f32, Custom); 437 438 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 439 440 // Use ANDPS and ORPS to simulate FCOPYSIGN. 441 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 442 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 443 444 // We don't support sin/cos/fmod 445 setOperationAction(ISD::FSIN , MVT::f32, Expand); 446 setOperationAction(ISD::FCOS , MVT::f32, Expand); 447 448 // Special cases we handle for FP constants. 449 addLegalFPImmediate(APFloat(+0.0f)); // xorps 450 addLegalFPImmediate(APFloat(+0.0)); // FLD0 451 addLegalFPImmediate(APFloat(+1.0)); // FLD1 452 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 453 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 454 455 if (!UnsafeFPMath) { 456 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 457 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 458 } 459 } else if (!UseSoftFloat) { 460 // f32 and f64 in x87. 461 // Set up the FP register classes. 462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 463 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 464 465 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 466 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 467 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 468 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 469 470 if (!UnsafeFPMath) { 471 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 472 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 473 } 474 addLegalFPImmediate(APFloat(+0.0)); // FLD0 475 addLegalFPImmediate(APFloat(+1.0)); // FLD1 476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 478 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 479 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 480 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 481 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 482 } 483 484 // Long double always uses X87. 485 if (!UseSoftFloat) { 486 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 487 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 488 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 489 { 490 bool ignored; 491 APFloat TmpFlt(+0.0); 492 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 493 &ignored); 494 addLegalFPImmediate(TmpFlt); // FLD0 495 TmpFlt.changeSign(); 496 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 497 APFloat TmpFlt2(+1.0); 498 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 499 &ignored); 500 addLegalFPImmediate(TmpFlt2); // FLD1 501 TmpFlt2.changeSign(); 502 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 503 } 504 505 if (!UnsafeFPMath) { 506 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 507 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 508 } 509 } 510 511 // Always use a library call for pow. 512 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 513 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 514 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 515 516 setOperationAction(ISD::FLOG, MVT::f80, Expand); 517 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 518 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 519 setOperationAction(ISD::FEXP, MVT::f80, Expand); 520 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 521 522 // First set operation action for all vector types to either promote 523 // (for widening) or expand (for scalarization). Then we will selectively 524 // turn on ones that can be effectively codegen'd. 525 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 526 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 527 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 528 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 529 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 530 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 531 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 532 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 533 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 534 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 535 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 538 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 540 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 541 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 542 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 543 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 548 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 549 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 550 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 551 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 575 } 576 577 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 578 // with -msoft-float, disable use of MMX as well. 579 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 580 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 581 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 582 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 583 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 584 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 585 586 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 587 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 588 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 589 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 590 591 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 592 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 593 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 594 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 595 596 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 597 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 598 599 setOperationAction(ISD::AND, MVT::v8i8, Promote); 600 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 601 setOperationAction(ISD::AND, MVT::v4i16, Promote); 602 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 603 setOperationAction(ISD::AND, MVT::v2i32, Promote); 604 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 605 setOperationAction(ISD::AND, MVT::v1i64, Legal); 606 607 setOperationAction(ISD::OR, MVT::v8i8, Promote); 608 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 609 setOperationAction(ISD::OR, MVT::v4i16, Promote); 610 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 611 setOperationAction(ISD::OR, MVT::v2i32, Promote); 612 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 613 setOperationAction(ISD::OR, MVT::v1i64, Legal); 614 615 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 616 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 617 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 618 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 619 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 620 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 621 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 622 623 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 624 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 625 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 626 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 627 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 628 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 629 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 630 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 631 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 632 633 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 634 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 635 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 636 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 637 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 638 639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 643 644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 648 649 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 650 651 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 652 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 653 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 654 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 655 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 656 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 657 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 658 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 659 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 660 } 661 662 if (!UseSoftFloat && Subtarget->hasSSE1()) { 663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 664 665 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 677 } 678 679 if (!UseSoftFloat && Subtarget->hasSSE2()) { 680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 681 682 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 683 // registers cannot be used even for integer operations. 684 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 685 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 686 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 687 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 688 689 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 690 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 691 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 692 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 693 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 694 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 695 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 696 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 697 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 698 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 699 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 700 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 701 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 702 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 703 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 704 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 705 706 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 707 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 708 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 709 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 710 711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 712 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 714 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 716 717 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 718 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 719 EVT VT = (MVT::SimpleValueType)i; 720 // Do not attempt to custom lower non-power-of-2 vectors 721 if (!isPowerOf2_32(VT.getVectorNumElements())) 722 continue; 723 // Do not attempt to custom lower non-128-bit vectors 724 if (!VT.is128BitVector()) 725 continue; 726 setOperationAction(ISD::BUILD_VECTOR, 727 VT.getSimpleVT().SimpleTy, Custom); 728 setOperationAction(ISD::VECTOR_SHUFFLE, 729 VT.getSimpleVT().SimpleTy, Custom); 730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 731 VT.getSimpleVT().SimpleTy, Custom); 732 } 733 734 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 739 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 740 741 if (Subtarget->is64Bit()) { 742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 744 } 745 746 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 747 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 748 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 749 EVT VT = SVT; 750 751 // Do not attempt to promote non-128-bit vectors 752 if (!VT.is128BitVector()) { 753 continue; 754 } 755 setOperationAction(ISD::AND, SVT, Promote); 756 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 757 setOperationAction(ISD::OR, SVT, Promote); 758 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 759 setOperationAction(ISD::XOR, SVT, Promote); 760 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 761 setOperationAction(ISD::LOAD, SVT, Promote); 762 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 763 setOperationAction(ISD::SELECT, SVT, Promote); 764 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 765 } 766 767 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 768 769 // Custom lower v2i64 and v2f64 selects. 770 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 771 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 772 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 773 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 774 775 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 776 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 777 if (!DisableMMX && Subtarget->hasMMX()) { 778 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 779 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 780 } 781 } 782 783 if (Subtarget->hasSSE41()) { 784 // FIXME: Do we need to handle scalar-to-vector here? 785 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 786 787 // i8 and i16 vectors are custom , because the source register and source 788 // source memory operand types are not the same width. f32 vectors are 789 // custom since the immediate controlling the insert encodes additional 790 // information. 791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 793 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 794 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 795 796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 798 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 799 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 800 801 if (Subtarget->is64Bit()) { 802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 803 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 804 } 805 } 806 807 if (Subtarget->hasSSE42()) { 808 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 809 } 810 811 if (!UseSoftFloat && Subtarget->hasAVX()) { 812 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 813 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 814 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 815 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 816 817 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 818 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 819 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 820 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 821 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 822 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 823 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 824 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 825 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 826 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 827 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 828 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 829 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 830 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 831 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 832 833 // Operations to consider commented out -v16i16 v32i8 834 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 835 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 836 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 837 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 838 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 839 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 840 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 841 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 842 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 843 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 844 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 845 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 846 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 847 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 848 849 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 850 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 851 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 852 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 853 854 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 855 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 856 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 857 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 859 860 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 861 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 862 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 863 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 866 867#if 0 868 // Not sure we want to do this since there are no 256-bit integer 869 // operations in AVX 870 871 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 872 // This includes 256-bit vectors 873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 874 EVT VT = (MVT::SimpleValueType)i; 875 876 // Do not attempt to custom lower non-power-of-2 vectors 877 if (!isPowerOf2_32(VT.getVectorNumElements())) 878 continue; 879 880 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 881 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 883 } 884 885 if (Subtarget->is64Bit()) { 886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 888 } 889#endif 890 891#if 0 892 // Not sure we want to do this since there are no 256-bit integer 893 // operations in AVX 894 895 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 896 // Including 256-bit vectors 897 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 898 EVT VT = (MVT::SimpleValueType)i; 899 900 if (!VT.is256BitVector()) { 901 continue; 902 } 903 setOperationAction(ISD::AND, VT, Promote); 904 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 905 setOperationAction(ISD::OR, VT, Promote); 906 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 907 setOperationAction(ISD::XOR, VT, Promote); 908 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 909 setOperationAction(ISD::LOAD, VT, Promote); 910 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 911 setOperationAction(ISD::SELECT, VT, Promote); 912 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 913 } 914 915 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 916#endif 917 } 918 919 // We want to custom lower some of our intrinsics. 920 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 921 922 // Add/Sub/Mul with overflow operations are custom lowered. 923 setOperationAction(ISD::SADDO, MVT::i32, Custom); 924 setOperationAction(ISD::SADDO, MVT::i64, Custom); 925 setOperationAction(ISD::UADDO, MVT::i32, Custom); 926 setOperationAction(ISD::UADDO, MVT::i64, Custom); 927 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 928 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 929 setOperationAction(ISD::USUBO, MVT::i32, Custom); 930 setOperationAction(ISD::USUBO, MVT::i64, Custom); 931 setOperationAction(ISD::SMULO, MVT::i32, Custom); 932 setOperationAction(ISD::SMULO, MVT::i64, Custom); 933 934 if (!Subtarget->is64Bit()) { 935 // These libcalls are not available in 32-bit. 936 setLibcallName(RTLIB::SHL_I128, 0); 937 setLibcallName(RTLIB::SRL_I128, 0); 938 setLibcallName(RTLIB::SRA_I128, 0); 939 } 940 941 // We have target-specific dag combine patterns for the following nodes: 942 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 943 setTargetDAGCombine(ISD::BUILD_VECTOR); 944 setTargetDAGCombine(ISD::SELECT); 945 setTargetDAGCombine(ISD::SHL); 946 setTargetDAGCombine(ISD::SRA); 947 setTargetDAGCombine(ISD::SRL); 948 setTargetDAGCombine(ISD::STORE); 949 setTargetDAGCombine(ISD::MEMBARRIER); 950 if (Subtarget->is64Bit()) 951 setTargetDAGCombine(ISD::MUL); 952 953 computeRegisterProperties(); 954 955 // FIXME: These should be based on subtarget info. Plus, the values should 956 // be smaller when we are in optimizing for size mode. 957 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 958 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 959 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 960 allowUnalignedMemoryAccesses = true; // x86 supports it! 961 setPrefLoopAlignment(16); 962 benefitFromCodePlacementOpt = true; 963} 964 965 966MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 967 return MVT::i8; 968} 969 970 971/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 972/// the desired ByVal argument alignment. 973static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 974 if (MaxAlign == 16) 975 return; 976 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 977 if (VTy->getBitWidth() == 128) 978 MaxAlign = 16; 979 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 980 unsigned EltAlign = 0; 981 getMaxByValAlign(ATy->getElementType(), EltAlign); 982 if (EltAlign > MaxAlign) 983 MaxAlign = EltAlign; 984 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 985 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 986 unsigned EltAlign = 0; 987 getMaxByValAlign(STy->getElementType(i), EltAlign); 988 if (EltAlign > MaxAlign) 989 MaxAlign = EltAlign; 990 if (MaxAlign == 16) 991 break; 992 } 993 } 994 return; 995} 996 997/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 998/// function arguments in the caller parameter area. For X86, aggregates 999/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1000/// are at 4-byte boundaries. 1001unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1002 if (Subtarget->is64Bit()) { 1003 // Max of 8 and alignment of type. 1004 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1005 if (TyAlign > 8) 1006 return TyAlign; 1007 return 8; 1008 } 1009 1010 unsigned Align = 4; 1011 if (Subtarget->hasSSE1()) 1012 getMaxByValAlign(Ty, Align); 1013 return Align; 1014} 1015 1016/// getOptimalMemOpType - Returns the target specific optimal type for load 1017/// and store operations as a result of memset, memcpy, and memmove 1018/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1019/// determining it. 1020EVT 1021X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1022 bool isSrcConst, bool isSrcStr, 1023 SelectionDAG &DAG) const { 1024 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1025 // linux. This is because the stack realignment code can't handle certain 1026 // cases like PR2962. This should be removed when PR2962 is fixed. 1027 const Function *F = DAG.getMachineFunction().getFunction(); 1028 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1029 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1030 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1031 return MVT::v4i32; 1032 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1033 return MVT::v4f32; 1034 } 1035 if (Subtarget->is64Bit() && Size >= 8) 1036 return MVT::i64; 1037 return MVT::i32; 1038} 1039 1040/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1041/// jumptable. 1042SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1043 SelectionDAG &DAG) const { 1044 if (usesGlobalOffsetTable()) 1045 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1046 if (!Subtarget->is64Bit()) 1047 // This doesn't have DebugLoc associated with it, but is not really the 1048 // same as a Register. 1049 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1050 getPointerTy()); 1051 return Table; 1052} 1053 1054/// getFunctionAlignment - Return the Log2 alignment of this function. 1055unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1056 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4; 1057} 1058 1059//===----------------------------------------------------------------------===// 1060// Return Value Calling Convention Implementation 1061//===----------------------------------------------------------------------===// 1062 1063#include "X86GenCallingConv.inc" 1064 1065SDValue 1066X86TargetLowering::LowerReturn(SDValue Chain, 1067 unsigned CallConv, bool isVarArg, 1068 const SmallVectorImpl<ISD::OutputArg> &Outs, 1069 DebugLoc dl, SelectionDAG &DAG) { 1070 1071 SmallVector<CCValAssign, 16> RVLocs; 1072 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1073 RVLocs, *DAG.getContext()); 1074 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1075 1076 // If this is the first return lowered for this function, add the regs to the 1077 // liveout set for the function. 1078 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1079 for (unsigned i = 0; i != RVLocs.size(); ++i) 1080 if (RVLocs[i].isRegLoc()) 1081 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1082 } 1083 1084 SDValue Flag; 1085 1086 SmallVector<SDValue, 6> RetOps; 1087 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1088 // Operand #1 = Bytes To Pop 1089 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 1090 1091 // Copy the result values into the output registers. 1092 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1093 CCValAssign &VA = RVLocs[i]; 1094 assert(VA.isRegLoc() && "Can only return in registers!"); 1095 SDValue ValToCopy = Outs[i].Val; 1096 1097 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1098 // the RET instruction and handled by the FP Stackifier. 1099 if (VA.getLocReg() == X86::ST0 || 1100 VA.getLocReg() == X86::ST1) { 1101 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1102 // change the value to the FP stack register class. 1103 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1104 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1105 RetOps.push_back(ValToCopy); 1106 // Don't emit a copytoreg. 1107 continue; 1108 } 1109 1110 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1111 // which is returned in RAX / RDX. 1112 if (Subtarget->is64Bit()) { 1113 EVT ValVT = ValToCopy.getValueType(); 1114 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1115 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1116 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1117 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1118 } 1119 } 1120 1121 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1122 Flag = Chain.getValue(1); 1123 } 1124 1125 // The x86-64 ABI for returning structs by value requires that we copy 1126 // the sret argument into %rax for the return. We saved the argument into 1127 // a virtual register in the entry block, so now we copy the value out 1128 // and into %rax. 1129 if (Subtarget->is64Bit() && 1130 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1131 MachineFunction &MF = DAG.getMachineFunction(); 1132 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1133 unsigned Reg = FuncInfo->getSRetReturnReg(); 1134 if (!Reg) { 1135 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1136 FuncInfo->setSRetReturnReg(Reg); 1137 } 1138 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1139 1140 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1141 Flag = Chain.getValue(1); 1142 } 1143 1144 RetOps[0] = Chain; // Update chain. 1145 1146 // Add the flag if we have it. 1147 if (Flag.getNode()) 1148 RetOps.push_back(Flag); 1149 1150 return DAG.getNode(X86ISD::RET_FLAG, dl, 1151 MVT::Other, &RetOps[0], RetOps.size()); 1152} 1153 1154/// LowerCallResult - Lower the result values of a call into the 1155/// appropriate copies out of appropriate physical registers. 1156/// 1157SDValue 1158X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1159 unsigned CallConv, bool isVarArg, 1160 const SmallVectorImpl<ISD::InputArg> &Ins, 1161 DebugLoc dl, SelectionDAG &DAG, 1162 SmallVectorImpl<SDValue> &InVals) { 1163 1164 // Assign locations to each value returned by this call. 1165 SmallVector<CCValAssign, 16> RVLocs; 1166 bool Is64Bit = Subtarget->is64Bit(); 1167 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1168 RVLocs, *DAG.getContext()); 1169 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1170 1171 // Copy all of the result registers out of their specified physreg. 1172 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1173 CCValAssign &VA = RVLocs[i]; 1174 EVT CopyVT = VA.getValVT(); 1175 1176 // If this is x86-64, and we disabled SSE, we can't return FP values 1177 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1178 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1179 llvm_report_error("SSE register return with SSE disabled"); 1180 } 1181 1182 // If this is a call to a function that returns an fp value on the floating 1183 // point stack, but where we prefer to use the value in xmm registers, copy 1184 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1185 if ((VA.getLocReg() == X86::ST0 || 1186 VA.getLocReg() == X86::ST1) && 1187 isScalarFPTypeInSSEReg(VA.getValVT())) { 1188 CopyVT = MVT::f80; 1189 } 1190 1191 SDValue Val; 1192 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1193 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1194 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1195 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1196 MVT::v2i64, InFlag).getValue(1); 1197 Val = Chain.getValue(0); 1198 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1199 Val, DAG.getConstant(0, MVT::i64)); 1200 } else { 1201 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1202 MVT::i64, InFlag).getValue(1); 1203 Val = Chain.getValue(0); 1204 } 1205 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1206 } else { 1207 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1208 CopyVT, InFlag).getValue(1); 1209 Val = Chain.getValue(0); 1210 } 1211 InFlag = Chain.getValue(2); 1212 1213 if (CopyVT != VA.getValVT()) { 1214 // Round the F80 the right size, which also moves to the appropriate xmm 1215 // register. 1216 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1217 // This truncation won't change the value. 1218 DAG.getIntPtrConstant(1)); 1219 } 1220 1221 InVals.push_back(Val); 1222 } 1223 1224 return Chain; 1225} 1226 1227 1228//===----------------------------------------------------------------------===// 1229// C & StdCall & Fast Calling Convention implementation 1230//===----------------------------------------------------------------------===// 1231// StdCall calling convention seems to be standard for many Windows' API 1232// routines and around. It differs from C calling convention just a little: 1233// callee should clean up the stack, not caller. Symbols should be also 1234// decorated in some fancy way :) It doesn't support any vector arguments. 1235// For info on fast calling convention see Fast Calling Convention (tail call) 1236// implementation LowerX86_32FastCCCallTo. 1237 1238/// CallIsStructReturn - Determines whether a call uses struct return 1239/// semantics. 1240static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1241 if (Outs.empty()) 1242 return false; 1243 1244 return Outs[0].Flags.isSRet(); 1245} 1246 1247/// ArgsAreStructReturn - Determines whether a function uses struct 1248/// return semantics. 1249static bool 1250ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1251 if (Ins.empty()) 1252 return false; 1253 1254 return Ins[0].Flags.isSRet(); 1255} 1256 1257/// IsCalleePop - Determines whether the callee is required to pop its 1258/// own arguments. Callee pop is necessary to support tail calls. 1259bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) { 1260 if (IsVarArg) 1261 return false; 1262 1263 switch (CallingConv) { 1264 default: 1265 return false; 1266 case CallingConv::X86_StdCall: 1267 return !Subtarget->is64Bit(); 1268 case CallingConv::X86_FastCall: 1269 return !Subtarget->is64Bit(); 1270 case CallingConv::Fast: 1271 return PerformTailCallOpt; 1272 } 1273} 1274 1275/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1276/// given CallingConvention value. 1277CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { 1278 if (Subtarget->is64Bit()) { 1279 if (Subtarget->isTargetWin64()) 1280 return CC_X86_Win64_C; 1281 else 1282 return CC_X86_64_C; 1283 } 1284 1285 if (CC == CallingConv::X86_FastCall) 1286 return CC_X86_32_FastCall; 1287 else if (CC == CallingConv::Fast) 1288 return CC_X86_32_FastCC; 1289 else 1290 return CC_X86_32_C; 1291} 1292 1293/// NameDecorationForCallConv - Selects the appropriate decoration to 1294/// apply to a MachineFunction containing a given calling convention. 1295NameDecorationStyle 1296X86TargetLowering::NameDecorationForCallConv(unsigned CallConv) { 1297 if (CallConv == CallingConv::X86_FastCall) 1298 return FastCall; 1299 else if (CallConv == CallingConv::X86_StdCall) 1300 return StdCall; 1301 return None; 1302} 1303 1304 1305/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1306/// by "Src" to address "Dst" with size and alignment information specified by 1307/// the specific parameter attribute. The copy will be passed as a byval 1308/// function parameter. 1309static SDValue 1310CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1311 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1312 DebugLoc dl) { 1313 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1314 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1315 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1316} 1317 1318SDValue 1319X86TargetLowering::LowerMemArgument(SDValue Chain, 1320 unsigned CallConv, 1321 const SmallVectorImpl<ISD::InputArg> &Ins, 1322 DebugLoc dl, SelectionDAG &DAG, 1323 const CCValAssign &VA, 1324 MachineFrameInfo *MFI, 1325 unsigned i) { 1326 1327 // Create the nodes corresponding to a load from this parameter slot. 1328 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1329 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt; 1330 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1331 EVT ValVT; 1332 1333 // If value is passed by pointer we have address passed instead of the value 1334 // itself. 1335 if (VA.getLocInfo() == CCValAssign::Indirect) 1336 ValVT = VA.getLocVT(); 1337 else 1338 ValVT = VA.getValVT(); 1339 1340 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1341 // changed with more analysis. 1342 // In case of tail call optimization mark all arguments mutable. Since they 1343 // could be overwritten by lowering of arguments in case of a tail call. 1344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1345 VA.getLocMemOffset(), isImmutable); 1346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1347 if (Flags.isByVal()) 1348 return FIN; 1349 return DAG.getLoad(ValVT, dl, Chain, FIN, 1350 PseudoSourceValue::getFixedStack(FI), 0); 1351} 1352 1353SDValue 1354X86TargetLowering::LowerFormalArguments(SDValue Chain, 1355 unsigned CallConv, 1356 bool isVarArg, 1357 const SmallVectorImpl<ISD::InputArg> &Ins, 1358 DebugLoc dl, 1359 SelectionDAG &DAG, 1360 SmallVectorImpl<SDValue> &InVals) { 1361 1362 MachineFunction &MF = DAG.getMachineFunction(); 1363 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1364 1365 const Function* Fn = MF.getFunction(); 1366 if (Fn->hasExternalLinkage() && 1367 Subtarget->isTargetCygMing() && 1368 Fn->getName() == "main") 1369 FuncInfo->setForceFramePointer(true); 1370 1371 // Decorate the function name. 1372 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv)); 1373 1374 MachineFrameInfo *MFI = MF.getFrameInfo(); 1375 bool Is64Bit = Subtarget->is64Bit(); 1376 bool IsWin64 = Subtarget->isTargetWin64(); 1377 1378 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1379 "Var args not supported with calling convention fastcc"); 1380 1381 // Assign locations to all of the incoming arguments. 1382 SmallVector<CCValAssign, 16> ArgLocs; 1383 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1384 ArgLocs, *DAG.getContext()); 1385 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1386 1387 unsigned LastVal = ~0U; 1388 SDValue ArgValue; 1389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1390 CCValAssign &VA = ArgLocs[i]; 1391 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1392 // places. 1393 assert(VA.getValNo() != LastVal && 1394 "Don't support value assigned to multiple locs yet"); 1395 LastVal = VA.getValNo(); 1396 1397 if (VA.isRegLoc()) { 1398 EVT RegVT = VA.getLocVT(); 1399 TargetRegisterClass *RC = NULL; 1400 if (RegVT == MVT::i32) 1401 RC = X86::GR32RegisterClass; 1402 else if (Is64Bit && RegVT == MVT::i64) 1403 RC = X86::GR64RegisterClass; 1404 else if (RegVT == MVT::f32) 1405 RC = X86::FR32RegisterClass; 1406 else if (RegVT == MVT::f64) 1407 RC = X86::FR64RegisterClass; 1408 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1409 RC = X86::VR128RegisterClass; 1410 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1411 RC = X86::VR64RegisterClass; 1412 else 1413 llvm_unreachable("Unknown argument type!"); 1414 1415 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1416 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1417 1418 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1419 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1420 // right size. 1421 if (VA.getLocInfo() == CCValAssign::SExt) 1422 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1423 DAG.getValueType(VA.getValVT())); 1424 else if (VA.getLocInfo() == CCValAssign::ZExt) 1425 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1426 DAG.getValueType(VA.getValVT())); 1427 else if (VA.getLocInfo() == CCValAssign::BCvt) 1428 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1429 1430 if (VA.isExtInLoc()) { 1431 // Handle MMX values passed in XMM regs. 1432 if (RegVT.isVector()) { 1433 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1434 ArgValue, DAG.getConstant(0, MVT::i64)); 1435 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1436 } else 1437 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1438 } 1439 } else { 1440 assert(VA.isMemLoc()); 1441 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1442 } 1443 1444 // If value is passed via pointer - do a load. 1445 if (VA.getLocInfo() == CCValAssign::Indirect) 1446 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0); 1447 1448 InVals.push_back(ArgValue); 1449 } 1450 1451 // The x86-64 ABI for returning structs by value requires that we copy 1452 // the sret argument into %rax for the return. Save the argument into 1453 // a virtual register so that we can access it from the return points. 1454 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1455 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1456 unsigned Reg = FuncInfo->getSRetReturnReg(); 1457 if (!Reg) { 1458 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1459 FuncInfo->setSRetReturnReg(Reg); 1460 } 1461 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1462 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1463 } 1464 1465 unsigned StackSize = CCInfo.getNextStackOffset(); 1466 // align stack specially for tail calls 1467 if (PerformTailCallOpt && CallConv == CallingConv::Fast) 1468 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1469 1470 // If the function takes variable number of arguments, make a frame index for 1471 // the start of the first vararg value... for expansion of llvm.va_start. 1472 if (isVarArg) { 1473 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1474 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1475 } 1476 if (Is64Bit) { 1477 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1478 1479 // FIXME: We should really autogenerate these arrays 1480 static const unsigned GPR64ArgRegsWin64[] = { 1481 X86::RCX, X86::RDX, X86::R8, X86::R9 1482 }; 1483 static const unsigned XMMArgRegsWin64[] = { 1484 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1485 }; 1486 static const unsigned GPR64ArgRegs64Bit[] = { 1487 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1488 }; 1489 static const unsigned XMMArgRegs64Bit[] = { 1490 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1491 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1492 }; 1493 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1494 1495 if (IsWin64) { 1496 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1497 GPR64ArgRegs = GPR64ArgRegsWin64; 1498 XMMArgRegs = XMMArgRegsWin64; 1499 } else { 1500 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1501 GPR64ArgRegs = GPR64ArgRegs64Bit; 1502 XMMArgRegs = XMMArgRegs64Bit; 1503 } 1504 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1505 TotalNumIntRegs); 1506 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1507 TotalNumXMMRegs); 1508 1509 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1510 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1511 "SSE register cannot be used when SSE is disabled!"); 1512 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1513 "SSE register cannot be used when SSE is disabled!"); 1514 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1515 // Kernel mode asks for SSE to be disabled, so don't push them 1516 // on the stack. 1517 TotalNumXMMRegs = 0; 1518 1519 // For X86-64, if there are vararg parameters that are passed via 1520 // registers, then we must store them to their spots on the stack so they 1521 // may be loaded by deferencing the result of va_next. 1522 VarArgsGPOffset = NumIntRegs * 8; 1523 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1524 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1525 TotalNumXMMRegs * 16, 16); 1526 1527 // Store the integer parameter registers. 1528 SmallVector<SDValue, 8> MemOps; 1529 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1530 unsigned Offset = VarArgsGPOffset; 1531 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1532 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1533 DAG.getIntPtrConstant(Offset)); 1534 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1535 X86::GR64RegisterClass); 1536 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1537 SDValue Store = 1538 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1539 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1540 Offset); 1541 MemOps.push_back(Store); 1542 Offset += 8; 1543 } 1544 1545 if (!MemOps.empty()) 1546 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1547 &MemOps[0], MemOps.size()); 1548 1549 // Now store the XMM (fp + vector) parameter registers. 1550 SmallVector<SDValue, 11> SaveXMMOps; 1551 SaveXMMOps.push_back(Chain); 1552 1553 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1554 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1555 SaveXMMOps.push_back(ALVal); 1556 1557 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1558 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1559 1560 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1561 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1562 X86::VR128RegisterClass); 1563 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1564 SaveXMMOps.push_back(Val); 1565 } 1566 Chain = DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, MVT::Other, 1567 &SaveXMMOps[0], SaveXMMOps.size()); 1568 } 1569 } 1570 1571 // Some CCs need callee pop. 1572 if (IsCalleePop(isVarArg, CallConv)) { 1573 BytesToPopOnReturn = StackSize; // Callee pops everything. 1574 BytesCallerReserves = 0; 1575 } else { 1576 BytesToPopOnReturn = 0; // Callee pops nothing. 1577 // If this is an sret function, the return should pop the hidden pointer. 1578 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins)) 1579 BytesToPopOnReturn = 4; 1580 BytesCallerReserves = StackSize; 1581 } 1582 1583 if (!Is64Bit) { 1584 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1585 if (CallConv == CallingConv::X86_FastCall) 1586 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1587 } 1588 1589 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1590 1591 return Chain; 1592} 1593 1594SDValue 1595X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1596 SDValue StackPtr, SDValue Arg, 1597 DebugLoc dl, SelectionDAG &DAG, 1598 const CCValAssign &VA, 1599 ISD::ArgFlagsTy Flags) { 1600 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1601 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1602 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1603 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1604 if (Flags.isByVal()) { 1605 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1606 } 1607 return DAG.getStore(Chain, dl, Arg, PtrOff, 1608 PseudoSourceValue::getStack(), LocMemOffset); 1609} 1610 1611/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1612/// optimization is performed and it is required. 1613SDValue 1614X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1615 SDValue &OutRetAddr, 1616 SDValue Chain, 1617 bool IsTailCall, 1618 bool Is64Bit, 1619 int FPDiff, 1620 DebugLoc dl) { 1621 if (!IsTailCall || FPDiff==0) return Chain; 1622 1623 // Adjust the Return address stack slot. 1624 EVT VT = getPointerTy(); 1625 OutRetAddr = getReturnAddressFrameIndex(DAG); 1626 1627 // Load the "old" Return address. 1628 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0); 1629 return SDValue(OutRetAddr.getNode(), 1); 1630} 1631 1632/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1633/// optimization is performed and it is required (FPDiff!=0). 1634static SDValue 1635EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1636 SDValue Chain, SDValue RetAddrFrIdx, 1637 bool Is64Bit, int FPDiff, DebugLoc dl) { 1638 // Store the return address to the appropriate stack slot. 1639 if (!FPDiff) return Chain; 1640 // Calculate the new stack slot for the return address. 1641 int SlotSize = Is64Bit ? 8 : 4; 1642 int NewReturnAddrFI = 1643 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1644 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1645 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1646 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1647 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1648 return Chain; 1649} 1650 1651SDValue 1652X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1653 unsigned CallConv, bool isVarArg, bool isTailCall, 1654 const SmallVectorImpl<ISD::OutputArg> &Outs, 1655 const SmallVectorImpl<ISD::InputArg> &Ins, 1656 DebugLoc dl, SelectionDAG &DAG, 1657 SmallVectorImpl<SDValue> &InVals) { 1658 1659 MachineFunction &MF = DAG.getMachineFunction(); 1660 bool Is64Bit = Subtarget->is64Bit(); 1661 bool IsStructRet = CallIsStructReturn(Outs); 1662 1663 assert((!isTailCall || 1664 (CallConv == CallingConv::Fast && PerformTailCallOpt)) && 1665 "IsEligibleForTailCallOptimization missed a case!"); 1666 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1667 "Var args not supported with calling convention fastcc"); 1668 1669 // Analyze operands of the call, assigning locations to each operand. 1670 SmallVector<CCValAssign, 16> ArgLocs; 1671 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1672 ArgLocs, *DAG.getContext()); 1673 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1674 1675 // Get a count of how many bytes are to be pushed on the stack. 1676 unsigned NumBytes = CCInfo.getNextStackOffset(); 1677 if (PerformTailCallOpt && CallConv == CallingConv::Fast) 1678 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1679 1680 int FPDiff = 0; 1681 if (isTailCall) { 1682 // Lower arguments at fp - stackoffset + fpdiff. 1683 unsigned NumBytesCallerPushed = 1684 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1685 FPDiff = NumBytesCallerPushed - NumBytes; 1686 1687 // Set the delta of movement of the returnaddr stackslot. 1688 // But only set if delta is greater than previous delta. 1689 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1690 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1691 } 1692 1693 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1694 1695 SDValue RetAddrFrIdx; 1696 // Load return adress for tail calls. 1697 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit, 1698 FPDiff, dl); 1699 1700 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1701 SmallVector<SDValue, 8> MemOpChains; 1702 SDValue StackPtr; 1703 1704 // Walk the register/memloc assignments, inserting copies/loads. In the case 1705 // of tail call optimization arguments are handle later. 1706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1707 CCValAssign &VA = ArgLocs[i]; 1708 EVT RegVT = VA.getLocVT(); 1709 SDValue Arg = Outs[i].Val; 1710 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1711 bool isByVal = Flags.isByVal(); 1712 1713 // Promote the value if needed. 1714 switch (VA.getLocInfo()) { 1715 default: llvm_unreachable("Unknown loc info!"); 1716 case CCValAssign::Full: break; 1717 case CCValAssign::SExt: 1718 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1719 break; 1720 case CCValAssign::ZExt: 1721 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1722 break; 1723 case CCValAssign::AExt: 1724 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1725 // Special case: passing MMX values in XMM registers. 1726 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1727 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1728 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1729 } else 1730 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1731 break; 1732 case CCValAssign::BCvt: 1733 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1734 break; 1735 case CCValAssign::Indirect: { 1736 // Store the argument. 1737 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1738 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1739 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1740 PseudoSourceValue::getFixedStack(FI), 0); 1741 Arg = SpillSlot; 1742 break; 1743 } 1744 } 1745 1746 if (VA.isRegLoc()) { 1747 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1748 } else { 1749 if (!isTailCall || (isTailCall && isByVal)) { 1750 assert(VA.isMemLoc()); 1751 if (StackPtr.getNode() == 0) 1752 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1753 1754 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1755 dl, DAG, VA, Flags)); 1756 } 1757 } 1758 } 1759 1760 if (!MemOpChains.empty()) 1761 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1762 &MemOpChains[0], MemOpChains.size()); 1763 1764 // Build a sequence of copy-to-reg nodes chained together with token chain 1765 // and flag operands which copy the outgoing args into registers. 1766 SDValue InFlag; 1767 // Tail call byval lowering might overwrite argument registers so in case of 1768 // tail call optimization the copies to registers are lowered later. 1769 if (!isTailCall) 1770 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1771 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1772 RegsToPass[i].second, InFlag); 1773 InFlag = Chain.getValue(1); 1774 } 1775 1776 1777 if (Subtarget->isPICStyleGOT()) { 1778 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1779 // GOT pointer. 1780 if (!isTailCall) { 1781 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1782 DAG.getNode(X86ISD::GlobalBaseReg, 1783 DebugLoc::getUnknownLoc(), 1784 getPointerTy()), 1785 InFlag); 1786 InFlag = Chain.getValue(1); 1787 } else { 1788 // If we are tail calling and generating PIC/GOT style code load the 1789 // address of the callee into ECX. The value in ecx is used as target of 1790 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1791 // for tail calls on PIC/GOT architectures. Normally we would just put the 1792 // address of GOT into ebx and then call target@PLT. But for tail calls 1793 // ebx would be restored (since ebx is callee saved) before jumping to the 1794 // target@PLT. 1795 1796 // Note: The actual moving to ECX is done further down. 1797 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1798 if (G && !G->getGlobal()->hasHiddenVisibility() && 1799 !G->getGlobal()->hasProtectedVisibility()) 1800 Callee = LowerGlobalAddress(Callee, DAG); 1801 else if (isa<ExternalSymbolSDNode>(Callee)) 1802 Callee = LowerExternalSymbol(Callee, DAG); 1803 } 1804 } 1805 1806 if (Is64Bit && isVarArg) { 1807 // From AMD64 ABI document: 1808 // For calls that may call functions that use varargs or stdargs 1809 // (prototype-less calls or calls to functions containing ellipsis (...) in 1810 // the declaration) %al is used as hidden argument to specify the number 1811 // of SSE registers used. The contents of %al do not need to match exactly 1812 // the number of registers, but must be an ubound on the number of SSE 1813 // registers used and is in the range 0 - 8 inclusive. 1814 1815 // FIXME: Verify this on Win64 1816 // Count the number of XMM registers allocated. 1817 static const unsigned XMMArgRegs[] = { 1818 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1819 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1820 }; 1821 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1822 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1823 && "SSE registers cannot be used when SSE is disabled"); 1824 1825 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1826 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1827 InFlag = Chain.getValue(1); 1828 } 1829 1830 1831 // For tail calls lower the arguments to the 'real' stack slot. 1832 if (isTailCall) { 1833 // Force all the incoming stack arguments to be loaded from the stack 1834 // before any new outgoing arguments are stored to the stack, because the 1835 // outgoing stack slots may alias the incoming argument stack slots, and 1836 // the alias isn't otherwise explicit. This is slightly more conservative 1837 // than necessary, because it means that each store effectively depends 1838 // on every argument instead of just those arguments it would clobber. 1839 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1840 1841 SmallVector<SDValue, 8> MemOpChains2; 1842 SDValue FIN; 1843 int FI = 0; 1844 // Do not flag preceeding copytoreg stuff together with the following stuff. 1845 InFlag = SDValue(); 1846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1847 CCValAssign &VA = ArgLocs[i]; 1848 if (!VA.isRegLoc()) { 1849 assert(VA.isMemLoc()); 1850 SDValue Arg = Outs[i].Val; 1851 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1852 // Create frame index. 1853 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1854 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1855 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1856 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1857 1858 if (Flags.isByVal()) { 1859 // Copy relative to framepointer. 1860 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1861 if (StackPtr.getNode() == 0) 1862 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1863 getPointerTy()); 1864 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1865 1866 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 1867 ArgChain, 1868 Flags, DAG, dl)); 1869 } else { 1870 // Store relative to framepointer. 1871 MemOpChains2.push_back( 1872 DAG.getStore(ArgChain, dl, Arg, FIN, 1873 PseudoSourceValue::getFixedStack(FI), 0)); 1874 } 1875 } 1876 } 1877 1878 if (!MemOpChains2.empty()) 1879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1880 &MemOpChains2[0], MemOpChains2.size()); 1881 1882 // Copy arguments to their registers. 1883 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1884 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1885 RegsToPass[i].second, InFlag); 1886 InFlag = Chain.getValue(1); 1887 } 1888 InFlag =SDValue(); 1889 1890 // Store the return address to the appropriate stack slot. 1891 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1892 FPDiff, dl); 1893 } 1894 1895 // If the callee is a GlobalAddress node (quite common, every direct call is) 1896 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1897 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1898 // We should use extra load for direct calls to dllimported functions in 1899 // non-JIT mode. 1900 GlobalValue *GV = G->getGlobal(); 1901 if (!GV->hasDLLImportLinkage()) { 1902 unsigned char OpFlags = 0; 1903 1904 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1905 // external symbols most go through the PLT in PIC mode. If the symbol 1906 // has hidden or protected visibility, or if it is static or local, then 1907 // we don't need to use the PLT - we can directly call it. 1908 if (Subtarget->isTargetELF() && 1909 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1910 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1911 OpFlags = X86II::MO_PLT; 1912 } else if (Subtarget->isPICStyleStubAny() && 1913 (GV->isDeclaration() || GV->isWeakForLinker()) && 1914 Subtarget->getDarwinVers() < 9) { 1915 // PC-relative references to external symbols should go through $stub, 1916 // unless we're building with the leopard linker or later, which 1917 // automatically synthesizes these stubs. 1918 OpFlags = X86II::MO_DARWIN_STUB; 1919 } 1920 1921 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 1922 G->getOffset(), OpFlags); 1923 } 1924 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1925 unsigned char OpFlags = 0; 1926 1927 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 1928 // symbols should go through the PLT. 1929 if (Subtarget->isTargetELF() && 1930 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1931 OpFlags = X86II::MO_PLT; 1932 } else if (Subtarget->isPICStyleStubAny() && 1933 Subtarget->getDarwinVers() < 9) { 1934 // PC-relative references to external symbols should go through $stub, 1935 // unless we're building with the leopard linker or later, which 1936 // automatically synthesizes these stubs. 1937 OpFlags = X86II::MO_DARWIN_STUB; 1938 } 1939 1940 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 1941 OpFlags); 1942 } else if (isTailCall) { 1943 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX; 1944 1945 Chain = DAG.getCopyToReg(Chain, dl, 1946 DAG.getRegister(Opc, getPointerTy()), 1947 Callee,InFlag); 1948 Callee = DAG.getRegister(Opc, getPointerTy()); 1949 // Add register as live out. 1950 MF.getRegInfo().addLiveOut(Opc); 1951 } 1952 1953 // Returns a chain & a flag for retval copy to use. 1954 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1955 SmallVector<SDValue, 8> Ops; 1956 1957 if (isTailCall) { 1958 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1959 DAG.getIntPtrConstant(0, true), InFlag); 1960 InFlag = Chain.getValue(1); 1961 } 1962 1963 Ops.push_back(Chain); 1964 Ops.push_back(Callee); 1965 1966 if (isTailCall) 1967 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1968 1969 // Add argument registers to the end of the list so that they are known live 1970 // into the call. 1971 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1972 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1973 RegsToPass[i].second.getValueType())); 1974 1975 // Add an implicit use GOT pointer in EBX. 1976 if (!isTailCall && Subtarget->isPICStyleGOT()) 1977 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1978 1979 // Add an implicit use of AL for x86 vararg functions. 1980 if (Is64Bit && isVarArg) 1981 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1982 1983 if (InFlag.getNode()) 1984 Ops.push_back(InFlag); 1985 1986 if (isTailCall) { 1987 // If this is the first return lowered for this function, add the regs 1988 // to the liveout set for the function. 1989 if (MF.getRegInfo().liveout_empty()) { 1990 SmallVector<CCValAssign, 16> RVLocs; 1991 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 1992 *DAG.getContext()); 1993 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1994 for (unsigned i = 0; i != RVLocs.size(); ++i) 1995 if (RVLocs[i].isRegLoc()) 1996 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1997 } 1998 1999 assert(((Callee.getOpcode() == ISD::Register && 2000 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || 2001 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) || 2002 Callee.getOpcode() == ISD::TargetExternalSymbol || 2003 Callee.getOpcode() == ISD::TargetGlobalAddress) && 2004 "Expecting an global address, external symbol, or register"); 2005 2006 return DAG.getNode(X86ISD::TC_RETURN, dl, 2007 NodeTys, &Ops[0], Ops.size()); 2008 } 2009 2010 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2011 InFlag = Chain.getValue(1); 2012 2013 // Create the CALLSEQ_END node. 2014 unsigned NumBytesForCalleeToPush; 2015 if (IsCalleePop(isVarArg, CallConv)) 2016 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2017 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet) 2018 // If this is is a call to a struct-return function, the callee 2019 // pops the hidden struct pointer, so we have to push it back. 2020 // This is common for Darwin/X86, Linux & Mingw32 targets. 2021 NumBytesForCalleeToPush = 4; 2022 else 2023 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2024 2025 // Returns a flag for retval copy to use. 2026 Chain = DAG.getCALLSEQ_END(Chain, 2027 DAG.getIntPtrConstant(NumBytes, true), 2028 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2029 true), 2030 InFlag); 2031 InFlag = Chain.getValue(1); 2032 2033 // Handle result values, copying them out of physregs into vregs that we 2034 // return. 2035 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2036 Ins, dl, DAG, InVals); 2037} 2038 2039 2040//===----------------------------------------------------------------------===// 2041// Fast Calling Convention (tail call) implementation 2042//===----------------------------------------------------------------------===// 2043 2044// Like std call, callee cleans arguments, convention except that ECX is 2045// reserved for storing the tail called function address. Only 2 registers are 2046// free for argument passing (inreg). Tail call optimization is performed 2047// provided: 2048// * tailcallopt is enabled 2049// * caller/callee are fastcc 2050// On X86_64 architecture with GOT-style position independent code only local 2051// (within module) calls are supported at the moment. 2052// To keep the stack aligned according to platform abi the function 2053// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2054// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2055// If a tail called function callee has more arguments than the caller the 2056// caller needs to make sure that there is room to move the RETADDR to. This is 2057// achieved by reserving an area the size of the argument delta right after the 2058// original REtADDR, but before the saved framepointer or the spilled registers 2059// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2060// stack layout: 2061// arg1 2062// arg2 2063// RETADDR 2064// [ new RETADDR 2065// move area ] 2066// (possible EBP) 2067// ESI 2068// EDI 2069// local1 .. 2070 2071/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2072/// for a 16 byte align requirement. 2073unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2074 SelectionDAG& DAG) { 2075 MachineFunction &MF = DAG.getMachineFunction(); 2076 const TargetMachine &TM = MF.getTarget(); 2077 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2078 unsigned StackAlignment = TFI.getStackAlignment(); 2079 uint64_t AlignMask = StackAlignment - 1; 2080 int64_t Offset = StackSize; 2081 uint64_t SlotSize = TD->getPointerSize(); 2082 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2083 // Number smaller than 12 so just add the difference. 2084 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2085 } else { 2086 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2087 Offset = ((~AlignMask) & Offset) + StackAlignment + 2088 (StackAlignment-SlotSize); 2089 } 2090 return Offset; 2091} 2092 2093/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2094/// for tail call optimization. Targets which want to do tail call 2095/// optimization should implement this function. 2096bool 2097X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2098 unsigned CalleeCC, 2099 bool isVarArg, 2100 const SmallVectorImpl<ISD::InputArg> &Ins, 2101 SelectionDAG& DAG) const { 2102 MachineFunction &MF = DAG.getMachineFunction(); 2103 unsigned CallerCC = MF.getFunction()->getCallingConv(); 2104 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC; 2105} 2106 2107FastISel * 2108X86TargetLowering::createFastISel(MachineFunction &mf, 2109 MachineModuleInfo *mmo, 2110 DwarfWriter *dw, 2111 DenseMap<const Value *, unsigned> &vm, 2112 DenseMap<const BasicBlock *, 2113 MachineBasicBlock *> &bm, 2114 DenseMap<const AllocaInst *, int> &am 2115#ifndef NDEBUG 2116 , SmallSet<Instruction*, 8> &cil 2117#endif 2118 ) { 2119 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2120#ifndef NDEBUG 2121 , cil 2122#endif 2123 ); 2124} 2125 2126 2127//===----------------------------------------------------------------------===// 2128// Other Lowering Hooks 2129//===----------------------------------------------------------------------===// 2130 2131 2132SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2133 MachineFunction &MF = DAG.getMachineFunction(); 2134 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2135 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2136 2137 if (ReturnAddrIndex == 0) { 2138 // Set up a frame object for the return address. 2139 uint64_t SlotSize = TD->getPointerSize(); 2140 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 2141 FuncInfo->setRAIndex(ReturnAddrIndex); 2142 } 2143 2144 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2145} 2146 2147 2148bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2149 bool hasSymbolicDisplacement) { 2150 // Offset should fit into 32 bit immediate field. 2151 if (!isInt32(Offset)) 2152 return false; 2153 2154 // If we don't have a symbolic displacement - we don't have any extra 2155 // restrictions. 2156 if (!hasSymbolicDisplacement) 2157 return true; 2158 2159 // FIXME: Some tweaks might be needed for medium code model. 2160 if (M != CodeModel::Small && M != CodeModel::Kernel) 2161 return false; 2162 2163 // For small code model we assume that latest object is 16MB before end of 31 2164 // bits boundary. We may also accept pretty large negative constants knowing 2165 // that all objects are in the positive half of address space. 2166 if (M == CodeModel::Small && Offset < 16*1024*1024) 2167 return true; 2168 2169 // For kernel code model we know that all object resist in the negative half 2170 // of 32bits address space. We may not accept negative offsets, since they may 2171 // be just off and we may accept pretty large positive ones. 2172 if (M == CodeModel::Kernel && Offset > 0) 2173 return true; 2174 2175 return false; 2176} 2177 2178/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2179/// specific condition code, returning the condition code and the LHS/RHS of the 2180/// comparison to make. 2181static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2182 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2183 if (!isFP) { 2184 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2185 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2186 // X > -1 -> X == 0, jump !sign. 2187 RHS = DAG.getConstant(0, RHS.getValueType()); 2188 return X86::COND_NS; 2189 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2190 // X < 0 -> X == 0, jump on sign. 2191 return X86::COND_S; 2192 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2193 // X < 1 -> X <= 0 2194 RHS = DAG.getConstant(0, RHS.getValueType()); 2195 return X86::COND_LE; 2196 } 2197 } 2198 2199 switch (SetCCOpcode) { 2200 default: llvm_unreachable("Invalid integer condition!"); 2201 case ISD::SETEQ: return X86::COND_E; 2202 case ISD::SETGT: return X86::COND_G; 2203 case ISD::SETGE: return X86::COND_GE; 2204 case ISD::SETLT: return X86::COND_L; 2205 case ISD::SETLE: return X86::COND_LE; 2206 case ISD::SETNE: return X86::COND_NE; 2207 case ISD::SETULT: return X86::COND_B; 2208 case ISD::SETUGT: return X86::COND_A; 2209 case ISD::SETULE: return X86::COND_BE; 2210 case ISD::SETUGE: return X86::COND_AE; 2211 } 2212 } 2213 2214 // First determine if it is required or is profitable to flip the operands. 2215 2216 // If LHS is a foldable load, but RHS is not, flip the condition. 2217 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2218 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2219 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2220 std::swap(LHS, RHS); 2221 } 2222 2223 switch (SetCCOpcode) { 2224 default: break; 2225 case ISD::SETOLT: 2226 case ISD::SETOLE: 2227 case ISD::SETUGT: 2228 case ISD::SETUGE: 2229 std::swap(LHS, RHS); 2230 break; 2231 } 2232 2233 // On a floating point condition, the flags are set as follows: 2234 // ZF PF CF op 2235 // 0 | 0 | 0 | X > Y 2236 // 0 | 0 | 1 | X < Y 2237 // 1 | 0 | 0 | X == Y 2238 // 1 | 1 | 1 | unordered 2239 switch (SetCCOpcode) { 2240 default: llvm_unreachable("Condcode should be pre-legalized away"); 2241 case ISD::SETUEQ: 2242 case ISD::SETEQ: return X86::COND_E; 2243 case ISD::SETOLT: // flipped 2244 case ISD::SETOGT: 2245 case ISD::SETGT: return X86::COND_A; 2246 case ISD::SETOLE: // flipped 2247 case ISD::SETOGE: 2248 case ISD::SETGE: return X86::COND_AE; 2249 case ISD::SETUGT: // flipped 2250 case ISD::SETULT: 2251 case ISD::SETLT: return X86::COND_B; 2252 case ISD::SETUGE: // flipped 2253 case ISD::SETULE: 2254 case ISD::SETLE: return X86::COND_BE; 2255 case ISD::SETONE: 2256 case ISD::SETNE: return X86::COND_NE; 2257 case ISD::SETUO: return X86::COND_P; 2258 case ISD::SETO: return X86::COND_NP; 2259 } 2260} 2261 2262/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2263/// code. Current x86 isa includes the following FP cmov instructions: 2264/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2265static bool hasFPCMov(unsigned X86CC) { 2266 switch (X86CC) { 2267 default: 2268 return false; 2269 case X86::COND_B: 2270 case X86::COND_BE: 2271 case X86::COND_E: 2272 case X86::COND_P: 2273 case X86::COND_A: 2274 case X86::COND_AE: 2275 case X86::COND_NE: 2276 case X86::COND_NP: 2277 return true; 2278 } 2279} 2280 2281/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2282/// the specified range (L, H]. 2283static bool isUndefOrInRange(int Val, int Low, int Hi) { 2284 return (Val < 0) || (Val >= Low && Val < Hi); 2285} 2286 2287/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2288/// specified value. 2289static bool isUndefOrEqual(int Val, int CmpVal) { 2290 if (Val < 0 || Val == CmpVal) 2291 return true; 2292 return false; 2293} 2294 2295/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2296/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2297/// the second operand. 2298static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2299 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2300 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2301 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2302 return (Mask[0] < 2 && Mask[1] < 2); 2303 return false; 2304} 2305 2306bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2307 SmallVector<int, 8> M; 2308 N->getMask(M); 2309 return ::isPSHUFDMask(M, N->getValueType(0)); 2310} 2311 2312/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2313/// is suitable for input to PSHUFHW. 2314static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2315 if (VT != MVT::v8i16) 2316 return false; 2317 2318 // Lower quadword copied in order or undef. 2319 for (int i = 0; i != 4; ++i) 2320 if (Mask[i] >= 0 && Mask[i] != i) 2321 return false; 2322 2323 // Upper quadword shuffled. 2324 for (int i = 4; i != 8; ++i) 2325 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2326 return false; 2327 2328 return true; 2329} 2330 2331bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2332 SmallVector<int, 8> M; 2333 N->getMask(M); 2334 return ::isPSHUFHWMask(M, N->getValueType(0)); 2335} 2336 2337/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2338/// is suitable for input to PSHUFLW. 2339static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2340 if (VT != MVT::v8i16) 2341 return false; 2342 2343 // Upper quadword copied in order. 2344 for (int i = 4; i != 8; ++i) 2345 if (Mask[i] >= 0 && Mask[i] != i) 2346 return false; 2347 2348 // Lower quadword shuffled. 2349 for (int i = 0; i != 4; ++i) 2350 if (Mask[i] >= 4) 2351 return false; 2352 2353 return true; 2354} 2355 2356bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2357 SmallVector<int, 8> M; 2358 N->getMask(M); 2359 return ::isPSHUFLWMask(M, N->getValueType(0)); 2360} 2361 2362/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2363/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2364static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2365 int NumElems = VT.getVectorNumElements(); 2366 if (NumElems != 2 && NumElems != 4) 2367 return false; 2368 2369 int Half = NumElems / 2; 2370 for (int i = 0; i < Half; ++i) 2371 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2372 return false; 2373 for (int i = Half; i < NumElems; ++i) 2374 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2375 return false; 2376 2377 return true; 2378} 2379 2380bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2381 SmallVector<int, 8> M; 2382 N->getMask(M); 2383 return ::isSHUFPMask(M, N->getValueType(0)); 2384} 2385 2386/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2387/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2388/// half elements to come from vector 1 (which would equal the dest.) and 2389/// the upper half to come from vector 2. 2390static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2391 int NumElems = VT.getVectorNumElements(); 2392 2393 if (NumElems != 2 && NumElems != 4) 2394 return false; 2395 2396 int Half = NumElems / 2; 2397 for (int i = 0; i < Half; ++i) 2398 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2399 return false; 2400 for (int i = Half; i < NumElems; ++i) 2401 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2402 return false; 2403 return true; 2404} 2405 2406static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2407 SmallVector<int, 8> M; 2408 N->getMask(M); 2409 return isCommutedSHUFPMask(M, N->getValueType(0)); 2410} 2411 2412/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2413/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2414bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2415 if (N->getValueType(0).getVectorNumElements() != 4) 2416 return false; 2417 2418 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2419 return isUndefOrEqual(N->getMaskElt(0), 6) && 2420 isUndefOrEqual(N->getMaskElt(1), 7) && 2421 isUndefOrEqual(N->getMaskElt(2), 2) && 2422 isUndefOrEqual(N->getMaskElt(3), 3); 2423} 2424 2425/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2426/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2427bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2428 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2429 2430 if (NumElems != 2 && NumElems != 4) 2431 return false; 2432 2433 for (unsigned i = 0; i < NumElems/2; ++i) 2434 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2435 return false; 2436 2437 for (unsigned i = NumElems/2; i < NumElems; ++i) 2438 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2439 return false; 2440 2441 return true; 2442} 2443 2444/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2445/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2446/// and MOVLHPS. 2447bool X86::isMOVHPMask(ShuffleVectorSDNode *N) { 2448 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2449 2450 if (NumElems != 2 && NumElems != 4) 2451 return false; 2452 2453 for (unsigned i = 0; i < NumElems/2; ++i) 2454 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2455 return false; 2456 2457 for (unsigned i = 0; i < NumElems/2; ++i) 2458 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2459 return false; 2460 2461 return true; 2462} 2463 2464/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2465/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2466/// <2, 3, 2, 3> 2467bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2468 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2469 2470 if (NumElems != 4) 2471 return false; 2472 2473 return isUndefOrEqual(N->getMaskElt(0), 2) && 2474 isUndefOrEqual(N->getMaskElt(1), 3) && 2475 isUndefOrEqual(N->getMaskElt(2), 2) && 2476 isUndefOrEqual(N->getMaskElt(3), 3); 2477} 2478 2479/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2480/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2481static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2482 bool V2IsSplat = false) { 2483 int NumElts = VT.getVectorNumElements(); 2484 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2485 return false; 2486 2487 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2488 int BitI = Mask[i]; 2489 int BitI1 = Mask[i+1]; 2490 if (!isUndefOrEqual(BitI, j)) 2491 return false; 2492 if (V2IsSplat) { 2493 if (!isUndefOrEqual(BitI1, NumElts)) 2494 return false; 2495 } else { 2496 if (!isUndefOrEqual(BitI1, j + NumElts)) 2497 return false; 2498 } 2499 } 2500 return true; 2501} 2502 2503bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2504 SmallVector<int, 8> M; 2505 N->getMask(M); 2506 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2507} 2508 2509/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2510/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2511static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2512 bool V2IsSplat = false) { 2513 int NumElts = VT.getVectorNumElements(); 2514 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2515 return false; 2516 2517 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2518 int BitI = Mask[i]; 2519 int BitI1 = Mask[i+1]; 2520 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2521 return false; 2522 if (V2IsSplat) { 2523 if (isUndefOrEqual(BitI1, NumElts)) 2524 return false; 2525 } else { 2526 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2527 return false; 2528 } 2529 } 2530 return true; 2531} 2532 2533bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2534 SmallVector<int, 8> M; 2535 N->getMask(M); 2536 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2537} 2538 2539/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2540/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2541/// <0, 0, 1, 1> 2542static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2543 int NumElems = VT.getVectorNumElements(); 2544 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2545 return false; 2546 2547 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2548 int BitI = Mask[i]; 2549 int BitI1 = Mask[i+1]; 2550 if (!isUndefOrEqual(BitI, j)) 2551 return false; 2552 if (!isUndefOrEqual(BitI1, j)) 2553 return false; 2554 } 2555 return true; 2556} 2557 2558bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2559 SmallVector<int, 8> M; 2560 N->getMask(M); 2561 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2562} 2563 2564/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2565/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2566/// <2, 2, 3, 3> 2567static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2568 int NumElems = VT.getVectorNumElements(); 2569 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2570 return false; 2571 2572 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2573 int BitI = Mask[i]; 2574 int BitI1 = Mask[i+1]; 2575 if (!isUndefOrEqual(BitI, j)) 2576 return false; 2577 if (!isUndefOrEqual(BitI1, j)) 2578 return false; 2579 } 2580 return true; 2581} 2582 2583bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2584 SmallVector<int, 8> M; 2585 N->getMask(M); 2586 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2587} 2588 2589/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2590/// specifies a shuffle of elements that is suitable for input to MOVSS, 2591/// MOVSD, and MOVD, i.e. setting the lowest element. 2592static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2593 if (VT.getVectorElementType().getSizeInBits() < 32) 2594 return false; 2595 2596 int NumElts = VT.getVectorNumElements(); 2597 2598 if (!isUndefOrEqual(Mask[0], NumElts)) 2599 return false; 2600 2601 for (int i = 1; i < NumElts; ++i) 2602 if (!isUndefOrEqual(Mask[i], i)) 2603 return false; 2604 2605 return true; 2606} 2607 2608bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2609 SmallVector<int, 8> M; 2610 N->getMask(M); 2611 return ::isMOVLMask(M, N->getValueType(0)); 2612} 2613 2614/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2615/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2616/// element of vector 2 and the other elements to come from vector 1 in order. 2617static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2618 bool V2IsSplat = false, bool V2IsUndef = false) { 2619 int NumOps = VT.getVectorNumElements(); 2620 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2621 return false; 2622 2623 if (!isUndefOrEqual(Mask[0], 0)) 2624 return false; 2625 2626 for (int i = 1; i < NumOps; ++i) 2627 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2628 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2629 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2630 return false; 2631 2632 return true; 2633} 2634 2635static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2636 bool V2IsUndef = false) { 2637 SmallVector<int, 8> M; 2638 N->getMask(M); 2639 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2640} 2641 2642/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2643/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2644bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2645 if (N->getValueType(0).getVectorNumElements() != 4) 2646 return false; 2647 2648 // Expect 1, 1, 3, 3 2649 for (unsigned i = 0; i < 2; ++i) { 2650 int Elt = N->getMaskElt(i); 2651 if (Elt >= 0 && Elt != 1) 2652 return false; 2653 } 2654 2655 bool HasHi = false; 2656 for (unsigned i = 2; i < 4; ++i) { 2657 int Elt = N->getMaskElt(i); 2658 if (Elt >= 0 && Elt != 3) 2659 return false; 2660 if (Elt == 3) 2661 HasHi = true; 2662 } 2663 // Don't use movshdup if it can be done with a shufps. 2664 // FIXME: verify that matching u, u, 3, 3 is what we want. 2665 return HasHi; 2666} 2667 2668/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2669/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2670bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 2671 if (N->getValueType(0).getVectorNumElements() != 4) 2672 return false; 2673 2674 // Expect 0, 0, 2, 2 2675 for (unsigned i = 0; i < 2; ++i) 2676 if (N->getMaskElt(i) > 0) 2677 return false; 2678 2679 bool HasHi = false; 2680 for (unsigned i = 2; i < 4; ++i) { 2681 int Elt = N->getMaskElt(i); 2682 if (Elt >= 0 && Elt != 2) 2683 return false; 2684 if (Elt == 2) 2685 HasHi = true; 2686 } 2687 // Don't use movsldup if it can be done with a shufps. 2688 return HasHi; 2689} 2690 2691/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2692/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2693bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 2694 int e = N->getValueType(0).getVectorNumElements() / 2; 2695 2696 for (int i = 0; i < e; ++i) 2697 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2698 return false; 2699 for (int i = 0; i < e; ++i) 2700 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 2701 return false; 2702 return true; 2703} 2704 2705/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2706/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2707/// instructions. 2708unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2710 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 2711 2712 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2713 unsigned Mask = 0; 2714 for (int i = 0; i < NumOperands; ++i) { 2715 int Val = SVOp->getMaskElt(NumOperands-i-1); 2716 if (Val < 0) Val = 0; 2717 if (Val >= NumOperands) Val -= NumOperands; 2718 Mask |= Val; 2719 if (i != NumOperands - 1) 2720 Mask <<= Shift; 2721 } 2722 return Mask; 2723} 2724 2725/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2726/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2727/// instructions. 2728unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2729 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2730 unsigned Mask = 0; 2731 // 8 nodes, but we only care about the last 4. 2732 for (unsigned i = 7; i >= 4; --i) { 2733 int Val = SVOp->getMaskElt(i); 2734 if (Val >= 0) 2735 Mask |= (Val - 4); 2736 if (i != 4) 2737 Mask <<= 2; 2738 } 2739 return Mask; 2740} 2741 2742/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2743/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2744/// instructions. 2745unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2746 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2747 unsigned Mask = 0; 2748 // 8 nodes, but we only care about the first 4. 2749 for (int i = 3; i >= 0; --i) { 2750 int Val = SVOp->getMaskElt(i); 2751 if (Val >= 0) 2752 Mask |= Val; 2753 if (i != 0) 2754 Mask <<= 2; 2755 } 2756 return Mask; 2757} 2758 2759/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2760/// constant +0.0. 2761bool X86::isZeroNode(SDValue Elt) { 2762 return ((isa<ConstantSDNode>(Elt) && 2763 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2764 (isa<ConstantFPSDNode>(Elt) && 2765 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2766} 2767 2768/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 2769/// their permute mask. 2770static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 2771 SelectionDAG &DAG) { 2772 EVT VT = SVOp->getValueType(0); 2773 unsigned NumElems = VT.getVectorNumElements(); 2774 SmallVector<int, 8> MaskVec; 2775 2776 for (unsigned i = 0; i != NumElems; ++i) { 2777 int idx = SVOp->getMaskElt(i); 2778 if (idx < 0) 2779 MaskVec.push_back(idx); 2780 else if (idx < (int)NumElems) 2781 MaskVec.push_back(idx + NumElems); 2782 else 2783 MaskVec.push_back(idx - NumElems); 2784 } 2785 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 2786 SVOp->getOperand(0), &MaskVec[0]); 2787} 2788 2789/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2790/// the two vector operands have swapped position. 2791static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 2792 unsigned NumElems = VT.getVectorNumElements(); 2793 for (unsigned i = 0; i != NumElems; ++i) { 2794 int idx = Mask[i]; 2795 if (idx < 0) 2796 continue; 2797 else if (idx < (int)NumElems) 2798 Mask[i] = idx + NumElems; 2799 else 2800 Mask[i] = idx - NumElems; 2801 } 2802} 2803 2804/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2805/// match movhlps. The lower half elements should come from upper half of 2806/// V1 (and in order), and the upper half elements should come from the upper 2807/// half of V2 (and in order). 2808static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 2809 if (Op->getValueType(0).getVectorNumElements() != 4) 2810 return false; 2811 for (unsigned i = 0, e = 2; i != e; ++i) 2812 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 2813 return false; 2814 for (unsigned i = 2; i != 4; ++i) 2815 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 2816 return false; 2817 return true; 2818} 2819 2820/// isScalarLoadToVector - Returns true if the node is a scalar load that 2821/// is promoted to a vector. It also returns the LoadSDNode by reference if 2822/// required. 2823static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2824 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2825 return false; 2826 N = N->getOperand(0).getNode(); 2827 if (!ISD::isNON_EXTLoad(N)) 2828 return false; 2829 if (LD) 2830 *LD = cast<LoadSDNode>(N); 2831 return true; 2832} 2833 2834/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2835/// match movlp{s|d}. The lower half elements should come from lower half of 2836/// V1 (and in order), and the upper half elements should come from the upper 2837/// half of V2 (and in order). And since V1 will become the source of the 2838/// MOVLP, it must be either a vector load or a scalar load to vector. 2839static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 2840 ShuffleVectorSDNode *Op) { 2841 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2842 return false; 2843 // Is V2 is a vector load, don't do this transformation. We will try to use 2844 // load folding shufps op. 2845 if (ISD::isNON_EXTLoad(V2)) 2846 return false; 2847 2848 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 2849 2850 if (NumElems != 2 && NumElems != 4) 2851 return false; 2852 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2853 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 2854 return false; 2855 for (unsigned i = NumElems/2; i != NumElems; ++i) 2856 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 2857 return false; 2858 return true; 2859} 2860 2861/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2862/// all the same. 2863static bool isSplatVector(SDNode *N) { 2864 if (N->getOpcode() != ISD::BUILD_VECTOR) 2865 return false; 2866 2867 SDValue SplatValue = N->getOperand(0); 2868 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2869 if (N->getOperand(i) != SplatValue) 2870 return false; 2871 return true; 2872} 2873 2874/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2875/// to an zero vector. 2876/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 2877static bool isZeroShuffle(ShuffleVectorSDNode *N) { 2878 SDValue V1 = N->getOperand(0); 2879 SDValue V2 = N->getOperand(1); 2880 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2881 for (unsigned i = 0; i != NumElems; ++i) { 2882 int Idx = N->getMaskElt(i); 2883 if (Idx >= (int)NumElems) { 2884 unsigned Opc = V2.getOpcode(); 2885 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2886 continue; 2887 if (Opc != ISD::BUILD_VECTOR || 2888 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 2889 return false; 2890 } else if (Idx >= 0) { 2891 unsigned Opc = V1.getOpcode(); 2892 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2893 continue; 2894 if (Opc != ISD::BUILD_VECTOR || 2895 !X86::isZeroNode(V1.getOperand(Idx))) 2896 return false; 2897 } 2898 } 2899 return true; 2900} 2901 2902/// getZeroVector - Returns a vector of specified type with all zero elements. 2903/// 2904static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 2905 DebugLoc dl) { 2906 assert(VT.isVector() && "Expected a vector type"); 2907 2908 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2909 // type. This ensures they get CSE'd. 2910 SDValue Vec; 2911 if (VT.getSizeInBits() == 64) { // MMX 2912 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2913 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2914 } else if (HasSSE2) { // SSE2 2915 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2916 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2917 } else { // SSE1 2918 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2919 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 2920 } 2921 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2922} 2923 2924/// getOnesVector - Returns a vector of specified type with all bits set. 2925/// 2926static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2927 assert(VT.isVector() && "Expected a vector type"); 2928 2929 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2930 // type. This ensures they get CSE'd. 2931 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2932 SDValue Vec; 2933 if (VT.getSizeInBits() == 64) // MMX 2934 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2935 else // SSE 2936 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2937 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2938} 2939 2940 2941/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2942/// that point to V2 points to its first element. 2943static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 2944 EVT VT = SVOp->getValueType(0); 2945 unsigned NumElems = VT.getVectorNumElements(); 2946 2947 bool Changed = false; 2948 SmallVector<int, 8> MaskVec; 2949 SVOp->getMask(MaskVec); 2950 2951 for (unsigned i = 0; i != NumElems; ++i) { 2952 if (MaskVec[i] > (int)NumElems) { 2953 MaskVec[i] = NumElems; 2954 Changed = true; 2955 } 2956 } 2957 if (Changed) 2958 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 2959 SVOp->getOperand(1), &MaskVec[0]); 2960 return SDValue(SVOp, 0); 2961} 2962 2963/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2964/// operation of specified width. 2965static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 2966 SDValue V2) { 2967 unsigned NumElems = VT.getVectorNumElements(); 2968 SmallVector<int, 8> Mask; 2969 Mask.push_back(NumElems); 2970 for (unsigned i = 1; i != NumElems; ++i) 2971 Mask.push_back(i); 2972 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2973} 2974 2975/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 2976static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 2977 SDValue V2) { 2978 unsigned NumElems = VT.getVectorNumElements(); 2979 SmallVector<int, 8> Mask; 2980 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2981 Mask.push_back(i); 2982 Mask.push_back(i + NumElems); 2983 } 2984 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2985} 2986 2987/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 2988static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 2989 SDValue V2) { 2990 unsigned NumElems = VT.getVectorNumElements(); 2991 unsigned Half = NumElems/2; 2992 SmallVector<int, 8> Mask; 2993 for (unsigned i = 0; i != Half; ++i) { 2994 Mask.push_back(i + Half); 2995 Mask.push_back(i + NumElems + Half); 2996 } 2997 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2998} 2999 3000/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3001static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3002 bool HasSSE2) { 3003 if (SV->getValueType(0).getVectorNumElements() <= 4) 3004 return SDValue(SV, 0); 3005 3006 EVT PVT = MVT::v4f32; 3007 EVT VT = SV->getValueType(0); 3008 DebugLoc dl = SV->getDebugLoc(); 3009 SDValue V1 = SV->getOperand(0); 3010 int NumElems = VT.getVectorNumElements(); 3011 int EltNo = SV->getSplatIndex(); 3012 3013 // unpack elements to the correct location 3014 while (NumElems > 4) { 3015 if (EltNo < NumElems/2) { 3016 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3017 } else { 3018 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3019 EltNo -= NumElems/2; 3020 } 3021 NumElems >>= 1; 3022 } 3023 3024 // Perform the splat. 3025 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3026 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3027 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3028 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3029} 3030 3031/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3032/// vector of zero or undef vector. This produces a shuffle where the low 3033/// element of V2 is swizzled into the zero/undef vector, landing at element 3034/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3035static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3036 bool isZero, bool HasSSE2, 3037 SelectionDAG &DAG) { 3038 EVT VT = V2.getValueType(); 3039 SDValue V1 = isZero 3040 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3041 unsigned NumElems = VT.getVectorNumElements(); 3042 SmallVector<int, 16> MaskVec; 3043 for (unsigned i = 0; i != NumElems; ++i) 3044 // If this is the insertion idx, put the low elt of V2 here. 3045 MaskVec.push_back(i == Idx ? NumElems : i); 3046 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3047} 3048 3049/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3050/// a shuffle that is zero. 3051static 3052unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3053 bool Low, SelectionDAG &DAG) { 3054 unsigned NumZeros = 0; 3055 for (int i = 0; i < NumElems; ++i) { 3056 unsigned Index = Low ? i : NumElems-i-1; 3057 int Idx = SVOp->getMaskElt(Index); 3058 if (Idx < 0) { 3059 ++NumZeros; 3060 continue; 3061 } 3062 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3063 if (Elt.getNode() && X86::isZeroNode(Elt)) 3064 ++NumZeros; 3065 else 3066 break; 3067 } 3068 return NumZeros; 3069} 3070 3071/// isVectorShift - Returns true if the shuffle can be implemented as a 3072/// logical left or right shift of a vector. 3073/// FIXME: split into pslldqi, psrldqi, palignr variants. 3074static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3075 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3076 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3077 3078 isLeft = true; 3079 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3080 if (!NumZeros) { 3081 isLeft = false; 3082 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3083 if (!NumZeros) 3084 return false; 3085 } 3086 bool SeenV1 = false; 3087 bool SeenV2 = false; 3088 for (int i = NumZeros; i < NumElems; ++i) { 3089 int Val = isLeft ? (i - NumZeros) : i; 3090 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3091 if (Idx < 0) 3092 continue; 3093 if (Idx < NumElems) 3094 SeenV1 = true; 3095 else { 3096 Idx -= NumElems; 3097 SeenV2 = true; 3098 } 3099 if (Idx != Val) 3100 return false; 3101 } 3102 if (SeenV1 && SeenV2) 3103 return false; 3104 3105 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3106 ShAmt = NumZeros; 3107 return true; 3108} 3109 3110 3111/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3112/// 3113static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3114 unsigned NumNonZero, unsigned NumZero, 3115 SelectionDAG &DAG, TargetLowering &TLI) { 3116 if (NumNonZero > 8) 3117 return SDValue(); 3118 3119 DebugLoc dl = Op.getDebugLoc(); 3120 SDValue V(0, 0); 3121 bool First = true; 3122 for (unsigned i = 0; i < 16; ++i) { 3123 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3124 if (ThisIsNonZero && First) { 3125 if (NumZero) 3126 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3127 else 3128 V = DAG.getUNDEF(MVT::v8i16); 3129 First = false; 3130 } 3131 3132 if ((i & 1) != 0) { 3133 SDValue ThisElt(0, 0), LastElt(0, 0); 3134 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3135 if (LastIsNonZero) { 3136 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3137 MVT::i16, Op.getOperand(i-1)); 3138 } 3139 if (ThisIsNonZero) { 3140 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3141 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3142 ThisElt, DAG.getConstant(8, MVT::i8)); 3143 if (LastIsNonZero) 3144 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3145 } else 3146 ThisElt = LastElt; 3147 3148 if (ThisElt.getNode()) 3149 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3150 DAG.getIntPtrConstant(i/2)); 3151 } 3152 } 3153 3154 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3155} 3156 3157/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3158/// 3159static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3160 unsigned NumNonZero, unsigned NumZero, 3161 SelectionDAG &DAG, TargetLowering &TLI) { 3162 if (NumNonZero > 4) 3163 return SDValue(); 3164 3165 DebugLoc dl = Op.getDebugLoc(); 3166 SDValue V(0, 0); 3167 bool First = true; 3168 for (unsigned i = 0; i < 8; ++i) { 3169 bool isNonZero = (NonZeros & (1 << i)) != 0; 3170 if (isNonZero) { 3171 if (First) { 3172 if (NumZero) 3173 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3174 else 3175 V = DAG.getUNDEF(MVT::v8i16); 3176 First = false; 3177 } 3178 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3179 MVT::v8i16, V, Op.getOperand(i), 3180 DAG.getIntPtrConstant(i)); 3181 } 3182 } 3183 3184 return V; 3185} 3186 3187/// getVShift - Return a vector logical shift node. 3188/// 3189static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3190 unsigned NumBits, SelectionDAG &DAG, 3191 const TargetLowering &TLI, DebugLoc dl) { 3192 bool isMMX = VT.getSizeInBits() == 64; 3193 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3194 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3195 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3196 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3197 DAG.getNode(Opc, dl, ShVT, SrcOp, 3198 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3199} 3200 3201SDValue 3202X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3203 DebugLoc dl = Op.getDebugLoc(); 3204 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3205 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3206 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3207 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3208 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3209 // eliminated on x86-32 hosts. 3210 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3211 return Op; 3212 3213 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3214 return getOnesVector(Op.getValueType(), DAG, dl); 3215 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3216 } 3217 3218 EVT VT = Op.getValueType(); 3219 EVT ExtVT = VT.getVectorElementType(); 3220 unsigned EVTBits = ExtVT.getSizeInBits(); 3221 3222 unsigned NumElems = Op.getNumOperands(); 3223 unsigned NumZero = 0; 3224 unsigned NumNonZero = 0; 3225 unsigned NonZeros = 0; 3226 bool IsAllConstants = true; 3227 SmallSet<SDValue, 8> Values; 3228 for (unsigned i = 0; i < NumElems; ++i) { 3229 SDValue Elt = Op.getOperand(i); 3230 if (Elt.getOpcode() == ISD::UNDEF) 3231 continue; 3232 Values.insert(Elt); 3233 if (Elt.getOpcode() != ISD::Constant && 3234 Elt.getOpcode() != ISD::ConstantFP) 3235 IsAllConstants = false; 3236 if (X86::isZeroNode(Elt)) 3237 NumZero++; 3238 else { 3239 NonZeros |= (1 << i); 3240 NumNonZero++; 3241 } 3242 } 3243 3244 if (NumNonZero == 0) { 3245 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3246 return DAG.getUNDEF(VT); 3247 } 3248 3249 // Special case for single non-zero, non-undef, element. 3250 if (NumNonZero == 1) { 3251 unsigned Idx = CountTrailingZeros_32(NonZeros); 3252 SDValue Item = Op.getOperand(Idx); 3253 3254 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3255 // the value are obviously zero, truncate the value to i32 and do the 3256 // insertion that way. Only do this if the value is non-constant or if the 3257 // value is a constant being inserted into element 0. It is cheaper to do 3258 // a constant pool load than it is to do a movd + shuffle. 3259 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3260 (!IsAllConstants || Idx == 0)) { 3261 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3262 // Handle MMX and SSE both. 3263 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3264 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3265 3266 // Truncate the value (which may itself be a constant) to i32, and 3267 // convert it to a vector with movd (S2V+shuffle to zero extend). 3268 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3269 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3270 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3271 Subtarget->hasSSE2(), DAG); 3272 3273 // Now we have our 32-bit value zero extended in the low element of 3274 // a vector. If Idx != 0, swizzle it into place. 3275 if (Idx != 0) { 3276 SmallVector<int, 4> Mask; 3277 Mask.push_back(Idx); 3278 for (unsigned i = 1; i != VecElts; ++i) 3279 Mask.push_back(i); 3280 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3281 DAG.getUNDEF(Item.getValueType()), 3282 &Mask[0]); 3283 } 3284 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3285 } 3286 } 3287 3288 // If we have a constant or non-constant insertion into the low element of 3289 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3290 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3291 // depending on what the source datatype is. 3292 if (Idx == 0) { 3293 if (NumZero == 0) { 3294 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3295 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3296 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3297 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3298 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3299 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3300 DAG); 3301 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3302 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3303 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3304 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3305 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3306 Subtarget->hasSSE2(), DAG); 3307 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3308 } 3309 } 3310 3311 // Is it a vector logical left shift? 3312 if (NumElems == 2 && Idx == 1 && 3313 X86::isZeroNode(Op.getOperand(0)) && 3314 !X86::isZeroNode(Op.getOperand(1))) { 3315 unsigned NumBits = VT.getSizeInBits(); 3316 return getVShift(true, VT, 3317 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3318 VT, Op.getOperand(1)), 3319 NumBits/2, DAG, *this, dl); 3320 } 3321 3322 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3323 return SDValue(); 3324 3325 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3326 // is a non-constant being inserted into an element other than the low one, 3327 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3328 // movd/movss) to move this into the low element, then shuffle it into 3329 // place. 3330 if (EVTBits == 32) { 3331 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3332 3333 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3334 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3335 Subtarget->hasSSE2(), DAG); 3336 SmallVector<int, 8> MaskVec; 3337 for (unsigned i = 0; i < NumElems; i++) 3338 MaskVec.push_back(i == Idx ? 0 : 1); 3339 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3340 } 3341 } 3342 3343 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3344 if (Values.size() == 1) 3345 return SDValue(); 3346 3347 // A vector full of immediates; various special cases are already 3348 // handled, so this is best done with a single constant-pool load. 3349 if (IsAllConstants) 3350 return SDValue(); 3351 3352 // Let legalizer expand 2-wide build_vectors. 3353 if (EVTBits == 64) { 3354 if (NumNonZero == 1) { 3355 // One half is zero or undef. 3356 unsigned Idx = CountTrailingZeros_32(NonZeros); 3357 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3358 Op.getOperand(Idx)); 3359 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3360 Subtarget->hasSSE2(), DAG); 3361 } 3362 return SDValue(); 3363 } 3364 3365 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3366 if (EVTBits == 8 && NumElems == 16) { 3367 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3368 *this); 3369 if (V.getNode()) return V; 3370 } 3371 3372 if (EVTBits == 16 && NumElems == 8) { 3373 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3374 *this); 3375 if (V.getNode()) return V; 3376 } 3377 3378 // If element VT is == 32 bits, turn it into a number of shuffles. 3379 SmallVector<SDValue, 8> V; 3380 V.resize(NumElems); 3381 if (NumElems == 4 && NumZero > 0) { 3382 for (unsigned i = 0; i < 4; ++i) { 3383 bool isZero = !(NonZeros & (1 << i)); 3384 if (isZero) 3385 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3386 else 3387 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3388 } 3389 3390 for (unsigned i = 0; i < 2; ++i) { 3391 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3392 default: break; 3393 case 0: 3394 V[i] = V[i*2]; // Must be a zero vector. 3395 break; 3396 case 1: 3397 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3398 break; 3399 case 2: 3400 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3401 break; 3402 case 3: 3403 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3404 break; 3405 } 3406 } 3407 3408 SmallVector<int, 8> MaskVec; 3409 bool Reverse = (NonZeros & 0x3) == 2; 3410 for (unsigned i = 0; i < 2; ++i) 3411 MaskVec.push_back(Reverse ? 1-i : i); 3412 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3413 for (unsigned i = 0; i < 2; ++i) 3414 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3415 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3416 } 3417 3418 if (Values.size() > 2) { 3419 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3420 // values to be inserted is equal to the number of elements, in which case 3421 // use the unpack code below in the hopes of matching the consecutive elts 3422 // load merge pattern for shuffles. 3423 // FIXME: We could probably just check that here directly. 3424 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3425 getSubtarget()->hasSSE41()) { 3426 V[0] = DAG.getUNDEF(VT); 3427 for (unsigned i = 0; i < NumElems; ++i) 3428 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3429 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3430 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3431 return V[0]; 3432 } 3433 // Expand into a number of unpckl*. 3434 // e.g. for v4f32 3435 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3436 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3437 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3438 for (unsigned i = 0; i < NumElems; ++i) 3439 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3440 NumElems >>= 1; 3441 while (NumElems != 0) { 3442 for (unsigned i = 0; i < NumElems; ++i) 3443 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3444 NumElems >>= 1; 3445 } 3446 return V[0]; 3447 } 3448 3449 return SDValue(); 3450} 3451 3452// v8i16 shuffles - Prefer shuffles in the following order: 3453// 1. [all] pshuflw, pshufhw, optional move 3454// 2. [ssse3] 1 x pshufb 3455// 3. [ssse3] 2 x pshufb + 1 x por 3456// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3457static 3458SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3459 SelectionDAG &DAG, X86TargetLowering &TLI) { 3460 SDValue V1 = SVOp->getOperand(0); 3461 SDValue V2 = SVOp->getOperand(1); 3462 DebugLoc dl = SVOp->getDebugLoc(); 3463 SmallVector<int, 8> MaskVals; 3464 3465 // Determine if more than 1 of the words in each of the low and high quadwords 3466 // of the result come from the same quadword of one of the two inputs. Undef 3467 // mask values count as coming from any quadword, for better codegen. 3468 SmallVector<unsigned, 4> LoQuad(4); 3469 SmallVector<unsigned, 4> HiQuad(4); 3470 BitVector InputQuads(4); 3471 for (unsigned i = 0; i < 8; ++i) { 3472 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3473 int EltIdx = SVOp->getMaskElt(i); 3474 MaskVals.push_back(EltIdx); 3475 if (EltIdx < 0) { 3476 ++Quad[0]; 3477 ++Quad[1]; 3478 ++Quad[2]; 3479 ++Quad[3]; 3480 continue; 3481 } 3482 ++Quad[EltIdx / 4]; 3483 InputQuads.set(EltIdx / 4); 3484 } 3485 3486 int BestLoQuad = -1; 3487 unsigned MaxQuad = 1; 3488 for (unsigned i = 0; i < 4; ++i) { 3489 if (LoQuad[i] > MaxQuad) { 3490 BestLoQuad = i; 3491 MaxQuad = LoQuad[i]; 3492 } 3493 } 3494 3495 int BestHiQuad = -1; 3496 MaxQuad = 1; 3497 for (unsigned i = 0; i < 4; ++i) { 3498 if (HiQuad[i] > MaxQuad) { 3499 BestHiQuad = i; 3500 MaxQuad = HiQuad[i]; 3501 } 3502 } 3503 3504 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3505 // of the two input vectors, shuffle them into one input vector so only a 3506 // single pshufb instruction is necessary. If There are more than 2 input 3507 // quads, disable the next transformation since it does not help SSSE3. 3508 bool V1Used = InputQuads[0] || InputQuads[1]; 3509 bool V2Used = InputQuads[2] || InputQuads[3]; 3510 if (TLI.getSubtarget()->hasSSSE3()) { 3511 if (InputQuads.count() == 2 && V1Used && V2Used) { 3512 BestLoQuad = InputQuads.find_first(); 3513 BestHiQuad = InputQuads.find_next(BestLoQuad); 3514 } 3515 if (InputQuads.count() > 2) { 3516 BestLoQuad = -1; 3517 BestHiQuad = -1; 3518 } 3519 } 3520 3521 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3522 // the shuffle mask. If a quad is scored as -1, that means that it contains 3523 // words from all 4 input quadwords. 3524 SDValue NewV; 3525 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3526 SmallVector<int, 8> MaskV; 3527 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3528 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3529 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3530 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3531 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3532 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3533 3534 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3535 // source words for the shuffle, to aid later transformations. 3536 bool AllWordsInNewV = true; 3537 bool InOrder[2] = { true, true }; 3538 for (unsigned i = 0; i != 8; ++i) { 3539 int idx = MaskVals[i]; 3540 if (idx != (int)i) 3541 InOrder[i/4] = false; 3542 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3543 continue; 3544 AllWordsInNewV = false; 3545 break; 3546 } 3547 3548 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3549 if (AllWordsInNewV) { 3550 for (int i = 0; i != 8; ++i) { 3551 int idx = MaskVals[i]; 3552 if (idx < 0) 3553 continue; 3554 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3555 if ((idx != i) && idx < 4) 3556 pshufhw = false; 3557 if ((idx != i) && idx > 3) 3558 pshuflw = false; 3559 } 3560 V1 = NewV; 3561 V2Used = false; 3562 BestLoQuad = 0; 3563 BestHiQuad = 1; 3564 } 3565 3566 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3567 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3568 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 3569 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 3570 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 3571 } 3572 } 3573 3574 // If we have SSSE3, and all words of the result are from 1 input vector, 3575 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 3576 // is present, fall back to case 4. 3577 if (TLI.getSubtarget()->hasSSSE3()) { 3578 SmallVector<SDValue,16> pshufbMask; 3579 3580 // If we have elements from both input vectors, set the high bit of the 3581 // shuffle mask element to zero out elements that come from V2 in the V1 3582 // mask, and elements that come from V1 in the V2 mask, so that the two 3583 // results can be OR'd together. 3584 bool TwoInputs = V1Used && V2Used; 3585 for (unsigned i = 0; i != 8; ++i) { 3586 int EltIdx = MaskVals[i] * 2; 3587 if (TwoInputs && (EltIdx >= 16)) { 3588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3590 continue; 3591 } 3592 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3593 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 3594 } 3595 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 3596 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3597 DAG.getNode(ISD::BUILD_VECTOR, dl, 3598 MVT::v16i8, &pshufbMask[0], 16)); 3599 if (!TwoInputs) 3600 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3601 3602 // Calculate the shuffle mask for the second input, shuffle it, and 3603 // OR it with the first shuffled input. 3604 pshufbMask.clear(); 3605 for (unsigned i = 0; i != 8; ++i) { 3606 int EltIdx = MaskVals[i] * 2; 3607 if (EltIdx < 16) { 3608 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3609 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3610 continue; 3611 } 3612 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3613 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 3614 } 3615 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 3616 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3617 DAG.getNode(ISD::BUILD_VECTOR, dl, 3618 MVT::v16i8, &pshufbMask[0], 16)); 3619 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3620 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3621 } 3622 3623 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 3624 // and update MaskVals with new element order. 3625 BitVector InOrder(8); 3626 if (BestLoQuad >= 0) { 3627 SmallVector<int, 8> MaskV; 3628 for (int i = 0; i != 4; ++i) { 3629 int idx = MaskVals[i]; 3630 if (idx < 0) { 3631 MaskV.push_back(-1); 3632 InOrder.set(i); 3633 } else if ((idx / 4) == BestLoQuad) { 3634 MaskV.push_back(idx & 3); 3635 InOrder.set(i); 3636 } else { 3637 MaskV.push_back(-1); 3638 } 3639 } 3640 for (unsigned i = 4; i != 8; ++i) 3641 MaskV.push_back(i); 3642 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3643 &MaskV[0]); 3644 } 3645 3646 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 3647 // and update MaskVals with the new element order. 3648 if (BestHiQuad >= 0) { 3649 SmallVector<int, 8> MaskV; 3650 for (unsigned i = 0; i != 4; ++i) 3651 MaskV.push_back(i); 3652 for (unsigned i = 4; i != 8; ++i) { 3653 int idx = MaskVals[i]; 3654 if (idx < 0) { 3655 MaskV.push_back(-1); 3656 InOrder.set(i); 3657 } else if ((idx / 4) == BestHiQuad) { 3658 MaskV.push_back((idx & 3) + 4); 3659 InOrder.set(i); 3660 } else { 3661 MaskV.push_back(-1); 3662 } 3663 } 3664 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3665 &MaskV[0]); 3666 } 3667 3668 // In case BestHi & BestLo were both -1, which means each quadword has a word 3669 // from each of the four input quadwords, calculate the InOrder bitvector now 3670 // before falling through to the insert/extract cleanup. 3671 if (BestLoQuad == -1 && BestHiQuad == -1) { 3672 NewV = V1; 3673 for (int i = 0; i != 8; ++i) 3674 if (MaskVals[i] < 0 || MaskVals[i] == i) 3675 InOrder.set(i); 3676 } 3677 3678 // The other elements are put in the right place using pextrw and pinsrw. 3679 for (unsigned i = 0; i != 8; ++i) { 3680 if (InOrder[i]) 3681 continue; 3682 int EltIdx = MaskVals[i]; 3683 if (EltIdx < 0) 3684 continue; 3685 SDValue ExtOp = (EltIdx < 8) 3686 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 3687 DAG.getIntPtrConstant(EltIdx)) 3688 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 3689 DAG.getIntPtrConstant(EltIdx - 8)); 3690 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 3691 DAG.getIntPtrConstant(i)); 3692 } 3693 return NewV; 3694} 3695 3696// v16i8 shuffles - Prefer shuffles in the following order: 3697// 1. [ssse3] 1 x pshufb 3698// 2. [ssse3] 2 x pshufb + 1 x por 3699// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 3700static 3701SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 3702 SelectionDAG &DAG, X86TargetLowering &TLI) { 3703 SDValue V1 = SVOp->getOperand(0); 3704 SDValue V2 = SVOp->getOperand(1); 3705 DebugLoc dl = SVOp->getDebugLoc(); 3706 SmallVector<int, 16> MaskVals; 3707 SVOp->getMask(MaskVals); 3708 3709 // If we have SSSE3, case 1 is generated when all result bytes come from 3710 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 3711 // present, fall back to case 3. 3712 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 3713 bool V1Only = true; 3714 bool V2Only = true; 3715 for (unsigned i = 0; i < 16; ++i) { 3716 int EltIdx = MaskVals[i]; 3717 if (EltIdx < 0) 3718 continue; 3719 if (EltIdx < 16) 3720 V2Only = false; 3721 else 3722 V1Only = false; 3723 } 3724 3725 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 3726 if (TLI.getSubtarget()->hasSSSE3()) { 3727 SmallVector<SDValue,16> pshufbMask; 3728 3729 // If all result elements are from one input vector, then only translate 3730 // undef mask values to 0x80 (zero out result) in the pshufb mask. 3731 // 3732 // Otherwise, we have elements from both input vectors, and must zero out 3733 // elements that come from V2 in the first mask, and V1 in the second mask 3734 // so that we can OR them together. 3735 bool TwoInputs = !(V1Only || V2Only); 3736 for (unsigned i = 0; i != 16; ++i) { 3737 int EltIdx = MaskVals[i]; 3738 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 3739 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3740 continue; 3741 } 3742 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3743 } 3744 // If all the elements are from V2, assign it to V1 and return after 3745 // building the first pshufb. 3746 if (V2Only) 3747 V1 = V2; 3748 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3749 DAG.getNode(ISD::BUILD_VECTOR, dl, 3750 MVT::v16i8, &pshufbMask[0], 16)); 3751 if (!TwoInputs) 3752 return V1; 3753 3754 // Calculate the shuffle mask for the second input, shuffle it, and 3755 // OR it with the first shuffled input. 3756 pshufbMask.clear(); 3757 for (unsigned i = 0; i != 16; ++i) { 3758 int EltIdx = MaskVals[i]; 3759 if (EltIdx < 16) { 3760 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3761 continue; 3762 } 3763 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3764 } 3765 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3766 DAG.getNode(ISD::BUILD_VECTOR, dl, 3767 MVT::v16i8, &pshufbMask[0], 16)); 3768 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3769 } 3770 3771 // No SSSE3 - Calculate in place words and then fix all out of place words 3772 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 3773 // the 16 different words that comprise the two doublequadword input vectors. 3774 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3775 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 3776 SDValue NewV = V2Only ? V2 : V1; 3777 for (int i = 0; i != 8; ++i) { 3778 int Elt0 = MaskVals[i*2]; 3779 int Elt1 = MaskVals[i*2+1]; 3780 3781 // This word of the result is all undef, skip it. 3782 if (Elt0 < 0 && Elt1 < 0) 3783 continue; 3784 3785 // This word of the result is already in the correct place, skip it. 3786 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 3787 continue; 3788 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 3789 continue; 3790 3791 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 3792 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 3793 SDValue InsElt; 3794 3795 // If Elt0 and Elt1 are defined, are consecutive, and can be load 3796 // using a single extract together, load it and store it. 3797 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 3798 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3799 DAG.getIntPtrConstant(Elt1 / 2)); 3800 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3801 DAG.getIntPtrConstant(i)); 3802 continue; 3803 } 3804 3805 // If Elt1 is defined, extract it from the appropriate source. If the 3806 // source byte is not also odd, shift the extracted word left 8 bits 3807 // otherwise clear the bottom 8 bits if we need to do an or. 3808 if (Elt1 >= 0) { 3809 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3810 DAG.getIntPtrConstant(Elt1 / 2)); 3811 if ((Elt1 & 1) == 0) 3812 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 3813 DAG.getConstant(8, TLI.getShiftAmountTy())); 3814 else if (Elt0 >= 0) 3815 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 3816 DAG.getConstant(0xFF00, MVT::i16)); 3817 } 3818 // If Elt0 is defined, extract it from the appropriate source. If the 3819 // source byte is not also even, shift the extracted word right 8 bits. If 3820 // Elt1 was also defined, OR the extracted values together before 3821 // inserting them in the result. 3822 if (Elt0 >= 0) { 3823 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 3824 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 3825 if ((Elt0 & 1) != 0) 3826 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 3827 DAG.getConstant(8, TLI.getShiftAmountTy())); 3828 else if (Elt1 >= 0) 3829 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 3830 DAG.getConstant(0x00FF, MVT::i16)); 3831 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 3832 : InsElt0; 3833 } 3834 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3835 DAG.getIntPtrConstant(i)); 3836 } 3837 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 3838} 3839 3840/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3841/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3842/// done when every pair / quad of shuffle mask elements point to elements in 3843/// the right sequence. e.g. 3844/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3845static 3846SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 3847 SelectionDAG &DAG, 3848 TargetLowering &TLI, DebugLoc dl) { 3849 EVT VT = SVOp->getValueType(0); 3850 SDValue V1 = SVOp->getOperand(0); 3851 SDValue V2 = SVOp->getOperand(1); 3852 unsigned NumElems = VT.getVectorNumElements(); 3853 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3854 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3855 EVT MaskEltVT = MaskVT.getVectorElementType(); 3856 EVT NewVT = MaskVT; 3857 switch (VT.getSimpleVT().SimpleTy) { 3858 default: assert(false && "Unexpected!"); 3859 case MVT::v4f32: NewVT = MVT::v2f64; break; 3860 case MVT::v4i32: NewVT = MVT::v2i64; break; 3861 case MVT::v8i16: NewVT = MVT::v4i32; break; 3862 case MVT::v16i8: NewVT = MVT::v4i32; break; 3863 } 3864 3865 if (NewWidth == 2) { 3866 if (VT.isInteger()) 3867 NewVT = MVT::v2i64; 3868 else 3869 NewVT = MVT::v2f64; 3870 } 3871 int Scale = NumElems / NewWidth; 3872 SmallVector<int, 8> MaskVec; 3873 for (unsigned i = 0; i < NumElems; i += Scale) { 3874 int StartIdx = -1; 3875 for (int j = 0; j < Scale; ++j) { 3876 int EltIdx = SVOp->getMaskElt(i+j); 3877 if (EltIdx < 0) 3878 continue; 3879 if (StartIdx == -1) 3880 StartIdx = EltIdx - (EltIdx % Scale); 3881 if (EltIdx != StartIdx + j) 3882 return SDValue(); 3883 } 3884 if (StartIdx == -1) 3885 MaskVec.push_back(-1); 3886 else 3887 MaskVec.push_back(StartIdx / Scale); 3888 } 3889 3890 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 3891 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 3892 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 3893} 3894 3895/// getVZextMovL - Return a zero-extending vector move low node. 3896/// 3897static SDValue getVZextMovL(EVT VT, EVT OpVT, 3898 SDValue SrcOp, SelectionDAG &DAG, 3899 const X86Subtarget *Subtarget, DebugLoc dl) { 3900 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3901 LoadSDNode *LD = NULL; 3902 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3903 LD = dyn_cast<LoadSDNode>(SrcOp); 3904 if (!LD) { 3905 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3906 // instead. 3907 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3908 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 3909 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3910 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3911 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 3912 // PR2108 3913 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3914 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3915 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3916 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3917 OpVT, 3918 SrcOp.getOperand(0) 3919 .getOperand(0)))); 3920 } 3921 } 3922 } 3923 3924 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3925 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3926 DAG.getNode(ISD::BIT_CONVERT, dl, 3927 OpVT, SrcOp))); 3928} 3929 3930/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3931/// shuffles. 3932static SDValue 3933LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3934 SDValue V1 = SVOp->getOperand(0); 3935 SDValue V2 = SVOp->getOperand(1); 3936 DebugLoc dl = SVOp->getDebugLoc(); 3937 EVT VT = SVOp->getValueType(0); 3938 3939 SmallVector<std::pair<int, int>, 8> Locs; 3940 Locs.resize(4); 3941 SmallVector<int, 8> Mask1(4U, -1); 3942 SmallVector<int, 8> PermMask; 3943 SVOp->getMask(PermMask); 3944 3945 unsigned NumHi = 0; 3946 unsigned NumLo = 0; 3947 for (unsigned i = 0; i != 4; ++i) { 3948 int Idx = PermMask[i]; 3949 if (Idx < 0) { 3950 Locs[i] = std::make_pair(-1, -1); 3951 } else { 3952 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 3953 if (Idx < 4) { 3954 Locs[i] = std::make_pair(0, NumLo); 3955 Mask1[NumLo] = Idx; 3956 NumLo++; 3957 } else { 3958 Locs[i] = std::make_pair(1, NumHi); 3959 if (2+NumHi < 4) 3960 Mask1[2+NumHi] = Idx; 3961 NumHi++; 3962 } 3963 } 3964 } 3965 3966 if (NumLo <= 2 && NumHi <= 2) { 3967 // If no more than two elements come from either vector. This can be 3968 // implemented with two shuffles. First shuffle gather the elements. 3969 // The second shuffle, which takes the first shuffle as both of its 3970 // vector operands, put the elements into the right order. 3971 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 3972 3973 SmallVector<int, 8> Mask2(4U, -1); 3974 3975 for (unsigned i = 0; i != 4; ++i) { 3976 if (Locs[i].first == -1) 3977 continue; 3978 else { 3979 unsigned Idx = (i < 2) ? 0 : 4; 3980 Idx += Locs[i].first * 2 + Locs[i].second; 3981 Mask2[i] = Idx; 3982 } 3983 } 3984 3985 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 3986 } else if (NumLo == 3 || NumHi == 3) { 3987 // Otherwise, we must have three elements from one vector, call it X, and 3988 // one element from the other, call it Y. First, use a shufps to build an 3989 // intermediate vector with the one element from Y and the element from X 3990 // that will be in the same half in the final destination (the indexes don't 3991 // matter). Then, use a shufps to build the final vector, taking the half 3992 // containing the element from Y from the intermediate, and the other half 3993 // from X. 3994 if (NumHi == 3) { 3995 // Normalize it so the 3 elements come from V1. 3996 CommuteVectorShuffleMask(PermMask, VT); 3997 std::swap(V1, V2); 3998 } 3999 4000 // Find the element from V2. 4001 unsigned HiIndex; 4002 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4003 int Val = PermMask[HiIndex]; 4004 if (Val < 0) 4005 continue; 4006 if (Val >= 4) 4007 break; 4008 } 4009 4010 Mask1[0] = PermMask[HiIndex]; 4011 Mask1[1] = -1; 4012 Mask1[2] = PermMask[HiIndex^1]; 4013 Mask1[3] = -1; 4014 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4015 4016 if (HiIndex >= 2) { 4017 Mask1[0] = PermMask[0]; 4018 Mask1[1] = PermMask[1]; 4019 Mask1[2] = HiIndex & 1 ? 6 : 4; 4020 Mask1[3] = HiIndex & 1 ? 4 : 6; 4021 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4022 } else { 4023 Mask1[0] = HiIndex & 1 ? 2 : 0; 4024 Mask1[1] = HiIndex & 1 ? 0 : 2; 4025 Mask1[2] = PermMask[2]; 4026 Mask1[3] = PermMask[3]; 4027 if (Mask1[2] >= 0) 4028 Mask1[2] += 4; 4029 if (Mask1[3] >= 0) 4030 Mask1[3] += 4; 4031 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4032 } 4033 } 4034 4035 // Break it into (shuffle shuffle_hi, shuffle_lo). 4036 Locs.clear(); 4037 SmallVector<int,8> LoMask(4U, -1); 4038 SmallVector<int,8> HiMask(4U, -1); 4039 4040 SmallVector<int,8> *MaskPtr = &LoMask; 4041 unsigned MaskIdx = 0; 4042 unsigned LoIdx = 0; 4043 unsigned HiIdx = 2; 4044 for (unsigned i = 0; i != 4; ++i) { 4045 if (i == 2) { 4046 MaskPtr = &HiMask; 4047 MaskIdx = 1; 4048 LoIdx = 0; 4049 HiIdx = 2; 4050 } 4051 int Idx = PermMask[i]; 4052 if (Idx < 0) { 4053 Locs[i] = std::make_pair(-1, -1); 4054 } else if (Idx < 4) { 4055 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4056 (*MaskPtr)[LoIdx] = Idx; 4057 LoIdx++; 4058 } else { 4059 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4060 (*MaskPtr)[HiIdx] = Idx; 4061 HiIdx++; 4062 } 4063 } 4064 4065 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4066 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4067 SmallVector<int, 8> MaskOps; 4068 for (unsigned i = 0; i != 4; ++i) { 4069 if (Locs[i].first == -1) { 4070 MaskOps.push_back(-1); 4071 } else { 4072 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4073 MaskOps.push_back(Idx); 4074 } 4075 } 4076 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4077} 4078 4079SDValue 4080X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4081 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4082 SDValue V1 = Op.getOperand(0); 4083 SDValue V2 = Op.getOperand(1); 4084 EVT VT = Op.getValueType(); 4085 DebugLoc dl = Op.getDebugLoc(); 4086 unsigned NumElems = VT.getVectorNumElements(); 4087 bool isMMX = VT.getSizeInBits() == 64; 4088 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4089 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4090 bool V1IsSplat = false; 4091 bool V2IsSplat = false; 4092 4093 if (isZeroShuffle(SVOp)) 4094 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4095 4096 // Promote splats to v4f32. 4097 if (SVOp->isSplat()) { 4098 if (isMMX || NumElems < 4) 4099 return Op; 4100 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4101 } 4102 4103 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4104 // do it! 4105 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4106 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4107 if (NewOp.getNode()) 4108 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4109 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4110 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4111 // FIXME: Figure out a cleaner way to do this. 4112 // Try to make use of movq to zero out the top part. 4113 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4114 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4115 if (NewOp.getNode()) { 4116 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4117 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4118 DAG, Subtarget, dl); 4119 } 4120 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4121 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4122 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4123 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4124 DAG, Subtarget, dl); 4125 } 4126 } 4127 4128 if (X86::isPSHUFDMask(SVOp)) 4129 return Op; 4130 4131 // Check if this can be converted into a logical shift. 4132 bool isLeft = false; 4133 unsigned ShAmt = 0; 4134 SDValue ShVal; 4135 bool isShift = getSubtarget()->hasSSE2() && 4136 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4137 if (isShift && ShVal.hasOneUse()) { 4138 // If the shifted value has multiple uses, it may be cheaper to use 4139 // v_set0 + movlhps or movhlps, etc. 4140 EVT EVT = VT.getVectorElementType(); 4141 ShAmt *= EVT.getSizeInBits(); 4142 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4143 } 4144 4145 if (X86::isMOVLMask(SVOp)) { 4146 if (V1IsUndef) 4147 return V2; 4148 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4149 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4150 if (!isMMX) 4151 return Op; 4152 } 4153 4154 // FIXME: fold these into legal mask. 4155 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4156 X86::isMOVSLDUPMask(SVOp) || 4157 X86::isMOVHLPSMask(SVOp) || 4158 X86::isMOVHPMask(SVOp) || 4159 X86::isMOVLPMask(SVOp))) 4160 return Op; 4161 4162 if (ShouldXformToMOVHLPS(SVOp) || 4163 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4164 return CommuteVectorShuffle(SVOp, DAG); 4165 4166 if (isShift) { 4167 // No better options. Use a vshl / vsrl. 4168 EVT EVT = VT.getVectorElementType(); 4169 ShAmt *= EVT.getSizeInBits(); 4170 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4171 } 4172 4173 bool Commuted = false; 4174 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4175 // 1,1,1,1 -> v8i16 though. 4176 V1IsSplat = isSplatVector(V1.getNode()); 4177 V2IsSplat = isSplatVector(V2.getNode()); 4178 4179 // Canonicalize the splat or undef, if present, to be on the RHS. 4180 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4181 Op = CommuteVectorShuffle(SVOp, DAG); 4182 SVOp = cast<ShuffleVectorSDNode>(Op); 4183 V1 = SVOp->getOperand(0); 4184 V2 = SVOp->getOperand(1); 4185 std::swap(V1IsSplat, V2IsSplat); 4186 std::swap(V1IsUndef, V2IsUndef); 4187 Commuted = true; 4188 } 4189 4190 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4191 // Shuffling low element of v1 into undef, just return v1. 4192 if (V2IsUndef) 4193 return V1; 4194 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4195 // the instruction selector will not match, so get a canonical MOVL with 4196 // swapped operands to undo the commute. 4197 return getMOVL(DAG, dl, VT, V2, V1); 4198 } 4199 4200 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4201 X86::isUNPCKH_v_undef_Mask(SVOp) || 4202 X86::isUNPCKLMask(SVOp) || 4203 X86::isUNPCKHMask(SVOp)) 4204 return Op; 4205 4206 if (V2IsSplat) { 4207 // Normalize mask so all entries that point to V2 points to its first 4208 // element then try to match unpck{h|l} again. If match, return a 4209 // new vector_shuffle with the corrected mask. 4210 SDValue NewMask = NormalizeMask(SVOp, DAG); 4211 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4212 if (NSVOp != SVOp) { 4213 if (X86::isUNPCKLMask(NSVOp, true)) { 4214 return NewMask; 4215 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4216 return NewMask; 4217 } 4218 } 4219 } 4220 4221 if (Commuted) { 4222 // Commute is back and try unpck* again. 4223 // FIXME: this seems wrong. 4224 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4225 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4226 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4227 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4228 X86::isUNPCKLMask(NewSVOp) || 4229 X86::isUNPCKHMask(NewSVOp)) 4230 return NewOp; 4231 } 4232 4233 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4234 4235 // Normalize the node to match x86 shuffle ops if needed 4236 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4237 return CommuteVectorShuffle(SVOp, DAG); 4238 4239 // Check for legal shuffle and return? 4240 SmallVector<int, 16> PermMask; 4241 SVOp->getMask(PermMask); 4242 if (isShuffleMaskLegal(PermMask, VT)) 4243 return Op; 4244 4245 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4246 if (VT == MVT::v8i16) { 4247 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4248 if (NewOp.getNode()) 4249 return NewOp; 4250 } 4251 4252 if (VT == MVT::v16i8) { 4253 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4254 if (NewOp.getNode()) 4255 return NewOp; 4256 } 4257 4258 // Handle all 4 wide cases with a number of shuffles except for MMX. 4259 if (NumElems == 4 && !isMMX) 4260 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4261 4262 return SDValue(); 4263} 4264 4265SDValue 4266X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4267 SelectionDAG &DAG) { 4268 EVT VT = Op.getValueType(); 4269 DebugLoc dl = Op.getDebugLoc(); 4270 if (VT.getSizeInBits() == 8) { 4271 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4272 Op.getOperand(0), Op.getOperand(1)); 4273 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4274 DAG.getValueType(VT)); 4275 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4276 } else if (VT.getSizeInBits() == 16) { 4277 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4278 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4279 if (Idx == 0) 4280 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4281 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4282 DAG.getNode(ISD::BIT_CONVERT, dl, 4283 MVT::v4i32, 4284 Op.getOperand(0)), 4285 Op.getOperand(1))); 4286 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4287 Op.getOperand(0), Op.getOperand(1)); 4288 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4289 DAG.getValueType(VT)); 4290 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4291 } else if (VT == MVT::f32) { 4292 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4293 // the result back to FR32 register. It's only worth matching if the 4294 // result has a single use which is a store or a bitcast to i32. And in 4295 // the case of a store, it's not worth it if the index is a constant 0, 4296 // because a MOVSSmr can be used instead, which is smaller and faster. 4297 if (!Op.hasOneUse()) 4298 return SDValue(); 4299 SDNode *User = *Op.getNode()->use_begin(); 4300 if ((User->getOpcode() != ISD::STORE || 4301 (isa<ConstantSDNode>(Op.getOperand(1)) && 4302 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4303 (User->getOpcode() != ISD::BIT_CONVERT || 4304 User->getValueType(0) != MVT::i32)) 4305 return SDValue(); 4306 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4307 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4308 Op.getOperand(0)), 4309 Op.getOperand(1)); 4310 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4311 } else if (VT == MVT::i32) { 4312 // ExtractPS works with constant index. 4313 if (isa<ConstantSDNode>(Op.getOperand(1))) 4314 return Op; 4315 } 4316 return SDValue(); 4317} 4318 4319 4320SDValue 4321X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4322 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4323 return SDValue(); 4324 4325 if (Subtarget->hasSSE41()) { 4326 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4327 if (Res.getNode()) 4328 return Res; 4329 } 4330 4331 EVT VT = Op.getValueType(); 4332 DebugLoc dl = Op.getDebugLoc(); 4333 // TODO: handle v16i8. 4334 if (VT.getSizeInBits() == 16) { 4335 SDValue Vec = Op.getOperand(0); 4336 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4337 if (Idx == 0) 4338 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4339 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4340 DAG.getNode(ISD::BIT_CONVERT, dl, 4341 MVT::v4i32, Vec), 4342 Op.getOperand(1))); 4343 // Transform it so it match pextrw which produces a 32-bit result. 4344 EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1); 4345 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, 4346 Op.getOperand(0), Op.getOperand(1)); 4347 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, 4348 DAG.getValueType(VT)); 4349 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4350 } else if (VT.getSizeInBits() == 32) { 4351 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4352 if (Idx == 0) 4353 return Op; 4354 4355 // SHUFPS the element to the lowest double word, then movss. 4356 int Mask[4] = { Idx, -1, -1, -1 }; 4357 EVT VVT = Op.getOperand(0).getValueType(); 4358 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4359 DAG.getUNDEF(VVT), Mask); 4360 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4361 DAG.getIntPtrConstant(0)); 4362 } else if (VT.getSizeInBits() == 64) { 4363 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4364 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4365 // to match extract_elt for f64. 4366 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4367 if (Idx == 0) 4368 return Op; 4369 4370 // UNPCKHPD the element to the lowest double word, then movsd. 4371 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4372 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4373 int Mask[2] = { 1, -1 }; 4374 EVT VVT = Op.getOperand(0).getValueType(); 4375 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4376 DAG.getUNDEF(VVT), Mask); 4377 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4378 DAG.getIntPtrConstant(0)); 4379 } 4380 4381 return SDValue(); 4382} 4383 4384SDValue 4385X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4386 EVT VT = Op.getValueType(); 4387 EVT EVT = VT.getVectorElementType(); 4388 DebugLoc dl = Op.getDebugLoc(); 4389 4390 SDValue N0 = Op.getOperand(0); 4391 SDValue N1 = Op.getOperand(1); 4392 SDValue N2 = Op.getOperand(2); 4393 4394 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4395 isa<ConstantSDNode>(N2)) { 4396 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4397 : X86ISD::PINSRW; 4398 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4399 // argument. 4400 if (N1.getValueType() != MVT::i32) 4401 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4402 if (N2.getValueType() != MVT::i32) 4403 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4404 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4405 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4406 // Bits [7:6] of the constant are the source select. This will always be 4407 // zero here. The DAG Combiner may combine an extract_elt index into these 4408 // bits. For example (insert (extract, 3), 2) could be matched by putting 4409 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4410 // Bits [5:4] of the constant are the destination select. This is the 4411 // value of the incoming immediate. 4412 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4413 // combine either bitwise AND or insert of float 0.0 to set these bits. 4414 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4415 // Create this as a scalar to vector.. 4416 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4417 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4418 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4419 // PINSR* works with constant index. 4420 return Op; 4421 } 4422 return SDValue(); 4423} 4424 4425SDValue 4426X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4427 EVT VT = Op.getValueType(); 4428 EVT EVT = VT.getVectorElementType(); 4429 4430 if (Subtarget->hasSSE41()) 4431 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4432 4433 if (EVT == MVT::i8) 4434 return SDValue(); 4435 4436 DebugLoc dl = Op.getDebugLoc(); 4437 SDValue N0 = Op.getOperand(0); 4438 SDValue N1 = Op.getOperand(1); 4439 SDValue N2 = Op.getOperand(2); 4440 4441 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4442 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4443 // as its second argument. 4444 if (N1.getValueType() != MVT::i32) 4445 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4446 if (N2.getValueType() != MVT::i32) 4447 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4448 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4449 } 4450 return SDValue(); 4451} 4452 4453SDValue 4454X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4455 DebugLoc dl = Op.getDebugLoc(); 4456 if (Op.getValueType() == MVT::v2f32) 4457 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4458 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4459 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4460 Op.getOperand(0)))); 4461 4462 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4463 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4464 4465 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4466 EVT VT = MVT::v2i32; 4467 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4468 default: break; 4469 case MVT::v16i8: 4470 case MVT::v8i16: 4471 VT = MVT::v4i32; 4472 break; 4473 } 4474 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4475 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4476} 4477 4478// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4479// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4480// one of the above mentioned nodes. It has to be wrapped because otherwise 4481// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4482// be used to form addressing mode. These wrapped nodes will be selected 4483// into MOV32ri. 4484SDValue 4485X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4486 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4487 4488 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4489 // global base reg. 4490 unsigned char OpFlag = 0; 4491 unsigned WrapperKind = X86ISD::Wrapper; 4492 CodeModel::Model M = getTargetMachine().getCodeModel(); 4493 4494 if (Subtarget->isPICStyleRIPRel() && 4495 (M == CodeModel::Small || M == CodeModel::Kernel)) 4496 WrapperKind = X86ISD::WrapperRIP; 4497 else if (Subtarget->isPICStyleGOT()) 4498 OpFlag = X86II::MO_GOTOFF; 4499 else if (Subtarget->isPICStyleStubPIC()) 4500 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4501 4502 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4503 CP->getAlignment(), 4504 CP->getOffset(), OpFlag); 4505 DebugLoc DL = CP->getDebugLoc(); 4506 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4507 // With PIC, the address is actually $g + Offset. 4508 if (OpFlag) { 4509 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4510 DAG.getNode(X86ISD::GlobalBaseReg, 4511 DebugLoc::getUnknownLoc(), getPointerTy()), 4512 Result); 4513 } 4514 4515 return Result; 4516} 4517 4518SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4519 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4520 4521 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4522 // global base reg. 4523 unsigned char OpFlag = 0; 4524 unsigned WrapperKind = X86ISD::Wrapper; 4525 CodeModel::Model M = getTargetMachine().getCodeModel(); 4526 4527 if (Subtarget->isPICStyleRIPRel() && 4528 (M == CodeModel::Small || M == CodeModel::Kernel)) 4529 WrapperKind = X86ISD::WrapperRIP; 4530 else if (Subtarget->isPICStyleGOT()) 4531 OpFlag = X86II::MO_GOTOFF; 4532 else if (Subtarget->isPICStyleStubPIC()) 4533 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4534 4535 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4536 OpFlag); 4537 DebugLoc DL = JT->getDebugLoc(); 4538 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4539 4540 // With PIC, the address is actually $g + Offset. 4541 if (OpFlag) { 4542 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4543 DAG.getNode(X86ISD::GlobalBaseReg, 4544 DebugLoc::getUnknownLoc(), getPointerTy()), 4545 Result); 4546 } 4547 4548 return Result; 4549} 4550 4551SDValue 4552X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4553 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4554 4555 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4556 // global base reg. 4557 unsigned char OpFlag = 0; 4558 unsigned WrapperKind = X86ISD::Wrapper; 4559 CodeModel::Model M = getTargetMachine().getCodeModel(); 4560 4561 if (Subtarget->isPICStyleRIPRel() && 4562 (M == CodeModel::Small || M == CodeModel::Kernel)) 4563 WrapperKind = X86ISD::WrapperRIP; 4564 else if (Subtarget->isPICStyleGOT()) 4565 OpFlag = X86II::MO_GOTOFF; 4566 else if (Subtarget->isPICStyleStubPIC()) 4567 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4568 4569 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 4570 4571 DebugLoc DL = Op.getDebugLoc(); 4572 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4573 4574 4575 // With PIC, the address is actually $g + Offset. 4576 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4577 !Subtarget->is64Bit()) { 4578 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4579 DAG.getNode(X86ISD::GlobalBaseReg, 4580 DebugLoc::getUnknownLoc(), 4581 getPointerTy()), 4582 Result); 4583 } 4584 4585 return Result; 4586} 4587 4588SDValue 4589X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 4590 int64_t Offset, 4591 SelectionDAG &DAG) const { 4592 // Create the TargetGlobalAddress node, folding in the constant 4593 // offset if it is legal. 4594 unsigned char OpFlags = 4595 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 4596 CodeModel::Model M = getTargetMachine().getCodeModel(); 4597 SDValue Result; 4598 if (OpFlags == X86II::MO_NO_FLAG && 4599 X86::isOffsetSuitableForCodeModel(Offset, M)) { 4600 // A direct static reference to a global. 4601 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4602 Offset = 0; 4603 } else { 4604 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 4605 } 4606 4607 if (Subtarget->isPICStyleRIPRel() && 4608 (M == CodeModel::Small || M == CodeModel::Kernel)) 4609 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 4610 else 4611 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4612 4613 // With PIC, the address is actually $g + Offset. 4614 if (isGlobalRelativeToPICBase(OpFlags)) { 4615 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4616 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 4617 Result); 4618 } 4619 4620 // For globals that require a load from a stub to get the address, emit the 4621 // load. 4622 if (isGlobalStubReference(OpFlags)) 4623 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 4624 PseudoSourceValue::getGOT(), 0); 4625 4626 // If there was a non-zero offset that we didn't fold, create an explicit 4627 // addition for it. 4628 if (Offset != 0) 4629 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 4630 DAG.getConstant(Offset, getPointerTy())); 4631 4632 return Result; 4633} 4634 4635SDValue 4636X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4637 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4638 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4639 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 4640} 4641 4642static SDValue 4643GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 4644 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 4645 unsigned char OperandFlags) { 4646 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4647 DebugLoc dl = GA->getDebugLoc(); 4648 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4649 GA->getValueType(0), 4650 GA->getOffset(), 4651 OperandFlags); 4652 if (InFlag) { 4653 SDValue Ops[] = { Chain, TGA, *InFlag }; 4654 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 4655 } else { 4656 SDValue Ops[] = { Chain, TGA }; 4657 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 4658 } 4659 SDValue Flag = Chain.getValue(1); 4660 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 4661} 4662 4663// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4664static SDValue 4665LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4666 const EVT PtrVT) { 4667 SDValue InFlag; 4668 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 4669 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 4670 DAG.getNode(X86ISD::GlobalBaseReg, 4671 DebugLoc::getUnknownLoc(), 4672 PtrVT), InFlag); 4673 InFlag = Chain.getValue(1); 4674 4675 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 4676} 4677 4678// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4679static SDValue 4680LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4681 const EVT PtrVT) { 4682 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 4683 X86::RAX, X86II::MO_TLSGD); 4684} 4685 4686// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4687// "local exec" model. 4688static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4689 const EVT PtrVT, TLSModel::Model model, 4690 bool is64Bit) { 4691 DebugLoc dl = GA->getDebugLoc(); 4692 // Get the Thread Pointer 4693 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 4694 DebugLoc::getUnknownLoc(), PtrVT, 4695 DAG.getRegister(is64Bit? X86::FS : X86::GS, 4696 MVT::i32)); 4697 4698 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 4699 NULL, 0); 4700 4701 unsigned char OperandFlags = 0; 4702 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 4703 // initialexec. 4704 unsigned WrapperKind = X86ISD::Wrapper; 4705 if (model == TLSModel::LocalExec) { 4706 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 4707 } else if (is64Bit) { 4708 assert(model == TLSModel::InitialExec); 4709 OperandFlags = X86II::MO_GOTTPOFF; 4710 WrapperKind = X86ISD::WrapperRIP; 4711 } else { 4712 assert(model == TLSModel::InitialExec); 4713 OperandFlags = X86II::MO_INDNTPOFF; 4714 } 4715 4716 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4717 // exec) 4718 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 4719 GA->getOffset(), OperandFlags); 4720 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 4721 4722 if (model == TLSModel::InitialExec) 4723 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 4724 PseudoSourceValue::getGOT(), 0); 4725 4726 // The address of the thread local variable is the add of the thread 4727 // pointer with the offset of the variable. 4728 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 4729} 4730 4731SDValue 4732X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4733 // TODO: implement the "local dynamic" model 4734 // TODO: implement the "initial exec"model for pic executables 4735 assert(Subtarget->isTargetELF() && 4736 "TLS not implemented for non-ELF targets"); 4737 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4738 const GlobalValue *GV = GA->getGlobal(); 4739 4740 // If GV is an alias then use the aliasee for determining 4741 // thread-localness. 4742 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 4743 GV = GA->resolveAliasedGlobal(false); 4744 4745 TLSModel::Model model = getTLSModel(GV, 4746 getTargetMachine().getRelocationModel()); 4747 4748 switch (model) { 4749 case TLSModel::GeneralDynamic: 4750 case TLSModel::LocalDynamic: // not implemented 4751 if (Subtarget->is64Bit()) 4752 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4753 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4754 4755 case TLSModel::InitialExec: 4756 case TLSModel::LocalExec: 4757 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 4758 Subtarget->is64Bit()); 4759 } 4760 4761 llvm_unreachable("Unreachable"); 4762 return SDValue(); 4763} 4764 4765 4766/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4767/// take a 2 x i32 value to shift plus a shift amount. 4768SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4769 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4770 EVT VT = Op.getValueType(); 4771 unsigned VTBits = VT.getSizeInBits(); 4772 DebugLoc dl = Op.getDebugLoc(); 4773 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4774 SDValue ShOpLo = Op.getOperand(0); 4775 SDValue ShOpHi = Op.getOperand(1); 4776 SDValue ShAmt = Op.getOperand(2); 4777 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 4778 DAG.getConstant(VTBits - 1, MVT::i8)) 4779 : DAG.getConstant(0, VT); 4780 4781 SDValue Tmp2, Tmp3; 4782 if (Op.getOpcode() == ISD::SHL_PARTS) { 4783 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 4784 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4785 } else { 4786 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 4787 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 4788 } 4789 4790 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 4791 DAG.getConstant(VTBits, MVT::i8)); 4792 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, 4793 AndNode, DAG.getConstant(0, MVT::i8)); 4794 4795 SDValue Hi, Lo; 4796 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4797 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4798 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4799 4800 if (Op.getOpcode() == ISD::SHL_PARTS) { 4801 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4802 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4803 } else { 4804 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4805 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4806 } 4807 4808 SDValue Ops[2] = { Lo, Hi }; 4809 return DAG.getMergeValues(Ops, 2, dl); 4810} 4811 4812SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4813 EVT SrcVT = Op.getOperand(0).getValueType(); 4814 4815 if (SrcVT.isVector()) { 4816 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 4817 return Op; 4818 } 4819 return SDValue(); 4820 } 4821 4822 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4823 "Unknown SINT_TO_FP to lower!"); 4824 4825 // These are really Legal; return the operand so the caller accepts it as 4826 // Legal. 4827 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4828 return Op; 4829 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 4830 Subtarget->is64Bit()) { 4831 return Op; 4832 } 4833 4834 DebugLoc dl = Op.getDebugLoc(); 4835 unsigned Size = SrcVT.getSizeInBits()/8; 4836 MachineFunction &MF = DAG.getMachineFunction(); 4837 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4838 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4839 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 4840 StackSlot, 4841 PseudoSourceValue::getFixedStack(SSFI), 0); 4842 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 4843} 4844 4845SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 4846 SDValue StackSlot, 4847 SelectionDAG &DAG) { 4848 // Build the FILD 4849 DebugLoc dl = Op.getDebugLoc(); 4850 SDVTList Tys; 4851 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4852 if (useSSE) 4853 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4854 else 4855 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4856 SmallVector<SDValue, 8> Ops; 4857 Ops.push_back(Chain); 4858 Ops.push_back(StackSlot); 4859 Ops.push_back(DAG.getValueType(SrcVT)); 4860 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 4861 Tys, &Ops[0], Ops.size()); 4862 4863 if (useSSE) { 4864 Chain = Result.getValue(1); 4865 SDValue InFlag = Result.getValue(2); 4866 4867 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4868 // shouldn't be necessary except that RFP cannot be live across 4869 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4870 MachineFunction &MF = DAG.getMachineFunction(); 4871 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4872 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4873 Tys = DAG.getVTList(MVT::Other); 4874 SmallVector<SDValue, 8> Ops; 4875 Ops.push_back(Chain); 4876 Ops.push_back(Result); 4877 Ops.push_back(StackSlot); 4878 Ops.push_back(DAG.getValueType(Op.getValueType())); 4879 Ops.push_back(InFlag); 4880 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size()); 4881 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 4882 PseudoSourceValue::getFixedStack(SSFI), 0); 4883 } 4884 4885 return Result; 4886} 4887 4888// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 4889SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 4890 // This algorithm is not obvious. Here it is in C code, more or less: 4891 /* 4892 double uint64_to_double( uint32_t hi, uint32_t lo ) { 4893 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 4894 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 4895 4896 // Copy ints to xmm registers. 4897 __m128i xh = _mm_cvtsi32_si128( hi ); 4898 __m128i xl = _mm_cvtsi32_si128( lo ); 4899 4900 // Combine into low half of a single xmm register. 4901 __m128i x = _mm_unpacklo_epi32( xh, xl ); 4902 __m128d d; 4903 double sd; 4904 4905 // Merge in appropriate exponents to give the integer bits the right 4906 // magnitude. 4907 x = _mm_unpacklo_epi32( x, exp ); 4908 4909 // Subtract away the biases to deal with the IEEE-754 double precision 4910 // implicit 1. 4911 d = _mm_sub_pd( (__m128d) x, bias ); 4912 4913 // All conversions up to here are exact. The correctly rounded result is 4914 // calculated using the current rounding mode using the following 4915 // horizontal add. 4916 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 4917 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 4918 // store doesn't really need to be here (except 4919 // maybe to zero the other double) 4920 return sd; 4921 } 4922 */ 4923 4924 DebugLoc dl = Op.getDebugLoc(); 4925 LLVMContext *Context = DAG.getContext(); 4926 4927 // Build some magic constants. 4928 std::vector<Constant*> CV0; 4929 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 4930 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 4931 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 4932 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 4933 Constant *C0 = ConstantVector::get(CV0); 4934 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 4935 4936 std::vector<Constant*> CV1; 4937 CV1.push_back( 4938 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 4939 CV1.push_back( 4940 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 4941 Constant *C1 = ConstantVector::get(CV1); 4942 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 4943 4944 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4945 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4946 Op.getOperand(0), 4947 DAG.getIntPtrConstant(1))); 4948 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4949 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4950 Op.getOperand(0), 4951 DAG.getIntPtrConstant(0))); 4952 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 4953 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 4954 PseudoSourceValue::getConstantPool(), 0, 4955 false, 16); 4956 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 4957 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 4958 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 4959 PseudoSourceValue::getConstantPool(), 0, 4960 false, 16); 4961 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 4962 4963 // Add the halves; easiest way is to swap them into another reg first. 4964 int ShufMask[2] = { 1, -1 }; 4965 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 4966 DAG.getUNDEF(MVT::v2f64), ShufMask); 4967 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 4968 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 4969 DAG.getIntPtrConstant(0)); 4970} 4971 4972// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 4973SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 4974 DebugLoc dl = Op.getDebugLoc(); 4975 // FP constant to bias correct the final result. 4976 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 4977 MVT::f64); 4978 4979 // Load the 32-bit value into an XMM register. 4980 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4981 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4982 Op.getOperand(0), 4983 DAG.getIntPtrConstant(0))); 4984 4985 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 4986 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 4987 DAG.getIntPtrConstant(0)); 4988 4989 // Or the load with the bias. 4990 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 4991 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 4992 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4993 MVT::v2f64, Load)), 4994 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 4995 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4996 MVT::v2f64, Bias))); 4997 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 4998 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 4999 DAG.getIntPtrConstant(0)); 5000 5001 // Subtract the bias. 5002 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5003 5004 // Handle final rounding. 5005 EVT DestVT = Op.getValueType(); 5006 5007 if (DestVT.bitsLT(MVT::f64)) { 5008 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5009 DAG.getIntPtrConstant(0)); 5010 } else if (DestVT.bitsGT(MVT::f64)) { 5011 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5012 } 5013 5014 // Handle final rounding. 5015 return Sub; 5016} 5017 5018SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5019 SDValue N0 = Op.getOperand(0); 5020 DebugLoc dl = Op.getDebugLoc(); 5021 5022 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5023 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5024 // the optimization here. 5025 if (DAG.SignBitIsZero(N0)) 5026 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5027 5028 EVT SrcVT = N0.getValueType(); 5029 if (SrcVT == MVT::i64) { 5030 // We only handle SSE2 f64 target here; caller can expand the rest. 5031 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5032 return SDValue(); 5033 5034 return LowerUINT_TO_FP_i64(Op, DAG); 5035 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5036 return LowerUINT_TO_FP_i32(Op, DAG); 5037 } 5038 5039 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5040 5041 // Make a 64-bit buffer, and use it to build an FILD. 5042 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5043 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5044 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5045 getPointerTy(), StackSlot, WordOff); 5046 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5047 StackSlot, NULL, 0); 5048 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5049 OffsetSlot, NULL, 0); 5050 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5051} 5052 5053std::pair<SDValue,SDValue> X86TargetLowering:: 5054FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5055 DebugLoc dl = Op.getDebugLoc(); 5056 5057 EVT DstTy = Op.getValueType(); 5058 5059 if (!IsSigned) { 5060 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5061 DstTy = MVT::i64; 5062 } 5063 5064 assert(DstTy.getSimpleVT() <= MVT::i64 && 5065 DstTy.getSimpleVT() >= MVT::i16 && 5066 "Unknown FP_TO_SINT to lower!"); 5067 5068 // These are really Legal. 5069 if (DstTy == MVT::i32 && 5070 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5071 return std::make_pair(SDValue(), SDValue()); 5072 if (Subtarget->is64Bit() && 5073 DstTy == MVT::i64 && 5074 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5075 return std::make_pair(SDValue(), SDValue()); 5076 5077 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5078 // stack slot. 5079 MachineFunction &MF = DAG.getMachineFunction(); 5080 unsigned MemSize = DstTy.getSizeInBits()/8; 5081 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5082 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5083 5084 unsigned Opc; 5085 switch (DstTy.getSimpleVT().SimpleTy) { 5086 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5087 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5088 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5089 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5090 } 5091 5092 SDValue Chain = DAG.getEntryNode(); 5093 SDValue Value = Op.getOperand(0); 5094 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5095 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5096 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5097 PseudoSourceValue::getFixedStack(SSFI), 0); 5098 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5099 SDValue Ops[] = { 5100 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5101 }; 5102 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5103 Chain = Value.getValue(1); 5104 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5105 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5106 } 5107 5108 // Build the FP_TO_INT*_IN_MEM 5109 SDValue Ops[] = { Chain, Value, StackSlot }; 5110 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5111 5112 return std::make_pair(FIST, StackSlot); 5113} 5114 5115SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5116 if (Op.getValueType().isVector()) { 5117 if (Op.getValueType() == MVT::v2i32 && 5118 Op.getOperand(0).getValueType() == MVT::v2f64) { 5119 return Op; 5120 } 5121 return SDValue(); 5122 } 5123 5124 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5125 SDValue FIST = Vals.first, StackSlot = Vals.second; 5126 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5127 if (FIST.getNode() == 0) return Op; 5128 5129 // Load the result. 5130 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5131 FIST, StackSlot, NULL, 0); 5132} 5133 5134SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5135 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5136 SDValue FIST = Vals.first, StackSlot = Vals.second; 5137 assert(FIST.getNode() && "Unexpected failure"); 5138 5139 // Load the result. 5140 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5141 FIST, StackSlot, NULL, 0); 5142} 5143 5144SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5145 LLVMContext *Context = DAG.getContext(); 5146 DebugLoc dl = Op.getDebugLoc(); 5147 EVT VT = Op.getValueType(); 5148 EVT EltVT = VT; 5149 if (VT.isVector()) 5150 EltVT = VT.getVectorElementType(); 5151 std::vector<Constant*> CV; 5152 if (EltVT == MVT::f64) { 5153 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5154 CV.push_back(C); 5155 CV.push_back(C); 5156 } else { 5157 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5158 CV.push_back(C); 5159 CV.push_back(C); 5160 CV.push_back(C); 5161 CV.push_back(C); 5162 } 5163 Constant *C = ConstantVector::get(CV); 5164 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5165 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5166 PseudoSourceValue::getConstantPool(), 0, 5167 false, 16); 5168 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5169} 5170 5171SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5172 LLVMContext *Context = DAG.getContext(); 5173 DebugLoc dl = Op.getDebugLoc(); 5174 EVT VT = Op.getValueType(); 5175 EVT EltVT = VT; 5176 unsigned EltNum = 1; 5177 if (VT.isVector()) { 5178 EltVT = VT.getVectorElementType(); 5179 EltNum = VT.getVectorNumElements(); 5180 } 5181 std::vector<Constant*> CV; 5182 if (EltVT == MVT::f64) { 5183 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5184 CV.push_back(C); 5185 CV.push_back(C); 5186 } else { 5187 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5188 CV.push_back(C); 5189 CV.push_back(C); 5190 CV.push_back(C); 5191 CV.push_back(C); 5192 } 5193 Constant *C = ConstantVector::get(CV); 5194 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5195 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5196 PseudoSourceValue::getConstantPool(), 0, 5197 false, 16); 5198 if (VT.isVector()) { 5199 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5200 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5201 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5202 Op.getOperand(0)), 5203 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5204 } else { 5205 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5206 } 5207} 5208 5209SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5210 LLVMContext *Context = DAG.getContext(); 5211 SDValue Op0 = Op.getOperand(0); 5212 SDValue Op1 = Op.getOperand(1); 5213 DebugLoc dl = Op.getDebugLoc(); 5214 EVT VT = Op.getValueType(); 5215 EVT SrcVT = Op1.getValueType(); 5216 5217 // If second operand is smaller, extend it first. 5218 if (SrcVT.bitsLT(VT)) { 5219 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5220 SrcVT = VT; 5221 } 5222 // And if it is bigger, shrink it first. 5223 if (SrcVT.bitsGT(VT)) { 5224 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5225 SrcVT = VT; 5226 } 5227 5228 // At this point the operands and the result should have the same 5229 // type, and that won't be f80 since that is not custom lowered. 5230 5231 // First get the sign bit of second operand. 5232 std::vector<Constant*> CV; 5233 if (SrcVT == MVT::f64) { 5234 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5235 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5236 } else { 5237 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5238 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5239 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5240 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5241 } 5242 Constant *C = ConstantVector::get(CV); 5243 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5244 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5245 PseudoSourceValue::getConstantPool(), 0, 5246 false, 16); 5247 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5248 5249 // Shift sign bit right or left if the two operands have different types. 5250 if (SrcVT.bitsGT(VT)) { 5251 // Op0 is MVT::f32, Op1 is MVT::f64. 5252 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5253 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5254 DAG.getConstant(32, MVT::i32)); 5255 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5256 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5257 DAG.getIntPtrConstant(0)); 5258 } 5259 5260 // Clear first operand sign bit. 5261 CV.clear(); 5262 if (VT == MVT::f64) { 5263 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5264 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5265 } else { 5266 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5267 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5268 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5269 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5270 } 5271 C = ConstantVector::get(CV); 5272 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5273 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5274 PseudoSourceValue::getConstantPool(), 0, 5275 false, 16); 5276 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5277 5278 // Or the value with the sign bit. 5279 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5280} 5281 5282/// Emit nodes that will be selected as "test Op0,Op0", or something 5283/// equivalent. 5284SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5285 SelectionDAG &DAG) { 5286 DebugLoc dl = Op.getDebugLoc(); 5287 5288 // CF and OF aren't always set the way we want. Determine which 5289 // of these we need. 5290 bool NeedCF = false; 5291 bool NeedOF = false; 5292 switch (X86CC) { 5293 case X86::COND_A: case X86::COND_AE: 5294 case X86::COND_B: case X86::COND_BE: 5295 NeedCF = true; 5296 break; 5297 case X86::COND_G: case X86::COND_GE: 5298 case X86::COND_L: case X86::COND_LE: 5299 case X86::COND_O: case X86::COND_NO: 5300 NeedOF = true; 5301 break; 5302 default: break; 5303 } 5304 5305 // See if we can use the EFLAGS value from the operand instead of 5306 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5307 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5308 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5309 unsigned Opcode = 0; 5310 unsigned NumOperands = 0; 5311 switch (Op.getNode()->getOpcode()) { 5312 case ISD::ADD: 5313 // Due to an isel shortcoming, be conservative if this add is likely to 5314 // be selected as part of a load-modify-store instruction. When the root 5315 // node in a match is a store, isel doesn't know how to remap non-chain 5316 // non-flag uses of other nodes in the match, such as the ADD in this 5317 // case. This leads to the ADD being left around and reselected, with 5318 // the result being two adds in the output. 5319 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5320 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5321 if (UI->getOpcode() == ISD::STORE) 5322 goto default_case; 5323 if (ConstantSDNode *C = 5324 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5325 // An add of one will be selected as an INC. 5326 if (C->getAPIntValue() == 1) { 5327 Opcode = X86ISD::INC; 5328 NumOperands = 1; 5329 break; 5330 } 5331 // An add of negative one (subtract of one) will be selected as a DEC. 5332 if (C->getAPIntValue().isAllOnesValue()) { 5333 Opcode = X86ISD::DEC; 5334 NumOperands = 1; 5335 break; 5336 } 5337 } 5338 // Otherwise use a regular EFLAGS-setting add. 5339 Opcode = X86ISD::ADD; 5340 NumOperands = 2; 5341 break; 5342 case ISD::SUB: 5343 // Due to the ISEL shortcoming noted above, be conservative if this sub is 5344 // likely to be selected as part of a load-modify-store instruction. 5345 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5346 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5347 if (UI->getOpcode() == ISD::STORE) 5348 goto default_case; 5349 // Otherwise use a regular EFLAGS-setting sub. 5350 Opcode = X86ISD::SUB; 5351 NumOperands = 2; 5352 break; 5353 case X86ISD::ADD: 5354 case X86ISD::SUB: 5355 case X86ISD::INC: 5356 case X86ISD::DEC: 5357 return SDValue(Op.getNode(), 1); 5358 default: 5359 default_case: 5360 break; 5361 } 5362 if (Opcode != 0) { 5363 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5364 SmallVector<SDValue, 4> Ops; 5365 for (unsigned i = 0; i != NumOperands; ++i) 5366 Ops.push_back(Op.getOperand(i)); 5367 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5368 DAG.ReplaceAllUsesWith(Op, New); 5369 return SDValue(New.getNode(), 1); 5370 } 5371 } 5372 5373 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5374 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5375 DAG.getConstant(0, Op.getValueType())); 5376} 5377 5378/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5379/// equivalent. 5380SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5381 SelectionDAG &DAG) { 5382 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5383 if (C->getAPIntValue() == 0) 5384 return EmitTest(Op0, X86CC, DAG); 5385 5386 DebugLoc dl = Op0.getDebugLoc(); 5387 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5388} 5389 5390SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5391 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5392 SDValue Op0 = Op.getOperand(0); 5393 SDValue Op1 = Op.getOperand(1); 5394 DebugLoc dl = Op.getDebugLoc(); 5395 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5396 5397 // Lower (X & (1 << N)) == 0 to BT(X, N). 5398 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5399 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5400 if (Op0.getOpcode() == ISD::AND && 5401 Op0.hasOneUse() && 5402 Op1.getOpcode() == ISD::Constant && 5403 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5404 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5405 SDValue LHS, RHS; 5406 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5407 if (ConstantSDNode *Op010C = 5408 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5409 if (Op010C->getZExtValue() == 1) { 5410 LHS = Op0.getOperand(0); 5411 RHS = Op0.getOperand(1).getOperand(1); 5412 } 5413 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5414 if (ConstantSDNode *Op000C = 5415 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5416 if (Op000C->getZExtValue() == 1) { 5417 LHS = Op0.getOperand(1); 5418 RHS = Op0.getOperand(0).getOperand(1); 5419 } 5420 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5421 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5422 SDValue AndLHS = Op0.getOperand(0); 5423 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5424 LHS = AndLHS.getOperand(0); 5425 RHS = AndLHS.getOperand(1); 5426 } 5427 } 5428 5429 if (LHS.getNode()) { 5430 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5431 // instruction. Since the shift amount is in-range-or-undefined, we know 5432 // that doing a bittest on the i16 value is ok. We extend to i32 because 5433 // the encoding for the i16 version is larger than the i32 version. 5434 if (LHS.getValueType() == MVT::i8) 5435 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5436 5437 // If the operand types disagree, extend the shift amount to match. Since 5438 // BT ignores high bits (like shifts) we can use anyextend. 5439 if (LHS.getValueType() != RHS.getValueType()) 5440 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5441 5442 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5443 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5444 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5445 DAG.getConstant(Cond, MVT::i8), BT); 5446 } 5447 } 5448 5449 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5450 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5451 5452 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 5453 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5454 DAG.getConstant(X86CC, MVT::i8), Cond); 5455} 5456 5457SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5458 SDValue Cond; 5459 SDValue Op0 = Op.getOperand(0); 5460 SDValue Op1 = Op.getOperand(1); 5461 SDValue CC = Op.getOperand(2); 5462 EVT VT = Op.getValueType(); 5463 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5464 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5465 DebugLoc dl = Op.getDebugLoc(); 5466 5467 if (isFP) { 5468 unsigned SSECC = 8; 5469 EVT VT0 = Op0.getValueType(); 5470 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5471 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5472 bool Swap = false; 5473 5474 switch (SetCCOpcode) { 5475 default: break; 5476 case ISD::SETOEQ: 5477 case ISD::SETEQ: SSECC = 0; break; 5478 case ISD::SETOGT: 5479 case ISD::SETGT: Swap = true; // Fallthrough 5480 case ISD::SETLT: 5481 case ISD::SETOLT: SSECC = 1; break; 5482 case ISD::SETOGE: 5483 case ISD::SETGE: Swap = true; // Fallthrough 5484 case ISD::SETLE: 5485 case ISD::SETOLE: SSECC = 2; break; 5486 case ISD::SETUO: SSECC = 3; break; 5487 case ISD::SETUNE: 5488 case ISD::SETNE: SSECC = 4; break; 5489 case ISD::SETULE: Swap = true; 5490 case ISD::SETUGE: SSECC = 5; break; 5491 case ISD::SETULT: Swap = true; 5492 case ISD::SETUGT: SSECC = 6; break; 5493 case ISD::SETO: SSECC = 7; break; 5494 } 5495 if (Swap) 5496 std::swap(Op0, Op1); 5497 5498 // In the two special cases we can't handle, emit two comparisons. 5499 if (SSECC == 8) { 5500 if (SetCCOpcode == ISD::SETUEQ) { 5501 SDValue UNORD, EQ; 5502 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5503 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5504 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 5505 } 5506 else if (SetCCOpcode == ISD::SETONE) { 5507 SDValue ORD, NEQ; 5508 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5509 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5510 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 5511 } 5512 llvm_unreachable("Illegal FP comparison"); 5513 } 5514 // Handle all other FP comparisons here. 5515 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5516 } 5517 5518 // We are handling one of the integer comparisons here. Since SSE only has 5519 // GT and EQ comparisons for integer, swapping operands and multiple 5520 // operations may be required for some comparisons. 5521 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5522 bool Swap = false, Invert = false, FlipSigns = false; 5523 5524 switch (VT.getSimpleVT().SimpleTy) { 5525 default: break; 5526 case MVT::v8i8: 5527 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5528 case MVT::v4i16: 5529 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5530 case MVT::v2i32: 5531 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5532 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5533 } 5534 5535 switch (SetCCOpcode) { 5536 default: break; 5537 case ISD::SETNE: Invert = true; 5538 case ISD::SETEQ: Opc = EQOpc; break; 5539 case ISD::SETLT: Swap = true; 5540 case ISD::SETGT: Opc = GTOpc; break; 5541 case ISD::SETGE: Swap = true; 5542 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5543 case ISD::SETULT: Swap = true; 5544 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5545 case ISD::SETUGE: Swap = true; 5546 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5547 } 5548 if (Swap) 5549 std::swap(Op0, Op1); 5550 5551 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5552 // bits of the inputs before performing those operations. 5553 if (FlipSigns) { 5554 EVT EltVT = VT.getVectorElementType(); 5555 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 5556 EltVT); 5557 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5558 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 5559 SignBits.size()); 5560 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 5561 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 5562 } 5563 5564 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 5565 5566 // If the logical-not of the result is required, perform that now. 5567 if (Invert) 5568 Result = DAG.getNOT(dl, Result, VT); 5569 5570 return Result; 5571} 5572 5573// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5574static bool isX86LogicalCmp(SDValue Op) { 5575 unsigned Opc = Op.getNode()->getOpcode(); 5576 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 5577 return true; 5578 if (Op.getResNo() == 1 && 5579 (Opc == X86ISD::ADD || 5580 Opc == X86ISD::SUB || 5581 Opc == X86ISD::SMUL || 5582 Opc == X86ISD::UMUL || 5583 Opc == X86ISD::INC || 5584 Opc == X86ISD::DEC)) 5585 return true; 5586 5587 return false; 5588} 5589 5590SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5591 bool addTest = true; 5592 SDValue Cond = Op.getOperand(0); 5593 DebugLoc dl = Op.getDebugLoc(); 5594 SDValue CC; 5595 5596 if (Cond.getOpcode() == ISD::SETCC) 5597 Cond = LowerSETCC(Cond, DAG); 5598 5599 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5600 // setting operand in place of the X86ISD::SETCC. 5601 if (Cond.getOpcode() == X86ISD::SETCC) { 5602 CC = Cond.getOperand(0); 5603 5604 SDValue Cmp = Cond.getOperand(1); 5605 unsigned Opc = Cmp.getOpcode(); 5606 EVT VT = Op.getValueType(); 5607 5608 bool IllegalFPCMov = false; 5609 if (VT.isFloatingPoint() && !VT.isVector() && 5610 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5611 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5612 5613 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 5614 Opc == X86ISD::BT) { // FIXME 5615 Cond = Cmp; 5616 addTest = false; 5617 } 5618 } 5619 5620 if (addTest) { 5621 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5622 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5623 } 5624 5625 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 5626 SmallVector<SDValue, 4> Ops; 5627 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5628 // condition is true. 5629 Ops.push_back(Op.getOperand(2)); 5630 Ops.push_back(Op.getOperand(1)); 5631 Ops.push_back(CC); 5632 Ops.push_back(Cond); 5633 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size()); 5634} 5635 5636// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5637// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5638// from the AND / OR. 5639static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5640 Opc = Op.getOpcode(); 5641 if (Opc != ISD::OR && Opc != ISD::AND) 5642 return false; 5643 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5644 Op.getOperand(0).hasOneUse() && 5645 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5646 Op.getOperand(1).hasOneUse()); 5647} 5648 5649// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 5650// 1 and that the SETCC node has a single use. 5651static bool isXor1OfSetCC(SDValue Op) { 5652 if (Op.getOpcode() != ISD::XOR) 5653 return false; 5654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5655 if (N1C && N1C->getAPIntValue() == 1) { 5656 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5657 Op.getOperand(0).hasOneUse(); 5658 } 5659 return false; 5660} 5661 5662SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5663 bool addTest = true; 5664 SDValue Chain = Op.getOperand(0); 5665 SDValue Cond = Op.getOperand(1); 5666 SDValue Dest = Op.getOperand(2); 5667 DebugLoc dl = Op.getDebugLoc(); 5668 SDValue CC; 5669 5670 if (Cond.getOpcode() == ISD::SETCC) 5671 Cond = LowerSETCC(Cond, DAG); 5672#if 0 5673 // FIXME: LowerXALUO doesn't handle these!! 5674 else if (Cond.getOpcode() == X86ISD::ADD || 5675 Cond.getOpcode() == X86ISD::SUB || 5676 Cond.getOpcode() == X86ISD::SMUL || 5677 Cond.getOpcode() == X86ISD::UMUL) 5678 Cond = LowerXALUO(Cond, DAG); 5679#endif 5680 5681 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5682 // setting operand in place of the X86ISD::SETCC. 5683 if (Cond.getOpcode() == X86ISD::SETCC) { 5684 CC = Cond.getOperand(0); 5685 5686 SDValue Cmp = Cond.getOperand(1); 5687 unsigned Opc = Cmp.getOpcode(); 5688 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 5689 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 5690 Cond = Cmp; 5691 addTest = false; 5692 } else { 5693 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5694 default: break; 5695 case X86::COND_O: 5696 case X86::COND_B: 5697 // These can only come from an arithmetic instruction with overflow, 5698 // e.g. SADDO, UADDO. 5699 Cond = Cond.getNode()->getOperand(1); 5700 addTest = false; 5701 break; 5702 } 5703 } 5704 } else { 5705 unsigned CondOpc; 5706 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5707 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5708 if (CondOpc == ISD::OR) { 5709 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5710 // two branches instead of an explicit OR instruction with a 5711 // separate test. 5712 if (Cmp == Cond.getOperand(1).getOperand(1) && 5713 isX86LogicalCmp(Cmp)) { 5714 CC = Cond.getOperand(0).getOperand(0); 5715 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5716 Chain, Dest, CC, Cmp); 5717 CC = Cond.getOperand(1).getOperand(0); 5718 Cond = Cmp; 5719 addTest = false; 5720 } 5721 } else { // ISD::AND 5722 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5723 // two branches instead of an explicit AND instruction with a 5724 // separate test. However, we only do this if this block doesn't 5725 // have a fall-through edge, because this requires an explicit 5726 // jmp when the condition is false. 5727 if (Cmp == Cond.getOperand(1).getOperand(1) && 5728 isX86LogicalCmp(Cmp) && 5729 Op.getNode()->hasOneUse()) { 5730 X86::CondCode CCode = 5731 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5732 CCode = X86::GetOppositeBranchCondition(CCode); 5733 CC = DAG.getConstant(CCode, MVT::i8); 5734 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5735 // Look for an unconditional branch following this conditional branch. 5736 // We need this because we need to reverse the successors in order 5737 // to implement FCMP_OEQ. 5738 if (User.getOpcode() == ISD::BR) { 5739 SDValue FalseBB = User.getOperand(1); 5740 SDValue NewBR = 5741 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5742 assert(NewBR == User); 5743 Dest = FalseBB; 5744 5745 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5746 Chain, Dest, CC, Cmp); 5747 X86::CondCode CCode = 5748 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5749 CCode = X86::GetOppositeBranchCondition(CCode); 5750 CC = DAG.getConstant(CCode, MVT::i8); 5751 Cond = Cmp; 5752 addTest = false; 5753 } 5754 } 5755 } 5756 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 5757 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 5758 // It should be transformed during dag combiner except when the condition 5759 // is set by a arithmetics with overflow node. 5760 X86::CondCode CCode = 5761 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5762 CCode = X86::GetOppositeBranchCondition(CCode); 5763 CC = DAG.getConstant(CCode, MVT::i8); 5764 Cond = Cond.getOperand(0).getOperand(1); 5765 addTest = false; 5766 } 5767 } 5768 5769 if (addTest) { 5770 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5771 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5772 } 5773 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5774 Chain, Dest, CC, Cond); 5775} 5776 5777 5778// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5779// Calls to _alloca is needed to probe the stack when allocating more than 4k 5780// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5781// that the guard pages used by the OS virtual memory manager are allocated in 5782// correct sequence. 5783SDValue 5784X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5785 SelectionDAG &DAG) { 5786 assert(Subtarget->isTargetCygMing() && 5787 "This should be used only on Cygwin/Mingw targets"); 5788 DebugLoc dl = Op.getDebugLoc(); 5789 5790 // Get the inputs. 5791 SDValue Chain = Op.getOperand(0); 5792 SDValue Size = Op.getOperand(1); 5793 // FIXME: Ensure alignment here 5794 5795 SDValue Flag; 5796 5797 EVT IntPtr = getPointerTy(); 5798 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5799 5800 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5801 5802 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 5803 Flag = Chain.getValue(1); 5804 5805 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5806 SDValue Ops[] = { Chain, 5807 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5808 DAG.getRegister(X86::EAX, IntPtr), 5809 DAG.getRegister(X86StackPtr, SPTy), 5810 Flag }; 5811 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 5812 Flag = Chain.getValue(1); 5813 5814 Chain = DAG.getCALLSEQ_END(Chain, 5815 DAG.getIntPtrConstant(0, true), 5816 DAG.getIntPtrConstant(0, true), 5817 Flag); 5818 5819 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 5820 5821 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5822 return DAG.getMergeValues(Ops1, 2, dl); 5823} 5824 5825SDValue 5826X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 5827 SDValue Chain, 5828 SDValue Dst, SDValue Src, 5829 SDValue Size, unsigned Align, 5830 const Value *DstSV, 5831 uint64_t DstSVOff) { 5832 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5833 5834 // If not DWORD aligned or size is more than the threshold, call the library. 5835 // The libc version is likely to be faster for these cases. It can use the 5836 // address value and run time information about the CPU. 5837 if ((Align & 3) != 0 || 5838 !ConstantSize || 5839 ConstantSize->getZExtValue() > 5840 getSubtarget()->getMaxInlineSizeThreshold()) { 5841 SDValue InFlag(0, 0); 5842 5843 // Check to see if there is a specialized entry-point for memory zeroing. 5844 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5845 5846 if (const char *bzeroEntry = V && 5847 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5848 EVT IntPtr = getPointerTy(); 5849 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 5850 TargetLowering::ArgListTy Args; 5851 TargetLowering::ArgListEntry Entry; 5852 Entry.Node = Dst; 5853 Entry.Ty = IntPtrTy; 5854 Args.push_back(Entry); 5855 Entry.Node = Size; 5856 Args.push_back(Entry); 5857 std::pair<SDValue,SDValue> CallResult = 5858 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 5859 false, false, false, false, 5860 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 5861 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 5862 return CallResult.second; 5863 } 5864 5865 // Otherwise have the target-independent code call memset. 5866 return SDValue(); 5867 } 5868 5869 uint64_t SizeVal = ConstantSize->getZExtValue(); 5870 SDValue InFlag(0, 0); 5871 EVT AVT; 5872 SDValue Count; 5873 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5874 unsigned BytesLeft = 0; 5875 bool TwoRepStos = false; 5876 if (ValC) { 5877 unsigned ValReg; 5878 uint64_t Val = ValC->getZExtValue() & 255; 5879 5880 // If the value is a constant, then we can potentially use larger sets. 5881 switch (Align & 3) { 5882 case 2: // WORD aligned 5883 AVT = MVT::i16; 5884 ValReg = X86::AX; 5885 Val = (Val << 8) | Val; 5886 break; 5887 case 0: // DWORD aligned 5888 AVT = MVT::i32; 5889 ValReg = X86::EAX; 5890 Val = (Val << 8) | Val; 5891 Val = (Val << 16) | Val; 5892 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5893 AVT = MVT::i64; 5894 ValReg = X86::RAX; 5895 Val = (Val << 32) | Val; 5896 } 5897 break; 5898 default: // Byte aligned 5899 AVT = MVT::i8; 5900 ValReg = X86::AL; 5901 Count = DAG.getIntPtrConstant(SizeVal); 5902 break; 5903 } 5904 5905 if (AVT.bitsGT(MVT::i8)) { 5906 unsigned UBytes = AVT.getSizeInBits() / 8; 5907 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5908 BytesLeft = SizeVal % UBytes; 5909 } 5910 5911 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 5912 InFlag); 5913 InFlag = Chain.getValue(1); 5914 } else { 5915 AVT = MVT::i8; 5916 Count = DAG.getIntPtrConstant(SizeVal); 5917 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 5918 InFlag = Chain.getValue(1); 5919 } 5920 5921 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5922 X86::ECX, 5923 Count, InFlag); 5924 InFlag = Chain.getValue(1); 5925 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5926 X86::EDI, 5927 Dst, InFlag); 5928 InFlag = Chain.getValue(1); 5929 5930 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5931 SmallVector<SDValue, 8> Ops; 5932 Ops.push_back(Chain); 5933 Ops.push_back(DAG.getValueType(AVT)); 5934 Ops.push_back(InFlag); 5935 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5936 5937 if (TwoRepStos) { 5938 InFlag = Chain.getValue(1); 5939 Count = Size; 5940 EVT CVT = Count.getValueType(); 5941 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 5942 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5943 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 5944 X86::ECX, 5945 Left, InFlag); 5946 InFlag = Chain.getValue(1); 5947 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5948 Ops.clear(); 5949 Ops.push_back(Chain); 5950 Ops.push_back(DAG.getValueType(MVT::i8)); 5951 Ops.push_back(InFlag); 5952 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5953 } else if (BytesLeft) { 5954 // Handle the last 1 - 7 bytes. 5955 unsigned Offset = SizeVal - BytesLeft; 5956 EVT AddrVT = Dst.getValueType(); 5957 EVT SizeVT = Size.getValueType(); 5958 5959 Chain = DAG.getMemset(Chain, dl, 5960 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 5961 DAG.getConstant(Offset, AddrVT)), 5962 Src, 5963 DAG.getConstant(BytesLeft, SizeVT), 5964 Align, DstSV, DstSVOff + Offset); 5965 } 5966 5967 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5968 return Chain; 5969} 5970 5971SDValue 5972X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 5973 SDValue Chain, SDValue Dst, SDValue Src, 5974 SDValue Size, unsigned Align, 5975 bool AlwaysInline, 5976 const Value *DstSV, uint64_t DstSVOff, 5977 const Value *SrcSV, uint64_t SrcSVOff) { 5978 // This requires the copy size to be a constant, preferrably 5979 // within a subtarget-specific limit. 5980 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5981 if (!ConstantSize) 5982 return SDValue(); 5983 uint64_t SizeVal = ConstantSize->getZExtValue(); 5984 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5985 return SDValue(); 5986 5987 /// If not DWORD aligned, call the library. 5988 if ((Align & 3) != 0) 5989 return SDValue(); 5990 5991 // DWORD aligned 5992 EVT AVT = MVT::i32; 5993 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5994 AVT = MVT::i64; 5995 5996 unsigned UBytes = AVT.getSizeInBits() / 8; 5997 unsigned CountVal = SizeVal / UBytes; 5998 SDValue Count = DAG.getIntPtrConstant(CountVal); 5999 unsigned BytesLeft = SizeVal % UBytes; 6000 6001 SDValue InFlag(0, 0); 6002 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6003 X86::ECX, 6004 Count, InFlag); 6005 InFlag = Chain.getValue(1); 6006 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6007 X86::EDI, 6008 Dst, InFlag); 6009 InFlag = Chain.getValue(1); 6010 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6011 X86::ESI, 6012 Src, InFlag); 6013 InFlag = Chain.getValue(1); 6014 6015 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6016 SmallVector<SDValue, 8> Ops; 6017 Ops.push_back(Chain); 6018 Ops.push_back(DAG.getValueType(AVT)); 6019 Ops.push_back(InFlag); 6020 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size()); 6021 6022 SmallVector<SDValue, 4> Results; 6023 Results.push_back(RepMovs); 6024 if (BytesLeft) { 6025 // Handle the last 1 - 7 bytes. 6026 unsigned Offset = SizeVal - BytesLeft; 6027 EVT DstVT = Dst.getValueType(); 6028 EVT SrcVT = Src.getValueType(); 6029 EVT SizeVT = Size.getValueType(); 6030 Results.push_back(DAG.getMemcpy(Chain, dl, 6031 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6032 DAG.getConstant(Offset, DstVT)), 6033 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6034 DAG.getConstant(Offset, SrcVT)), 6035 DAG.getConstant(BytesLeft, SizeVT), 6036 Align, AlwaysInline, 6037 DstSV, DstSVOff + Offset, 6038 SrcSV, SrcSVOff + Offset)); 6039 } 6040 6041 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6042 &Results[0], Results.size()); 6043} 6044 6045SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6046 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6047 DebugLoc dl = Op.getDebugLoc(); 6048 6049 if (!Subtarget->is64Bit()) { 6050 // vastart just stores the address of the VarArgsFrameIndex slot into the 6051 // memory location argument. 6052 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6053 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 6054 } 6055 6056 // __va_list_tag: 6057 // gp_offset (0 - 6 * 8) 6058 // fp_offset (48 - 48 + 8 * 16) 6059 // overflow_arg_area (point to parameters coming in memory). 6060 // reg_save_area 6061 SmallVector<SDValue, 8> MemOps; 6062 SDValue FIN = Op.getOperand(1); 6063 // Store gp_offset 6064 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6065 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6066 FIN, SV, 0); 6067 MemOps.push_back(Store); 6068 6069 // Store fp_offset 6070 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6071 FIN, DAG.getIntPtrConstant(4)); 6072 Store = DAG.getStore(Op.getOperand(0), dl, 6073 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6074 FIN, SV, 0); 6075 MemOps.push_back(Store); 6076 6077 // Store ptr to overflow_arg_area 6078 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6079 FIN, DAG.getIntPtrConstant(4)); 6080 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6081 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0); 6082 MemOps.push_back(Store); 6083 6084 // Store ptr to reg_save_area. 6085 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6086 FIN, DAG.getIntPtrConstant(8)); 6087 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6088 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); 6089 MemOps.push_back(Store); 6090 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6091 &MemOps[0], MemOps.size()); 6092} 6093 6094SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6095 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6096 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6097 SDValue Chain = Op.getOperand(0); 6098 SDValue SrcPtr = Op.getOperand(1); 6099 SDValue SrcSV = Op.getOperand(2); 6100 6101 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6102 return SDValue(); 6103} 6104 6105SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6106 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6107 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6108 SDValue Chain = Op.getOperand(0); 6109 SDValue DstPtr = Op.getOperand(1); 6110 SDValue SrcPtr = Op.getOperand(2); 6111 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6112 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6113 DebugLoc dl = Op.getDebugLoc(); 6114 6115 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6116 DAG.getIntPtrConstant(24), 8, false, 6117 DstSV, 0, SrcSV, 0); 6118} 6119 6120SDValue 6121X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6122 DebugLoc dl = Op.getDebugLoc(); 6123 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6124 switch (IntNo) { 6125 default: return SDValue(); // Don't custom lower most intrinsics. 6126 // Comparison intrinsics. 6127 case Intrinsic::x86_sse_comieq_ss: 6128 case Intrinsic::x86_sse_comilt_ss: 6129 case Intrinsic::x86_sse_comile_ss: 6130 case Intrinsic::x86_sse_comigt_ss: 6131 case Intrinsic::x86_sse_comige_ss: 6132 case Intrinsic::x86_sse_comineq_ss: 6133 case Intrinsic::x86_sse_ucomieq_ss: 6134 case Intrinsic::x86_sse_ucomilt_ss: 6135 case Intrinsic::x86_sse_ucomile_ss: 6136 case Intrinsic::x86_sse_ucomigt_ss: 6137 case Intrinsic::x86_sse_ucomige_ss: 6138 case Intrinsic::x86_sse_ucomineq_ss: 6139 case Intrinsic::x86_sse2_comieq_sd: 6140 case Intrinsic::x86_sse2_comilt_sd: 6141 case Intrinsic::x86_sse2_comile_sd: 6142 case Intrinsic::x86_sse2_comigt_sd: 6143 case Intrinsic::x86_sse2_comige_sd: 6144 case Intrinsic::x86_sse2_comineq_sd: 6145 case Intrinsic::x86_sse2_ucomieq_sd: 6146 case Intrinsic::x86_sse2_ucomilt_sd: 6147 case Intrinsic::x86_sse2_ucomile_sd: 6148 case Intrinsic::x86_sse2_ucomigt_sd: 6149 case Intrinsic::x86_sse2_ucomige_sd: 6150 case Intrinsic::x86_sse2_ucomineq_sd: { 6151 unsigned Opc = 0; 6152 ISD::CondCode CC = ISD::SETCC_INVALID; 6153 switch (IntNo) { 6154 default: break; 6155 case Intrinsic::x86_sse_comieq_ss: 6156 case Intrinsic::x86_sse2_comieq_sd: 6157 Opc = X86ISD::COMI; 6158 CC = ISD::SETEQ; 6159 break; 6160 case Intrinsic::x86_sse_comilt_ss: 6161 case Intrinsic::x86_sse2_comilt_sd: 6162 Opc = X86ISD::COMI; 6163 CC = ISD::SETLT; 6164 break; 6165 case Intrinsic::x86_sse_comile_ss: 6166 case Intrinsic::x86_sse2_comile_sd: 6167 Opc = X86ISD::COMI; 6168 CC = ISD::SETLE; 6169 break; 6170 case Intrinsic::x86_sse_comigt_ss: 6171 case Intrinsic::x86_sse2_comigt_sd: 6172 Opc = X86ISD::COMI; 6173 CC = ISD::SETGT; 6174 break; 6175 case Intrinsic::x86_sse_comige_ss: 6176 case Intrinsic::x86_sse2_comige_sd: 6177 Opc = X86ISD::COMI; 6178 CC = ISD::SETGE; 6179 break; 6180 case Intrinsic::x86_sse_comineq_ss: 6181 case Intrinsic::x86_sse2_comineq_sd: 6182 Opc = X86ISD::COMI; 6183 CC = ISD::SETNE; 6184 break; 6185 case Intrinsic::x86_sse_ucomieq_ss: 6186 case Intrinsic::x86_sse2_ucomieq_sd: 6187 Opc = X86ISD::UCOMI; 6188 CC = ISD::SETEQ; 6189 break; 6190 case Intrinsic::x86_sse_ucomilt_ss: 6191 case Intrinsic::x86_sse2_ucomilt_sd: 6192 Opc = X86ISD::UCOMI; 6193 CC = ISD::SETLT; 6194 break; 6195 case Intrinsic::x86_sse_ucomile_ss: 6196 case Intrinsic::x86_sse2_ucomile_sd: 6197 Opc = X86ISD::UCOMI; 6198 CC = ISD::SETLE; 6199 break; 6200 case Intrinsic::x86_sse_ucomigt_ss: 6201 case Intrinsic::x86_sse2_ucomigt_sd: 6202 Opc = X86ISD::UCOMI; 6203 CC = ISD::SETGT; 6204 break; 6205 case Intrinsic::x86_sse_ucomige_ss: 6206 case Intrinsic::x86_sse2_ucomige_sd: 6207 Opc = X86ISD::UCOMI; 6208 CC = ISD::SETGE; 6209 break; 6210 case Intrinsic::x86_sse_ucomineq_ss: 6211 case Intrinsic::x86_sse2_ucomineq_sd: 6212 Opc = X86ISD::UCOMI; 6213 CC = ISD::SETNE; 6214 break; 6215 } 6216 6217 SDValue LHS = Op.getOperand(1); 6218 SDValue RHS = Op.getOperand(2); 6219 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6220 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6221 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6222 DAG.getConstant(X86CC, MVT::i8), Cond); 6223 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6224 } 6225 // ptest intrinsics. The intrinsic these come from are designed to return 6226 // an integer value, not just an instruction so lower it to the ptest 6227 // pattern and a setcc for the result. 6228 case Intrinsic::x86_sse41_ptestz: 6229 case Intrinsic::x86_sse41_ptestc: 6230 case Intrinsic::x86_sse41_ptestnzc:{ 6231 unsigned X86CC = 0; 6232 switch (IntNo) { 6233 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6234 case Intrinsic::x86_sse41_ptestz: 6235 // ZF = 1 6236 X86CC = X86::COND_E; 6237 break; 6238 case Intrinsic::x86_sse41_ptestc: 6239 // CF = 1 6240 X86CC = X86::COND_B; 6241 break; 6242 case Intrinsic::x86_sse41_ptestnzc: 6243 // ZF and CF = 0 6244 X86CC = X86::COND_A; 6245 break; 6246 } 6247 6248 SDValue LHS = Op.getOperand(1); 6249 SDValue RHS = Op.getOperand(2); 6250 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6251 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6252 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6253 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6254 } 6255 6256 // Fix vector shift instructions where the last operand is a non-immediate 6257 // i32 value. 6258 case Intrinsic::x86_sse2_pslli_w: 6259 case Intrinsic::x86_sse2_pslli_d: 6260 case Intrinsic::x86_sse2_pslli_q: 6261 case Intrinsic::x86_sse2_psrli_w: 6262 case Intrinsic::x86_sse2_psrli_d: 6263 case Intrinsic::x86_sse2_psrli_q: 6264 case Intrinsic::x86_sse2_psrai_w: 6265 case Intrinsic::x86_sse2_psrai_d: 6266 case Intrinsic::x86_mmx_pslli_w: 6267 case Intrinsic::x86_mmx_pslli_d: 6268 case Intrinsic::x86_mmx_pslli_q: 6269 case Intrinsic::x86_mmx_psrli_w: 6270 case Intrinsic::x86_mmx_psrli_d: 6271 case Intrinsic::x86_mmx_psrli_q: 6272 case Intrinsic::x86_mmx_psrai_w: 6273 case Intrinsic::x86_mmx_psrai_d: { 6274 SDValue ShAmt = Op.getOperand(2); 6275 if (isa<ConstantSDNode>(ShAmt)) 6276 return SDValue(); 6277 6278 unsigned NewIntNo = 0; 6279 EVT ShAmtVT = MVT::v4i32; 6280 switch (IntNo) { 6281 case Intrinsic::x86_sse2_pslli_w: 6282 NewIntNo = Intrinsic::x86_sse2_psll_w; 6283 break; 6284 case Intrinsic::x86_sse2_pslli_d: 6285 NewIntNo = Intrinsic::x86_sse2_psll_d; 6286 break; 6287 case Intrinsic::x86_sse2_pslli_q: 6288 NewIntNo = Intrinsic::x86_sse2_psll_q; 6289 break; 6290 case Intrinsic::x86_sse2_psrli_w: 6291 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6292 break; 6293 case Intrinsic::x86_sse2_psrli_d: 6294 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6295 break; 6296 case Intrinsic::x86_sse2_psrli_q: 6297 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6298 break; 6299 case Intrinsic::x86_sse2_psrai_w: 6300 NewIntNo = Intrinsic::x86_sse2_psra_w; 6301 break; 6302 case Intrinsic::x86_sse2_psrai_d: 6303 NewIntNo = Intrinsic::x86_sse2_psra_d; 6304 break; 6305 default: { 6306 ShAmtVT = MVT::v2i32; 6307 switch (IntNo) { 6308 case Intrinsic::x86_mmx_pslli_w: 6309 NewIntNo = Intrinsic::x86_mmx_psll_w; 6310 break; 6311 case Intrinsic::x86_mmx_pslli_d: 6312 NewIntNo = Intrinsic::x86_mmx_psll_d; 6313 break; 6314 case Intrinsic::x86_mmx_pslli_q: 6315 NewIntNo = Intrinsic::x86_mmx_psll_q; 6316 break; 6317 case Intrinsic::x86_mmx_psrli_w: 6318 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6319 break; 6320 case Intrinsic::x86_mmx_psrli_d: 6321 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6322 break; 6323 case Intrinsic::x86_mmx_psrli_q: 6324 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6325 break; 6326 case Intrinsic::x86_mmx_psrai_w: 6327 NewIntNo = Intrinsic::x86_mmx_psra_w; 6328 break; 6329 case Intrinsic::x86_mmx_psrai_d: 6330 NewIntNo = Intrinsic::x86_mmx_psra_d; 6331 break; 6332 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6333 } 6334 break; 6335 } 6336 } 6337 EVT VT = Op.getValueType(); 6338 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, 6339 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt)); 6340 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6341 DAG.getConstant(NewIntNo, MVT::i32), 6342 Op.getOperand(1), ShAmt); 6343 } 6344 } 6345} 6346 6347SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6348 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6349 DebugLoc dl = Op.getDebugLoc(); 6350 6351 if (Depth > 0) { 6352 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6353 SDValue Offset = 6354 DAG.getConstant(TD->getPointerSize(), 6355 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6356 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6357 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6358 FrameAddr, Offset), 6359 NULL, 0); 6360 } 6361 6362 // Just load the return address. 6363 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6364 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6365 RetAddrFI, NULL, 0); 6366} 6367 6368SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6369 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6370 MFI->setFrameAddressIsTaken(true); 6371 EVT VT = Op.getValueType(); 6372 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6373 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6374 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6375 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6376 while (Depth--) 6377 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 6378 return FrameAddr; 6379} 6380 6381SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6382 SelectionDAG &DAG) { 6383 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6384} 6385 6386SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6387{ 6388 MachineFunction &MF = DAG.getMachineFunction(); 6389 SDValue Chain = Op.getOperand(0); 6390 SDValue Offset = Op.getOperand(1); 6391 SDValue Handler = Op.getOperand(2); 6392 DebugLoc dl = Op.getDebugLoc(); 6393 6394 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6395 getPointerTy()); 6396 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6397 6398 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6399 DAG.getIntPtrConstant(-TD->getPointerSize())); 6400 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 6401 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); 6402 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 6403 MF.getRegInfo().addLiveOut(StoreAddrReg); 6404 6405 return DAG.getNode(X86ISD::EH_RETURN, dl, 6406 MVT::Other, 6407 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 6408} 6409 6410SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 6411 SelectionDAG &DAG) { 6412 SDValue Root = Op.getOperand(0); 6413 SDValue Trmp = Op.getOperand(1); // trampoline 6414 SDValue FPtr = Op.getOperand(2); // nested function 6415 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 6416 DebugLoc dl = Op.getDebugLoc(); 6417 6418 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6419 6420 const X86InstrInfo *TII = 6421 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 6422 6423 if (Subtarget->is64Bit()) { 6424 SDValue OutChains[6]; 6425 6426 // Large code-model. 6427 6428 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 6429 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 6430 6431 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 6432 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 6433 6434 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 6435 6436 // Load the pointer to the nested function into R11. 6437 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 6438 SDValue Addr = Trmp; 6439 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6440 Addr, TrmpAddr, 0); 6441 6442 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6443 DAG.getConstant(2, MVT::i64)); 6444 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); 6445 6446 // Load the 'nest' parameter value into R10. 6447 // R10 is specified in X86CallingConv.td 6448 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 6449 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6450 DAG.getConstant(10, MVT::i64)); 6451 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6452 Addr, TrmpAddr, 10); 6453 6454 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6455 DAG.getConstant(12, MVT::i64)); 6456 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); 6457 6458 // Jump to the nested function. 6459 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 6460 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6461 DAG.getConstant(20, MVT::i64)); 6462 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6463 Addr, TrmpAddr, 20); 6464 6465 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 6466 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6467 DAG.getConstant(22, MVT::i64)); 6468 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 6469 TrmpAddr, 22); 6470 6471 SDValue Ops[] = 6472 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 6473 return DAG.getMergeValues(Ops, 2, dl); 6474 } else { 6475 const Function *Func = 6476 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 6477 unsigned CC = Func->getCallingConv(); 6478 unsigned NestReg; 6479 6480 switch (CC) { 6481 default: 6482 llvm_unreachable("Unsupported calling convention"); 6483 case CallingConv::C: 6484 case CallingConv::X86_StdCall: { 6485 // Pass 'nest' parameter in ECX. 6486 // Must be kept in sync with X86CallingConv.td 6487 NestReg = X86::ECX; 6488 6489 // Check that ECX wasn't needed by an 'inreg' parameter. 6490 const FunctionType *FTy = Func->getFunctionType(); 6491 const AttrListPtr &Attrs = Func->getAttributes(); 6492 6493 if (!Attrs.isEmpty() && !Func->isVarArg()) { 6494 unsigned InRegCount = 0; 6495 unsigned Idx = 1; 6496 6497 for (FunctionType::param_iterator I = FTy->param_begin(), 6498 E = FTy->param_end(); I != E; ++I, ++Idx) 6499 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 6500 // FIXME: should only count parameters that are lowered to integers. 6501 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 6502 6503 if (InRegCount > 2) { 6504 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 6505 } 6506 } 6507 break; 6508 } 6509 case CallingConv::X86_FastCall: 6510 case CallingConv::Fast: 6511 // Pass 'nest' parameter in EAX. 6512 // Must be kept in sync with X86CallingConv.td 6513 NestReg = X86::EAX; 6514 break; 6515 } 6516 6517 SDValue OutChains[4]; 6518 SDValue Addr, Disp; 6519 6520 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6521 DAG.getConstant(10, MVT::i32)); 6522 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 6523 6524 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 6525 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 6526 OutChains[0] = DAG.getStore(Root, dl, 6527 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6528 Trmp, TrmpAddr, 0); 6529 6530 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6531 DAG.getConstant(1, MVT::i32)); 6532 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); 6533 6534 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6535 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6536 DAG.getConstant(5, MVT::i32)); 6537 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 6538 TrmpAddr, 5, false, 1); 6539 6540 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6541 DAG.getConstant(6, MVT::i32)); 6542 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); 6543 6544 SDValue Ops[] = 6545 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 6546 return DAG.getMergeValues(Ops, 2, dl); 6547 } 6548} 6549 6550SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6551 /* 6552 The rounding mode is in bits 11:10 of FPSR, and has the following 6553 settings: 6554 00 Round to nearest 6555 01 Round to -inf 6556 10 Round to +inf 6557 11 Round to 0 6558 6559 FLT_ROUNDS, on the other hand, expects the following: 6560 -1 Undefined 6561 0 Round to 0 6562 1 Round to nearest 6563 2 Round to +inf 6564 3 Round to -inf 6565 6566 To perform the conversion, we do: 6567 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6568 */ 6569 6570 MachineFunction &MF = DAG.getMachineFunction(); 6571 const TargetMachine &TM = MF.getTarget(); 6572 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6573 unsigned StackAlignment = TFI.getStackAlignment(); 6574 EVT VT = Op.getValueType(); 6575 DebugLoc dl = Op.getDebugLoc(); 6576 6577 // Save FP Control Word to stack slot 6578 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6579 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6580 6581 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 6582 DAG.getEntryNode(), StackSlot); 6583 6584 // Load FP Control Word from stack slot 6585 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); 6586 6587 // Transform as necessary 6588 SDValue CWD1 = 6589 DAG.getNode(ISD::SRL, dl, MVT::i16, 6590 DAG.getNode(ISD::AND, dl, MVT::i16, 6591 CWD, DAG.getConstant(0x800, MVT::i16)), 6592 DAG.getConstant(11, MVT::i8)); 6593 SDValue CWD2 = 6594 DAG.getNode(ISD::SRL, dl, MVT::i16, 6595 DAG.getNode(ISD::AND, dl, MVT::i16, 6596 CWD, DAG.getConstant(0x400, MVT::i16)), 6597 DAG.getConstant(9, MVT::i8)); 6598 6599 SDValue RetVal = 6600 DAG.getNode(ISD::AND, dl, MVT::i16, 6601 DAG.getNode(ISD::ADD, dl, MVT::i16, 6602 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 6603 DAG.getConstant(1, MVT::i16)), 6604 DAG.getConstant(3, MVT::i16)); 6605 6606 6607 return DAG.getNode((VT.getSizeInBits() < 16 ? 6608 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 6609} 6610 6611SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6612 EVT VT = Op.getValueType(); 6613 EVT OpVT = VT; 6614 unsigned NumBits = VT.getSizeInBits(); 6615 DebugLoc dl = Op.getDebugLoc(); 6616 6617 Op = Op.getOperand(0); 6618 if (VT == MVT::i8) { 6619 // Zero extend to i32 since there is not an i8 bsr. 6620 OpVT = MVT::i32; 6621 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6622 } 6623 6624 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6625 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6626 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 6627 6628 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6629 SmallVector<SDValue, 4> Ops; 6630 Ops.push_back(Op); 6631 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6632 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6633 Ops.push_back(Op.getValue(1)); 6634 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6635 6636 // Finally xor with NumBits-1. 6637 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6638 6639 if (VT == MVT::i8) 6640 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6641 return Op; 6642} 6643 6644SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6645 EVT VT = Op.getValueType(); 6646 EVT OpVT = VT; 6647 unsigned NumBits = VT.getSizeInBits(); 6648 DebugLoc dl = Op.getDebugLoc(); 6649 6650 Op = Op.getOperand(0); 6651 if (VT == MVT::i8) { 6652 OpVT = MVT::i32; 6653 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6654 } 6655 6656 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6657 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6658 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 6659 6660 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6661 SmallVector<SDValue, 4> Ops; 6662 Ops.push_back(Op); 6663 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6664 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6665 Ops.push_back(Op.getValue(1)); 6666 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6667 6668 if (VT == MVT::i8) 6669 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6670 return Op; 6671} 6672 6673SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6674 EVT VT = Op.getValueType(); 6675 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6676 DebugLoc dl = Op.getDebugLoc(); 6677 6678 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6679 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6680 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6681 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6682 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6683 // 6684 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6685 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6686 // return AloBlo + AloBhi + AhiBlo; 6687 6688 SDValue A = Op.getOperand(0); 6689 SDValue B = Op.getOperand(1); 6690 6691 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6692 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6693 A, DAG.getConstant(32, MVT::i32)); 6694 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6695 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6696 B, DAG.getConstant(32, MVT::i32)); 6697 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6698 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6699 A, B); 6700 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6701 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6702 A, Bhi); 6703 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6704 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6705 Ahi, B); 6706 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6707 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6708 AloBhi, DAG.getConstant(32, MVT::i32)); 6709 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6710 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6711 AhiBlo, DAG.getConstant(32, MVT::i32)); 6712 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 6713 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 6714 return Res; 6715} 6716 6717 6718SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6719 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6720 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6721 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6722 // has only one use. 6723 SDNode *N = Op.getNode(); 6724 SDValue LHS = N->getOperand(0); 6725 SDValue RHS = N->getOperand(1); 6726 unsigned BaseOp = 0; 6727 unsigned Cond = 0; 6728 DebugLoc dl = Op.getDebugLoc(); 6729 6730 switch (Op.getOpcode()) { 6731 default: llvm_unreachable("Unknown ovf instruction!"); 6732 case ISD::SADDO: 6733 // A subtract of one will be selected as a INC. Note that INC doesn't 6734 // set CF, so we can't do this for UADDO. 6735 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6736 if (C->getAPIntValue() == 1) { 6737 BaseOp = X86ISD::INC; 6738 Cond = X86::COND_O; 6739 break; 6740 } 6741 BaseOp = X86ISD::ADD; 6742 Cond = X86::COND_O; 6743 break; 6744 case ISD::UADDO: 6745 BaseOp = X86ISD::ADD; 6746 Cond = X86::COND_B; 6747 break; 6748 case ISD::SSUBO: 6749 // A subtract of one will be selected as a DEC. Note that DEC doesn't 6750 // set CF, so we can't do this for USUBO. 6751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6752 if (C->getAPIntValue() == 1) { 6753 BaseOp = X86ISD::DEC; 6754 Cond = X86::COND_O; 6755 break; 6756 } 6757 BaseOp = X86ISD::SUB; 6758 Cond = X86::COND_O; 6759 break; 6760 case ISD::USUBO: 6761 BaseOp = X86ISD::SUB; 6762 Cond = X86::COND_B; 6763 break; 6764 case ISD::SMULO: 6765 BaseOp = X86ISD::SMUL; 6766 Cond = X86::COND_O; 6767 break; 6768 case ISD::UMULO: 6769 BaseOp = X86ISD::UMUL; 6770 Cond = X86::COND_B; 6771 break; 6772 } 6773 6774 // Also sets EFLAGS. 6775 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6776 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 6777 6778 SDValue SetCC = 6779 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 6780 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6781 6782 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6783 return Sum; 6784} 6785 6786SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6787 EVT T = Op.getValueType(); 6788 DebugLoc dl = Op.getDebugLoc(); 6789 unsigned Reg = 0; 6790 unsigned size = 0; 6791 switch(T.getSimpleVT().SimpleTy) { 6792 default: 6793 assert(false && "Invalid value type!"); 6794 case MVT::i8: Reg = X86::AL; size = 1; break; 6795 case MVT::i16: Reg = X86::AX; size = 2; break; 6796 case MVT::i32: Reg = X86::EAX; size = 4; break; 6797 case MVT::i64: 6798 assert(Subtarget->is64Bit() && "Node not type legal!"); 6799 Reg = X86::RAX; size = 8; 6800 break; 6801 } 6802 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 6803 Op.getOperand(2), SDValue()); 6804 SDValue Ops[] = { cpIn.getValue(0), 6805 Op.getOperand(1), 6806 Op.getOperand(3), 6807 DAG.getTargetConstant(size, MVT::i8), 6808 cpIn.getValue(1) }; 6809 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6810 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 6811 SDValue cpOut = 6812 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 6813 return cpOut; 6814} 6815 6816SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6817 SelectionDAG &DAG) { 6818 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6819 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6820 SDValue TheChain = Op.getOperand(0); 6821 DebugLoc dl = Op.getDebugLoc(); 6822 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6823 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 6824 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 6825 rax.getValue(2)); 6826 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 6827 DAG.getConstant(32, MVT::i8)); 6828 SDValue Ops[] = { 6829 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 6830 rdx.getValue(1) 6831 }; 6832 return DAG.getMergeValues(Ops, 2, dl); 6833} 6834 6835SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6836 SDNode *Node = Op.getNode(); 6837 DebugLoc dl = Node->getDebugLoc(); 6838 EVT T = Node->getValueType(0); 6839 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 6840 DAG.getConstant(0, T), Node->getOperand(2)); 6841 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 6842 cast<AtomicSDNode>(Node)->getMemoryVT(), 6843 Node->getOperand(0), 6844 Node->getOperand(1), negOp, 6845 cast<AtomicSDNode>(Node)->getSrcValue(), 6846 cast<AtomicSDNode>(Node)->getAlignment()); 6847} 6848 6849/// LowerOperation - Provide custom lowering hooks for some operations. 6850/// 6851SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6852 switch (Op.getOpcode()) { 6853 default: llvm_unreachable("Should not custom lower this!"); 6854 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6855 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6856 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6857 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6858 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6859 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6860 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6861 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6862 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6863 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6864 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6865 case ISD::SHL_PARTS: 6866 case ISD::SRA_PARTS: 6867 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6868 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6869 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6870 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6871 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 6872 case ISD::FABS: return LowerFABS(Op, DAG); 6873 case ISD::FNEG: return LowerFNEG(Op, DAG); 6874 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6875 case ISD::SETCC: return LowerSETCC(Op, DAG); 6876 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6877 case ISD::SELECT: return LowerSELECT(Op, DAG); 6878 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6879 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6880 case ISD::VASTART: return LowerVASTART(Op, DAG); 6881 case ISD::VAARG: return LowerVAARG(Op, DAG); 6882 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6883 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6884 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6885 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6886 case ISD::FRAME_TO_ARGS_OFFSET: 6887 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6888 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6889 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6890 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6891 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6892 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6893 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6894 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6895 case ISD::SADDO: 6896 case ISD::UADDO: 6897 case ISD::SSUBO: 6898 case ISD::USUBO: 6899 case ISD::SMULO: 6900 case ISD::UMULO: return LowerXALUO(Op, DAG); 6901 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6902 } 6903} 6904 6905void X86TargetLowering:: 6906ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6907 SelectionDAG &DAG, unsigned NewOp) { 6908 EVT T = Node->getValueType(0); 6909 DebugLoc dl = Node->getDebugLoc(); 6910 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6911 6912 SDValue Chain = Node->getOperand(0); 6913 SDValue In1 = Node->getOperand(1); 6914 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6915 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6916 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6917 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6918 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6919 // have a MemOperand. Pass the info through as a normal operand. 6920 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6921 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6922 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6923 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); 6924 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6925 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6926 Results.push_back(Result.getValue(2)); 6927} 6928 6929/// ReplaceNodeResults - Replace a node with an illegal result type 6930/// with a new node built out of custom code. 6931void X86TargetLowering::ReplaceNodeResults(SDNode *N, 6932 SmallVectorImpl<SDValue>&Results, 6933 SelectionDAG &DAG) { 6934 DebugLoc dl = N->getDebugLoc(); 6935 switch (N->getOpcode()) { 6936 default: 6937 assert(false && "Do not know how to custom type legalize this operation!"); 6938 return; 6939 case ISD::FP_TO_SINT: { 6940 std::pair<SDValue,SDValue> Vals = 6941 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 6942 SDValue FIST = Vals.first, StackSlot = Vals.second; 6943 if (FIST.getNode() != 0) { 6944 EVT VT = N->getValueType(0); 6945 // Return a load from the stack slot. 6946 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); 6947 } 6948 return; 6949 } 6950 case ISD::READCYCLECOUNTER: { 6951 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6952 SDValue TheChain = N->getOperand(0); 6953 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6954 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 6955 rd.getValue(1)); 6956 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 6957 eax.getValue(2)); 6958 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 6959 SDValue Ops[] = { eax, edx }; 6960 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 6961 Results.push_back(edx.getValue(1)); 6962 return; 6963 } 6964 case ISD::ATOMIC_CMP_SWAP: { 6965 EVT T = N->getValueType(0); 6966 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 6967 SDValue cpInL, cpInH; 6968 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6969 DAG.getConstant(0, MVT::i32)); 6970 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6971 DAG.getConstant(1, MVT::i32)); 6972 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 6973 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 6974 cpInL.getValue(1)); 6975 SDValue swapInL, swapInH; 6976 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6977 DAG.getConstant(0, MVT::i32)); 6978 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6979 DAG.getConstant(1, MVT::i32)); 6980 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 6981 cpInH.getValue(1)); 6982 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 6983 swapInL.getValue(1)); 6984 SDValue Ops[] = { swapInH.getValue(0), 6985 N->getOperand(1), 6986 swapInH.getValue(1) }; 6987 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6988 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 6989 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 6990 MVT::i32, Result.getValue(1)); 6991 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 6992 MVT::i32, cpOutL.getValue(2)); 6993 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 6994 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6995 Results.push_back(cpOutH.getValue(1)); 6996 return; 6997 } 6998 case ISD::ATOMIC_LOAD_ADD: 6999 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7000 return; 7001 case ISD::ATOMIC_LOAD_AND: 7002 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7003 return; 7004 case ISD::ATOMIC_LOAD_NAND: 7005 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7006 return; 7007 case ISD::ATOMIC_LOAD_OR: 7008 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7009 return; 7010 case ISD::ATOMIC_LOAD_SUB: 7011 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7012 return; 7013 case ISD::ATOMIC_LOAD_XOR: 7014 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7015 return; 7016 case ISD::ATOMIC_SWAP: 7017 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7018 return; 7019 } 7020} 7021 7022const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7023 switch (Opcode) { 7024 default: return NULL; 7025 case X86ISD::BSF: return "X86ISD::BSF"; 7026 case X86ISD::BSR: return "X86ISD::BSR"; 7027 case X86ISD::SHLD: return "X86ISD::SHLD"; 7028 case X86ISD::SHRD: return "X86ISD::SHRD"; 7029 case X86ISD::FAND: return "X86ISD::FAND"; 7030 case X86ISD::FOR: return "X86ISD::FOR"; 7031 case X86ISD::FXOR: return "X86ISD::FXOR"; 7032 case X86ISD::FSRL: return "X86ISD::FSRL"; 7033 case X86ISD::FILD: return "X86ISD::FILD"; 7034 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7035 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7036 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7037 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7038 case X86ISD::FLD: return "X86ISD::FLD"; 7039 case X86ISD::FST: return "X86ISD::FST"; 7040 case X86ISD::CALL: return "X86ISD::CALL"; 7041 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7042 case X86ISD::BT: return "X86ISD::BT"; 7043 case X86ISD::CMP: return "X86ISD::CMP"; 7044 case X86ISD::COMI: return "X86ISD::COMI"; 7045 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7046 case X86ISD::SETCC: return "X86ISD::SETCC"; 7047 case X86ISD::CMOV: return "X86ISD::CMOV"; 7048 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7049 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7050 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7051 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7052 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7053 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7054 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7055 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7056 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7057 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7058 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7059 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7060 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7061 case X86ISD::FMAX: return "X86ISD::FMAX"; 7062 case X86ISD::FMIN: return "X86ISD::FMIN"; 7063 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7064 case X86ISD::FRCP: return "X86ISD::FRCP"; 7065 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7066 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7067 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7068 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7069 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7070 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7071 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7072 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7073 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7074 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7075 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7076 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7077 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7078 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7079 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7080 case X86ISD::VSHL: return "X86ISD::VSHL"; 7081 case X86ISD::VSRL: return "X86ISD::VSRL"; 7082 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7083 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7084 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7085 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7086 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7087 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7088 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7089 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7090 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7091 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7092 case X86ISD::ADD: return "X86ISD::ADD"; 7093 case X86ISD::SUB: return "X86ISD::SUB"; 7094 case X86ISD::SMUL: return "X86ISD::SMUL"; 7095 case X86ISD::UMUL: return "X86ISD::UMUL"; 7096 case X86ISD::INC: return "X86ISD::INC"; 7097 case X86ISD::DEC: return "X86ISD::DEC"; 7098 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7099 case X86ISD::PTEST: return "X86ISD::PTEST"; 7100 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7101 } 7102} 7103 7104// isLegalAddressingMode - Return true if the addressing mode represented 7105// by AM is legal for this target, for a load/store of the specified type. 7106bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7107 const Type *Ty) const { 7108 // X86 supports extremely general addressing modes. 7109 CodeModel::Model M = getTargetMachine().getCodeModel(); 7110 7111 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7112 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7113 return false; 7114 7115 if (AM.BaseGV) { 7116 unsigned GVFlags = 7117 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7118 7119 // If a reference to this global requires an extra load, we can't fold it. 7120 if (isGlobalStubReference(GVFlags)) 7121 return false; 7122 7123 // If BaseGV requires a register for the PIC base, we cannot also have a 7124 // BaseReg specified. 7125 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7126 return false; 7127 7128 // If lower 4G is not available, then we must use rip-relative addressing. 7129 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7130 return false; 7131 } 7132 7133 switch (AM.Scale) { 7134 case 0: 7135 case 1: 7136 case 2: 7137 case 4: 7138 case 8: 7139 // These scales always work. 7140 break; 7141 case 3: 7142 case 5: 7143 case 9: 7144 // These scales are formed with basereg+scalereg. Only accept if there is 7145 // no basereg yet. 7146 if (AM.HasBaseReg) 7147 return false; 7148 break; 7149 default: // Other stuff never works. 7150 return false; 7151 } 7152 7153 return true; 7154} 7155 7156 7157bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7158 if (!Ty1->isInteger() || !Ty2->isInteger()) 7159 return false; 7160 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7161 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7162 if (NumBits1 <= NumBits2) 7163 return false; 7164 return Subtarget->is64Bit() || NumBits1 < 64; 7165} 7166 7167bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7168 if (!VT1.isInteger() || !VT2.isInteger()) 7169 return false; 7170 unsigned NumBits1 = VT1.getSizeInBits(); 7171 unsigned NumBits2 = VT2.getSizeInBits(); 7172 if (NumBits1 <= NumBits2) 7173 return false; 7174 return Subtarget->is64Bit() || NumBits1 < 64; 7175} 7176 7177bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7178 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7179 return Ty1 == Type::getInt32Ty(Ty1->getContext()) && 7180 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit(); 7181} 7182 7183bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7184 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7185 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7186} 7187 7188bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7189 // i16 instructions are longer (0x66 prefix) and potentially slower. 7190 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7191} 7192 7193/// isShuffleMaskLegal - Targets can use this to indicate that they only 7194/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7195/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7196/// are assumed to be legal. 7197bool 7198X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7199 EVT VT) const { 7200 // Only do shuffles on 128-bit vector types for now. 7201 if (VT.getSizeInBits() == 64) 7202 return false; 7203 7204 // FIXME: pshufb, blends, palignr, shifts. 7205 return (VT.getVectorNumElements() == 2 || 7206 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7207 isMOVLMask(M, VT) || 7208 isSHUFPMask(M, VT) || 7209 isPSHUFDMask(M, VT) || 7210 isPSHUFHWMask(M, VT) || 7211 isPSHUFLWMask(M, VT) || 7212 isUNPCKLMask(M, VT) || 7213 isUNPCKHMask(M, VT) || 7214 isUNPCKL_v_undef_Mask(M, VT) || 7215 isUNPCKH_v_undef_Mask(M, VT)); 7216} 7217 7218bool 7219X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7220 EVT VT) const { 7221 unsigned NumElts = VT.getVectorNumElements(); 7222 // FIXME: This collection of masks seems suspect. 7223 if (NumElts == 2) 7224 return true; 7225 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7226 return (isMOVLMask(Mask, VT) || 7227 isCommutedMOVLMask(Mask, VT, true) || 7228 isSHUFPMask(Mask, VT) || 7229 isCommutedSHUFPMask(Mask, VT)); 7230 } 7231 return false; 7232} 7233 7234//===----------------------------------------------------------------------===// 7235// X86 Scheduler Hooks 7236//===----------------------------------------------------------------------===// 7237 7238// private utility function 7239MachineBasicBlock * 7240X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7241 MachineBasicBlock *MBB, 7242 unsigned regOpc, 7243 unsigned immOpc, 7244 unsigned LoadOpc, 7245 unsigned CXchgOpc, 7246 unsigned copyOpc, 7247 unsigned notOpc, 7248 unsigned EAXreg, 7249 TargetRegisterClass *RC, 7250 bool invSrc) const { 7251 // For the atomic bitwise operator, we generate 7252 // thisMBB: 7253 // newMBB: 7254 // ld t1 = [bitinstr.addr] 7255 // op t2 = t1, [bitinstr.val] 7256 // mov EAX = t1 7257 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7258 // bz newMBB 7259 // fallthrough -->nextMBB 7260 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7261 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7262 MachineFunction::iterator MBBIter = MBB; 7263 ++MBBIter; 7264 7265 /// First build the CFG 7266 MachineFunction *F = MBB->getParent(); 7267 MachineBasicBlock *thisMBB = MBB; 7268 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7269 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7270 F->insert(MBBIter, newMBB); 7271 F->insert(MBBIter, nextMBB); 7272 7273 // Move all successors to thisMBB to nextMBB 7274 nextMBB->transferSuccessors(thisMBB); 7275 7276 // Update thisMBB to fall through to newMBB 7277 thisMBB->addSuccessor(newMBB); 7278 7279 // newMBB jumps to itself and fall through to nextMBB 7280 newMBB->addSuccessor(nextMBB); 7281 newMBB->addSuccessor(newMBB); 7282 7283 // Insert instructions into newMBB based on incoming instruction 7284 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7285 "unexpected number of operands"); 7286 DebugLoc dl = bInstr->getDebugLoc(); 7287 MachineOperand& destOper = bInstr->getOperand(0); 7288 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7289 int numArgs = bInstr->getNumOperands() - 1; 7290 for (int i=0; i < numArgs; ++i) 7291 argOpers[i] = &bInstr->getOperand(i+1); 7292 7293 // x86 address has 4 operands: base, index, scale, and displacement 7294 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7295 int valArgIndx = lastAddrIndx + 1; 7296 7297 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7298 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7299 for (int i=0; i <= lastAddrIndx; ++i) 7300 (*MIB).addOperand(*argOpers[i]); 7301 7302 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7303 if (invSrc) { 7304 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7305 } 7306 else 7307 tt = t1; 7308 7309 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7310 assert((argOpers[valArgIndx]->isReg() || 7311 argOpers[valArgIndx]->isImm()) && 7312 "invalid operand"); 7313 if (argOpers[valArgIndx]->isReg()) 7314 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7315 else 7316 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7317 MIB.addReg(tt); 7318 (*MIB).addOperand(*argOpers[valArgIndx]); 7319 7320 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7321 MIB.addReg(t1); 7322 7323 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7324 for (int i=0; i <= lastAddrIndx; ++i) 7325 (*MIB).addOperand(*argOpers[i]); 7326 MIB.addReg(t2); 7327 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7328 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7329 7330 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7331 MIB.addReg(EAXreg); 7332 7333 // insert branch 7334 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7335 7336 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7337 return nextMBB; 7338} 7339 7340// private utility function: 64 bit atomics on 32 bit host. 7341MachineBasicBlock * 7342X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7343 MachineBasicBlock *MBB, 7344 unsigned regOpcL, 7345 unsigned regOpcH, 7346 unsigned immOpcL, 7347 unsigned immOpcH, 7348 bool invSrc) const { 7349 // For the atomic bitwise operator, we generate 7350 // thisMBB (instructions are in pairs, except cmpxchg8b) 7351 // ld t1,t2 = [bitinstr.addr] 7352 // newMBB: 7353 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7354 // op t5, t6 <- out1, out2, [bitinstr.val] 7355 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7356 // mov ECX, EBX <- t5, t6 7357 // mov EAX, EDX <- t1, t2 7358 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7359 // mov t3, t4 <- EAX, EDX 7360 // bz newMBB 7361 // result in out1, out2 7362 // fallthrough -->nextMBB 7363 7364 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7365 const unsigned LoadOpc = X86::MOV32rm; 7366 const unsigned copyOpc = X86::MOV32rr; 7367 const unsigned NotOpc = X86::NOT32r; 7368 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7369 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7370 MachineFunction::iterator MBBIter = MBB; 7371 ++MBBIter; 7372 7373 /// First build the CFG 7374 MachineFunction *F = MBB->getParent(); 7375 MachineBasicBlock *thisMBB = MBB; 7376 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7377 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7378 F->insert(MBBIter, newMBB); 7379 F->insert(MBBIter, nextMBB); 7380 7381 // Move all successors to thisMBB to nextMBB 7382 nextMBB->transferSuccessors(thisMBB); 7383 7384 // Update thisMBB to fall through to newMBB 7385 thisMBB->addSuccessor(newMBB); 7386 7387 // newMBB jumps to itself and fall through to nextMBB 7388 newMBB->addSuccessor(nextMBB); 7389 newMBB->addSuccessor(newMBB); 7390 7391 DebugLoc dl = bInstr->getDebugLoc(); 7392 // Insert instructions into newMBB based on incoming instruction 7393 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 7394 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 7395 "unexpected number of operands"); 7396 MachineOperand& dest1Oper = bInstr->getOperand(0); 7397 MachineOperand& dest2Oper = bInstr->getOperand(1); 7398 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7399 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 7400 argOpers[i] = &bInstr->getOperand(i+2); 7401 7402 // x86 address has 4 operands: base, index, scale, and displacement 7403 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7404 7405 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7406 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 7407 for (int i=0; i <= lastAddrIndx; ++i) 7408 (*MIB).addOperand(*argOpers[i]); 7409 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7410 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 7411 // add 4 to displacement. 7412 for (int i=0; i <= lastAddrIndx-2; ++i) 7413 (*MIB).addOperand(*argOpers[i]); 7414 MachineOperand newOp3 = *(argOpers[3]); 7415 if (newOp3.isImm()) 7416 newOp3.setImm(newOp3.getImm()+4); 7417 else 7418 newOp3.setOffset(newOp3.getOffset()+4); 7419 (*MIB).addOperand(newOp3); 7420 (*MIB).addOperand(*argOpers[lastAddrIndx]); 7421 7422 // t3/4 are defined later, at the bottom of the loop 7423 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 7424 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 7425 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 7426 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 7427 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 7428 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 7429 7430 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 7431 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 7432 if (invSrc) { 7433 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1); 7434 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2); 7435 } else { 7436 tt1 = t1; 7437 tt2 = t2; 7438 } 7439 7440 int valArgIndx = lastAddrIndx + 1; 7441 assert((argOpers[valArgIndx]->isReg() || 7442 argOpers[valArgIndx]->isImm()) && 7443 "invalid operand"); 7444 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 7445 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 7446 if (argOpers[valArgIndx]->isReg()) 7447 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 7448 else 7449 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 7450 if (regOpcL != X86::MOV32rr) 7451 MIB.addReg(tt1); 7452 (*MIB).addOperand(*argOpers[valArgIndx]); 7453 assert(argOpers[valArgIndx + 1]->isReg() == 7454 argOpers[valArgIndx]->isReg()); 7455 assert(argOpers[valArgIndx + 1]->isImm() == 7456 argOpers[valArgIndx]->isImm()); 7457 if (argOpers[valArgIndx + 1]->isReg()) 7458 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 7459 else 7460 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 7461 if (regOpcH != X86::MOV32rr) 7462 MIB.addReg(tt2); 7463 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 7464 7465 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 7466 MIB.addReg(t1); 7467 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 7468 MIB.addReg(t2); 7469 7470 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 7471 MIB.addReg(t5); 7472 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 7473 MIB.addReg(t6); 7474 7475 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 7476 for (int i=0; i <= lastAddrIndx; ++i) 7477 (*MIB).addOperand(*argOpers[i]); 7478 7479 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7480 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7481 7482 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 7483 MIB.addReg(X86::EAX); 7484 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 7485 MIB.addReg(X86::EDX); 7486 7487 // insert branch 7488 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7489 7490 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7491 return nextMBB; 7492} 7493 7494// private utility function 7495MachineBasicBlock * 7496X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 7497 MachineBasicBlock *MBB, 7498 unsigned cmovOpc) const { 7499 // For the atomic min/max operator, we generate 7500 // thisMBB: 7501 // newMBB: 7502 // ld t1 = [min/max.addr] 7503 // mov t2 = [min/max.val] 7504 // cmp t1, t2 7505 // cmov[cond] t2 = t1 7506 // mov EAX = t1 7507 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7508 // bz newMBB 7509 // fallthrough -->nextMBB 7510 // 7511 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7512 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7513 MachineFunction::iterator MBBIter = MBB; 7514 ++MBBIter; 7515 7516 /// First build the CFG 7517 MachineFunction *F = MBB->getParent(); 7518 MachineBasicBlock *thisMBB = MBB; 7519 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7520 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7521 F->insert(MBBIter, newMBB); 7522 F->insert(MBBIter, nextMBB); 7523 7524 // Move all successors of thisMBB to nextMBB 7525 nextMBB->transferSuccessors(thisMBB); 7526 7527 // Update thisMBB to fall through to newMBB 7528 thisMBB->addSuccessor(newMBB); 7529 7530 // newMBB jumps to newMBB and fall through to nextMBB 7531 newMBB->addSuccessor(nextMBB); 7532 newMBB->addSuccessor(newMBB); 7533 7534 DebugLoc dl = mInstr->getDebugLoc(); 7535 // Insert instructions into newMBB based on incoming instruction 7536 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 7537 "unexpected number of operands"); 7538 MachineOperand& destOper = mInstr->getOperand(0); 7539 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7540 int numArgs = mInstr->getNumOperands() - 1; 7541 for (int i=0; i < numArgs; ++i) 7542 argOpers[i] = &mInstr->getOperand(i+1); 7543 7544 // x86 address has 4 operands: base, index, scale, and displacement 7545 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7546 int valArgIndx = lastAddrIndx + 1; 7547 7548 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7549 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 7550 for (int i=0; i <= lastAddrIndx; ++i) 7551 (*MIB).addOperand(*argOpers[i]); 7552 7553 // We only support register and immediate values 7554 assert((argOpers[valArgIndx]->isReg() || 7555 argOpers[valArgIndx]->isImm()) && 7556 "invalid operand"); 7557 7558 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7559 if (argOpers[valArgIndx]->isReg()) 7560 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7561 else 7562 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7563 (*MIB).addOperand(*argOpers[valArgIndx]); 7564 7565 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 7566 MIB.addReg(t1); 7567 7568 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 7569 MIB.addReg(t1); 7570 MIB.addReg(t2); 7571 7572 // Generate movc 7573 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7574 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 7575 MIB.addReg(t2); 7576 MIB.addReg(t1); 7577 7578 // Cmp and exchange if none has modified the memory location 7579 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 7580 for (int i=0; i <= lastAddrIndx; ++i) 7581 (*MIB).addOperand(*argOpers[i]); 7582 MIB.addReg(t3); 7583 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7584 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 7585 7586 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 7587 MIB.addReg(X86::EAX); 7588 7589 // insert branch 7590 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7591 7592 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 7593 return nextMBB; 7594} 7595 7596MachineBasicBlock * 7597X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 7598 MachineInstr *MI, 7599 MachineBasicBlock *MBB) const { 7600 // Emit code to save XMM registers to the stack. The ABI says that the 7601 // number of registers to save is given in %al, so it's theoretically 7602 // possible to do an indirect jump trick to avoid saving all of them, 7603 // however this code takes a simpler approach and just executes all 7604 // of the stores if %al is non-zero. It's less code, and it's probably 7605 // easier on the hardware branch predictor, and stores aren't all that 7606 // expensive anyway. 7607 7608 // Create the new basic blocks. One block contains all the XMM stores, 7609 // and one block is the final destination regardless of whether any 7610 // stores were performed. 7611 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7612 MachineFunction *F = MBB->getParent(); 7613 MachineFunction::iterator MBBIter = MBB; 7614 ++MBBIter; 7615 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 7616 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 7617 F->insert(MBBIter, XMMSaveMBB); 7618 F->insert(MBBIter, EndMBB); 7619 7620 // Set up the CFG. 7621 // Move any original successors of MBB to the end block. 7622 EndMBB->transferSuccessors(MBB); 7623 // The original block will now fall through to the XMM save block. 7624 MBB->addSuccessor(XMMSaveMBB); 7625 // The XMMSaveMBB will fall through to the end block. 7626 XMMSaveMBB->addSuccessor(EndMBB); 7627 7628 // Now add the instructions. 7629 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7630 DebugLoc DL = MI->getDebugLoc(); 7631 7632 unsigned CountReg = MI->getOperand(0).getReg(); 7633 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 7634 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 7635 7636 if (!Subtarget->isTargetWin64()) { 7637 // If %al is 0, branch around the XMM save block. 7638 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 7639 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB); 7640 MBB->addSuccessor(EndMBB); 7641 } 7642 7643 // In the XMM save block, save all the XMM argument registers. 7644 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 7645 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 7646 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 7647 .addFrameIndex(RegSaveFrameIndex) 7648 .addImm(/*Scale=*/1) 7649 .addReg(/*IndexReg=*/0) 7650 .addImm(/*Disp=*/Offset) 7651 .addReg(/*Segment=*/0) 7652 .addReg(MI->getOperand(i).getReg()) 7653 .addMemOperand(MachineMemOperand( 7654 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 7655 MachineMemOperand::MOStore, Offset, 7656 /*Size=*/16, /*Align=*/16)); 7657 } 7658 7659 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7660 7661 return EndMBB; 7662} 7663 7664MachineBasicBlock * 7665X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7666 MachineBasicBlock *BB) const { 7667 DebugLoc dl = MI->getDebugLoc(); 7668 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7669 switch (MI->getOpcode()) { 7670 default: assert(false && "Unexpected instr type to insert"); 7671 case X86::CMOV_V1I64: 7672 case X86::CMOV_FR32: 7673 case X86::CMOV_FR64: 7674 case X86::CMOV_V4F32: 7675 case X86::CMOV_V2F64: 7676 case X86::CMOV_V2I64: { 7677 // To "insert" a SELECT_CC instruction, we actually have to insert the 7678 // diamond control-flow pattern. The incoming instruction knows the 7679 // destination vreg to set, the condition code register to branch on, the 7680 // true/false values to select between, and a branch opcode to use. 7681 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7682 MachineFunction::iterator It = BB; 7683 ++It; 7684 7685 // thisMBB: 7686 // ... 7687 // TrueVal = ... 7688 // cmpTY ccX, r1, r2 7689 // bCC copy1MBB 7690 // fallthrough --> copy0MBB 7691 MachineBasicBlock *thisMBB = BB; 7692 MachineFunction *F = BB->getParent(); 7693 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7694 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7695 unsigned Opc = 7696 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7697 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 7698 F->insert(It, copy0MBB); 7699 F->insert(It, sinkMBB); 7700 // Update machine-CFG edges by transferring all successors of the current 7701 // block to the new block which will contain the Phi node for the select. 7702 sinkMBB->transferSuccessors(BB); 7703 7704 // Add the true and fallthrough blocks as its successors. 7705 BB->addSuccessor(copy0MBB); 7706 BB->addSuccessor(sinkMBB); 7707 7708 // copy0MBB: 7709 // %FalseValue = ... 7710 // # fallthrough to sinkMBB 7711 BB = copy0MBB; 7712 7713 // Update machine-CFG edges 7714 BB->addSuccessor(sinkMBB); 7715 7716 // sinkMBB: 7717 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7718 // ... 7719 BB = sinkMBB; 7720 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7721 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7722 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7723 7724 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7725 return BB; 7726 } 7727 7728 case X86::FP32_TO_INT16_IN_MEM: 7729 case X86::FP32_TO_INT32_IN_MEM: 7730 case X86::FP32_TO_INT64_IN_MEM: 7731 case X86::FP64_TO_INT16_IN_MEM: 7732 case X86::FP64_TO_INT32_IN_MEM: 7733 case X86::FP64_TO_INT64_IN_MEM: 7734 case X86::FP80_TO_INT16_IN_MEM: 7735 case X86::FP80_TO_INT32_IN_MEM: 7736 case X86::FP80_TO_INT64_IN_MEM: { 7737 // Change the floating point control register to use "round towards zero" 7738 // mode when truncating to an integer value. 7739 MachineFunction *F = BB->getParent(); 7740 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7741 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7742 7743 // Load the old value of the high byte of the control word... 7744 unsigned OldCW = 7745 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7746 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW), 7747 CWFrameIdx); 7748 7749 // Set the high part to be round to zero... 7750 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx) 7751 .addImm(0xC7F); 7752 7753 // Reload the modified control word now... 7754 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7755 7756 // Restore the memory image of control word to original value 7757 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx) 7758 .addReg(OldCW); 7759 7760 // Get the X86 opcode to use. 7761 unsigned Opc; 7762 switch (MI->getOpcode()) { 7763 default: llvm_unreachable("illegal opcode!"); 7764 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7765 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7766 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7767 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7768 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7769 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7770 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7771 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7772 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7773 } 7774 7775 X86AddressMode AM; 7776 MachineOperand &Op = MI->getOperand(0); 7777 if (Op.isReg()) { 7778 AM.BaseType = X86AddressMode::RegBase; 7779 AM.Base.Reg = Op.getReg(); 7780 } else { 7781 AM.BaseType = X86AddressMode::FrameIndexBase; 7782 AM.Base.FrameIndex = Op.getIndex(); 7783 } 7784 Op = MI->getOperand(1); 7785 if (Op.isImm()) 7786 AM.Scale = Op.getImm(); 7787 Op = MI->getOperand(2); 7788 if (Op.isImm()) 7789 AM.IndexReg = Op.getImm(); 7790 Op = MI->getOperand(3); 7791 if (Op.isGlobal()) { 7792 AM.GV = Op.getGlobal(); 7793 } else { 7794 AM.Disp = Op.getImm(); 7795 } 7796 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM) 7797 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 7798 7799 // Reload the original control word now. 7800 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7801 7802 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7803 return BB; 7804 } 7805 case X86::ATOMAND32: 7806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7807 X86::AND32ri, X86::MOV32rm, 7808 X86::LCMPXCHG32, X86::MOV32rr, 7809 X86::NOT32r, X86::EAX, 7810 X86::GR32RegisterClass); 7811 case X86::ATOMOR32: 7812 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7813 X86::OR32ri, X86::MOV32rm, 7814 X86::LCMPXCHG32, X86::MOV32rr, 7815 X86::NOT32r, X86::EAX, 7816 X86::GR32RegisterClass); 7817 case X86::ATOMXOR32: 7818 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7819 X86::XOR32ri, X86::MOV32rm, 7820 X86::LCMPXCHG32, X86::MOV32rr, 7821 X86::NOT32r, X86::EAX, 7822 X86::GR32RegisterClass); 7823 case X86::ATOMNAND32: 7824 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7825 X86::AND32ri, X86::MOV32rm, 7826 X86::LCMPXCHG32, X86::MOV32rr, 7827 X86::NOT32r, X86::EAX, 7828 X86::GR32RegisterClass, true); 7829 case X86::ATOMMIN32: 7830 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7831 case X86::ATOMMAX32: 7832 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7833 case X86::ATOMUMIN32: 7834 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7835 case X86::ATOMUMAX32: 7836 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7837 7838 case X86::ATOMAND16: 7839 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7840 X86::AND16ri, X86::MOV16rm, 7841 X86::LCMPXCHG16, X86::MOV16rr, 7842 X86::NOT16r, X86::AX, 7843 X86::GR16RegisterClass); 7844 case X86::ATOMOR16: 7845 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7846 X86::OR16ri, X86::MOV16rm, 7847 X86::LCMPXCHG16, X86::MOV16rr, 7848 X86::NOT16r, X86::AX, 7849 X86::GR16RegisterClass); 7850 case X86::ATOMXOR16: 7851 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7852 X86::XOR16ri, X86::MOV16rm, 7853 X86::LCMPXCHG16, X86::MOV16rr, 7854 X86::NOT16r, X86::AX, 7855 X86::GR16RegisterClass); 7856 case X86::ATOMNAND16: 7857 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7858 X86::AND16ri, X86::MOV16rm, 7859 X86::LCMPXCHG16, X86::MOV16rr, 7860 X86::NOT16r, X86::AX, 7861 X86::GR16RegisterClass, true); 7862 case X86::ATOMMIN16: 7863 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 7864 case X86::ATOMMAX16: 7865 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 7866 case X86::ATOMUMIN16: 7867 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 7868 case X86::ATOMUMAX16: 7869 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 7870 7871 case X86::ATOMAND8: 7872 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7873 X86::AND8ri, X86::MOV8rm, 7874 X86::LCMPXCHG8, X86::MOV8rr, 7875 X86::NOT8r, X86::AL, 7876 X86::GR8RegisterClass); 7877 case X86::ATOMOR8: 7878 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 7879 X86::OR8ri, X86::MOV8rm, 7880 X86::LCMPXCHG8, X86::MOV8rr, 7881 X86::NOT8r, X86::AL, 7882 X86::GR8RegisterClass); 7883 case X86::ATOMXOR8: 7884 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 7885 X86::XOR8ri, X86::MOV8rm, 7886 X86::LCMPXCHG8, X86::MOV8rr, 7887 X86::NOT8r, X86::AL, 7888 X86::GR8RegisterClass); 7889 case X86::ATOMNAND8: 7890 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7891 X86::AND8ri, X86::MOV8rm, 7892 X86::LCMPXCHG8, X86::MOV8rr, 7893 X86::NOT8r, X86::AL, 7894 X86::GR8RegisterClass, true); 7895 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 7896 // This group is for 64-bit host. 7897 case X86::ATOMAND64: 7898 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7899 X86::AND64ri32, X86::MOV64rm, 7900 X86::LCMPXCHG64, X86::MOV64rr, 7901 X86::NOT64r, X86::RAX, 7902 X86::GR64RegisterClass); 7903 case X86::ATOMOR64: 7904 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 7905 X86::OR64ri32, X86::MOV64rm, 7906 X86::LCMPXCHG64, X86::MOV64rr, 7907 X86::NOT64r, X86::RAX, 7908 X86::GR64RegisterClass); 7909 case X86::ATOMXOR64: 7910 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 7911 X86::XOR64ri32, X86::MOV64rm, 7912 X86::LCMPXCHG64, X86::MOV64rr, 7913 X86::NOT64r, X86::RAX, 7914 X86::GR64RegisterClass); 7915 case X86::ATOMNAND64: 7916 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7917 X86::AND64ri32, X86::MOV64rm, 7918 X86::LCMPXCHG64, X86::MOV64rr, 7919 X86::NOT64r, X86::RAX, 7920 X86::GR64RegisterClass, true); 7921 case X86::ATOMMIN64: 7922 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 7923 case X86::ATOMMAX64: 7924 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 7925 case X86::ATOMUMIN64: 7926 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 7927 case X86::ATOMUMAX64: 7928 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 7929 7930 // This group does 64-bit operations on a 32-bit host. 7931 case X86::ATOMAND6432: 7932 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7933 X86::AND32rr, X86::AND32rr, 7934 X86::AND32ri, X86::AND32ri, 7935 false); 7936 case X86::ATOMOR6432: 7937 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7938 X86::OR32rr, X86::OR32rr, 7939 X86::OR32ri, X86::OR32ri, 7940 false); 7941 case X86::ATOMXOR6432: 7942 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7943 X86::XOR32rr, X86::XOR32rr, 7944 X86::XOR32ri, X86::XOR32ri, 7945 false); 7946 case X86::ATOMNAND6432: 7947 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7948 X86::AND32rr, X86::AND32rr, 7949 X86::AND32ri, X86::AND32ri, 7950 true); 7951 case X86::ATOMADD6432: 7952 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7953 X86::ADD32rr, X86::ADC32rr, 7954 X86::ADD32ri, X86::ADC32ri, 7955 false); 7956 case X86::ATOMSUB6432: 7957 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7958 X86::SUB32rr, X86::SBB32rr, 7959 X86::SUB32ri, X86::SBB32ri, 7960 false); 7961 case X86::ATOMSWAP6432: 7962 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7963 X86::MOV32rr, X86::MOV32rr, 7964 X86::MOV32ri, X86::MOV32ri, 7965 false); 7966 case X86::VASTART_SAVE_XMM_REGS: 7967 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 7968 } 7969} 7970 7971//===----------------------------------------------------------------------===// 7972// X86 Optimization Hooks 7973//===----------------------------------------------------------------------===// 7974 7975void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7976 const APInt &Mask, 7977 APInt &KnownZero, 7978 APInt &KnownOne, 7979 const SelectionDAG &DAG, 7980 unsigned Depth) const { 7981 unsigned Opc = Op.getOpcode(); 7982 assert((Opc >= ISD::BUILTIN_OP_END || 7983 Opc == ISD::INTRINSIC_WO_CHAIN || 7984 Opc == ISD::INTRINSIC_W_CHAIN || 7985 Opc == ISD::INTRINSIC_VOID) && 7986 "Should use MaskedValueIsZero if you don't know whether Op" 7987 " is a target node!"); 7988 7989 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 7990 switch (Opc) { 7991 default: break; 7992 case X86ISD::ADD: 7993 case X86ISD::SUB: 7994 case X86ISD::SMUL: 7995 case X86ISD::UMUL: 7996 case X86ISD::INC: 7997 case X86ISD::DEC: 7998 // These nodes' second result is a boolean. 7999 if (Op.getResNo() == 0) 8000 break; 8001 // Fallthrough 8002 case X86ISD::SETCC: 8003 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8004 Mask.getBitWidth() - 1); 8005 break; 8006 } 8007} 8008 8009/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8010/// node is a GlobalAddress + offset. 8011bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8012 GlobalValue* &GA, int64_t &Offset) const{ 8013 if (N->getOpcode() == X86ISD::Wrapper) { 8014 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8015 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8016 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8017 return true; 8018 } 8019 } 8020 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8021} 8022 8023static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 8024 const TargetLowering &TLI) { 8025 GlobalValue *GV; 8026 int64_t Offset = 0; 8027 if (TLI.isGAPlusOffset(Base, GV, Offset)) 8028 return (GV->getAlignment() >= N && (Offset % N) == 0); 8029 // DAG combine handles the stack object case. 8030 return false; 8031} 8032 8033static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 8034 EVT EVT, LoadSDNode *&LDBase, 8035 unsigned &LastLoadedElt, 8036 SelectionDAG &DAG, MachineFrameInfo *MFI, 8037 const TargetLowering &TLI) { 8038 LDBase = NULL; 8039 LastLoadedElt = -1U; 8040 for (unsigned i = 0; i < NumElems; ++i) { 8041 if (N->getMaskElt(i) < 0) { 8042 if (!LDBase) 8043 return false; 8044 continue; 8045 } 8046 8047 SDValue Elt = DAG.getShuffleScalarElt(N, i); 8048 if (!Elt.getNode() || 8049 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 8050 return false; 8051 if (!LDBase) { 8052 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 8053 return false; 8054 LDBase = cast<LoadSDNode>(Elt.getNode()); 8055 LastLoadedElt = i; 8056 continue; 8057 } 8058 if (Elt.getOpcode() == ISD::UNDEF) 8059 continue; 8060 8061 LoadSDNode *LD = cast<LoadSDNode>(Elt); 8062 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI)) 8063 return false; 8064 LastLoadedElt = i; 8065 } 8066 return true; 8067} 8068 8069/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8070/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8071/// if the load addresses are consecutive, non-overlapping, and in the right 8072/// order. In the case of v2i64, it will see if it can rewrite the 8073/// shuffle to be an appropriate build vector so it can take advantage of 8074// performBuildVectorCombine. 8075static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8076 const TargetLowering &TLI) { 8077 DebugLoc dl = N->getDebugLoc(); 8078 EVT VT = N->getValueType(0); 8079 EVT EVT = VT.getVectorElementType(); 8080 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8081 unsigned NumElems = VT.getVectorNumElements(); 8082 8083 if (VT.getSizeInBits() != 128) 8084 return SDValue(); 8085 8086 // Try to combine a vector_shuffle into a 128-bit load. 8087 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8088 LoadSDNode *LD = NULL; 8089 unsigned LastLoadedElt; 8090 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG, 8091 MFI, TLI)) 8092 return SDValue(); 8093 8094 if (LastLoadedElt == NumElems - 1) { 8095 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI)) 8096 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8097 LD->getSrcValue(), LD->getSrcValueOffset(), 8098 LD->isVolatile()); 8099 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8100 LD->getSrcValue(), LD->getSrcValueOffset(), 8101 LD->isVolatile(), LD->getAlignment()); 8102 } else if (NumElems == 4 && LastLoadedElt == 1) { 8103 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 8104 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 8105 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 8106 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 8107 } 8108 return SDValue(); 8109} 8110 8111/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8112static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8113 const X86Subtarget *Subtarget) { 8114 DebugLoc DL = N->getDebugLoc(); 8115 SDValue Cond = N->getOperand(0); 8116 // Get the LHS/RHS of the select. 8117 SDValue LHS = N->getOperand(1); 8118 SDValue RHS = N->getOperand(2); 8119 8120 // If we have SSE[12] support, try to form min/max nodes. 8121 if (Subtarget->hasSSE2() && 8122 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8123 Cond.getOpcode() == ISD::SETCC) { 8124 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8125 8126 unsigned Opcode = 0; 8127 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 8128 switch (CC) { 8129 default: break; 8130 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 8131 case ISD::SETULE: 8132 case ISD::SETLE: 8133 if (!UnsafeFPMath) break; 8134 // FALL THROUGH. 8135 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 8136 case ISD::SETLT: 8137 Opcode = X86ISD::FMIN; 8138 break; 8139 8140 case ISD::SETOGT: // (X > Y) ? X : Y -> max 8141 case ISD::SETUGT: 8142 case ISD::SETGT: 8143 if (!UnsafeFPMath) break; 8144 // FALL THROUGH. 8145 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 8146 case ISD::SETGE: 8147 Opcode = X86ISD::FMAX; 8148 break; 8149 } 8150 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8151 switch (CC) { 8152 default: break; 8153 case ISD::SETOGT: // (X > Y) ? Y : X -> min 8154 case ISD::SETUGT: 8155 case ISD::SETGT: 8156 if (!UnsafeFPMath) break; 8157 // FALL THROUGH. 8158 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 8159 case ISD::SETGE: 8160 Opcode = X86ISD::FMIN; 8161 break; 8162 8163 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 8164 case ISD::SETULE: 8165 case ISD::SETLE: 8166 if (!UnsafeFPMath) break; 8167 // FALL THROUGH. 8168 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 8169 case ISD::SETLT: 8170 Opcode = X86ISD::FMAX; 8171 break; 8172 } 8173 } 8174 8175 if (Opcode) 8176 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 8177 } 8178 8179 // If this is a select between two integer constants, try to do some 8180 // optimizations. 8181 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 8182 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 8183 // Don't do this for crazy integer types. 8184 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 8185 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 8186 // so that TrueC (the true value) is larger than FalseC. 8187 bool NeedsCondInvert = false; 8188 8189 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 8190 // Efficiently invertible. 8191 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 8192 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 8193 isa<ConstantSDNode>(Cond.getOperand(1))))) { 8194 NeedsCondInvert = true; 8195 std::swap(TrueC, FalseC); 8196 } 8197 8198 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 8199 if (FalseC->getAPIntValue() == 0 && 8200 TrueC->getAPIntValue().isPowerOf2()) { 8201 if (NeedsCondInvert) // Invert the condition if needed. 8202 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8203 DAG.getConstant(1, Cond.getValueType())); 8204 8205 // Zero extend the condition if needed. 8206 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 8207 8208 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8209 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 8210 DAG.getConstant(ShAmt, MVT::i8)); 8211 } 8212 8213 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 8214 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8215 if (NeedsCondInvert) // Invert the condition if needed. 8216 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8217 DAG.getConstant(1, Cond.getValueType())); 8218 8219 // Zero extend the condition if needed. 8220 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8221 FalseC->getValueType(0), Cond); 8222 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8223 SDValue(FalseC, 0)); 8224 } 8225 8226 // Optimize cases that will turn into an LEA instruction. This requires 8227 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8228 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8229 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8230 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8231 8232 bool isFastMultiplier = false; 8233 if (Diff < 10) { 8234 switch ((unsigned char)Diff) { 8235 default: break; 8236 case 1: // result = add base, cond 8237 case 2: // result = lea base( , cond*2) 8238 case 3: // result = lea base(cond, cond*2) 8239 case 4: // result = lea base( , cond*4) 8240 case 5: // result = lea base(cond, cond*4) 8241 case 8: // result = lea base( , cond*8) 8242 case 9: // result = lea base(cond, cond*8) 8243 isFastMultiplier = true; 8244 break; 8245 } 8246 } 8247 8248 if (isFastMultiplier) { 8249 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8250 if (NeedsCondInvert) // Invert the condition if needed. 8251 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8252 DAG.getConstant(1, Cond.getValueType())); 8253 8254 // Zero extend the condition if needed. 8255 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8256 Cond); 8257 // Scale the condition by the difference. 8258 if (Diff != 1) 8259 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8260 DAG.getConstant(Diff, Cond.getValueType())); 8261 8262 // Add the base if non-zero. 8263 if (FalseC->getAPIntValue() != 0) 8264 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8265 SDValue(FalseC, 0)); 8266 return Cond; 8267 } 8268 } 8269 } 8270 } 8271 8272 return SDValue(); 8273} 8274 8275/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 8276static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 8277 TargetLowering::DAGCombinerInfo &DCI) { 8278 DebugLoc DL = N->getDebugLoc(); 8279 8280 // If the flag operand isn't dead, don't touch this CMOV. 8281 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 8282 return SDValue(); 8283 8284 // If this is a select between two integer constants, try to do some 8285 // optimizations. Note that the operands are ordered the opposite of SELECT 8286 // operands. 8287 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 8288 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 8289 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 8290 // larger than FalseC (the false value). 8291 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 8292 8293 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 8294 CC = X86::GetOppositeBranchCondition(CC); 8295 std::swap(TrueC, FalseC); 8296 } 8297 8298 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 8299 // This is efficient for any integer data type (including i8/i16) and 8300 // shift amount. 8301 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 8302 SDValue Cond = N->getOperand(3); 8303 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8304 DAG.getConstant(CC, MVT::i8), Cond); 8305 8306 // Zero extend the condition if needed. 8307 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 8308 8309 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8310 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 8311 DAG.getConstant(ShAmt, MVT::i8)); 8312 if (N->getNumValues() == 2) // Dead flag value? 8313 return DCI.CombineTo(N, Cond, SDValue()); 8314 return Cond; 8315 } 8316 8317 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 8318 // for any integer data type, including i8/i16. 8319 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8320 SDValue Cond = N->getOperand(3); 8321 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8322 DAG.getConstant(CC, MVT::i8), Cond); 8323 8324 // Zero extend the condition if needed. 8325 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8326 FalseC->getValueType(0), Cond); 8327 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8328 SDValue(FalseC, 0)); 8329 8330 if (N->getNumValues() == 2) // Dead flag value? 8331 return DCI.CombineTo(N, Cond, SDValue()); 8332 return Cond; 8333 } 8334 8335 // Optimize cases that will turn into an LEA instruction. This requires 8336 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8337 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8338 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8339 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8340 8341 bool isFastMultiplier = false; 8342 if (Diff < 10) { 8343 switch ((unsigned char)Diff) { 8344 default: break; 8345 case 1: // result = add base, cond 8346 case 2: // result = lea base( , cond*2) 8347 case 3: // result = lea base(cond, cond*2) 8348 case 4: // result = lea base( , cond*4) 8349 case 5: // result = lea base(cond, cond*4) 8350 case 8: // result = lea base( , cond*8) 8351 case 9: // result = lea base(cond, cond*8) 8352 isFastMultiplier = true; 8353 break; 8354 } 8355 } 8356 8357 if (isFastMultiplier) { 8358 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8359 SDValue Cond = N->getOperand(3); 8360 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8361 DAG.getConstant(CC, MVT::i8), Cond); 8362 // Zero extend the condition if needed. 8363 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8364 Cond); 8365 // Scale the condition by the difference. 8366 if (Diff != 1) 8367 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8368 DAG.getConstant(Diff, Cond.getValueType())); 8369 8370 // Add the base if non-zero. 8371 if (FalseC->getAPIntValue() != 0) 8372 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8373 SDValue(FalseC, 0)); 8374 if (N->getNumValues() == 2) // Dead flag value? 8375 return DCI.CombineTo(N, Cond, SDValue()); 8376 return Cond; 8377 } 8378 } 8379 } 8380 } 8381 return SDValue(); 8382} 8383 8384 8385/// PerformMulCombine - Optimize a single multiply with constant into two 8386/// in order to implement it with two cheaper instructions, e.g. 8387/// LEA + SHL, LEA + LEA. 8388static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 8389 TargetLowering::DAGCombinerInfo &DCI) { 8390 if (DAG.getMachineFunction(). 8391 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 8392 return SDValue(); 8393 8394 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 8395 return SDValue(); 8396 8397 EVT VT = N->getValueType(0); 8398 if (VT != MVT::i64) 8399 return SDValue(); 8400 8401 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8402 if (!C) 8403 return SDValue(); 8404 uint64_t MulAmt = C->getZExtValue(); 8405 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 8406 return SDValue(); 8407 8408 uint64_t MulAmt1 = 0; 8409 uint64_t MulAmt2 = 0; 8410 if ((MulAmt % 9) == 0) { 8411 MulAmt1 = 9; 8412 MulAmt2 = MulAmt / 9; 8413 } else if ((MulAmt % 5) == 0) { 8414 MulAmt1 = 5; 8415 MulAmt2 = MulAmt / 5; 8416 } else if ((MulAmt % 3) == 0) { 8417 MulAmt1 = 3; 8418 MulAmt2 = MulAmt / 3; 8419 } 8420 if (MulAmt2 && 8421 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 8422 DebugLoc DL = N->getDebugLoc(); 8423 8424 if (isPowerOf2_64(MulAmt2) && 8425 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 8426 // If second multiplifer is pow2, issue it first. We want the multiply by 8427 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 8428 // is an add. 8429 std::swap(MulAmt1, MulAmt2); 8430 8431 SDValue NewMul; 8432 if (isPowerOf2_64(MulAmt1)) 8433 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 8434 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 8435 else 8436 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 8437 DAG.getConstant(MulAmt1, VT)); 8438 8439 if (isPowerOf2_64(MulAmt2)) 8440 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 8441 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 8442 else 8443 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 8444 DAG.getConstant(MulAmt2, VT)); 8445 8446 // Do not add new nodes to DAG combiner worklist. 8447 DCI.CombineTo(N, NewMul, false); 8448 } 8449 return SDValue(); 8450} 8451 8452 8453/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 8454/// when possible. 8455static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 8456 const X86Subtarget *Subtarget) { 8457 // On X86 with SSE2 support, we can transform this to a vector shift if 8458 // all elements are shifted by the same amount. We can't do this in legalize 8459 // because the a constant vector is typically transformed to a constant pool 8460 // so we have no knowledge of the shift amount. 8461 if (!Subtarget->hasSSE2()) 8462 return SDValue(); 8463 8464 EVT VT = N->getValueType(0); 8465 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 8466 return SDValue(); 8467 8468 SDValue ShAmtOp = N->getOperand(1); 8469 EVT EltVT = VT.getVectorElementType(); 8470 DebugLoc DL = N->getDebugLoc(); 8471 SDValue BaseShAmt; 8472 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 8473 unsigned NumElts = VT.getVectorNumElements(); 8474 unsigned i = 0; 8475 for (; i != NumElts; ++i) { 8476 SDValue Arg = ShAmtOp.getOperand(i); 8477 if (Arg.getOpcode() == ISD::UNDEF) continue; 8478 BaseShAmt = Arg; 8479 break; 8480 } 8481 for (; i != NumElts; ++i) { 8482 SDValue Arg = ShAmtOp.getOperand(i); 8483 if (Arg.getOpcode() == ISD::UNDEF) continue; 8484 if (Arg != BaseShAmt) { 8485 return SDValue(); 8486 } 8487 } 8488 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 8489 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 8490 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 8491 DAG.getIntPtrConstant(0)); 8492 } else 8493 return SDValue(); 8494 8495 if (EltVT.bitsGT(MVT::i32)) 8496 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 8497 else if (EltVT.bitsLT(MVT::i32)) 8498 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt); 8499 8500 // The shift amount is identical so we can do a vector shift. 8501 SDValue ValOp = N->getOperand(0); 8502 switch (N->getOpcode()) { 8503 default: 8504 llvm_unreachable("Unknown shift opcode!"); 8505 break; 8506 case ISD::SHL: 8507 if (VT == MVT::v2i64) 8508 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8509 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8510 ValOp, BaseShAmt); 8511 if (VT == MVT::v4i32) 8512 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8513 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8514 ValOp, BaseShAmt); 8515 if (VT == MVT::v8i16) 8516 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8517 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8518 ValOp, BaseShAmt); 8519 break; 8520 case ISD::SRA: 8521 if (VT == MVT::v4i32) 8522 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8523 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 8524 ValOp, BaseShAmt); 8525 if (VT == MVT::v8i16) 8526 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8527 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 8528 ValOp, BaseShAmt); 8529 break; 8530 case ISD::SRL: 8531 if (VT == MVT::v2i64) 8532 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8533 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8534 ValOp, BaseShAmt); 8535 if (VT == MVT::v4i32) 8536 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8537 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 8538 ValOp, BaseShAmt); 8539 if (VT == MVT::v8i16) 8540 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8541 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 8542 ValOp, BaseShAmt); 8543 break; 8544 } 8545 return SDValue(); 8546} 8547 8548/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 8549static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 8550 const X86Subtarget *Subtarget) { 8551 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 8552 // the FP state in cases where an emms may be missing. 8553 // A preferable solution to the general problem is to figure out the right 8554 // places to insert EMMS. This qualifies as a quick hack. 8555 8556 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 8557 StoreSDNode *St = cast<StoreSDNode>(N); 8558 EVT VT = St->getValue().getValueType(); 8559 if (VT.getSizeInBits() != 64) 8560 return SDValue(); 8561 8562 const Function *F = DAG.getMachineFunction().getFunction(); 8563 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 8564 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 8565 && Subtarget->hasSSE2(); 8566 if ((VT.isVector() || 8567 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 8568 isa<LoadSDNode>(St->getValue()) && 8569 !cast<LoadSDNode>(St->getValue())->isVolatile() && 8570 St->getChain().hasOneUse() && !St->isVolatile()) { 8571 SDNode* LdVal = St->getValue().getNode(); 8572 LoadSDNode *Ld = 0; 8573 int TokenFactorIndex = -1; 8574 SmallVector<SDValue, 8> Ops; 8575 SDNode* ChainVal = St->getChain().getNode(); 8576 // Must be a store of a load. We currently handle two cases: the load 8577 // is a direct child, and it's under an intervening TokenFactor. It is 8578 // possible to dig deeper under nested TokenFactors. 8579 if (ChainVal == LdVal) 8580 Ld = cast<LoadSDNode>(St->getChain()); 8581 else if (St->getValue().hasOneUse() && 8582 ChainVal->getOpcode() == ISD::TokenFactor) { 8583 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 8584 if (ChainVal->getOperand(i).getNode() == LdVal) { 8585 TokenFactorIndex = i; 8586 Ld = cast<LoadSDNode>(St->getValue()); 8587 } else 8588 Ops.push_back(ChainVal->getOperand(i)); 8589 } 8590 } 8591 8592 if (!Ld || !ISD::isNormalLoad(Ld)) 8593 return SDValue(); 8594 8595 // If this is not the MMX case, i.e. we are just turning i64 load/store 8596 // into f64 load/store, avoid the transformation if there are multiple 8597 // uses of the loaded value. 8598 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 8599 return SDValue(); 8600 8601 DebugLoc LdDL = Ld->getDebugLoc(); 8602 DebugLoc StDL = N->getDebugLoc(); 8603 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 8604 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 8605 // pair instead. 8606 if (Subtarget->is64Bit() || F64IsLegal) { 8607 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 8608 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 8609 Ld->getBasePtr(), Ld->getSrcValue(), 8610 Ld->getSrcValueOffset(), Ld->isVolatile(), 8611 Ld->getAlignment()); 8612 SDValue NewChain = NewLd.getValue(1); 8613 if (TokenFactorIndex != -1) { 8614 Ops.push_back(NewChain); 8615 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8616 Ops.size()); 8617 } 8618 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 8619 St->getSrcValue(), St->getSrcValueOffset(), 8620 St->isVolatile(), St->getAlignment()); 8621 } 8622 8623 // Otherwise, lower to two pairs of 32-bit loads / stores. 8624 SDValue LoAddr = Ld->getBasePtr(); 8625 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 8626 DAG.getConstant(4, MVT::i32)); 8627 8628 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 8629 Ld->getSrcValue(), Ld->getSrcValueOffset(), 8630 Ld->isVolatile(), Ld->getAlignment()); 8631 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 8632 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 8633 Ld->isVolatile(), 8634 MinAlign(Ld->getAlignment(), 4)); 8635 8636 SDValue NewChain = LoLd.getValue(1); 8637 if (TokenFactorIndex != -1) { 8638 Ops.push_back(LoLd); 8639 Ops.push_back(HiLd); 8640 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8641 Ops.size()); 8642 } 8643 8644 LoAddr = St->getBasePtr(); 8645 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 8646 DAG.getConstant(4, MVT::i32)); 8647 8648 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 8649 St->getSrcValue(), St->getSrcValueOffset(), 8650 St->isVolatile(), St->getAlignment()); 8651 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 8652 St->getSrcValue(), 8653 St->getSrcValueOffset() + 4, 8654 St->isVolatile(), 8655 MinAlign(St->getAlignment(), 4)); 8656 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 8657 } 8658 return SDValue(); 8659} 8660 8661/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 8662/// X86ISD::FXOR nodes. 8663static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 8664 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 8665 // F[X]OR(0.0, x) -> x 8666 // F[X]OR(x, 0.0) -> x 8667 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8668 if (C->getValueAPF().isPosZero()) 8669 return N->getOperand(1); 8670 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8671 if (C->getValueAPF().isPosZero()) 8672 return N->getOperand(0); 8673 return SDValue(); 8674} 8675 8676/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 8677static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 8678 // FAND(0.0, x) -> 0.0 8679 // FAND(x, 0.0) -> 0.0 8680 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8681 if (C->getValueAPF().isPosZero()) 8682 return N->getOperand(0); 8683 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8684 if (C->getValueAPF().isPosZero()) 8685 return N->getOperand(1); 8686 return SDValue(); 8687} 8688 8689static SDValue PerformBTCombine(SDNode *N, 8690 SelectionDAG &DAG, 8691 TargetLowering::DAGCombinerInfo &DCI) { 8692 // BT ignores high bits in the bit index operand. 8693 SDValue Op1 = N->getOperand(1); 8694 if (Op1.hasOneUse()) { 8695 unsigned BitWidth = Op1.getValueSizeInBits(); 8696 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 8697 APInt KnownZero, KnownOne; 8698 TargetLowering::TargetLoweringOpt TLO(DAG); 8699 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8700 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 8701 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 8702 DCI.CommitTargetLoweringOpt(TLO); 8703 } 8704 return SDValue(); 8705} 8706 8707static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 8708 SDValue Op = N->getOperand(0); 8709 if (Op.getOpcode() == ISD::BIT_CONVERT) 8710 Op = Op.getOperand(0); 8711 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 8712 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 8713 VT.getVectorElementType().getSizeInBits() == 8714 OpVT.getVectorElementType().getSizeInBits()) { 8715 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 8716 } 8717 return SDValue(); 8718} 8719 8720// On X86 and X86-64, atomic operations are lowered to locked instructions. 8721// Locked instructions, in turn, have implicit fence semantics (all memory 8722// operations are flushed before issuing the locked instruction, and the 8723// are not buffered), so we can fold away the common pattern of 8724// fence-atomic-fence. 8725static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 8726 SDValue atomic = N->getOperand(0); 8727 switch (atomic.getOpcode()) { 8728 case ISD::ATOMIC_CMP_SWAP: 8729 case ISD::ATOMIC_SWAP: 8730 case ISD::ATOMIC_LOAD_ADD: 8731 case ISD::ATOMIC_LOAD_SUB: 8732 case ISD::ATOMIC_LOAD_AND: 8733 case ISD::ATOMIC_LOAD_OR: 8734 case ISD::ATOMIC_LOAD_XOR: 8735 case ISD::ATOMIC_LOAD_NAND: 8736 case ISD::ATOMIC_LOAD_MIN: 8737 case ISD::ATOMIC_LOAD_MAX: 8738 case ISD::ATOMIC_LOAD_UMIN: 8739 case ISD::ATOMIC_LOAD_UMAX: 8740 break; 8741 default: 8742 return SDValue(); 8743 } 8744 8745 SDValue fence = atomic.getOperand(0); 8746 if (fence.getOpcode() != ISD::MEMBARRIER) 8747 return SDValue(); 8748 8749 switch (atomic.getOpcode()) { 8750 case ISD::ATOMIC_CMP_SWAP: 8751 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 8752 atomic.getOperand(1), atomic.getOperand(2), 8753 atomic.getOperand(3)); 8754 case ISD::ATOMIC_SWAP: 8755 case ISD::ATOMIC_LOAD_ADD: 8756 case ISD::ATOMIC_LOAD_SUB: 8757 case ISD::ATOMIC_LOAD_AND: 8758 case ISD::ATOMIC_LOAD_OR: 8759 case ISD::ATOMIC_LOAD_XOR: 8760 case ISD::ATOMIC_LOAD_NAND: 8761 case ISD::ATOMIC_LOAD_MIN: 8762 case ISD::ATOMIC_LOAD_MAX: 8763 case ISD::ATOMIC_LOAD_UMIN: 8764 case ISD::ATOMIC_LOAD_UMAX: 8765 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 8766 atomic.getOperand(1), atomic.getOperand(2)); 8767 default: 8768 return SDValue(); 8769 } 8770} 8771 8772SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 8773 DAGCombinerInfo &DCI) const { 8774 SelectionDAG &DAG = DCI.DAG; 8775 switch (N->getOpcode()) { 8776 default: break; 8777 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 8778 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 8779 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 8780 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 8781 case ISD::SHL: 8782 case ISD::SRA: 8783 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 8784 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 8785 case X86ISD::FXOR: 8786 case X86ISD::FOR: return PerformFORCombine(N, DAG); 8787 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 8788 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 8789 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 8790 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 8791 } 8792 8793 return SDValue(); 8794} 8795 8796//===----------------------------------------------------------------------===// 8797// X86 Inline Assembly Support 8798//===----------------------------------------------------------------------===// 8799 8800static bool LowerToBSwap(CallInst *CI) { 8801 // FIXME: this should verify that we are targetting a 486 or better. If not, 8802 // we will turn this bswap into something that will be lowered to logical ops 8803 // instead of emitting the bswap asm. For now, we don't support 486 or lower 8804 // so don't worry about this. 8805 8806 // Verify this is a simple bswap. 8807 if (CI->getNumOperands() != 2 || 8808 CI->getType() != CI->getOperand(1)->getType() || 8809 !CI->getType()->isInteger()) 8810 return false; 8811 8812 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8813 if (!Ty || Ty->getBitWidth() % 16 != 0) 8814 return false; 8815 8816 // Okay, we can do this xform, do so now. 8817 const Type *Tys[] = { Ty }; 8818 Module *M = CI->getParent()->getParent()->getParent(); 8819 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 8820 8821 Value *Op = CI->getOperand(1); 8822 Op = CallInst::Create(Int, Op, CI->getName(), CI); 8823 8824 CI->replaceAllUsesWith(Op); 8825 CI->eraseFromParent(); 8826 return true; 8827} 8828 8829bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 8830 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8831 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 8832 8833 std::string AsmStr = IA->getAsmString(); 8834 8835 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 8836 std::vector<std::string> AsmPieces; 8837 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 8838 8839 switch (AsmPieces.size()) { 8840 default: return false; 8841 case 1: 8842 AsmStr = AsmPieces[0]; 8843 AsmPieces.clear(); 8844 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 8845 8846 // bswap $0 8847 if (AsmPieces.size() == 2 && 8848 (AsmPieces[0] == "bswap" || 8849 AsmPieces[0] == "bswapq" || 8850 AsmPieces[0] == "bswapl") && 8851 (AsmPieces[1] == "$0" || 8852 AsmPieces[1] == "${0:q}")) { 8853 // No need to check constraints, nothing other than the equivalent of 8854 // "=r,0" would be valid here. 8855 return LowerToBSwap(CI); 8856 } 8857 // rorw $$8, ${0:w} --> llvm.bswap.i16 8858 if (CI->getType() == Type::getInt16Ty(CI->getContext()) && 8859 AsmPieces.size() == 3 && 8860 AsmPieces[0] == "rorw" && 8861 AsmPieces[1] == "$$8," && 8862 AsmPieces[2] == "${0:w}" && 8863 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") { 8864 return LowerToBSwap(CI); 8865 } 8866 break; 8867 case 3: 8868 if (CI->getType() == Type::getInt64Ty(CI->getContext()) && 8869 Constraints.size() >= 2 && 8870 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 8871 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 8872 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 8873 std::vector<std::string> Words; 8874 SplitString(AsmPieces[0], Words, " \t"); 8875 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 8876 Words.clear(); 8877 SplitString(AsmPieces[1], Words, " \t"); 8878 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 8879 Words.clear(); 8880 SplitString(AsmPieces[2], Words, " \t,"); 8881 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 8882 Words[2] == "%edx") { 8883 return LowerToBSwap(CI); 8884 } 8885 } 8886 } 8887 } 8888 break; 8889 } 8890 return false; 8891} 8892 8893 8894 8895/// getConstraintType - Given a constraint letter, return the type of 8896/// constraint it is for this target. 8897X86TargetLowering::ConstraintType 8898X86TargetLowering::getConstraintType(const std::string &Constraint) const { 8899 if (Constraint.size() == 1) { 8900 switch (Constraint[0]) { 8901 case 'A': 8902 return C_Register; 8903 case 'f': 8904 case 'r': 8905 case 'R': 8906 case 'l': 8907 case 'q': 8908 case 'Q': 8909 case 'x': 8910 case 'y': 8911 case 'Y': 8912 return C_RegisterClass; 8913 case 'e': 8914 case 'Z': 8915 return C_Other; 8916 default: 8917 break; 8918 } 8919 } 8920 return TargetLowering::getConstraintType(Constraint); 8921} 8922 8923/// LowerXConstraint - try to replace an X constraint, which matches anything, 8924/// with another that has more specific requirements based on the type of the 8925/// corresponding operand. 8926const char *X86TargetLowering:: 8927LowerXConstraint(EVT ConstraintVT) const { 8928 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 8929 // 'f' like normal targets. 8930 if (ConstraintVT.isFloatingPoint()) { 8931 if (Subtarget->hasSSE2()) 8932 return "Y"; 8933 if (Subtarget->hasSSE1()) 8934 return "x"; 8935 } 8936 8937 return TargetLowering::LowerXConstraint(ConstraintVT); 8938} 8939 8940/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8941/// vector. If it is invalid, don't add anything to Ops. 8942void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8943 char Constraint, 8944 bool hasMemory, 8945 std::vector<SDValue>&Ops, 8946 SelectionDAG &DAG) const { 8947 SDValue Result(0, 0); 8948 8949 switch (Constraint) { 8950 default: break; 8951 case 'I': 8952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8953 if (C->getZExtValue() <= 31) { 8954 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8955 break; 8956 } 8957 } 8958 return; 8959 case 'J': 8960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8961 if (C->getZExtValue() <= 63) { 8962 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8963 break; 8964 } 8965 } 8966 return; 8967 case 'K': 8968 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8969 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 8970 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8971 break; 8972 } 8973 } 8974 return; 8975 case 'N': 8976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8977 if (C->getZExtValue() <= 255) { 8978 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8979 break; 8980 } 8981 } 8982 return; 8983 case 'e': { 8984 // 32-bit signed value 8985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8986 const ConstantInt *CI = C->getConstantIntValue(); 8987 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 8988 C->getSExtValue())) { 8989 // Widen to 64 bits here to get it sign extended. 8990 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 8991 break; 8992 } 8993 // FIXME gcc accepts some relocatable values here too, but only in certain 8994 // memory models; it's complicated. 8995 } 8996 return; 8997 } 8998 case 'Z': { 8999 // 32-bit unsigned value 9000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9001 const ConstantInt *CI = C->getConstantIntValue(); 9002 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9003 C->getZExtValue())) { 9004 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9005 break; 9006 } 9007 } 9008 // FIXME gcc accepts some relocatable values here too, but only in certain 9009 // memory models; it's complicated. 9010 return; 9011 } 9012 case 'i': { 9013 // Literal immediates are always ok. 9014 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 9015 // Widen to 64 bits here to get it sign extended. 9016 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 9017 break; 9018 } 9019 9020 // If we are in non-pic codegen mode, we allow the address of a global (with 9021 // an optional displacement) to be used with 'i'. 9022 GlobalAddressSDNode *GA = 0; 9023 int64_t Offset = 0; 9024 9025 // Match either (GA), (GA+C), (GA+C1+C2), etc. 9026 while (1) { 9027 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 9028 Offset += GA->getOffset(); 9029 break; 9030 } else if (Op.getOpcode() == ISD::ADD) { 9031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9032 Offset += C->getZExtValue(); 9033 Op = Op.getOperand(0); 9034 continue; 9035 } 9036 } else if (Op.getOpcode() == ISD::SUB) { 9037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9038 Offset += -C->getZExtValue(); 9039 Op = Op.getOperand(0); 9040 continue; 9041 } 9042 } 9043 9044 // Otherwise, this isn't something we can handle, reject it. 9045 return; 9046 } 9047 9048 GlobalValue *GV = GA->getGlobal(); 9049 // If we require an extra load to get this address, as in PIC mode, we 9050 // can't accept it. 9051 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 9052 getTargetMachine()))) 9053 return; 9054 9055 if (hasMemory) 9056 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 9057 else 9058 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 9059 Result = Op; 9060 break; 9061 } 9062 } 9063 9064 if (Result.getNode()) { 9065 Ops.push_back(Result); 9066 return; 9067 } 9068 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 9069 Ops, DAG); 9070} 9071 9072std::vector<unsigned> X86TargetLowering:: 9073getRegClassForInlineAsmConstraint(const std::string &Constraint, 9074 EVT VT) const { 9075 if (Constraint.size() == 1) { 9076 // FIXME: not handling fp-stack yet! 9077 switch (Constraint[0]) { // GCC X86 Constraint Letters 9078 default: break; // Unknown constraint letter 9079 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 9080 if (Subtarget->is64Bit()) { 9081 if (VT == MVT::i32) 9082 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 9083 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 9084 X86::R10D,X86::R11D,X86::R12D, 9085 X86::R13D,X86::R14D,X86::R15D, 9086 X86::EBP, X86::ESP, 0); 9087 else if (VT == MVT::i16) 9088 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 9089 X86::SI, X86::DI, X86::R8W,X86::R9W, 9090 X86::R10W,X86::R11W,X86::R12W, 9091 X86::R13W,X86::R14W,X86::R15W, 9092 X86::BP, X86::SP, 0); 9093 else if (VT == MVT::i8) 9094 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 9095 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 9096 X86::R10B,X86::R11B,X86::R12B, 9097 X86::R13B,X86::R14B,X86::R15B, 9098 X86::BPL, X86::SPL, 0); 9099 9100 else if (VT == MVT::i64) 9101 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 9102 X86::RSI, X86::RDI, X86::R8, X86::R9, 9103 X86::R10, X86::R11, X86::R12, 9104 X86::R13, X86::R14, X86::R15, 9105 X86::RBP, X86::RSP, 0); 9106 9107 break; 9108 } 9109 // 32-bit fallthrough 9110 case 'Q': // Q_REGS 9111 if (VT == MVT::i32) 9112 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 9113 else if (VT == MVT::i16) 9114 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 9115 else if (VT == MVT::i8) 9116 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 9117 else if (VT == MVT::i64) 9118 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 9119 break; 9120 } 9121 } 9122 9123 return std::vector<unsigned>(); 9124} 9125 9126std::pair<unsigned, const TargetRegisterClass*> 9127X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 9128 EVT VT) const { 9129 // First, see if this is a constraint that directly corresponds to an LLVM 9130 // register class. 9131 if (Constraint.size() == 1) { 9132 // GCC Constraint Letters 9133 switch (Constraint[0]) { 9134 default: break; 9135 case 'r': // GENERAL_REGS 9136 case 'R': // LEGACY_REGS 9137 case 'l': // INDEX_REGS 9138 if (VT == MVT::i8) 9139 return std::make_pair(0U, X86::GR8RegisterClass); 9140 if (VT == MVT::i16) 9141 return std::make_pair(0U, X86::GR16RegisterClass); 9142 if (VT == MVT::i32 || !Subtarget->is64Bit()) 9143 return std::make_pair(0U, X86::GR32RegisterClass); 9144 return std::make_pair(0U, X86::GR64RegisterClass); 9145 case 'f': // FP Stack registers. 9146 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 9147 // value to the correct fpstack register class. 9148 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 9149 return std::make_pair(0U, X86::RFP32RegisterClass); 9150 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 9151 return std::make_pair(0U, X86::RFP64RegisterClass); 9152 return std::make_pair(0U, X86::RFP80RegisterClass); 9153 case 'y': // MMX_REGS if MMX allowed. 9154 if (!Subtarget->hasMMX()) break; 9155 return std::make_pair(0U, X86::VR64RegisterClass); 9156 case 'Y': // SSE_REGS if SSE2 allowed 9157 if (!Subtarget->hasSSE2()) break; 9158 // FALL THROUGH. 9159 case 'x': // SSE_REGS if SSE1 allowed 9160 if (!Subtarget->hasSSE1()) break; 9161 9162 switch (VT.getSimpleVT().SimpleTy) { 9163 default: break; 9164 // Scalar SSE types. 9165 case MVT::f32: 9166 case MVT::i32: 9167 return std::make_pair(0U, X86::FR32RegisterClass); 9168 case MVT::f64: 9169 case MVT::i64: 9170 return std::make_pair(0U, X86::FR64RegisterClass); 9171 // Vector types. 9172 case MVT::v16i8: 9173 case MVT::v8i16: 9174 case MVT::v4i32: 9175 case MVT::v2i64: 9176 case MVT::v4f32: 9177 case MVT::v2f64: 9178 return std::make_pair(0U, X86::VR128RegisterClass); 9179 } 9180 break; 9181 } 9182 } 9183 9184 // Use the default implementation in TargetLowering to convert the register 9185 // constraint into a member of a register class. 9186 std::pair<unsigned, const TargetRegisterClass*> Res; 9187 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 9188 9189 // Not found as a standard register? 9190 if (Res.second == 0) { 9191 // GCC calls "st(0)" just plain "st". 9192 if (StringsEqualNoCase("{st}", Constraint)) { 9193 Res.first = X86::ST0; 9194 Res.second = X86::RFP80RegisterClass; 9195 } 9196 // 'A' means EAX + EDX. 9197 if (Constraint == "A") { 9198 Res.first = X86::EAX; 9199 Res.second = X86::GR32_ADRegisterClass; 9200 } 9201 return Res; 9202 } 9203 9204 // Otherwise, check to see if this is a register class of the wrong value 9205 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 9206 // turn into {ax},{dx}. 9207 if (Res.second->hasType(VT)) 9208 return Res; // Correct type already, nothing to do. 9209 9210 // All of the single-register GCC register classes map their values onto 9211 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 9212 // really want an 8-bit or 32-bit register, map to the appropriate register 9213 // class and return the appropriate register. 9214 if (Res.second == X86::GR16RegisterClass) { 9215 if (VT == MVT::i8) { 9216 unsigned DestReg = 0; 9217 switch (Res.first) { 9218 default: break; 9219 case X86::AX: DestReg = X86::AL; break; 9220 case X86::DX: DestReg = X86::DL; break; 9221 case X86::CX: DestReg = X86::CL; break; 9222 case X86::BX: DestReg = X86::BL; break; 9223 } 9224 if (DestReg) { 9225 Res.first = DestReg; 9226 Res.second = X86::GR8RegisterClass; 9227 } 9228 } else if (VT == MVT::i32) { 9229 unsigned DestReg = 0; 9230 switch (Res.first) { 9231 default: break; 9232 case X86::AX: DestReg = X86::EAX; break; 9233 case X86::DX: DestReg = X86::EDX; break; 9234 case X86::CX: DestReg = X86::ECX; break; 9235 case X86::BX: DestReg = X86::EBX; break; 9236 case X86::SI: DestReg = X86::ESI; break; 9237 case X86::DI: DestReg = X86::EDI; break; 9238 case X86::BP: DestReg = X86::EBP; break; 9239 case X86::SP: DestReg = X86::ESP; break; 9240 } 9241 if (DestReg) { 9242 Res.first = DestReg; 9243 Res.second = X86::GR32RegisterClass; 9244 } 9245 } else if (VT == MVT::i64) { 9246 unsigned DestReg = 0; 9247 switch (Res.first) { 9248 default: break; 9249 case X86::AX: DestReg = X86::RAX; break; 9250 case X86::DX: DestReg = X86::RDX; break; 9251 case X86::CX: DestReg = X86::RCX; break; 9252 case X86::BX: DestReg = X86::RBX; break; 9253 case X86::SI: DestReg = X86::RSI; break; 9254 case X86::DI: DestReg = X86::RDI; break; 9255 case X86::BP: DestReg = X86::RBP; break; 9256 case X86::SP: DestReg = X86::RSP; break; 9257 } 9258 if (DestReg) { 9259 Res.first = DestReg; 9260 Res.second = X86::GR64RegisterClass; 9261 } 9262 } 9263 } else if (Res.second == X86::FR32RegisterClass || 9264 Res.second == X86::FR64RegisterClass || 9265 Res.second == X86::VR128RegisterClass) { 9266 // Handle references to XMM physical registers that got mapped into the 9267 // wrong class. This can happen with constraints like {xmm0} where the 9268 // target independent register mapper will just pick the first match it can 9269 // find, ignoring the required type. 9270 if (VT == MVT::f32) 9271 Res.second = X86::FR32RegisterClass; 9272 else if (VT == MVT::f64) 9273 Res.second = X86::FR64RegisterClass; 9274 else if (X86::VR128RegisterClass->hasType(VT)) 9275 Res.second = X86::VR128RegisterClass; 9276 } 9277 9278 return Res; 9279} 9280 9281//===----------------------------------------------------------------------===// 9282// X86 Widen vector type 9283//===----------------------------------------------------------------------===// 9284 9285/// getWidenVectorType: given a vector type, returns the type to widen 9286/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 9287/// If there is no vector type that we want to widen to, returns MVT::Other 9288/// When and where to widen is target dependent based on the cost of 9289/// scalarizing vs using the wider vector type. 9290 9291EVT X86TargetLowering::getWidenVectorType(EVT VT) const { 9292 assert(VT.isVector()); 9293 if (isTypeLegal(VT)) 9294 return VT; 9295 9296 // TODO: In computeRegisterProperty, we can compute the list of legal vector 9297 // type based on element type. This would speed up our search (though 9298 // it may not be worth it since the size of the list is relatively 9299 // small). 9300 EVT EltVT = VT.getVectorElementType(); 9301 unsigned NElts = VT.getVectorNumElements(); 9302 9303 // On X86, it make sense to widen any vector wider than 1 9304 if (NElts <= 1) 9305 return MVT::Other; 9306 9307 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 9308 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 9309 EVT SVT = (MVT::SimpleValueType)nVT; 9310 9311 if (isTypeLegal(SVT) && 9312 SVT.getVectorElementType() == EltVT && 9313 SVT.getVectorNumElements() > NElts) 9314 return SVT; 9315 } 9316 return MVT::Other; 9317} 9318