X86ISelLowering.cpp revision d96d0723323847156928fd34d3f049311ba948f6
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/ADT/VectorExtras.h" 26#include "llvm/Analysis/ScalarEvolutionExpressions.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/ADT/StringExtras.h" 36using namespace llvm; 37 38// FIXME: temporary. 39static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 40 cl::desc("Enable fastcc on X86")); 41X86TargetLowering::X86TargetLowering(TargetMachine &TM) 42 : TargetLowering(TM) { 43 Subtarget = &TM.getSubtarget<X86Subtarget>(); 44 X86ScalarSSE = Subtarget->hasSSE2(); 45 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 46 47 // Set up the TargetLowering object. 48 49 // X86 is weird, it always uses i8 for shift amounts and setcc results. 50 setShiftAmountType(MVT::i8); 51 setSetCCResultType(MVT::i8); 52 setSetCCResultContents(ZeroOrOneSetCCResult); 53 setSchedulingPreference(SchedulingForRegPressure); 54 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 55 setStackPointerRegisterToSaveRestore(X86StackPtr); 56 57 if (Subtarget->isTargetDarwin()) { 58 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 59 setUseUnderscoreSetJmp(false); 60 setUseUnderscoreLongJmp(false); 61 } else if (Subtarget->isTargetMingw()) { 62 // MS runtime is weird: it exports _setjmp, but longjmp! 63 setUseUnderscoreSetJmp(true); 64 setUseUnderscoreLongJmp(false); 65 } else { 66 setUseUnderscoreSetJmp(true); 67 setUseUnderscoreLongJmp(true); 68 } 69 70 // Add legal addressing mode scale values. 71 addLegalAddressScale(8); 72 addLegalAddressScale(4); 73 addLegalAddressScale(2); 74 // Enter the ones which require both scale + index last. These are more 75 // expensive. 76 addLegalAddressScale(9); 77 addLegalAddressScale(5); 78 addLegalAddressScale(3); 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 82 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 83 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 84 if (Subtarget->is64Bit()) 85 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 86 87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 88 89 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 90 // operation. 91 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 92 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 93 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 94 95 if (Subtarget->is64Bit()) { 96 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 98 } else { 99 if (X86ScalarSSE) 100 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 101 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 102 else 103 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 104 } 105 106 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 107 // this operation. 108 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 109 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 110 // SSE has no i16 to fp conversion, only i32 111 if (X86ScalarSSE) 112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 113 else { 114 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 115 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 116 } 117 118 if (!Subtarget->is64Bit()) { 119 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode. 120 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 121 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 122 } 123 124 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 125 // this operation. 126 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 127 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 128 129 if (X86ScalarSSE) { 130 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 131 } else { 132 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 133 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 134 } 135 136 // Handle FP_TO_UINT by promoting the destination to a larger signed 137 // conversion. 138 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 139 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 140 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 141 142 if (Subtarget->is64Bit()) { 143 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 145 } else { 146 if (X86ScalarSSE && !Subtarget->hasSSE3()) 147 // Expand FP_TO_UINT into a select. 148 // FIXME: We would like to use a Custom expander here eventually to do 149 // the optimal thing for SSE vs. the default expansion in the legalizer. 150 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 151 else 152 // With SSE3 we can use fisttpll to convert to a signed i64. 153 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 154 } 155 156 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 157 if (!X86ScalarSSE) { 158 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 159 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 160 } 161 162 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 163 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 164 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 165 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 166 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 167 if (Subtarget->is64Bit()) 168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 172 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 173 setOperationAction(ISD::FREM , MVT::f64 , Expand); 174 175 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 176 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 177 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 178 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 179 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 180 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 181 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 182 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 183 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 184 if (Subtarget->is64Bit()) { 185 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 186 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 187 setOperationAction(ISD::CTLZ , MVT::i64 , Expand); 188 } 189 190 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 191 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 192 193 // These should be promoted to a larger select which is supported. 194 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 195 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 196 // X86 wants to expand cmov itself. 197 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 198 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 199 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 200 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 201 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 202 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 203 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 204 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 205 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 206 if (Subtarget->is64Bit()) { 207 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 208 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 209 } 210 // X86 ret instruction may pop stack. 211 setOperationAction(ISD::RET , MVT::Other, Custom); 212 // Darwin ABI issue. 213 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 214 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 215 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 216 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 217 if (Subtarget->is64Bit()) { 218 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 219 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 220 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 221 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 222 } 223 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 224 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 225 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 226 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 227 // X86 wants to expand memset / memcpy itself. 228 setOperationAction(ISD::MEMSET , MVT::Other, Custom); 229 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 230 231 // We don't have line number support yet. 232 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 233 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 234 // FIXME - use subtarget debug flags 235 if (!Subtarget->isTargetDarwin() && 236 !Subtarget->isTargetELF() && 237 !Subtarget->isTargetCygMing()) 238 setOperationAction(ISD::LABEL, MVT::Other, Expand); 239 240 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 241 setOperationAction(ISD::VASTART , MVT::Other, Custom); 242 243 // Use the default implementation. 244 setOperationAction(ISD::VAARG , MVT::Other, Expand); 245 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 246 setOperationAction(ISD::VAEND , MVT::Other, Expand); 247 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 248 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 249 if (Subtarget->is64Bit()) 250 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 252 253 if (X86ScalarSSE) { 254 // Set up the FP register classes. 255 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 256 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 257 258 // Use ANDPD to simulate FABS. 259 setOperationAction(ISD::FABS , MVT::f64, Custom); 260 setOperationAction(ISD::FABS , MVT::f32, Custom); 261 262 // Use XORP to simulate FNEG. 263 setOperationAction(ISD::FNEG , MVT::f64, Custom); 264 setOperationAction(ISD::FNEG , MVT::f32, Custom); 265 266 // Use ANDPD and ORPD to simulate FCOPYSIGN. 267 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 268 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 269 270 // We don't support sin/cos/fmod 271 setOperationAction(ISD::FSIN , MVT::f64, Expand); 272 setOperationAction(ISD::FCOS , MVT::f64, Expand); 273 setOperationAction(ISD::FREM , MVT::f64, Expand); 274 setOperationAction(ISD::FSIN , MVT::f32, Expand); 275 setOperationAction(ISD::FCOS , MVT::f32, Expand); 276 setOperationAction(ISD::FREM , MVT::f32, Expand); 277 278 // Expand FP immediates into loads from the stack, except for the special 279 // cases we handle. 280 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 281 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 282 addLegalFPImmediate(+0.0); // xorps / xorpd 283 } else { 284 // Set up the FP register classes. 285 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 286 287 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 288 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 289 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 290 291 if (!UnsafeFPMath) { 292 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 293 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 294 } 295 296 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 297 addLegalFPImmediate(+0.0); // FLD0 298 addLegalFPImmediate(+1.0); // FLD1 299 addLegalFPImmediate(-0.0); // FLD0/FCHS 300 addLegalFPImmediate(-1.0); // FLD1/FCHS 301 } 302 303 // First set operation action for all vector types to expand. Then we 304 // will selectively turn on ones that can be effectively codegen'd. 305 for (unsigned VT = (unsigned)MVT::Vector + 1; 306 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { 307 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); 308 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); 309 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); 310 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); 311 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 312 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); 313 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 314 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 315 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 316 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 317 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 318 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); 319 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); 320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 321 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 322 } 323 324 if (Subtarget->hasMMX()) { 325 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 326 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 327 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 328 329 // FIXME: add MMX packed arithmetics 330 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); 331 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); 332 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); 333 } 334 335 if (Subtarget->hasSSE1()) { 336 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 337 338 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 339 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 340 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 341 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 342 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 343 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 344 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 346 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 347 } 348 349 if (Subtarget->hasSSE2()) { 350 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 351 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 352 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 353 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 354 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 355 356 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 357 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 358 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 359 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 360 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 361 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 362 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 363 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 364 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 365 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 366 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 367 368 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 369 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 371 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 372 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones. 373 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 374 375 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 376 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 377 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); 378 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); 379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); 380 } 381 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 382 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 383 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 387 388 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 389 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 390 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); 391 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); 392 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); 393 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); 394 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); 395 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); 396 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); 397 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); 398 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 399 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); 400 } 401 402 // Custom lower v2i64 and v2f64 selects. 403 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 404 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 405 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 406 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 407 } 408 409 // We want to custom lower some of our intrinsics. 410 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 411 412 // We have target-specific dag combine patterns for the following nodes: 413 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 414 setTargetDAGCombine(ISD::SELECT); 415 416 computeRegisterProperties(); 417 418 // FIXME: These should be based on subtarget info. Plus, the values should 419 // be smaller when we are in optimizing for size mode. 420 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores 421 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores 422 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores 423 allowUnalignedMemoryAccesses = true; // x86 supports it! 424} 425 426//===----------------------------------------------------------------------===// 427// C & StdCall Calling Convention implementation 428//===----------------------------------------------------------------------===// 429// StdCall calling convention seems to be standard for many Windows' API 430// routines and around. It differs from C calling convention just a little: 431// callee should clean up the stack, not caller. Symbols should be also 432// decorated in some fancy way :) It doesn't support any vector arguments. 433 434/// AddLiveIn - This helper function adds the specified physical register to the 435/// MachineFunction as a live in value. It also creates a corresponding virtual 436/// register for it. 437static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 438 const TargetRegisterClass *RC) { 439 assert(RC->contains(PReg) && "Not the correct regclass!"); 440 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 441 MF.addLiveIn(PReg, VReg); 442 return VReg; 443} 444 445/// HowToPassArgument - Returns how an formal argument of the specified type 446/// should be passed. If it is through stack, returns the size of the stack 447/// slot; if it is through integer or XMM register, returns the number of 448/// integer or XMM registers are needed. 449static void 450HowToPassCallArgument(MVT::ValueType ObjectVT, 451 bool ArgInReg, 452 unsigned NumIntRegs, unsigned NumXMMRegs, 453 unsigned MaxNumIntRegs, 454 unsigned &ObjSize, unsigned &ObjIntRegs, 455 unsigned &ObjXMMRegs, 456 bool AllowVectors = true) { 457 ObjSize = 0; 458 ObjIntRegs = 0; 459 ObjXMMRegs = 0; 460 461 if (MaxNumIntRegs>3) { 462 // We don't have too much registers on ia32! :) 463 MaxNumIntRegs = 3; 464 } 465 466 switch (ObjectVT) { 467 default: assert(0 && "Unhandled argument type!"); 468 case MVT::i8: 469 if (ArgInReg && (NumIntRegs < MaxNumIntRegs)) 470 ObjIntRegs = 1; 471 else 472 ObjSize = 1; 473 break; 474 case MVT::i16: 475 if (ArgInReg && (NumIntRegs < MaxNumIntRegs)) 476 ObjIntRegs = 1; 477 else 478 ObjSize = 2; 479 break; 480 case MVT::i32: 481 if (ArgInReg && (NumIntRegs < MaxNumIntRegs)) 482 ObjIntRegs = 1; 483 else 484 ObjSize = 4; 485 break; 486 case MVT::i64: 487 if (ArgInReg && (NumIntRegs+2 <= MaxNumIntRegs)) { 488 ObjIntRegs = 2; 489 } else if (ArgInReg && (NumIntRegs+1 <= MaxNumIntRegs)) { 490 ObjIntRegs = 1; 491 ObjSize = 4; 492 } else 493 ObjSize = 8; 494 case MVT::f32: 495 ObjSize = 4; 496 break; 497 case MVT::f64: 498 ObjSize = 8; 499 break; 500 case MVT::v16i8: 501 case MVT::v8i16: 502 case MVT::v4i32: 503 case MVT::v2i64: 504 case MVT::v4f32: 505 case MVT::v2f64: 506 if (AllowVectors) { 507 if (NumXMMRegs < 4) 508 ObjXMMRegs = 1; 509 else 510 ObjSize = 16; 511 break; 512 } else 513 assert(0 && "Unhandled argument type [vector]!"); 514 } 515} 516 517SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG, 518 bool isStdCall) { 519 unsigned NumArgs = Op.Val->getNumValues() - 1; 520 MachineFunction &MF = DAG.getMachineFunction(); 521 MachineFrameInfo *MFI = MF.getFrameInfo(); 522 SDOperand Root = Op.getOperand(0); 523 std::vector<SDOperand> ArgValues; 524 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 525 526 // Add DAG nodes to load the arguments... On entry to a function on the X86, 527 // the stack frame looks like this: 528 // 529 // [ESP] -- return address 530 // [ESP + 4] -- first argument (leftmost lexically) 531 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size 532 // ... 533 // 534 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 535 unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return 536 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 537 unsigned NumIntRegs = 0; // Integer regs used for parameter passing 538 539 static const unsigned XMMArgRegs[] = { 540 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 541 }; 542 static const unsigned GPRArgRegs[][3] = { 543 { X86::AL, X86::DL, X86::CL }, 544 { X86::AX, X86::DX, X86::CX }, 545 { X86::EAX, X86::EDX, X86::ECX } 546 }; 547 static const TargetRegisterClass* GPRClasses[3] = { 548 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass 549 }; 550 551 // Handle regparm attribute 552 std::vector<bool> ArgInRegs(NumArgs, false); 553 std::vector<bool> SRetArgs(NumArgs, false); 554 if (!isVarArg) { 555 for (unsigned i = 0; i<NumArgs; ++i) { 556 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue(); 557 ArgInRegs[i] = (Flags >> 1) & 1; 558 SRetArgs[i] = (Flags >> 2) & 1; 559 } 560 } 561 562 for (unsigned i = 0; i < NumArgs; ++i) { 563 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 564 unsigned ArgIncrement = 4; 565 unsigned ObjSize = 0; 566 unsigned ObjXMMRegs = 0; 567 unsigned ObjIntRegs = 0; 568 unsigned Reg = 0; 569 SDOperand ArgValue; 570 571 HowToPassCallArgument(ObjectVT, 572 ArgInRegs[i], 573 NumIntRegs, NumXMMRegs, 3, 574 ObjSize, ObjIntRegs, ObjXMMRegs, 575 !isStdCall); 576 577 if (ObjSize > 4) 578 ArgIncrement = ObjSize; 579 580 if (ObjIntRegs || ObjXMMRegs) { 581 switch (ObjectVT) { 582 default: assert(0 && "Unhandled argument type!"); 583 case MVT::i8: 584 case MVT::i16: 585 case MVT::i32: { 586 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs]; 587 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]); 588 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 589 break; 590 } 591 case MVT::v16i8: 592 case MVT::v8i16: 593 case MVT::v4i32: 594 case MVT::v2i64: 595 case MVT::v4f32: 596 case MVT::v2f64: 597 assert(!isStdCall && "Unhandled argument type!"); 598 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); 599 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 600 break; 601 } 602 NumIntRegs += ObjIntRegs; 603 NumXMMRegs += ObjXMMRegs; 604 } 605 if (ObjSize) { 606 // XMM arguments have to be aligned on 16-byte boundary. 607 if (ObjSize == 16) 608 ArgOffset = ((ArgOffset + 15) / 16) * 16; 609 // Create the SelectionDAG nodes corresponding to a load from this 610 // parameter. 611 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 612 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 613 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); 614 615 ArgOffset += ArgIncrement; // Move on to the next argument. 616 if (SRetArgs[i]) 617 NumSRetBytes += ArgIncrement; 618 } 619 620 ArgValues.push_back(ArgValue); 621 } 622 623 ArgValues.push_back(Root); 624 625 // If the function takes variable number of arguments, make a frame index for 626 // the start of the first vararg value... for expansion of llvm.va_start. 627 if (isVarArg) 628 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 629 630 if (isStdCall && !isVarArg) { 631 BytesToPopOnReturn = ArgOffset; // Callee pops everything.. 632 BytesCallerReserves = 0; 633 } else { 634 BytesToPopOnReturn = NumSRetBytes; // Callee pops hidden struct pointer. 635 BytesCallerReserves = ArgOffset; 636 } 637 638 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 639 ReturnAddrIndex = 0; // No return address slot generated yet. 640 641 642 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 643 644 // Return the new list of results. 645 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 646 Op.Val->value_end()); 647 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 648} 649 650SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, 651 bool isStdCall) { 652 SDOperand Chain = Op.getOperand(0); 653 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 654 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 655 SDOperand Callee = Op.getOperand(4); 656 MVT::ValueType RetVT= Op.Val->getValueType(0); 657 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 658 659 static const unsigned XMMArgRegs[] = { 660 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 661 }; 662 static const unsigned GPR32ArgRegs[] = { 663 X86::EAX, X86::EDX, X86::ECX 664 }; 665 666 // Count how many bytes are to be pushed on the stack. 667 unsigned NumBytes = 0; 668 // Keep track of the number of integer regs passed so far. 669 unsigned NumIntRegs = 0; 670 // Keep track of the number of XMM regs passed so far. 671 unsigned NumXMMRegs = 0; 672 // How much bytes on stack used for struct return 673 unsigned NumSRetBytes= 0; 674 675 // Handle regparm attribute 676 std::vector<bool> ArgInRegs(NumOps, false); 677 std::vector<bool> SRetArgs(NumOps, false); 678 for (unsigned i = 0; i<NumOps; ++i) { 679 unsigned Flags = 680 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 681 ArgInRegs[i] = (Flags >> 1) & 1; 682 SRetArgs[i] = (Flags >> 2) & 1; 683 } 684 685 // Calculate stack frame size 686 for (unsigned i = 0; i != NumOps; ++i) { 687 SDOperand Arg = Op.getOperand(5+2*i); 688 unsigned ArgIncrement = 4; 689 unsigned ObjSize = 0; 690 unsigned ObjIntRegs = 0; 691 unsigned ObjXMMRegs = 0; 692 693 HowToPassCallArgument(Arg.getValueType(), 694 ArgInRegs[i], 695 NumIntRegs, NumXMMRegs, 3, 696 ObjSize, ObjIntRegs, ObjXMMRegs, 697 !isStdCall); 698 if (ObjSize > 4) 699 ArgIncrement = ObjSize; 700 701 NumIntRegs += ObjIntRegs; 702 NumXMMRegs += ObjXMMRegs; 703 if (ObjSize) { 704 // XMM arguments have to be aligned on 16-byte boundary. 705 if (ObjSize == 16) 706 NumBytes = ((NumBytes + 15) / 16) * 16; 707 NumBytes += ArgIncrement; 708 } 709 } 710 711 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 712 713 // Arguments go on the stack in reverse order, as specified by the ABI. 714 unsigned ArgOffset = 0; 715 NumXMMRegs = 0; 716 NumIntRegs = 0; 717 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 718 std::vector<SDOperand> MemOpChains; 719 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 720 for (unsigned i = 0; i != NumOps; ++i) { 721 SDOperand Arg = Op.getOperand(5+2*i); 722 unsigned ArgIncrement = 4; 723 unsigned ObjSize = 0; 724 unsigned ObjIntRegs = 0; 725 unsigned ObjXMMRegs = 0; 726 727 HowToPassCallArgument(Arg.getValueType(), 728 ArgInRegs[i], 729 NumIntRegs, NumXMMRegs, 3, 730 ObjSize, ObjIntRegs, ObjXMMRegs, 731 !isStdCall); 732 733 if (ObjSize > 4) 734 ArgIncrement = ObjSize; 735 736 if (Arg.getValueType() == MVT::i8 || Arg.getValueType() == MVT::i16) { 737 // Promote the integer to 32 bits. If the input type is signed use a 738 // sign extend, otherwise use a zero extend. 739 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 740 741 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 742 Arg = DAG.getNode(ExtOp, MVT::i32, Arg); 743 } 744 745 if (ObjIntRegs || ObjXMMRegs) { 746 switch (Arg.getValueType()) { 747 default: assert(0 && "Unhandled argument type!"); 748 case MVT::i32: 749 RegsToPass.push_back(std::make_pair(GPR32ArgRegs[NumIntRegs], Arg)); 750 break; 751 case MVT::v16i8: 752 case MVT::v8i16: 753 case MVT::v4i32: 754 case MVT::v2i64: 755 case MVT::v4f32: 756 case MVT::v2f64: 757 assert(!isStdCall && "Unhandled argument type!"); 758 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 759 break; 760 } 761 762 NumIntRegs += ObjIntRegs; 763 NumXMMRegs += ObjXMMRegs; 764 } 765 if (ObjSize) { 766 // XMM arguments have to be aligned on 16-byte boundary. 767 if (ObjSize == 16) 768 ArgOffset = ((ArgOffset + 15) / 16) * 16; 769 770 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 771 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 772 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 773 774 ArgOffset += ArgIncrement; // Move on to the next argument. 775 if (SRetArgs[i]) 776 NumSRetBytes += ArgIncrement; 777 } 778 } 779 780 // Sanity check: we haven't seen NumSRetBytes > 4 781 assert((NumSRetBytes<=4) && 782 "Too much space for struct-return pointer requested"); 783 784 if (!MemOpChains.empty()) 785 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 786 &MemOpChains[0], MemOpChains.size()); 787 788 // Build a sequence of copy-to-reg nodes chained together with token chain 789 // and flag operands which copy the outgoing args into registers. 790 SDOperand InFlag; 791 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 792 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 793 InFlag); 794 InFlag = Chain.getValue(1); 795 } 796 797 // ELF / PIC requires GOT in the EBX register before function calls via PLT 798 // GOT pointer. 799 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 800 Subtarget->isPICStyleGOT()) { 801 Chain = DAG.getCopyToReg(Chain, X86::EBX, 802 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 803 InFlag); 804 InFlag = Chain.getValue(1); 805 } 806 807 // If the callee is a GlobalAddress node (quite common, every direct call is) 808 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 809 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 810 // We should use extra load for direct calls to dllimported functions in 811 // non-JIT mode. 812 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 813 getTargetMachine(), true)) 814 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 815 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 816 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 817 818 // Returns a chain & a flag for retval copy to use. 819 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 820 std::vector<SDOperand> Ops; 821 Ops.push_back(Chain); 822 Ops.push_back(Callee); 823 824 // Add argument registers to the end of the list so that they are known live 825 // into the call. 826 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 827 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 828 RegsToPass[i].second.getValueType())); 829 830 // Add an implicit use GOT pointer in EBX. 831 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 832 Subtarget->isPICStyleGOT()) 833 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 834 835 if (InFlag.Val) 836 Ops.push_back(InFlag); 837 838 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 839 NodeTys, &Ops[0], Ops.size()); 840 InFlag = Chain.getValue(1); 841 842 // Create the CALLSEQ_END node. 843 unsigned NumBytesForCalleeToPush = 0; 844 845 if (isStdCall) { 846 if (isVarArg) { 847 NumBytesForCalleeToPush = NumSRetBytes; 848 } else { 849 NumBytesForCalleeToPush = NumBytes; 850 } 851 } else { 852 // If this is is a call to a struct-return function, the callee 853 // pops the hidden struct pointer, so we have to push it back. 854 // This is common for Darwin/X86, Linux & Mingw32 targets. 855 NumBytesForCalleeToPush = NumSRetBytes; 856 } 857 858 if (RetVT != MVT::Other) 859 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 860 else 861 NodeTys = DAG.getVTList(MVT::Other); 862 Ops.clear(); 863 Ops.push_back(Chain); 864 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 865 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy())); 866 Ops.push_back(InFlag); 867 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 868 if (RetVT != MVT::Other) 869 InFlag = Chain.getValue(1); 870 871 std::vector<SDOperand> ResultVals; 872 switch (RetVT) { 873 default: assert(0 && "Unknown value type to return!"); 874 case MVT::Other: break; 875 case MVT::i8: 876 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 877 ResultVals.push_back(Chain.getValue(0)); 878 NodeTys = DAG.getVTList(MVT::i8, MVT::Other); 879 break; 880 case MVT::i16: 881 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 882 ResultVals.push_back(Chain.getValue(0)); 883 NodeTys = DAG.getVTList(MVT::i16, MVT::Other); 884 break; 885 case MVT::i32: 886 if (Op.Val->getValueType(1) == MVT::i32) { 887 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 888 ResultVals.push_back(Chain.getValue(0)); 889 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32, 890 Chain.getValue(2)).getValue(1); 891 ResultVals.push_back(Chain.getValue(0)); 892 NodeTys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 893 } else { 894 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 895 ResultVals.push_back(Chain.getValue(0)); 896 NodeTys = DAG.getVTList(MVT::i32, MVT::Other); 897 } 898 break; 899 case MVT::v16i8: 900 case MVT::v8i16: 901 case MVT::v4i32: 902 case MVT::v2i64: 903 case MVT::v4f32: 904 case MVT::v2f64: 905 assert(!isStdCall && "Unknown value type to return!"); 906 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 907 ResultVals.push_back(Chain.getValue(0)); 908 NodeTys = DAG.getVTList(RetVT, MVT::Other); 909 break; 910 case MVT::f32: 911 case MVT::f64: { 912 std::vector<MVT::ValueType> Tys; 913 Tys.push_back(MVT::f64); 914 Tys.push_back(MVT::Other); 915 Tys.push_back(MVT::Flag); 916 std::vector<SDOperand> Ops; 917 Ops.push_back(Chain); 918 Ops.push_back(InFlag); 919 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 920 &Ops[0], Ops.size()); 921 Chain = RetVal.getValue(1); 922 InFlag = RetVal.getValue(2); 923 if (X86ScalarSSE) { 924 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 925 // shouldn't be necessary except that RFP cannot be live across 926 // multiple blocks. When stackifier is fixed, they can be uncoupled. 927 MachineFunction &MF = DAG.getMachineFunction(); 928 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 929 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 930 Tys.clear(); 931 Tys.push_back(MVT::Other); 932 Ops.clear(); 933 Ops.push_back(Chain); 934 Ops.push_back(RetVal); 935 Ops.push_back(StackSlot); 936 Ops.push_back(DAG.getValueType(RetVT)); 937 Ops.push_back(InFlag); 938 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 939 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0); 940 Chain = RetVal.getValue(1); 941 } 942 943 if (RetVT == MVT::f32 && !X86ScalarSSE) 944 // FIXME: we would really like to remember that this FP_ROUND 945 // operation is okay to eliminate if we allow excess FP precision. 946 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 947 ResultVals.push_back(RetVal); 948 NodeTys = DAG.getVTList(RetVT, MVT::Other); 949 break; 950 } 951 } 952 953 // If the function returns void, just return the chain. 954 if (ResultVals.empty()) 955 return Chain; 956 957 // Otherwise, merge everything together with a MERGE_VALUES node. 958 ResultVals.push_back(Chain); 959 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 960 &ResultVals[0], ResultVals.size()); 961 return Res.getValue(Op.ResNo); 962} 963 964 965//===----------------------------------------------------------------------===// 966// X86-64 C Calling Convention implementation 967//===----------------------------------------------------------------------===// 968 969/// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified 970/// type should be passed. If it is through stack, returns the size of the stack 971/// slot; if it is through integer or XMM register, returns the number of 972/// integer or XMM registers are needed. 973static void 974HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT, 975 unsigned NumIntRegs, unsigned NumXMMRegs, 976 unsigned &ObjSize, unsigned &ObjIntRegs, 977 unsigned &ObjXMMRegs) { 978 ObjSize = 0; 979 ObjIntRegs = 0; 980 ObjXMMRegs = 0; 981 982 switch (ObjectVT) { 983 default: assert(0 && "Unhandled argument type!"); 984 case MVT::i8: 985 case MVT::i16: 986 case MVT::i32: 987 case MVT::i64: 988 if (NumIntRegs < 6) 989 ObjIntRegs = 1; 990 else { 991 switch (ObjectVT) { 992 default: break; 993 case MVT::i8: ObjSize = 1; break; 994 case MVT::i16: ObjSize = 2; break; 995 case MVT::i32: ObjSize = 4; break; 996 case MVT::i64: ObjSize = 8; break; 997 } 998 } 999 break; 1000 case MVT::f32: 1001 case MVT::f64: 1002 case MVT::v16i8: 1003 case MVT::v8i16: 1004 case MVT::v4i32: 1005 case MVT::v2i64: 1006 case MVT::v4f32: 1007 case MVT::v2f64: 1008 if (NumXMMRegs < 8) 1009 ObjXMMRegs = 1; 1010 else { 1011 switch (ObjectVT) { 1012 default: break; 1013 case MVT::f32: ObjSize = 4; break; 1014 case MVT::f64: ObjSize = 8; break; 1015 case MVT::v16i8: 1016 case MVT::v8i16: 1017 case MVT::v4i32: 1018 case MVT::v2i64: 1019 case MVT::v4f32: 1020 case MVT::v2f64: ObjSize = 16; break; 1021 } 1022 break; 1023 } 1024 } 1025} 1026 1027SDOperand 1028X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { 1029 unsigned NumArgs = Op.Val->getNumValues() - 1; 1030 MachineFunction &MF = DAG.getMachineFunction(); 1031 MachineFrameInfo *MFI = MF.getFrameInfo(); 1032 SDOperand Root = Op.getOperand(0); 1033 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1034 std::vector<SDOperand> ArgValues; 1035 1036 // Add DAG nodes to load the arguments... On entry to a function on the X86, 1037 // the stack frame looks like this: 1038 // 1039 // [RSP] -- return address 1040 // [RSP + 8] -- first nonreg argument (leftmost lexically) 1041 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size 1042 // ... 1043 // 1044 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 1045 unsigned NumIntRegs = 0; // Int regs used for parameter passing. 1046 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1047 1048 static const unsigned GPR8ArgRegs[] = { 1049 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B 1050 }; 1051 static const unsigned GPR16ArgRegs[] = { 1052 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W 1053 }; 1054 static const unsigned GPR32ArgRegs[] = { 1055 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 1056 }; 1057 static const unsigned GPR64ArgRegs[] = { 1058 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1059 }; 1060 static const unsigned XMMArgRegs[] = { 1061 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1062 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1063 }; 1064 1065 for (unsigned i = 0; i < NumArgs; ++i) { 1066 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 1067 unsigned ArgIncrement = 8; 1068 unsigned ObjSize = 0; 1069 unsigned ObjIntRegs = 0; 1070 unsigned ObjXMMRegs = 0; 1071 1072 // FIXME: __int128 and long double support? 1073 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs, 1074 ObjSize, ObjIntRegs, ObjXMMRegs); 1075 if (ObjSize > 8) 1076 ArgIncrement = ObjSize; 1077 1078 unsigned Reg = 0; 1079 SDOperand ArgValue; 1080 if (ObjIntRegs || ObjXMMRegs) { 1081 switch (ObjectVT) { 1082 default: assert(0 && "Unhandled argument type!"); 1083 case MVT::i8: 1084 case MVT::i16: 1085 case MVT::i32: 1086 case MVT::i64: { 1087 TargetRegisterClass *RC = NULL; 1088 switch (ObjectVT) { 1089 default: break; 1090 case MVT::i8: 1091 RC = X86::GR8RegisterClass; 1092 Reg = GPR8ArgRegs[NumIntRegs]; 1093 break; 1094 case MVT::i16: 1095 RC = X86::GR16RegisterClass; 1096 Reg = GPR16ArgRegs[NumIntRegs]; 1097 break; 1098 case MVT::i32: 1099 RC = X86::GR32RegisterClass; 1100 Reg = GPR32ArgRegs[NumIntRegs]; 1101 break; 1102 case MVT::i64: 1103 RC = X86::GR64RegisterClass; 1104 Reg = GPR64ArgRegs[NumIntRegs]; 1105 break; 1106 } 1107 Reg = AddLiveIn(MF, Reg, RC); 1108 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 1109 break; 1110 } 1111 case MVT::f32: 1112 case MVT::f64: 1113 case MVT::v16i8: 1114 case MVT::v8i16: 1115 case MVT::v4i32: 1116 case MVT::v2i64: 1117 case MVT::v4f32: 1118 case MVT::v2f64: { 1119 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ? 1120 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ? 1121 X86::FR64RegisterClass : X86::VR128RegisterClass); 1122 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC); 1123 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 1124 break; 1125 } 1126 } 1127 NumIntRegs += ObjIntRegs; 1128 NumXMMRegs += ObjXMMRegs; 1129 } else if (ObjSize) { 1130 // XMM arguments have to be aligned on 16-byte boundary. 1131 if (ObjSize == 16) 1132 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1133 // Create the SelectionDAG nodes corresponding to a load from this 1134 // parameter. 1135 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1136 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1137 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); 1138 ArgOffset += ArgIncrement; // Move on to the next argument. 1139 } 1140 1141 ArgValues.push_back(ArgValue); 1142 } 1143 1144 // If the function takes variable number of arguments, make a frame index for 1145 // the start of the first vararg value... for expansion of llvm.va_start. 1146 if (isVarArg) { 1147 // For X86-64, if there are vararg parameters that are passed via 1148 // registers, then we must store them to their spots on the stack so they 1149 // may be loaded by deferencing the result of va_next. 1150 VarArgsGPOffset = NumIntRegs * 8; 1151 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16; 1152 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 1153 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16); 1154 1155 // Store the integer parameter registers. 1156 std::vector<SDOperand> MemOps; 1157 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1158 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1159 DAG.getConstant(VarArgsGPOffset, getPointerTy())); 1160 for (; NumIntRegs != 6; ++NumIntRegs) { 1161 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1162 X86::GR64RegisterClass); 1163 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1164 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1165 MemOps.push_back(Store); 1166 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1167 DAG.getConstant(8, getPointerTy())); 1168 } 1169 1170 // Now store the XMM (fp + vector) parameter registers. 1171 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1172 DAG.getConstant(VarArgsFPOffset, getPointerTy())); 1173 for (; NumXMMRegs != 8; ++NumXMMRegs) { 1174 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1175 X86::VR128RegisterClass); 1176 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1177 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1178 MemOps.push_back(Store); 1179 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1180 DAG.getConstant(16, getPointerTy())); 1181 } 1182 if (!MemOps.empty()) 1183 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1184 &MemOps[0], MemOps.size()); 1185 } 1186 1187 ArgValues.push_back(Root); 1188 1189 ReturnAddrIndex = 0; // No return address slot generated yet. 1190 BytesToPopOnReturn = 0; // Callee pops nothing. 1191 BytesCallerReserves = ArgOffset; 1192 1193 // Return the new list of results. 1194 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 1195 Op.Val->value_end()); 1196 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 1197} 1198 1199SDOperand 1200X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) { 1201 SDOperand Chain = Op.getOperand(0); 1202 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1203 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1204 SDOperand Callee = Op.getOperand(4); 1205 MVT::ValueType RetVT= Op.Val->getValueType(0); 1206 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1207 1208 // Count how many bytes are to be pushed on the stack. 1209 unsigned NumBytes = 0; 1210 unsigned NumIntRegs = 0; // Int regs used for parameter passing. 1211 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1212 1213 static const unsigned GPR8ArgRegs[] = { 1214 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B 1215 }; 1216 static const unsigned GPR16ArgRegs[] = { 1217 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W 1218 }; 1219 static const unsigned GPR32ArgRegs[] = { 1220 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 1221 }; 1222 static const unsigned GPR64ArgRegs[] = { 1223 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1224 }; 1225 static const unsigned XMMArgRegs[] = { 1226 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1227 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1228 }; 1229 1230 for (unsigned i = 0; i != NumOps; ++i) { 1231 SDOperand Arg = Op.getOperand(5+2*i); 1232 MVT::ValueType ArgVT = Arg.getValueType(); 1233 1234 switch (ArgVT) { 1235 default: assert(0 && "Unknown value type!"); 1236 case MVT::i8: 1237 case MVT::i16: 1238 case MVT::i32: 1239 case MVT::i64: 1240 if (NumIntRegs < 6) 1241 ++NumIntRegs; 1242 else 1243 NumBytes += 8; 1244 break; 1245 case MVT::f32: 1246 case MVT::f64: 1247 case MVT::v16i8: 1248 case MVT::v8i16: 1249 case MVT::v4i32: 1250 case MVT::v2i64: 1251 case MVT::v4f32: 1252 case MVT::v2f64: 1253 if (NumXMMRegs < 8) 1254 NumXMMRegs++; 1255 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64) 1256 NumBytes += 8; 1257 else { 1258 // XMM arguments have to be aligned on 16-byte boundary. 1259 NumBytes = ((NumBytes + 15) / 16) * 16; 1260 NumBytes += 16; 1261 } 1262 break; 1263 } 1264 } 1265 1266 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1267 1268 // Arguments go on the stack in reverse order, as specified by the ABI. 1269 unsigned ArgOffset = 0; 1270 NumIntRegs = 0; 1271 NumXMMRegs = 0; 1272 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1273 std::vector<SDOperand> MemOpChains; 1274 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 1275 for (unsigned i = 0; i != NumOps; ++i) { 1276 SDOperand Arg = Op.getOperand(5+2*i); 1277 MVT::ValueType ArgVT = Arg.getValueType(); 1278 1279 switch (ArgVT) { 1280 default: assert(0 && "Unexpected ValueType for argument!"); 1281 case MVT::i8: 1282 case MVT::i16: 1283 case MVT::i32: 1284 case MVT::i64: 1285 if (NumIntRegs < 6) { 1286 unsigned Reg = 0; 1287 switch (ArgVT) { 1288 default: break; 1289 case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break; 1290 case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break; 1291 case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break; 1292 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break; 1293 } 1294 RegsToPass.push_back(std::make_pair(Reg, Arg)); 1295 ++NumIntRegs; 1296 } else { 1297 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1298 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1299 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1300 ArgOffset += 8; 1301 } 1302 break; 1303 case MVT::f32: 1304 case MVT::f64: 1305 case MVT::v16i8: 1306 case MVT::v8i16: 1307 case MVT::v4i32: 1308 case MVT::v2i64: 1309 case MVT::v4f32: 1310 case MVT::v2f64: 1311 if (NumXMMRegs < 8) { 1312 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 1313 NumXMMRegs++; 1314 } else { 1315 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) { 1316 // XMM arguments have to be aligned on 16-byte boundary. 1317 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1318 } 1319 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1320 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1321 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1322 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) 1323 ArgOffset += 8; 1324 else 1325 ArgOffset += 16; 1326 } 1327 } 1328 } 1329 1330 if (!MemOpChains.empty()) 1331 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1332 &MemOpChains[0], MemOpChains.size()); 1333 1334 // Build a sequence of copy-to-reg nodes chained together with token chain 1335 // and flag operands which copy the outgoing args into registers. 1336 SDOperand InFlag; 1337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1338 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1339 InFlag); 1340 InFlag = Chain.getValue(1); 1341 } 1342 1343 if (isVarArg) { 1344 // From AMD64 ABI document: 1345 // For calls that may call functions that use varargs or stdargs 1346 // (prototype-less calls or calls to functions containing ellipsis (...) in 1347 // the declaration) %al is used as hidden argument to specify the number 1348 // of SSE registers used. The contents of %al do not need to match exactly 1349 // the number of registers, but must be an ubound on the number of SSE 1350 // registers used and is in the range 0 - 8 inclusive. 1351 Chain = DAG.getCopyToReg(Chain, X86::AL, 1352 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1353 InFlag = Chain.getValue(1); 1354 } 1355 1356 // If the callee is a GlobalAddress node (quite common, every direct call is) 1357 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1358 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1359 // We should use extra load for direct calls to dllimported functions in 1360 // non-JIT mode. 1361 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1362 getTargetMachine(), true)) 1363 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1364 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1365 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1366 1367 // Returns a chain & a flag for retval copy to use. 1368 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1369 std::vector<SDOperand> Ops; 1370 Ops.push_back(Chain); 1371 Ops.push_back(Callee); 1372 1373 // Add argument registers to the end of the list so that they are known live 1374 // into the call. 1375 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1376 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1377 RegsToPass[i].second.getValueType())); 1378 1379 if (InFlag.Val) 1380 Ops.push_back(InFlag); 1381 1382 // FIXME: Do not generate X86ISD::TAILCALL for now. 1383 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1384 NodeTys, &Ops[0], Ops.size()); 1385 InFlag = Chain.getValue(1); 1386 1387 if (RetVT != MVT::Other) 1388 // Returns a flag for retval copy to use. 1389 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1390 else 1391 NodeTys = DAG.getVTList(MVT::Other); 1392 Ops.clear(); 1393 Ops.push_back(Chain); 1394 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1395 Ops.push_back(DAG.getConstant(0, getPointerTy())); 1396 Ops.push_back(InFlag); 1397 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1398 if (RetVT != MVT::Other) 1399 InFlag = Chain.getValue(1); 1400 1401 std::vector<SDOperand> ResultVals; 1402 switch (RetVT) { 1403 default: assert(0 && "Unknown value type to return!"); 1404 case MVT::Other: break; 1405 case MVT::i8: 1406 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 1407 ResultVals.push_back(Chain.getValue(0)); 1408 NodeTys = DAG.getVTList(MVT::i8, MVT::Other); 1409 break; 1410 case MVT::i16: 1411 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 1412 ResultVals.push_back(Chain.getValue(0)); 1413 NodeTys = DAG.getVTList(MVT::i16, MVT::Other); 1414 break; 1415 case MVT::i32: 1416 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1417 ResultVals.push_back(Chain.getValue(0)); 1418 NodeTys = DAG.getVTList(MVT::i32, MVT::Other); 1419 break; 1420 case MVT::i64: 1421 if (Op.Val->getValueType(1) == MVT::i64) { 1422 // FIXME: __int128 support? 1423 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1); 1424 ResultVals.push_back(Chain.getValue(0)); 1425 Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64, 1426 Chain.getValue(2)).getValue(1); 1427 ResultVals.push_back(Chain.getValue(0)); 1428 NodeTys = DAG.getVTList(MVT::i64, MVT::i64, MVT::Other); 1429 } else { 1430 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1); 1431 ResultVals.push_back(Chain.getValue(0)); 1432 NodeTys = DAG.getVTList(MVT::i64, MVT::Other); 1433 } 1434 break; 1435 case MVT::f32: 1436 case MVT::f64: 1437 case MVT::v16i8: 1438 case MVT::v8i16: 1439 case MVT::v4i32: 1440 case MVT::v2i64: 1441 case MVT::v4f32: 1442 case MVT::v2f64: 1443 // FIXME: long double support? 1444 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 1445 ResultVals.push_back(Chain.getValue(0)); 1446 NodeTys = DAG.getVTList(RetVT, MVT::Other); 1447 break; 1448 } 1449 1450 // If the function returns void, just return the chain. 1451 if (ResultVals.empty()) 1452 return Chain; 1453 1454 // Otherwise, merge everything together with a MERGE_VALUES node. 1455 ResultVals.push_back(Chain); 1456 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1457 &ResultVals[0], ResultVals.size()); 1458 return Res.getValue(Op.ResNo); 1459} 1460 1461//===----------------------------------------------------------------------===// 1462// Fast & FastCall Calling Convention implementation 1463//===----------------------------------------------------------------------===// 1464// 1465// The X86 'fast' calling convention passes up to two integer arguments in 1466// registers (an appropriate portion of EAX/EDX), passes arguments in C order, 1467// and requires that the callee pop its arguments off the stack (allowing proper 1468// tail calls), and has the same return value conventions as C calling convs. 1469// 1470// This calling convention always arranges for the callee pop value to be 8n+4 1471// bytes, which is needed for tail recursion elimination and stack alignment 1472// reasons. 1473// 1474// Note that this can be enhanced in the future to pass fp vals in registers 1475// (when we have a global fp allocator) and do other tricks. 1476// 1477//===----------------------------------------------------------------------===// 1478// The X86 'fastcall' calling convention passes up to two integer arguments in 1479// registers (an appropriate portion of ECX/EDX), passes arguments in C order, 1480// and requires that the callee pop its arguments off the stack (allowing proper 1481// tail calls), and has the same return value conventions as C calling convs. 1482// 1483// This calling convention always arranges for the callee pop value to be 8n+4 1484// bytes, which is needed for tail recursion elimination and stack alignment 1485// reasons. 1486 1487 1488SDOperand 1489X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG, 1490 bool isFastCall) { 1491 unsigned NumArgs = Op.Val->getNumValues()-1; 1492 MachineFunction &MF = DAG.getMachineFunction(); 1493 MachineFrameInfo *MFI = MF.getFrameInfo(); 1494 SDOperand Root = Op.getOperand(0); 1495 std::vector<SDOperand> ArgValues; 1496 1497 // Add DAG nodes to load the arguments... On entry to a function the stack 1498 // frame looks like this: 1499 // 1500 // [ESP] -- return address 1501 // [ESP + 4] -- first nonreg argument (leftmost lexically) 1502 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size 1503 // ... 1504 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 1505 1506 // Keep track of the number of integer regs passed so far. This can be either 1507 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX 1508 // are both used). 1509 unsigned NumIntRegs = 0; 1510 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1511 1512 static const unsigned XMMArgRegs[] = { 1513 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1514 }; 1515 1516 static const unsigned GPRArgRegs[][2][2] = { 1517 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }}, 1518 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }}, 1519 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }} 1520 }; 1521 1522 static const TargetRegisterClass* GPRClasses[3] = { 1523 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass 1524 }; 1525 1526 unsigned GPRInd = (isFastCall ? 1 : 0); 1527 for (unsigned i = 0; i < NumArgs; ++i) { 1528 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 1529 unsigned ArgIncrement = 4; 1530 unsigned ObjSize = 0; 1531 unsigned ObjXMMRegs = 0; 1532 unsigned ObjIntRegs = 0; 1533 unsigned Reg = 0; 1534 SDOperand ArgValue; 1535 1536 HowToPassCallArgument(ObjectVT, 1537 true, // Use as much registers as possible 1538 NumIntRegs, NumXMMRegs, 1539 (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS), 1540 ObjSize, ObjIntRegs, ObjXMMRegs, 1541 !isFastCall); 1542 1543 if (ObjSize > 4) 1544 ArgIncrement = ObjSize; 1545 1546 if (ObjIntRegs || ObjXMMRegs) { 1547 switch (ObjectVT) { 1548 default: assert(0 && "Unhandled argument type!"); 1549 case MVT::i8: 1550 case MVT::i16: 1551 case MVT::i32: { 1552 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs]; 1553 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]); 1554 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 1555 break; 1556 } 1557 case MVT::v16i8: 1558 case MVT::v8i16: 1559 case MVT::v4i32: 1560 case MVT::v2i64: 1561 case MVT::v4f32: 1562 case MVT::v2f64: { 1563 assert(!isFastCall && "Unhandled argument type!"); 1564 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); 1565 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 1566 break; 1567 } 1568 } 1569 NumIntRegs += ObjIntRegs; 1570 NumXMMRegs += ObjXMMRegs; 1571 } 1572 if (ObjSize) { 1573 // XMM arguments have to be aligned on 16-byte boundary. 1574 if (ObjSize == 16) 1575 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1576 // Create the SelectionDAG nodes corresponding to a load from this 1577 // parameter. 1578 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1579 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1580 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); 1581 1582 ArgOffset += ArgIncrement; // Move on to the next argument. 1583 } 1584 1585 ArgValues.push_back(ArgValue); 1586 } 1587 1588 ArgValues.push_back(Root); 1589 1590 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1591 // arguments and the arguments after the retaddr has been pushed are aligned. 1592 if ((ArgOffset & 7) == 0) 1593 ArgOffset += 4; 1594 1595 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1596 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 1597 ReturnAddrIndex = 0; // No return address slot generated yet. 1598 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 1599 BytesCallerReserves = 0; 1600 1601 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 1602 1603 // Finally, inform the code generator which regs we return values in. 1604 switch (getValueType(MF.getFunction()->getReturnType())) { 1605 default: assert(0 && "Unknown type!"); 1606 case MVT::isVoid: break; 1607 case MVT::i1: 1608 case MVT::i8: 1609 case MVT::i16: 1610 case MVT::i32: 1611 MF.addLiveOut(X86::EAX); 1612 break; 1613 case MVT::i64: 1614 MF.addLiveOut(X86::EAX); 1615 MF.addLiveOut(X86::EDX); 1616 break; 1617 case MVT::f32: 1618 case MVT::f64: 1619 MF.addLiveOut(X86::ST0); 1620 break; 1621 case MVT::v16i8: 1622 case MVT::v8i16: 1623 case MVT::v4i32: 1624 case MVT::v2i64: 1625 case MVT::v4f32: 1626 case MVT::v2f64: 1627 assert(!isFastCall && "Unknown result type"); 1628 MF.addLiveOut(X86::XMM0); 1629 break; 1630 } 1631 1632 // Return the new list of results. 1633 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 1634 Op.Val->value_end()); 1635 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 1636} 1637 1638SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, 1639 bool isFastCall) { 1640 SDOperand Chain = Op.getOperand(0); 1641 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1642 SDOperand Callee = Op.getOperand(4); 1643 MVT::ValueType RetVT= Op.Val->getValueType(0); 1644 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1645 1646 // Count how many bytes are to be pushed on the stack. 1647 unsigned NumBytes = 0; 1648 1649 // Keep track of the number of integer regs passed so far. This can be either 1650 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX 1651 // are both used). 1652 unsigned NumIntRegs = 0; 1653 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1654 1655 static const unsigned GPRArgRegs[][2][2] = { 1656 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }}, 1657 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }}, 1658 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }} 1659 }; 1660 static const unsigned XMMArgRegs[] = { 1661 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1662 }; 1663 1664 unsigned GPRInd = (isFastCall ? 1 : 0); 1665 for (unsigned i = 0; i != NumOps; ++i) { 1666 SDOperand Arg = Op.getOperand(5+2*i); 1667 1668 switch (Arg.getValueType()) { 1669 default: assert(0 && "Unknown value type!"); 1670 case MVT::i8: 1671 case MVT::i16: 1672 case MVT::i32: { 1673 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS); 1674 if (NumIntRegs < MaxNumIntRegs) { 1675 ++NumIntRegs; 1676 break; 1677 } 1678 } // Fall through 1679 case MVT::f32: 1680 NumBytes += 4; 1681 break; 1682 case MVT::f64: 1683 NumBytes += 8; 1684 break; 1685 case MVT::v16i8: 1686 case MVT::v8i16: 1687 case MVT::v4i32: 1688 case MVT::v2i64: 1689 case MVT::v4f32: 1690 case MVT::v2f64: 1691 assert(!isFastCall && "Unknown value type!"); 1692 if (NumXMMRegs < 4) 1693 NumXMMRegs++; 1694 else { 1695 // XMM arguments have to be aligned on 16-byte boundary. 1696 NumBytes = ((NumBytes + 15) / 16) * 16; 1697 NumBytes += 16; 1698 } 1699 break; 1700 } 1701 } 1702 1703 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1704 // arguments and the arguments after the retaddr has been pushed are aligned. 1705 if ((NumBytes & 7) == 0) 1706 NumBytes += 4; 1707 1708 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1709 1710 // Arguments go on the stack in reverse order, as specified by the ABI. 1711 unsigned ArgOffset = 0; 1712 NumIntRegs = 0; 1713 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1714 std::vector<SDOperand> MemOpChains; 1715 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 1716 for (unsigned i = 0; i != NumOps; ++i) { 1717 SDOperand Arg = Op.getOperand(5+2*i); 1718 1719 switch (Arg.getValueType()) { 1720 default: assert(0 && "Unexpected ValueType for argument!"); 1721 case MVT::i8: 1722 case MVT::i16: 1723 case MVT::i32: { 1724 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS); 1725 if (NumIntRegs < MaxNumIntRegs) { 1726 unsigned RegToUse = 1727 GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs]; 1728 RegsToPass.push_back(std::make_pair(RegToUse, Arg)); 1729 ++NumIntRegs; 1730 break; 1731 } 1732 } // Fall through 1733 case MVT::f32: { 1734 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1735 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1736 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1737 ArgOffset += 4; 1738 break; 1739 } 1740 case MVT::f64: { 1741 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1742 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1743 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1744 ArgOffset += 8; 1745 break; 1746 } 1747 case MVT::v16i8: 1748 case MVT::v8i16: 1749 case MVT::v4i32: 1750 case MVT::v2i64: 1751 case MVT::v4f32: 1752 case MVT::v2f64: 1753 assert(!isFastCall && "Unexpected ValueType for argument!"); 1754 if (NumXMMRegs < 4) { 1755 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 1756 NumXMMRegs++; 1757 } else { 1758 // XMM arguments have to be aligned on 16-byte boundary. 1759 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1760 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1761 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1762 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1763 ArgOffset += 16; 1764 } 1765 break; 1766 } 1767 } 1768 1769 if (!MemOpChains.empty()) 1770 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1771 &MemOpChains[0], MemOpChains.size()); 1772 1773 // Build a sequence of copy-to-reg nodes chained together with token chain 1774 // and flag operands which copy the outgoing args into registers. 1775 SDOperand InFlag; 1776 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1777 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1778 InFlag); 1779 InFlag = Chain.getValue(1); 1780 } 1781 1782 // If the callee is a GlobalAddress node (quite common, every direct call is) 1783 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1784 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1785 // We should use extra load for direct calls to dllimported functions in 1786 // non-JIT mode. 1787 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1788 getTargetMachine(), true)) 1789 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1790 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1791 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1792 1793 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1794 // GOT pointer. 1795 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1796 Subtarget->isPICStyleGOT()) { 1797 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1798 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1799 InFlag); 1800 InFlag = Chain.getValue(1); 1801 } 1802 1803 // Returns a chain & a flag for retval copy to use. 1804 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1805 std::vector<SDOperand> Ops; 1806 Ops.push_back(Chain); 1807 Ops.push_back(Callee); 1808 1809 // Add argument registers to the end of the list so that they are known live 1810 // into the call. 1811 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1812 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1813 RegsToPass[i].second.getValueType())); 1814 1815 // Add an implicit use GOT pointer in EBX. 1816 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1817 Subtarget->isPICStyleGOT()) 1818 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1819 1820 if (InFlag.Val) 1821 Ops.push_back(InFlag); 1822 1823 // FIXME: Do not generate X86ISD::TAILCALL for now. 1824 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1825 NodeTys, &Ops[0], Ops.size()); 1826 InFlag = Chain.getValue(1); 1827 1828 if (RetVT != MVT::Other) 1829 // Returns a flag for retval copy to use. 1830 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1831 else 1832 NodeTys = DAG.getVTList(MVT::Other); 1833 Ops.clear(); 1834 Ops.push_back(Chain); 1835 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1836 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1837 Ops.push_back(InFlag); 1838 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1839 if (RetVT != MVT::Other) 1840 InFlag = Chain.getValue(1); 1841 1842 std::vector<SDOperand> ResultVals; 1843 switch (RetVT) { 1844 default: assert(0 && "Unknown value type to return!"); 1845 case MVT::Other: break; 1846 case MVT::i8: 1847 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 1848 ResultVals.push_back(Chain.getValue(0)); 1849 NodeTys = DAG.getVTList(MVT::i8, MVT::Other); 1850 break; 1851 case MVT::i16: 1852 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 1853 ResultVals.push_back(Chain.getValue(0)); 1854 NodeTys = DAG.getVTList(MVT::i16, MVT::Other); 1855 break; 1856 case MVT::i32: 1857 if (Op.Val->getValueType(1) == MVT::i32) { 1858 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1859 ResultVals.push_back(Chain.getValue(0)); 1860 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32, 1861 Chain.getValue(2)).getValue(1); 1862 ResultVals.push_back(Chain.getValue(0)); 1863 NodeTys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 1864 } else { 1865 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1866 ResultVals.push_back(Chain.getValue(0)); 1867 NodeTys = DAG.getVTList(MVT::i32, MVT::Other); 1868 } 1869 break; 1870 case MVT::v16i8: 1871 case MVT::v8i16: 1872 case MVT::v4i32: 1873 case MVT::v2i64: 1874 case MVT::v4f32: 1875 case MVT::v2f64: 1876 if (isFastCall) { 1877 assert(0 && "Unknown value type to return!"); 1878 } else { 1879 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 1880 ResultVals.push_back(Chain.getValue(0)); 1881 NodeTys = DAG.getVTList(RetVT, MVT::Other); 1882 } 1883 break; 1884 case MVT::f32: 1885 case MVT::f64: { 1886 std::vector<MVT::ValueType> Tys; 1887 Tys.push_back(MVT::f64); 1888 Tys.push_back(MVT::Other); 1889 Tys.push_back(MVT::Flag); 1890 std::vector<SDOperand> Ops; 1891 Ops.push_back(Chain); 1892 Ops.push_back(InFlag); 1893 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 1894 &Ops[0], Ops.size()); 1895 Chain = RetVal.getValue(1); 1896 InFlag = RetVal.getValue(2); 1897 if (X86ScalarSSE) { 1898 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 1899 // shouldn't be necessary except that RFP cannot be live across 1900 // multiple blocks. When stackifier is fixed, they can be uncoupled. 1901 MachineFunction &MF = DAG.getMachineFunction(); 1902 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 1903 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1904 Tys.clear(); 1905 Tys.push_back(MVT::Other); 1906 Ops.clear(); 1907 Ops.push_back(Chain); 1908 Ops.push_back(RetVal); 1909 Ops.push_back(StackSlot); 1910 Ops.push_back(DAG.getValueType(RetVT)); 1911 Ops.push_back(InFlag); 1912 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 1913 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0); 1914 Chain = RetVal.getValue(1); 1915 } 1916 1917 if (RetVT == MVT::f32 && !X86ScalarSSE) 1918 // FIXME: we would really like to remember that this FP_ROUND 1919 // operation is okay to eliminate if we allow excess FP precision. 1920 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 1921 ResultVals.push_back(RetVal); 1922 NodeTys = DAG.getVTList(RetVT, MVT::Other); 1923 1924 break; 1925 } 1926 } 1927 1928 1929 // If the function returns void, just return the chain. 1930 if (ResultVals.empty()) 1931 return Chain; 1932 1933 // Otherwise, merge everything together with a MERGE_VALUES node. 1934 ResultVals.push_back(Chain); 1935 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1936 &ResultVals[0], ResultVals.size()); 1937 return Res.getValue(Op.ResNo); 1938} 1939 1940SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1941 if (ReturnAddrIndex == 0) { 1942 // Set up a frame object for the return address. 1943 MachineFunction &MF = DAG.getMachineFunction(); 1944 if (Subtarget->is64Bit()) 1945 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); 1946 else 1947 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1948 } 1949 1950 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1951} 1952 1953 1954 1955/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 1956/// specific condition code. It returns a false if it cannot do a direct 1957/// translation. X86CC is the translated CondCode. LHS/RHS are modified as 1958/// needed. 1959static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1960 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, 1961 SelectionDAG &DAG) { 1962 X86CC = X86::COND_INVALID; 1963 if (!isFP) { 1964 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1965 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1966 // X > -1 -> X == 0, jump !sign. 1967 RHS = DAG.getConstant(0, RHS.getValueType()); 1968 X86CC = X86::COND_NS; 1969 return true; 1970 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1971 // X < 0 -> X == 0, jump on sign. 1972 X86CC = X86::COND_S; 1973 return true; 1974 } 1975 } 1976 1977 switch (SetCCOpcode) { 1978 default: break; 1979 case ISD::SETEQ: X86CC = X86::COND_E; break; 1980 case ISD::SETGT: X86CC = X86::COND_G; break; 1981 case ISD::SETGE: X86CC = X86::COND_GE; break; 1982 case ISD::SETLT: X86CC = X86::COND_L; break; 1983 case ISD::SETLE: X86CC = X86::COND_LE; break; 1984 case ISD::SETNE: X86CC = X86::COND_NE; break; 1985 case ISD::SETULT: X86CC = X86::COND_B; break; 1986 case ISD::SETUGT: X86CC = X86::COND_A; break; 1987 case ISD::SETULE: X86CC = X86::COND_BE; break; 1988 case ISD::SETUGE: X86CC = X86::COND_AE; break; 1989 } 1990 } else { 1991 // On a floating point condition, the flags are set as follows: 1992 // ZF PF CF op 1993 // 0 | 0 | 0 | X > Y 1994 // 0 | 0 | 1 | X < Y 1995 // 1 | 0 | 0 | X == Y 1996 // 1 | 1 | 1 | unordered 1997 bool Flip = false; 1998 switch (SetCCOpcode) { 1999 default: break; 2000 case ISD::SETUEQ: 2001 case ISD::SETEQ: X86CC = X86::COND_E; break; 2002 case ISD::SETOLT: Flip = true; // Fallthrough 2003 case ISD::SETOGT: 2004 case ISD::SETGT: X86CC = X86::COND_A; break; 2005 case ISD::SETOLE: Flip = true; // Fallthrough 2006 case ISD::SETOGE: 2007 case ISD::SETGE: X86CC = X86::COND_AE; break; 2008 case ISD::SETUGT: Flip = true; // Fallthrough 2009 case ISD::SETULT: 2010 case ISD::SETLT: X86CC = X86::COND_B; break; 2011 case ISD::SETUGE: Flip = true; // Fallthrough 2012 case ISD::SETULE: 2013 case ISD::SETLE: X86CC = X86::COND_BE; break; 2014 case ISD::SETONE: 2015 case ISD::SETNE: X86CC = X86::COND_NE; break; 2016 case ISD::SETUO: X86CC = X86::COND_P; break; 2017 case ISD::SETO: X86CC = X86::COND_NP; break; 2018 } 2019 if (Flip) 2020 std::swap(LHS, RHS); 2021 } 2022 2023 return X86CC != X86::COND_INVALID; 2024} 2025 2026/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2027/// code. Current x86 isa includes the following FP cmov instructions: 2028/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2029static bool hasFPCMov(unsigned X86CC) { 2030 switch (X86CC) { 2031 default: 2032 return false; 2033 case X86::COND_B: 2034 case X86::COND_BE: 2035 case X86::COND_E: 2036 case X86::COND_P: 2037 case X86::COND_A: 2038 case X86::COND_AE: 2039 case X86::COND_NE: 2040 case X86::COND_NP: 2041 return true; 2042 } 2043} 2044 2045/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2046/// true if Op is undef or if its value falls within the specified range (L, H]. 2047static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { 2048 if (Op.getOpcode() == ISD::UNDEF) 2049 return true; 2050 2051 unsigned Val = cast<ConstantSDNode>(Op)->getValue(); 2052 return (Val >= Low && Val < Hi); 2053} 2054 2055/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2056/// true if Op is undef or if its value equal to the specified value. 2057static bool isUndefOrEqual(SDOperand Op, unsigned Val) { 2058 if (Op.getOpcode() == ISD::UNDEF) 2059 return true; 2060 return cast<ConstantSDNode>(Op)->getValue() == Val; 2061} 2062 2063/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2064/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2065bool X86::isPSHUFDMask(SDNode *N) { 2066 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2067 2068 if (N->getNumOperands() != 4) 2069 return false; 2070 2071 // Check if the value doesn't reference the second vector. 2072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2073 SDOperand Arg = N->getOperand(i); 2074 if (Arg.getOpcode() == ISD::UNDEF) continue; 2075 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2076 if (cast<ConstantSDNode>(Arg)->getValue() >= 4) 2077 return false; 2078 } 2079 2080 return true; 2081} 2082 2083/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2084/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2085bool X86::isPSHUFHWMask(SDNode *N) { 2086 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2087 2088 if (N->getNumOperands() != 8) 2089 return false; 2090 2091 // Lower quadword copied in order. 2092 for (unsigned i = 0; i != 4; ++i) { 2093 SDOperand Arg = N->getOperand(i); 2094 if (Arg.getOpcode() == ISD::UNDEF) continue; 2095 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2096 if (cast<ConstantSDNode>(Arg)->getValue() != i) 2097 return false; 2098 } 2099 2100 // Upper quadword shuffled. 2101 for (unsigned i = 4; i != 8; ++i) { 2102 SDOperand Arg = N->getOperand(i); 2103 if (Arg.getOpcode() == ISD::UNDEF) continue; 2104 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2105 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2106 if (Val < 4 || Val > 7) 2107 return false; 2108 } 2109 2110 return true; 2111} 2112 2113/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2114/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2115bool X86::isPSHUFLWMask(SDNode *N) { 2116 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2117 2118 if (N->getNumOperands() != 8) 2119 return false; 2120 2121 // Upper quadword copied in order. 2122 for (unsigned i = 4; i != 8; ++i) 2123 if (!isUndefOrEqual(N->getOperand(i), i)) 2124 return false; 2125 2126 // Lower quadword shuffled. 2127 for (unsigned i = 0; i != 4; ++i) 2128 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2129 return false; 2130 2131 return true; 2132} 2133 2134/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2135/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2136static bool isSHUFPMask(std::vector<SDOperand> &N) { 2137 unsigned NumElems = N.size(); 2138 if (NumElems != 2 && NumElems != 4) return false; 2139 2140 unsigned Half = NumElems / 2; 2141 for (unsigned i = 0; i < Half; ++i) 2142 if (!isUndefOrInRange(N[i], 0, NumElems)) 2143 return false; 2144 for (unsigned i = Half; i < NumElems; ++i) 2145 if (!isUndefOrInRange(N[i], NumElems, NumElems*2)) 2146 return false; 2147 2148 return true; 2149} 2150 2151bool X86::isSHUFPMask(SDNode *N) { 2152 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2153 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2154 return ::isSHUFPMask(Ops); 2155} 2156 2157/// isCommutedSHUFP - Returns true if the shuffle mask is except 2158/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2159/// half elements to come from vector 1 (which would equal the dest.) and 2160/// the upper half to come from vector 2. 2161static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) { 2162 unsigned NumElems = Ops.size(); 2163 if (NumElems != 2 && NumElems != 4) return false; 2164 2165 unsigned Half = NumElems / 2; 2166 for (unsigned i = 0; i < Half; ++i) 2167 if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2)) 2168 return false; 2169 for (unsigned i = Half; i < NumElems; ++i) 2170 if (!isUndefOrInRange(Ops[i], 0, NumElems)) 2171 return false; 2172 return true; 2173} 2174 2175static bool isCommutedSHUFP(SDNode *N) { 2176 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2177 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2178 return isCommutedSHUFP(Ops); 2179} 2180 2181/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2182/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2183bool X86::isMOVHLPSMask(SDNode *N) { 2184 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2185 2186 if (N->getNumOperands() != 4) 2187 return false; 2188 2189 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2190 return isUndefOrEqual(N->getOperand(0), 6) && 2191 isUndefOrEqual(N->getOperand(1), 7) && 2192 isUndefOrEqual(N->getOperand(2), 2) && 2193 isUndefOrEqual(N->getOperand(3), 3); 2194} 2195 2196/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2197/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2198/// <2, 3, 2, 3> 2199bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2200 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2201 2202 if (N->getNumOperands() != 4) 2203 return false; 2204 2205 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2206 return isUndefOrEqual(N->getOperand(0), 2) && 2207 isUndefOrEqual(N->getOperand(1), 3) && 2208 isUndefOrEqual(N->getOperand(2), 2) && 2209 isUndefOrEqual(N->getOperand(3), 3); 2210} 2211 2212/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2213/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2214bool X86::isMOVLPMask(SDNode *N) { 2215 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2216 2217 unsigned NumElems = N->getNumOperands(); 2218 if (NumElems != 2 && NumElems != 4) 2219 return false; 2220 2221 for (unsigned i = 0; i < NumElems/2; ++i) 2222 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2223 return false; 2224 2225 for (unsigned i = NumElems/2; i < NumElems; ++i) 2226 if (!isUndefOrEqual(N->getOperand(i), i)) 2227 return false; 2228 2229 return true; 2230} 2231 2232/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2233/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2234/// and MOVLHPS. 2235bool X86::isMOVHPMask(SDNode *N) { 2236 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2237 2238 unsigned NumElems = N->getNumOperands(); 2239 if (NumElems != 2 && NumElems != 4) 2240 return false; 2241 2242 for (unsigned i = 0; i < NumElems/2; ++i) 2243 if (!isUndefOrEqual(N->getOperand(i), i)) 2244 return false; 2245 2246 for (unsigned i = 0; i < NumElems/2; ++i) { 2247 SDOperand Arg = N->getOperand(i + NumElems/2); 2248 if (!isUndefOrEqual(Arg, i + NumElems)) 2249 return false; 2250 } 2251 2252 return true; 2253} 2254 2255/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2256/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2257bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) { 2258 unsigned NumElems = N.size(); 2259 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2260 return false; 2261 2262 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2263 SDOperand BitI = N[i]; 2264 SDOperand BitI1 = N[i+1]; 2265 if (!isUndefOrEqual(BitI, j)) 2266 return false; 2267 if (V2IsSplat) { 2268 if (isUndefOrEqual(BitI1, NumElems)) 2269 return false; 2270 } else { 2271 if (!isUndefOrEqual(BitI1, j + NumElems)) 2272 return false; 2273 } 2274 } 2275 2276 return true; 2277} 2278 2279bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2280 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2281 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2282 return ::isUNPCKLMask(Ops, V2IsSplat); 2283} 2284 2285/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2286/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2287bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) { 2288 unsigned NumElems = N.size(); 2289 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2290 return false; 2291 2292 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2293 SDOperand BitI = N[i]; 2294 SDOperand BitI1 = N[i+1]; 2295 if (!isUndefOrEqual(BitI, j + NumElems/2)) 2296 return false; 2297 if (V2IsSplat) { 2298 if (isUndefOrEqual(BitI1, NumElems)) 2299 return false; 2300 } else { 2301 if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems)) 2302 return false; 2303 } 2304 } 2305 2306 return true; 2307} 2308 2309bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2310 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2311 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2312 return ::isUNPCKHMask(Ops, V2IsSplat); 2313} 2314 2315/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2316/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2317/// <0, 0, 1, 1> 2318bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2319 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2320 2321 unsigned NumElems = N->getNumOperands(); 2322 if (NumElems != 4 && NumElems != 8 && NumElems != 16) 2323 return false; 2324 2325 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2326 SDOperand BitI = N->getOperand(i); 2327 SDOperand BitI1 = N->getOperand(i+1); 2328 2329 if (!isUndefOrEqual(BitI, j)) 2330 return false; 2331 if (!isUndefOrEqual(BitI1, j)) 2332 return false; 2333 } 2334 2335 return true; 2336} 2337 2338/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2339/// specifies a shuffle of elements that is suitable for input to MOVSS, 2340/// MOVSD, and MOVD, i.e. setting the lowest element. 2341static bool isMOVLMask(std::vector<SDOperand> &N) { 2342 unsigned NumElems = N.size(); 2343 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2344 return false; 2345 2346 if (!isUndefOrEqual(N[0], NumElems)) 2347 return false; 2348 2349 for (unsigned i = 1; i < NumElems; ++i) { 2350 SDOperand Arg = N[i]; 2351 if (!isUndefOrEqual(Arg, i)) 2352 return false; 2353 } 2354 2355 return true; 2356} 2357 2358bool X86::isMOVLMask(SDNode *N) { 2359 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2360 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2361 return ::isMOVLMask(Ops); 2362} 2363 2364/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2365/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2366/// element of vector 2 and the other elements to come from vector 1 in order. 2367static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false, 2368 bool V2IsUndef = false) { 2369 unsigned NumElems = Ops.size(); 2370 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2371 return false; 2372 2373 if (!isUndefOrEqual(Ops[0], 0)) 2374 return false; 2375 2376 for (unsigned i = 1; i < NumElems; ++i) { 2377 SDOperand Arg = Ops[i]; 2378 if (!(isUndefOrEqual(Arg, i+NumElems) || 2379 (V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) || 2380 (V2IsSplat && isUndefOrEqual(Arg, NumElems)))) 2381 return false; 2382 } 2383 2384 return true; 2385} 2386 2387static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2388 bool V2IsUndef = false) { 2389 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2390 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2391 return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef); 2392} 2393 2394/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2395/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2396bool X86::isMOVSHDUPMask(SDNode *N) { 2397 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2398 2399 if (N->getNumOperands() != 4) 2400 return false; 2401 2402 // Expect 1, 1, 3, 3 2403 for (unsigned i = 0; i < 2; ++i) { 2404 SDOperand Arg = N->getOperand(i); 2405 if (Arg.getOpcode() == ISD::UNDEF) continue; 2406 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2407 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2408 if (Val != 1) return false; 2409 } 2410 2411 bool HasHi = false; 2412 for (unsigned i = 2; i < 4; ++i) { 2413 SDOperand Arg = N->getOperand(i); 2414 if (Arg.getOpcode() == ISD::UNDEF) continue; 2415 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2416 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2417 if (Val != 3) return false; 2418 HasHi = true; 2419 } 2420 2421 // Don't use movshdup if it can be done with a shufps. 2422 return HasHi; 2423} 2424 2425/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2426/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2427bool X86::isMOVSLDUPMask(SDNode *N) { 2428 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2429 2430 if (N->getNumOperands() != 4) 2431 return false; 2432 2433 // Expect 0, 0, 2, 2 2434 for (unsigned i = 0; i < 2; ++i) { 2435 SDOperand Arg = N->getOperand(i); 2436 if (Arg.getOpcode() == ISD::UNDEF) continue; 2437 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2438 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2439 if (Val != 0) return false; 2440 } 2441 2442 bool HasHi = false; 2443 for (unsigned i = 2; i < 4; ++i) { 2444 SDOperand Arg = N->getOperand(i); 2445 if (Arg.getOpcode() == ISD::UNDEF) continue; 2446 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2447 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2448 if (Val != 2) return false; 2449 HasHi = true; 2450 } 2451 2452 // Don't use movshdup if it can be done with a shufps. 2453 return HasHi; 2454} 2455 2456/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2457/// a splat of a single element. 2458static bool isSplatMask(SDNode *N) { 2459 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2460 2461 // This is a splat operation if each element of the permute is the same, and 2462 // if the value doesn't reference the second vector. 2463 unsigned NumElems = N->getNumOperands(); 2464 SDOperand ElementBase; 2465 unsigned i = 0; 2466 for (; i != NumElems; ++i) { 2467 SDOperand Elt = N->getOperand(i); 2468 if (isa<ConstantSDNode>(Elt)) { 2469 ElementBase = Elt; 2470 break; 2471 } 2472 } 2473 2474 if (!ElementBase.Val) 2475 return false; 2476 2477 for (; i != NumElems; ++i) { 2478 SDOperand Arg = N->getOperand(i); 2479 if (Arg.getOpcode() == ISD::UNDEF) continue; 2480 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2481 if (Arg != ElementBase) return false; 2482 } 2483 2484 // Make sure it is a splat of the first vector operand. 2485 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; 2486} 2487 2488/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2489/// a splat of a single element and it's a 2 or 4 element mask. 2490bool X86::isSplatMask(SDNode *N) { 2491 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2492 2493 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2494 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2495 return false; 2496 return ::isSplatMask(N); 2497} 2498 2499/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2500/// specifies a splat of zero element. 2501bool X86::isSplatLoMask(SDNode *N) { 2502 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2503 2504 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2505 if (!isUndefOrEqual(N->getOperand(i), 0)) 2506 return false; 2507 return true; 2508} 2509 2510/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2511/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2512/// instructions. 2513unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2514 unsigned NumOperands = N->getNumOperands(); 2515 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2516 unsigned Mask = 0; 2517 for (unsigned i = 0; i < NumOperands; ++i) { 2518 unsigned Val = 0; 2519 SDOperand Arg = N->getOperand(NumOperands-i-1); 2520 if (Arg.getOpcode() != ISD::UNDEF) 2521 Val = cast<ConstantSDNode>(Arg)->getValue(); 2522 if (Val >= NumOperands) Val -= NumOperands; 2523 Mask |= Val; 2524 if (i != NumOperands - 1) 2525 Mask <<= Shift; 2526 } 2527 2528 return Mask; 2529} 2530 2531/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2532/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2533/// instructions. 2534unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2535 unsigned Mask = 0; 2536 // 8 nodes, but we only care about the last 4. 2537 for (unsigned i = 7; i >= 4; --i) { 2538 unsigned Val = 0; 2539 SDOperand Arg = N->getOperand(i); 2540 if (Arg.getOpcode() != ISD::UNDEF) 2541 Val = cast<ConstantSDNode>(Arg)->getValue(); 2542 Mask |= (Val - 4); 2543 if (i != 4) 2544 Mask <<= 2; 2545 } 2546 2547 return Mask; 2548} 2549 2550/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2551/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2552/// instructions. 2553unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2554 unsigned Mask = 0; 2555 // 8 nodes, but we only care about the first 4. 2556 for (int i = 3; i >= 0; --i) { 2557 unsigned Val = 0; 2558 SDOperand Arg = N->getOperand(i); 2559 if (Arg.getOpcode() != ISD::UNDEF) 2560 Val = cast<ConstantSDNode>(Arg)->getValue(); 2561 Mask |= Val; 2562 if (i != 0) 2563 Mask <<= 2; 2564 } 2565 2566 return Mask; 2567} 2568 2569/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2570/// specifies a 8 element shuffle that can be broken into a pair of 2571/// PSHUFHW and PSHUFLW. 2572static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2573 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2574 2575 if (N->getNumOperands() != 8) 2576 return false; 2577 2578 // Lower quadword shuffled. 2579 for (unsigned i = 0; i != 4; ++i) { 2580 SDOperand Arg = N->getOperand(i); 2581 if (Arg.getOpcode() == ISD::UNDEF) continue; 2582 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2583 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2584 if (Val > 4) 2585 return false; 2586 } 2587 2588 // Upper quadword shuffled. 2589 for (unsigned i = 4; i != 8; ++i) { 2590 SDOperand Arg = N->getOperand(i); 2591 if (Arg.getOpcode() == ISD::UNDEF) continue; 2592 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2593 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2594 if (Val < 4 || Val > 7) 2595 return false; 2596 } 2597 2598 return true; 2599} 2600 2601/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as 2602/// values in ther permute mask. 2603static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, 2604 SDOperand &V2, SDOperand &Mask, 2605 SelectionDAG &DAG) { 2606 MVT::ValueType VT = Op.getValueType(); 2607 MVT::ValueType MaskVT = Mask.getValueType(); 2608 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT); 2609 unsigned NumElems = Mask.getNumOperands(); 2610 std::vector<SDOperand> MaskVec; 2611 2612 for (unsigned i = 0; i != NumElems; ++i) { 2613 SDOperand Arg = Mask.getOperand(i); 2614 if (Arg.getOpcode() == ISD::UNDEF) { 2615 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2616 continue; 2617 } 2618 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2619 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2620 if (Val < NumElems) 2621 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2622 else 2623 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2624 } 2625 2626 std::swap(V1, V2); 2627 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2628 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2629} 2630 2631/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2632/// match movhlps. The lower half elements should come from upper half of 2633/// V1 (and in order), and the upper half elements should come from the upper 2634/// half of V2 (and in order). 2635static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2636 unsigned NumElems = Mask->getNumOperands(); 2637 if (NumElems != 4) 2638 return false; 2639 for (unsigned i = 0, e = 2; i != e; ++i) 2640 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2641 return false; 2642 for (unsigned i = 2; i != 4; ++i) 2643 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2644 return false; 2645 return true; 2646} 2647 2648/// isScalarLoadToVector - Returns true if the node is a scalar load that 2649/// is promoted to a vector. 2650static inline bool isScalarLoadToVector(SDNode *N) { 2651 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { 2652 N = N->getOperand(0).Val; 2653 return ISD::isNON_EXTLoad(N); 2654 } 2655 return false; 2656} 2657 2658/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2659/// match movlp{s|d}. The lower half elements should come from lower half of 2660/// V1 (and in order), and the upper half elements should come from the upper 2661/// half of V2 (and in order). And since V1 will become the source of the 2662/// MOVLP, it must be either a vector load or a scalar load to vector. 2663static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2664 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2665 return false; 2666 // Is V2 is a vector load, don't do this transformation. We will try to use 2667 // load folding shufps op. 2668 if (ISD::isNON_EXTLoad(V2)) 2669 return false; 2670 2671 unsigned NumElems = Mask->getNumOperands(); 2672 if (NumElems != 2 && NumElems != 4) 2673 return false; 2674 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2675 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2676 return false; 2677 for (unsigned i = NumElems/2; i != NumElems; ++i) 2678 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2679 return false; 2680 return true; 2681} 2682 2683/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2684/// all the same. 2685static bool isSplatVector(SDNode *N) { 2686 if (N->getOpcode() != ISD::BUILD_VECTOR) 2687 return false; 2688 2689 SDOperand SplatValue = N->getOperand(0); 2690 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2691 if (N->getOperand(i) != SplatValue) 2692 return false; 2693 return true; 2694} 2695 2696/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2697/// to an undef. 2698static bool isUndefShuffle(SDNode *N) { 2699 if (N->getOpcode() != ISD::BUILD_VECTOR) 2700 return false; 2701 2702 SDOperand V1 = N->getOperand(0); 2703 SDOperand V2 = N->getOperand(1); 2704 SDOperand Mask = N->getOperand(2); 2705 unsigned NumElems = Mask.getNumOperands(); 2706 for (unsigned i = 0; i != NumElems; ++i) { 2707 SDOperand Arg = Mask.getOperand(i); 2708 if (Arg.getOpcode() != ISD::UNDEF) { 2709 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2710 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2711 return false; 2712 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2713 return false; 2714 } 2715 } 2716 return true; 2717} 2718 2719/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2720/// that point to V2 points to its first element. 2721static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { 2722 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2723 2724 bool Changed = false; 2725 std::vector<SDOperand> MaskVec; 2726 unsigned NumElems = Mask.getNumOperands(); 2727 for (unsigned i = 0; i != NumElems; ++i) { 2728 SDOperand Arg = Mask.getOperand(i); 2729 if (Arg.getOpcode() != ISD::UNDEF) { 2730 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2731 if (Val > NumElems) { 2732 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2733 Changed = true; 2734 } 2735 } 2736 MaskVec.push_back(Arg); 2737 } 2738 2739 if (Changed) 2740 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2741 &MaskVec[0], MaskVec.size()); 2742 return Mask; 2743} 2744 2745/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2746/// operation of specified width. 2747static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2748 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2749 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2750 2751 std::vector<SDOperand> MaskVec; 2752 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2753 for (unsigned i = 1; i != NumElems; ++i) 2754 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2755 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2756} 2757 2758/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2759/// of specified width. 2760static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2761 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2762 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2763 std::vector<SDOperand> MaskVec; 2764 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2765 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2766 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2767 } 2768 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2769} 2770 2771/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2772/// of specified width. 2773static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2774 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2775 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2776 unsigned Half = NumElems/2; 2777 std::vector<SDOperand> MaskVec; 2778 for (unsigned i = 0; i != Half; ++i) { 2779 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2780 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2781 } 2782 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2783} 2784 2785/// getZeroVector - Returns a vector of specified type with all zero elements. 2786/// 2787static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) { 2788 assert(MVT::isVector(VT) && "Expected a vector type"); 2789 unsigned NumElems = getVectorNumElements(VT); 2790 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 2791 bool isFP = MVT::isFloatingPoint(EVT); 2792 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT); 2793 std::vector<SDOperand> ZeroVec(NumElems, Zero); 2794 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size()); 2795} 2796 2797/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32. 2798/// 2799static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) { 2800 SDOperand V1 = Op.getOperand(0); 2801 SDOperand Mask = Op.getOperand(2); 2802 MVT::ValueType VT = Op.getValueType(); 2803 unsigned NumElems = Mask.getNumOperands(); 2804 Mask = getUnpacklMask(NumElems, DAG); 2805 while (NumElems != 4) { 2806 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 2807 NumElems >>= 1; 2808 } 2809 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1); 2810 2811 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 2812 Mask = getZeroVector(MaskVT, DAG); 2813 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1, 2814 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask); 2815 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 2816} 2817 2818/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2819/// constant +0.0. 2820static inline bool isZeroNode(SDOperand Elt) { 2821 return ((isa<ConstantSDNode>(Elt) && 2822 cast<ConstantSDNode>(Elt)->getValue() == 0) || 2823 (isa<ConstantFPSDNode>(Elt) && 2824 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0))); 2825} 2826 2827/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 2828/// vector and zero or undef vector. 2829static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT, 2830 unsigned NumElems, unsigned Idx, 2831 bool isZero, SelectionDAG &DAG) { 2832 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT); 2833 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2834 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 2835 SDOperand Zero = DAG.getConstant(0, EVT); 2836 std::vector<SDOperand> MaskVec(NumElems, Zero); 2837 MaskVec[Idx] = DAG.getConstant(NumElems, EVT); 2838 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2839 &MaskVec[0], MaskVec.size()); 2840 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2841} 2842 2843/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 2844/// 2845static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, 2846 unsigned NumNonZero, unsigned NumZero, 2847 SelectionDAG &DAG, TargetLowering &TLI) { 2848 if (NumNonZero > 8) 2849 return SDOperand(); 2850 2851 SDOperand V(0, 0); 2852 bool First = true; 2853 for (unsigned i = 0; i < 16; ++i) { 2854 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 2855 if (ThisIsNonZero && First) { 2856 if (NumZero) 2857 V = getZeroVector(MVT::v8i16, DAG); 2858 else 2859 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2860 First = false; 2861 } 2862 2863 if ((i & 1) != 0) { 2864 SDOperand ThisElt(0, 0), LastElt(0, 0); 2865 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 2866 if (LastIsNonZero) { 2867 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 2868 } 2869 if (ThisIsNonZero) { 2870 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 2871 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 2872 ThisElt, DAG.getConstant(8, MVT::i8)); 2873 if (LastIsNonZero) 2874 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 2875 } else 2876 ThisElt = LastElt; 2877 2878 if (ThisElt.Val) 2879 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 2880 DAG.getConstant(i/2, TLI.getPointerTy())); 2881 } 2882 } 2883 2884 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 2885} 2886 2887/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16. 2888/// 2889static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, 2890 unsigned NumNonZero, unsigned NumZero, 2891 SelectionDAG &DAG, TargetLowering &TLI) { 2892 if (NumNonZero > 4) 2893 return SDOperand(); 2894 2895 SDOperand V(0, 0); 2896 bool First = true; 2897 for (unsigned i = 0; i < 8; ++i) { 2898 bool isNonZero = (NonZeros & (1 << i)) != 0; 2899 if (isNonZero) { 2900 if (First) { 2901 if (NumZero) 2902 V = getZeroVector(MVT::v8i16, DAG); 2903 else 2904 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2905 First = false; 2906 } 2907 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 2908 DAG.getConstant(i, TLI.getPointerTy())); 2909 } 2910 } 2911 2912 return V; 2913} 2914 2915SDOperand 2916X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2917 // All zero's are handled with pxor. 2918 if (ISD::isBuildVectorAllZeros(Op.Val)) 2919 return Op; 2920 2921 // All one's are handled with pcmpeqd. 2922 if (ISD::isBuildVectorAllOnes(Op.Val)) 2923 return Op; 2924 2925 MVT::ValueType VT = Op.getValueType(); 2926 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 2927 unsigned EVTBits = MVT::getSizeInBits(EVT); 2928 2929 unsigned NumElems = Op.getNumOperands(); 2930 unsigned NumZero = 0; 2931 unsigned NumNonZero = 0; 2932 unsigned NonZeros = 0; 2933 std::set<SDOperand> Values; 2934 for (unsigned i = 0; i < NumElems; ++i) { 2935 SDOperand Elt = Op.getOperand(i); 2936 if (Elt.getOpcode() != ISD::UNDEF) { 2937 Values.insert(Elt); 2938 if (isZeroNode(Elt)) 2939 NumZero++; 2940 else { 2941 NonZeros |= (1 << i); 2942 NumNonZero++; 2943 } 2944 } 2945 } 2946 2947 if (NumNonZero == 0) 2948 // Must be a mix of zero and undef. Return a zero vector. 2949 return getZeroVector(VT, DAG); 2950 2951 // Splat is obviously ok. Let legalizer expand it to a shuffle. 2952 if (Values.size() == 1) 2953 return SDOperand(); 2954 2955 // Special case for single non-zero element. 2956 if (NumNonZero == 1) { 2957 unsigned Idx = CountTrailingZeros_32(NonZeros); 2958 SDOperand Item = Op.getOperand(Idx); 2959 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 2960 if (Idx == 0) 2961 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 2962 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx, 2963 NumZero > 0, DAG); 2964 2965 if (EVTBits == 32) { 2966 // Turn it into a shuffle of zero and zero-extended scalar to vector. 2967 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0, 2968 DAG); 2969 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2970 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 2971 std::vector<SDOperand> MaskVec; 2972 for (unsigned i = 0; i < NumElems; i++) 2973 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 2974 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2975 &MaskVec[0], MaskVec.size()); 2976 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 2977 DAG.getNode(ISD::UNDEF, VT), Mask); 2978 } 2979 } 2980 2981 // Let legalizer expand 2-wide build_vector's. 2982 if (EVTBits == 64) 2983 return SDOperand(); 2984 2985 // If element VT is < 32 bits, convert it to inserts into a zero vector. 2986 if (EVTBits == 8) { 2987 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 2988 *this); 2989 if (V.Val) return V; 2990 } 2991 2992 if (EVTBits == 16) { 2993 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 2994 *this); 2995 if (V.Val) return V; 2996 } 2997 2998 // If element VT is == 32 bits, turn it into a number of shuffles. 2999 std::vector<SDOperand> V(NumElems); 3000 if (NumElems == 4 && NumZero > 0) { 3001 for (unsigned i = 0; i < 4; ++i) { 3002 bool isZero = !(NonZeros & (1 << i)); 3003 if (isZero) 3004 V[i] = getZeroVector(VT, DAG); 3005 else 3006 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3007 } 3008 3009 for (unsigned i = 0; i < 2; ++i) { 3010 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3011 default: break; 3012 case 0: 3013 V[i] = V[i*2]; // Must be a zero vector. 3014 break; 3015 case 1: 3016 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3017 getMOVLMask(NumElems, DAG)); 3018 break; 3019 case 2: 3020 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3021 getMOVLMask(NumElems, DAG)); 3022 break; 3023 case 3: 3024 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3025 getUnpacklMask(NumElems, DAG)); 3026 break; 3027 } 3028 } 3029 3030 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) 3031 // clears the upper bits. 3032 // FIXME: we can do the same for v4f32 case when we know both parts of 3033 // the lower half come from scalar_to_vector (loadf32). We should do 3034 // that in post legalizer dag combiner with target specific hooks. 3035 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) 3036 return V[0]; 3037 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3038 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 3039 std::vector<SDOperand> MaskVec; 3040 bool Reverse = (NonZeros & 0x3) == 2; 3041 for (unsigned i = 0; i < 2; ++i) 3042 if (Reverse) 3043 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3044 else 3045 MaskVec.push_back(DAG.getConstant(i, EVT)); 3046 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3047 for (unsigned i = 0; i < 2; ++i) 3048 if (Reverse) 3049 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3050 else 3051 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3052 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3053 &MaskVec[0], MaskVec.size()); 3054 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3055 } 3056 3057 if (Values.size() > 2) { 3058 // Expand into a number of unpckl*. 3059 // e.g. for v4f32 3060 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3061 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3062 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3063 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); 3064 for (unsigned i = 0; i < NumElems; ++i) 3065 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3066 NumElems >>= 1; 3067 while (NumElems != 0) { 3068 for (unsigned i = 0; i < NumElems; ++i) 3069 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3070 UnpckMask); 3071 NumElems >>= 1; 3072 } 3073 return V[0]; 3074 } 3075 3076 return SDOperand(); 3077} 3078 3079SDOperand 3080X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 3081 SDOperand V1 = Op.getOperand(0); 3082 SDOperand V2 = Op.getOperand(1); 3083 SDOperand PermMask = Op.getOperand(2); 3084 MVT::ValueType VT = Op.getValueType(); 3085 unsigned NumElems = PermMask.getNumOperands(); 3086 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 3087 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 3088 bool V1IsSplat = false; 3089 bool V2IsSplat = false; 3090 3091 if (isUndefShuffle(Op.Val)) 3092 return DAG.getNode(ISD::UNDEF, VT); 3093 3094 if (isSplatMask(PermMask.Val)) { 3095 if (NumElems <= 4) return Op; 3096 // Promote it to a v4i32 splat. 3097 return PromoteSplat(Op, DAG); 3098 } 3099 3100 if (X86::isMOVLMask(PermMask.Val)) 3101 return (V1IsUndef) ? V2 : Op; 3102 3103 if (X86::isMOVSHDUPMask(PermMask.Val) || 3104 X86::isMOVSLDUPMask(PermMask.Val) || 3105 X86::isMOVHLPSMask(PermMask.Val) || 3106 X86::isMOVHPMask(PermMask.Val) || 3107 X86::isMOVLPMask(PermMask.Val)) 3108 return Op; 3109 3110 if (ShouldXformToMOVHLPS(PermMask.Val) || 3111 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) 3112 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3113 3114 bool Commuted = false; 3115 V1IsSplat = isSplatVector(V1.Val); 3116 V2IsSplat = isSplatVector(V2.Val); 3117 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 3118 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3119 std::swap(V1IsSplat, V2IsSplat); 3120 std::swap(V1IsUndef, V2IsUndef); 3121 Commuted = true; 3122 } 3123 3124 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { 3125 if (V2IsUndef) return V1; 3126 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3127 if (V2IsSplat) { 3128 // V2 is a splat, so the mask may be malformed. That is, it may point 3129 // to any V2 element. The instruction selectior won't like this. Get 3130 // a corrected mask and commute to form a proper MOVS{S|D}. 3131 SDOperand NewMask = getMOVLMask(NumElems, DAG); 3132 if (NewMask.Val != PermMask.Val) 3133 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3134 } 3135 return Op; 3136 } 3137 3138 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3139 X86::isUNPCKLMask(PermMask.Val) || 3140 X86::isUNPCKHMask(PermMask.Val)) 3141 return Op; 3142 3143 if (V2IsSplat) { 3144 // Normalize mask so all entries that point to V2 points to its first 3145 // element then try to match unpck{h|l} again. If match, return a 3146 // new vector_shuffle with the corrected mask. 3147 SDOperand NewMask = NormalizeMask(PermMask, DAG); 3148 if (NewMask.Val != PermMask.Val) { 3149 if (X86::isUNPCKLMask(PermMask.Val, true)) { 3150 SDOperand NewMask = getUnpacklMask(NumElems, DAG); 3151 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3152 } else if (X86::isUNPCKHMask(PermMask.Val, true)) { 3153 SDOperand NewMask = getUnpackhMask(NumElems, DAG); 3154 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3155 } 3156 } 3157 } 3158 3159 // Normalize the node to match x86 shuffle ops if needed 3160 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val)) 3161 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3162 3163 if (Commuted) { 3164 // Commute is back and try unpck* again. 3165 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3166 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3167 X86::isUNPCKLMask(PermMask.Val) || 3168 X86::isUNPCKHMask(PermMask.Val)) 3169 return Op; 3170 } 3171 3172 // If VT is integer, try PSHUF* first, then SHUFP*. 3173 if (MVT::isInteger(VT)) { 3174 if (X86::isPSHUFDMask(PermMask.Val) || 3175 X86::isPSHUFHWMask(PermMask.Val) || 3176 X86::isPSHUFLWMask(PermMask.Val)) { 3177 if (V2.getOpcode() != ISD::UNDEF) 3178 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3179 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3180 return Op; 3181 } 3182 3183 if (X86::isSHUFPMask(PermMask.Val)) 3184 return Op; 3185 3186 // Handle v8i16 shuffle high / low shuffle node pair. 3187 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { 3188 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3189 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3190 std::vector<SDOperand> MaskVec; 3191 for (unsigned i = 0; i != 4; ++i) 3192 MaskVec.push_back(PermMask.getOperand(i)); 3193 for (unsigned i = 4; i != 8; ++i) 3194 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3195 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3196 &MaskVec[0], MaskVec.size()); 3197 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3198 MaskVec.clear(); 3199 for (unsigned i = 0; i != 4; ++i) 3200 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3201 for (unsigned i = 4; i != 8; ++i) 3202 MaskVec.push_back(PermMask.getOperand(i)); 3203 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size()); 3204 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3205 } 3206 } else { 3207 // Floating point cases in the other order. 3208 if (X86::isSHUFPMask(PermMask.Val)) 3209 return Op; 3210 if (X86::isPSHUFDMask(PermMask.Val) || 3211 X86::isPSHUFHWMask(PermMask.Val) || 3212 X86::isPSHUFLWMask(PermMask.Val)) { 3213 if (V2.getOpcode() != ISD::UNDEF) 3214 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3215 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3216 return Op; 3217 } 3218 } 3219 3220 if (NumElems == 4) { 3221 MVT::ValueType MaskVT = PermMask.getValueType(); 3222 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 3223 std::vector<std::pair<int, int> > Locs; 3224 Locs.reserve(NumElems); 3225 std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3226 std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3227 unsigned NumHi = 0; 3228 unsigned NumLo = 0; 3229 // If no more than two elements come from either vector. This can be 3230 // implemented with two shuffles. First shuffle gather the elements. 3231 // The second shuffle, which takes the first shuffle as both of its 3232 // vector operands, put the elements into the right order. 3233 for (unsigned i = 0; i != NumElems; ++i) { 3234 SDOperand Elt = PermMask.getOperand(i); 3235 if (Elt.getOpcode() == ISD::UNDEF) { 3236 Locs[i] = std::make_pair(-1, -1); 3237 } else { 3238 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 3239 if (Val < NumElems) { 3240 Locs[i] = std::make_pair(0, NumLo); 3241 Mask1[NumLo] = Elt; 3242 NumLo++; 3243 } else { 3244 Locs[i] = std::make_pair(1, NumHi); 3245 if (2+NumHi < NumElems) 3246 Mask1[2+NumHi] = Elt; 3247 NumHi++; 3248 } 3249 } 3250 } 3251 if (NumLo <= 2 && NumHi <= 2) { 3252 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3253 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3254 &Mask1[0], Mask1.size())); 3255 for (unsigned i = 0; i != NumElems; ++i) { 3256 if (Locs[i].first == -1) 3257 continue; 3258 else { 3259 unsigned Idx = (i < NumElems/2) ? 0 : NumElems; 3260 Idx += Locs[i].first * (NumElems/2) + Locs[i].second; 3261 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3262 } 3263 } 3264 3265 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3266 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3267 &Mask2[0], Mask2.size())); 3268 } 3269 3270 // Break it into (shuffle shuffle_hi, shuffle_lo). 3271 Locs.clear(); 3272 std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3273 std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3274 std::vector<SDOperand> *MaskPtr = &LoMask; 3275 unsigned MaskIdx = 0; 3276 unsigned LoIdx = 0; 3277 unsigned HiIdx = NumElems/2; 3278 for (unsigned i = 0; i != NumElems; ++i) { 3279 if (i == NumElems/2) { 3280 MaskPtr = &HiMask; 3281 MaskIdx = 1; 3282 LoIdx = 0; 3283 HiIdx = NumElems/2; 3284 } 3285 SDOperand Elt = PermMask.getOperand(i); 3286 if (Elt.getOpcode() == ISD::UNDEF) { 3287 Locs[i] = std::make_pair(-1, -1); 3288 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) { 3289 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3290 (*MaskPtr)[LoIdx] = Elt; 3291 LoIdx++; 3292 } else { 3293 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3294 (*MaskPtr)[HiIdx] = Elt; 3295 HiIdx++; 3296 } 3297 } 3298 3299 SDOperand LoShuffle = 3300 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3301 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3302 &LoMask[0], LoMask.size())); 3303 SDOperand HiShuffle = 3304 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3305 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3306 &HiMask[0], HiMask.size())); 3307 std::vector<SDOperand> MaskOps; 3308 for (unsigned i = 0; i != NumElems; ++i) { 3309 if (Locs[i].first == -1) { 3310 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3311 } else { 3312 unsigned Idx = Locs[i].first * NumElems + Locs[i].second; 3313 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3314 } 3315 } 3316 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3317 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3318 &MaskOps[0], MaskOps.size())); 3319 } 3320 3321 return SDOperand(); 3322} 3323 3324SDOperand 3325X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3326 if (!isa<ConstantSDNode>(Op.getOperand(1))) 3327 return SDOperand(); 3328 3329 MVT::ValueType VT = Op.getValueType(); 3330 // TODO: handle v16i8. 3331 if (MVT::getSizeInBits(VT) == 16) { 3332 // Transform it so it match pextrw which produces a 32-bit result. 3333 MVT::ValueType EVT = (MVT::ValueType)(VT+1); 3334 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 3335 Op.getOperand(0), Op.getOperand(1)); 3336 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 3337 DAG.getValueType(VT)); 3338 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 3339 } else if (MVT::getSizeInBits(VT) == 32) { 3340 SDOperand Vec = Op.getOperand(0); 3341 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3342 if (Idx == 0) 3343 return Op; 3344 // SHUFPS the element to the lowest double word, then movss. 3345 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3346 std::vector<SDOperand> IdxVec; 3347 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT))); 3348 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3349 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3350 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3351 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3352 &IdxVec[0], IdxVec.size()); 3353 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3354 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 3355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3356 DAG.getConstant(0, getPointerTy())); 3357 } else if (MVT::getSizeInBits(VT) == 64) { 3358 SDOperand Vec = Op.getOperand(0); 3359 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3360 if (Idx == 0) 3361 return Op; 3362 3363 // UNPCKHPD the element to the lowest double word, then movsd. 3364 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 3365 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 3366 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3367 std::vector<SDOperand> IdxVec; 3368 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); 3369 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3370 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3371 &IdxVec[0], IdxVec.size()); 3372 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3373 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 3374 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3375 DAG.getConstant(0, getPointerTy())); 3376 } 3377 3378 return SDOperand(); 3379} 3380 3381SDOperand 3382X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3383 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 3384 // as its second argument. 3385 MVT::ValueType VT = Op.getValueType(); 3386 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT); 3387 SDOperand N0 = Op.getOperand(0); 3388 SDOperand N1 = Op.getOperand(1); 3389 SDOperand N2 = Op.getOperand(2); 3390 if (MVT::getSizeInBits(BaseVT) == 16) { 3391 if (N1.getValueType() != MVT::i32) 3392 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 3393 if (N2.getValueType() != MVT::i32) 3394 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32); 3395 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 3396 } else if (MVT::getSizeInBits(BaseVT) == 32) { 3397 unsigned Idx = cast<ConstantSDNode>(N2)->getValue(); 3398 if (Idx == 0) { 3399 // Use a movss. 3400 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1); 3401 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3402 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3403 std::vector<SDOperand> MaskVec; 3404 MaskVec.push_back(DAG.getConstant(4, BaseVT)); 3405 for (unsigned i = 1; i <= 3; ++i) 3406 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3407 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1, 3408 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3409 &MaskVec[0], MaskVec.size())); 3410 } else { 3411 // Use two pinsrw instructions to insert a 32 bit value. 3412 Idx <<= 1; 3413 if (MVT::isFloatingPoint(N1.getValueType())) { 3414 if (ISD::isNON_EXTLoad(N1.Val)) { 3415 // Just load directly from f32mem to GR32. 3416 LoadSDNode *LD = cast<LoadSDNode>(N1); 3417 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(), 3418 LD->getSrcValue(), LD->getSrcValueOffset()); 3419 } else { 3420 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1); 3421 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1); 3422 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1, 3423 DAG.getConstant(0, getPointerTy())); 3424 } 3425 } 3426 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0); 3427 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 3428 DAG.getConstant(Idx, getPointerTy())); 3429 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8)); 3430 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 3431 DAG.getConstant(Idx+1, getPointerTy())); 3432 return DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3433 } 3434 } 3435 3436 return SDOperand(); 3437} 3438 3439SDOperand 3440X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 3441 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 3442 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt); 3443} 3444 3445// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 3446// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 3447// one of the above mentioned nodes. It has to be wrapped because otherwise 3448// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 3449// be used to form addressing mode. These wrapped nodes will be selected 3450// into MOV32ri. 3451SDOperand 3452X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 3453 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 3454 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(), 3455 getPointerTy(), 3456 CP->getAlignment()); 3457 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3458 // With PIC, the address is actually $g + Offset. 3459 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3460 !Subtarget->isPICStyleRIPRel()) { 3461 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3462 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3463 Result); 3464 } 3465 3466 return Result; 3467} 3468 3469SDOperand 3470X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 3471 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 3472 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); 3473 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3474 // With PIC, the address is actually $g + Offset. 3475 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3476 !Subtarget->isPICStyleRIPRel()) { 3477 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3478 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3479 Result); 3480 } 3481 3482 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 3483 // load the value at address GV, not the value of GV itself. This means that 3484 // the GlobalAddress must be in the base or index register of the address, not 3485 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 3486 // The same applies for external symbols during PIC codegen 3487 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) 3488 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); 3489 3490 return Result; 3491} 3492 3493SDOperand 3494X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { 3495 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 3496 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 3497 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3498 // With PIC, the address is actually $g + Offset. 3499 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3500 !Subtarget->isPICStyleRIPRel()) { 3501 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3502 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3503 Result); 3504 } 3505 3506 return Result; 3507} 3508 3509SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 3510 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 3511 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 3512 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3513 // With PIC, the address is actually $g + Offset. 3514 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3515 !Subtarget->isPICStyleRIPRel()) { 3516 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3517 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3518 Result); 3519 } 3520 3521 return Result; 3522} 3523 3524SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { 3525 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 3526 "Not an i64 shift!"); 3527 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 3528 SDOperand ShOpLo = Op.getOperand(0); 3529 SDOperand ShOpHi = Op.getOperand(1); 3530 SDOperand ShAmt = Op.getOperand(2); 3531 SDOperand Tmp1 = isSRA ? 3532 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) : 3533 DAG.getConstant(0, MVT::i32); 3534 3535 SDOperand Tmp2, Tmp3; 3536 if (Op.getOpcode() == ISD::SHL_PARTS) { 3537 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); 3538 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); 3539 } else { 3540 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); 3541 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); 3542 } 3543 3544 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3545 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 3546 DAG.getConstant(32, MVT::i8)); 3547 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)}; 3548 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1); 3549 3550 SDOperand Hi, Lo; 3551 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); 3552 3553 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag); 3554 SmallVector<SDOperand, 4> Ops; 3555 if (Op.getOpcode() == ISD::SHL_PARTS) { 3556 Ops.push_back(Tmp2); 3557 Ops.push_back(Tmp3); 3558 Ops.push_back(CC); 3559 Ops.push_back(InFlag); 3560 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3561 InFlag = Hi.getValue(1); 3562 3563 Ops.clear(); 3564 Ops.push_back(Tmp3); 3565 Ops.push_back(Tmp1); 3566 Ops.push_back(CC); 3567 Ops.push_back(InFlag); 3568 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3569 } else { 3570 Ops.push_back(Tmp2); 3571 Ops.push_back(Tmp3); 3572 Ops.push_back(CC); 3573 Ops.push_back(InFlag); 3574 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3575 InFlag = Lo.getValue(1); 3576 3577 Ops.clear(); 3578 Ops.push_back(Tmp3); 3579 Ops.push_back(Tmp1); 3580 Ops.push_back(CC); 3581 Ops.push_back(InFlag); 3582 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3583 } 3584 3585 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32); 3586 Ops.clear(); 3587 Ops.push_back(Lo); 3588 Ops.push_back(Hi); 3589 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); 3590} 3591 3592SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 3593 assert(Op.getOperand(0).getValueType() <= MVT::i64 && 3594 Op.getOperand(0).getValueType() >= MVT::i16 && 3595 "Unknown SINT_TO_FP to lower!"); 3596 3597 SDOperand Result; 3598 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3599 unsigned Size = MVT::getSizeInBits(SrcVT)/8; 3600 MachineFunction &MF = DAG.getMachineFunction(); 3601 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 3602 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3603 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 3604 StackSlot, NULL, 0); 3605 3606 // Build the FILD 3607 std::vector<MVT::ValueType> Tys; 3608 Tys.push_back(MVT::f64); 3609 Tys.push_back(MVT::Other); 3610 if (X86ScalarSSE) Tys.push_back(MVT::Flag); 3611 std::vector<SDOperand> Ops; 3612 Ops.push_back(Chain); 3613 Ops.push_back(StackSlot); 3614 Ops.push_back(DAG.getValueType(SrcVT)); 3615 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD, 3616 Tys, &Ops[0], Ops.size()); 3617 3618 if (X86ScalarSSE) { 3619 Chain = Result.getValue(1); 3620 SDOperand InFlag = Result.getValue(2); 3621 3622 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 3623 // shouldn't be necessary except that RFP cannot be live across 3624 // multiple blocks. When stackifier is fixed, they can be uncoupled. 3625 MachineFunction &MF = DAG.getMachineFunction(); 3626 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3627 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3628 std::vector<MVT::ValueType> Tys; 3629 Tys.push_back(MVT::Other); 3630 std::vector<SDOperand> Ops; 3631 Ops.push_back(Chain); 3632 Ops.push_back(Result); 3633 Ops.push_back(StackSlot); 3634 Ops.push_back(DAG.getValueType(Op.getValueType())); 3635 Ops.push_back(InFlag); 3636 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 3637 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0); 3638 } 3639 3640 return Result; 3641} 3642 3643SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 3644 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 3645 "Unknown FP_TO_SINT to lower!"); 3646 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 3647 // stack slot. 3648 MachineFunction &MF = DAG.getMachineFunction(); 3649 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 3650 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 3651 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3652 3653 unsigned Opc; 3654 switch (Op.getValueType()) { 3655 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 3656 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 3657 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 3658 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 3659 } 3660 3661 SDOperand Chain = DAG.getEntryNode(); 3662 SDOperand Value = Op.getOperand(0); 3663 if (X86ScalarSSE) { 3664 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 3665 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); 3666 std::vector<MVT::ValueType> Tys; 3667 Tys.push_back(MVT::f64); 3668 Tys.push_back(MVT::Other); 3669 std::vector<SDOperand> Ops; 3670 Ops.push_back(Chain); 3671 Ops.push_back(StackSlot); 3672 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType())); 3673 Value = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size()); 3674 Chain = Value.getValue(1); 3675 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 3676 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3677 } 3678 3679 // Build the FP_TO_INT*_IN_MEM 3680 std::vector<SDOperand> Ops; 3681 Ops.push_back(Chain); 3682 Ops.push_back(Value); 3683 Ops.push_back(StackSlot); 3684 SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size()); 3685 3686 // Load the result. 3687 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 3688} 3689 3690SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { 3691 MVT::ValueType VT = Op.getValueType(); 3692 const Type *OpNTy = MVT::getTypeForValueType(VT); 3693 std::vector<Constant*> CV; 3694 if (VT == MVT::f64) { 3695 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63)))); 3696 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3697 } else { 3698 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31)))); 3699 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3700 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3701 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3702 } 3703 Constant *CS = ConstantStruct::get(CV); 3704 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3705 std::vector<MVT::ValueType> Tys; 3706 Tys.push_back(VT); 3707 Tys.push_back(MVT::Other); 3708 SmallVector<SDOperand, 3> Ops; 3709 Ops.push_back(DAG.getEntryNode()); 3710 Ops.push_back(CPIdx); 3711 Ops.push_back(DAG.getSrcValue(NULL)); 3712 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3713 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 3714} 3715 3716SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { 3717 MVT::ValueType VT = Op.getValueType(); 3718 const Type *OpNTy = MVT::getTypeForValueType(VT); 3719 std::vector<Constant*> CV; 3720 if (VT == MVT::f64) { 3721 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63))); 3722 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3723 } else { 3724 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31))); 3725 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3726 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3727 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3728 } 3729 Constant *CS = ConstantStruct::get(CV); 3730 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3731 std::vector<MVT::ValueType> Tys; 3732 Tys.push_back(VT); 3733 Tys.push_back(MVT::Other); 3734 SmallVector<SDOperand, 3> Ops; 3735 Ops.push_back(DAG.getEntryNode()); 3736 Ops.push_back(CPIdx); 3737 Ops.push_back(DAG.getSrcValue(NULL)); 3738 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3739 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 3740} 3741 3742SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 3743 SDOperand Op0 = Op.getOperand(0); 3744 SDOperand Op1 = Op.getOperand(1); 3745 MVT::ValueType VT = Op.getValueType(); 3746 MVT::ValueType SrcVT = Op1.getValueType(); 3747 const Type *SrcTy = MVT::getTypeForValueType(SrcVT); 3748 3749 // If second operand is smaller, extend it first. 3750 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) { 3751 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 3752 SrcVT = VT; 3753 } 3754 3755 // First get the sign bit of second operand. 3756 std::vector<Constant*> CV; 3757 if (SrcVT == MVT::f64) { 3758 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63))); 3759 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3760 } else { 3761 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31))); 3762 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3763 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3764 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3765 } 3766 Constant *CS = ConstantStruct::get(CV); 3767 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3768 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other); 3769 SmallVector<SDOperand, 3> Ops; 3770 Ops.push_back(DAG.getEntryNode()); 3771 Ops.push_back(CPIdx); 3772 Ops.push_back(DAG.getSrcValue(NULL)); 3773 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3774 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 3775 3776 // Shift sign bit right or left if the two operands have different types. 3777 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { 3778 // Op0 is MVT::f32, Op1 is MVT::f64. 3779 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 3780 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 3781 DAG.getConstant(32, MVT::i32)); 3782 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 3783 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 3784 DAG.getConstant(0, getPointerTy())); 3785 } 3786 3787 // Clear first operand sign bit. 3788 CV.clear(); 3789 if (VT == MVT::f64) { 3790 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63)))); 3791 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3792 } else { 3793 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31)))); 3794 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3795 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3796 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3797 } 3798 CS = ConstantStruct::get(CV); 3799 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3800 Tys = DAG.getVTList(VT, MVT::Other); 3801 Ops.clear(); 3802 Ops.push_back(DAG.getEntryNode()); 3803 Ops.push_back(CPIdx); 3804 Ops.push_back(DAG.getSrcValue(NULL)); 3805 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3806 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 3807 3808 // Or the value with the sign bit. 3809 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 3810} 3811 3812SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG, 3813 SDOperand Chain) { 3814 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 3815 SDOperand Cond; 3816 SDOperand Op0 = Op.getOperand(0); 3817 SDOperand Op1 = Op.getOperand(1); 3818 SDOperand CC = Op.getOperand(2); 3819 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3820 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3821 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 3822 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 3823 unsigned X86CC; 3824 3825 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, 3826 Op0, Op1, DAG)) { 3827 SDOperand Ops1[] = { Chain, Op0, Op1 }; 3828 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1); 3829 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 3830 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3831 } 3832 3833 assert(isFP && "Illegal integer SetCC!"); 3834 3835 SDOperand COps[] = { Chain, Op0, Op1 }; 3836 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1); 3837 3838 switch (SetCCOpcode) { 3839 default: assert(false && "Illegal floating point SetCC!"); 3840 case ISD::SETOEQ: { // !PF & ZF 3841 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond }; 3842 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2); 3843 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8), 3844 Tmp1.getValue(1) }; 3845 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3846 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 3847 } 3848 case ISD::SETUNE: { // PF | !ZF 3849 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond }; 3850 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2); 3851 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8), 3852 Tmp1.getValue(1) }; 3853 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3854 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 3855 } 3856 } 3857} 3858 3859SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { 3860 bool addTest = true; 3861 SDOperand Chain = DAG.getEntryNode(); 3862 SDOperand Cond = Op.getOperand(0); 3863 SDOperand CC; 3864 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3865 3866 if (Cond.getOpcode() == ISD::SETCC) 3867 Cond = LowerSETCC(Cond, DAG, Chain); 3868 3869 if (Cond.getOpcode() == X86ISD::SETCC) { 3870 CC = Cond.getOperand(0); 3871 3872 // If condition flag is set by a X86ISD::CMP, then make a copy of it 3873 // (since flag operand cannot be shared). Use it as the condition setting 3874 // operand in place of the X86ISD::SETCC. 3875 // If the X86ISD::SETCC has more than one use, then perhaps it's better 3876 // to use a test instead of duplicating the X86ISD::CMP (for register 3877 // pressure reason)? 3878 SDOperand Cmp = Cond.getOperand(1); 3879 unsigned Opc = Cmp.getOpcode(); 3880 bool IllegalFPCMov = !X86ScalarSSE && 3881 MVT::isFloatingPoint(Op.getValueType()) && 3882 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 3883 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) && 3884 !IllegalFPCMov) { 3885 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 3886 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 3887 addTest = false; 3888 } 3889 } 3890 3891 if (addTest) { 3892 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 3893 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 3894 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 3895 } 3896 3897 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag); 3898 SmallVector<SDOperand, 4> Ops; 3899 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 3900 // condition is true. 3901 Ops.push_back(Op.getOperand(2)); 3902 Ops.push_back(Op.getOperand(1)); 3903 Ops.push_back(CC); 3904 Ops.push_back(Cond.getValue(1)); 3905 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3906} 3907 3908SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { 3909 bool addTest = true; 3910 SDOperand Chain = Op.getOperand(0); 3911 SDOperand Cond = Op.getOperand(1); 3912 SDOperand Dest = Op.getOperand(2); 3913 SDOperand CC; 3914 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3915 3916 if (Cond.getOpcode() == ISD::SETCC) 3917 Cond = LowerSETCC(Cond, DAG, Chain); 3918 3919 if (Cond.getOpcode() == X86ISD::SETCC) { 3920 CC = Cond.getOperand(0); 3921 3922 // If condition flag is set by a X86ISD::CMP, then make a copy of it 3923 // (since flag operand cannot be shared). Use it as the condition setting 3924 // operand in place of the X86ISD::SETCC. 3925 // If the X86ISD::SETCC has more than one use, then perhaps it's better 3926 // to use a test instead of duplicating the X86ISD::CMP (for register 3927 // pressure reason)? 3928 SDOperand Cmp = Cond.getOperand(1); 3929 unsigned Opc = Cmp.getOpcode(); 3930 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) { 3931 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 3932 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 3933 addTest = false; 3934 } 3935 } 3936 3937 if (addTest) { 3938 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 3939 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 3940 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 3941 } 3942 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 3943 Cond, Op.getOperand(2), CC, Cond.getValue(1)); 3944} 3945 3946SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 3947 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3948 3949 if (Subtarget->is64Bit()) 3950 return LowerX86_64CCCCallTo(Op, DAG); 3951 else 3952 switch (CallingConv) { 3953 default: 3954 assert(0 && "Unsupported calling convention"); 3955 case CallingConv::Fast: 3956 if (EnableFastCC) { 3957 return LowerFastCCCallTo(Op, DAG); 3958 } 3959 // Falls through 3960 case CallingConv::C: 3961 return LowerCCCCallTo(Op, DAG); 3962 case CallingConv::X86_StdCall: 3963 return LowerCCCCallTo(Op, DAG, true); 3964 case CallingConv::X86_FastCall: 3965 return LowerFastCCCallTo(Op, DAG, true); 3966 } 3967} 3968 3969SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { 3970 SDOperand Copy; 3971 3972 switch(Op.getNumOperands()) { 3973 default: 3974 assert(0 && "Do not know how to return this many arguments!"); 3975 abort(); 3976 case 1: // ret void. 3977 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), 3978 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 3979 case 3: { 3980 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 3981 3982 if (MVT::isVector(ArgVT) || 3983 (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) { 3984 // Integer or FP vector result -> XMM0. 3985 if (DAG.getMachineFunction().liveout_empty()) 3986 DAG.getMachineFunction().addLiveOut(X86::XMM0); 3987 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1), 3988 SDOperand()); 3989 } else if (MVT::isInteger(ArgVT)) { 3990 // Integer result -> EAX / RAX. 3991 // The C calling convention guarantees the return value has been 3992 // promoted to at least MVT::i32. The X86-64 ABI doesn't require the 3993 // value to be promoted MVT::i64. So we don't have to extend it to 3994 // 64-bit. Return the value in EAX, but mark RAX as liveout. 3995 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 3996 if (DAG.getMachineFunction().liveout_empty()) 3997 DAG.getMachineFunction().addLiveOut(Reg); 3998 3999 Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX; 4000 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1), 4001 SDOperand()); 4002 } else if (!X86ScalarSSE) { 4003 // FP return with fp-stack value. 4004 if (DAG.getMachineFunction().liveout_empty()) 4005 DAG.getMachineFunction().addLiveOut(X86::ST0); 4006 4007 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4008 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; 4009 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2); 4010 } else { 4011 // FP return with ScalarSSE (return on fp-stack). 4012 if (DAG.getMachineFunction().liveout_empty()) 4013 DAG.getMachineFunction().addLiveOut(X86::ST0); 4014 4015 SDOperand MemLoc; 4016 SDOperand Chain = Op.getOperand(0); 4017 SDOperand Value = Op.getOperand(1); 4018 4019 if (ISD::isNON_EXTLoad(Value.Val) && 4020 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) { 4021 Chain = Value.getOperand(0); 4022 MemLoc = Value.getOperand(1); 4023 } else { 4024 // Spill the value to memory and reload it into top of stack. 4025 unsigned Size = MVT::getSizeInBits(ArgVT)/8; 4026 MachineFunction &MF = DAG.getMachineFunction(); 4027 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4028 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); 4029 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0); 4030 } 4031 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other); 4032 SDOperand Ops[] = { Chain, MemLoc, DAG.getValueType(ArgVT) }; 4033 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 4034 4035 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4036 Ops[0] = Copy.getValue(1); 4037 Ops[1] = Copy; 4038 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2); 4039 } 4040 break; 4041 } 4042 case 5: { 4043 unsigned Reg1 = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 4044 unsigned Reg2 = Subtarget->is64Bit() ? X86::RDX : X86::EDX; 4045 if (DAG.getMachineFunction().liveout_empty()) { 4046 DAG.getMachineFunction().addLiveOut(Reg1); 4047 DAG.getMachineFunction().addLiveOut(Reg2); 4048 } 4049 4050 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg2, Op.getOperand(3), 4051 SDOperand()); 4052 Copy = DAG.getCopyToReg(Copy, Reg1, Op.getOperand(1), Copy.getValue(1)); 4053 break; 4054 } 4055 } 4056 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, 4057 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), 4058 Copy.getValue(1)); 4059} 4060 4061SDOperand 4062X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 4063 MachineFunction &MF = DAG.getMachineFunction(); 4064 const Function* Fn = MF.getFunction(); 4065 if (Fn->hasExternalLinkage() && 4066 Subtarget->isTargetCygMing() && 4067 Fn->getName() == "main") 4068 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true); 4069 4070 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4071 if (Subtarget->is64Bit()) 4072 return LowerX86_64CCCArguments(Op, DAG); 4073 else 4074 switch(CC) { 4075 default: 4076 assert(0 && "Unsupported calling convention"); 4077 case CallingConv::Fast: 4078 if (EnableFastCC) { 4079 return LowerFastCCArguments(Op, DAG); 4080 } 4081 // Falls through 4082 case CallingConv::C: 4083 return LowerCCCArguments(Op, DAG); 4084 case CallingConv::X86_StdCall: 4085 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall); 4086 return LowerCCCArguments(Op, DAG, true); 4087 case CallingConv::X86_FastCall: 4088 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall); 4089 return LowerFastCCArguments(Op, DAG, true); 4090 } 4091} 4092 4093SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { 4094 SDOperand InFlag(0, 0); 4095 SDOperand Chain = Op.getOperand(0); 4096 unsigned Align = 4097 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 4098 if (Align == 0) Align = 1; 4099 4100 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 4101 // If not DWORD aligned, call memset if size is less than the threshold. 4102 // It knows how to align to the right boundary first. 4103 if ((Align & 3) != 0 || 4104 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 4105 MVT::ValueType IntPtr = getPointerTy(); 4106 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 4107 TargetLowering::ArgListTy Args; 4108 TargetLowering::ArgListEntry Entry; 4109 Entry.Node = Op.getOperand(1); 4110 Entry.Ty = IntPtrTy; 4111 Entry.isSigned = false; 4112 Entry.isInReg = false; 4113 Entry.isSRet = false; 4114 Args.push_back(Entry); 4115 // Extend the unsigned i8 argument to be an int value for the call. 4116 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); 4117 Entry.Ty = IntPtrTy; 4118 Entry.isSigned = false; 4119 Entry.isInReg = false; 4120 Entry.isSRet = false; 4121 Args.push_back(Entry); 4122 Entry.Node = Op.getOperand(3); 4123 Args.push_back(Entry); 4124 std::pair<SDOperand,SDOperand> CallResult = 4125 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 4126 DAG.getExternalSymbol("memset", IntPtr), Args, DAG); 4127 return CallResult.second; 4128 } 4129 4130 MVT::ValueType AVT; 4131 SDOperand Count; 4132 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 4133 unsigned BytesLeft = 0; 4134 bool TwoRepStos = false; 4135 if (ValC) { 4136 unsigned ValReg; 4137 uint64_t Val = ValC->getValue() & 255; 4138 4139 // If the value is a constant, then we can potentially use larger sets. 4140 switch (Align & 3) { 4141 case 2: // WORD aligned 4142 AVT = MVT::i16; 4143 ValReg = X86::AX; 4144 Val = (Val << 8) | Val; 4145 break; 4146 case 0: // DWORD aligned 4147 AVT = MVT::i32; 4148 ValReg = X86::EAX; 4149 Val = (Val << 8) | Val; 4150 Val = (Val << 16) | Val; 4151 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned 4152 AVT = MVT::i64; 4153 ValReg = X86::RAX; 4154 Val = (Val << 32) | Val; 4155 } 4156 break; 4157 default: // Byte aligned 4158 AVT = MVT::i8; 4159 ValReg = X86::AL; 4160 Count = Op.getOperand(3); 4161 break; 4162 } 4163 4164 if (AVT > MVT::i8) { 4165 if (I) { 4166 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4167 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 4168 BytesLeft = I->getValue() % UBytes; 4169 } else { 4170 assert(AVT >= MVT::i32 && 4171 "Do not use rep;stos if not at least DWORD aligned"); 4172 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 4173 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 4174 TwoRepStos = true; 4175 } 4176 } 4177 4178 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 4179 InFlag); 4180 InFlag = Chain.getValue(1); 4181 } else { 4182 AVT = MVT::i8; 4183 Count = Op.getOperand(3); 4184 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); 4185 InFlag = Chain.getValue(1); 4186 } 4187 4188 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4189 Count, InFlag); 4190 InFlag = Chain.getValue(1); 4191 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4192 Op.getOperand(1), InFlag); 4193 InFlag = Chain.getValue(1); 4194 4195 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4196 std::vector<SDOperand> Ops; 4197 Ops.push_back(Chain); 4198 Ops.push_back(DAG.getValueType(AVT)); 4199 Ops.push_back(InFlag); 4200 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4201 4202 if (TwoRepStos) { 4203 InFlag = Chain.getValue(1); 4204 Count = Op.getOperand(3); 4205 MVT::ValueType CVT = Count.getValueType(); 4206 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 4207 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 4208 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 4209 Left, InFlag); 4210 InFlag = Chain.getValue(1); 4211 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4212 Ops.clear(); 4213 Ops.push_back(Chain); 4214 Ops.push_back(DAG.getValueType(MVT::i8)); 4215 Ops.push_back(InFlag); 4216 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4217 } else if (BytesLeft) { 4218 // Issue stores for the last 1 - 7 bytes. 4219 SDOperand Value; 4220 unsigned Val = ValC->getValue() & 255; 4221 unsigned Offset = I->getValue() - BytesLeft; 4222 SDOperand DstAddr = Op.getOperand(1); 4223 MVT::ValueType AddrVT = DstAddr.getValueType(); 4224 if (BytesLeft >= 4) { 4225 Val = (Val << 8) | Val; 4226 Val = (Val << 16) | Val; 4227 Value = DAG.getConstant(Val, MVT::i32); 4228 Chain = DAG.getStore(Chain, Value, 4229 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4230 DAG.getConstant(Offset, AddrVT)), 4231 NULL, 0); 4232 BytesLeft -= 4; 4233 Offset += 4; 4234 } 4235 if (BytesLeft >= 2) { 4236 Value = DAG.getConstant((Val << 8) | Val, MVT::i16); 4237 Chain = DAG.getStore(Chain, Value, 4238 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4239 DAG.getConstant(Offset, AddrVT)), 4240 NULL, 0); 4241 BytesLeft -= 2; 4242 Offset += 2; 4243 } 4244 if (BytesLeft == 1) { 4245 Value = DAG.getConstant(Val, MVT::i8); 4246 Chain = DAG.getStore(Chain, Value, 4247 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4248 DAG.getConstant(Offset, AddrVT)), 4249 NULL, 0); 4250 } 4251 } 4252 4253 return Chain; 4254} 4255 4256SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 4257 SDOperand Chain = Op.getOperand(0); 4258 unsigned Align = 4259 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 4260 if (Align == 0) Align = 1; 4261 4262 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 4263 // If not DWORD aligned, call memcpy if size is less than the threshold. 4264 // It knows how to align to the right boundary first. 4265 if ((Align & 3) != 0 || 4266 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 4267 MVT::ValueType IntPtr = getPointerTy(); 4268 TargetLowering::ArgListTy Args; 4269 TargetLowering::ArgListEntry Entry; 4270 Entry.Ty = getTargetData()->getIntPtrType(); 4271 Entry.isSigned = false; 4272 Entry.isInReg = false; 4273 Entry.isSRet = false; 4274 Entry.Node = Op.getOperand(1); Args.push_back(Entry); 4275 Entry.Node = Op.getOperand(2); Args.push_back(Entry); 4276 Entry.Node = Op.getOperand(3); Args.push_back(Entry); 4277 std::pair<SDOperand,SDOperand> CallResult = 4278 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 4279 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 4280 return CallResult.second; 4281 } 4282 4283 MVT::ValueType AVT; 4284 SDOperand Count; 4285 unsigned BytesLeft = 0; 4286 bool TwoRepMovs = false; 4287 switch (Align & 3) { 4288 case 2: // WORD aligned 4289 AVT = MVT::i16; 4290 break; 4291 case 0: // DWORD aligned 4292 AVT = MVT::i32; 4293 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned 4294 AVT = MVT::i64; 4295 break; 4296 default: // Byte aligned 4297 AVT = MVT::i8; 4298 Count = Op.getOperand(3); 4299 break; 4300 } 4301 4302 if (AVT > MVT::i8) { 4303 if (I) { 4304 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4305 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 4306 BytesLeft = I->getValue() % UBytes; 4307 } else { 4308 assert(AVT >= MVT::i32 && 4309 "Do not use rep;movs if not at least DWORD aligned"); 4310 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 4311 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 4312 TwoRepMovs = true; 4313 } 4314 } 4315 4316 SDOperand InFlag(0, 0); 4317 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4318 Count, InFlag); 4319 InFlag = Chain.getValue(1); 4320 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4321 Op.getOperand(1), InFlag); 4322 InFlag = Chain.getValue(1); 4323 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 4324 Op.getOperand(2), InFlag); 4325 InFlag = Chain.getValue(1); 4326 4327 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4328 std::vector<SDOperand> Ops; 4329 Ops.push_back(Chain); 4330 Ops.push_back(DAG.getValueType(AVT)); 4331 Ops.push_back(InFlag); 4332 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 4333 4334 if (TwoRepMovs) { 4335 InFlag = Chain.getValue(1); 4336 Count = Op.getOperand(3); 4337 MVT::ValueType CVT = Count.getValueType(); 4338 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 4339 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 4340 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 4341 Left, InFlag); 4342 InFlag = Chain.getValue(1); 4343 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4344 Ops.clear(); 4345 Ops.push_back(Chain); 4346 Ops.push_back(DAG.getValueType(MVT::i8)); 4347 Ops.push_back(InFlag); 4348 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 4349 } else if (BytesLeft) { 4350 // Issue loads and stores for the last 1 - 7 bytes. 4351 unsigned Offset = I->getValue() - BytesLeft; 4352 SDOperand DstAddr = Op.getOperand(1); 4353 MVT::ValueType DstVT = DstAddr.getValueType(); 4354 SDOperand SrcAddr = Op.getOperand(2); 4355 MVT::ValueType SrcVT = SrcAddr.getValueType(); 4356 SDOperand Value; 4357 if (BytesLeft >= 4) { 4358 Value = DAG.getLoad(MVT::i32, Chain, 4359 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4360 DAG.getConstant(Offset, SrcVT)), 4361 NULL, 0); 4362 Chain = Value.getValue(1); 4363 Chain = DAG.getStore(Chain, Value, 4364 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4365 DAG.getConstant(Offset, DstVT)), 4366 NULL, 0); 4367 BytesLeft -= 4; 4368 Offset += 4; 4369 } 4370 if (BytesLeft >= 2) { 4371 Value = DAG.getLoad(MVT::i16, Chain, 4372 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4373 DAG.getConstant(Offset, SrcVT)), 4374 NULL, 0); 4375 Chain = Value.getValue(1); 4376 Chain = DAG.getStore(Chain, Value, 4377 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4378 DAG.getConstant(Offset, DstVT)), 4379 NULL, 0); 4380 BytesLeft -= 2; 4381 Offset += 2; 4382 } 4383 4384 if (BytesLeft == 1) { 4385 Value = DAG.getLoad(MVT::i8, Chain, 4386 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4387 DAG.getConstant(Offset, SrcVT)), 4388 NULL, 0); 4389 Chain = Value.getValue(1); 4390 Chain = DAG.getStore(Chain, Value, 4391 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4392 DAG.getConstant(Offset, DstVT)), 4393 NULL, 0); 4394 } 4395 } 4396 4397 return Chain; 4398} 4399 4400SDOperand 4401X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) { 4402 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4403 std::vector<SDOperand> Ops; 4404 Ops.push_back(Op.getOperand(0)); 4405 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size()); 4406 Ops.clear(); 4407 if (Subtarget->is64Bit()) { 4408 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 4409 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX, 4410 MVT::i64, Copy1.getValue(2)); 4411 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2, 4412 DAG.getConstant(32, MVT::i8)); 4413 Ops.push_back(DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp)); 4414 Ops.push_back(Copy2.getValue(1)); 4415 4416 Tys = DAG.getVTList(MVT::i64, MVT::Other); 4417 } else { 4418 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 4419 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX, 4420 MVT::i32, Copy1.getValue(2)); 4421 Ops.push_back(Copy1); 4422 Ops.push_back(Copy2); 4423 Ops.push_back(Copy2.getValue(1)); 4424 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4425 } 4426 return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size()); 4427} 4428 4429SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { 4430 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 4431 4432 if (!Subtarget->is64Bit()) { 4433 // vastart just stores the address of the VarArgsFrameIndex slot into the 4434 // memory location argument. 4435 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4436 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(), 4437 SV->getOffset()); 4438 } 4439 4440 // __va_list_tag: 4441 // gp_offset (0 - 6 * 8) 4442 // fp_offset (48 - 48 + 8 * 16) 4443 // overflow_arg_area (point to parameters coming in memory). 4444 // reg_save_area 4445 std::vector<SDOperand> MemOps; 4446 SDOperand FIN = Op.getOperand(1); 4447 // Store gp_offset 4448 SDOperand Store = DAG.getStore(Op.getOperand(0), 4449 DAG.getConstant(VarArgsGPOffset, MVT::i32), 4450 FIN, SV->getValue(), SV->getOffset()); 4451 MemOps.push_back(Store); 4452 4453 // Store fp_offset 4454 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4455 DAG.getConstant(4, getPointerTy())); 4456 Store = DAG.getStore(Op.getOperand(0), 4457 DAG.getConstant(VarArgsFPOffset, MVT::i32), 4458 FIN, SV->getValue(), SV->getOffset()); 4459 MemOps.push_back(Store); 4460 4461 // Store ptr to overflow_arg_area 4462 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4463 DAG.getConstant(4, getPointerTy())); 4464 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4465 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(), 4466 SV->getOffset()); 4467 MemOps.push_back(Store); 4468 4469 // Store ptr to reg_save_area. 4470 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4471 DAG.getConstant(8, getPointerTy())); 4472 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 4473 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(), 4474 SV->getOffset()); 4475 MemOps.push_back(Store); 4476 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 4477} 4478 4479SDOperand 4480X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 4481 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 4482 switch (IntNo) { 4483 default: return SDOperand(); // Don't custom lower most intrinsics. 4484 // Comparison intrinsics. 4485 case Intrinsic::x86_sse_comieq_ss: 4486 case Intrinsic::x86_sse_comilt_ss: 4487 case Intrinsic::x86_sse_comile_ss: 4488 case Intrinsic::x86_sse_comigt_ss: 4489 case Intrinsic::x86_sse_comige_ss: 4490 case Intrinsic::x86_sse_comineq_ss: 4491 case Intrinsic::x86_sse_ucomieq_ss: 4492 case Intrinsic::x86_sse_ucomilt_ss: 4493 case Intrinsic::x86_sse_ucomile_ss: 4494 case Intrinsic::x86_sse_ucomigt_ss: 4495 case Intrinsic::x86_sse_ucomige_ss: 4496 case Intrinsic::x86_sse_ucomineq_ss: 4497 case Intrinsic::x86_sse2_comieq_sd: 4498 case Intrinsic::x86_sse2_comilt_sd: 4499 case Intrinsic::x86_sse2_comile_sd: 4500 case Intrinsic::x86_sse2_comigt_sd: 4501 case Intrinsic::x86_sse2_comige_sd: 4502 case Intrinsic::x86_sse2_comineq_sd: 4503 case Intrinsic::x86_sse2_ucomieq_sd: 4504 case Intrinsic::x86_sse2_ucomilt_sd: 4505 case Intrinsic::x86_sse2_ucomile_sd: 4506 case Intrinsic::x86_sse2_ucomigt_sd: 4507 case Intrinsic::x86_sse2_ucomige_sd: 4508 case Intrinsic::x86_sse2_ucomineq_sd: { 4509 unsigned Opc = 0; 4510 ISD::CondCode CC = ISD::SETCC_INVALID; 4511 switch (IntNo) { 4512 default: break; 4513 case Intrinsic::x86_sse_comieq_ss: 4514 case Intrinsic::x86_sse2_comieq_sd: 4515 Opc = X86ISD::COMI; 4516 CC = ISD::SETEQ; 4517 break; 4518 case Intrinsic::x86_sse_comilt_ss: 4519 case Intrinsic::x86_sse2_comilt_sd: 4520 Opc = X86ISD::COMI; 4521 CC = ISD::SETLT; 4522 break; 4523 case Intrinsic::x86_sse_comile_ss: 4524 case Intrinsic::x86_sse2_comile_sd: 4525 Opc = X86ISD::COMI; 4526 CC = ISD::SETLE; 4527 break; 4528 case Intrinsic::x86_sse_comigt_ss: 4529 case Intrinsic::x86_sse2_comigt_sd: 4530 Opc = X86ISD::COMI; 4531 CC = ISD::SETGT; 4532 break; 4533 case Intrinsic::x86_sse_comige_ss: 4534 case Intrinsic::x86_sse2_comige_sd: 4535 Opc = X86ISD::COMI; 4536 CC = ISD::SETGE; 4537 break; 4538 case Intrinsic::x86_sse_comineq_ss: 4539 case Intrinsic::x86_sse2_comineq_sd: 4540 Opc = X86ISD::COMI; 4541 CC = ISD::SETNE; 4542 break; 4543 case Intrinsic::x86_sse_ucomieq_ss: 4544 case Intrinsic::x86_sse2_ucomieq_sd: 4545 Opc = X86ISD::UCOMI; 4546 CC = ISD::SETEQ; 4547 break; 4548 case Intrinsic::x86_sse_ucomilt_ss: 4549 case Intrinsic::x86_sse2_ucomilt_sd: 4550 Opc = X86ISD::UCOMI; 4551 CC = ISD::SETLT; 4552 break; 4553 case Intrinsic::x86_sse_ucomile_ss: 4554 case Intrinsic::x86_sse2_ucomile_sd: 4555 Opc = X86ISD::UCOMI; 4556 CC = ISD::SETLE; 4557 break; 4558 case Intrinsic::x86_sse_ucomigt_ss: 4559 case Intrinsic::x86_sse2_ucomigt_sd: 4560 Opc = X86ISD::UCOMI; 4561 CC = ISD::SETGT; 4562 break; 4563 case Intrinsic::x86_sse_ucomige_ss: 4564 case Intrinsic::x86_sse2_ucomige_sd: 4565 Opc = X86ISD::UCOMI; 4566 CC = ISD::SETGE; 4567 break; 4568 case Intrinsic::x86_sse_ucomineq_ss: 4569 case Intrinsic::x86_sse2_ucomineq_sd: 4570 Opc = X86ISD::UCOMI; 4571 CC = ISD::SETNE; 4572 break; 4573 } 4574 4575 unsigned X86CC; 4576 SDOperand LHS = Op.getOperand(1); 4577 SDOperand RHS = Op.getOperand(2); 4578 translateX86CC(CC, true, X86CC, LHS, RHS, DAG); 4579 4580 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4581 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS }; 4582 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3); 4583 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 4584 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 4585 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 4586 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); 4587 } 4588 } 4589} 4590 4591SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 4592 // Depths > 0 not supported yet! 4593 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 4594 return SDOperand(); 4595 4596 // Just load the return address 4597 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 4598 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 4599} 4600 4601SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 4602 // Depths > 0 not supported yet! 4603 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 4604 return SDOperand(); 4605 4606 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 4607 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 4608 DAG.getConstant(4, getPointerTy())); 4609} 4610 4611/// LowerOperation - Provide custom lowering hooks for some operations. 4612/// 4613SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4614 switch (Op.getOpcode()) { 4615 default: assert(0 && "Should not custom lower this!"); 4616 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4617 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4618 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4619 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 4620 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4621 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4622 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4623 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 4624 case ISD::SHL_PARTS: 4625 case ISD::SRA_PARTS: 4626 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 4627 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4628 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 4629 case ISD::FABS: return LowerFABS(Op, DAG); 4630 case ISD::FNEG: return LowerFNEG(Op, DAG); 4631 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4632 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode()); 4633 case ISD::SELECT: return LowerSELECT(Op, DAG); 4634 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 4635 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4636 case ISD::CALL: return LowerCALL(Op, DAG); 4637 case ISD::RET: return LowerRET(Op, DAG); 4638 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 4639 case ISD::MEMSET: return LowerMEMSET(Op, DAG); 4640 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 4641 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG); 4642 case ISD::VASTART: return LowerVASTART(Op, DAG); 4643 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4644 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4645 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4646 } 4647 return SDOperand(); 4648} 4649 4650const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 4651 switch (Opcode) { 4652 default: return NULL; 4653 case X86ISD::SHLD: return "X86ISD::SHLD"; 4654 case X86ISD::SHRD: return "X86ISD::SHRD"; 4655 case X86ISD::FAND: return "X86ISD::FAND"; 4656 case X86ISD::FOR: return "X86ISD::FOR"; 4657 case X86ISD::FXOR: return "X86ISD::FXOR"; 4658 case X86ISD::FSRL: return "X86ISD::FSRL"; 4659 case X86ISD::FILD: return "X86ISD::FILD"; 4660 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 4661 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 4662 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 4663 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 4664 case X86ISD::FLD: return "X86ISD::FLD"; 4665 case X86ISD::FST: return "X86ISD::FST"; 4666 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; 4667 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; 4668 case X86ISD::CALL: return "X86ISD::CALL"; 4669 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 4670 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 4671 case X86ISD::CMP: return "X86ISD::CMP"; 4672 case X86ISD::COMI: return "X86ISD::COMI"; 4673 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 4674 case X86ISD::SETCC: return "X86ISD::SETCC"; 4675 case X86ISD::CMOV: return "X86ISD::CMOV"; 4676 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 4677 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 4678 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 4679 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 4680 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; 4681 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA"; 4682 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 4683 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 4684 case X86ISD::S2VEC: return "X86ISD::S2VEC"; 4685 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 4686 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 4687 case X86ISD::FMAX: return "X86ISD::FMAX"; 4688 case X86ISD::FMIN: return "X86ISD::FMIN"; 4689 } 4690} 4691 4692/// isLegalAddressImmediate - Return true if the integer value or 4693/// GlobalValue can be used as the offset of the target addressing mode. 4694bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const { 4695 // X86 allows a sign-extended 32-bit immediate field. 4696 return (V > -(1LL << 32) && V < (1LL << 32)-1); 4697} 4698 4699bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { 4700 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement 4701 // field unless we are in small code model. 4702 if (Subtarget->is64Bit() && 4703 getTargetMachine().getCodeModel() != CodeModel::Small) 4704 return false; 4705 4706 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)); 4707} 4708 4709/// isShuffleMaskLegal - Targets can use this to indicate that they only 4710/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4711/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4712/// are assumed to be legal. 4713bool 4714X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 4715 // Only do shuffles on 128-bit vector types for now. 4716 if (MVT::getSizeInBits(VT) == 64) return false; 4717 return (Mask.Val->getNumOperands() <= 4 || 4718 isSplatMask(Mask.Val) || 4719 isPSHUFHW_PSHUFLWMask(Mask.Val) || 4720 X86::isUNPCKLMask(Mask.Val) || 4721 X86::isUNPCKL_v_undef_Mask(Mask.Val) || 4722 X86::isUNPCKHMask(Mask.Val)); 4723} 4724 4725bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 4726 MVT::ValueType EVT, 4727 SelectionDAG &DAG) const { 4728 unsigned NumElts = BVOps.size(); 4729 // Only do shuffles on 128-bit vector types for now. 4730 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; 4731 if (NumElts == 2) return true; 4732 if (NumElts == 4) { 4733 return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) || 4734 isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps)); 4735 } 4736 return false; 4737} 4738 4739//===----------------------------------------------------------------------===// 4740// X86 Scheduler Hooks 4741//===----------------------------------------------------------------------===// 4742 4743MachineBasicBlock * 4744X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 4745 MachineBasicBlock *BB) { 4746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4747 switch (MI->getOpcode()) { 4748 default: assert(false && "Unexpected instr type to insert"); 4749 case X86::CMOV_FR32: 4750 case X86::CMOV_FR64: 4751 case X86::CMOV_V4F32: 4752 case X86::CMOV_V2F64: 4753 case X86::CMOV_V2I64: { 4754 // To "insert" a SELECT_CC instruction, we actually have to insert the 4755 // diamond control-flow pattern. The incoming instruction knows the 4756 // destination vreg to set, the condition code register to branch on, the 4757 // true/false values to select between, and a branch opcode to use. 4758 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4759 ilist<MachineBasicBlock>::iterator It = BB; 4760 ++It; 4761 4762 // thisMBB: 4763 // ... 4764 // TrueVal = ... 4765 // cmpTY ccX, r1, r2 4766 // bCC copy1MBB 4767 // fallthrough --> copy0MBB 4768 MachineBasicBlock *thisMBB = BB; 4769 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 4770 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 4771 unsigned Opc = 4772 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 4773 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 4774 MachineFunction *F = BB->getParent(); 4775 F->getBasicBlockList().insert(It, copy0MBB); 4776 F->getBasicBlockList().insert(It, sinkMBB); 4777 // Update machine-CFG edges by first adding all successors of the current 4778 // block to the new block which will contain the Phi node for the select. 4779 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 4780 e = BB->succ_end(); i != e; ++i) 4781 sinkMBB->addSuccessor(*i); 4782 // Next, remove all successors of the current block, and add the true 4783 // and fallthrough blocks as its successors. 4784 while(!BB->succ_empty()) 4785 BB->removeSuccessor(BB->succ_begin()); 4786 BB->addSuccessor(copy0MBB); 4787 BB->addSuccessor(sinkMBB); 4788 4789 // copy0MBB: 4790 // %FalseValue = ... 4791 // # fallthrough to sinkMBB 4792 BB = copy0MBB; 4793 4794 // Update machine-CFG edges 4795 BB->addSuccessor(sinkMBB); 4796 4797 // sinkMBB: 4798 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4799 // ... 4800 BB = sinkMBB; 4801 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 4802 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 4803 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4804 4805 delete MI; // The pseudo instruction is gone now. 4806 return BB; 4807 } 4808 4809 case X86::FP_TO_INT16_IN_MEM: 4810 case X86::FP_TO_INT32_IN_MEM: 4811 case X86::FP_TO_INT64_IN_MEM: { 4812 // Change the floating point control register to use "round towards zero" 4813 // mode when truncating to an integer value. 4814 MachineFunction *F = BB->getParent(); 4815 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 4816 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 4817 4818 // Load the old value of the high byte of the control word... 4819 unsigned OldCW = 4820 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); 4821 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 4822 4823 // Set the high part to be round to zero... 4824 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 4825 .addImm(0xC7F); 4826 4827 // Reload the modified control word now... 4828 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 4829 4830 // Restore the memory image of control word to original value 4831 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 4832 .addReg(OldCW); 4833 4834 // Get the X86 opcode to use. 4835 unsigned Opc; 4836 switch (MI->getOpcode()) { 4837 default: assert(0 && "illegal opcode!"); 4838 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; 4839 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; 4840 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; 4841 } 4842 4843 X86AddressMode AM; 4844 MachineOperand &Op = MI->getOperand(0); 4845 if (Op.isRegister()) { 4846 AM.BaseType = X86AddressMode::RegBase; 4847 AM.Base.Reg = Op.getReg(); 4848 } else { 4849 AM.BaseType = X86AddressMode::FrameIndexBase; 4850 AM.Base.FrameIndex = Op.getFrameIndex(); 4851 } 4852 Op = MI->getOperand(1); 4853 if (Op.isImmediate()) 4854 AM.Scale = Op.getImm(); 4855 Op = MI->getOperand(2); 4856 if (Op.isImmediate()) 4857 AM.IndexReg = Op.getImm(); 4858 Op = MI->getOperand(3); 4859 if (Op.isGlobalAddress()) { 4860 AM.GV = Op.getGlobal(); 4861 } else { 4862 AM.Disp = Op.getImm(); 4863 } 4864 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 4865 .addReg(MI->getOperand(4).getReg()); 4866 4867 // Reload the original control word now. 4868 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 4869 4870 delete MI; // The pseudo instruction is gone now. 4871 return BB; 4872 } 4873 } 4874} 4875 4876//===----------------------------------------------------------------------===// 4877// X86 Optimization Hooks 4878//===----------------------------------------------------------------------===// 4879 4880void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 4881 uint64_t Mask, 4882 uint64_t &KnownZero, 4883 uint64_t &KnownOne, 4884 unsigned Depth) const { 4885 unsigned Opc = Op.getOpcode(); 4886 assert((Opc >= ISD::BUILTIN_OP_END || 4887 Opc == ISD::INTRINSIC_WO_CHAIN || 4888 Opc == ISD::INTRINSIC_W_CHAIN || 4889 Opc == ISD::INTRINSIC_VOID) && 4890 "Should use MaskedValueIsZero if you don't know whether Op" 4891 " is a target node!"); 4892 4893 KnownZero = KnownOne = 0; // Don't know anything. 4894 switch (Opc) { 4895 default: break; 4896 case X86ISD::SETCC: 4897 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 4898 break; 4899 } 4900} 4901 4902/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4903/// element of the result of the vector shuffle. 4904static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) { 4905 MVT::ValueType VT = N->getValueType(0); 4906 SDOperand PermMask = N->getOperand(2); 4907 unsigned NumElems = PermMask.getNumOperands(); 4908 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1); 4909 i %= NumElems; 4910 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4911 return (i == 0) 4912 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 4913 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { 4914 SDOperand Idx = PermMask.getOperand(i); 4915 if (Idx.getOpcode() == ISD::UNDEF) 4916 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 4917 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG); 4918 } 4919 return SDOperand(); 4920} 4921 4922/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 4923/// node is a GlobalAddress + an offset. 4924static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) { 4925 unsigned Opc = N->getOpcode(); 4926 if (Opc == X86ISD::Wrapper) { 4927 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) { 4928 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 4929 return true; 4930 } 4931 } else if (Opc == ISD::ADD) { 4932 SDOperand N1 = N->getOperand(0); 4933 SDOperand N2 = N->getOperand(1); 4934 if (isGAPlusOffset(N1.Val, GA, Offset)) { 4935 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 4936 if (V) { 4937 Offset += V->getSignExtended(); 4938 return true; 4939 } 4940 } else if (isGAPlusOffset(N2.Val, GA, Offset)) { 4941 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 4942 if (V) { 4943 Offset += V->getSignExtended(); 4944 return true; 4945 } 4946 } 4947 } 4948 return false; 4949} 4950 4951/// isConsecutiveLoad - Returns true if N is loading from an address of Base 4952/// + Dist * Size. 4953static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size, 4954 MachineFrameInfo *MFI) { 4955 if (N->getOperand(0).Val != Base->getOperand(0).Val) 4956 return false; 4957 4958 SDOperand Loc = N->getOperand(1); 4959 SDOperand BaseLoc = Base->getOperand(1); 4960 if (Loc.getOpcode() == ISD::FrameIndex) { 4961 if (BaseLoc.getOpcode() != ISD::FrameIndex) 4962 return false; 4963 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex(); 4964 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 4965 int FS = MFI->getObjectSize(FI); 4966 int BFS = MFI->getObjectSize(BFI); 4967 if (FS != BFS || FS != Size) return false; 4968 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size); 4969 } else { 4970 GlobalValue *GV1 = NULL; 4971 GlobalValue *GV2 = NULL; 4972 int64_t Offset1 = 0; 4973 int64_t Offset2 = 0; 4974 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); 4975 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); 4976 if (isGA1 && isGA2 && GV1 == GV2) 4977 return Offset1 == (Offset2 + Dist*Size); 4978 } 4979 4980 return false; 4981} 4982 4983static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, 4984 const X86Subtarget *Subtarget) { 4985 GlobalValue *GV; 4986 int64_t Offset; 4987 if (isGAPlusOffset(Base, GV, Offset)) 4988 return (GV->getAlignment() >= 16 && (Offset % 16) == 0); 4989 else { 4990 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!"); 4991 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex(); 4992 if (BFI < 0) 4993 // Fixed objects do not specify alignment, however the offsets are known. 4994 return ((Subtarget->getStackAlignment() % 16) == 0 && 4995 (MFI->getObjectOffset(BFI) % 16) == 0); 4996 else 4997 return MFI->getObjectAlignment(BFI) >= 16; 4998 } 4999 return false; 5000} 5001 5002 5003/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 5004/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 5005/// if the load addresses are consecutive, non-overlapping, and in the right 5006/// order. 5007static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 5008 const X86Subtarget *Subtarget) { 5009 MachineFunction &MF = DAG.getMachineFunction(); 5010 MachineFrameInfo *MFI = MF.getFrameInfo(); 5011 MVT::ValueType VT = N->getValueType(0); 5012 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 5013 SDOperand PermMask = N->getOperand(2); 5014 int NumElems = (int)PermMask.getNumOperands(); 5015 SDNode *Base = NULL; 5016 for (int i = 0; i < NumElems; ++i) { 5017 SDOperand Idx = PermMask.getOperand(i); 5018 if (Idx.getOpcode() == ISD::UNDEF) { 5019 if (!Base) return SDOperand(); 5020 } else { 5021 SDOperand Arg = 5022 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG); 5023 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val)) 5024 return SDOperand(); 5025 if (!Base) 5026 Base = Arg.Val; 5027 else if (!isConsecutiveLoad(Arg.Val, Base, 5028 i, MVT::getSizeInBits(EVT)/8,MFI)) 5029 return SDOperand(); 5030 } 5031 } 5032 5033 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); 5034 if (isAlign16) { 5035 LoadSDNode *LD = cast<LoadSDNode>(Base); 5036 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 5037 LD->getSrcValueOffset()); 5038 } else { 5039 // Just use movups, it's shorter. 5040 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other); 5041 SmallVector<SDOperand, 3> Ops; 5042 Ops.push_back(Base->getOperand(0)); 5043 Ops.push_back(Base->getOperand(1)); 5044 Ops.push_back(Base->getOperand(2)); 5045 return DAG.getNode(ISD::BIT_CONVERT, VT, 5046 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size())); 5047 } 5048} 5049 5050/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 5051static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 5052 const X86Subtarget *Subtarget) { 5053 SDOperand Cond = N->getOperand(0); 5054 5055 // If we have SSE[12] support, try to form min/max nodes. 5056 if (Subtarget->hasSSE2() && 5057 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 5058 if (Cond.getOpcode() == ISD::SETCC) { 5059 // Get the LHS/RHS of the select. 5060 SDOperand LHS = N->getOperand(1); 5061 SDOperand RHS = N->getOperand(2); 5062 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 5063 5064 unsigned Opcode = 0; 5065 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 5066 switch (CC) { 5067 default: break; 5068 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 5069 case ISD::SETULE: 5070 case ISD::SETLE: 5071 if (!UnsafeFPMath) break; 5072 // FALL THROUGH. 5073 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 5074 case ISD::SETLT: 5075 Opcode = X86ISD::FMIN; 5076 break; 5077 5078 case ISD::SETOGT: // (X > Y) ? X : Y -> max 5079 case ISD::SETUGT: 5080 case ISD::SETGT: 5081 if (!UnsafeFPMath) break; 5082 // FALL THROUGH. 5083 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 5084 case ISD::SETGE: 5085 Opcode = X86ISD::FMAX; 5086 break; 5087 } 5088 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 5089 switch (CC) { 5090 default: break; 5091 case ISD::SETOGT: // (X > Y) ? Y : X -> min 5092 case ISD::SETUGT: 5093 case ISD::SETGT: 5094 if (!UnsafeFPMath) break; 5095 // FALL THROUGH. 5096 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 5097 case ISD::SETGE: 5098 Opcode = X86ISD::FMIN; 5099 break; 5100 5101 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 5102 case ISD::SETULE: 5103 case ISD::SETLE: 5104 if (!UnsafeFPMath) break; 5105 // FALL THROUGH. 5106 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 5107 case ISD::SETLT: 5108 Opcode = X86ISD::FMAX; 5109 break; 5110 } 5111 } 5112 5113 if (Opcode) 5114 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 5115 } 5116 5117 } 5118 5119 return SDOperand(); 5120} 5121 5122 5123SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, 5124 DAGCombinerInfo &DCI) const { 5125 SelectionDAG &DAG = DCI.DAG; 5126 switch (N->getOpcode()) { 5127 default: break; 5128 case ISD::VECTOR_SHUFFLE: 5129 return PerformShuffleCombine(N, DAG, Subtarget); 5130 case ISD::SELECT: 5131 return PerformSELECTCombine(N, DAG, Subtarget); 5132 } 5133 5134 return SDOperand(); 5135} 5136 5137//===----------------------------------------------------------------------===// 5138// X86 Inline Assembly Support 5139//===----------------------------------------------------------------------===// 5140 5141/// getConstraintType - Given a constraint letter, return the type of 5142/// constraint it is for this target. 5143X86TargetLowering::ConstraintType 5144X86TargetLowering::getConstraintType(char ConstraintLetter) const { 5145 switch (ConstraintLetter) { 5146 case 'A': 5147 case 'r': 5148 case 'R': 5149 case 'l': 5150 case 'q': 5151 case 'Q': 5152 case 'x': 5153 case 'Y': 5154 return C_RegisterClass; 5155 default: return TargetLowering::getConstraintType(ConstraintLetter); 5156 } 5157} 5158 5159/// isOperandValidForConstraint - Return the specified operand (possibly 5160/// modified) if the specified SDOperand is valid for the specified target 5161/// constraint letter, otherwise return null. 5162SDOperand X86TargetLowering:: 5163isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) { 5164 switch (Constraint) { 5165 default: break; 5166 case 'i': 5167 // Literal immediates are always ok. 5168 if (isa<ConstantSDNode>(Op)) return Op; 5169 5170 // If we are in non-pic codegen mode, we allow the address of a global to 5171 // be used with 'i'. 5172 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { 5173 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 5174 return SDOperand(0, 0); 5175 5176 if (GA->getOpcode() != ISD::TargetGlobalAddress) 5177 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5178 GA->getOffset()); 5179 return Op; 5180 } 5181 5182 // Otherwise, not valid for this mode. 5183 return SDOperand(0, 0); 5184 } 5185 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG); 5186} 5187 5188 5189std::vector<unsigned> X86TargetLowering:: 5190getRegClassForInlineAsmConstraint(const std::string &Constraint, 5191 MVT::ValueType VT) const { 5192 if (Constraint.size() == 1) { 5193 // FIXME: not handling fp-stack yet! 5194 // FIXME: not handling MMX registers yet ('y' constraint). 5195 switch (Constraint[0]) { // GCC X86 Constraint Letters 5196 default: break; // Unknown constraint letter 5197 case 'A': // EAX/EDX 5198 if (VT == MVT::i32 || VT == MVT::i64) 5199 return make_vector<unsigned>(X86::EAX, X86::EDX, 0); 5200 break; 5201 case 'r': // GENERAL_REGS 5202 case 'R': // LEGACY_REGS 5203 if (VT == MVT::i64 && Subtarget->is64Bit()) 5204 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 5205 X86::RSI, X86::RDI, X86::RBP, X86::RSP, 5206 X86::R8, X86::R9, X86::R10, X86::R11, 5207 X86::R12, X86::R13, X86::R14, X86::R15, 0); 5208 if (VT == MVT::i32) 5209 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 5210 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); 5211 else if (VT == MVT::i16) 5212 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 5213 X86::SI, X86::DI, X86::BP, X86::SP, 0); 5214 else if (VT == MVT::i8) 5215 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 5216 break; 5217 case 'l': // INDEX_REGS 5218 if (VT == MVT::i32) 5219 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 5220 X86::ESI, X86::EDI, X86::EBP, 0); 5221 else if (VT == MVT::i16) 5222 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 5223 X86::SI, X86::DI, X86::BP, 0); 5224 else if (VT == MVT::i8) 5225 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 5226 break; 5227 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 5228 case 'Q': // Q_REGS 5229 if (VT == MVT::i32) 5230 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 5231 else if (VT == MVT::i16) 5232 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 5233 else if (VT == MVT::i8) 5234 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 5235 break; 5236 case 'x': // SSE_REGS if SSE1 allowed 5237 if (Subtarget->hasSSE1()) 5238 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 5239 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 5240 0); 5241 return std::vector<unsigned>(); 5242 case 'Y': // SSE_REGS if SSE2 allowed 5243 if (Subtarget->hasSSE2()) 5244 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 5245 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 5246 0); 5247 return std::vector<unsigned>(); 5248 } 5249 } 5250 5251 return std::vector<unsigned>(); 5252} 5253 5254std::pair<unsigned, const TargetRegisterClass*> 5255X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5256 MVT::ValueType VT) const { 5257 // Use the default implementation in TargetLowering to convert the register 5258 // constraint into a member of a register class. 5259 std::pair<unsigned, const TargetRegisterClass*> Res; 5260 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5261 5262 // Not found as a standard register? 5263 if (Res.second == 0) { 5264 // GCC calls "st(0)" just plain "st". 5265 if (StringsEqualNoCase("{st}", Constraint)) { 5266 Res.first = X86::ST0; 5267 Res.second = X86::RSTRegisterClass; 5268 } 5269 5270 return Res; 5271 } 5272 5273 // Otherwise, check to see if this is a register class of the wrong value 5274 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 5275 // turn into {ax},{dx}. 5276 if (Res.second->hasType(VT)) 5277 return Res; // Correct type already, nothing to do. 5278 5279 // All of the single-register GCC register classes map their values onto 5280 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 5281 // really want an 8-bit or 32-bit register, map to the appropriate register 5282 // class and return the appropriate register. 5283 if (Res.second != X86::GR16RegisterClass) 5284 return Res; 5285 5286 if (VT == MVT::i8) { 5287 unsigned DestReg = 0; 5288 switch (Res.first) { 5289 default: break; 5290 case X86::AX: DestReg = X86::AL; break; 5291 case X86::DX: DestReg = X86::DL; break; 5292 case X86::CX: DestReg = X86::CL; break; 5293 case X86::BX: DestReg = X86::BL; break; 5294 } 5295 if (DestReg) { 5296 Res.first = DestReg; 5297 Res.second = Res.second = X86::GR8RegisterClass; 5298 } 5299 } else if (VT == MVT::i32) { 5300 unsigned DestReg = 0; 5301 switch (Res.first) { 5302 default: break; 5303 case X86::AX: DestReg = X86::EAX; break; 5304 case X86::DX: DestReg = X86::EDX; break; 5305 case X86::CX: DestReg = X86::ECX; break; 5306 case X86::BX: DestReg = X86::EBX; break; 5307 case X86::SI: DestReg = X86::ESI; break; 5308 case X86::DI: DestReg = X86::EDI; break; 5309 case X86::BP: DestReg = X86::EBP; break; 5310 case X86::SP: DestReg = X86::ESP; break; 5311 } 5312 if (DestReg) { 5313 Res.first = DestReg; 5314 Res.second = Res.second = X86::GR32RegisterClass; 5315 } 5316 } else if (VT == MVT::i64) { 5317 unsigned DestReg = 0; 5318 switch (Res.first) { 5319 default: break; 5320 case X86::AX: DestReg = X86::RAX; break; 5321 case X86::DX: DestReg = X86::RDX; break; 5322 case X86::CX: DestReg = X86::RCX; break; 5323 case X86::BX: DestReg = X86::RBX; break; 5324 case X86::SI: DestReg = X86::RSI; break; 5325 case X86::DI: DestReg = X86::RDI; break; 5326 case X86::BP: DestReg = X86::RBP; break; 5327 case X86::SP: DestReg = X86::RSP; break; 5328 } 5329 if (DestReg) { 5330 Res.first = DestReg; 5331 Res.second = Res.second = X86::GR64RegisterClass; 5332 } 5333 } 5334 5335 return Res; 5336} 5337