X86ISelLowering.cpp revision dca62d53b74164364b3eaa58df3a284cf86fa016
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/MC/MCAsmInfo.h" 40#include "llvm/MC/MCContext.h" 41#include "llvm/MC/MCExpr.h" 42#include "llvm/MC/MCSymbol.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/Support/CallSite.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetOptions.h" 55using namespace llvm; 56using namespace dwarf; 57 58STATISTIC(NumTailCalls, "Number of tail calls"); 59 60// Forward declarations. 61static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64static SDValue Insert128BitVector(SDValue Result, 65 SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl); 69 70static SDValue Extract128BitVector(SDValue Vec, 71 SDValue Idx, 72 SelectionDAG &DAG, 73 DebugLoc dl); 74 75/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 76/// sets things up to match to an AVX VEXTRACTF128 instruction or a 77/// simple subregister reference. Idx is an index in the 128 bits we 78/// want. It need not be aligned to a 128-bit bounday. That makes 79/// lowering EXTRACT_VECTOR_ELT operations easier. 80static SDValue Extract128BitVector(SDValue Vec, 81 SDValue Idx, 82 SelectionDAG &DAG, 83 DebugLoc dl) { 84 EVT VT = Vec.getValueType(); 85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 86 EVT ElVT = VT.getVectorElementType(); 87 int Factor = VT.getSizeInBits()/128; 88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 89 VT.getVectorNumElements()/Factor); 90 91 // Extract from UNDEF is UNDEF. 92 if (Vec.getOpcode() == ISD::UNDEF) 93 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 94 95 if (isa<ConstantSDNode>(Idx)) { 96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 97 98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 99 // we can match to VEXTRACTF128. 100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 101 102 // This is the index of the first element of the 128-bit chunk 103 // we want. 104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 105 * ElemsPerChunk); 106 107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 109 VecIdx); 110 111 return Result; 112 } 113 114 return SDValue(); 115} 116 117/// Generate a DAG to put 128-bits into a vector > 128 bits. This 118/// sets things up to match to an AVX VINSERTF128 instruction or a 119/// simple superregister reference. Idx is an index in the 128 bits 120/// we want. It need not be aligned to a 128-bit bounday. That makes 121/// lowering INSERT_VECTOR_ELT operations easier. 122static SDValue Insert128BitVector(SDValue Result, 123 SDValue Vec, 124 SDValue Idx, 125 SelectionDAG &DAG, 126 DebugLoc dl) { 127 if (isa<ConstantSDNode>(Idx)) { 128 EVT VT = Vec.getValueType(); 129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 130 131 EVT ElVT = VT.getVectorElementType(); 132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 133 EVT ResultVT = Result.getValueType(); 134 135 // Insert the relevant 128 bits. 136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 137 138 // This is the index of the first element of the 128-bit chunk 139 // we want. 140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 141 * ElemsPerChunk); 142 143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 145 VecIdx); 146 return Result; 147 } 148 149 return SDValue(); 150} 151 152static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 154 bool is64Bit = Subtarget->is64Bit(); 155 156 if (Subtarget->isTargetEnvMacho()) { 157 if (is64Bit) 158 return new X8664_MachoTargetObjectFile(); 159 return new TargetLoweringObjectFileMachO(); 160 } 161 162 if (Subtarget->isTargetELF()) 163 return new TargetLoweringObjectFileELF(); 164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 165 return new TargetLoweringObjectFileCOFF(); 166 llvm_unreachable("unknown subtarget type"); 167} 168 169X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 170 : TargetLowering(TM, createTLOF(TM)) { 171 Subtarget = &TM.getSubtarget<X86Subtarget>(); 172 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 173 X86ScalarSSEf32 = Subtarget->hasXMM(); 174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 175 176 RegInfo = TM.getRegisterInfo(); 177 TD = getTargetData(); 178 179 // Set up the TargetLowering object. 180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 181 182 // X86 is weird, it always uses i8 for shift amounts and setcc results. 183 setBooleanContents(ZeroOrOneBooleanContent); 184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 186 187 // For 64-bit since we have so many registers use the ILP scheduler, for 188 // 32-bit code use the register pressure specific scheduling. 189 if (Subtarget->is64Bit()) 190 setSchedulingPreference(Sched::ILP); 191 else 192 setSchedulingPreference(Sched::RegPressure); 193 setStackPointerRegisterToSaveRestore(X86StackPtr); 194 195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 196 // Setup Windows compiler runtime calls. 197 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 199 setLibcallName(RTLIB::SREM_I64, "_allrem"); 200 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 201 setLibcallName(RTLIB::MUL_I64, "_allmul"); 202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 211 } 212 213 if (Subtarget->isTargetDarwin()) { 214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 215 setUseUnderscoreSetJmp(false); 216 setUseUnderscoreLongJmp(false); 217 } else if (Subtarget->isTargetMingw()) { 218 // MS runtime is weird: it exports _setjmp, but longjmp! 219 setUseUnderscoreSetJmp(true); 220 setUseUnderscoreLongJmp(false); 221 } else { 222 setUseUnderscoreSetJmp(true); 223 setUseUnderscoreLongJmp(true); 224 } 225 226 // Set up the register classes. 227 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 228 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 229 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 230 if (Subtarget->is64Bit()) 231 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 232 233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 234 235 // We don't accept any truncstore of integer registers. 236 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 239 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 241 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 242 243 // SETOEQ and SETUNE require checking two conditions. 244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 250 251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 252 // operation. 253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 256 257 if (Subtarget->is64Bit()) { 258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 260 } else if (!UseSoftFloat) { 261 // We have an algorithm for SSE2->double, and we turn this into a 262 // 64-bit FILD followed by conditional FADD for other targets. 263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 264 // We have an algorithm for SSE2, and we turn this into a 64-bit 265 // FILD for other targets. 266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 267 } 268 269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 270 // this operation. 271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 273 274 if (!UseSoftFloat) { 275 // SSE has no i16 to fp conversion, only i32 276 if (X86ScalarSSEf32) { 277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 278 // f32 and f64 cases are Legal, f80 case is not 279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 280 } else { 281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 283 } 284 } else { 285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 287 } 288 289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 290 // are Legal, f80 is custom lowered. 291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 293 294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 295 // this operation. 296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 298 299 if (X86ScalarSSEf32) { 300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 301 // f32 and f64 cases are Legal, f80 case is not 302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 303 } else { 304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 306 } 307 308 // Handle FP_TO_UINT by promoting the destination to a larger signed 309 // conversion. 310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 313 314 if (Subtarget->is64Bit()) { 315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 317 } else if (!UseSoftFloat) { 318 // Since AVX is a superset of SSE3, only check for SSE here. 319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 320 // Expand FP_TO_UINT into a select. 321 // FIXME: We would like to use a Custom expander here eventually to do 322 // the optimal thing for SSE vs. the default expansion in the legalizer. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 324 else 325 // With SSE3 we can use fisttpll to convert to a signed i64; without 326 // SSE, we're stuck with a fistpll. 327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 328 } 329 330 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 331 if (!X86ScalarSSEf64) { 332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 334 if (Subtarget->is64Bit()) { 335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 336 // Without SSE, i64->f64 goes through memory. 337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 338 } 339 } 340 341 // Scalar integer divide and remainder are lowered to use operations that 342 // produce two results, to match the available instructions. This exposes 343 // the two-result form to trivial CSE, which is able to combine x/y and x%y 344 // into a single instruction. 345 // 346 // Scalar integer multiply-high is also lowered to use two-result 347 // operations, to match the available instructions. However, plain multiply 348 // (low) operations are left as Legal, as there are single-result 349 // instructions for this in x86. Using the two-result multiply instructions 350 // when both high and low results are needed must be arranged by dagcombine. 351 for (unsigned i = 0, e = 4; i != e; ++i) { 352 MVT VT = IntVTs[i]; 353 setOperationAction(ISD::MULHS, VT, Expand); 354 setOperationAction(ISD::MULHU, VT, Expand); 355 setOperationAction(ISD::SDIV, VT, Expand); 356 setOperationAction(ISD::UDIV, VT, Expand); 357 setOperationAction(ISD::SREM, VT, Expand); 358 setOperationAction(ISD::UREM, VT, Expand); 359 360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 361 setOperationAction(ISD::ADDC, VT, Custom); 362 setOperationAction(ISD::ADDE, VT, Custom); 363 setOperationAction(ISD::SUBC, VT, Custom); 364 setOperationAction(ISD::SUBE, VT, Custom); 365 } 366 367 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 368 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 369 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 371 if (Subtarget->is64Bit()) 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f32 , Expand); 378 setOperationAction(ISD::FREM , MVT::f64 , Expand); 379 setOperationAction(ISD::FREM , MVT::f80 , Expand); 380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 381 382 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 383 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 384 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 385 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 387 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 388 if (Subtarget->is64Bit()) { 389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 390 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 391 } 392 393 if (Subtarget->hasPOPCNT()) { 394 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 395 } else { 396 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 397 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 398 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 399 if (Subtarget->is64Bit()) 400 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 401 } 402 403 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 404 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 405 406 // These should be promoted to a larger select which is supported. 407 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 408 // X86 wants to expand cmov itself. 409 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 410 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 411 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 412 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 413 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 414 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 415 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 416 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 417 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 418 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 419 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 420 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 421 if (Subtarget->is64Bit()) { 422 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 423 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 424 } 425 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 426 427 // Darwin ABI issue. 428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 432 if (Subtarget->is64Bit()) 433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 436 if (Subtarget->is64Bit()) { 437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 442 } 443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 447 if (Subtarget->is64Bit()) { 448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 451 } 452 453 if (Subtarget->hasXMM()) 454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 455 456 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 457 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 458 459 // On X86 and X86-64, atomic operations are lowered to locked instructions. 460 // Locked instructions, in turn, have implicit fence semantics (all memory 461 // operations are flushed before issuing the locked instruction, and they 462 // are not buffered), so we can fold away the common pattern of 463 // fence-atomic-fence. 464 setShouldFoldAtomicFences(true); 465 466 // Expand certain atomics 467 for (unsigned i = 0, e = 4; i != e; ++i) { 468 MVT VT = IntVTs[i]; 469 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 470 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 471 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 472 } 473 474 if (!Subtarget->is64Bit()) { 475 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 476 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 477 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 478 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 479 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 480 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 481 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 482 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 483 } 484 485 if (Subtarget->hasCmpxchg16b()) { 486 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 487 } 488 489 // FIXME - use subtarget debug flags 490 if (!Subtarget->isTargetDarwin() && 491 !Subtarget->isTargetELF() && 492 !Subtarget->isTargetCygMing()) { 493 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 494 } 495 496 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 497 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 498 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 499 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 500 if (Subtarget->is64Bit()) { 501 setExceptionPointerRegister(X86::RAX); 502 setExceptionSelectorRegister(X86::RDX); 503 } else { 504 setExceptionPointerRegister(X86::EAX); 505 setExceptionSelectorRegister(X86::EDX); 506 } 507 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 508 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 509 510 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 511 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 512 513 setOperationAction(ISD::TRAP, MVT::Other, Legal); 514 515 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 516 setOperationAction(ISD::VASTART , MVT::Other, Custom); 517 setOperationAction(ISD::VAEND , MVT::Other, Expand); 518 if (Subtarget->is64Bit()) { 519 setOperationAction(ISD::VAARG , MVT::Other, Custom); 520 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 521 } else { 522 setOperationAction(ISD::VAARG , MVT::Other, Expand); 523 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 524 } 525 526 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 527 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 528 529 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 530 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 531 MVT::i64 : MVT::i32, Custom); 532 else if (EnableSegmentedStacks) 533 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 534 MVT::i64 : MVT::i32, Custom); 535 else 536 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 537 MVT::i64 : MVT::i32, Expand); 538 539 if (!UseSoftFloat && X86ScalarSSEf64) { 540 // f32 and f64 use SSE. 541 // Set up the FP register classes. 542 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 543 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 544 545 // Use ANDPD to simulate FABS. 546 setOperationAction(ISD::FABS , MVT::f64, Custom); 547 setOperationAction(ISD::FABS , MVT::f32, Custom); 548 549 // Use XORP to simulate FNEG. 550 setOperationAction(ISD::FNEG , MVT::f64, Custom); 551 setOperationAction(ISD::FNEG , MVT::f32, Custom); 552 553 // Use ANDPD and ORPD to simulate FCOPYSIGN. 554 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 555 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 556 557 // Lower this to FGETSIGNx86 plus an AND. 558 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 559 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 560 561 // We don't support sin/cos/fmod 562 setOperationAction(ISD::FSIN , MVT::f64, Expand); 563 setOperationAction(ISD::FCOS , MVT::f64, Expand); 564 setOperationAction(ISD::FSIN , MVT::f32, Expand); 565 setOperationAction(ISD::FCOS , MVT::f32, Expand); 566 567 // Expand FP immediates into loads from the stack, except for the special 568 // cases we handle. 569 addLegalFPImmediate(APFloat(+0.0)); // xorpd 570 addLegalFPImmediate(APFloat(+0.0f)); // xorps 571 } else if (!UseSoftFloat && X86ScalarSSEf32) { 572 // Use SSE for f32, x87 for f64. 573 // Set up the FP register classes. 574 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 575 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 576 577 // Use ANDPS to simulate FABS. 578 setOperationAction(ISD::FABS , MVT::f32, Custom); 579 580 // Use XORP to simulate FNEG. 581 setOperationAction(ISD::FNEG , MVT::f32, Custom); 582 583 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 584 585 // Use ANDPS and ORPS to simulate FCOPYSIGN. 586 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 587 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 588 589 // We don't support sin/cos/fmod 590 setOperationAction(ISD::FSIN , MVT::f32, Expand); 591 setOperationAction(ISD::FCOS , MVT::f32, Expand); 592 593 // Special cases we handle for FP constants. 594 addLegalFPImmediate(APFloat(+0.0f)); // xorps 595 addLegalFPImmediate(APFloat(+0.0)); // FLD0 596 addLegalFPImmediate(APFloat(+1.0)); // FLD1 597 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 598 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 599 600 if (!UnsafeFPMath) { 601 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 602 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 603 } 604 } else if (!UseSoftFloat) { 605 // f32 and f64 in x87. 606 // Set up the FP register classes. 607 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 608 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 609 610 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 611 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 612 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 613 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 614 615 if (!UnsafeFPMath) { 616 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 617 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 618 } 619 addLegalFPImmediate(APFloat(+0.0)); // FLD0 620 addLegalFPImmediate(APFloat(+1.0)); // FLD1 621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 623 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 624 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 625 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 626 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 627 } 628 629 // We don't support FMA. 630 setOperationAction(ISD::FMA, MVT::f64, Expand); 631 setOperationAction(ISD::FMA, MVT::f32, Expand); 632 633 // Long double always uses X87. 634 if (!UseSoftFloat) { 635 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 636 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 637 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 638 { 639 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 640 addLegalFPImmediate(TmpFlt); // FLD0 641 TmpFlt.changeSign(); 642 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 643 644 bool ignored; 645 APFloat TmpFlt2(+1.0); 646 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 647 &ignored); 648 addLegalFPImmediate(TmpFlt2); // FLD1 649 TmpFlt2.changeSign(); 650 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 651 } 652 653 if (!UnsafeFPMath) { 654 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 655 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 656 } 657 658 setOperationAction(ISD::FMA, MVT::f80, Expand); 659 } 660 661 // Always use a library call for pow. 662 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 663 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 664 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 665 666 setOperationAction(ISD::FLOG, MVT::f80, Expand); 667 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 668 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 669 setOperationAction(ISD::FEXP, MVT::f80, Expand); 670 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 671 672 // First set operation action for all vector types to either promote 673 // (for widening) or expand (for scalarization). Then we will selectively 674 // turn on ones that can be effectively codegen'd. 675 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 676 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 677 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 678 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 679 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 680 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 681 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 682 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 683 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 684 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 685 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 692 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 694 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 695 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 703 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 732 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 733 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 734 setTruncStoreAction((MVT::SimpleValueType)VT, 735 (MVT::SimpleValueType)InnerVT, Expand); 736 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 737 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 738 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 739 } 740 741 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 742 // with -msoft-float, disable use of MMX as well. 743 if (!UseSoftFloat && Subtarget->hasMMX()) { 744 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 745 // No operations on x86mmx supported, everything uses intrinsics. 746 } 747 748 // MMX-sized vectors (other than x86mmx) are expected to be expanded 749 // into smaller operations. 750 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 751 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 752 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 753 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 754 setOperationAction(ISD::AND, MVT::v8i8, Expand); 755 setOperationAction(ISD::AND, MVT::v4i16, Expand); 756 setOperationAction(ISD::AND, MVT::v2i32, Expand); 757 setOperationAction(ISD::AND, MVT::v1i64, Expand); 758 setOperationAction(ISD::OR, MVT::v8i8, Expand); 759 setOperationAction(ISD::OR, MVT::v4i16, Expand); 760 setOperationAction(ISD::OR, MVT::v2i32, Expand); 761 setOperationAction(ISD::OR, MVT::v1i64, Expand); 762 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 763 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 764 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 765 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 766 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 768 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 769 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 771 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 772 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 773 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 774 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 775 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 776 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 777 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 778 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 779 780 if (!UseSoftFloat && Subtarget->hasXMM()) { 781 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 782 783 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 789 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 790 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 791 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 793 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 794 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 795 } 796 797 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 798 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 799 800 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 801 // registers cannot be used even for integer operations. 802 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 803 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 804 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 805 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 806 807 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 808 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 809 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 810 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 811 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 812 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 813 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 814 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 815 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 816 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 817 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 818 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 819 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 820 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 821 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 822 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 823 824 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 825 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 826 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 827 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 828 829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 834 835 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 836 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 837 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 838 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 839 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 840 841 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 842 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 843 EVT VT = (MVT::SimpleValueType)i; 844 // Do not attempt to custom lower non-power-of-2 vectors 845 if (!isPowerOf2_32(VT.getVectorNumElements())) 846 continue; 847 // Do not attempt to custom lower non-128-bit vectors 848 if (!VT.is128BitVector()) 849 continue; 850 setOperationAction(ISD::BUILD_VECTOR, 851 VT.getSimpleVT().SimpleTy, Custom); 852 setOperationAction(ISD::VECTOR_SHUFFLE, 853 VT.getSimpleVT().SimpleTy, Custom); 854 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 855 VT.getSimpleVT().SimpleTy, Custom); 856 } 857 858 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 859 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 860 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 861 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 864 865 if (Subtarget->is64Bit()) { 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 867 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 868 } 869 870 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 871 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 872 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 873 EVT VT = SVT; 874 875 // Do not attempt to promote non-128-bit vectors 876 if (!VT.is128BitVector()) 877 continue; 878 879 setOperationAction(ISD::AND, SVT, Promote); 880 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 881 setOperationAction(ISD::OR, SVT, Promote); 882 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 883 setOperationAction(ISD::XOR, SVT, Promote); 884 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 885 setOperationAction(ISD::LOAD, SVT, Promote); 886 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 887 setOperationAction(ISD::SELECT, SVT, Promote); 888 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 889 } 890 891 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 892 893 // Custom lower v2i64 and v2f64 selects. 894 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 895 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 896 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 897 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 898 899 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 900 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 901 } 902 903 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 904 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 905 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 906 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 907 setOperationAction(ISD::FRINT, MVT::f32, Legal); 908 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 909 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 910 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 911 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 912 setOperationAction(ISD::FRINT, MVT::f64, Legal); 913 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 914 915 // FIXME: Do we need to handle scalar-to-vector here? 916 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 917 918 // Can turn SHL into an integer multiply. 919 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 920 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 921 922 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 923 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 924 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 925 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 926 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 927 928 // i8 and i16 vectors are custom , because the source register and source 929 // source memory operand types are not the same width. f32 vectors are 930 // custom since the immediate controlling the insert encodes additional 931 // information. 932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 935 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 936 937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 938 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 939 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 941 942 if (Subtarget->is64Bit()) { 943 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 945 } 946 } 947 948 if (Subtarget->hasXMMInt()) { 949 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 950 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 951 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 952 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 953 954 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 955 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 956 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 957 958 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 959 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 960 } 961 962 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 963 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 964 965 if (!UseSoftFloat && Subtarget->hasAVX()) { 966 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 967 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 968 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 969 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 970 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 971 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 972 973 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 974 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 975 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 976 977 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 978 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 979 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 980 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 981 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 982 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 983 984 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 985 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 986 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 987 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 988 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 989 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 990 991 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 992 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 993 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 994 995 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 996 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 997 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 998 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 999 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1000 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1001 1002 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1003 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1004 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1005 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1006 1007 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1008 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1009 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1010 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1011 1012 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1013 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1014 1015 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1016 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1017 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1018 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1019 1020 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1021 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1022 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1023 1024 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1025 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1026 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1027 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1028 1029 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1030 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1031 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1032 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1033 1034 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1035 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1036 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1037 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1038 1039 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1040 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1041 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1042 // Don't lower v32i8 because there is no 128-bit byte mul 1043 1044 // Custom lower several nodes for 256-bit types. 1045 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1046 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1047 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1048 EVT VT = SVT; 1049 1050 // Extract subvector is special because the value type 1051 // (result) is 128-bit but the source is 256-bit wide. 1052 if (VT.is128BitVector()) 1053 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1054 1055 // Do not attempt to custom lower other non-256-bit vectors 1056 if (!VT.is256BitVector()) 1057 continue; 1058 1059 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1060 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1061 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1062 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1063 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1064 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1065 } 1066 1067 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1068 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1069 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1070 EVT VT = SVT; 1071 1072 // Do not attempt to promote non-256-bit vectors 1073 if (!VT.is256BitVector()) 1074 continue; 1075 1076 setOperationAction(ISD::AND, SVT, Promote); 1077 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1078 setOperationAction(ISD::OR, SVT, Promote); 1079 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1080 setOperationAction(ISD::XOR, SVT, Promote); 1081 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1082 setOperationAction(ISD::LOAD, SVT, Promote); 1083 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1084 setOperationAction(ISD::SELECT, SVT, Promote); 1085 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1086 } 1087 } 1088 1089 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1090 // of this type with custom code. 1091 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1092 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1093 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1094 } 1095 1096 // We want to custom lower some of our intrinsics. 1097 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1098 1099 1100 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1101 // handle type legalization for these operations here. 1102 // 1103 // FIXME: We really should do custom legalization for addition and 1104 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1105 // than generic legalization for 64-bit multiplication-with-overflow, though. 1106 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1107 // Add/Sub/Mul with overflow operations are custom lowered. 1108 MVT VT = IntVTs[i]; 1109 setOperationAction(ISD::SADDO, VT, Custom); 1110 setOperationAction(ISD::UADDO, VT, Custom); 1111 setOperationAction(ISD::SSUBO, VT, Custom); 1112 setOperationAction(ISD::USUBO, VT, Custom); 1113 setOperationAction(ISD::SMULO, VT, Custom); 1114 setOperationAction(ISD::UMULO, VT, Custom); 1115 } 1116 1117 // There are no 8-bit 3-address imul/mul instructions 1118 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1119 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1120 1121 if (!Subtarget->is64Bit()) { 1122 // These libcalls are not available in 32-bit. 1123 setLibcallName(RTLIB::SHL_I128, 0); 1124 setLibcallName(RTLIB::SRL_I128, 0); 1125 setLibcallName(RTLIB::SRA_I128, 0); 1126 } 1127 1128 // We have target-specific dag combine patterns for the following nodes: 1129 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1130 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1131 setTargetDAGCombine(ISD::BUILD_VECTOR); 1132 setTargetDAGCombine(ISD::VSELECT); 1133 setTargetDAGCombine(ISD::SELECT); 1134 setTargetDAGCombine(ISD::SHL); 1135 setTargetDAGCombine(ISD::SRA); 1136 setTargetDAGCombine(ISD::SRL); 1137 setTargetDAGCombine(ISD::OR); 1138 setTargetDAGCombine(ISD::AND); 1139 setTargetDAGCombine(ISD::ADD); 1140 setTargetDAGCombine(ISD::FADD); 1141 setTargetDAGCombine(ISD::FSUB); 1142 setTargetDAGCombine(ISD::SUB); 1143 setTargetDAGCombine(ISD::LOAD); 1144 setTargetDAGCombine(ISD::STORE); 1145 setTargetDAGCombine(ISD::ZERO_EXTEND); 1146 setTargetDAGCombine(ISD::SINT_TO_FP); 1147 if (Subtarget->is64Bit()) 1148 setTargetDAGCombine(ISD::MUL); 1149 1150 computeRegisterProperties(); 1151 1152 // On Darwin, -Os means optimize for size without hurting performance, 1153 // do not reduce the limit. 1154 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1155 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1156 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1157 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1158 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1159 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1160 setPrefLoopAlignment(16); 1161 benefitFromCodePlacementOpt = true; 1162 1163 setPrefFunctionAlignment(4); 1164} 1165 1166 1167EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1168 if (!VT.isVector()) return MVT::i8; 1169 return VT.changeVectorElementTypeToInteger(); 1170} 1171 1172 1173/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1174/// the desired ByVal argument alignment. 1175static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1176 if (MaxAlign == 16) 1177 return; 1178 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1179 if (VTy->getBitWidth() == 128) 1180 MaxAlign = 16; 1181 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1182 unsigned EltAlign = 0; 1183 getMaxByValAlign(ATy->getElementType(), EltAlign); 1184 if (EltAlign > MaxAlign) 1185 MaxAlign = EltAlign; 1186 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1187 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1188 unsigned EltAlign = 0; 1189 getMaxByValAlign(STy->getElementType(i), EltAlign); 1190 if (EltAlign > MaxAlign) 1191 MaxAlign = EltAlign; 1192 if (MaxAlign == 16) 1193 break; 1194 } 1195 } 1196 return; 1197} 1198 1199/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1200/// function arguments in the caller parameter area. For X86, aggregates 1201/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1202/// are at 4-byte boundaries. 1203unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1204 if (Subtarget->is64Bit()) { 1205 // Max of 8 and alignment of type. 1206 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1207 if (TyAlign > 8) 1208 return TyAlign; 1209 return 8; 1210 } 1211 1212 unsigned Align = 4; 1213 if (Subtarget->hasXMM()) 1214 getMaxByValAlign(Ty, Align); 1215 return Align; 1216} 1217 1218/// getOptimalMemOpType - Returns the target specific optimal type for load 1219/// and store operations as a result of memset, memcpy, and memmove 1220/// lowering. If DstAlign is zero that means it's safe to destination 1221/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1222/// means there isn't a need to check it against alignment requirement, 1223/// probably because the source does not need to be loaded. If 1224/// 'NonScalarIntSafe' is true, that means it's safe to return a 1225/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1226/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1227/// constant so it does not need to be loaded. 1228/// It returns EVT::Other if the type should be determined using generic 1229/// target-independent logic. 1230EVT 1231X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1232 unsigned DstAlign, unsigned SrcAlign, 1233 bool NonScalarIntSafe, 1234 bool MemcpyStrSrc, 1235 MachineFunction &MF) const { 1236 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1237 // linux. This is because the stack realignment code can't handle certain 1238 // cases like PR2962. This should be removed when PR2962 is fixed. 1239 const Function *F = MF.getFunction(); 1240 if (NonScalarIntSafe && 1241 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1242 if (Size >= 16 && 1243 (Subtarget->isUnalignedMemAccessFast() || 1244 ((DstAlign == 0 || DstAlign >= 16) && 1245 (SrcAlign == 0 || SrcAlign >= 16))) && 1246 Subtarget->getStackAlignment() >= 16) { 1247 if (Subtarget->hasAVX() && 1248 Subtarget->getStackAlignment() >= 32) 1249 return MVT::v8f32; 1250 if (Subtarget->hasXMMInt()) 1251 return MVT::v4i32; 1252 if (Subtarget->hasXMM()) 1253 return MVT::v4f32; 1254 } else if (!MemcpyStrSrc && Size >= 8 && 1255 !Subtarget->is64Bit() && 1256 Subtarget->getStackAlignment() >= 8 && 1257 Subtarget->hasXMMInt()) { 1258 // Do not use f64 to lower memcpy if source is string constant. It's 1259 // better to use i32 to avoid the loads. 1260 return MVT::f64; 1261 } 1262 } 1263 if (Subtarget->is64Bit() && Size >= 8) 1264 return MVT::i64; 1265 return MVT::i32; 1266} 1267 1268/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1269/// current function. The returned value is a member of the 1270/// MachineJumpTableInfo::JTEntryKind enum. 1271unsigned X86TargetLowering::getJumpTableEncoding() const { 1272 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1273 // symbol. 1274 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1275 Subtarget->isPICStyleGOT()) 1276 return MachineJumpTableInfo::EK_Custom32; 1277 1278 // Otherwise, use the normal jump table encoding heuristics. 1279 return TargetLowering::getJumpTableEncoding(); 1280} 1281 1282const MCExpr * 1283X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1284 const MachineBasicBlock *MBB, 1285 unsigned uid,MCContext &Ctx) const{ 1286 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1287 Subtarget->isPICStyleGOT()); 1288 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1289 // entries. 1290 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1291 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1292} 1293 1294/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1295/// jumptable. 1296SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1297 SelectionDAG &DAG) const { 1298 if (!Subtarget->is64Bit()) 1299 // This doesn't have DebugLoc associated with it, but is not really the 1300 // same as a Register. 1301 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1302 return Table; 1303} 1304 1305/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1306/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1307/// MCExpr. 1308const MCExpr *X86TargetLowering:: 1309getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1310 MCContext &Ctx) const { 1311 // X86-64 uses RIP relative addressing based on the jump table label. 1312 if (Subtarget->isPICStyleRIPRel()) 1313 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1314 1315 // Otherwise, the reference is relative to the PIC base. 1316 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1317} 1318 1319// FIXME: Why this routine is here? Move to RegInfo! 1320std::pair<const TargetRegisterClass*, uint8_t> 1321X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1322 const TargetRegisterClass *RRC = 0; 1323 uint8_t Cost = 1; 1324 switch (VT.getSimpleVT().SimpleTy) { 1325 default: 1326 return TargetLowering::findRepresentativeClass(VT); 1327 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1328 RRC = (Subtarget->is64Bit() 1329 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1330 break; 1331 case MVT::x86mmx: 1332 RRC = X86::VR64RegisterClass; 1333 break; 1334 case MVT::f32: case MVT::f64: 1335 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1336 case MVT::v4f32: case MVT::v2f64: 1337 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1338 case MVT::v4f64: 1339 RRC = X86::VR128RegisterClass; 1340 break; 1341 } 1342 return std::make_pair(RRC, Cost); 1343} 1344 1345bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1346 unsigned &Offset) const { 1347 if (!Subtarget->isTargetLinux()) 1348 return false; 1349 1350 if (Subtarget->is64Bit()) { 1351 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1352 Offset = 0x28; 1353 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1354 AddressSpace = 256; 1355 else 1356 AddressSpace = 257; 1357 } else { 1358 // %gs:0x14 on i386 1359 Offset = 0x14; 1360 AddressSpace = 256; 1361 } 1362 return true; 1363} 1364 1365 1366//===----------------------------------------------------------------------===// 1367// Return Value Calling Convention Implementation 1368//===----------------------------------------------------------------------===// 1369 1370#include "X86GenCallingConv.inc" 1371 1372bool 1373X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1374 MachineFunction &MF, bool isVarArg, 1375 const SmallVectorImpl<ISD::OutputArg> &Outs, 1376 LLVMContext &Context) const { 1377 SmallVector<CCValAssign, 16> RVLocs; 1378 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1379 RVLocs, Context); 1380 return CCInfo.CheckReturn(Outs, RetCC_X86); 1381} 1382 1383SDValue 1384X86TargetLowering::LowerReturn(SDValue Chain, 1385 CallingConv::ID CallConv, bool isVarArg, 1386 const SmallVectorImpl<ISD::OutputArg> &Outs, 1387 const SmallVectorImpl<SDValue> &OutVals, 1388 DebugLoc dl, SelectionDAG &DAG) const { 1389 MachineFunction &MF = DAG.getMachineFunction(); 1390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1391 1392 SmallVector<CCValAssign, 16> RVLocs; 1393 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1394 RVLocs, *DAG.getContext()); 1395 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1396 1397 // Add the regs to the liveout set for the function. 1398 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1399 for (unsigned i = 0; i != RVLocs.size(); ++i) 1400 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1401 MRI.addLiveOut(RVLocs[i].getLocReg()); 1402 1403 SDValue Flag; 1404 1405 SmallVector<SDValue, 6> RetOps; 1406 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1407 // Operand #1 = Bytes To Pop 1408 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1409 MVT::i16)); 1410 1411 // Copy the result values into the output registers. 1412 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1413 CCValAssign &VA = RVLocs[i]; 1414 assert(VA.isRegLoc() && "Can only return in registers!"); 1415 SDValue ValToCopy = OutVals[i]; 1416 EVT ValVT = ValToCopy.getValueType(); 1417 1418 // If this is x86-64, and we disabled SSE, we can't return FP values, 1419 // or SSE or MMX vectors. 1420 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1421 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1422 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1423 report_fatal_error("SSE register return with SSE disabled"); 1424 } 1425 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1426 // llvm-gcc has never done it right and no one has noticed, so this 1427 // should be OK for now. 1428 if (ValVT == MVT::f64 && 1429 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1430 report_fatal_error("SSE2 register return with SSE2 disabled"); 1431 1432 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1433 // the RET instruction and handled by the FP Stackifier. 1434 if (VA.getLocReg() == X86::ST0 || 1435 VA.getLocReg() == X86::ST1) { 1436 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1437 // change the value to the FP stack register class. 1438 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1439 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1440 RetOps.push_back(ValToCopy); 1441 // Don't emit a copytoreg. 1442 continue; 1443 } 1444 1445 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1446 // which is returned in RAX / RDX. 1447 if (Subtarget->is64Bit()) { 1448 if (ValVT == MVT::x86mmx) { 1449 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1450 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1451 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1452 ValToCopy); 1453 // If we don't have SSE2 available, convert to v4f32 so the generated 1454 // register is legal. 1455 if (!Subtarget->hasXMMInt()) 1456 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1457 } 1458 } 1459 } 1460 1461 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1462 Flag = Chain.getValue(1); 1463 } 1464 1465 // The x86-64 ABI for returning structs by value requires that we copy 1466 // the sret argument into %rax for the return. We saved the argument into 1467 // a virtual register in the entry block, so now we copy the value out 1468 // and into %rax. 1469 if (Subtarget->is64Bit() && 1470 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1471 MachineFunction &MF = DAG.getMachineFunction(); 1472 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1473 unsigned Reg = FuncInfo->getSRetReturnReg(); 1474 assert(Reg && 1475 "SRetReturnReg should have been set in LowerFormalArguments()."); 1476 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1477 1478 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1479 Flag = Chain.getValue(1); 1480 1481 // RAX now acts like a return value. 1482 MRI.addLiveOut(X86::RAX); 1483 } 1484 1485 RetOps[0] = Chain; // Update chain. 1486 1487 // Add the flag if we have it. 1488 if (Flag.getNode()) 1489 RetOps.push_back(Flag); 1490 1491 return DAG.getNode(X86ISD::RET_FLAG, dl, 1492 MVT::Other, &RetOps[0], RetOps.size()); 1493} 1494 1495bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1496 if (N->getNumValues() != 1) 1497 return false; 1498 if (!N->hasNUsesOfValue(1, 0)) 1499 return false; 1500 1501 SDNode *Copy = *N->use_begin(); 1502 if (Copy->getOpcode() != ISD::CopyToReg && 1503 Copy->getOpcode() != ISD::FP_EXTEND) 1504 return false; 1505 1506 bool HasRet = false; 1507 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1508 UI != UE; ++UI) { 1509 if (UI->getOpcode() != X86ISD::RET_FLAG) 1510 return false; 1511 HasRet = true; 1512 } 1513 1514 return HasRet; 1515} 1516 1517EVT 1518X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1519 ISD::NodeType ExtendKind) const { 1520 MVT ReturnMVT; 1521 // TODO: Is this also valid on 32-bit? 1522 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1523 ReturnMVT = MVT::i8; 1524 else 1525 ReturnMVT = MVT::i32; 1526 1527 EVT MinVT = getRegisterType(Context, ReturnMVT); 1528 return VT.bitsLT(MinVT) ? MinVT : VT; 1529} 1530 1531/// LowerCallResult - Lower the result values of a call into the 1532/// appropriate copies out of appropriate physical registers. 1533/// 1534SDValue 1535X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1536 CallingConv::ID CallConv, bool isVarArg, 1537 const SmallVectorImpl<ISD::InputArg> &Ins, 1538 DebugLoc dl, SelectionDAG &DAG, 1539 SmallVectorImpl<SDValue> &InVals) const { 1540 1541 // Assign locations to each value returned by this call. 1542 SmallVector<CCValAssign, 16> RVLocs; 1543 bool Is64Bit = Subtarget->is64Bit(); 1544 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1545 getTargetMachine(), RVLocs, *DAG.getContext()); 1546 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1547 1548 // Copy all of the result registers out of their specified physreg. 1549 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1550 CCValAssign &VA = RVLocs[i]; 1551 EVT CopyVT = VA.getValVT(); 1552 1553 // If this is x86-64, and we disabled SSE, we can't return FP values 1554 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1555 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1556 report_fatal_error("SSE register return with SSE disabled"); 1557 } 1558 1559 SDValue Val; 1560 1561 // If this is a call to a function that returns an fp value on the floating 1562 // point stack, we must guarantee the the value is popped from the stack, so 1563 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1564 // if the return value is not used. We use the FpPOP_RETVAL instruction 1565 // instead. 1566 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1567 // If we prefer to use the value in xmm registers, copy it out as f80 and 1568 // use a truncate to move it from fp stack reg to xmm reg. 1569 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1570 SDValue Ops[] = { Chain, InFlag }; 1571 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1572 MVT::Other, MVT::Glue, Ops, 2), 1); 1573 Val = Chain.getValue(0); 1574 1575 // Round the f80 to the right size, which also moves it to the appropriate 1576 // xmm register. 1577 if (CopyVT != VA.getValVT()) 1578 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1579 // This truncation won't change the value. 1580 DAG.getIntPtrConstant(1)); 1581 } else { 1582 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1583 CopyVT, InFlag).getValue(1); 1584 Val = Chain.getValue(0); 1585 } 1586 InFlag = Chain.getValue(2); 1587 InVals.push_back(Val); 1588 } 1589 1590 return Chain; 1591} 1592 1593 1594//===----------------------------------------------------------------------===// 1595// C & StdCall & Fast Calling Convention implementation 1596//===----------------------------------------------------------------------===// 1597// StdCall calling convention seems to be standard for many Windows' API 1598// routines and around. It differs from C calling convention just a little: 1599// callee should clean up the stack, not caller. Symbols should be also 1600// decorated in some fancy way :) It doesn't support any vector arguments. 1601// For info on fast calling convention see Fast Calling Convention (tail call) 1602// implementation LowerX86_32FastCCCallTo. 1603 1604/// CallIsStructReturn - Determines whether a call uses struct return 1605/// semantics. 1606static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1607 if (Outs.empty()) 1608 return false; 1609 1610 return Outs[0].Flags.isSRet(); 1611} 1612 1613/// ArgsAreStructReturn - Determines whether a function uses struct 1614/// return semantics. 1615static bool 1616ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1617 if (Ins.empty()) 1618 return false; 1619 1620 return Ins[0].Flags.isSRet(); 1621} 1622 1623/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1624/// by "Src" to address "Dst" with size and alignment information specified by 1625/// the specific parameter attribute. The copy will be passed as a byval 1626/// function parameter. 1627static SDValue 1628CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1629 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1630 DebugLoc dl) { 1631 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1632 1633 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1634 /*isVolatile*/false, /*AlwaysInline=*/true, 1635 MachinePointerInfo(), MachinePointerInfo()); 1636} 1637 1638/// IsTailCallConvention - Return true if the calling convention is one that 1639/// supports tail call optimization. 1640static bool IsTailCallConvention(CallingConv::ID CC) { 1641 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1642} 1643 1644bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1645 if (!CI->isTailCall()) 1646 return false; 1647 1648 CallSite CS(CI); 1649 CallingConv::ID CalleeCC = CS.getCallingConv(); 1650 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1651 return false; 1652 1653 return true; 1654} 1655 1656/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1657/// a tailcall target by changing its ABI. 1658static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1659 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1660} 1661 1662SDValue 1663X86TargetLowering::LowerMemArgument(SDValue Chain, 1664 CallingConv::ID CallConv, 1665 const SmallVectorImpl<ISD::InputArg> &Ins, 1666 DebugLoc dl, SelectionDAG &DAG, 1667 const CCValAssign &VA, 1668 MachineFrameInfo *MFI, 1669 unsigned i) const { 1670 // Create the nodes corresponding to a load from this parameter slot. 1671 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1672 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1673 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1674 EVT ValVT; 1675 1676 // If value is passed by pointer we have address passed instead of the value 1677 // itself. 1678 if (VA.getLocInfo() == CCValAssign::Indirect) 1679 ValVT = VA.getLocVT(); 1680 else 1681 ValVT = VA.getValVT(); 1682 1683 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1684 // changed with more analysis. 1685 // In case of tail call optimization mark all arguments mutable. Since they 1686 // could be overwritten by lowering of arguments in case of a tail call. 1687 if (Flags.isByVal()) { 1688 unsigned Bytes = Flags.getByValSize(); 1689 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1690 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1691 return DAG.getFrameIndex(FI, getPointerTy()); 1692 } else { 1693 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1694 VA.getLocMemOffset(), isImmutable); 1695 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1696 return DAG.getLoad(ValVT, dl, Chain, FIN, 1697 MachinePointerInfo::getFixedStack(FI), 1698 false, false, 0); 1699 } 1700} 1701 1702SDValue 1703X86TargetLowering::LowerFormalArguments(SDValue Chain, 1704 CallingConv::ID CallConv, 1705 bool isVarArg, 1706 const SmallVectorImpl<ISD::InputArg> &Ins, 1707 DebugLoc dl, 1708 SelectionDAG &DAG, 1709 SmallVectorImpl<SDValue> &InVals) 1710 const { 1711 MachineFunction &MF = DAG.getMachineFunction(); 1712 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1713 1714 const Function* Fn = MF.getFunction(); 1715 if (Fn->hasExternalLinkage() && 1716 Subtarget->isTargetCygMing() && 1717 Fn->getName() == "main") 1718 FuncInfo->setForceFramePointer(true); 1719 1720 MachineFrameInfo *MFI = MF.getFrameInfo(); 1721 bool Is64Bit = Subtarget->is64Bit(); 1722 bool IsWin64 = Subtarget->isTargetWin64(); 1723 1724 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1725 "Var args not supported with calling convention fastcc or ghc"); 1726 1727 // Assign locations to all of the incoming arguments. 1728 SmallVector<CCValAssign, 16> ArgLocs; 1729 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1730 ArgLocs, *DAG.getContext()); 1731 1732 // Allocate shadow area for Win64 1733 if (IsWin64) { 1734 CCInfo.AllocateStack(32, 8); 1735 } 1736 1737 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1738 1739 unsigned LastVal = ~0U; 1740 SDValue ArgValue; 1741 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1742 CCValAssign &VA = ArgLocs[i]; 1743 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1744 // places. 1745 assert(VA.getValNo() != LastVal && 1746 "Don't support value assigned to multiple locs yet"); 1747 LastVal = VA.getValNo(); 1748 1749 if (VA.isRegLoc()) { 1750 EVT RegVT = VA.getLocVT(); 1751 TargetRegisterClass *RC = NULL; 1752 if (RegVT == MVT::i32) 1753 RC = X86::GR32RegisterClass; 1754 else if (Is64Bit && RegVT == MVT::i64) 1755 RC = X86::GR64RegisterClass; 1756 else if (RegVT == MVT::f32) 1757 RC = X86::FR32RegisterClass; 1758 else if (RegVT == MVT::f64) 1759 RC = X86::FR64RegisterClass; 1760 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1761 RC = X86::VR256RegisterClass; 1762 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1763 RC = X86::VR128RegisterClass; 1764 else if (RegVT == MVT::x86mmx) 1765 RC = X86::VR64RegisterClass; 1766 else 1767 llvm_unreachable("Unknown argument type!"); 1768 1769 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1770 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1771 1772 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1773 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1774 // right size. 1775 if (VA.getLocInfo() == CCValAssign::SExt) 1776 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1777 DAG.getValueType(VA.getValVT())); 1778 else if (VA.getLocInfo() == CCValAssign::ZExt) 1779 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1780 DAG.getValueType(VA.getValVT())); 1781 else if (VA.getLocInfo() == CCValAssign::BCvt) 1782 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1783 1784 if (VA.isExtInLoc()) { 1785 // Handle MMX values passed in XMM regs. 1786 if (RegVT.isVector()) { 1787 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1788 ArgValue); 1789 } else 1790 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1791 } 1792 } else { 1793 assert(VA.isMemLoc()); 1794 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1795 } 1796 1797 // If value is passed via pointer - do a load. 1798 if (VA.getLocInfo() == CCValAssign::Indirect) 1799 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1800 MachinePointerInfo(), false, false, 0); 1801 1802 InVals.push_back(ArgValue); 1803 } 1804 1805 // The x86-64 ABI for returning structs by value requires that we copy 1806 // the sret argument into %rax for the return. Save the argument into 1807 // a virtual register so that we can access it from the return points. 1808 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1809 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1810 unsigned Reg = FuncInfo->getSRetReturnReg(); 1811 if (!Reg) { 1812 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1813 FuncInfo->setSRetReturnReg(Reg); 1814 } 1815 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1816 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1817 } 1818 1819 unsigned StackSize = CCInfo.getNextStackOffset(); 1820 // Align stack specially for tail calls. 1821 if (FuncIsMadeTailCallSafe(CallConv)) 1822 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1823 1824 // If the function takes variable number of arguments, make a frame index for 1825 // the start of the first vararg value... for expansion of llvm.va_start. 1826 if (isVarArg) { 1827 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1828 CallConv != CallingConv::X86_ThisCall)) { 1829 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1830 } 1831 if (Is64Bit) { 1832 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1833 1834 // FIXME: We should really autogenerate these arrays 1835 static const unsigned GPR64ArgRegsWin64[] = { 1836 X86::RCX, X86::RDX, X86::R8, X86::R9 1837 }; 1838 static const unsigned GPR64ArgRegs64Bit[] = { 1839 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1840 }; 1841 static const unsigned XMMArgRegs64Bit[] = { 1842 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1843 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1844 }; 1845 const unsigned *GPR64ArgRegs; 1846 unsigned NumXMMRegs = 0; 1847 1848 if (IsWin64) { 1849 // The XMM registers which might contain var arg parameters are shadowed 1850 // in their paired GPR. So we only need to save the GPR to their home 1851 // slots. 1852 TotalNumIntRegs = 4; 1853 GPR64ArgRegs = GPR64ArgRegsWin64; 1854 } else { 1855 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1856 GPR64ArgRegs = GPR64ArgRegs64Bit; 1857 1858 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1859 } 1860 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1861 TotalNumIntRegs); 1862 1863 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1864 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1865 "SSE register cannot be used when SSE is disabled!"); 1866 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1867 "SSE register cannot be used when SSE is disabled!"); 1868 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1869 // Kernel mode asks for SSE to be disabled, so don't push them 1870 // on the stack. 1871 TotalNumXMMRegs = 0; 1872 1873 if (IsWin64) { 1874 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1875 // Get to the caller-allocated home save location. Add 8 to account 1876 // for the return address. 1877 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1878 FuncInfo->setRegSaveFrameIndex( 1879 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1880 // Fixup to set vararg frame on shadow area (4 x i64). 1881 if (NumIntRegs < 4) 1882 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1883 } else { 1884 // For X86-64, if there are vararg parameters that are passed via 1885 // registers, then we must store them to their spots on the stack so they 1886 // may be loaded by deferencing the result of va_next. 1887 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1888 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1889 FuncInfo->setRegSaveFrameIndex( 1890 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1891 false)); 1892 } 1893 1894 // Store the integer parameter registers. 1895 SmallVector<SDValue, 8> MemOps; 1896 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1897 getPointerTy()); 1898 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1899 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1900 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1901 DAG.getIntPtrConstant(Offset)); 1902 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1903 X86::GR64RegisterClass); 1904 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1905 SDValue Store = 1906 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1907 MachinePointerInfo::getFixedStack( 1908 FuncInfo->getRegSaveFrameIndex(), Offset), 1909 false, false, 0); 1910 MemOps.push_back(Store); 1911 Offset += 8; 1912 } 1913 1914 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1915 // Now store the XMM (fp + vector) parameter registers. 1916 SmallVector<SDValue, 11> SaveXMMOps; 1917 SaveXMMOps.push_back(Chain); 1918 1919 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1920 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1921 SaveXMMOps.push_back(ALVal); 1922 1923 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1924 FuncInfo->getRegSaveFrameIndex())); 1925 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1926 FuncInfo->getVarArgsFPOffset())); 1927 1928 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1929 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1930 X86::VR128RegisterClass); 1931 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1932 SaveXMMOps.push_back(Val); 1933 } 1934 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1935 MVT::Other, 1936 &SaveXMMOps[0], SaveXMMOps.size())); 1937 } 1938 1939 if (!MemOps.empty()) 1940 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1941 &MemOps[0], MemOps.size()); 1942 } 1943 } 1944 1945 // Some CCs need callee pop. 1946 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 1947 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1948 } else { 1949 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1950 // If this is an sret function, the return should pop the hidden pointer. 1951 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1952 FuncInfo->setBytesToPopOnReturn(4); 1953 } 1954 1955 if (!Is64Bit) { 1956 // RegSaveFrameIndex is X86-64 only. 1957 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1958 if (CallConv == CallingConv::X86_FastCall || 1959 CallConv == CallingConv::X86_ThisCall) 1960 // fastcc functions can't have varargs. 1961 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1962 } 1963 1964 FuncInfo->setArgumentStackSize(StackSize); 1965 1966 return Chain; 1967} 1968 1969SDValue 1970X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1971 SDValue StackPtr, SDValue Arg, 1972 DebugLoc dl, SelectionDAG &DAG, 1973 const CCValAssign &VA, 1974 ISD::ArgFlagsTy Flags) const { 1975 unsigned LocMemOffset = VA.getLocMemOffset(); 1976 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1977 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1978 if (Flags.isByVal()) 1979 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1980 1981 return DAG.getStore(Chain, dl, Arg, PtrOff, 1982 MachinePointerInfo::getStack(LocMemOffset), 1983 false, false, 0); 1984} 1985 1986/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1987/// optimization is performed and it is required. 1988SDValue 1989X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1990 SDValue &OutRetAddr, SDValue Chain, 1991 bool IsTailCall, bool Is64Bit, 1992 int FPDiff, DebugLoc dl) const { 1993 // Adjust the Return address stack slot. 1994 EVT VT = getPointerTy(); 1995 OutRetAddr = getReturnAddressFrameIndex(DAG); 1996 1997 // Load the "old" Return address. 1998 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1999 false, false, 0); 2000 return SDValue(OutRetAddr.getNode(), 1); 2001} 2002 2003/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2004/// optimization is performed and it is required (FPDiff!=0). 2005static SDValue 2006EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2007 SDValue Chain, SDValue RetAddrFrIdx, 2008 bool Is64Bit, int FPDiff, DebugLoc dl) { 2009 // Store the return address to the appropriate stack slot. 2010 if (!FPDiff) return Chain; 2011 // Calculate the new stack slot for the return address. 2012 int SlotSize = Is64Bit ? 8 : 4; 2013 int NewReturnAddrFI = 2014 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2015 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2016 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2017 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2018 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2019 false, false, 0); 2020 return Chain; 2021} 2022 2023SDValue 2024X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2025 CallingConv::ID CallConv, bool isVarArg, 2026 bool &isTailCall, 2027 const SmallVectorImpl<ISD::OutputArg> &Outs, 2028 const SmallVectorImpl<SDValue> &OutVals, 2029 const SmallVectorImpl<ISD::InputArg> &Ins, 2030 DebugLoc dl, SelectionDAG &DAG, 2031 SmallVectorImpl<SDValue> &InVals) const { 2032 MachineFunction &MF = DAG.getMachineFunction(); 2033 bool Is64Bit = Subtarget->is64Bit(); 2034 bool IsWin64 = Subtarget->isTargetWin64(); 2035 bool IsStructRet = CallIsStructReturn(Outs); 2036 bool IsSibcall = false; 2037 2038 if (isTailCall) { 2039 // Check if it's really possible to do a tail call. 2040 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2041 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2042 Outs, OutVals, Ins, DAG); 2043 2044 // Sibcalls are automatically detected tailcalls which do not require 2045 // ABI changes. 2046 if (!GuaranteedTailCallOpt && isTailCall) 2047 IsSibcall = true; 2048 2049 if (isTailCall) 2050 ++NumTailCalls; 2051 } 2052 2053 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2054 "Var args not supported with calling convention fastcc or ghc"); 2055 2056 // Analyze operands of the call, assigning locations to each operand. 2057 SmallVector<CCValAssign, 16> ArgLocs; 2058 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2059 ArgLocs, *DAG.getContext()); 2060 2061 // Allocate shadow area for Win64 2062 if (IsWin64) { 2063 CCInfo.AllocateStack(32, 8); 2064 } 2065 2066 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2067 2068 // Get a count of how many bytes are to be pushed on the stack. 2069 unsigned NumBytes = CCInfo.getNextStackOffset(); 2070 if (IsSibcall) 2071 // This is a sibcall. The memory operands are available in caller's 2072 // own caller's stack. 2073 NumBytes = 0; 2074 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2075 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2076 2077 int FPDiff = 0; 2078 if (isTailCall && !IsSibcall) { 2079 // Lower arguments at fp - stackoffset + fpdiff. 2080 unsigned NumBytesCallerPushed = 2081 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2082 FPDiff = NumBytesCallerPushed - NumBytes; 2083 2084 // Set the delta of movement of the returnaddr stackslot. 2085 // But only set if delta is greater than previous delta. 2086 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2087 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2088 } 2089 2090 if (!IsSibcall) 2091 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2092 2093 SDValue RetAddrFrIdx; 2094 // Load return address for tail calls. 2095 if (isTailCall && FPDiff) 2096 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2097 Is64Bit, FPDiff, dl); 2098 2099 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2100 SmallVector<SDValue, 8> MemOpChains; 2101 SDValue StackPtr; 2102 2103 // Walk the register/memloc assignments, inserting copies/loads. In the case 2104 // of tail call optimization arguments are handle later. 2105 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2106 CCValAssign &VA = ArgLocs[i]; 2107 EVT RegVT = VA.getLocVT(); 2108 SDValue Arg = OutVals[i]; 2109 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2110 bool isByVal = Flags.isByVal(); 2111 2112 // Promote the value if needed. 2113 switch (VA.getLocInfo()) { 2114 default: llvm_unreachable("Unknown loc info!"); 2115 case CCValAssign::Full: break; 2116 case CCValAssign::SExt: 2117 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2118 break; 2119 case CCValAssign::ZExt: 2120 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2121 break; 2122 case CCValAssign::AExt: 2123 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2124 // Special case: passing MMX values in XMM registers. 2125 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2126 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2127 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2128 } else 2129 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2130 break; 2131 case CCValAssign::BCvt: 2132 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2133 break; 2134 case CCValAssign::Indirect: { 2135 // Store the argument. 2136 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2137 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2138 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2139 MachinePointerInfo::getFixedStack(FI), 2140 false, false, 0); 2141 Arg = SpillSlot; 2142 break; 2143 } 2144 } 2145 2146 if (VA.isRegLoc()) { 2147 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2148 if (isVarArg && IsWin64) { 2149 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2150 // shadow reg if callee is a varargs function. 2151 unsigned ShadowReg = 0; 2152 switch (VA.getLocReg()) { 2153 case X86::XMM0: ShadowReg = X86::RCX; break; 2154 case X86::XMM1: ShadowReg = X86::RDX; break; 2155 case X86::XMM2: ShadowReg = X86::R8; break; 2156 case X86::XMM3: ShadowReg = X86::R9; break; 2157 } 2158 if (ShadowReg) 2159 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2160 } 2161 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2162 assert(VA.isMemLoc()); 2163 if (StackPtr.getNode() == 0) 2164 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2165 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2166 dl, DAG, VA, Flags)); 2167 } 2168 } 2169 2170 if (!MemOpChains.empty()) 2171 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2172 &MemOpChains[0], MemOpChains.size()); 2173 2174 // Build a sequence of copy-to-reg nodes chained together with token chain 2175 // and flag operands which copy the outgoing args into registers. 2176 SDValue InFlag; 2177 // Tail call byval lowering might overwrite argument registers so in case of 2178 // tail call optimization the copies to registers are lowered later. 2179 if (!isTailCall) 2180 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2181 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2182 RegsToPass[i].second, InFlag); 2183 InFlag = Chain.getValue(1); 2184 } 2185 2186 if (Subtarget->isPICStyleGOT()) { 2187 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2188 // GOT pointer. 2189 if (!isTailCall) { 2190 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2191 DAG.getNode(X86ISD::GlobalBaseReg, 2192 DebugLoc(), getPointerTy()), 2193 InFlag); 2194 InFlag = Chain.getValue(1); 2195 } else { 2196 // If we are tail calling and generating PIC/GOT style code load the 2197 // address of the callee into ECX. The value in ecx is used as target of 2198 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2199 // for tail calls on PIC/GOT architectures. Normally we would just put the 2200 // address of GOT into ebx and then call target@PLT. But for tail calls 2201 // ebx would be restored (since ebx is callee saved) before jumping to the 2202 // target@PLT. 2203 2204 // Note: The actual moving to ECX is done further down. 2205 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2206 if (G && !G->getGlobal()->hasHiddenVisibility() && 2207 !G->getGlobal()->hasProtectedVisibility()) 2208 Callee = LowerGlobalAddress(Callee, DAG); 2209 else if (isa<ExternalSymbolSDNode>(Callee)) 2210 Callee = LowerExternalSymbol(Callee, DAG); 2211 } 2212 } 2213 2214 if (Is64Bit && isVarArg && !IsWin64) { 2215 // From AMD64 ABI document: 2216 // For calls that may call functions that use varargs or stdargs 2217 // (prototype-less calls or calls to functions containing ellipsis (...) in 2218 // the declaration) %al is used as hidden argument to specify the number 2219 // of SSE registers used. The contents of %al do not need to match exactly 2220 // the number of registers, but must be an ubound on the number of SSE 2221 // registers used and is in the range 0 - 8 inclusive. 2222 2223 // Count the number of XMM registers allocated. 2224 static const unsigned XMMArgRegs[] = { 2225 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2226 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2227 }; 2228 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2229 assert((Subtarget->hasXMM() || !NumXMMRegs) 2230 && "SSE registers cannot be used when SSE is disabled"); 2231 2232 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2233 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2234 InFlag = Chain.getValue(1); 2235 } 2236 2237 2238 // For tail calls lower the arguments to the 'real' stack slot. 2239 if (isTailCall) { 2240 // Force all the incoming stack arguments to be loaded from the stack 2241 // before any new outgoing arguments are stored to the stack, because the 2242 // outgoing stack slots may alias the incoming argument stack slots, and 2243 // the alias isn't otherwise explicit. This is slightly more conservative 2244 // than necessary, because it means that each store effectively depends 2245 // on every argument instead of just those arguments it would clobber. 2246 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2247 2248 SmallVector<SDValue, 8> MemOpChains2; 2249 SDValue FIN; 2250 int FI = 0; 2251 // Do not flag preceding copytoreg stuff together with the following stuff. 2252 InFlag = SDValue(); 2253 if (GuaranteedTailCallOpt) { 2254 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2255 CCValAssign &VA = ArgLocs[i]; 2256 if (VA.isRegLoc()) 2257 continue; 2258 assert(VA.isMemLoc()); 2259 SDValue Arg = OutVals[i]; 2260 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2261 // Create frame index. 2262 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2263 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2264 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2265 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2266 2267 if (Flags.isByVal()) { 2268 // Copy relative to framepointer. 2269 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2270 if (StackPtr.getNode() == 0) 2271 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2272 getPointerTy()); 2273 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2274 2275 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2276 ArgChain, 2277 Flags, DAG, dl)); 2278 } else { 2279 // Store relative to framepointer. 2280 MemOpChains2.push_back( 2281 DAG.getStore(ArgChain, dl, Arg, FIN, 2282 MachinePointerInfo::getFixedStack(FI), 2283 false, false, 0)); 2284 } 2285 } 2286 } 2287 2288 if (!MemOpChains2.empty()) 2289 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2290 &MemOpChains2[0], MemOpChains2.size()); 2291 2292 // Copy arguments to their registers. 2293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2294 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2295 RegsToPass[i].second, InFlag); 2296 InFlag = Chain.getValue(1); 2297 } 2298 InFlag =SDValue(); 2299 2300 // Store the return address to the appropriate stack slot. 2301 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2302 FPDiff, dl); 2303 } 2304 2305 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2306 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2307 // In the 64-bit large code model, we have to make all calls 2308 // through a register, since the call instruction's 32-bit 2309 // pc-relative offset may not be large enough to hold the whole 2310 // address. 2311 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2312 // If the callee is a GlobalAddress node (quite common, every direct call 2313 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2314 // it. 2315 2316 // We should use extra load for direct calls to dllimported functions in 2317 // non-JIT mode. 2318 const GlobalValue *GV = G->getGlobal(); 2319 if (!GV->hasDLLImportLinkage()) { 2320 unsigned char OpFlags = 0; 2321 bool ExtraLoad = false; 2322 unsigned WrapperKind = ISD::DELETED_NODE; 2323 2324 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2325 // external symbols most go through the PLT in PIC mode. If the symbol 2326 // has hidden or protected visibility, or if it is static or local, then 2327 // we don't need to use the PLT - we can directly call it. 2328 if (Subtarget->isTargetELF() && 2329 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2330 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2331 OpFlags = X86II::MO_PLT; 2332 } else if (Subtarget->isPICStyleStubAny() && 2333 (GV->isDeclaration() || GV->isWeakForLinker()) && 2334 (!Subtarget->getTargetTriple().isMacOSX() || 2335 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2336 // PC-relative references to external symbols should go through $stub, 2337 // unless we're building with the leopard linker or later, which 2338 // automatically synthesizes these stubs. 2339 OpFlags = X86II::MO_DARWIN_STUB; 2340 } else if (Subtarget->isPICStyleRIPRel() && 2341 isa<Function>(GV) && 2342 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2343 // If the function is marked as non-lazy, generate an indirect call 2344 // which loads from the GOT directly. This avoids runtime overhead 2345 // at the cost of eager binding (and one extra byte of encoding). 2346 OpFlags = X86II::MO_GOTPCREL; 2347 WrapperKind = X86ISD::WrapperRIP; 2348 ExtraLoad = true; 2349 } 2350 2351 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2352 G->getOffset(), OpFlags); 2353 2354 // Add a wrapper if needed. 2355 if (WrapperKind != ISD::DELETED_NODE) 2356 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2357 // Add extra indirection if needed. 2358 if (ExtraLoad) 2359 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2360 MachinePointerInfo::getGOT(), 2361 false, false, 0); 2362 } 2363 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2364 unsigned char OpFlags = 0; 2365 2366 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2367 // external symbols should go through the PLT. 2368 if (Subtarget->isTargetELF() && 2369 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2370 OpFlags = X86II::MO_PLT; 2371 } else if (Subtarget->isPICStyleStubAny() && 2372 (!Subtarget->getTargetTriple().isMacOSX() || 2373 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2374 // PC-relative references to external symbols should go through $stub, 2375 // unless we're building with the leopard linker or later, which 2376 // automatically synthesizes these stubs. 2377 OpFlags = X86II::MO_DARWIN_STUB; 2378 } 2379 2380 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2381 OpFlags); 2382 } 2383 2384 // Returns a chain & a flag for retval copy to use. 2385 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2386 SmallVector<SDValue, 8> Ops; 2387 2388 if (!IsSibcall && isTailCall) { 2389 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2390 DAG.getIntPtrConstant(0, true), InFlag); 2391 InFlag = Chain.getValue(1); 2392 } 2393 2394 Ops.push_back(Chain); 2395 Ops.push_back(Callee); 2396 2397 if (isTailCall) 2398 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2399 2400 // Add argument registers to the end of the list so that they are known live 2401 // into the call. 2402 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2403 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2404 RegsToPass[i].second.getValueType())); 2405 2406 // Add an implicit use GOT pointer in EBX. 2407 if (!isTailCall && Subtarget->isPICStyleGOT()) 2408 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2409 2410 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2411 if (Is64Bit && isVarArg && !IsWin64) 2412 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2413 2414 if (InFlag.getNode()) 2415 Ops.push_back(InFlag); 2416 2417 if (isTailCall) { 2418 // We used to do: 2419 //// If this is the first return lowered for this function, add the regs 2420 //// to the liveout set for the function. 2421 // This isn't right, although it's probably harmless on x86; liveouts 2422 // should be computed from returns not tail calls. Consider a void 2423 // function making a tail call to a function returning int. 2424 return DAG.getNode(X86ISD::TC_RETURN, dl, 2425 NodeTys, &Ops[0], Ops.size()); 2426 } 2427 2428 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2429 InFlag = Chain.getValue(1); 2430 2431 // Create the CALLSEQ_END node. 2432 unsigned NumBytesForCalleeToPush; 2433 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2434 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2435 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2436 // If this is a call to a struct-return function, the callee 2437 // pops the hidden struct pointer, so we have to push it back. 2438 // This is common for Darwin/X86, Linux & Mingw32 targets. 2439 NumBytesForCalleeToPush = 4; 2440 else 2441 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2442 2443 // Returns a flag for retval copy to use. 2444 if (!IsSibcall) { 2445 Chain = DAG.getCALLSEQ_END(Chain, 2446 DAG.getIntPtrConstant(NumBytes, true), 2447 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2448 true), 2449 InFlag); 2450 InFlag = Chain.getValue(1); 2451 } 2452 2453 // Handle result values, copying them out of physregs into vregs that we 2454 // return. 2455 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2456 Ins, dl, DAG, InVals); 2457} 2458 2459 2460//===----------------------------------------------------------------------===// 2461// Fast Calling Convention (tail call) implementation 2462//===----------------------------------------------------------------------===// 2463 2464// Like std call, callee cleans arguments, convention except that ECX is 2465// reserved for storing the tail called function address. Only 2 registers are 2466// free for argument passing (inreg). Tail call optimization is performed 2467// provided: 2468// * tailcallopt is enabled 2469// * caller/callee are fastcc 2470// On X86_64 architecture with GOT-style position independent code only local 2471// (within module) calls are supported at the moment. 2472// To keep the stack aligned according to platform abi the function 2473// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2474// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2475// If a tail called function callee has more arguments than the caller the 2476// caller needs to make sure that there is room to move the RETADDR to. This is 2477// achieved by reserving an area the size of the argument delta right after the 2478// original REtADDR, but before the saved framepointer or the spilled registers 2479// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2480// stack layout: 2481// arg1 2482// arg2 2483// RETADDR 2484// [ new RETADDR 2485// move area ] 2486// (possible EBP) 2487// ESI 2488// EDI 2489// local1 .. 2490 2491/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2492/// for a 16 byte align requirement. 2493unsigned 2494X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2495 SelectionDAG& DAG) const { 2496 MachineFunction &MF = DAG.getMachineFunction(); 2497 const TargetMachine &TM = MF.getTarget(); 2498 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2499 unsigned StackAlignment = TFI.getStackAlignment(); 2500 uint64_t AlignMask = StackAlignment - 1; 2501 int64_t Offset = StackSize; 2502 uint64_t SlotSize = TD->getPointerSize(); 2503 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2504 // Number smaller than 12 so just add the difference. 2505 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2506 } else { 2507 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2508 Offset = ((~AlignMask) & Offset) + StackAlignment + 2509 (StackAlignment-SlotSize); 2510 } 2511 return Offset; 2512} 2513 2514/// MatchingStackOffset - Return true if the given stack call argument is 2515/// already available in the same position (relatively) of the caller's 2516/// incoming argument stack. 2517static 2518bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2519 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2520 const X86InstrInfo *TII) { 2521 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2522 int FI = INT_MAX; 2523 if (Arg.getOpcode() == ISD::CopyFromReg) { 2524 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2525 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2526 return false; 2527 MachineInstr *Def = MRI->getVRegDef(VR); 2528 if (!Def) 2529 return false; 2530 if (!Flags.isByVal()) { 2531 if (!TII->isLoadFromStackSlot(Def, FI)) 2532 return false; 2533 } else { 2534 unsigned Opcode = Def->getOpcode(); 2535 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2536 Def->getOperand(1).isFI()) { 2537 FI = Def->getOperand(1).getIndex(); 2538 Bytes = Flags.getByValSize(); 2539 } else 2540 return false; 2541 } 2542 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2543 if (Flags.isByVal()) 2544 // ByVal argument is passed in as a pointer but it's now being 2545 // dereferenced. e.g. 2546 // define @foo(%struct.X* %A) { 2547 // tail call @bar(%struct.X* byval %A) 2548 // } 2549 return false; 2550 SDValue Ptr = Ld->getBasePtr(); 2551 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2552 if (!FINode) 2553 return false; 2554 FI = FINode->getIndex(); 2555 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2556 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2557 FI = FINode->getIndex(); 2558 Bytes = Flags.getByValSize(); 2559 } else 2560 return false; 2561 2562 assert(FI != INT_MAX); 2563 if (!MFI->isFixedObjectIndex(FI)) 2564 return false; 2565 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2566} 2567 2568/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2569/// for tail call optimization. Targets which want to do tail call 2570/// optimization should implement this function. 2571bool 2572X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2573 CallingConv::ID CalleeCC, 2574 bool isVarArg, 2575 bool isCalleeStructRet, 2576 bool isCallerStructRet, 2577 const SmallVectorImpl<ISD::OutputArg> &Outs, 2578 const SmallVectorImpl<SDValue> &OutVals, 2579 const SmallVectorImpl<ISD::InputArg> &Ins, 2580 SelectionDAG& DAG) const { 2581 if (!IsTailCallConvention(CalleeCC) && 2582 CalleeCC != CallingConv::C) 2583 return false; 2584 2585 // If -tailcallopt is specified, make fastcc functions tail-callable. 2586 const MachineFunction &MF = DAG.getMachineFunction(); 2587 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2588 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2589 bool CCMatch = CallerCC == CalleeCC; 2590 2591 if (GuaranteedTailCallOpt) { 2592 if (IsTailCallConvention(CalleeCC) && CCMatch) 2593 return true; 2594 return false; 2595 } 2596 2597 // Look for obvious safe cases to perform tail call optimization that do not 2598 // require ABI changes. This is what gcc calls sibcall. 2599 2600 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2601 // emit a special epilogue. 2602 if (RegInfo->needsStackRealignment(MF)) 2603 return false; 2604 2605 // Also avoid sibcall optimization if either caller or callee uses struct 2606 // return semantics. 2607 if (isCalleeStructRet || isCallerStructRet) 2608 return false; 2609 2610 // An stdcall caller is expected to clean up its arguments; the callee 2611 // isn't going to do that. 2612 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2613 return false; 2614 2615 // Do not sibcall optimize vararg calls unless all arguments are passed via 2616 // registers. 2617 if (isVarArg && !Outs.empty()) { 2618 2619 // Optimizing for varargs on Win64 is unlikely to be safe without 2620 // additional testing. 2621 if (Subtarget->isTargetWin64()) 2622 return false; 2623 2624 SmallVector<CCValAssign, 16> ArgLocs; 2625 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2626 getTargetMachine(), ArgLocs, *DAG.getContext()); 2627 2628 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2629 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2630 if (!ArgLocs[i].isRegLoc()) 2631 return false; 2632 } 2633 2634 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2635 // Therefore if it's not used by the call it is not safe to optimize this into 2636 // a sibcall. 2637 bool Unused = false; 2638 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2639 if (!Ins[i].Used) { 2640 Unused = true; 2641 break; 2642 } 2643 } 2644 if (Unused) { 2645 SmallVector<CCValAssign, 16> RVLocs; 2646 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2647 getTargetMachine(), RVLocs, *DAG.getContext()); 2648 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2649 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2650 CCValAssign &VA = RVLocs[i]; 2651 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2652 return false; 2653 } 2654 } 2655 2656 // If the calling conventions do not match, then we'd better make sure the 2657 // results are returned in the same way as what the caller expects. 2658 if (!CCMatch) { 2659 SmallVector<CCValAssign, 16> RVLocs1; 2660 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2661 getTargetMachine(), RVLocs1, *DAG.getContext()); 2662 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2663 2664 SmallVector<CCValAssign, 16> RVLocs2; 2665 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2666 getTargetMachine(), RVLocs2, *DAG.getContext()); 2667 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2668 2669 if (RVLocs1.size() != RVLocs2.size()) 2670 return false; 2671 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2672 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2673 return false; 2674 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2675 return false; 2676 if (RVLocs1[i].isRegLoc()) { 2677 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2678 return false; 2679 } else { 2680 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2681 return false; 2682 } 2683 } 2684 } 2685 2686 // If the callee takes no arguments then go on to check the results of the 2687 // call. 2688 if (!Outs.empty()) { 2689 // Check if stack adjustment is needed. For now, do not do this if any 2690 // argument is passed on the stack. 2691 SmallVector<CCValAssign, 16> ArgLocs; 2692 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2693 getTargetMachine(), ArgLocs, *DAG.getContext()); 2694 2695 // Allocate shadow area for Win64 2696 if (Subtarget->isTargetWin64()) { 2697 CCInfo.AllocateStack(32, 8); 2698 } 2699 2700 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2701 if (CCInfo.getNextStackOffset()) { 2702 MachineFunction &MF = DAG.getMachineFunction(); 2703 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2704 return false; 2705 2706 // Check if the arguments are already laid out in the right way as 2707 // the caller's fixed stack objects. 2708 MachineFrameInfo *MFI = MF.getFrameInfo(); 2709 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2710 const X86InstrInfo *TII = 2711 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2712 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2713 CCValAssign &VA = ArgLocs[i]; 2714 SDValue Arg = OutVals[i]; 2715 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2716 if (VA.getLocInfo() == CCValAssign::Indirect) 2717 return false; 2718 if (!VA.isRegLoc()) { 2719 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2720 MFI, MRI, TII)) 2721 return false; 2722 } 2723 } 2724 } 2725 2726 // If the tailcall address may be in a register, then make sure it's 2727 // possible to register allocate for it. In 32-bit, the call address can 2728 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2729 // callee-saved registers are restored. These happen to be the same 2730 // registers used to pass 'inreg' arguments so watch out for those. 2731 if (!Subtarget->is64Bit() && 2732 !isa<GlobalAddressSDNode>(Callee) && 2733 !isa<ExternalSymbolSDNode>(Callee)) { 2734 unsigned NumInRegs = 0; 2735 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2736 CCValAssign &VA = ArgLocs[i]; 2737 if (!VA.isRegLoc()) 2738 continue; 2739 unsigned Reg = VA.getLocReg(); 2740 switch (Reg) { 2741 default: break; 2742 case X86::EAX: case X86::EDX: case X86::ECX: 2743 if (++NumInRegs == 3) 2744 return false; 2745 break; 2746 } 2747 } 2748 } 2749 } 2750 2751 return true; 2752} 2753 2754FastISel * 2755X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2756 return X86::createFastISel(funcInfo); 2757} 2758 2759 2760//===----------------------------------------------------------------------===// 2761// Other Lowering Hooks 2762//===----------------------------------------------------------------------===// 2763 2764static bool MayFoldLoad(SDValue Op) { 2765 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2766} 2767 2768static bool MayFoldIntoStore(SDValue Op) { 2769 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2770} 2771 2772static bool isTargetShuffle(unsigned Opcode) { 2773 switch(Opcode) { 2774 default: return false; 2775 case X86ISD::PSHUFD: 2776 case X86ISD::PSHUFHW: 2777 case X86ISD::PSHUFLW: 2778 case X86ISD::SHUFPD: 2779 case X86ISD::PALIGN: 2780 case X86ISD::SHUFPS: 2781 case X86ISD::MOVLHPS: 2782 case X86ISD::MOVLHPD: 2783 case X86ISD::MOVHLPS: 2784 case X86ISD::MOVLPS: 2785 case X86ISD::MOVLPD: 2786 case X86ISD::MOVSHDUP: 2787 case X86ISD::MOVSLDUP: 2788 case X86ISD::MOVDDUP: 2789 case X86ISD::MOVSS: 2790 case X86ISD::MOVSD: 2791 case X86ISD::UNPCKLPS: 2792 case X86ISD::UNPCKLPD: 2793 case X86ISD::VUNPCKLPSY: 2794 case X86ISD::VUNPCKLPDY: 2795 case X86ISD::PUNPCKLWD: 2796 case X86ISD::PUNPCKLBW: 2797 case X86ISD::PUNPCKLDQ: 2798 case X86ISD::PUNPCKLQDQ: 2799 case X86ISD::UNPCKHPS: 2800 case X86ISD::UNPCKHPD: 2801 case X86ISD::VUNPCKHPSY: 2802 case X86ISD::VUNPCKHPDY: 2803 case X86ISD::PUNPCKHWD: 2804 case X86ISD::PUNPCKHBW: 2805 case X86ISD::PUNPCKHDQ: 2806 case X86ISD::PUNPCKHQDQ: 2807 case X86ISD::VPERMILPS: 2808 case X86ISD::VPERMILPSY: 2809 case X86ISD::VPERMILPD: 2810 case X86ISD::VPERMILPDY: 2811 case X86ISD::VPERM2F128: 2812 return true; 2813 } 2814 return false; 2815} 2816 2817static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2818 SDValue V1, SelectionDAG &DAG) { 2819 switch(Opc) { 2820 default: llvm_unreachable("Unknown x86 shuffle node"); 2821 case X86ISD::MOVSHDUP: 2822 case X86ISD::MOVSLDUP: 2823 case X86ISD::MOVDDUP: 2824 return DAG.getNode(Opc, dl, VT, V1); 2825 } 2826 2827 return SDValue(); 2828} 2829 2830static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2831 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2832 switch(Opc) { 2833 default: llvm_unreachable("Unknown x86 shuffle node"); 2834 case X86ISD::PSHUFD: 2835 case X86ISD::PSHUFHW: 2836 case X86ISD::PSHUFLW: 2837 case X86ISD::VPERMILPS: 2838 case X86ISD::VPERMILPSY: 2839 case X86ISD::VPERMILPD: 2840 case X86ISD::VPERMILPDY: 2841 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2842 } 2843 2844 return SDValue(); 2845} 2846 2847static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2848 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2849 switch(Opc) { 2850 default: llvm_unreachable("Unknown x86 shuffle node"); 2851 case X86ISD::PALIGN: 2852 case X86ISD::SHUFPD: 2853 case X86ISD::SHUFPS: 2854 case X86ISD::VPERM2F128: 2855 return DAG.getNode(Opc, dl, VT, V1, V2, 2856 DAG.getConstant(TargetMask, MVT::i8)); 2857 } 2858 return SDValue(); 2859} 2860 2861static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2862 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2863 switch(Opc) { 2864 default: llvm_unreachable("Unknown x86 shuffle node"); 2865 case X86ISD::MOVLHPS: 2866 case X86ISD::MOVLHPD: 2867 case X86ISD::MOVHLPS: 2868 case X86ISD::MOVLPS: 2869 case X86ISD::MOVLPD: 2870 case X86ISD::MOVSS: 2871 case X86ISD::MOVSD: 2872 case X86ISD::UNPCKLPS: 2873 case X86ISD::UNPCKLPD: 2874 case X86ISD::VUNPCKLPSY: 2875 case X86ISD::VUNPCKLPDY: 2876 case X86ISD::PUNPCKLWD: 2877 case X86ISD::PUNPCKLBW: 2878 case X86ISD::PUNPCKLDQ: 2879 case X86ISD::PUNPCKLQDQ: 2880 case X86ISD::UNPCKHPS: 2881 case X86ISD::UNPCKHPD: 2882 case X86ISD::VUNPCKHPSY: 2883 case X86ISD::VUNPCKHPDY: 2884 case X86ISD::PUNPCKHWD: 2885 case X86ISD::PUNPCKHBW: 2886 case X86ISD::PUNPCKHDQ: 2887 case X86ISD::PUNPCKHQDQ: 2888 return DAG.getNode(Opc, dl, VT, V1, V2); 2889 } 2890 return SDValue(); 2891} 2892 2893SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2894 MachineFunction &MF = DAG.getMachineFunction(); 2895 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2896 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2897 2898 if (ReturnAddrIndex == 0) { 2899 // Set up a frame object for the return address. 2900 uint64_t SlotSize = TD->getPointerSize(); 2901 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2902 false); 2903 FuncInfo->setRAIndex(ReturnAddrIndex); 2904 } 2905 2906 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2907} 2908 2909 2910bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2911 bool hasSymbolicDisplacement) { 2912 // Offset should fit into 32 bit immediate field. 2913 if (!isInt<32>(Offset)) 2914 return false; 2915 2916 // If we don't have a symbolic displacement - we don't have any extra 2917 // restrictions. 2918 if (!hasSymbolicDisplacement) 2919 return true; 2920 2921 // FIXME: Some tweaks might be needed for medium code model. 2922 if (M != CodeModel::Small && M != CodeModel::Kernel) 2923 return false; 2924 2925 // For small code model we assume that latest object is 16MB before end of 31 2926 // bits boundary. We may also accept pretty large negative constants knowing 2927 // that all objects are in the positive half of address space. 2928 if (M == CodeModel::Small && Offset < 16*1024*1024) 2929 return true; 2930 2931 // For kernel code model we know that all object resist in the negative half 2932 // of 32bits address space. We may not accept negative offsets, since they may 2933 // be just off and we may accept pretty large positive ones. 2934 if (M == CodeModel::Kernel && Offset > 0) 2935 return true; 2936 2937 return false; 2938} 2939 2940/// isCalleePop - Determines whether the callee is required to pop its 2941/// own arguments. Callee pop is necessary to support tail calls. 2942bool X86::isCalleePop(CallingConv::ID CallingConv, 2943 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2944 if (IsVarArg) 2945 return false; 2946 2947 switch (CallingConv) { 2948 default: 2949 return false; 2950 case CallingConv::X86_StdCall: 2951 return !is64Bit; 2952 case CallingConv::X86_FastCall: 2953 return !is64Bit; 2954 case CallingConv::X86_ThisCall: 2955 return !is64Bit; 2956 case CallingConv::Fast: 2957 return TailCallOpt; 2958 case CallingConv::GHC: 2959 return TailCallOpt; 2960 } 2961} 2962 2963/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2964/// specific condition code, returning the condition code and the LHS/RHS of the 2965/// comparison to make. 2966static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2967 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2968 if (!isFP) { 2969 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2970 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2971 // X > -1 -> X == 0, jump !sign. 2972 RHS = DAG.getConstant(0, RHS.getValueType()); 2973 return X86::COND_NS; 2974 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2975 // X < 0 -> X == 0, jump on sign. 2976 return X86::COND_S; 2977 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2978 // X < 1 -> X <= 0 2979 RHS = DAG.getConstant(0, RHS.getValueType()); 2980 return X86::COND_LE; 2981 } 2982 } 2983 2984 switch (SetCCOpcode) { 2985 default: llvm_unreachable("Invalid integer condition!"); 2986 case ISD::SETEQ: return X86::COND_E; 2987 case ISD::SETGT: return X86::COND_G; 2988 case ISD::SETGE: return X86::COND_GE; 2989 case ISD::SETLT: return X86::COND_L; 2990 case ISD::SETLE: return X86::COND_LE; 2991 case ISD::SETNE: return X86::COND_NE; 2992 case ISD::SETULT: return X86::COND_B; 2993 case ISD::SETUGT: return X86::COND_A; 2994 case ISD::SETULE: return X86::COND_BE; 2995 case ISD::SETUGE: return X86::COND_AE; 2996 } 2997 } 2998 2999 // First determine if it is required or is profitable to flip the operands. 3000 3001 // If LHS is a foldable load, but RHS is not, flip the condition. 3002 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3003 !ISD::isNON_EXTLoad(RHS.getNode())) { 3004 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3005 std::swap(LHS, RHS); 3006 } 3007 3008 switch (SetCCOpcode) { 3009 default: break; 3010 case ISD::SETOLT: 3011 case ISD::SETOLE: 3012 case ISD::SETUGT: 3013 case ISD::SETUGE: 3014 std::swap(LHS, RHS); 3015 break; 3016 } 3017 3018 // On a floating point condition, the flags are set as follows: 3019 // ZF PF CF op 3020 // 0 | 0 | 0 | X > Y 3021 // 0 | 0 | 1 | X < Y 3022 // 1 | 0 | 0 | X == Y 3023 // 1 | 1 | 1 | unordered 3024 switch (SetCCOpcode) { 3025 default: llvm_unreachable("Condcode should be pre-legalized away"); 3026 case ISD::SETUEQ: 3027 case ISD::SETEQ: return X86::COND_E; 3028 case ISD::SETOLT: // flipped 3029 case ISD::SETOGT: 3030 case ISD::SETGT: return X86::COND_A; 3031 case ISD::SETOLE: // flipped 3032 case ISD::SETOGE: 3033 case ISD::SETGE: return X86::COND_AE; 3034 case ISD::SETUGT: // flipped 3035 case ISD::SETULT: 3036 case ISD::SETLT: return X86::COND_B; 3037 case ISD::SETUGE: // flipped 3038 case ISD::SETULE: 3039 case ISD::SETLE: return X86::COND_BE; 3040 case ISD::SETONE: 3041 case ISD::SETNE: return X86::COND_NE; 3042 case ISD::SETUO: return X86::COND_P; 3043 case ISD::SETO: return X86::COND_NP; 3044 case ISD::SETOEQ: 3045 case ISD::SETUNE: return X86::COND_INVALID; 3046 } 3047} 3048 3049/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3050/// code. Current x86 isa includes the following FP cmov instructions: 3051/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3052static bool hasFPCMov(unsigned X86CC) { 3053 switch (X86CC) { 3054 default: 3055 return false; 3056 case X86::COND_B: 3057 case X86::COND_BE: 3058 case X86::COND_E: 3059 case X86::COND_P: 3060 case X86::COND_A: 3061 case X86::COND_AE: 3062 case X86::COND_NE: 3063 case X86::COND_NP: 3064 return true; 3065 } 3066} 3067 3068/// isFPImmLegal - Returns true if the target can instruction select the 3069/// specified FP immediate natively. If false, the legalizer will 3070/// materialize the FP immediate as a load from a constant pool. 3071bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3072 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3073 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3074 return true; 3075 } 3076 return false; 3077} 3078 3079/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3080/// the specified range (L, H]. 3081static bool isUndefOrInRange(int Val, int Low, int Hi) { 3082 return (Val < 0) || (Val >= Low && Val < Hi); 3083} 3084 3085/// isUndefOrInRange - Return true if every element in Mask, begining 3086/// from position Pos and ending in Pos+Size, falls within the specified 3087/// range (L, L+Pos]. or is undef. 3088static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3089 int Pos, int Size, int Low, int Hi) { 3090 for (int i = Pos, e = Pos+Size; i != e; ++i) 3091 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3092 return false; 3093 return true; 3094} 3095 3096/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3097/// specified value. 3098static bool isUndefOrEqual(int Val, int CmpVal) { 3099 if (Val < 0 || Val == CmpVal) 3100 return true; 3101 return false; 3102} 3103 3104/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3105/// from position Pos and ending in Pos+Size, falls within the specified 3106/// sequential range (L, L+Pos]. or is undef. 3107static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3108 int Pos, int Size, int Low) { 3109 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3110 if (!isUndefOrEqual(Mask[i], Low)) 3111 return false; 3112 return true; 3113} 3114 3115/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3116/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3117/// the second operand. 3118static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3119 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3120 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3121 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3122 return (Mask[0] < 2 && Mask[1] < 2); 3123 return false; 3124} 3125 3126bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3127 SmallVector<int, 8> M; 3128 N->getMask(M); 3129 return ::isPSHUFDMask(M, N->getValueType(0)); 3130} 3131 3132/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3133/// is suitable for input to PSHUFHW. 3134static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3135 if (VT != MVT::v8i16) 3136 return false; 3137 3138 // Lower quadword copied in order or undef. 3139 for (int i = 0; i != 4; ++i) 3140 if (Mask[i] >= 0 && Mask[i] != i) 3141 return false; 3142 3143 // Upper quadword shuffled. 3144 for (int i = 4; i != 8; ++i) 3145 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3146 return false; 3147 3148 return true; 3149} 3150 3151bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3152 SmallVector<int, 8> M; 3153 N->getMask(M); 3154 return ::isPSHUFHWMask(M, N->getValueType(0)); 3155} 3156 3157/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3158/// is suitable for input to PSHUFLW. 3159static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3160 if (VT != MVT::v8i16) 3161 return false; 3162 3163 // Upper quadword copied in order. 3164 for (int i = 4; i != 8; ++i) 3165 if (Mask[i] >= 0 && Mask[i] != i) 3166 return false; 3167 3168 // Lower quadword shuffled. 3169 for (int i = 0; i != 4; ++i) 3170 if (Mask[i] >= 4) 3171 return false; 3172 3173 return true; 3174} 3175 3176bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3177 SmallVector<int, 8> M; 3178 N->getMask(M); 3179 return ::isPSHUFLWMask(M, N->getValueType(0)); 3180} 3181 3182/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3183/// is suitable for input to PALIGNR. 3184static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3185 bool hasSSSE3OrAVX) { 3186 int i, e = VT.getVectorNumElements(); 3187 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3188 return false; 3189 3190 // Do not handle v2i64 / v2f64 shuffles with palignr. 3191 if (e < 4 || !hasSSSE3OrAVX) 3192 return false; 3193 3194 for (i = 0; i != e; ++i) 3195 if (Mask[i] >= 0) 3196 break; 3197 3198 // All undef, not a palignr. 3199 if (i == e) 3200 return false; 3201 3202 // Make sure we're shifting in the right direction. 3203 if (Mask[i] <= i) 3204 return false; 3205 3206 int s = Mask[i] - i; 3207 3208 // Check the rest of the elements to see if they are consecutive. 3209 for (++i; i != e; ++i) { 3210 int m = Mask[i]; 3211 if (m >= 0 && m != s+i) 3212 return false; 3213 } 3214 return true; 3215} 3216 3217/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand 3218/// specifies a shuffle of elements that is suitable for input to 256-bit 3219/// VSHUFPSY. 3220static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3221 const X86Subtarget *Subtarget) { 3222 int NumElems = VT.getVectorNumElements(); 3223 3224 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3225 return false; 3226 3227 if (NumElems != 8) 3228 return false; 3229 3230 // VSHUFPSY divides the resulting vector into 4 chunks. 3231 // The sources are also splitted into 4 chunks, and each destination 3232 // chunk must come from a different source chunk. 3233 // 3234 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3235 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3236 // 3237 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3238 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3239 // 3240 int QuarterSize = NumElems/4; 3241 int HalfSize = QuarterSize*2; 3242 for (int i = 0; i < QuarterSize; ++i) 3243 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3244 return false; 3245 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3246 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3247 return false; 3248 3249 // The mask of the second half must be the same as the first but with 3250 // the appropriate offsets. This works in the same way as VPERMILPS 3251 // works with masks. 3252 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { 3253 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3254 return false; 3255 int FstHalfIdx = i-HalfSize; 3256 if (Mask[FstHalfIdx] < 0) 3257 continue; 3258 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3259 return false; 3260 } 3261 for (int i = QuarterSize*3; i < NumElems; ++i) { 3262 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3263 return false; 3264 int FstHalfIdx = i-HalfSize; 3265 if (Mask[FstHalfIdx] < 0) 3266 continue; 3267 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3268 return false; 3269 3270 } 3271 3272 return true; 3273} 3274 3275/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle 3276/// the specified VECTOR_MASK mask with VSHUFPSY instruction. 3277static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { 3278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3279 EVT VT = SVOp->getValueType(0); 3280 int NumElems = VT.getVectorNumElements(); 3281 3282 assert(NumElems == 8 && VT.getSizeInBits() == 256 && 3283 "Only supports v8i32 and v8f32 types"); 3284 3285 int HalfSize = NumElems/2; 3286 unsigned Mask = 0; 3287 for (int i = 0; i != NumElems ; ++i) { 3288 if (SVOp->getMaskElt(i) < 0) 3289 continue; 3290 // The mask of the first half must be equal to the second one. 3291 unsigned Shamt = (i%HalfSize)*2; 3292 unsigned Elt = SVOp->getMaskElt(i) % HalfSize; 3293 Mask |= Elt << Shamt; 3294 } 3295 3296 return Mask; 3297} 3298 3299/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand 3300/// specifies a shuffle of elements that is suitable for input to 256-bit 3301/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS 3302/// version and the mask of the second half isn't binded with the first 3303/// one. 3304static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3305 const X86Subtarget *Subtarget) { 3306 int NumElems = VT.getVectorNumElements(); 3307 3308 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3309 return false; 3310 3311 if (NumElems != 4) 3312 return false; 3313 3314 // VSHUFPSY divides the resulting vector into 4 chunks. 3315 // The sources are also splitted into 4 chunks, and each destination 3316 // chunk must come from a different source chunk. 3317 // 3318 // SRC1 => X3 X2 X1 X0 3319 // SRC2 => Y3 Y2 Y1 Y0 3320 // 3321 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 3322 // 3323 int QuarterSize = NumElems/4; 3324 int HalfSize = QuarterSize*2; 3325 for (int i = 0; i < QuarterSize; ++i) 3326 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3327 return false; 3328 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3329 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3330 return false; 3331 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) 3332 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3333 return false; 3334 for (int i = QuarterSize*3; i < NumElems; ++i) 3335 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3336 return false; 3337 3338 return true; 3339} 3340 3341/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle 3342/// the specified VECTOR_MASK mask with VSHUFPDY instruction. 3343static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { 3344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3345 EVT VT = SVOp->getValueType(0); 3346 int NumElems = VT.getVectorNumElements(); 3347 3348 assert(NumElems == 4 && VT.getSizeInBits() == 256 && 3349 "Only supports v4i64 and v4f64 types"); 3350 3351 int HalfSize = NumElems/2; 3352 unsigned Mask = 0; 3353 for (int i = 0; i != NumElems ; ++i) { 3354 if (SVOp->getMaskElt(i) < 0) 3355 continue; 3356 int Elt = SVOp->getMaskElt(i) % HalfSize; 3357 Mask |= Elt << i; 3358 } 3359 3360 return Mask; 3361} 3362 3363/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3364/// specifies a shuffle of elements that is suitable for input to 128-bit 3365/// SHUFPS and SHUFPD. 3366static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3367 int NumElems = VT.getVectorNumElements(); 3368 3369 if (VT.getSizeInBits() != 128) 3370 return false; 3371 3372 if (NumElems != 2 && NumElems != 4) 3373 return false; 3374 3375 int Half = NumElems / 2; 3376 for (int i = 0; i < Half; ++i) 3377 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3378 return false; 3379 for (int i = Half; i < NumElems; ++i) 3380 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3381 return false; 3382 3383 return true; 3384} 3385 3386bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3387 SmallVector<int, 8> M; 3388 N->getMask(M); 3389 return ::isSHUFPMask(M, N->getValueType(0)); 3390} 3391 3392/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3393/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3394/// half elements to come from vector 1 (which would equal the dest.) and 3395/// the upper half to come from vector 2. 3396static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3397 int NumElems = VT.getVectorNumElements(); 3398 3399 if (NumElems != 2 && NumElems != 4) 3400 return false; 3401 3402 int Half = NumElems / 2; 3403 for (int i = 0; i < Half; ++i) 3404 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3405 return false; 3406 for (int i = Half; i < NumElems; ++i) 3407 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3408 return false; 3409 return true; 3410} 3411 3412static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3413 SmallVector<int, 8> M; 3414 N->getMask(M); 3415 return isCommutedSHUFPMask(M, N->getValueType(0)); 3416} 3417 3418/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3419/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3420bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3421 EVT VT = N->getValueType(0); 3422 unsigned NumElems = VT.getVectorNumElements(); 3423 3424 if (VT.getSizeInBits() != 128) 3425 return false; 3426 3427 if (NumElems != 4) 3428 return false; 3429 3430 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3431 return isUndefOrEqual(N->getMaskElt(0), 6) && 3432 isUndefOrEqual(N->getMaskElt(1), 7) && 3433 isUndefOrEqual(N->getMaskElt(2), 2) && 3434 isUndefOrEqual(N->getMaskElt(3), 3); 3435} 3436 3437/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3438/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3439/// <2, 3, 2, 3> 3440bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3441 EVT VT = N->getValueType(0); 3442 unsigned NumElems = VT.getVectorNumElements(); 3443 3444 if (VT.getSizeInBits() != 128) 3445 return false; 3446 3447 if (NumElems != 4) 3448 return false; 3449 3450 return isUndefOrEqual(N->getMaskElt(0), 2) && 3451 isUndefOrEqual(N->getMaskElt(1), 3) && 3452 isUndefOrEqual(N->getMaskElt(2), 2) && 3453 isUndefOrEqual(N->getMaskElt(3), 3); 3454} 3455 3456/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3457/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3458bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3459 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3460 3461 if (NumElems != 2 && NumElems != 4) 3462 return false; 3463 3464 for (unsigned i = 0; i < NumElems/2; ++i) 3465 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3466 return false; 3467 3468 for (unsigned i = NumElems/2; i < NumElems; ++i) 3469 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3470 return false; 3471 3472 return true; 3473} 3474 3475/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3476/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3477bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3478 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3479 3480 if ((NumElems != 2 && NumElems != 4) 3481 || N->getValueType(0).getSizeInBits() > 128) 3482 return false; 3483 3484 for (unsigned i = 0; i < NumElems/2; ++i) 3485 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3486 return false; 3487 3488 for (unsigned i = 0; i < NumElems/2; ++i) 3489 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3490 return false; 3491 3492 return true; 3493} 3494 3495/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3496/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3497static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3498 bool V2IsSplat = false) { 3499 int NumElts = VT.getVectorNumElements(); 3500 3501 assert((VT.is128BitVector() || VT.is256BitVector()) && 3502 "Unsupported vector type for unpckh"); 3503 3504 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3505 return false; 3506 3507 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3508 // independently on 128-bit lanes. 3509 unsigned NumLanes = VT.getSizeInBits()/128; 3510 unsigned NumLaneElts = NumElts/NumLanes; 3511 3512 unsigned Start = 0; 3513 unsigned End = NumLaneElts; 3514 for (unsigned s = 0; s < NumLanes; ++s) { 3515 for (unsigned i = Start, j = s * NumLaneElts; 3516 i != End; 3517 i += 2, ++j) { 3518 int BitI = Mask[i]; 3519 int BitI1 = Mask[i+1]; 3520 if (!isUndefOrEqual(BitI, j)) 3521 return false; 3522 if (V2IsSplat) { 3523 if (!isUndefOrEqual(BitI1, NumElts)) 3524 return false; 3525 } else { 3526 if (!isUndefOrEqual(BitI1, j + NumElts)) 3527 return false; 3528 } 3529 } 3530 // Process the next 128 bits. 3531 Start += NumLaneElts; 3532 End += NumLaneElts; 3533 } 3534 3535 return true; 3536} 3537 3538bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3539 SmallVector<int, 8> M; 3540 N->getMask(M); 3541 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3542} 3543 3544/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3545/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3546static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3547 bool V2IsSplat = false) { 3548 int NumElts = VT.getVectorNumElements(); 3549 3550 assert((VT.is128BitVector() || VT.is256BitVector()) && 3551 "Unsupported vector type for unpckh"); 3552 3553 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3554 return false; 3555 3556 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3557 // independently on 128-bit lanes. 3558 unsigned NumLanes = VT.getSizeInBits()/128; 3559 unsigned NumLaneElts = NumElts/NumLanes; 3560 3561 unsigned Start = 0; 3562 unsigned End = NumLaneElts; 3563 for (unsigned l = 0; l != NumLanes; ++l) { 3564 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3565 i != End; i += 2, ++j) { 3566 int BitI = Mask[i]; 3567 int BitI1 = Mask[i+1]; 3568 if (!isUndefOrEqual(BitI, j)) 3569 return false; 3570 if (V2IsSplat) { 3571 if (isUndefOrEqual(BitI1, NumElts)) 3572 return false; 3573 } else { 3574 if (!isUndefOrEqual(BitI1, j+NumElts)) 3575 return false; 3576 } 3577 } 3578 // Process the next 128 bits. 3579 Start += NumLaneElts; 3580 End += NumLaneElts; 3581 } 3582 return true; 3583} 3584 3585bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3586 SmallVector<int, 8> M; 3587 N->getMask(M); 3588 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3589} 3590 3591/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3592/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3593/// <0, 0, 1, 1> 3594static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3595 int NumElems = VT.getVectorNumElements(); 3596 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3597 return false; 3598 3599 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3600 // FIXME: Need a better way to get rid of this, there's no latency difference 3601 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3602 // the former later. We should also remove the "_undef" special mask. 3603 if (NumElems == 4 && VT.getSizeInBits() == 256) 3604 return false; 3605 3606 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3607 // independently on 128-bit lanes. 3608 unsigned NumLanes = VT.getSizeInBits() / 128; 3609 unsigned NumLaneElts = NumElems / NumLanes; 3610 3611 for (unsigned s = 0; s < NumLanes; ++s) { 3612 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3613 i != NumLaneElts * (s + 1); 3614 i += 2, ++j) { 3615 int BitI = Mask[i]; 3616 int BitI1 = Mask[i+1]; 3617 3618 if (!isUndefOrEqual(BitI, j)) 3619 return false; 3620 if (!isUndefOrEqual(BitI1, j)) 3621 return false; 3622 } 3623 } 3624 3625 return true; 3626} 3627 3628bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3629 SmallVector<int, 8> M; 3630 N->getMask(M); 3631 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3632} 3633 3634/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3635/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3636/// <2, 2, 3, 3> 3637static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3638 int NumElems = VT.getVectorNumElements(); 3639 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3640 return false; 3641 3642 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3643 int BitI = Mask[i]; 3644 int BitI1 = Mask[i+1]; 3645 if (!isUndefOrEqual(BitI, j)) 3646 return false; 3647 if (!isUndefOrEqual(BitI1, j)) 3648 return false; 3649 } 3650 return true; 3651} 3652 3653bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3654 SmallVector<int, 8> M; 3655 N->getMask(M); 3656 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3657} 3658 3659/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3660/// specifies a shuffle of elements that is suitable for input to MOVSS, 3661/// MOVSD, and MOVD, i.e. setting the lowest element. 3662static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3663 if (VT.getVectorElementType().getSizeInBits() < 32) 3664 return false; 3665 3666 int NumElts = VT.getVectorNumElements(); 3667 3668 if (!isUndefOrEqual(Mask[0], NumElts)) 3669 return false; 3670 3671 for (int i = 1; i < NumElts; ++i) 3672 if (!isUndefOrEqual(Mask[i], i)) 3673 return false; 3674 3675 return true; 3676} 3677 3678bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3679 SmallVector<int, 8> M; 3680 N->getMask(M); 3681 return ::isMOVLMask(M, N->getValueType(0)); 3682} 3683 3684/// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered 3685/// as permutations between 128-bit chunks or halves. As an example: this 3686/// shuffle bellow: 3687/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3688/// The first half comes from the second half of V1 and the second half from the 3689/// the second half of V2. 3690static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3691 const X86Subtarget *Subtarget) { 3692 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3693 return false; 3694 3695 // The shuffle result is divided into half A and half B. In total the two 3696 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3697 // B must come from C, D, E or F. 3698 int HalfSize = VT.getVectorNumElements()/2; 3699 bool MatchA = false, MatchB = false; 3700 3701 // Check if A comes from one of C, D, E, F. 3702 for (int Half = 0; Half < 4; ++Half) { 3703 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3704 MatchA = true; 3705 break; 3706 } 3707 } 3708 3709 // Check if B comes from one of C, D, E, F. 3710 for (int Half = 0; Half < 4; ++Half) { 3711 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3712 MatchB = true; 3713 break; 3714 } 3715 } 3716 3717 return MatchA && MatchB; 3718} 3719 3720/// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle 3721/// the specified VECTOR_MASK mask with VPERM2F128 instructions. 3722static unsigned getShuffleVPERM2F128Immediate(SDNode *N) { 3723 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3724 EVT VT = SVOp->getValueType(0); 3725 3726 int HalfSize = VT.getVectorNumElements()/2; 3727 3728 int FstHalf = 0, SndHalf = 0; 3729 for (int i = 0; i < HalfSize; ++i) { 3730 if (SVOp->getMaskElt(i) > 0) { 3731 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3732 break; 3733 } 3734 } 3735 for (int i = HalfSize; i < HalfSize*2; ++i) { 3736 if (SVOp->getMaskElt(i) > 0) { 3737 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3738 break; 3739 } 3740 } 3741 3742 return (FstHalf | (SndHalf << 4)); 3743} 3744 3745/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3746/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3747/// Note that VPERMIL mask matching is different depending whether theunderlying 3748/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3749/// to the same elements of the low, but to the higher half of the source. 3750/// In VPERMILPD the two lanes could be shuffled independently of each other 3751/// with the same restriction that lanes can't be crossed. 3752static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3753 const X86Subtarget *Subtarget) { 3754 int NumElts = VT.getVectorNumElements(); 3755 int NumLanes = VT.getSizeInBits()/128; 3756 3757 if (!Subtarget->hasAVX()) 3758 return false; 3759 3760 // Only match 256-bit with 64-bit types 3761 if (VT.getSizeInBits() != 256 || NumElts != 4) 3762 return false; 3763 3764 // The mask on the high lane is independent of the low. Both can match 3765 // any element in inside its own lane, but can't cross. 3766 int LaneSize = NumElts/NumLanes; 3767 for (int l = 0; l < NumLanes; ++l) 3768 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3769 int LaneStart = l*LaneSize; 3770 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3771 return false; 3772 } 3773 3774 return true; 3775} 3776 3777/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3778/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3779/// Note that VPERMIL mask matching is different depending whether theunderlying 3780/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3781/// to the same elements of the low, but to the higher half of the source. 3782/// In VPERMILPD the two lanes could be shuffled independently of each other 3783/// with the same restriction that lanes can't be crossed. 3784static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3785 const X86Subtarget *Subtarget) { 3786 unsigned NumElts = VT.getVectorNumElements(); 3787 unsigned NumLanes = VT.getSizeInBits()/128; 3788 3789 if (!Subtarget->hasAVX()) 3790 return false; 3791 3792 // Only match 256-bit with 32-bit types 3793 if (VT.getSizeInBits() != 256 || NumElts != 8) 3794 return false; 3795 3796 // The mask on the high lane should be the same as the low. Actually, 3797 // they can differ if any of the corresponding index in a lane is undef 3798 // and the other stays in range. 3799 int LaneSize = NumElts/NumLanes; 3800 for (int i = 0; i < LaneSize; ++i) { 3801 int HighElt = i+LaneSize; 3802 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3803 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3804 3805 if (!HighValid || !LowValid) 3806 return false; 3807 if (Mask[i] < 0 || Mask[HighElt] < 0) 3808 continue; 3809 if (Mask[HighElt]-Mask[i] != LaneSize) 3810 return false; 3811 } 3812 3813 return true; 3814} 3815 3816/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3817/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3818static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3820 EVT VT = SVOp->getValueType(0); 3821 3822 int NumElts = VT.getVectorNumElements(); 3823 int NumLanes = VT.getSizeInBits()/128; 3824 int LaneSize = NumElts/NumLanes; 3825 3826 // Although the mask is equal for both lanes do it twice to get the cases 3827 // where a mask will match because the same mask element is undef on the 3828 // first half but valid on the second. This would get pathological cases 3829 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3830 unsigned Mask = 0; 3831 for (int l = 0; l < NumLanes; ++l) { 3832 for (int i = 0; i < LaneSize; ++i) { 3833 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3834 if (MaskElt < 0) 3835 continue; 3836 if (MaskElt >= LaneSize) 3837 MaskElt -= LaneSize; 3838 Mask |= MaskElt << (i*2); 3839 } 3840 } 3841 3842 return Mask; 3843} 3844 3845/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3846/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3847static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3849 EVT VT = SVOp->getValueType(0); 3850 3851 int NumElts = VT.getVectorNumElements(); 3852 int NumLanes = VT.getSizeInBits()/128; 3853 3854 unsigned Mask = 0; 3855 int LaneSize = NumElts/NumLanes; 3856 for (int l = 0; l < NumLanes; ++l) 3857 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3858 int MaskElt = SVOp->getMaskElt(i); 3859 if (MaskElt < 0) 3860 continue; 3861 Mask |= (MaskElt-l*LaneSize) << i; 3862 } 3863 3864 return Mask; 3865} 3866 3867/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3868/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3869/// element of vector 2 and the other elements to come from vector 1 in order. 3870static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3871 bool V2IsSplat = false, bool V2IsUndef = false) { 3872 int NumOps = VT.getVectorNumElements(); 3873 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3874 return false; 3875 3876 if (!isUndefOrEqual(Mask[0], 0)) 3877 return false; 3878 3879 for (int i = 1; i < NumOps; ++i) 3880 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3881 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3882 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3883 return false; 3884 3885 return true; 3886} 3887 3888static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3889 bool V2IsUndef = false) { 3890 SmallVector<int, 8> M; 3891 N->getMask(M); 3892 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3893} 3894 3895/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3896/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3897/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3898bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3899 const X86Subtarget *Subtarget) { 3900 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3901 return false; 3902 3903 // The second vector must be undef 3904 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3905 return false; 3906 3907 EVT VT = N->getValueType(0); 3908 unsigned NumElems = VT.getVectorNumElements(); 3909 3910 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3911 (VT.getSizeInBits() == 256 && NumElems != 8)) 3912 return false; 3913 3914 // "i+1" is the value the indexed mask element must have 3915 for (unsigned i = 0; i < NumElems; i += 2) 3916 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3917 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3918 return false; 3919 3920 return true; 3921} 3922 3923/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3924/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3925/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3926bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3927 const X86Subtarget *Subtarget) { 3928 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3929 return false; 3930 3931 // The second vector must be undef 3932 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3933 return false; 3934 3935 EVT VT = N->getValueType(0); 3936 unsigned NumElems = VT.getVectorNumElements(); 3937 3938 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3939 (VT.getSizeInBits() == 256 && NumElems != 8)) 3940 return false; 3941 3942 // "i" is the value the indexed mask element must have 3943 for (unsigned i = 0; i < NumElems; i += 2) 3944 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3945 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3946 return false; 3947 3948 return true; 3949} 3950 3951/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3952/// specifies a shuffle of elements that is suitable for input to 256-bit 3953/// version of MOVDDUP. 3954static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, 3955 const X86Subtarget *Subtarget) { 3956 EVT VT = N->getValueType(0); 3957 int NumElts = VT.getVectorNumElements(); 3958 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; 3959 3960 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || 3961 !V2IsUndef || NumElts != 4) 3962 return false; 3963 3964 for (int i = 0; i != NumElts/2; ++i) 3965 if (!isUndefOrEqual(N->getMaskElt(i), 0)) 3966 return false; 3967 for (int i = NumElts/2; i != NumElts; ++i) 3968 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) 3969 return false; 3970 return true; 3971} 3972 3973/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3974/// specifies a shuffle of elements that is suitable for input to 128-bit 3975/// version of MOVDDUP. 3976bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3977 EVT VT = N->getValueType(0); 3978 3979 if (VT.getSizeInBits() != 128) 3980 return false; 3981 3982 int e = VT.getVectorNumElements() / 2; 3983 for (int i = 0; i < e; ++i) 3984 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3985 return false; 3986 for (int i = 0; i < e; ++i) 3987 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3988 return false; 3989 return true; 3990} 3991 3992/// isVEXTRACTF128Index - Return true if the specified 3993/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3994/// suitable for input to VEXTRACTF128. 3995bool X86::isVEXTRACTF128Index(SDNode *N) { 3996 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3997 return false; 3998 3999 // The index should be aligned on a 128-bit boundary. 4000 uint64_t Index = 4001 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4002 4003 unsigned VL = N->getValueType(0).getVectorNumElements(); 4004 unsigned VBits = N->getValueType(0).getSizeInBits(); 4005 unsigned ElSize = VBits / VL; 4006 bool Result = (Index * ElSize) % 128 == 0; 4007 4008 return Result; 4009} 4010 4011/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4012/// operand specifies a subvector insert that is suitable for input to 4013/// VINSERTF128. 4014bool X86::isVINSERTF128Index(SDNode *N) { 4015 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4016 return false; 4017 4018 // The index should be aligned on a 128-bit boundary. 4019 uint64_t Index = 4020 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4021 4022 unsigned VL = N->getValueType(0).getVectorNumElements(); 4023 unsigned VBits = N->getValueType(0).getSizeInBits(); 4024 unsigned ElSize = VBits / VL; 4025 bool Result = (Index * ElSize) % 128 == 0; 4026 4027 return Result; 4028} 4029 4030/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4031/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4032unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 4033 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4034 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 4035 4036 unsigned Shift = (NumOperands == 4) ? 2 : 1; 4037 unsigned Mask = 0; 4038 for (int i = 0; i < NumOperands; ++i) { 4039 int Val = SVOp->getMaskElt(NumOperands-i-1); 4040 if (Val < 0) Val = 0; 4041 if (Val >= NumOperands) Val -= NumOperands; 4042 Mask |= Val; 4043 if (i != NumOperands - 1) 4044 Mask <<= Shift; 4045 } 4046 return Mask; 4047} 4048 4049/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4050/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4051unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 4052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4053 unsigned Mask = 0; 4054 // 8 nodes, but we only care about the last 4. 4055 for (unsigned i = 7; i >= 4; --i) { 4056 int Val = SVOp->getMaskElt(i); 4057 if (Val >= 0) 4058 Mask |= (Val - 4); 4059 if (i != 4) 4060 Mask <<= 2; 4061 } 4062 return Mask; 4063} 4064 4065/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4066/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4067unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4069 unsigned Mask = 0; 4070 // 8 nodes, but we only care about the first 4. 4071 for (int i = 3; i >= 0; --i) { 4072 int Val = SVOp->getMaskElt(i); 4073 if (Val >= 0) 4074 Mask |= Val; 4075 if (i != 0) 4076 Mask <<= 2; 4077 } 4078 return Mask; 4079} 4080 4081/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4082/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4083unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 4084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4085 EVT VVT = N->getValueType(0); 4086 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 4087 int Val = 0; 4088 4089 unsigned i, e; 4090 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 4091 Val = SVOp->getMaskElt(i); 4092 if (Val >= 0) 4093 break; 4094 } 4095 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4096 return (Val - i) * EltSize; 4097} 4098 4099/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4100/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4101/// instructions. 4102unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4103 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4104 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4105 4106 uint64_t Index = 4107 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4108 4109 EVT VecVT = N->getOperand(0).getValueType(); 4110 EVT ElVT = VecVT.getVectorElementType(); 4111 4112 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4113 return Index / NumElemsPerChunk; 4114} 4115 4116/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4117/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4118/// instructions. 4119unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4120 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4121 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4122 4123 uint64_t Index = 4124 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4125 4126 EVT VecVT = N->getValueType(0); 4127 EVT ElVT = VecVT.getVectorElementType(); 4128 4129 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4130 return Index / NumElemsPerChunk; 4131} 4132 4133/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4134/// constant +0.0. 4135bool X86::isZeroNode(SDValue Elt) { 4136 return ((isa<ConstantSDNode>(Elt) && 4137 cast<ConstantSDNode>(Elt)->isNullValue()) || 4138 (isa<ConstantFPSDNode>(Elt) && 4139 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4140} 4141 4142/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4143/// their permute mask. 4144static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4145 SelectionDAG &DAG) { 4146 EVT VT = SVOp->getValueType(0); 4147 unsigned NumElems = VT.getVectorNumElements(); 4148 SmallVector<int, 8> MaskVec; 4149 4150 for (unsigned i = 0; i != NumElems; ++i) { 4151 int idx = SVOp->getMaskElt(i); 4152 if (idx < 0) 4153 MaskVec.push_back(idx); 4154 else if (idx < (int)NumElems) 4155 MaskVec.push_back(idx + NumElems); 4156 else 4157 MaskVec.push_back(idx - NumElems); 4158 } 4159 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4160 SVOp->getOperand(0), &MaskVec[0]); 4161} 4162 4163/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 4164/// the two vector operands have swapped position. 4165static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 4166 unsigned NumElems = VT.getVectorNumElements(); 4167 for (unsigned i = 0; i != NumElems; ++i) { 4168 int idx = Mask[i]; 4169 if (idx < 0) 4170 continue; 4171 else if (idx < (int)NumElems) 4172 Mask[i] = idx + NumElems; 4173 else 4174 Mask[i] = idx - NumElems; 4175 } 4176} 4177 4178/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4179/// match movhlps. The lower half elements should come from upper half of 4180/// V1 (and in order), and the upper half elements should come from the upper 4181/// half of V2 (and in order). 4182static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4183 EVT VT = Op->getValueType(0); 4184 if (VT.getSizeInBits() != 128) 4185 return false; 4186 if (VT.getVectorNumElements() != 4) 4187 return false; 4188 for (unsigned i = 0, e = 2; i != e; ++i) 4189 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4190 return false; 4191 for (unsigned i = 2; i != 4; ++i) 4192 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4193 return false; 4194 return true; 4195} 4196 4197/// isScalarLoadToVector - Returns true if the node is a scalar load that 4198/// is promoted to a vector. It also returns the LoadSDNode by reference if 4199/// required. 4200static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4201 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4202 return false; 4203 N = N->getOperand(0).getNode(); 4204 if (!ISD::isNON_EXTLoad(N)) 4205 return false; 4206 if (LD) 4207 *LD = cast<LoadSDNode>(N); 4208 return true; 4209} 4210 4211/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4212/// match movlp{s|d}. The lower half elements should come from lower half of 4213/// V1 (and in order), and the upper half elements should come from the upper 4214/// half of V2 (and in order). And since V1 will become the source of the 4215/// MOVLP, it must be either a vector load or a scalar load to vector. 4216static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4217 ShuffleVectorSDNode *Op) { 4218 EVT VT = Op->getValueType(0); 4219 if (VT.getSizeInBits() != 128) 4220 return false; 4221 4222 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4223 return false; 4224 // Is V2 is a vector load, don't do this transformation. We will try to use 4225 // load folding shufps op. 4226 if (ISD::isNON_EXTLoad(V2)) 4227 return false; 4228 4229 unsigned NumElems = VT.getVectorNumElements(); 4230 4231 if (NumElems != 2 && NumElems != 4) 4232 return false; 4233 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4234 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4235 return false; 4236 for (unsigned i = NumElems/2; i != NumElems; ++i) 4237 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4238 return false; 4239 return true; 4240} 4241 4242/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4243/// all the same. 4244static bool isSplatVector(SDNode *N) { 4245 if (N->getOpcode() != ISD::BUILD_VECTOR) 4246 return false; 4247 4248 SDValue SplatValue = N->getOperand(0); 4249 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4250 if (N->getOperand(i) != SplatValue) 4251 return false; 4252 return true; 4253} 4254 4255/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4256/// to an zero vector. 4257/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4258static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4259 SDValue V1 = N->getOperand(0); 4260 SDValue V2 = N->getOperand(1); 4261 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4262 for (unsigned i = 0; i != NumElems; ++i) { 4263 int Idx = N->getMaskElt(i); 4264 if (Idx >= (int)NumElems) { 4265 unsigned Opc = V2.getOpcode(); 4266 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4267 continue; 4268 if (Opc != ISD::BUILD_VECTOR || 4269 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4270 return false; 4271 } else if (Idx >= 0) { 4272 unsigned Opc = V1.getOpcode(); 4273 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4274 continue; 4275 if (Opc != ISD::BUILD_VECTOR || 4276 !X86::isZeroNode(V1.getOperand(Idx))) 4277 return false; 4278 } 4279 } 4280 return true; 4281} 4282 4283/// getZeroVector - Returns a vector of specified type with all zero elements. 4284/// 4285static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG, 4286 DebugLoc dl) { 4287 assert(VT.isVector() && "Expected a vector type"); 4288 4289 // Always build SSE zero vectors as <4 x i32> bitcasted 4290 // to their dest type. This ensures they get CSE'd. 4291 SDValue Vec; 4292 if (VT.getSizeInBits() == 128) { // SSE 4293 if (HasXMMInt) { // SSE2 4294 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4295 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4296 } else { // SSE1 4297 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4298 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4299 } 4300 } else if (VT.getSizeInBits() == 256) { // AVX 4301 // 256-bit logic and arithmetic instructions in AVX are 4302 // all floating-point, no support for integer ops. Default 4303 // to emitting fp zeroed vectors then. 4304 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4305 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4307 } 4308 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4309} 4310 4311/// getOnesVector - Returns a vector of specified type with all bits set. 4312/// Always build ones vectors as <4 x i32>. For 256-bit types, use two 4313/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 4314/// original type, ensuring they get CSE'd. 4315static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4316 assert(VT.isVector() && "Expected a vector type"); 4317 assert((VT.is128BitVector() || VT.is256BitVector()) 4318 && "Expected a 128-bit or 256-bit vector type"); 4319 4320 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4321 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 4322 Cst, Cst, Cst, Cst); 4323 4324 if (VT.is256BitVector()) { 4325 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4326 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4327 Vec = Insert128BitVector(InsV, Vec, 4328 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4329 } 4330 4331 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4332} 4333 4334/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4335/// that point to V2 points to its first element. 4336static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4337 EVT VT = SVOp->getValueType(0); 4338 unsigned NumElems = VT.getVectorNumElements(); 4339 4340 bool Changed = false; 4341 SmallVector<int, 8> MaskVec; 4342 SVOp->getMask(MaskVec); 4343 4344 for (unsigned i = 0; i != NumElems; ++i) { 4345 if (MaskVec[i] > (int)NumElems) { 4346 MaskVec[i] = NumElems; 4347 Changed = true; 4348 } 4349 } 4350 if (Changed) 4351 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4352 SVOp->getOperand(1), &MaskVec[0]); 4353 return SDValue(SVOp, 0); 4354} 4355 4356/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4357/// operation of specified width. 4358static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4359 SDValue V2) { 4360 unsigned NumElems = VT.getVectorNumElements(); 4361 SmallVector<int, 8> Mask; 4362 Mask.push_back(NumElems); 4363 for (unsigned i = 1; i != NumElems; ++i) 4364 Mask.push_back(i); 4365 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4366} 4367 4368/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4369static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4370 SDValue V2) { 4371 unsigned NumElems = VT.getVectorNumElements(); 4372 SmallVector<int, 8> Mask; 4373 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4374 Mask.push_back(i); 4375 Mask.push_back(i + NumElems); 4376 } 4377 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4378} 4379 4380/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4381static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4382 SDValue V2) { 4383 unsigned NumElems = VT.getVectorNumElements(); 4384 unsigned Half = NumElems/2; 4385 SmallVector<int, 8> Mask; 4386 for (unsigned i = 0; i != Half; ++i) { 4387 Mask.push_back(i + Half); 4388 Mask.push_back(i + NumElems + Half); 4389 } 4390 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4391} 4392 4393// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4394// a generic shuffle instruction because the target has no such instructions. 4395// Generate shuffles which repeat i16 and i8 several times until they can be 4396// represented by v4f32 and then be manipulated by target suported shuffles. 4397static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4398 EVT VT = V.getValueType(); 4399 int NumElems = VT.getVectorNumElements(); 4400 DebugLoc dl = V.getDebugLoc(); 4401 4402 while (NumElems > 4) { 4403 if (EltNo < NumElems/2) { 4404 V = getUnpackl(DAG, dl, VT, V, V); 4405 } else { 4406 V = getUnpackh(DAG, dl, VT, V, V); 4407 EltNo -= NumElems/2; 4408 } 4409 NumElems >>= 1; 4410 } 4411 return V; 4412} 4413 4414/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4415static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4416 EVT VT = V.getValueType(); 4417 DebugLoc dl = V.getDebugLoc(); 4418 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4419 && "Vector size not supported"); 4420 4421 if (VT.getSizeInBits() == 128) { 4422 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4423 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4424 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4425 &SplatMask[0]); 4426 } else { 4427 // To use VPERMILPS to splat scalars, the second half of indicies must 4428 // refer to the higher part, which is a duplication of the lower one, 4429 // because VPERMILPS can only handle in-lane permutations. 4430 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4431 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4432 4433 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4434 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4435 &SplatMask[0]); 4436 } 4437 4438 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4439} 4440 4441/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4442static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4443 EVT SrcVT = SV->getValueType(0); 4444 SDValue V1 = SV->getOperand(0); 4445 DebugLoc dl = SV->getDebugLoc(); 4446 4447 int EltNo = SV->getSplatIndex(); 4448 int NumElems = SrcVT.getVectorNumElements(); 4449 unsigned Size = SrcVT.getSizeInBits(); 4450 4451 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4452 "Unknown how to promote splat for type"); 4453 4454 // Extract the 128-bit part containing the splat element and update 4455 // the splat element index when it refers to the higher register. 4456 if (Size == 256) { 4457 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4458 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4459 if (Idx > 0) 4460 EltNo -= NumElems/2; 4461 } 4462 4463 // All i16 and i8 vector types can't be used directly by a generic shuffle 4464 // instruction because the target has no such instruction. Generate shuffles 4465 // which repeat i16 and i8 several times until they fit in i32, and then can 4466 // be manipulated by target suported shuffles. 4467 EVT EltVT = SrcVT.getVectorElementType(); 4468 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4469 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4470 4471 // Recreate the 256-bit vector and place the same 128-bit vector 4472 // into the low and high part. This is necessary because we want 4473 // to use VPERM* to shuffle the vectors 4474 if (Size == 256) { 4475 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4476 DAG.getConstant(0, MVT::i32), DAG, dl); 4477 V1 = Insert128BitVector(InsV, V1, 4478 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4479 } 4480 4481 return getLegalSplat(DAG, V1, EltNo); 4482} 4483 4484/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4485/// vector of zero or undef vector. This produces a shuffle where the low 4486/// element of V2 is swizzled into the zero/undef vector, landing at element 4487/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4488static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4489 bool isZero, bool HasXMMInt, 4490 SelectionDAG &DAG) { 4491 EVT VT = V2.getValueType(); 4492 SDValue V1 = isZero 4493 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4494 unsigned NumElems = VT.getVectorNumElements(); 4495 SmallVector<int, 16> MaskVec; 4496 for (unsigned i = 0; i != NumElems; ++i) 4497 // If this is the insertion idx, put the low elt of V2 here. 4498 MaskVec.push_back(i == Idx ? NumElems : i); 4499 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4500} 4501 4502/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4503/// element of the result of the vector shuffle. 4504static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4505 unsigned Depth) { 4506 if (Depth == 6) 4507 return SDValue(); // Limit search depth. 4508 4509 SDValue V = SDValue(N, 0); 4510 EVT VT = V.getValueType(); 4511 unsigned Opcode = V.getOpcode(); 4512 4513 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4514 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4515 Index = SV->getMaskElt(Index); 4516 4517 if (Index < 0) 4518 return DAG.getUNDEF(VT.getVectorElementType()); 4519 4520 int NumElems = VT.getVectorNumElements(); 4521 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4522 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4523 } 4524 4525 // Recurse into target specific vector shuffles to find scalars. 4526 if (isTargetShuffle(Opcode)) { 4527 int NumElems = VT.getVectorNumElements(); 4528 SmallVector<unsigned, 16> ShuffleMask; 4529 SDValue ImmN; 4530 4531 switch(Opcode) { 4532 case X86ISD::SHUFPS: 4533 case X86ISD::SHUFPD: 4534 ImmN = N->getOperand(N->getNumOperands()-1); 4535 DecodeSHUFPSMask(NumElems, 4536 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4537 ShuffleMask); 4538 break; 4539 case X86ISD::PUNPCKHBW: 4540 case X86ISD::PUNPCKHWD: 4541 case X86ISD::PUNPCKHDQ: 4542 case X86ISD::PUNPCKHQDQ: 4543 DecodePUNPCKHMask(NumElems, ShuffleMask); 4544 break; 4545 case X86ISD::UNPCKHPS: 4546 case X86ISD::UNPCKHPD: 4547 case X86ISD::VUNPCKHPSY: 4548 case X86ISD::VUNPCKHPDY: 4549 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4550 break; 4551 case X86ISD::PUNPCKLBW: 4552 case X86ISD::PUNPCKLWD: 4553 case X86ISD::PUNPCKLDQ: 4554 case X86ISD::PUNPCKLQDQ: 4555 DecodePUNPCKLMask(VT, ShuffleMask); 4556 break; 4557 case X86ISD::UNPCKLPS: 4558 case X86ISD::UNPCKLPD: 4559 case X86ISD::VUNPCKLPSY: 4560 case X86ISD::VUNPCKLPDY: 4561 DecodeUNPCKLPMask(VT, ShuffleMask); 4562 break; 4563 case X86ISD::MOVHLPS: 4564 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4565 break; 4566 case X86ISD::MOVLHPS: 4567 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4568 break; 4569 case X86ISD::PSHUFD: 4570 ImmN = N->getOperand(N->getNumOperands()-1); 4571 DecodePSHUFMask(NumElems, 4572 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4573 ShuffleMask); 4574 break; 4575 case X86ISD::PSHUFHW: 4576 ImmN = N->getOperand(N->getNumOperands()-1); 4577 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4578 ShuffleMask); 4579 break; 4580 case X86ISD::PSHUFLW: 4581 ImmN = N->getOperand(N->getNumOperands()-1); 4582 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4583 ShuffleMask); 4584 break; 4585 case X86ISD::MOVSS: 4586 case X86ISD::MOVSD: { 4587 // The index 0 always comes from the first element of the second source, 4588 // this is why MOVSS and MOVSD are used in the first place. The other 4589 // elements come from the other positions of the first source vector. 4590 unsigned OpNum = (Index == 0) ? 1 : 0; 4591 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4592 Depth+1); 4593 } 4594 case X86ISD::VPERMILPS: 4595 ImmN = N->getOperand(N->getNumOperands()-1); 4596 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4597 ShuffleMask); 4598 break; 4599 case X86ISD::VPERMILPSY: 4600 ImmN = N->getOperand(N->getNumOperands()-1); 4601 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4602 ShuffleMask); 4603 break; 4604 case X86ISD::VPERMILPD: 4605 ImmN = N->getOperand(N->getNumOperands()-1); 4606 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4607 ShuffleMask); 4608 break; 4609 case X86ISD::VPERMILPDY: 4610 ImmN = N->getOperand(N->getNumOperands()-1); 4611 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4612 ShuffleMask); 4613 break; 4614 case X86ISD::VPERM2F128: 4615 ImmN = N->getOperand(N->getNumOperands()-1); 4616 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4617 ShuffleMask); 4618 break; 4619 case X86ISD::MOVDDUP: 4620 case X86ISD::MOVLHPD: 4621 case X86ISD::MOVLPD: 4622 case X86ISD::MOVLPS: 4623 case X86ISD::MOVSHDUP: 4624 case X86ISD::MOVSLDUP: 4625 case X86ISD::PALIGN: 4626 return SDValue(); // Not yet implemented. 4627 default: 4628 assert(0 && "unknown target shuffle node"); 4629 return SDValue(); 4630 } 4631 4632 Index = ShuffleMask[Index]; 4633 if (Index < 0) 4634 return DAG.getUNDEF(VT.getVectorElementType()); 4635 4636 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4637 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4638 Depth+1); 4639 } 4640 4641 // Actual nodes that may contain scalar elements 4642 if (Opcode == ISD::BITCAST) { 4643 V = V.getOperand(0); 4644 EVT SrcVT = V.getValueType(); 4645 unsigned NumElems = VT.getVectorNumElements(); 4646 4647 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4648 return SDValue(); 4649 } 4650 4651 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4652 return (Index == 0) ? V.getOperand(0) 4653 : DAG.getUNDEF(VT.getVectorElementType()); 4654 4655 if (V.getOpcode() == ISD::BUILD_VECTOR) 4656 return V.getOperand(Index); 4657 4658 return SDValue(); 4659} 4660 4661/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4662/// shuffle operation which come from a consecutively from a zero. The 4663/// search can start in two different directions, from left or right. 4664static 4665unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4666 bool ZerosFromLeft, SelectionDAG &DAG) { 4667 int i = 0; 4668 4669 while (i < NumElems) { 4670 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4671 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4672 if (!(Elt.getNode() && 4673 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4674 break; 4675 ++i; 4676 } 4677 4678 return i; 4679} 4680 4681/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4682/// MaskE correspond consecutively to elements from one of the vector operands, 4683/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4684static 4685bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4686 int OpIdx, int NumElems, unsigned &OpNum) { 4687 bool SeenV1 = false; 4688 bool SeenV2 = false; 4689 4690 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4691 int Idx = SVOp->getMaskElt(i); 4692 // Ignore undef indicies 4693 if (Idx < 0) 4694 continue; 4695 4696 if (Idx < NumElems) 4697 SeenV1 = true; 4698 else 4699 SeenV2 = true; 4700 4701 // Only accept consecutive elements from the same vector 4702 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4703 return false; 4704 } 4705 4706 OpNum = SeenV1 ? 0 : 1; 4707 return true; 4708} 4709 4710/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4711/// logical left shift of a vector. 4712static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4713 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4714 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4715 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4716 false /* check zeros from right */, DAG); 4717 unsigned OpSrc; 4718 4719 if (!NumZeros) 4720 return false; 4721 4722 // Considering the elements in the mask that are not consecutive zeros, 4723 // check if they consecutively come from only one of the source vectors. 4724 // 4725 // V1 = {X, A, B, C} 0 4726 // \ \ \ / 4727 // vector_shuffle V1, V2 <1, 2, 3, X> 4728 // 4729 if (!isShuffleMaskConsecutive(SVOp, 4730 0, // Mask Start Index 4731 NumElems-NumZeros-1, // Mask End Index 4732 NumZeros, // Where to start looking in the src vector 4733 NumElems, // Number of elements in vector 4734 OpSrc)) // Which source operand ? 4735 return false; 4736 4737 isLeft = false; 4738 ShAmt = NumZeros; 4739 ShVal = SVOp->getOperand(OpSrc); 4740 return true; 4741} 4742 4743/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4744/// logical left shift of a vector. 4745static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4746 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4747 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4748 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4749 true /* check zeros from left */, DAG); 4750 unsigned OpSrc; 4751 4752 if (!NumZeros) 4753 return false; 4754 4755 // Considering the elements in the mask that are not consecutive zeros, 4756 // check if they consecutively come from only one of the source vectors. 4757 // 4758 // 0 { A, B, X, X } = V2 4759 // / \ / / 4760 // vector_shuffle V1, V2 <X, X, 4, 5> 4761 // 4762 if (!isShuffleMaskConsecutive(SVOp, 4763 NumZeros, // Mask Start Index 4764 NumElems-1, // Mask End Index 4765 0, // Where to start looking in the src vector 4766 NumElems, // Number of elements in vector 4767 OpSrc)) // Which source operand ? 4768 return false; 4769 4770 isLeft = true; 4771 ShAmt = NumZeros; 4772 ShVal = SVOp->getOperand(OpSrc); 4773 return true; 4774} 4775 4776/// isVectorShift - Returns true if the shuffle can be implemented as a 4777/// logical left or right shift of a vector. 4778static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4779 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4780 // Although the logic below support any bitwidth size, there are no 4781 // shift instructions which handle more than 128-bit vectors. 4782 if (SVOp->getValueType(0).getSizeInBits() > 128) 4783 return false; 4784 4785 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4786 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4787 return true; 4788 4789 return false; 4790} 4791 4792/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4793/// 4794static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4795 unsigned NumNonZero, unsigned NumZero, 4796 SelectionDAG &DAG, 4797 const TargetLowering &TLI) { 4798 if (NumNonZero > 8) 4799 return SDValue(); 4800 4801 DebugLoc dl = Op.getDebugLoc(); 4802 SDValue V(0, 0); 4803 bool First = true; 4804 for (unsigned i = 0; i < 16; ++i) { 4805 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4806 if (ThisIsNonZero && First) { 4807 if (NumZero) 4808 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4809 else 4810 V = DAG.getUNDEF(MVT::v8i16); 4811 First = false; 4812 } 4813 4814 if ((i & 1) != 0) { 4815 SDValue ThisElt(0, 0), LastElt(0, 0); 4816 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4817 if (LastIsNonZero) { 4818 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4819 MVT::i16, Op.getOperand(i-1)); 4820 } 4821 if (ThisIsNonZero) { 4822 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4823 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4824 ThisElt, DAG.getConstant(8, MVT::i8)); 4825 if (LastIsNonZero) 4826 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4827 } else 4828 ThisElt = LastElt; 4829 4830 if (ThisElt.getNode()) 4831 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4832 DAG.getIntPtrConstant(i/2)); 4833 } 4834 } 4835 4836 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4837} 4838 4839/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4840/// 4841static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4842 unsigned NumNonZero, unsigned NumZero, 4843 SelectionDAG &DAG, 4844 const TargetLowering &TLI) { 4845 if (NumNonZero > 4) 4846 return SDValue(); 4847 4848 DebugLoc dl = Op.getDebugLoc(); 4849 SDValue V(0, 0); 4850 bool First = true; 4851 for (unsigned i = 0; i < 8; ++i) { 4852 bool isNonZero = (NonZeros & (1 << i)) != 0; 4853 if (isNonZero) { 4854 if (First) { 4855 if (NumZero) 4856 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4857 else 4858 V = DAG.getUNDEF(MVT::v8i16); 4859 First = false; 4860 } 4861 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4862 MVT::v8i16, V, Op.getOperand(i), 4863 DAG.getIntPtrConstant(i)); 4864 } 4865 } 4866 4867 return V; 4868} 4869 4870/// getVShift - Return a vector logical shift node. 4871/// 4872static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4873 unsigned NumBits, SelectionDAG &DAG, 4874 const TargetLowering &TLI, DebugLoc dl) { 4875 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4876 EVT ShVT = MVT::v2i64; 4877 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4878 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4879 return DAG.getNode(ISD::BITCAST, dl, VT, 4880 DAG.getNode(Opc, dl, ShVT, SrcOp, 4881 DAG.getConstant(NumBits, 4882 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4883} 4884 4885SDValue 4886X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4887 SelectionDAG &DAG) const { 4888 4889 // Check if the scalar load can be widened into a vector load. And if 4890 // the address is "base + cst" see if the cst can be "absorbed" into 4891 // the shuffle mask. 4892 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4893 SDValue Ptr = LD->getBasePtr(); 4894 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4895 return SDValue(); 4896 EVT PVT = LD->getValueType(0); 4897 if (PVT != MVT::i32 && PVT != MVT::f32) 4898 return SDValue(); 4899 4900 int FI = -1; 4901 int64_t Offset = 0; 4902 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4903 FI = FINode->getIndex(); 4904 Offset = 0; 4905 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4906 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4907 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4908 Offset = Ptr.getConstantOperandVal(1); 4909 Ptr = Ptr.getOperand(0); 4910 } else { 4911 return SDValue(); 4912 } 4913 4914 // FIXME: 256-bit vector instructions don't require a strict alignment, 4915 // improve this code to support it better. 4916 unsigned RequiredAlign = VT.getSizeInBits()/8; 4917 SDValue Chain = LD->getChain(); 4918 // Make sure the stack object alignment is at least 16 or 32. 4919 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4920 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4921 if (MFI->isFixedObjectIndex(FI)) { 4922 // Can't change the alignment. FIXME: It's possible to compute 4923 // the exact stack offset and reference FI + adjust offset instead. 4924 // If someone *really* cares about this. That's the way to implement it. 4925 return SDValue(); 4926 } else { 4927 MFI->setObjectAlignment(FI, RequiredAlign); 4928 } 4929 } 4930 4931 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4932 // Ptr + (Offset & ~15). 4933 if (Offset < 0) 4934 return SDValue(); 4935 if ((Offset % RequiredAlign) & 3) 4936 return SDValue(); 4937 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4938 if (StartOffset) 4939 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4940 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4941 4942 int EltNo = (Offset - StartOffset) >> 2; 4943 int NumElems = VT.getVectorNumElements(); 4944 4945 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4946 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4947 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4948 LD->getPointerInfo().getWithOffset(StartOffset), 4949 false, false, 0); 4950 4951 // Canonicalize it to a v4i32 or v8i32 shuffle. 4952 SmallVector<int, 8> Mask; 4953 for (int i = 0; i < NumElems; ++i) 4954 Mask.push_back(EltNo); 4955 4956 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4957 return DAG.getNode(ISD::BITCAST, dl, NVT, 4958 DAG.getVectorShuffle(CanonVT, dl, V1, 4959 DAG.getUNDEF(CanonVT),&Mask[0])); 4960 } 4961 4962 return SDValue(); 4963} 4964 4965/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4966/// vector of type 'VT', see if the elements can be replaced by a single large 4967/// load which has the same value as a build_vector whose operands are 'elts'. 4968/// 4969/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4970/// 4971/// FIXME: we'd also like to handle the case where the last elements are zero 4972/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4973/// There's even a handy isZeroNode for that purpose. 4974static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4975 DebugLoc &DL, SelectionDAG &DAG) { 4976 EVT EltVT = VT.getVectorElementType(); 4977 unsigned NumElems = Elts.size(); 4978 4979 LoadSDNode *LDBase = NULL; 4980 unsigned LastLoadedElt = -1U; 4981 4982 // For each element in the initializer, see if we've found a load or an undef. 4983 // If we don't find an initial load element, or later load elements are 4984 // non-consecutive, bail out. 4985 for (unsigned i = 0; i < NumElems; ++i) { 4986 SDValue Elt = Elts[i]; 4987 4988 if (!Elt.getNode() || 4989 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4990 return SDValue(); 4991 if (!LDBase) { 4992 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4993 return SDValue(); 4994 LDBase = cast<LoadSDNode>(Elt.getNode()); 4995 LastLoadedElt = i; 4996 continue; 4997 } 4998 if (Elt.getOpcode() == ISD::UNDEF) 4999 continue; 5000 5001 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5002 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5003 return SDValue(); 5004 LastLoadedElt = i; 5005 } 5006 5007 // If we have found an entire vector of loads and undefs, then return a large 5008 // load of the entire vector width starting at the base pointer. If we found 5009 // consecutive loads for the low half, generate a vzext_load node. 5010 if (LastLoadedElt == NumElems - 1) { 5011 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5012 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5013 LDBase->getPointerInfo(), 5014 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 5015 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5016 LDBase->getPointerInfo(), 5017 LDBase->isVolatile(), LDBase->isNonTemporal(), 5018 LDBase->getAlignment()); 5019 } else if (NumElems == 4 && LastLoadedElt == 1 && 5020 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5021 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5022 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5023 SDValue ResNode = 5024 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5025 LDBase->getPointerInfo(), 5026 LDBase->getAlignment(), 5027 false/*isVolatile*/, true/*ReadMem*/, 5028 false/*WriteMem*/); 5029 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5030 } 5031 return SDValue(); 5032} 5033 5034SDValue 5035X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5036 DebugLoc dl = Op.getDebugLoc(); 5037 5038 EVT VT = Op.getValueType(); 5039 EVT ExtVT = VT.getVectorElementType(); 5040 unsigned NumElems = Op.getNumOperands(); 5041 5042 // Vectors containing all zeros can be matched by pxor and xorps later 5043 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5044 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5045 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5046 if (Op.getValueType() == MVT::v4i32 || 5047 Op.getValueType() == MVT::v8i32) 5048 return Op; 5049 5050 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl); 5051 } 5052 5053 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5054 // vectors or broken into v4i32 operations on 256-bit vectors. 5055 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5056 if (Op.getValueType() == MVT::v4i32) 5057 return Op; 5058 5059 return getOnesVector(Op.getValueType(), DAG, dl); 5060 } 5061 5062 unsigned EVTBits = ExtVT.getSizeInBits(); 5063 5064 unsigned NumZero = 0; 5065 unsigned NumNonZero = 0; 5066 unsigned NonZeros = 0; 5067 bool IsAllConstants = true; 5068 SmallSet<SDValue, 8> Values; 5069 for (unsigned i = 0; i < NumElems; ++i) { 5070 SDValue Elt = Op.getOperand(i); 5071 if (Elt.getOpcode() == ISD::UNDEF) 5072 continue; 5073 Values.insert(Elt); 5074 if (Elt.getOpcode() != ISD::Constant && 5075 Elt.getOpcode() != ISD::ConstantFP) 5076 IsAllConstants = false; 5077 if (X86::isZeroNode(Elt)) 5078 NumZero++; 5079 else { 5080 NonZeros |= (1 << i); 5081 NumNonZero++; 5082 } 5083 } 5084 5085 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5086 if (NumNonZero == 0) 5087 return DAG.getUNDEF(VT); 5088 5089 // Special case for single non-zero, non-undef, element. 5090 if (NumNonZero == 1) { 5091 unsigned Idx = CountTrailingZeros_32(NonZeros); 5092 SDValue Item = Op.getOperand(Idx); 5093 5094 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5095 // the value are obviously zero, truncate the value to i32 and do the 5096 // insertion that way. Only do this if the value is non-constant or if the 5097 // value is a constant being inserted into element 0. It is cheaper to do 5098 // a constant pool load than it is to do a movd + shuffle. 5099 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5100 (!IsAllConstants || Idx == 0)) { 5101 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5102 // Handle SSE only. 5103 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5104 EVT VecVT = MVT::v4i32; 5105 unsigned VecElts = 4; 5106 5107 // Truncate the value (which may itself be a constant) to i32, and 5108 // convert it to a vector with movd (S2V+shuffle to zero extend). 5109 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5110 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5111 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5112 Subtarget->hasXMMInt(), DAG); 5113 5114 // Now we have our 32-bit value zero extended in the low element of 5115 // a vector. If Idx != 0, swizzle it into place. 5116 if (Idx != 0) { 5117 SmallVector<int, 4> Mask; 5118 Mask.push_back(Idx); 5119 for (unsigned i = 1; i != VecElts; ++i) 5120 Mask.push_back(i); 5121 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5122 DAG.getUNDEF(Item.getValueType()), 5123 &Mask[0]); 5124 } 5125 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5126 } 5127 } 5128 5129 // If we have a constant or non-constant insertion into the low element of 5130 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5131 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5132 // depending on what the source datatype is. 5133 if (Idx == 0) { 5134 if (NumZero == 0) { 5135 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5136 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5137 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5138 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5139 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5140 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), 5141 DAG); 5142 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5143 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5144 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5145 EVT MiddleVT = MVT::v4i32; 5146 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 5147 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5148 Subtarget->hasXMMInt(), DAG); 5149 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5150 } 5151 } 5152 5153 // Is it a vector logical left shift? 5154 if (NumElems == 2 && Idx == 1 && 5155 X86::isZeroNode(Op.getOperand(0)) && 5156 !X86::isZeroNode(Op.getOperand(1))) { 5157 unsigned NumBits = VT.getSizeInBits(); 5158 return getVShift(true, VT, 5159 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5160 VT, Op.getOperand(1)), 5161 NumBits/2, DAG, *this, dl); 5162 } 5163 5164 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5165 return SDValue(); 5166 5167 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5168 // is a non-constant being inserted into an element other than the low one, 5169 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5170 // movd/movss) to move this into the low element, then shuffle it into 5171 // place. 5172 if (EVTBits == 32) { 5173 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5174 5175 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5176 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5177 Subtarget->hasXMMInt(), DAG); 5178 SmallVector<int, 8> MaskVec; 5179 for (unsigned i = 0; i < NumElems; i++) 5180 MaskVec.push_back(i == Idx ? 0 : 1); 5181 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5182 } 5183 } 5184 5185 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5186 if (Values.size() == 1) { 5187 if (EVTBits == 32) { 5188 // Instead of a shuffle like this: 5189 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5190 // Check if it's possible to issue this instead. 5191 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5192 unsigned Idx = CountTrailingZeros_32(NonZeros); 5193 SDValue Item = Op.getOperand(Idx); 5194 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5195 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5196 } 5197 return SDValue(); 5198 } 5199 5200 // A vector full of immediates; various special cases are already 5201 // handled, so this is best done with a single constant-pool load. 5202 if (IsAllConstants) 5203 return SDValue(); 5204 5205 // For AVX-length vectors, build the individual 128-bit pieces and use 5206 // shuffles to put them in place. 5207 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5208 SmallVector<SDValue, 32> V; 5209 for (unsigned i = 0; i < NumElems; ++i) 5210 V.push_back(Op.getOperand(i)); 5211 5212 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5213 5214 // Build both the lower and upper subvector. 5215 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5216 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5217 NumElems/2); 5218 5219 // Recreate the wider vector with the lower and upper part. 5220 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5221 DAG.getConstant(0, MVT::i32), DAG, dl); 5222 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5223 DAG, dl); 5224 } 5225 5226 // Let legalizer expand 2-wide build_vectors. 5227 if (EVTBits == 64) { 5228 if (NumNonZero == 1) { 5229 // One half is zero or undef. 5230 unsigned Idx = CountTrailingZeros_32(NonZeros); 5231 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5232 Op.getOperand(Idx)); 5233 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5234 Subtarget->hasXMMInt(), DAG); 5235 } 5236 return SDValue(); 5237 } 5238 5239 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5240 if (EVTBits == 8 && NumElems == 16) { 5241 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5242 *this); 5243 if (V.getNode()) return V; 5244 } 5245 5246 if (EVTBits == 16 && NumElems == 8) { 5247 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5248 *this); 5249 if (V.getNode()) return V; 5250 } 5251 5252 // If element VT is == 32 bits, turn it into a number of shuffles. 5253 SmallVector<SDValue, 8> V; 5254 V.resize(NumElems); 5255 if (NumElems == 4 && NumZero > 0) { 5256 for (unsigned i = 0; i < 4; ++i) { 5257 bool isZero = !(NonZeros & (1 << i)); 5258 if (isZero) 5259 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 5260 else 5261 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5262 } 5263 5264 for (unsigned i = 0; i < 2; ++i) { 5265 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5266 default: break; 5267 case 0: 5268 V[i] = V[i*2]; // Must be a zero vector. 5269 break; 5270 case 1: 5271 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5272 break; 5273 case 2: 5274 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5275 break; 5276 case 3: 5277 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5278 break; 5279 } 5280 } 5281 5282 SmallVector<int, 8> MaskVec; 5283 bool Reverse = (NonZeros & 0x3) == 2; 5284 for (unsigned i = 0; i < 2; ++i) 5285 MaskVec.push_back(Reverse ? 1-i : i); 5286 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5287 for (unsigned i = 0; i < 2; ++i) 5288 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5289 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5290 } 5291 5292 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5293 // Check for a build vector of consecutive loads. 5294 for (unsigned i = 0; i < NumElems; ++i) 5295 V[i] = Op.getOperand(i); 5296 5297 // Check for elements which are consecutive loads. 5298 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5299 if (LD.getNode()) 5300 return LD; 5301 5302 // For SSE 4.1, use insertps to put the high elements into the low element. 5303 if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) { 5304 SDValue Result; 5305 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5306 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5307 else 5308 Result = DAG.getUNDEF(VT); 5309 5310 for (unsigned i = 1; i < NumElems; ++i) { 5311 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5312 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5313 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5314 } 5315 return Result; 5316 } 5317 5318 // Otherwise, expand into a number of unpckl*, start by extending each of 5319 // our (non-undef) elements to the full vector width with the element in the 5320 // bottom slot of the vector (which generates no code for SSE). 5321 for (unsigned i = 0; i < NumElems; ++i) { 5322 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5323 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5324 else 5325 V[i] = DAG.getUNDEF(VT); 5326 } 5327 5328 // Next, we iteratively mix elements, e.g. for v4f32: 5329 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5330 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5331 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5332 unsigned EltStride = NumElems >> 1; 5333 while (EltStride != 0) { 5334 for (unsigned i = 0; i < EltStride; ++i) { 5335 // If V[i+EltStride] is undef and this is the first round of mixing, 5336 // then it is safe to just drop this shuffle: V[i] is already in the 5337 // right place, the one element (since it's the first round) being 5338 // inserted as undef can be dropped. This isn't safe for successive 5339 // rounds because they will permute elements within both vectors. 5340 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5341 EltStride == NumElems/2) 5342 continue; 5343 5344 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5345 } 5346 EltStride >>= 1; 5347 } 5348 return V[0]; 5349 } 5350 return SDValue(); 5351} 5352 5353// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5354// them in a MMX register. This is better than doing a stack convert. 5355static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5356 DebugLoc dl = Op.getDebugLoc(); 5357 EVT ResVT = Op.getValueType(); 5358 5359 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5360 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5361 int Mask[2]; 5362 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5363 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5364 InVec = Op.getOperand(1); 5365 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5366 unsigned NumElts = ResVT.getVectorNumElements(); 5367 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5368 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5369 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5370 } else { 5371 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5372 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5373 Mask[0] = 0; Mask[1] = 2; 5374 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5375 } 5376 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5377} 5378 5379// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5380// to create 256-bit vectors from two other 128-bit ones. 5381static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5382 DebugLoc dl = Op.getDebugLoc(); 5383 EVT ResVT = Op.getValueType(); 5384 5385 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5386 5387 SDValue V1 = Op.getOperand(0); 5388 SDValue V2 = Op.getOperand(1); 5389 unsigned NumElems = ResVT.getVectorNumElements(); 5390 5391 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5392 DAG.getConstant(0, MVT::i32), DAG, dl); 5393 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5394 DAG, dl); 5395} 5396 5397SDValue 5398X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5399 EVT ResVT = Op.getValueType(); 5400 5401 assert(Op.getNumOperands() == 2); 5402 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5403 "Unsupported CONCAT_VECTORS for value type"); 5404 5405 // We support concatenate two MMX registers and place them in a MMX register. 5406 // This is better than doing a stack convert. 5407 if (ResVT.is128BitVector()) 5408 return LowerMMXCONCAT_VECTORS(Op, DAG); 5409 5410 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5411 // from two other 128-bit ones. 5412 return LowerAVXCONCAT_VECTORS(Op, DAG); 5413} 5414 5415// v8i16 shuffles - Prefer shuffles in the following order: 5416// 1. [all] pshuflw, pshufhw, optional move 5417// 2. [ssse3] 1 x pshufb 5418// 3. [ssse3] 2 x pshufb + 1 x por 5419// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5420SDValue 5421X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5422 SelectionDAG &DAG) const { 5423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5424 SDValue V1 = SVOp->getOperand(0); 5425 SDValue V2 = SVOp->getOperand(1); 5426 DebugLoc dl = SVOp->getDebugLoc(); 5427 SmallVector<int, 8> MaskVals; 5428 5429 // Determine if more than 1 of the words in each of the low and high quadwords 5430 // of the result come from the same quadword of one of the two inputs. Undef 5431 // mask values count as coming from any quadword, for better codegen. 5432 SmallVector<unsigned, 4> LoQuad(4); 5433 SmallVector<unsigned, 4> HiQuad(4); 5434 BitVector InputQuads(4); 5435 for (unsigned i = 0; i < 8; ++i) { 5436 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 5437 int EltIdx = SVOp->getMaskElt(i); 5438 MaskVals.push_back(EltIdx); 5439 if (EltIdx < 0) { 5440 ++Quad[0]; 5441 ++Quad[1]; 5442 ++Quad[2]; 5443 ++Quad[3]; 5444 continue; 5445 } 5446 ++Quad[EltIdx / 4]; 5447 InputQuads.set(EltIdx / 4); 5448 } 5449 5450 int BestLoQuad = -1; 5451 unsigned MaxQuad = 1; 5452 for (unsigned i = 0; i < 4; ++i) { 5453 if (LoQuad[i] > MaxQuad) { 5454 BestLoQuad = i; 5455 MaxQuad = LoQuad[i]; 5456 } 5457 } 5458 5459 int BestHiQuad = -1; 5460 MaxQuad = 1; 5461 for (unsigned i = 0; i < 4; ++i) { 5462 if (HiQuad[i] > MaxQuad) { 5463 BestHiQuad = i; 5464 MaxQuad = HiQuad[i]; 5465 } 5466 } 5467 5468 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5469 // of the two input vectors, shuffle them into one input vector so only a 5470 // single pshufb instruction is necessary. If There are more than 2 input 5471 // quads, disable the next transformation since it does not help SSSE3. 5472 bool V1Used = InputQuads[0] || InputQuads[1]; 5473 bool V2Used = InputQuads[2] || InputQuads[3]; 5474 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5475 if (InputQuads.count() == 2 && V1Used && V2Used) { 5476 BestLoQuad = InputQuads.find_first(); 5477 BestHiQuad = InputQuads.find_next(BestLoQuad); 5478 } 5479 if (InputQuads.count() > 2) { 5480 BestLoQuad = -1; 5481 BestHiQuad = -1; 5482 } 5483 } 5484 5485 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5486 // the shuffle mask. If a quad is scored as -1, that means that it contains 5487 // words from all 4 input quadwords. 5488 SDValue NewV; 5489 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5490 SmallVector<int, 8> MaskV; 5491 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5492 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5493 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5494 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5495 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5496 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5497 5498 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5499 // source words for the shuffle, to aid later transformations. 5500 bool AllWordsInNewV = true; 5501 bool InOrder[2] = { true, true }; 5502 for (unsigned i = 0; i != 8; ++i) { 5503 int idx = MaskVals[i]; 5504 if (idx != (int)i) 5505 InOrder[i/4] = false; 5506 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5507 continue; 5508 AllWordsInNewV = false; 5509 break; 5510 } 5511 5512 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5513 if (AllWordsInNewV) { 5514 for (int i = 0; i != 8; ++i) { 5515 int idx = MaskVals[i]; 5516 if (idx < 0) 5517 continue; 5518 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5519 if ((idx != i) && idx < 4) 5520 pshufhw = false; 5521 if ((idx != i) && idx > 3) 5522 pshuflw = false; 5523 } 5524 V1 = NewV; 5525 V2Used = false; 5526 BestLoQuad = 0; 5527 BestHiQuad = 1; 5528 } 5529 5530 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5531 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5532 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5533 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5534 unsigned TargetMask = 0; 5535 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5536 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5537 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5538 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5539 V1 = NewV.getOperand(0); 5540 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5541 } 5542 } 5543 5544 // If we have SSSE3, and all words of the result are from 1 input vector, 5545 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5546 // is present, fall back to case 4. 5547 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5548 SmallVector<SDValue,16> pshufbMask; 5549 5550 // If we have elements from both input vectors, set the high bit of the 5551 // shuffle mask element to zero out elements that come from V2 in the V1 5552 // mask, and elements that come from V1 in the V2 mask, so that the two 5553 // results can be OR'd together. 5554 bool TwoInputs = V1Used && V2Used; 5555 for (unsigned i = 0; i != 8; ++i) { 5556 int EltIdx = MaskVals[i] * 2; 5557 if (TwoInputs && (EltIdx >= 16)) { 5558 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5559 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5560 continue; 5561 } 5562 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5563 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5564 } 5565 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5566 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5567 DAG.getNode(ISD::BUILD_VECTOR, dl, 5568 MVT::v16i8, &pshufbMask[0], 16)); 5569 if (!TwoInputs) 5570 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5571 5572 // Calculate the shuffle mask for the second input, shuffle it, and 5573 // OR it with the first shuffled input. 5574 pshufbMask.clear(); 5575 for (unsigned i = 0; i != 8; ++i) { 5576 int EltIdx = MaskVals[i] * 2; 5577 if (EltIdx < 16) { 5578 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5579 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5580 continue; 5581 } 5582 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5583 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5584 } 5585 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5586 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5587 DAG.getNode(ISD::BUILD_VECTOR, dl, 5588 MVT::v16i8, &pshufbMask[0], 16)); 5589 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5590 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5591 } 5592 5593 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5594 // and update MaskVals with new element order. 5595 BitVector InOrder(8); 5596 if (BestLoQuad >= 0) { 5597 SmallVector<int, 8> MaskV; 5598 for (int i = 0; i != 4; ++i) { 5599 int idx = MaskVals[i]; 5600 if (idx < 0) { 5601 MaskV.push_back(-1); 5602 InOrder.set(i); 5603 } else if ((idx / 4) == BestLoQuad) { 5604 MaskV.push_back(idx & 3); 5605 InOrder.set(i); 5606 } else { 5607 MaskV.push_back(-1); 5608 } 5609 } 5610 for (unsigned i = 4; i != 8; ++i) 5611 MaskV.push_back(i); 5612 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5613 &MaskV[0]); 5614 5615 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5616 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5617 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5618 NewV.getOperand(0), 5619 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5620 DAG); 5621 } 5622 5623 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5624 // and update MaskVals with the new element order. 5625 if (BestHiQuad >= 0) { 5626 SmallVector<int, 8> MaskV; 5627 for (unsigned i = 0; i != 4; ++i) 5628 MaskV.push_back(i); 5629 for (unsigned i = 4; i != 8; ++i) { 5630 int idx = MaskVals[i]; 5631 if (idx < 0) { 5632 MaskV.push_back(-1); 5633 InOrder.set(i); 5634 } else if ((idx / 4) == BestHiQuad) { 5635 MaskV.push_back((idx & 3) + 4); 5636 InOrder.set(i); 5637 } else { 5638 MaskV.push_back(-1); 5639 } 5640 } 5641 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5642 &MaskV[0]); 5643 5644 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5645 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5646 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5647 NewV.getOperand(0), 5648 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5649 DAG); 5650 } 5651 5652 // In case BestHi & BestLo were both -1, which means each quadword has a word 5653 // from each of the four input quadwords, calculate the InOrder bitvector now 5654 // before falling through to the insert/extract cleanup. 5655 if (BestLoQuad == -1 && BestHiQuad == -1) { 5656 NewV = V1; 5657 for (int i = 0; i != 8; ++i) 5658 if (MaskVals[i] < 0 || MaskVals[i] == i) 5659 InOrder.set(i); 5660 } 5661 5662 // The other elements are put in the right place using pextrw and pinsrw. 5663 for (unsigned i = 0; i != 8; ++i) { 5664 if (InOrder[i]) 5665 continue; 5666 int EltIdx = MaskVals[i]; 5667 if (EltIdx < 0) 5668 continue; 5669 SDValue ExtOp = (EltIdx < 8) 5670 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5671 DAG.getIntPtrConstant(EltIdx)) 5672 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5673 DAG.getIntPtrConstant(EltIdx - 8)); 5674 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5675 DAG.getIntPtrConstant(i)); 5676 } 5677 return NewV; 5678} 5679 5680// v16i8 shuffles - Prefer shuffles in the following order: 5681// 1. [ssse3] 1 x pshufb 5682// 2. [ssse3] 2 x pshufb + 1 x por 5683// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5684static 5685SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5686 SelectionDAG &DAG, 5687 const X86TargetLowering &TLI) { 5688 SDValue V1 = SVOp->getOperand(0); 5689 SDValue V2 = SVOp->getOperand(1); 5690 DebugLoc dl = SVOp->getDebugLoc(); 5691 SmallVector<int, 16> MaskVals; 5692 SVOp->getMask(MaskVals); 5693 5694 // If we have SSSE3, case 1 is generated when all result bytes come from 5695 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5696 // present, fall back to case 3. 5697 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5698 bool V1Only = true; 5699 bool V2Only = true; 5700 for (unsigned i = 0; i < 16; ++i) { 5701 int EltIdx = MaskVals[i]; 5702 if (EltIdx < 0) 5703 continue; 5704 if (EltIdx < 16) 5705 V2Only = false; 5706 else 5707 V1Only = false; 5708 } 5709 5710 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5711 if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) { 5712 SmallVector<SDValue,16> pshufbMask; 5713 5714 // If all result elements are from one input vector, then only translate 5715 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5716 // 5717 // Otherwise, we have elements from both input vectors, and must zero out 5718 // elements that come from V2 in the first mask, and V1 in the second mask 5719 // so that we can OR them together. 5720 bool TwoInputs = !(V1Only || V2Only); 5721 for (unsigned i = 0; i != 16; ++i) { 5722 int EltIdx = MaskVals[i]; 5723 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5724 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5725 continue; 5726 } 5727 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5728 } 5729 // If all the elements are from V2, assign it to V1 and return after 5730 // building the first pshufb. 5731 if (V2Only) 5732 V1 = V2; 5733 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5734 DAG.getNode(ISD::BUILD_VECTOR, dl, 5735 MVT::v16i8, &pshufbMask[0], 16)); 5736 if (!TwoInputs) 5737 return V1; 5738 5739 // Calculate the shuffle mask for the second input, shuffle it, and 5740 // OR it with the first shuffled input. 5741 pshufbMask.clear(); 5742 for (unsigned i = 0; i != 16; ++i) { 5743 int EltIdx = MaskVals[i]; 5744 if (EltIdx < 16) { 5745 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5746 continue; 5747 } 5748 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5749 } 5750 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5751 DAG.getNode(ISD::BUILD_VECTOR, dl, 5752 MVT::v16i8, &pshufbMask[0], 16)); 5753 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5754 } 5755 5756 // No SSSE3 - Calculate in place words and then fix all out of place words 5757 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5758 // the 16 different words that comprise the two doublequadword input vectors. 5759 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5760 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5761 SDValue NewV = V2Only ? V2 : V1; 5762 for (int i = 0; i != 8; ++i) { 5763 int Elt0 = MaskVals[i*2]; 5764 int Elt1 = MaskVals[i*2+1]; 5765 5766 // This word of the result is all undef, skip it. 5767 if (Elt0 < 0 && Elt1 < 0) 5768 continue; 5769 5770 // This word of the result is already in the correct place, skip it. 5771 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5772 continue; 5773 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5774 continue; 5775 5776 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5777 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5778 SDValue InsElt; 5779 5780 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5781 // using a single extract together, load it and store it. 5782 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5783 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5784 DAG.getIntPtrConstant(Elt1 / 2)); 5785 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5786 DAG.getIntPtrConstant(i)); 5787 continue; 5788 } 5789 5790 // If Elt1 is defined, extract it from the appropriate source. If the 5791 // source byte is not also odd, shift the extracted word left 8 bits 5792 // otherwise clear the bottom 8 bits if we need to do an or. 5793 if (Elt1 >= 0) { 5794 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5795 DAG.getIntPtrConstant(Elt1 / 2)); 5796 if ((Elt1 & 1) == 0) 5797 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5798 DAG.getConstant(8, 5799 TLI.getShiftAmountTy(InsElt.getValueType()))); 5800 else if (Elt0 >= 0) 5801 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5802 DAG.getConstant(0xFF00, MVT::i16)); 5803 } 5804 // If Elt0 is defined, extract it from the appropriate source. If the 5805 // source byte is not also even, shift the extracted word right 8 bits. If 5806 // Elt1 was also defined, OR the extracted values together before 5807 // inserting them in the result. 5808 if (Elt0 >= 0) { 5809 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5810 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5811 if ((Elt0 & 1) != 0) 5812 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5813 DAG.getConstant(8, 5814 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5815 else if (Elt1 >= 0) 5816 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5817 DAG.getConstant(0x00FF, MVT::i16)); 5818 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5819 : InsElt0; 5820 } 5821 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5822 DAG.getIntPtrConstant(i)); 5823 } 5824 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5825} 5826 5827/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5828/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5829/// done when every pair / quad of shuffle mask elements point to elements in 5830/// the right sequence. e.g. 5831/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5832static 5833SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5834 SelectionDAG &DAG, DebugLoc dl) { 5835 EVT VT = SVOp->getValueType(0); 5836 SDValue V1 = SVOp->getOperand(0); 5837 SDValue V2 = SVOp->getOperand(1); 5838 unsigned NumElems = VT.getVectorNumElements(); 5839 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5840 EVT NewVT; 5841 switch (VT.getSimpleVT().SimpleTy) { 5842 default: assert(false && "Unexpected!"); 5843 case MVT::v4f32: NewVT = MVT::v2f64; break; 5844 case MVT::v4i32: NewVT = MVT::v2i64; break; 5845 case MVT::v8i16: NewVT = MVT::v4i32; break; 5846 case MVT::v16i8: NewVT = MVT::v4i32; break; 5847 } 5848 5849 int Scale = NumElems / NewWidth; 5850 SmallVector<int, 8> MaskVec; 5851 for (unsigned i = 0; i < NumElems; i += Scale) { 5852 int StartIdx = -1; 5853 for (int j = 0; j < Scale; ++j) { 5854 int EltIdx = SVOp->getMaskElt(i+j); 5855 if (EltIdx < 0) 5856 continue; 5857 if (StartIdx == -1) 5858 StartIdx = EltIdx - (EltIdx % Scale); 5859 if (EltIdx != StartIdx + j) 5860 return SDValue(); 5861 } 5862 if (StartIdx == -1) 5863 MaskVec.push_back(-1); 5864 else 5865 MaskVec.push_back(StartIdx / Scale); 5866 } 5867 5868 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5869 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5870 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5871} 5872 5873/// getVZextMovL - Return a zero-extending vector move low node. 5874/// 5875static SDValue getVZextMovL(EVT VT, EVT OpVT, 5876 SDValue SrcOp, SelectionDAG &DAG, 5877 const X86Subtarget *Subtarget, DebugLoc dl) { 5878 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5879 LoadSDNode *LD = NULL; 5880 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5881 LD = dyn_cast<LoadSDNode>(SrcOp); 5882 if (!LD) { 5883 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5884 // instead. 5885 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5886 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5887 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5888 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5889 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5890 // PR2108 5891 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5892 return DAG.getNode(ISD::BITCAST, dl, VT, 5893 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5895 OpVT, 5896 SrcOp.getOperand(0) 5897 .getOperand(0)))); 5898 } 5899 } 5900 } 5901 5902 return DAG.getNode(ISD::BITCAST, dl, VT, 5903 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5904 DAG.getNode(ISD::BITCAST, dl, 5905 OpVT, SrcOp))); 5906} 5907 5908/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5909/// shuffle node referes to only one lane in the sources. 5910static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5911 EVT VT = SVOp->getValueType(0); 5912 int NumElems = VT.getVectorNumElements(); 5913 int HalfSize = NumElems/2; 5914 SmallVector<int, 16> M; 5915 SVOp->getMask(M); 5916 bool MatchA = false, MatchB = false; 5917 5918 for (int l = 0; l < NumElems*2; l += HalfSize) { 5919 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5920 MatchA = true; 5921 break; 5922 } 5923 } 5924 5925 for (int l = 0; l < NumElems*2; l += HalfSize) { 5926 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5927 MatchB = true; 5928 break; 5929 } 5930 } 5931 5932 return MatchA && MatchB; 5933} 5934 5935/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5936/// which could not be matched by any known target speficic shuffle 5937static SDValue 5938LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5939 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5940 // If each half of a vector shuffle node referes to only one lane in the 5941 // source vectors, extract each used 128-bit lane and shuffle them using 5942 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5943 // the work to the legalizer. 5944 DebugLoc dl = SVOp->getDebugLoc(); 5945 EVT VT = SVOp->getValueType(0); 5946 int NumElems = VT.getVectorNumElements(); 5947 int HalfSize = NumElems/2; 5948 5949 // Extract the reference for each half 5950 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5951 int FstVecOpNum = 0, SndVecOpNum = 0; 5952 for (int i = 0; i < HalfSize; ++i) { 5953 int Elt = SVOp->getMaskElt(i); 5954 if (SVOp->getMaskElt(i) < 0) 5955 continue; 5956 FstVecOpNum = Elt/NumElems; 5957 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5958 break; 5959 } 5960 for (int i = HalfSize; i < NumElems; ++i) { 5961 int Elt = SVOp->getMaskElt(i); 5962 if (SVOp->getMaskElt(i) < 0) 5963 continue; 5964 SndVecOpNum = Elt/NumElems; 5965 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5966 break; 5967 } 5968 5969 // Extract the subvectors 5970 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 5971 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 5972 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 5973 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 5974 5975 // Generate 128-bit shuffles 5976 SmallVector<int, 16> MaskV1, MaskV2; 5977 for (int i = 0; i < HalfSize; ++i) { 5978 int Elt = SVOp->getMaskElt(i); 5979 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5980 } 5981 for (int i = HalfSize; i < NumElems; ++i) { 5982 int Elt = SVOp->getMaskElt(i); 5983 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5984 } 5985 5986 EVT NVT = V1.getValueType(); 5987 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 5988 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 5989 5990 // Concatenate the result back 5991 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 5992 DAG.getConstant(0, MVT::i32), DAG, dl); 5993 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5994 DAG, dl); 5995 } 5996 5997 return SDValue(); 5998} 5999 6000/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6001/// 4 elements, and match them with several different shuffle types. 6002static SDValue 6003LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6004 SDValue V1 = SVOp->getOperand(0); 6005 SDValue V2 = SVOp->getOperand(1); 6006 DebugLoc dl = SVOp->getDebugLoc(); 6007 EVT VT = SVOp->getValueType(0); 6008 6009 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6010 6011 SmallVector<std::pair<int, int>, 8> Locs; 6012 Locs.resize(4); 6013 SmallVector<int, 8> Mask1(4U, -1); 6014 SmallVector<int, 8> PermMask; 6015 SVOp->getMask(PermMask); 6016 6017 unsigned NumHi = 0; 6018 unsigned NumLo = 0; 6019 for (unsigned i = 0; i != 4; ++i) { 6020 int Idx = PermMask[i]; 6021 if (Idx < 0) { 6022 Locs[i] = std::make_pair(-1, -1); 6023 } else { 6024 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6025 if (Idx < 4) { 6026 Locs[i] = std::make_pair(0, NumLo); 6027 Mask1[NumLo] = Idx; 6028 NumLo++; 6029 } else { 6030 Locs[i] = std::make_pair(1, NumHi); 6031 if (2+NumHi < 4) 6032 Mask1[2+NumHi] = Idx; 6033 NumHi++; 6034 } 6035 } 6036 } 6037 6038 if (NumLo <= 2 && NumHi <= 2) { 6039 // If no more than two elements come from either vector. This can be 6040 // implemented with two shuffles. First shuffle gather the elements. 6041 // The second shuffle, which takes the first shuffle as both of its 6042 // vector operands, put the elements into the right order. 6043 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6044 6045 SmallVector<int, 8> Mask2(4U, -1); 6046 6047 for (unsigned i = 0; i != 4; ++i) { 6048 if (Locs[i].first == -1) 6049 continue; 6050 else { 6051 unsigned Idx = (i < 2) ? 0 : 4; 6052 Idx += Locs[i].first * 2 + Locs[i].second; 6053 Mask2[i] = Idx; 6054 } 6055 } 6056 6057 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6058 } else if (NumLo == 3 || NumHi == 3) { 6059 // Otherwise, we must have three elements from one vector, call it X, and 6060 // one element from the other, call it Y. First, use a shufps to build an 6061 // intermediate vector with the one element from Y and the element from X 6062 // that will be in the same half in the final destination (the indexes don't 6063 // matter). Then, use a shufps to build the final vector, taking the half 6064 // containing the element from Y from the intermediate, and the other half 6065 // from X. 6066 if (NumHi == 3) { 6067 // Normalize it so the 3 elements come from V1. 6068 CommuteVectorShuffleMask(PermMask, VT); 6069 std::swap(V1, V2); 6070 } 6071 6072 // Find the element from V2. 6073 unsigned HiIndex; 6074 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6075 int Val = PermMask[HiIndex]; 6076 if (Val < 0) 6077 continue; 6078 if (Val >= 4) 6079 break; 6080 } 6081 6082 Mask1[0] = PermMask[HiIndex]; 6083 Mask1[1] = -1; 6084 Mask1[2] = PermMask[HiIndex^1]; 6085 Mask1[3] = -1; 6086 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6087 6088 if (HiIndex >= 2) { 6089 Mask1[0] = PermMask[0]; 6090 Mask1[1] = PermMask[1]; 6091 Mask1[2] = HiIndex & 1 ? 6 : 4; 6092 Mask1[3] = HiIndex & 1 ? 4 : 6; 6093 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6094 } else { 6095 Mask1[0] = HiIndex & 1 ? 2 : 0; 6096 Mask1[1] = HiIndex & 1 ? 0 : 2; 6097 Mask1[2] = PermMask[2]; 6098 Mask1[3] = PermMask[3]; 6099 if (Mask1[2] >= 0) 6100 Mask1[2] += 4; 6101 if (Mask1[3] >= 0) 6102 Mask1[3] += 4; 6103 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6104 } 6105 } 6106 6107 // Break it into (shuffle shuffle_hi, shuffle_lo). 6108 Locs.clear(); 6109 Locs.resize(4); 6110 SmallVector<int,8> LoMask(4U, -1); 6111 SmallVector<int,8> HiMask(4U, -1); 6112 6113 SmallVector<int,8> *MaskPtr = &LoMask; 6114 unsigned MaskIdx = 0; 6115 unsigned LoIdx = 0; 6116 unsigned HiIdx = 2; 6117 for (unsigned i = 0; i != 4; ++i) { 6118 if (i == 2) { 6119 MaskPtr = &HiMask; 6120 MaskIdx = 1; 6121 LoIdx = 0; 6122 HiIdx = 2; 6123 } 6124 int Idx = PermMask[i]; 6125 if (Idx < 0) { 6126 Locs[i] = std::make_pair(-1, -1); 6127 } else if (Idx < 4) { 6128 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6129 (*MaskPtr)[LoIdx] = Idx; 6130 LoIdx++; 6131 } else { 6132 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6133 (*MaskPtr)[HiIdx] = Idx; 6134 HiIdx++; 6135 } 6136 } 6137 6138 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6139 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6140 SmallVector<int, 8> MaskOps; 6141 for (unsigned i = 0; i != 4; ++i) { 6142 if (Locs[i].first == -1) { 6143 MaskOps.push_back(-1); 6144 } else { 6145 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6146 MaskOps.push_back(Idx); 6147 } 6148 } 6149 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6150} 6151 6152static bool MayFoldVectorLoad(SDValue V) { 6153 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6154 V = V.getOperand(0); 6155 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6156 V = V.getOperand(0); 6157 if (MayFoldLoad(V)) 6158 return true; 6159 return false; 6160} 6161 6162// FIXME: the version above should always be used. Since there's 6163// a bug where several vector shuffles can't be folded because the 6164// DAG is not updated during lowering and a node claims to have two 6165// uses while it only has one, use this version, and let isel match 6166// another instruction if the load really happens to have more than 6167// one use. Remove this version after this bug get fixed. 6168// rdar://8434668, PR8156 6169static bool RelaxedMayFoldVectorLoad(SDValue V) { 6170 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6171 V = V.getOperand(0); 6172 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6173 V = V.getOperand(0); 6174 if (ISD::isNormalLoad(V.getNode())) 6175 return true; 6176 return false; 6177} 6178 6179/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6180/// a vector extract, and if both can be later optimized into a single load. 6181/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6182/// here because otherwise a target specific shuffle node is going to be 6183/// emitted for this shuffle, and the optimization not done. 6184/// FIXME: This is probably not the best approach, but fix the problem 6185/// until the right path is decided. 6186static 6187bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6188 const TargetLowering &TLI) { 6189 EVT VT = V.getValueType(); 6190 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6191 6192 // Be sure that the vector shuffle is present in a pattern like this: 6193 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6194 if (!V.hasOneUse()) 6195 return false; 6196 6197 SDNode *N = *V.getNode()->use_begin(); 6198 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6199 return false; 6200 6201 SDValue EltNo = N->getOperand(1); 6202 if (!isa<ConstantSDNode>(EltNo)) 6203 return false; 6204 6205 // If the bit convert changed the number of elements, it is unsafe 6206 // to examine the mask. 6207 bool HasShuffleIntoBitcast = false; 6208 if (V.getOpcode() == ISD::BITCAST) { 6209 EVT SrcVT = V.getOperand(0).getValueType(); 6210 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6211 return false; 6212 V = V.getOperand(0); 6213 HasShuffleIntoBitcast = true; 6214 } 6215 6216 // Select the input vector, guarding against out of range extract vector. 6217 unsigned NumElems = VT.getVectorNumElements(); 6218 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6219 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6220 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6221 6222 // Skip one more bit_convert if necessary 6223 if (V.getOpcode() == ISD::BITCAST) 6224 V = V.getOperand(0); 6225 6226 if (ISD::isNormalLoad(V.getNode())) { 6227 // Is the original load suitable? 6228 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6229 6230 // FIXME: avoid the multi-use bug that is preventing lots of 6231 // of foldings to be detected, this is still wrong of course, but 6232 // give the temporary desired behavior, and if it happens that 6233 // the load has real more uses, during isel it will not fold, and 6234 // will generate poor code. 6235 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 6236 return false; 6237 6238 if (!HasShuffleIntoBitcast) 6239 return true; 6240 6241 // If there's a bitcast before the shuffle, check if the load type and 6242 // alignment is valid. 6243 unsigned Align = LN0->getAlignment(); 6244 unsigned NewAlign = 6245 TLI.getTargetData()->getABITypeAlignment( 6246 VT.getTypeForEVT(*DAG.getContext())); 6247 6248 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6249 return false; 6250 } 6251 6252 return true; 6253} 6254 6255static 6256SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6257 EVT VT = Op.getValueType(); 6258 6259 // Canonizalize to v2f64. 6260 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6261 return DAG.getNode(ISD::BITCAST, dl, VT, 6262 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6263 V1, DAG)); 6264} 6265 6266static 6267SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6268 bool HasXMMInt) { 6269 SDValue V1 = Op.getOperand(0); 6270 SDValue V2 = Op.getOperand(1); 6271 EVT VT = Op.getValueType(); 6272 6273 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6274 6275 if (HasXMMInt && VT == MVT::v2f64) 6276 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6277 6278 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6279 return DAG.getNode(ISD::BITCAST, dl, VT, 6280 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6281 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6282 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6283} 6284 6285static 6286SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6287 SDValue V1 = Op.getOperand(0); 6288 SDValue V2 = Op.getOperand(1); 6289 EVT VT = Op.getValueType(); 6290 6291 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6292 "unsupported shuffle type"); 6293 6294 if (V2.getOpcode() == ISD::UNDEF) 6295 V2 = V1; 6296 6297 // v4i32 or v4f32 6298 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6299} 6300 6301static inline unsigned getSHUFPOpcode(EVT VT) { 6302 switch(VT.getSimpleVT().SimpleTy) { 6303 case MVT::v8i32: // Use fp unit for int unpack. 6304 case MVT::v8f32: 6305 case MVT::v4i32: // Use fp unit for int unpack. 6306 case MVT::v4f32: return X86ISD::SHUFPS; 6307 case MVT::v4i64: // Use fp unit for int unpack. 6308 case MVT::v4f64: 6309 case MVT::v2i64: // Use fp unit for int unpack. 6310 case MVT::v2f64: return X86ISD::SHUFPD; 6311 default: 6312 llvm_unreachable("Unknown type for shufp*"); 6313 } 6314 return 0; 6315} 6316 6317static 6318SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) { 6319 SDValue V1 = Op.getOperand(0); 6320 SDValue V2 = Op.getOperand(1); 6321 EVT VT = Op.getValueType(); 6322 unsigned NumElems = VT.getVectorNumElements(); 6323 6324 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6325 // operand of these instructions is only memory, so check if there's a 6326 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6327 // same masks. 6328 bool CanFoldLoad = false; 6329 6330 // Trivial case, when V2 comes from a load. 6331 if (MayFoldVectorLoad(V2)) 6332 CanFoldLoad = true; 6333 6334 // When V1 is a load, it can be folded later into a store in isel, example: 6335 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6336 // turns into: 6337 // (MOVLPSmr addr:$src1, VR128:$src2) 6338 // So, recognize this potential and also use MOVLPS or MOVLPD 6339 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6340 CanFoldLoad = true; 6341 6342 // Both of them can't be memory operations though. 6343 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 6344 CanFoldLoad = false; 6345 6346 if (CanFoldLoad) { 6347 if (HasXMMInt && NumElems == 2) 6348 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6349 6350 if (NumElems == 4) 6351 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6352 } 6353 6354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6355 // movl and movlp will both match v2i64, but v2i64 is never matched by 6356 // movl earlier because we make it strict to avoid messing with the movlp load 6357 // folding logic (see the code above getMOVLP call). Match it here then, 6358 // this is horrible, but will stay like this until we move all shuffle 6359 // matching to x86 specific nodes. Note that for the 1st condition all 6360 // types are matched with movsd. 6361 if (HasXMMInt) { 6362 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6363 // as to remove this logic from here, as much as possible 6364 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6365 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6366 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6367 } 6368 6369 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6370 6371 // Invert the operand order and use SHUFPS to match it. 6372 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, 6373 X86::getShuffleSHUFImmediate(SVOp), DAG); 6374} 6375 6376static inline unsigned getUNPCKLOpcode(EVT VT) { 6377 switch(VT.getSimpleVT().SimpleTy) { 6378 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 6379 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 6380 case MVT::v4f32: return X86ISD::UNPCKLPS; 6381 case MVT::v2f64: return X86ISD::UNPCKLPD; 6382 case MVT::v8i32: // Use fp unit for int unpack. 6383 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 6384 case MVT::v4i64: // Use fp unit for int unpack. 6385 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 6386 case MVT::v16i8: return X86ISD::PUNPCKLBW; 6387 case MVT::v8i16: return X86ISD::PUNPCKLWD; 6388 default: 6389 llvm_unreachable("Unknown type for unpckl"); 6390 } 6391 return 0; 6392} 6393 6394static inline unsigned getUNPCKHOpcode(EVT VT) { 6395 switch(VT.getSimpleVT().SimpleTy) { 6396 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 6397 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 6398 case MVT::v4f32: return X86ISD::UNPCKHPS; 6399 case MVT::v2f64: return X86ISD::UNPCKHPD; 6400 case MVT::v8i32: // Use fp unit for int unpack. 6401 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 6402 case MVT::v4i64: // Use fp unit for int unpack. 6403 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 6404 case MVT::v16i8: return X86ISD::PUNPCKHBW; 6405 case MVT::v8i16: return X86ISD::PUNPCKHWD; 6406 default: 6407 llvm_unreachable("Unknown type for unpckh"); 6408 } 6409 return 0; 6410} 6411 6412static inline unsigned getVPERMILOpcode(EVT VT) { 6413 switch(VT.getSimpleVT().SimpleTy) { 6414 case MVT::v4i32: 6415 case MVT::v4f32: return X86ISD::VPERMILPS; 6416 case MVT::v2i64: 6417 case MVT::v2f64: return X86ISD::VPERMILPD; 6418 case MVT::v8i32: 6419 case MVT::v8f32: return X86ISD::VPERMILPSY; 6420 case MVT::v4i64: 6421 case MVT::v4f64: return X86ISD::VPERMILPDY; 6422 default: 6423 llvm_unreachable("Unknown type for vpermil"); 6424 } 6425 return 0; 6426} 6427 6428/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 6429/// a vbroadcast node. The nodes are suitable whenever we can fold a load coming 6430/// from a 32 or 64 bit scalar. Update Op to the desired load to be folded. 6431static bool isVectorBroadcast(SDValue &Op) { 6432 EVT VT = Op.getValueType(); 6433 bool Is256 = VT.getSizeInBits() == 256; 6434 6435 assert((VT.getSizeInBits() == 128 || Is256) && 6436 "Unsupported type for vbroadcast node"); 6437 6438 SDValue V = Op; 6439 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6440 V = V.getOperand(0); 6441 6442 if (Is256 && !(V.hasOneUse() && 6443 V.getOpcode() == ISD::INSERT_SUBVECTOR && 6444 V.getOperand(0).getOpcode() == ISD::UNDEF)) 6445 return false; 6446 6447 if (Is256) 6448 V = V.getOperand(1); 6449 6450 if (!V.hasOneUse()) 6451 return false; 6452 6453 // Check the source scalar_to_vector type. 256-bit broadcasts are 6454 // supported for 32/64-bit sizes, while 128-bit ones are only supported 6455 // for 32-bit scalars. 6456 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR) 6457 return false; 6458 6459 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits(); 6460 if (ScalarSize != 32 && ScalarSize != 64) 6461 return false; 6462 if (!Is256 && ScalarSize == 64) 6463 return false; 6464 6465 V = V.getOperand(0); 6466 if (!MayFoldLoad(V)) 6467 return false; 6468 6469 // Return the load node 6470 Op = V; 6471 return true; 6472} 6473 6474static 6475SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6476 const TargetLowering &TLI, 6477 const X86Subtarget *Subtarget) { 6478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6479 EVT VT = Op.getValueType(); 6480 DebugLoc dl = Op.getDebugLoc(); 6481 SDValue V1 = Op.getOperand(0); 6482 SDValue V2 = Op.getOperand(1); 6483 6484 if (isZeroShuffle(SVOp)) 6485 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 6486 6487 // Handle splat operations 6488 if (SVOp->isSplat()) { 6489 unsigned NumElem = VT.getVectorNumElements(); 6490 int Size = VT.getSizeInBits(); 6491 // Special case, this is the only place now where it's allowed to return 6492 // a vector_shuffle operation without using a target specific node, because 6493 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6494 // this be moved to DAGCombine instead? 6495 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6496 return Op; 6497 6498 // Use vbroadcast whenever the splat comes from a foldable load 6499 if (Subtarget->hasAVX() && isVectorBroadcast(V1)) 6500 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1); 6501 6502 // Handle splats by matching through known shuffle masks 6503 if ((Size == 128 && NumElem <= 4) || 6504 (Size == 256 && NumElem < 8)) 6505 return SDValue(); 6506 6507 // All remaning splats are promoted to target supported vector shuffles. 6508 return PromoteSplat(SVOp, DAG); 6509 } 6510 6511 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6512 // do it! 6513 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6514 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6515 if (NewOp.getNode()) 6516 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6517 } else if ((VT == MVT::v4i32 || 6518 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) { 6519 // FIXME: Figure out a cleaner way to do this. 6520 // Try to make use of movq to zero out the top part. 6521 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6522 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6523 if (NewOp.getNode()) { 6524 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6525 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6526 DAG, Subtarget, dl); 6527 } 6528 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6529 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6530 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6531 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6532 DAG, Subtarget, dl); 6533 } 6534 } 6535 return SDValue(); 6536} 6537 6538SDValue 6539X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6540 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6541 SDValue V1 = Op.getOperand(0); 6542 SDValue V2 = Op.getOperand(1); 6543 EVT VT = Op.getValueType(); 6544 DebugLoc dl = Op.getDebugLoc(); 6545 unsigned NumElems = VT.getVectorNumElements(); 6546 bool isMMX = VT.getSizeInBits() == 64; 6547 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6548 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6549 bool V1IsSplat = false; 6550 bool V2IsSplat = false; 6551 bool HasXMMInt = Subtarget->hasXMMInt(); 6552 MachineFunction &MF = DAG.getMachineFunction(); 6553 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6554 6555 // Shuffle operations on MMX not supported. 6556 if (isMMX) 6557 return Op; 6558 6559 // Vector shuffle lowering takes 3 steps: 6560 // 6561 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6562 // narrowing and commutation of operands should be handled. 6563 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6564 // shuffle nodes. 6565 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6566 // so the shuffle can be broken into other shuffles and the legalizer can 6567 // try the lowering again. 6568 // 6569 // The general ideia is that no vector_shuffle operation should be left to 6570 // be matched during isel, all of them must be converted to a target specific 6571 // node here. 6572 6573 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6574 // narrowing and commutation of operands should be handled. The actual code 6575 // doesn't include all of those, work in progress... 6576 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6577 if (NewOp.getNode()) 6578 return NewOp; 6579 6580 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6581 // unpckh_undef). Only use pshufd if speed is more important than size. 6582 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6583 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6584 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6585 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6586 6587 if (X86::isMOVDDUPMask(SVOp) && 6588 (Subtarget->hasSSE3() || Subtarget->hasAVX()) && 6589 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6590 return getMOVDDup(Op, dl, V1, DAG); 6591 6592 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6593 return getMOVHighToLow(Op, dl, DAG); 6594 6595 // Use to match splats 6596 if (HasXMMInt && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6597 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6598 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6599 6600 if (X86::isPSHUFDMask(SVOp)) { 6601 // The actual implementation will match the mask in the if above and then 6602 // during isel it can match several different instructions, not only pshufd 6603 // as its name says, sad but true, emulate the behavior for now... 6604 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6605 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6606 6607 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6608 6609 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6610 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6611 6612 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, 6613 TargetMask, DAG); 6614 } 6615 6616 // Check if this can be converted into a logical shift. 6617 bool isLeft = false; 6618 unsigned ShAmt = 0; 6619 SDValue ShVal; 6620 bool isShift = getSubtarget()->hasXMMInt() && 6621 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6622 if (isShift && ShVal.hasOneUse()) { 6623 // If the shifted value has multiple uses, it may be cheaper to use 6624 // v_set0 + movlhps or movhlps, etc. 6625 EVT EltVT = VT.getVectorElementType(); 6626 ShAmt *= EltVT.getSizeInBits(); 6627 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6628 } 6629 6630 if (X86::isMOVLMask(SVOp)) { 6631 if (V1IsUndef) 6632 return V2; 6633 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6634 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6635 if (!X86::isMOVLPMask(SVOp)) { 6636 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6637 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6638 6639 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6640 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6641 } 6642 } 6643 6644 // FIXME: fold these into legal mask. 6645 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6646 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt); 6647 6648 if (X86::isMOVHLPSMask(SVOp)) 6649 return getMOVHighToLow(Op, dl, DAG); 6650 6651 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6652 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6653 6654 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6655 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6656 6657 if (X86::isMOVLPMask(SVOp)) 6658 return getMOVLP(Op, dl, DAG, HasXMMInt); 6659 6660 if (ShouldXformToMOVHLPS(SVOp) || 6661 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6662 return CommuteVectorShuffle(SVOp, DAG); 6663 6664 if (isShift) { 6665 // No better options. Use a vshl / vsrl. 6666 EVT EltVT = VT.getVectorElementType(); 6667 ShAmt *= EltVT.getSizeInBits(); 6668 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6669 } 6670 6671 bool Commuted = false; 6672 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6673 // 1,1,1,1 -> v8i16 though. 6674 V1IsSplat = isSplatVector(V1.getNode()); 6675 V2IsSplat = isSplatVector(V2.getNode()); 6676 6677 // Canonicalize the splat or undef, if present, to be on the RHS. 6678 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6679 Op = CommuteVectorShuffle(SVOp, DAG); 6680 SVOp = cast<ShuffleVectorSDNode>(Op); 6681 V1 = SVOp->getOperand(0); 6682 V2 = SVOp->getOperand(1); 6683 std::swap(V1IsSplat, V2IsSplat); 6684 std::swap(V1IsUndef, V2IsUndef); 6685 Commuted = true; 6686 } 6687 6688 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6689 // Shuffling low element of v1 into undef, just return v1. 6690 if (V2IsUndef) 6691 return V1; 6692 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6693 // the instruction selector will not match, so get a canonical MOVL with 6694 // swapped operands to undo the commute. 6695 return getMOVL(DAG, dl, VT, V2, V1); 6696 } 6697 6698 if (X86::isUNPCKLMask(SVOp)) 6699 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6700 6701 if (X86::isUNPCKHMask(SVOp)) 6702 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6703 6704 if (V2IsSplat) { 6705 // Normalize mask so all entries that point to V2 points to its first 6706 // element then try to match unpck{h|l} again. If match, return a 6707 // new vector_shuffle with the corrected mask. 6708 SDValue NewMask = NormalizeMask(SVOp, DAG); 6709 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6710 if (NSVOp != SVOp) { 6711 if (X86::isUNPCKLMask(NSVOp, true)) { 6712 return NewMask; 6713 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6714 return NewMask; 6715 } 6716 } 6717 } 6718 6719 if (Commuted) { 6720 // Commute is back and try unpck* again. 6721 // FIXME: this seems wrong. 6722 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6723 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6724 6725 if (X86::isUNPCKLMask(NewSVOp)) 6726 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6727 6728 if (X86::isUNPCKHMask(NewSVOp)) 6729 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6730 } 6731 6732 // Normalize the node to match x86 shuffle ops if needed 6733 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6734 return CommuteVectorShuffle(SVOp, DAG); 6735 6736 // The checks below are all present in isShuffleMaskLegal, but they are 6737 // inlined here right now to enable us to directly emit target specific 6738 // nodes, and remove one by one until they don't return Op anymore. 6739 SmallVector<int, 16> M; 6740 SVOp->getMask(M); 6741 6742 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX())) 6743 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6744 X86::getShufflePALIGNRImmediate(SVOp), 6745 DAG); 6746 6747 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6748 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6749 if (VT == MVT::v2f64) 6750 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6751 if (VT == MVT::v2i64) 6752 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6753 } 6754 6755 if (isPSHUFHWMask(M, VT)) 6756 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6757 X86::getShufflePSHUFHWImmediate(SVOp), 6758 DAG); 6759 6760 if (isPSHUFLWMask(M, VT)) 6761 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6762 X86::getShufflePSHUFLWImmediate(SVOp), 6763 DAG); 6764 6765 if (isSHUFPMask(M, VT)) 6766 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6767 X86::getShuffleSHUFImmediate(SVOp), DAG); 6768 6769 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6770 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6771 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6772 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6773 6774 //===--------------------------------------------------------------------===// 6775 // Generate target specific nodes for 128 or 256-bit shuffles only 6776 // supported in the AVX instruction set. 6777 // 6778 6779 // Handle VMOVDDUPY permutations 6780 if (isMOVDDUPYMask(SVOp, Subtarget)) 6781 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6782 6783 // Handle VPERMILPS* permutations 6784 if (isVPERMILPSMask(M, VT, Subtarget)) 6785 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6786 getShuffleVPERMILPSImmediate(SVOp), DAG); 6787 6788 // Handle VPERMILPD* permutations 6789 if (isVPERMILPDMask(M, VT, Subtarget)) 6790 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6791 getShuffleVPERMILPDImmediate(SVOp), DAG); 6792 6793 // Handle VPERM2F128 permutations 6794 if (isVPERM2F128Mask(M, VT, Subtarget)) 6795 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, 6796 getShuffleVPERM2F128Immediate(SVOp), DAG); 6797 6798 // Handle VSHUFPSY permutations 6799 if (isVSHUFPSYMask(M, VT, Subtarget)) 6800 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6801 getShuffleVSHUFPSYImmediate(SVOp), DAG); 6802 6803 // Handle VSHUFPDY permutations 6804 if (isVSHUFPDYMask(M, VT, Subtarget)) 6805 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6806 getShuffleVSHUFPDYImmediate(SVOp), DAG); 6807 6808 //===--------------------------------------------------------------------===// 6809 // Since no target specific shuffle was selected for this generic one, 6810 // lower it into other known shuffles. FIXME: this isn't true yet, but 6811 // this is the plan. 6812 // 6813 6814 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6815 if (VT == MVT::v8i16) { 6816 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6817 if (NewOp.getNode()) 6818 return NewOp; 6819 } 6820 6821 if (VT == MVT::v16i8) { 6822 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6823 if (NewOp.getNode()) 6824 return NewOp; 6825 } 6826 6827 // Handle all 128-bit wide vectors with 4 elements, and match them with 6828 // several different shuffle types. 6829 if (NumElems == 4 && VT.getSizeInBits() == 128) 6830 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6831 6832 // Handle general 256-bit shuffles 6833 if (VT.is256BitVector()) 6834 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6835 6836 return SDValue(); 6837} 6838 6839SDValue 6840X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6841 SelectionDAG &DAG) const { 6842 EVT VT = Op.getValueType(); 6843 DebugLoc dl = Op.getDebugLoc(); 6844 6845 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6846 return SDValue(); 6847 6848 if (VT.getSizeInBits() == 8) { 6849 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6850 Op.getOperand(0), Op.getOperand(1)); 6851 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6852 DAG.getValueType(VT)); 6853 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6854 } else if (VT.getSizeInBits() == 16) { 6855 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6856 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6857 if (Idx == 0) 6858 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6859 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6860 DAG.getNode(ISD::BITCAST, dl, 6861 MVT::v4i32, 6862 Op.getOperand(0)), 6863 Op.getOperand(1))); 6864 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6865 Op.getOperand(0), Op.getOperand(1)); 6866 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6867 DAG.getValueType(VT)); 6868 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6869 } else if (VT == MVT::f32) { 6870 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6871 // the result back to FR32 register. It's only worth matching if the 6872 // result has a single use which is a store or a bitcast to i32. And in 6873 // the case of a store, it's not worth it if the index is a constant 0, 6874 // because a MOVSSmr can be used instead, which is smaller and faster. 6875 if (!Op.hasOneUse()) 6876 return SDValue(); 6877 SDNode *User = *Op.getNode()->use_begin(); 6878 if ((User->getOpcode() != ISD::STORE || 6879 (isa<ConstantSDNode>(Op.getOperand(1)) && 6880 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6881 (User->getOpcode() != ISD::BITCAST || 6882 User->getValueType(0) != MVT::i32)) 6883 return SDValue(); 6884 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6885 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6886 Op.getOperand(0)), 6887 Op.getOperand(1)); 6888 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6889 } else if (VT == MVT::i32) { 6890 // ExtractPS works with constant index. 6891 if (isa<ConstantSDNode>(Op.getOperand(1))) 6892 return Op; 6893 } 6894 return SDValue(); 6895} 6896 6897 6898SDValue 6899X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6900 SelectionDAG &DAG) const { 6901 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6902 return SDValue(); 6903 6904 SDValue Vec = Op.getOperand(0); 6905 EVT VecVT = Vec.getValueType(); 6906 6907 // If this is a 256-bit vector result, first extract the 128-bit vector and 6908 // then extract the element from the 128-bit vector. 6909 if (VecVT.getSizeInBits() == 256) { 6910 DebugLoc dl = Op.getNode()->getDebugLoc(); 6911 unsigned NumElems = VecVT.getVectorNumElements(); 6912 SDValue Idx = Op.getOperand(1); 6913 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6914 6915 // Get the 128-bit vector. 6916 bool Upper = IdxVal >= NumElems/2; 6917 Vec = Extract128BitVector(Vec, 6918 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6919 6920 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6921 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6922 } 6923 6924 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6925 6926 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 6927 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6928 if (Res.getNode()) 6929 return Res; 6930 } 6931 6932 EVT VT = Op.getValueType(); 6933 DebugLoc dl = Op.getDebugLoc(); 6934 // TODO: handle v16i8. 6935 if (VT.getSizeInBits() == 16) { 6936 SDValue Vec = Op.getOperand(0); 6937 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6938 if (Idx == 0) 6939 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6940 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6941 DAG.getNode(ISD::BITCAST, dl, 6942 MVT::v4i32, Vec), 6943 Op.getOperand(1))); 6944 // Transform it so it match pextrw which produces a 32-bit result. 6945 EVT EltVT = MVT::i32; 6946 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6947 Op.getOperand(0), Op.getOperand(1)); 6948 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6949 DAG.getValueType(VT)); 6950 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6951 } else if (VT.getSizeInBits() == 32) { 6952 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6953 if (Idx == 0) 6954 return Op; 6955 6956 // SHUFPS the element to the lowest double word, then movss. 6957 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6958 EVT VVT = Op.getOperand(0).getValueType(); 6959 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6960 DAG.getUNDEF(VVT), Mask); 6961 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6962 DAG.getIntPtrConstant(0)); 6963 } else if (VT.getSizeInBits() == 64) { 6964 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6965 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6966 // to match extract_elt for f64. 6967 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6968 if (Idx == 0) 6969 return Op; 6970 6971 // UNPCKHPD the element to the lowest double word, then movsd. 6972 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6973 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6974 int Mask[2] = { 1, -1 }; 6975 EVT VVT = Op.getOperand(0).getValueType(); 6976 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6977 DAG.getUNDEF(VVT), Mask); 6978 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6979 DAG.getIntPtrConstant(0)); 6980 } 6981 6982 return SDValue(); 6983} 6984 6985SDValue 6986X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6987 SelectionDAG &DAG) const { 6988 EVT VT = Op.getValueType(); 6989 EVT EltVT = VT.getVectorElementType(); 6990 DebugLoc dl = Op.getDebugLoc(); 6991 6992 SDValue N0 = Op.getOperand(0); 6993 SDValue N1 = Op.getOperand(1); 6994 SDValue N2 = Op.getOperand(2); 6995 6996 if (VT.getSizeInBits() == 256) 6997 return SDValue(); 6998 6999 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7000 isa<ConstantSDNode>(N2)) { 7001 unsigned Opc; 7002 if (VT == MVT::v8i16) 7003 Opc = X86ISD::PINSRW; 7004 else if (VT == MVT::v16i8) 7005 Opc = X86ISD::PINSRB; 7006 else 7007 Opc = X86ISD::PINSRB; 7008 7009 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7010 // argument. 7011 if (N1.getValueType() != MVT::i32) 7012 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7013 if (N2.getValueType() != MVT::i32) 7014 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7015 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7016 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7017 // Bits [7:6] of the constant are the source select. This will always be 7018 // zero here. The DAG Combiner may combine an extract_elt index into these 7019 // bits. For example (insert (extract, 3), 2) could be matched by putting 7020 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7021 // Bits [5:4] of the constant are the destination select. This is the 7022 // value of the incoming immediate. 7023 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7024 // combine either bitwise AND or insert of float 0.0 to set these bits. 7025 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7026 // Create this as a scalar to vector.. 7027 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7028 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7029 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 7030 // PINSR* works with constant index. 7031 return Op; 7032 } 7033 return SDValue(); 7034} 7035 7036SDValue 7037X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7038 EVT VT = Op.getValueType(); 7039 EVT EltVT = VT.getVectorElementType(); 7040 7041 DebugLoc dl = Op.getDebugLoc(); 7042 SDValue N0 = Op.getOperand(0); 7043 SDValue N1 = Op.getOperand(1); 7044 SDValue N2 = Op.getOperand(2); 7045 7046 // If this is a 256-bit vector result, first extract the 128-bit vector, 7047 // insert the element into the extracted half and then place it back. 7048 if (VT.getSizeInBits() == 256) { 7049 if (!isa<ConstantSDNode>(N2)) 7050 return SDValue(); 7051 7052 // Get the desired 128-bit vector half. 7053 unsigned NumElems = VT.getVectorNumElements(); 7054 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7055 bool Upper = IdxVal >= NumElems/2; 7056 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 7057 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 7058 7059 // Insert the element into the desired half. 7060 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 7061 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 7062 7063 // Insert the changed part back to the 256-bit vector 7064 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 7065 } 7066 7067 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 7068 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7069 7070 if (EltVT == MVT::i8) 7071 return SDValue(); 7072 7073 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7074 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7075 // as its second argument. 7076 if (N1.getValueType() != MVT::i32) 7077 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7078 if (N2.getValueType() != MVT::i32) 7079 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7080 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7081 } 7082 return SDValue(); 7083} 7084 7085SDValue 7086X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7087 LLVMContext *Context = DAG.getContext(); 7088 DebugLoc dl = Op.getDebugLoc(); 7089 EVT OpVT = Op.getValueType(); 7090 7091 // If this is a 256-bit vector result, first insert into a 128-bit 7092 // vector and then insert into the 256-bit vector. 7093 if (OpVT.getSizeInBits() > 128) { 7094 // Insert into a 128-bit vector. 7095 EVT VT128 = EVT::getVectorVT(*Context, 7096 OpVT.getVectorElementType(), 7097 OpVT.getVectorNumElements() / 2); 7098 7099 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7100 7101 // Insert the 128-bit vector. 7102 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7103 DAG.getConstant(0, MVT::i32), 7104 DAG, dl); 7105 } 7106 7107 if (Op.getValueType() == MVT::v1i64 && 7108 Op.getOperand(0).getValueType() == MVT::i64) 7109 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7110 7111 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7112 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7113 "Expected an SSE type!"); 7114 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7115 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7116} 7117 7118// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7119// a simple subregister reference or explicit instructions to grab 7120// upper bits of a vector. 7121SDValue 7122X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7123 if (Subtarget->hasAVX()) { 7124 DebugLoc dl = Op.getNode()->getDebugLoc(); 7125 SDValue Vec = Op.getNode()->getOperand(0); 7126 SDValue Idx = Op.getNode()->getOperand(1); 7127 7128 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7129 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7130 return Extract128BitVector(Vec, Idx, DAG, dl); 7131 } 7132 } 7133 return SDValue(); 7134} 7135 7136// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7137// simple superregister reference or explicit instructions to insert 7138// the upper bits of a vector. 7139SDValue 7140X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7141 if (Subtarget->hasAVX()) { 7142 DebugLoc dl = Op.getNode()->getDebugLoc(); 7143 SDValue Vec = Op.getNode()->getOperand(0); 7144 SDValue SubVec = Op.getNode()->getOperand(1); 7145 SDValue Idx = Op.getNode()->getOperand(2); 7146 7147 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7148 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7149 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7150 } 7151 } 7152 return SDValue(); 7153} 7154 7155// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7156// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7157// one of the above mentioned nodes. It has to be wrapped because otherwise 7158// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7159// be used to form addressing mode. These wrapped nodes will be selected 7160// into MOV32ri. 7161SDValue 7162X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7163 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7164 7165 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7166 // global base reg. 7167 unsigned char OpFlag = 0; 7168 unsigned WrapperKind = X86ISD::Wrapper; 7169 CodeModel::Model M = getTargetMachine().getCodeModel(); 7170 7171 if (Subtarget->isPICStyleRIPRel() && 7172 (M == CodeModel::Small || M == CodeModel::Kernel)) 7173 WrapperKind = X86ISD::WrapperRIP; 7174 else if (Subtarget->isPICStyleGOT()) 7175 OpFlag = X86II::MO_GOTOFF; 7176 else if (Subtarget->isPICStyleStubPIC()) 7177 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7178 7179 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7180 CP->getAlignment(), 7181 CP->getOffset(), OpFlag); 7182 DebugLoc DL = CP->getDebugLoc(); 7183 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7184 // With PIC, the address is actually $g + Offset. 7185 if (OpFlag) { 7186 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7187 DAG.getNode(X86ISD::GlobalBaseReg, 7188 DebugLoc(), getPointerTy()), 7189 Result); 7190 } 7191 7192 return Result; 7193} 7194 7195SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7196 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7197 7198 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7199 // global base reg. 7200 unsigned char OpFlag = 0; 7201 unsigned WrapperKind = X86ISD::Wrapper; 7202 CodeModel::Model M = getTargetMachine().getCodeModel(); 7203 7204 if (Subtarget->isPICStyleRIPRel() && 7205 (M == CodeModel::Small || M == CodeModel::Kernel)) 7206 WrapperKind = X86ISD::WrapperRIP; 7207 else if (Subtarget->isPICStyleGOT()) 7208 OpFlag = X86II::MO_GOTOFF; 7209 else if (Subtarget->isPICStyleStubPIC()) 7210 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7211 7212 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7213 OpFlag); 7214 DebugLoc DL = JT->getDebugLoc(); 7215 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7216 7217 // With PIC, the address is actually $g + Offset. 7218 if (OpFlag) 7219 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7220 DAG.getNode(X86ISD::GlobalBaseReg, 7221 DebugLoc(), getPointerTy()), 7222 Result); 7223 7224 return Result; 7225} 7226 7227SDValue 7228X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7229 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7230 7231 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7232 // global base reg. 7233 unsigned char OpFlag = 0; 7234 unsigned WrapperKind = X86ISD::Wrapper; 7235 CodeModel::Model M = getTargetMachine().getCodeModel(); 7236 7237 if (Subtarget->isPICStyleRIPRel() && 7238 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7239 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7240 OpFlag = X86II::MO_GOTPCREL; 7241 WrapperKind = X86ISD::WrapperRIP; 7242 } else if (Subtarget->isPICStyleGOT()) { 7243 OpFlag = X86II::MO_GOT; 7244 } else if (Subtarget->isPICStyleStubPIC()) { 7245 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7246 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7247 OpFlag = X86II::MO_DARWIN_NONLAZY; 7248 } 7249 7250 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7251 7252 DebugLoc DL = Op.getDebugLoc(); 7253 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7254 7255 7256 // With PIC, the address is actually $g + Offset. 7257 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7258 !Subtarget->is64Bit()) { 7259 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7260 DAG.getNode(X86ISD::GlobalBaseReg, 7261 DebugLoc(), getPointerTy()), 7262 Result); 7263 } 7264 7265 // For symbols that require a load from a stub to get the address, emit the 7266 // load. 7267 if (isGlobalStubReference(OpFlag)) 7268 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7269 MachinePointerInfo::getGOT(), false, false, 0); 7270 7271 return Result; 7272} 7273 7274SDValue 7275X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7276 // Create the TargetBlockAddressAddress node. 7277 unsigned char OpFlags = 7278 Subtarget->ClassifyBlockAddressReference(); 7279 CodeModel::Model M = getTargetMachine().getCodeModel(); 7280 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7281 DebugLoc dl = Op.getDebugLoc(); 7282 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7283 /*isTarget=*/true, OpFlags); 7284 7285 if (Subtarget->isPICStyleRIPRel() && 7286 (M == CodeModel::Small || M == CodeModel::Kernel)) 7287 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7288 else 7289 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7290 7291 // With PIC, the address is actually $g + Offset. 7292 if (isGlobalRelativeToPICBase(OpFlags)) { 7293 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7294 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7295 Result); 7296 } 7297 7298 return Result; 7299} 7300 7301SDValue 7302X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7303 int64_t Offset, 7304 SelectionDAG &DAG) const { 7305 // Create the TargetGlobalAddress node, folding in the constant 7306 // offset if it is legal. 7307 unsigned char OpFlags = 7308 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7309 CodeModel::Model M = getTargetMachine().getCodeModel(); 7310 SDValue Result; 7311 if (OpFlags == X86II::MO_NO_FLAG && 7312 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7313 // A direct static reference to a global. 7314 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7315 Offset = 0; 7316 } else { 7317 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7318 } 7319 7320 if (Subtarget->isPICStyleRIPRel() && 7321 (M == CodeModel::Small || M == CodeModel::Kernel)) 7322 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7323 else 7324 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7325 7326 // With PIC, the address is actually $g + Offset. 7327 if (isGlobalRelativeToPICBase(OpFlags)) { 7328 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7329 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7330 Result); 7331 } 7332 7333 // For globals that require a load from a stub to get the address, emit the 7334 // load. 7335 if (isGlobalStubReference(OpFlags)) 7336 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7337 MachinePointerInfo::getGOT(), false, false, 0); 7338 7339 // If there was a non-zero offset that we didn't fold, create an explicit 7340 // addition for it. 7341 if (Offset != 0) 7342 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7343 DAG.getConstant(Offset, getPointerTy())); 7344 7345 return Result; 7346} 7347 7348SDValue 7349X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7350 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7351 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7352 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7353} 7354 7355static SDValue 7356GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7357 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7358 unsigned char OperandFlags) { 7359 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7360 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7361 DebugLoc dl = GA->getDebugLoc(); 7362 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7363 GA->getValueType(0), 7364 GA->getOffset(), 7365 OperandFlags); 7366 if (InFlag) { 7367 SDValue Ops[] = { Chain, TGA, *InFlag }; 7368 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7369 } else { 7370 SDValue Ops[] = { Chain, TGA }; 7371 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7372 } 7373 7374 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7375 MFI->setAdjustsStack(true); 7376 7377 SDValue Flag = Chain.getValue(1); 7378 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7379} 7380 7381// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7382static SDValue 7383LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7384 const EVT PtrVT) { 7385 SDValue InFlag; 7386 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7387 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7388 DAG.getNode(X86ISD::GlobalBaseReg, 7389 DebugLoc(), PtrVT), InFlag); 7390 InFlag = Chain.getValue(1); 7391 7392 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7393} 7394 7395// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7396static SDValue 7397LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7398 const EVT PtrVT) { 7399 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7400 X86::RAX, X86II::MO_TLSGD); 7401} 7402 7403// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7404// "local exec" model. 7405static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7406 const EVT PtrVT, TLSModel::Model model, 7407 bool is64Bit) { 7408 DebugLoc dl = GA->getDebugLoc(); 7409 7410 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7411 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7412 is64Bit ? 257 : 256)); 7413 7414 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7415 DAG.getIntPtrConstant(0), 7416 MachinePointerInfo(Ptr), false, false, 0); 7417 7418 unsigned char OperandFlags = 0; 7419 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7420 // initialexec. 7421 unsigned WrapperKind = X86ISD::Wrapper; 7422 if (model == TLSModel::LocalExec) { 7423 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7424 } else if (is64Bit) { 7425 assert(model == TLSModel::InitialExec); 7426 OperandFlags = X86II::MO_GOTTPOFF; 7427 WrapperKind = X86ISD::WrapperRIP; 7428 } else { 7429 assert(model == TLSModel::InitialExec); 7430 OperandFlags = X86II::MO_INDNTPOFF; 7431 } 7432 7433 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7434 // exec) 7435 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7436 GA->getValueType(0), 7437 GA->getOffset(), OperandFlags); 7438 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7439 7440 if (model == TLSModel::InitialExec) 7441 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7442 MachinePointerInfo::getGOT(), false, false, 0); 7443 7444 // The address of the thread local variable is the add of the thread 7445 // pointer with the offset of the variable. 7446 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7447} 7448 7449SDValue 7450X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7451 7452 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7453 const GlobalValue *GV = GA->getGlobal(); 7454 7455 if (Subtarget->isTargetELF()) { 7456 // TODO: implement the "local dynamic" model 7457 // TODO: implement the "initial exec"model for pic executables 7458 7459 // If GV is an alias then use the aliasee for determining 7460 // thread-localness. 7461 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7462 GV = GA->resolveAliasedGlobal(false); 7463 7464 TLSModel::Model model 7465 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7466 7467 switch (model) { 7468 case TLSModel::GeneralDynamic: 7469 case TLSModel::LocalDynamic: // not implemented 7470 if (Subtarget->is64Bit()) 7471 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7472 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7473 7474 case TLSModel::InitialExec: 7475 case TLSModel::LocalExec: 7476 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7477 Subtarget->is64Bit()); 7478 } 7479 } else if (Subtarget->isTargetDarwin()) { 7480 // Darwin only has one model of TLS. Lower to that. 7481 unsigned char OpFlag = 0; 7482 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7483 X86ISD::WrapperRIP : X86ISD::Wrapper; 7484 7485 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7486 // global base reg. 7487 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7488 !Subtarget->is64Bit(); 7489 if (PIC32) 7490 OpFlag = X86II::MO_TLVP_PIC_BASE; 7491 else 7492 OpFlag = X86II::MO_TLVP; 7493 DebugLoc DL = Op.getDebugLoc(); 7494 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7495 GA->getValueType(0), 7496 GA->getOffset(), OpFlag); 7497 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7498 7499 // With PIC32, the address is actually $g + Offset. 7500 if (PIC32) 7501 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7502 DAG.getNode(X86ISD::GlobalBaseReg, 7503 DebugLoc(), getPointerTy()), 7504 Offset); 7505 7506 // Lowering the machine isd will make sure everything is in the right 7507 // location. 7508 SDValue Chain = DAG.getEntryNode(); 7509 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7510 SDValue Args[] = { Chain, Offset }; 7511 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7512 7513 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7514 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7515 MFI->setAdjustsStack(true); 7516 7517 // And our return value (tls address) is in the standard call return value 7518 // location. 7519 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7520 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 7521 } 7522 7523 assert(false && 7524 "TLS not implemented for this target."); 7525 7526 llvm_unreachable("Unreachable"); 7527 return SDValue(); 7528} 7529 7530 7531/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7532/// take a 2 x i32 value to shift plus a shift amount. 7533SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7534 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7535 EVT VT = Op.getValueType(); 7536 unsigned VTBits = VT.getSizeInBits(); 7537 DebugLoc dl = Op.getDebugLoc(); 7538 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7539 SDValue ShOpLo = Op.getOperand(0); 7540 SDValue ShOpHi = Op.getOperand(1); 7541 SDValue ShAmt = Op.getOperand(2); 7542 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7543 DAG.getConstant(VTBits - 1, MVT::i8)) 7544 : DAG.getConstant(0, VT); 7545 7546 SDValue Tmp2, Tmp3; 7547 if (Op.getOpcode() == ISD::SHL_PARTS) { 7548 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7549 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7550 } else { 7551 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7552 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7553 } 7554 7555 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7556 DAG.getConstant(VTBits, MVT::i8)); 7557 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7558 AndNode, DAG.getConstant(0, MVT::i8)); 7559 7560 SDValue Hi, Lo; 7561 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7562 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7563 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7564 7565 if (Op.getOpcode() == ISD::SHL_PARTS) { 7566 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7567 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7568 } else { 7569 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7570 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7571 } 7572 7573 SDValue Ops[2] = { Lo, Hi }; 7574 return DAG.getMergeValues(Ops, 2, dl); 7575} 7576 7577SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7578 SelectionDAG &DAG) const { 7579 EVT SrcVT = Op.getOperand(0).getValueType(); 7580 7581 if (SrcVT.isVector()) 7582 return SDValue(); 7583 7584 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7585 "Unknown SINT_TO_FP to lower!"); 7586 7587 // These are really Legal; return the operand so the caller accepts it as 7588 // Legal. 7589 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7590 return Op; 7591 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7592 Subtarget->is64Bit()) { 7593 return Op; 7594 } 7595 7596 DebugLoc dl = Op.getDebugLoc(); 7597 unsigned Size = SrcVT.getSizeInBits()/8; 7598 MachineFunction &MF = DAG.getMachineFunction(); 7599 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7600 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7601 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7602 StackSlot, 7603 MachinePointerInfo::getFixedStack(SSFI), 7604 false, false, 0); 7605 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7606} 7607 7608SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7609 SDValue StackSlot, 7610 SelectionDAG &DAG) const { 7611 // Build the FILD 7612 DebugLoc DL = Op.getDebugLoc(); 7613 SDVTList Tys; 7614 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7615 if (useSSE) 7616 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7617 else 7618 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7619 7620 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7621 7622 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7623 MachineMemOperand *MMO; 7624 if (FI) { 7625 int SSFI = FI->getIndex(); 7626 MMO = 7627 DAG.getMachineFunction() 7628 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7629 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7630 } else { 7631 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7632 StackSlot = StackSlot.getOperand(1); 7633 } 7634 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7635 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7636 X86ISD::FILD, DL, 7637 Tys, Ops, array_lengthof(Ops), 7638 SrcVT, MMO); 7639 7640 if (useSSE) { 7641 Chain = Result.getValue(1); 7642 SDValue InFlag = Result.getValue(2); 7643 7644 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7645 // shouldn't be necessary except that RFP cannot be live across 7646 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7647 MachineFunction &MF = DAG.getMachineFunction(); 7648 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7649 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7650 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7651 Tys = DAG.getVTList(MVT::Other); 7652 SDValue Ops[] = { 7653 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7654 }; 7655 MachineMemOperand *MMO = 7656 DAG.getMachineFunction() 7657 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7658 MachineMemOperand::MOStore, SSFISize, SSFISize); 7659 7660 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7661 Ops, array_lengthof(Ops), 7662 Op.getValueType(), MMO); 7663 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7664 MachinePointerInfo::getFixedStack(SSFI), 7665 false, false, 0); 7666 } 7667 7668 return Result; 7669} 7670 7671// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7672SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7673 SelectionDAG &DAG) const { 7674 // This algorithm is not obvious. Here it is in C code, more or less: 7675 /* 7676 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7677 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7678 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7679 7680 // Copy ints to xmm registers. 7681 __m128i xh = _mm_cvtsi32_si128( hi ); 7682 __m128i xl = _mm_cvtsi32_si128( lo ); 7683 7684 // Combine into low half of a single xmm register. 7685 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7686 __m128d d; 7687 double sd; 7688 7689 // Merge in appropriate exponents to give the integer bits the right 7690 // magnitude. 7691 x = _mm_unpacklo_epi32( x, exp ); 7692 7693 // Subtract away the biases to deal with the IEEE-754 double precision 7694 // implicit 1. 7695 d = _mm_sub_pd( (__m128d) x, bias ); 7696 7697 // All conversions up to here are exact. The correctly rounded result is 7698 // calculated using the current rounding mode using the following 7699 // horizontal add. 7700 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7701 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7702 // store doesn't really need to be here (except 7703 // maybe to zero the other double) 7704 return sd; 7705 } 7706 */ 7707 7708 DebugLoc dl = Op.getDebugLoc(); 7709 LLVMContext *Context = DAG.getContext(); 7710 7711 // Build some magic constants. 7712 std::vector<Constant*> CV0; 7713 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7714 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7715 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7716 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7717 Constant *C0 = ConstantVector::get(CV0); 7718 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7719 7720 std::vector<Constant*> CV1; 7721 CV1.push_back( 7722 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7723 CV1.push_back( 7724 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7725 Constant *C1 = ConstantVector::get(CV1); 7726 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7727 7728 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7729 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7730 Op.getOperand(0), 7731 DAG.getIntPtrConstant(1))); 7732 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7733 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7734 Op.getOperand(0), 7735 DAG.getIntPtrConstant(0))); 7736 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7737 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7738 MachinePointerInfo::getConstantPool(), 7739 false, false, 16); 7740 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7741 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7742 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7743 MachinePointerInfo::getConstantPool(), 7744 false, false, 16); 7745 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7746 7747 // Add the halves; easiest way is to swap them into another reg first. 7748 int ShufMask[2] = { 1, -1 }; 7749 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7750 DAG.getUNDEF(MVT::v2f64), ShufMask); 7751 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7752 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7753 DAG.getIntPtrConstant(0)); 7754} 7755 7756// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7757SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7758 SelectionDAG &DAG) const { 7759 DebugLoc dl = Op.getDebugLoc(); 7760 // FP constant to bias correct the final result. 7761 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7762 MVT::f64); 7763 7764 // Load the 32-bit value into an XMM register. 7765 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7766 Op.getOperand(0)); 7767 7768 // Zero out the upper parts of the register. 7769 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(), 7770 DAG); 7771 7772 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7773 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7774 DAG.getIntPtrConstant(0)); 7775 7776 // Or the load with the bias. 7777 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7778 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7779 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7780 MVT::v2f64, Load)), 7781 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7782 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7783 MVT::v2f64, Bias))); 7784 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7785 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7786 DAG.getIntPtrConstant(0)); 7787 7788 // Subtract the bias. 7789 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7790 7791 // Handle final rounding. 7792 EVT DestVT = Op.getValueType(); 7793 7794 if (DestVT.bitsLT(MVT::f64)) { 7795 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7796 DAG.getIntPtrConstant(0)); 7797 } else if (DestVT.bitsGT(MVT::f64)) { 7798 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7799 } 7800 7801 // Handle final rounding. 7802 return Sub; 7803} 7804 7805SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7806 SelectionDAG &DAG) const { 7807 SDValue N0 = Op.getOperand(0); 7808 DebugLoc dl = Op.getDebugLoc(); 7809 7810 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7811 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7812 // the optimization here. 7813 if (DAG.SignBitIsZero(N0)) 7814 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7815 7816 EVT SrcVT = N0.getValueType(); 7817 EVT DstVT = Op.getValueType(); 7818 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7819 return LowerUINT_TO_FP_i64(Op, DAG); 7820 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7821 return LowerUINT_TO_FP_i32(Op, DAG); 7822 7823 // Make a 64-bit buffer, and use it to build an FILD. 7824 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7825 if (SrcVT == MVT::i32) { 7826 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7827 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7828 getPointerTy(), StackSlot, WordOff); 7829 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7830 StackSlot, MachinePointerInfo(), 7831 false, false, 0); 7832 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7833 OffsetSlot, MachinePointerInfo(), 7834 false, false, 0); 7835 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7836 return Fild; 7837 } 7838 7839 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7840 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7841 StackSlot, MachinePointerInfo(), 7842 false, false, 0); 7843 // For i64 source, we need to add the appropriate power of 2 if the input 7844 // was negative. This is the same as the optimization in 7845 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7846 // we must be careful to do the computation in x87 extended precision, not 7847 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7848 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7849 MachineMemOperand *MMO = 7850 DAG.getMachineFunction() 7851 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7852 MachineMemOperand::MOLoad, 8, 8); 7853 7854 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7855 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7856 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7857 MVT::i64, MMO); 7858 7859 APInt FF(32, 0x5F800000ULL); 7860 7861 // Check whether the sign bit is set. 7862 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7863 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7864 ISD::SETLT); 7865 7866 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7867 SDValue FudgePtr = DAG.getConstantPool( 7868 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7869 getPointerTy()); 7870 7871 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7872 SDValue Zero = DAG.getIntPtrConstant(0); 7873 SDValue Four = DAG.getIntPtrConstant(4); 7874 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7875 Zero, Four); 7876 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7877 7878 // Load the value out, extending it from f32 to f80. 7879 // FIXME: Avoid the extend by constructing the right constant pool? 7880 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7881 FudgePtr, MachinePointerInfo::getConstantPool(), 7882 MVT::f32, false, false, 4); 7883 // Extend everything to 80 bits to force it to be done on x87. 7884 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7885 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7886} 7887 7888std::pair<SDValue,SDValue> X86TargetLowering:: 7889FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7890 DebugLoc DL = Op.getDebugLoc(); 7891 7892 EVT DstTy = Op.getValueType(); 7893 7894 if (!IsSigned) { 7895 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7896 DstTy = MVT::i64; 7897 } 7898 7899 assert(DstTy.getSimpleVT() <= MVT::i64 && 7900 DstTy.getSimpleVT() >= MVT::i16 && 7901 "Unknown FP_TO_SINT to lower!"); 7902 7903 // These are really Legal. 7904 if (DstTy == MVT::i32 && 7905 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7906 return std::make_pair(SDValue(), SDValue()); 7907 if (Subtarget->is64Bit() && 7908 DstTy == MVT::i64 && 7909 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7910 return std::make_pair(SDValue(), SDValue()); 7911 7912 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7913 // stack slot. 7914 MachineFunction &MF = DAG.getMachineFunction(); 7915 unsigned MemSize = DstTy.getSizeInBits()/8; 7916 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7917 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7918 7919 7920 7921 unsigned Opc; 7922 switch (DstTy.getSimpleVT().SimpleTy) { 7923 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7924 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7925 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7926 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7927 } 7928 7929 SDValue Chain = DAG.getEntryNode(); 7930 SDValue Value = Op.getOperand(0); 7931 EVT TheVT = Op.getOperand(0).getValueType(); 7932 if (isScalarFPTypeInSSEReg(TheVT)) { 7933 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7934 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7935 MachinePointerInfo::getFixedStack(SSFI), 7936 false, false, 0); 7937 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7938 SDValue Ops[] = { 7939 Chain, StackSlot, DAG.getValueType(TheVT) 7940 }; 7941 7942 MachineMemOperand *MMO = 7943 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7944 MachineMemOperand::MOLoad, MemSize, MemSize); 7945 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7946 DstTy, MMO); 7947 Chain = Value.getValue(1); 7948 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7949 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7950 } 7951 7952 MachineMemOperand *MMO = 7953 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7954 MachineMemOperand::MOStore, MemSize, MemSize); 7955 7956 // Build the FP_TO_INT*_IN_MEM 7957 SDValue Ops[] = { Chain, Value, StackSlot }; 7958 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7959 Ops, 3, DstTy, MMO); 7960 7961 return std::make_pair(FIST, StackSlot); 7962} 7963 7964SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7965 SelectionDAG &DAG) const { 7966 if (Op.getValueType().isVector()) 7967 return SDValue(); 7968 7969 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7970 SDValue FIST = Vals.first, StackSlot = Vals.second; 7971 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7972 if (FIST.getNode() == 0) return Op; 7973 7974 // Load the result. 7975 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7976 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7977} 7978 7979SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7980 SelectionDAG &DAG) const { 7981 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7982 SDValue FIST = Vals.first, StackSlot = Vals.second; 7983 assert(FIST.getNode() && "Unexpected failure"); 7984 7985 // Load the result. 7986 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7987 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7988} 7989 7990SDValue X86TargetLowering::LowerFABS(SDValue Op, 7991 SelectionDAG &DAG) const { 7992 LLVMContext *Context = DAG.getContext(); 7993 DebugLoc dl = Op.getDebugLoc(); 7994 EVT VT = Op.getValueType(); 7995 EVT EltVT = VT; 7996 if (VT.isVector()) 7997 EltVT = VT.getVectorElementType(); 7998 std::vector<Constant*> CV; 7999 if (EltVT == MVT::f64) { 8000 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8001 CV.push_back(C); 8002 CV.push_back(C); 8003 } else { 8004 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8005 CV.push_back(C); 8006 CV.push_back(C); 8007 CV.push_back(C); 8008 CV.push_back(C); 8009 } 8010 Constant *C = ConstantVector::get(CV); 8011 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8012 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8013 MachinePointerInfo::getConstantPool(), 8014 false, false, 16); 8015 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8016} 8017 8018SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8019 LLVMContext *Context = DAG.getContext(); 8020 DebugLoc dl = Op.getDebugLoc(); 8021 EVT VT = Op.getValueType(); 8022 EVT EltVT = VT; 8023 if (VT.isVector()) 8024 EltVT = VT.getVectorElementType(); 8025 std::vector<Constant*> CV; 8026 if (EltVT == MVT::f64) { 8027 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8028 CV.push_back(C); 8029 CV.push_back(C); 8030 } else { 8031 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8032 CV.push_back(C); 8033 CV.push_back(C); 8034 CV.push_back(C); 8035 CV.push_back(C); 8036 } 8037 Constant *C = ConstantVector::get(CV); 8038 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8039 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8040 MachinePointerInfo::getConstantPool(), 8041 false, false, 16); 8042 if (VT.isVector()) { 8043 return DAG.getNode(ISD::BITCAST, dl, VT, 8044 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 8045 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8046 Op.getOperand(0)), 8047 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 8048 } else { 8049 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8050 } 8051} 8052 8053SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8054 LLVMContext *Context = DAG.getContext(); 8055 SDValue Op0 = Op.getOperand(0); 8056 SDValue Op1 = Op.getOperand(1); 8057 DebugLoc dl = Op.getDebugLoc(); 8058 EVT VT = Op.getValueType(); 8059 EVT SrcVT = Op1.getValueType(); 8060 8061 // If second operand is smaller, extend it first. 8062 if (SrcVT.bitsLT(VT)) { 8063 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8064 SrcVT = VT; 8065 } 8066 // And if it is bigger, shrink it first. 8067 if (SrcVT.bitsGT(VT)) { 8068 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8069 SrcVT = VT; 8070 } 8071 8072 // At this point the operands and the result should have the same 8073 // type, and that won't be f80 since that is not custom lowered. 8074 8075 // First get the sign bit of second operand. 8076 std::vector<Constant*> CV; 8077 if (SrcVT == MVT::f64) { 8078 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8079 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8080 } else { 8081 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8082 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8083 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8084 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8085 } 8086 Constant *C = ConstantVector::get(CV); 8087 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8088 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8089 MachinePointerInfo::getConstantPool(), 8090 false, false, 16); 8091 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8092 8093 // Shift sign bit right or left if the two operands have different types. 8094 if (SrcVT.bitsGT(VT)) { 8095 // Op0 is MVT::f32, Op1 is MVT::f64. 8096 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8097 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8098 DAG.getConstant(32, MVT::i32)); 8099 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8100 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8101 DAG.getIntPtrConstant(0)); 8102 } 8103 8104 // Clear first operand sign bit. 8105 CV.clear(); 8106 if (VT == MVT::f64) { 8107 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8108 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8109 } else { 8110 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8111 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8112 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8113 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8114 } 8115 C = ConstantVector::get(CV); 8116 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8117 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8118 MachinePointerInfo::getConstantPool(), 8119 false, false, 16); 8120 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8121 8122 // Or the value with the sign bit. 8123 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8124} 8125 8126SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8127 SDValue N0 = Op.getOperand(0); 8128 DebugLoc dl = Op.getDebugLoc(); 8129 EVT VT = Op.getValueType(); 8130 8131 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8132 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8133 DAG.getConstant(1, VT)); 8134 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8135} 8136 8137/// Emit nodes that will be selected as "test Op0,Op0", or something 8138/// equivalent. 8139SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8140 SelectionDAG &DAG) const { 8141 DebugLoc dl = Op.getDebugLoc(); 8142 8143 // CF and OF aren't always set the way we want. Determine which 8144 // of these we need. 8145 bool NeedCF = false; 8146 bool NeedOF = false; 8147 switch (X86CC) { 8148 default: break; 8149 case X86::COND_A: case X86::COND_AE: 8150 case X86::COND_B: case X86::COND_BE: 8151 NeedCF = true; 8152 break; 8153 case X86::COND_G: case X86::COND_GE: 8154 case X86::COND_L: case X86::COND_LE: 8155 case X86::COND_O: case X86::COND_NO: 8156 NeedOF = true; 8157 break; 8158 } 8159 8160 // See if we can use the EFLAGS value from the operand instead of 8161 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8162 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8163 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8164 // Emit a CMP with 0, which is the TEST pattern. 8165 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8166 DAG.getConstant(0, Op.getValueType())); 8167 8168 unsigned Opcode = 0; 8169 unsigned NumOperands = 0; 8170 switch (Op.getNode()->getOpcode()) { 8171 case ISD::ADD: 8172 // Due to an isel shortcoming, be conservative if this add is likely to be 8173 // selected as part of a load-modify-store instruction. When the root node 8174 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8175 // uses of other nodes in the match, such as the ADD in this case. This 8176 // leads to the ADD being left around and reselected, with the result being 8177 // two adds in the output. Alas, even if none our users are stores, that 8178 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8179 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8180 // climbing the DAG back to the root, and it doesn't seem to be worth the 8181 // effort. 8182 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8183 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8184 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 8185 goto default_case; 8186 8187 if (ConstantSDNode *C = 8188 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8189 // An add of one will be selected as an INC. 8190 if (C->getAPIntValue() == 1) { 8191 Opcode = X86ISD::INC; 8192 NumOperands = 1; 8193 break; 8194 } 8195 8196 // An add of negative one (subtract of one) will be selected as a DEC. 8197 if (C->getAPIntValue().isAllOnesValue()) { 8198 Opcode = X86ISD::DEC; 8199 NumOperands = 1; 8200 break; 8201 } 8202 } 8203 8204 // Otherwise use a regular EFLAGS-setting add. 8205 Opcode = X86ISD::ADD; 8206 NumOperands = 2; 8207 break; 8208 case ISD::AND: { 8209 // If the primary and result isn't used, don't bother using X86ISD::AND, 8210 // because a TEST instruction will be better. 8211 bool NonFlagUse = false; 8212 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8213 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8214 SDNode *User = *UI; 8215 unsigned UOpNo = UI.getOperandNo(); 8216 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8217 // Look pass truncate. 8218 UOpNo = User->use_begin().getOperandNo(); 8219 User = *User->use_begin(); 8220 } 8221 8222 if (User->getOpcode() != ISD::BRCOND && 8223 User->getOpcode() != ISD::SETCC && 8224 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8225 NonFlagUse = true; 8226 break; 8227 } 8228 } 8229 8230 if (!NonFlagUse) 8231 break; 8232 } 8233 // FALL THROUGH 8234 case ISD::SUB: 8235 case ISD::OR: 8236 case ISD::XOR: 8237 // Due to the ISEL shortcoming noted above, be conservative if this op is 8238 // likely to be selected as part of a load-modify-store instruction. 8239 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8240 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8241 if (UI->getOpcode() == ISD::STORE) 8242 goto default_case; 8243 8244 // Otherwise use a regular EFLAGS-setting instruction. 8245 switch (Op.getNode()->getOpcode()) { 8246 default: llvm_unreachable("unexpected operator!"); 8247 case ISD::SUB: Opcode = X86ISD::SUB; break; 8248 case ISD::OR: Opcode = X86ISD::OR; break; 8249 case ISD::XOR: Opcode = X86ISD::XOR; break; 8250 case ISD::AND: Opcode = X86ISD::AND; break; 8251 } 8252 8253 NumOperands = 2; 8254 break; 8255 case X86ISD::ADD: 8256 case X86ISD::SUB: 8257 case X86ISD::INC: 8258 case X86ISD::DEC: 8259 case X86ISD::OR: 8260 case X86ISD::XOR: 8261 case X86ISD::AND: 8262 return SDValue(Op.getNode(), 1); 8263 default: 8264 default_case: 8265 break; 8266 } 8267 8268 if (Opcode == 0) 8269 // Emit a CMP with 0, which is the TEST pattern. 8270 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8271 DAG.getConstant(0, Op.getValueType())); 8272 8273 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8274 SmallVector<SDValue, 4> Ops; 8275 for (unsigned i = 0; i != NumOperands; ++i) 8276 Ops.push_back(Op.getOperand(i)); 8277 8278 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8279 DAG.ReplaceAllUsesWith(Op, New); 8280 return SDValue(New.getNode(), 1); 8281} 8282 8283/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8284/// equivalent. 8285SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8286 SelectionDAG &DAG) const { 8287 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8288 if (C->getAPIntValue() == 0) 8289 return EmitTest(Op0, X86CC, DAG); 8290 8291 DebugLoc dl = Op0.getDebugLoc(); 8292 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8293} 8294 8295/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8296/// if it's possible. 8297SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8298 DebugLoc dl, SelectionDAG &DAG) const { 8299 SDValue Op0 = And.getOperand(0); 8300 SDValue Op1 = And.getOperand(1); 8301 if (Op0.getOpcode() == ISD::TRUNCATE) 8302 Op0 = Op0.getOperand(0); 8303 if (Op1.getOpcode() == ISD::TRUNCATE) 8304 Op1 = Op1.getOperand(0); 8305 8306 SDValue LHS, RHS; 8307 if (Op1.getOpcode() == ISD::SHL) 8308 std::swap(Op0, Op1); 8309 if (Op0.getOpcode() == ISD::SHL) { 8310 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8311 if (And00C->getZExtValue() == 1) { 8312 // If we looked past a truncate, check that it's only truncating away 8313 // known zeros. 8314 unsigned BitWidth = Op0.getValueSizeInBits(); 8315 unsigned AndBitWidth = And.getValueSizeInBits(); 8316 if (BitWidth > AndBitWidth) { 8317 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8318 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8319 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8320 return SDValue(); 8321 } 8322 LHS = Op1; 8323 RHS = Op0.getOperand(1); 8324 } 8325 } else if (Op1.getOpcode() == ISD::Constant) { 8326 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8327 SDValue AndLHS = Op0; 8328 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 8329 LHS = AndLHS.getOperand(0); 8330 RHS = AndLHS.getOperand(1); 8331 } 8332 } 8333 8334 if (LHS.getNode()) { 8335 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8336 // instruction. Since the shift amount is in-range-or-undefined, we know 8337 // that doing a bittest on the i32 value is ok. We extend to i32 because 8338 // the encoding for the i16 version is larger than the i32 version. 8339 // Also promote i16 to i32 for performance / code size reason. 8340 if (LHS.getValueType() == MVT::i8 || 8341 LHS.getValueType() == MVT::i16) 8342 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8343 8344 // If the operand types disagree, extend the shift amount to match. Since 8345 // BT ignores high bits (like shifts) we can use anyextend. 8346 if (LHS.getValueType() != RHS.getValueType()) 8347 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8348 8349 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8350 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8351 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8352 DAG.getConstant(Cond, MVT::i8), BT); 8353 } 8354 8355 return SDValue(); 8356} 8357 8358SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8359 8360 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8361 8362 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8363 SDValue Op0 = Op.getOperand(0); 8364 SDValue Op1 = Op.getOperand(1); 8365 DebugLoc dl = Op.getDebugLoc(); 8366 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8367 8368 // Optimize to BT if possible. 8369 // Lower (X & (1 << N)) == 0 to BT(X, N). 8370 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8371 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8372 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8373 Op1.getOpcode() == ISD::Constant && 8374 cast<ConstantSDNode>(Op1)->isNullValue() && 8375 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8376 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8377 if (NewSetCC.getNode()) 8378 return NewSetCC; 8379 } 8380 8381 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8382 // these. 8383 if (Op1.getOpcode() == ISD::Constant && 8384 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8385 cast<ConstantSDNode>(Op1)->isNullValue()) && 8386 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8387 8388 // If the input is a setcc, then reuse the input setcc or use a new one with 8389 // the inverted condition. 8390 if (Op0.getOpcode() == X86ISD::SETCC) { 8391 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8392 bool Invert = (CC == ISD::SETNE) ^ 8393 cast<ConstantSDNode>(Op1)->isNullValue(); 8394 if (!Invert) return Op0; 8395 8396 CCode = X86::GetOppositeBranchCondition(CCode); 8397 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8398 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8399 } 8400 } 8401 8402 bool isFP = Op1.getValueType().isFloatingPoint(); 8403 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8404 if (X86CC == X86::COND_INVALID) 8405 return SDValue(); 8406 8407 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8408 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8409 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8410} 8411 8412// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8413// ones, and then concatenate the result back. 8414static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8415 EVT VT = Op.getValueType(); 8416 8417 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8418 "Unsupported value type for operation"); 8419 8420 int NumElems = VT.getVectorNumElements(); 8421 DebugLoc dl = Op.getDebugLoc(); 8422 SDValue CC = Op.getOperand(2); 8423 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8424 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8425 8426 // Extract the LHS vectors 8427 SDValue LHS = Op.getOperand(0); 8428 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8429 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8430 8431 // Extract the RHS vectors 8432 SDValue RHS = Op.getOperand(1); 8433 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8434 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8435 8436 // Issue the operation on the smaller types and concatenate the result back 8437 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8438 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8439 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8440 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8441 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8442} 8443 8444 8445SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8446 SDValue Cond; 8447 SDValue Op0 = Op.getOperand(0); 8448 SDValue Op1 = Op.getOperand(1); 8449 SDValue CC = Op.getOperand(2); 8450 EVT VT = Op.getValueType(); 8451 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8452 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8453 DebugLoc dl = Op.getDebugLoc(); 8454 8455 if (isFP) { 8456 unsigned SSECC = 8; 8457 EVT EltVT = Op0.getValueType().getVectorElementType(); 8458 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8459 8460 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8461 bool Swap = false; 8462 8463 // SSE Condition code mapping: 8464 // 0 - EQ 8465 // 1 - LT 8466 // 2 - LE 8467 // 3 - UNORD 8468 // 4 - NEQ 8469 // 5 - NLT 8470 // 6 - NLE 8471 // 7 - ORD 8472 switch (SetCCOpcode) { 8473 default: break; 8474 case ISD::SETOEQ: 8475 case ISD::SETEQ: SSECC = 0; break; 8476 case ISD::SETOGT: 8477 case ISD::SETGT: Swap = true; // Fallthrough 8478 case ISD::SETLT: 8479 case ISD::SETOLT: SSECC = 1; break; 8480 case ISD::SETOGE: 8481 case ISD::SETGE: Swap = true; // Fallthrough 8482 case ISD::SETLE: 8483 case ISD::SETOLE: SSECC = 2; break; 8484 case ISD::SETUO: SSECC = 3; break; 8485 case ISD::SETUNE: 8486 case ISD::SETNE: SSECC = 4; break; 8487 case ISD::SETULE: Swap = true; 8488 case ISD::SETUGE: SSECC = 5; break; 8489 case ISD::SETULT: Swap = true; 8490 case ISD::SETUGT: SSECC = 6; break; 8491 case ISD::SETO: SSECC = 7; break; 8492 } 8493 if (Swap) 8494 std::swap(Op0, Op1); 8495 8496 // In the two special cases we can't handle, emit two comparisons. 8497 if (SSECC == 8) { 8498 if (SetCCOpcode == ISD::SETUEQ) { 8499 SDValue UNORD, EQ; 8500 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8501 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8502 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8503 } 8504 else if (SetCCOpcode == ISD::SETONE) { 8505 SDValue ORD, NEQ; 8506 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8507 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8508 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8509 } 8510 llvm_unreachable("Illegal FP comparison"); 8511 } 8512 // Handle all other FP comparisons here. 8513 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8514 } 8515 8516 // Break 256-bit integer vector compare into smaller ones. 8517 if (!isFP && VT.getSizeInBits() == 256) 8518 return Lower256IntVSETCC(Op, DAG); 8519 8520 // We are handling one of the integer comparisons here. Since SSE only has 8521 // GT and EQ comparisons for integer, swapping operands and multiple 8522 // operations may be required for some comparisons. 8523 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8524 bool Swap = false, Invert = false, FlipSigns = false; 8525 8526 switch (VT.getSimpleVT().SimpleTy) { 8527 default: break; 8528 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8529 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8530 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8531 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8532 } 8533 8534 switch (SetCCOpcode) { 8535 default: break; 8536 case ISD::SETNE: Invert = true; 8537 case ISD::SETEQ: Opc = EQOpc; break; 8538 case ISD::SETLT: Swap = true; 8539 case ISD::SETGT: Opc = GTOpc; break; 8540 case ISD::SETGE: Swap = true; 8541 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8542 case ISD::SETULT: Swap = true; 8543 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8544 case ISD::SETUGE: Swap = true; 8545 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8546 } 8547 if (Swap) 8548 std::swap(Op0, Op1); 8549 8550 // Check that the operation in question is available (most are plain SSE2, 8551 // but PCMPGTQ and PCMPEQQ have different requirements). 8552 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX()) 8553 return SDValue(); 8554 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX()) 8555 return SDValue(); 8556 8557 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8558 // bits of the inputs before performing those operations. 8559 if (FlipSigns) { 8560 EVT EltVT = VT.getVectorElementType(); 8561 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8562 EltVT); 8563 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8564 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8565 SignBits.size()); 8566 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8567 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8568 } 8569 8570 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8571 8572 // If the logical-not of the result is required, perform that now. 8573 if (Invert) 8574 Result = DAG.getNOT(dl, Result, VT); 8575 8576 return Result; 8577} 8578 8579// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8580static bool isX86LogicalCmp(SDValue Op) { 8581 unsigned Opc = Op.getNode()->getOpcode(); 8582 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8583 return true; 8584 if (Op.getResNo() == 1 && 8585 (Opc == X86ISD::ADD || 8586 Opc == X86ISD::SUB || 8587 Opc == X86ISD::ADC || 8588 Opc == X86ISD::SBB || 8589 Opc == X86ISD::SMUL || 8590 Opc == X86ISD::UMUL || 8591 Opc == X86ISD::INC || 8592 Opc == X86ISD::DEC || 8593 Opc == X86ISD::OR || 8594 Opc == X86ISD::XOR || 8595 Opc == X86ISD::AND)) 8596 return true; 8597 8598 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8599 return true; 8600 8601 return false; 8602} 8603 8604static bool isZero(SDValue V) { 8605 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8606 return C && C->isNullValue(); 8607} 8608 8609static bool isAllOnes(SDValue V) { 8610 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8611 return C && C->isAllOnesValue(); 8612} 8613 8614SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8615 bool addTest = true; 8616 SDValue Cond = Op.getOperand(0); 8617 SDValue Op1 = Op.getOperand(1); 8618 SDValue Op2 = Op.getOperand(2); 8619 DebugLoc DL = Op.getDebugLoc(); 8620 SDValue CC; 8621 8622 if (Cond.getOpcode() == ISD::SETCC) { 8623 SDValue NewCond = LowerSETCC(Cond, DAG); 8624 if (NewCond.getNode()) 8625 Cond = NewCond; 8626 } 8627 8628 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8629 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8630 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8631 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8632 if (Cond.getOpcode() == X86ISD::SETCC && 8633 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8634 isZero(Cond.getOperand(1).getOperand(1))) { 8635 SDValue Cmp = Cond.getOperand(1); 8636 8637 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8638 8639 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8640 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8641 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8642 8643 SDValue CmpOp0 = Cmp.getOperand(0); 8644 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8645 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8646 8647 SDValue Res = // Res = 0 or -1. 8648 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8649 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8650 8651 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8652 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8653 8654 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8655 if (N2C == 0 || !N2C->isNullValue()) 8656 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8657 return Res; 8658 } 8659 } 8660 8661 // Look past (and (setcc_carry (cmp ...)), 1). 8662 if (Cond.getOpcode() == ISD::AND && 8663 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8665 if (C && C->getAPIntValue() == 1) 8666 Cond = Cond.getOperand(0); 8667 } 8668 8669 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8670 // setting operand in place of the X86ISD::SETCC. 8671 if (Cond.getOpcode() == X86ISD::SETCC || 8672 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8673 CC = Cond.getOperand(0); 8674 8675 SDValue Cmp = Cond.getOperand(1); 8676 unsigned Opc = Cmp.getOpcode(); 8677 EVT VT = Op.getValueType(); 8678 8679 bool IllegalFPCMov = false; 8680 if (VT.isFloatingPoint() && !VT.isVector() && 8681 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8682 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8683 8684 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8685 Opc == X86ISD::BT) { // FIXME 8686 Cond = Cmp; 8687 addTest = false; 8688 } 8689 } 8690 8691 if (addTest) { 8692 // Look pass the truncate. 8693 if (Cond.getOpcode() == ISD::TRUNCATE) 8694 Cond = Cond.getOperand(0); 8695 8696 // We know the result of AND is compared against zero. Try to match 8697 // it to BT. 8698 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8699 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8700 if (NewSetCC.getNode()) { 8701 CC = NewSetCC.getOperand(0); 8702 Cond = NewSetCC.getOperand(1); 8703 addTest = false; 8704 } 8705 } 8706 } 8707 8708 if (addTest) { 8709 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8710 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8711 } 8712 8713 // a < b ? -1 : 0 -> RES = ~setcc_carry 8714 // a < b ? 0 : -1 -> RES = setcc_carry 8715 // a >= b ? -1 : 0 -> RES = setcc_carry 8716 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8717 if (Cond.getOpcode() == X86ISD::CMP) { 8718 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8719 8720 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8721 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8722 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8723 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8724 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8725 return DAG.getNOT(DL, Res, Res.getValueType()); 8726 return Res; 8727 } 8728 } 8729 8730 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8731 // condition is true. 8732 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8733 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8734 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8735} 8736 8737// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8738// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8739// from the AND / OR. 8740static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8741 Opc = Op.getOpcode(); 8742 if (Opc != ISD::OR && Opc != ISD::AND) 8743 return false; 8744 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8745 Op.getOperand(0).hasOneUse() && 8746 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8747 Op.getOperand(1).hasOneUse()); 8748} 8749 8750// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8751// 1 and that the SETCC node has a single use. 8752static bool isXor1OfSetCC(SDValue Op) { 8753 if (Op.getOpcode() != ISD::XOR) 8754 return false; 8755 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8756 if (N1C && N1C->getAPIntValue() == 1) { 8757 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8758 Op.getOperand(0).hasOneUse(); 8759 } 8760 return false; 8761} 8762 8763SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8764 bool addTest = true; 8765 SDValue Chain = Op.getOperand(0); 8766 SDValue Cond = Op.getOperand(1); 8767 SDValue Dest = Op.getOperand(2); 8768 DebugLoc dl = Op.getDebugLoc(); 8769 SDValue CC; 8770 8771 if (Cond.getOpcode() == ISD::SETCC) { 8772 SDValue NewCond = LowerSETCC(Cond, DAG); 8773 if (NewCond.getNode()) 8774 Cond = NewCond; 8775 } 8776#if 0 8777 // FIXME: LowerXALUO doesn't handle these!! 8778 else if (Cond.getOpcode() == X86ISD::ADD || 8779 Cond.getOpcode() == X86ISD::SUB || 8780 Cond.getOpcode() == X86ISD::SMUL || 8781 Cond.getOpcode() == X86ISD::UMUL) 8782 Cond = LowerXALUO(Cond, DAG); 8783#endif 8784 8785 // Look pass (and (setcc_carry (cmp ...)), 1). 8786 if (Cond.getOpcode() == ISD::AND && 8787 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8789 if (C && C->getAPIntValue() == 1) 8790 Cond = Cond.getOperand(0); 8791 } 8792 8793 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8794 // setting operand in place of the X86ISD::SETCC. 8795 if (Cond.getOpcode() == X86ISD::SETCC || 8796 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8797 CC = Cond.getOperand(0); 8798 8799 SDValue Cmp = Cond.getOperand(1); 8800 unsigned Opc = Cmp.getOpcode(); 8801 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8802 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8803 Cond = Cmp; 8804 addTest = false; 8805 } else { 8806 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8807 default: break; 8808 case X86::COND_O: 8809 case X86::COND_B: 8810 // These can only come from an arithmetic instruction with overflow, 8811 // e.g. SADDO, UADDO. 8812 Cond = Cond.getNode()->getOperand(1); 8813 addTest = false; 8814 break; 8815 } 8816 } 8817 } else { 8818 unsigned CondOpc; 8819 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8820 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8821 if (CondOpc == ISD::OR) { 8822 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8823 // two branches instead of an explicit OR instruction with a 8824 // separate test. 8825 if (Cmp == Cond.getOperand(1).getOperand(1) && 8826 isX86LogicalCmp(Cmp)) { 8827 CC = Cond.getOperand(0).getOperand(0); 8828 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8829 Chain, Dest, CC, Cmp); 8830 CC = Cond.getOperand(1).getOperand(0); 8831 Cond = Cmp; 8832 addTest = false; 8833 } 8834 } else { // ISD::AND 8835 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8836 // two branches instead of an explicit AND instruction with a 8837 // separate test. However, we only do this if this block doesn't 8838 // have a fall-through edge, because this requires an explicit 8839 // jmp when the condition is false. 8840 if (Cmp == Cond.getOperand(1).getOperand(1) && 8841 isX86LogicalCmp(Cmp) && 8842 Op.getNode()->hasOneUse()) { 8843 X86::CondCode CCode = 8844 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8845 CCode = X86::GetOppositeBranchCondition(CCode); 8846 CC = DAG.getConstant(CCode, MVT::i8); 8847 SDNode *User = *Op.getNode()->use_begin(); 8848 // Look for an unconditional branch following this conditional branch. 8849 // We need this because we need to reverse the successors in order 8850 // to implement FCMP_OEQ. 8851 if (User->getOpcode() == ISD::BR) { 8852 SDValue FalseBB = User->getOperand(1); 8853 SDNode *NewBR = 8854 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8855 assert(NewBR == User); 8856 (void)NewBR; 8857 Dest = FalseBB; 8858 8859 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8860 Chain, Dest, CC, Cmp); 8861 X86::CondCode CCode = 8862 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8863 CCode = X86::GetOppositeBranchCondition(CCode); 8864 CC = DAG.getConstant(CCode, MVT::i8); 8865 Cond = Cmp; 8866 addTest = false; 8867 } 8868 } 8869 } 8870 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8871 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8872 // It should be transformed during dag combiner except when the condition 8873 // is set by a arithmetics with overflow node. 8874 X86::CondCode CCode = 8875 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8876 CCode = X86::GetOppositeBranchCondition(CCode); 8877 CC = DAG.getConstant(CCode, MVT::i8); 8878 Cond = Cond.getOperand(0).getOperand(1); 8879 addTest = false; 8880 } 8881 } 8882 8883 if (addTest) { 8884 // Look pass the truncate. 8885 if (Cond.getOpcode() == ISD::TRUNCATE) 8886 Cond = Cond.getOperand(0); 8887 8888 // We know the result of AND is compared against zero. Try to match 8889 // it to BT. 8890 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8891 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8892 if (NewSetCC.getNode()) { 8893 CC = NewSetCC.getOperand(0); 8894 Cond = NewSetCC.getOperand(1); 8895 addTest = false; 8896 } 8897 } 8898 } 8899 8900 if (addTest) { 8901 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8902 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8903 } 8904 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8905 Chain, Dest, CC, Cond); 8906} 8907 8908 8909// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8910// Calls to _alloca is needed to probe the stack when allocating more than 4k 8911// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8912// that the guard pages used by the OS virtual memory manager are allocated in 8913// correct sequence. 8914SDValue 8915X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8916 SelectionDAG &DAG) const { 8917 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8918 EnableSegmentedStacks) && 8919 "This should be used only on Windows targets or when segmented stacks " 8920 "are being used"); 8921 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8922 DebugLoc dl = Op.getDebugLoc(); 8923 8924 // Get the inputs. 8925 SDValue Chain = Op.getOperand(0); 8926 SDValue Size = Op.getOperand(1); 8927 // FIXME: Ensure alignment here 8928 8929 bool Is64Bit = Subtarget->is64Bit(); 8930 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8931 8932 if (EnableSegmentedStacks) { 8933 MachineFunction &MF = DAG.getMachineFunction(); 8934 MachineRegisterInfo &MRI = MF.getRegInfo(); 8935 8936 if (Is64Bit) { 8937 // The 64 bit implementation of segmented stacks needs to clobber both r10 8938 // r11. This makes it impossible to use it along with nested parameters. 8939 const Function *F = MF.getFunction(); 8940 8941 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8942 I != E; I++) 8943 if (I->hasNestAttr()) 8944 report_fatal_error("Cannot use segmented stacks with functions that " 8945 "have nested arguments."); 8946 } 8947 8948 const TargetRegisterClass *AddrRegClass = 8949 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8950 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8951 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8952 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8953 DAG.getRegister(Vreg, SPTy)); 8954 SDValue Ops1[2] = { Value, Chain }; 8955 return DAG.getMergeValues(Ops1, 2, dl); 8956 } else { 8957 SDValue Flag; 8958 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8959 8960 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8961 Flag = Chain.getValue(1); 8962 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8963 8964 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8965 Flag = Chain.getValue(1); 8966 8967 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8968 8969 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8970 return DAG.getMergeValues(Ops1, 2, dl); 8971 } 8972} 8973 8974SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8975 MachineFunction &MF = DAG.getMachineFunction(); 8976 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8977 8978 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8979 DebugLoc DL = Op.getDebugLoc(); 8980 8981 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8982 // vastart just stores the address of the VarArgsFrameIndex slot into the 8983 // memory location argument. 8984 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8985 getPointerTy()); 8986 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8987 MachinePointerInfo(SV), false, false, 0); 8988 } 8989 8990 // __va_list_tag: 8991 // gp_offset (0 - 6 * 8) 8992 // fp_offset (48 - 48 + 8 * 16) 8993 // overflow_arg_area (point to parameters coming in memory). 8994 // reg_save_area 8995 SmallVector<SDValue, 8> MemOps; 8996 SDValue FIN = Op.getOperand(1); 8997 // Store gp_offset 8998 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8999 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9000 MVT::i32), 9001 FIN, MachinePointerInfo(SV), false, false, 0); 9002 MemOps.push_back(Store); 9003 9004 // Store fp_offset 9005 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9006 FIN, DAG.getIntPtrConstant(4)); 9007 Store = DAG.getStore(Op.getOperand(0), DL, 9008 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9009 MVT::i32), 9010 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9011 MemOps.push_back(Store); 9012 9013 // Store ptr to overflow_arg_area 9014 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9015 FIN, DAG.getIntPtrConstant(4)); 9016 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9017 getPointerTy()); 9018 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9019 MachinePointerInfo(SV, 8), 9020 false, false, 0); 9021 MemOps.push_back(Store); 9022 9023 // Store ptr to reg_save_area. 9024 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9025 FIN, DAG.getIntPtrConstant(8)); 9026 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9027 getPointerTy()); 9028 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9029 MachinePointerInfo(SV, 16), false, false, 0); 9030 MemOps.push_back(Store); 9031 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9032 &MemOps[0], MemOps.size()); 9033} 9034 9035SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9036 assert(Subtarget->is64Bit() && 9037 "LowerVAARG only handles 64-bit va_arg!"); 9038 assert((Subtarget->isTargetLinux() || 9039 Subtarget->isTargetDarwin()) && 9040 "Unhandled target in LowerVAARG"); 9041 assert(Op.getNode()->getNumOperands() == 4); 9042 SDValue Chain = Op.getOperand(0); 9043 SDValue SrcPtr = Op.getOperand(1); 9044 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9045 unsigned Align = Op.getConstantOperandVal(3); 9046 DebugLoc dl = Op.getDebugLoc(); 9047 9048 EVT ArgVT = Op.getNode()->getValueType(0); 9049 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9050 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9051 uint8_t ArgMode; 9052 9053 // Decide which area this value should be read from. 9054 // TODO: Implement the AMD64 ABI in its entirety. This simple 9055 // selection mechanism works only for the basic types. 9056 if (ArgVT == MVT::f80) { 9057 llvm_unreachable("va_arg for f80 not yet implemented"); 9058 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9059 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9060 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9061 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9062 } else { 9063 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9064 } 9065 9066 if (ArgMode == 2) { 9067 // Sanity Check: Make sure using fp_offset makes sense. 9068 assert(!UseSoftFloat && 9069 !(DAG.getMachineFunction() 9070 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9071 Subtarget->hasXMM()); 9072 } 9073 9074 // Insert VAARG_64 node into the DAG 9075 // VAARG_64 returns two values: Variable Argument Address, Chain 9076 SmallVector<SDValue, 11> InstOps; 9077 InstOps.push_back(Chain); 9078 InstOps.push_back(SrcPtr); 9079 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9080 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9081 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9082 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9083 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9084 VTs, &InstOps[0], InstOps.size(), 9085 MVT::i64, 9086 MachinePointerInfo(SV), 9087 /*Align=*/0, 9088 /*Volatile=*/false, 9089 /*ReadMem=*/true, 9090 /*WriteMem=*/true); 9091 Chain = VAARG.getValue(1); 9092 9093 // Load the next argument and return it 9094 return DAG.getLoad(ArgVT, dl, 9095 Chain, 9096 VAARG, 9097 MachinePointerInfo(), 9098 false, false, 0); 9099} 9100 9101SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9102 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9103 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9104 SDValue Chain = Op.getOperand(0); 9105 SDValue DstPtr = Op.getOperand(1); 9106 SDValue SrcPtr = Op.getOperand(2); 9107 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9108 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9109 DebugLoc DL = Op.getDebugLoc(); 9110 9111 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9112 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9113 false, 9114 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9115} 9116 9117SDValue 9118X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9119 DebugLoc dl = Op.getDebugLoc(); 9120 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9121 switch (IntNo) { 9122 default: return SDValue(); // Don't custom lower most intrinsics. 9123 // Comparison intrinsics. 9124 case Intrinsic::x86_sse_comieq_ss: 9125 case Intrinsic::x86_sse_comilt_ss: 9126 case Intrinsic::x86_sse_comile_ss: 9127 case Intrinsic::x86_sse_comigt_ss: 9128 case Intrinsic::x86_sse_comige_ss: 9129 case Intrinsic::x86_sse_comineq_ss: 9130 case Intrinsic::x86_sse_ucomieq_ss: 9131 case Intrinsic::x86_sse_ucomilt_ss: 9132 case Intrinsic::x86_sse_ucomile_ss: 9133 case Intrinsic::x86_sse_ucomigt_ss: 9134 case Intrinsic::x86_sse_ucomige_ss: 9135 case Intrinsic::x86_sse_ucomineq_ss: 9136 case Intrinsic::x86_sse2_comieq_sd: 9137 case Intrinsic::x86_sse2_comilt_sd: 9138 case Intrinsic::x86_sse2_comile_sd: 9139 case Intrinsic::x86_sse2_comigt_sd: 9140 case Intrinsic::x86_sse2_comige_sd: 9141 case Intrinsic::x86_sse2_comineq_sd: 9142 case Intrinsic::x86_sse2_ucomieq_sd: 9143 case Intrinsic::x86_sse2_ucomilt_sd: 9144 case Intrinsic::x86_sse2_ucomile_sd: 9145 case Intrinsic::x86_sse2_ucomigt_sd: 9146 case Intrinsic::x86_sse2_ucomige_sd: 9147 case Intrinsic::x86_sse2_ucomineq_sd: { 9148 unsigned Opc = 0; 9149 ISD::CondCode CC = ISD::SETCC_INVALID; 9150 switch (IntNo) { 9151 default: break; 9152 case Intrinsic::x86_sse_comieq_ss: 9153 case Intrinsic::x86_sse2_comieq_sd: 9154 Opc = X86ISD::COMI; 9155 CC = ISD::SETEQ; 9156 break; 9157 case Intrinsic::x86_sse_comilt_ss: 9158 case Intrinsic::x86_sse2_comilt_sd: 9159 Opc = X86ISD::COMI; 9160 CC = ISD::SETLT; 9161 break; 9162 case Intrinsic::x86_sse_comile_ss: 9163 case Intrinsic::x86_sse2_comile_sd: 9164 Opc = X86ISD::COMI; 9165 CC = ISD::SETLE; 9166 break; 9167 case Intrinsic::x86_sse_comigt_ss: 9168 case Intrinsic::x86_sse2_comigt_sd: 9169 Opc = X86ISD::COMI; 9170 CC = ISD::SETGT; 9171 break; 9172 case Intrinsic::x86_sse_comige_ss: 9173 case Intrinsic::x86_sse2_comige_sd: 9174 Opc = X86ISD::COMI; 9175 CC = ISD::SETGE; 9176 break; 9177 case Intrinsic::x86_sse_comineq_ss: 9178 case Intrinsic::x86_sse2_comineq_sd: 9179 Opc = X86ISD::COMI; 9180 CC = ISD::SETNE; 9181 break; 9182 case Intrinsic::x86_sse_ucomieq_ss: 9183 case Intrinsic::x86_sse2_ucomieq_sd: 9184 Opc = X86ISD::UCOMI; 9185 CC = ISD::SETEQ; 9186 break; 9187 case Intrinsic::x86_sse_ucomilt_ss: 9188 case Intrinsic::x86_sse2_ucomilt_sd: 9189 Opc = X86ISD::UCOMI; 9190 CC = ISD::SETLT; 9191 break; 9192 case Intrinsic::x86_sse_ucomile_ss: 9193 case Intrinsic::x86_sse2_ucomile_sd: 9194 Opc = X86ISD::UCOMI; 9195 CC = ISD::SETLE; 9196 break; 9197 case Intrinsic::x86_sse_ucomigt_ss: 9198 case Intrinsic::x86_sse2_ucomigt_sd: 9199 Opc = X86ISD::UCOMI; 9200 CC = ISD::SETGT; 9201 break; 9202 case Intrinsic::x86_sse_ucomige_ss: 9203 case Intrinsic::x86_sse2_ucomige_sd: 9204 Opc = X86ISD::UCOMI; 9205 CC = ISD::SETGE; 9206 break; 9207 case Intrinsic::x86_sse_ucomineq_ss: 9208 case Intrinsic::x86_sse2_ucomineq_sd: 9209 Opc = X86ISD::UCOMI; 9210 CC = ISD::SETNE; 9211 break; 9212 } 9213 9214 SDValue LHS = Op.getOperand(1); 9215 SDValue RHS = Op.getOperand(2); 9216 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9217 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9218 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9219 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9220 DAG.getConstant(X86CC, MVT::i8), Cond); 9221 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9222 } 9223 // Arithmetic intrinsics. 9224 case Intrinsic::x86_sse3_hadd_ps: 9225 case Intrinsic::x86_sse3_hadd_pd: 9226 case Intrinsic::x86_avx_hadd_ps_256: 9227 case Intrinsic::x86_avx_hadd_pd_256: 9228 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9229 Op.getOperand(1), Op.getOperand(2)); 9230 case Intrinsic::x86_sse3_hsub_ps: 9231 case Intrinsic::x86_sse3_hsub_pd: 9232 case Intrinsic::x86_avx_hsub_ps_256: 9233 case Intrinsic::x86_avx_hsub_pd_256: 9234 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9235 Op.getOperand(1), Op.getOperand(2)); 9236 // ptest and testp intrinsics. The intrinsic these come from are designed to 9237 // return an integer value, not just an instruction so lower it to the ptest 9238 // or testp pattern and a setcc for the result. 9239 case Intrinsic::x86_sse41_ptestz: 9240 case Intrinsic::x86_sse41_ptestc: 9241 case Intrinsic::x86_sse41_ptestnzc: 9242 case Intrinsic::x86_avx_ptestz_256: 9243 case Intrinsic::x86_avx_ptestc_256: 9244 case Intrinsic::x86_avx_ptestnzc_256: 9245 case Intrinsic::x86_avx_vtestz_ps: 9246 case Intrinsic::x86_avx_vtestc_ps: 9247 case Intrinsic::x86_avx_vtestnzc_ps: 9248 case Intrinsic::x86_avx_vtestz_pd: 9249 case Intrinsic::x86_avx_vtestc_pd: 9250 case Intrinsic::x86_avx_vtestnzc_pd: 9251 case Intrinsic::x86_avx_vtestz_ps_256: 9252 case Intrinsic::x86_avx_vtestc_ps_256: 9253 case Intrinsic::x86_avx_vtestnzc_ps_256: 9254 case Intrinsic::x86_avx_vtestz_pd_256: 9255 case Intrinsic::x86_avx_vtestc_pd_256: 9256 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9257 bool IsTestPacked = false; 9258 unsigned X86CC = 0; 9259 switch (IntNo) { 9260 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9261 case Intrinsic::x86_avx_vtestz_ps: 9262 case Intrinsic::x86_avx_vtestz_pd: 9263 case Intrinsic::x86_avx_vtestz_ps_256: 9264 case Intrinsic::x86_avx_vtestz_pd_256: 9265 IsTestPacked = true; // Fallthrough 9266 case Intrinsic::x86_sse41_ptestz: 9267 case Intrinsic::x86_avx_ptestz_256: 9268 // ZF = 1 9269 X86CC = X86::COND_E; 9270 break; 9271 case Intrinsic::x86_avx_vtestc_ps: 9272 case Intrinsic::x86_avx_vtestc_pd: 9273 case Intrinsic::x86_avx_vtestc_ps_256: 9274 case Intrinsic::x86_avx_vtestc_pd_256: 9275 IsTestPacked = true; // Fallthrough 9276 case Intrinsic::x86_sse41_ptestc: 9277 case Intrinsic::x86_avx_ptestc_256: 9278 // CF = 1 9279 X86CC = X86::COND_B; 9280 break; 9281 case Intrinsic::x86_avx_vtestnzc_ps: 9282 case Intrinsic::x86_avx_vtestnzc_pd: 9283 case Intrinsic::x86_avx_vtestnzc_ps_256: 9284 case Intrinsic::x86_avx_vtestnzc_pd_256: 9285 IsTestPacked = true; // Fallthrough 9286 case Intrinsic::x86_sse41_ptestnzc: 9287 case Intrinsic::x86_avx_ptestnzc_256: 9288 // ZF and CF = 0 9289 X86CC = X86::COND_A; 9290 break; 9291 } 9292 9293 SDValue LHS = Op.getOperand(1); 9294 SDValue RHS = Op.getOperand(2); 9295 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9296 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9297 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9298 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9299 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9300 } 9301 9302 // Fix vector shift instructions where the last operand is a non-immediate 9303 // i32 value. 9304 case Intrinsic::x86_sse2_pslli_w: 9305 case Intrinsic::x86_sse2_pslli_d: 9306 case Intrinsic::x86_sse2_pslli_q: 9307 case Intrinsic::x86_sse2_psrli_w: 9308 case Intrinsic::x86_sse2_psrli_d: 9309 case Intrinsic::x86_sse2_psrli_q: 9310 case Intrinsic::x86_sse2_psrai_w: 9311 case Intrinsic::x86_sse2_psrai_d: 9312 case Intrinsic::x86_mmx_pslli_w: 9313 case Intrinsic::x86_mmx_pslli_d: 9314 case Intrinsic::x86_mmx_pslli_q: 9315 case Intrinsic::x86_mmx_psrli_w: 9316 case Intrinsic::x86_mmx_psrli_d: 9317 case Intrinsic::x86_mmx_psrli_q: 9318 case Intrinsic::x86_mmx_psrai_w: 9319 case Intrinsic::x86_mmx_psrai_d: { 9320 SDValue ShAmt = Op.getOperand(2); 9321 if (isa<ConstantSDNode>(ShAmt)) 9322 return SDValue(); 9323 9324 unsigned NewIntNo = 0; 9325 EVT ShAmtVT = MVT::v4i32; 9326 switch (IntNo) { 9327 case Intrinsic::x86_sse2_pslli_w: 9328 NewIntNo = Intrinsic::x86_sse2_psll_w; 9329 break; 9330 case Intrinsic::x86_sse2_pslli_d: 9331 NewIntNo = Intrinsic::x86_sse2_psll_d; 9332 break; 9333 case Intrinsic::x86_sse2_pslli_q: 9334 NewIntNo = Intrinsic::x86_sse2_psll_q; 9335 break; 9336 case Intrinsic::x86_sse2_psrli_w: 9337 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9338 break; 9339 case Intrinsic::x86_sse2_psrli_d: 9340 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9341 break; 9342 case Intrinsic::x86_sse2_psrli_q: 9343 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9344 break; 9345 case Intrinsic::x86_sse2_psrai_w: 9346 NewIntNo = Intrinsic::x86_sse2_psra_w; 9347 break; 9348 case Intrinsic::x86_sse2_psrai_d: 9349 NewIntNo = Intrinsic::x86_sse2_psra_d; 9350 break; 9351 default: { 9352 ShAmtVT = MVT::v2i32; 9353 switch (IntNo) { 9354 case Intrinsic::x86_mmx_pslli_w: 9355 NewIntNo = Intrinsic::x86_mmx_psll_w; 9356 break; 9357 case Intrinsic::x86_mmx_pslli_d: 9358 NewIntNo = Intrinsic::x86_mmx_psll_d; 9359 break; 9360 case Intrinsic::x86_mmx_pslli_q: 9361 NewIntNo = Intrinsic::x86_mmx_psll_q; 9362 break; 9363 case Intrinsic::x86_mmx_psrli_w: 9364 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9365 break; 9366 case Intrinsic::x86_mmx_psrli_d: 9367 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9368 break; 9369 case Intrinsic::x86_mmx_psrli_q: 9370 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9371 break; 9372 case Intrinsic::x86_mmx_psrai_w: 9373 NewIntNo = Intrinsic::x86_mmx_psra_w; 9374 break; 9375 case Intrinsic::x86_mmx_psrai_d: 9376 NewIntNo = Intrinsic::x86_mmx_psra_d; 9377 break; 9378 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9379 } 9380 break; 9381 } 9382 } 9383 9384 // The vector shift intrinsics with scalars uses 32b shift amounts but 9385 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9386 // to be zero. 9387 SDValue ShOps[4]; 9388 ShOps[0] = ShAmt; 9389 ShOps[1] = DAG.getConstant(0, MVT::i32); 9390 if (ShAmtVT == MVT::v4i32) { 9391 ShOps[2] = DAG.getUNDEF(MVT::i32); 9392 ShOps[3] = DAG.getUNDEF(MVT::i32); 9393 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9394 } else { 9395 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9396// FIXME this must be lowered to get rid of the invalid type. 9397 } 9398 9399 EVT VT = Op.getValueType(); 9400 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9401 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9402 DAG.getConstant(NewIntNo, MVT::i32), 9403 Op.getOperand(1), ShAmt); 9404 } 9405 } 9406} 9407 9408SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9409 SelectionDAG &DAG) const { 9410 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9411 MFI->setReturnAddressIsTaken(true); 9412 9413 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9414 DebugLoc dl = Op.getDebugLoc(); 9415 9416 if (Depth > 0) { 9417 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9418 SDValue Offset = 9419 DAG.getConstant(TD->getPointerSize(), 9420 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9421 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9422 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9423 FrameAddr, Offset), 9424 MachinePointerInfo(), false, false, 0); 9425 } 9426 9427 // Just load the return address. 9428 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9429 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9430 RetAddrFI, MachinePointerInfo(), false, false, 0); 9431} 9432 9433SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9434 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9435 MFI->setFrameAddressIsTaken(true); 9436 9437 EVT VT = Op.getValueType(); 9438 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9439 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9440 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9441 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9442 while (Depth--) 9443 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9444 MachinePointerInfo(), 9445 false, false, 0); 9446 return FrameAddr; 9447} 9448 9449SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9450 SelectionDAG &DAG) const { 9451 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9452} 9453 9454SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9455 MachineFunction &MF = DAG.getMachineFunction(); 9456 SDValue Chain = Op.getOperand(0); 9457 SDValue Offset = Op.getOperand(1); 9458 SDValue Handler = Op.getOperand(2); 9459 DebugLoc dl = Op.getDebugLoc(); 9460 9461 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9462 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9463 getPointerTy()); 9464 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9465 9466 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9467 DAG.getIntPtrConstant(TD->getPointerSize())); 9468 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9469 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9470 false, false, 0); 9471 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9472 MF.getRegInfo().addLiveOut(StoreAddrReg); 9473 9474 return DAG.getNode(X86ISD::EH_RETURN, dl, 9475 MVT::Other, 9476 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9477} 9478 9479SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9480 SelectionDAG &DAG) const { 9481 return Op.getOperand(0); 9482} 9483 9484SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9485 SelectionDAG &DAG) const { 9486 SDValue Root = Op.getOperand(0); 9487 SDValue Trmp = Op.getOperand(1); // trampoline 9488 SDValue FPtr = Op.getOperand(2); // nested function 9489 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9490 DebugLoc dl = Op.getDebugLoc(); 9491 9492 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9493 9494 if (Subtarget->is64Bit()) { 9495 SDValue OutChains[6]; 9496 9497 // Large code-model. 9498 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9499 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9500 9501 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9502 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9503 9504 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9505 9506 // Load the pointer to the nested function into R11. 9507 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9508 SDValue Addr = Trmp; 9509 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9510 Addr, MachinePointerInfo(TrmpAddr), 9511 false, false, 0); 9512 9513 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9514 DAG.getConstant(2, MVT::i64)); 9515 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9516 MachinePointerInfo(TrmpAddr, 2), 9517 false, false, 2); 9518 9519 // Load the 'nest' parameter value into R10. 9520 // R10 is specified in X86CallingConv.td 9521 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9522 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9523 DAG.getConstant(10, MVT::i64)); 9524 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9525 Addr, MachinePointerInfo(TrmpAddr, 10), 9526 false, false, 0); 9527 9528 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9529 DAG.getConstant(12, MVT::i64)); 9530 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9531 MachinePointerInfo(TrmpAddr, 12), 9532 false, false, 2); 9533 9534 // Jump to the nested function. 9535 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9536 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9537 DAG.getConstant(20, MVT::i64)); 9538 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9539 Addr, MachinePointerInfo(TrmpAddr, 20), 9540 false, false, 0); 9541 9542 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9543 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9544 DAG.getConstant(22, MVT::i64)); 9545 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9546 MachinePointerInfo(TrmpAddr, 22), 9547 false, false, 0); 9548 9549 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9550 } else { 9551 const Function *Func = 9552 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9553 CallingConv::ID CC = Func->getCallingConv(); 9554 unsigned NestReg; 9555 9556 switch (CC) { 9557 default: 9558 llvm_unreachable("Unsupported calling convention"); 9559 case CallingConv::C: 9560 case CallingConv::X86_StdCall: { 9561 // Pass 'nest' parameter in ECX. 9562 // Must be kept in sync with X86CallingConv.td 9563 NestReg = X86::ECX; 9564 9565 // Check that ECX wasn't needed by an 'inreg' parameter. 9566 FunctionType *FTy = Func->getFunctionType(); 9567 const AttrListPtr &Attrs = Func->getAttributes(); 9568 9569 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9570 unsigned InRegCount = 0; 9571 unsigned Idx = 1; 9572 9573 for (FunctionType::param_iterator I = FTy->param_begin(), 9574 E = FTy->param_end(); I != E; ++I, ++Idx) 9575 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9576 // FIXME: should only count parameters that are lowered to integers. 9577 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9578 9579 if (InRegCount > 2) { 9580 report_fatal_error("Nest register in use - reduce number of inreg" 9581 " parameters!"); 9582 } 9583 } 9584 break; 9585 } 9586 case CallingConv::X86_FastCall: 9587 case CallingConv::X86_ThisCall: 9588 case CallingConv::Fast: 9589 // Pass 'nest' parameter in EAX. 9590 // Must be kept in sync with X86CallingConv.td 9591 NestReg = X86::EAX; 9592 break; 9593 } 9594 9595 SDValue OutChains[4]; 9596 SDValue Addr, Disp; 9597 9598 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9599 DAG.getConstant(10, MVT::i32)); 9600 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9601 9602 // This is storing the opcode for MOV32ri. 9603 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9604 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9605 OutChains[0] = DAG.getStore(Root, dl, 9606 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9607 Trmp, MachinePointerInfo(TrmpAddr), 9608 false, false, 0); 9609 9610 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9611 DAG.getConstant(1, MVT::i32)); 9612 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9613 MachinePointerInfo(TrmpAddr, 1), 9614 false, false, 1); 9615 9616 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9617 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9618 DAG.getConstant(5, MVT::i32)); 9619 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9620 MachinePointerInfo(TrmpAddr, 5), 9621 false, false, 1); 9622 9623 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9624 DAG.getConstant(6, MVT::i32)); 9625 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9626 MachinePointerInfo(TrmpAddr, 6), 9627 false, false, 1); 9628 9629 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9630 } 9631} 9632 9633SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9634 SelectionDAG &DAG) const { 9635 /* 9636 The rounding mode is in bits 11:10 of FPSR, and has the following 9637 settings: 9638 00 Round to nearest 9639 01 Round to -inf 9640 10 Round to +inf 9641 11 Round to 0 9642 9643 FLT_ROUNDS, on the other hand, expects the following: 9644 -1 Undefined 9645 0 Round to 0 9646 1 Round to nearest 9647 2 Round to +inf 9648 3 Round to -inf 9649 9650 To perform the conversion, we do: 9651 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9652 */ 9653 9654 MachineFunction &MF = DAG.getMachineFunction(); 9655 const TargetMachine &TM = MF.getTarget(); 9656 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9657 unsigned StackAlignment = TFI.getStackAlignment(); 9658 EVT VT = Op.getValueType(); 9659 DebugLoc DL = Op.getDebugLoc(); 9660 9661 // Save FP Control Word to stack slot 9662 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9663 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9664 9665 9666 MachineMemOperand *MMO = 9667 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9668 MachineMemOperand::MOStore, 2, 2); 9669 9670 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9671 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9672 DAG.getVTList(MVT::Other), 9673 Ops, 2, MVT::i16, MMO); 9674 9675 // Load FP Control Word from stack slot 9676 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9677 MachinePointerInfo(), false, false, 0); 9678 9679 // Transform as necessary 9680 SDValue CWD1 = 9681 DAG.getNode(ISD::SRL, DL, MVT::i16, 9682 DAG.getNode(ISD::AND, DL, MVT::i16, 9683 CWD, DAG.getConstant(0x800, MVT::i16)), 9684 DAG.getConstant(11, MVT::i8)); 9685 SDValue CWD2 = 9686 DAG.getNode(ISD::SRL, DL, MVT::i16, 9687 DAG.getNode(ISD::AND, DL, MVT::i16, 9688 CWD, DAG.getConstant(0x400, MVT::i16)), 9689 DAG.getConstant(9, MVT::i8)); 9690 9691 SDValue RetVal = 9692 DAG.getNode(ISD::AND, DL, MVT::i16, 9693 DAG.getNode(ISD::ADD, DL, MVT::i16, 9694 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9695 DAG.getConstant(1, MVT::i16)), 9696 DAG.getConstant(3, MVT::i16)); 9697 9698 9699 return DAG.getNode((VT.getSizeInBits() < 16 ? 9700 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9701} 9702 9703SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9704 EVT VT = Op.getValueType(); 9705 EVT OpVT = VT; 9706 unsigned NumBits = VT.getSizeInBits(); 9707 DebugLoc dl = Op.getDebugLoc(); 9708 9709 Op = Op.getOperand(0); 9710 if (VT == MVT::i8) { 9711 // Zero extend to i32 since there is not an i8 bsr. 9712 OpVT = MVT::i32; 9713 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9714 } 9715 9716 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9717 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9718 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9719 9720 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9721 SDValue Ops[] = { 9722 Op, 9723 DAG.getConstant(NumBits+NumBits-1, OpVT), 9724 DAG.getConstant(X86::COND_E, MVT::i8), 9725 Op.getValue(1) 9726 }; 9727 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9728 9729 // Finally xor with NumBits-1. 9730 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9731 9732 if (VT == MVT::i8) 9733 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9734 return Op; 9735} 9736 9737SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9738 EVT VT = Op.getValueType(); 9739 EVT OpVT = VT; 9740 unsigned NumBits = VT.getSizeInBits(); 9741 DebugLoc dl = Op.getDebugLoc(); 9742 9743 Op = Op.getOperand(0); 9744 if (VT == MVT::i8) { 9745 OpVT = MVT::i32; 9746 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9747 } 9748 9749 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9750 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9751 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9752 9753 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9754 SDValue Ops[] = { 9755 Op, 9756 DAG.getConstant(NumBits, OpVT), 9757 DAG.getConstant(X86::COND_E, MVT::i8), 9758 Op.getValue(1) 9759 }; 9760 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9761 9762 if (VT == MVT::i8) 9763 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9764 return Op; 9765} 9766 9767// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9768// ones, and then concatenate the result back. 9769static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9770 EVT VT = Op.getValueType(); 9771 9772 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9773 "Unsupported value type for operation"); 9774 9775 int NumElems = VT.getVectorNumElements(); 9776 DebugLoc dl = Op.getDebugLoc(); 9777 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9778 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9779 9780 // Extract the LHS vectors 9781 SDValue LHS = Op.getOperand(0); 9782 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9783 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9784 9785 // Extract the RHS vectors 9786 SDValue RHS = Op.getOperand(1); 9787 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9788 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9789 9790 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9791 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9792 9793 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9794 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9795 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9796} 9797 9798SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9799 assert(Op.getValueType().getSizeInBits() == 256 && 9800 Op.getValueType().isInteger() && 9801 "Only handle AVX 256-bit vector integer operation"); 9802 return Lower256IntArith(Op, DAG); 9803} 9804 9805SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9806 assert(Op.getValueType().getSizeInBits() == 256 && 9807 Op.getValueType().isInteger() && 9808 "Only handle AVX 256-bit vector integer operation"); 9809 return Lower256IntArith(Op, DAG); 9810} 9811 9812SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9813 EVT VT = Op.getValueType(); 9814 9815 // Decompose 256-bit ops into smaller 128-bit ops. 9816 if (VT.getSizeInBits() == 256) 9817 return Lower256IntArith(Op, DAG); 9818 9819 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9820 DebugLoc dl = Op.getDebugLoc(); 9821 9822 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9823 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9824 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9825 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9826 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9827 // 9828 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9829 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9830 // return AloBlo + AloBhi + AhiBlo; 9831 9832 SDValue A = Op.getOperand(0); 9833 SDValue B = Op.getOperand(1); 9834 9835 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9836 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9837 A, DAG.getConstant(32, MVT::i32)); 9838 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9839 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9840 B, DAG.getConstant(32, MVT::i32)); 9841 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9842 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9843 A, B); 9844 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9845 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9846 A, Bhi); 9847 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9848 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9849 Ahi, B); 9850 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9851 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9852 AloBhi, DAG.getConstant(32, MVT::i32)); 9853 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9854 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9855 AhiBlo, DAG.getConstant(32, MVT::i32)); 9856 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9857 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9858 return Res; 9859} 9860 9861SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 9862 9863 EVT VT = Op.getValueType(); 9864 DebugLoc dl = Op.getDebugLoc(); 9865 SDValue R = Op.getOperand(0); 9866 SDValue Amt = Op.getOperand(1); 9867 LLVMContext *Context = DAG.getContext(); 9868 9869 if (!Subtarget->hasXMMInt()) 9870 return SDValue(); 9871 9872 // Decompose 256-bit shifts into smaller 128-bit shifts. 9873 if (VT.getSizeInBits() == 256) { 9874 int NumElems = VT.getVectorNumElements(); 9875 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9876 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9877 9878 // Extract the two vectors 9879 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 9880 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 9881 DAG, dl); 9882 9883 // Recreate the shift amount vectors 9884 SDValue Amt1, Amt2; 9885 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 9886 // Constant shift amount 9887 SmallVector<SDValue, 4> Amt1Csts; 9888 SmallVector<SDValue, 4> Amt2Csts; 9889 for (int i = 0; i < NumElems/2; ++i) 9890 Amt1Csts.push_back(Amt->getOperand(i)); 9891 for (int i = NumElems/2; i < NumElems; ++i) 9892 Amt2Csts.push_back(Amt->getOperand(i)); 9893 9894 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9895 &Amt1Csts[0], NumElems/2); 9896 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9897 &Amt2Csts[0], NumElems/2); 9898 } else { 9899 // Variable shift amount 9900 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 9901 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 9902 DAG, dl); 9903 } 9904 9905 // Issue new vector shifts for the smaller types 9906 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 9907 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 9908 9909 // Concatenate the result back 9910 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 9911 } 9912 9913 // Optimize shl/srl/sra with constant shift amount. 9914 if (isSplatVector(Amt.getNode())) { 9915 SDValue SclrAmt = Amt->getOperand(0); 9916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 9917 uint64_t ShiftAmt = C->getZExtValue(); 9918 9919 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 9920 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9921 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9922 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9923 9924 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 9925 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9926 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9927 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9928 9929 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 9930 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9931 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9932 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9933 9934 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 9935 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9936 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9937 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9938 9939 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 9940 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9941 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9942 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9943 9944 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 9945 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9946 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9947 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9948 9949 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 9950 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9951 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9952 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9953 9954 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 9955 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9956 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9957 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9958 } 9959 } 9960 9961 // Lower SHL with variable shift amount. 9962 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 9963 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9964 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9965 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 9966 9967 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 9968 9969 std::vector<Constant*> CV(4, CI); 9970 Constant *C = ConstantVector::get(CV); 9971 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9972 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9973 MachinePointerInfo::getConstantPool(), 9974 false, false, 16); 9975 9976 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 9977 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 9978 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 9979 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 9980 } 9981 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 9982 // a = a << 5; 9983 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9984 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9985 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 9986 9987 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 9988 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 9989 9990 std::vector<Constant*> CVM1(16, CM1); 9991 std::vector<Constant*> CVM2(16, CM2); 9992 Constant *C = ConstantVector::get(CVM1); 9993 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9994 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9995 MachinePointerInfo::getConstantPool(), 9996 false, false, 16); 9997 9998 // r = pblendv(r, psllw(r & (char16)15, 4), a); 9999 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10000 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10001 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10002 DAG.getConstant(4, MVT::i32)); 10003 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10004 // a += a 10005 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10006 10007 C = ConstantVector::get(CVM2); 10008 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10009 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10010 MachinePointerInfo::getConstantPool(), 10011 false, false, 16); 10012 10013 // r = pblendv(r, psllw(r & (char16)63, 2), a); 10014 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10015 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10016 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10017 DAG.getConstant(2, MVT::i32)); 10018 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10019 // a += a 10020 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10021 10022 // return pblendv(r, r+r, a); 10023 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, 10024 R, DAG.getNode(ISD::ADD, dl, VT, R, R)); 10025 return R; 10026 } 10027 return SDValue(); 10028} 10029 10030SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10031 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10032 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10033 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10034 // has only one use. 10035 SDNode *N = Op.getNode(); 10036 SDValue LHS = N->getOperand(0); 10037 SDValue RHS = N->getOperand(1); 10038 unsigned BaseOp = 0; 10039 unsigned Cond = 0; 10040 DebugLoc DL = Op.getDebugLoc(); 10041 switch (Op.getOpcode()) { 10042 default: llvm_unreachable("Unknown ovf instruction!"); 10043 case ISD::SADDO: 10044 // A subtract of one will be selected as a INC. Note that INC doesn't 10045 // set CF, so we can't do this for UADDO. 10046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10047 if (C->isOne()) { 10048 BaseOp = X86ISD::INC; 10049 Cond = X86::COND_O; 10050 break; 10051 } 10052 BaseOp = X86ISD::ADD; 10053 Cond = X86::COND_O; 10054 break; 10055 case ISD::UADDO: 10056 BaseOp = X86ISD::ADD; 10057 Cond = X86::COND_B; 10058 break; 10059 case ISD::SSUBO: 10060 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10061 // set CF, so we can't do this for USUBO. 10062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10063 if (C->isOne()) { 10064 BaseOp = X86ISD::DEC; 10065 Cond = X86::COND_O; 10066 break; 10067 } 10068 BaseOp = X86ISD::SUB; 10069 Cond = X86::COND_O; 10070 break; 10071 case ISD::USUBO: 10072 BaseOp = X86ISD::SUB; 10073 Cond = X86::COND_B; 10074 break; 10075 case ISD::SMULO: 10076 BaseOp = X86ISD::SMUL; 10077 Cond = X86::COND_O; 10078 break; 10079 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10080 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10081 MVT::i32); 10082 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10083 10084 SDValue SetCC = 10085 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10086 DAG.getConstant(X86::COND_O, MVT::i32), 10087 SDValue(Sum.getNode(), 2)); 10088 10089 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10090 } 10091 } 10092 10093 // Also sets EFLAGS. 10094 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10095 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10096 10097 SDValue SetCC = 10098 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10099 DAG.getConstant(Cond, MVT::i32), 10100 SDValue(Sum.getNode(), 1)); 10101 10102 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10103} 10104 10105SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 10106 DebugLoc dl = Op.getDebugLoc(); 10107 SDNode* Node = Op.getNode(); 10108 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 10109 EVT VT = Node->getValueType(0); 10110 if (Subtarget->hasXMMInt() && VT.isVector()) { 10111 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10112 ExtraVT.getScalarType().getSizeInBits(); 10113 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10114 10115 unsigned SHLIntrinsicsID = 0; 10116 unsigned SRAIntrinsicsID = 0; 10117 switch (VT.getSimpleVT().SimpleTy) { 10118 default: 10119 return SDValue(); 10120 case MVT::v4i32: { 10121 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10122 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10123 break; 10124 } 10125 case MVT::v8i16: { 10126 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10127 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10128 break; 10129 } 10130 } 10131 10132 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10133 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10134 Node->getOperand(0), ShAmt); 10135 10136 // In case of 1 bit sext, no need to shr 10137 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; 10138 10139 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10140 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10141 Tmp1, ShAmt); 10142 } 10143 10144 return SDValue(); 10145} 10146 10147 10148SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10149 DebugLoc dl = Op.getDebugLoc(); 10150 10151 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10152 // There isn't any reason to disable it if the target processor supports it. 10153 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) { 10154 SDValue Chain = Op.getOperand(0); 10155 SDValue Zero = DAG.getConstant(0, MVT::i32); 10156 SDValue Ops[] = { 10157 DAG.getRegister(X86::ESP, MVT::i32), // Base 10158 DAG.getTargetConstant(1, MVT::i8), // Scale 10159 DAG.getRegister(0, MVT::i32), // Index 10160 DAG.getTargetConstant(0, MVT::i32), // Disp 10161 DAG.getRegister(0, MVT::i32), // Segment. 10162 Zero, 10163 Chain 10164 }; 10165 SDNode *Res = 10166 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10167 array_lengthof(Ops)); 10168 return SDValue(Res, 0); 10169 } 10170 10171 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10172 if (!isDev) 10173 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10174 10175 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10176 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10177 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10178 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10179 10180 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10181 if (!Op1 && !Op2 && !Op3 && Op4) 10182 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10183 10184 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10185 if (Op1 && !Op2 && !Op3 && !Op4) 10186 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10187 10188 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10189 // (MFENCE)>; 10190 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10191} 10192 10193SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10194 SelectionDAG &DAG) const { 10195 DebugLoc dl = Op.getDebugLoc(); 10196 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10197 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10198 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10199 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10200 10201 // The only fence that needs an instruction is a sequentially-consistent 10202 // cross-thread fence. 10203 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10204 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10205 // no-sse2). There isn't any reason to disable it if the target processor 10206 // supports it. 10207 if (Subtarget->hasXMMInt() || Subtarget->is64Bit()) 10208 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10209 10210 SDValue Chain = Op.getOperand(0); 10211 SDValue Zero = DAG.getConstant(0, MVT::i32); 10212 SDValue Ops[] = { 10213 DAG.getRegister(X86::ESP, MVT::i32), // Base 10214 DAG.getTargetConstant(1, MVT::i8), // Scale 10215 DAG.getRegister(0, MVT::i32), // Index 10216 DAG.getTargetConstant(0, MVT::i32), // Disp 10217 DAG.getRegister(0, MVT::i32), // Segment. 10218 Zero, 10219 Chain 10220 }; 10221 SDNode *Res = 10222 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10223 array_lengthof(Ops)); 10224 return SDValue(Res, 0); 10225 } 10226 10227 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10228 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10229} 10230 10231 10232SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10233 EVT T = Op.getValueType(); 10234 DebugLoc DL = Op.getDebugLoc(); 10235 unsigned Reg = 0; 10236 unsigned size = 0; 10237 switch(T.getSimpleVT().SimpleTy) { 10238 default: 10239 assert(false && "Invalid value type!"); 10240 case MVT::i8: Reg = X86::AL; size = 1; break; 10241 case MVT::i16: Reg = X86::AX; size = 2; break; 10242 case MVT::i32: Reg = X86::EAX; size = 4; break; 10243 case MVT::i64: 10244 assert(Subtarget->is64Bit() && "Node not type legal!"); 10245 Reg = X86::RAX; size = 8; 10246 break; 10247 } 10248 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10249 Op.getOperand(2), SDValue()); 10250 SDValue Ops[] = { cpIn.getValue(0), 10251 Op.getOperand(1), 10252 Op.getOperand(3), 10253 DAG.getTargetConstant(size, MVT::i8), 10254 cpIn.getValue(1) }; 10255 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10256 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10257 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10258 Ops, 5, T, MMO); 10259 SDValue cpOut = 10260 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10261 return cpOut; 10262} 10263 10264SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10265 SelectionDAG &DAG) const { 10266 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10267 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10268 SDValue TheChain = Op.getOperand(0); 10269 DebugLoc dl = Op.getDebugLoc(); 10270 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10271 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10272 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10273 rax.getValue(2)); 10274 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10275 DAG.getConstant(32, MVT::i8)); 10276 SDValue Ops[] = { 10277 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10278 rdx.getValue(1) 10279 }; 10280 return DAG.getMergeValues(Ops, 2, dl); 10281} 10282 10283SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10284 SelectionDAG &DAG) const { 10285 EVT SrcVT = Op.getOperand(0).getValueType(); 10286 EVT DstVT = Op.getValueType(); 10287 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() && 10288 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10289 assert((DstVT == MVT::i64 || 10290 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10291 "Unexpected custom BITCAST"); 10292 // i64 <=> MMX conversions are Legal. 10293 if (SrcVT==MVT::i64 && DstVT.isVector()) 10294 return Op; 10295 if (DstVT==MVT::i64 && SrcVT.isVector()) 10296 return Op; 10297 // MMX <=> MMX conversions are Legal. 10298 if (SrcVT.isVector() && DstVT.isVector()) 10299 return Op; 10300 // All other conversions need to be expanded. 10301 return SDValue(); 10302} 10303 10304SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10305 SDNode *Node = Op.getNode(); 10306 DebugLoc dl = Node->getDebugLoc(); 10307 EVT T = Node->getValueType(0); 10308 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10309 DAG.getConstant(0, T), Node->getOperand(2)); 10310 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10311 cast<AtomicSDNode>(Node)->getMemoryVT(), 10312 Node->getOperand(0), 10313 Node->getOperand(1), negOp, 10314 cast<AtomicSDNode>(Node)->getSrcValue(), 10315 cast<AtomicSDNode>(Node)->getAlignment(), 10316 cast<AtomicSDNode>(Node)->getOrdering(), 10317 cast<AtomicSDNode>(Node)->getSynchScope()); 10318} 10319 10320static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10321 SDNode *Node = Op.getNode(); 10322 DebugLoc dl = Node->getDebugLoc(); 10323 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10324 10325 // Convert seq_cst store -> xchg 10326 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10327 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10328 // (The only way to get a 16-byte store is cmpxchg16b) 10329 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10330 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10331 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10332 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10333 cast<AtomicSDNode>(Node)->getMemoryVT(), 10334 Node->getOperand(0), 10335 Node->getOperand(1), Node->getOperand(2), 10336 cast<AtomicSDNode>(Node)->getMemOperand(), 10337 cast<AtomicSDNode>(Node)->getOrdering(), 10338 cast<AtomicSDNode>(Node)->getSynchScope()); 10339 return Swap.getValue(1); 10340 } 10341 // Other atomic stores have a simple pattern. 10342 return Op; 10343} 10344 10345static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10346 EVT VT = Op.getNode()->getValueType(0); 10347 10348 // Let legalize expand this if it isn't a legal type yet. 10349 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10350 return SDValue(); 10351 10352 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10353 10354 unsigned Opc; 10355 bool ExtraOp = false; 10356 switch (Op.getOpcode()) { 10357 default: assert(0 && "Invalid code"); 10358 case ISD::ADDC: Opc = X86ISD::ADD; break; 10359 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10360 case ISD::SUBC: Opc = X86ISD::SUB; break; 10361 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10362 } 10363 10364 if (!ExtraOp) 10365 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10366 Op.getOperand(1)); 10367 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10368 Op.getOperand(1), Op.getOperand(2)); 10369} 10370 10371/// LowerOperation - Provide custom lowering hooks for some operations. 10372/// 10373SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10374 switch (Op.getOpcode()) { 10375 default: llvm_unreachable("Should not custom lower this!"); 10376 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10377 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10378 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10379 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10380 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10381 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10382 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10383 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10384 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10385 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10386 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10387 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10388 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10389 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10390 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10391 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10392 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10393 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10394 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10395 case ISD::SHL_PARTS: 10396 case ISD::SRA_PARTS: 10397 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10398 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10399 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10400 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10401 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10402 case ISD::FABS: return LowerFABS(Op, DAG); 10403 case ISD::FNEG: return LowerFNEG(Op, DAG); 10404 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10405 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10406 case ISD::SETCC: return LowerSETCC(Op, DAG); 10407 case ISD::SELECT: return LowerSELECT(Op, DAG); 10408 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10409 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10410 case ISD::VASTART: return LowerVASTART(Op, DAG); 10411 case ISD::VAARG: return LowerVAARG(Op, DAG); 10412 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10413 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10414 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10415 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10416 case ISD::FRAME_TO_ARGS_OFFSET: 10417 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10418 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10419 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10420 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10421 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10422 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10423 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10424 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10425 case ISD::MUL: return LowerMUL(Op, DAG); 10426 case ISD::SRA: 10427 case ISD::SRL: 10428 case ISD::SHL: return LowerShift(Op, DAG); 10429 case ISD::SADDO: 10430 case ISD::UADDO: 10431 case ISD::SSUBO: 10432 case ISD::USUBO: 10433 case ISD::SMULO: 10434 case ISD::UMULO: return LowerXALUO(Op, DAG); 10435 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10436 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10437 case ISD::ADDC: 10438 case ISD::ADDE: 10439 case ISD::SUBC: 10440 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10441 case ISD::ADD: return LowerADD(Op, DAG); 10442 case ISD::SUB: return LowerSUB(Op, DAG); 10443 } 10444} 10445 10446static void ReplaceATOMIC_LOAD(SDNode *Node, 10447 SmallVectorImpl<SDValue> &Results, 10448 SelectionDAG &DAG) { 10449 DebugLoc dl = Node->getDebugLoc(); 10450 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10451 10452 // Convert wide load -> cmpxchg8b/cmpxchg16b 10453 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10454 // (The only way to get a 16-byte load is cmpxchg16b) 10455 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10456 SDValue Zero = DAG.getConstant(0, VT); 10457 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10458 Node->getOperand(0), 10459 Node->getOperand(1), Zero, Zero, 10460 cast<AtomicSDNode>(Node)->getMemOperand(), 10461 cast<AtomicSDNode>(Node)->getOrdering(), 10462 cast<AtomicSDNode>(Node)->getSynchScope()); 10463 Results.push_back(Swap.getValue(0)); 10464 Results.push_back(Swap.getValue(1)); 10465} 10466 10467void X86TargetLowering:: 10468ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10469 SelectionDAG &DAG, unsigned NewOp) const { 10470 EVT T = Node->getValueType(0); 10471 DebugLoc dl = Node->getDebugLoc(); 10472 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 10473 10474 SDValue Chain = Node->getOperand(0); 10475 SDValue In1 = Node->getOperand(1); 10476 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10477 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10478 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10479 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10480 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10481 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10482 SDValue Result = 10483 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10484 cast<MemSDNode>(Node)->getMemOperand()); 10485 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10486 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10487 Results.push_back(Result.getValue(2)); 10488} 10489 10490/// ReplaceNodeResults - Replace a node with an illegal result type 10491/// with a new node built out of custom code. 10492void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10493 SmallVectorImpl<SDValue>&Results, 10494 SelectionDAG &DAG) const { 10495 DebugLoc dl = N->getDebugLoc(); 10496 switch (N->getOpcode()) { 10497 default: 10498 assert(false && "Do not know how to custom type legalize this operation!"); 10499 return; 10500 case ISD::SIGN_EXTEND_INREG: 10501 case ISD::ADDC: 10502 case ISD::ADDE: 10503 case ISD::SUBC: 10504 case ISD::SUBE: 10505 // We don't want to expand or promote these. 10506 return; 10507 case ISD::FP_TO_SINT: { 10508 std::pair<SDValue,SDValue> Vals = 10509 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10510 SDValue FIST = Vals.first, StackSlot = Vals.second; 10511 if (FIST.getNode() != 0) { 10512 EVT VT = N->getValueType(0); 10513 // Return a load from the stack slot. 10514 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10515 MachinePointerInfo(), false, false, 0)); 10516 } 10517 return; 10518 } 10519 case ISD::READCYCLECOUNTER: { 10520 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10521 SDValue TheChain = N->getOperand(0); 10522 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10523 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10524 rd.getValue(1)); 10525 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10526 eax.getValue(2)); 10527 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10528 SDValue Ops[] = { eax, edx }; 10529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10530 Results.push_back(edx.getValue(1)); 10531 return; 10532 } 10533 case ISD::ATOMIC_CMP_SWAP: { 10534 EVT T = N->getValueType(0); 10535 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10536 bool Regs64bit = T == MVT::i128; 10537 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10538 SDValue cpInL, cpInH; 10539 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10540 DAG.getConstant(0, HalfT)); 10541 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10542 DAG.getConstant(1, HalfT)); 10543 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10544 Regs64bit ? X86::RAX : X86::EAX, 10545 cpInL, SDValue()); 10546 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10547 Regs64bit ? X86::RDX : X86::EDX, 10548 cpInH, cpInL.getValue(1)); 10549 SDValue swapInL, swapInH; 10550 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10551 DAG.getConstant(0, HalfT)); 10552 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10553 DAG.getConstant(1, HalfT)); 10554 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10555 Regs64bit ? X86::RBX : X86::EBX, 10556 swapInL, cpInH.getValue(1)); 10557 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10558 Regs64bit ? X86::RCX : X86::ECX, 10559 swapInH, swapInL.getValue(1)); 10560 SDValue Ops[] = { swapInH.getValue(0), 10561 N->getOperand(1), 10562 swapInH.getValue(1) }; 10563 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10564 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10565 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10566 X86ISD::LCMPXCHG8_DAG; 10567 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10568 Ops, 3, T, MMO); 10569 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10570 Regs64bit ? X86::RAX : X86::EAX, 10571 HalfT, Result.getValue(1)); 10572 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10573 Regs64bit ? X86::RDX : X86::EDX, 10574 HalfT, cpOutL.getValue(2)); 10575 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10576 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10577 Results.push_back(cpOutH.getValue(1)); 10578 return; 10579 } 10580 case ISD::ATOMIC_LOAD_ADD: 10581 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10582 return; 10583 case ISD::ATOMIC_LOAD_AND: 10584 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10585 return; 10586 case ISD::ATOMIC_LOAD_NAND: 10587 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10588 return; 10589 case ISD::ATOMIC_LOAD_OR: 10590 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10591 return; 10592 case ISD::ATOMIC_LOAD_SUB: 10593 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10594 return; 10595 case ISD::ATOMIC_LOAD_XOR: 10596 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10597 return; 10598 case ISD::ATOMIC_SWAP: 10599 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10600 return; 10601 case ISD::ATOMIC_LOAD: 10602 ReplaceATOMIC_LOAD(N, Results, DAG); 10603 } 10604} 10605 10606const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10607 switch (Opcode) { 10608 default: return NULL; 10609 case X86ISD::BSF: return "X86ISD::BSF"; 10610 case X86ISD::BSR: return "X86ISD::BSR"; 10611 case X86ISD::SHLD: return "X86ISD::SHLD"; 10612 case X86ISD::SHRD: return "X86ISD::SHRD"; 10613 case X86ISD::FAND: return "X86ISD::FAND"; 10614 case X86ISD::FOR: return "X86ISD::FOR"; 10615 case X86ISD::FXOR: return "X86ISD::FXOR"; 10616 case X86ISD::FSRL: return "X86ISD::FSRL"; 10617 case X86ISD::FILD: return "X86ISD::FILD"; 10618 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10619 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10620 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10621 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10622 case X86ISD::FLD: return "X86ISD::FLD"; 10623 case X86ISD::FST: return "X86ISD::FST"; 10624 case X86ISD::CALL: return "X86ISD::CALL"; 10625 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10626 case X86ISD::BT: return "X86ISD::BT"; 10627 case X86ISD::CMP: return "X86ISD::CMP"; 10628 case X86ISD::COMI: return "X86ISD::COMI"; 10629 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10630 case X86ISD::SETCC: return "X86ISD::SETCC"; 10631 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10632 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10633 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10634 case X86ISD::CMOV: return "X86ISD::CMOV"; 10635 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10636 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10637 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10638 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10639 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10640 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10641 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10642 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10643 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10644 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10645 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10646 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10647 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10648 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10649 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 10650 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 10651 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 10652 case X86ISD::FMAX: return "X86ISD::FMAX"; 10653 case X86ISD::FMIN: return "X86ISD::FMIN"; 10654 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10655 case X86ISD::FRCP: return "X86ISD::FRCP"; 10656 case X86ISD::FHADD: return "X86ISD::FHADD"; 10657 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10658 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10659 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10660 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10661 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10662 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10663 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10664 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10665 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10666 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10667 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10668 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10669 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10670 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10671 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10672 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10673 case X86ISD::VSHL: return "X86ISD::VSHL"; 10674 case X86ISD::VSRL: return "X86ISD::VSRL"; 10675 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10676 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10677 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10678 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10679 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10680 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10681 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10682 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10683 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10684 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10685 case X86ISD::ADD: return "X86ISD::ADD"; 10686 case X86ISD::SUB: return "X86ISD::SUB"; 10687 case X86ISD::ADC: return "X86ISD::ADC"; 10688 case X86ISD::SBB: return "X86ISD::SBB"; 10689 case X86ISD::SMUL: return "X86ISD::SMUL"; 10690 case X86ISD::UMUL: return "X86ISD::UMUL"; 10691 case X86ISD::INC: return "X86ISD::INC"; 10692 case X86ISD::DEC: return "X86ISD::DEC"; 10693 case X86ISD::OR: return "X86ISD::OR"; 10694 case X86ISD::XOR: return "X86ISD::XOR"; 10695 case X86ISD::AND: return "X86ISD::AND"; 10696 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10697 case X86ISD::PTEST: return "X86ISD::PTEST"; 10698 case X86ISD::TESTP: return "X86ISD::TESTP"; 10699 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10700 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10701 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10702 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10703 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10704 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10705 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 10706 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 10707 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10708 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10709 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10710 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 10711 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10712 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10713 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10714 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10715 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10716 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10717 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10718 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10719 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10720 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 10721 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 10722 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 10723 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 10724 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 10725 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 10726 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 10727 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 10728 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 10729 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 10730 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 10731 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 10732 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 10733 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 10734 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 10735 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 10736 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 10737 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 10738 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128"; 10739 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10740 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10741 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10742 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10743 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 10744 } 10745} 10746 10747// isLegalAddressingMode - Return true if the addressing mode represented 10748// by AM is legal for this target, for a load/store of the specified type. 10749bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10750 Type *Ty) const { 10751 // X86 supports extremely general addressing modes. 10752 CodeModel::Model M = getTargetMachine().getCodeModel(); 10753 Reloc::Model R = getTargetMachine().getRelocationModel(); 10754 10755 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10756 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10757 return false; 10758 10759 if (AM.BaseGV) { 10760 unsigned GVFlags = 10761 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 10762 10763 // If a reference to this global requires an extra load, we can't fold it. 10764 if (isGlobalStubReference(GVFlags)) 10765 return false; 10766 10767 // If BaseGV requires a register for the PIC base, we cannot also have a 10768 // BaseReg specified. 10769 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 10770 return false; 10771 10772 // If lower 4G is not available, then we must use rip-relative addressing. 10773 if ((M != CodeModel::Small || R != Reloc::Static) && 10774 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 10775 return false; 10776 } 10777 10778 switch (AM.Scale) { 10779 case 0: 10780 case 1: 10781 case 2: 10782 case 4: 10783 case 8: 10784 // These scales always work. 10785 break; 10786 case 3: 10787 case 5: 10788 case 9: 10789 // These scales are formed with basereg+scalereg. Only accept if there is 10790 // no basereg yet. 10791 if (AM.HasBaseReg) 10792 return false; 10793 break; 10794 default: // Other stuff never works. 10795 return false; 10796 } 10797 10798 return true; 10799} 10800 10801 10802bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 10803 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 10804 return false; 10805 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 10806 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 10807 if (NumBits1 <= NumBits2) 10808 return false; 10809 return true; 10810} 10811 10812bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 10813 if (!VT1.isInteger() || !VT2.isInteger()) 10814 return false; 10815 unsigned NumBits1 = VT1.getSizeInBits(); 10816 unsigned NumBits2 = VT2.getSizeInBits(); 10817 if (NumBits1 <= NumBits2) 10818 return false; 10819 return true; 10820} 10821 10822bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 10823 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10824 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 10825} 10826 10827bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 10828 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10829 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 10830} 10831 10832bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 10833 // i16 instructions are longer (0x66 prefix) and potentially slower. 10834 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 10835} 10836 10837/// isShuffleMaskLegal - Targets can use this to indicate that they only 10838/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 10839/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 10840/// are assumed to be legal. 10841bool 10842X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 10843 EVT VT) const { 10844 // Very little shuffling can be done for 64-bit vectors right now. 10845 if (VT.getSizeInBits() == 64) 10846 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()); 10847 10848 // FIXME: pshufb, blends, shifts. 10849 return (VT.getVectorNumElements() == 2 || 10850 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 10851 isMOVLMask(M, VT) || 10852 isSHUFPMask(M, VT) || 10853 isPSHUFDMask(M, VT) || 10854 isPSHUFHWMask(M, VT) || 10855 isPSHUFLWMask(M, VT) || 10856 isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) || 10857 isUNPCKLMask(M, VT) || 10858 isUNPCKHMask(M, VT) || 10859 isUNPCKL_v_undef_Mask(M, VT) || 10860 isUNPCKH_v_undef_Mask(M, VT)); 10861} 10862 10863bool 10864X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 10865 EVT VT) const { 10866 unsigned NumElts = VT.getVectorNumElements(); 10867 // FIXME: This collection of masks seems suspect. 10868 if (NumElts == 2) 10869 return true; 10870 if (NumElts == 4 && VT.getSizeInBits() == 128) { 10871 return (isMOVLMask(Mask, VT) || 10872 isCommutedMOVLMask(Mask, VT, true) || 10873 isSHUFPMask(Mask, VT) || 10874 isCommutedSHUFPMask(Mask, VT)); 10875 } 10876 return false; 10877} 10878 10879//===----------------------------------------------------------------------===// 10880// X86 Scheduler Hooks 10881//===----------------------------------------------------------------------===// 10882 10883// private utility function 10884MachineBasicBlock * 10885X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 10886 MachineBasicBlock *MBB, 10887 unsigned regOpc, 10888 unsigned immOpc, 10889 unsigned LoadOpc, 10890 unsigned CXchgOpc, 10891 unsigned notOpc, 10892 unsigned EAXreg, 10893 TargetRegisterClass *RC, 10894 bool invSrc) const { 10895 // For the atomic bitwise operator, we generate 10896 // thisMBB: 10897 // newMBB: 10898 // ld t1 = [bitinstr.addr] 10899 // op t2 = t1, [bitinstr.val] 10900 // mov EAX = t1 10901 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10902 // bz newMBB 10903 // fallthrough -->nextMBB 10904 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10905 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10906 MachineFunction::iterator MBBIter = MBB; 10907 ++MBBIter; 10908 10909 /// First build the CFG 10910 MachineFunction *F = MBB->getParent(); 10911 MachineBasicBlock *thisMBB = MBB; 10912 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10913 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10914 F->insert(MBBIter, newMBB); 10915 F->insert(MBBIter, nextMBB); 10916 10917 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10918 nextMBB->splice(nextMBB->begin(), thisMBB, 10919 llvm::next(MachineBasicBlock::iterator(bInstr)), 10920 thisMBB->end()); 10921 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10922 10923 // Update thisMBB to fall through to newMBB 10924 thisMBB->addSuccessor(newMBB); 10925 10926 // newMBB jumps to itself and fall through to nextMBB 10927 newMBB->addSuccessor(nextMBB); 10928 newMBB->addSuccessor(newMBB); 10929 10930 // Insert instructions into newMBB based on incoming instruction 10931 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10932 "unexpected number of operands"); 10933 DebugLoc dl = bInstr->getDebugLoc(); 10934 MachineOperand& destOper = bInstr->getOperand(0); 10935 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10936 int numArgs = bInstr->getNumOperands() - 1; 10937 for (int i=0; i < numArgs; ++i) 10938 argOpers[i] = &bInstr->getOperand(i+1); 10939 10940 // x86 address has 4 operands: base, index, scale, and displacement 10941 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10942 int valArgIndx = lastAddrIndx + 1; 10943 10944 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10945 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 10946 for (int i=0; i <= lastAddrIndx; ++i) 10947 (*MIB).addOperand(*argOpers[i]); 10948 10949 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 10950 if (invSrc) { 10951 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 10952 } 10953 else 10954 tt = t1; 10955 10956 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10957 assert((argOpers[valArgIndx]->isReg() || 10958 argOpers[valArgIndx]->isImm()) && 10959 "invalid operand"); 10960 if (argOpers[valArgIndx]->isReg()) 10961 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 10962 else 10963 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 10964 MIB.addReg(tt); 10965 (*MIB).addOperand(*argOpers[valArgIndx]); 10966 10967 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 10968 MIB.addReg(t1); 10969 10970 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 10971 for (int i=0; i <= lastAddrIndx; ++i) 10972 (*MIB).addOperand(*argOpers[i]); 10973 MIB.addReg(t2); 10974 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10975 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10976 bInstr->memoperands_end()); 10977 10978 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10979 MIB.addReg(EAXreg); 10980 10981 // insert branch 10982 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10983 10984 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10985 return nextMBB; 10986} 10987 10988// private utility function: 64 bit atomics on 32 bit host. 10989MachineBasicBlock * 10990X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 10991 MachineBasicBlock *MBB, 10992 unsigned regOpcL, 10993 unsigned regOpcH, 10994 unsigned immOpcL, 10995 unsigned immOpcH, 10996 bool invSrc) const { 10997 // For the atomic bitwise operator, we generate 10998 // thisMBB (instructions are in pairs, except cmpxchg8b) 10999 // ld t1,t2 = [bitinstr.addr] 11000 // newMBB: 11001 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11002 // op t5, t6 <- out1, out2, [bitinstr.val] 11003 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11004 // mov ECX, EBX <- t5, t6 11005 // mov EAX, EDX <- t1, t2 11006 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11007 // mov t3, t4 <- EAX, EDX 11008 // bz newMBB 11009 // result in out1, out2 11010 // fallthrough -->nextMBB 11011 11012 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11013 const unsigned LoadOpc = X86::MOV32rm; 11014 const unsigned NotOpc = X86::NOT32r; 11015 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11016 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11017 MachineFunction::iterator MBBIter = MBB; 11018 ++MBBIter; 11019 11020 /// First build the CFG 11021 MachineFunction *F = MBB->getParent(); 11022 MachineBasicBlock *thisMBB = MBB; 11023 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11024 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11025 F->insert(MBBIter, newMBB); 11026 F->insert(MBBIter, nextMBB); 11027 11028 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11029 nextMBB->splice(nextMBB->begin(), thisMBB, 11030 llvm::next(MachineBasicBlock::iterator(bInstr)), 11031 thisMBB->end()); 11032 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11033 11034 // Update thisMBB to fall through to newMBB 11035 thisMBB->addSuccessor(newMBB); 11036 11037 // newMBB jumps to itself and fall through to nextMBB 11038 newMBB->addSuccessor(nextMBB); 11039 newMBB->addSuccessor(newMBB); 11040 11041 DebugLoc dl = bInstr->getDebugLoc(); 11042 // Insert instructions into newMBB based on incoming instruction 11043 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11044 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11045 "unexpected number of operands"); 11046 MachineOperand& dest1Oper = bInstr->getOperand(0); 11047 MachineOperand& dest2Oper = bInstr->getOperand(1); 11048 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11049 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11050 argOpers[i] = &bInstr->getOperand(i+2); 11051 11052 // We use some of the operands multiple times, so conservatively just 11053 // clear any kill flags that might be present. 11054 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11055 argOpers[i]->setIsKill(false); 11056 } 11057 11058 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11059 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11060 11061 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11062 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11063 for (int i=0; i <= lastAddrIndx; ++i) 11064 (*MIB).addOperand(*argOpers[i]); 11065 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11066 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11067 // add 4 to displacement. 11068 for (int i=0; i <= lastAddrIndx-2; ++i) 11069 (*MIB).addOperand(*argOpers[i]); 11070 MachineOperand newOp3 = *(argOpers[3]); 11071 if (newOp3.isImm()) 11072 newOp3.setImm(newOp3.getImm()+4); 11073 else 11074 newOp3.setOffset(newOp3.getOffset()+4); 11075 (*MIB).addOperand(newOp3); 11076 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11077 11078 // t3/4 are defined later, at the bottom of the loop 11079 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11080 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11081 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11082 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11083 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11084 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11085 11086 // The subsequent operations should be using the destination registers of 11087 //the PHI instructions. 11088 if (invSrc) { 11089 t1 = F->getRegInfo().createVirtualRegister(RC); 11090 t2 = F->getRegInfo().createVirtualRegister(RC); 11091 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11092 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11093 } else { 11094 t1 = dest1Oper.getReg(); 11095 t2 = dest2Oper.getReg(); 11096 } 11097 11098 int valArgIndx = lastAddrIndx + 1; 11099 assert((argOpers[valArgIndx]->isReg() || 11100 argOpers[valArgIndx]->isImm()) && 11101 "invalid operand"); 11102 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11103 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11104 if (argOpers[valArgIndx]->isReg()) 11105 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11106 else 11107 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11108 if (regOpcL != X86::MOV32rr) 11109 MIB.addReg(t1); 11110 (*MIB).addOperand(*argOpers[valArgIndx]); 11111 assert(argOpers[valArgIndx + 1]->isReg() == 11112 argOpers[valArgIndx]->isReg()); 11113 assert(argOpers[valArgIndx + 1]->isImm() == 11114 argOpers[valArgIndx]->isImm()); 11115 if (argOpers[valArgIndx + 1]->isReg()) 11116 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11117 else 11118 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11119 if (regOpcH != X86::MOV32rr) 11120 MIB.addReg(t2); 11121 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11122 11123 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11124 MIB.addReg(t1); 11125 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11126 MIB.addReg(t2); 11127 11128 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11129 MIB.addReg(t5); 11130 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11131 MIB.addReg(t6); 11132 11133 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11134 for (int i=0; i <= lastAddrIndx; ++i) 11135 (*MIB).addOperand(*argOpers[i]); 11136 11137 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11138 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11139 bInstr->memoperands_end()); 11140 11141 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11142 MIB.addReg(X86::EAX); 11143 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11144 MIB.addReg(X86::EDX); 11145 11146 // insert branch 11147 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11148 11149 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11150 return nextMBB; 11151} 11152 11153// private utility function 11154MachineBasicBlock * 11155X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11156 MachineBasicBlock *MBB, 11157 unsigned cmovOpc) const { 11158 // For the atomic min/max operator, we generate 11159 // thisMBB: 11160 // newMBB: 11161 // ld t1 = [min/max.addr] 11162 // mov t2 = [min/max.val] 11163 // cmp t1, t2 11164 // cmov[cond] t2 = t1 11165 // mov EAX = t1 11166 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11167 // bz newMBB 11168 // fallthrough -->nextMBB 11169 // 11170 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11171 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11172 MachineFunction::iterator MBBIter = MBB; 11173 ++MBBIter; 11174 11175 /// First build the CFG 11176 MachineFunction *F = MBB->getParent(); 11177 MachineBasicBlock *thisMBB = MBB; 11178 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11179 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11180 F->insert(MBBIter, newMBB); 11181 F->insert(MBBIter, nextMBB); 11182 11183 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11184 nextMBB->splice(nextMBB->begin(), thisMBB, 11185 llvm::next(MachineBasicBlock::iterator(mInstr)), 11186 thisMBB->end()); 11187 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11188 11189 // Update thisMBB to fall through to newMBB 11190 thisMBB->addSuccessor(newMBB); 11191 11192 // newMBB jumps to newMBB and fall through to nextMBB 11193 newMBB->addSuccessor(nextMBB); 11194 newMBB->addSuccessor(newMBB); 11195 11196 DebugLoc dl = mInstr->getDebugLoc(); 11197 // Insert instructions into newMBB based on incoming instruction 11198 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11199 "unexpected number of operands"); 11200 MachineOperand& destOper = mInstr->getOperand(0); 11201 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11202 int numArgs = mInstr->getNumOperands() - 1; 11203 for (int i=0; i < numArgs; ++i) 11204 argOpers[i] = &mInstr->getOperand(i+1); 11205 11206 // x86 address has 4 operands: base, index, scale, and displacement 11207 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11208 int valArgIndx = lastAddrIndx + 1; 11209 11210 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11211 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11212 for (int i=0; i <= lastAddrIndx; ++i) 11213 (*MIB).addOperand(*argOpers[i]); 11214 11215 // We only support register and immediate values 11216 assert((argOpers[valArgIndx]->isReg() || 11217 argOpers[valArgIndx]->isImm()) && 11218 "invalid operand"); 11219 11220 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11221 if (argOpers[valArgIndx]->isReg()) 11222 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11223 else 11224 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11225 (*MIB).addOperand(*argOpers[valArgIndx]); 11226 11227 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11228 MIB.addReg(t1); 11229 11230 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11231 MIB.addReg(t1); 11232 MIB.addReg(t2); 11233 11234 // Generate movc 11235 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11236 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11237 MIB.addReg(t2); 11238 MIB.addReg(t1); 11239 11240 // Cmp and exchange if none has modified the memory location 11241 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11242 for (int i=0; i <= lastAddrIndx; ++i) 11243 (*MIB).addOperand(*argOpers[i]); 11244 MIB.addReg(t3); 11245 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11246 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11247 mInstr->memoperands_end()); 11248 11249 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11250 MIB.addReg(X86::EAX); 11251 11252 // insert branch 11253 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11254 11255 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11256 return nextMBB; 11257} 11258 11259// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11260// or XMM0_V32I8 in AVX all of this code can be replaced with that 11261// in the .td file. 11262MachineBasicBlock * 11263X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11264 unsigned numArgs, bool memArg) const { 11265 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 11266 "Target must have SSE4.2 or AVX features enabled"); 11267 11268 DebugLoc dl = MI->getDebugLoc(); 11269 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11270 unsigned Opc; 11271 if (!Subtarget->hasAVX()) { 11272 if (memArg) 11273 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11274 else 11275 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11276 } else { 11277 if (memArg) 11278 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11279 else 11280 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11281 } 11282 11283 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11284 for (unsigned i = 0; i < numArgs; ++i) { 11285 MachineOperand &Op = MI->getOperand(i+1); 11286 if (!(Op.isReg() && Op.isImplicit())) 11287 MIB.addOperand(Op); 11288 } 11289 BuildMI(*BB, MI, dl, 11290 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11291 MI->getOperand(0).getReg()) 11292 .addReg(X86::XMM0); 11293 11294 MI->eraseFromParent(); 11295 return BB; 11296} 11297 11298MachineBasicBlock * 11299X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11300 DebugLoc dl = MI->getDebugLoc(); 11301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11302 11303 // Address into RAX/EAX, other two args into ECX, EDX. 11304 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11305 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11306 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11307 for (int i = 0; i < X86::AddrNumOperands; ++i) 11308 MIB.addOperand(MI->getOperand(i)); 11309 11310 unsigned ValOps = X86::AddrNumOperands; 11311 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11312 .addReg(MI->getOperand(ValOps).getReg()); 11313 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11314 .addReg(MI->getOperand(ValOps+1).getReg()); 11315 11316 // The instruction doesn't actually take any operands though. 11317 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11318 11319 MI->eraseFromParent(); // The pseudo is gone now. 11320 return BB; 11321} 11322 11323MachineBasicBlock * 11324X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11325 DebugLoc dl = MI->getDebugLoc(); 11326 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11327 11328 // First arg in ECX, the second in EAX. 11329 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11330 .addReg(MI->getOperand(0).getReg()); 11331 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11332 .addReg(MI->getOperand(1).getReg()); 11333 11334 // The instruction doesn't actually take any operands though. 11335 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11336 11337 MI->eraseFromParent(); // The pseudo is gone now. 11338 return BB; 11339} 11340 11341MachineBasicBlock * 11342X86TargetLowering::EmitVAARG64WithCustomInserter( 11343 MachineInstr *MI, 11344 MachineBasicBlock *MBB) const { 11345 // Emit va_arg instruction on X86-64. 11346 11347 // Operands to this pseudo-instruction: 11348 // 0 ) Output : destination address (reg) 11349 // 1-5) Input : va_list address (addr, i64mem) 11350 // 6 ) ArgSize : Size (in bytes) of vararg type 11351 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11352 // 8 ) Align : Alignment of type 11353 // 9 ) EFLAGS (implicit-def) 11354 11355 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11356 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11357 11358 unsigned DestReg = MI->getOperand(0).getReg(); 11359 MachineOperand &Base = MI->getOperand(1); 11360 MachineOperand &Scale = MI->getOperand(2); 11361 MachineOperand &Index = MI->getOperand(3); 11362 MachineOperand &Disp = MI->getOperand(4); 11363 MachineOperand &Segment = MI->getOperand(5); 11364 unsigned ArgSize = MI->getOperand(6).getImm(); 11365 unsigned ArgMode = MI->getOperand(7).getImm(); 11366 unsigned Align = MI->getOperand(8).getImm(); 11367 11368 // Memory Reference 11369 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11370 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11371 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11372 11373 // Machine Information 11374 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11375 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11376 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11377 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11378 DebugLoc DL = MI->getDebugLoc(); 11379 11380 // struct va_list { 11381 // i32 gp_offset 11382 // i32 fp_offset 11383 // i64 overflow_area (address) 11384 // i64 reg_save_area (address) 11385 // } 11386 // sizeof(va_list) = 24 11387 // alignment(va_list) = 8 11388 11389 unsigned TotalNumIntRegs = 6; 11390 unsigned TotalNumXMMRegs = 8; 11391 bool UseGPOffset = (ArgMode == 1); 11392 bool UseFPOffset = (ArgMode == 2); 11393 unsigned MaxOffset = TotalNumIntRegs * 8 + 11394 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11395 11396 /* Align ArgSize to a multiple of 8 */ 11397 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11398 bool NeedsAlign = (Align > 8); 11399 11400 MachineBasicBlock *thisMBB = MBB; 11401 MachineBasicBlock *overflowMBB; 11402 MachineBasicBlock *offsetMBB; 11403 MachineBasicBlock *endMBB; 11404 11405 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11406 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11407 unsigned OffsetReg = 0; 11408 11409 if (!UseGPOffset && !UseFPOffset) { 11410 // If we only pull from the overflow region, we don't create a branch. 11411 // We don't need to alter control flow. 11412 OffsetDestReg = 0; // unused 11413 OverflowDestReg = DestReg; 11414 11415 offsetMBB = NULL; 11416 overflowMBB = thisMBB; 11417 endMBB = thisMBB; 11418 } else { 11419 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11420 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11421 // If not, pull from overflow_area. (branch to overflowMBB) 11422 // 11423 // thisMBB 11424 // | . 11425 // | . 11426 // offsetMBB overflowMBB 11427 // | . 11428 // | . 11429 // endMBB 11430 11431 // Registers for the PHI in endMBB 11432 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11433 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11434 11435 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11436 MachineFunction *MF = MBB->getParent(); 11437 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11438 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11439 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11440 11441 MachineFunction::iterator MBBIter = MBB; 11442 ++MBBIter; 11443 11444 // Insert the new basic blocks 11445 MF->insert(MBBIter, offsetMBB); 11446 MF->insert(MBBIter, overflowMBB); 11447 MF->insert(MBBIter, endMBB); 11448 11449 // Transfer the remainder of MBB and its successor edges to endMBB. 11450 endMBB->splice(endMBB->begin(), thisMBB, 11451 llvm::next(MachineBasicBlock::iterator(MI)), 11452 thisMBB->end()); 11453 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11454 11455 // Make offsetMBB and overflowMBB successors of thisMBB 11456 thisMBB->addSuccessor(offsetMBB); 11457 thisMBB->addSuccessor(overflowMBB); 11458 11459 // endMBB is a successor of both offsetMBB and overflowMBB 11460 offsetMBB->addSuccessor(endMBB); 11461 overflowMBB->addSuccessor(endMBB); 11462 11463 // Load the offset value into a register 11464 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11465 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11466 .addOperand(Base) 11467 .addOperand(Scale) 11468 .addOperand(Index) 11469 .addDisp(Disp, UseFPOffset ? 4 : 0) 11470 .addOperand(Segment) 11471 .setMemRefs(MMOBegin, MMOEnd); 11472 11473 // Check if there is enough room left to pull this argument. 11474 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11475 .addReg(OffsetReg) 11476 .addImm(MaxOffset + 8 - ArgSizeA8); 11477 11478 // Branch to "overflowMBB" if offset >= max 11479 // Fall through to "offsetMBB" otherwise 11480 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11481 .addMBB(overflowMBB); 11482 } 11483 11484 // In offsetMBB, emit code to use the reg_save_area. 11485 if (offsetMBB) { 11486 assert(OffsetReg != 0); 11487 11488 // Read the reg_save_area address. 11489 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11490 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11491 .addOperand(Base) 11492 .addOperand(Scale) 11493 .addOperand(Index) 11494 .addDisp(Disp, 16) 11495 .addOperand(Segment) 11496 .setMemRefs(MMOBegin, MMOEnd); 11497 11498 // Zero-extend the offset 11499 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11500 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11501 .addImm(0) 11502 .addReg(OffsetReg) 11503 .addImm(X86::sub_32bit); 11504 11505 // Add the offset to the reg_save_area to get the final address. 11506 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11507 .addReg(OffsetReg64) 11508 .addReg(RegSaveReg); 11509 11510 // Compute the offset for the next argument 11511 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11512 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11513 .addReg(OffsetReg) 11514 .addImm(UseFPOffset ? 16 : 8); 11515 11516 // Store it back into the va_list. 11517 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11518 .addOperand(Base) 11519 .addOperand(Scale) 11520 .addOperand(Index) 11521 .addDisp(Disp, UseFPOffset ? 4 : 0) 11522 .addOperand(Segment) 11523 .addReg(NextOffsetReg) 11524 .setMemRefs(MMOBegin, MMOEnd); 11525 11526 // Jump to endMBB 11527 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11528 .addMBB(endMBB); 11529 } 11530 11531 // 11532 // Emit code to use overflow area 11533 // 11534 11535 // Load the overflow_area address into a register. 11536 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11537 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11538 .addOperand(Base) 11539 .addOperand(Scale) 11540 .addOperand(Index) 11541 .addDisp(Disp, 8) 11542 .addOperand(Segment) 11543 .setMemRefs(MMOBegin, MMOEnd); 11544 11545 // If we need to align it, do so. Otherwise, just copy the address 11546 // to OverflowDestReg. 11547 if (NeedsAlign) { 11548 // Align the overflow address 11549 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11550 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11551 11552 // aligned_addr = (addr + (align-1)) & ~(align-1) 11553 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11554 .addReg(OverflowAddrReg) 11555 .addImm(Align-1); 11556 11557 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11558 .addReg(TmpReg) 11559 .addImm(~(uint64_t)(Align-1)); 11560 } else { 11561 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11562 .addReg(OverflowAddrReg); 11563 } 11564 11565 // Compute the next overflow address after this argument. 11566 // (the overflow address should be kept 8-byte aligned) 11567 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11568 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11569 .addReg(OverflowDestReg) 11570 .addImm(ArgSizeA8); 11571 11572 // Store the new overflow address. 11573 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11574 .addOperand(Base) 11575 .addOperand(Scale) 11576 .addOperand(Index) 11577 .addDisp(Disp, 8) 11578 .addOperand(Segment) 11579 .addReg(NextAddrReg) 11580 .setMemRefs(MMOBegin, MMOEnd); 11581 11582 // If we branched, emit the PHI to the front of endMBB. 11583 if (offsetMBB) { 11584 BuildMI(*endMBB, endMBB->begin(), DL, 11585 TII->get(X86::PHI), DestReg) 11586 .addReg(OffsetDestReg).addMBB(offsetMBB) 11587 .addReg(OverflowDestReg).addMBB(overflowMBB); 11588 } 11589 11590 // Erase the pseudo instruction 11591 MI->eraseFromParent(); 11592 11593 return endMBB; 11594} 11595 11596MachineBasicBlock * 11597X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11598 MachineInstr *MI, 11599 MachineBasicBlock *MBB) const { 11600 // Emit code to save XMM registers to the stack. The ABI says that the 11601 // number of registers to save is given in %al, so it's theoretically 11602 // possible to do an indirect jump trick to avoid saving all of them, 11603 // however this code takes a simpler approach and just executes all 11604 // of the stores if %al is non-zero. It's less code, and it's probably 11605 // easier on the hardware branch predictor, and stores aren't all that 11606 // expensive anyway. 11607 11608 // Create the new basic blocks. One block contains all the XMM stores, 11609 // and one block is the final destination regardless of whether any 11610 // stores were performed. 11611 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11612 MachineFunction *F = MBB->getParent(); 11613 MachineFunction::iterator MBBIter = MBB; 11614 ++MBBIter; 11615 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11616 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11617 F->insert(MBBIter, XMMSaveMBB); 11618 F->insert(MBBIter, EndMBB); 11619 11620 // Transfer the remainder of MBB and its successor edges to EndMBB. 11621 EndMBB->splice(EndMBB->begin(), MBB, 11622 llvm::next(MachineBasicBlock::iterator(MI)), 11623 MBB->end()); 11624 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11625 11626 // The original block will now fall through to the XMM save block. 11627 MBB->addSuccessor(XMMSaveMBB); 11628 // The XMMSaveMBB will fall through to the end block. 11629 XMMSaveMBB->addSuccessor(EndMBB); 11630 11631 // Now add the instructions. 11632 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11633 DebugLoc DL = MI->getDebugLoc(); 11634 11635 unsigned CountReg = MI->getOperand(0).getReg(); 11636 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11637 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11638 11639 if (!Subtarget->isTargetWin64()) { 11640 // If %al is 0, branch around the XMM save block. 11641 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11642 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11643 MBB->addSuccessor(EndMBB); 11644 } 11645 11646 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11647 // In the XMM save block, save all the XMM argument registers. 11648 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11649 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11650 MachineMemOperand *MMO = 11651 F->getMachineMemOperand( 11652 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11653 MachineMemOperand::MOStore, 11654 /*Size=*/16, /*Align=*/16); 11655 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11656 .addFrameIndex(RegSaveFrameIndex) 11657 .addImm(/*Scale=*/1) 11658 .addReg(/*IndexReg=*/0) 11659 .addImm(/*Disp=*/Offset) 11660 .addReg(/*Segment=*/0) 11661 .addReg(MI->getOperand(i).getReg()) 11662 .addMemOperand(MMO); 11663 } 11664 11665 MI->eraseFromParent(); // The pseudo instruction is gone now. 11666 11667 return EndMBB; 11668} 11669 11670MachineBasicBlock * 11671X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11672 MachineBasicBlock *BB) const { 11673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11674 DebugLoc DL = MI->getDebugLoc(); 11675 11676 // To "insert" a SELECT_CC instruction, we actually have to insert the 11677 // diamond control-flow pattern. The incoming instruction knows the 11678 // destination vreg to set, the condition code register to branch on, the 11679 // true/false values to select between, and a branch opcode to use. 11680 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11681 MachineFunction::iterator It = BB; 11682 ++It; 11683 11684 // thisMBB: 11685 // ... 11686 // TrueVal = ... 11687 // cmpTY ccX, r1, r2 11688 // bCC copy1MBB 11689 // fallthrough --> copy0MBB 11690 MachineBasicBlock *thisMBB = BB; 11691 MachineFunction *F = BB->getParent(); 11692 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11693 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11694 F->insert(It, copy0MBB); 11695 F->insert(It, sinkMBB); 11696 11697 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11698 // live into the sink and copy blocks. 11699 if (!MI->killsRegister(X86::EFLAGS)) { 11700 copy0MBB->addLiveIn(X86::EFLAGS); 11701 sinkMBB->addLiveIn(X86::EFLAGS); 11702 } 11703 11704 // Transfer the remainder of BB and its successor edges to sinkMBB. 11705 sinkMBB->splice(sinkMBB->begin(), BB, 11706 llvm::next(MachineBasicBlock::iterator(MI)), 11707 BB->end()); 11708 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11709 11710 // Add the true and fallthrough blocks as its successors. 11711 BB->addSuccessor(copy0MBB); 11712 BB->addSuccessor(sinkMBB); 11713 11714 // Create the conditional branch instruction. 11715 unsigned Opc = 11716 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11717 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11718 11719 // copy0MBB: 11720 // %FalseValue = ... 11721 // # fallthrough to sinkMBB 11722 copy0MBB->addSuccessor(sinkMBB); 11723 11724 // sinkMBB: 11725 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11726 // ... 11727 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11728 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11729 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11730 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11731 11732 MI->eraseFromParent(); // The pseudo instruction is gone now. 11733 return sinkMBB; 11734} 11735 11736MachineBasicBlock * 11737X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 11738 bool Is64Bit) const { 11739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11740 DebugLoc DL = MI->getDebugLoc(); 11741 MachineFunction *MF = BB->getParent(); 11742 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11743 11744 assert(EnableSegmentedStacks); 11745 11746 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 11747 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 11748 11749 // BB: 11750 // ... [Till the alloca] 11751 // If stacklet is not large enough, jump to mallocMBB 11752 // 11753 // bumpMBB: 11754 // Allocate by subtracting from RSP 11755 // Jump to continueMBB 11756 // 11757 // mallocMBB: 11758 // Allocate by call to runtime 11759 // 11760 // continueMBB: 11761 // ... 11762 // [rest of original BB] 11763 // 11764 11765 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11766 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11767 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11768 11769 MachineRegisterInfo &MRI = MF->getRegInfo(); 11770 const TargetRegisterClass *AddrRegClass = 11771 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 11772 11773 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11774 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11775 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 11776 sizeVReg = MI->getOperand(1).getReg(), 11777 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 11778 11779 MachineFunction::iterator MBBIter = BB; 11780 ++MBBIter; 11781 11782 MF->insert(MBBIter, bumpMBB); 11783 MF->insert(MBBIter, mallocMBB); 11784 MF->insert(MBBIter, continueMBB); 11785 11786 continueMBB->splice(continueMBB->begin(), BB, llvm::next 11787 (MachineBasicBlock::iterator(MI)), BB->end()); 11788 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 11789 11790 // Add code to the main basic block to check if the stack limit has been hit, 11791 // and if so, jump to mallocMBB otherwise to bumpMBB. 11792 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 11793 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg) 11794 .addReg(tmpSPVReg).addReg(sizeVReg); 11795 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 11796 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 11797 .addReg(tmpSPVReg); 11798 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 11799 11800 // bumpMBB simply decreases the stack pointer, since we know the current 11801 // stacklet has enough space. 11802 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 11803 .addReg(tmpSPVReg); 11804 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 11805 .addReg(tmpSPVReg); 11806 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11807 11808 // Calls into a routine in libgcc to allocate more space from the heap. 11809 if (Is64Bit) { 11810 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 11811 .addReg(sizeVReg); 11812 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 11813 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 11814 } else { 11815 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 11816 .addImm(12); 11817 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 11818 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 11819 .addExternalSymbol("__morestack_allocate_stack_space"); 11820 } 11821 11822 if (!Is64Bit) 11823 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 11824 .addImm(16); 11825 11826 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 11827 .addReg(Is64Bit ? X86::RAX : X86::EAX); 11828 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11829 11830 // Set up the CFG correctly. 11831 BB->addSuccessor(bumpMBB); 11832 BB->addSuccessor(mallocMBB); 11833 mallocMBB->addSuccessor(continueMBB); 11834 bumpMBB->addSuccessor(continueMBB); 11835 11836 // Take care of the PHI nodes. 11837 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 11838 MI->getOperand(0).getReg()) 11839 .addReg(mallocPtrVReg).addMBB(mallocMBB) 11840 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 11841 11842 // Delete the original pseudo instruction. 11843 MI->eraseFromParent(); 11844 11845 // And we're done. 11846 return continueMBB; 11847} 11848 11849MachineBasicBlock * 11850X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 11851 MachineBasicBlock *BB) const { 11852 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11853 DebugLoc DL = MI->getDebugLoc(); 11854 11855 assert(!Subtarget->isTargetEnvMacho()); 11856 11857 // The lowering is pretty easy: we're just emitting the call to _alloca. The 11858 // non-trivial part is impdef of ESP. 11859 11860 if (Subtarget->isTargetWin64()) { 11861 if (Subtarget->isTargetCygMing()) { 11862 // ___chkstk(Mingw64): 11863 // Clobbers R10, R11, RAX and EFLAGS. 11864 // Updates RSP. 11865 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11866 .addExternalSymbol("___chkstk") 11867 .addReg(X86::RAX, RegState::Implicit) 11868 .addReg(X86::RSP, RegState::Implicit) 11869 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 11870 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 11871 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11872 } else { 11873 // __chkstk(MSVCRT): does not update stack pointer. 11874 // Clobbers R10, R11 and EFLAGS. 11875 // FIXME: RAX(allocated size) might be reused and not killed. 11876 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11877 .addExternalSymbol("__chkstk") 11878 .addReg(X86::RAX, RegState::Implicit) 11879 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11880 // RAX has the offset to subtracted from RSP. 11881 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 11882 .addReg(X86::RSP) 11883 .addReg(X86::RAX); 11884 } 11885 } else { 11886 const char *StackProbeSymbol = 11887 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 11888 11889 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 11890 .addExternalSymbol(StackProbeSymbol) 11891 .addReg(X86::EAX, RegState::Implicit) 11892 .addReg(X86::ESP, RegState::Implicit) 11893 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 11894 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 11895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11896 } 11897 11898 MI->eraseFromParent(); // The pseudo instruction is gone now. 11899 return BB; 11900} 11901 11902MachineBasicBlock * 11903X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 11904 MachineBasicBlock *BB) const { 11905 // This is pretty easy. We're taking the value that we received from 11906 // our load from the relocation, sticking it in either RDI (x86-64) 11907 // or EAX and doing an indirect call. The return value will then 11908 // be in the normal return register. 11909 const X86InstrInfo *TII 11910 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 11911 DebugLoc DL = MI->getDebugLoc(); 11912 MachineFunction *F = BB->getParent(); 11913 11914 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 11915 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 11916 11917 if (Subtarget->is64Bit()) { 11918 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11919 TII->get(X86::MOV64rm), X86::RDI) 11920 .addReg(X86::RIP) 11921 .addImm(0).addReg(0) 11922 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11923 MI->getOperand(3).getTargetFlags()) 11924 .addReg(0); 11925 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 11926 addDirectMem(MIB, X86::RDI); 11927 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 11928 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11929 TII->get(X86::MOV32rm), X86::EAX) 11930 .addReg(0) 11931 .addImm(0).addReg(0) 11932 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11933 MI->getOperand(3).getTargetFlags()) 11934 .addReg(0); 11935 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11936 addDirectMem(MIB, X86::EAX); 11937 } else { 11938 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11939 TII->get(X86::MOV32rm), X86::EAX) 11940 .addReg(TII->getGlobalBaseReg(F)) 11941 .addImm(0).addReg(0) 11942 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11943 MI->getOperand(3).getTargetFlags()) 11944 .addReg(0); 11945 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11946 addDirectMem(MIB, X86::EAX); 11947 } 11948 11949 MI->eraseFromParent(); // The pseudo instruction is gone now. 11950 return BB; 11951} 11952 11953MachineBasicBlock * 11954X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 11955 MachineBasicBlock *BB) const { 11956 switch (MI->getOpcode()) { 11957 default: assert(0 && "Unexpected instr type to insert"); 11958 case X86::TAILJMPd64: 11959 case X86::TAILJMPr64: 11960 case X86::TAILJMPm64: 11961 assert(0 && "TAILJMP64 would not be touched here."); 11962 case X86::TCRETURNdi64: 11963 case X86::TCRETURNri64: 11964 case X86::TCRETURNmi64: 11965 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 11966 // On AMD64, additional defs should be added before register allocation. 11967 if (!Subtarget->isTargetWin64()) { 11968 MI->addRegisterDefined(X86::RSI); 11969 MI->addRegisterDefined(X86::RDI); 11970 MI->addRegisterDefined(X86::XMM6); 11971 MI->addRegisterDefined(X86::XMM7); 11972 MI->addRegisterDefined(X86::XMM8); 11973 MI->addRegisterDefined(X86::XMM9); 11974 MI->addRegisterDefined(X86::XMM10); 11975 MI->addRegisterDefined(X86::XMM11); 11976 MI->addRegisterDefined(X86::XMM12); 11977 MI->addRegisterDefined(X86::XMM13); 11978 MI->addRegisterDefined(X86::XMM14); 11979 MI->addRegisterDefined(X86::XMM15); 11980 } 11981 return BB; 11982 case X86::WIN_ALLOCA: 11983 return EmitLoweredWinAlloca(MI, BB); 11984 case X86::SEG_ALLOCA_32: 11985 return EmitLoweredSegAlloca(MI, BB, false); 11986 case X86::SEG_ALLOCA_64: 11987 return EmitLoweredSegAlloca(MI, BB, true); 11988 case X86::TLSCall_32: 11989 case X86::TLSCall_64: 11990 return EmitLoweredTLSCall(MI, BB); 11991 case X86::CMOV_GR8: 11992 case X86::CMOV_FR32: 11993 case X86::CMOV_FR64: 11994 case X86::CMOV_V4F32: 11995 case X86::CMOV_V2F64: 11996 case X86::CMOV_V2I64: 11997 case X86::CMOV_V8F32: 11998 case X86::CMOV_V4F64: 11999 case X86::CMOV_V4I64: 12000 case X86::CMOV_GR16: 12001 case X86::CMOV_GR32: 12002 case X86::CMOV_RFP32: 12003 case X86::CMOV_RFP64: 12004 case X86::CMOV_RFP80: 12005 return EmitLoweredSelect(MI, BB); 12006 12007 case X86::FP32_TO_INT16_IN_MEM: 12008 case X86::FP32_TO_INT32_IN_MEM: 12009 case X86::FP32_TO_INT64_IN_MEM: 12010 case X86::FP64_TO_INT16_IN_MEM: 12011 case X86::FP64_TO_INT32_IN_MEM: 12012 case X86::FP64_TO_INT64_IN_MEM: 12013 case X86::FP80_TO_INT16_IN_MEM: 12014 case X86::FP80_TO_INT32_IN_MEM: 12015 case X86::FP80_TO_INT64_IN_MEM: { 12016 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12017 DebugLoc DL = MI->getDebugLoc(); 12018 12019 // Change the floating point control register to use "round towards zero" 12020 // mode when truncating to an integer value. 12021 MachineFunction *F = BB->getParent(); 12022 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12023 addFrameReference(BuildMI(*BB, MI, DL, 12024 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12025 12026 // Load the old value of the high byte of the control word... 12027 unsigned OldCW = 12028 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12029 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12030 CWFrameIdx); 12031 12032 // Set the high part to be round to zero... 12033 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12034 .addImm(0xC7F); 12035 12036 // Reload the modified control word now... 12037 addFrameReference(BuildMI(*BB, MI, DL, 12038 TII->get(X86::FLDCW16m)), CWFrameIdx); 12039 12040 // Restore the memory image of control word to original value 12041 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12042 .addReg(OldCW); 12043 12044 // Get the X86 opcode to use. 12045 unsigned Opc; 12046 switch (MI->getOpcode()) { 12047 default: llvm_unreachable("illegal opcode!"); 12048 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12049 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12050 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12051 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12052 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12053 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12054 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12055 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12056 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12057 } 12058 12059 X86AddressMode AM; 12060 MachineOperand &Op = MI->getOperand(0); 12061 if (Op.isReg()) { 12062 AM.BaseType = X86AddressMode::RegBase; 12063 AM.Base.Reg = Op.getReg(); 12064 } else { 12065 AM.BaseType = X86AddressMode::FrameIndexBase; 12066 AM.Base.FrameIndex = Op.getIndex(); 12067 } 12068 Op = MI->getOperand(1); 12069 if (Op.isImm()) 12070 AM.Scale = Op.getImm(); 12071 Op = MI->getOperand(2); 12072 if (Op.isImm()) 12073 AM.IndexReg = Op.getImm(); 12074 Op = MI->getOperand(3); 12075 if (Op.isGlobal()) { 12076 AM.GV = Op.getGlobal(); 12077 } else { 12078 AM.Disp = Op.getImm(); 12079 } 12080 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12081 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12082 12083 // Reload the original control word now. 12084 addFrameReference(BuildMI(*BB, MI, DL, 12085 TII->get(X86::FLDCW16m)), CWFrameIdx); 12086 12087 MI->eraseFromParent(); // The pseudo instruction is gone now. 12088 return BB; 12089 } 12090 // String/text processing lowering. 12091 case X86::PCMPISTRM128REG: 12092 case X86::VPCMPISTRM128REG: 12093 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12094 case X86::PCMPISTRM128MEM: 12095 case X86::VPCMPISTRM128MEM: 12096 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12097 case X86::PCMPESTRM128REG: 12098 case X86::VPCMPESTRM128REG: 12099 return EmitPCMP(MI, BB, 5, false /* in mem */); 12100 case X86::PCMPESTRM128MEM: 12101 case X86::VPCMPESTRM128MEM: 12102 return EmitPCMP(MI, BB, 5, true /* in mem */); 12103 12104 // Thread synchronization. 12105 case X86::MONITOR: 12106 return EmitMonitor(MI, BB); 12107 case X86::MWAIT: 12108 return EmitMwait(MI, BB); 12109 12110 // Atomic Lowering. 12111 case X86::ATOMAND32: 12112 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12113 X86::AND32ri, X86::MOV32rm, 12114 X86::LCMPXCHG32, 12115 X86::NOT32r, X86::EAX, 12116 X86::GR32RegisterClass); 12117 case X86::ATOMOR32: 12118 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12119 X86::OR32ri, X86::MOV32rm, 12120 X86::LCMPXCHG32, 12121 X86::NOT32r, X86::EAX, 12122 X86::GR32RegisterClass); 12123 case X86::ATOMXOR32: 12124 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12125 X86::XOR32ri, X86::MOV32rm, 12126 X86::LCMPXCHG32, 12127 X86::NOT32r, X86::EAX, 12128 X86::GR32RegisterClass); 12129 case X86::ATOMNAND32: 12130 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12131 X86::AND32ri, X86::MOV32rm, 12132 X86::LCMPXCHG32, 12133 X86::NOT32r, X86::EAX, 12134 X86::GR32RegisterClass, true); 12135 case X86::ATOMMIN32: 12136 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12137 case X86::ATOMMAX32: 12138 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12139 case X86::ATOMUMIN32: 12140 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12141 case X86::ATOMUMAX32: 12142 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12143 12144 case X86::ATOMAND16: 12145 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12146 X86::AND16ri, X86::MOV16rm, 12147 X86::LCMPXCHG16, 12148 X86::NOT16r, X86::AX, 12149 X86::GR16RegisterClass); 12150 case X86::ATOMOR16: 12151 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12152 X86::OR16ri, X86::MOV16rm, 12153 X86::LCMPXCHG16, 12154 X86::NOT16r, X86::AX, 12155 X86::GR16RegisterClass); 12156 case X86::ATOMXOR16: 12157 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12158 X86::XOR16ri, X86::MOV16rm, 12159 X86::LCMPXCHG16, 12160 X86::NOT16r, X86::AX, 12161 X86::GR16RegisterClass); 12162 case X86::ATOMNAND16: 12163 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12164 X86::AND16ri, X86::MOV16rm, 12165 X86::LCMPXCHG16, 12166 X86::NOT16r, X86::AX, 12167 X86::GR16RegisterClass, true); 12168 case X86::ATOMMIN16: 12169 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12170 case X86::ATOMMAX16: 12171 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12172 case X86::ATOMUMIN16: 12173 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12174 case X86::ATOMUMAX16: 12175 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12176 12177 case X86::ATOMAND8: 12178 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12179 X86::AND8ri, X86::MOV8rm, 12180 X86::LCMPXCHG8, 12181 X86::NOT8r, X86::AL, 12182 X86::GR8RegisterClass); 12183 case X86::ATOMOR8: 12184 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12185 X86::OR8ri, X86::MOV8rm, 12186 X86::LCMPXCHG8, 12187 X86::NOT8r, X86::AL, 12188 X86::GR8RegisterClass); 12189 case X86::ATOMXOR8: 12190 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12191 X86::XOR8ri, X86::MOV8rm, 12192 X86::LCMPXCHG8, 12193 X86::NOT8r, X86::AL, 12194 X86::GR8RegisterClass); 12195 case X86::ATOMNAND8: 12196 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12197 X86::AND8ri, X86::MOV8rm, 12198 X86::LCMPXCHG8, 12199 X86::NOT8r, X86::AL, 12200 X86::GR8RegisterClass, true); 12201 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12202 // This group is for 64-bit host. 12203 case X86::ATOMAND64: 12204 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12205 X86::AND64ri32, X86::MOV64rm, 12206 X86::LCMPXCHG64, 12207 X86::NOT64r, X86::RAX, 12208 X86::GR64RegisterClass); 12209 case X86::ATOMOR64: 12210 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12211 X86::OR64ri32, X86::MOV64rm, 12212 X86::LCMPXCHG64, 12213 X86::NOT64r, X86::RAX, 12214 X86::GR64RegisterClass); 12215 case X86::ATOMXOR64: 12216 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12217 X86::XOR64ri32, X86::MOV64rm, 12218 X86::LCMPXCHG64, 12219 X86::NOT64r, X86::RAX, 12220 X86::GR64RegisterClass); 12221 case X86::ATOMNAND64: 12222 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12223 X86::AND64ri32, X86::MOV64rm, 12224 X86::LCMPXCHG64, 12225 X86::NOT64r, X86::RAX, 12226 X86::GR64RegisterClass, true); 12227 case X86::ATOMMIN64: 12228 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12229 case X86::ATOMMAX64: 12230 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12231 case X86::ATOMUMIN64: 12232 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12233 case X86::ATOMUMAX64: 12234 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12235 12236 // This group does 64-bit operations on a 32-bit host. 12237 case X86::ATOMAND6432: 12238 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12239 X86::AND32rr, X86::AND32rr, 12240 X86::AND32ri, X86::AND32ri, 12241 false); 12242 case X86::ATOMOR6432: 12243 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12244 X86::OR32rr, X86::OR32rr, 12245 X86::OR32ri, X86::OR32ri, 12246 false); 12247 case X86::ATOMXOR6432: 12248 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12249 X86::XOR32rr, X86::XOR32rr, 12250 X86::XOR32ri, X86::XOR32ri, 12251 false); 12252 case X86::ATOMNAND6432: 12253 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12254 X86::AND32rr, X86::AND32rr, 12255 X86::AND32ri, X86::AND32ri, 12256 true); 12257 case X86::ATOMADD6432: 12258 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12259 X86::ADD32rr, X86::ADC32rr, 12260 X86::ADD32ri, X86::ADC32ri, 12261 false); 12262 case X86::ATOMSUB6432: 12263 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12264 X86::SUB32rr, X86::SBB32rr, 12265 X86::SUB32ri, X86::SBB32ri, 12266 false); 12267 case X86::ATOMSWAP6432: 12268 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12269 X86::MOV32rr, X86::MOV32rr, 12270 X86::MOV32ri, X86::MOV32ri, 12271 false); 12272 case X86::VASTART_SAVE_XMM_REGS: 12273 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12274 12275 case X86::VAARG_64: 12276 return EmitVAARG64WithCustomInserter(MI, BB); 12277 } 12278} 12279 12280//===----------------------------------------------------------------------===// 12281// X86 Optimization Hooks 12282//===----------------------------------------------------------------------===// 12283 12284void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12285 const APInt &Mask, 12286 APInt &KnownZero, 12287 APInt &KnownOne, 12288 const SelectionDAG &DAG, 12289 unsigned Depth) const { 12290 unsigned Opc = Op.getOpcode(); 12291 assert((Opc >= ISD::BUILTIN_OP_END || 12292 Opc == ISD::INTRINSIC_WO_CHAIN || 12293 Opc == ISD::INTRINSIC_W_CHAIN || 12294 Opc == ISD::INTRINSIC_VOID) && 12295 "Should use MaskedValueIsZero if you don't know whether Op" 12296 " is a target node!"); 12297 12298 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12299 switch (Opc) { 12300 default: break; 12301 case X86ISD::ADD: 12302 case X86ISD::SUB: 12303 case X86ISD::ADC: 12304 case X86ISD::SBB: 12305 case X86ISD::SMUL: 12306 case X86ISD::UMUL: 12307 case X86ISD::INC: 12308 case X86ISD::DEC: 12309 case X86ISD::OR: 12310 case X86ISD::XOR: 12311 case X86ISD::AND: 12312 // These nodes' second result is a boolean. 12313 if (Op.getResNo() == 0) 12314 break; 12315 // Fallthrough 12316 case X86ISD::SETCC: 12317 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12318 Mask.getBitWidth() - 1); 12319 break; 12320 case ISD::INTRINSIC_WO_CHAIN: { 12321 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12322 unsigned NumLoBits = 0; 12323 switch (IntId) { 12324 default: break; 12325 case Intrinsic::x86_sse_movmsk_ps: 12326 case Intrinsic::x86_avx_movmsk_ps_256: 12327 case Intrinsic::x86_sse2_movmsk_pd: 12328 case Intrinsic::x86_avx_movmsk_pd_256: 12329 case Intrinsic::x86_mmx_pmovmskb: 12330 case Intrinsic::x86_sse2_pmovmskb_128: { 12331 // High bits of movmskp{s|d}, pmovmskb are known zero. 12332 switch (IntId) { 12333 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12334 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12335 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12336 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12337 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12338 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12339 } 12340 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12341 Mask.getBitWidth() - NumLoBits); 12342 break; 12343 } 12344 } 12345 break; 12346 } 12347 } 12348} 12349 12350unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12351 unsigned Depth) const { 12352 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12353 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12354 return Op.getValueType().getScalarType().getSizeInBits(); 12355 12356 // Fallback case. 12357 return 1; 12358} 12359 12360/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12361/// node is a GlobalAddress + offset. 12362bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12363 const GlobalValue* &GA, 12364 int64_t &Offset) const { 12365 if (N->getOpcode() == X86ISD::Wrapper) { 12366 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12367 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12368 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12369 return true; 12370 } 12371 } 12372 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12373} 12374 12375/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12376/// same as extracting the high 128-bit part of 256-bit vector and then 12377/// inserting the result into the low part of a new 256-bit vector 12378static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12379 EVT VT = SVOp->getValueType(0); 12380 int NumElems = VT.getVectorNumElements(); 12381 12382 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12383 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12384 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12385 SVOp->getMaskElt(j) >= 0) 12386 return false; 12387 12388 return true; 12389} 12390 12391/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12392/// same as extracting the low 128-bit part of 256-bit vector and then 12393/// inserting the result into the high part of a new 256-bit vector 12394static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12395 EVT VT = SVOp->getValueType(0); 12396 int NumElems = VT.getVectorNumElements(); 12397 12398 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12399 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12400 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12401 SVOp->getMaskElt(j) >= 0) 12402 return false; 12403 12404 return true; 12405} 12406 12407/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12408static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12409 TargetLowering::DAGCombinerInfo &DCI) { 12410 DebugLoc dl = N->getDebugLoc(); 12411 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12412 SDValue V1 = SVOp->getOperand(0); 12413 SDValue V2 = SVOp->getOperand(1); 12414 EVT VT = SVOp->getValueType(0); 12415 int NumElems = VT.getVectorNumElements(); 12416 12417 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12418 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12419 // 12420 // 0,0,0,... 12421 // | 12422 // V UNDEF BUILD_VECTOR UNDEF 12423 // \ / \ / 12424 // CONCAT_VECTOR CONCAT_VECTOR 12425 // \ / 12426 // \ / 12427 // RESULT: V + zero extended 12428 // 12429 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12430 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12431 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12432 return SDValue(); 12433 12434 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12435 return SDValue(); 12436 12437 // To match the shuffle mask, the first half of the mask should 12438 // be exactly the first vector, and all the rest a splat with the 12439 // first element of the second one. 12440 for (int i = 0; i < NumElems/2; ++i) 12441 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12442 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12443 return SDValue(); 12444 12445 // Emit a zeroed vector and insert the desired subvector on its 12446 // first half. 12447 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 12448 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12449 DAG.getConstant(0, MVT::i32), DAG, dl); 12450 return DCI.CombineTo(N, InsV); 12451 } 12452 12453 //===--------------------------------------------------------------------===// 12454 // Combine some shuffles into subvector extracts and inserts: 12455 // 12456 12457 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12458 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12459 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12460 DAG, dl); 12461 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12462 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12463 return DCI.CombineTo(N, InsV); 12464 } 12465 12466 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12467 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12468 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12469 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12470 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12471 return DCI.CombineTo(N, InsV); 12472 } 12473 12474 return SDValue(); 12475} 12476 12477/// PerformShuffleCombine - Performs several different shuffle combines. 12478static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12479 TargetLowering::DAGCombinerInfo &DCI, 12480 const X86Subtarget *Subtarget) { 12481 DebugLoc dl = N->getDebugLoc(); 12482 EVT VT = N->getValueType(0); 12483 12484 // Don't create instructions with illegal types after legalize types has run. 12485 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12486 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12487 return SDValue(); 12488 12489 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12490 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12491 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12492 return PerformShuffleCombine256(N, DAG, DCI); 12493 12494 // Only handle 128 wide vector from here on. 12495 if (VT.getSizeInBits() != 128) 12496 return SDValue(); 12497 12498 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12499 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12500 // consecutive, non-overlapping, and in the right order. 12501 SmallVector<SDValue, 16> Elts; 12502 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12503 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12504 12505 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12506} 12507 12508/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12509/// generation and convert it from being a bunch of shuffles and extracts 12510/// to a simple store and scalar loads to extract the elements. 12511static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12512 const TargetLowering &TLI) { 12513 SDValue InputVector = N->getOperand(0); 12514 12515 // Only operate on vectors of 4 elements, where the alternative shuffling 12516 // gets to be more expensive. 12517 if (InputVector.getValueType() != MVT::v4i32) 12518 return SDValue(); 12519 12520 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12521 // single use which is a sign-extend or zero-extend, and all elements are 12522 // used. 12523 SmallVector<SDNode *, 4> Uses; 12524 unsigned ExtractedElements = 0; 12525 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12526 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12527 if (UI.getUse().getResNo() != InputVector.getResNo()) 12528 return SDValue(); 12529 12530 SDNode *Extract = *UI; 12531 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12532 return SDValue(); 12533 12534 if (Extract->getValueType(0) != MVT::i32) 12535 return SDValue(); 12536 if (!Extract->hasOneUse()) 12537 return SDValue(); 12538 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12539 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12540 return SDValue(); 12541 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12542 return SDValue(); 12543 12544 // Record which element was extracted. 12545 ExtractedElements |= 12546 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12547 12548 Uses.push_back(Extract); 12549 } 12550 12551 // If not all the elements were used, this may not be worthwhile. 12552 if (ExtractedElements != 15) 12553 return SDValue(); 12554 12555 // Ok, we've now decided to do the transformation. 12556 DebugLoc dl = InputVector.getDebugLoc(); 12557 12558 // Store the value to a temporary stack slot. 12559 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12560 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12561 MachinePointerInfo(), false, false, 0); 12562 12563 // Replace each use (extract) with a load of the appropriate element. 12564 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12565 UE = Uses.end(); UI != UE; ++UI) { 12566 SDNode *Extract = *UI; 12567 12568 // cOMpute the element's address. 12569 SDValue Idx = Extract->getOperand(1); 12570 unsigned EltSize = 12571 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12572 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12573 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12574 12575 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12576 StackPtr, OffsetVal); 12577 12578 // Load the scalar. 12579 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12580 ScalarAddr, MachinePointerInfo(), 12581 false, false, 0); 12582 12583 // Replace the exact with the load. 12584 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12585 } 12586 12587 // The replacement was made in place; don't return anything. 12588 return SDValue(); 12589} 12590 12591/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12592/// nodes. 12593static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12594 const X86Subtarget *Subtarget) { 12595 DebugLoc DL = N->getDebugLoc(); 12596 SDValue Cond = N->getOperand(0); 12597 // Get the LHS/RHS of the select. 12598 SDValue LHS = N->getOperand(1); 12599 SDValue RHS = N->getOperand(2); 12600 EVT VT = LHS.getValueType(); 12601 12602 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12603 // instructions match the semantics of the common C idiom x<y?x:y but not 12604 // x<=y?x:y, because of how they handle negative zero (which can be 12605 // ignored in unsafe-math mode). 12606 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12607 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12608 (Subtarget->hasXMMInt() || 12609 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12610 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12611 12612 unsigned Opcode = 0; 12613 // Check for x CC y ? x : y. 12614 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12615 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12616 switch (CC) { 12617 default: break; 12618 case ISD::SETULT: 12619 // Converting this to a min would handle NaNs incorrectly, and swapping 12620 // the operands would cause it to handle comparisons between positive 12621 // and negative zero incorrectly. 12622 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12623 if (!UnsafeFPMath && 12624 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12625 break; 12626 std::swap(LHS, RHS); 12627 } 12628 Opcode = X86ISD::FMIN; 12629 break; 12630 case ISD::SETOLE: 12631 // Converting this to a min would handle comparisons between positive 12632 // and negative zero incorrectly. 12633 if (!UnsafeFPMath && 12634 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12635 break; 12636 Opcode = X86ISD::FMIN; 12637 break; 12638 case ISD::SETULE: 12639 // Converting this to a min would handle both negative zeros and NaNs 12640 // incorrectly, but we can swap the operands to fix both. 12641 std::swap(LHS, RHS); 12642 case ISD::SETOLT: 12643 case ISD::SETLT: 12644 case ISD::SETLE: 12645 Opcode = X86ISD::FMIN; 12646 break; 12647 12648 case ISD::SETOGE: 12649 // Converting this to a max would handle comparisons between positive 12650 // and negative zero incorrectly. 12651 if (!UnsafeFPMath && 12652 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12653 break; 12654 Opcode = X86ISD::FMAX; 12655 break; 12656 case ISD::SETUGT: 12657 // Converting this to a max would handle NaNs incorrectly, and swapping 12658 // the operands would cause it to handle comparisons between positive 12659 // and negative zero incorrectly. 12660 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12661 if (!UnsafeFPMath && 12662 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12663 break; 12664 std::swap(LHS, RHS); 12665 } 12666 Opcode = X86ISD::FMAX; 12667 break; 12668 case ISD::SETUGE: 12669 // Converting this to a max would handle both negative zeros and NaNs 12670 // incorrectly, but we can swap the operands to fix both. 12671 std::swap(LHS, RHS); 12672 case ISD::SETOGT: 12673 case ISD::SETGT: 12674 case ISD::SETGE: 12675 Opcode = X86ISD::FMAX; 12676 break; 12677 } 12678 // Check for x CC y ? y : x -- a min/max with reversed arms. 12679 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12680 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12681 switch (CC) { 12682 default: break; 12683 case ISD::SETOGE: 12684 // Converting this to a min would handle comparisons between positive 12685 // and negative zero incorrectly, and swapping the operands would 12686 // cause it to handle NaNs incorrectly. 12687 if (!UnsafeFPMath && 12688 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12689 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12690 break; 12691 std::swap(LHS, RHS); 12692 } 12693 Opcode = X86ISD::FMIN; 12694 break; 12695 case ISD::SETUGT: 12696 // Converting this to a min would handle NaNs incorrectly. 12697 if (!UnsafeFPMath && 12698 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12699 break; 12700 Opcode = X86ISD::FMIN; 12701 break; 12702 case ISD::SETUGE: 12703 // Converting this to a min would handle both negative zeros and NaNs 12704 // incorrectly, but we can swap the operands to fix both. 12705 std::swap(LHS, RHS); 12706 case ISD::SETOGT: 12707 case ISD::SETGT: 12708 case ISD::SETGE: 12709 Opcode = X86ISD::FMIN; 12710 break; 12711 12712 case ISD::SETULT: 12713 // Converting this to a max would handle NaNs incorrectly. 12714 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12715 break; 12716 Opcode = X86ISD::FMAX; 12717 break; 12718 case ISD::SETOLE: 12719 // Converting this to a max would handle comparisons between positive 12720 // and negative zero incorrectly, and swapping the operands would 12721 // cause it to handle NaNs incorrectly. 12722 if (!UnsafeFPMath && 12723 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 12724 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12725 break; 12726 std::swap(LHS, RHS); 12727 } 12728 Opcode = X86ISD::FMAX; 12729 break; 12730 case ISD::SETULE: 12731 // Converting this to a max would handle both negative zeros and NaNs 12732 // incorrectly, but we can swap the operands to fix both. 12733 std::swap(LHS, RHS); 12734 case ISD::SETOLT: 12735 case ISD::SETLT: 12736 case ISD::SETLE: 12737 Opcode = X86ISD::FMAX; 12738 break; 12739 } 12740 } 12741 12742 if (Opcode) 12743 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 12744 } 12745 12746 // If this is a select between two integer constants, try to do some 12747 // optimizations. 12748 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 12749 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 12750 // Don't do this for crazy integer types. 12751 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 12752 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 12753 // so that TrueC (the true value) is larger than FalseC. 12754 bool NeedsCondInvert = false; 12755 12756 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 12757 // Efficiently invertible. 12758 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 12759 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 12760 isa<ConstantSDNode>(Cond.getOperand(1))))) { 12761 NeedsCondInvert = true; 12762 std::swap(TrueC, FalseC); 12763 } 12764 12765 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 12766 if (FalseC->getAPIntValue() == 0 && 12767 TrueC->getAPIntValue().isPowerOf2()) { 12768 if (NeedsCondInvert) // Invert the condition if needed. 12769 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12770 DAG.getConstant(1, Cond.getValueType())); 12771 12772 // Zero extend the condition if needed. 12773 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 12774 12775 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12776 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 12777 DAG.getConstant(ShAmt, MVT::i8)); 12778 } 12779 12780 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 12781 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12782 if (NeedsCondInvert) // Invert the condition if needed. 12783 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12784 DAG.getConstant(1, Cond.getValueType())); 12785 12786 // Zero extend the condition if needed. 12787 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12788 FalseC->getValueType(0), Cond); 12789 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12790 SDValue(FalseC, 0)); 12791 } 12792 12793 // Optimize cases that will turn into an LEA instruction. This requires 12794 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12795 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12796 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12797 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12798 12799 bool isFastMultiplier = false; 12800 if (Diff < 10) { 12801 switch ((unsigned char)Diff) { 12802 default: break; 12803 case 1: // result = add base, cond 12804 case 2: // result = lea base( , cond*2) 12805 case 3: // result = lea base(cond, cond*2) 12806 case 4: // result = lea base( , cond*4) 12807 case 5: // result = lea base(cond, cond*4) 12808 case 8: // result = lea base( , cond*8) 12809 case 9: // result = lea base(cond, cond*8) 12810 isFastMultiplier = true; 12811 break; 12812 } 12813 } 12814 12815 if (isFastMultiplier) { 12816 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12817 if (NeedsCondInvert) // Invert the condition if needed. 12818 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12819 DAG.getConstant(1, Cond.getValueType())); 12820 12821 // Zero extend the condition if needed. 12822 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12823 Cond); 12824 // Scale the condition by the difference. 12825 if (Diff != 1) 12826 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12827 DAG.getConstant(Diff, Cond.getValueType())); 12828 12829 // Add the base if non-zero. 12830 if (FalseC->getAPIntValue() != 0) 12831 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12832 SDValue(FalseC, 0)); 12833 return Cond; 12834 } 12835 } 12836 } 12837 } 12838 12839 return SDValue(); 12840} 12841 12842/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 12843static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 12844 TargetLowering::DAGCombinerInfo &DCI) { 12845 DebugLoc DL = N->getDebugLoc(); 12846 12847 // If the flag operand isn't dead, don't touch this CMOV. 12848 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 12849 return SDValue(); 12850 12851 SDValue FalseOp = N->getOperand(0); 12852 SDValue TrueOp = N->getOperand(1); 12853 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 12854 SDValue Cond = N->getOperand(3); 12855 if (CC == X86::COND_E || CC == X86::COND_NE) { 12856 switch (Cond.getOpcode()) { 12857 default: break; 12858 case X86ISD::BSR: 12859 case X86ISD::BSF: 12860 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 12861 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 12862 return (CC == X86::COND_E) ? FalseOp : TrueOp; 12863 } 12864 } 12865 12866 // If this is a select between two integer constants, try to do some 12867 // optimizations. Note that the operands are ordered the opposite of SELECT 12868 // operands. 12869 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 12870 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 12871 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 12872 // larger than FalseC (the false value). 12873 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 12874 CC = X86::GetOppositeBranchCondition(CC); 12875 std::swap(TrueC, FalseC); 12876 } 12877 12878 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 12879 // This is efficient for any integer data type (including i8/i16) and 12880 // shift amount. 12881 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 12882 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12883 DAG.getConstant(CC, MVT::i8), Cond); 12884 12885 // Zero extend the condition if needed. 12886 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 12887 12888 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12889 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 12890 DAG.getConstant(ShAmt, MVT::i8)); 12891 if (N->getNumValues() == 2) // Dead flag value? 12892 return DCI.CombineTo(N, Cond, SDValue()); 12893 return Cond; 12894 } 12895 12896 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 12897 // for any integer data type, including i8/i16. 12898 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12899 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12900 DAG.getConstant(CC, MVT::i8), Cond); 12901 12902 // Zero extend the condition if needed. 12903 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12904 FalseC->getValueType(0), Cond); 12905 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12906 SDValue(FalseC, 0)); 12907 12908 if (N->getNumValues() == 2) // Dead flag value? 12909 return DCI.CombineTo(N, Cond, SDValue()); 12910 return Cond; 12911 } 12912 12913 // Optimize cases that will turn into an LEA instruction. This requires 12914 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12915 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12916 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12917 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12918 12919 bool isFastMultiplier = false; 12920 if (Diff < 10) { 12921 switch ((unsigned char)Diff) { 12922 default: break; 12923 case 1: // result = add base, cond 12924 case 2: // result = lea base( , cond*2) 12925 case 3: // result = lea base(cond, cond*2) 12926 case 4: // result = lea base( , cond*4) 12927 case 5: // result = lea base(cond, cond*4) 12928 case 8: // result = lea base( , cond*8) 12929 case 9: // result = lea base(cond, cond*8) 12930 isFastMultiplier = true; 12931 break; 12932 } 12933 } 12934 12935 if (isFastMultiplier) { 12936 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12937 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12938 DAG.getConstant(CC, MVT::i8), Cond); 12939 // Zero extend the condition if needed. 12940 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12941 Cond); 12942 // Scale the condition by the difference. 12943 if (Diff != 1) 12944 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12945 DAG.getConstant(Diff, Cond.getValueType())); 12946 12947 // Add the base if non-zero. 12948 if (FalseC->getAPIntValue() != 0) 12949 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12950 SDValue(FalseC, 0)); 12951 if (N->getNumValues() == 2) // Dead flag value? 12952 return DCI.CombineTo(N, Cond, SDValue()); 12953 return Cond; 12954 } 12955 } 12956 } 12957 } 12958 return SDValue(); 12959} 12960 12961 12962/// PerformMulCombine - Optimize a single multiply with constant into two 12963/// in order to implement it with two cheaper instructions, e.g. 12964/// LEA + SHL, LEA + LEA. 12965static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 12966 TargetLowering::DAGCombinerInfo &DCI) { 12967 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 12968 return SDValue(); 12969 12970 EVT VT = N->getValueType(0); 12971 if (VT != MVT::i64) 12972 return SDValue(); 12973 12974 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 12975 if (!C) 12976 return SDValue(); 12977 uint64_t MulAmt = C->getZExtValue(); 12978 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 12979 return SDValue(); 12980 12981 uint64_t MulAmt1 = 0; 12982 uint64_t MulAmt2 = 0; 12983 if ((MulAmt % 9) == 0) { 12984 MulAmt1 = 9; 12985 MulAmt2 = MulAmt / 9; 12986 } else if ((MulAmt % 5) == 0) { 12987 MulAmt1 = 5; 12988 MulAmt2 = MulAmt / 5; 12989 } else if ((MulAmt % 3) == 0) { 12990 MulAmt1 = 3; 12991 MulAmt2 = MulAmt / 3; 12992 } 12993 if (MulAmt2 && 12994 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 12995 DebugLoc DL = N->getDebugLoc(); 12996 12997 if (isPowerOf2_64(MulAmt2) && 12998 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 12999 // If second multiplifer is pow2, issue it first. We want the multiply by 13000 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13001 // is an add. 13002 std::swap(MulAmt1, MulAmt2); 13003 13004 SDValue NewMul; 13005 if (isPowerOf2_64(MulAmt1)) 13006 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13007 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13008 else 13009 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13010 DAG.getConstant(MulAmt1, VT)); 13011 13012 if (isPowerOf2_64(MulAmt2)) 13013 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13014 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13015 else 13016 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13017 DAG.getConstant(MulAmt2, VT)); 13018 13019 // Do not add new nodes to DAG combiner worklist. 13020 DCI.CombineTo(N, NewMul, false); 13021 } 13022 return SDValue(); 13023} 13024 13025static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13026 SDValue N0 = N->getOperand(0); 13027 SDValue N1 = N->getOperand(1); 13028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13029 EVT VT = N0.getValueType(); 13030 13031 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13032 // since the result of setcc_c is all zero's or all ones. 13033 if (N1C && N0.getOpcode() == ISD::AND && 13034 N0.getOperand(1).getOpcode() == ISD::Constant) { 13035 SDValue N00 = N0.getOperand(0); 13036 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13037 ((N00.getOpcode() == ISD::ANY_EXTEND || 13038 N00.getOpcode() == ISD::ZERO_EXTEND) && 13039 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13040 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13041 APInt ShAmt = N1C->getAPIntValue(); 13042 Mask = Mask.shl(ShAmt); 13043 if (Mask != 0) 13044 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13045 N00, DAG.getConstant(Mask, VT)); 13046 } 13047 } 13048 13049 return SDValue(); 13050} 13051 13052/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13053/// when possible. 13054static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13055 const X86Subtarget *Subtarget) { 13056 EVT VT = N->getValueType(0); 13057 if (!VT.isVector() && VT.isInteger() && 13058 N->getOpcode() == ISD::SHL) 13059 return PerformSHLCombine(N, DAG); 13060 13061 // On X86 with SSE2 support, we can transform this to a vector shift if 13062 // all elements are shifted by the same amount. We can't do this in legalize 13063 // because the a constant vector is typically transformed to a constant pool 13064 // so we have no knowledge of the shift amount. 13065 if (!Subtarget->hasXMMInt()) 13066 return SDValue(); 13067 13068 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 13069 return SDValue(); 13070 13071 SDValue ShAmtOp = N->getOperand(1); 13072 EVT EltVT = VT.getVectorElementType(); 13073 DebugLoc DL = N->getDebugLoc(); 13074 SDValue BaseShAmt = SDValue(); 13075 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13076 unsigned NumElts = VT.getVectorNumElements(); 13077 unsigned i = 0; 13078 for (; i != NumElts; ++i) { 13079 SDValue Arg = ShAmtOp.getOperand(i); 13080 if (Arg.getOpcode() == ISD::UNDEF) continue; 13081 BaseShAmt = Arg; 13082 break; 13083 } 13084 for (; i != NumElts; ++i) { 13085 SDValue Arg = ShAmtOp.getOperand(i); 13086 if (Arg.getOpcode() == ISD::UNDEF) continue; 13087 if (Arg != BaseShAmt) { 13088 return SDValue(); 13089 } 13090 } 13091 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13092 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13093 SDValue InVec = ShAmtOp.getOperand(0); 13094 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13095 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13096 unsigned i = 0; 13097 for (; i != NumElts; ++i) { 13098 SDValue Arg = InVec.getOperand(i); 13099 if (Arg.getOpcode() == ISD::UNDEF) continue; 13100 BaseShAmt = Arg; 13101 break; 13102 } 13103 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13104 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13105 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13106 if (C->getZExtValue() == SplatIdx) 13107 BaseShAmt = InVec.getOperand(1); 13108 } 13109 } 13110 if (BaseShAmt.getNode() == 0) 13111 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13112 DAG.getIntPtrConstant(0)); 13113 } else 13114 return SDValue(); 13115 13116 // The shift amount is an i32. 13117 if (EltVT.bitsGT(MVT::i32)) 13118 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13119 else if (EltVT.bitsLT(MVT::i32)) 13120 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13121 13122 // The shift amount is identical so we can do a vector shift. 13123 SDValue ValOp = N->getOperand(0); 13124 switch (N->getOpcode()) { 13125 default: 13126 llvm_unreachable("Unknown shift opcode!"); 13127 break; 13128 case ISD::SHL: 13129 if (VT == MVT::v2i64) 13130 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13131 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13132 ValOp, BaseShAmt); 13133 if (VT == MVT::v4i32) 13134 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13135 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13136 ValOp, BaseShAmt); 13137 if (VT == MVT::v8i16) 13138 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13139 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13140 ValOp, BaseShAmt); 13141 break; 13142 case ISD::SRA: 13143 if (VT == MVT::v4i32) 13144 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13145 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13146 ValOp, BaseShAmt); 13147 if (VT == MVT::v8i16) 13148 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13149 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13150 ValOp, BaseShAmt); 13151 break; 13152 case ISD::SRL: 13153 if (VT == MVT::v2i64) 13154 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13155 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13156 ValOp, BaseShAmt); 13157 if (VT == MVT::v4i32) 13158 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13159 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13160 ValOp, BaseShAmt); 13161 if (VT == MVT::v8i16) 13162 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13163 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13164 ValOp, BaseShAmt); 13165 break; 13166 } 13167 return SDValue(); 13168} 13169 13170 13171// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13172// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13173// and friends. Likewise for OR -> CMPNEQSS. 13174static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13175 TargetLowering::DAGCombinerInfo &DCI, 13176 const X86Subtarget *Subtarget) { 13177 unsigned opcode; 13178 13179 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13180 // we're requiring SSE2 for both. 13181 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13182 SDValue N0 = N->getOperand(0); 13183 SDValue N1 = N->getOperand(1); 13184 SDValue CMP0 = N0->getOperand(1); 13185 SDValue CMP1 = N1->getOperand(1); 13186 DebugLoc DL = N->getDebugLoc(); 13187 13188 // The SETCCs should both refer to the same CMP. 13189 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13190 return SDValue(); 13191 13192 SDValue CMP00 = CMP0->getOperand(0); 13193 SDValue CMP01 = CMP0->getOperand(1); 13194 EVT VT = CMP00.getValueType(); 13195 13196 if (VT == MVT::f32 || VT == MVT::f64) { 13197 bool ExpectingFlags = false; 13198 // Check for any users that want flags: 13199 for (SDNode::use_iterator UI = N->use_begin(), 13200 UE = N->use_end(); 13201 !ExpectingFlags && UI != UE; ++UI) 13202 switch (UI->getOpcode()) { 13203 default: 13204 case ISD::BR_CC: 13205 case ISD::BRCOND: 13206 case ISD::SELECT: 13207 ExpectingFlags = true; 13208 break; 13209 case ISD::CopyToReg: 13210 case ISD::SIGN_EXTEND: 13211 case ISD::ZERO_EXTEND: 13212 case ISD::ANY_EXTEND: 13213 break; 13214 } 13215 13216 if (!ExpectingFlags) { 13217 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13218 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13219 13220 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13221 X86::CondCode tmp = cc0; 13222 cc0 = cc1; 13223 cc1 = tmp; 13224 } 13225 13226 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13227 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13228 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13229 X86ISD::NodeType NTOperator = is64BitFP ? 13230 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13231 // FIXME: need symbolic constants for these magic numbers. 13232 // See X86ATTInstPrinter.cpp:printSSECC(). 13233 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13234 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13235 DAG.getConstant(x86cc, MVT::i8)); 13236 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13237 OnesOrZeroesF); 13238 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13239 DAG.getConstant(1, MVT::i32)); 13240 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13241 return OneBitOfTruth; 13242 } 13243 } 13244 } 13245 } 13246 return SDValue(); 13247} 13248 13249/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13250/// so it can be folded inside ANDNP. 13251static bool CanFoldXORWithAllOnes(const SDNode *N) { 13252 EVT VT = N->getValueType(0); 13253 13254 // Match direct AllOnes for 128 and 256-bit vectors 13255 if (ISD::isBuildVectorAllOnes(N)) 13256 return true; 13257 13258 // Look through a bit convert. 13259 if (N->getOpcode() == ISD::BITCAST) 13260 N = N->getOperand(0).getNode(); 13261 13262 // Sometimes the operand may come from a insert_subvector building a 256-bit 13263 // allones vector 13264 if (VT.getSizeInBits() == 256 && 13265 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13266 SDValue V1 = N->getOperand(0); 13267 SDValue V2 = N->getOperand(1); 13268 13269 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13270 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13271 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13272 ISD::isBuildVectorAllOnes(V2.getNode())) 13273 return true; 13274 } 13275 13276 return false; 13277} 13278 13279static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13280 TargetLowering::DAGCombinerInfo &DCI, 13281 const X86Subtarget *Subtarget) { 13282 if (DCI.isBeforeLegalizeOps()) 13283 return SDValue(); 13284 13285 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13286 if (R.getNode()) 13287 return R; 13288 13289 // Want to form ANDNP nodes: 13290 // 1) In the hopes of then easily combining them with OR and AND nodes 13291 // to form PBLEND/PSIGN. 13292 // 2) To match ANDN packed intrinsics 13293 EVT VT = N->getValueType(0); 13294 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13295 return SDValue(); 13296 13297 SDValue N0 = N->getOperand(0); 13298 SDValue N1 = N->getOperand(1); 13299 DebugLoc DL = N->getDebugLoc(); 13300 13301 // Check LHS for vnot 13302 if (N0.getOpcode() == ISD::XOR && 13303 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13304 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13305 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13306 13307 // Check RHS for vnot 13308 if (N1.getOpcode() == ISD::XOR && 13309 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13310 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13311 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13312 13313 return SDValue(); 13314} 13315 13316static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13317 TargetLowering::DAGCombinerInfo &DCI, 13318 const X86Subtarget *Subtarget) { 13319 if (DCI.isBeforeLegalizeOps()) 13320 return SDValue(); 13321 13322 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13323 if (R.getNode()) 13324 return R; 13325 13326 EVT VT = N->getValueType(0); 13327 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 13328 return SDValue(); 13329 13330 SDValue N0 = N->getOperand(0); 13331 SDValue N1 = N->getOperand(1); 13332 13333 // look for psign/blend 13334 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 13335 if (VT == MVT::v2i64) { 13336 // Canonicalize pandn to RHS 13337 if (N0.getOpcode() == X86ISD::ANDNP) 13338 std::swap(N0, N1); 13339 // or (and (m, x), (pandn m, y)) 13340 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13341 SDValue Mask = N1.getOperand(0); 13342 SDValue X = N1.getOperand(1); 13343 SDValue Y; 13344 if (N0.getOperand(0) == Mask) 13345 Y = N0.getOperand(1); 13346 if (N0.getOperand(1) == Mask) 13347 Y = N0.getOperand(0); 13348 13349 // Check to see if the mask appeared in both the AND and ANDNP and 13350 if (!Y.getNode()) 13351 return SDValue(); 13352 13353 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13354 if (Mask.getOpcode() != ISD::BITCAST || 13355 X.getOpcode() != ISD::BITCAST || 13356 Y.getOpcode() != ISD::BITCAST) 13357 return SDValue(); 13358 13359 // Look through mask bitcast. 13360 Mask = Mask.getOperand(0); 13361 EVT MaskVT = Mask.getValueType(); 13362 13363 // Validate that the Mask operand is a vector sra node. The sra node 13364 // will be an intrinsic. 13365 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13366 return SDValue(); 13367 13368 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13369 // there is no psrai.b 13370 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13371 case Intrinsic::x86_sse2_psrai_w: 13372 case Intrinsic::x86_sse2_psrai_d: 13373 break; 13374 default: return SDValue(); 13375 } 13376 13377 // Check that the SRA is all signbits. 13378 SDValue SraC = Mask.getOperand(2); 13379 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13380 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13381 if ((SraAmt + 1) != EltBits) 13382 return SDValue(); 13383 13384 DebugLoc DL = N->getDebugLoc(); 13385 13386 // Now we know we at least have a plendvb with the mask val. See if 13387 // we can form a psignb/w/d. 13388 // psign = x.type == y.type == mask.type && y = sub(0, x); 13389 X = X.getOperand(0); 13390 Y = Y.getOperand(0); 13391 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13392 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13393 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 13394 unsigned Opc = 0; 13395 switch (EltBits) { 13396 case 8: Opc = X86ISD::PSIGNB; break; 13397 case 16: Opc = X86ISD::PSIGNW; break; 13398 case 32: Opc = X86ISD::PSIGND; break; 13399 default: break; 13400 } 13401 if (Opc) { 13402 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 13403 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 13404 } 13405 } 13406 // PBLENDVB only available on SSE 4.1 13407 if (!(Subtarget->hasSSE41() || Subtarget->hasAVX())) 13408 return SDValue(); 13409 13410 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 13411 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 13412 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 13413 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y); 13414 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 13415 } 13416 } 13417 } 13418 13419 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13420 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13421 std::swap(N0, N1); 13422 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13423 return SDValue(); 13424 if (!N0.hasOneUse() || !N1.hasOneUse()) 13425 return SDValue(); 13426 13427 SDValue ShAmt0 = N0.getOperand(1); 13428 if (ShAmt0.getValueType() != MVT::i8) 13429 return SDValue(); 13430 SDValue ShAmt1 = N1.getOperand(1); 13431 if (ShAmt1.getValueType() != MVT::i8) 13432 return SDValue(); 13433 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13434 ShAmt0 = ShAmt0.getOperand(0); 13435 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13436 ShAmt1 = ShAmt1.getOperand(0); 13437 13438 DebugLoc DL = N->getDebugLoc(); 13439 unsigned Opc = X86ISD::SHLD; 13440 SDValue Op0 = N0.getOperand(0); 13441 SDValue Op1 = N1.getOperand(0); 13442 if (ShAmt0.getOpcode() == ISD::SUB) { 13443 Opc = X86ISD::SHRD; 13444 std::swap(Op0, Op1); 13445 std::swap(ShAmt0, ShAmt1); 13446 } 13447 13448 unsigned Bits = VT.getSizeInBits(); 13449 if (ShAmt1.getOpcode() == ISD::SUB) { 13450 SDValue Sum = ShAmt1.getOperand(0); 13451 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13452 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13453 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13454 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13455 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13456 return DAG.getNode(Opc, DL, VT, 13457 Op0, Op1, 13458 DAG.getNode(ISD::TRUNCATE, DL, 13459 MVT::i8, ShAmt0)); 13460 } 13461 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13462 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13463 if (ShAmt0C && 13464 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13465 return DAG.getNode(Opc, DL, VT, 13466 N0.getOperand(0), N1.getOperand(0), 13467 DAG.getNode(ISD::TRUNCATE, DL, 13468 MVT::i8, ShAmt0)); 13469 } 13470 13471 return SDValue(); 13472} 13473 13474/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13475static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13476 const X86Subtarget *Subtarget) { 13477 LoadSDNode *Ld = cast<LoadSDNode>(N); 13478 EVT RegVT = Ld->getValueType(0); 13479 EVT MemVT = Ld->getMemoryVT(); 13480 DebugLoc dl = Ld->getDebugLoc(); 13481 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13482 13483 ISD::LoadExtType Ext = Ld->getExtensionType(); 13484 13485 // If this is a vector EXT Load then attempt to optimize it using a 13486 // shuffle. We need SSE4 for the shuffles. 13487 // TODO: It is possible to support ZExt by zeroing the undef values 13488 // during the shuffle phase or after the shuffle. 13489 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13490 assert(MemVT != RegVT && "Cannot extend to the same type"); 13491 assert(MemVT.isVector() && "Must load a vector from memory"); 13492 13493 unsigned NumElems = RegVT.getVectorNumElements(); 13494 unsigned RegSz = RegVT.getSizeInBits(); 13495 unsigned MemSz = MemVT.getSizeInBits(); 13496 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13497 // All sizes must be a power of two 13498 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13499 13500 // Attempt to load the original value using a single load op. 13501 // Find a scalar type which is equal to the loaded word size. 13502 MVT SclrLoadTy = MVT::i8; 13503 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13504 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13505 MVT Tp = (MVT::SimpleValueType)tp; 13506 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13507 SclrLoadTy = Tp; 13508 break; 13509 } 13510 } 13511 13512 // Proceed if a load word is found. 13513 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13514 13515 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13516 RegSz/SclrLoadTy.getSizeInBits()); 13517 13518 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13519 RegSz/MemVT.getScalarType().getSizeInBits()); 13520 // Can't shuffle using an illegal type. 13521 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13522 13523 // Perform a single load. 13524 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13525 Ld->getBasePtr(), 13526 Ld->getPointerInfo(), Ld->isVolatile(), 13527 Ld->isNonTemporal(), Ld->getAlignment()); 13528 13529 // Insert the word loaded into a vector. 13530 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13531 LoadUnitVecVT, ScalarLoad); 13532 13533 // Bitcast the loaded value to a vector of the original element type, in 13534 // the size of the target vector type. 13535 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); 13536 unsigned SizeRatio = RegSz/MemSz; 13537 13538 // Redistribute the loaded elements into the different locations. 13539 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13540 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 13541 13542 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 13543 DAG.getUNDEF(SlicedVec.getValueType()), 13544 ShuffleVec.data()); 13545 13546 // Bitcast to the requested type. 13547 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 13548 // Replace the original load with the new sequence 13549 // and return the new chain. 13550 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 13551 return SDValue(ScalarLoad.getNode(), 1); 13552 } 13553 13554 return SDValue(); 13555} 13556 13557/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 13558static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 13559 const X86Subtarget *Subtarget) { 13560 StoreSDNode *St = cast<StoreSDNode>(N); 13561 EVT VT = St->getValue().getValueType(); 13562 EVT StVT = St->getMemoryVT(); 13563 DebugLoc dl = St->getDebugLoc(); 13564 SDValue StoredVal = St->getOperand(1); 13565 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13566 13567 // If we are saving a concatination of two XMM registers, perform two stores. 13568 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 13569 // 128-bit ones. If in the future the cost becomes only one memory access the 13570 // first version would be better. 13571 if (VT.getSizeInBits() == 256 && 13572 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 13573 StoredVal.getNumOperands() == 2) { 13574 13575 SDValue Value0 = StoredVal.getOperand(0); 13576 SDValue Value1 = StoredVal.getOperand(1); 13577 13578 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 13579 SDValue Ptr0 = St->getBasePtr(); 13580 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 13581 13582 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 13583 St->getPointerInfo(), St->isVolatile(), 13584 St->isNonTemporal(), St->getAlignment()); 13585 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 13586 St->getPointerInfo(), St->isVolatile(), 13587 St->isNonTemporal(), St->getAlignment()); 13588 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 13589 } 13590 13591 // Optimize trunc store (of multiple scalars) to shuffle and store. 13592 // First, pack all of the elements in one place. Next, store to memory 13593 // in fewer chunks. 13594 if (St->isTruncatingStore() && VT.isVector()) { 13595 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13596 unsigned NumElems = VT.getVectorNumElements(); 13597 assert(StVT != VT && "Cannot truncate to the same type"); 13598 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 13599 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 13600 13601 // From, To sizes and ElemCount must be pow of two 13602 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 13603 // We are going to use the original vector elt for storing. 13604 // Accumulated smaller vector elements must be a multiple of the store size. 13605 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 13606 13607 unsigned SizeRatio = FromSz / ToSz; 13608 13609 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 13610 13611 // Create a type on which we perform the shuffle 13612 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 13613 StVT.getScalarType(), NumElems*SizeRatio); 13614 13615 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 13616 13617 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 13618 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13619 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 13620 13621 // Can't shuffle using an illegal type 13622 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13623 13624 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 13625 DAG.getUNDEF(WideVec.getValueType()), 13626 ShuffleVec.data()); 13627 // At this point all of the data is stored at the bottom of the 13628 // register. We now need to save it to mem. 13629 13630 // Find the largest store unit 13631 MVT StoreType = MVT::i8; 13632 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13633 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13634 MVT Tp = (MVT::SimpleValueType)tp; 13635 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 13636 StoreType = Tp; 13637 } 13638 13639 // Bitcast the original vector into a vector of store-size units 13640 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 13641 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 13642 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 13643 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 13644 SmallVector<SDValue, 8> Chains; 13645 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 13646 TLI.getPointerTy()); 13647 SDValue Ptr = St->getBasePtr(); 13648 13649 // Perform one or more big stores into memory. 13650 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 13651 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 13652 StoreType, ShuffWide, 13653 DAG.getIntPtrConstant(i)); 13654 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 13655 St->getPointerInfo(), St->isVolatile(), 13656 St->isNonTemporal(), St->getAlignment()); 13657 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 13658 Chains.push_back(Ch); 13659 } 13660 13661 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 13662 Chains.size()); 13663 } 13664 13665 13666 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 13667 // the FP state in cases where an emms may be missing. 13668 // A preferable solution to the general problem is to figure out the right 13669 // places to insert EMMS. This qualifies as a quick hack. 13670 13671 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 13672 if (VT.getSizeInBits() != 64) 13673 return SDValue(); 13674 13675 const Function *F = DAG.getMachineFunction().getFunction(); 13676 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 13677 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 13678 && Subtarget->hasXMMInt(); 13679 if ((VT.isVector() || 13680 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 13681 isa<LoadSDNode>(St->getValue()) && 13682 !cast<LoadSDNode>(St->getValue())->isVolatile() && 13683 St->getChain().hasOneUse() && !St->isVolatile()) { 13684 SDNode* LdVal = St->getValue().getNode(); 13685 LoadSDNode *Ld = 0; 13686 int TokenFactorIndex = -1; 13687 SmallVector<SDValue, 8> Ops; 13688 SDNode* ChainVal = St->getChain().getNode(); 13689 // Must be a store of a load. We currently handle two cases: the load 13690 // is a direct child, and it's under an intervening TokenFactor. It is 13691 // possible to dig deeper under nested TokenFactors. 13692 if (ChainVal == LdVal) 13693 Ld = cast<LoadSDNode>(St->getChain()); 13694 else if (St->getValue().hasOneUse() && 13695 ChainVal->getOpcode() == ISD::TokenFactor) { 13696 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 13697 if (ChainVal->getOperand(i).getNode() == LdVal) { 13698 TokenFactorIndex = i; 13699 Ld = cast<LoadSDNode>(St->getValue()); 13700 } else 13701 Ops.push_back(ChainVal->getOperand(i)); 13702 } 13703 } 13704 13705 if (!Ld || !ISD::isNormalLoad(Ld)) 13706 return SDValue(); 13707 13708 // If this is not the MMX case, i.e. we are just turning i64 load/store 13709 // into f64 load/store, avoid the transformation if there are multiple 13710 // uses of the loaded value. 13711 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 13712 return SDValue(); 13713 13714 DebugLoc LdDL = Ld->getDebugLoc(); 13715 DebugLoc StDL = N->getDebugLoc(); 13716 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 13717 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 13718 // pair instead. 13719 if (Subtarget->is64Bit() || F64IsLegal) { 13720 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 13721 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 13722 Ld->getPointerInfo(), Ld->isVolatile(), 13723 Ld->isNonTemporal(), Ld->getAlignment()); 13724 SDValue NewChain = NewLd.getValue(1); 13725 if (TokenFactorIndex != -1) { 13726 Ops.push_back(NewChain); 13727 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13728 Ops.size()); 13729 } 13730 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 13731 St->getPointerInfo(), 13732 St->isVolatile(), St->isNonTemporal(), 13733 St->getAlignment()); 13734 } 13735 13736 // Otherwise, lower to two pairs of 32-bit loads / stores. 13737 SDValue LoAddr = Ld->getBasePtr(); 13738 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 13739 DAG.getConstant(4, MVT::i32)); 13740 13741 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 13742 Ld->getPointerInfo(), 13743 Ld->isVolatile(), Ld->isNonTemporal(), 13744 Ld->getAlignment()); 13745 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 13746 Ld->getPointerInfo().getWithOffset(4), 13747 Ld->isVolatile(), Ld->isNonTemporal(), 13748 MinAlign(Ld->getAlignment(), 4)); 13749 13750 SDValue NewChain = LoLd.getValue(1); 13751 if (TokenFactorIndex != -1) { 13752 Ops.push_back(LoLd); 13753 Ops.push_back(HiLd); 13754 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13755 Ops.size()); 13756 } 13757 13758 LoAddr = St->getBasePtr(); 13759 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 13760 DAG.getConstant(4, MVT::i32)); 13761 13762 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 13763 St->getPointerInfo(), 13764 St->isVolatile(), St->isNonTemporal(), 13765 St->getAlignment()); 13766 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 13767 St->getPointerInfo().getWithOffset(4), 13768 St->isVolatile(), 13769 St->isNonTemporal(), 13770 MinAlign(St->getAlignment(), 4)); 13771 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 13772 } 13773 return SDValue(); 13774} 13775 13776/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 13777/// and return the operands for the horizontal operation in LHS and RHS. A 13778/// horizontal operation performs the binary operation on successive elements 13779/// of its first operand, then on successive elements of its second operand, 13780/// returning the resulting values in a vector. For example, if 13781/// A = < float a0, float a1, float a2, float a3 > 13782/// and 13783/// B = < float b0, float b1, float b2, float b3 > 13784/// then the result of doing a horizontal operation on A and B is 13785/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 13786/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 13787/// A horizontal-op B, for some already available A and B, and if so then LHS is 13788/// set to A, RHS to B, and the routine returns 'true'. 13789/// Note that the binary operation should have the property that if one of the 13790/// operands is UNDEF then the result is UNDEF. 13791static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) { 13792 // Look for the following pattern: if 13793 // A = < float a0, float a1, float a2, float a3 > 13794 // B = < float b0, float b1, float b2, float b3 > 13795 // and 13796 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 13797 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 13798 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 13799 // which is A horizontal-op B. 13800 13801 // At least one of the operands should be a vector shuffle. 13802 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 13803 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 13804 return false; 13805 13806 EVT VT = LHS.getValueType(); 13807 unsigned N = VT.getVectorNumElements(); 13808 13809 // View LHS in the form 13810 // LHS = VECTOR_SHUFFLE A, B, LMask 13811 // If LHS is not a shuffle then pretend it is the shuffle 13812 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 13813 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 13814 // type VT. 13815 SDValue A, B; 13816 SmallVector<int, 8> LMask(N); 13817 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 13818 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 13819 A = LHS.getOperand(0); 13820 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 13821 B = LHS.getOperand(1); 13822 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 13823 } else { 13824 if (LHS.getOpcode() != ISD::UNDEF) 13825 A = LHS; 13826 for (unsigned i = 0; i != N; ++i) 13827 LMask[i] = i; 13828 } 13829 13830 // Likewise, view RHS in the form 13831 // RHS = VECTOR_SHUFFLE C, D, RMask 13832 SDValue C, D; 13833 SmallVector<int, 8> RMask(N); 13834 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 13835 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 13836 C = RHS.getOperand(0); 13837 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 13838 D = RHS.getOperand(1); 13839 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 13840 } else { 13841 if (RHS.getOpcode() != ISD::UNDEF) 13842 C = RHS; 13843 for (unsigned i = 0; i != N; ++i) 13844 RMask[i] = i; 13845 } 13846 13847 // Check that the shuffles are both shuffling the same vectors. 13848 if (!(A == C && B == D) && !(A == D && B == C)) 13849 return false; 13850 13851 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 13852 if (!A.getNode() && !B.getNode()) 13853 return false; 13854 13855 // If A and B occur in reverse order in RHS, then "swap" them (which means 13856 // rewriting the mask). 13857 if (A != C) 13858 for (unsigned i = 0; i != N; ++i) { 13859 unsigned Idx = RMask[i]; 13860 if (Idx < N) 13861 RMask[i] += N; 13862 else if (Idx < 2*N) 13863 RMask[i] -= N; 13864 } 13865 13866 // At this point LHS and RHS are equivalent to 13867 // LHS = VECTOR_SHUFFLE A, B, LMask 13868 // RHS = VECTOR_SHUFFLE A, B, RMask 13869 // Check that the masks correspond to performing a horizontal operation. 13870 for (unsigned i = 0; i != N; ++i) { 13871 unsigned LIdx = LMask[i], RIdx = RMask[i]; 13872 13873 // Ignore any UNDEF components. 13874 if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N)) 13875 || (!B.getNode() && (LIdx >= N || RIdx >= N))) 13876 continue; 13877 13878 // Check that successive elements are being operated on. If not, this is 13879 // not a horizontal operation. 13880 if (!(LIdx == 2*i && RIdx == 2*i + 1) && 13881 !(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i)) 13882 return false; 13883 } 13884 13885 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 13886 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 13887 return true; 13888} 13889 13890/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 13891static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 13892 const X86Subtarget *Subtarget) { 13893 EVT VT = N->getValueType(0); 13894 SDValue LHS = N->getOperand(0); 13895 SDValue RHS = N->getOperand(1); 13896 13897 // Try to synthesize horizontal adds from adds of shuffles. 13898 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 13899 (VT == MVT::v4f32 || VT == MVT::v2f64) && 13900 isHorizontalBinOp(LHS, RHS, true)) 13901 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 13902 return SDValue(); 13903} 13904 13905/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 13906static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 13907 const X86Subtarget *Subtarget) { 13908 EVT VT = N->getValueType(0); 13909 SDValue LHS = N->getOperand(0); 13910 SDValue RHS = N->getOperand(1); 13911 13912 // Try to synthesize horizontal subs from subs of shuffles. 13913 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 13914 (VT == MVT::v4f32 || VT == MVT::v2f64) && 13915 isHorizontalBinOp(LHS, RHS, false)) 13916 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 13917 return SDValue(); 13918} 13919 13920/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 13921/// X86ISD::FXOR nodes. 13922static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 13923 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 13924 // F[X]OR(0.0, x) -> x 13925 // F[X]OR(x, 0.0) -> x 13926 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13927 if (C->getValueAPF().isPosZero()) 13928 return N->getOperand(1); 13929 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13930 if (C->getValueAPF().isPosZero()) 13931 return N->getOperand(0); 13932 return SDValue(); 13933} 13934 13935/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 13936static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 13937 // FAND(0.0, x) -> 0.0 13938 // FAND(x, 0.0) -> 0.0 13939 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13940 if (C->getValueAPF().isPosZero()) 13941 return N->getOperand(0); 13942 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13943 if (C->getValueAPF().isPosZero()) 13944 return N->getOperand(1); 13945 return SDValue(); 13946} 13947 13948static SDValue PerformBTCombine(SDNode *N, 13949 SelectionDAG &DAG, 13950 TargetLowering::DAGCombinerInfo &DCI) { 13951 // BT ignores high bits in the bit index operand. 13952 SDValue Op1 = N->getOperand(1); 13953 if (Op1.hasOneUse()) { 13954 unsigned BitWidth = Op1.getValueSizeInBits(); 13955 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 13956 APInt KnownZero, KnownOne; 13957 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 13958 !DCI.isBeforeLegalizeOps()); 13959 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13960 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 13961 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 13962 DCI.CommitTargetLoweringOpt(TLO); 13963 } 13964 return SDValue(); 13965} 13966 13967static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 13968 SDValue Op = N->getOperand(0); 13969 if (Op.getOpcode() == ISD::BITCAST) 13970 Op = Op.getOperand(0); 13971 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 13972 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 13973 VT.getVectorElementType().getSizeInBits() == 13974 OpVT.getVectorElementType().getSizeInBits()) { 13975 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 13976 } 13977 return SDValue(); 13978} 13979 13980static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 13981 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 13982 // (and (i32 x86isd::setcc_carry), 1) 13983 // This eliminates the zext. This transformation is necessary because 13984 // ISD::SETCC is always legalized to i8. 13985 DebugLoc dl = N->getDebugLoc(); 13986 SDValue N0 = N->getOperand(0); 13987 EVT VT = N->getValueType(0); 13988 if (N0.getOpcode() == ISD::AND && 13989 N0.hasOneUse() && 13990 N0.getOperand(0).hasOneUse()) { 13991 SDValue N00 = N0.getOperand(0); 13992 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 13993 return SDValue(); 13994 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 13995 if (!C || C->getZExtValue() != 1) 13996 return SDValue(); 13997 return DAG.getNode(ISD::AND, dl, VT, 13998 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 13999 N00.getOperand(0), N00.getOperand(1)), 14000 DAG.getConstant(1, VT)); 14001 } 14002 14003 return SDValue(); 14004} 14005 14006// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14007static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14008 unsigned X86CC = N->getConstantOperandVal(0); 14009 SDValue EFLAG = N->getOperand(1); 14010 DebugLoc DL = N->getDebugLoc(); 14011 14012 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14013 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14014 // cases. 14015 if (X86CC == X86::COND_B) 14016 return DAG.getNode(ISD::AND, DL, MVT::i8, 14017 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14018 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14019 DAG.getConstant(1, MVT::i8)); 14020 14021 return SDValue(); 14022} 14023 14024static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14025 const X86TargetLowering *XTLI) { 14026 SDValue Op0 = N->getOperand(0); 14027 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14028 // a 32-bit target where SSE doesn't support i64->FP operations. 14029 if (Op0.getOpcode() == ISD::LOAD) { 14030 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14031 EVT VT = Ld->getValueType(0); 14032 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14033 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14034 !XTLI->getSubtarget()->is64Bit() && 14035 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14036 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14037 Ld->getChain(), Op0, DAG); 14038 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14039 return FILDChain; 14040 } 14041 } 14042 return SDValue(); 14043} 14044 14045// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14046static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14047 X86TargetLowering::DAGCombinerInfo &DCI) { 14048 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14049 // the result is either zero or one (depending on the input carry bit). 14050 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14051 if (X86::isZeroNode(N->getOperand(0)) && 14052 X86::isZeroNode(N->getOperand(1)) && 14053 // We don't have a good way to replace an EFLAGS use, so only do this when 14054 // dead right now. 14055 SDValue(N, 1).use_empty()) { 14056 DebugLoc DL = N->getDebugLoc(); 14057 EVT VT = N->getValueType(0); 14058 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14059 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14060 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14061 DAG.getConstant(X86::COND_B,MVT::i8), 14062 N->getOperand(2)), 14063 DAG.getConstant(1, VT)); 14064 return DCI.CombineTo(N, Res1, CarryOut); 14065 } 14066 14067 return SDValue(); 14068} 14069 14070// fold (add Y, (sete X, 0)) -> adc 0, Y 14071// (add Y, (setne X, 0)) -> sbb -1, Y 14072// (sub (sete X, 0), Y) -> sbb 0, Y 14073// (sub (setne X, 0), Y) -> adc -1, Y 14074static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14075 DebugLoc DL = N->getDebugLoc(); 14076 14077 // Look through ZExts. 14078 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14079 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14080 return SDValue(); 14081 14082 SDValue SetCC = Ext.getOperand(0); 14083 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14084 return SDValue(); 14085 14086 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14087 if (CC != X86::COND_E && CC != X86::COND_NE) 14088 return SDValue(); 14089 14090 SDValue Cmp = SetCC.getOperand(1); 14091 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14092 !X86::isZeroNode(Cmp.getOperand(1)) || 14093 !Cmp.getOperand(0).getValueType().isInteger()) 14094 return SDValue(); 14095 14096 SDValue CmpOp0 = Cmp.getOperand(0); 14097 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14098 DAG.getConstant(1, CmpOp0.getValueType())); 14099 14100 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14101 if (CC == X86::COND_NE) 14102 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14103 DL, OtherVal.getValueType(), OtherVal, 14104 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14105 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14106 DL, OtherVal.getValueType(), OtherVal, 14107 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14108} 14109 14110static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 14111 SDValue Op0 = N->getOperand(0); 14112 SDValue Op1 = N->getOperand(1); 14113 14114 // X86 can't encode an immediate LHS of a sub. See if we can push the 14115 // negation into a preceding instruction. 14116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14117 // If the RHS of the sub is a XOR with one use and a constant, invert the 14118 // immediate. Then add one to the LHS of the sub so we can turn 14119 // X-Y -> X+~Y+1, saving one register. 14120 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14121 isa<ConstantSDNode>(Op1.getOperand(1))) { 14122 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14123 EVT VT = Op0.getValueType(); 14124 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14125 Op1.getOperand(0), 14126 DAG.getConstant(~XorC, VT)); 14127 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14128 DAG.getConstant(C->getAPIntValue()+1, VT)); 14129 } 14130 } 14131 14132 return OptimizeConditionalInDecrement(N, DAG); 14133} 14134 14135SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14136 DAGCombinerInfo &DCI) const { 14137 SelectionDAG &DAG = DCI.DAG; 14138 switch (N->getOpcode()) { 14139 default: break; 14140 case ISD::EXTRACT_VECTOR_ELT: 14141 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14142 case ISD::VSELECT: 14143 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14144 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14145 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 14146 case ISD::SUB: return PerformSubCombine(N, DAG); 14147 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14148 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14149 case ISD::SHL: 14150 case ISD::SRA: 14151 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14152 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14153 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14154 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14155 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14156 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14157 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14158 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14159 case X86ISD::FXOR: 14160 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14161 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14162 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14163 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14164 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14165 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14166 case X86ISD::SHUFPS: // Handle all target specific shuffles 14167 case X86ISD::SHUFPD: 14168 case X86ISD::PALIGN: 14169 case X86ISD::PUNPCKHBW: 14170 case X86ISD::PUNPCKHWD: 14171 case X86ISD::PUNPCKHDQ: 14172 case X86ISD::PUNPCKHQDQ: 14173 case X86ISD::UNPCKHPS: 14174 case X86ISD::UNPCKHPD: 14175 case X86ISD::VUNPCKHPSY: 14176 case X86ISD::VUNPCKHPDY: 14177 case X86ISD::PUNPCKLBW: 14178 case X86ISD::PUNPCKLWD: 14179 case X86ISD::PUNPCKLDQ: 14180 case X86ISD::PUNPCKLQDQ: 14181 case X86ISD::UNPCKLPS: 14182 case X86ISD::UNPCKLPD: 14183 case X86ISD::VUNPCKLPSY: 14184 case X86ISD::VUNPCKLPDY: 14185 case X86ISD::MOVHLPS: 14186 case X86ISD::MOVLHPS: 14187 case X86ISD::PSHUFD: 14188 case X86ISD::PSHUFHW: 14189 case X86ISD::PSHUFLW: 14190 case X86ISD::MOVSS: 14191 case X86ISD::MOVSD: 14192 case X86ISD::VPERMILPS: 14193 case X86ISD::VPERMILPSY: 14194 case X86ISD::VPERMILPD: 14195 case X86ISD::VPERMILPDY: 14196 case X86ISD::VPERM2F128: 14197 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14198 } 14199 14200 return SDValue(); 14201} 14202 14203/// isTypeDesirableForOp - Return true if the target has native support for 14204/// the specified value type and it is 'desirable' to use the type for the 14205/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14206/// instruction encodings are longer and some i16 instructions are slow. 14207bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14208 if (!isTypeLegal(VT)) 14209 return false; 14210 if (VT != MVT::i16) 14211 return true; 14212 14213 switch (Opc) { 14214 default: 14215 return true; 14216 case ISD::LOAD: 14217 case ISD::SIGN_EXTEND: 14218 case ISD::ZERO_EXTEND: 14219 case ISD::ANY_EXTEND: 14220 case ISD::SHL: 14221 case ISD::SRL: 14222 case ISD::SUB: 14223 case ISD::ADD: 14224 case ISD::MUL: 14225 case ISD::AND: 14226 case ISD::OR: 14227 case ISD::XOR: 14228 return false; 14229 } 14230} 14231 14232/// IsDesirableToPromoteOp - This method query the target whether it is 14233/// beneficial for dag combiner to promote the specified node. If true, it 14234/// should return the desired promotion type by reference. 14235bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14236 EVT VT = Op.getValueType(); 14237 if (VT != MVT::i16) 14238 return false; 14239 14240 bool Promote = false; 14241 bool Commute = false; 14242 switch (Op.getOpcode()) { 14243 default: break; 14244 case ISD::LOAD: { 14245 LoadSDNode *LD = cast<LoadSDNode>(Op); 14246 // If the non-extending load has a single use and it's not live out, then it 14247 // might be folded. 14248 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14249 Op.hasOneUse()*/) { 14250 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14251 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14252 // The only case where we'd want to promote LOAD (rather then it being 14253 // promoted as an operand is when it's only use is liveout. 14254 if (UI->getOpcode() != ISD::CopyToReg) 14255 return false; 14256 } 14257 } 14258 Promote = true; 14259 break; 14260 } 14261 case ISD::SIGN_EXTEND: 14262 case ISD::ZERO_EXTEND: 14263 case ISD::ANY_EXTEND: 14264 Promote = true; 14265 break; 14266 case ISD::SHL: 14267 case ISD::SRL: { 14268 SDValue N0 = Op.getOperand(0); 14269 // Look out for (store (shl (load), x)). 14270 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14271 return false; 14272 Promote = true; 14273 break; 14274 } 14275 case ISD::ADD: 14276 case ISD::MUL: 14277 case ISD::AND: 14278 case ISD::OR: 14279 case ISD::XOR: 14280 Commute = true; 14281 // fallthrough 14282 case ISD::SUB: { 14283 SDValue N0 = Op.getOperand(0); 14284 SDValue N1 = Op.getOperand(1); 14285 if (!Commute && MayFoldLoad(N1)) 14286 return false; 14287 // Avoid disabling potential load folding opportunities. 14288 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14289 return false; 14290 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14291 return false; 14292 Promote = true; 14293 } 14294 } 14295 14296 PVT = MVT::i32; 14297 return Promote; 14298} 14299 14300//===----------------------------------------------------------------------===// 14301// X86 Inline Assembly Support 14302//===----------------------------------------------------------------------===// 14303 14304bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14305 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14306 14307 std::string AsmStr = IA->getAsmString(); 14308 14309 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14310 SmallVector<StringRef, 4> AsmPieces; 14311 SplitString(AsmStr, AsmPieces, ";\n"); 14312 14313 switch (AsmPieces.size()) { 14314 default: return false; 14315 case 1: 14316 AsmStr = AsmPieces[0]; 14317 AsmPieces.clear(); 14318 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 14319 14320 // FIXME: this should verify that we are targeting a 486 or better. If not, 14321 // we will turn this bswap into something that will be lowered to logical ops 14322 // instead of emitting the bswap asm. For now, we don't support 486 or lower 14323 // so don't worry about this. 14324 // bswap $0 14325 if (AsmPieces.size() == 2 && 14326 (AsmPieces[0] == "bswap" || 14327 AsmPieces[0] == "bswapq" || 14328 AsmPieces[0] == "bswapl") && 14329 (AsmPieces[1] == "$0" || 14330 AsmPieces[1] == "${0:q}")) { 14331 // No need to check constraints, nothing other than the equivalent of 14332 // "=r,0" would be valid here. 14333 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14334 if (!Ty || Ty->getBitWidth() % 16 != 0) 14335 return false; 14336 return IntrinsicLowering::LowerToByteSwap(CI); 14337 } 14338 // rorw $$8, ${0:w} --> llvm.bswap.i16 14339 if (CI->getType()->isIntegerTy(16) && 14340 AsmPieces.size() == 3 && 14341 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 14342 AsmPieces[1] == "$$8," && 14343 AsmPieces[2] == "${0:w}" && 14344 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14345 AsmPieces.clear(); 14346 const std::string &ConstraintsStr = IA->getConstraintString(); 14347 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14348 std::sort(AsmPieces.begin(), AsmPieces.end()); 14349 if (AsmPieces.size() == 4 && 14350 AsmPieces[0] == "~{cc}" && 14351 AsmPieces[1] == "~{dirflag}" && 14352 AsmPieces[2] == "~{flags}" && 14353 AsmPieces[3] == "~{fpsr}") { 14354 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14355 if (!Ty || Ty->getBitWidth() % 16 != 0) 14356 return false; 14357 return IntrinsicLowering::LowerToByteSwap(CI); 14358 } 14359 } 14360 break; 14361 case 3: 14362 if (CI->getType()->isIntegerTy(32) && 14363 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14364 SmallVector<StringRef, 4> Words; 14365 SplitString(AsmPieces[0], Words, " \t,"); 14366 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14367 Words[2] == "${0:w}") { 14368 Words.clear(); 14369 SplitString(AsmPieces[1], Words, " \t,"); 14370 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 14371 Words[2] == "$0") { 14372 Words.clear(); 14373 SplitString(AsmPieces[2], Words, " \t,"); 14374 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14375 Words[2] == "${0:w}") { 14376 AsmPieces.clear(); 14377 const std::string &ConstraintsStr = IA->getConstraintString(); 14378 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14379 std::sort(AsmPieces.begin(), AsmPieces.end()); 14380 if (AsmPieces.size() == 4 && 14381 AsmPieces[0] == "~{cc}" && 14382 AsmPieces[1] == "~{dirflag}" && 14383 AsmPieces[2] == "~{flags}" && 14384 AsmPieces[3] == "~{fpsr}") { 14385 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14386 if (!Ty || Ty->getBitWidth() % 16 != 0) 14387 return false; 14388 return IntrinsicLowering::LowerToByteSwap(CI); 14389 } 14390 } 14391 } 14392 } 14393 } 14394 14395 if (CI->getType()->isIntegerTy(64)) { 14396 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14397 if (Constraints.size() >= 2 && 14398 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14399 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14400 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14401 SmallVector<StringRef, 4> Words; 14402 SplitString(AsmPieces[0], Words, " \t"); 14403 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 14404 Words.clear(); 14405 SplitString(AsmPieces[1], Words, " \t"); 14406 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 14407 Words.clear(); 14408 SplitString(AsmPieces[2], Words, " \t,"); 14409 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 14410 Words[2] == "%edx") { 14411 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14412 if (!Ty || Ty->getBitWidth() % 16 != 0) 14413 return false; 14414 return IntrinsicLowering::LowerToByteSwap(CI); 14415 } 14416 } 14417 } 14418 } 14419 } 14420 break; 14421 } 14422 return false; 14423} 14424 14425 14426 14427/// getConstraintType - Given a constraint letter, return the type of 14428/// constraint it is for this target. 14429X86TargetLowering::ConstraintType 14430X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14431 if (Constraint.size() == 1) { 14432 switch (Constraint[0]) { 14433 case 'R': 14434 case 'q': 14435 case 'Q': 14436 case 'f': 14437 case 't': 14438 case 'u': 14439 case 'y': 14440 case 'x': 14441 case 'Y': 14442 case 'l': 14443 return C_RegisterClass; 14444 case 'a': 14445 case 'b': 14446 case 'c': 14447 case 'd': 14448 case 'S': 14449 case 'D': 14450 case 'A': 14451 return C_Register; 14452 case 'I': 14453 case 'J': 14454 case 'K': 14455 case 'L': 14456 case 'M': 14457 case 'N': 14458 case 'G': 14459 case 'C': 14460 case 'e': 14461 case 'Z': 14462 return C_Other; 14463 default: 14464 break; 14465 } 14466 } 14467 return TargetLowering::getConstraintType(Constraint); 14468} 14469 14470/// Examine constraint type and operand type and determine a weight value. 14471/// This object must already have been set up with the operand type 14472/// and the current alternative constraint selected. 14473TargetLowering::ConstraintWeight 14474 X86TargetLowering::getSingleConstraintMatchWeight( 14475 AsmOperandInfo &info, const char *constraint) const { 14476 ConstraintWeight weight = CW_Invalid; 14477 Value *CallOperandVal = info.CallOperandVal; 14478 // If we don't have a value, we can't do a match, 14479 // but allow it at the lowest weight. 14480 if (CallOperandVal == NULL) 14481 return CW_Default; 14482 Type *type = CallOperandVal->getType(); 14483 // Look at the constraint type. 14484 switch (*constraint) { 14485 default: 14486 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14487 case 'R': 14488 case 'q': 14489 case 'Q': 14490 case 'a': 14491 case 'b': 14492 case 'c': 14493 case 'd': 14494 case 'S': 14495 case 'D': 14496 case 'A': 14497 if (CallOperandVal->getType()->isIntegerTy()) 14498 weight = CW_SpecificReg; 14499 break; 14500 case 'f': 14501 case 't': 14502 case 'u': 14503 if (type->isFloatingPointTy()) 14504 weight = CW_SpecificReg; 14505 break; 14506 case 'y': 14507 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14508 weight = CW_SpecificReg; 14509 break; 14510 case 'x': 14511 case 'Y': 14512 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 14513 weight = CW_Register; 14514 break; 14515 case 'I': 14516 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14517 if (C->getZExtValue() <= 31) 14518 weight = CW_Constant; 14519 } 14520 break; 14521 case 'J': 14522 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14523 if (C->getZExtValue() <= 63) 14524 weight = CW_Constant; 14525 } 14526 break; 14527 case 'K': 14528 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14529 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 14530 weight = CW_Constant; 14531 } 14532 break; 14533 case 'L': 14534 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14535 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 14536 weight = CW_Constant; 14537 } 14538 break; 14539 case 'M': 14540 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14541 if (C->getZExtValue() <= 3) 14542 weight = CW_Constant; 14543 } 14544 break; 14545 case 'N': 14546 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14547 if (C->getZExtValue() <= 0xff) 14548 weight = CW_Constant; 14549 } 14550 break; 14551 case 'G': 14552 case 'C': 14553 if (dyn_cast<ConstantFP>(CallOperandVal)) { 14554 weight = CW_Constant; 14555 } 14556 break; 14557 case 'e': 14558 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14559 if ((C->getSExtValue() >= -0x80000000LL) && 14560 (C->getSExtValue() <= 0x7fffffffLL)) 14561 weight = CW_Constant; 14562 } 14563 break; 14564 case 'Z': 14565 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14566 if (C->getZExtValue() <= 0xffffffff) 14567 weight = CW_Constant; 14568 } 14569 break; 14570 } 14571 return weight; 14572} 14573 14574/// LowerXConstraint - try to replace an X constraint, which matches anything, 14575/// with another that has more specific requirements based on the type of the 14576/// corresponding operand. 14577const char *X86TargetLowering:: 14578LowerXConstraint(EVT ConstraintVT) const { 14579 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 14580 // 'f' like normal targets. 14581 if (ConstraintVT.isFloatingPoint()) { 14582 if (Subtarget->hasXMMInt()) 14583 return "Y"; 14584 if (Subtarget->hasXMM()) 14585 return "x"; 14586 } 14587 14588 return TargetLowering::LowerXConstraint(ConstraintVT); 14589} 14590 14591/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 14592/// vector. If it is invalid, don't add anything to Ops. 14593void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 14594 std::string &Constraint, 14595 std::vector<SDValue>&Ops, 14596 SelectionDAG &DAG) const { 14597 SDValue Result(0, 0); 14598 14599 // Only support length 1 constraints for now. 14600 if (Constraint.length() > 1) return; 14601 14602 char ConstraintLetter = Constraint[0]; 14603 switch (ConstraintLetter) { 14604 default: break; 14605 case 'I': 14606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14607 if (C->getZExtValue() <= 31) { 14608 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14609 break; 14610 } 14611 } 14612 return; 14613 case 'J': 14614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14615 if (C->getZExtValue() <= 63) { 14616 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14617 break; 14618 } 14619 } 14620 return; 14621 case 'K': 14622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14623 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 14624 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14625 break; 14626 } 14627 } 14628 return; 14629 case 'N': 14630 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14631 if (C->getZExtValue() <= 255) { 14632 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14633 break; 14634 } 14635 } 14636 return; 14637 case 'e': { 14638 // 32-bit signed value 14639 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14640 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14641 C->getSExtValue())) { 14642 // Widen to 64 bits here to get it sign extended. 14643 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 14644 break; 14645 } 14646 // FIXME gcc accepts some relocatable values here too, but only in certain 14647 // memory models; it's complicated. 14648 } 14649 return; 14650 } 14651 case 'Z': { 14652 // 32-bit unsigned value 14653 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14654 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14655 C->getZExtValue())) { 14656 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14657 break; 14658 } 14659 } 14660 // FIXME gcc accepts some relocatable values here too, but only in certain 14661 // memory models; it's complicated. 14662 return; 14663 } 14664 case 'i': { 14665 // Literal immediates are always ok. 14666 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 14667 // Widen to 64 bits here to get it sign extended. 14668 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 14669 break; 14670 } 14671 14672 // In any sort of PIC mode addresses need to be computed at runtime by 14673 // adding in a register or some sort of table lookup. These can't 14674 // be used as immediates. 14675 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 14676 return; 14677 14678 // If we are in non-pic codegen mode, we allow the address of a global (with 14679 // an optional displacement) to be used with 'i'. 14680 GlobalAddressSDNode *GA = 0; 14681 int64_t Offset = 0; 14682 14683 // Match either (GA), (GA+C), (GA+C1+C2), etc. 14684 while (1) { 14685 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 14686 Offset += GA->getOffset(); 14687 break; 14688 } else if (Op.getOpcode() == ISD::ADD) { 14689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14690 Offset += C->getZExtValue(); 14691 Op = Op.getOperand(0); 14692 continue; 14693 } 14694 } else if (Op.getOpcode() == ISD::SUB) { 14695 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14696 Offset += -C->getZExtValue(); 14697 Op = Op.getOperand(0); 14698 continue; 14699 } 14700 } 14701 14702 // Otherwise, this isn't something we can handle, reject it. 14703 return; 14704 } 14705 14706 const GlobalValue *GV = GA->getGlobal(); 14707 // If we require an extra load to get this address, as in PIC mode, we 14708 // can't accept it. 14709 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 14710 getTargetMachine()))) 14711 return; 14712 14713 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 14714 GA->getValueType(0), Offset); 14715 break; 14716 } 14717 } 14718 14719 if (Result.getNode()) { 14720 Ops.push_back(Result); 14721 return; 14722 } 14723 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 14724} 14725 14726std::pair<unsigned, const TargetRegisterClass*> 14727X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 14728 EVT VT) const { 14729 // First, see if this is a constraint that directly corresponds to an LLVM 14730 // register class. 14731 if (Constraint.size() == 1) { 14732 // GCC Constraint Letters 14733 switch (Constraint[0]) { 14734 default: break; 14735 // TODO: Slight differences here in allocation order and leaving 14736 // RIP in the class. Do they matter any more here than they do 14737 // in the normal allocation? 14738 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 14739 if (Subtarget->is64Bit()) { 14740 if (VT == MVT::i32 || VT == MVT::f32) 14741 return std::make_pair(0U, X86::GR32RegisterClass); 14742 else if (VT == MVT::i16) 14743 return std::make_pair(0U, X86::GR16RegisterClass); 14744 else if (VT == MVT::i8 || VT == MVT::i1) 14745 return std::make_pair(0U, X86::GR8RegisterClass); 14746 else if (VT == MVT::i64 || VT == MVT::f64) 14747 return std::make_pair(0U, X86::GR64RegisterClass); 14748 break; 14749 } 14750 // 32-bit fallthrough 14751 case 'Q': // Q_REGS 14752 if (VT == MVT::i32 || VT == MVT::f32) 14753 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 14754 else if (VT == MVT::i16) 14755 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 14756 else if (VT == MVT::i8 || VT == MVT::i1) 14757 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 14758 else if (VT == MVT::i64) 14759 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 14760 break; 14761 case 'r': // GENERAL_REGS 14762 case 'l': // INDEX_REGS 14763 if (VT == MVT::i8 || VT == MVT::i1) 14764 return std::make_pair(0U, X86::GR8RegisterClass); 14765 if (VT == MVT::i16) 14766 return std::make_pair(0U, X86::GR16RegisterClass); 14767 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 14768 return std::make_pair(0U, X86::GR32RegisterClass); 14769 return std::make_pair(0U, X86::GR64RegisterClass); 14770 case 'R': // LEGACY_REGS 14771 if (VT == MVT::i8 || VT == MVT::i1) 14772 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 14773 if (VT == MVT::i16) 14774 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 14775 if (VT == MVT::i32 || !Subtarget->is64Bit()) 14776 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 14777 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 14778 case 'f': // FP Stack registers. 14779 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 14780 // value to the correct fpstack register class. 14781 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 14782 return std::make_pair(0U, X86::RFP32RegisterClass); 14783 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 14784 return std::make_pair(0U, X86::RFP64RegisterClass); 14785 return std::make_pair(0U, X86::RFP80RegisterClass); 14786 case 'y': // MMX_REGS if MMX allowed. 14787 if (!Subtarget->hasMMX()) break; 14788 return std::make_pair(0U, X86::VR64RegisterClass); 14789 case 'Y': // SSE_REGS if SSE2 allowed 14790 if (!Subtarget->hasXMMInt()) break; 14791 // FALL THROUGH. 14792 case 'x': // SSE_REGS if SSE1 allowed 14793 if (!Subtarget->hasXMM()) break; 14794 14795 switch (VT.getSimpleVT().SimpleTy) { 14796 default: break; 14797 // Scalar SSE types. 14798 case MVT::f32: 14799 case MVT::i32: 14800 return std::make_pair(0U, X86::FR32RegisterClass); 14801 case MVT::f64: 14802 case MVT::i64: 14803 return std::make_pair(0U, X86::FR64RegisterClass); 14804 // Vector types. 14805 case MVT::v16i8: 14806 case MVT::v8i16: 14807 case MVT::v4i32: 14808 case MVT::v2i64: 14809 case MVT::v4f32: 14810 case MVT::v2f64: 14811 return std::make_pair(0U, X86::VR128RegisterClass); 14812 } 14813 break; 14814 } 14815 } 14816 14817 // Use the default implementation in TargetLowering to convert the register 14818 // constraint into a member of a register class. 14819 std::pair<unsigned, const TargetRegisterClass*> Res; 14820 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 14821 14822 // Not found as a standard register? 14823 if (Res.second == 0) { 14824 // Map st(0) -> st(7) -> ST0 14825 if (Constraint.size() == 7 && Constraint[0] == '{' && 14826 tolower(Constraint[1]) == 's' && 14827 tolower(Constraint[2]) == 't' && 14828 Constraint[3] == '(' && 14829 (Constraint[4] >= '0' && Constraint[4] <= '7') && 14830 Constraint[5] == ')' && 14831 Constraint[6] == '}') { 14832 14833 Res.first = X86::ST0+Constraint[4]-'0'; 14834 Res.second = X86::RFP80RegisterClass; 14835 return Res; 14836 } 14837 14838 // GCC allows "st(0)" to be called just plain "st". 14839 if (StringRef("{st}").equals_lower(Constraint)) { 14840 Res.first = X86::ST0; 14841 Res.second = X86::RFP80RegisterClass; 14842 return Res; 14843 } 14844 14845 // flags -> EFLAGS 14846 if (StringRef("{flags}").equals_lower(Constraint)) { 14847 Res.first = X86::EFLAGS; 14848 Res.second = X86::CCRRegisterClass; 14849 return Res; 14850 } 14851 14852 // 'A' means EAX + EDX. 14853 if (Constraint == "A") { 14854 Res.first = X86::EAX; 14855 Res.second = X86::GR32_ADRegisterClass; 14856 return Res; 14857 } 14858 return Res; 14859 } 14860 14861 // Otherwise, check to see if this is a register class of the wrong value 14862 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 14863 // turn into {ax},{dx}. 14864 if (Res.second->hasType(VT)) 14865 return Res; // Correct type already, nothing to do. 14866 14867 // All of the single-register GCC register classes map their values onto 14868 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 14869 // really want an 8-bit or 32-bit register, map to the appropriate register 14870 // class and return the appropriate register. 14871 if (Res.second == X86::GR16RegisterClass) { 14872 if (VT == MVT::i8) { 14873 unsigned DestReg = 0; 14874 switch (Res.first) { 14875 default: break; 14876 case X86::AX: DestReg = X86::AL; break; 14877 case X86::DX: DestReg = X86::DL; break; 14878 case X86::CX: DestReg = X86::CL; break; 14879 case X86::BX: DestReg = X86::BL; break; 14880 } 14881 if (DestReg) { 14882 Res.first = DestReg; 14883 Res.second = X86::GR8RegisterClass; 14884 } 14885 } else if (VT == MVT::i32) { 14886 unsigned DestReg = 0; 14887 switch (Res.first) { 14888 default: break; 14889 case X86::AX: DestReg = X86::EAX; break; 14890 case X86::DX: DestReg = X86::EDX; break; 14891 case X86::CX: DestReg = X86::ECX; break; 14892 case X86::BX: DestReg = X86::EBX; break; 14893 case X86::SI: DestReg = X86::ESI; break; 14894 case X86::DI: DestReg = X86::EDI; break; 14895 case X86::BP: DestReg = X86::EBP; break; 14896 case X86::SP: DestReg = X86::ESP; break; 14897 } 14898 if (DestReg) { 14899 Res.first = DestReg; 14900 Res.second = X86::GR32RegisterClass; 14901 } 14902 } else if (VT == MVT::i64) { 14903 unsigned DestReg = 0; 14904 switch (Res.first) { 14905 default: break; 14906 case X86::AX: DestReg = X86::RAX; break; 14907 case X86::DX: DestReg = X86::RDX; break; 14908 case X86::CX: DestReg = X86::RCX; break; 14909 case X86::BX: DestReg = X86::RBX; break; 14910 case X86::SI: DestReg = X86::RSI; break; 14911 case X86::DI: DestReg = X86::RDI; break; 14912 case X86::BP: DestReg = X86::RBP; break; 14913 case X86::SP: DestReg = X86::RSP; break; 14914 } 14915 if (DestReg) { 14916 Res.first = DestReg; 14917 Res.second = X86::GR64RegisterClass; 14918 } 14919 } 14920 } else if (Res.second == X86::FR32RegisterClass || 14921 Res.second == X86::FR64RegisterClass || 14922 Res.second == X86::VR128RegisterClass) { 14923 // Handle references to XMM physical registers that got mapped into the 14924 // wrong class. This can happen with constraints like {xmm0} where the 14925 // target independent register mapper will just pick the first match it can 14926 // find, ignoring the required type. 14927 if (VT == MVT::f32) 14928 Res.second = X86::FR32RegisterClass; 14929 else if (VT == MVT::f64) 14930 Res.second = X86::FR64RegisterClass; 14931 else if (X86::VR128RegisterClass->hasType(VT)) 14932 Res.second = X86::VR128RegisterClass; 14933 } 14934 14935 return Res; 14936} 14937