X86ISelLowering.cpp revision e11130340898467ab6f46503455a6956995c259b
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/ADT/VectorExtras.h" 26#include "llvm/Analysis/ScalarEvolutionExpressions.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37// FIXME: temporary. 38static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 39 cl::desc("Enable fastcc on X86")); 40static cl::opt<bool> NoShuffleOpti("disable-x86-shuffle-opti", cl::Hidden, 41 cl::desc("Disable vector shuffle optimizations on X86")); 42 43X86TargetLowering::X86TargetLowering(TargetMachine &TM) 44 : TargetLowering(TM) { 45 Subtarget = &TM.getSubtarget<X86Subtarget>(); 46 X86ScalarSSE = Subtarget->hasSSE2(); 47 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 48 49 // Set up the TargetLowering object. 50 51 // X86 is weird, it always uses i8 for shift amounts and setcc results. 52 setShiftAmountType(MVT::i8); 53 setSetCCResultType(MVT::i8); 54 setSetCCResultContents(ZeroOrOneSetCCResult); 55 setSchedulingPreference(SchedulingForRegPressure); 56 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 57 setStackPointerRegisterToSaveRestore(X86StackPtr); 58 59 if (!Subtarget->isTargetDarwin()) 60 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 61 setUseUnderscoreSetJmpLongJmp(true); 62 63 // Add legal addressing mode scale values. 64 addLegalAddressScale(8); 65 addLegalAddressScale(4); 66 addLegalAddressScale(2); 67 // Enter the ones which require both scale + index last. These are more 68 // expensive. 69 addLegalAddressScale(9); 70 addLegalAddressScale(5); 71 addLegalAddressScale(3); 72 73 // Set up the register classes. 74 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 75 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 76 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 77 if (Subtarget->is64Bit()) 78 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 79 80 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 81 82 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 83 // operation. 84 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 85 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 86 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 87 88 if (Subtarget->is64Bit()) { 89 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 90 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 91 } else { 92 if (X86ScalarSSE) 93 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 94 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 95 else 96 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 97 } 98 99 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 100 // this operation. 101 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 102 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 103 // SSE has no i16 to fp conversion, only i32 104 if (X86ScalarSSE) 105 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 106 else { 107 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 108 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 109 } 110 111 if (!Subtarget->is64Bit()) { 112 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode. 113 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 114 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 115 } 116 117 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 118 // this operation. 119 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 120 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 121 122 if (X86ScalarSSE) { 123 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 124 } else { 125 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 126 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 127 } 128 129 // Handle FP_TO_UINT by promoting the destination to a larger signed 130 // conversion. 131 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 132 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 133 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 134 135 if (Subtarget->is64Bit()) { 136 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 137 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 138 } else { 139 if (X86ScalarSSE && !Subtarget->hasSSE3()) 140 // Expand FP_TO_UINT into a select. 141 // FIXME: We would like to use a Custom expander here eventually to do 142 // the optimal thing for SSE vs. the default expansion in the legalizer. 143 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 144 else 145 // With SSE3 we can use fisttpll to convert to a signed i64. 146 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 147 } 148 149 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 150 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 151 152 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 153 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 154 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 155 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 156 if (Subtarget->is64Bit()) 157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 161 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 162 setOperationAction(ISD::FREM , MVT::f64 , Expand); 163 164 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 165 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 166 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 167 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 168 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 169 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 170 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 171 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 172 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 173 if (Subtarget->is64Bit()) { 174 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 175 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 176 setOperationAction(ISD::CTLZ , MVT::i64 , Expand); 177 } 178 179 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 180 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 181 182 // These should be promoted to a larger select which is supported. 183 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 184 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 185 // X86 wants to expand cmov itself. 186 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 187 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 188 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 189 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 190 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 191 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 192 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 193 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 194 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 195 if (Subtarget->is64Bit()) { 196 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 197 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 198 } 199 // X86 ret instruction may pop stack. 200 setOperationAction(ISD::RET , MVT::Other, Custom); 201 // Darwin ABI issue. 202 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 203 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 204 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 205 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 206 if (Subtarget->is64Bit()) { 207 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 208 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 209 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 210 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 211 } 212 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 213 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 214 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 215 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 216 // X86 wants to expand memset / memcpy itself. 217 setOperationAction(ISD::MEMSET , MVT::Other, Custom); 218 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 219 220 // We don't have line number support yet. 221 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 222 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 223 // FIXME - use subtarget debug flags 224 if (!Subtarget->isTargetDarwin()) 225 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 226 227 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 228 setOperationAction(ISD::VASTART , MVT::Other, Custom); 229 230 // Use the default implementation. 231 setOperationAction(ISD::VAARG , MVT::Other, Expand); 232 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 233 setOperationAction(ISD::VAEND , MVT::Other, Expand); 234 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 235 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 236 if (Subtarget->is64Bit()) 237 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 238 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 239 240 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 242 243 if (X86ScalarSSE) { 244 // Set up the FP register classes. 245 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 246 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 247 248 // Use ANDPD to simulate FABS. 249 setOperationAction(ISD::FABS , MVT::f64, Custom); 250 setOperationAction(ISD::FABS , MVT::f32, Custom); 251 252 // Use XORP to simulate FNEG. 253 setOperationAction(ISD::FNEG , MVT::f64, Custom); 254 setOperationAction(ISD::FNEG , MVT::f32, Custom); 255 256 // We don't support sin/cos/fmod 257 setOperationAction(ISD::FSIN , MVT::f64, Expand); 258 setOperationAction(ISD::FCOS , MVT::f64, Expand); 259 setOperationAction(ISD::FREM , MVT::f64, Expand); 260 setOperationAction(ISD::FSIN , MVT::f32, Expand); 261 setOperationAction(ISD::FCOS , MVT::f32, Expand); 262 setOperationAction(ISD::FREM , MVT::f32, Expand); 263 264 // Expand FP immediates into loads from the stack, except for the special 265 // cases we handle. 266 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 267 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 268 addLegalFPImmediate(+0.0); // xorps / xorpd 269 } else { 270 // Set up the FP register classes. 271 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 272 273 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 274 275 if (!UnsafeFPMath) { 276 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 277 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 278 } 279 280 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 281 addLegalFPImmediate(+0.0); // FLD0 282 addLegalFPImmediate(+1.0); // FLD1 283 addLegalFPImmediate(-0.0); // FLD0/FCHS 284 addLegalFPImmediate(-1.0); // FLD1/FCHS 285 } 286 287 // First set operation action for all vector types to expand. Then we 288 // will selectively turn on ones that can be effectively codegen'd. 289 for (unsigned VT = (unsigned)MVT::Vector + 1; 290 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { 291 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); 292 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); 293 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 294 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); 295 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); 296 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 297 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 298 } 299 300 if (Subtarget->hasMMX()) { 301 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 302 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 303 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 304 305 // FIXME: add MMX packed arithmetics 306 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); 307 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); 308 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); 309 } 310 311 if (Subtarget->hasSSE1()) { 312 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 313 314 setOperationAction(ISD::AND, MVT::v4f32, Legal); 315 setOperationAction(ISD::OR, MVT::v4f32, Legal); 316 setOperationAction(ISD::XOR, MVT::v4f32, Legal); 317 setOperationAction(ISD::ADD, MVT::v4f32, Legal); 318 setOperationAction(ISD::SUB, MVT::v4f32, Legal); 319 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 320 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 321 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 322 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 324 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 325 } 326 327 if (Subtarget->hasSSE2()) { 328 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 329 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 330 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 331 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 332 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 333 334 setOperationAction(ISD::ADD, MVT::v2f64, Legal); 335 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 336 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 337 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 338 setOperationAction(ISD::SUB, MVT::v2f64, Legal); 339 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 340 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 341 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 342 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 343 setOperationAction(ISD::MUL, MVT::v2f64, Legal); 344 345 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 346 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 347 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 348 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 349 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones. 350 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 351 352 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 353 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 354 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); 355 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); 356 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); 357 } 358 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 359 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 360 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 361 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 362 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 364 365 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 366 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 367 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); 368 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); 369 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); 370 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); 371 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); 372 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); 373 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); 374 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); 375 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 376 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); 377 } 378 379 // Custom lower v2i64 and v2f64 selects. 380 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 381 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 382 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 383 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 384 } 385 386 // We want to custom lower some of our intrinsics. 387 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 388 389 // We have target-specific dag combine patterns for the following nodes: 390 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 391 setTargetDAGCombine(ISD::SELECT); 392 393 computeRegisterProperties(); 394 395 // FIXME: These should be based on subtarget info. Plus, the values should 396 // be smaller when we are in optimizing for size mode. 397 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores 398 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores 399 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores 400 allowUnalignedMemoryAccesses = true; // x86 supports it! 401} 402 403//===----------------------------------------------------------------------===// 404// C Calling Convention implementation 405//===----------------------------------------------------------------------===// 406 407/// AddLiveIn - This helper function adds the specified physical register to the 408/// MachineFunction as a live in value. It also creates a corresponding virtual 409/// register for it. 410static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 411 TargetRegisterClass *RC) { 412 assert(RC->contains(PReg) && "Not the correct regclass!"); 413 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 414 MF.addLiveIn(PReg, VReg); 415 return VReg; 416} 417 418/// HowToPassCCCArgument - Returns how an formal argument of the specified type 419/// should be passed. If it is through stack, returns the size of the stack 420/// slot; if it is through XMM register, returns the number of XMM registers 421/// are needed. 422static void 423HowToPassCCCArgument(MVT::ValueType ObjectVT, unsigned NumXMMRegs, 424 unsigned &ObjSize, unsigned &ObjXMMRegs) { 425 ObjXMMRegs = 0; 426 427 switch (ObjectVT) { 428 default: assert(0 && "Unhandled argument type!"); 429 case MVT::i8: ObjSize = 1; break; 430 case MVT::i16: ObjSize = 2; break; 431 case MVT::i32: ObjSize = 4; break; 432 case MVT::i64: ObjSize = 8; break; 433 case MVT::f32: ObjSize = 4; break; 434 case MVT::f64: ObjSize = 8; break; 435 case MVT::v16i8: 436 case MVT::v8i16: 437 case MVT::v4i32: 438 case MVT::v2i64: 439 case MVT::v4f32: 440 case MVT::v2f64: 441 if (NumXMMRegs < 4) 442 ObjXMMRegs = 1; 443 else 444 ObjSize = 16; 445 break; 446 } 447} 448 449SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) { 450 unsigned NumArgs = Op.Val->getNumValues() - 1; 451 MachineFunction &MF = DAG.getMachineFunction(); 452 MachineFrameInfo *MFI = MF.getFrameInfo(); 453 SDOperand Root = Op.getOperand(0); 454 std::vector<SDOperand> ArgValues; 455 456 // Add DAG nodes to load the arguments... On entry to a function on the X86, 457 // the stack frame looks like this: 458 // 459 // [ESP] -- return address 460 // [ESP + 4] -- first argument (leftmost lexically) 461 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size 462 // ... 463 // 464 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 465 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 466 static const unsigned XMMArgRegs[] = { 467 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 468 }; 469 for (unsigned i = 0; i < NumArgs; ++i) { 470 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 471 unsigned ArgIncrement = 4; 472 unsigned ObjSize = 0; 473 unsigned ObjXMMRegs = 0; 474 HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs); 475 if (ObjSize > 4) 476 ArgIncrement = ObjSize; 477 478 SDOperand ArgValue; 479 if (ObjXMMRegs) { 480 // Passed in a XMM register. 481 unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 482 X86::VR128RegisterClass); 483 ArgValue= DAG.getCopyFromReg(Root, Reg, ObjectVT); 484 ArgValues.push_back(ArgValue); 485 NumXMMRegs += ObjXMMRegs; 486 } else { 487 // XMM arguments have to be aligned on 16-byte boundary. 488 if (ObjSize == 16) 489 ArgOffset = ((ArgOffset + 15) / 16) * 16; 490 // Create the frame index object for this incoming parameter... 491 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 492 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 493 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 494 DAG.getSrcValue(NULL)); 495 ArgValues.push_back(ArgValue); 496 ArgOffset += ArgIncrement; // Move on to the next argument... 497 } 498 } 499 500 ArgValues.push_back(Root); 501 502 // If the function takes variable number of arguments, make a frame index for 503 // the start of the first vararg value... for expansion of llvm.va_start. 504 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 505 if (isVarArg) 506 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 507 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 508 ReturnAddrIndex = 0; // No return address slot generated yet. 509 BytesToPopOnReturn = 0; // Callee pops nothing. 510 BytesCallerReserves = ArgOffset; 511 512 // If this is a struct return on Darwin/X86, the callee pops the hidden struct 513 // pointer. 514 if (MF.getFunction()->getCallingConv() == CallingConv::CSRet && 515 Subtarget->isTargetDarwin()) 516 BytesToPopOnReturn = 4; 517 518 // Return the new list of results. 519 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 520 Op.Val->value_end()); 521 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 522} 523 524 525SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) { 526 SDOperand Chain = Op.getOperand(0); 527 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 528 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 529 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 530 SDOperand Callee = Op.getOperand(4); 531 MVT::ValueType RetVT= Op.Val->getValueType(0); 532 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 533 534 // Keep track of the number of XMM regs passed so far. 535 unsigned NumXMMRegs = 0; 536 static const unsigned XMMArgRegs[] = { 537 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 538 }; 539 540 // Count how many bytes are to be pushed on the stack. 541 unsigned NumBytes = 0; 542 for (unsigned i = 0; i != NumOps; ++i) { 543 SDOperand Arg = Op.getOperand(5+2*i); 544 545 switch (Arg.getValueType()) { 546 default: assert(0 && "Unexpected ValueType for argument!"); 547 case MVT::i8: 548 case MVT::i16: 549 case MVT::i32: 550 case MVT::f32: 551 NumBytes += 4; 552 break; 553 case MVT::i64: 554 case MVT::f64: 555 NumBytes += 8; 556 break; 557 case MVT::v16i8: 558 case MVT::v8i16: 559 case MVT::v4i32: 560 case MVT::v2i64: 561 case MVT::v4f32: 562 case MVT::v2f64: 563 if (NumXMMRegs < 4) 564 ++NumXMMRegs; 565 else { 566 // XMM arguments have to be aligned on 16-byte boundary. 567 NumBytes = ((NumBytes + 15) / 16) * 16; 568 NumBytes += 16; 569 } 570 break; 571 } 572 } 573 574 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 575 576 // Arguments go on the stack in reverse order, as specified by the ABI. 577 unsigned ArgOffset = 0; 578 NumXMMRegs = 0; 579 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 580 std::vector<SDOperand> MemOpChains; 581 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 582 for (unsigned i = 0; i != NumOps; ++i) { 583 SDOperand Arg = Op.getOperand(5+2*i); 584 585 switch (Arg.getValueType()) { 586 default: assert(0 && "Unexpected ValueType for argument!"); 587 case MVT::i8: 588 case MVT::i16: { 589 // Promote the integer to 32 bits. If the input type is signed use a 590 // sign extend, otherwise use a zero extend. 591 unsigned ExtOp = 592 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue() ? 593 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 594 Arg = DAG.getNode(ExtOp, MVT::i32, Arg); 595 } 596 // Fallthrough 597 598 case MVT::i32: 599 case MVT::f32: { 600 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 601 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 602 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 603 Arg, PtrOff, DAG.getSrcValue(NULL))); 604 ArgOffset += 4; 605 break; 606 } 607 case MVT::i64: 608 case MVT::f64: { 609 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 610 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 611 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 612 Arg, PtrOff, DAG.getSrcValue(NULL))); 613 ArgOffset += 8; 614 break; 615 } 616 case MVT::v16i8: 617 case MVT::v8i16: 618 case MVT::v4i32: 619 case MVT::v2i64: 620 case MVT::v4f32: 621 case MVT::v2f64: 622 if (NumXMMRegs < 4) { 623 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 624 NumXMMRegs++; 625 } else { 626 // XMM arguments have to be aligned on 16-byte boundary. 627 ArgOffset = ((ArgOffset + 15) / 16) * 16; 628 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 629 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 630 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 631 Arg, PtrOff, DAG.getSrcValue(NULL))); 632 ArgOffset += 16; 633 } 634 } 635 } 636 637 if (!MemOpChains.empty()) 638 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 639 &MemOpChains[0], MemOpChains.size()); 640 641 // Build a sequence of copy-to-reg nodes chained together with token chain 642 // and flag operands which copy the outgoing args into registers. 643 SDOperand InFlag; 644 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 645 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 646 InFlag); 647 InFlag = Chain.getValue(1); 648 } 649 650 // If the callee is a GlobalAddress node (quite common, every direct call is) 651 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 652 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 653 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 654 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 655 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 656 657 std::vector<MVT::ValueType> NodeTys; 658 NodeTys.push_back(MVT::Other); // Returns a chain 659 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 660 std::vector<SDOperand> Ops; 661 Ops.push_back(Chain); 662 Ops.push_back(Callee); 663 664 // Add argument registers to the end of the list so that they are known live 665 // into the call. 666 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 667 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 668 RegsToPass[i].second.getValueType())); 669 670 if (InFlag.Val) 671 Ops.push_back(InFlag); 672 673 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 674 NodeTys, &Ops[0], Ops.size()); 675 InFlag = Chain.getValue(1); 676 677 // Create the CALLSEQ_END node. 678 unsigned NumBytesForCalleeToPush = 0; 679 680 // If this is is a call to a struct-return function on Darwin/X86, the callee 681 // pops the hidden struct pointer, so we have to push it back. 682 if (CallingConv == CallingConv::CSRet && Subtarget->isTargetDarwin()) 683 NumBytesForCalleeToPush = 4; 684 685 NodeTys.clear(); 686 NodeTys.push_back(MVT::Other); // Returns a chain 687 if (RetVT != MVT::Other) 688 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 689 Ops.clear(); 690 Ops.push_back(Chain); 691 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 692 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy())); 693 Ops.push_back(InFlag); 694 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 695 if (RetVT != MVT::Other) 696 InFlag = Chain.getValue(1); 697 698 std::vector<SDOperand> ResultVals; 699 NodeTys.clear(); 700 switch (RetVT) { 701 default: assert(0 && "Unknown value type to return!"); 702 case MVT::Other: break; 703 case MVT::i8: 704 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 705 ResultVals.push_back(Chain.getValue(0)); 706 NodeTys.push_back(MVT::i8); 707 break; 708 case MVT::i16: 709 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 710 ResultVals.push_back(Chain.getValue(0)); 711 NodeTys.push_back(MVT::i16); 712 break; 713 case MVT::i32: 714 if (Op.Val->getValueType(1) == MVT::i32) { 715 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 716 ResultVals.push_back(Chain.getValue(0)); 717 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32, 718 Chain.getValue(2)).getValue(1); 719 ResultVals.push_back(Chain.getValue(0)); 720 NodeTys.push_back(MVT::i32); 721 } else { 722 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 723 ResultVals.push_back(Chain.getValue(0)); 724 } 725 NodeTys.push_back(MVT::i32); 726 break; 727 case MVT::v16i8: 728 case MVT::v8i16: 729 case MVT::v4i32: 730 case MVT::v2i64: 731 case MVT::v4f32: 732 case MVT::v2f64: 733 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 734 ResultVals.push_back(Chain.getValue(0)); 735 NodeTys.push_back(RetVT); 736 break; 737 case MVT::f32: 738 case MVT::f64: { 739 std::vector<MVT::ValueType> Tys; 740 Tys.push_back(MVT::f64); 741 Tys.push_back(MVT::Other); 742 Tys.push_back(MVT::Flag); 743 std::vector<SDOperand> Ops; 744 Ops.push_back(Chain); 745 Ops.push_back(InFlag); 746 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 747 &Ops[0], Ops.size()); 748 Chain = RetVal.getValue(1); 749 InFlag = RetVal.getValue(2); 750 if (X86ScalarSSE) { 751 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 752 // shouldn't be necessary except that RFP cannot be live across 753 // multiple blocks. When stackifier is fixed, they can be uncoupled. 754 MachineFunction &MF = DAG.getMachineFunction(); 755 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 756 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 757 Tys.clear(); 758 Tys.push_back(MVT::Other); 759 Ops.clear(); 760 Ops.push_back(Chain); 761 Ops.push_back(RetVal); 762 Ops.push_back(StackSlot); 763 Ops.push_back(DAG.getValueType(RetVT)); 764 Ops.push_back(InFlag); 765 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 766 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, 767 DAG.getSrcValue(NULL)); 768 Chain = RetVal.getValue(1); 769 } 770 771 if (RetVT == MVT::f32 && !X86ScalarSSE) 772 // FIXME: we would really like to remember that this FP_ROUND 773 // operation is okay to eliminate if we allow excess FP precision. 774 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 775 ResultVals.push_back(RetVal); 776 NodeTys.push_back(RetVT); 777 break; 778 } 779 } 780 781 // If the function returns void, just return the chain. 782 if (ResultVals.empty()) 783 return Chain; 784 785 // Otherwise, merge everything together with a MERGE_VALUES node. 786 NodeTys.push_back(MVT::Other); 787 ResultVals.push_back(Chain); 788 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 789 &ResultVals[0], ResultVals.size()); 790 return Res.getValue(Op.ResNo); 791} 792 793 794//===----------------------------------------------------------------------===// 795// X86-64 C Calling Convention implementation 796//===----------------------------------------------------------------------===// 797 798/// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified 799/// type should be passed. If it is through stack, returns the size of the stack 800/// slot; if it is through integer or XMM register, returns the number of 801/// integer or XMM registers are needed. 802static void 803HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT, 804 unsigned NumIntRegs, unsigned NumXMMRegs, 805 unsigned &ObjSize, unsigned &ObjIntRegs, 806 unsigned &ObjXMMRegs) { 807 ObjSize = 0; 808 ObjIntRegs = 0; 809 ObjXMMRegs = 0; 810 811 switch (ObjectVT) { 812 default: assert(0 && "Unhandled argument type!"); 813 case MVT::i8: 814 case MVT::i16: 815 case MVT::i32: 816 case MVT::i64: 817 if (NumIntRegs < 6) 818 ObjIntRegs = 1; 819 else { 820 switch (ObjectVT) { 821 default: break; 822 case MVT::i8: ObjSize = 1; break; 823 case MVT::i16: ObjSize = 2; break; 824 case MVT::i32: ObjSize = 4; break; 825 case MVT::i64: ObjSize = 8; break; 826 } 827 } 828 break; 829 case MVT::f32: 830 case MVT::f64: 831 case MVT::v16i8: 832 case MVT::v8i16: 833 case MVT::v4i32: 834 case MVT::v2i64: 835 case MVT::v4f32: 836 case MVT::v2f64: 837 if (NumXMMRegs < 8) 838 ObjXMMRegs = 1; 839 else { 840 switch (ObjectVT) { 841 default: break; 842 case MVT::f32: ObjSize = 4; break; 843 case MVT::f64: ObjSize = 8; break; 844 case MVT::v16i8: 845 case MVT::v8i16: 846 case MVT::v4i32: 847 case MVT::v2i64: 848 case MVT::v4f32: 849 case MVT::v2f64: ObjSize = 16; break; 850 } 851 break; 852 } 853 } 854} 855 856SDOperand 857X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { 858 unsigned NumArgs = Op.Val->getNumValues() - 1; 859 MachineFunction &MF = DAG.getMachineFunction(); 860 MachineFrameInfo *MFI = MF.getFrameInfo(); 861 SDOperand Root = Op.getOperand(0); 862 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 863 std::vector<SDOperand> ArgValues; 864 865 // Add DAG nodes to load the arguments... On entry to a function on the X86, 866 // the stack frame looks like this: 867 // 868 // [RSP] -- return address 869 // [RSP + 8] -- first nonreg argument (leftmost lexically) 870 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size 871 // ... 872 // 873 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 874 unsigned NumIntRegs = 0; // Int regs used for parameter passing. 875 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 876 877 static const unsigned GPR8ArgRegs[] = { 878 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B 879 }; 880 static const unsigned GPR16ArgRegs[] = { 881 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W 882 }; 883 static const unsigned GPR32ArgRegs[] = { 884 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 885 }; 886 static const unsigned GPR64ArgRegs[] = { 887 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 888 }; 889 static const unsigned XMMArgRegs[] = { 890 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 891 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 892 }; 893 894 for (unsigned i = 0; i < NumArgs; ++i) { 895 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 896 unsigned ArgIncrement = 8; 897 unsigned ObjSize = 0; 898 unsigned ObjIntRegs = 0; 899 unsigned ObjXMMRegs = 0; 900 901 // FIXME: __int128 and long double support? 902 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs, 903 ObjSize, ObjIntRegs, ObjXMMRegs); 904 if (ObjSize > 8) 905 ArgIncrement = ObjSize; 906 907 unsigned Reg = 0; 908 SDOperand ArgValue; 909 if (ObjIntRegs || ObjXMMRegs) { 910 switch (ObjectVT) { 911 default: assert(0 && "Unhandled argument type!"); 912 case MVT::i8: 913 case MVT::i16: 914 case MVT::i32: 915 case MVT::i64: { 916 TargetRegisterClass *RC = NULL; 917 switch (ObjectVT) { 918 default: break; 919 case MVT::i8: 920 RC = X86::GR8RegisterClass; 921 Reg = GPR8ArgRegs[NumIntRegs]; 922 break; 923 case MVT::i16: 924 RC = X86::GR16RegisterClass; 925 Reg = GPR16ArgRegs[NumIntRegs]; 926 break; 927 case MVT::i32: 928 RC = X86::GR32RegisterClass; 929 Reg = GPR32ArgRegs[NumIntRegs]; 930 break; 931 case MVT::i64: 932 RC = X86::GR64RegisterClass; 933 Reg = GPR64ArgRegs[NumIntRegs]; 934 break; 935 } 936 Reg = AddLiveIn(MF, Reg, RC); 937 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 938 break; 939 } 940 case MVT::f32: 941 case MVT::f64: 942 case MVT::v16i8: 943 case MVT::v8i16: 944 case MVT::v4i32: 945 case MVT::v2i64: 946 case MVT::v4f32: 947 case MVT::v2f64: { 948 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ? 949 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ? 950 X86::FR64RegisterClass : X86::VR128RegisterClass); 951 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC); 952 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 953 break; 954 } 955 } 956 NumIntRegs += ObjIntRegs; 957 NumXMMRegs += ObjXMMRegs; 958 } else if (ObjSize) { 959 // XMM arguments have to be aligned on 16-byte boundary. 960 if (ObjSize == 16) 961 ArgOffset = ((ArgOffset + 15) / 16) * 16; 962 // Create the SelectionDAG nodes corresponding to a load from this 963 // parameter. 964 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 965 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 966 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 967 DAG.getSrcValue(NULL)); 968 ArgOffset += ArgIncrement; // Move on to the next argument. 969 } 970 971 ArgValues.push_back(ArgValue); 972 } 973 974 // If the function takes variable number of arguments, make a frame index for 975 // the start of the first vararg value... for expansion of llvm.va_start. 976 if (isVarArg) { 977 // For X86-64, if there are vararg parameters that are passed via 978 // registers, then we must store them to their spots on the stack so they 979 // may be loaded by deferencing the result of va_next. 980 VarArgsGPOffset = NumIntRegs * 8; 981 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16; 982 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 983 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16); 984 985 // Store the integer parameter registers. 986 std::vector<SDOperand> MemOps; 987 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 988 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 989 DAG.getConstant(VarArgsGPOffset, getPointerTy())); 990 for (; NumIntRegs != 6; ++NumIntRegs) { 991 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 992 X86::GR64RegisterClass); 993 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 994 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 995 Val, FIN, DAG.getSrcValue(NULL)); 996 MemOps.push_back(Store); 997 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 998 DAG.getConstant(8, getPointerTy())); 999 } 1000 1001 // Now store the XMM (fp + vector) parameter registers. 1002 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1003 DAG.getConstant(VarArgsFPOffset, getPointerTy())); 1004 for (; NumXMMRegs != 8; ++NumXMMRegs) { 1005 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1006 X86::VR128RegisterClass); 1007 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1008 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 1009 Val, FIN, DAG.getSrcValue(NULL)); 1010 MemOps.push_back(Store); 1011 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1012 DAG.getConstant(16, getPointerTy())); 1013 } 1014 if (!MemOps.empty()) 1015 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1016 &MemOps[0], MemOps.size()); 1017 } 1018 1019 ArgValues.push_back(Root); 1020 1021 ReturnAddrIndex = 0; // No return address slot generated yet. 1022 BytesToPopOnReturn = 0; // Callee pops nothing. 1023 BytesCallerReserves = ArgOffset; 1024 1025 // Return the new list of results. 1026 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 1027 Op.Val->value_end()); 1028 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 1029} 1030 1031SDOperand 1032X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) { 1033 SDOperand Chain = Op.getOperand(0); 1034 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1035 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1036 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1037 SDOperand Callee = Op.getOperand(4); 1038 MVT::ValueType RetVT= Op.Val->getValueType(0); 1039 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1040 1041 // Count how many bytes are to be pushed on the stack. 1042 unsigned NumBytes = 0; 1043 unsigned NumIntRegs = 0; // Int regs used for parameter passing. 1044 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1045 1046 static const unsigned GPR8ArgRegs[] = { 1047 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B 1048 }; 1049 static const unsigned GPR16ArgRegs[] = { 1050 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W 1051 }; 1052 static const unsigned GPR32ArgRegs[] = { 1053 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 1054 }; 1055 static const unsigned GPR64ArgRegs[] = { 1056 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1057 }; 1058 static const unsigned XMMArgRegs[] = { 1059 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1060 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1061 }; 1062 1063 for (unsigned i = 0; i != NumOps; ++i) { 1064 SDOperand Arg = Op.getOperand(5+2*i); 1065 MVT::ValueType ArgVT = Arg.getValueType(); 1066 1067 switch (ArgVT) { 1068 default: assert(0 && "Unknown value type!"); 1069 case MVT::i8: 1070 case MVT::i16: 1071 case MVT::i32: 1072 case MVT::i64: 1073 if (NumIntRegs < 6) 1074 ++NumIntRegs; 1075 else 1076 NumBytes += 8; 1077 break; 1078 case MVT::f32: 1079 case MVT::f64: 1080 case MVT::v16i8: 1081 case MVT::v8i16: 1082 case MVT::v4i32: 1083 case MVT::v2i64: 1084 case MVT::v4f32: 1085 case MVT::v2f64: 1086 if (NumXMMRegs < 8) 1087 NumXMMRegs++; 1088 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64) 1089 NumBytes += 8; 1090 else { 1091 // XMM arguments have to be aligned on 16-byte boundary. 1092 NumBytes = ((NumBytes + 15) / 16) * 16; 1093 NumBytes += 16; 1094 } 1095 break; 1096 } 1097 } 1098 1099 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1100 1101 // Arguments go on the stack in reverse order, as specified by the ABI. 1102 unsigned ArgOffset = 0; 1103 NumIntRegs = 0; 1104 NumXMMRegs = 0; 1105 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1106 std::vector<SDOperand> MemOpChains; 1107 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 1108 for (unsigned i = 0; i != NumOps; ++i) { 1109 SDOperand Arg = Op.getOperand(5+2*i); 1110 MVT::ValueType ArgVT = Arg.getValueType(); 1111 1112 switch (ArgVT) { 1113 default: assert(0 && "Unexpected ValueType for argument!"); 1114 case MVT::i8: 1115 case MVT::i16: 1116 case MVT::i32: 1117 case MVT::i64: 1118 if (NumIntRegs < 6) { 1119 unsigned Reg = 0; 1120 switch (ArgVT) { 1121 default: break; 1122 case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break; 1123 case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break; 1124 case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break; 1125 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break; 1126 } 1127 RegsToPass.push_back(std::make_pair(Reg, Arg)); 1128 ++NumIntRegs; 1129 } else { 1130 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1131 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1132 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1133 Arg, PtrOff, DAG.getSrcValue(NULL))); 1134 ArgOffset += 8; 1135 } 1136 break; 1137 case MVT::f32: 1138 case MVT::f64: 1139 case MVT::v16i8: 1140 case MVT::v8i16: 1141 case MVT::v4i32: 1142 case MVT::v2i64: 1143 case MVT::v4f32: 1144 case MVT::v2f64: 1145 if (NumXMMRegs < 8) { 1146 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 1147 NumXMMRegs++; 1148 } else { 1149 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) { 1150 // XMM arguments have to be aligned on 16-byte boundary. 1151 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1152 } 1153 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1154 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1155 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1156 Arg, PtrOff, DAG.getSrcValue(NULL))); 1157 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) 1158 ArgOffset += 8; 1159 else 1160 ArgOffset += 16; 1161 } 1162 } 1163 } 1164 1165 if (!MemOpChains.empty()) 1166 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1167 &MemOpChains[0], MemOpChains.size()); 1168 1169 // Build a sequence of copy-to-reg nodes chained together with token chain 1170 // and flag operands which copy the outgoing args into registers. 1171 SDOperand InFlag; 1172 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1173 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1174 InFlag); 1175 InFlag = Chain.getValue(1); 1176 } 1177 1178 if (isVarArg) { 1179 // From AMD64 ABI document: 1180 // For calls that may call functions that use varargs or stdargs 1181 // (prototype-less calls or calls to functions containing ellipsis (...) in 1182 // the declaration) %al is used as hidden argument to specify the number 1183 // of SSE registers used. The contents of %al do not need to match exactly 1184 // the number of registers, but must be an ubound on the number of SSE 1185 // registers used and is in the range 0 - 8 inclusive. 1186 Chain = DAG.getCopyToReg(Chain, X86::AL, 1187 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1188 InFlag = Chain.getValue(1); 1189 } 1190 1191 // If the callee is a GlobalAddress node (quite common, every direct call is) 1192 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1193 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1194 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1195 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1196 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1197 1198 std::vector<MVT::ValueType> NodeTys; 1199 NodeTys.push_back(MVT::Other); // Returns a chain 1200 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1201 std::vector<SDOperand> Ops; 1202 Ops.push_back(Chain); 1203 Ops.push_back(Callee); 1204 1205 // Add argument registers to the end of the list so that they are known live 1206 // into the call. 1207 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1208 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1209 RegsToPass[i].second.getValueType())); 1210 1211 if (InFlag.Val) 1212 Ops.push_back(InFlag); 1213 1214 // FIXME: Do not generate X86ISD::TAILCALL for now. 1215 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1216 NodeTys, &Ops[0], Ops.size()); 1217 InFlag = Chain.getValue(1); 1218 1219 NodeTys.clear(); 1220 NodeTys.push_back(MVT::Other); // Returns a chain 1221 if (RetVT != MVT::Other) 1222 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1223 Ops.clear(); 1224 Ops.push_back(Chain); 1225 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1226 Ops.push_back(DAG.getConstant(0, getPointerTy())); 1227 Ops.push_back(InFlag); 1228 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1229 if (RetVT != MVT::Other) 1230 InFlag = Chain.getValue(1); 1231 1232 std::vector<SDOperand> ResultVals; 1233 NodeTys.clear(); 1234 switch (RetVT) { 1235 default: assert(0 && "Unknown value type to return!"); 1236 case MVT::Other: break; 1237 case MVT::i8: 1238 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 1239 ResultVals.push_back(Chain.getValue(0)); 1240 NodeTys.push_back(MVT::i8); 1241 break; 1242 case MVT::i16: 1243 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 1244 ResultVals.push_back(Chain.getValue(0)); 1245 NodeTys.push_back(MVT::i16); 1246 break; 1247 case MVT::i32: 1248 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1249 ResultVals.push_back(Chain.getValue(0)); 1250 NodeTys.push_back(MVT::i32); 1251 break; 1252 case MVT::i64: 1253 if (Op.Val->getValueType(1) == MVT::i64) { 1254 // FIXME: __int128 support? 1255 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1); 1256 ResultVals.push_back(Chain.getValue(0)); 1257 Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64, 1258 Chain.getValue(2)).getValue(1); 1259 ResultVals.push_back(Chain.getValue(0)); 1260 NodeTys.push_back(MVT::i64); 1261 } else { 1262 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1); 1263 ResultVals.push_back(Chain.getValue(0)); 1264 } 1265 NodeTys.push_back(MVT::i64); 1266 break; 1267 case MVT::f32: 1268 case MVT::f64: 1269 case MVT::v16i8: 1270 case MVT::v8i16: 1271 case MVT::v4i32: 1272 case MVT::v2i64: 1273 case MVT::v4f32: 1274 case MVT::v2f64: 1275 // FIXME: long double support? 1276 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 1277 ResultVals.push_back(Chain.getValue(0)); 1278 NodeTys.push_back(RetVT); 1279 break; 1280 } 1281 1282 // If the function returns void, just return the chain. 1283 if (ResultVals.empty()) 1284 return Chain; 1285 1286 // Otherwise, merge everything together with a MERGE_VALUES node. 1287 NodeTys.push_back(MVT::Other); 1288 ResultVals.push_back(Chain); 1289 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1290 &ResultVals[0], ResultVals.size()); 1291 return Res.getValue(Op.ResNo); 1292} 1293 1294//===----------------------------------------------------------------------===// 1295// Fast Calling Convention implementation 1296//===----------------------------------------------------------------------===// 1297// 1298// The X86 'fast' calling convention passes up to two integer arguments in 1299// registers (an appropriate portion of EAX/EDX), passes arguments in C order, 1300// and requires that the callee pop its arguments off the stack (allowing proper 1301// tail calls), and has the same return value conventions as C calling convs. 1302// 1303// This calling convention always arranges for the callee pop value to be 8n+4 1304// bytes, which is needed for tail recursion elimination and stack alignment 1305// reasons. 1306// 1307// Note that this can be enhanced in the future to pass fp vals in registers 1308// (when we have a global fp allocator) and do other tricks. 1309// 1310 1311/// HowToPassFastCCArgument - Returns how an formal argument of the specified 1312/// type should be passed. If it is through stack, returns the size of the stack 1313/// slot; if it is through integer or XMM register, returns the number of 1314/// integer or XMM registers are needed. 1315static void 1316HowToPassFastCCArgument(MVT::ValueType ObjectVT, 1317 unsigned NumIntRegs, unsigned NumXMMRegs, 1318 unsigned &ObjSize, unsigned &ObjIntRegs, 1319 unsigned &ObjXMMRegs) { 1320 ObjSize = 0; 1321 ObjIntRegs = 0; 1322 ObjXMMRegs = 0; 1323 1324 switch (ObjectVT) { 1325 default: assert(0 && "Unhandled argument type!"); 1326 case MVT::i8: 1327#if FASTCC_NUM_INT_ARGS_INREGS > 0 1328 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) 1329 ObjIntRegs = 1; 1330 else 1331#endif 1332 ObjSize = 1; 1333 break; 1334 case MVT::i16: 1335#if FASTCC_NUM_INT_ARGS_INREGS > 0 1336 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) 1337 ObjIntRegs = 1; 1338 else 1339#endif 1340 ObjSize = 2; 1341 break; 1342 case MVT::i32: 1343#if FASTCC_NUM_INT_ARGS_INREGS > 0 1344 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) 1345 ObjIntRegs = 1; 1346 else 1347#endif 1348 ObjSize = 4; 1349 break; 1350 case MVT::i64: 1351#if FASTCC_NUM_INT_ARGS_INREGS > 0 1352 if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) { 1353 ObjIntRegs = 2; 1354 } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) { 1355 ObjIntRegs = 1; 1356 ObjSize = 4; 1357 } else 1358#endif 1359 ObjSize = 8; 1360 case MVT::f32: 1361 ObjSize = 4; 1362 break; 1363 case MVT::f64: 1364 ObjSize = 8; 1365 break; 1366 case MVT::v16i8: 1367 case MVT::v8i16: 1368 case MVT::v4i32: 1369 case MVT::v2i64: 1370 case MVT::v4f32: 1371 case MVT::v2f64: 1372 if (NumXMMRegs < 4) 1373 ObjXMMRegs = 1; 1374 else 1375 ObjSize = 16; 1376 break; 1377 } 1378} 1379 1380SDOperand 1381X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) { 1382 unsigned NumArgs = Op.Val->getNumValues()-1; 1383 MachineFunction &MF = DAG.getMachineFunction(); 1384 MachineFrameInfo *MFI = MF.getFrameInfo(); 1385 SDOperand Root = Op.getOperand(0); 1386 std::vector<SDOperand> ArgValues; 1387 1388 // Add DAG nodes to load the arguments... On entry to a function the stack 1389 // frame looks like this: 1390 // 1391 // [ESP] -- return address 1392 // [ESP + 4] -- first nonreg argument (leftmost lexically) 1393 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size 1394 // ... 1395 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 1396 1397 // Keep track of the number of integer regs passed so far. This can be either 1398 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 1399 // used). 1400 unsigned NumIntRegs = 0; 1401 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1402 1403 static const unsigned XMMArgRegs[] = { 1404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1405 }; 1406 1407 for (unsigned i = 0; i < NumArgs; ++i) { 1408 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 1409 unsigned ArgIncrement = 4; 1410 unsigned ObjSize = 0; 1411 unsigned ObjIntRegs = 0; 1412 unsigned ObjXMMRegs = 0; 1413 1414 HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs, 1415 ObjSize, ObjIntRegs, ObjXMMRegs); 1416 if (ObjSize > 4) 1417 ArgIncrement = ObjSize; 1418 1419 unsigned Reg = 0; 1420 SDOperand ArgValue; 1421 if (ObjIntRegs || ObjXMMRegs) { 1422 switch (ObjectVT) { 1423 default: assert(0 && "Unhandled argument type!"); 1424 case MVT::i8: 1425 Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, 1426 X86::GR8RegisterClass); 1427 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i8); 1428 break; 1429 case MVT::i16: 1430 Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, 1431 X86::GR16RegisterClass); 1432 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i16); 1433 break; 1434 case MVT::i32: 1435 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX, 1436 X86::GR32RegisterClass); 1437 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32); 1438 break; 1439 case MVT::i64: 1440 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX, 1441 X86::GR32RegisterClass); 1442 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32); 1443 if (ObjIntRegs == 2) { 1444 Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass); 1445 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, Reg, MVT::i32); 1446 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 1447 } 1448 break; 1449 case MVT::v16i8: 1450 case MVT::v8i16: 1451 case MVT::v4i32: 1452 case MVT::v2i64: 1453 case MVT::v4f32: 1454 case MVT::v2f64: 1455 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); 1456 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT); 1457 break; 1458 } 1459 NumIntRegs += ObjIntRegs; 1460 NumXMMRegs += ObjXMMRegs; 1461 } 1462 1463 if (ObjSize) { 1464 // XMM arguments have to be aligned on 16-byte boundary. 1465 if (ObjSize == 16) 1466 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1467 // Create the SelectionDAG nodes corresponding to a load from this 1468 // parameter. 1469 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1470 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1471 if (ObjectVT == MVT::i64 && ObjIntRegs) { 1472 SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 1473 DAG.getSrcValue(NULL)); 1474 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 1475 } else 1476 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 1477 DAG.getSrcValue(NULL)); 1478 ArgOffset += ArgIncrement; // Move on to the next argument. 1479 } 1480 1481 ArgValues.push_back(ArgValue); 1482 } 1483 1484 ArgValues.push_back(Root); 1485 1486 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1487 // arguments and the arguments after the retaddr has been pushed are aligned. 1488 if ((ArgOffset & 7) == 0) 1489 ArgOffset += 4; 1490 1491 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1492 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 1493 ReturnAddrIndex = 0; // No return address slot generated yet. 1494 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 1495 BytesCallerReserves = 0; 1496 1497 // Finally, inform the code generator which regs we return values in. 1498 switch (getValueType(MF.getFunction()->getReturnType())) { 1499 default: assert(0 && "Unknown type!"); 1500 case MVT::isVoid: break; 1501 case MVT::i1: 1502 case MVT::i8: 1503 case MVT::i16: 1504 case MVT::i32: 1505 MF.addLiveOut(X86::EAX); 1506 break; 1507 case MVT::i64: 1508 MF.addLiveOut(X86::EAX); 1509 MF.addLiveOut(X86::EDX); 1510 break; 1511 case MVT::f32: 1512 case MVT::f64: 1513 MF.addLiveOut(X86::ST0); 1514 break; 1515 case MVT::v16i8: 1516 case MVT::v8i16: 1517 case MVT::v4i32: 1518 case MVT::v2i64: 1519 case MVT::v4f32: 1520 case MVT::v2f64: 1521 MF.addLiveOut(X86::XMM0); 1522 break; 1523 } 1524 1525 // Return the new list of results. 1526 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 1527 Op.Val->value_end()); 1528 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 1529} 1530 1531SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, 1532 bool isFastCall) { 1533 SDOperand Chain = Op.getOperand(0); 1534 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1535 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1536 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1537 SDOperand Callee = Op.getOperand(4); 1538 MVT::ValueType RetVT= Op.Val->getValueType(0); 1539 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1540 1541 // Count how many bytes are to be pushed on the stack. 1542 unsigned NumBytes = 0; 1543 1544 // Keep track of the number of integer regs passed so far. This can be either 1545 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 1546 // used). 1547 unsigned NumIntRegs = 0; 1548 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing. 1549 1550 static const unsigned GPRArgRegs[][2] = { 1551 { X86::AL, X86::DL }, 1552 { X86::AX, X86::DX }, 1553 { X86::EAX, X86::EDX } 1554 }; 1555 static const unsigned FastCallGPRArgRegs[][2] = { 1556 { X86::CL, X86::DL }, 1557 { X86::CX, X86::DX }, 1558 { X86::ECX, X86::EDX } 1559 }; 1560 static const unsigned XMMArgRegs[] = { 1561 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1562 }; 1563 1564 for (unsigned i = 0; i != NumOps; ++i) { 1565 SDOperand Arg = Op.getOperand(5+2*i); 1566 1567 switch (Arg.getValueType()) { 1568 default: assert(0 && "Unknown value type!"); 1569 case MVT::i8: 1570 case MVT::i16: 1571 case MVT::i32: { 1572 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS); 1573 if (NumIntRegs < MaxNumIntRegs) { 1574 ++NumIntRegs; 1575 break; 1576 } 1577 } // Fall through 1578 case MVT::f32: 1579 NumBytes += 4; 1580 break; 1581 case MVT::f64: 1582 NumBytes += 8; 1583 break; 1584 case MVT::v16i8: 1585 case MVT::v8i16: 1586 case MVT::v4i32: 1587 case MVT::v2i64: 1588 case MVT::v4f32: 1589 case MVT::v2f64: 1590 if (isFastCall) { 1591 assert(0 && "Unknown value type!"); 1592 } else { 1593 if (NumXMMRegs < 4) 1594 NumXMMRegs++; 1595 else { 1596 // XMM arguments have to be aligned on 16-byte boundary. 1597 NumBytes = ((NumBytes + 15) / 16) * 16; 1598 NumBytes += 16; 1599 } 1600 } 1601 break; 1602 } 1603 } 1604 1605 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1606 // arguments and the arguments after the retaddr has been pushed are aligned. 1607 if ((NumBytes & 7) == 0) 1608 NumBytes += 4; 1609 1610 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1611 1612 // Arguments go on the stack in reverse order, as specified by the ABI. 1613 unsigned ArgOffset = 0; 1614 NumIntRegs = 0; 1615 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1616 std::vector<SDOperand> MemOpChains; 1617 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 1618 for (unsigned i = 0; i != NumOps; ++i) { 1619 SDOperand Arg = Op.getOperand(5+2*i); 1620 1621 switch (Arg.getValueType()) { 1622 default: assert(0 && "Unexpected ValueType for argument!"); 1623 case MVT::i8: 1624 case MVT::i16: 1625 case MVT::i32: { 1626 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS); 1627 if (NumIntRegs < MaxNumIntRegs) { 1628 RegsToPass.push_back( 1629 std::make_pair(GPRArgRegs[Arg.getValueType()-MVT::i8][NumIntRegs], 1630 Arg)); 1631 ++NumIntRegs; 1632 break; 1633 } 1634 } // Fall through 1635 case MVT::f32: { 1636 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1637 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1638 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1639 Arg, PtrOff, DAG.getSrcValue(NULL))); 1640 ArgOffset += 4; 1641 break; 1642 } 1643 case MVT::f64: { 1644 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1645 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1646 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1647 Arg, PtrOff, DAG.getSrcValue(NULL))); 1648 ArgOffset += 8; 1649 break; 1650 } 1651 case MVT::v16i8: 1652 case MVT::v8i16: 1653 case MVT::v4i32: 1654 case MVT::v2i64: 1655 case MVT::v4f32: 1656 case MVT::v2f64: 1657 if (isFastCall) { 1658 assert(0 && "Unexpected ValueType for argument!"); 1659 } else { 1660 if (NumXMMRegs < 4) { 1661 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg)); 1662 NumXMMRegs++; 1663 } else { 1664 // XMM arguments have to be aligned on 16-byte boundary. 1665 ArgOffset = ((ArgOffset + 15) / 16) * 16; 1666 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1667 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1668 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1669 Arg, PtrOff, DAG.getSrcValue(NULL))); 1670 ArgOffset += 16; 1671 } 1672 } 1673 break; 1674 } 1675 } 1676 1677 if (!MemOpChains.empty()) 1678 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1679 &MemOpChains[0], MemOpChains.size()); 1680 1681 // Build a sequence of copy-to-reg nodes chained together with token chain 1682 // and flag operands which copy the outgoing args into registers. 1683 SDOperand InFlag; 1684 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1685 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1686 InFlag); 1687 InFlag = Chain.getValue(1); 1688 } 1689 1690 // If the callee is a GlobalAddress node (quite common, every direct call is) 1691 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1692 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1693 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1694 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1695 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1696 1697 std::vector<MVT::ValueType> NodeTys; 1698 NodeTys.push_back(MVT::Other); // Returns a chain 1699 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1700 std::vector<SDOperand> Ops; 1701 Ops.push_back(Chain); 1702 Ops.push_back(Callee); 1703 1704 // Add argument registers to the end of the list so that they are known live 1705 // into the call. 1706 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1707 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1708 RegsToPass[i].second.getValueType())); 1709 1710 if (InFlag.Val) 1711 Ops.push_back(InFlag); 1712 1713 // FIXME: Do not generate X86ISD::TAILCALL for now. 1714 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1715 NodeTys, &Ops[0], Ops.size()); 1716 InFlag = Chain.getValue(1); 1717 1718 NodeTys.clear(); 1719 NodeTys.push_back(MVT::Other); // Returns a chain 1720 if (RetVT != MVT::Other) 1721 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1722 Ops.clear(); 1723 Ops.push_back(Chain); 1724 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1725 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1726 Ops.push_back(InFlag); 1727 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1728 if (RetVT != MVT::Other) 1729 InFlag = Chain.getValue(1); 1730 1731 std::vector<SDOperand> ResultVals; 1732 NodeTys.clear(); 1733 switch (RetVT) { 1734 default: assert(0 && "Unknown value type to return!"); 1735 case MVT::Other: break; 1736 case MVT::i8: 1737 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 1738 ResultVals.push_back(Chain.getValue(0)); 1739 NodeTys.push_back(MVT::i8); 1740 break; 1741 case MVT::i16: 1742 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 1743 ResultVals.push_back(Chain.getValue(0)); 1744 NodeTys.push_back(MVT::i16); 1745 break; 1746 case MVT::i32: 1747 if (Op.Val->getValueType(1) == MVT::i32) { 1748 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1749 ResultVals.push_back(Chain.getValue(0)); 1750 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32, 1751 Chain.getValue(2)).getValue(1); 1752 ResultVals.push_back(Chain.getValue(0)); 1753 NodeTys.push_back(MVT::i32); 1754 } else { 1755 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 1756 ResultVals.push_back(Chain.getValue(0)); 1757 } 1758 NodeTys.push_back(MVT::i32); 1759 break; 1760 case MVT::v16i8: 1761 case MVT::v8i16: 1762 case MVT::v4i32: 1763 case MVT::v2i64: 1764 case MVT::v4f32: 1765 case MVT::v2f64: 1766 if (isFastCall) { 1767 assert(0 && "Unknown value type to return!"); 1768 } else { 1769 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1); 1770 ResultVals.push_back(Chain.getValue(0)); 1771 NodeTys.push_back(RetVT); 1772 } 1773 break; 1774 case MVT::f32: 1775 case MVT::f64: { 1776 std::vector<MVT::ValueType> Tys; 1777 Tys.push_back(MVT::f64); 1778 Tys.push_back(MVT::Other); 1779 Tys.push_back(MVT::Flag); 1780 std::vector<SDOperand> Ops; 1781 Ops.push_back(Chain); 1782 Ops.push_back(InFlag); 1783 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 1784 &Ops[0], Ops.size()); 1785 Chain = RetVal.getValue(1); 1786 InFlag = RetVal.getValue(2); 1787 if (X86ScalarSSE) { 1788 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 1789 // shouldn't be necessary except that RFP cannot be live across 1790 // multiple blocks. When stackifier is fixed, they can be uncoupled. 1791 MachineFunction &MF = DAG.getMachineFunction(); 1792 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 1793 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1794 Tys.clear(); 1795 Tys.push_back(MVT::Other); 1796 Ops.clear(); 1797 Ops.push_back(Chain); 1798 Ops.push_back(RetVal); 1799 Ops.push_back(StackSlot); 1800 Ops.push_back(DAG.getValueType(RetVT)); 1801 Ops.push_back(InFlag); 1802 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 1803 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, 1804 DAG.getSrcValue(NULL)); 1805 Chain = RetVal.getValue(1); 1806 } 1807 1808 if (RetVT == MVT::f32 && !X86ScalarSSE) 1809 // FIXME: we would really like to remember that this FP_ROUND 1810 // operation is okay to eliminate if we allow excess FP precision. 1811 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 1812 ResultVals.push_back(RetVal); 1813 NodeTys.push_back(RetVT); 1814 break; 1815 } 1816 } 1817 1818 1819 // If the function returns void, just return the chain. 1820 if (ResultVals.empty()) 1821 return Chain; 1822 1823 // Otherwise, merge everything together with a MERGE_VALUES node. 1824 NodeTys.push_back(MVT::Other); 1825 ResultVals.push_back(Chain); 1826 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1827 &ResultVals[0], ResultVals.size()); 1828 return Res.getValue(Op.ResNo); 1829} 1830 1831//===----------------------------------------------------------------------===// 1832// StdCall Calling Convention implementation 1833//===----------------------------------------------------------------------===// 1834// StdCall calling convention seems to be standard for many Windows' API 1835// routines and around. It differs from C calling convention just a little: 1836// callee should clean up the stack, not caller. Symbols should be also 1837// decorated in some fancy way :) It doesn't support any vector arguments. 1838 1839/// HowToPassStdCallCCArgument - Returns how an formal argument of the specified 1840/// type should be passed. Returns the size of the stack slot 1841static void 1842HowToPassStdCallCCArgument(MVT::ValueType ObjectVT, unsigned &ObjSize) { 1843 switch (ObjectVT) { 1844 default: assert(0 && "Unhandled argument type!"); 1845 case MVT::i8: ObjSize = 1; break; 1846 case MVT::i16: ObjSize = 2; break; 1847 case MVT::i32: ObjSize = 4; break; 1848 case MVT::i64: ObjSize = 8; break; 1849 case MVT::f32: ObjSize = 4; break; 1850 case MVT::f64: ObjSize = 8; break; 1851 } 1852} 1853 1854SDOperand X86TargetLowering::LowerStdCallCCArguments(SDOperand Op, 1855 SelectionDAG &DAG) { 1856 unsigned NumArgs = Op.Val->getNumValues() - 1; 1857 MachineFunction &MF = DAG.getMachineFunction(); 1858 MachineFrameInfo *MFI = MF.getFrameInfo(); 1859 SDOperand Root = Op.getOperand(0); 1860 std::vector<SDOperand> ArgValues; 1861 1862 // Add DAG nodes to load the arguments... On entry to a function on the X86, 1863 // the stack frame looks like this: 1864 // 1865 // [ESP] -- return address 1866 // [ESP + 4] -- first argument (leftmost lexically) 1867 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size 1868 // ... 1869 // 1870 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 1871 for (unsigned i = 0; i < NumArgs; ++i) { 1872 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 1873 unsigned ArgIncrement = 4; 1874 unsigned ObjSize = 0; 1875 HowToPassStdCallCCArgument(ObjectVT, ObjSize); 1876 if (ObjSize > 4) 1877 ArgIncrement = ObjSize; 1878 1879 SDOperand ArgValue; 1880 // Create the frame index object for this incoming parameter... 1881 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1882 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1883 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 1884 DAG.getSrcValue(NULL)); 1885 ArgValues.push_back(ArgValue); 1886 ArgOffset += ArgIncrement; // Move on to the next argument... 1887 } 1888 1889 ArgValues.push_back(Root); 1890 1891 // If the function takes variable number of arguments, make a frame index for 1892 // the start of the first vararg value... for expansion of llvm.va_start. 1893 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1894 if (isVarArg) { 1895 BytesToPopOnReturn = 0; // Callee pops nothing. 1896 BytesCallerReserves = ArgOffset; 1897 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 1898 } else { 1899 BytesToPopOnReturn = ArgOffset; // Callee pops everything.. 1900 BytesCallerReserves = 0; 1901 } 1902 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 1903 ReturnAddrIndex = 0; // No return address slot generated yet. 1904 1905 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 1906 1907 // Return the new list of results. 1908 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 1909 Op.Val->value_end()); 1910 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 1911} 1912 1913 1914SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op, 1915 SelectionDAG &DAG) { 1916 SDOperand Chain = Op.getOperand(0); 1917 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1918 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1919 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1920 SDOperand Callee = Op.getOperand(4); 1921 MVT::ValueType RetVT= Op.Val->getValueType(0); 1922 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1923 1924 // Count how many bytes are to be pushed on the stack. 1925 unsigned NumBytes = 0; 1926 for (unsigned i = 0; i != NumOps; ++i) { 1927 SDOperand Arg = Op.getOperand(5+2*i); 1928 1929 switch (Arg.getValueType()) { 1930 default: assert(0 && "Unexpected ValueType for argument!"); 1931 case MVT::i8: 1932 case MVT::i16: 1933 case MVT::i32: 1934 case MVT::f32: 1935 NumBytes += 4; 1936 break; 1937 case MVT::i64: 1938 case MVT::f64: 1939 NumBytes += 8; 1940 break; 1941 } 1942 } 1943 1944 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1945 1946 // Arguments go on the stack in reverse order, as specified by the ABI. 1947 unsigned ArgOffset = 0; 1948 std::vector<SDOperand> MemOpChains; 1949 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy()); 1950 for (unsigned i = 0; i != NumOps; ++i) { 1951 SDOperand Arg = Op.getOperand(5+2*i); 1952 1953 switch (Arg.getValueType()) { 1954 default: assert(0 && "Unexpected ValueType for argument!"); 1955 case MVT::i8: 1956 case MVT::i16: { 1957 // Promote the integer to 32 bits. If the input type is signed use a 1958 // sign extend, otherwise use a zero extend. 1959 unsigned ExtOp = 1960 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue() ? 1961 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1962 Arg = DAG.getNode(ExtOp, MVT::i32, Arg); 1963 } 1964 // Fallthrough 1965 1966 case MVT::i32: 1967 case MVT::f32: { 1968 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1969 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1970 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1971 Arg, PtrOff, DAG.getSrcValue(NULL))); 1972 ArgOffset += 4; 1973 break; 1974 } 1975 case MVT::i64: 1976 case MVT::f64: { 1977 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1978 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1979 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1980 Arg, PtrOff, DAG.getSrcValue(NULL))); 1981 ArgOffset += 8; 1982 break; 1983 } 1984 } 1985 } 1986 1987 if (!MemOpChains.empty()) 1988 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1989 &MemOpChains[0], MemOpChains.size()); 1990 1991 // If the callee is a GlobalAddress node (quite common, every direct call is) 1992 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1993 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1994 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1995 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1996 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1997 1998 std::vector<MVT::ValueType> NodeTys; 1999 NodeTys.push_back(MVT::Other); // Returns a chain 2000 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2001 std::vector<SDOperand> Ops; 2002 Ops.push_back(Chain); 2003 Ops.push_back(Callee); 2004 2005 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 2006 NodeTys, &Ops[0], Ops.size()); 2007 SDOperand InFlag = Chain.getValue(1); 2008 2009 // Create the CALLSEQ_END node. 2010 unsigned NumBytesForCalleeToPush; 2011 2012 if (isVarArg) { 2013 NumBytesForCalleeToPush = 0; 2014 } else { 2015 NumBytesForCalleeToPush = NumBytes; 2016 } 2017 2018 NodeTys.clear(); 2019 NodeTys.push_back(MVT::Other); // Returns a chain 2020 if (RetVT != MVT::Other) 2021 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2022 Ops.clear(); 2023 Ops.push_back(Chain); 2024 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 2025 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy())); 2026 Ops.push_back(InFlag); 2027 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 2028 if (RetVT != MVT::Other) 2029 InFlag = Chain.getValue(1); 2030 2031 std::vector<SDOperand> ResultVals; 2032 NodeTys.clear(); 2033 switch (RetVT) { 2034 default: assert(0 && "Unknown value type to return!"); 2035 case MVT::Other: break; 2036 case MVT::i8: 2037 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1); 2038 ResultVals.push_back(Chain.getValue(0)); 2039 NodeTys.push_back(MVT::i8); 2040 break; 2041 case MVT::i16: 2042 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1); 2043 ResultVals.push_back(Chain.getValue(0)); 2044 NodeTys.push_back(MVT::i16); 2045 break; 2046 case MVT::i32: 2047 if (Op.Val->getValueType(1) == MVT::i32) { 2048 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 2049 ResultVals.push_back(Chain.getValue(0)); 2050 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32, 2051 Chain.getValue(2)).getValue(1); 2052 ResultVals.push_back(Chain.getValue(0)); 2053 NodeTys.push_back(MVT::i32); 2054 } else { 2055 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1); 2056 ResultVals.push_back(Chain.getValue(0)); 2057 } 2058 NodeTys.push_back(MVT::i32); 2059 break; 2060 case MVT::f32: 2061 case MVT::f64: { 2062 std::vector<MVT::ValueType> Tys; 2063 Tys.push_back(MVT::f64); 2064 Tys.push_back(MVT::Other); 2065 Tys.push_back(MVT::Flag); 2066 std::vector<SDOperand> Ops; 2067 Ops.push_back(Chain); 2068 Ops.push_back(InFlag); 2069 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 2070 &Ops[0], Ops.size()); 2071 Chain = RetVal.getValue(1); 2072 InFlag = RetVal.getValue(2); 2073 if (X86ScalarSSE) { 2074 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 2075 // shouldn't be necessary except that RFP cannot be live across 2076 // multiple blocks. When stackifier is fixed, they can be uncoupled. 2077 MachineFunction &MF = DAG.getMachineFunction(); 2078 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 2079 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 2080 Tys.clear(); 2081 Tys.push_back(MVT::Other); 2082 Ops.clear(); 2083 Ops.push_back(Chain); 2084 Ops.push_back(RetVal); 2085 Ops.push_back(StackSlot); 2086 Ops.push_back(DAG.getValueType(RetVT)); 2087 Ops.push_back(InFlag); 2088 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 2089 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, 2090 DAG.getSrcValue(NULL)); 2091 Chain = RetVal.getValue(1); 2092 } 2093 2094 if (RetVT == MVT::f32 && !X86ScalarSSE) 2095 // FIXME: we would really like to remember that this FP_ROUND 2096 // operation is okay to eliminate if we allow excess FP precision. 2097 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 2098 ResultVals.push_back(RetVal); 2099 NodeTys.push_back(RetVT); 2100 break; 2101 } 2102 } 2103 2104 // If the function returns void, just return the chain. 2105 if (ResultVals.empty()) 2106 return Chain; 2107 2108 // Otherwise, merge everything together with a MERGE_VALUES node. 2109 NodeTys.push_back(MVT::Other); 2110 ResultVals.push_back(Chain); 2111 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 2112 &ResultVals[0], ResultVals.size()); 2113 return Res.getValue(Op.ResNo); 2114} 2115 2116//===----------------------------------------------------------------------===// 2117// FastCall Calling Convention implementation 2118//===----------------------------------------------------------------------===// 2119// 2120// The X86 'fastcall' calling convention passes up to two integer arguments in 2121// registers (an appropriate portion of ECX/EDX), passes arguments in C order, 2122// and requires that the callee pop its arguments off the stack (allowing proper 2123// tail calls), and has the same return value conventions as C calling convs. 2124// 2125// This calling convention always arranges for the callee pop value to be 8n+4 2126// bytes, which is needed for tail recursion elimination and stack alignment 2127// reasons. 2128// 2129 2130/// HowToPassFastCallCCArgument - Returns how an formal argument of the 2131/// specified type should be passed. If it is through stack, returns the size of 2132/// the stack slot; if it is through integer register, returns the number of 2133/// integer registers are needed. 2134static void 2135HowToPassFastCallCCArgument(MVT::ValueType ObjectVT, 2136 unsigned NumIntRegs, 2137 unsigned &ObjSize, 2138 unsigned &ObjIntRegs) 2139{ 2140 ObjSize = 0; 2141 ObjIntRegs = 0; 2142 2143 switch (ObjectVT) { 2144 default: assert(0 && "Unhandled argument type!"); 2145 case MVT::i8: 2146 if (NumIntRegs < 2) 2147 ObjIntRegs = 1; 2148 else 2149 ObjSize = 1; 2150 break; 2151 case MVT::i16: 2152 if (NumIntRegs < 2) 2153 ObjIntRegs = 1; 2154 else 2155 ObjSize = 2; 2156 break; 2157 case MVT::i32: 2158 if (NumIntRegs < 2) 2159 ObjIntRegs = 1; 2160 else 2161 ObjSize = 4; 2162 break; 2163 case MVT::i64: 2164 if (NumIntRegs+2 <= 2) { 2165 ObjIntRegs = 2; 2166 } else if (NumIntRegs+1 <= 2) { 2167 ObjIntRegs = 1; 2168 ObjSize = 4; 2169 } else 2170 ObjSize = 8; 2171 case MVT::f32: 2172 ObjSize = 4; 2173 break; 2174 case MVT::f64: 2175 ObjSize = 8; 2176 break; 2177 } 2178} 2179 2180SDOperand 2181X86TargetLowering::LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG) { 2182 unsigned NumArgs = Op.Val->getNumValues()-1; 2183 MachineFunction &MF = DAG.getMachineFunction(); 2184 MachineFrameInfo *MFI = MF.getFrameInfo(); 2185 SDOperand Root = Op.getOperand(0); 2186 std::vector<SDOperand> ArgValues; 2187 2188 // Add DAG nodes to load the arguments... On entry to a function the stack 2189 // frame looks like this: 2190 // 2191 // [ESP] -- return address 2192 // [ESP + 4] -- first nonreg argument (leftmost lexically) 2193 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size 2194 // ... 2195 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 2196 2197 // Keep track of the number of integer regs passed so far. This can be either 2198 // 0 (neither ECX or EDX used), 1 (ECX is used) or 2 (ECX and EDX are both 2199 // used). 2200 unsigned NumIntRegs = 0; 2201 2202 for (unsigned i = 0; i < NumArgs; ++i) { 2203 MVT::ValueType ObjectVT = Op.getValue(i).getValueType(); 2204 unsigned ArgIncrement = 4; 2205 unsigned ObjSize = 0; 2206 unsigned ObjIntRegs = 0; 2207 2208 HowToPassFastCallCCArgument(ObjectVT, NumIntRegs, ObjSize, ObjIntRegs); 2209 if (ObjSize > 4) 2210 ArgIncrement = ObjSize; 2211 2212 unsigned Reg = 0; 2213 SDOperand ArgValue; 2214 if (ObjIntRegs) { 2215 switch (ObjectVT) { 2216 default: assert(0 && "Unhandled argument type!"); 2217 case MVT::i8: 2218 Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::CL, 2219 X86::GR8RegisterClass); 2220 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i8); 2221 break; 2222 case MVT::i16: 2223 Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::CX, 2224 X86::GR16RegisterClass); 2225 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i16); 2226 break; 2227 case MVT::i32: 2228 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::ECX, 2229 X86::GR32RegisterClass); 2230 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32); 2231 break; 2232 case MVT::i64: 2233 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::ECX, 2234 X86::GR32RegisterClass); 2235 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32); 2236 if (ObjIntRegs == 2) { 2237 Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass); 2238 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, Reg, MVT::i32); 2239 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 2240 } 2241 break; 2242 } 2243 2244 NumIntRegs += ObjIntRegs; 2245 } 2246 2247 if (ObjSize) { 2248 // Create the SelectionDAG nodes corresponding to a load from this 2249 // parameter. 2250 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 2251 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 2252 if (ObjectVT == MVT::i64 && ObjIntRegs) { 2253 SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 2254 DAG.getSrcValue(NULL)); 2255 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 2256 } else 2257 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, 2258 DAG.getSrcValue(NULL)); 2259 ArgOffset += ArgIncrement; // Move on to the next argument. 2260 } 2261 2262 ArgValues.push_back(ArgValue); 2263 } 2264 2265 ArgValues.push_back(Root); 2266 2267 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 2268 // arguments and the arguments after the retaddr has been pushed are aligned. 2269 if ((ArgOffset & 7) == 0) 2270 ArgOffset += 4; 2271 2272 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 2273 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 2274 ReturnAddrIndex = 0; // No return address slot generated yet. 2275 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 2276 BytesCallerReserves = 0; 2277 2278 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 2279 2280 // Finally, inform the code generator which regs we return values in. 2281 switch (getValueType(MF.getFunction()->getReturnType())) { 2282 default: assert(0 && "Unknown type!"); 2283 case MVT::isVoid: break; 2284 case MVT::i1: 2285 case MVT::i8: 2286 case MVT::i16: 2287 case MVT::i32: 2288 MF.addLiveOut(X86::ECX); 2289 break; 2290 case MVT::i64: 2291 MF.addLiveOut(X86::ECX); 2292 MF.addLiveOut(X86::EDX); 2293 break; 2294 case MVT::f32: 2295 case MVT::f64: 2296 MF.addLiveOut(X86::ST0); 2297 break; 2298 } 2299 2300 // Return the new list of results. 2301 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(), 2302 Op.Val->value_end()); 2303 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size()); 2304} 2305 2306SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2307 if (ReturnAddrIndex == 0) { 2308 // Set up a frame object for the return address. 2309 MachineFunction &MF = DAG.getMachineFunction(); 2310 if (Subtarget->is64Bit()) 2311 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); 2312 else 2313 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 2314 } 2315 2316 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2317} 2318 2319 2320 2321std::pair<SDOperand, SDOperand> X86TargetLowering:: 2322LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 2323 SelectionDAG &DAG) { 2324 SDOperand Result; 2325 if (Depth) // Depths > 0 not supported yet! 2326 Result = DAG.getConstant(0, getPointerTy()); 2327 else { 2328 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 2329 if (!isFrameAddress) 2330 // Just load the return address 2331 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, 2332 DAG.getSrcValue(NULL)); 2333 else 2334 Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 2335 DAG.getConstant(4, getPointerTy())); 2336 } 2337 return std::make_pair(Result, Chain); 2338} 2339 2340/// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode 2341/// which corresponds to the condition code. 2342static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) { 2343 switch (X86CC) { 2344 default: assert(0 && "Unknown X86 conditional code!"); 2345 case X86ISD::COND_A: return X86::JA; 2346 case X86ISD::COND_AE: return X86::JAE; 2347 case X86ISD::COND_B: return X86::JB; 2348 case X86ISD::COND_BE: return X86::JBE; 2349 case X86ISD::COND_E: return X86::JE; 2350 case X86ISD::COND_G: return X86::JG; 2351 case X86ISD::COND_GE: return X86::JGE; 2352 case X86ISD::COND_L: return X86::JL; 2353 case X86ISD::COND_LE: return X86::JLE; 2354 case X86ISD::COND_NE: return X86::JNE; 2355 case X86ISD::COND_NO: return X86::JNO; 2356 case X86ISD::COND_NP: return X86::JNP; 2357 case X86ISD::COND_NS: return X86::JNS; 2358 case X86ISD::COND_O: return X86::JO; 2359 case X86ISD::COND_P: return X86::JP; 2360 case X86ISD::COND_S: return X86::JS; 2361 } 2362} 2363 2364/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 2365/// specific condition code. It returns a false if it cannot do a direct 2366/// translation. X86CC is the translated CondCode. LHS/RHS are modified as 2367/// needed. 2368static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2369 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, 2370 SelectionDAG &DAG) { 2371 X86CC = X86ISD::COND_INVALID; 2372 if (!isFP) { 2373 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2374 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2375 // X > -1 -> X == 0, jump !sign. 2376 RHS = DAG.getConstant(0, RHS.getValueType()); 2377 X86CC = X86ISD::COND_NS; 2378 return true; 2379 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2380 // X < 0 -> X == 0, jump on sign. 2381 X86CC = X86ISD::COND_S; 2382 return true; 2383 } 2384 } 2385 2386 switch (SetCCOpcode) { 2387 default: break; 2388 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 2389 case ISD::SETGT: X86CC = X86ISD::COND_G; break; 2390 case ISD::SETGE: X86CC = X86ISD::COND_GE; break; 2391 case ISD::SETLT: X86CC = X86ISD::COND_L; break; 2392 case ISD::SETLE: X86CC = X86ISD::COND_LE; break; 2393 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 2394 case ISD::SETULT: X86CC = X86ISD::COND_B; break; 2395 case ISD::SETUGT: X86CC = X86ISD::COND_A; break; 2396 case ISD::SETULE: X86CC = X86ISD::COND_BE; break; 2397 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break; 2398 } 2399 } else { 2400 // On a floating point condition, the flags are set as follows: 2401 // ZF PF CF op 2402 // 0 | 0 | 0 | X > Y 2403 // 0 | 0 | 1 | X < Y 2404 // 1 | 0 | 0 | X == Y 2405 // 1 | 1 | 1 | unordered 2406 bool Flip = false; 2407 switch (SetCCOpcode) { 2408 default: break; 2409 case ISD::SETUEQ: 2410 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 2411 case ISD::SETOLT: Flip = true; // Fallthrough 2412 case ISD::SETOGT: 2413 case ISD::SETGT: X86CC = X86ISD::COND_A; break; 2414 case ISD::SETOLE: Flip = true; // Fallthrough 2415 case ISD::SETOGE: 2416 case ISD::SETGE: X86CC = X86ISD::COND_AE; break; 2417 case ISD::SETUGT: Flip = true; // Fallthrough 2418 case ISD::SETULT: 2419 case ISD::SETLT: X86CC = X86ISD::COND_B; break; 2420 case ISD::SETUGE: Flip = true; // Fallthrough 2421 case ISD::SETULE: 2422 case ISD::SETLE: X86CC = X86ISD::COND_BE; break; 2423 case ISD::SETONE: 2424 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 2425 case ISD::SETUO: X86CC = X86ISD::COND_P; break; 2426 case ISD::SETO: X86CC = X86ISD::COND_NP; break; 2427 } 2428 if (Flip) 2429 std::swap(LHS, RHS); 2430 } 2431 2432 return X86CC != X86ISD::COND_INVALID; 2433} 2434 2435/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2436/// code. Current x86 isa includes the following FP cmov instructions: 2437/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2438static bool hasFPCMov(unsigned X86CC) { 2439 switch (X86CC) { 2440 default: 2441 return false; 2442 case X86ISD::COND_B: 2443 case X86ISD::COND_BE: 2444 case X86ISD::COND_E: 2445 case X86ISD::COND_P: 2446 case X86ISD::COND_A: 2447 case X86ISD::COND_AE: 2448 case X86ISD::COND_NE: 2449 case X86ISD::COND_NP: 2450 return true; 2451 } 2452} 2453 2454/// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra 2455/// load. For Darwin, external and weak symbols are indirect, loading the value 2456/// at address GV rather then the value of GV itself. This means that the 2457/// GlobalAddress must be in the base or index register of the address, not the 2458/// GV offset field. 2459static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) { 2460 return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 2461 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())); 2462} 2463 2464/// WindowsGVRequiresExtraLoad - true if accessing the GV requires an extra 2465/// load. For Windows, dllimported symbols are indirect, loading the value at 2466/// address GV rather then the value of GV itself. This means that the 2467/// GlobalAddress must be in the base or index register of the address, not the 2468/// GV offset field. 2469static bool WindowsGVRequiresExtraLoad(GlobalValue *GV) { 2470 return (GV->hasDLLImportLinkage()); 2471} 2472 2473/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2474/// true if Op is undef or if its value falls within the specified range (L, H]. 2475static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { 2476 if (Op.getOpcode() == ISD::UNDEF) 2477 return true; 2478 2479 unsigned Val = cast<ConstantSDNode>(Op)->getValue(); 2480 return (Val >= Low && Val < Hi); 2481} 2482 2483/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2484/// true if Op is undef or if its value equal to the specified value. 2485static bool isUndefOrEqual(SDOperand Op, unsigned Val) { 2486 if (Op.getOpcode() == ISD::UNDEF) 2487 return true; 2488 return cast<ConstantSDNode>(Op)->getValue() == Val; 2489} 2490 2491/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2492/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2493bool X86::isPSHUFDMask(SDNode *N) { 2494 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2495 2496 if (N->getNumOperands() != 4) 2497 return false; 2498 2499 // Check if the value doesn't reference the second vector. 2500 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2501 SDOperand Arg = N->getOperand(i); 2502 if (Arg.getOpcode() == ISD::UNDEF) continue; 2503 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2504 if (cast<ConstantSDNode>(Arg)->getValue() >= 4) 2505 return false; 2506 } 2507 2508 return true; 2509} 2510 2511/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2512/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2513bool X86::isPSHUFHWMask(SDNode *N) { 2514 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2515 2516 if (N->getNumOperands() != 8) 2517 return false; 2518 2519 // Lower quadword copied in order. 2520 for (unsigned i = 0; i != 4; ++i) { 2521 SDOperand Arg = N->getOperand(i); 2522 if (Arg.getOpcode() == ISD::UNDEF) continue; 2523 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2524 if (cast<ConstantSDNode>(Arg)->getValue() != i) 2525 return false; 2526 } 2527 2528 // Upper quadword shuffled. 2529 for (unsigned i = 4; i != 8; ++i) { 2530 SDOperand Arg = N->getOperand(i); 2531 if (Arg.getOpcode() == ISD::UNDEF) continue; 2532 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2533 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2534 if (Val < 4 || Val > 7) 2535 return false; 2536 } 2537 2538 return true; 2539} 2540 2541/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2542/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2543bool X86::isPSHUFLWMask(SDNode *N) { 2544 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2545 2546 if (N->getNumOperands() != 8) 2547 return false; 2548 2549 // Upper quadword copied in order. 2550 for (unsigned i = 4; i != 8; ++i) 2551 if (!isUndefOrEqual(N->getOperand(i), i)) 2552 return false; 2553 2554 // Lower quadword shuffled. 2555 for (unsigned i = 0; i != 4; ++i) 2556 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2557 return false; 2558 2559 return true; 2560} 2561 2562/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2563/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2564static bool isSHUFPMask(std::vector<SDOperand> &N) { 2565 unsigned NumElems = N.size(); 2566 if (NumElems != 2 && NumElems != 4) return false; 2567 2568 unsigned Half = NumElems / 2; 2569 for (unsigned i = 0; i < Half; ++i) 2570 if (!isUndefOrInRange(N[i], 0, NumElems)) 2571 return false; 2572 for (unsigned i = Half; i < NumElems; ++i) 2573 if (!isUndefOrInRange(N[i], NumElems, NumElems*2)) 2574 return false; 2575 2576 return true; 2577} 2578 2579bool X86::isSHUFPMask(SDNode *N) { 2580 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2581 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2582 return ::isSHUFPMask(Ops); 2583} 2584 2585/// isCommutedSHUFP - Returns true if the shuffle mask is except 2586/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2587/// half elements to come from vector 1 (which would equal the dest.) and 2588/// the upper half to come from vector 2. 2589static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) { 2590 unsigned NumElems = Ops.size(); 2591 if (NumElems != 2 && NumElems != 4) return false; 2592 2593 unsigned Half = NumElems / 2; 2594 for (unsigned i = 0; i < Half; ++i) 2595 if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2)) 2596 return false; 2597 for (unsigned i = Half; i < NumElems; ++i) 2598 if (!isUndefOrInRange(Ops[i], 0, NumElems)) 2599 return false; 2600 return true; 2601} 2602 2603static bool isCommutedSHUFP(SDNode *N) { 2604 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2605 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2606 return isCommutedSHUFP(Ops); 2607} 2608 2609/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2610/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2611bool X86::isMOVHLPSMask(SDNode *N) { 2612 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2613 2614 if (N->getNumOperands() != 4) 2615 return false; 2616 2617 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2618 return isUndefOrEqual(N->getOperand(0), 6) && 2619 isUndefOrEqual(N->getOperand(1), 7) && 2620 isUndefOrEqual(N->getOperand(2), 2) && 2621 isUndefOrEqual(N->getOperand(3), 3); 2622} 2623 2624/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2625/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2626bool X86::isMOVLPMask(SDNode *N) { 2627 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2628 2629 unsigned NumElems = N->getNumOperands(); 2630 if (NumElems != 2 && NumElems != 4) 2631 return false; 2632 2633 for (unsigned i = 0; i < NumElems/2; ++i) 2634 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2635 return false; 2636 2637 for (unsigned i = NumElems/2; i < NumElems; ++i) 2638 if (!isUndefOrEqual(N->getOperand(i), i)) 2639 return false; 2640 2641 return true; 2642} 2643 2644/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2645/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2646/// and MOVLHPS. 2647bool X86::isMOVHPMask(SDNode *N) { 2648 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2649 2650 unsigned NumElems = N->getNumOperands(); 2651 if (NumElems != 2 && NumElems != 4) 2652 return false; 2653 2654 for (unsigned i = 0; i < NumElems/2; ++i) 2655 if (!isUndefOrEqual(N->getOperand(i), i)) 2656 return false; 2657 2658 for (unsigned i = 0; i < NumElems/2; ++i) { 2659 SDOperand Arg = N->getOperand(i + NumElems/2); 2660 if (!isUndefOrEqual(Arg, i + NumElems)) 2661 return false; 2662 } 2663 2664 return true; 2665} 2666 2667/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2668/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2669bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) { 2670 unsigned NumElems = N.size(); 2671 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2672 return false; 2673 2674 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2675 SDOperand BitI = N[i]; 2676 SDOperand BitI1 = N[i+1]; 2677 if (!isUndefOrEqual(BitI, j)) 2678 return false; 2679 if (V2IsSplat) { 2680 if (isUndefOrEqual(BitI1, NumElems)) 2681 return false; 2682 } else { 2683 if (!isUndefOrEqual(BitI1, j + NumElems)) 2684 return false; 2685 } 2686 } 2687 2688 return true; 2689} 2690 2691bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2692 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2693 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2694 return ::isUNPCKLMask(Ops, V2IsSplat); 2695} 2696 2697/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2698/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2699bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) { 2700 unsigned NumElems = N.size(); 2701 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2702 return false; 2703 2704 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2705 SDOperand BitI = N[i]; 2706 SDOperand BitI1 = N[i+1]; 2707 if (!isUndefOrEqual(BitI, j + NumElems/2)) 2708 return false; 2709 if (V2IsSplat) { 2710 if (isUndefOrEqual(BitI1, NumElems)) 2711 return false; 2712 } else { 2713 if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems)) 2714 return false; 2715 } 2716 } 2717 2718 return true; 2719} 2720 2721bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2722 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2723 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2724 return ::isUNPCKHMask(Ops, V2IsSplat); 2725} 2726 2727/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2728/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2729/// <0, 0, 1, 1> 2730bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2731 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2732 2733 unsigned NumElems = N->getNumOperands(); 2734 if (NumElems != 4 && NumElems != 8 && NumElems != 16) 2735 return false; 2736 2737 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2738 SDOperand BitI = N->getOperand(i); 2739 SDOperand BitI1 = N->getOperand(i+1); 2740 2741 if (!isUndefOrEqual(BitI, j)) 2742 return false; 2743 if (!isUndefOrEqual(BitI1, j)) 2744 return false; 2745 } 2746 2747 return true; 2748} 2749 2750/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2751/// specifies a shuffle of elements that is suitable for input to MOVSS, 2752/// MOVSD, and MOVD, i.e. setting the lowest element. 2753static bool isMOVLMask(std::vector<SDOperand> &N) { 2754 unsigned NumElems = N.size(); 2755 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2756 return false; 2757 2758 if (!isUndefOrEqual(N[0], NumElems)) 2759 return false; 2760 2761 for (unsigned i = 1; i < NumElems; ++i) { 2762 SDOperand Arg = N[i]; 2763 if (!isUndefOrEqual(Arg, i)) 2764 return false; 2765 } 2766 2767 return true; 2768} 2769 2770bool X86::isMOVLMask(SDNode *N) { 2771 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2772 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2773 return ::isMOVLMask(Ops); 2774} 2775 2776/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2777/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2778/// element of vector 2 and the other elements to come from vector 1 in order. 2779static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false, 2780 bool V2IsUndef = false) { 2781 unsigned NumElems = Ops.size(); 2782 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2783 return false; 2784 2785 if (!isUndefOrEqual(Ops[0], 0)) 2786 return false; 2787 2788 for (unsigned i = 1; i < NumElems; ++i) { 2789 SDOperand Arg = Ops[i]; 2790 if (!(isUndefOrEqual(Arg, i+NumElems) || 2791 (V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) || 2792 (V2IsSplat && isUndefOrEqual(Arg, NumElems)))) 2793 return false; 2794 } 2795 2796 return true; 2797} 2798 2799static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2800 bool V2IsUndef = false) { 2801 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2802 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 2803 return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef); 2804} 2805 2806/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2807/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2808bool X86::isMOVSHDUPMask(SDNode *N) { 2809 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2810 2811 if (N->getNumOperands() != 4) 2812 return false; 2813 2814 // Expect 1, 1, 3, 3 2815 for (unsigned i = 0; i < 2; ++i) { 2816 SDOperand Arg = N->getOperand(i); 2817 if (Arg.getOpcode() == ISD::UNDEF) continue; 2818 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2819 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2820 if (Val != 1) return false; 2821 } 2822 2823 bool HasHi = false; 2824 for (unsigned i = 2; i < 4; ++i) { 2825 SDOperand Arg = N->getOperand(i); 2826 if (Arg.getOpcode() == ISD::UNDEF) continue; 2827 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2828 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2829 if (Val != 3) return false; 2830 HasHi = true; 2831 } 2832 2833 // Don't use movshdup if it can be done with a shufps. 2834 return HasHi; 2835} 2836 2837/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2838/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2839bool X86::isMOVSLDUPMask(SDNode *N) { 2840 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2841 2842 if (N->getNumOperands() != 4) 2843 return false; 2844 2845 // Expect 0, 0, 2, 2 2846 for (unsigned i = 0; i < 2; ++i) { 2847 SDOperand Arg = N->getOperand(i); 2848 if (Arg.getOpcode() == ISD::UNDEF) continue; 2849 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2850 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2851 if (Val != 0) return false; 2852 } 2853 2854 bool HasHi = false; 2855 for (unsigned i = 2; i < 4; ++i) { 2856 SDOperand Arg = N->getOperand(i); 2857 if (Arg.getOpcode() == ISD::UNDEF) continue; 2858 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2859 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2860 if (Val != 2) return false; 2861 HasHi = true; 2862 } 2863 2864 // Don't use movshdup if it can be done with a shufps. 2865 return HasHi; 2866} 2867 2868/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2869/// a splat of a single element. 2870static bool isSplatMask(SDNode *N) { 2871 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2872 2873 // This is a splat operation if each element of the permute is the same, and 2874 // if the value doesn't reference the second vector. 2875 unsigned NumElems = N->getNumOperands(); 2876 SDOperand ElementBase; 2877 unsigned i = 0; 2878 for (; i != NumElems; ++i) { 2879 SDOperand Elt = N->getOperand(i); 2880 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) { 2881 ElementBase = Elt; 2882 break; 2883 } 2884 } 2885 2886 if (!ElementBase.Val) 2887 return false; 2888 2889 for (; i != NumElems; ++i) { 2890 SDOperand Arg = N->getOperand(i); 2891 if (Arg.getOpcode() == ISD::UNDEF) continue; 2892 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2893 if (Arg != ElementBase) return false; 2894 } 2895 2896 // Make sure it is a splat of the first vector operand. 2897 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; 2898} 2899 2900/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2901/// a splat of a single element and it's a 2 or 4 element mask. 2902bool X86::isSplatMask(SDNode *N) { 2903 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2904 2905 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2906 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2907 return false; 2908 return ::isSplatMask(N); 2909} 2910 2911/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2912/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2913/// instructions. 2914unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2915 unsigned NumOperands = N->getNumOperands(); 2916 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2917 unsigned Mask = 0; 2918 for (unsigned i = 0; i < NumOperands; ++i) { 2919 unsigned Val = 0; 2920 SDOperand Arg = N->getOperand(NumOperands-i-1); 2921 if (Arg.getOpcode() != ISD::UNDEF) 2922 Val = cast<ConstantSDNode>(Arg)->getValue(); 2923 if (Val >= NumOperands) Val -= NumOperands; 2924 Mask |= Val; 2925 if (i != NumOperands - 1) 2926 Mask <<= Shift; 2927 } 2928 2929 return Mask; 2930} 2931 2932/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2933/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2934/// instructions. 2935unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2936 unsigned Mask = 0; 2937 // 8 nodes, but we only care about the last 4. 2938 for (unsigned i = 7; i >= 4; --i) { 2939 unsigned Val = 0; 2940 SDOperand Arg = N->getOperand(i); 2941 if (Arg.getOpcode() != ISD::UNDEF) 2942 Val = cast<ConstantSDNode>(Arg)->getValue(); 2943 Mask |= (Val - 4); 2944 if (i != 4) 2945 Mask <<= 2; 2946 } 2947 2948 return Mask; 2949} 2950 2951/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2952/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2953/// instructions. 2954unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2955 unsigned Mask = 0; 2956 // 8 nodes, but we only care about the first 4. 2957 for (int i = 3; i >= 0; --i) { 2958 unsigned Val = 0; 2959 SDOperand Arg = N->getOperand(i); 2960 if (Arg.getOpcode() != ISD::UNDEF) 2961 Val = cast<ConstantSDNode>(Arg)->getValue(); 2962 Mask |= Val; 2963 if (i != 0) 2964 Mask <<= 2; 2965 } 2966 2967 return Mask; 2968} 2969 2970/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2971/// specifies a 8 element shuffle that can be broken into a pair of 2972/// PSHUFHW and PSHUFLW. 2973static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2974 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2975 2976 if (N->getNumOperands() != 8) 2977 return false; 2978 2979 // Lower quadword shuffled. 2980 for (unsigned i = 0; i != 4; ++i) { 2981 SDOperand Arg = N->getOperand(i); 2982 if (Arg.getOpcode() == ISD::UNDEF) continue; 2983 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2984 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2985 if (Val > 4) 2986 return false; 2987 } 2988 2989 // Upper quadword shuffled. 2990 for (unsigned i = 4; i != 8; ++i) { 2991 SDOperand Arg = N->getOperand(i); 2992 if (Arg.getOpcode() == ISD::UNDEF) continue; 2993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2994 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2995 if (Val < 4 || Val > 7) 2996 return false; 2997 } 2998 2999 return true; 3000} 3001 3002/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as 3003/// values in ther permute mask. 3004static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) { 3005 SDOperand V1 = Op.getOperand(0); 3006 SDOperand V2 = Op.getOperand(1); 3007 SDOperand Mask = Op.getOperand(2); 3008 MVT::ValueType VT = Op.getValueType(); 3009 MVT::ValueType MaskVT = Mask.getValueType(); 3010 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT); 3011 unsigned NumElems = Mask.getNumOperands(); 3012 std::vector<SDOperand> MaskVec; 3013 3014 for (unsigned i = 0; i != NumElems; ++i) { 3015 SDOperand Arg = Mask.getOperand(i); 3016 if (Arg.getOpcode() == ISD::UNDEF) { 3017 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 3018 continue; 3019 } 3020 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 3021 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 3022 if (Val < NumElems) 3023 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 3024 else 3025 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 3026 } 3027 3028 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 3029 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask); 3030} 3031 3032/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3033/// match movhlps. The lower half elements should come from upper half of 3034/// V1 (and in order), and the upper half elements should come from the upper 3035/// half of V2 (and in order). 3036static bool ShouldXformToMOVHLPS(SDNode *Mask) { 3037 unsigned NumElems = Mask->getNumOperands(); 3038 if (NumElems != 4) 3039 return false; 3040 for (unsigned i = 0, e = 2; i != e; ++i) 3041 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 3042 return false; 3043 for (unsigned i = 2; i != 4; ++i) 3044 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 3045 return false; 3046 return true; 3047} 3048 3049/// isScalarLoadToVector - Returns true if the node is a scalar load that 3050/// is promoted to a vector. 3051static inline bool isScalarLoadToVector(SDNode *N) { 3052 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { 3053 N = N->getOperand(0).Val; 3054 return (N->getOpcode() == ISD::LOAD); 3055 } 3056 return false; 3057} 3058 3059/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3060/// match movlp{s|d}. The lower half elements should come from lower half of 3061/// V1 (and in order), and the upper half elements should come from the upper 3062/// half of V2 (and in order). And since V1 will become the source of the 3063/// MOVLP, it must be either a vector load or a scalar load to vector. 3064static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) { 3065 if (V1->getOpcode() != ISD::LOAD && !isScalarLoadToVector(V1)) 3066 return false; 3067 3068 unsigned NumElems = Mask->getNumOperands(); 3069 if (NumElems != 2 && NumElems != 4) 3070 return false; 3071 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3072 if (!isUndefOrEqual(Mask->getOperand(i), i)) 3073 return false; 3074 for (unsigned i = NumElems/2; i != NumElems; ++i) 3075 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 3076 return false; 3077 return true; 3078} 3079 3080/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3081/// all the same. 3082static bool isSplatVector(SDNode *N) { 3083 if (N->getOpcode() != ISD::BUILD_VECTOR) 3084 return false; 3085 3086 SDOperand SplatValue = N->getOperand(0); 3087 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3088 if (N->getOperand(i) != SplatValue) 3089 return false; 3090 return true; 3091} 3092 3093/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3094/// to an undef. 3095static bool isUndefShuffle(SDNode *N) { 3096 if (N->getOpcode() != ISD::BUILD_VECTOR) 3097 return false; 3098 3099 SDOperand V1 = N->getOperand(0); 3100 SDOperand V2 = N->getOperand(1); 3101 SDOperand Mask = N->getOperand(2); 3102 unsigned NumElems = Mask.getNumOperands(); 3103 for (unsigned i = 0; i != NumElems; ++i) { 3104 SDOperand Arg = Mask.getOperand(i); 3105 if (Arg.getOpcode() != ISD::UNDEF) { 3106 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 3107 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 3108 return false; 3109 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 3110 return false; 3111 } 3112 } 3113 return true; 3114} 3115 3116/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3117/// that point to V2 points to its first element. 3118static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { 3119 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 3120 3121 bool Changed = false; 3122 std::vector<SDOperand> MaskVec; 3123 unsigned NumElems = Mask.getNumOperands(); 3124 for (unsigned i = 0; i != NumElems; ++i) { 3125 SDOperand Arg = Mask.getOperand(i); 3126 if (Arg.getOpcode() != ISD::UNDEF) { 3127 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 3128 if (Val > NumElems) { 3129 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 3130 Changed = true; 3131 } 3132 } 3133 MaskVec.push_back(Arg); 3134 } 3135 3136 if (Changed) 3137 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 3138 &MaskVec[0], MaskVec.size()); 3139 return Mask; 3140} 3141 3142/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3143/// operation of specified width. 3144static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 3145 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3146 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3147 3148 std::vector<SDOperand> MaskVec; 3149 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 3150 for (unsigned i = 1; i != NumElems; ++i) 3151 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3152 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 3153} 3154 3155/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 3156/// of specified width. 3157static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 3158 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3159 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3160 std::vector<SDOperand> MaskVec; 3161 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3162 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3163 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 3164 } 3165 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 3166} 3167 3168/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 3169/// of specified width. 3170static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 3171 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3172 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3173 unsigned Half = NumElems/2; 3174 std::vector<SDOperand> MaskVec; 3175 for (unsigned i = 0; i != Half; ++i) { 3176 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 3177 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 3178 } 3179 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 3180} 3181 3182/// getZeroVector - Returns a vector of specified type with all zero elements. 3183/// 3184static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) { 3185 assert(MVT::isVector(VT) && "Expected a vector type"); 3186 unsigned NumElems = getVectorNumElements(VT); 3187 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 3188 bool isFP = MVT::isFloatingPoint(EVT); 3189 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT); 3190 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3191 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size()); 3192} 3193 3194/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32. 3195/// 3196static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) { 3197 SDOperand V1 = Op.getOperand(0); 3198 SDOperand Mask = Op.getOperand(2); 3199 MVT::ValueType VT = Op.getValueType(); 3200 unsigned NumElems = Mask.getNumOperands(); 3201 Mask = getUnpacklMask(NumElems, DAG); 3202 while (NumElems != 4) { 3203 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 3204 NumElems >>= 1; 3205 } 3206 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1); 3207 3208 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3209 Mask = getZeroVector(MaskVT, DAG); 3210 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1, 3211 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask); 3212 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 3213} 3214 3215/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3216/// constant +0.0. 3217static inline bool isZeroNode(SDOperand Elt) { 3218 return ((isa<ConstantSDNode>(Elt) && 3219 cast<ConstantSDNode>(Elt)->getValue() == 0) || 3220 (isa<ConstantFPSDNode>(Elt) && 3221 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0))); 3222} 3223 3224/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3225/// vector and zero or undef vector. 3226static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT, 3227 unsigned NumElems, unsigned Idx, 3228 bool isZero, SelectionDAG &DAG) { 3229 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT); 3230 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3231 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 3232 SDOperand Zero = DAG.getConstant(0, EVT); 3233 std::vector<SDOperand> MaskVec(NumElems, Zero); 3234 MaskVec[Idx] = DAG.getConstant(NumElems, EVT); 3235 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3236 &MaskVec[0], MaskVec.size()); 3237 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3238} 3239 3240/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3241/// 3242static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, 3243 unsigned NumNonZero, unsigned NumZero, 3244 SelectionDAG &DAG, TargetLowering &TLI) { 3245 if (NumNonZero > 8) 3246 return SDOperand(); 3247 3248 SDOperand V(0, 0); 3249 bool First = true; 3250 for (unsigned i = 0; i < 16; ++i) { 3251 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3252 if (ThisIsNonZero && First) { 3253 if (NumZero) 3254 V = getZeroVector(MVT::v8i16, DAG); 3255 else 3256 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3257 First = false; 3258 } 3259 3260 if ((i & 1) != 0) { 3261 SDOperand ThisElt(0, 0), LastElt(0, 0); 3262 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3263 if (LastIsNonZero) { 3264 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 3265 } 3266 if (ThisIsNonZero) { 3267 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 3268 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 3269 ThisElt, DAG.getConstant(8, MVT::i8)); 3270 if (LastIsNonZero) 3271 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 3272 } else 3273 ThisElt = LastElt; 3274 3275 if (ThisElt.Val) 3276 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 3277 DAG.getConstant(i/2, TLI.getPointerTy())); 3278 } 3279 } 3280 3281 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 3282} 3283 3284/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16. 3285/// 3286static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, 3287 unsigned NumNonZero, unsigned NumZero, 3288 SelectionDAG &DAG, TargetLowering &TLI) { 3289 if (NumNonZero > 4) 3290 return SDOperand(); 3291 3292 SDOperand V(0, 0); 3293 bool First = true; 3294 for (unsigned i = 0; i < 8; ++i) { 3295 bool isNonZero = (NonZeros & (1 << i)) != 0; 3296 if (isNonZero) { 3297 if (First) { 3298 if (NumZero) 3299 V = getZeroVector(MVT::v8i16, DAG); 3300 else 3301 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3302 First = false; 3303 } 3304 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 3305 DAG.getConstant(i, TLI.getPointerTy())); 3306 } 3307 } 3308 3309 return V; 3310} 3311 3312SDOperand 3313X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 3314 // All zero's are handled with pxor. 3315 if (ISD::isBuildVectorAllZeros(Op.Val)) 3316 return Op; 3317 3318 // All one's are handled with pcmpeqd. 3319 if (ISD::isBuildVectorAllOnes(Op.Val)) 3320 return Op; 3321 3322 MVT::ValueType VT = Op.getValueType(); 3323 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 3324 unsigned EVTBits = MVT::getSizeInBits(EVT); 3325 3326 unsigned NumElems = Op.getNumOperands(); 3327 unsigned NumZero = 0; 3328 unsigned NumNonZero = 0; 3329 unsigned NonZeros = 0; 3330 std::set<SDOperand> Values; 3331 for (unsigned i = 0; i < NumElems; ++i) { 3332 SDOperand Elt = Op.getOperand(i); 3333 if (Elt.getOpcode() != ISD::UNDEF) { 3334 Values.insert(Elt); 3335 if (isZeroNode(Elt)) 3336 NumZero++; 3337 else { 3338 NonZeros |= (1 << i); 3339 NumNonZero++; 3340 } 3341 } 3342 } 3343 3344 if (NumNonZero == 0) 3345 // Must be a mix of zero and undef. Return a zero vector. 3346 return getZeroVector(VT, DAG); 3347 3348 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3349 if (Values.size() == 1) 3350 return SDOperand(); 3351 3352 // Special case for single non-zero element. 3353 if (!NoShuffleOpti && NumNonZero == 1) { 3354 unsigned Idx = CountTrailingZeros_32(NonZeros); 3355 SDOperand Item = Op.getOperand(Idx); 3356 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3357 if (Idx == 0) 3358 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3359 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx, 3360 NumZero > 0, DAG); 3361 3362 if (EVTBits == 32) { 3363 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3364 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0, 3365 DAG); 3366 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3367 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 3368 std::vector<SDOperand> MaskVec; 3369 for (unsigned i = 0; i < NumElems; i++) 3370 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3371 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3372 &MaskVec[0], MaskVec.size()); 3373 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 3374 DAG.getNode(ISD::UNDEF, VT), Mask); 3375 } 3376 } 3377 3378 // Let legalizer expand 2-wide build_vector's. 3379 if (EVTBits == 64) 3380 return SDOperand(); 3381 3382 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3383 if (EVTBits == 8) { 3384 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3385 *this); 3386 if (V.Val) return V; 3387 } 3388 3389 if (EVTBits == 16) { 3390 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3391 *this); 3392 if (V.Val) return V; 3393 } 3394 3395 // If element VT is == 32 bits, turn it into a number of shuffles. 3396 std::vector<SDOperand> V(NumElems); 3397 if (NumElems == 4 && NumZero > 0) { 3398 for (unsigned i = 0; i < 4; ++i) { 3399 bool isZero = !(NonZeros & (1 << i)); 3400 if (isZero) 3401 V[i] = getZeroVector(VT, DAG); 3402 else 3403 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3404 } 3405 3406 for (unsigned i = 0; i < 2; ++i) { 3407 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3408 default: break; 3409 case 0: 3410 V[i] = V[i*2]; // Must be a zero vector. 3411 break; 3412 case 1: 3413 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3414 getMOVLMask(NumElems, DAG)); 3415 break; 3416 case 2: 3417 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3418 getMOVLMask(NumElems, DAG)); 3419 break; 3420 case 3: 3421 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3422 getUnpacklMask(NumElems, DAG)); 3423 break; 3424 } 3425 } 3426 3427 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) 3428 // clears the upper bits. 3429 // FIXME: we can do the same for v4f32 case when we know both parts of 3430 // the lower half come from scalar_to_vector (loadf32). We should do 3431 // that in post legalizer dag combiner with target specific hooks. 3432 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) 3433 return V[0]; 3434 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3435 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 3436 std::vector<SDOperand> MaskVec; 3437 bool Reverse = (NonZeros & 0x3) == 2; 3438 for (unsigned i = 0; i < 2; ++i) 3439 if (Reverse) 3440 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3441 else 3442 MaskVec.push_back(DAG.getConstant(i, EVT)); 3443 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3444 for (unsigned i = 0; i < 2; ++i) 3445 if (Reverse) 3446 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3447 else 3448 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3449 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3450 &MaskVec[0], MaskVec.size()); 3451 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3452 } 3453 3454 if (Values.size() > 2) { 3455 // Expand into a number of unpckl*. 3456 // e.g. for v4f32 3457 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3458 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3459 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3460 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); 3461 for (unsigned i = 0; i < NumElems; ++i) 3462 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3463 NumElems >>= 1; 3464 while (NumElems != 0) { 3465 for (unsigned i = 0; i < NumElems; ++i) 3466 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3467 UnpckMask); 3468 NumElems >>= 1; 3469 } 3470 return V[0]; 3471 } 3472 3473 return SDOperand(); 3474} 3475 3476SDOperand 3477X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 3478 SDOperand V1 = Op.getOperand(0); 3479 SDOperand V2 = Op.getOperand(1); 3480 SDOperand PermMask = Op.getOperand(2); 3481 MVT::ValueType VT = Op.getValueType(); 3482 unsigned NumElems = PermMask.getNumOperands(); 3483 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 3484 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 3485 3486 if (isUndefShuffle(Op.Val)) 3487 return DAG.getNode(ISD::UNDEF, VT); 3488 3489 if (isSplatMask(PermMask.Val)) { 3490 if (NumElems <= 4) return Op; 3491 // Promote it to a v4i32 splat. 3492 if (!NoShuffleOpti) 3493 return PromoteSplat(Op, DAG); 3494 } 3495 3496 if (!NoShuffleOpti) { 3497 if (X86::isMOVLMask(PermMask.Val)) 3498 return (V1IsUndef) ? V2 : Op; 3499 3500 if (X86::isMOVSHDUPMask(PermMask.Val) || 3501 X86::isMOVSLDUPMask(PermMask.Val) || 3502 X86::isMOVHLPSMask(PermMask.Val) || 3503 X86::isMOVHPMask(PermMask.Val) || 3504 X86::isMOVLPMask(PermMask.Val)) 3505 return Op; 3506 3507 if (ShouldXformToMOVHLPS(PermMask.Val) || 3508 ShouldXformToMOVLP(V1.Val, PermMask.Val)) 3509 return CommuteVectorShuffle(Op, DAG); 3510 3511 bool V1IsSplat = isSplatVector(V1.Val); 3512 bool V2IsSplat = isSplatVector(V2.Val); 3513 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 3514 Op = CommuteVectorShuffle(Op, DAG); 3515 V1 = Op.getOperand(0); 3516 V2 = Op.getOperand(1); 3517 PermMask = Op.getOperand(2); 3518 std::swap(V1IsSplat, V2IsSplat); 3519 std::swap(V1IsUndef, V2IsUndef); 3520 } 3521 3522 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { 3523 if (V2IsUndef) return V1; 3524 Op = CommuteVectorShuffle(Op, DAG); 3525 V1 = Op.getOperand(0); 3526 V2 = Op.getOperand(1); 3527 PermMask = Op.getOperand(2); 3528 if (V2IsSplat) { 3529 // V2 is a splat, so the mask may be malformed. That is, it may point 3530 // to any V2 element. The instruction selectior won't like this. Get 3531 // a corrected mask and commute to form a proper MOVS{S|D}. 3532 SDOperand NewMask = getMOVLMask(NumElems, DAG); 3533 if (NewMask.Val != PermMask.Val) 3534 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3535 } 3536 return Op; 3537 } 3538 3539 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3540 X86::isUNPCKLMask(PermMask.Val) || 3541 X86::isUNPCKHMask(PermMask.Val)) 3542 return Op; 3543 3544 if (V2IsSplat) { 3545 // Normalize mask so all entries that point to V2 points to its first 3546 // element then try to match unpck{h|l} again. If match, return a 3547 // new vector_shuffle with the corrected mask. 3548 SDOperand NewMask = NormalizeMask(PermMask, DAG); 3549 if (NewMask.Val != PermMask.Val) { 3550 if (X86::isUNPCKLMask(PermMask.Val, true)) { 3551 SDOperand NewMask = getUnpacklMask(NumElems, DAG); 3552 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3553 } else if (X86::isUNPCKHMask(PermMask.Val, true)) { 3554 SDOperand NewMask = getUnpackhMask(NumElems, DAG); 3555 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3556 } 3557 } 3558 } 3559 } 3560 3561 // Normalize the node to match x86 shuffle ops if needed 3562 if (V2.getOpcode() != ISD::UNDEF) 3563 if (isCommutedSHUFP(PermMask.Val)) { 3564 Op = CommuteVectorShuffle(Op, DAG); 3565 V1 = Op.getOperand(0); 3566 V2 = Op.getOperand(1); 3567 PermMask = Op.getOperand(2); 3568 } 3569 3570 // If VT is integer, try PSHUF* first, then SHUFP*. 3571 if (MVT::isInteger(VT)) { 3572 if (X86::isPSHUFDMask(PermMask.Val) || 3573 X86::isPSHUFHWMask(PermMask.Val) || 3574 X86::isPSHUFLWMask(PermMask.Val)) { 3575 if (V2.getOpcode() != ISD::UNDEF) 3576 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3577 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3578 return Op; 3579 } 3580 3581 if (X86::isSHUFPMask(PermMask.Val)) 3582 return Op; 3583 3584 // Handle v8i16 shuffle high / low shuffle node pair. 3585 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { 3586 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3587 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3588 std::vector<SDOperand> MaskVec; 3589 for (unsigned i = 0; i != 4; ++i) 3590 MaskVec.push_back(PermMask.getOperand(i)); 3591 for (unsigned i = 4; i != 8; ++i) 3592 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3593 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3594 &MaskVec[0], MaskVec.size()); 3595 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3596 MaskVec.clear(); 3597 for (unsigned i = 0; i != 4; ++i) 3598 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3599 for (unsigned i = 4; i != 8; ++i) 3600 MaskVec.push_back(PermMask.getOperand(i)); 3601 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size()); 3602 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3603 } 3604 } else { 3605 // Floating point cases in the other order. 3606 if (X86::isSHUFPMask(PermMask.Val)) 3607 return Op; 3608 if (X86::isPSHUFDMask(PermMask.Val) || 3609 X86::isPSHUFHWMask(PermMask.Val) || 3610 X86::isPSHUFLWMask(PermMask.Val)) { 3611 if (V2.getOpcode() != ISD::UNDEF) 3612 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3613 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3614 return Op; 3615 } 3616 } 3617 3618 if (NumElems == 4) { 3619 MVT::ValueType MaskVT = PermMask.getValueType(); 3620 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 3621 std::vector<std::pair<int, int> > Locs; 3622 Locs.reserve(NumElems); 3623 std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3624 std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3625 unsigned NumHi = 0; 3626 unsigned NumLo = 0; 3627 // If no more than two elements come from either vector. This can be 3628 // implemented with two shuffles. First shuffle gather the elements. 3629 // The second shuffle, which takes the first shuffle as both of its 3630 // vector operands, put the elements into the right order. 3631 for (unsigned i = 0; i != NumElems; ++i) { 3632 SDOperand Elt = PermMask.getOperand(i); 3633 if (Elt.getOpcode() == ISD::UNDEF) { 3634 Locs[i] = std::make_pair(-1, -1); 3635 } else { 3636 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 3637 if (Val < NumElems) { 3638 Locs[i] = std::make_pair(0, NumLo); 3639 Mask1[NumLo] = Elt; 3640 NumLo++; 3641 } else { 3642 Locs[i] = std::make_pair(1, NumHi); 3643 if (2+NumHi < NumElems) 3644 Mask1[2+NumHi] = Elt; 3645 NumHi++; 3646 } 3647 } 3648 } 3649 if (NumLo <= 2 && NumHi <= 2) { 3650 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3651 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3652 &Mask1[0], Mask1.size())); 3653 for (unsigned i = 0; i != NumElems; ++i) { 3654 if (Locs[i].first == -1) 3655 continue; 3656 else { 3657 unsigned Idx = (i < NumElems/2) ? 0 : NumElems; 3658 Idx += Locs[i].first * (NumElems/2) + Locs[i].second; 3659 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3660 } 3661 } 3662 3663 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3664 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3665 &Mask2[0], Mask2.size())); 3666 } 3667 3668 // Break it into (shuffle shuffle_hi, shuffle_lo). 3669 Locs.clear(); 3670 std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3671 std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3672 std::vector<SDOperand> *MaskPtr = &LoMask; 3673 unsigned MaskIdx = 0; 3674 unsigned LoIdx = 0; 3675 unsigned HiIdx = NumElems/2; 3676 for (unsigned i = 0; i != NumElems; ++i) { 3677 if (i == NumElems/2) { 3678 MaskPtr = &HiMask; 3679 MaskIdx = 1; 3680 LoIdx = 0; 3681 HiIdx = NumElems/2; 3682 } 3683 SDOperand Elt = PermMask.getOperand(i); 3684 if (Elt.getOpcode() == ISD::UNDEF) { 3685 Locs[i] = std::make_pair(-1, -1); 3686 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) { 3687 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3688 (*MaskPtr)[LoIdx] = Elt; 3689 LoIdx++; 3690 } else { 3691 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3692 (*MaskPtr)[HiIdx] = Elt; 3693 HiIdx++; 3694 } 3695 } 3696 3697 SDOperand LoShuffle = 3698 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3699 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3700 &LoMask[0], LoMask.size())); 3701 SDOperand HiShuffle = 3702 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3703 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3704 &HiMask[0], HiMask.size())); 3705 std::vector<SDOperand> MaskOps; 3706 for (unsigned i = 0; i != NumElems; ++i) { 3707 if (Locs[i].first == -1) { 3708 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3709 } else { 3710 unsigned Idx = Locs[i].first * NumElems + Locs[i].second; 3711 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3712 } 3713 } 3714 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3715 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3716 &MaskOps[0], MaskOps.size())); 3717 } 3718 3719 return SDOperand(); 3720} 3721 3722SDOperand 3723X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3724 if (!isa<ConstantSDNode>(Op.getOperand(1))) 3725 return SDOperand(); 3726 3727 MVT::ValueType VT = Op.getValueType(); 3728 // TODO: handle v16i8. 3729 if (MVT::getSizeInBits(VT) == 16) { 3730 // Transform it so it match pextrw which produces a 32-bit result. 3731 MVT::ValueType EVT = (MVT::ValueType)(VT+1); 3732 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 3733 Op.getOperand(0), Op.getOperand(1)); 3734 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 3735 DAG.getValueType(VT)); 3736 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 3737 } else if (MVT::getSizeInBits(VT) == 32) { 3738 SDOperand Vec = Op.getOperand(0); 3739 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3740 if (Idx == 0) 3741 return Op; 3742 // SHUFPS the element to the lowest double word, then movss. 3743 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3744 std::vector<SDOperand> IdxVec; 3745 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT))); 3746 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3747 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3748 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3749 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3750 &IdxVec[0], IdxVec.size()); 3751 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3752 Vec, Vec, Mask); 3753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3754 DAG.getConstant(0, getPointerTy())); 3755 } else if (MVT::getSizeInBits(VT) == 64) { 3756 SDOperand Vec = Op.getOperand(0); 3757 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3758 if (Idx == 0) 3759 return Op; 3760 3761 // UNPCKHPD the element to the lowest double word, then movsd. 3762 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 3763 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 3764 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3765 std::vector<SDOperand> IdxVec; 3766 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); 3767 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 3768 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3769 &IdxVec[0], IdxVec.size()); 3770 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3771 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 3772 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3773 DAG.getConstant(0, getPointerTy())); 3774 } 3775 3776 return SDOperand(); 3777} 3778 3779SDOperand 3780X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3781 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 3782 // as its second argument. 3783 MVT::ValueType VT = Op.getValueType(); 3784 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT); 3785 SDOperand N0 = Op.getOperand(0); 3786 SDOperand N1 = Op.getOperand(1); 3787 SDOperand N2 = Op.getOperand(2); 3788 if (MVT::getSizeInBits(BaseVT) == 16) { 3789 if (N1.getValueType() != MVT::i32) 3790 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 3791 if (N2.getValueType() != MVT::i32) 3792 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32); 3793 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 3794 } else if (MVT::getSizeInBits(BaseVT) == 32) { 3795 unsigned Idx = cast<ConstantSDNode>(N2)->getValue(); 3796 if (Idx == 0) { 3797 // Use a movss. 3798 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1); 3799 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3800 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 3801 std::vector<SDOperand> MaskVec; 3802 MaskVec.push_back(DAG.getConstant(4, BaseVT)); 3803 for (unsigned i = 1; i <= 3; ++i) 3804 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3805 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1, 3806 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3807 &MaskVec[0], MaskVec.size())); 3808 } else { 3809 // Use two pinsrw instructions to insert a 32 bit value. 3810 Idx <<= 1; 3811 if (MVT::isFloatingPoint(N1.getValueType())) { 3812 if (N1.getOpcode() == ISD::LOAD) { 3813 // Just load directly from f32mem to GR32. 3814 N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1), 3815 N1.getOperand(2)); 3816 } else { 3817 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1); 3818 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1); 3819 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1, 3820 DAG.getConstant(0, getPointerTy())); 3821 } 3822 } 3823 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0); 3824 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 3825 DAG.getConstant(Idx, getPointerTy())); 3826 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8)); 3827 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 3828 DAG.getConstant(Idx+1, getPointerTy())); 3829 return DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3830 } 3831 } 3832 3833 return SDOperand(); 3834} 3835 3836SDOperand 3837X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 3838 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 3839 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt); 3840} 3841 3842// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 3843// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 3844// one of the above mentioned nodes. It has to be wrapped because otherwise 3845// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 3846// be used to form addressing mode. These wrapped nodes will be selected 3847// into MOV32ri. 3848SDOperand 3849X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 3850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 3851 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), 3852 DAG.getTargetConstantPool(CP->getConstVal(), 3853 getPointerTy(), 3854 CP->getAlignment())); 3855 if (Subtarget->isTargetDarwin()) { 3856 // With PIC, the address is actually $g + Offset. 3857 if (!Subtarget->is64Bit() && 3858 getTargetMachine().getRelocationModel() == Reloc::PIC_) 3859 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3860 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); 3861 } 3862 3863 return Result; 3864} 3865 3866SDOperand 3867X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 3868 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 3869 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), 3870 DAG.getTargetGlobalAddress(GV, 3871 getPointerTy())); 3872 if (Subtarget->isTargetDarwin()) { 3873 // With PIC, the address is actually $g + Offset. 3874 if (!Subtarget->is64Bit() && 3875 getTargetMachine().getRelocationModel() == Reloc::PIC_) 3876 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3877 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3878 Result); 3879 3880 // For Darwin, external and weak symbols are indirect, so we want to load 3881 // the value at address GV, not the value of GV itself. This means that 3882 // the GlobalAddress must be in the base or index register of the address, 3883 // not the GV offset field. 3884 if (getTargetMachine().getRelocationModel() != Reloc::Static && 3885 DarwinGVRequiresExtraLoad(GV)) 3886 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), 3887 Result, DAG.getSrcValue(NULL)); 3888 } else if (Subtarget->isTargetCygwin() || Subtarget->isTargetWindows()) { 3889 // FIXME: What's about PIC? 3890 if (WindowsGVRequiresExtraLoad(GV)) { 3891 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), 3892 Result, DAG.getSrcValue(NULL)); 3893 } 3894 } 3895 3896 3897 return Result; 3898} 3899 3900SDOperand 3901X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { 3902 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 3903 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), 3904 DAG.getTargetExternalSymbol(Sym, 3905 getPointerTy())); 3906 if (Subtarget->isTargetDarwin()) { 3907 // With PIC, the address is actually $g + Offset. 3908 if (!Subtarget->is64Bit() && 3909 getTargetMachine().getRelocationModel() == Reloc::PIC_) 3910 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3911 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3912 Result); 3913 } 3914 3915 return Result; 3916} 3917 3918SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { 3919 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 3920 "Not an i64 shift!"); 3921 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 3922 SDOperand ShOpLo = Op.getOperand(0); 3923 SDOperand ShOpHi = Op.getOperand(1); 3924 SDOperand ShAmt = Op.getOperand(2); 3925 SDOperand Tmp1 = isSRA ? 3926 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) : 3927 DAG.getConstant(0, MVT::i32); 3928 3929 SDOperand Tmp2, Tmp3; 3930 if (Op.getOpcode() == ISD::SHL_PARTS) { 3931 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); 3932 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); 3933 } else { 3934 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); 3935 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); 3936 } 3937 3938 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3939 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 3940 DAG.getConstant(32, MVT::i8)); 3941 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)}; 3942 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1); 3943 3944 SDOperand Hi, Lo; 3945 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 3946 3947 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag); 3948 SmallVector<SDOperand, 4> Ops; 3949 if (Op.getOpcode() == ISD::SHL_PARTS) { 3950 Ops.push_back(Tmp2); 3951 Ops.push_back(Tmp3); 3952 Ops.push_back(CC); 3953 Ops.push_back(InFlag); 3954 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3955 InFlag = Hi.getValue(1); 3956 3957 Ops.clear(); 3958 Ops.push_back(Tmp3); 3959 Ops.push_back(Tmp1); 3960 Ops.push_back(CC); 3961 Ops.push_back(InFlag); 3962 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3963 } else { 3964 Ops.push_back(Tmp2); 3965 Ops.push_back(Tmp3); 3966 Ops.push_back(CC); 3967 Ops.push_back(InFlag); 3968 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3969 InFlag = Lo.getValue(1); 3970 3971 Ops.clear(); 3972 Ops.push_back(Tmp3); 3973 Ops.push_back(Tmp1); 3974 Ops.push_back(CC); 3975 Ops.push_back(InFlag); 3976 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3977 } 3978 3979 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32); 3980 Ops.clear(); 3981 Ops.push_back(Lo); 3982 Ops.push_back(Hi); 3983 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); 3984} 3985 3986SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 3987 assert(Op.getOperand(0).getValueType() <= MVT::i64 && 3988 Op.getOperand(0).getValueType() >= MVT::i16 && 3989 "Unknown SINT_TO_FP to lower!"); 3990 3991 SDOperand Result; 3992 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3993 unsigned Size = MVT::getSizeInBits(SrcVT)/8; 3994 MachineFunction &MF = DAG.getMachineFunction(); 3995 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 3996 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3997 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, 3998 DAG.getEntryNode(), Op.getOperand(0), 3999 StackSlot, DAG.getSrcValue(NULL)); 4000 4001 // Build the FILD 4002 std::vector<MVT::ValueType> Tys; 4003 Tys.push_back(MVT::f64); 4004 Tys.push_back(MVT::Other); 4005 if (X86ScalarSSE) Tys.push_back(MVT::Flag); 4006 std::vector<SDOperand> Ops; 4007 Ops.push_back(Chain); 4008 Ops.push_back(StackSlot); 4009 Ops.push_back(DAG.getValueType(SrcVT)); 4010 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD, 4011 Tys, &Ops[0], Ops.size()); 4012 4013 if (X86ScalarSSE) { 4014 Chain = Result.getValue(1); 4015 SDOperand InFlag = Result.getValue(2); 4016 4017 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4018 // shouldn't be necessary except that RFP cannot be live across 4019 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4020 MachineFunction &MF = DAG.getMachineFunction(); 4021 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4022 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4023 std::vector<MVT::ValueType> Tys; 4024 Tys.push_back(MVT::Other); 4025 std::vector<SDOperand> Ops; 4026 Ops.push_back(Chain); 4027 Ops.push_back(Result); 4028 Ops.push_back(StackSlot); 4029 Ops.push_back(DAG.getValueType(Op.getValueType())); 4030 Ops.push_back(InFlag); 4031 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 4032 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 4033 DAG.getSrcValue(NULL)); 4034 } 4035 4036 return Result; 4037} 4038 4039SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 4040 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 4041 "Unknown FP_TO_SINT to lower!"); 4042 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 4043 // stack slot. 4044 MachineFunction &MF = DAG.getMachineFunction(); 4045 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 4046 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4047 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4048 4049 unsigned Opc; 4050 switch (Op.getValueType()) { 4051 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 4052 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 4053 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 4054 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 4055 } 4056 4057 SDOperand Chain = DAG.getEntryNode(); 4058 SDOperand Value = Op.getOperand(0); 4059 if (X86ScalarSSE) { 4060 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 4061 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot, 4062 DAG.getSrcValue(0)); 4063 std::vector<MVT::ValueType> Tys; 4064 Tys.push_back(MVT::f64); 4065 Tys.push_back(MVT::Other); 4066 std::vector<SDOperand> Ops; 4067 Ops.push_back(Chain); 4068 Ops.push_back(StackSlot); 4069 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType())); 4070 Value = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size()); 4071 Chain = Value.getValue(1); 4072 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4073 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4074 } 4075 4076 // Build the FP_TO_INT*_IN_MEM 4077 std::vector<SDOperand> Ops; 4078 Ops.push_back(Chain); 4079 Ops.push_back(Value); 4080 Ops.push_back(StackSlot); 4081 SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size()); 4082 4083 // Load the result. 4084 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, 4085 DAG.getSrcValue(NULL)); 4086} 4087 4088SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { 4089 MVT::ValueType VT = Op.getValueType(); 4090 const Type *OpNTy = MVT::getTypeForValueType(VT); 4091 std::vector<Constant*> CV; 4092 if (VT == MVT::f64) { 4093 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63)))); 4094 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4095 } else { 4096 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31)))); 4097 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4098 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4099 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4100 } 4101 Constant *CS = ConstantStruct::get(CV); 4102 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 4103 std::vector<MVT::ValueType> Tys; 4104 Tys.push_back(VT); 4105 Tys.push_back(MVT::Other); 4106 SmallVector<SDOperand, 3> Ops; 4107 Ops.push_back(DAG.getEntryNode()); 4108 Ops.push_back(CPIdx); 4109 Ops.push_back(DAG.getSrcValue(NULL)); 4110 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 4111 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 4112} 4113 4114SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { 4115 MVT::ValueType VT = Op.getValueType(); 4116 const Type *OpNTy = MVT::getTypeForValueType(VT); 4117 std::vector<Constant*> CV; 4118 if (VT == MVT::f64) { 4119 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63))); 4120 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4121 } else { 4122 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31))); 4123 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4124 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4125 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 4126 } 4127 Constant *CS = ConstantStruct::get(CV); 4128 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 4129 std::vector<MVT::ValueType> Tys; 4130 Tys.push_back(VT); 4131 Tys.push_back(MVT::Other); 4132 SmallVector<SDOperand, 3> Ops; 4133 Ops.push_back(DAG.getEntryNode()); 4134 Ops.push_back(CPIdx); 4135 Ops.push_back(DAG.getSrcValue(NULL)); 4136 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 4137 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 4138} 4139 4140SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG, 4141 SDOperand Chain) { 4142 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 4143 SDOperand Cond; 4144 SDOperand Op0 = Op.getOperand(0); 4145 SDOperand Op1 = Op.getOperand(1); 4146 SDOperand CC = Op.getOperand(2); 4147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 4148 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4149 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 4150 unsigned X86CC; 4151 4152 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 4153 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, 4154 Op0, Op1, DAG)) { 4155 SDOperand Ops1[] = { Chain, Op0, Op1 }; 4156 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops1, 3).getValue(1); 4157 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 4158 return DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 4159 } 4160 4161 assert(isFP && "Illegal integer SetCC!"); 4162 4163 SDOperand COps[] = { Chain, Op0, Op1 }; 4164 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1); 4165 4166 switch (SetCCOpcode) { 4167 default: assert(false && "Illegal floating point SetCC!"); 4168 case ISD::SETOEQ: { // !PF & ZF 4169 SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_NP, MVT::i8), Cond }; 4170 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2); 4171 SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_E, MVT::i8), 4172 Tmp1.getValue(1) }; 4173 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 4174 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 4175 } 4176 case ISD::SETUNE: { // PF | !ZF 4177 SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_P, MVT::i8), Cond }; 4178 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2); 4179 SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_NE, MVT::i8), 4180 Tmp1.getValue(1) }; 4181 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 4182 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 4183 } 4184 } 4185} 4186 4187SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { 4188 bool addTest = true; 4189 SDOperand Chain = DAG.getEntryNode(); 4190 SDOperand Cond = Op.getOperand(0); 4191 SDOperand CC; 4192 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4193 4194 if (Cond.getOpcode() == ISD::SETCC) 4195 Cond = LowerSETCC(Cond, DAG, Chain); 4196 4197 if (Cond.getOpcode() == X86ISD::SETCC) { 4198 CC = Cond.getOperand(0); 4199 4200 // If condition flag is set by a X86ISD::CMP, then make a copy of it 4201 // (since flag operand cannot be shared). Use it as the condition setting 4202 // operand in place of the X86ISD::SETCC. 4203 // If the X86ISD::SETCC has more than one use, then perhaps it's better 4204 // to use a test instead of duplicating the X86ISD::CMP (for register 4205 // pressure reason)? 4206 SDOperand Cmp = Cond.getOperand(1); 4207 unsigned Opc = Cmp.getOpcode(); 4208 bool IllegalFPCMov = !X86ScalarSSE && 4209 MVT::isFloatingPoint(Op.getValueType()) && 4210 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 4211 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) && 4212 !IllegalFPCMov) { 4213 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 4214 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 4215 addTest = false; 4216 } 4217 } 4218 4219 if (addTest) { 4220 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 4221 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 4222 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 4223 } 4224 4225 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag); 4226 SmallVector<SDOperand, 4> Ops; 4227 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 4228 // condition is true. 4229 Ops.push_back(Op.getOperand(2)); 4230 Ops.push_back(Op.getOperand(1)); 4231 Ops.push_back(CC); 4232 Ops.push_back(Cond.getValue(1)); 4233 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 4234} 4235 4236SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { 4237 bool addTest = true; 4238 SDOperand Chain = Op.getOperand(0); 4239 SDOperand Cond = Op.getOperand(1); 4240 SDOperand Dest = Op.getOperand(2); 4241 SDOperand CC; 4242 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4243 4244 if (Cond.getOpcode() == ISD::SETCC) 4245 Cond = LowerSETCC(Cond, DAG, Chain); 4246 4247 if (Cond.getOpcode() == X86ISD::SETCC) { 4248 CC = Cond.getOperand(0); 4249 4250 // If condition flag is set by a X86ISD::CMP, then make a copy of it 4251 // (since flag operand cannot be shared). Use it as the condition setting 4252 // operand in place of the X86ISD::SETCC. 4253 // If the X86ISD::SETCC has more than one use, then perhaps it's better 4254 // to use a test instead of duplicating the X86ISD::CMP (for register 4255 // pressure reason)? 4256 SDOperand Cmp = Cond.getOperand(1); 4257 unsigned Opc = Cmp.getOpcode(); 4258 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) { 4259 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 4260 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 4261 addTest = false; 4262 } 4263 } 4264 4265 if (addTest) { 4266 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 4267 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 4268 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 4269 } 4270 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 4271 Cond, Op.getOperand(2), CC, Cond.getValue(1)); 4272} 4273 4274SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 4275 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4276 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), 4277 DAG.getTargetJumpTable(JT->getIndex(), 4278 getPointerTy())); 4279 if (Subtarget->isTargetDarwin()) { 4280 // With PIC, the address is actually $g + Offset. 4281 if (!Subtarget->is64Bit() && 4282 getTargetMachine().getRelocationModel() == Reloc::PIC_) 4283 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4284 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4285 Result); 4286 } 4287 4288 return Result; 4289} 4290 4291SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 4292 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4293 4294 if (Subtarget->is64Bit()) 4295 return LowerX86_64CCCCallTo(Op, DAG); 4296 else 4297 switch (CallingConv) { 4298 default: 4299 assert(0 && "Unsupported calling convention"); 4300 case CallingConv::Fast: 4301 if (EnableFastCC) { 4302 return LowerFastCCCallTo(Op, DAG, false); 4303 } 4304 // Falls through 4305 case CallingConv::C: 4306 case CallingConv::CSRet: 4307 return LowerCCCCallTo(Op, DAG); 4308 case CallingConv::X86_StdCall: 4309 return LowerStdCallCCCallTo(Op, DAG); 4310 case CallingConv::X86_FastCall: 4311 return LowerFastCCCallTo(Op, DAG, true); 4312 } 4313} 4314 4315SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { 4316 SDOperand Copy; 4317 4318 switch(Op.getNumOperands()) { 4319 default: 4320 assert(0 && "Do not know how to return this many arguments!"); 4321 abort(); 4322 case 1: // ret void. 4323 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), 4324 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 4325 case 3: { 4326 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 4327 4328 if (MVT::isVector(ArgVT) || 4329 (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) { 4330 // Integer or FP vector result -> XMM0. 4331 if (DAG.getMachineFunction().liveout_empty()) 4332 DAG.getMachineFunction().addLiveOut(X86::XMM0); 4333 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1), 4334 SDOperand()); 4335 } else if (MVT::isInteger(ArgVT)) { 4336 // Integer result -> EAX / RAX. 4337 // The C calling convention guarantees the return value has been 4338 // promoted to at least MVT::i32. The X86-64 ABI doesn't require the 4339 // value to be promoted MVT::i64. So we don't have to extend it to 4340 // 64-bit. Return the value in EAX, but mark RAX as liveout. 4341 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 4342 if (DAG.getMachineFunction().liveout_empty()) 4343 DAG.getMachineFunction().addLiveOut(Reg); 4344 4345 Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX; 4346 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1), 4347 SDOperand()); 4348 } else if (!X86ScalarSSE) { 4349 // FP return with fp-stack value. 4350 if (DAG.getMachineFunction().liveout_empty()) 4351 DAG.getMachineFunction().addLiveOut(X86::ST0); 4352 4353 std::vector<MVT::ValueType> Tys; 4354 Tys.push_back(MVT::Other); 4355 Tys.push_back(MVT::Flag); 4356 std::vector<SDOperand> Ops; 4357 Ops.push_back(Op.getOperand(0)); 4358 Ops.push_back(Op.getOperand(1)); 4359 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size()); 4360 } else { 4361 // FP return with ScalarSSE (return on fp-stack). 4362 if (DAG.getMachineFunction().liveout_empty()) 4363 DAG.getMachineFunction().addLiveOut(X86::ST0); 4364 4365 SDOperand MemLoc; 4366 SDOperand Chain = Op.getOperand(0); 4367 SDOperand Value = Op.getOperand(1); 4368 4369 if (Value.getOpcode() == ISD::LOAD && 4370 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) { 4371 Chain = Value.getOperand(0); 4372 MemLoc = Value.getOperand(1); 4373 } else { 4374 // Spill the value to memory and reload it into top of stack. 4375 unsigned Size = MVT::getSizeInBits(ArgVT)/8; 4376 MachineFunction &MF = DAG.getMachineFunction(); 4377 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4378 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); 4379 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 4380 Value, MemLoc, DAG.getSrcValue(0)); 4381 } 4382 std::vector<MVT::ValueType> Tys; 4383 Tys.push_back(MVT::f64); 4384 Tys.push_back(MVT::Other); 4385 std::vector<SDOperand> Ops; 4386 Ops.push_back(Chain); 4387 Ops.push_back(MemLoc); 4388 Ops.push_back(DAG.getValueType(ArgVT)); 4389 Copy = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size()); 4390 Tys.clear(); 4391 Tys.push_back(MVT::Other); 4392 Tys.push_back(MVT::Flag); 4393 Ops.clear(); 4394 Ops.push_back(Copy.getValue(1)); 4395 Ops.push_back(Copy); 4396 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size()); 4397 } 4398 break; 4399 } 4400 case 5: { 4401 unsigned Reg1 = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 4402 unsigned Reg2 = Subtarget->is64Bit() ? X86::RDX : X86::EDX; 4403 if (DAG.getMachineFunction().liveout_empty()) { 4404 DAG.getMachineFunction().addLiveOut(Reg1); 4405 DAG.getMachineFunction().addLiveOut(Reg2); 4406 } 4407 4408 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg2, Op.getOperand(3), 4409 SDOperand()); 4410 Copy = DAG.getCopyToReg(Copy, Reg1, Op.getOperand(1), Copy.getValue(1)); 4411 break; 4412 } 4413 } 4414 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, 4415 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), 4416 Copy.getValue(1)); 4417} 4418 4419SDOperand 4420X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 4421 MachineFunction &MF = DAG.getMachineFunction(); 4422 const Function* Fn = MF.getFunction(); 4423 if (Fn->hasExternalLinkage() && 4424 Subtarget->isTargetCygwin() && 4425 Fn->getName() == "main") 4426 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true); 4427 4428 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4429 if (Subtarget->is64Bit()) 4430 return LowerX86_64CCCArguments(Op, DAG); 4431 else 4432 switch(CC) { 4433 default: 4434 assert(0 && "Unsupported calling convention"); 4435 case CallingConv::Fast: 4436 if (EnableFastCC) { 4437 return LowerFastCCArguments(Op, DAG); 4438 } 4439 // Falls through 4440 case CallingConv::C: 4441 case CallingConv::CSRet: 4442 return LowerCCCArguments(Op, DAG); 4443 case CallingConv::X86_StdCall: 4444 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall); 4445 return LowerStdCallCCArguments(Op, DAG); 4446 case CallingConv::X86_FastCall: 4447 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall); 4448 return LowerFastCallCCArguments(Op, DAG); 4449 } 4450} 4451 4452SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { 4453 SDOperand InFlag(0, 0); 4454 SDOperand Chain = Op.getOperand(0); 4455 unsigned Align = 4456 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 4457 if (Align == 0) Align = 1; 4458 4459 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 4460 // If not DWORD aligned, call memset if size is less than the threshold. 4461 // It knows how to align to the right boundary first. 4462 if ((Align & 3) != 0 || 4463 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 4464 MVT::ValueType IntPtr = getPointerTy(); 4465 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 4466 std::vector<std::pair<SDOperand, const Type*> > Args; 4467 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); 4468 // Extend the ubyte argument to be an int value for the call. 4469 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); 4470 Args.push_back(std::make_pair(Val, IntPtrTy)); 4471 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy)); 4472 std::pair<SDOperand,SDOperand> CallResult = 4473 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false, 4474 DAG.getExternalSymbol("memset", IntPtr), Args, DAG); 4475 return CallResult.second; 4476 } 4477 4478 MVT::ValueType AVT; 4479 SDOperand Count; 4480 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 4481 unsigned BytesLeft = 0; 4482 bool TwoRepStos = false; 4483 if (ValC) { 4484 unsigned ValReg; 4485 uint64_t Val = ValC->getValue() & 255; 4486 4487 // If the value is a constant, then we can potentially use larger sets. 4488 switch (Align & 3) { 4489 case 2: // WORD aligned 4490 AVT = MVT::i16; 4491 ValReg = X86::AX; 4492 Val = (Val << 8) | Val; 4493 break; 4494 case 0: // DWORD aligned 4495 AVT = MVT::i32; 4496 ValReg = X86::EAX; 4497 Val = (Val << 8) | Val; 4498 Val = (Val << 16) | Val; 4499 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned 4500 AVT = MVT::i64; 4501 ValReg = X86::RAX; 4502 Val = (Val << 32) | Val; 4503 } 4504 break; 4505 default: // Byte aligned 4506 AVT = MVT::i8; 4507 ValReg = X86::AL; 4508 Count = Op.getOperand(3); 4509 break; 4510 } 4511 4512 if (AVT > MVT::i8) { 4513 if (I) { 4514 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4515 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 4516 BytesLeft = I->getValue() % UBytes; 4517 } else { 4518 assert(AVT >= MVT::i32 && 4519 "Do not use rep;stos if not at least DWORD aligned"); 4520 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 4521 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 4522 TwoRepStos = true; 4523 } 4524 } 4525 4526 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 4527 InFlag); 4528 InFlag = Chain.getValue(1); 4529 } else { 4530 AVT = MVT::i8; 4531 Count = Op.getOperand(3); 4532 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); 4533 InFlag = Chain.getValue(1); 4534 } 4535 4536 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4537 Count, InFlag); 4538 InFlag = Chain.getValue(1); 4539 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4540 Op.getOperand(1), InFlag); 4541 InFlag = Chain.getValue(1); 4542 4543 std::vector<MVT::ValueType> Tys; 4544 Tys.push_back(MVT::Other); 4545 Tys.push_back(MVT::Flag); 4546 std::vector<SDOperand> Ops; 4547 Ops.push_back(Chain); 4548 Ops.push_back(DAG.getValueType(AVT)); 4549 Ops.push_back(InFlag); 4550 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4551 4552 if (TwoRepStos) { 4553 InFlag = Chain.getValue(1); 4554 Count = Op.getOperand(3); 4555 MVT::ValueType CVT = Count.getValueType(); 4556 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 4557 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 4558 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 4559 Left, InFlag); 4560 InFlag = Chain.getValue(1); 4561 Tys.clear(); 4562 Tys.push_back(MVT::Other); 4563 Tys.push_back(MVT::Flag); 4564 Ops.clear(); 4565 Ops.push_back(Chain); 4566 Ops.push_back(DAG.getValueType(MVT::i8)); 4567 Ops.push_back(InFlag); 4568 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4569 } else if (BytesLeft) { 4570 // Issue stores for the last 1 - 7 bytes. 4571 SDOperand Value; 4572 unsigned Val = ValC->getValue() & 255; 4573 unsigned Offset = I->getValue() - BytesLeft; 4574 SDOperand DstAddr = Op.getOperand(1); 4575 MVT::ValueType AddrVT = DstAddr.getValueType(); 4576 if (BytesLeft >= 4) { 4577 Val = (Val << 8) | Val; 4578 Val = (Val << 16) | Val; 4579 Value = DAG.getConstant(Val, MVT::i32); 4580 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4581 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4582 DAG.getConstant(Offset, AddrVT)), 4583 DAG.getSrcValue(NULL)); 4584 BytesLeft -= 4; 4585 Offset += 4; 4586 } 4587 if (BytesLeft >= 2) { 4588 Value = DAG.getConstant((Val << 8) | Val, MVT::i16); 4589 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4590 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4591 DAG.getConstant(Offset, AddrVT)), 4592 DAG.getSrcValue(NULL)); 4593 BytesLeft -= 2; 4594 Offset += 2; 4595 } 4596 if (BytesLeft == 1) { 4597 Value = DAG.getConstant(Val, MVT::i8); 4598 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4599 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4600 DAG.getConstant(Offset, AddrVT)), 4601 DAG.getSrcValue(NULL)); 4602 } 4603 } 4604 4605 return Chain; 4606} 4607 4608SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 4609 SDOperand Chain = Op.getOperand(0); 4610 unsigned Align = 4611 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 4612 if (Align == 0) Align = 1; 4613 4614 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 4615 // If not DWORD aligned, call memcpy if size is less than the threshold. 4616 // It knows how to align to the right boundary first. 4617 if ((Align & 3) != 0 || 4618 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 4619 MVT::ValueType IntPtr = getPointerTy(); 4620 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 4621 std::vector<std::pair<SDOperand, const Type*> > Args; 4622 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); 4623 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy)); 4624 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy)); 4625 std::pair<SDOperand,SDOperand> CallResult = 4626 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false, 4627 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 4628 return CallResult.second; 4629 } 4630 4631 MVT::ValueType AVT; 4632 SDOperand Count; 4633 unsigned BytesLeft = 0; 4634 bool TwoRepMovs = false; 4635 switch (Align & 3) { 4636 case 2: // WORD aligned 4637 AVT = MVT::i16; 4638 break; 4639 case 0: // DWORD aligned 4640 AVT = MVT::i32; 4641 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned 4642 AVT = MVT::i64; 4643 break; 4644 default: // Byte aligned 4645 AVT = MVT::i8; 4646 Count = Op.getOperand(3); 4647 break; 4648 } 4649 4650 if (AVT > MVT::i8) { 4651 if (I) { 4652 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4653 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 4654 BytesLeft = I->getValue() % UBytes; 4655 } else { 4656 assert(AVT >= MVT::i32 && 4657 "Do not use rep;movs if not at least DWORD aligned"); 4658 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 4659 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 4660 TwoRepMovs = true; 4661 } 4662 } 4663 4664 SDOperand InFlag(0, 0); 4665 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4666 Count, InFlag); 4667 InFlag = Chain.getValue(1); 4668 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4669 Op.getOperand(1), InFlag); 4670 InFlag = Chain.getValue(1); 4671 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 4672 Op.getOperand(2), InFlag); 4673 InFlag = Chain.getValue(1); 4674 4675 std::vector<MVT::ValueType> Tys; 4676 Tys.push_back(MVT::Other); 4677 Tys.push_back(MVT::Flag); 4678 std::vector<SDOperand> Ops; 4679 Ops.push_back(Chain); 4680 Ops.push_back(DAG.getValueType(AVT)); 4681 Ops.push_back(InFlag); 4682 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 4683 4684 if (TwoRepMovs) { 4685 InFlag = Chain.getValue(1); 4686 Count = Op.getOperand(3); 4687 MVT::ValueType CVT = Count.getValueType(); 4688 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 4689 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 4690 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 4691 Left, InFlag); 4692 InFlag = Chain.getValue(1); 4693 Tys.clear(); 4694 Tys.push_back(MVT::Other); 4695 Tys.push_back(MVT::Flag); 4696 Ops.clear(); 4697 Ops.push_back(Chain); 4698 Ops.push_back(DAG.getValueType(MVT::i8)); 4699 Ops.push_back(InFlag); 4700 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 4701 } else if (BytesLeft) { 4702 // Issue loads and stores for the last 1 - 7 bytes. 4703 unsigned Offset = I->getValue() - BytesLeft; 4704 SDOperand DstAddr = Op.getOperand(1); 4705 MVT::ValueType DstVT = DstAddr.getValueType(); 4706 SDOperand SrcAddr = Op.getOperand(2); 4707 MVT::ValueType SrcVT = SrcAddr.getValueType(); 4708 SDOperand Value; 4709 if (BytesLeft >= 4) { 4710 Value = DAG.getLoad(MVT::i32, Chain, 4711 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4712 DAG.getConstant(Offset, SrcVT)), 4713 DAG.getSrcValue(NULL)); 4714 Chain = Value.getValue(1); 4715 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4716 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4717 DAG.getConstant(Offset, DstVT)), 4718 DAG.getSrcValue(NULL)); 4719 BytesLeft -= 4; 4720 Offset += 4; 4721 } 4722 if (BytesLeft >= 2) { 4723 Value = DAG.getLoad(MVT::i16, Chain, 4724 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4725 DAG.getConstant(Offset, SrcVT)), 4726 DAG.getSrcValue(NULL)); 4727 Chain = Value.getValue(1); 4728 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4729 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4730 DAG.getConstant(Offset, DstVT)), 4731 DAG.getSrcValue(NULL)); 4732 BytesLeft -= 2; 4733 Offset += 2; 4734 } 4735 4736 if (BytesLeft == 1) { 4737 Value = DAG.getLoad(MVT::i8, Chain, 4738 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4739 DAG.getConstant(Offset, SrcVT)), 4740 DAG.getSrcValue(NULL)); 4741 Chain = Value.getValue(1); 4742 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, 4743 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4744 DAG.getConstant(Offset, DstVT)), 4745 DAG.getSrcValue(NULL)); 4746 } 4747 } 4748 4749 return Chain; 4750} 4751 4752SDOperand 4753X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) { 4754 std::vector<MVT::ValueType> Tys; 4755 Tys.push_back(MVT::Other); 4756 Tys.push_back(MVT::Flag); 4757 std::vector<SDOperand> Ops; 4758 Ops.push_back(Op.getOperand(0)); 4759 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size()); 4760 Ops.clear(); 4761 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); 4762 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, 4763 MVT::i32, Ops[0].getValue(2))); 4764 Ops.push_back(Ops[1].getValue(1)); 4765 Tys[0] = Tys[1] = MVT::i32; 4766 Tys.push_back(MVT::Other); 4767 return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size()); 4768} 4769 4770SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { 4771 if (!Subtarget->is64Bit()) { 4772 // vastart just stores the address of the VarArgsFrameIndex slot into the 4773 // memory location argument. 4774 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4775 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 4776 Op.getOperand(1), Op.getOperand(2)); 4777 } 4778 4779 // __va_list_tag: 4780 // gp_offset (0 - 6 * 8) 4781 // fp_offset (48 - 48 + 8 * 16) 4782 // overflow_arg_area (point to parameters coming in memory). 4783 // reg_save_area 4784 std::vector<SDOperand> MemOps; 4785 SDOperand FIN = Op.getOperand(1); 4786 // Store gp_offset 4787 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 4788 DAG.getConstant(VarArgsGPOffset, MVT::i32), 4789 FIN, Op.getOperand(2)); 4790 MemOps.push_back(Store); 4791 4792 // Store fp_offset 4793 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4794 DAG.getConstant(4, getPointerTy())); 4795 Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 4796 DAG.getConstant(VarArgsFPOffset, MVT::i32), 4797 FIN, Op.getOperand(2)); 4798 MemOps.push_back(Store); 4799 4800 // Store ptr to overflow_arg_area 4801 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4802 DAG.getConstant(4, getPointerTy())); 4803 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4804 Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 4805 OVFIN, FIN, Op.getOperand(2)); 4806 MemOps.push_back(Store); 4807 4808 // Store ptr to reg_save_area. 4809 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 4810 DAG.getConstant(8, getPointerTy())); 4811 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 4812 Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 4813 RSFIN, FIN, Op.getOperand(2)); 4814 MemOps.push_back(Store); 4815 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 4816} 4817 4818SDOperand 4819X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 4820 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 4821 switch (IntNo) { 4822 default: return SDOperand(); // Don't custom lower most intrinsics. 4823 // Comparison intrinsics. 4824 case Intrinsic::x86_sse_comieq_ss: 4825 case Intrinsic::x86_sse_comilt_ss: 4826 case Intrinsic::x86_sse_comile_ss: 4827 case Intrinsic::x86_sse_comigt_ss: 4828 case Intrinsic::x86_sse_comige_ss: 4829 case Intrinsic::x86_sse_comineq_ss: 4830 case Intrinsic::x86_sse_ucomieq_ss: 4831 case Intrinsic::x86_sse_ucomilt_ss: 4832 case Intrinsic::x86_sse_ucomile_ss: 4833 case Intrinsic::x86_sse_ucomigt_ss: 4834 case Intrinsic::x86_sse_ucomige_ss: 4835 case Intrinsic::x86_sse_ucomineq_ss: 4836 case Intrinsic::x86_sse2_comieq_sd: 4837 case Intrinsic::x86_sse2_comilt_sd: 4838 case Intrinsic::x86_sse2_comile_sd: 4839 case Intrinsic::x86_sse2_comigt_sd: 4840 case Intrinsic::x86_sse2_comige_sd: 4841 case Intrinsic::x86_sse2_comineq_sd: 4842 case Intrinsic::x86_sse2_ucomieq_sd: 4843 case Intrinsic::x86_sse2_ucomilt_sd: 4844 case Intrinsic::x86_sse2_ucomile_sd: 4845 case Intrinsic::x86_sse2_ucomigt_sd: 4846 case Intrinsic::x86_sse2_ucomige_sd: 4847 case Intrinsic::x86_sse2_ucomineq_sd: { 4848 unsigned Opc = 0; 4849 ISD::CondCode CC = ISD::SETCC_INVALID; 4850 switch (IntNo) { 4851 default: break; 4852 case Intrinsic::x86_sse_comieq_ss: 4853 case Intrinsic::x86_sse2_comieq_sd: 4854 Opc = X86ISD::COMI; 4855 CC = ISD::SETEQ; 4856 break; 4857 case Intrinsic::x86_sse_comilt_ss: 4858 case Intrinsic::x86_sse2_comilt_sd: 4859 Opc = X86ISD::COMI; 4860 CC = ISD::SETLT; 4861 break; 4862 case Intrinsic::x86_sse_comile_ss: 4863 case Intrinsic::x86_sse2_comile_sd: 4864 Opc = X86ISD::COMI; 4865 CC = ISD::SETLE; 4866 break; 4867 case Intrinsic::x86_sse_comigt_ss: 4868 case Intrinsic::x86_sse2_comigt_sd: 4869 Opc = X86ISD::COMI; 4870 CC = ISD::SETGT; 4871 break; 4872 case Intrinsic::x86_sse_comige_ss: 4873 case Intrinsic::x86_sse2_comige_sd: 4874 Opc = X86ISD::COMI; 4875 CC = ISD::SETGE; 4876 break; 4877 case Intrinsic::x86_sse_comineq_ss: 4878 case Intrinsic::x86_sse2_comineq_sd: 4879 Opc = X86ISD::COMI; 4880 CC = ISD::SETNE; 4881 break; 4882 case Intrinsic::x86_sse_ucomieq_ss: 4883 case Intrinsic::x86_sse2_ucomieq_sd: 4884 Opc = X86ISD::UCOMI; 4885 CC = ISD::SETEQ; 4886 break; 4887 case Intrinsic::x86_sse_ucomilt_ss: 4888 case Intrinsic::x86_sse2_ucomilt_sd: 4889 Opc = X86ISD::UCOMI; 4890 CC = ISD::SETLT; 4891 break; 4892 case Intrinsic::x86_sse_ucomile_ss: 4893 case Intrinsic::x86_sse2_ucomile_sd: 4894 Opc = X86ISD::UCOMI; 4895 CC = ISD::SETLE; 4896 break; 4897 case Intrinsic::x86_sse_ucomigt_ss: 4898 case Intrinsic::x86_sse2_ucomigt_sd: 4899 Opc = X86ISD::UCOMI; 4900 CC = ISD::SETGT; 4901 break; 4902 case Intrinsic::x86_sse_ucomige_ss: 4903 case Intrinsic::x86_sse2_ucomige_sd: 4904 Opc = X86ISD::UCOMI; 4905 CC = ISD::SETGE; 4906 break; 4907 case Intrinsic::x86_sse_ucomineq_ss: 4908 case Intrinsic::x86_sse2_ucomineq_sd: 4909 Opc = X86ISD::UCOMI; 4910 CC = ISD::SETNE; 4911 break; 4912 } 4913 4914 unsigned X86CC; 4915 SDOperand LHS = Op.getOperand(1); 4916 SDOperand RHS = Op.getOperand(2); 4917 translateX86CC(CC, true, X86CC, LHS, RHS, DAG); 4918 4919 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4920 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS }; 4921 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3); 4922 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 4923 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 4924 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 4925 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); 4926 } 4927 } 4928} 4929 4930/// LowerOperation - Provide custom lowering hooks for some operations. 4931/// 4932SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 4933 switch (Op.getOpcode()) { 4934 default: assert(0 && "Should not custom lower this!"); 4935 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4936 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4937 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4938 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 4939 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4940 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4941 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4942 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 4943 case ISD::SHL_PARTS: 4944 case ISD::SRA_PARTS: 4945 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 4946 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4947 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 4948 case ISD::FABS: return LowerFABS(Op, DAG); 4949 case ISD::FNEG: return LowerFNEG(Op, DAG); 4950 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode()); 4951 case ISD::SELECT: return LowerSELECT(Op, DAG); 4952 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 4953 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4954 case ISD::CALL: return LowerCALL(Op, DAG); 4955 case ISD::RET: return LowerRET(Op, DAG); 4956 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 4957 case ISD::MEMSET: return LowerMEMSET(Op, DAG); 4958 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 4959 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG); 4960 case ISD::VASTART: return LowerVASTART(Op, DAG); 4961 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4962 } 4963} 4964 4965const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 4966 switch (Opcode) { 4967 default: return NULL; 4968 case X86ISD::SHLD: return "X86ISD::SHLD"; 4969 case X86ISD::SHRD: return "X86ISD::SHRD"; 4970 case X86ISD::FAND: return "X86ISD::FAND"; 4971 case X86ISD::FXOR: return "X86ISD::FXOR"; 4972 case X86ISD::FILD: return "X86ISD::FILD"; 4973 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 4974 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 4975 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 4976 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 4977 case X86ISD::FLD: return "X86ISD::FLD"; 4978 case X86ISD::FST: return "X86ISD::FST"; 4979 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; 4980 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; 4981 case X86ISD::CALL: return "X86ISD::CALL"; 4982 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 4983 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 4984 case X86ISD::CMP: return "X86ISD::CMP"; 4985 case X86ISD::COMI: return "X86ISD::COMI"; 4986 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 4987 case X86ISD::SETCC: return "X86ISD::SETCC"; 4988 case X86ISD::CMOV: return "X86ISD::CMOV"; 4989 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 4990 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 4991 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 4992 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 4993 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; 4994 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA"; 4995 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 4996 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 4997 case X86ISD::S2VEC: return "X86ISD::S2VEC"; 4998 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 4999 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 5000 } 5001} 5002 5003/// isLegalAddressImmediate - Return true if the integer value or 5004/// GlobalValue can be used as the offset of the target addressing mode. 5005bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const { 5006 // X86 allows a sign-extended 32-bit immediate field. 5007 return (V > -(1LL << 32) && V < (1LL << 32)-1); 5008} 5009 5010bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { 5011 // GV is 64-bit but displacement field is 32-bit unless we are in small code 5012 // model. Mac OS X happens to support only small PIC code model. 5013 // FIXME: better support for other OS's. 5014 if (Subtarget->is64Bit() && !Subtarget->isTargetDarwin()) 5015 return false; 5016 if (Subtarget->isTargetDarwin()) { 5017 Reloc::Model RModel = getTargetMachine().getRelocationModel(); 5018 if (RModel == Reloc::Static) 5019 return true; 5020 else if (RModel == Reloc::DynamicNoPIC) 5021 return !DarwinGVRequiresExtraLoad(GV); 5022 else 5023 return false; 5024 } else 5025 return true; 5026} 5027 5028/// isShuffleMaskLegal - Targets can use this to indicate that they only 5029/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 5030/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 5031/// are assumed to be legal. 5032bool 5033X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 5034 // Only do shuffles on 128-bit vector types for now. 5035 if (MVT::getSizeInBits(VT) == 64) return false; 5036 return (Mask.Val->getNumOperands() <= 4 || 5037 isSplatMask(Mask.Val) || 5038 isPSHUFHW_PSHUFLWMask(Mask.Val) || 5039 X86::isUNPCKLMask(Mask.Val) || 5040 X86::isUNPCKL_v_undef_Mask(Mask.Val) || 5041 X86::isUNPCKHMask(Mask.Val)); 5042} 5043 5044bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 5045 MVT::ValueType EVT, 5046 SelectionDAG &DAG) const { 5047 unsigned NumElts = BVOps.size(); 5048 // Only do shuffles on 128-bit vector types for now. 5049 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; 5050 if (NumElts == 2) return true; 5051 if (NumElts == 4) { 5052 return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) || 5053 isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps)); 5054 } 5055 return false; 5056} 5057 5058//===----------------------------------------------------------------------===// 5059// X86 Scheduler Hooks 5060//===----------------------------------------------------------------------===// 5061 5062MachineBasicBlock * 5063X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 5064 MachineBasicBlock *BB) { 5065 switch (MI->getOpcode()) { 5066 default: assert(false && "Unexpected instr type to insert"); 5067 case X86::CMOV_FR32: 5068 case X86::CMOV_FR64: 5069 case X86::CMOV_V4F32: 5070 case X86::CMOV_V2F64: 5071 case X86::CMOV_V2I64: { 5072 // To "insert" a SELECT_CC instruction, we actually have to insert the 5073 // diamond control-flow pattern. The incoming instruction knows the 5074 // destination vreg to set, the condition code register to branch on, the 5075 // true/false values to select between, and a branch opcode to use. 5076 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5077 ilist<MachineBasicBlock>::iterator It = BB; 5078 ++It; 5079 5080 // thisMBB: 5081 // ... 5082 // TrueVal = ... 5083 // cmpTY ccX, r1, r2 5084 // bCC copy1MBB 5085 // fallthrough --> copy0MBB 5086 MachineBasicBlock *thisMBB = BB; 5087 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 5088 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 5089 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue()); 5090 BuildMI(BB, Opc, 1).addMBB(sinkMBB); 5091 MachineFunction *F = BB->getParent(); 5092 F->getBasicBlockList().insert(It, copy0MBB); 5093 F->getBasicBlockList().insert(It, sinkMBB); 5094 // Update machine-CFG edges by first adding all successors of the current 5095 // block to the new block which will contain the Phi node for the select. 5096 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 5097 e = BB->succ_end(); i != e; ++i) 5098 sinkMBB->addSuccessor(*i); 5099 // Next, remove all successors of the current block, and add the true 5100 // and fallthrough blocks as its successors. 5101 while(!BB->succ_empty()) 5102 BB->removeSuccessor(BB->succ_begin()); 5103 BB->addSuccessor(copy0MBB); 5104 BB->addSuccessor(sinkMBB); 5105 5106 // copy0MBB: 5107 // %FalseValue = ... 5108 // # fallthrough to sinkMBB 5109 BB = copy0MBB; 5110 5111 // Update machine-CFG edges 5112 BB->addSuccessor(sinkMBB); 5113 5114 // sinkMBB: 5115 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5116 // ... 5117 BB = sinkMBB; 5118 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg()) 5119 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 5120 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5121 5122 delete MI; // The pseudo instruction is gone now. 5123 return BB; 5124 } 5125 5126 case X86::FP_TO_INT16_IN_MEM: 5127 case X86::FP_TO_INT32_IN_MEM: 5128 case X86::FP_TO_INT64_IN_MEM: { 5129 // Change the floating point control register to use "round towards zero" 5130 // mode when truncating to an integer value. 5131 MachineFunction *F = BB->getParent(); 5132 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 5133 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); 5134 5135 // Load the old value of the high byte of the control word... 5136 unsigned OldCW = 5137 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); 5138 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); 5139 5140 // Set the high part to be round to zero... 5141 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); 5142 5143 // Reload the modified control word now... 5144 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); 5145 5146 // Restore the memory image of control word to original value 5147 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); 5148 5149 // Get the X86 opcode to use. 5150 unsigned Opc; 5151 switch (MI->getOpcode()) { 5152 default: assert(0 && "illegal opcode!"); 5153 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; 5154 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; 5155 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; 5156 } 5157 5158 X86AddressMode AM; 5159 MachineOperand &Op = MI->getOperand(0); 5160 if (Op.isRegister()) { 5161 AM.BaseType = X86AddressMode::RegBase; 5162 AM.Base.Reg = Op.getReg(); 5163 } else { 5164 AM.BaseType = X86AddressMode::FrameIndexBase; 5165 AM.Base.FrameIndex = Op.getFrameIndex(); 5166 } 5167 Op = MI->getOperand(1); 5168 if (Op.isImmediate()) 5169 AM.Scale = Op.getImmedValue(); 5170 Op = MI->getOperand(2); 5171 if (Op.isImmediate()) 5172 AM.IndexReg = Op.getImmedValue(); 5173 Op = MI->getOperand(3); 5174 if (Op.isGlobalAddress()) { 5175 AM.GV = Op.getGlobal(); 5176 } else { 5177 AM.Disp = Op.getImmedValue(); 5178 } 5179 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg()); 5180 5181 // Reload the original control word now. 5182 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); 5183 5184 delete MI; // The pseudo instruction is gone now. 5185 return BB; 5186 } 5187 } 5188} 5189 5190//===----------------------------------------------------------------------===// 5191// X86 Optimization Hooks 5192//===----------------------------------------------------------------------===// 5193 5194void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 5195 uint64_t Mask, 5196 uint64_t &KnownZero, 5197 uint64_t &KnownOne, 5198 unsigned Depth) const { 5199 unsigned Opc = Op.getOpcode(); 5200 assert((Opc >= ISD::BUILTIN_OP_END || 5201 Opc == ISD::INTRINSIC_WO_CHAIN || 5202 Opc == ISD::INTRINSIC_W_CHAIN || 5203 Opc == ISD::INTRINSIC_VOID) && 5204 "Should use MaskedValueIsZero if you don't know whether Op" 5205 " is a target node!"); 5206 5207 KnownZero = KnownOne = 0; // Don't know anything. 5208 switch (Opc) { 5209 default: break; 5210 case X86ISD::SETCC: 5211 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 5212 break; 5213 } 5214} 5215 5216/// getShuffleScalarElt - Returns the scalar element that will make up the ith 5217/// element of the result of the vector shuffle. 5218static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) { 5219 MVT::ValueType VT = N->getValueType(0); 5220 SDOperand PermMask = N->getOperand(2); 5221 unsigned NumElems = PermMask.getNumOperands(); 5222 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1); 5223 i %= NumElems; 5224 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5225 return (i == 0) 5226 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 5227 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { 5228 SDOperand Idx = PermMask.getOperand(i); 5229 if (Idx.getOpcode() == ISD::UNDEF) 5230 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 5231 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG); 5232 } 5233 return SDOperand(); 5234} 5235 5236/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 5237/// node is a GlobalAddress + an offset. 5238static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) { 5239 if (N->getOpcode() == X86ISD::Wrapper) { 5240 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) { 5241 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 5242 return true; 5243 } 5244 } else if (N->getOpcode() == ISD::ADD) { 5245 SDOperand N1 = N->getOperand(0); 5246 SDOperand N2 = N->getOperand(1); 5247 if (isGAPlusOffset(N1.Val, GA, Offset)) { 5248 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 5249 if (V) { 5250 Offset += V->getSignExtended(); 5251 return true; 5252 } 5253 } else if (isGAPlusOffset(N2.Val, GA, Offset)) { 5254 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 5255 if (V) { 5256 Offset += V->getSignExtended(); 5257 return true; 5258 } 5259 } 5260 } 5261 return false; 5262} 5263 5264/// isConsecutiveLoad - Returns true if N is loading from an address of Base 5265/// + Dist * Size. 5266static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size, 5267 MachineFrameInfo *MFI) { 5268 if (N->getOperand(0).Val != Base->getOperand(0).Val) 5269 return false; 5270 5271 SDOperand Loc = N->getOperand(1); 5272 SDOperand BaseLoc = Base->getOperand(1); 5273 if (Loc.getOpcode() == ISD::FrameIndex) { 5274 if (BaseLoc.getOpcode() != ISD::FrameIndex) 5275 return false; 5276 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex(); 5277 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 5278 int FS = MFI->getObjectSize(FI); 5279 int BFS = MFI->getObjectSize(BFI); 5280 if (FS != BFS || FS != Size) return false; 5281 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size); 5282 } else { 5283 GlobalValue *GV1 = NULL; 5284 GlobalValue *GV2 = NULL; 5285 int64_t Offset1 = 0; 5286 int64_t Offset2 = 0; 5287 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); 5288 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); 5289 if (isGA1 && isGA2 && GV1 == GV2) 5290 return Offset1 == (Offset2 + Dist*Size); 5291 } 5292 5293 return false; 5294} 5295 5296static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, 5297 const X86Subtarget *Subtarget) { 5298 GlobalValue *GV; 5299 int64_t Offset; 5300 if (isGAPlusOffset(Base, GV, Offset)) 5301 return (GV->getAlignment() >= 16 && (Offset % 16) == 0); 5302 else { 5303 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!"); 5304 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex(); 5305 if (BFI < 0) 5306 // Fixed objects do not specify alignment, however the offsets are known. 5307 return ((Subtarget->getStackAlignment() % 16) == 0 && 5308 (MFI->getObjectOffset(BFI) % 16) == 0); 5309 else 5310 return MFI->getObjectAlignment(BFI) >= 16; 5311 } 5312 return false; 5313} 5314 5315 5316/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 5317/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 5318/// if the load addresses are consecutive, non-overlapping, and in the right 5319/// order. 5320static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 5321 const X86Subtarget *Subtarget) { 5322 MachineFunction &MF = DAG.getMachineFunction(); 5323 MachineFrameInfo *MFI = MF.getFrameInfo(); 5324 MVT::ValueType VT = N->getValueType(0); 5325 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 5326 SDOperand PermMask = N->getOperand(2); 5327 int NumElems = (int)PermMask.getNumOperands(); 5328 SDNode *Base = NULL; 5329 for (int i = 0; i < NumElems; ++i) { 5330 SDOperand Idx = PermMask.getOperand(i); 5331 if (Idx.getOpcode() == ISD::UNDEF) { 5332 if (!Base) return SDOperand(); 5333 } else { 5334 SDOperand Arg = 5335 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG); 5336 if (!Arg.Val || Arg.getOpcode() != ISD::LOAD) 5337 return SDOperand(); 5338 if (!Base) 5339 Base = Arg.Val; 5340 else if (!isConsecutiveLoad(Arg.Val, Base, 5341 i, MVT::getSizeInBits(EVT)/8,MFI)) 5342 return SDOperand(); 5343 } 5344 } 5345 5346 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); 5347 if (isAlign16) 5348 return DAG.getLoad(VT, Base->getOperand(0), Base->getOperand(1), 5349 Base->getOperand(2)); 5350 else { 5351 // Just use movups, it's shorter. 5352 std::vector<MVT::ValueType> Tys; 5353 Tys.push_back(MVT::v4f32); 5354 Tys.push_back(MVT::Other); 5355 SmallVector<SDOperand, 3> Ops; 5356 Ops.push_back(Base->getOperand(0)); 5357 Ops.push_back(Base->getOperand(1)); 5358 Ops.push_back(Base->getOperand(2)); 5359 return DAG.getNode(ISD::BIT_CONVERT, VT, 5360 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size())); 5361 } 5362} 5363 5364/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 5365static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 5366 const X86Subtarget *Subtarget) { 5367 SDOperand Cond = N->getOperand(0); 5368 5369 // If we have SSE[12] support, try to form min/max nodes. 5370 if (Subtarget->hasSSE2() && 5371 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 5372 if (Cond.getOpcode() == ISD::SETCC) { 5373 // Get the LHS/RHS of the select. 5374 SDOperand LHS = N->getOperand(1); 5375 SDOperand RHS = N->getOperand(2); 5376 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 5377 5378 unsigned IntNo = 0; 5379 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 5380 // (X olt Y) ? X : Y -> min 5381 if (CC == ISD::SETOLT || CC == ISD::SETLT) 5382 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_min_ss : 5383 Intrinsic::x86_sse2_min_sd; 5384 // (X uge Y) ? X : Y -> max 5385 if (CC == ISD::SETUGE || CC == ISD::SETGE) 5386 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_max_ss : 5387 Intrinsic::x86_sse2_max_sd; 5388 // TODO: Handle more cases if unsafe math! 5389 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 5390 // (X uge Y) ? Y : X -> min 5391 if (CC == ISD::SETUGE || CC == ISD::SETGE) 5392 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_min_ss : 5393 Intrinsic::x86_sse2_min_sd; 5394 // (X olt Y) ? Y : X -> max 5395 if (CC == ISD::SETOLT || CC == ISD::SETLT) 5396 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_max_ss : 5397 Intrinsic::x86_sse2_max_sd; 5398 // TODO: Handle more cases if unsafe math! 5399 } 5400 5401 // minss/maxss take a v4f32 operand. 5402 if (IntNo) { 5403 if (LHS.getValueType() == MVT::f32) { 5404 LHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, LHS); 5405 RHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, RHS); 5406 } else { 5407 LHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, LHS); 5408 RHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, RHS); 5409 } 5410 5411 MVT::ValueType PtrTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5412 SDOperand IntNoN = DAG.getConstant(IntNo, PtrTy); 5413 5414 SDOperand Val = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, LHS.getValueType(), 5415 IntNoN, LHS, RHS); 5416 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getValueType(0), Val, 5417 DAG.getConstant(0, PtrTy)); 5418 } 5419 } 5420 5421 } 5422 5423 return SDOperand(); 5424} 5425 5426 5427SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, 5428 DAGCombinerInfo &DCI) const { 5429 TargetMachine &TM = getTargetMachine(); 5430 SelectionDAG &DAG = DCI.DAG; 5431 switch (N->getOpcode()) { 5432 default: break; 5433 case ISD::VECTOR_SHUFFLE: 5434 return PerformShuffleCombine(N, DAG, Subtarget); 5435 case ISD::SELECT: 5436 return PerformSELECTCombine(N, DAG, Subtarget); 5437 } 5438 5439 return SDOperand(); 5440} 5441 5442//===----------------------------------------------------------------------===// 5443// X86 Inline Assembly Support 5444//===----------------------------------------------------------------------===// 5445 5446/// getConstraintType - Given a constraint letter, return the type of 5447/// constraint it is for this target. 5448X86TargetLowering::ConstraintType 5449X86TargetLowering::getConstraintType(char ConstraintLetter) const { 5450 switch (ConstraintLetter) { 5451 case 'A': 5452 case 'r': 5453 case 'R': 5454 case 'l': 5455 case 'q': 5456 case 'Q': 5457 case 'x': 5458 case 'Y': 5459 return C_RegisterClass; 5460 default: return TargetLowering::getConstraintType(ConstraintLetter); 5461 } 5462} 5463 5464std::vector<unsigned> X86TargetLowering:: 5465getRegClassForInlineAsmConstraint(const std::string &Constraint, 5466 MVT::ValueType VT) const { 5467 if (Constraint.size() == 1) { 5468 // FIXME: not handling fp-stack yet! 5469 // FIXME: not handling MMX registers yet ('y' constraint). 5470 switch (Constraint[0]) { // GCC X86 Constraint Letters 5471 default: break; // Unknown constraint letter 5472 case 'A': // EAX/EDX 5473 if (VT == MVT::i32 || VT == MVT::i64) 5474 return make_vector<unsigned>(X86::EAX, X86::EDX, 0); 5475 break; 5476 case 'r': // GENERAL_REGS 5477 case 'R': // LEGACY_REGS 5478 if (VT == MVT::i32) 5479 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 5480 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); 5481 else if (VT == MVT::i16) 5482 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 5483 X86::SI, X86::DI, X86::BP, X86::SP, 0); 5484 else if (VT == MVT::i8) 5485 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 5486 break; 5487 case 'l': // INDEX_REGS 5488 if (VT == MVT::i32) 5489 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 5490 X86::ESI, X86::EDI, X86::EBP, 0); 5491 else if (VT == MVT::i16) 5492 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 5493 X86::SI, X86::DI, X86::BP, 0); 5494 else if (VT == MVT::i8) 5495 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 5496 break; 5497 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 5498 case 'Q': // Q_REGS 5499 if (VT == MVT::i32) 5500 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 5501 else if (VT == MVT::i16) 5502 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 5503 else if (VT == MVT::i8) 5504 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 5505 break; 5506 case 'x': // SSE_REGS if SSE1 allowed 5507 if (Subtarget->hasSSE1()) 5508 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 5509 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 5510 0); 5511 return std::vector<unsigned>(); 5512 case 'Y': // SSE_REGS if SSE2 allowed 5513 if (Subtarget->hasSSE2()) 5514 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 5515 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 5516 0); 5517 return std::vector<unsigned>(); 5518 } 5519 } 5520 5521 return std::vector<unsigned>(); 5522} 5523 5524std::pair<unsigned, const TargetRegisterClass*> 5525X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5526 MVT::ValueType VT) const { 5527 // Use the default implementation in TargetLowering to convert the register 5528 // constraint into a member of a register class. 5529 std::pair<unsigned, const TargetRegisterClass*> Res; 5530 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5531 5532 // Not found? Bail out. 5533 if (Res.second == 0) return Res; 5534 5535 // Otherwise, check to see if this is a register class of the wrong value 5536 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 5537 // turn into {ax},{dx}. 5538 if (Res.second->hasType(VT)) 5539 return Res; // Correct type already, nothing to do. 5540 5541 // All of the single-register GCC register classes map their values onto 5542 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 5543 // really want an 8-bit or 32-bit register, map to the appropriate register 5544 // class and return the appropriate register. 5545 if (Res.second != X86::GR16RegisterClass) 5546 return Res; 5547 5548 if (VT == MVT::i8) { 5549 unsigned DestReg = 0; 5550 switch (Res.first) { 5551 default: break; 5552 case X86::AX: DestReg = X86::AL; break; 5553 case X86::DX: DestReg = X86::DL; break; 5554 case X86::CX: DestReg = X86::CL; break; 5555 case X86::BX: DestReg = X86::BL; break; 5556 } 5557 if (DestReg) { 5558 Res.first = DestReg; 5559 Res.second = Res.second = X86::GR8RegisterClass; 5560 } 5561 } else if (VT == MVT::i32) { 5562 unsigned DestReg = 0; 5563 switch (Res.first) { 5564 default: break; 5565 case X86::AX: DestReg = X86::EAX; break; 5566 case X86::DX: DestReg = X86::EDX; break; 5567 case X86::CX: DestReg = X86::ECX; break; 5568 case X86::BX: DestReg = X86::EBX; break; 5569 case X86::SI: DestReg = X86::ESI; break; 5570 case X86::DI: DestReg = X86::EDI; break; 5571 case X86::BP: DestReg = X86::EBP; break; 5572 case X86::SP: DestReg = X86::ESP; break; 5573 } 5574 if (DestReg) { 5575 Res.first = DestReg; 5576 Res.second = Res.second = X86::GR32RegisterClass; 5577 } 5578 } else if (VT == MVT::i64) { 5579 unsigned DestReg = 0; 5580 switch (Res.first) { 5581 default: break; 5582 case X86::AX: DestReg = X86::RAX; break; 5583 case X86::DX: DestReg = X86::RDX; break; 5584 case X86::CX: DestReg = X86::RCX; break; 5585 case X86::BX: DestReg = X86::RBX; break; 5586 case X86::SI: DestReg = X86::RSI; break; 5587 case X86::DI: DestReg = X86::RDI; break; 5588 case X86::BP: DestReg = X86::RBP; break; 5589 case X86::SP: DestReg = X86::RSP; break; 5590 } 5591 if (DestReg) { 5592 Res.first = DestReg; 5593 Res.second = Res.second = X86::GR64RegisterClass; 5594 } 5595 } 5596 5597 return Res; 5598} 5599 5600