X86ISelLowering.cpp revision e5af2d3a224d4b38760a26d237cde040cb6e14eb
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Function.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/ADT/BitVector.h" 27#include "llvm/ADT/VectorExtras.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/PseudoSourceValue.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/ADT/SmallSet.h" 40#include "llvm/ADT/StringExtras.h" 41#include "llvm/Support/CommandLine.h" 42using namespace llvm; 43 44static cl::opt<bool> 45DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 46 47// Forward declarations. 48static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG); 49 50X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 51 : TargetLowering(TM) { 52 Subtarget = &TM.getSubtarget<X86Subtarget>(); 53 X86ScalarSSEf64 = Subtarget->hasSSE2(); 54 X86ScalarSSEf32 = Subtarget->hasSSE1(); 55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 56 57 bool Fast = false; 58 59 RegInfo = TM.getRegisterInfo(); 60 TD = getTargetData(); 61 62 // Set up the TargetLowering object. 63 64 // X86 is weird, it always uses i8 for shift amounts and setcc results. 65 setShiftAmountType(MVT::i8); 66 setBooleanContents(ZeroOrOneBooleanContent); 67 setSchedulingPreference(SchedulingForRegPressure); 68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 69 setStackPointerRegisterToSaveRestore(X86StackPtr); 70 71 if (Subtarget->isTargetDarwin()) { 72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(false); 74 setUseUnderscoreLongJmp(false); 75 } else if (Subtarget->isTargetMingw()) { 76 // MS runtime is weird: it exports _setjmp, but longjmp! 77 setUseUnderscoreSetJmp(true); 78 setUseUnderscoreLongJmp(false); 79 } else { 80 setUseUnderscoreSetJmp(true); 81 setUseUnderscoreLongJmp(true); 82 } 83 84 // Set up the register classes. 85 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 86 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 87 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 88 if (Subtarget->is64Bit()) 89 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 90 91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 92 93 // We don't accept any truncstore of integer registers. 94 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 95 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 97 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 99 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 100 101 // SETOEQ and SETUNE require checking two conditions. 102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 108 109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 110 // operation. 111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 114 115 if (Subtarget->is64Bit()) { 116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 118 } else { 119 if (X86ScalarSSEf64) { 120 // We have an impenetrably clever algorithm for ui64->double only. 121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 122 123 // We have faster algorithm for ui32->single only. 124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 125 } else 126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 127 } 128 129 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 130 // this operation. 131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 133 // SSE has no i16 to fp conversion, only i32 134 if (X86ScalarSSEf32) { 135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 136 // f32 and f64 cases are Legal, f80 case is not 137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 138 } else { 139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 141 } 142 143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 144 // are Legal, f80 is custom lowered. 145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 147 148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 149 // this operation. 150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 152 153 if (X86ScalarSSEf32) { 154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 155 // f32 and f64 cases are Legal, f80 case is not 156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 157 } else { 158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 160 } 161 162 // Handle FP_TO_UINT by promoting the destination to a larger signed 163 // conversion. 164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 167 168 if (Subtarget->is64Bit()) { 169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 171 } else { 172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 173 // Expand FP_TO_UINT into a select. 174 // FIXME: We would like to use a Custom expander here eventually to do 175 // the optimal thing for SSE vs. the default expansion in the legalizer. 176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 177 else 178 // With SSE3 we can use fisttpll to convert to a signed i64. 179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 180 } 181 182 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 183 if (!X86ScalarSSEf64) { 184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 186 } 187 188 // Scalar integer divide and remainder are lowered to use operations that 189 // produce two results, to match the available instructions. This exposes 190 // the two-result form to trivial CSE, which is able to combine x/y and x%y 191 // into a single instruction. 192 // 193 // Scalar integer multiply-high is also lowered to use two-result 194 // operations, to match the available instructions. However, plain multiply 195 // (low) operations are left as Legal, as there are single-result 196 // instructions for this in x86. Using the two-result multiply instructions 197 // when both high and low results are needed must be arranged by dagcombine. 198 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 199 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 200 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 201 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 202 setOperationAction(ISD::SREM , MVT::i8 , Expand); 203 setOperationAction(ISD::UREM , MVT::i8 , Expand); 204 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 205 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 206 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 207 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 208 setOperationAction(ISD::SREM , MVT::i16 , Expand); 209 setOperationAction(ISD::UREM , MVT::i16 , Expand); 210 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 211 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 212 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 213 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 214 setOperationAction(ISD::SREM , MVT::i32 , Expand); 215 setOperationAction(ISD::UREM , MVT::i32 , Expand); 216 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 217 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 218 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 219 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 220 setOperationAction(ISD::SREM , MVT::i64 , Expand); 221 setOperationAction(ISD::UREM , MVT::i64 , Expand); 222 223 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 224 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 225 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 227 if (Subtarget->is64Bit()) 228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 233 setOperationAction(ISD::FREM , MVT::f32 , Expand); 234 setOperationAction(ISD::FREM , MVT::f64 , Expand); 235 setOperationAction(ISD::FREM , MVT::f80 , Expand); 236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 237 238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 247 if (Subtarget->is64Bit()) { 248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 251 } 252 253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 255 256 // These should be promoted to a larger select which is supported. 257 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 258 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 259 // X86 wants to expand cmov itself. 260 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 261 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 262 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 263 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 264 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 265 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 266 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 267 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 268 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 269 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 270 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 271 if (Subtarget->is64Bit()) { 272 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 273 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 274 } 275 // X86 ret instruction may pop stack. 276 setOperationAction(ISD::RET , MVT::Other, Custom); 277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 278 279 // Darwin ABI issue. 280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 284 if (Subtarget->is64Bit()) 285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 292 } 293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 297 if (Subtarget->is64Bit()) { 298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 301 } 302 303 if (Subtarget->hasSSE1()) 304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 305 306 if (!Subtarget->hasSSE2()) 307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 308 309 // Expand certain atomics 310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 314 315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 319 320 if (!Subtarget->is64Bit()) { 321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 328 } 329 330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 332 // FIXME - use subtarget debug flags 333 if (!Subtarget->isTargetDarwin() && 334 !Subtarget->isTargetELF() && 335 !Subtarget->isTargetCygMing()) { 336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 338 } 339 340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 344 if (Subtarget->is64Bit()) { 345 setExceptionPointerRegister(X86::RAX); 346 setExceptionSelectorRegister(X86::RDX); 347 } else { 348 setExceptionPointerRegister(X86::EAX); 349 setExceptionSelectorRegister(X86::EDX); 350 } 351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 353 354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 355 356 setOperationAction(ISD::TRAP, MVT::Other, Legal); 357 358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 359 setOperationAction(ISD::VASTART , MVT::Other, Custom); 360 setOperationAction(ISD::VAEND , MVT::Other, Expand); 361 if (Subtarget->is64Bit()) { 362 setOperationAction(ISD::VAARG , MVT::Other, Custom); 363 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 364 } else { 365 setOperationAction(ISD::VAARG , MVT::Other, Expand); 366 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 367 } 368 369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 371 if (Subtarget->is64Bit()) 372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 373 if (Subtarget->isTargetCygMing()) 374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 375 else 376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 377 378 if (X86ScalarSSEf64) { 379 // f32 and f64 use SSE. 380 // Set up the FP register classes. 381 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 382 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 383 384 // Use ANDPD to simulate FABS. 385 setOperationAction(ISD::FABS , MVT::f64, Custom); 386 setOperationAction(ISD::FABS , MVT::f32, Custom); 387 388 // Use XORP to simulate FNEG. 389 setOperationAction(ISD::FNEG , MVT::f64, Custom); 390 setOperationAction(ISD::FNEG , MVT::f32, Custom); 391 392 // Use ANDPD and ORPD to simulate FCOPYSIGN. 393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 395 396 // We don't support sin/cos/fmod 397 setOperationAction(ISD::FSIN , MVT::f64, Expand); 398 setOperationAction(ISD::FCOS , MVT::f64, Expand); 399 setOperationAction(ISD::FSIN , MVT::f32, Expand); 400 setOperationAction(ISD::FCOS , MVT::f32, Expand); 401 402 // Expand FP immediates into loads from the stack, except for the special 403 // cases we handle. 404 addLegalFPImmediate(APFloat(+0.0)); // xorpd 405 addLegalFPImmediate(APFloat(+0.0f)); // xorps 406 407 // Floating truncations from f80 and extensions to f80 go through memory. 408 // If optimizing, we lie about this though and handle it in 409 // InstructionSelectPreprocess so that dagcombine2 can hack on these. 410 if (Fast) { 411 setConvertAction(MVT::f32, MVT::f80, Expand); 412 setConvertAction(MVT::f64, MVT::f80, Expand); 413 setConvertAction(MVT::f80, MVT::f32, Expand); 414 setConvertAction(MVT::f80, MVT::f64, Expand); 415 } 416 } else if (X86ScalarSSEf32) { 417 // Use SSE for f32, x87 for f64. 418 // Set up the FP register classes. 419 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 421 422 // Use ANDPS to simulate FABS. 423 setOperationAction(ISD::FABS , MVT::f32, Custom); 424 425 // Use XORP to simulate FNEG. 426 setOperationAction(ISD::FNEG , MVT::f32, Custom); 427 428 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 429 430 // Use ANDPS and ORPS to simulate FCOPYSIGN. 431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 433 434 // We don't support sin/cos/fmod 435 setOperationAction(ISD::FSIN , MVT::f32, Expand); 436 setOperationAction(ISD::FCOS , MVT::f32, Expand); 437 438 // Special cases we handle for FP constants. 439 addLegalFPImmediate(APFloat(+0.0f)); // xorps 440 addLegalFPImmediate(APFloat(+0.0)); // FLD0 441 addLegalFPImmediate(APFloat(+1.0)); // FLD1 442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 444 445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about 446 // this though and handle it in InstructionSelectPreprocess so that 447 // dagcombine2 can hack on these. 448 if (Fast) { 449 setConvertAction(MVT::f32, MVT::f64, Expand); 450 setConvertAction(MVT::f32, MVT::f80, Expand); 451 setConvertAction(MVT::f80, MVT::f32, Expand); 452 setConvertAction(MVT::f64, MVT::f32, Expand); 453 // And x87->x87 truncations also. 454 setConvertAction(MVT::f80, MVT::f64, Expand); 455 } 456 457 if (!UnsafeFPMath) { 458 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 459 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 460 } 461 } else { 462 // f32 and f64 in x87. 463 // Set up the FP register classes. 464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 466 467 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 468 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 471 472 // Floating truncations go through memory. If optimizing, we lie about 473 // this though and handle it in InstructionSelectPreprocess so that 474 // dagcombine2 can hack on these. 475 if (Fast) { 476 setConvertAction(MVT::f80, MVT::f32, Expand); 477 setConvertAction(MVT::f64, MVT::f32, Expand); 478 setConvertAction(MVT::f80, MVT::f64, Expand); 479 } 480 481 if (!UnsafeFPMath) { 482 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 483 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 484 } 485 addLegalFPImmediate(APFloat(+0.0)); // FLD0 486 addLegalFPImmediate(APFloat(+1.0)); // FLD1 487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 493 } 494 495 // Long double always uses X87. 496 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 497 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 498 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 499 { 500 bool ignored; 501 APFloat TmpFlt(+0.0); 502 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 503 &ignored); 504 addLegalFPImmediate(TmpFlt); // FLD0 505 TmpFlt.changeSign(); 506 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 507 APFloat TmpFlt2(+1.0); 508 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 509 &ignored); 510 addLegalFPImmediate(TmpFlt2); // FLD1 511 TmpFlt2.changeSign(); 512 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 513 } 514 515 if (!UnsafeFPMath) { 516 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 517 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 518 } 519 520 // Always use a library call for pow. 521 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 522 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 523 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 524 525 setOperationAction(ISD::FLOG, MVT::f80, Expand); 526 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 527 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 528 setOperationAction(ISD::FEXP, MVT::f80, Expand); 529 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 530 531 // First set operation action for all vector types to either promote 532 // (for widening) or expand (for scalarization). Then we will selectively 533 // turn on ones that can be effectively codegen'd. 534 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 535 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 536 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 538 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 540 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 541 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 542 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 543 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 548 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 549 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 550 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 551 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 579 } 580 581 if (!DisableMMX && Subtarget->hasMMX()) { 582 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 583 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 584 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 585 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 586 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 587 588 // FIXME: add MMX packed arithmetics 589 590 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 591 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 592 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 593 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 594 595 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 596 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 597 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 598 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 599 600 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 601 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 602 603 setOperationAction(ISD::AND, MVT::v8i8, Promote); 604 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 605 setOperationAction(ISD::AND, MVT::v4i16, Promote); 606 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 607 setOperationAction(ISD::AND, MVT::v2i32, Promote); 608 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 609 setOperationAction(ISD::AND, MVT::v1i64, Legal); 610 611 setOperationAction(ISD::OR, MVT::v8i8, Promote); 612 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 613 setOperationAction(ISD::OR, MVT::v4i16, Promote); 614 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 615 setOperationAction(ISD::OR, MVT::v2i32, Promote); 616 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 617 setOperationAction(ISD::OR, MVT::v1i64, Legal); 618 619 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 620 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 621 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 622 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 623 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 624 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 625 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 626 627 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 628 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 629 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 630 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 631 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 632 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 633 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 634 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 635 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 636 637 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 638 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 640 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 641 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 642 643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 647 648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 652 653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 654 655 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 656 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 657 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 658 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 659 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 660 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 661 } 662 663 if (Subtarget->hasSSE1()) { 664 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 665 666 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 667 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 668 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 669 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 670 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 671 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 672 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 673 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 675 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 676 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 677 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 678 } 679 680 if (Subtarget->hasSSE2()) { 681 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 682 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 683 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 684 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 685 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 686 687 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 688 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 689 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 690 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 691 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 692 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 693 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 694 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 695 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 696 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 697 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 698 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 699 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 700 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 701 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 702 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 703 704 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 705 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 706 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 707 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 708 709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 714 715 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 716 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 717 MVT VT = (MVT::SimpleValueType)i; 718 // Do not attempt to custom lower non-power-of-2 vectors 719 if (!isPowerOf2_32(VT.getVectorNumElements())) 720 continue; 721 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 722 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 724 } 725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 726 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 728 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 729 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 731 if (Subtarget->is64Bit()) { 732 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 733 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 734 } 735 736 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 737 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 738 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); 739 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64); 740 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); 741 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64); 742 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); 743 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64); 744 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); 745 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64); 746 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); 747 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64); 748 } 749 750 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 751 752 // Custom lower v2i64 and v2f64 selects. 753 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 754 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 755 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 756 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 757 758 } 759 760 if (Subtarget->hasSSE41()) { 761 // FIXME: Do we need to handle scalar-to-vector here? 762 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 763 764 // i8 and i16 vectors are custom , because the source register and source 765 // source memory operand types are not the same width. f32 vectors are 766 // custom since the immediate controlling the insert encodes additional 767 // information. 768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 772 773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 777 778 if (Subtarget->is64Bit()) { 779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 781 } 782 } 783 784 if (Subtarget->hasSSE42()) { 785 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 786 } 787 788 // We want to custom lower some of our intrinsics. 789 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 790 791 // Add/Sub/Mul with overflow operations are custom lowered. 792 setOperationAction(ISD::SADDO, MVT::i32, Custom); 793 setOperationAction(ISD::SADDO, MVT::i64, Custom); 794 setOperationAction(ISD::UADDO, MVT::i32, Custom); 795 setOperationAction(ISD::UADDO, MVT::i64, Custom); 796 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 797 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 798 setOperationAction(ISD::USUBO, MVT::i32, Custom); 799 setOperationAction(ISD::USUBO, MVT::i64, Custom); 800 setOperationAction(ISD::SMULO, MVT::i32, Custom); 801 setOperationAction(ISD::SMULO, MVT::i64, Custom); 802 setOperationAction(ISD::UMULO, MVT::i32, Custom); 803 setOperationAction(ISD::UMULO, MVT::i64, Custom); 804 805 // We have target-specific dag combine patterns for the following nodes: 806 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 807 setTargetDAGCombine(ISD::BUILD_VECTOR); 808 setTargetDAGCombine(ISD::SELECT); 809 setTargetDAGCombine(ISD::SHL); 810 setTargetDAGCombine(ISD::SRA); 811 setTargetDAGCombine(ISD::SRL); 812 setTargetDAGCombine(ISD::STORE); 813 814 computeRegisterProperties(); 815 816 // FIXME: These should be based on subtarget info. Plus, the values should 817 // be smaller when we are in optimizing for size mode. 818 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 819 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 820 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 821 allowUnalignedMemoryAccesses = true; // x86 supports it! 822 setPrefLoopAlignment(16); 823} 824 825 826MVT X86TargetLowering::getSetCCResultType(MVT VT) const { 827 return MVT::i8; 828} 829 830 831/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 832/// the desired ByVal argument alignment. 833static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 834 if (MaxAlign == 16) 835 return; 836 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 837 if (VTy->getBitWidth() == 128) 838 MaxAlign = 16; 839 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 840 unsigned EltAlign = 0; 841 getMaxByValAlign(ATy->getElementType(), EltAlign); 842 if (EltAlign > MaxAlign) 843 MaxAlign = EltAlign; 844 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 845 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 846 unsigned EltAlign = 0; 847 getMaxByValAlign(STy->getElementType(i), EltAlign); 848 if (EltAlign > MaxAlign) 849 MaxAlign = EltAlign; 850 if (MaxAlign == 16) 851 break; 852 } 853 } 854 return; 855} 856 857/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 858/// function arguments in the caller parameter area. For X86, aggregates 859/// that contain SSE vectors are placed at 16-byte boundaries while the rest 860/// are at 4-byte boundaries. 861unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 862 if (Subtarget->is64Bit()) { 863 // Max of 8 and alignment of type. 864 unsigned TyAlign = TD->getABITypeAlignment(Ty); 865 if (TyAlign > 8) 866 return TyAlign; 867 return 8; 868 } 869 870 unsigned Align = 4; 871 if (Subtarget->hasSSE1()) 872 getMaxByValAlign(Ty, Align); 873 return Align; 874} 875 876/// getOptimalMemOpType - Returns the target specific optimal type for load 877/// and store operations as a result of memset, memcpy, and memmove 878/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 879/// determining it. 880MVT 881X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 882 bool isSrcConst, bool isSrcStr) const { 883 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 884 // linux. This is because the stack realignment code can't handle certain 885 // cases like PR2962. This should be removed when PR2962 is fixed. 886 if (Subtarget->getStackAlignment() >= 16) { 887 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 888 return MVT::v4i32; 889 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 890 return MVT::v4f32; 891 } 892 if (Subtarget->is64Bit() && Size >= 8) 893 return MVT::i64; 894 return MVT::i32; 895} 896 897 898/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 899/// jumptable. 900SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 901 SelectionDAG &DAG) const { 902 if (usesGlobalOffsetTable()) 903 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 904 if (!Subtarget->isPICStyleRIPRel()) 905 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()); 906 return Table; 907} 908 909//===----------------------------------------------------------------------===// 910// Return Value Calling Convention Implementation 911//===----------------------------------------------------------------------===// 912 913#include "X86GenCallingConv.inc" 914 915/// LowerRET - Lower an ISD::RET node. 916SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 917 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 918 919 SmallVector<CCValAssign, 16> RVLocs; 920 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 921 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 922 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 923 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86); 924 925 // If this is the first return lowered for this function, add the regs to the 926 // liveout set for the function. 927 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 928 for (unsigned i = 0; i != RVLocs.size(); ++i) 929 if (RVLocs[i].isRegLoc()) 930 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 931 } 932 SDValue Chain = Op.getOperand(0); 933 934 // Handle tail call return. 935 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); 936 if (Chain.getOpcode() == X86ISD::TAILCALL) { 937 SDValue TailCall = Chain; 938 SDValue TargetAddress = TailCall.getOperand(1); 939 SDValue StackAdjustment = TailCall.getOperand(2); 940 assert(((TargetAddress.getOpcode() == ISD::Register && 941 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX || 942 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || 943 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 944 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 945 "Expecting an global address, external symbol, or register"); 946 assert(StackAdjustment.getOpcode() == ISD::Constant && 947 "Expecting a const value"); 948 949 SmallVector<SDValue,8> Operands; 950 Operands.push_back(Chain.getOperand(0)); 951 Operands.push_back(TargetAddress); 952 Operands.push_back(StackAdjustment); 953 // Copy registers used by the call. Last operand is a flag so it is not 954 // copied. 955 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 956 Operands.push_back(Chain.getOperand(i)); 957 } 958 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], 959 Operands.size()); 960 } 961 962 // Regular return. 963 SDValue Flag; 964 965 SmallVector<SDValue, 6> RetOps; 966 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 967 // Operand #1 = Bytes To Pop 968 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 969 970 // Copy the result values into the output registers. 971 for (unsigned i = 0; i != RVLocs.size(); ++i) { 972 CCValAssign &VA = RVLocs[i]; 973 assert(VA.isRegLoc() && "Can only return in registers!"); 974 SDValue ValToCopy = Op.getOperand(i*2+1); 975 976 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 977 // the RET instruction and handled by the FP Stackifier. 978 if (RVLocs[i].getLocReg() == X86::ST0 || 979 RVLocs[i].getLocReg() == X86::ST1) { 980 // If this is a copy from an xmm register to ST(0), use an FPExtend to 981 // change the value to the FP stack register class. 982 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) 983 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); 984 RetOps.push_back(ValToCopy); 985 // Don't emit a copytoreg. 986 continue; 987 } 988 989 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); 990 Flag = Chain.getValue(1); 991 } 992 993 // The x86-64 ABI for returning structs by value requires that we copy 994 // the sret argument into %rax for the return. We saved the argument into 995 // a virtual register in the entry block, so now we copy the value out 996 // and into %rax. 997 if (Subtarget->is64Bit() && 998 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 999 MachineFunction &MF = DAG.getMachineFunction(); 1000 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1001 unsigned Reg = FuncInfo->getSRetReturnReg(); 1002 if (!Reg) { 1003 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1004 FuncInfo->setSRetReturnReg(Reg); 1005 } 1006 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); 1007 1008 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); 1009 Flag = Chain.getValue(1); 1010 } 1011 1012 RetOps[0] = Chain; // Update chain. 1013 1014 // Add the flag if we have it. 1015 if (Flag.getNode()) 1016 RetOps.push_back(Flag); 1017 1018 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); 1019} 1020 1021 1022/// LowerCallResult - Lower the result values of an ISD::CALL into the 1023/// appropriate copies out of appropriate physical registers. This assumes that 1024/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 1025/// being lowered. The returns a SDNode with the same number of values as the 1026/// ISD::CALL. 1027SDNode *X86TargetLowering:: 1028LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 1029 unsigned CallingConv, SelectionDAG &DAG) { 1030 1031 // Assign locations to each value returned by this call. 1032 SmallVector<CCValAssign, 16> RVLocs; 1033 bool isVarArg = TheCall->isVarArg(); 1034 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 1035 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 1036 1037 SmallVector<SDValue, 8> ResultVals; 1038 1039 // Copy all of the result registers out of their specified physreg. 1040 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1041 MVT CopyVT = RVLocs[i].getValVT(); 1042 1043 // If this is a call to a function that returns an fp value on the floating 1044 // point stack, but where we prefer to use the value in xmm registers, copy 1045 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1046 if ((RVLocs[i].getLocReg() == X86::ST0 || 1047 RVLocs[i].getLocReg() == X86::ST1) && 1048 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 1049 CopyVT = MVT::f80; 1050 } 1051 1052 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 1053 CopyVT, InFlag).getValue(1); 1054 SDValue Val = Chain.getValue(0); 1055 InFlag = Chain.getValue(2); 1056 1057 if (CopyVT != RVLocs[i].getValVT()) { 1058 // Round the F80 the right size, which also moves to the appropriate xmm 1059 // register. 1060 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, 1061 // This truncation won't change the value. 1062 DAG.getIntPtrConstant(1)); 1063 } 1064 1065 ResultVals.push_back(Val); 1066 } 1067 1068 // Merge everything together with a MERGE_VALUES node. 1069 ResultVals.push_back(Chain); 1070 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], 1071 ResultVals.size()).getNode(); 1072} 1073 1074 1075//===----------------------------------------------------------------------===// 1076// C & StdCall & Fast Calling Convention implementation 1077//===----------------------------------------------------------------------===// 1078// StdCall calling convention seems to be standard for many Windows' API 1079// routines and around. It differs from C calling convention just a little: 1080// callee should clean up the stack, not caller. Symbols should be also 1081// decorated in some fancy way :) It doesn't support any vector arguments. 1082// For info on fast calling convention see Fast Calling Convention (tail call) 1083// implementation LowerX86_32FastCCCallTo. 1084 1085/// AddLiveIn - This helper function adds the specified physical register to the 1086/// MachineFunction as a live in value. It also creates a corresponding virtual 1087/// register for it. 1088static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 1089 const TargetRegisterClass *RC) { 1090 assert(RC->contains(PReg) && "Not the correct regclass!"); 1091 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1092 MF.getRegInfo().addLiveIn(PReg, VReg); 1093 return VReg; 1094} 1095 1096/// CallIsStructReturn - Determines whether a CALL node uses struct return 1097/// semantics. 1098static bool CallIsStructReturn(CallSDNode *TheCall) { 1099 unsigned NumOps = TheCall->getNumArgs(); 1100 if (!NumOps) 1101 return false; 1102 1103 return TheCall->getArgFlags(0).isSRet(); 1104} 1105 1106/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 1107/// return semantics. 1108static bool ArgsAreStructReturn(SDValue Op) { 1109 unsigned NumArgs = Op.getNode()->getNumValues() - 1; 1110 if (!NumArgs) 1111 return false; 1112 1113 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 1114} 1115 1116/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires 1117/// the callee to pop its own arguments. Callee pop is necessary to support tail 1118/// calls. 1119bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) { 1120 if (IsVarArg) 1121 return false; 1122 1123 switch (CallingConv) { 1124 default: 1125 return false; 1126 case CallingConv::X86_StdCall: 1127 return !Subtarget->is64Bit(); 1128 case CallingConv::X86_FastCall: 1129 return !Subtarget->is64Bit(); 1130 case CallingConv::Fast: 1131 return PerformTailCallOpt; 1132 } 1133} 1134 1135/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1136/// given CallingConvention value. 1137CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { 1138 if (Subtarget->is64Bit()) { 1139 if (Subtarget->isTargetWin64()) 1140 return CC_X86_Win64_C; 1141 else if (CC == CallingConv::Fast && PerformTailCallOpt) 1142 return CC_X86_64_TailCall; 1143 else 1144 return CC_X86_64_C; 1145 } 1146 1147 if (CC == CallingConv::X86_FastCall) 1148 return CC_X86_32_FastCall; 1149 else if (CC == CallingConv::Fast) 1150 return CC_X86_32_FastCC; 1151 else 1152 return CC_X86_32_C; 1153} 1154 1155/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1156/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1157NameDecorationStyle 1158X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { 1159 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1160 if (CC == CallingConv::X86_FastCall) 1161 return FastCall; 1162 else if (CC == CallingConv::X86_StdCall) 1163 return StdCall; 1164 return None; 1165} 1166 1167 1168/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1169/// in a register before calling. 1170bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1171 return !IsTailCall && !Is64Bit && 1172 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1173 Subtarget->isPICStyleGOT(); 1174} 1175 1176/// CallRequiresFnAddressInReg - Check whether the call requires the function 1177/// address to be loaded in a register. 1178bool 1179X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1180 return !Is64Bit && IsTailCall && 1181 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1182 Subtarget->isPICStyleGOT(); 1183} 1184 1185/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1186/// by "Src" to address "Dst" with size and alignment information specified by 1187/// the specific parameter attribute. The copy will be passed as a byval 1188/// function parameter. 1189static SDValue 1190CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1191 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { 1192 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1193 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), 1194 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1195} 1196 1197SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, 1198 const CCValAssign &VA, 1199 MachineFrameInfo *MFI, 1200 unsigned CC, 1201 SDValue Root, unsigned i) { 1202 // Create the nodes corresponding to a load from this parameter slot. 1203 ISD::ArgFlagsTy Flags = 1204 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1205 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1206 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1207 1208 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1209 // changed with more analysis. 1210 // In case of tail call optimization mark all arguments mutable. Since they 1211 // could be overwritten by lowering of arguments in case of a tail call. 1212 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1213 VA.getLocMemOffset(), isImmutable); 1214 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1215 if (Flags.isByVal()) 1216 return FIN; 1217 return DAG.getLoad(VA.getValVT(), Root, FIN, 1218 PseudoSourceValue::getFixedStack(FI), 0); 1219} 1220 1221SDValue 1222X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1223 MachineFunction &MF = DAG.getMachineFunction(); 1224 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1225 1226 const Function* Fn = MF.getFunction(); 1227 if (Fn->hasExternalLinkage() && 1228 Subtarget->isTargetCygMing() && 1229 Fn->getName() == "main") 1230 FuncInfo->setForceFramePointer(true); 1231 1232 // Decorate the function name. 1233 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1234 1235 MachineFrameInfo *MFI = MF.getFrameInfo(); 1236 SDValue Root = Op.getOperand(0); 1237 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1238 unsigned CC = MF.getFunction()->getCallingConv(); 1239 bool Is64Bit = Subtarget->is64Bit(); 1240 bool IsWin64 = Subtarget->isTargetWin64(); 1241 1242 assert(!(isVarArg && CC == CallingConv::Fast) && 1243 "Var args not supported with calling convention fastcc"); 1244 1245 // Assign locations to all of the incoming arguments. 1246 SmallVector<CCValAssign, 16> ArgLocs; 1247 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1248 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC)); 1249 1250 SmallVector<SDValue, 8> ArgValues; 1251 unsigned LastVal = ~0U; 1252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1253 CCValAssign &VA = ArgLocs[i]; 1254 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1255 // places. 1256 assert(VA.getValNo() != LastVal && 1257 "Don't support value assigned to multiple locs yet"); 1258 LastVal = VA.getValNo(); 1259 1260 if (VA.isRegLoc()) { 1261 MVT RegVT = VA.getLocVT(); 1262 TargetRegisterClass *RC = NULL; 1263 if (RegVT == MVT::i32) 1264 RC = X86::GR32RegisterClass; 1265 else if (Is64Bit && RegVT == MVT::i64) 1266 RC = X86::GR64RegisterClass; 1267 else if (RegVT == MVT::f32) 1268 RC = X86::FR32RegisterClass; 1269 else if (RegVT == MVT::f64) 1270 RC = X86::FR64RegisterClass; 1271 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1272 RC = X86::VR128RegisterClass; 1273 else if (RegVT.isVector()) { 1274 assert(RegVT.getSizeInBits() == 64); 1275 if (!Is64Bit) 1276 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. 1277 else { 1278 // Darwin calling convention passes MMX values in either GPRs or 1279 // XMMs in x86-64. Other targets pass them in memory. 1280 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { 1281 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. 1282 RegVT = MVT::v2i64; 1283 } else { 1284 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. 1285 RegVT = MVT::i64; 1286 } 1287 } 1288 } else { 1289 assert(0 && "Unknown argument type!"); 1290 } 1291 1292 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1293 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 1294 1295 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1296 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1297 // right size. 1298 if (VA.getLocInfo() == CCValAssign::SExt) 1299 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 1300 DAG.getValueType(VA.getValVT())); 1301 else if (VA.getLocInfo() == CCValAssign::ZExt) 1302 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 1303 DAG.getValueType(VA.getValVT())); 1304 1305 if (VA.getLocInfo() != CCValAssign::Full) 1306 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 1307 1308 // Handle MMX values passed in GPRs. 1309 if (Is64Bit && RegVT != VA.getLocVT()) { 1310 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) 1311 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1312 else if (RC == X86::VR128RegisterClass) { 1313 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, 1314 DAG.getConstant(0, MVT::i64)); 1315 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1316 } 1317 } 1318 1319 ArgValues.push_back(ArgValue); 1320 } else { 1321 assert(VA.isMemLoc()); 1322 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1323 } 1324 } 1325 1326 // The x86-64 ABI for returning structs by value requires that we copy 1327 // the sret argument into %rax for the return. Save the argument into 1328 // a virtual register so that we can access it from the return points. 1329 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1330 MachineFunction &MF = DAG.getMachineFunction(); 1331 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1332 unsigned Reg = FuncInfo->getSRetReturnReg(); 1333 if (!Reg) { 1334 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1335 FuncInfo->setSRetReturnReg(Reg); 1336 } 1337 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); 1338 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); 1339 } 1340 1341 unsigned StackSize = CCInfo.getNextStackOffset(); 1342 // align stack specially for tail calls 1343 if (PerformTailCallOpt && CC == CallingConv::Fast) 1344 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1345 1346 // If the function takes variable number of arguments, make a frame index for 1347 // the start of the first vararg value... for expansion of llvm.va_start. 1348 if (isVarArg) { 1349 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1350 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1351 } 1352 if (Is64Bit) { 1353 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1354 1355 // FIXME: We should really autogenerate these arrays 1356 static const unsigned GPR64ArgRegsWin64[] = { 1357 X86::RCX, X86::RDX, X86::R8, X86::R9 1358 }; 1359 static const unsigned XMMArgRegsWin64[] = { 1360 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1361 }; 1362 static const unsigned GPR64ArgRegs64Bit[] = { 1363 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1364 }; 1365 static const unsigned XMMArgRegs64Bit[] = { 1366 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1367 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1368 }; 1369 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1370 1371 if (IsWin64) { 1372 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1373 GPR64ArgRegs = GPR64ArgRegsWin64; 1374 XMMArgRegs = XMMArgRegsWin64; 1375 } else { 1376 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1377 GPR64ArgRegs = GPR64ArgRegs64Bit; 1378 XMMArgRegs = XMMArgRegs64Bit; 1379 } 1380 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1381 TotalNumIntRegs); 1382 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1383 TotalNumXMMRegs); 1384 1385 // For X86-64, if there are vararg parameters that are passed via 1386 // registers, then we must store them to their spots on the stack so they 1387 // may be loaded by deferencing the result of va_next. 1388 VarArgsGPOffset = NumIntRegs * 8; 1389 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1390 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1391 TotalNumXMMRegs * 16, 16); 1392 1393 // Store the integer parameter registers. 1394 SmallVector<SDValue, 8> MemOps; 1395 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1396 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1397 DAG.getIntPtrConstant(VarArgsGPOffset)); 1398 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1399 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1400 X86::GR64RegisterClass); 1401 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1402 SDValue Store = 1403 DAG.getStore(Val.getValue(1), Val, FIN, 1404 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1405 MemOps.push_back(Store); 1406 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1407 DAG.getIntPtrConstant(8)); 1408 } 1409 1410 // Now store the XMM (fp + vector) parameter registers. 1411 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1412 DAG.getIntPtrConstant(VarArgsFPOffset)); 1413 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1414 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1415 X86::VR128RegisterClass); 1416 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1417 SDValue Store = 1418 DAG.getStore(Val.getValue(1), Val, FIN, 1419 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1420 MemOps.push_back(Store); 1421 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1422 DAG.getIntPtrConstant(16)); 1423 } 1424 if (!MemOps.empty()) 1425 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1426 &MemOps[0], MemOps.size()); 1427 } 1428 } 1429 1430 ArgValues.push_back(Root); 1431 1432 // Some CCs need callee pop. 1433 if (IsCalleePop(isVarArg, CC)) { 1434 BytesToPopOnReturn = StackSize; // Callee pops everything. 1435 BytesCallerReserves = 0; 1436 } else { 1437 BytesToPopOnReturn = 0; // Callee pops nothing. 1438 // If this is an sret function, the return should pop the hidden pointer. 1439 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op)) 1440 BytesToPopOnReturn = 4; 1441 BytesCallerReserves = StackSize; 1442 } 1443 1444 if (!Is64Bit) { 1445 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1446 if (CC == CallingConv::X86_FastCall) 1447 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1448 } 1449 1450 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1451 1452 // Return the new list of results. 1453 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), 1454 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 1455} 1456 1457SDValue 1458X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 1459 const SDValue &StackPtr, 1460 const CCValAssign &VA, 1461 SDValue Chain, 1462 SDValue Arg, ISD::ArgFlagsTy Flags) { 1463 unsigned LocMemOffset = VA.getLocMemOffset(); 1464 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1465 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1466 if (Flags.isByVal()) { 1467 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); 1468 } 1469 return DAG.getStore(Chain, Arg, PtrOff, 1470 PseudoSourceValue::getStack(), LocMemOffset); 1471} 1472 1473/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1474/// optimization is performed and it is required. 1475SDValue 1476X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1477 SDValue &OutRetAddr, 1478 SDValue Chain, 1479 bool IsTailCall, 1480 bool Is64Bit, 1481 int FPDiff) { 1482 if (!IsTailCall || FPDiff==0) return Chain; 1483 1484 // Adjust the Return address stack slot. 1485 MVT VT = getPointerTy(); 1486 OutRetAddr = getReturnAddressFrameIndex(DAG); 1487 1488 // Load the "old" Return address. 1489 OutRetAddr = DAG.getLoad(VT, Chain, OutRetAddr, NULL, 0); 1490 return SDValue(OutRetAddr.getNode(), 1); 1491} 1492 1493/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1494/// optimization is performed and it is required (FPDiff!=0). 1495static SDValue 1496EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1497 SDValue Chain, SDValue RetAddrFrIdx, 1498 bool Is64Bit, int FPDiff) { 1499 // Store the return address to the appropriate stack slot. 1500 if (!FPDiff) return Chain; 1501 // Calculate the new stack slot for the return address. 1502 int SlotSize = Is64Bit ? 8 : 4; 1503 int NewReturnAddrFI = 1504 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1505 MVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1506 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1507 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, 1508 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1509 return Chain; 1510} 1511 1512SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 1513 MachineFunction &MF = DAG.getMachineFunction(); 1514 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 1515 SDValue Chain = TheCall->getChain(); 1516 unsigned CC = TheCall->getCallingConv(); 1517 bool isVarArg = TheCall->isVarArg(); 1518 bool IsTailCall = TheCall->isTailCall() && 1519 CC == CallingConv::Fast && PerformTailCallOpt; 1520 SDValue Callee = TheCall->getCallee(); 1521 bool Is64Bit = Subtarget->is64Bit(); 1522 bool IsStructRet = CallIsStructReturn(TheCall); 1523 1524 assert(!(isVarArg && CC == CallingConv::Fast) && 1525 "Var args not supported with calling convention fastcc"); 1526 1527 // Analyze operands of the call, assigning locations to each operand. 1528 SmallVector<CCValAssign, 16> ArgLocs; 1529 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1530 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC)); 1531 1532 // Get a count of how many bytes are to be pushed on the stack. 1533 unsigned NumBytes = CCInfo.getNextStackOffset(); 1534 if (PerformTailCallOpt && CC == CallingConv::Fast) 1535 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1536 1537 int FPDiff = 0; 1538 if (IsTailCall) { 1539 // Lower arguments at fp - stackoffset + fpdiff. 1540 unsigned NumBytesCallerPushed = 1541 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1542 FPDiff = NumBytesCallerPushed - NumBytes; 1543 1544 // Set the delta of movement of the returnaddr stackslot. 1545 // But only set if delta is greater than previous delta. 1546 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1547 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1548 } 1549 1550 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1551 1552 SDValue RetAddrFrIdx; 1553 // Load return adress for tail calls. 1554 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, 1555 FPDiff); 1556 1557 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1558 SmallVector<SDValue, 8> MemOpChains; 1559 SDValue StackPtr; 1560 1561 // Walk the register/memloc assignments, inserting copies/loads. In the case 1562 // of tail call optimization arguments are handle later. 1563 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1564 CCValAssign &VA = ArgLocs[i]; 1565 SDValue Arg = TheCall->getArg(i); 1566 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1567 bool isByVal = Flags.isByVal(); 1568 1569 // Promote the value if needed. 1570 switch (VA.getLocInfo()) { 1571 default: assert(0 && "Unknown loc info!"); 1572 case CCValAssign::Full: break; 1573 case CCValAssign::SExt: 1574 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 1575 break; 1576 case CCValAssign::ZExt: 1577 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1578 break; 1579 case CCValAssign::AExt: 1580 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1581 break; 1582 } 1583 1584 if (VA.isRegLoc()) { 1585 if (Is64Bit) { 1586 MVT RegVT = VA.getLocVT(); 1587 if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1588 switch (VA.getLocReg()) { 1589 default: 1590 break; 1591 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: 1592 case X86::R8: { 1593 // Special case: passing MMX values in GPR registers. 1594 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1595 break; 1596 } 1597 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: 1598 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { 1599 // Special case: passing MMX values in XMM registers. 1600 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1601 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg); 1602 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 1603 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg, 1604 getMOVLMask(2, DAG)); 1605 break; 1606 } 1607 } 1608 } 1609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1610 } else { 1611 if (!IsTailCall || (IsTailCall && isByVal)) { 1612 assert(VA.isMemLoc()); 1613 if (StackPtr.getNode() == 0) 1614 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1615 1616 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 1617 Chain, Arg, Flags)); 1618 } 1619 } 1620 } 1621 1622 if (!MemOpChains.empty()) 1623 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1624 &MemOpChains[0], MemOpChains.size()); 1625 1626 // Build a sequence of copy-to-reg nodes chained together with token chain 1627 // and flag operands which copy the outgoing args into registers. 1628 SDValue InFlag; 1629 // Tail call byval lowering might overwrite argument registers so in case of 1630 // tail call optimization the copies to registers are lowered later. 1631 if (!IsTailCall) 1632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1633 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1634 InFlag); 1635 InFlag = Chain.getValue(1); 1636 } 1637 1638 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1639 // GOT pointer. 1640 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1641 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1642 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1643 InFlag); 1644 InFlag = Chain.getValue(1); 1645 } 1646 // If we are tail calling and generating PIC/GOT style code load the address 1647 // of the callee into ecx. The value in ecx is used as target of the tail 1648 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1649 // calls on PIC/GOT architectures. Normally we would just put the address of 1650 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1651 // restored (since ebx is callee saved) before jumping to the target@PLT. 1652 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1653 // Note: The actual moving to ecx is done further down. 1654 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1655 if (G && !G->getGlobal()->hasHiddenVisibility() && 1656 !G->getGlobal()->hasProtectedVisibility()) 1657 Callee = LowerGlobalAddress(Callee, DAG); 1658 else if (isa<ExternalSymbolSDNode>(Callee)) 1659 Callee = LowerExternalSymbol(Callee,DAG); 1660 } 1661 1662 if (Is64Bit && isVarArg) { 1663 // From AMD64 ABI document: 1664 // For calls that may call functions that use varargs or stdargs 1665 // (prototype-less calls or calls to functions containing ellipsis (...) in 1666 // the declaration) %al is used as hidden argument to specify the number 1667 // of SSE registers used. The contents of %al do not need to match exactly 1668 // the number of registers, but must be an ubound on the number of SSE 1669 // registers used and is in the range 0 - 8 inclusive. 1670 1671 // FIXME: Verify this on Win64 1672 // Count the number of XMM registers allocated. 1673 static const unsigned XMMArgRegs[] = { 1674 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1675 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1676 }; 1677 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1678 1679 Chain = DAG.getCopyToReg(Chain, X86::AL, 1680 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1681 InFlag = Chain.getValue(1); 1682 } 1683 1684 1685 // For tail calls lower the arguments to the 'real' stack slot. 1686 if (IsTailCall) { 1687 SmallVector<SDValue, 8> MemOpChains2; 1688 SDValue FIN; 1689 int FI = 0; 1690 // Do not flag preceeding copytoreg stuff together with the following stuff. 1691 InFlag = SDValue(); 1692 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1693 CCValAssign &VA = ArgLocs[i]; 1694 if (!VA.isRegLoc()) { 1695 assert(VA.isMemLoc()); 1696 SDValue Arg = TheCall->getArg(i); 1697 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1698 // Create frame index. 1699 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1700 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1701 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1702 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1703 1704 if (Flags.isByVal()) { 1705 // Copy relative to framepointer. 1706 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1707 if (StackPtr.getNode() == 0) 1708 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1709 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); 1710 1711 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, 1712 Flags, DAG)); 1713 } else { 1714 // Store relative to framepointer. 1715 MemOpChains2.push_back( 1716 DAG.getStore(Chain, Arg, FIN, 1717 PseudoSourceValue::getFixedStack(FI), 0)); 1718 } 1719 } 1720 } 1721 1722 if (!MemOpChains2.empty()) 1723 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1724 &MemOpChains2[0], MemOpChains2.size()); 1725 1726 // Copy arguments to their registers. 1727 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1728 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1729 InFlag); 1730 InFlag = Chain.getValue(1); 1731 } 1732 InFlag =SDValue(); 1733 1734 // Store the return address to the appropriate stack slot. 1735 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1736 FPDiff); 1737 } 1738 1739 // If the callee is a GlobalAddress node (quite common, every direct call is) 1740 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1742 // We should use extra load for direct calls to dllimported functions in 1743 // non-JIT mode. 1744 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1745 getTargetMachine(), true)) 1746 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(), 1747 G->getOffset()); 1748 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1749 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1750 } else if (IsTailCall) { 1751 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX; 1752 1753 Chain = DAG.getCopyToReg(Chain, 1754 DAG.getRegister(Opc, getPointerTy()), 1755 Callee,InFlag); 1756 Callee = DAG.getRegister(Opc, getPointerTy()); 1757 // Add register as live out. 1758 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1759 } 1760 1761 // Returns a chain & a flag for retval copy to use. 1762 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1763 SmallVector<SDValue, 8> Ops; 1764 1765 if (IsTailCall) { 1766 Ops.push_back(Chain); 1767 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true)); 1768 Ops.push_back(DAG.getIntPtrConstant(0, true)); 1769 if (InFlag.getNode()) 1770 Ops.push_back(InFlag); 1771 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1772 InFlag = Chain.getValue(1); 1773 1774 // Returns a chain & a flag for retval copy to use. 1775 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1776 Ops.clear(); 1777 } 1778 1779 Ops.push_back(Chain); 1780 Ops.push_back(Callee); 1781 1782 if (IsTailCall) 1783 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1784 1785 // Add argument registers to the end of the list so that they are known live 1786 // into the call. 1787 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1788 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1789 RegsToPass[i].second.getValueType())); 1790 1791 // Add an implicit use GOT pointer in EBX. 1792 if (!IsTailCall && !Is64Bit && 1793 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1794 Subtarget->isPICStyleGOT()) 1795 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1796 1797 // Add an implicit use of AL for x86 vararg functions. 1798 if (Is64Bit && isVarArg) 1799 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1800 1801 if (InFlag.getNode()) 1802 Ops.push_back(InFlag); 1803 1804 if (IsTailCall) { 1805 assert(InFlag.getNode() && 1806 "Flag must be set. Depend on flag being set in LowerRET"); 1807 Chain = DAG.getNode(X86ISD::TAILCALL, 1808 TheCall->getVTList(), &Ops[0], Ops.size()); 1809 1810 return SDValue(Chain.getNode(), Op.getResNo()); 1811 } 1812 1813 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); 1814 InFlag = Chain.getValue(1); 1815 1816 // Create the CALLSEQ_END node. 1817 unsigned NumBytesForCalleeToPush; 1818 if (IsCalleePop(isVarArg, CC)) 1819 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1820 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet) 1821 // If this is is a call to a struct-return function, the callee 1822 // pops the hidden struct pointer, so we have to push it back. 1823 // This is common for Darwin/X86, Linux & Mingw32 targets. 1824 NumBytesForCalleeToPush = 4; 1825 else 1826 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1827 1828 // Returns a flag for retval copy to use. 1829 Chain = DAG.getCALLSEQ_END(Chain, 1830 DAG.getIntPtrConstant(NumBytes, true), 1831 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 1832 true), 1833 InFlag); 1834 InFlag = Chain.getValue(1); 1835 1836 // Handle result values, copying them out of physregs into vregs that we 1837 // return. 1838 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 1839 Op.getResNo()); 1840} 1841 1842 1843//===----------------------------------------------------------------------===// 1844// Fast Calling Convention (tail call) implementation 1845//===----------------------------------------------------------------------===// 1846 1847// Like std call, callee cleans arguments, convention except that ECX is 1848// reserved for storing the tail called function address. Only 2 registers are 1849// free for argument passing (inreg). Tail call optimization is performed 1850// provided: 1851// * tailcallopt is enabled 1852// * caller/callee are fastcc 1853// On X86_64 architecture with GOT-style position independent code only local 1854// (within module) calls are supported at the moment. 1855// To keep the stack aligned according to platform abi the function 1856// GetAlignedArgumentStackSize ensures that argument delta is always multiples 1857// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 1858// If a tail called function callee has more arguments than the caller the 1859// caller needs to make sure that there is room to move the RETADDR to. This is 1860// achieved by reserving an area the size of the argument delta right after the 1861// original REtADDR, but before the saved framepointer or the spilled registers 1862// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 1863// stack layout: 1864// arg1 1865// arg2 1866// RETADDR 1867// [ new RETADDR 1868// move area ] 1869// (possible EBP) 1870// ESI 1871// EDI 1872// local1 .. 1873 1874/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 1875/// for a 16 byte align requirement. 1876unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 1877 SelectionDAG& DAG) { 1878 MachineFunction &MF = DAG.getMachineFunction(); 1879 const TargetMachine &TM = MF.getTarget(); 1880 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 1881 unsigned StackAlignment = TFI.getStackAlignment(); 1882 uint64_t AlignMask = StackAlignment - 1; 1883 int64_t Offset = StackSize; 1884 uint64_t SlotSize = TD->getPointerSize(); 1885 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 1886 // Number smaller than 12 so just add the difference. 1887 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 1888 } else { 1889 // Mask out lower bits, add stackalignment once plus the 12 bytes. 1890 Offset = ((~AlignMask) & Offset) + StackAlignment + 1891 (StackAlignment-SlotSize); 1892 } 1893 return Offset; 1894} 1895 1896/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1897/// following the call is a return. A function is eligible if caller/callee 1898/// calling conventions match, currently only fastcc supports tail calls, and 1899/// the function CALL is immediatly followed by a RET. 1900bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 1901 SDValue Ret, 1902 SelectionDAG& DAG) const { 1903 if (!PerformTailCallOpt) 1904 return false; 1905 1906 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 1907 MachineFunction &MF = DAG.getMachineFunction(); 1908 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1909 unsigned CalleeCC= TheCall->getCallingConv(); 1910 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1911 SDValue Callee = TheCall->getCallee(); 1912 // On x86/32Bit PIC/GOT tail calls are supported. 1913 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 1914 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 1915 return true; 1916 1917 // Can only do local tail calls (in same module, hidden or protected) on 1918 // x86_64 PIC/GOT at the moment. 1919 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1920 return G->getGlobal()->hasHiddenVisibility() 1921 || G->getGlobal()->hasProtectedVisibility(); 1922 } 1923 } 1924 1925 return false; 1926} 1927 1928FastISel * 1929X86TargetLowering::createFastISel(MachineFunction &mf, 1930 MachineModuleInfo *mmo, 1931 DwarfWriter *dw, 1932 DenseMap<const Value *, unsigned> &vm, 1933 DenseMap<const BasicBlock *, 1934 MachineBasicBlock *> &bm, 1935 DenseMap<const AllocaInst *, int> &am 1936#ifndef NDEBUG 1937 , SmallSet<Instruction*, 8> &cil 1938#endif 1939 ) { 1940 return X86::createFastISel(mf, mmo, dw, vm, bm, am 1941#ifndef NDEBUG 1942 , cil 1943#endif 1944 ); 1945} 1946 1947 1948//===----------------------------------------------------------------------===// 1949// Other Lowering Hooks 1950//===----------------------------------------------------------------------===// 1951 1952 1953SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1954 MachineFunction &MF = DAG.getMachineFunction(); 1955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1956 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1957 1958 if (ReturnAddrIndex == 0) { 1959 // Set up a frame object for the return address. 1960 uint64_t SlotSize = TD->getPointerSize(); 1961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 1962 FuncInfo->setRAIndex(ReturnAddrIndex); 1963 } 1964 1965 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1966} 1967 1968 1969/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 1970/// specific condition code, returning the condition code and the LHS/RHS of the 1971/// comparison to make. 1972static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1973 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 1974 if (!isFP) { 1975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1976 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1977 // X > -1 -> X == 0, jump !sign. 1978 RHS = DAG.getConstant(0, RHS.getValueType()); 1979 return X86::COND_NS; 1980 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1981 // X < 0 -> X == 0, jump on sign. 1982 return X86::COND_S; 1983 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 1984 // X < 1 -> X <= 0 1985 RHS = DAG.getConstant(0, RHS.getValueType()); 1986 return X86::COND_LE; 1987 } 1988 } 1989 1990 switch (SetCCOpcode) { 1991 default: assert(0 && "Invalid integer condition!"); 1992 case ISD::SETEQ: return X86::COND_E; 1993 case ISD::SETGT: return X86::COND_G; 1994 case ISD::SETGE: return X86::COND_GE; 1995 case ISD::SETLT: return X86::COND_L; 1996 case ISD::SETLE: return X86::COND_LE; 1997 case ISD::SETNE: return X86::COND_NE; 1998 case ISD::SETULT: return X86::COND_B; 1999 case ISD::SETUGT: return X86::COND_A; 2000 case ISD::SETULE: return X86::COND_BE; 2001 case ISD::SETUGE: return X86::COND_AE; 2002 } 2003 } 2004 2005 // First determine if it is required or is profitable to flip the operands. 2006 2007 // If LHS is a foldable load, but RHS is not, flip the condition. 2008 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2009 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2010 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2011 std::swap(LHS, RHS); 2012 } 2013 2014 switch (SetCCOpcode) { 2015 default: break; 2016 case ISD::SETOLT: 2017 case ISD::SETOLE: 2018 case ISD::SETUGT: 2019 case ISD::SETUGE: 2020 std::swap(LHS, RHS); 2021 break; 2022 } 2023 2024 // On a floating point condition, the flags are set as follows: 2025 // ZF PF CF op 2026 // 0 | 0 | 0 | X > Y 2027 // 0 | 0 | 1 | X < Y 2028 // 1 | 0 | 0 | X == Y 2029 // 1 | 1 | 1 | unordered 2030 switch (SetCCOpcode) { 2031 default: assert(0 && "Condcode should be pre-legalized away"); 2032 case ISD::SETUEQ: 2033 case ISD::SETEQ: return X86::COND_E; 2034 case ISD::SETOLT: // flipped 2035 case ISD::SETOGT: 2036 case ISD::SETGT: return X86::COND_A; 2037 case ISD::SETOLE: // flipped 2038 case ISD::SETOGE: 2039 case ISD::SETGE: return X86::COND_AE; 2040 case ISD::SETUGT: // flipped 2041 case ISD::SETULT: 2042 case ISD::SETLT: return X86::COND_B; 2043 case ISD::SETUGE: // flipped 2044 case ISD::SETULE: 2045 case ISD::SETLE: return X86::COND_BE; 2046 case ISD::SETONE: 2047 case ISD::SETNE: return X86::COND_NE; 2048 case ISD::SETUO: return X86::COND_P; 2049 case ISD::SETO: return X86::COND_NP; 2050 } 2051} 2052 2053/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2054/// code. Current x86 isa includes the following FP cmov instructions: 2055/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2056static bool hasFPCMov(unsigned X86CC) { 2057 switch (X86CC) { 2058 default: 2059 return false; 2060 case X86::COND_B: 2061 case X86::COND_BE: 2062 case X86::COND_E: 2063 case X86::COND_P: 2064 case X86::COND_A: 2065 case X86::COND_AE: 2066 case X86::COND_NE: 2067 case X86::COND_NP: 2068 return true; 2069 } 2070} 2071 2072/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2073/// true if Op is undef or if its value falls within the specified range (L, H]. 2074static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) { 2075 if (Op.getOpcode() == ISD::UNDEF) 2076 return true; 2077 2078 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue(); 2079 return (Val >= Low && Val < Hi); 2080} 2081 2082/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2083/// true if Op is undef or if its value equal to the specified value. 2084static bool isUndefOrEqual(SDValue Op, unsigned Val) { 2085 if (Op.getOpcode() == ISD::UNDEF) 2086 return true; 2087 return cast<ConstantSDNode>(Op)->getZExtValue() == Val; 2088} 2089 2090/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2091/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2092bool X86::isPSHUFDMask(SDNode *N) { 2093 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2094 2095 if (N->getNumOperands() != 2 && N->getNumOperands() != 4) 2096 return false; 2097 2098 // Check if the value doesn't reference the second vector. 2099 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2100 SDValue Arg = N->getOperand(i); 2101 if (Arg.getOpcode() == ISD::UNDEF) continue; 2102 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2103 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e) 2104 return false; 2105 } 2106 2107 return true; 2108} 2109 2110/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2111/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2112bool X86::isPSHUFHWMask(SDNode *N) { 2113 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2114 2115 if (N->getNumOperands() != 8) 2116 return false; 2117 2118 // Lower quadword copied in order. 2119 for (unsigned i = 0; i != 4; ++i) { 2120 SDValue Arg = N->getOperand(i); 2121 if (Arg.getOpcode() == ISD::UNDEF) continue; 2122 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2123 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i) 2124 return false; 2125 } 2126 2127 // Upper quadword shuffled. 2128 for (unsigned i = 4; i != 8; ++i) { 2129 SDValue Arg = N->getOperand(i); 2130 if (Arg.getOpcode() == ISD::UNDEF) continue; 2131 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2132 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2133 if (Val < 4 || Val > 7) 2134 return false; 2135 } 2136 2137 return true; 2138} 2139 2140/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2141/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2142bool X86::isPSHUFLWMask(SDNode *N) { 2143 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2144 2145 if (N->getNumOperands() != 8) 2146 return false; 2147 2148 // Upper quadword copied in order. 2149 for (unsigned i = 4; i != 8; ++i) 2150 if (!isUndefOrEqual(N->getOperand(i), i)) 2151 return false; 2152 2153 // Lower quadword shuffled. 2154 for (unsigned i = 0; i != 4; ++i) 2155 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2156 return false; 2157 2158 return true; 2159} 2160 2161/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2162/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2163template<class SDOperand> 2164static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) { 2165 if (NumElems != 2 && NumElems != 4) return false; 2166 2167 unsigned Half = NumElems / 2; 2168 for (unsigned i = 0; i < Half; ++i) 2169 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 2170 return false; 2171 for (unsigned i = Half; i < NumElems; ++i) 2172 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 2173 return false; 2174 2175 return true; 2176} 2177 2178bool X86::isSHUFPMask(SDNode *N) { 2179 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2180 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 2181} 2182 2183/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2184/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2185/// half elements to come from vector 1 (which would equal the dest.) and 2186/// the upper half to come from vector 2. 2187template<class SDOperand> 2188static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) { 2189 if (NumOps != 2 && NumOps != 4) return false; 2190 2191 unsigned Half = NumOps / 2; 2192 for (unsigned i = 0; i < Half; ++i) 2193 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 2194 return false; 2195 for (unsigned i = Half; i < NumOps; ++i) 2196 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 2197 return false; 2198 return true; 2199} 2200 2201static bool isCommutedSHUFP(SDNode *N) { 2202 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2203 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 2204} 2205 2206/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2207/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2208bool X86::isMOVHLPSMask(SDNode *N) { 2209 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2210 2211 if (N->getNumOperands() != 4) 2212 return false; 2213 2214 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2215 return isUndefOrEqual(N->getOperand(0), 6) && 2216 isUndefOrEqual(N->getOperand(1), 7) && 2217 isUndefOrEqual(N->getOperand(2), 2) && 2218 isUndefOrEqual(N->getOperand(3), 3); 2219} 2220 2221/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2222/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2223/// <2, 3, 2, 3> 2224bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2225 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2226 2227 if (N->getNumOperands() != 4) 2228 return false; 2229 2230 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2231 return isUndefOrEqual(N->getOperand(0), 2) && 2232 isUndefOrEqual(N->getOperand(1), 3) && 2233 isUndefOrEqual(N->getOperand(2), 2) && 2234 isUndefOrEqual(N->getOperand(3), 3); 2235} 2236 2237/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2238/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2239bool X86::isMOVLPMask(SDNode *N) { 2240 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2241 2242 unsigned NumElems = N->getNumOperands(); 2243 if (NumElems != 2 && NumElems != 4) 2244 return false; 2245 2246 for (unsigned i = 0; i < NumElems/2; ++i) 2247 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2248 return false; 2249 2250 for (unsigned i = NumElems/2; i < NumElems; ++i) 2251 if (!isUndefOrEqual(N->getOperand(i), i)) 2252 return false; 2253 2254 return true; 2255} 2256 2257/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2258/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2259/// and MOVLHPS. 2260bool X86::isMOVHPMask(SDNode *N) { 2261 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2262 2263 unsigned NumElems = N->getNumOperands(); 2264 if (NumElems != 2 && NumElems != 4) 2265 return false; 2266 2267 for (unsigned i = 0; i < NumElems/2; ++i) 2268 if (!isUndefOrEqual(N->getOperand(i), i)) 2269 return false; 2270 2271 for (unsigned i = 0; i < NumElems/2; ++i) { 2272 SDValue Arg = N->getOperand(i + NumElems/2); 2273 if (!isUndefOrEqual(Arg, i + NumElems)) 2274 return false; 2275 } 2276 2277 return true; 2278} 2279 2280/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2281/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2282template<class SDOperand> 2283bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts, 2284 bool V2IsSplat = false) { 2285 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2286 return false; 2287 2288 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2289 SDValue BitI = Elts[i]; 2290 SDValue BitI1 = Elts[i+1]; 2291 if (!isUndefOrEqual(BitI, j)) 2292 return false; 2293 if (V2IsSplat) { 2294 if (isUndefOrEqual(BitI1, NumElts)) 2295 return false; 2296 } else { 2297 if (!isUndefOrEqual(BitI1, j + NumElts)) 2298 return false; 2299 } 2300 } 2301 2302 return true; 2303} 2304 2305bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2306 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2307 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2308} 2309 2310/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2311/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2312template<class SDOperand> 2313bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts, 2314 bool V2IsSplat = false) { 2315 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2316 return false; 2317 2318 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2319 SDValue BitI = Elts[i]; 2320 SDValue BitI1 = Elts[i+1]; 2321 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2322 return false; 2323 if (V2IsSplat) { 2324 if (isUndefOrEqual(BitI1, NumElts)) 2325 return false; 2326 } else { 2327 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2328 return false; 2329 } 2330 } 2331 2332 return true; 2333} 2334 2335bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2336 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2337 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2338} 2339 2340/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2341/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2342/// <0, 0, 1, 1> 2343bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2344 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2345 2346 unsigned NumElems = N->getNumOperands(); 2347 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2348 return false; 2349 2350 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2351 SDValue BitI = N->getOperand(i); 2352 SDValue BitI1 = N->getOperand(i+1); 2353 2354 if (!isUndefOrEqual(BitI, j)) 2355 return false; 2356 if (!isUndefOrEqual(BitI1, j)) 2357 return false; 2358 } 2359 2360 return true; 2361} 2362 2363/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2364/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2365/// <2, 2, 3, 3> 2366bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { 2367 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2368 2369 unsigned NumElems = N->getNumOperands(); 2370 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2371 return false; 2372 2373 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2374 SDValue BitI = N->getOperand(i); 2375 SDValue BitI1 = N->getOperand(i + 1); 2376 2377 if (!isUndefOrEqual(BitI, j)) 2378 return false; 2379 if (!isUndefOrEqual(BitI1, j)) 2380 return false; 2381 } 2382 2383 return true; 2384} 2385 2386/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2387/// specifies a shuffle of elements that is suitable for input to MOVSS, 2388/// MOVSD, and MOVD, i.e. setting the lowest element. 2389template<class SDOperand> 2390static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) { 2391 if (NumElts != 2 && NumElts != 4) 2392 return false; 2393 2394 if (!isUndefOrEqual(Elts[0], NumElts)) 2395 return false; 2396 2397 for (unsigned i = 1; i < NumElts; ++i) { 2398 if (!isUndefOrEqual(Elts[i], i)) 2399 return false; 2400 } 2401 2402 return true; 2403} 2404 2405bool X86::isMOVLMask(SDNode *N) { 2406 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2407 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 2408} 2409 2410/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2411/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2412/// element of vector 2 and the other elements to come from vector 1 in order. 2413template<class SDOperand> 2414static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps, 2415 bool V2IsSplat = false, 2416 bool V2IsUndef = false) { 2417 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2418 return false; 2419 2420 if (!isUndefOrEqual(Ops[0], 0)) 2421 return false; 2422 2423 for (unsigned i = 1; i < NumOps; ++i) { 2424 SDValue Arg = Ops[i]; 2425 if (!(isUndefOrEqual(Arg, i+NumOps) || 2426 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 2427 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 2428 return false; 2429 } 2430 2431 return true; 2432} 2433 2434static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2435 bool V2IsUndef = false) { 2436 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2437 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 2438 V2IsSplat, V2IsUndef); 2439} 2440 2441/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2442/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2443bool X86::isMOVSHDUPMask(SDNode *N) { 2444 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2445 2446 if (N->getNumOperands() != 4) 2447 return false; 2448 2449 // Expect 1, 1, 3, 3 2450 for (unsigned i = 0; i < 2; ++i) { 2451 SDValue Arg = N->getOperand(i); 2452 if (Arg.getOpcode() == ISD::UNDEF) continue; 2453 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2454 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2455 if (Val != 1) return false; 2456 } 2457 2458 bool HasHi = false; 2459 for (unsigned i = 2; i < 4; ++i) { 2460 SDValue Arg = N->getOperand(i); 2461 if (Arg.getOpcode() == ISD::UNDEF) continue; 2462 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2463 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2464 if (Val != 3) return false; 2465 HasHi = true; 2466 } 2467 2468 // Don't use movshdup if it can be done with a shufps. 2469 return HasHi; 2470} 2471 2472/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2473/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2474bool X86::isMOVSLDUPMask(SDNode *N) { 2475 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2476 2477 if (N->getNumOperands() != 4) 2478 return false; 2479 2480 // Expect 0, 0, 2, 2 2481 for (unsigned i = 0; i < 2; ++i) { 2482 SDValue Arg = N->getOperand(i); 2483 if (Arg.getOpcode() == ISD::UNDEF) continue; 2484 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2485 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2486 if (Val != 0) return false; 2487 } 2488 2489 bool HasHi = false; 2490 for (unsigned i = 2; i < 4; ++i) { 2491 SDValue Arg = N->getOperand(i); 2492 if (Arg.getOpcode() == ISD::UNDEF) continue; 2493 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2494 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2495 if (Val != 2) return false; 2496 HasHi = true; 2497 } 2498 2499 // Don't use movshdup if it can be done with a shufps. 2500 return HasHi; 2501} 2502 2503/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand 2504/// specifies a identity operation on the LHS or RHS. 2505static bool isIdentityMask(SDNode *N, bool RHS = false) { 2506 unsigned NumElems = N->getNumOperands(); 2507 for (unsigned i = 0; i < NumElems; ++i) 2508 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) 2509 return false; 2510 return true; 2511} 2512 2513/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2514/// a splat of a single element. 2515static bool isSplatMask(SDNode *N) { 2516 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2517 2518 // This is a splat operation if each element of the permute is the same, and 2519 // if the value doesn't reference the second vector. 2520 unsigned NumElems = N->getNumOperands(); 2521 SDValue ElementBase; 2522 unsigned i = 0; 2523 for (; i != NumElems; ++i) { 2524 SDValue Elt = N->getOperand(i); 2525 if (isa<ConstantSDNode>(Elt)) { 2526 ElementBase = Elt; 2527 break; 2528 } 2529 } 2530 2531 if (!ElementBase.getNode()) 2532 return false; 2533 2534 for (; i != NumElems; ++i) { 2535 SDValue Arg = N->getOperand(i); 2536 if (Arg.getOpcode() == ISD::UNDEF) continue; 2537 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2538 if (Arg != ElementBase) return false; 2539 } 2540 2541 // Make sure it is a splat of the first vector operand. 2542 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems; 2543} 2544 2545/// getSplatMaskEltNo - Given a splat mask, return the index to the element 2546/// we want to splat. 2547static SDValue getSplatMaskEltNo(SDNode *N) { 2548 assert(isSplatMask(N) && "Not a splat mask"); 2549 unsigned NumElems = N->getNumOperands(); 2550 SDValue ElementBase; 2551 unsigned i = 0; 2552 for (; i != NumElems; ++i) { 2553 SDValue Elt = N->getOperand(i); 2554 if (isa<ConstantSDNode>(Elt)) 2555 return Elt; 2556 } 2557 assert(0 && " No splat value found!"); 2558 return SDValue(); 2559} 2560 2561 2562/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2563/// a splat of a single element and it's a 2 or 4 element mask. 2564bool X86::isSplatMask(SDNode *N) { 2565 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2566 2567 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2568 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2569 return false; 2570 return ::isSplatMask(N); 2571} 2572 2573/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2574/// specifies a splat of zero element. 2575bool X86::isSplatLoMask(SDNode *N) { 2576 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2577 2578 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2579 if (!isUndefOrEqual(N->getOperand(i), 0)) 2580 return false; 2581 return true; 2582} 2583 2584/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2585/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2586bool X86::isMOVDDUPMask(SDNode *N) { 2587 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2588 2589 unsigned e = N->getNumOperands() / 2; 2590 for (unsigned i = 0; i < e; ++i) 2591 if (!isUndefOrEqual(N->getOperand(i), i)) 2592 return false; 2593 for (unsigned i = 0; i < e; ++i) 2594 if (!isUndefOrEqual(N->getOperand(e+i), i)) 2595 return false; 2596 return true; 2597} 2598 2599/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2600/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2601/// instructions. 2602unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2603 unsigned NumOperands = N->getNumOperands(); 2604 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2605 unsigned Mask = 0; 2606 for (unsigned i = 0; i < NumOperands; ++i) { 2607 unsigned Val = 0; 2608 SDValue Arg = N->getOperand(NumOperands-i-1); 2609 if (Arg.getOpcode() != ISD::UNDEF) 2610 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2611 if (Val >= NumOperands) Val -= NumOperands; 2612 Mask |= Val; 2613 if (i != NumOperands - 1) 2614 Mask <<= Shift; 2615 } 2616 2617 return Mask; 2618} 2619 2620/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2621/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2622/// instructions. 2623unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2624 unsigned Mask = 0; 2625 // 8 nodes, but we only care about the last 4. 2626 for (unsigned i = 7; i >= 4; --i) { 2627 unsigned Val = 0; 2628 SDValue Arg = N->getOperand(i); 2629 if (Arg.getOpcode() != ISD::UNDEF) 2630 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2631 Mask |= (Val - 4); 2632 if (i != 4) 2633 Mask <<= 2; 2634 } 2635 2636 return Mask; 2637} 2638 2639/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2640/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2641/// instructions. 2642unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2643 unsigned Mask = 0; 2644 // 8 nodes, but we only care about the first 4. 2645 for (int i = 3; i >= 0; --i) { 2646 unsigned Val = 0; 2647 SDValue Arg = N->getOperand(i); 2648 if (Arg.getOpcode() != ISD::UNDEF) 2649 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2650 Mask |= Val; 2651 if (i != 0) 2652 Mask <<= 2; 2653 } 2654 2655 return Mask; 2656} 2657 2658/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2659/// specifies a 8 element shuffle that can be broken into a pair of 2660/// PSHUFHW and PSHUFLW. 2661static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2662 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2663 2664 if (N->getNumOperands() != 8) 2665 return false; 2666 2667 // Lower quadword shuffled. 2668 for (unsigned i = 0; i != 4; ++i) { 2669 SDValue Arg = N->getOperand(i); 2670 if (Arg.getOpcode() == ISD::UNDEF) continue; 2671 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2672 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2673 if (Val >= 4) 2674 return false; 2675 } 2676 2677 // Upper quadword shuffled. 2678 for (unsigned i = 4; i != 8; ++i) { 2679 SDValue Arg = N->getOperand(i); 2680 if (Arg.getOpcode() == ISD::UNDEF) continue; 2681 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2682 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2683 if (Val < 4 || Val > 7) 2684 return false; 2685 } 2686 2687 return true; 2688} 2689 2690/// CommuteVectorShuffle - Swap vector_shuffle operands as well as 2691/// values in ther permute mask. 2692static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1, 2693 SDValue &V2, SDValue &Mask, 2694 SelectionDAG &DAG) { 2695 MVT VT = Op.getValueType(); 2696 MVT MaskVT = Mask.getValueType(); 2697 MVT EltVT = MaskVT.getVectorElementType(); 2698 unsigned NumElems = Mask.getNumOperands(); 2699 SmallVector<SDValue, 8> MaskVec; 2700 2701 for (unsigned i = 0; i != NumElems; ++i) { 2702 SDValue Arg = Mask.getOperand(i); 2703 if (Arg.getOpcode() == ISD::UNDEF) { 2704 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2705 continue; 2706 } 2707 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2708 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2709 if (Val < NumElems) 2710 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2711 else 2712 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2713 } 2714 2715 std::swap(V1, V2); 2716 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2717 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2718} 2719 2720/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2721/// the two vector operands have swapped position. 2722static 2723SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) { 2724 MVT MaskVT = Mask.getValueType(); 2725 MVT EltVT = MaskVT.getVectorElementType(); 2726 unsigned NumElems = Mask.getNumOperands(); 2727 SmallVector<SDValue, 8> MaskVec; 2728 for (unsigned i = 0; i != NumElems; ++i) { 2729 SDValue Arg = Mask.getOperand(i); 2730 if (Arg.getOpcode() == ISD::UNDEF) { 2731 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2732 continue; 2733 } 2734 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2735 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2736 if (Val < NumElems) 2737 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2738 else 2739 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2740 } 2741 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2742} 2743 2744 2745/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2746/// match movhlps. The lower half elements should come from upper half of 2747/// V1 (and in order), and the upper half elements should come from the upper 2748/// half of V2 (and in order). 2749static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2750 unsigned NumElems = Mask->getNumOperands(); 2751 if (NumElems != 4) 2752 return false; 2753 for (unsigned i = 0, e = 2; i != e; ++i) 2754 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2755 return false; 2756 for (unsigned i = 2; i != 4; ++i) 2757 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2758 return false; 2759 return true; 2760} 2761 2762/// isScalarLoadToVector - Returns true if the node is a scalar load that 2763/// is promoted to a vector. It also returns the LoadSDNode by reference if 2764/// required. 2765static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2766 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2767 return false; 2768 N = N->getOperand(0).getNode(); 2769 if (!ISD::isNON_EXTLoad(N)) 2770 return false; 2771 if (LD) 2772 *LD = cast<LoadSDNode>(N); 2773 return true; 2774} 2775 2776/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2777/// match movlp{s|d}. The lower half elements should come from lower half of 2778/// V1 (and in order), and the upper half elements should come from the upper 2779/// half of V2 (and in order). And since V1 will become the source of the 2780/// MOVLP, it must be either a vector load or a scalar load to vector. 2781static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2782 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2783 return false; 2784 // Is V2 is a vector load, don't do this transformation. We will try to use 2785 // load folding shufps op. 2786 if (ISD::isNON_EXTLoad(V2)) 2787 return false; 2788 2789 unsigned NumElems = Mask->getNumOperands(); 2790 if (NumElems != 2 && NumElems != 4) 2791 return false; 2792 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2793 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2794 return false; 2795 for (unsigned i = NumElems/2; i != NumElems; ++i) 2796 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2797 return false; 2798 return true; 2799} 2800 2801/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2802/// all the same. 2803static bool isSplatVector(SDNode *N) { 2804 if (N->getOpcode() != ISD::BUILD_VECTOR) 2805 return false; 2806 2807 SDValue SplatValue = N->getOperand(0); 2808 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2809 if (N->getOperand(i) != SplatValue) 2810 return false; 2811 return true; 2812} 2813 2814/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2815/// to an undef. 2816static bool isUndefShuffle(SDNode *N) { 2817 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2818 return false; 2819 2820 SDValue V1 = N->getOperand(0); 2821 SDValue V2 = N->getOperand(1); 2822 SDValue Mask = N->getOperand(2); 2823 unsigned NumElems = Mask.getNumOperands(); 2824 for (unsigned i = 0; i != NumElems; ++i) { 2825 SDValue Arg = Mask.getOperand(i); 2826 if (Arg.getOpcode() != ISD::UNDEF) { 2827 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2828 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2829 return false; 2830 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2831 return false; 2832 } 2833 } 2834 return true; 2835} 2836 2837/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2838/// constant +0.0. 2839static inline bool isZeroNode(SDValue Elt) { 2840 return ((isa<ConstantSDNode>(Elt) && 2841 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2842 (isa<ConstantFPSDNode>(Elt) && 2843 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2844} 2845 2846/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2847/// to an zero vector. 2848static bool isZeroShuffle(SDNode *N) { 2849 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2850 return false; 2851 2852 SDValue V1 = N->getOperand(0); 2853 SDValue V2 = N->getOperand(1); 2854 SDValue Mask = N->getOperand(2); 2855 unsigned NumElems = Mask.getNumOperands(); 2856 for (unsigned i = 0; i != NumElems; ++i) { 2857 SDValue Arg = Mask.getOperand(i); 2858 if (Arg.getOpcode() == ISD::UNDEF) 2859 continue; 2860 2861 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 2862 if (Idx < NumElems) { 2863 unsigned Opc = V1.getNode()->getOpcode(); 2864 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2865 continue; 2866 if (Opc != ISD::BUILD_VECTOR || 2867 !isZeroNode(V1.getNode()->getOperand(Idx))) 2868 return false; 2869 } else if (Idx >= NumElems) { 2870 unsigned Opc = V2.getNode()->getOpcode(); 2871 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2872 continue; 2873 if (Opc != ISD::BUILD_VECTOR || 2874 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems))) 2875 return false; 2876 } 2877 } 2878 return true; 2879} 2880 2881/// getZeroVector - Returns a vector of specified type with all zero elements. 2882/// 2883static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { 2884 assert(VT.isVector() && "Expected a vector type"); 2885 2886 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2887 // type. This ensures they get CSE'd. 2888 SDValue Vec; 2889 if (VT.getSizeInBits() == 64) { // MMX 2890 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2891 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2892 } else if (HasSSE2) { // SSE2 2893 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2894 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2895 } else { // SSE1 2896 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2897 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst); 2898 } 2899 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2900} 2901 2902/// getOnesVector - Returns a vector of specified type with all bits set. 2903/// 2904static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) { 2905 assert(VT.isVector() && "Expected a vector type"); 2906 2907 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2908 // type. This ensures they get CSE'd. 2909 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2910 SDValue Vec; 2911 if (VT.getSizeInBits() == 64) // MMX 2912 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2913 else // SSE 2914 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2915 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2916} 2917 2918 2919/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2920/// that point to V2 points to its first element. 2921static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) { 2922 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2923 2924 bool Changed = false; 2925 SmallVector<SDValue, 8> MaskVec; 2926 unsigned NumElems = Mask.getNumOperands(); 2927 for (unsigned i = 0; i != NumElems; ++i) { 2928 SDValue Arg = Mask.getOperand(i); 2929 if (Arg.getOpcode() != ISD::UNDEF) { 2930 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2931 if (Val > NumElems) { 2932 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2933 Changed = true; 2934 } 2935 } 2936 MaskVec.push_back(Arg); 2937 } 2938 2939 if (Changed) 2940 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2941 &MaskVec[0], MaskVec.size()); 2942 return Mask; 2943} 2944 2945/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2946/// operation of specified width. 2947static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2948 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2949 MVT BaseVT = MaskVT.getVectorElementType(); 2950 2951 SmallVector<SDValue, 8> MaskVec; 2952 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2953 for (unsigned i = 1; i != NumElems; ++i) 2954 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2955 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2956} 2957 2958/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2959/// of specified width. 2960static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2961 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2962 MVT BaseVT = MaskVT.getVectorElementType(); 2963 SmallVector<SDValue, 8> MaskVec; 2964 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2965 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2966 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2967 } 2968 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2969} 2970 2971/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2972/// of specified width. 2973static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2974 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2975 MVT BaseVT = MaskVT.getVectorElementType(); 2976 unsigned Half = NumElems/2; 2977 SmallVector<SDValue, 8> MaskVec; 2978 for (unsigned i = 0; i != Half; ++i) { 2979 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2980 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2981 } 2982 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2983} 2984 2985/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps 2986/// element #0 of a vector with the specified index, leaving the rest of the 2987/// elements in place. 2988static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, 2989 SelectionDAG &DAG) { 2990 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2991 MVT BaseVT = MaskVT.getVectorElementType(); 2992 SmallVector<SDValue, 8> MaskVec; 2993 // Element #0 of the result gets the elt we are replacing. 2994 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); 2995 for (unsigned i = 1; i != NumElems; ++i) 2996 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); 2997 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2998} 2999 3000/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3001static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) { 3002 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; 3003 MVT VT = Op.getValueType(); 3004 if (PVT == VT) 3005 return Op; 3006 SDValue V1 = Op.getOperand(0); 3007 SDValue Mask = Op.getOperand(2); 3008 unsigned MaskNumElems = Mask.getNumOperands(); 3009 unsigned NumElems = MaskNumElems; 3010 // Special handling of v4f32 -> v4i32. 3011 if (VT != MVT::v4f32) { 3012 // Find which element we want to splat. 3013 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode(); 3014 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue(); 3015 // unpack elements to the correct location 3016 while (NumElems > 4) { 3017 if (EltNo < NumElems/2) { 3018 Mask = getUnpacklMask(MaskNumElems, DAG); 3019 } else { 3020 Mask = getUnpackhMask(MaskNumElems, DAG); 3021 EltNo -= NumElems/2; 3022 } 3023 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 3024 NumElems >>= 1; 3025 } 3026 SDValue Cst = DAG.getConstant(EltNo, MVT::i32); 3027 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 3028 } 3029 3030 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); 3031 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, 3032 DAG.getNode(ISD::UNDEF, PVT), Mask); 3033 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 3034} 3035 3036/// isVectorLoad - Returns true if the node is a vector load, a scalar 3037/// load that's promoted to vector, or a load bitcasted. 3038static bool isVectorLoad(SDValue Op) { 3039 assert(Op.getValueType().isVector() && "Expected a vector type"); 3040 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR || 3041 Op.getOpcode() == ISD::BIT_CONVERT) { 3042 return isa<LoadSDNode>(Op.getOperand(0)); 3043 } 3044 return isa<LoadSDNode>(Op); 3045} 3046 3047 3048/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64. 3049/// 3050static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask, 3051 SelectionDAG &DAG, bool HasSSE3) { 3052 // If we have sse3 and shuffle has more than one use or input is a load, then 3053 // use movddup. Otherwise, use movlhps. 3054 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1)); 3055 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32; 3056 MVT VT = Op.getValueType(); 3057 if (VT == PVT) 3058 return Op; 3059 unsigned NumElems = PVT.getVectorNumElements(); 3060 if (NumElems == 2) { 3061 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3062 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 3063 } else { 3064 assert(NumElems == 4); 3065 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32); 3066 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32); 3067 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1); 3068 } 3069 3070 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); 3071 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, 3072 DAG.getNode(ISD::UNDEF, PVT), Mask); 3073 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 3074} 3075 3076/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3077/// vector of zero or undef vector. This produces a shuffle where the low 3078/// element of V2 is swizzled into the zero/undef vector, landing at element 3079/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3080static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3081 bool isZero, bool HasSSE2, 3082 SelectionDAG &DAG) { 3083 MVT VT = V2.getValueType(); 3084 SDValue V1 = isZero 3085 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); 3086 unsigned NumElems = V2.getValueType().getVectorNumElements(); 3087 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3088 MVT EVT = MaskVT.getVectorElementType(); 3089 SmallVector<SDValue, 16> MaskVec; 3090 for (unsigned i = 0; i != NumElems; ++i) 3091 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. 3092 MaskVec.push_back(DAG.getConstant(NumElems, EVT)); 3093 else 3094 MaskVec.push_back(DAG.getConstant(i, EVT)); 3095 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3096 &MaskVec[0], MaskVec.size()); 3097 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3098} 3099 3100/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3101/// a shuffle that is zero. 3102static 3103unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask, 3104 unsigned NumElems, bool Low, 3105 SelectionDAG &DAG) { 3106 unsigned NumZeros = 0; 3107 for (unsigned i = 0; i < NumElems; ++i) { 3108 unsigned Index = Low ? i : NumElems-i-1; 3109 SDValue Idx = Mask.getOperand(Index); 3110 if (Idx.getOpcode() == ISD::UNDEF) { 3111 ++NumZeros; 3112 continue; 3113 } 3114 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index); 3115 if (Elt.getNode() && isZeroNode(Elt)) 3116 ++NumZeros; 3117 else 3118 break; 3119 } 3120 return NumZeros; 3121} 3122 3123/// isVectorShift - Returns true if the shuffle can be implemented as a 3124/// logical left or right shift of a vector. 3125static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG, 3126 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3127 unsigned NumElems = Mask.getNumOperands(); 3128 3129 isLeft = true; 3130 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG); 3131 if (!NumZeros) { 3132 isLeft = false; 3133 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG); 3134 if (!NumZeros) 3135 return false; 3136 } 3137 3138 bool SeenV1 = false; 3139 bool SeenV2 = false; 3140 for (unsigned i = NumZeros; i < NumElems; ++i) { 3141 unsigned Val = isLeft ? (i - NumZeros) : i; 3142 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); 3143 if (Idx.getOpcode() == ISD::UNDEF) 3144 continue; 3145 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 3146 if (Index < NumElems) 3147 SeenV1 = true; 3148 else { 3149 Index -= NumElems; 3150 SeenV2 = true; 3151 } 3152 if (Index != Val) 3153 return false; 3154 } 3155 if (SeenV1 && SeenV2) 3156 return false; 3157 3158 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1); 3159 ShAmt = NumZeros; 3160 return true; 3161} 3162 3163 3164/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3165/// 3166static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3167 unsigned NumNonZero, unsigned NumZero, 3168 SelectionDAG &DAG, TargetLowering &TLI) { 3169 if (NumNonZero > 8) 3170 return SDValue(); 3171 3172 SDValue V(0, 0); 3173 bool First = true; 3174 for (unsigned i = 0; i < 16; ++i) { 3175 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3176 if (ThisIsNonZero && First) { 3177 if (NumZero) 3178 V = getZeroVector(MVT::v8i16, true, DAG); 3179 else 3180 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3181 First = false; 3182 } 3183 3184 if ((i & 1) != 0) { 3185 SDValue ThisElt(0, 0), LastElt(0, 0); 3186 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3187 if (LastIsNonZero) { 3188 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 3189 } 3190 if (ThisIsNonZero) { 3191 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 3192 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 3193 ThisElt, DAG.getConstant(8, MVT::i8)); 3194 if (LastIsNonZero) 3195 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 3196 } else 3197 ThisElt = LastElt; 3198 3199 if (ThisElt.getNode()) 3200 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 3201 DAG.getIntPtrConstant(i/2)); 3202 } 3203 } 3204 3205 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 3206} 3207 3208/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3209/// 3210static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3211 unsigned NumNonZero, unsigned NumZero, 3212 SelectionDAG &DAG, TargetLowering &TLI) { 3213 if (NumNonZero > 4) 3214 return SDValue(); 3215 3216 SDValue V(0, 0); 3217 bool First = true; 3218 for (unsigned i = 0; i < 8; ++i) { 3219 bool isNonZero = (NonZeros & (1 << i)) != 0; 3220 if (isNonZero) { 3221 if (First) { 3222 if (NumZero) 3223 V = getZeroVector(MVT::v8i16, true, DAG); 3224 else 3225 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3226 First = false; 3227 } 3228 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 3229 DAG.getIntPtrConstant(i)); 3230 } 3231 } 3232 3233 return V; 3234} 3235 3236/// getVShift - Return a vector logical shift node. 3237/// 3238static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, 3239 unsigned NumBits, SelectionDAG &DAG, 3240 const TargetLowering &TLI) { 3241 bool isMMX = VT.getSizeInBits() == 64; 3242 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3243 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3244 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp); 3245 return DAG.getNode(ISD::BIT_CONVERT, VT, 3246 DAG.getNode(Opc, ShVT, SrcOp, 3247 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3248} 3249 3250SDValue 3251X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3252 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3253 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3254 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3255 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3256 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3257 // eliminated on x86-32 hosts. 3258 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3259 return Op; 3260 3261 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3262 return getOnesVector(Op.getValueType(), DAG); 3263 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG); 3264 } 3265 3266 MVT VT = Op.getValueType(); 3267 MVT EVT = VT.getVectorElementType(); 3268 unsigned EVTBits = EVT.getSizeInBits(); 3269 3270 unsigned NumElems = Op.getNumOperands(); 3271 unsigned NumZero = 0; 3272 unsigned NumNonZero = 0; 3273 unsigned NonZeros = 0; 3274 bool IsAllConstants = true; 3275 SmallSet<SDValue, 8> Values; 3276 for (unsigned i = 0; i < NumElems; ++i) { 3277 SDValue Elt = Op.getOperand(i); 3278 if (Elt.getOpcode() == ISD::UNDEF) 3279 continue; 3280 Values.insert(Elt); 3281 if (Elt.getOpcode() != ISD::Constant && 3282 Elt.getOpcode() != ISD::ConstantFP) 3283 IsAllConstants = false; 3284 if (isZeroNode(Elt)) 3285 NumZero++; 3286 else { 3287 NonZeros |= (1 << i); 3288 NumNonZero++; 3289 } 3290 } 3291 3292 if (NumNonZero == 0) { 3293 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3294 return DAG.getNode(ISD::UNDEF, VT); 3295 } 3296 3297 // Special case for single non-zero, non-undef, element. 3298 if (NumNonZero == 1 && NumElems <= 4) { 3299 unsigned Idx = CountTrailingZeros_32(NonZeros); 3300 SDValue Item = Op.getOperand(Idx); 3301 3302 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3303 // the value are obviously zero, truncate the value to i32 and do the 3304 // insertion that way. Only do this if the value is non-constant or if the 3305 // value is a constant being inserted into element 0. It is cheaper to do 3306 // a constant pool load than it is to do a movd + shuffle. 3307 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 3308 (!IsAllConstants || Idx == 0)) { 3309 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3310 // Handle MMX and SSE both. 3311 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3312 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3313 3314 // Truncate the value (which may itself be a constant) to i32, and 3315 // convert it to a vector with movd (S2V+shuffle to zero extend). 3316 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); 3317 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); 3318 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3319 Subtarget->hasSSE2(), DAG); 3320 3321 // Now we have our 32-bit value zero extended in the low element of 3322 // a vector. If Idx != 0, swizzle it into place. 3323 if (Idx != 0) { 3324 SDValue Ops[] = { 3325 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), 3326 getSwapEltZeroMask(VecElts, Idx, DAG) 3327 }; 3328 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); 3329 } 3330 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); 3331 } 3332 } 3333 3334 // If we have a constant or non-constant insertion into the low element of 3335 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3336 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3337 // depending on what the source datatype is. Because we can only get here 3338 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. 3339 if (Idx == 0 && 3340 // Don't do this for i64 values on x86-32. 3341 (EVT != MVT::i64 || Subtarget->is64Bit())) { 3342 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3343 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3344 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3345 Subtarget->hasSSE2(), DAG); 3346 } 3347 3348 // Is it a vector logical left shift? 3349 if (NumElems == 2 && Idx == 1 && 3350 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { 3351 unsigned NumBits = VT.getSizeInBits(); 3352 return getVShift(true, VT, 3353 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)), 3354 NumBits/2, DAG, *this); 3355 } 3356 3357 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3358 return SDValue(); 3359 3360 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3361 // is a non-constant being inserted into an element other than the low one, 3362 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3363 // movd/movss) to move this into the low element, then shuffle it into 3364 // place. 3365 if (EVTBits == 32) { 3366 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3367 3368 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3369 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3370 Subtarget->hasSSE2(), DAG); 3371 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3372 MVT MaskEVT = MaskVT.getVectorElementType(); 3373 SmallVector<SDValue, 8> MaskVec; 3374 for (unsigned i = 0; i < NumElems; i++) 3375 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3376 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3377 &MaskVec[0], MaskVec.size()); 3378 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 3379 DAG.getNode(ISD::UNDEF, VT), Mask); 3380 } 3381 } 3382 3383 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3384 if (Values.size() == 1) 3385 return SDValue(); 3386 3387 // A vector full of immediates; various special cases are already 3388 // handled, so this is best done with a single constant-pool load. 3389 if (IsAllConstants) 3390 return SDValue(); 3391 3392 // Let legalizer expand 2-wide build_vectors. 3393 if (EVTBits == 64) { 3394 if (NumNonZero == 1) { 3395 // One half is zero or undef. 3396 unsigned Idx = CountTrailingZeros_32(NonZeros); 3397 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, 3398 Op.getOperand(Idx)); 3399 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3400 Subtarget->hasSSE2(), DAG); 3401 } 3402 return SDValue(); 3403 } 3404 3405 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3406 if (EVTBits == 8 && NumElems == 16) { 3407 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3408 *this); 3409 if (V.getNode()) return V; 3410 } 3411 3412 if (EVTBits == 16 && NumElems == 8) { 3413 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3414 *this); 3415 if (V.getNode()) return V; 3416 } 3417 3418 // If element VT is == 32 bits, turn it into a number of shuffles. 3419 SmallVector<SDValue, 8> V; 3420 V.resize(NumElems); 3421 if (NumElems == 4 && NumZero > 0) { 3422 for (unsigned i = 0; i < 4; ++i) { 3423 bool isZero = !(NonZeros & (1 << i)); 3424 if (isZero) 3425 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG); 3426 else 3427 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3428 } 3429 3430 for (unsigned i = 0; i < 2; ++i) { 3431 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3432 default: break; 3433 case 0: 3434 V[i] = V[i*2]; // Must be a zero vector. 3435 break; 3436 case 1: 3437 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3438 getMOVLMask(NumElems, DAG)); 3439 break; 3440 case 2: 3441 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3442 getMOVLMask(NumElems, DAG)); 3443 break; 3444 case 3: 3445 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3446 getUnpacklMask(NumElems, DAG)); 3447 break; 3448 } 3449 } 3450 3451 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3452 MVT EVT = MaskVT.getVectorElementType(); 3453 SmallVector<SDValue, 8> MaskVec; 3454 bool Reverse = (NonZeros & 0x3) == 2; 3455 for (unsigned i = 0; i < 2; ++i) 3456 if (Reverse) 3457 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3458 else 3459 MaskVec.push_back(DAG.getConstant(i, EVT)); 3460 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3461 for (unsigned i = 0; i < 2; ++i) 3462 if (Reverse) 3463 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3464 else 3465 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3466 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3467 &MaskVec[0], MaskVec.size()); 3468 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3469 } 3470 3471 if (Values.size() > 2) { 3472 // Expand into a number of unpckl*. 3473 // e.g. for v4f32 3474 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3475 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3476 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3477 SDValue UnpckMask = getUnpacklMask(NumElems, DAG); 3478 for (unsigned i = 0; i < NumElems; ++i) 3479 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3480 NumElems >>= 1; 3481 while (NumElems != 0) { 3482 for (unsigned i = 0; i < NumElems; ++i) 3483 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3484 UnpckMask); 3485 NumElems >>= 1; 3486 } 3487 return V[0]; 3488 } 3489 3490 return SDValue(); 3491} 3492 3493static 3494SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, 3495 SDValue PermMask, SelectionDAG &DAG, 3496 TargetLowering &TLI) { 3497 SDValue NewV; 3498 MVT MaskVT = MVT::getIntVectorWithNumElements(8); 3499 MVT MaskEVT = MaskVT.getVectorElementType(); 3500 MVT PtrVT = TLI.getPointerTy(); 3501 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(), 3502 PermMask.getNode()->op_end()); 3503 3504 // First record which half of which vector the low elements come from. 3505 SmallVector<unsigned, 4> LowQuad(4); 3506 for (unsigned i = 0; i < 4; ++i) { 3507 SDValue Elt = MaskElts[i]; 3508 if (Elt.getOpcode() == ISD::UNDEF) 3509 continue; 3510 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3511 int QuadIdx = EltIdx / 4; 3512 ++LowQuad[QuadIdx]; 3513 } 3514 3515 int BestLowQuad = -1; 3516 unsigned MaxQuad = 1; 3517 for (unsigned i = 0; i < 4; ++i) { 3518 if (LowQuad[i] > MaxQuad) { 3519 BestLowQuad = i; 3520 MaxQuad = LowQuad[i]; 3521 } 3522 } 3523 3524 // Record which half of which vector the high elements come from. 3525 SmallVector<unsigned, 4> HighQuad(4); 3526 for (unsigned i = 4; i < 8; ++i) { 3527 SDValue Elt = MaskElts[i]; 3528 if (Elt.getOpcode() == ISD::UNDEF) 3529 continue; 3530 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3531 int QuadIdx = EltIdx / 4; 3532 ++HighQuad[QuadIdx]; 3533 } 3534 3535 int BestHighQuad = -1; 3536 MaxQuad = 1; 3537 for (unsigned i = 0; i < 4; ++i) { 3538 if (HighQuad[i] > MaxQuad) { 3539 BestHighQuad = i; 3540 MaxQuad = HighQuad[i]; 3541 } 3542 } 3543 3544 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. 3545 if (BestLowQuad != -1 || BestHighQuad != -1) { 3546 // First sort the 4 chunks in order using shufpd. 3547 SmallVector<SDValue, 8> MaskVec; 3548 3549 if (BestLowQuad != -1) 3550 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); 3551 else 3552 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 3553 3554 if (BestHighQuad != -1) 3555 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); 3556 else 3557 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 3558 3559 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); 3560 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 3561 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), 3562 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); 3563 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); 3564 3565 // Now sort high and low parts separately. 3566 BitVector InOrder(8); 3567 if (BestLowQuad != -1) { 3568 // Sort lower half in order using PSHUFLW. 3569 MaskVec.clear(); 3570 bool AnyOutOrder = false; 3571 3572 for (unsigned i = 0; i != 4; ++i) { 3573 SDValue Elt = MaskElts[i]; 3574 if (Elt.getOpcode() == ISD::UNDEF) { 3575 MaskVec.push_back(Elt); 3576 InOrder.set(i); 3577 } else { 3578 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3579 if (EltIdx != i) 3580 AnyOutOrder = true; 3581 3582 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT)); 3583 3584 // If this element is in the right place after this shuffle, then 3585 // remember it. 3586 if ((int)(EltIdx / 4) == BestLowQuad) 3587 InOrder.set(i); 3588 } 3589 } 3590 if (AnyOutOrder) { 3591 for (unsigned i = 4; i != 8; ++i) 3592 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3593 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3594 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3595 } 3596 } 3597 3598 if (BestHighQuad != -1) { 3599 // Sort high half in order using PSHUFHW if possible. 3600 MaskVec.clear(); 3601 3602 for (unsigned i = 0; i != 4; ++i) 3603 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3604 3605 bool AnyOutOrder = false; 3606 for (unsigned i = 4; i != 8; ++i) { 3607 SDValue Elt = MaskElts[i]; 3608 if (Elt.getOpcode() == ISD::UNDEF) { 3609 MaskVec.push_back(Elt); 3610 InOrder.set(i); 3611 } else { 3612 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3613 if (EltIdx != i) 3614 AnyOutOrder = true; 3615 3616 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT)); 3617 3618 // If this element is in the right place after this shuffle, then 3619 // remember it. 3620 if ((int)(EltIdx / 4) == BestHighQuad) 3621 InOrder.set(i); 3622 } 3623 } 3624 3625 if (AnyOutOrder) { 3626 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3627 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3628 } 3629 } 3630 3631 // The other elements are put in the right place using pextrw and pinsrw. 3632 for (unsigned i = 0; i != 8; ++i) { 3633 if (InOrder[i]) 3634 continue; 3635 SDValue Elt = MaskElts[i]; 3636 if (Elt.getOpcode() == ISD::UNDEF) 3637 continue; 3638 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3639 SDValue ExtOp = (EltIdx < 8) 3640 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3641 DAG.getConstant(EltIdx, PtrVT)) 3642 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3643 DAG.getConstant(EltIdx - 8, PtrVT)); 3644 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3645 DAG.getConstant(i, PtrVT)); 3646 } 3647 3648 return NewV; 3649 } 3650 3651 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as 3652 // few as possible. First, let's find out how many elements are already in the 3653 // right order. 3654 unsigned V1InOrder = 0; 3655 unsigned V1FromV1 = 0; 3656 unsigned V2InOrder = 0; 3657 unsigned V2FromV2 = 0; 3658 SmallVector<SDValue, 8> V1Elts; 3659 SmallVector<SDValue, 8> V2Elts; 3660 for (unsigned i = 0; i < 8; ++i) { 3661 SDValue Elt = MaskElts[i]; 3662 if (Elt.getOpcode() == ISD::UNDEF) { 3663 V1Elts.push_back(Elt); 3664 V2Elts.push_back(Elt); 3665 ++V1InOrder; 3666 ++V2InOrder; 3667 continue; 3668 } 3669 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3670 if (EltIdx == i) { 3671 V1Elts.push_back(Elt); 3672 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); 3673 ++V1InOrder; 3674 } else if (EltIdx == i+8) { 3675 V1Elts.push_back(Elt); 3676 V2Elts.push_back(DAG.getConstant(i, MaskEVT)); 3677 ++V2InOrder; 3678 } else if (EltIdx < 8) { 3679 V1Elts.push_back(Elt); 3680 V2Elts.push_back(DAG.getConstant(EltIdx+8, MaskEVT)); 3681 ++V1FromV1; 3682 } else { 3683 V1Elts.push_back(Elt); 3684 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT)); 3685 ++V2FromV2; 3686 } 3687 } 3688 3689 if (V2InOrder > V1InOrder) { 3690 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3691 std::swap(V1, V2); 3692 std::swap(V1Elts, V2Elts); 3693 std::swap(V1FromV1, V2FromV2); 3694 } 3695 3696 if ((V1FromV1 + V1InOrder) != 8) { 3697 // Some elements are from V2. 3698 if (V1FromV1) { 3699 // If there are elements that are from V1 but out of place, 3700 // then first sort them in place 3701 SmallVector<SDValue, 8> MaskVec; 3702 for (unsigned i = 0; i < 8; ++i) { 3703 SDValue Elt = V1Elts[i]; 3704 if (Elt.getOpcode() == ISD::UNDEF) { 3705 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3706 continue; 3707 } 3708 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3709 if (EltIdx >= 8) 3710 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3711 else 3712 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); 3713 } 3714 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3715 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); 3716 } 3717 3718 NewV = V1; 3719 for (unsigned i = 0; i < 8; ++i) { 3720 SDValue Elt = V1Elts[i]; 3721 if (Elt.getOpcode() == ISD::UNDEF) 3722 continue; 3723 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3724 if (EltIdx < 8) 3725 continue; 3726 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3727 DAG.getConstant(EltIdx - 8, PtrVT)); 3728 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3729 DAG.getConstant(i, PtrVT)); 3730 } 3731 return NewV; 3732 } else { 3733 // All elements are from V1. 3734 NewV = V1; 3735 for (unsigned i = 0; i < 8; ++i) { 3736 SDValue Elt = V1Elts[i]; 3737 if (Elt.getOpcode() == ISD::UNDEF) 3738 continue; 3739 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3740 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3741 DAG.getConstant(EltIdx, PtrVT)); 3742 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3743 DAG.getConstant(i, PtrVT)); 3744 } 3745 return NewV; 3746 } 3747} 3748 3749/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3750/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3751/// done when every pair / quad of shuffle mask elements point to elements in 3752/// the right sequence. e.g. 3753/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3754static 3755SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, 3756 MVT VT, 3757 SDValue PermMask, SelectionDAG &DAG, 3758 TargetLowering &TLI) { 3759 unsigned NumElems = PermMask.getNumOperands(); 3760 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3761 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3762 MVT MaskEltVT = MaskVT.getVectorElementType(); 3763 MVT NewVT = MaskVT; 3764 switch (VT.getSimpleVT()) { 3765 default: assert(false && "Unexpected!"); 3766 case MVT::v4f32: NewVT = MVT::v2f64; break; 3767 case MVT::v4i32: NewVT = MVT::v2i64; break; 3768 case MVT::v8i16: NewVT = MVT::v4i32; break; 3769 case MVT::v16i8: NewVT = MVT::v4i32; break; 3770 } 3771 3772 if (NewWidth == 2) { 3773 if (VT.isInteger()) 3774 NewVT = MVT::v2i64; 3775 else 3776 NewVT = MVT::v2f64; 3777 } 3778 unsigned Scale = NumElems / NewWidth; 3779 SmallVector<SDValue, 8> MaskVec; 3780 for (unsigned i = 0; i < NumElems; i += Scale) { 3781 unsigned StartIdx = ~0U; 3782 for (unsigned j = 0; j < Scale; ++j) { 3783 SDValue Elt = PermMask.getOperand(i+j); 3784 if (Elt.getOpcode() == ISD::UNDEF) 3785 continue; 3786 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3787 if (StartIdx == ~0U) 3788 StartIdx = EltIdx - (EltIdx % Scale); 3789 if (EltIdx != StartIdx + j) 3790 return SDValue(); 3791 } 3792 if (StartIdx == ~0U) 3793 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT)); 3794 else 3795 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT)); 3796 } 3797 3798 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); 3799 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); 3800 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, 3801 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3802 &MaskVec[0], MaskVec.size())); 3803} 3804 3805/// getVZextMovL - Return a zero-extending vector move low node. 3806/// 3807static SDValue getVZextMovL(MVT VT, MVT OpVT, 3808 SDValue SrcOp, SelectionDAG &DAG, 3809 const X86Subtarget *Subtarget) { 3810 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3811 LoadSDNode *LD = NULL; 3812 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3813 LD = dyn_cast<LoadSDNode>(SrcOp); 3814 if (!LD) { 3815 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3816 // instead. 3817 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3818 if ((EVT != MVT::i64 || Subtarget->is64Bit()) && 3819 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3820 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3821 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { 3822 // PR2108 3823 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3824 return DAG.getNode(ISD::BIT_CONVERT, VT, 3825 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3826 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT, 3827 SrcOp.getOperand(0) 3828 .getOperand(0)))); 3829 } 3830 } 3831 } 3832 3833 return DAG.getNode(ISD::BIT_CONVERT, VT, 3834 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3835 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp))); 3836} 3837 3838/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3839/// shuffles. 3840static SDValue 3841LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, 3842 SDValue PermMask, MVT VT, SelectionDAG &DAG) { 3843 MVT MaskVT = PermMask.getValueType(); 3844 MVT MaskEVT = MaskVT.getVectorElementType(); 3845 SmallVector<std::pair<int, int>, 8> Locs; 3846 Locs.resize(4); 3847 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3848 unsigned NumHi = 0; 3849 unsigned NumLo = 0; 3850 for (unsigned i = 0; i != 4; ++i) { 3851 SDValue Elt = PermMask.getOperand(i); 3852 if (Elt.getOpcode() == ISD::UNDEF) { 3853 Locs[i] = std::make_pair(-1, -1); 3854 } else { 3855 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 3856 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!"); 3857 if (Val < 4) { 3858 Locs[i] = std::make_pair(0, NumLo); 3859 Mask1[NumLo] = Elt; 3860 NumLo++; 3861 } else { 3862 Locs[i] = std::make_pair(1, NumHi); 3863 if (2+NumHi < 4) 3864 Mask1[2+NumHi] = Elt; 3865 NumHi++; 3866 } 3867 } 3868 } 3869 3870 if (NumLo <= 2 && NumHi <= 2) { 3871 // If no more than two elements come from either vector. This can be 3872 // implemented with two shuffles. First shuffle gather the elements. 3873 // The second shuffle, which takes the first shuffle as both of its 3874 // vector operands, put the elements into the right order. 3875 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3876 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3877 &Mask1[0], Mask1.size())); 3878 3879 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3880 for (unsigned i = 0; i != 4; ++i) { 3881 if (Locs[i].first == -1) 3882 continue; 3883 else { 3884 unsigned Idx = (i < 2) ? 0 : 4; 3885 Idx += Locs[i].first * 2 + Locs[i].second; 3886 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3887 } 3888 } 3889 3890 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3891 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3892 &Mask2[0], Mask2.size())); 3893 } else if (NumLo == 3 || NumHi == 3) { 3894 // Otherwise, we must have three elements from one vector, call it X, and 3895 // one element from the other, call it Y. First, use a shufps to build an 3896 // intermediate vector with the one element from Y and the element from X 3897 // that will be in the same half in the final destination (the indexes don't 3898 // matter). Then, use a shufps to build the final vector, taking the half 3899 // containing the element from Y from the intermediate, and the other half 3900 // from X. 3901 if (NumHi == 3) { 3902 // Normalize it so the 3 elements come from V1. 3903 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3904 std::swap(V1, V2); 3905 } 3906 3907 // Find the element from V2. 3908 unsigned HiIndex; 3909 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 3910 SDValue Elt = PermMask.getOperand(HiIndex); 3911 if (Elt.getOpcode() == ISD::UNDEF) 3912 continue; 3913 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 3914 if (Val >= 4) 3915 break; 3916 } 3917 3918 Mask1[0] = PermMask.getOperand(HiIndex); 3919 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT); 3920 Mask1[2] = PermMask.getOperand(HiIndex^1); 3921 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT); 3922 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3923 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3924 3925 if (HiIndex >= 2) { 3926 Mask1[0] = PermMask.getOperand(0); 3927 Mask1[1] = PermMask.getOperand(1); 3928 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT); 3929 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT); 3930 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3931 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3932 } else { 3933 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT); 3934 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT); 3935 Mask1[2] = PermMask.getOperand(2); 3936 Mask1[3] = PermMask.getOperand(3); 3937 if (Mask1[2].getOpcode() != ISD::UNDEF) 3938 Mask1[2] = 3939 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4, 3940 MaskEVT); 3941 if (Mask1[3].getOpcode() != ISD::UNDEF) 3942 Mask1[3] = 3943 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4, 3944 MaskEVT); 3945 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, 3946 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3947 } 3948 } 3949 3950 // Break it into (shuffle shuffle_hi, shuffle_lo). 3951 Locs.clear(); 3952 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3953 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3954 SmallVector<SDValue,8> *MaskPtr = &LoMask; 3955 unsigned MaskIdx = 0; 3956 unsigned LoIdx = 0; 3957 unsigned HiIdx = 2; 3958 for (unsigned i = 0; i != 4; ++i) { 3959 if (i == 2) { 3960 MaskPtr = &HiMask; 3961 MaskIdx = 1; 3962 LoIdx = 0; 3963 HiIdx = 2; 3964 } 3965 SDValue Elt = PermMask.getOperand(i); 3966 if (Elt.getOpcode() == ISD::UNDEF) { 3967 Locs[i] = std::make_pair(-1, -1); 3968 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) { 3969 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3970 (*MaskPtr)[LoIdx] = Elt; 3971 LoIdx++; 3972 } else { 3973 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3974 (*MaskPtr)[HiIdx] = Elt; 3975 HiIdx++; 3976 } 3977 } 3978 3979 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3980 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3981 &LoMask[0], LoMask.size())); 3982 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3983 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3984 &HiMask[0], HiMask.size())); 3985 SmallVector<SDValue, 8> MaskOps; 3986 for (unsigned i = 0; i != 4; ++i) { 3987 if (Locs[i].first == -1) { 3988 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3989 } else { 3990 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 3991 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3992 } 3993 } 3994 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3995 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3996 &MaskOps[0], MaskOps.size())); 3997} 3998 3999SDValue 4000X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4001 SDValue V1 = Op.getOperand(0); 4002 SDValue V2 = Op.getOperand(1); 4003 SDValue PermMask = Op.getOperand(2); 4004 MVT VT = Op.getValueType(); 4005 unsigned NumElems = PermMask.getNumOperands(); 4006 bool isMMX = VT.getSizeInBits() == 64; 4007 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4008 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4009 bool V1IsSplat = false; 4010 bool V2IsSplat = false; 4011 4012 if (isUndefShuffle(Op.getNode())) 4013 return DAG.getNode(ISD::UNDEF, VT); 4014 4015 if (isZeroShuffle(Op.getNode())) 4016 return getZeroVector(VT, Subtarget->hasSSE2(), DAG); 4017 4018 if (isIdentityMask(PermMask.getNode())) 4019 return V1; 4020 else if (isIdentityMask(PermMask.getNode(), true)) 4021 return V2; 4022 4023 // Canonicalize movddup shuffles. 4024 if (V2IsUndef && Subtarget->hasSSE2() && 4025 VT.getSizeInBits() == 128 && 4026 X86::isMOVDDUPMask(PermMask.getNode())) 4027 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3()); 4028 4029 if (isSplatMask(PermMask.getNode())) { 4030 if (isMMX || NumElems < 4) return Op; 4031 // Promote it to a v4{if}32 splat. 4032 return PromoteSplat(Op, DAG, Subtarget->hasSSE2()); 4033 } 4034 4035 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4036 // do it! 4037 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4038 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 4039 if (NewOp.getNode()) 4040 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 4041 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4042 // FIXME: Figure out a cleaner way to do this. 4043 // Try to make use of movq to zero out the top part. 4044 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4045 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4046 DAG, *this); 4047 if (NewOp.getNode()) { 4048 SDValue NewV1 = NewOp.getOperand(0); 4049 SDValue NewV2 = NewOp.getOperand(1); 4050 SDValue NewMask = NewOp.getOperand(2); 4051 if (isCommutedMOVL(NewMask.getNode(), true, false)) { 4052 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); 4053 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget); 4054 } 4055 } 4056 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4057 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4058 DAG, *this); 4059 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode())) 4060 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4061 DAG, Subtarget); 4062 } 4063 } 4064 4065 // Check if this can be converted into a logical shift. 4066 bool isLeft = false; 4067 unsigned ShAmt = 0; 4068 SDValue ShVal; 4069 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt); 4070 if (isShift && ShVal.hasOneUse()) { 4071 // If the shifted value has multiple uses, it may be cheaper to use 4072 // v_set0 + movlhps or movhlps, etc. 4073 MVT EVT = VT.getVectorElementType(); 4074 ShAmt *= EVT.getSizeInBits(); 4075 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 4076 } 4077 4078 if (X86::isMOVLMask(PermMask.getNode())) { 4079 if (V1IsUndef) 4080 return V2; 4081 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4082 return getVZextMovL(VT, VT, V2, DAG, Subtarget); 4083 if (!isMMX) 4084 return Op; 4085 } 4086 4087 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) || 4088 X86::isMOVSLDUPMask(PermMask.getNode()) || 4089 X86::isMOVHLPSMask(PermMask.getNode()) || 4090 X86::isMOVHPMask(PermMask.getNode()) || 4091 X86::isMOVLPMask(PermMask.getNode()))) 4092 return Op; 4093 4094 if (ShouldXformToMOVHLPS(PermMask.getNode()) || 4095 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode())) 4096 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4097 4098 if (isShift) { 4099 // No better options. Use a vshl / vsrl. 4100 MVT EVT = VT.getVectorElementType(); 4101 ShAmt *= EVT.getSizeInBits(); 4102 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 4103 } 4104 4105 bool Commuted = false; 4106 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4107 // 1,1,1,1 -> v8i16 though. 4108 V1IsSplat = isSplatVector(V1.getNode()); 4109 V2IsSplat = isSplatVector(V2.getNode()); 4110 4111 // Canonicalize the splat or undef, if present, to be on the RHS. 4112 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4113 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4114 std::swap(V1IsSplat, V2IsSplat); 4115 std::swap(V1IsUndef, V2IsUndef); 4116 Commuted = true; 4117 } 4118 4119 // FIXME: Figure out a cleaner way to do this. 4120 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) { 4121 if (V2IsUndef) return V1; 4122 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4123 if (V2IsSplat) { 4124 // V2 is a splat, so the mask may be malformed. That is, it may point 4125 // to any V2 element. The instruction selectior won't like this. Get 4126 // a corrected mask and commute to form a proper MOVS{S|D}. 4127 SDValue NewMask = getMOVLMask(NumElems, DAG); 4128 if (NewMask.getNode() != PermMask.getNode()) 4129 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4130 } 4131 return Op; 4132 } 4133 4134 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4135 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4136 X86::isUNPCKLMask(PermMask.getNode()) || 4137 X86::isUNPCKHMask(PermMask.getNode())) 4138 return Op; 4139 4140 if (V2IsSplat) { 4141 // Normalize mask so all entries that point to V2 points to its first 4142 // element then try to match unpck{h|l} again. If match, return a 4143 // new vector_shuffle with the corrected mask. 4144 SDValue NewMask = NormalizeMask(PermMask, DAG); 4145 if (NewMask.getNode() != PermMask.getNode()) { 4146 if (X86::isUNPCKLMask(PermMask.getNode(), true)) { 4147 SDValue NewMask = getUnpacklMask(NumElems, DAG); 4148 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4149 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) { 4150 SDValue NewMask = getUnpackhMask(NumElems, DAG); 4151 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4152 } 4153 } 4154 } 4155 4156 // Normalize the node to match x86 shuffle ops if needed 4157 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode())) 4158 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4159 4160 if (Commuted) { 4161 // Commute is back and try unpck* again. 4162 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4163 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4164 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4165 X86::isUNPCKLMask(PermMask.getNode()) || 4166 X86::isUNPCKHMask(PermMask.getNode())) 4167 return Op; 4168 } 4169 4170 // Try PSHUF* first, then SHUFP*. 4171 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically 4172 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. 4173 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) { 4174 if (V2.getOpcode() != ISD::UNDEF) 4175 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 4176 DAG.getNode(ISD::UNDEF, VT), PermMask); 4177 return Op; 4178 } 4179 4180 if (!isMMX) { 4181 if (Subtarget->hasSSE2() && 4182 (X86::isPSHUFDMask(PermMask.getNode()) || 4183 X86::isPSHUFHWMask(PermMask.getNode()) || 4184 X86::isPSHUFLWMask(PermMask.getNode()))) { 4185 MVT RVT = VT; 4186 if (VT == MVT::v4f32) { 4187 RVT = MVT::v4i32; 4188 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, 4189 DAG.getNode(ISD::BIT_CONVERT, RVT, V1), 4190 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4191 } else if (V2.getOpcode() != ISD::UNDEF) 4192 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1, 4193 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4194 if (RVT != VT) 4195 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); 4196 return Op; 4197 } 4198 4199 // Binary or unary shufps. 4200 if (X86::isSHUFPMask(PermMask.getNode()) || 4201 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode()))) 4202 return Op; 4203 } 4204 4205 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4206 if (VT == MVT::v8i16) { 4207 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); 4208 if (NewOp.getNode()) 4209 return NewOp; 4210 } 4211 4212 // Handle all 4 wide cases with a number of shuffles except for MMX. 4213 if (NumElems == 4 && !isMMX) 4214 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG); 4215 4216 return SDValue(); 4217} 4218 4219SDValue 4220X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4221 SelectionDAG &DAG) { 4222 MVT VT = Op.getValueType(); 4223 if (VT.getSizeInBits() == 8) { 4224 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, 4225 Op.getOperand(0), Op.getOperand(1)); 4226 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4227 DAG.getValueType(VT)); 4228 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4229 } else if (VT.getSizeInBits() == 16) { 4230 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4231 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4232 if (Idx == 0) 4233 return DAG.getNode(ISD::TRUNCATE, MVT::i16, 4234 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4235 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, 4236 Op.getOperand(0)), 4237 Op.getOperand(1))); 4238 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, 4239 Op.getOperand(0), Op.getOperand(1)); 4240 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4241 DAG.getValueType(VT)); 4242 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4243 } else if (VT == MVT::f32) { 4244 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4245 // the result back to FR32 register. It's only worth matching if the 4246 // result has a single use which is a store or a bitcast to i32. And in 4247 // the case of a store, it's not worth it if the index is a constant 0, 4248 // because a MOVSSmr can be used instead, which is smaller and faster. 4249 if (!Op.hasOneUse()) 4250 return SDValue(); 4251 SDNode *User = *Op.getNode()->use_begin(); 4252 if ((User->getOpcode() != ISD::STORE || 4253 (isa<ConstantSDNode>(Op.getOperand(1)) && 4254 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4255 (User->getOpcode() != ISD::BIT_CONVERT || 4256 User->getValueType(0) != MVT::i32)) 4257 return SDValue(); 4258 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4259 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), 4260 Op.getOperand(1)); 4261 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); 4262 } else if (VT == MVT::i32) { 4263 // ExtractPS works with constant index. 4264 if (isa<ConstantSDNode>(Op.getOperand(1))) 4265 return Op; 4266 } 4267 return SDValue(); 4268} 4269 4270 4271SDValue 4272X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4273 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4274 return SDValue(); 4275 4276 if (Subtarget->hasSSE41()) { 4277 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4278 if (Res.getNode()) 4279 return Res; 4280 } 4281 4282 MVT VT = Op.getValueType(); 4283 // TODO: handle v16i8. 4284 if (VT.getSizeInBits() == 16) { 4285 SDValue Vec = Op.getOperand(0); 4286 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4287 if (Idx == 0) 4288 return DAG.getNode(ISD::TRUNCATE, MVT::i16, 4289 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4290 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), 4291 Op.getOperand(1))); 4292 // Transform it so it match pextrw which produces a 32-bit result. 4293 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); 4294 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 4295 Op.getOperand(0), Op.getOperand(1)); 4296 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 4297 DAG.getValueType(VT)); 4298 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4299 } else if (VT.getSizeInBits() == 32) { 4300 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4301 if (Idx == 0) 4302 return Op; 4303 // SHUFPS the element to the lowest double word, then movss. 4304 MVT MaskVT = MVT::getIntVectorWithNumElements(4); 4305 SmallVector<SDValue, 8> IdxVec; 4306 IdxVec. 4307 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); 4308 IdxVec. 4309 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4310 IdxVec. 4311 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4312 IdxVec. 4313 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4314 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4315 &IdxVec[0], IdxVec.size()); 4316 SDValue Vec = Op.getOperand(0); 4317 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4318 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4319 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4320 DAG.getIntPtrConstant(0)); 4321 } else if (VT.getSizeInBits() == 64) { 4322 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4323 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4324 // to match extract_elt for f64. 4325 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4326 if (Idx == 0) 4327 return Op; 4328 4329 // UNPCKHPD the element to the lowest double word, then movsd. 4330 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4331 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4332 MVT MaskVT = MVT::getIntVectorWithNumElements(2); 4333 SmallVector<SDValue, 8> IdxVec; 4334 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); 4335 IdxVec. 4336 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4337 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4338 &IdxVec[0], IdxVec.size()); 4339 SDValue Vec = Op.getOperand(0); 4340 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4341 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4342 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4343 DAG.getIntPtrConstant(0)); 4344 } 4345 4346 return SDValue(); 4347} 4348 4349SDValue 4350X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4351 MVT VT = Op.getValueType(); 4352 MVT EVT = VT.getVectorElementType(); 4353 4354 SDValue N0 = Op.getOperand(0); 4355 SDValue N1 = Op.getOperand(1); 4356 SDValue N2 = Op.getOperand(2); 4357 4358 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4359 isa<ConstantSDNode>(N2)) { 4360 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4361 : X86ISD::PINSRW; 4362 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4363 // argument. 4364 if (N1.getValueType() != MVT::i32) 4365 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4366 if (N2.getValueType() != MVT::i32) 4367 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4368 return DAG.getNode(Opc, VT, N0, N1, N2); 4369 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4370 // Bits [7:6] of the constant are the source select. This will always be 4371 // zero here. The DAG Combiner may combine an extract_elt index into these 4372 // bits. For example (insert (extract, 3), 2) could be matched by putting 4373 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4374 // Bits [5:4] of the constant are the destination select. This is the 4375 // value of the incoming immediate. 4376 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4377 // combine either bitwise AND or insert of float 0.0 to set these bits. 4378 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4379 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); 4380 } else if (EVT == MVT::i32) { 4381 // InsertPS works with constant index. 4382 if (isa<ConstantSDNode>(N2)) 4383 return Op; 4384 } 4385 return SDValue(); 4386} 4387 4388SDValue 4389X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4390 MVT VT = Op.getValueType(); 4391 MVT EVT = VT.getVectorElementType(); 4392 4393 if (Subtarget->hasSSE41()) 4394 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4395 4396 if (EVT == MVT::i8) 4397 return SDValue(); 4398 4399 SDValue N0 = Op.getOperand(0); 4400 SDValue N1 = Op.getOperand(1); 4401 SDValue N2 = Op.getOperand(2); 4402 4403 if (EVT.getSizeInBits() == 16) { 4404 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4405 // as its second argument. 4406 if (N1.getValueType() != MVT::i32) 4407 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4408 if (N2.getValueType() != MVT::i32) 4409 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4410 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 4411 } 4412 return SDValue(); 4413} 4414 4415SDValue 4416X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4417 if (Op.getValueType() == MVT::v2f32) 4418 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32, 4419 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32, 4420 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, 4421 Op.getOperand(0)))); 4422 4423 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 4424 MVT VT = MVT::v2i32; 4425 switch (Op.getValueType().getSimpleVT()) { 4426 default: break; 4427 case MVT::v16i8: 4428 case MVT::v8i16: 4429 VT = MVT::v4i32; 4430 break; 4431 } 4432 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), 4433 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); 4434} 4435 4436// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4437// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4438// one of the above mentioned nodes. It has to be wrapped because otherwise 4439// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4440// be used to form addressing mode. These wrapped nodes will be selected 4441// into MOV32ri. 4442SDValue 4443X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4444 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4445 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), 4446 getPointerTy(), 4447 CP->getAlignment()); 4448 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4449 // With PIC, the address is actually $g + Offset. 4450 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4451 !Subtarget->isPICStyleRIPRel()) { 4452 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4453 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4454 Result); 4455 } 4456 4457 return Result; 4458} 4459 4460SDValue 4461X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, 4462 int64_t Offset, 4463 SelectionDAG &DAG) const { 4464 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 4465 bool ExtraLoadRequired = 4466 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false); 4467 4468 // Create the TargetGlobalAddress node, folding in the constant 4469 // offset if it is legal. 4470 SDValue Result; 4471 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) { 4472 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4473 Offset = 0; 4474 } else 4475 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0); 4476 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4477 4478 // With PIC, the address is actually $g + Offset. 4479 if (IsPic && !Subtarget->isPICStyleRIPRel()) { 4480 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4481 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4482 Result); 4483 } 4484 4485 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 4486 // load the value at address GV, not the value of GV itself. This means that 4487 // the GlobalAddress must be in the base or index register of the address, not 4488 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 4489 // The same applies for external symbols during PIC codegen 4490 if (ExtraLoadRequired) 4491 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, 4492 PseudoSourceValue::getGOT(), 0); 4493 4494 // If there was a non-zero offset that we didn't fold, create an explicit 4495 // addition for it. 4496 if (Offset != 0) 4497 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result, 4498 DAG.getConstant(Offset, getPointerTy())); 4499 4500 return Result; 4501} 4502 4503SDValue 4504X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4505 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4506 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4507 return LowerGlobalAddress(GV, Offset, DAG); 4508} 4509 4510// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4511static SDValue 4512LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4513 const MVT PtrVT) { 4514 SDValue InFlag; 4515 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, 4516 DAG.getNode(X86ISD::GlobalBaseReg, 4517 PtrVT), InFlag); 4518 InFlag = Chain.getValue(1); 4519 4520 // emit leal symbol@TLSGD(,%ebx,1), %eax 4521 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4522 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4523 GA->getValueType(0), 4524 GA->getOffset()); 4525 SDValue Ops[] = { Chain, TGA, InFlag }; 4526 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); 4527 InFlag = Result.getValue(2); 4528 Chain = Result.getValue(1); 4529 4530 // call ___tls_get_addr. This function receives its argument in 4531 // the register EAX. 4532 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); 4533 InFlag = Chain.getValue(1); 4534 4535 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4536 SDValue Ops1[] = { Chain, 4537 DAG.getTargetExternalSymbol("___tls_get_addr", 4538 PtrVT), 4539 DAG.getRegister(X86::EAX, PtrVT), 4540 DAG.getRegister(X86::EBX, PtrVT), 4541 InFlag }; 4542 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); 4543 InFlag = Chain.getValue(1); 4544 4545 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); 4546} 4547 4548// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4549static SDValue 4550LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4551 const MVT PtrVT) { 4552 SDValue InFlag, Chain; 4553 4554 // emit leaq symbol@TLSGD(%rip), %rdi 4555 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4556 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4557 GA->getValueType(0), 4558 GA->getOffset()); 4559 SDValue Ops[] = { DAG.getEntryNode(), TGA}; 4560 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); 4561 Chain = Result.getValue(1); 4562 InFlag = Result.getValue(2); 4563 4564 // call __tls_get_addr. This function receives its argument in 4565 // the register RDI. 4566 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag); 4567 InFlag = Chain.getValue(1); 4568 4569 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4570 SDValue Ops1[] = { Chain, 4571 DAG.getTargetExternalSymbol("__tls_get_addr", 4572 PtrVT), 4573 DAG.getRegister(X86::RDI, PtrVT), 4574 InFlag }; 4575 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4); 4576 InFlag = Chain.getValue(1); 4577 4578 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag); 4579} 4580 4581// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4582// "local exec" model. 4583static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4584 const MVT PtrVT) { 4585 // Get the Thread Pointer 4586 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); 4587 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4588 // exec) 4589 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4590 GA->getValueType(0), 4591 GA->getOffset()); 4592 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); 4593 4594 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model 4595 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, 4596 PseudoSourceValue::getGOT(), 0); 4597 4598 // The address of the thread local variable is the add of the thread 4599 // pointer with the offset of the variable. 4600 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 4601} 4602 4603SDValue 4604X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4605 // TODO: implement the "local dynamic" model 4606 // TODO: implement the "initial exec"model for pic executables 4607 assert(Subtarget->isTargetELF() && 4608 "TLS not implemented for non-ELF targets"); 4609 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4610 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 4611 // otherwise use the "Local Exec"TLS Model 4612 if (Subtarget->is64Bit()) { 4613 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4614 } else { 4615 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 4616 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4617 else 4618 return LowerToTLSExecModel(GA, DAG, getPointerTy()); 4619 } 4620} 4621 4622SDValue 4623X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4624 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4625 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 4626 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4627 // With PIC, the address is actually $g + Offset. 4628 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4629 !Subtarget->isPICStyleRIPRel()) { 4630 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4631 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4632 Result); 4633 } 4634 4635 return Result; 4636} 4637 4638SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4639 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4640 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 4641 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4642 // With PIC, the address is actually $g + Offset. 4643 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4644 !Subtarget->isPICStyleRIPRel()) { 4645 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4646 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4647 Result); 4648 } 4649 4650 return Result; 4651} 4652 4653/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4654/// take a 2 x i32 value to shift plus a shift amount. 4655SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4656 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4657 MVT VT = Op.getValueType(); 4658 unsigned VTBits = VT.getSizeInBits(); 4659 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4660 SDValue ShOpLo = Op.getOperand(0); 4661 SDValue ShOpHi = Op.getOperand(1); 4662 SDValue ShAmt = Op.getOperand(2); 4663 SDValue Tmp1 = isSRA ? 4664 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : 4665 DAG.getConstant(0, VT); 4666 4667 SDValue Tmp2, Tmp3; 4668 if (Op.getOpcode() == ISD::SHL_PARTS) { 4669 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); 4670 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); 4671 } else { 4672 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); 4673 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); 4674 } 4675 4676 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 4677 DAG.getConstant(VTBits, MVT::i8)); 4678 SDValue Cond = DAG.getNode(X86ISD::CMP, VT, 4679 AndNode, DAG.getConstant(0, MVT::i8)); 4680 4681 SDValue Hi, Lo; 4682 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4683 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4684 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4685 4686 if (Op.getOpcode() == ISD::SHL_PARTS) { 4687 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4688 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4689 } else { 4690 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4691 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4692 } 4693 4694 SDValue Ops[2] = { Lo, Hi }; 4695 return DAG.getMergeValues(Ops, 2); 4696} 4697 4698SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4699 MVT SrcVT = Op.getOperand(0).getValueType(); 4700 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4701 "Unknown SINT_TO_FP to lower!"); 4702 4703 // These are really Legal; caller falls through into that case. 4704 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4705 return SDValue(); 4706 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && 4707 Subtarget->is64Bit()) 4708 return SDValue(); 4709 4710 unsigned Size = SrcVT.getSizeInBits()/8; 4711 MachineFunction &MF = DAG.getMachineFunction(); 4712 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4713 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4714 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 4715 StackSlot, 4716 PseudoSourceValue::getFixedStack(SSFI), 0); 4717 4718 // Build the FILD 4719 SDVTList Tys; 4720 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4721 if (useSSE) 4722 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4723 else 4724 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4725 SmallVector<SDValue, 8> Ops; 4726 Ops.push_back(Chain); 4727 Ops.push_back(StackSlot); 4728 Ops.push_back(DAG.getValueType(SrcVT)); 4729 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, 4730 Tys, &Ops[0], Ops.size()); 4731 4732 if (useSSE) { 4733 Chain = Result.getValue(1); 4734 SDValue InFlag = Result.getValue(2); 4735 4736 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4737 // shouldn't be necessary except that RFP cannot be live across 4738 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4739 MachineFunction &MF = DAG.getMachineFunction(); 4740 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4741 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4742 Tys = DAG.getVTList(MVT::Other); 4743 SmallVector<SDValue, 8> Ops; 4744 Ops.push_back(Chain); 4745 Ops.push_back(Result); 4746 Ops.push_back(StackSlot); 4747 Ops.push_back(DAG.getValueType(Op.getValueType())); 4748 Ops.push_back(InFlag); 4749 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 4750 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 4751 PseudoSourceValue::getFixedStack(SSFI), 0); 4752 } 4753 4754 return Result; 4755} 4756 4757// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 4758SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 4759 // This algorithm is not obvious. Here it is in C code, more or less: 4760 /* 4761 double uint64_to_double( uint32_t hi, uint32_t lo ) { 4762 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 4763 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 4764 4765 // Copy ints to xmm registers. 4766 __m128i xh = _mm_cvtsi32_si128( hi ); 4767 __m128i xl = _mm_cvtsi32_si128( lo ); 4768 4769 // Combine into low half of a single xmm register. 4770 __m128i x = _mm_unpacklo_epi32( xh, xl ); 4771 __m128d d; 4772 double sd; 4773 4774 // Merge in appropriate exponents to give the integer bits the right 4775 // magnitude. 4776 x = _mm_unpacklo_epi32( x, exp ); 4777 4778 // Subtract away the biases to deal with the IEEE-754 double precision 4779 // implicit 1. 4780 d = _mm_sub_pd( (__m128d) x, bias ); 4781 4782 // All conversions up to here are exact. The correctly rounded result is 4783 // calculated using the current rounding mode using the following 4784 // horizontal add. 4785 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 4786 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 4787 // store doesn't really need to be here (except 4788 // maybe to zero the other double) 4789 return sd; 4790 } 4791 */ 4792 4793 // Build some magic constants. 4794 std::vector<Constant*> CV0; 4795 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000))); 4796 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000))); 4797 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4798 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4799 Constant *C0 = ConstantVector::get(CV0); 4800 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4); 4801 4802 std::vector<Constant*> CV1; 4803 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL)))); 4804 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL)))); 4805 Constant *C1 = ConstantVector::get(CV1); 4806 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4); 4807 4808 SmallVector<SDValue, 4> MaskVec; 4809 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 4810 MaskVec.push_back(DAG.getConstant(4, MVT::i32)); 4811 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 4812 MaskVec.push_back(DAG.getConstant(5, MVT::i32)); 4813 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0], 4814 MaskVec.size()); 4815 SmallVector<SDValue, 4> MaskVec2; 4816 MaskVec2.push_back(DAG.getConstant(1, MVT::i32)); 4817 MaskVec2.push_back(DAG.getConstant(0, MVT::i32)); 4818 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0], 4819 MaskVec2.size()); 4820 4821 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, 4822 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 4823 Op.getOperand(0), 4824 DAG.getIntPtrConstant(1))); 4825 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, 4826 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 4827 Op.getOperand(0), 4828 DAG.getIntPtrConstant(0))); 4829 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, 4830 XR1, XR2, UnpcklMask); 4831 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0, 4832 PseudoSourceValue::getConstantPool(), 0, 4833 false, 16); 4834 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, 4835 Unpck1, CLod0, UnpcklMask); 4836 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2); 4837 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1, 4838 PseudoSourceValue::getConstantPool(), 0, 4839 false, 16); 4840 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1); 4841 4842 // Add the halves; easiest way is to swap them into another reg first. 4843 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64, 4844 Sub, Sub, ShufMask); 4845 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub); 4846 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add, 4847 DAG.getIntPtrConstant(0)); 4848} 4849 4850// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 4851SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 4852 // FP constant to bias correct the final result. 4853 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 4854 MVT::f64); 4855 4856 // Load the 32-bit value into an XMM register. 4857 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, 4858 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 4859 Op.getOperand(0), 4860 DAG.getIntPtrConstant(0))); 4861 4862 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, 4863 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Load), 4864 DAG.getIntPtrConstant(0)); 4865 4866 // Or the load with the bias. 4867 SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64, 4868 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, 4869 DAG.getNode(ISD::SCALAR_TO_VECTOR, 4870 MVT::v2f64, Load)), 4871 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, 4872 DAG.getNode(ISD::SCALAR_TO_VECTOR, 4873 MVT::v2f64, Bias))); 4874 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, 4875 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or), 4876 DAG.getIntPtrConstant(0)); 4877 4878 // Subtract the bias. 4879 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Or, Bias); 4880 4881 // Handle final rounding. 4882 MVT DestVT = Op.getValueType(); 4883 4884 if (DestVT.bitsLT(MVT::f64)) { 4885 return DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 4886 DAG.getIntPtrConstant(0)); 4887 } else if (DestVT.bitsGT(MVT::f64)) { 4888 return DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 4889 } 4890 4891 // Handle final rounding. 4892 return Sub; 4893} 4894 4895SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4896 SDValue N0 = Op.getOperand(0); 4897 4898 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 4899 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 4900 // the optimization here. 4901 if (DAG.SignBitIsZero(N0)) 4902 return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0); 4903 4904 MVT SrcVT = N0.getValueType(); 4905 if (SrcVT == MVT::i64) { 4906 // We only handle SSE2 f64 target here; caller can handle the rest. 4907 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 4908 return SDValue(); 4909 4910 return LowerUINT_TO_FP_i64(Op, DAG); 4911 } else if (SrcVT == MVT::i32) { 4912 return LowerUINT_TO_FP_i32(Op, DAG); 4913 } 4914 4915 assert(0 && "Unknown UINT_TO_FP to lower!"); 4916 return SDValue(); 4917} 4918 4919std::pair<SDValue,SDValue> X86TargetLowering:: 4920FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { 4921 assert(Op.getValueType().getSimpleVT() <= MVT::i64 && 4922 Op.getValueType().getSimpleVT() >= MVT::i16 && 4923 "Unknown FP_TO_SINT to lower!"); 4924 4925 // These are really Legal. 4926 if (Op.getValueType() == MVT::i32 && 4927 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 4928 return std::make_pair(SDValue(), SDValue()); 4929 if (Subtarget->is64Bit() && 4930 Op.getValueType() == MVT::i64 && 4931 Op.getOperand(0).getValueType() != MVT::f80) 4932 return std::make_pair(SDValue(), SDValue()); 4933 4934 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 4935 // stack slot. 4936 MachineFunction &MF = DAG.getMachineFunction(); 4937 unsigned MemSize = Op.getValueType().getSizeInBits()/8; 4938 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4939 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4940 unsigned Opc; 4941 switch (Op.getValueType().getSimpleVT()) { 4942 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 4943 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 4944 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 4945 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 4946 } 4947 4948 SDValue Chain = DAG.getEntryNode(); 4949 SDValue Value = Op.getOperand(0); 4950 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 4951 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 4952 Chain = DAG.getStore(Chain, Value, StackSlot, 4953 PseudoSourceValue::getFixedStack(SSFI), 0); 4954 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 4955 SDValue Ops[] = { 4956 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 4957 }; 4958 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 4959 Chain = Value.getValue(1); 4960 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4961 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4962 } 4963 4964 // Build the FP_TO_INT*_IN_MEM 4965 SDValue Ops[] = { Chain, Value, StackSlot }; 4966 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); 4967 4968 return std::make_pair(FIST, StackSlot); 4969} 4970 4971SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 4972 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG); 4973 SDValue FIST = Vals.first, StackSlot = Vals.second; 4974 if (FIST.getNode() == 0) return SDValue(); 4975 4976 // Load the result. 4977 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 4978} 4979 4980SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 4981 MVT VT = Op.getValueType(); 4982 MVT EltVT = VT; 4983 if (VT.isVector()) 4984 EltVT = VT.getVectorElementType(); 4985 std::vector<Constant*> CV; 4986 if (EltVT == MVT::f64) { 4987 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); 4988 CV.push_back(C); 4989 CV.push_back(C); 4990 } else { 4991 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); 4992 CV.push_back(C); 4993 CV.push_back(C); 4994 CV.push_back(C); 4995 CV.push_back(C); 4996 } 4997 Constant *C = ConstantVector::get(CV); 4998 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4999 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5000 PseudoSourceValue::getConstantPool(), 0, 5001 false, 16); 5002 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 5003} 5004 5005SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5006 MVT VT = Op.getValueType(); 5007 MVT EltVT = VT; 5008 unsigned EltNum = 1; 5009 if (VT.isVector()) { 5010 EltVT = VT.getVectorElementType(); 5011 EltNum = VT.getVectorNumElements(); 5012 } 5013 std::vector<Constant*> CV; 5014 if (EltVT == MVT::f64) { 5015 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); 5016 CV.push_back(C); 5017 CV.push_back(C); 5018 } else { 5019 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); 5020 CV.push_back(C); 5021 CV.push_back(C); 5022 CV.push_back(C); 5023 CV.push_back(C); 5024 } 5025 Constant *C = ConstantVector::get(CV); 5026 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5027 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5028 PseudoSourceValue::getConstantPool(), 0, 5029 false, 16); 5030 if (VT.isVector()) { 5031 return DAG.getNode(ISD::BIT_CONVERT, VT, 5032 DAG.getNode(ISD::XOR, MVT::v2i64, 5033 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), 5034 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); 5035 } else { 5036 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 5037 } 5038} 5039 5040SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5041 SDValue Op0 = Op.getOperand(0); 5042 SDValue Op1 = Op.getOperand(1); 5043 MVT VT = Op.getValueType(); 5044 MVT SrcVT = Op1.getValueType(); 5045 5046 // If second operand is smaller, extend it first. 5047 if (SrcVT.bitsLT(VT)) { 5048 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 5049 SrcVT = VT; 5050 } 5051 // And if it is bigger, shrink it first. 5052 if (SrcVT.bitsGT(VT)) { 5053 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); 5054 SrcVT = VT; 5055 } 5056 5057 // At this point the operands and the result should have the same 5058 // type, and that won't be f80 since that is not custom lowered. 5059 5060 // First get the sign bit of second operand. 5061 std::vector<Constant*> CV; 5062 if (SrcVT == MVT::f64) { 5063 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); 5064 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5065 } else { 5066 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); 5067 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5068 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5069 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5070 } 5071 Constant *C = ConstantVector::get(CV); 5072 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5073 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, 5074 PseudoSourceValue::getConstantPool(), 0, 5075 false, 16); 5076 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 5077 5078 // Shift sign bit right or left if the two operands have different types. 5079 if (SrcVT.bitsGT(VT)) { 5080 // Op0 is MVT::f32, Op1 is MVT::f64. 5081 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 5082 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 5083 DAG.getConstant(32, MVT::i32)); 5084 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 5085 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 5086 DAG.getIntPtrConstant(0)); 5087 } 5088 5089 // Clear first operand sign bit. 5090 CV.clear(); 5091 if (VT == MVT::f64) { 5092 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); 5093 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5094 } else { 5095 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); 5096 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5097 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5098 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5099 } 5100 C = ConstantVector::get(CV); 5101 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5102 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5103 PseudoSourceValue::getConstantPool(), 0, 5104 false, 16); 5105 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 5106 5107 // Or the value with the sign bit. 5108 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 5109} 5110 5111SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5112 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5113 SDValue Op0 = Op.getOperand(0); 5114 SDValue Op1 = Op.getOperand(1); 5115 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5116 5117 // Lower (X & (1 << N)) == 0 to BT(X, N). 5118 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5119 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5120 if (Op0.getOpcode() == ISD::AND && 5121 Op0.hasOneUse() && 5122 Op1.getOpcode() == ISD::Constant && 5123 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5124 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5125 SDValue LHS, RHS; 5126 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5127 if (ConstantSDNode *Op010C = 5128 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5129 if (Op010C->getZExtValue() == 1) { 5130 LHS = Op0.getOperand(0); 5131 RHS = Op0.getOperand(1).getOperand(1); 5132 } 5133 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5134 if (ConstantSDNode *Op000C = 5135 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5136 if (Op000C->getZExtValue() == 1) { 5137 LHS = Op0.getOperand(1); 5138 RHS = Op0.getOperand(0).getOperand(1); 5139 } 5140 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5141 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5142 SDValue AndLHS = Op0.getOperand(0); 5143 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5144 LHS = AndLHS.getOperand(0); 5145 RHS = AndLHS.getOperand(1); 5146 } 5147 } 5148 5149 if (LHS.getNode()) { 5150 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5151 // instruction. Since the shift amount is in-range-or-undefined, we know 5152 // that doing a bittest on the i16 value is ok. We extend to i32 because 5153 // the encoding for the i16 version is larger than the i32 version. 5154 if (LHS.getValueType() == MVT::i8) 5155 LHS = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, LHS); 5156 5157 // If the operand types disagree, extend the shift amount to match. Since 5158 // BT ignores high bits (like shifts) we can use anyextend. 5159 if (LHS.getValueType() != RHS.getValueType()) 5160 RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS); 5161 5162 SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS); 5163 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5164 return DAG.getNode(X86ISD::SETCC, MVT::i8, 5165 DAG.getConstant(Cond, MVT::i8), BT); 5166 } 5167 } 5168 5169 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5170 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5171 5172 SDValue Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 5173 return DAG.getNode(X86ISD::SETCC, MVT::i8, 5174 DAG.getConstant(X86CC, MVT::i8), Cond); 5175} 5176 5177SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5178 SDValue Cond; 5179 SDValue Op0 = Op.getOperand(0); 5180 SDValue Op1 = Op.getOperand(1); 5181 SDValue CC = Op.getOperand(2); 5182 MVT VT = Op.getValueType(); 5183 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5184 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5185 5186 if (isFP) { 5187 unsigned SSECC = 8; 5188 MVT VT0 = Op0.getValueType(); 5189 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5190 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5191 bool Swap = false; 5192 5193 switch (SetCCOpcode) { 5194 default: break; 5195 case ISD::SETOEQ: 5196 case ISD::SETEQ: SSECC = 0; break; 5197 case ISD::SETOGT: 5198 case ISD::SETGT: Swap = true; // Fallthrough 5199 case ISD::SETLT: 5200 case ISD::SETOLT: SSECC = 1; break; 5201 case ISD::SETOGE: 5202 case ISD::SETGE: Swap = true; // Fallthrough 5203 case ISD::SETLE: 5204 case ISD::SETOLE: SSECC = 2; break; 5205 case ISD::SETUO: SSECC = 3; break; 5206 case ISD::SETUNE: 5207 case ISD::SETNE: SSECC = 4; break; 5208 case ISD::SETULE: Swap = true; 5209 case ISD::SETUGE: SSECC = 5; break; 5210 case ISD::SETULT: Swap = true; 5211 case ISD::SETUGT: SSECC = 6; break; 5212 case ISD::SETO: SSECC = 7; break; 5213 } 5214 if (Swap) 5215 std::swap(Op0, Op1); 5216 5217 // In the two special cases we can't handle, emit two comparisons. 5218 if (SSECC == 8) { 5219 if (SetCCOpcode == ISD::SETUEQ) { 5220 SDValue UNORD, EQ; 5221 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5222 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5223 return DAG.getNode(ISD::OR, VT, UNORD, EQ); 5224 } 5225 else if (SetCCOpcode == ISD::SETONE) { 5226 SDValue ORD, NEQ; 5227 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5228 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5229 return DAG.getNode(ISD::AND, VT, ORD, NEQ); 5230 } 5231 assert(0 && "Illegal FP comparison"); 5232 } 5233 // Handle all other FP comparisons here. 5234 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5235 } 5236 5237 // We are handling one of the integer comparisons here. Since SSE only has 5238 // GT and EQ comparisons for integer, swapping operands and multiple 5239 // operations may be required for some comparisons. 5240 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5241 bool Swap = false, Invert = false, FlipSigns = false; 5242 5243 switch (VT.getSimpleVT()) { 5244 default: break; 5245 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5246 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5247 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5248 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5249 } 5250 5251 switch (SetCCOpcode) { 5252 default: break; 5253 case ISD::SETNE: Invert = true; 5254 case ISD::SETEQ: Opc = EQOpc; break; 5255 case ISD::SETLT: Swap = true; 5256 case ISD::SETGT: Opc = GTOpc; break; 5257 case ISD::SETGE: Swap = true; 5258 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5259 case ISD::SETULT: Swap = true; 5260 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5261 case ISD::SETUGE: Swap = true; 5262 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5263 } 5264 if (Swap) 5265 std::swap(Op0, Op1); 5266 5267 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5268 // bits of the inputs before performing those operations. 5269 if (FlipSigns) { 5270 MVT EltVT = VT.getVectorElementType(); 5271 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT); 5272 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5273 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], 5274 SignBits.size()); 5275 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec); 5276 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec); 5277 } 5278 5279 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1); 5280 5281 // If the logical-not of the result is required, perform that now. 5282 if (Invert) 5283 Result = DAG.getNOT(Result, VT); 5284 5285 return Result; 5286} 5287 5288// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5289static bool isX86LogicalCmp(unsigned Opc) { 5290 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI; 5291} 5292 5293SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5294 bool addTest = true; 5295 SDValue Cond = Op.getOperand(0); 5296 SDValue CC; 5297 5298 if (Cond.getOpcode() == ISD::SETCC) 5299 Cond = LowerSETCC(Cond, DAG); 5300 5301 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5302 // setting operand in place of the X86ISD::SETCC. 5303 if (Cond.getOpcode() == X86ISD::SETCC) { 5304 CC = Cond.getOperand(0); 5305 5306 SDValue Cmp = Cond.getOperand(1); 5307 unsigned Opc = Cmp.getOpcode(); 5308 MVT VT = Op.getValueType(); 5309 5310 bool IllegalFPCMov = false; 5311 if (VT.isFloatingPoint() && !VT.isVector() && 5312 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5313 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5314 5315 if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME 5316 Cond = Cmp; 5317 addTest = false; 5318 } 5319 } 5320 5321 if (addTest) { 5322 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5323 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 5324 } 5325 5326 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), 5327 MVT::Flag); 5328 SmallVector<SDValue, 4> Ops; 5329 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5330 // condition is true. 5331 Ops.push_back(Op.getOperand(2)); 5332 Ops.push_back(Op.getOperand(1)); 5333 Ops.push_back(CC); 5334 Ops.push_back(Cond); 5335 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 5336} 5337 5338// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5339// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5340// from the AND / OR. 5341static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5342 Opc = Op.getOpcode(); 5343 if (Opc != ISD::OR && Opc != ISD::AND) 5344 return false; 5345 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5346 Op.getOperand(0).hasOneUse() && 5347 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5348 Op.getOperand(1).hasOneUse()); 5349} 5350 5351SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5352 bool addTest = true; 5353 SDValue Chain = Op.getOperand(0); 5354 SDValue Cond = Op.getOperand(1); 5355 SDValue Dest = Op.getOperand(2); 5356 SDValue CC; 5357 5358 if (Cond.getOpcode() == ISD::SETCC) 5359 Cond = LowerSETCC(Cond, DAG); 5360#if 0 5361 // FIXME: LowerXALUO doesn't handle these!! 5362 else if (Cond.getOpcode() == X86ISD::ADD || 5363 Cond.getOpcode() == X86ISD::SUB || 5364 Cond.getOpcode() == X86ISD::SMUL || 5365 Cond.getOpcode() == X86ISD::UMUL) 5366 Cond = LowerXALUO(Cond, DAG); 5367#endif 5368 5369 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5370 // setting operand in place of the X86ISD::SETCC. 5371 if (Cond.getOpcode() == X86ISD::SETCC) { 5372 CC = Cond.getOperand(0); 5373 5374 SDValue Cmp = Cond.getOperand(1); 5375 unsigned Opc = Cmp.getOpcode(); 5376 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 5377 if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) { 5378 Cond = Cmp; 5379 addTest = false; 5380 } else { 5381 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5382 default: break; 5383 case X86::COND_O: 5384 case X86::COND_B: 5385 // These can only come from an arithmetic instruction with overflow, 5386 // e.g. SADDO, UADDO. 5387 Cond = Cond.getNode()->getOperand(1); 5388 addTest = false; 5389 break; 5390 } 5391 } 5392 } else { 5393 unsigned CondOpc; 5394 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5395 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5396 unsigned Opc = Cmp.getOpcode(); 5397 if (CondOpc == ISD::OR) { 5398 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5399 // two branches instead of an explicit OR instruction with a 5400 // separate test. 5401 if (Cmp == Cond.getOperand(1).getOperand(1) && 5402 isX86LogicalCmp(Opc)) { 5403 CC = Cond.getOperand(0).getOperand(0); 5404 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5405 Chain, Dest, CC, Cmp); 5406 CC = Cond.getOperand(1).getOperand(0); 5407 Cond = Cmp; 5408 addTest = false; 5409 } 5410 } else { // ISD::AND 5411 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5412 // two branches instead of an explicit AND instruction with a 5413 // separate test. However, we only do this if this block doesn't 5414 // have a fall-through edge, because this requires an explicit 5415 // jmp when the condition is false. 5416 if (Cmp == Cond.getOperand(1).getOperand(1) && 5417 isX86LogicalCmp(Opc) && 5418 Op.getNode()->hasOneUse()) { 5419 X86::CondCode CCode = 5420 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5421 CCode = X86::GetOppositeBranchCondition(CCode); 5422 CC = DAG.getConstant(CCode, MVT::i8); 5423 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5424 // Look for an unconditional branch following this conditional branch. 5425 // We need this because we need to reverse the successors in order 5426 // to implement FCMP_OEQ. 5427 if (User.getOpcode() == ISD::BR) { 5428 SDValue FalseBB = User.getOperand(1); 5429 SDValue NewBR = 5430 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5431 assert(NewBR == User); 5432 Dest = FalseBB; 5433 5434 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5435 Chain, Dest, CC, Cmp); 5436 X86::CondCode CCode = 5437 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5438 CCode = X86::GetOppositeBranchCondition(CCode); 5439 CC = DAG.getConstant(CCode, MVT::i8); 5440 Cond = Cmp; 5441 addTest = false; 5442 } 5443 } 5444 } 5445 } 5446 } 5447 5448 if (addTest) { 5449 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5450 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 5451 } 5452 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5453 Chain, Dest, CC, Cond); 5454} 5455 5456 5457// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5458// Calls to _alloca is needed to probe the stack when allocating more than 4k 5459// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5460// that the guard pages used by the OS virtual memory manager are allocated in 5461// correct sequence. 5462SDValue 5463X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5464 SelectionDAG &DAG) { 5465 assert(Subtarget->isTargetCygMing() && 5466 "This should be used only on Cygwin/Mingw targets"); 5467 5468 // Get the inputs. 5469 SDValue Chain = Op.getOperand(0); 5470 SDValue Size = Op.getOperand(1); 5471 // FIXME: Ensure alignment here 5472 5473 SDValue Flag; 5474 5475 MVT IntPtr = getPointerTy(); 5476 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5477 5478 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5479 5480 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); 5481 Flag = Chain.getValue(1); 5482 5483 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5484 SDValue Ops[] = { Chain, 5485 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5486 DAG.getRegister(X86::EAX, IntPtr), 5487 DAG.getRegister(X86StackPtr, SPTy), 5488 Flag }; 5489 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5); 5490 Flag = Chain.getValue(1); 5491 5492 Chain = DAG.getCALLSEQ_END(Chain, 5493 DAG.getIntPtrConstant(0, true), 5494 DAG.getIntPtrConstant(0, true), 5495 Flag); 5496 5497 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); 5498 5499 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5500 return DAG.getMergeValues(Ops1, 2); 5501} 5502 5503SDValue 5504X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, 5505 SDValue Chain, 5506 SDValue Dst, SDValue Src, 5507 SDValue Size, unsigned Align, 5508 const Value *DstSV, 5509 uint64_t DstSVOff) { 5510 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5511 5512 // If not DWORD aligned or size is more than the threshold, call the library. 5513 // The libc version is likely to be faster for these cases. It can use the 5514 // address value and run time information about the CPU. 5515 if ((Align & 3) != 0 || 5516 !ConstantSize || 5517 ConstantSize->getZExtValue() > 5518 getSubtarget()->getMaxInlineSizeThreshold()) { 5519 SDValue InFlag(0, 0); 5520 5521 // Check to see if there is a specialized entry-point for memory zeroing. 5522 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5523 5524 if (const char *bzeroEntry = V && 5525 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5526 MVT IntPtr = getPointerTy(); 5527 const Type *IntPtrTy = TD->getIntPtrType(); 5528 TargetLowering::ArgListTy Args; 5529 TargetLowering::ArgListEntry Entry; 5530 Entry.Node = Dst; 5531 Entry.Ty = IntPtrTy; 5532 Args.push_back(Entry); 5533 Entry.Node = Size; 5534 Args.push_back(Entry); 5535 std::pair<SDValue,SDValue> CallResult = 5536 LowerCallTo(Chain, Type::VoidTy, false, false, false, false, 5537 CallingConv::C, false, 5538 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG); 5539 return CallResult.second; 5540 } 5541 5542 // Otherwise have the target-independent code call memset. 5543 return SDValue(); 5544 } 5545 5546 uint64_t SizeVal = ConstantSize->getZExtValue(); 5547 SDValue InFlag(0, 0); 5548 MVT AVT; 5549 SDValue Count; 5550 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5551 unsigned BytesLeft = 0; 5552 bool TwoRepStos = false; 5553 if (ValC) { 5554 unsigned ValReg; 5555 uint64_t Val = ValC->getZExtValue() & 255; 5556 5557 // If the value is a constant, then we can potentially use larger sets. 5558 switch (Align & 3) { 5559 case 2: // WORD aligned 5560 AVT = MVT::i16; 5561 ValReg = X86::AX; 5562 Val = (Val << 8) | Val; 5563 break; 5564 case 0: // DWORD aligned 5565 AVT = MVT::i32; 5566 ValReg = X86::EAX; 5567 Val = (Val << 8) | Val; 5568 Val = (Val << 16) | Val; 5569 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5570 AVT = MVT::i64; 5571 ValReg = X86::RAX; 5572 Val = (Val << 32) | Val; 5573 } 5574 break; 5575 default: // Byte aligned 5576 AVT = MVT::i8; 5577 ValReg = X86::AL; 5578 Count = DAG.getIntPtrConstant(SizeVal); 5579 break; 5580 } 5581 5582 if (AVT.bitsGT(MVT::i8)) { 5583 unsigned UBytes = AVT.getSizeInBits() / 8; 5584 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5585 BytesLeft = SizeVal % UBytes; 5586 } 5587 5588 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 5589 InFlag); 5590 InFlag = Chain.getValue(1); 5591 } else { 5592 AVT = MVT::i8; 5593 Count = DAG.getIntPtrConstant(SizeVal); 5594 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag); 5595 InFlag = Chain.getValue(1); 5596 } 5597 5598 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5599 Count, InFlag); 5600 InFlag = Chain.getValue(1); 5601 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5602 Dst, InFlag); 5603 InFlag = Chain.getValue(1); 5604 5605 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5606 SmallVector<SDValue, 8> Ops; 5607 Ops.push_back(Chain); 5608 Ops.push_back(DAG.getValueType(AVT)); 5609 Ops.push_back(InFlag); 5610 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5611 5612 if (TwoRepStos) { 5613 InFlag = Chain.getValue(1); 5614 Count = Size; 5615 MVT CVT = Count.getValueType(); 5616 SDValue Left = DAG.getNode(ISD::AND, CVT, Count, 5617 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5618 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 5619 Left, InFlag); 5620 InFlag = Chain.getValue(1); 5621 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5622 Ops.clear(); 5623 Ops.push_back(Chain); 5624 Ops.push_back(DAG.getValueType(MVT::i8)); 5625 Ops.push_back(InFlag); 5626 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5627 } else if (BytesLeft) { 5628 // Handle the last 1 - 7 bytes. 5629 unsigned Offset = SizeVal - BytesLeft; 5630 MVT AddrVT = Dst.getValueType(); 5631 MVT SizeVT = Size.getValueType(); 5632 5633 Chain = DAG.getMemset(Chain, 5634 DAG.getNode(ISD::ADD, AddrVT, Dst, 5635 DAG.getConstant(Offset, AddrVT)), 5636 Src, 5637 DAG.getConstant(BytesLeft, SizeVT), 5638 Align, DstSV, DstSVOff + Offset); 5639 } 5640 5641 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5642 return Chain; 5643} 5644 5645SDValue 5646X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 5647 SDValue Chain, SDValue Dst, SDValue Src, 5648 SDValue Size, unsigned Align, 5649 bool AlwaysInline, 5650 const Value *DstSV, uint64_t DstSVOff, 5651 const Value *SrcSV, uint64_t SrcSVOff) { 5652 // This requires the copy size to be a constant, preferrably 5653 // within a subtarget-specific limit. 5654 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5655 if (!ConstantSize) 5656 return SDValue(); 5657 uint64_t SizeVal = ConstantSize->getZExtValue(); 5658 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5659 return SDValue(); 5660 5661 /// If not DWORD aligned, call the library. 5662 if ((Align & 3) != 0) 5663 return SDValue(); 5664 5665 // DWORD aligned 5666 MVT AVT = MVT::i32; 5667 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5668 AVT = MVT::i64; 5669 5670 unsigned UBytes = AVT.getSizeInBits() / 8; 5671 unsigned CountVal = SizeVal / UBytes; 5672 SDValue Count = DAG.getIntPtrConstant(CountVal); 5673 unsigned BytesLeft = SizeVal % UBytes; 5674 5675 SDValue InFlag(0, 0); 5676 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5677 Count, InFlag); 5678 InFlag = Chain.getValue(1); 5679 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5680 Dst, InFlag); 5681 InFlag = Chain.getValue(1); 5682 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 5683 Src, InFlag); 5684 InFlag = Chain.getValue(1); 5685 5686 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5687 SmallVector<SDValue, 8> Ops; 5688 Ops.push_back(Chain); 5689 Ops.push_back(DAG.getValueType(AVT)); 5690 Ops.push_back(InFlag); 5691 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 5692 5693 SmallVector<SDValue, 4> Results; 5694 Results.push_back(RepMovs); 5695 if (BytesLeft) { 5696 // Handle the last 1 - 7 bytes. 5697 unsigned Offset = SizeVal - BytesLeft; 5698 MVT DstVT = Dst.getValueType(); 5699 MVT SrcVT = Src.getValueType(); 5700 MVT SizeVT = Size.getValueType(); 5701 Results.push_back(DAG.getMemcpy(Chain, 5702 DAG.getNode(ISD::ADD, DstVT, Dst, 5703 DAG.getConstant(Offset, DstVT)), 5704 DAG.getNode(ISD::ADD, SrcVT, Src, 5705 DAG.getConstant(Offset, SrcVT)), 5706 DAG.getConstant(BytesLeft, SizeVT), 5707 Align, AlwaysInline, 5708 DstSV, DstSVOff + Offset, 5709 SrcSV, SrcSVOff + Offset)); 5710 } 5711 5712 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size()); 5713} 5714 5715SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 5716 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 5717 5718 if (!Subtarget->is64Bit()) { 5719 // vastart just stores the address of the VarArgsFrameIndex slot into the 5720 // memory location argument. 5721 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5722 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); 5723 } 5724 5725 // __va_list_tag: 5726 // gp_offset (0 - 6 * 8) 5727 // fp_offset (48 - 48 + 8 * 16) 5728 // overflow_arg_area (point to parameters coming in memory). 5729 // reg_save_area 5730 SmallVector<SDValue, 8> MemOps; 5731 SDValue FIN = Op.getOperand(1); 5732 // Store gp_offset 5733 SDValue Store = DAG.getStore(Op.getOperand(0), 5734 DAG.getConstant(VarArgsGPOffset, MVT::i32), 5735 FIN, SV, 0); 5736 MemOps.push_back(Store); 5737 5738 // Store fp_offset 5739 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5740 Store = DAG.getStore(Op.getOperand(0), 5741 DAG.getConstant(VarArgsFPOffset, MVT::i32), 5742 FIN, SV, 0); 5743 MemOps.push_back(Store); 5744 5745 // Store ptr to overflow_arg_area 5746 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5747 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5748 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); 5749 MemOps.push_back(Store); 5750 5751 // Store ptr to reg_save_area. 5752 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); 5753 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 5754 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); 5755 MemOps.push_back(Store); 5756 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 5757} 5758 5759SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 5760 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5761 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 5762 SDValue Chain = Op.getOperand(0); 5763 SDValue SrcPtr = Op.getOperand(1); 5764 SDValue SrcSV = Op.getOperand(2); 5765 5766 assert(0 && "VAArgInst is not yet implemented for x86-64!"); 5767 abort(); 5768 return SDValue(); 5769} 5770 5771SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 5772 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5773 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 5774 SDValue Chain = Op.getOperand(0); 5775 SDValue DstPtr = Op.getOperand(1); 5776 SDValue SrcPtr = Op.getOperand(2); 5777 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 5778 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5779 5780 return DAG.getMemcpy(Chain, DstPtr, SrcPtr, 5781 DAG.getIntPtrConstant(24), 8, false, 5782 DstSV, 0, SrcSV, 0); 5783} 5784 5785SDValue 5786X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 5787 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5788 switch (IntNo) { 5789 default: return SDValue(); // Don't custom lower most intrinsics. 5790 // Comparison intrinsics. 5791 case Intrinsic::x86_sse_comieq_ss: 5792 case Intrinsic::x86_sse_comilt_ss: 5793 case Intrinsic::x86_sse_comile_ss: 5794 case Intrinsic::x86_sse_comigt_ss: 5795 case Intrinsic::x86_sse_comige_ss: 5796 case Intrinsic::x86_sse_comineq_ss: 5797 case Intrinsic::x86_sse_ucomieq_ss: 5798 case Intrinsic::x86_sse_ucomilt_ss: 5799 case Intrinsic::x86_sse_ucomile_ss: 5800 case Intrinsic::x86_sse_ucomigt_ss: 5801 case Intrinsic::x86_sse_ucomige_ss: 5802 case Intrinsic::x86_sse_ucomineq_ss: 5803 case Intrinsic::x86_sse2_comieq_sd: 5804 case Intrinsic::x86_sse2_comilt_sd: 5805 case Intrinsic::x86_sse2_comile_sd: 5806 case Intrinsic::x86_sse2_comigt_sd: 5807 case Intrinsic::x86_sse2_comige_sd: 5808 case Intrinsic::x86_sse2_comineq_sd: 5809 case Intrinsic::x86_sse2_ucomieq_sd: 5810 case Intrinsic::x86_sse2_ucomilt_sd: 5811 case Intrinsic::x86_sse2_ucomile_sd: 5812 case Intrinsic::x86_sse2_ucomigt_sd: 5813 case Intrinsic::x86_sse2_ucomige_sd: 5814 case Intrinsic::x86_sse2_ucomineq_sd: { 5815 unsigned Opc = 0; 5816 ISD::CondCode CC = ISD::SETCC_INVALID; 5817 switch (IntNo) { 5818 default: break; 5819 case Intrinsic::x86_sse_comieq_ss: 5820 case Intrinsic::x86_sse2_comieq_sd: 5821 Opc = X86ISD::COMI; 5822 CC = ISD::SETEQ; 5823 break; 5824 case Intrinsic::x86_sse_comilt_ss: 5825 case Intrinsic::x86_sse2_comilt_sd: 5826 Opc = X86ISD::COMI; 5827 CC = ISD::SETLT; 5828 break; 5829 case Intrinsic::x86_sse_comile_ss: 5830 case Intrinsic::x86_sse2_comile_sd: 5831 Opc = X86ISD::COMI; 5832 CC = ISD::SETLE; 5833 break; 5834 case Intrinsic::x86_sse_comigt_ss: 5835 case Intrinsic::x86_sse2_comigt_sd: 5836 Opc = X86ISD::COMI; 5837 CC = ISD::SETGT; 5838 break; 5839 case Intrinsic::x86_sse_comige_ss: 5840 case Intrinsic::x86_sse2_comige_sd: 5841 Opc = X86ISD::COMI; 5842 CC = ISD::SETGE; 5843 break; 5844 case Intrinsic::x86_sse_comineq_ss: 5845 case Intrinsic::x86_sse2_comineq_sd: 5846 Opc = X86ISD::COMI; 5847 CC = ISD::SETNE; 5848 break; 5849 case Intrinsic::x86_sse_ucomieq_ss: 5850 case Intrinsic::x86_sse2_ucomieq_sd: 5851 Opc = X86ISD::UCOMI; 5852 CC = ISD::SETEQ; 5853 break; 5854 case Intrinsic::x86_sse_ucomilt_ss: 5855 case Intrinsic::x86_sse2_ucomilt_sd: 5856 Opc = X86ISD::UCOMI; 5857 CC = ISD::SETLT; 5858 break; 5859 case Intrinsic::x86_sse_ucomile_ss: 5860 case Intrinsic::x86_sse2_ucomile_sd: 5861 Opc = X86ISD::UCOMI; 5862 CC = ISD::SETLE; 5863 break; 5864 case Intrinsic::x86_sse_ucomigt_ss: 5865 case Intrinsic::x86_sse2_ucomigt_sd: 5866 Opc = X86ISD::UCOMI; 5867 CC = ISD::SETGT; 5868 break; 5869 case Intrinsic::x86_sse_ucomige_ss: 5870 case Intrinsic::x86_sse2_ucomige_sd: 5871 Opc = X86ISD::UCOMI; 5872 CC = ISD::SETGE; 5873 break; 5874 case Intrinsic::x86_sse_ucomineq_ss: 5875 case Intrinsic::x86_sse2_ucomineq_sd: 5876 Opc = X86ISD::UCOMI; 5877 CC = ISD::SETNE; 5878 break; 5879 } 5880 5881 SDValue LHS = Op.getOperand(1); 5882 SDValue RHS = Op.getOperand(2); 5883 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 5884 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); 5885 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, 5886 DAG.getConstant(X86CC, MVT::i8), Cond); 5887 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC); 5888 } 5889 5890 // Fix vector shift instructions where the last operand is a non-immediate 5891 // i32 value. 5892 case Intrinsic::x86_sse2_pslli_w: 5893 case Intrinsic::x86_sse2_pslli_d: 5894 case Intrinsic::x86_sse2_pslli_q: 5895 case Intrinsic::x86_sse2_psrli_w: 5896 case Intrinsic::x86_sse2_psrli_d: 5897 case Intrinsic::x86_sse2_psrli_q: 5898 case Intrinsic::x86_sse2_psrai_w: 5899 case Intrinsic::x86_sse2_psrai_d: 5900 case Intrinsic::x86_mmx_pslli_w: 5901 case Intrinsic::x86_mmx_pslli_d: 5902 case Intrinsic::x86_mmx_pslli_q: 5903 case Intrinsic::x86_mmx_psrli_w: 5904 case Intrinsic::x86_mmx_psrli_d: 5905 case Intrinsic::x86_mmx_psrli_q: 5906 case Intrinsic::x86_mmx_psrai_w: 5907 case Intrinsic::x86_mmx_psrai_d: { 5908 SDValue ShAmt = Op.getOperand(2); 5909 if (isa<ConstantSDNode>(ShAmt)) 5910 return SDValue(); 5911 5912 unsigned NewIntNo = 0; 5913 MVT ShAmtVT = MVT::v4i32; 5914 switch (IntNo) { 5915 case Intrinsic::x86_sse2_pslli_w: 5916 NewIntNo = Intrinsic::x86_sse2_psll_w; 5917 break; 5918 case Intrinsic::x86_sse2_pslli_d: 5919 NewIntNo = Intrinsic::x86_sse2_psll_d; 5920 break; 5921 case Intrinsic::x86_sse2_pslli_q: 5922 NewIntNo = Intrinsic::x86_sse2_psll_q; 5923 break; 5924 case Intrinsic::x86_sse2_psrli_w: 5925 NewIntNo = Intrinsic::x86_sse2_psrl_w; 5926 break; 5927 case Intrinsic::x86_sse2_psrli_d: 5928 NewIntNo = Intrinsic::x86_sse2_psrl_d; 5929 break; 5930 case Intrinsic::x86_sse2_psrli_q: 5931 NewIntNo = Intrinsic::x86_sse2_psrl_q; 5932 break; 5933 case Intrinsic::x86_sse2_psrai_w: 5934 NewIntNo = Intrinsic::x86_sse2_psra_w; 5935 break; 5936 case Intrinsic::x86_sse2_psrai_d: 5937 NewIntNo = Intrinsic::x86_sse2_psra_d; 5938 break; 5939 default: { 5940 ShAmtVT = MVT::v2i32; 5941 switch (IntNo) { 5942 case Intrinsic::x86_mmx_pslli_w: 5943 NewIntNo = Intrinsic::x86_mmx_psll_w; 5944 break; 5945 case Intrinsic::x86_mmx_pslli_d: 5946 NewIntNo = Intrinsic::x86_mmx_psll_d; 5947 break; 5948 case Intrinsic::x86_mmx_pslli_q: 5949 NewIntNo = Intrinsic::x86_mmx_psll_q; 5950 break; 5951 case Intrinsic::x86_mmx_psrli_w: 5952 NewIntNo = Intrinsic::x86_mmx_psrl_w; 5953 break; 5954 case Intrinsic::x86_mmx_psrli_d: 5955 NewIntNo = Intrinsic::x86_mmx_psrl_d; 5956 break; 5957 case Intrinsic::x86_mmx_psrli_q: 5958 NewIntNo = Intrinsic::x86_mmx_psrl_q; 5959 break; 5960 case Intrinsic::x86_mmx_psrai_w: 5961 NewIntNo = Intrinsic::x86_mmx_psra_w; 5962 break; 5963 case Intrinsic::x86_mmx_psrai_d: 5964 NewIntNo = Intrinsic::x86_mmx_psra_d; 5965 break; 5966 default: abort(); // Can't reach here. 5967 } 5968 break; 5969 } 5970 } 5971 MVT VT = Op.getValueType(); 5972 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, 5973 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); 5974 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 5975 DAG.getConstant(NewIntNo, MVT::i32), 5976 Op.getOperand(1), ShAmt); 5977 } 5978 } 5979} 5980 5981SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 5982 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5983 5984 if (Depth > 0) { 5985 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5986 SDValue Offset = 5987 DAG.getConstant(TD->getPointerSize(), 5988 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 5989 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), 5990 DAG.getNode(ISD::ADD, getPointerTy(), FrameAddr, Offset), 5991 NULL, 0); 5992 } 5993 5994 // Just load the return address. 5995 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 5996 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 5997} 5998 5999SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6000 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6001 MFI->setFrameAddressIsTaken(true); 6002 MVT VT = Op.getValueType(); 6003 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6004 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6005 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT); 6006 while (Depth--) 6007 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0); 6008 return FrameAddr; 6009} 6010 6011SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6012 SelectionDAG &DAG) { 6013 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6014} 6015 6016SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6017{ 6018 MachineFunction &MF = DAG.getMachineFunction(); 6019 SDValue Chain = Op.getOperand(0); 6020 SDValue Offset = Op.getOperand(1); 6021 SDValue Handler = Op.getOperand(2); 6022 6023 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6024 getPointerTy()); 6025 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6026 6027 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, 6028 DAG.getIntPtrConstant(-TD->getPointerSize())); 6029 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); 6030 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); 6031 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr); 6032 MF.getRegInfo().addLiveOut(StoreAddrReg); 6033 6034 return DAG.getNode(X86ISD::EH_RETURN, 6035 MVT::Other, 6036 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 6037} 6038 6039SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 6040 SelectionDAG &DAG) { 6041 SDValue Root = Op.getOperand(0); 6042 SDValue Trmp = Op.getOperand(1); // trampoline 6043 SDValue FPtr = Op.getOperand(2); // nested function 6044 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 6045 6046 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6047 6048 const X86InstrInfo *TII = 6049 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 6050 6051 if (Subtarget->is64Bit()) { 6052 SDValue OutChains[6]; 6053 6054 // Large code-model. 6055 6056 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 6057 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 6058 6059 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 6060 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 6061 6062 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 6063 6064 // Load the pointer to the nested function into R11. 6065 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 6066 SDValue Addr = Trmp; 6067 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 6068 TrmpAddr, 0); 6069 6070 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); 6071 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); 6072 6073 // Load the 'nest' parameter value into R10. 6074 // R10 is specified in X86CallingConv.td 6075 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 6076 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); 6077 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 6078 TrmpAddr, 10); 6079 6080 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); 6081 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); 6082 6083 // Jump to the nested function. 6084 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 6085 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); 6086 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 6087 TrmpAddr, 20); 6088 6089 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 6090 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); 6091 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, 6092 TrmpAddr, 22); 6093 6094 SDValue Ops[] = 6095 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; 6096 return DAG.getMergeValues(Ops, 2); 6097 } else { 6098 const Function *Func = 6099 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 6100 unsigned CC = Func->getCallingConv(); 6101 unsigned NestReg; 6102 6103 switch (CC) { 6104 default: 6105 assert(0 && "Unsupported calling convention"); 6106 case CallingConv::C: 6107 case CallingConv::X86_StdCall: { 6108 // Pass 'nest' parameter in ECX. 6109 // Must be kept in sync with X86CallingConv.td 6110 NestReg = X86::ECX; 6111 6112 // Check that ECX wasn't needed by an 'inreg' parameter. 6113 const FunctionType *FTy = Func->getFunctionType(); 6114 const AttrListPtr &Attrs = Func->getAttributes(); 6115 6116 if (!Attrs.isEmpty() && !Func->isVarArg()) { 6117 unsigned InRegCount = 0; 6118 unsigned Idx = 1; 6119 6120 for (FunctionType::param_iterator I = FTy->param_begin(), 6121 E = FTy->param_end(); I != E; ++I, ++Idx) 6122 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 6123 // FIXME: should only count parameters that are lowered to integers. 6124 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 6125 6126 if (InRegCount > 2) { 6127 cerr << "Nest register in use - reduce number of inreg parameters!\n"; 6128 abort(); 6129 } 6130 } 6131 break; 6132 } 6133 case CallingConv::X86_FastCall: 6134 case CallingConv::Fast: 6135 // Pass 'nest' parameter in EAX. 6136 // Must be kept in sync with X86CallingConv.td 6137 NestReg = X86::EAX; 6138 break; 6139 } 6140 6141 SDValue OutChains[4]; 6142 SDValue Addr, Disp; 6143 6144 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); 6145 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); 6146 6147 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 6148 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 6149 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6150 Trmp, TrmpAddr, 0); 6151 6152 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); 6153 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); 6154 6155 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6156 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); 6157 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, 6158 TrmpAddr, 5, false, 1); 6159 6160 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); 6161 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); 6162 6163 SDValue Ops[] = 6164 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; 6165 return DAG.getMergeValues(Ops, 2); 6166 } 6167} 6168 6169SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6170 /* 6171 The rounding mode is in bits 11:10 of FPSR, and has the following 6172 settings: 6173 00 Round to nearest 6174 01 Round to -inf 6175 10 Round to +inf 6176 11 Round to 0 6177 6178 FLT_ROUNDS, on the other hand, expects the following: 6179 -1 Undefined 6180 0 Round to 0 6181 1 Round to nearest 6182 2 Round to +inf 6183 3 Round to -inf 6184 6185 To perform the conversion, we do: 6186 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6187 */ 6188 6189 MachineFunction &MF = DAG.getMachineFunction(); 6190 const TargetMachine &TM = MF.getTarget(); 6191 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6192 unsigned StackAlignment = TFI.getStackAlignment(); 6193 MVT VT = Op.getValueType(); 6194 6195 // Save FP Control Word to stack slot 6196 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6197 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6198 6199 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, 6200 DAG.getEntryNode(), StackSlot); 6201 6202 // Load FP Control Word from stack slot 6203 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); 6204 6205 // Transform as necessary 6206 SDValue CWD1 = 6207 DAG.getNode(ISD::SRL, MVT::i16, 6208 DAG.getNode(ISD::AND, MVT::i16, 6209 CWD, DAG.getConstant(0x800, MVT::i16)), 6210 DAG.getConstant(11, MVT::i8)); 6211 SDValue CWD2 = 6212 DAG.getNode(ISD::SRL, MVT::i16, 6213 DAG.getNode(ISD::AND, MVT::i16, 6214 CWD, DAG.getConstant(0x400, MVT::i16)), 6215 DAG.getConstant(9, MVT::i8)); 6216 6217 SDValue RetVal = 6218 DAG.getNode(ISD::AND, MVT::i16, 6219 DAG.getNode(ISD::ADD, MVT::i16, 6220 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), 6221 DAG.getConstant(1, MVT::i16)), 6222 DAG.getConstant(3, MVT::i16)); 6223 6224 6225 return DAG.getNode((VT.getSizeInBits() < 16 ? 6226 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 6227} 6228 6229SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6230 MVT VT = Op.getValueType(); 6231 MVT OpVT = VT; 6232 unsigned NumBits = VT.getSizeInBits(); 6233 6234 Op = Op.getOperand(0); 6235 if (VT == MVT::i8) { 6236 // Zero extend to i32 since there is not an i8 bsr. 6237 OpVT = MVT::i32; 6238 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 6239 } 6240 6241 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6242 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6243 Op = DAG.getNode(X86ISD::BSR, VTs, Op); 6244 6245 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6246 SmallVector<SDValue, 4> Ops; 6247 Ops.push_back(Op); 6248 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6249 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6250 Ops.push_back(Op.getValue(1)); 6251 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 6252 6253 // Finally xor with NumBits-1. 6254 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6255 6256 if (VT == MVT::i8) 6257 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 6258 return Op; 6259} 6260 6261SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6262 MVT VT = Op.getValueType(); 6263 MVT OpVT = VT; 6264 unsigned NumBits = VT.getSizeInBits(); 6265 6266 Op = Op.getOperand(0); 6267 if (VT == MVT::i8) { 6268 OpVT = MVT::i32; 6269 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 6270 } 6271 6272 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6273 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6274 Op = DAG.getNode(X86ISD::BSF, VTs, Op); 6275 6276 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6277 SmallVector<SDValue, 4> Ops; 6278 Ops.push_back(Op); 6279 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6280 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6281 Ops.push_back(Op.getValue(1)); 6282 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 6283 6284 if (VT == MVT::i8) 6285 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 6286 return Op; 6287} 6288 6289SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6290 MVT VT = Op.getValueType(); 6291 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6292 6293 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6294 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6295 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6296 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6297 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6298 // 6299 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6300 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6301 // return AloBlo + AloBhi + AhiBlo; 6302 6303 SDValue A = Op.getOperand(0); 6304 SDValue B = Op.getOperand(1); 6305 6306 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6307 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6308 A, DAG.getConstant(32, MVT::i32)); 6309 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6310 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6311 B, DAG.getConstant(32, MVT::i32)); 6312 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6313 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6314 A, B); 6315 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6316 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6317 A, Bhi); 6318 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6319 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6320 Ahi, B); 6321 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6322 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6323 AloBhi, DAG.getConstant(32, MVT::i32)); 6324 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6325 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6326 AhiBlo, DAG.getConstant(32, MVT::i32)); 6327 SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi); 6328 Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo); 6329 return Res; 6330} 6331 6332 6333SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6334 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6335 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6336 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6337 // has only one use. 6338 SDNode *N = Op.getNode(); 6339 SDValue LHS = N->getOperand(0); 6340 SDValue RHS = N->getOperand(1); 6341 unsigned BaseOp = 0; 6342 unsigned Cond = 0; 6343 6344 switch (Op.getOpcode()) { 6345 default: assert(0 && "Unknown ovf instruction!"); 6346 case ISD::SADDO: 6347 BaseOp = X86ISD::ADD; 6348 Cond = X86::COND_O; 6349 break; 6350 case ISD::UADDO: 6351 BaseOp = X86ISD::ADD; 6352 Cond = X86::COND_B; 6353 break; 6354 case ISD::SSUBO: 6355 BaseOp = X86ISD::SUB; 6356 Cond = X86::COND_O; 6357 break; 6358 case ISD::USUBO: 6359 BaseOp = X86ISD::SUB; 6360 Cond = X86::COND_B; 6361 break; 6362 case ISD::SMULO: 6363 BaseOp = X86ISD::SMUL; 6364 Cond = X86::COND_O; 6365 break; 6366 case ISD::UMULO: 6367 BaseOp = X86ISD::UMUL; 6368 Cond = X86::COND_B; 6369 break; 6370 } 6371 6372 // Also sets EFLAGS. 6373 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6374 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS); 6375 6376 SDValue SetCC = 6377 DAG.getNode(X86ISD::SETCC, N->getValueType(1), 6378 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6379 6380 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6381 return Sum; 6382} 6383 6384SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6385 MVT T = Op.getValueType(); 6386 unsigned Reg = 0; 6387 unsigned size = 0; 6388 switch(T.getSimpleVT()) { 6389 default: 6390 assert(false && "Invalid value type!"); 6391 case MVT::i8: Reg = X86::AL; size = 1; break; 6392 case MVT::i16: Reg = X86::AX; size = 2; break; 6393 case MVT::i32: Reg = X86::EAX; size = 4; break; 6394 case MVT::i64: 6395 assert(Subtarget->is64Bit() && "Node not type legal!"); 6396 Reg = X86::RAX; size = 8; 6397 break; 6398 } 6399 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, 6400 Op.getOperand(2), SDValue()); 6401 SDValue Ops[] = { cpIn.getValue(0), 6402 Op.getOperand(1), 6403 Op.getOperand(3), 6404 DAG.getTargetConstant(size, MVT::i8), 6405 cpIn.getValue(1) }; 6406 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6407 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); 6408 SDValue cpOut = 6409 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); 6410 return cpOut; 6411} 6412 6413SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6414 SelectionDAG &DAG) { 6415 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6416 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6417 SDValue TheChain = Op.getOperand(0); 6418 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 6419 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 6420 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64, 6421 rax.getValue(2)); 6422 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, 6423 DAG.getConstant(32, MVT::i8)); 6424 SDValue Ops[] = { 6425 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), 6426 rdx.getValue(1) 6427 }; 6428 return DAG.getMergeValues(Ops, 2); 6429} 6430 6431SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6432 SDNode *Node = Op.getNode(); 6433 MVT T = Node->getValueType(0); 6434 SDValue negOp = DAG.getNode(ISD::SUB, T, 6435 DAG.getConstant(0, T), Node->getOperand(2)); 6436 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, 6437 cast<AtomicSDNode>(Node)->getMemoryVT(), 6438 Node->getOperand(0), 6439 Node->getOperand(1), negOp, 6440 cast<AtomicSDNode>(Node)->getSrcValue(), 6441 cast<AtomicSDNode>(Node)->getAlignment()); 6442} 6443 6444/// LowerOperation - Provide custom lowering hooks for some operations. 6445/// 6446SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6447 switch (Op.getOpcode()) { 6448 default: assert(0 && "Should not custom lower this!"); 6449 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6450 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6451 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6452 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6453 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6454 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6455 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6456 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6457 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6458 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6459 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6460 case ISD::SHL_PARTS: 6461 case ISD::SRA_PARTS: 6462 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6463 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6464 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6465 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6466 case ISD::FABS: return LowerFABS(Op, DAG); 6467 case ISD::FNEG: return LowerFNEG(Op, DAG); 6468 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6469 case ISD::SETCC: return LowerSETCC(Op, DAG); 6470 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6471 case ISD::SELECT: return LowerSELECT(Op, DAG); 6472 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6473 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6474 case ISD::CALL: return LowerCALL(Op, DAG); 6475 case ISD::RET: return LowerRET(Op, DAG); 6476 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 6477 case ISD::VASTART: return LowerVASTART(Op, DAG); 6478 case ISD::VAARG: return LowerVAARG(Op, DAG); 6479 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6480 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6481 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6482 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6483 case ISD::FRAME_TO_ARGS_OFFSET: 6484 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6485 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6486 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6487 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6488 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6489 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6490 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6491 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6492 case ISD::SADDO: 6493 case ISD::UADDO: 6494 case ISD::SSUBO: 6495 case ISD::USUBO: 6496 case ISD::SMULO: 6497 case ISD::UMULO: return LowerXALUO(Op, DAG); 6498 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6499 } 6500} 6501 6502void X86TargetLowering:: 6503ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6504 SelectionDAG &DAG, unsigned NewOp) { 6505 MVT T = Node->getValueType(0); 6506 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6507 6508 SDValue Chain = Node->getOperand(0); 6509 SDValue In1 = Node->getOperand(1); 6510 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 6511 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6512 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 6513 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6514 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6515 // have a MemOperand. Pass the info through as a normal operand. 6516 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6517 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6518 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6519 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5); 6520 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6521 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); 6522 Results.push_back(Result.getValue(2)); 6523} 6524 6525/// ReplaceNodeResults - Replace a node with an illegal result type 6526/// with a new node built out of custom code. 6527void X86TargetLowering::ReplaceNodeResults(SDNode *N, 6528 SmallVectorImpl<SDValue>&Results, 6529 SelectionDAG &DAG) { 6530 switch (N->getOpcode()) { 6531 default: 6532 assert(false && "Do not know how to custom type legalize this operation!"); 6533 return; 6534 case ISD::FP_TO_SINT: { 6535 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG); 6536 SDValue FIST = Vals.first, StackSlot = Vals.second; 6537 if (FIST.getNode() != 0) { 6538 MVT VT = N->getValueType(0); 6539 // Return a load from the stack slot. 6540 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0)); 6541 } 6542 return; 6543 } 6544 case ISD::READCYCLECOUNTER: { 6545 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6546 SDValue TheChain = N->getOperand(0); 6547 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 6548 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 6549 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32, 6550 eax.getValue(2)); 6551 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 6552 SDValue Ops[] = { eax, edx }; 6553 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2)); 6554 Results.push_back(edx.getValue(1)); 6555 return; 6556 } 6557 case ISD::ATOMIC_CMP_SWAP: { 6558 MVT T = N->getValueType(0); 6559 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 6560 SDValue cpInL, cpInH; 6561 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), 6562 DAG.getConstant(0, MVT::i32)); 6563 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), 6564 DAG.getConstant(1, MVT::i32)); 6565 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue()); 6566 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH, 6567 cpInL.getValue(1)); 6568 SDValue swapInL, swapInH; 6569 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), 6570 DAG.getConstant(0, MVT::i32)); 6571 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), 6572 DAG.getConstant(1, MVT::i32)); 6573 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL, 6574 cpInH.getValue(1)); 6575 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH, 6576 swapInL.getValue(1)); 6577 SDValue Ops[] = { swapInH.getValue(0), 6578 N->getOperand(1), 6579 swapInH.getValue(1) }; 6580 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6581 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); 6582 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, 6583 Result.getValue(1)); 6584 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, 6585 cpOutL.getValue(2)); 6586 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 6587 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); 6588 Results.push_back(cpOutH.getValue(1)); 6589 return; 6590 } 6591 case ISD::ATOMIC_LOAD_ADD: 6592 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 6593 return; 6594 case ISD::ATOMIC_LOAD_AND: 6595 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 6596 return; 6597 case ISD::ATOMIC_LOAD_NAND: 6598 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 6599 return; 6600 case ISD::ATOMIC_LOAD_OR: 6601 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 6602 return; 6603 case ISD::ATOMIC_LOAD_SUB: 6604 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 6605 return; 6606 case ISD::ATOMIC_LOAD_XOR: 6607 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 6608 return; 6609 case ISD::ATOMIC_SWAP: 6610 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 6611 return; 6612 } 6613} 6614 6615const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 6616 switch (Opcode) { 6617 default: return NULL; 6618 case X86ISD::BSF: return "X86ISD::BSF"; 6619 case X86ISD::BSR: return "X86ISD::BSR"; 6620 case X86ISD::SHLD: return "X86ISD::SHLD"; 6621 case X86ISD::SHRD: return "X86ISD::SHRD"; 6622 case X86ISD::FAND: return "X86ISD::FAND"; 6623 case X86ISD::FOR: return "X86ISD::FOR"; 6624 case X86ISD::FXOR: return "X86ISD::FXOR"; 6625 case X86ISD::FSRL: return "X86ISD::FSRL"; 6626 case X86ISD::FILD: return "X86ISD::FILD"; 6627 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 6628 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 6629 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 6630 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 6631 case X86ISD::FLD: return "X86ISD::FLD"; 6632 case X86ISD::FST: return "X86ISD::FST"; 6633 case X86ISD::CALL: return "X86ISD::CALL"; 6634 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 6635 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 6636 case X86ISD::BT: return "X86ISD::BT"; 6637 case X86ISD::CMP: return "X86ISD::CMP"; 6638 case X86ISD::COMI: return "X86ISD::COMI"; 6639 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 6640 case X86ISD::SETCC: return "X86ISD::SETCC"; 6641 case X86ISD::CMOV: return "X86ISD::CMOV"; 6642 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 6643 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 6644 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 6645 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 6646 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 6647 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 6648 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 6649 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 6650 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 6651 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 6652 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 6653 case X86ISD::FMAX: return "X86ISD::FMAX"; 6654 case X86ISD::FMIN: return "X86ISD::FMIN"; 6655 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 6656 case X86ISD::FRCP: return "X86ISD::FRCP"; 6657 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 6658 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; 6659 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 6660 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 6661 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 6662 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 6663 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 6664 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 6665 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 6666 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 6667 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 6668 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 6669 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 6670 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 6671 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 6672 case X86ISD::VSHL: return "X86ISD::VSHL"; 6673 case X86ISD::VSRL: return "X86ISD::VSRL"; 6674 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 6675 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 6676 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 6677 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 6678 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 6679 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 6680 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 6681 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 6682 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 6683 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 6684 case X86ISD::ADD: return "X86ISD::ADD"; 6685 case X86ISD::SUB: return "X86ISD::SUB"; 6686 case X86ISD::SMUL: return "X86ISD::SMUL"; 6687 case X86ISD::UMUL: return "X86ISD::UMUL"; 6688 } 6689} 6690 6691// isLegalAddressingMode - Return true if the addressing mode represented 6692// by AM is legal for this target, for a load/store of the specified type. 6693bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 6694 const Type *Ty) const { 6695 // X86 supports extremely general addressing modes. 6696 6697 // X86 allows a sign-extended 32-bit immediate field as a displacement. 6698 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 6699 return false; 6700 6701 if (AM.BaseGV) { 6702 // We can only fold this if we don't need an extra load. 6703 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 6704 return false; 6705 // If BaseGV requires a register, we cannot also have a BaseReg. 6706 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) && 6707 AM.HasBaseReg) 6708 return false; 6709 6710 // X86-64 only supports addr of globals in small code model. 6711 if (Subtarget->is64Bit()) { 6712 if (getTargetMachine().getCodeModel() != CodeModel::Small) 6713 return false; 6714 // If lower 4G is not available, then we must use rip-relative addressing. 6715 if (AM.BaseOffs || AM.Scale > 1) 6716 return false; 6717 } 6718 } 6719 6720 switch (AM.Scale) { 6721 case 0: 6722 case 1: 6723 case 2: 6724 case 4: 6725 case 8: 6726 // These scales always work. 6727 break; 6728 case 3: 6729 case 5: 6730 case 9: 6731 // These scales are formed with basereg+scalereg. Only accept if there is 6732 // no basereg yet. 6733 if (AM.HasBaseReg) 6734 return false; 6735 break; 6736 default: // Other stuff never works. 6737 return false; 6738 } 6739 6740 return true; 6741} 6742 6743 6744bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 6745 if (!Ty1->isInteger() || !Ty2->isInteger()) 6746 return false; 6747 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6748 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6749 if (NumBits1 <= NumBits2) 6750 return false; 6751 return Subtarget->is64Bit() || NumBits1 < 64; 6752} 6753 6754bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { 6755 if (!VT1.isInteger() || !VT2.isInteger()) 6756 return false; 6757 unsigned NumBits1 = VT1.getSizeInBits(); 6758 unsigned NumBits2 = VT2.getSizeInBits(); 6759 if (NumBits1 <= NumBits2) 6760 return false; 6761 return Subtarget->is64Bit() || NumBits1 < 64; 6762} 6763 6764/// isShuffleMaskLegal - Targets can use this to indicate that they only 6765/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 6766/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 6767/// are assumed to be legal. 6768bool 6769X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const { 6770 // Only do shuffles on 128-bit vector types for now. 6771 if (VT.getSizeInBits() == 64) return false; 6772 return (Mask.getNode()->getNumOperands() <= 4 || 6773 isIdentityMask(Mask.getNode()) || 6774 isIdentityMask(Mask.getNode(), true) || 6775 isSplatMask(Mask.getNode()) || 6776 isPSHUFHW_PSHUFLWMask(Mask.getNode()) || 6777 X86::isUNPCKLMask(Mask.getNode()) || 6778 X86::isUNPCKHMask(Mask.getNode()) || 6779 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) || 6780 X86::isUNPCKH_v_undef_Mask(Mask.getNode())); 6781} 6782 6783bool 6784X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 6785 MVT EVT, SelectionDAG &DAG) const { 6786 unsigned NumElts = BVOps.size(); 6787 // Only do shuffles on 128-bit vector types for now. 6788 if (EVT.getSizeInBits() * NumElts == 64) return false; 6789 if (NumElts == 2) return true; 6790 if (NumElts == 4) { 6791 return (isMOVLMask(&BVOps[0], 4) || 6792 isCommutedMOVL(&BVOps[0], 4, true) || 6793 isSHUFPMask(&BVOps[0], 4) || 6794 isCommutedSHUFP(&BVOps[0], 4)); 6795 } 6796 return false; 6797} 6798 6799//===----------------------------------------------------------------------===// 6800// X86 Scheduler Hooks 6801//===----------------------------------------------------------------------===// 6802 6803// private utility function 6804MachineBasicBlock * 6805X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 6806 MachineBasicBlock *MBB, 6807 unsigned regOpc, 6808 unsigned immOpc, 6809 unsigned LoadOpc, 6810 unsigned CXchgOpc, 6811 unsigned copyOpc, 6812 unsigned notOpc, 6813 unsigned EAXreg, 6814 TargetRegisterClass *RC, 6815 bool invSrc) { 6816 // For the atomic bitwise operator, we generate 6817 // thisMBB: 6818 // newMBB: 6819 // ld t1 = [bitinstr.addr] 6820 // op t2 = t1, [bitinstr.val] 6821 // mov EAX = t1 6822 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 6823 // bz newMBB 6824 // fallthrough -->nextMBB 6825 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6826 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6827 MachineFunction::iterator MBBIter = MBB; 6828 ++MBBIter; 6829 6830 /// First build the CFG 6831 MachineFunction *F = MBB->getParent(); 6832 MachineBasicBlock *thisMBB = MBB; 6833 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6834 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6835 F->insert(MBBIter, newMBB); 6836 F->insert(MBBIter, nextMBB); 6837 6838 // Move all successors to thisMBB to nextMBB 6839 nextMBB->transferSuccessors(thisMBB); 6840 6841 // Update thisMBB to fall through to newMBB 6842 thisMBB->addSuccessor(newMBB); 6843 6844 // newMBB jumps to itself and fall through to nextMBB 6845 newMBB->addSuccessor(nextMBB); 6846 newMBB->addSuccessor(newMBB); 6847 6848 // Insert instructions into newMBB based on incoming instruction 6849 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); 6850 MachineOperand& destOper = bInstr->getOperand(0); 6851 MachineOperand* argOpers[6]; 6852 int numArgs = bInstr->getNumOperands() - 1; 6853 for (int i=0; i < numArgs; ++i) 6854 argOpers[i] = &bInstr->getOperand(i+1); 6855 6856 // x86 address has 4 operands: base, index, scale, and displacement 6857 int lastAddrIndx = 3; // [0,3] 6858 int valArgIndx = 4; 6859 6860 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 6861 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1); 6862 for (int i=0; i <= lastAddrIndx; ++i) 6863 (*MIB).addOperand(*argOpers[i]); 6864 6865 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 6866 if (invSrc) { 6867 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1); 6868 } 6869 else 6870 tt = t1; 6871 6872 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 6873 assert((argOpers[valArgIndx]->isReg() || 6874 argOpers[valArgIndx]->isImm()) && 6875 "invalid operand"); 6876 if (argOpers[valArgIndx]->isReg()) 6877 MIB = BuildMI(newMBB, TII->get(regOpc), t2); 6878 else 6879 MIB = BuildMI(newMBB, TII->get(immOpc), t2); 6880 MIB.addReg(tt); 6881 (*MIB).addOperand(*argOpers[valArgIndx]); 6882 6883 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg); 6884 MIB.addReg(t1); 6885 6886 MIB = BuildMI(newMBB, TII->get(CXchgOpc)); 6887 for (int i=0; i <= lastAddrIndx; ++i) 6888 (*MIB).addOperand(*argOpers[i]); 6889 MIB.addReg(t2); 6890 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6891 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 6892 6893 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg()); 6894 MIB.addReg(EAXreg); 6895 6896 // insert branch 6897 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6898 6899 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 6900 return nextMBB; 6901} 6902 6903// private utility function: 64 bit atomics on 32 bit host. 6904MachineBasicBlock * 6905X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 6906 MachineBasicBlock *MBB, 6907 unsigned regOpcL, 6908 unsigned regOpcH, 6909 unsigned immOpcL, 6910 unsigned immOpcH, 6911 bool invSrc) { 6912 // For the atomic bitwise operator, we generate 6913 // thisMBB (instructions are in pairs, except cmpxchg8b) 6914 // ld t1,t2 = [bitinstr.addr] 6915 // newMBB: 6916 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 6917 // op t5, t6 <- out1, out2, [bitinstr.val] 6918 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 6919 // mov ECX, EBX <- t5, t6 6920 // mov EAX, EDX <- t1, t2 6921 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 6922 // mov t3, t4 <- EAX, EDX 6923 // bz newMBB 6924 // result in out1, out2 6925 // fallthrough -->nextMBB 6926 6927 const TargetRegisterClass *RC = X86::GR32RegisterClass; 6928 const unsigned LoadOpc = X86::MOV32rm; 6929 const unsigned copyOpc = X86::MOV32rr; 6930 const unsigned NotOpc = X86::NOT32r; 6931 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6932 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6933 MachineFunction::iterator MBBIter = MBB; 6934 ++MBBIter; 6935 6936 /// First build the CFG 6937 MachineFunction *F = MBB->getParent(); 6938 MachineBasicBlock *thisMBB = MBB; 6939 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6940 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6941 F->insert(MBBIter, newMBB); 6942 F->insert(MBBIter, nextMBB); 6943 6944 // Move all successors to thisMBB to nextMBB 6945 nextMBB->transferSuccessors(thisMBB); 6946 6947 // Update thisMBB to fall through to newMBB 6948 thisMBB->addSuccessor(newMBB); 6949 6950 // newMBB jumps to itself and fall through to nextMBB 6951 newMBB->addSuccessor(nextMBB); 6952 newMBB->addSuccessor(newMBB); 6953 6954 // Insert instructions into newMBB based on incoming instruction 6955 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 6956 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands"); 6957 MachineOperand& dest1Oper = bInstr->getOperand(0); 6958 MachineOperand& dest2Oper = bInstr->getOperand(1); 6959 MachineOperand* argOpers[6]; 6960 for (int i=0; i < 6; ++i) 6961 argOpers[i] = &bInstr->getOperand(i+2); 6962 6963 // x86 address has 4 operands: base, index, scale, and displacement 6964 int lastAddrIndx = 3; // [0,3] 6965 6966 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 6967 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1); 6968 for (int i=0; i <= lastAddrIndx; ++i) 6969 (*MIB).addOperand(*argOpers[i]); 6970 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 6971 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2); 6972 // add 4 to displacement. 6973 for (int i=0; i <= lastAddrIndx-1; ++i) 6974 (*MIB).addOperand(*argOpers[i]); 6975 MachineOperand newOp3 = *(argOpers[3]); 6976 if (newOp3.isImm()) 6977 newOp3.setImm(newOp3.getImm()+4); 6978 else 6979 newOp3.setOffset(newOp3.getOffset()+4); 6980 (*MIB).addOperand(newOp3); 6981 6982 // t3/4 are defined later, at the bottom of the loop 6983 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 6984 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 6985 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg()) 6986 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 6987 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg()) 6988 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 6989 6990 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 6991 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 6992 if (invSrc) { 6993 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1); 6994 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2); 6995 } else { 6996 tt1 = t1; 6997 tt2 = t2; 6998 } 6999 7000 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) && 7001 "invalid operand"); 7002 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 7003 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 7004 if (argOpers[4]->isReg()) 7005 MIB = BuildMI(newMBB, TII->get(regOpcL), t5); 7006 else 7007 MIB = BuildMI(newMBB, TII->get(immOpcL), t5); 7008 if (regOpcL != X86::MOV32rr) 7009 MIB.addReg(tt1); 7010 (*MIB).addOperand(*argOpers[4]); 7011 assert(argOpers[5]->isReg() == argOpers[4]->isReg()); 7012 assert(argOpers[5]->isImm() == argOpers[4]->isImm()); 7013 if (argOpers[5]->isReg()) 7014 MIB = BuildMI(newMBB, TII->get(regOpcH), t6); 7015 else 7016 MIB = BuildMI(newMBB, TII->get(immOpcH), t6); 7017 if (regOpcH != X86::MOV32rr) 7018 MIB.addReg(tt2); 7019 (*MIB).addOperand(*argOpers[5]); 7020 7021 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX); 7022 MIB.addReg(t1); 7023 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX); 7024 MIB.addReg(t2); 7025 7026 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX); 7027 MIB.addReg(t5); 7028 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX); 7029 MIB.addReg(t6); 7030 7031 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B)); 7032 for (int i=0; i <= lastAddrIndx; ++i) 7033 (*MIB).addOperand(*argOpers[i]); 7034 7035 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7036 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7037 7038 MIB = BuildMI(newMBB, TII->get(copyOpc), t3); 7039 MIB.addReg(X86::EAX); 7040 MIB = BuildMI(newMBB, TII->get(copyOpc), t4); 7041 MIB.addReg(X86::EDX); 7042 7043 // insert branch 7044 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 7045 7046 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7047 return nextMBB; 7048} 7049 7050// private utility function 7051MachineBasicBlock * 7052X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 7053 MachineBasicBlock *MBB, 7054 unsigned cmovOpc) { 7055 // For the atomic min/max operator, we generate 7056 // thisMBB: 7057 // newMBB: 7058 // ld t1 = [min/max.addr] 7059 // mov t2 = [min/max.val] 7060 // cmp t1, t2 7061 // cmov[cond] t2 = t1 7062 // mov EAX = t1 7063 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7064 // bz newMBB 7065 // fallthrough -->nextMBB 7066 // 7067 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7068 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7069 MachineFunction::iterator MBBIter = MBB; 7070 ++MBBIter; 7071 7072 /// First build the CFG 7073 MachineFunction *F = MBB->getParent(); 7074 MachineBasicBlock *thisMBB = MBB; 7075 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7076 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7077 F->insert(MBBIter, newMBB); 7078 F->insert(MBBIter, nextMBB); 7079 7080 // Move all successors to thisMBB to nextMBB 7081 nextMBB->transferSuccessors(thisMBB); 7082 7083 // Update thisMBB to fall through to newMBB 7084 thisMBB->addSuccessor(newMBB); 7085 7086 // newMBB jumps to newMBB and fall through to nextMBB 7087 newMBB->addSuccessor(nextMBB); 7088 newMBB->addSuccessor(newMBB); 7089 7090 // Insert instructions into newMBB based on incoming instruction 7091 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); 7092 MachineOperand& destOper = mInstr->getOperand(0); 7093 MachineOperand* argOpers[6]; 7094 int numArgs = mInstr->getNumOperands() - 1; 7095 for (int i=0; i < numArgs; ++i) 7096 argOpers[i] = &mInstr->getOperand(i+1); 7097 7098 // x86 address has 4 operands: base, index, scale, and displacement 7099 int lastAddrIndx = 3; // [0,3] 7100 int valArgIndx = 4; 7101 7102 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7103 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1); 7104 for (int i=0; i <= lastAddrIndx; ++i) 7105 (*MIB).addOperand(*argOpers[i]); 7106 7107 // We only support register and immediate values 7108 assert((argOpers[valArgIndx]->isReg() || 7109 argOpers[valArgIndx]->isImm()) && 7110 "invalid operand"); 7111 7112 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7113 if (argOpers[valArgIndx]->isReg()) 7114 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 7115 else 7116 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 7117 (*MIB).addOperand(*argOpers[valArgIndx]); 7118 7119 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX); 7120 MIB.addReg(t1); 7121 7122 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr)); 7123 MIB.addReg(t1); 7124 MIB.addReg(t2); 7125 7126 // Generate movc 7127 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7128 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3); 7129 MIB.addReg(t2); 7130 MIB.addReg(t1); 7131 7132 // Cmp and exchange if none has modified the memory location 7133 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); 7134 for (int i=0; i <= lastAddrIndx; ++i) 7135 (*MIB).addOperand(*argOpers[i]); 7136 MIB.addReg(t3); 7137 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7138 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 7139 7140 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); 7141 MIB.addReg(X86::EAX); 7142 7143 // insert branch 7144 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 7145 7146 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 7147 return nextMBB; 7148} 7149 7150 7151MachineBasicBlock * 7152X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7153 MachineBasicBlock *BB) { 7154 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7155 switch (MI->getOpcode()) { 7156 default: assert(false && "Unexpected instr type to insert"); 7157 case X86::CMOV_V1I64: 7158 case X86::CMOV_FR32: 7159 case X86::CMOV_FR64: 7160 case X86::CMOV_V4F32: 7161 case X86::CMOV_V2F64: 7162 case X86::CMOV_V2I64: { 7163 // To "insert" a SELECT_CC instruction, we actually have to insert the 7164 // diamond control-flow pattern. The incoming instruction knows the 7165 // destination vreg to set, the condition code register to branch on, the 7166 // true/false values to select between, and a branch opcode to use. 7167 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7168 MachineFunction::iterator It = BB; 7169 ++It; 7170 7171 // thisMBB: 7172 // ... 7173 // TrueVal = ... 7174 // cmpTY ccX, r1, r2 7175 // bCC copy1MBB 7176 // fallthrough --> copy0MBB 7177 MachineBasicBlock *thisMBB = BB; 7178 MachineFunction *F = BB->getParent(); 7179 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7180 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7181 unsigned Opc = 7182 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7183 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 7184 F->insert(It, copy0MBB); 7185 F->insert(It, sinkMBB); 7186 // Update machine-CFG edges by transferring all successors of the current 7187 // block to the new block which will contain the Phi node for the select. 7188 sinkMBB->transferSuccessors(BB); 7189 7190 // Add the true and fallthrough blocks as its successors. 7191 BB->addSuccessor(copy0MBB); 7192 BB->addSuccessor(sinkMBB); 7193 7194 // copy0MBB: 7195 // %FalseValue = ... 7196 // # fallthrough to sinkMBB 7197 BB = copy0MBB; 7198 7199 // Update machine-CFG edges 7200 BB->addSuccessor(sinkMBB); 7201 7202 // sinkMBB: 7203 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7204 // ... 7205 BB = sinkMBB; 7206 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7207 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7208 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7209 7210 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7211 return BB; 7212 } 7213 7214 case X86::FP32_TO_INT16_IN_MEM: 7215 case X86::FP32_TO_INT32_IN_MEM: 7216 case X86::FP32_TO_INT64_IN_MEM: 7217 case X86::FP64_TO_INT16_IN_MEM: 7218 case X86::FP64_TO_INT32_IN_MEM: 7219 case X86::FP64_TO_INT64_IN_MEM: 7220 case X86::FP80_TO_INT16_IN_MEM: 7221 case X86::FP80_TO_INT32_IN_MEM: 7222 case X86::FP80_TO_INT64_IN_MEM: { 7223 // Change the floating point control register to use "round towards zero" 7224 // mode when truncating to an integer value. 7225 MachineFunction *F = BB->getParent(); 7226 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7227 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7228 7229 // Load the old value of the high byte of the control word... 7230 unsigned OldCW = 7231 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7232 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 7233 7234 // Set the high part to be round to zero... 7235 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 7236 .addImm(0xC7F); 7237 7238 // Reload the modified control word now... 7239 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 7240 7241 // Restore the memory image of control word to original value 7242 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 7243 .addReg(OldCW); 7244 7245 // Get the X86 opcode to use. 7246 unsigned Opc; 7247 switch (MI->getOpcode()) { 7248 default: assert(0 && "illegal opcode!"); 7249 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7250 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7251 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7252 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7253 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7254 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7255 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7256 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7257 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7258 } 7259 7260 X86AddressMode AM; 7261 MachineOperand &Op = MI->getOperand(0); 7262 if (Op.isReg()) { 7263 AM.BaseType = X86AddressMode::RegBase; 7264 AM.Base.Reg = Op.getReg(); 7265 } else { 7266 AM.BaseType = X86AddressMode::FrameIndexBase; 7267 AM.Base.FrameIndex = Op.getIndex(); 7268 } 7269 Op = MI->getOperand(1); 7270 if (Op.isImm()) 7271 AM.Scale = Op.getImm(); 7272 Op = MI->getOperand(2); 7273 if (Op.isImm()) 7274 AM.IndexReg = Op.getImm(); 7275 Op = MI->getOperand(3); 7276 if (Op.isGlobal()) { 7277 AM.GV = Op.getGlobal(); 7278 } else { 7279 AM.Disp = Op.getImm(); 7280 } 7281 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 7282 .addReg(MI->getOperand(4).getReg()); 7283 7284 // Reload the original control word now. 7285 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 7286 7287 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7288 return BB; 7289 } 7290 case X86::ATOMAND32: 7291 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7292 X86::AND32ri, X86::MOV32rm, 7293 X86::LCMPXCHG32, X86::MOV32rr, 7294 X86::NOT32r, X86::EAX, 7295 X86::GR32RegisterClass); 7296 case X86::ATOMOR32: 7297 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7298 X86::OR32ri, X86::MOV32rm, 7299 X86::LCMPXCHG32, X86::MOV32rr, 7300 X86::NOT32r, X86::EAX, 7301 X86::GR32RegisterClass); 7302 case X86::ATOMXOR32: 7303 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7304 X86::XOR32ri, X86::MOV32rm, 7305 X86::LCMPXCHG32, X86::MOV32rr, 7306 X86::NOT32r, X86::EAX, 7307 X86::GR32RegisterClass); 7308 case X86::ATOMNAND32: 7309 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7310 X86::AND32ri, X86::MOV32rm, 7311 X86::LCMPXCHG32, X86::MOV32rr, 7312 X86::NOT32r, X86::EAX, 7313 X86::GR32RegisterClass, true); 7314 case X86::ATOMMIN32: 7315 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7316 case X86::ATOMMAX32: 7317 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7318 case X86::ATOMUMIN32: 7319 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7320 case X86::ATOMUMAX32: 7321 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7322 7323 case X86::ATOMAND16: 7324 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7325 X86::AND16ri, X86::MOV16rm, 7326 X86::LCMPXCHG16, X86::MOV16rr, 7327 X86::NOT16r, X86::AX, 7328 X86::GR16RegisterClass); 7329 case X86::ATOMOR16: 7330 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7331 X86::OR16ri, X86::MOV16rm, 7332 X86::LCMPXCHG16, X86::MOV16rr, 7333 X86::NOT16r, X86::AX, 7334 X86::GR16RegisterClass); 7335 case X86::ATOMXOR16: 7336 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7337 X86::XOR16ri, X86::MOV16rm, 7338 X86::LCMPXCHG16, X86::MOV16rr, 7339 X86::NOT16r, X86::AX, 7340 X86::GR16RegisterClass); 7341 case X86::ATOMNAND16: 7342 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7343 X86::AND16ri, X86::MOV16rm, 7344 X86::LCMPXCHG16, X86::MOV16rr, 7345 X86::NOT16r, X86::AX, 7346 X86::GR16RegisterClass, true); 7347 case X86::ATOMMIN16: 7348 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 7349 case X86::ATOMMAX16: 7350 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 7351 case X86::ATOMUMIN16: 7352 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 7353 case X86::ATOMUMAX16: 7354 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 7355 7356 case X86::ATOMAND8: 7357 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7358 X86::AND8ri, X86::MOV8rm, 7359 X86::LCMPXCHG8, X86::MOV8rr, 7360 X86::NOT8r, X86::AL, 7361 X86::GR8RegisterClass); 7362 case X86::ATOMOR8: 7363 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 7364 X86::OR8ri, X86::MOV8rm, 7365 X86::LCMPXCHG8, X86::MOV8rr, 7366 X86::NOT8r, X86::AL, 7367 X86::GR8RegisterClass); 7368 case X86::ATOMXOR8: 7369 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 7370 X86::XOR8ri, X86::MOV8rm, 7371 X86::LCMPXCHG8, X86::MOV8rr, 7372 X86::NOT8r, X86::AL, 7373 X86::GR8RegisterClass); 7374 case X86::ATOMNAND8: 7375 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7376 X86::AND8ri, X86::MOV8rm, 7377 X86::LCMPXCHG8, X86::MOV8rr, 7378 X86::NOT8r, X86::AL, 7379 X86::GR8RegisterClass, true); 7380 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 7381 // This group is for 64-bit host. 7382 case X86::ATOMAND64: 7383 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7384 X86::AND64ri32, X86::MOV64rm, 7385 X86::LCMPXCHG64, X86::MOV64rr, 7386 X86::NOT64r, X86::RAX, 7387 X86::GR64RegisterClass); 7388 case X86::ATOMOR64: 7389 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 7390 X86::OR64ri32, X86::MOV64rm, 7391 X86::LCMPXCHG64, X86::MOV64rr, 7392 X86::NOT64r, X86::RAX, 7393 X86::GR64RegisterClass); 7394 case X86::ATOMXOR64: 7395 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 7396 X86::XOR64ri32, X86::MOV64rm, 7397 X86::LCMPXCHG64, X86::MOV64rr, 7398 X86::NOT64r, X86::RAX, 7399 X86::GR64RegisterClass); 7400 case X86::ATOMNAND64: 7401 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7402 X86::AND64ri32, X86::MOV64rm, 7403 X86::LCMPXCHG64, X86::MOV64rr, 7404 X86::NOT64r, X86::RAX, 7405 X86::GR64RegisterClass, true); 7406 case X86::ATOMMIN64: 7407 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 7408 case X86::ATOMMAX64: 7409 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 7410 case X86::ATOMUMIN64: 7411 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 7412 case X86::ATOMUMAX64: 7413 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 7414 7415 // This group does 64-bit operations on a 32-bit host. 7416 case X86::ATOMAND6432: 7417 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7418 X86::AND32rr, X86::AND32rr, 7419 X86::AND32ri, X86::AND32ri, 7420 false); 7421 case X86::ATOMOR6432: 7422 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7423 X86::OR32rr, X86::OR32rr, 7424 X86::OR32ri, X86::OR32ri, 7425 false); 7426 case X86::ATOMXOR6432: 7427 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7428 X86::XOR32rr, X86::XOR32rr, 7429 X86::XOR32ri, X86::XOR32ri, 7430 false); 7431 case X86::ATOMNAND6432: 7432 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7433 X86::AND32rr, X86::AND32rr, 7434 X86::AND32ri, X86::AND32ri, 7435 true); 7436 case X86::ATOMADD6432: 7437 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7438 X86::ADD32rr, X86::ADC32rr, 7439 X86::ADD32ri, X86::ADC32ri, 7440 false); 7441 case X86::ATOMSUB6432: 7442 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7443 X86::SUB32rr, X86::SBB32rr, 7444 X86::SUB32ri, X86::SBB32ri, 7445 false); 7446 case X86::ATOMSWAP6432: 7447 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7448 X86::MOV32rr, X86::MOV32rr, 7449 X86::MOV32ri, X86::MOV32ri, 7450 false); 7451 } 7452} 7453 7454//===----------------------------------------------------------------------===// 7455// X86 Optimization Hooks 7456//===----------------------------------------------------------------------===// 7457 7458void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7459 const APInt &Mask, 7460 APInt &KnownZero, 7461 APInt &KnownOne, 7462 const SelectionDAG &DAG, 7463 unsigned Depth) const { 7464 unsigned Opc = Op.getOpcode(); 7465 assert((Opc >= ISD::BUILTIN_OP_END || 7466 Opc == ISD::INTRINSIC_WO_CHAIN || 7467 Opc == ISD::INTRINSIC_W_CHAIN || 7468 Opc == ISD::INTRINSIC_VOID) && 7469 "Should use MaskedValueIsZero if you don't know whether Op" 7470 " is a target node!"); 7471 7472 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 7473 switch (Opc) { 7474 default: break; 7475 case X86ISD::SETCC: 7476 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 7477 Mask.getBitWidth() - 1); 7478 break; 7479 } 7480} 7481 7482/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 7483/// node is a GlobalAddress + offset. 7484bool X86TargetLowering::isGAPlusOffset(SDNode *N, 7485 GlobalValue* &GA, int64_t &Offset) const{ 7486 if (N->getOpcode() == X86ISD::Wrapper) { 7487 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 7488 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 7489 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 7490 return true; 7491 } 7492 } 7493 return TargetLowering::isGAPlusOffset(N, GA, Offset); 7494} 7495 7496static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 7497 const TargetLowering &TLI) { 7498 GlobalValue *GV; 7499 int64_t Offset = 0; 7500 if (TLI.isGAPlusOffset(Base, GV, Offset)) 7501 return (GV->getAlignment() >= N && (Offset % N) == 0); 7502 // DAG combine handles the stack object case. 7503 return false; 7504} 7505 7506static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask, 7507 unsigned NumElems, MVT EVT, 7508 SDNode *&Base, 7509 SelectionDAG &DAG, MachineFrameInfo *MFI, 7510 const TargetLowering &TLI) { 7511 Base = NULL; 7512 for (unsigned i = 0; i < NumElems; ++i) { 7513 SDValue Idx = PermMask.getOperand(i); 7514 if (Idx.getOpcode() == ISD::UNDEF) { 7515 if (!Base) 7516 return false; 7517 continue; 7518 } 7519 7520 SDValue Elt = DAG.getShuffleScalarElt(N, i); 7521 if (!Elt.getNode() || 7522 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 7523 return false; 7524 if (!Base) { 7525 Base = Elt.getNode(); 7526 if (Base->getOpcode() == ISD::UNDEF) 7527 return false; 7528 continue; 7529 } 7530 if (Elt.getOpcode() == ISD::UNDEF) 7531 continue; 7532 7533 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base, 7534 EVT.getSizeInBits()/8, i, MFI)) 7535 return false; 7536 } 7537 return true; 7538} 7539 7540/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 7541/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 7542/// if the load addresses are consecutive, non-overlapping, and in the right 7543/// order. 7544static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 7545 const TargetLowering &TLI) { 7546 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7547 MVT VT = N->getValueType(0); 7548 MVT EVT = VT.getVectorElementType(); 7549 SDValue PermMask = N->getOperand(2); 7550 unsigned NumElems = PermMask.getNumOperands(); 7551 SDNode *Base = NULL; 7552 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base, 7553 DAG, MFI, TLI)) 7554 return SDValue(); 7555 7556 LoadSDNode *LD = cast<LoadSDNode>(Base); 7557 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI)) 7558 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 7559 LD->getSrcValueOffset(), LD->isVolatile()); 7560 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 7561 LD->getSrcValueOffset(), LD->isVolatile(), 7562 LD->getAlignment()); 7563} 7564 7565/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. 7566static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, 7567 TargetLowering::DAGCombinerInfo &DCI, 7568 const X86Subtarget *Subtarget, 7569 const TargetLowering &TLI) { 7570 unsigned NumOps = N->getNumOperands(); 7571 7572 // Ignore single operand BUILD_VECTOR. 7573 if (NumOps == 1) 7574 return SDValue(); 7575 7576 MVT VT = N->getValueType(0); 7577 MVT EVT = VT.getVectorElementType(); 7578 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) 7579 // We are looking for load i64 and zero extend. We want to transform 7580 // it before legalizer has a chance to expand it. Also look for i64 7581 // BUILD_PAIR bit casted to f64. 7582 return SDValue(); 7583 // This must be an insertion into a zero vector. 7584 SDValue HighElt = N->getOperand(1); 7585 if (!isZeroNode(HighElt)) 7586 return SDValue(); 7587 7588 // Value must be a load. 7589 SDNode *Base = N->getOperand(0).getNode(); 7590 if (!isa<LoadSDNode>(Base)) { 7591 if (Base->getOpcode() != ISD::BIT_CONVERT) 7592 return SDValue(); 7593 Base = Base->getOperand(0).getNode(); 7594 if (!isa<LoadSDNode>(Base)) 7595 return SDValue(); 7596 } 7597 7598 // Transform it into VZEXT_LOAD addr. 7599 LoadSDNode *LD = cast<LoadSDNode>(Base); 7600 7601 // Load must not be an extload. 7602 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 7603 return SDValue(); 7604 7605 SDVTList Tys = DAG.getVTList(VT, MVT::Other); 7606 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 7607 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2); 7608 TargetLowering::TargetLoweringOpt TLO(DAG); 7609 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1)); 7610 DCI.CommitTargetLoweringOpt(TLO); 7611 return ResNode; 7612} 7613 7614/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 7615static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 7616 const X86Subtarget *Subtarget) { 7617 SDValue Cond = N->getOperand(0); 7618 7619 // If we have SSE[12] support, try to form min/max nodes. 7620 if (Subtarget->hasSSE2() && 7621 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 7622 if (Cond.getOpcode() == ISD::SETCC) { 7623 // Get the LHS/RHS of the select. 7624 SDValue LHS = N->getOperand(1); 7625 SDValue RHS = N->getOperand(2); 7626 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 7627 7628 unsigned Opcode = 0; 7629 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 7630 switch (CC) { 7631 default: break; 7632 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 7633 case ISD::SETULE: 7634 case ISD::SETLE: 7635 if (!UnsafeFPMath) break; 7636 // FALL THROUGH. 7637 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 7638 case ISD::SETLT: 7639 Opcode = X86ISD::FMIN; 7640 break; 7641 7642 case ISD::SETOGT: // (X > Y) ? X : Y -> max 7643 case ISD::SETUGT: 7644 case ISD::SETGT: 7645 if (!UnsafeFPMath) break; 7646 // FALL THROUGH. 7647 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 7648 case ISD::SETGE: 7649 Opcode = X86ISD::FMAX; 7650 break; 7651 } 7652 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 7653 switch (CC) { 7654 default: break; 7655 case ISD::SETOGT: // (X > Y) ? Y : X -> min 7656 case ISD::SETUGT: 7657 case ISD::SETGT: 7658 if (!UnsafeFPMath) break; 7659 // FALL THROUGH. 7660 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 7661 case ISD::SETGE: 7662 Opcode = X86ISD::FMIN; 7663 break; 7664 7665 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 7666 case ISD::SETULE: 7667 case ISD::SETLE: 7668 if (!UnsafeFPMath) break; 7669 // FALL THROUGH. 7670 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 7671 case ISD::SETLT: 7672 Opcode = X86ISD::FMAX; 7673 break; 7674 } 7675 } 7676 7677 if (Opcode) 7678 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 7679 } 7680 7681 } 7682 7683 return SDValue(); 7684} 7685 7686/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 7687/// when possible. 7688static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 7689 const X86Subtarget *Subtarget) { 7690 // On X86 with SSE2 support, we can transform this to a vector shift if 7691 // all elements are shifted by the same amount. We can't do this in legalize 7692 // because the a constant vector is typically transformed to a constant pool 7693 // so we have no knowledge of the shift amount. 7694 if (!Subtarget->hasSSE2()) 7695 return SDValue(); 7696 7697 MVT VT = N->getValueType(0); 7698 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 7699 return SDValue(); 7700 7701 SDValue ShAmtOp = N->getOperand(1); 7702 MVT EltVT = VT.getVectorElementType(); 7703 SDValue BaseShAmt; 7704 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 7705 unsigned NumElts = VT.getVectorNumElements(); 7706 unsigned i = 0; 7707 for (; i != NumElts; ++i) { 7708 SDValue Arg = ShAmtOp.getOperand(i); 7709 if (Arg.getOpcode() == ISD::UNDEF) continue; 7710 BaseShAmt = Arg; 7711 break; 7712 } 7713 for (; i != NumElts; ++i) { 7714 SDValue Arg = ShAmtOp.getOperand(i); 7715 if (Arg.getOpcode() == ISD::UNDEF) continue; 7716 if (Arg != BaseShAmt) { 7717 return SDValue(); 7718 } 7719 } 7720 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 7721 isSplatMask(ShAmtOp.getOperand(2).getNode())) { 7722 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, ShAmtOp, 7723 DAG.getIntPtrConstant(0)); 7724 } else 7725 return SDValue(); 7726 7727 if (EltVT.bitsGT(MVT::i32)) 7728 BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt); 7729 else if (EltVT.bitsLT(MVT::i32)) 7730 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BaseShAmt); 7731 7732 // The shift amount is identical so we can do a vector shift. 7733 SDValue ValOp = N->getOperand(0); 7734 switch (N->getOpcode()) { 7735 default: 7736 assert(0 && "Unknown shift opcode!"); 7737 break; 7738 case ISD::SHL: 7739 if (VT == MVT::v2i64) 7740 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7741 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7742 ValOp, BaseShAmt); 7743 if (VT == MVT::v4i32) 7744 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7745 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 7746 ValOp, BaseShAmt); 7747 if (VT == MVT::v8i16) 7748 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7749 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 7750 ValOp, BaseShAmt); 7751 break; 7752 case ISD::SRA: 7753 if (VT == MVT::v4i32) 7754 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7755 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 7756 ValOp, BaseShAmt); 7757 if (VT == MVT::v8i16) 7758 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7759 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 7760 ValOp, BaseShAmt); 7761 break; 7762 case ISD::SRL: 7763 if (VT == MVT::v2i64) 7764 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7765 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7766 ValOp, BaseShAmt); 7767 if (VT == MVT::v4i32) 7768 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7769 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 7770 ValOp, BaseShAmt); 7771 if (VT == MVT::v8i16) 7772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 7773 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 7774 ValOp, BaseShAmt); 7775 break; 7776 } 7777 return SDValue(); 7778} 7779 7780/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 7781static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 7782 const X86Subtarget *Subtarget) { 7783 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 7784 // the FP state in cases where an emms may be missing. 7785 // A preferable solution to the general problem is to figure out the right 7786 // places to insert EMMS. This qualifies as a quick hack. 7787 StoreSDNode *St = cast<StoreSDNode>(N); 7788 if (St->getValue().getValueType().isVector() && 7789 St->getValue().getValueType().getSizeInBits() == 64 && 7790 isa<LoadSDNode>(St->getValue()) && 7791 !cast<LoadSDNode>(St->getValue())->isVolatile() && 7792 St->getChain().hasOneUse() && !St->isVolatile()) { 7793 SDNode* LdVal = St->getValue().getNode(); 7794 LoadSDNode *Ld = 0; 7795 int TokenFactorIndex = -1; 7796 SmallVector<SDValue, 8> Ops; 7797 SDNode* ChainVal = St->getChain().getNode(); 7798 // Must be a store of a load. We currently handle two cases: the load 7799 // is a direct child, and it's under an intervening TokenFactor. It is 7800 // possible to dig deeper under nested TokenFactors. 7801 if (ChainVal == LdVal) 7802 Ld = cast<LoadSDNode>(St->getChain()); 7803 else if (St->getValue().hasOneUse() && 7804 ChainVal->getOpcode() == ISD::TokenFactor) { 7805 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 7806 if (ChainVal->getOperand(i).getNode() == LdVal) { 7807 TokenFactorIndex = i; 7808 Ld = cast<LoadSDNode>(St->getValue()); 7809 } else 7810 Ops.push_back(ChainVal->getOperand(i)); 7811 } 7812 } 7813 if (Ld) { 7814 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 7815 if (Subtarget->is64Bit()) { 7816 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), 7817 Ld->getBasePtr(), Ld->getSrcValue(), 7818 Ld->getSrcValueOffset(), Ld->isVolatile(), 7819 Ld->getAlignment()); 7820 SDValue NewChain = NewLd.getValue(1); 7821 if (TokenFactorIndex != -1) { 7822 Ops.push_back(NewChain); 7823 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 7824 Ops.size()); 7825 } 7826 return DAG.getStore(NewChain, NewLd, St->getBasePtr(), 7827 St->getSrcValue(), St->getSrcValueOffset(), 7828 St->isVolatile(), St->getAlignment()); 7829 } 7830 7831 // Otherwise, lower to two 32-bit copies. 7832 SDValue LoAddr = Ld->getBasePtr(); 7833 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 7834 DAG.getConstant(4, MVT::i32)); 7835 7836 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, 7837 Ld->getSrcValue(), Ld->getSrcValueOffset(), 7838 Ld->isVolatile(), Ld->getAlignment()); 7839 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, 7840 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 7841 Ld->isVolatile(), 7842 MinAlign(Ld->getAlignment(), 4)); 7843 7844 SDValue NewChain = LoLd.getValue(1); 7845 if (TokenFactorIndex != -1) { 7846 Ops.push_back(LoLd); 7847 Ops.push_back(HiLd); 7848 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 7849 Ops.size()); 7850 } 7851 7852 LoAddr = St->getBasePtr(); 7853 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 7854 DAG.getConstant(4, MVT::i32)); 7855 7856 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr, 7857 St->getSrcValue(), St->getSrcValueOffset(), 7858 St->isVolatile(), St->getAlignment()); 7859 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr, 7860 St->getSrcValue(), 7861 St->getSrcValueOffset() + 4, 7862 St->isVolatile(), 7863 MinAlign(St->getAlignment(), 4)); 7864 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); 7865 } 7866 } 7867 return SDValue(); 7868} 7869 7870/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 7871/// X86ISD::FXOR nodes. 7872static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 7873 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 7874 // F[X]OR(0.0, x) -> x 7875 // F[X]OR(x, 0.0) -> x 7876 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 7877 if (C->getValueAPF().isPosZero()) 7878 return N->getOperand(1); 7879 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 7880 if (C->getValueAPF().isPosZero()) 7881 return N->getOperand(0); 7882 return SDValue(); 7883} 7884 7885/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 7886static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 7887 // FAND(0.0, x) -> 0.0 7888 // FAND(x, 0.0) -> 0.0 7889 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 7890 if (C->getValueAPF().isPosZero()) 7891 return N->getOperand(0); 7892 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 7893 if (C->getValueAPF().isPosZero()) 7894 return N->getOperand(1); 7895 return SDValue(); 7896} 7897 7898static SDValue PerformBTCombine(SDNode *N, 7899 SelectionDAG &DAG, 7900 TargetLowering::DAGCombinerInfo &DCI) { 7901 // BT ignores high bits in the bit index operand. 7902 SDValue Op1 = N->getOperand(1); 7903 if (Op1.hasOneUse()) { 7904 unsigned BitWidth = Op1.getValueSizeInBits(); 7905 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 7906 APInt KnownZero, KnownOne; 7907 TargetLowering::TargetLoweringOpt TLO(DAG); 7908 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7909 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 7910 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 7911 DCI.CommitTargetLoweringOpt(TLO); 7912 } 7913 return SDValue(); 7914} 7915 7916SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 7917 DAGCombinerInfo &DCI) const { 7918 SelectionDAG &DAG = DCI.DAG; 7919 switch (N->getOpcode()) { 7920 default: break; 7921 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 7922 case ISD::BUILD_VECTOR: 7923 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this); 7924 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 7925 case ISD::SHL: 7926 case ISD::SRA: 7927 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 7928 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 7929 case X86ISD::FXOR: 7930 case X86ISD::FOR: return PerformFORCombine(N, DAG); 7931 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 7932 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 7933 } 7934 7935 return SDValue(); 7936} 7937 7938//===----------------------------------------------------------------------===// 7939// X86 Inline Assembly Support 7940//===----------------------------------------------------------------------===// 7941 7942/// getConstraintType - Given a constraint letter, return the type of 7943/// constraint it is for this target. 7944X86TargetLowering::ConstraintType 7945X86TargetLowering::getConstraintType(const std::string &Constraint) const { 7946 if (Constraint.size() == 1) { 7947 switch (Constraint[0]) { 7948 case 'A': 7949 return C_Register; 7950 case 'f': 7951 case 'r': 7952 case 'R': 7953 case 'l': 7954 case 'q': 7955 case 'Q': 7956 case 'x': 7957 case 'y': 7958 case 'Y': 7959 return C_RegisterClass; 7960 default: 7961 break; 7962 } 7963 } 7964 return TargetLowering::getConstraintType(Constraint); 7965} 7966 7967/// LowerXConstraint - try to replace an X constraint, which matches anything, 7968/// with another that has more specific requirements based on the type of the 7969/// corresponding operand. 7970const char *X86TargetLowering:: 7971LowerXConstraint(MVT ConstraintVT) const { 7972 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 7973 // 'f' like normal targets. 7974 if (ConstraintVT.isFloatingPoint()) { 7975 if (Subtarget->hasSSE2()) 7976 return "Y"; 7977 if (Subtarget->hasSSE1()) 7978 return "x"; 7979 } 7980 7981 return TargetLowering::LowerXConstraint(ConstraintVT); 7982} 7983 7984/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 7985/// vector. If it is invalid, don't add anything to Ops. 7986void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 7987 char Constraint, 7988 bool hasMemory, 7989 std::vector<SDValue>&Ops, 7990 SelectionDAG &DAG) const { 7991 SDValue Result(0, 0); 7992 7993 switch (Constraint) { 7994 default: break; 7995 case 'I': 7996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7997 if (C->getZExtValue() <= 31) { 7998 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 7999 break; 8000 } 8001 } 8002 return; 8003 case 'J': 8004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8005 if (C->getZExtValue() <= 63) { 8006 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8007 break; 8008 } 8009 } 8010 return; 8011 case 'N': 8012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8013 if (C->getZExtValue() <= 255) { 8014 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8015 break; 8016 } 8017 } 8018 return; 8019 case 'i': { 8020 // Literal immediates are always ok. 8021 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 8022 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType()); 8023 break; 8024 } 8025 8026 // If we are in non-pic codegen mode, we allow the address of a global (with 8027 // an optional displacement) to be used with 'i'. 8028 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 8029 int64_t Offset = 0; 8030 8031 // Match either (GA) or (GA+C) 8032 if (GA) { 8033 Offset = GA->getOffset(); 8034 } else if (Op.getOpcode() == ISD::ADD) { 8035 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8036 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 8037 if (C && GA) { 8038 Offset = GA->getOffset()+C->getZExtValue(); 8039 } else { 8040 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8041 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 8042 if (C && GA) 8043 Offset = GA->getOffset()+C->getZExtValue(); 8044 else 8045 C = 0, GA = 0; 8046 } 8047 } 8048 8049 if (GA) { 8050 if (hasMemory) 8051 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG); 8052 else 8053 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 8054 Offset); 8055 Result = Op; 8056 break; 8057 } 8058 8059 // Otherwise, not valid for this mode. 8060 return; 8061 } 8062 } 8063 8064 if (Result.getNode()) { 8065 Ops.push_back(Result); 8066 return; 8067 } 8068 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 8069 Ops, DAG); 8070} 8071 8072std::vector<unsigned> X86TargetLowering:: 8073getRegClassForInlineAsmConstraint(const std::string &Constraint, 8074 MVT VT) const { 8075 if (Constraint.size() == 1) { 8076 // FIXME: not handling fp-stack yet! 8077 switch (Constraint[0]) { // GCC X86 Constraint Letters 8078 default: break; // Unknown constraint letter 8079 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 8080 case 'Q': // Q_REGS 8081 if (VT == MVT::i32) 8082 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 8083 else if (VT == MVT::i16) 8084 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 8085 else if (VT == MVT::i8) 8086 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 8087 else if (VT == MVT::i64) 8088 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 8089 break; 8090 } 8091 } 8092 8093 return std::vector<unsigned>(); 8094} 8095 8096std::pair<unsigned, const TargetRegisterClass*> 8097X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8098 MVT VT) const { 8099 // First, see if this is a constraint that directly corresponds to an LLVM 8100 // register class. 8101 if (Constraint.size() == 1) { 8102 // GCC Constraint Letters 8103 switch (Constraint[0]) { 8104 default: break; 8105 case 'r': // GENERAL_REGS 8106 case 'R': // LEGACY_REGS 8107 case 'l': // INDEX_REGS 8108 if (VT == MVT::i8) 8109 return std::make_pair(0U, X86::GR8RegisterClass); 8110 if (VT == MVT::i16) 8111 return std::make_pair(0U, X86::GR16RegisterClass); 8112 if (VT == MVT::i32 || !Subtarget->is64Bit()) 8113 return std::make_pair(0U, X86::GR32RegisterClass); 8114 return std::make_pair(0U, X86::GR64RegisterClass); 8115 case 'f': // FP Stack registers. 8116 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 8117 // value to the correct fpstack register class. 8118 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 8119 return std::make_pair(0U, X86::RFP32RegisterClass); 8120 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 8121 return std::make_pair(0U, X86::RFP64RegisterClass); 8122 return std::make_pair(0U, X86::RFP80RegisterClass); 8123 case 'y': // MMX_REGS if MMX allowed. 8124 if (!Subtarget->hasMMX()) break; 8125 return std::make_pair(0U, X86::VR64RegisterClass); 8126 case 'Y': // SSE_REGS if SSE2 allowed 8127 if (!Subtarget->hasSSE2()) break; 8128 // FALL THROUGH. 8129 case 'x': // SSE_REGS if SSE1 allowed 8130 if (!Subtarget->hasSSE1()) break; 8131 8132 switch (VT.getSimpleVT()) { 8133 default: break; 8134 // Scalar SSE types. 8135 case MVT::f32: 8136 case MVT::i32: 8137 return std::make_pair(0U, X86::FR32RegisterClass); 8138 case MVT::f64: 8139 case MVT::i64: 8140 return std::make_pair(0U, X86::FR64RegisterClass); 8141 // Vector types. 8142 case MVT::v16i8: 8143 case MVT::v8i16: 8144 case MVT::v4i32: 8145 case MVT::v2i64: 8146 case MVT::v4f32: 8147 case MVT::v2f64: 8148 return std::make_pair(0U, X86::VR128RegisterClass); 8149 } 8150 break; 8151 } 8152 } 8153 8154 // Use the default implementation in TargetLowering to convert the register 8155 // constraint into a member of a register class. 8156 std::pair<unsigned, const TargetRegisterClass*> Res; 8157 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8158 8159 // Not found as a standard register? 8160 if (Res.second == 0) { 8161 // GCC calls "st(0)" just plain "st". 8162 if (StringsEqualNoCase("{st}", Constraint)) { 8163 Res.first = X86::ST0; 8164 Res.second = X86::RFP80RegisterClass; 8165 } 8166 // 'A' means EAX + EDX. 8167 if (Constraint == "A") { 8168 Res.first = X86::EAX; 8169 Res.second = X86::GRADRegisterClass; 8170 } 8171 return Res; 8172 } 8173 8174 // Otherwise, check to see if this is a register class of the wrong value 8175 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 8176 // turn into {ax},{dx}. 8177 if (Res.second->hasType(VT)) 8178 return Res; // Correct type already, nothing to do. 8179 8180 // All of the single-register GCC register classes map their values onto 8181 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 8182 // really want an 8-bit or 32-bit register, map to the appropriate register 8183 // class and return the appropriate register. 8184 if (Res.second == X86::GR16RegisterClass) { 8185 if (VT == MVT::i8) { 8186 unsigned DestReg = 0; 8187 switch (Res.first) { 8188 default: break; 8189 case X86::AX: DestReg = X86::AL; break; 8190 case X86::DX: DestReg = X86::DL; break; 8191 case X86::CX: DestReg = X86::CL; break; 8192 case X86::BX: DestReg = X86::BL; break; 8193 } 8194 if (DestReg) { 8195 Res.first = DestReg; 8196 Res.second = Res.second = X86::GR8RegisterClass; 8197 } 8198 } else if (VT == MVT::i32) { 8199 unsigned DestReg = 0; 8200 switch (Res.first) { 8201 default: break; 8202 case X86::AX: DestReg = X86::EAX; break; 8203 case X86::DX: DestReg = X86::EDX; break; 8204 case X86::CX: DestReg = X86::ECX; break; 8205 case X86::BX: DestReg = X86::EBX; break; 8206 case X86::SI: DestReg = X86::ESI; break; 8207 case X86::DI: DestReg = X86::EDI; break; 8208 case X86::BP: DestReg = X86::EBP; break; 8209 case X86::SP: DestReg = X86::ESP; break; 8210 } 8211 if (DestReg) { 8212 Res.first = DestReg; 8213 Res.second = Res.second = X86::GR32RegisterClass; 8214 } 8215 } else if (VT == MVT::i64) { 8216 unsigned DestReg = 0; 8217 switch (Res.first) { 8218 default: break; 8219 case X86::AX: DestReg = X86::RAX; break; 8220 case X86::DX: DestReg = X86::RDX; break; 8221 case X86::CX: DestReg = X86::RCX; break; 8222 case X86::BX: DestReg = X86::RBX; break; 8223 case X86::SI: DestReg = X86::RSI; break; 8224 case X86::DI: DestReg = X86::RDI; break; 8225 case X86::BP: DestReg = X86::RBP; break; 8226 case X86::SP: DestReg = X86::RSP; break; 8227 } 8228 if (DestReg) { 8229 Res.first = DestReg; 8230 Res.second = Res.second = X86::GR64RegisterClass; 8231 } 8232 } 8233 } else if (Res.second == X86::FR32RegisterClass || 8234 Res.second == X86::FR64RegisterClass || 8235 Res.second == X86::VR128RegisterClass) { 8236 // Handle references to XMM physical registers that got mapped into the 8237 // wrong class. This can happen with constraints like {xmm0} where the 8238 // target independent register mapper will just pick the first match it can 8239 // find, ignoring the required type. 8240 if (VT == MVT::f32) 8241 Res.second = X86::FR32RegisterClass; 8242 else if (VT == MVT::f64) 8243 Res.second = X86::FR64RegisterClass; 8244 else if (X86::VR128RegisterClass->hasType(VT)) 8245 Res.second = X86::VR128RegisterClass; 8246 } 8247 8248 return Res; 8249} 8250 8251//===----------------------------------------------------------------------===// 8252// X86 Widen vector type 8253//===----------------------------------------------------------------------===// 8254 8255/// getWidenVectorType: given a vector type, returns the type to widen 8256/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 8257/// If there is no vector type that we want to widen to, returns MVT::Other 8258/// When and where to widen is target dependent based on the cost of 8259/// scalarizing vs using the wider vector type. 8260 8261MVT X86TargetLowering::getWidenVectorType(MVT VT) const { 8262 assert(VT.isVector()); 8263 if (isTypeLegal(VT)) 8264 return VT; 8265 8266 // TODO: In computeRegisterProperty, we can compute the list of legal vector 8267 // type based on element type. This would speed up our search (though 8268 // it may not be worth it since the size of the list is relatively 8269 // small). 8270 MVT EltVT = VT.getVectorElementType(); 8271 unsigned NElts = VT.getVectorNumElements(); 8272 8273 // On X86, it make sense to widen any vector wider than 1 8274 if (NElts <= 1) 8275 return MVT::Other; 8276 8277 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 8278 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 8279 MVT SVT = (MVT::SimpleValueType)nVT; 8280 8281 if (isTypeLegal(SVT) && 8282 SVT.getVectorElementType() == EltVT && 8283 SVT.getVectorNumElements() > NElts) 8284 return SVT; 8285 } 8286 return MVT::Other; 8287} 8288